date:20170801

[llvm-branch-commits] [polly] r309656 - [release 5.0][Release Notes] Polly-ACC works with Julia

2017-08-01 Thread Singapuram Sanjay Srivallabh via llvm-branch-commits

Author: singam-sanjay
Date: Mon Jul 31 22:02:26 2017
New Revision: 309656

URL: http://llvm.org/viewvc/llvm-project?rev=309656&view=rev
Log:
[release 5.0][Release Notes] Polly-ACC works with Julia

Summary: Polly can now offload Julia to GPUs. This was enabled by the pull 
requests https://github.com/JuliaLang/julia/pull/21736 and 
https://github.com/JuliaLang/julia/pull/22036.

Reviewers: grosser, bollu

Subscribers: pollydev

Tags: #polly

Differential Revision: https://reviews.llvm.org/D36050

Modified:
polly/branches/release_50/docs/ReleaseNotes.rst

Modified: polly/branches/release_50/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/polly/branches/release_50/docs/ReleaseNotes.rst?rev=309656&r1=309655&r2=309656&view=diff
==
--- polly/branches/release_50/docs/ReleaseNotes.rst (original)
+++ polly/branches/release_50/docs/ReleaseNotes.rst Mon Jul 31 22:02:26 2017
@@ -88,3 +88,10 @@ Polly now uses the LLVM OptimizationDiag
 This allows Polly remarks to appear in the yaml optimization record when 
compiling
 with the flag -fsave-optimization-record. This also allow Polly remarks to 
appear in the opt-viewer
 tool, allowing for remarks to be viewed next to the source code, and sorted by 
hotness.
+
+--
+Polly-ACC works with Julia
+--
+
+Polly can now offload Julia to GPUs. This feature is enabled by setting the 
+USE_POLLY_ACC variable to 1, i.e. USE_POLLY_ACC:=1.


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[llvm-branch-commits] [cfe-branch] r309764 - Merging r309752:

2017-08-01 Thread Hans Wennborg via llvm-branch-commits

Author: hans
Date: Tue Aug  1 16:32:23 2017
New Revision: 309764

URL: http://llvm.org/viewvc/llvm-project?rev=309764&view=rev
Log:
Merging r309752:

r309752 | bruno | 2017-08-01 15:10:36 -0700 (Tue, 01 Aug 2017) | 6 lines

[Headers][Darwin] Allow #include_next to work on Darwin prior to 10.7

This fixes PR31504 and it's a follow up from adding #include_next
for Darwin in r289018.

rdar://problem/29856682


Modified:
cfe/branches/release_50/   (props changed)
cfe/branches/release_50/lib/Headers/float.h

Propchange: cfe/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug  1 16:32:23 2017
@@ -1,4 +1,4 @@
 /cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:308455,308824,308897,309058,309112-309113,309226,309327,309382-309383,309488,309503
+/cfe/trunk:308455,308824,308897,309058,309112-309113,309226,309327,309382-309383,309488,309503,309752
 /cfe/trunk/test:170344
 /cfe/trunk/test/SemaTemplate:126920

Modified: cfe/branches/release_50/lib/Headers/float.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/lib/Headers/float.h?rev=309764&r1=309763&r2=309764&view=diff
==
--- cfe/branches/release_50/lib/Headers/float.h (original)
+++ cfe/branches/release_50/lib/Headers/float.h Tue Aug  1 16:32:23 2017
@@ -33,6 +33,15 @@
  */
 #if (defined(__APPLE__) || (defined(__MINGW32__) || defined(_MSC_VER))) && \
 __STDC_HOSTED__ && __has_include_next()
+
+/* Prior to Apple's 10.7 SDK, float.h SDK header used to apply an extra level
+ * of #include_next to keep Metrowerks compilers happy. Avoid this
+ * extra indirection.
+ */
+#ifdef __APPLE__
+#define _FLOAT_H_
+#endif
+
 #  include_next 
 
 /* Undefine anything that we'll be redefining below. */


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[llvm-branch-commits] [llvm-branch] r309765 - Merging r309495:

2017-08-01 Thread Hans Wennborg via llvm-branch-commits

Author: hans
Date: Tue Aug  1 16:38:46 2017
New Revision: 309765

URL: http://llvm.org/viewvc/llvm-project?rev=309765&view=rev
Log:
Merging r309495:

r309495 | fhahn | 2017-07-29 13:35:28 -0700 (Sat, 29 Jul 2017) | 30 lines

[AArch64] Tie source and destination operands for AESMC/AESIMC. 

Summary:
Most CPUs implementing AES fusion require instruction pairs of the form
AESE Vn, _
AESMC Vn, Vn
and
AESD Vn, _
AESIMC Vn, Vn

The constraint is added to AES(I)MC instructions which use the result of
an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which
constraint source and destination registers to be the same.

A nice side effect of this change is that now all possible pairs are
scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll
test case.

I had to update aes_load_store. The version I added initially was very
reduced and with the new constraint, AESE/AESMC could not be scheduled
back-to-back. I updated the test to be more realistic and still expose
the same scheduling problem as the initial test case.

Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga

Reviewed By: t.p.northover, evandro

Subscribers: aemerson, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35299


Modified:
llvm/branches/release_50/   (props changed)
llvm/branches/release_50/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.td
llvm/branches/release_50/lib/Target/AArch64/AArch64MacroFusion.cpp
llvm/branches/release_50/test/CodeGen/AArch64/misched-fusion-aes.ll
llvm/branches/release_50/test/MC/AArch64/arm64-crypto.s

Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug  1 16:38:46 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495

Modified: 
llvm/branches/release_50/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp?rev=309765&r1=309764&r2=309765&view=diff
==
--- llvm/branches/release_50/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 
(original)
+++ llvm/branches/release_50/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 
Tue Aug  1 16:38:46 2017
@@ -946,6 +946,18 @@ bool AArch64ExpandPseudo::expandMI(Machi
   case AArch64::CMP_SWAP_128:
 return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
 
+  case AArch64::AESMCrrTied:
+  case AArch64::AESIMCrrTied: {
+MachineInstrBuilder MIB =
+BuildMI(MBB, MBBI, MI.getDebugLoc(),
+TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
+  AArch64::AESIMCrr))
+  .add(MI.getOperand(0))
+  .add(MI.getOperand(1));
+transferImpOps(MI, MIB, MIB);
+MI.eraseFromParent();
+return true;
+   }
   }
   return false;
 }

Modified: llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.td?rev=309765&r1=309764&r2=309765&view=diff
==
--- llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/branches/release_50/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug  1 
16:38:46 2017
@@ -37,6 +37,9 @@ def HasFullFP16  : Predicate<"Subtar
  AssemblerPredicate<"FeatureFullFP16", 
"fullfp16">;
 def HasSPE   : Predicate<"Subtarget->hasSPE()">,
  AssemblerPredicate<"FeatureSPE", "spe">;
+def HasFuseAES   : Predicate<"Subtarget->hasFuseAES()">,
+ AssemblerPredicate<"FeatureFuseAES",
+ "fuse-aes">;
 def HasSVE   : Predicate<"Subtarget->hasSVE()">,
  AssemblerPredicate<"FeatureSVE", "sve">;
 
@@ -5304,6 +5307,31 @@ def AESDrr   : AESTiedInst<0b0101, "aesd
 def AESMCrr  : AESInst<0b0110, "aesmc",  int_aarch64_crypto_aesmc>;
 def AESIMCrr : AESInst<0b0111, "aesimc", int_aarch64_crypto_aesimc>;
 
+// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required
+// for AES fus

[llvm-branch-commits] [llvm-branch] r309767 - Merging r309561:

2017-08-01 Thread Hans Wennborg via llvm-branch-commits

Author: hans
Date: Tue Aug  1 16:44:38 2017
New Revision: 309767

URL: http://llvm.org/viewvc/llvm-project?rev=309767&view=rev
Log:
Merging r309561:

r309561 | sdardis | 2017-07-31 07:06:58 -0700 (Mon, 31 Jul 2017) | 14 lines

[SelectionDAG][mips] Fix PR33883

PR33883 shows that calls to intrinsic functions should not have their vector
arguments or returns subject to ABI changes required by the target.

This resolves PR33883.

Thanks to Alex Crichton for reporting the issue!

Reviewers: zoran.jovanovic, atanasyan

Differential Revision: https://reviews.llvm.org/D35765




Added:
llvm/branches/release_50/test/CodeGen/Mips/cconv/pr33883.ll
  - copied unchanged from r309561, 
llvm/trunk/test/CodeGen/Mips/cconv/pr33883.ll
Modified:
llvm/branches/release_50/   (props changed)
llvm/branches/release_50/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Propchange: llvm/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug  1 16:44:38 2017
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495
+/llvm/trunk:155241,308483-308484,308503,308808,308813,308891,308906,308950,308963,308978,308986,309113,309302,309321,309323,309325,309330,309343,309353,309355,309422,309481,309483,309495,309561

Modified: 
llvm/branches/release_50/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=309767&r1=309766&r2=309767&view=diff
==
--- llvm/branches/release_50/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
(original)
+++ llvm/branches/release_50/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
Tue Aug  1 16:44:38 2017
@@ -99,6 +99,27 @@ LimitFPPrecision("limit-float-precision"
 // store [4096 x i8] %data, [4096 x i8]* %buffer
 static const unsigned MaxParallelChains = 64;
 
+// True if the Value passed requires ABI mangling as it is a parameter to a
+// function or a return value from a function which is not an intrinsic.
+static bool isABIRegCopy(const Value * V) {
+  const bool IsRetInst = V && isa(V);
+  const bool IsCallInst = V && isa(V);
+  const bool IsInLineAsm =
+  IsCallInst && static_cast(V)->isInlineAsm();
+  const bool IsIndirectFunctionCall =
+  IsCallInst && !IsInLineAsm &&
+  !static_cast(V)->getCalledFunction();
+  // It is possible that the call instruction is an inline asm statement or an
+  // indirect function call in which case the return value of
+  // getCalledFunction() would be nullptr.
+  const bool IsInstrinsicCall =
+  IsCallInst && !IsInLineAsm && !IsIndirectFunctionCall &&
+  static_cast(V)->getCalledFunction()->getIntrinsicID() 
!=
+  Intrinsic::not_intrinsic;
+
+  return IsRetInst || (IsCallInst && (!IsInLineAsm && !IsInstrinsicCall));
+}
+
 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
   const SDValue *Parts, unsigned NumParts,
   MVT PartVT, EVT ValueVT, const Value *V,
@@ -1026,13 +1047,9 @@ SDValue SelectionDAGBuilder::getCopyFrom
 
   if (It != FuncInfo.ValueMap.end()) {
 unsigned InReg = It->second;
-bool IsABIRegCopy =
-V && ((isa(V) &&
-   !(static_cast(V))->isInlineAsm()) ||
-  isa(V));
 
 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
- DAG.getDataLayout(), InReg, Ty, IsABIRegCopy);
+ DAG.getDataLayout(), InReg, Ty, isABIRegCopy(V));
 SDValue Chain = DAG.getEntryNode();
 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
  V);
@@ -1221,13 +1238,9 @@ SDValue SelectionDAGBuilder::getValueImp
   // If this is an instruction which fast-isel has deferred, select it now.
   if (const Instruction *Inst = dyn_cast(V)) {
 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
-bool IsABIRegCopy =
-V && ((isa(V) &&
-   !(static_cast(V))->isInlineAsm()) ||
-  isa(V));
 
 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
- Inst->getType(), IsABIRegCopy);
+ Inst->getType(), isABIRegCopy(V));
 SDValue Chain = DAG.getEntryNode();
 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, 
V);
   }
@@ -8281,13 +8294,9 @@ SelectionDAGBuilder::CopyValueToVirtualR
   const TargetLowering &TLI = DAG.getTargetLowe

[llvm-branch-commits] [cfe-branch] r309770 - Merging r309722:

2017-08-01 Thread Hans Wennborg via llvm-branch-commits

Author: hans
Date: Tue Aug  1 16:54:32 2017
New Revision: 309770

URL: http://llvm.org/viewvc/llvm-project?rev=309770&view=rev
Log:
Merging r309722:

r309722 | bruno | 2017-08-01 12:05:25 -0700 (Tue, 01 Aug 2017) | 7 lines

[Sema] Fix lax conversion between non ext vectors

r282968 introduced a regression due to the lack of proper testing.
Re-add lax conversion support between non ext vectors for compound
assignments and add a test for that.

rdar://problem/28639467


Modified:
cfe/branches/release_50/   (props changed)
cfe/branches/release_50/lib/Sema/SemaExpr.cpp
cfe/branches/release_50/test/Sema/vector-cast.c

Propchange: cfe/branches/release_50/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug  1 16:54:32 2017
@@ -1,4 +1,4 @@
 /cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:308455,308824,308897,309058,309112-309113,309226,309327,309382-309383,309488,309503,309752
+/cfe/trunk:308455,308824,308897,309058,309112-309113,309226,309327,309382-309383,309488,309503,309722,309752
 /cfe/trunk/test:170344
 /cfe/trunk/test/SemaTemplate:126920

Modified: cfe/branches/release_50/lib/Sema/SemaExpr.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/lib/Sema/SemaExpr.cpp?rev=309770&r1=309769&r2=309770&view=diff
==
--- cfe/branches/release_50/lib/Sema/SemaExpr.cpp (original)
+++ cfe/branches/release_50/lib/Sema/SemaExpr.cpp Tue Aug  1 16:54:32 2017
@@ -8288,7 +8288,7 @@ QualType Sema::CheckVectorOperands(ExprR
 // type. Note that this is already done by non-compound assignments in
 // CheckAssignmentConstraints. If it's a scalar type, only bitcast for
 // <1 x T> -> T. The result is also a vector type.
-} else if (OtherType->isExtVectorType() ||
+} else if (OtherType->isExtVectorType() || OtherType->isVectorType() ||
(OtherType->isScalarType() && VT->getNumElements() == 1)) {
   ExprResult *RHSExpr = &RHS;
   *RHSExpr = ImpCastExprToType(RHSExpr->get(), LHSType, CK_BitCast);

Modified: cfe/branches/release_50/test/Sema/vector-cast.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_50/test/Sema/vector-cast.c?rev=309770&r1=309769&r2=309770&view=diff
==
--- cfe/branches/release_50/test/Sema/vector-cast.c (original)
+++ cfe/branches/release_50/test/Sema/vector-cast.c Tue Aug  1 16:54:32 2017
@@ -48,6 +48,9 @@ typedef float float2 __attribute__ ((vec
 typedef __attribute__((vector_size(8))) double float64x1_t;
 typedef __attribute__((vector_size(16))) double float64x2_t;
 float64x1_t vget_low_f64(float64x2_t __p0);
+typedef float float16 __attribute__((__vector_size__(16)));
+typedef signed int vSInt32 __attribute__((__vector_size__(16)));
+typedef unsigned int vUInt32 __attribute__((__vector_size__(16)));
 
 void f4() {
   float2 f2;
@@ -73,3 +76,8 @@ void f5() {
   v = ptr; // expected-error-re {{assigning to 'short_sizeof_pointer' (vector 
of {{[0-9]+}} 'short' values) from incompatible type 'void *'}}
   ptr = v; // expected-error {{assigning to 'void *' from incompatible type 
'short_sizeof_pointer'}}
 }
+
+void f6(vSInt32 a0) {
+  vUInt32 counter = (float16){0.0f, 0.0f, 0.0f, 0.0f}; // expected-warning 
{{incompatible vector types initializing 'vUInt32' (vector of 4 'unsigned int' 
values) with an expression of type 'float16' (vector of 4 'float' values)}}
+  counter -= a0;
+}


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[llvm-branch-commits] [polly] r309656 - [release 5.0][Release Notes] Polly-ACC works with Julia

[llvm-branch-commits] [cfe-branch] r309764 - Merging r309752:

[llvm-branch-commits] [llvm-branch] r309765 - Merging r309495:

[llvm-branch-commits] [llvm-branch] r309767 - Merging r309561:

[llvm-branch-commits] [cfe-branch] r309770 - Merging r309722:

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