date:20160402

[llvm-branch-commits] [llvm-branch] r265243 - Merging r263118: ARM: correct __builtin_longjmp on WoA

2016-04-02 Thread Renato Golin via llvm-branch-commits

Author: rengolin
Date: Sat Apr  2 15:31:15 2016
New Revision: 265243

URL: http://llvm.org/viewvc/llvm-project?rev=265243&view=rev
Log:
Merging r263118: ARM: correct __builtin_longjmp on WoA



Added:
llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
Modified:
llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp?rev=265243&r1=265242&r2=265243&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp Sat Apr  2 
15:31:15 2016
@@ -1843,8 +1843,10 @@ void ARMAsmPrinter::EmitInstruction(cons
 // ldr $scratch, [$src, #4]
 // ldr r7, [$src]
 // bx $scratch
+const Triple &TT = TM.getTargetTriple();
 unsigned SrcReg = MI->getOperand(0).getReg();
 unsigned ScratchReg = MI->getOperand(1).getReg();
+
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
   .addReg(ScratchReg)
   .addReg(SrcReg)
@@ -1871,7 +1873,7 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
-  .addReg(ARM::R7)
+  .addReg(TT.isOSWindows() ? ARM::R11 : ARM::R7)
   .addReg(SrcReg)
   .addImm(0)
   // Predicate.

Added: llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll?rev=265243&view=auto
==
--- llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll (added)
+++ llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll Sat 
Apr  2 15:31:15 2016
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck 
%s
+
+declare void @llvm.eh.sjlj.longjmp(i8*)
+
+define arm_aapcs_vfpcc void @test___builtin_longjump(i8* %b) {
+entry:
+  tail call void @llvm.eh.sjlj.longjmp(i8* %b)
+  unreachable
+}
+
+; CHECK: ldr r[[SP:[0-9]+]], [r0, #8]
+; CHECK: mov sp, r[[SP]]
+; CHECK: ldr r[[PC:[0-9]+]], [r0, #4]
+; CHECK: ldr r11, [r0]
+; CHECK: bx  r[[PC]]
+


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[llvm-branch-commits] [llvm-branch] r265244 - Merging r263123: ARM: follow up improvements for SVN r263118

2016-04-02 Thread Renato Golin via llvm-branch-commits

Author: rengolin
Date: Sat Apr  2 15:32:54 2016
New Revision: 265244

URL: http://llvm.org/viewvc/llvm-project?rev=265244&view=rev
Log:
Merging r263123: ARM: follow up improvements for SVN r263118

Modified:
llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll

Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp Sat Apr  2 
15:32:54 2016
@@ -1837,13 +1837,13 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 return;
   }
-  case ARM::tInt_eh_sjlj_longjmp: {
+  case ARM::tInt_eh_sjlj_longjmp:
+  case ARM::tInt_WIN_eh_sjlj_longjmp: {
 // ldr $scratch, [$src, #8]
 // mov sp, $scratch
 // ldr $scratch, [$src, #4]
 // ldr r7, [$src]
 // bx $scratch
-const Triple &TT = TM.getTargetTriple();
 unsigned SrcReg = MI->getOperand(0).getReg();
 unsigned ScratchReg = MI->getOperand(1).getReg();
 
@@ -1873,7 +1873,7 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
-  .addReg(TT.isOSWindows() ? ARM::R11 : ARM::R7)
+  .addReg(Opc == ARM::tInt_WIN_eh_sjlj_longjmp ? ARM::R11 : ARM::R7)
   .addReg(SrcReg)
   .addImm(0)
   // Predicate.

Modified: llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Apr  2 
15:32:54 2016
@@ -632,6 +632,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeIn
   case ARM::Int_eh_sjlj_longjmp:
 return 16;
   case ARM::tInt_eh_sjlj_longjmp:
+  case ARM::tInt_WIN_eh_sjlj_longjmp:
 return 10;
   case ARM::Int_eh_sjlj_setjmp:
   case ARM::Int_eh_sjlj_setjmp_nofp:

Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td Sat Apr  2 15:32:54 
2016
@@ -279,6 +279,8 @@ def IsARM: Predicate<"!Subta
 def IsMachO  : Predicate<"Subtarget->isTargetMachO()">;
 def IsNotMachO   : Predicate<"!Subtarget->isTargetMachO()">;
 def IsNaCl   : Predicate<"Subtarget->isTargetNaCl()">;
+def IsWindows: Predicate<"Subtarget->isTargetWindows()">;
+def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
 def UseNaClTrap  : Predicate<"Subtarget->useNaClTrap()">,
  AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
 def DontUseNaClTrap  : Predicate<"!Subtarget->useNaClTrap()">;

Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td Sat Apr  2 
15:32:54 2016
@@ -1310,7 +1310,14 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (i
   AddrModeNone, 0, IndexModeNone,
   Pseudo, NoItinerary, "", "",
   [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
- Requires<[IsThumb]>;
+ Requires<[IsThumb,IsNotWindows]>;
+
+let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
+Defs = [ R11, LR, SP ] in
+def tInt_WIN_eh_sjlj_longjmp
+  : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
+   Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, 
GPR:$scratch)]>,
+Requires<[IsThumb,IsWindows]>;
 
 
//===--===//
 // Non-Instruction Patterns

Modified: llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llv

[llvm-branch-commits] [llvm-branch] r265245 - Merging r263714: ARM: Revert SVN r253865, 254158, fix windows division

2016-04-02 Thread Renato Golin via llvm-branch-commits

Author: rengolin
Date: Sat Apr  2 15:36:55 2016
New Revision: 265245

URL: http://llvm.org/viewvc/llvm-project?rev=265245&view=rev
Log:
Merging r263714: ARM: Revert SVN r253865, 254158, fix windows division

Added:
llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll
Removed:
llvm/branches/release_38/test/CodeGen/ARM/Windows/overflow.ll
Modified:
llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_38/test/CodeGen/ARM/Windows/division.ll

Modified: llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp?rev=265245&r1=265244&r2=265245&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp Sat Apr  2 
15:36:55 2016
@@ -390,10 +390,6 @@ ARMTargetLowering::ARMTargetLowering(con
   { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
   { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
   { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::SDIV_I32, "__rt_sdiv",   CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::UDIV_I32, "__rt_udiv",   CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::UDIV_I64, "__rt_udiv64", CallingConv::ARM_AAPCS_VFP },
 };
 
 for (const auto &LC : LibraryCalls) {
@@ -780,6 +776,14 @@ ARMTargetLowering::ARMTargetLowering(con
 setOperationAction(ISD::UDIV,  MVT::i32, LibCall);
   }
 
+  if (Subtarget->isTargetWindows() && !Subtarget->hasDivide()) {
+setOperationAction(ISD::SDIV, MVT::i32, Custom);
+setOperationAction(ISD::UDIV, MVT::i32, Custom);
+
+setOperationAction(ISD::SDIV, MVT::i64, Custom);
+setOperationAction(ISD::UDIV, MVT::i64, Custom);
+  }
+
   setOperationAction(ISD::SREM,  MVT::i32, Expand);
   setOperationAction(ISD::UREM,  MVT::i32, Expand);
   // Register based DivRem for AEABI (RTABI 4.2)
@@ -6956,8 +6960,14 @@ SDValue ARMTargetLowering::LowerOperatio
   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
   case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::MUL:   return LowerMUL(Op, DAG);
-  case ISD::SDIV:  return LowerSDIV(Op, DAG);
-  case ISD::UDIV:  return LowerUDIV(Op, DAG);
+  case ISD::SDIV:
+if (Subtarget->isTargetWindows())
+  return LowerDIV_Windows(Op, DAG, /* Signed */ true);
+return LowerSDIV(Op, DAG);
+  case ISD::UDIV:
+if (Subtarget->isTargetWindows())
+  return LowerDIV_Windows(Op, DAG, /* Signed */ false);
+return LowerUDIV(Op, DAG);
   case ISD::ADDC:
   case ISD::ADDE:
   case ISD::SUBC:
@@ -7947,7 +7957,7 @@ ARMTargetLowering::EmitLowered__dbzchk(M
   MF->push_back(ContBB);
   ContBB->splice(ContBB->begin(), MBB,
  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
-  MBB->addSuccessor(ContBB);
+  ContBB->transferSuccessorsAndUpdatePHIs(MBB);
 
   MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
   MF->push_back(TrapBB);
@@ -7957,6 +7967,7 @@ ARMTargetLowering::EmitLowered__dbzchk(M
   BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
   .addReg(MI->getOperand(0).getReg())
   .addMBB(TrapBB);
+  MBB->addSuccessor(ContBB);
 
   MI->eraseFromParent();
   return ContBB;

Added: llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll?rev=265245&view=auto
==
--- llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll (added)
+++ llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll Sat Apr  2 
15:36:55 2016
@@ -0,0 +1,80 @@
+; RUN: llc -mtriple thumbv7--windows-itanium 
-print-machineinstrs=expand-isel-pseudos -o /dev/null %s 2>&1 | FileCheck %s 
-check-prefix CHECK-DIV
+
+; int f(int n, int d) {
+;   if (n / d)
+; return 1;
+;   return 0;
+; }
+
+define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {
+entry:
+  %retval = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %d.addr = alloca i32, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %d, i32* %d.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
+  %1 = load i32, i32* %d.addr, align 4
+  %div = sdiv i32 %0, %1
+  %tobool = icmp ne i32 %div, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  store i32 1, i32* %retval, align 4
+  br label %return
+
+if.end:
+  store i32 0, i32* %retval, align 4
+  br label %return
+
+return:
+  %2 = load i32, i32* %retval, align 4
+  ret i32 %2
+}
+
+; CHECK-DIV-DAG: BB#0
+; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4
+; CHECK-DIV-DAG: BB#1
+; CHECK-DIV-DAG: Successors according to CFG: BB#3
+; CHECK-DIV-DAG: BB#2
+; CHECK-DIV-

[llvm-branch-commits] [llvm-branch] r265243 - Merging r263118: ARM: correct __builtin_longjmp on WoA

[llvm-branch-commits] [llvm-branch] r265244 - Merging r263123: ARM: follow up improvements for SVN r263118

[llvm-branch-commits] [llvm-branch] r265245 - Merging r263714: ARM: Revert SVN r253865, 254158, fix windows division

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