[PATCH] crypto/nx842: Mask XERS0 bit in return value
NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
nothing to do with NX request. Since this bit can be set with other
valuable return status, mast this bit.
One of other bits (INITIATED, BUSY or REJECTED) will be returned for
any given NX request.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/icswx.h |1 +
drivers/crypto/nx/nx-842-powernv.c | 12
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/icswx.h b/arch/powerpc/include/asm/icswx.h
index 9f8402b..27e588f 100644
--- a/arch/powerpc/include/asm/icswx.h
+++ b/arch/powerpc/include/asm/icswx.h
@@ -164,6 +164,7 @@ struct coprocessor_request_block {
#define ICSWX_INITIATED(0x8)
#define ICSWX_BUSY (0x4)
#define ICSWX_REJECTED (0x2)
+#define ICSWX_XERS0(0x1) /* undefined or set from XERSO. */
static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
{
diff --git a/drivers/crypto/nx/nx-842-powernv.c
b/drivers/crypto/nx/nx-842-powernv.c
index 9ef51fa..6e105e8 100644
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -442,6 +442,14 @@ static int nx842_powernv_function(const unsigned char *in,
unsigned int inlen,
(unsigned int)ccw,
(unsigned int)be32_to_cpu(crb->ccw));
+ /*
+* NX842 coprocessor sets 3rd bit in CR register with XER[S0].
+* XER[S0] is the integer summary overflow bit which is nothing
+* to do NX. Since this bit can be set with other return values,
+* mask this bit.
+*/
+ ret &= ~ICSWX_XERS0;
+
switch (ret) {
case ICSWX_INITIATED:
ret = wait_for_csb(wmem, csb);
@@ -454,10 +462,6 @@ static int nx842_powernv_function(const unsigned char *in,
unsigned int inlen,
pr_err_ratelimited("ICSWX rejected\n");
ret = -EPROTO;
break;
- default:
- pr_err_ratelimited("Invalid ICSWX return code %x\n", ret);
- ret = -EPROTO;
- break;
}
if (!ret)
--
1.7.0.4
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[PATCH] cpufreq: powernv: Redesign the presentation of throttle notification
Replace the throttling event console messages to perf trace event
"power:powernv_throttle" and throttle counter stats which are
exported in sysfs. The newly added sysfs files are as follows:
1)/sys/devices/system/node/node0/throttle_frequencies
This gives the throttle stats for each of the available frequencies.
The throttle stat of a frequency is the total number of times the max
frequency was reduced to that frequency.
# cat /sys/devices/system/node/node0/throttle_frequencies
4023000 0
399 0
3956000 1
3923000 0
389 0
3857000 2
3823000 0
379 0
3757000 2
3724000 1
369 1
...
2)/sys/devices/system/node/node0/throttle_reasons
This gives the stats for each of the supported throttle reasons.
This gives the total number of times the frequency was throttled due
to each of the reasons.
# cat /sys/devices/system/node/node0/throttle_reasons
No throttling 7
Power Cap 0
Processor Over Temperature 7
Power Supply Failure 0
Over Current 0
OCC Reset 0
3)/sys/devices/system/node/node0/throttle_stat
This gives the total number of throttle events occurred in turbo
range of frequencies and non-turbo(below nominal) range of
frequencies.
# cat /sys/devices/system/node/node0/throttle_stat
Turbo 7
Nominal 0
Signed-off-by: Shilpasri G Bhat
---
drivers/cpufreq/powernv-cpufreq.c | 186 +-
include/trace/events/power.h | 22 +
2 files changed, 166 insertions(+), 42 deletions(-)
diff --git a/drivers/cpufreq/powernv-cpufreq.c
b/drivers/cpufreq/powernv-cpufreq.c
index cb50138..bdde9d6 100644
--- a/drivers/cpufreq/powernv-cpufreq.c
+++ b/drivers/cpufreq/powernv-cpufreq.c
@@ -28,6 +28,9 @@
#include
#include
#include
+#include
+#include
+#include
#include
#include
@@ -43,12 +46,27 @@
static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
static bool rebooting, throttled, occ_reset;
+static char throttle_reason[][30] = {
+ "No throttling",
+ "Power Cap",
+ "Processor Over Temperature",
+ "Power Supply Failure",
+ "Over Current",
+ "OCC Reset"
+};
+
static struct chip {
unsigned int id;
bool throttled;
cpumask_t mask;
struct work_struct throttle;
bool restore;
+ /* Pmax throttle stats */
+ int throt_reason;
+ int throt_turbo;
+ int throt_nominal;
+ int reason[OCC_MAX_THROTTLE_STATUS + 1];
+ int *pstate_stat;
} *chips;
static int nr_chips;
@@ -309,40 +327,54 @@ static inline unsigned int get_nominal_index(void)
return powernv_pstate_info.max - powernv_pstate_info.nominal;
}
-static void powernv_cpufreq_throttle_check(void *data)
+static void powernv_cpufreq_read_pmax(void *data)
{
unsigned int cpu = smp_processor_id();
unsigned long pmsr;
- int pmsr_pmax, i;
-
- pmsr = get_pmspr(SPRN_PMSR);
+ int pmsr_pmax, index, i;
for (i = 0; i < nr_chips; i++)
if (chips[i].id == cpu_to_chip_id(cpu))
break;
- /* Check for Pmax Capping */
+ pmsr = get_pmspr(SPRN_PMSR);
pmsr_pmax = (s8)PMSR_MAX(pmsr);
if (pmsr_pmax != powernv_pstate_info.max) {
if (chips[i].throttled)
- goto next;
+ return;
chips[i].throttled = true;
- if (pmsr_pmax < powernv_pstate_info.nominal)
- pr_crit("CPU %d on Chip %u has Pmax reduced below
nominal frequency (%d < %d)\n",
+ if (pmsr_pmax < powernv_pstate_info.nominal) {
+ pr_warn("CPU %d on Chip %u has Pmax reduced below
nominal frequency (%d < %d)\n",
cpu, chips[i].id, pmsr_pmax,
powernv_pstate_info.nominal);
- else
- pr_info("CPU %d on Chip %u has Pmax reduced below turbo
frequency (%d < %d)\n",
- cpu, chips[i].id, pmsr_pmax,
- powernv_pstate_info.max);
+ chips[i].throt_nominal++;
+ } else {
+ chips[i].throt_turbo++;
+ }
+ index = powernv_pstate_info.max - pmsr_pmax;
+ if (index >= 0 && index < powernv_pstate_info.nr_pstates)
+ chips[i].pstate_stat[index]++;
+ trace_powernv_throttle(chips[i].id,
+ throttle_reason[chips[i].throt_reason],
+ pmsr_pmax);
} else if (chips[i].throttled) {
chips[i].throttled = false;
- pr_info("CPU %d on Chip %u has Pmax rest
[PATCH] powerpc/476fpe: Add support for kexec
PPC476FPE has a different PVR from previous PPC476 processors. The kexec code checks the PVR in order to correctly setup the MMU. When the initial support for 476FPE processors was added the corresponding change in the kexec code was missed. This patch simply adds the check and solves the following bug on kexec: kexec: Starting new kernel Bye! Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0xee9a50f8 cpu 0x0: Vector: 400 (Instruction Access) at [ee9d7d20] pc: ee9a50f8 lr: ee9a50e4 sp: ee9d7dd0 msr: 21020 current = 0xee40f000 pid = 960, comm = kexec enter ? for help [link register ] ee9a50e4 [ee9d7dd0] c0013748 default_machine_kexec+0x58/0x70 (unreliable) [ee9d7df0] c0012f04 machine_kexec+0x34/0x40 [ee9d7e00] c00aa1ec kernel_kexec+0x9c/0xb0 [ee9d7e20] c005d704 SyS_reboot+0x1f4/0x220 [ee9d7f40] c000db68 ret_from_syscall+0x0/0x3c --- Exception: c01 (System Call) at b77b69f4 SP (bfc4a670) is in userspace 0:mon> Signed-off-by: Alistair Popple Reported-by: Ivan Mikhaylov --- arch/powerpc/kernel/misc_32.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index ed3ab50..be8edd6 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -743,6 +743,8 @@ relocate_new_kernel: /* Check for 47x cores */ mfspr r3,SPRN_PVR srwir3,r3,16 + cmplwi cr0,r3,PVR_476FPE@h + beq setup_map_47x cmplwi cr0,r3,PVR_476@h beq setup_map_47x cmplwi cr0,r3,PVR_476_ISS@h -- 2.1.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 6/6] cxlflash: Enable device id for future IBM CXL adapter
On 11/12/15 09:54, Uma Krishnan wrote: From: Manoj Kumar This drop enables a future card with a device id of 0x0600 to be recognized by the cxlflash driver. No card specific programming has been added. These card specific changes will be staged in later. Signed-off-by: Manoj N. Kumar Without the card-specific code, how does the driver behave if the new card is plugged in? Andrew -- Andrew Donnellan Software Engineer, OzLabs andrew.donnel...@au1.ibm.com Australia Development Lab, Canberra +61 2 6201 8874 (work)IBM Australia Limited ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] cxlflash: Fix to avoid virtual LUN failover failure
> Virtual LUNs may be accessed through one or both ports of the adapter.
Is it possible that there might ever be adapters with a number of ports
other than 2? In particular, is it possible for 3 or 4 port adapters to
exist?
If so, do you need something with a bit more fidelity?
If not, this is a good approach.
Regards,
Daniel
> This access is encoded in the translation entries that comprise the
> virtual LUN and used by the AFU for load-balancing I/O and handling
> failover scenarios. In a link loss scenario, even though the AFU is
> able to maintain connectivity to the LUN, it is up to the application
> to retry the failed I/O. When applications are unaware of the virtual
> LUN's underlying topology, they are unable to make a sound decision of
> when to retry an I/O and therefore are forced to make their reaction to
> a failed I/O absolute. The result is either a failure to retry I/O or
> increased latency for scenarios where a retry is pointless.
>
> To remedy this scenario, provide feedback back to the application on
> virtual LUN creation as to which ports the LUN may be accessed. LUN's
> spanning both ports are candidates for a retry in a presence of an I/O
> failure.
>
> Signed-off-by: Matthew R. Ochs
> ---
> drivers/scsi/cxlflash/vlun.c | 2 ++
> include/uapi/scsi/cxlflash_ioctl.h | 10 ++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/scsi/cxlflash/vlun.c b/drivers/scsi/cxlflash/vlun.c
> index a53f583..50f8e93 100644
> --- a/drivers/scsi/cxlflash/vlun.c
> +++ b/drivers/scsi/cxlflash/vlun.c
> @@ -1008,6 +1008,8 @@ int cxlflash_disk_virtual_open(struct scsi_device
> *sdev, void *arg)
> virt->last_lba = last_lba;
> virt->rsrc_handle = rsrc_handle;
>
> + if (lli->port_sel == BOTH_PORTS)
> + virt->hdr.return_flags |= DK_CXLFLASH_ALL_PORTS_ACTIVE;
> out:
> if (likely(ctxi))
> put_context(ctxi);
> diff --git a/include/uapi/scsi/cxlflash_ioctl.h
> b/include/uapi/scsi/cxlflash_ioctl.h
> index 831351b..2302f3c 100644
> --- a/include/uapi/scsi/cxlflash_ioctl.h
> +++ b/include/uapi/scsi/cxlflash_ioctl.h
> @@ -31,6 +31,16 @@ struct dk_cxlflash_hdr {
> };
>
> /*
> + * Return flag definitions available to all ioctls
> + *
> + * Similar to the input flags, these are grown from the bottom-up with the
> + * intention that ioctl-specific return flag definitions would grow from the
> + * top-down, allowing the two sets to co-exist. While not required/enforced
> + * at this time, this provides future flexibility.
> + */
> +#define DK_CXLFLASH_ALL_PORTS_ACTIVE 0x0001ULL
> +
> +/*
> * Notes:
> * -
> * The 'context_id' field of all ioctl structures contains the context
> --
> 2.1.0
>
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[PATCH V6 0/4] perf/powerpc: Add ability to sample intr machine state in powerpc
This short patch series adds the ability to sample the interrupted machine state for each hardware sample. To test this patchset, Eg: $ perf record -I? # list supported registers output: available registers: gpr0 gpr1 gpr2 gpr3 gpr4 gpr5 gpr6 gpr7 gpr8 gpr9 gpr10 gpr11 gpr12 gpr13 gpr14 gpr15 gpr16 gpr17 gpr18 gpr19 gpr20 gpr21 gpr22 gpr23 gpr24 gpr25 gpr26 gpr27 gpr28 gpr29 gpr30 gpr31 nip msr orig_r3 ctr link xer ccr trap dar dsisr usage: perf record [] [] or: perf record [] -- [] -I, --intr-regs[=] sample selected machine registers on interrupt, use -I ? to list register names $ perf record -I ls # record machine state at interrupt $ perf script -D # read the perf.data file Samplfdoutput obtained for this patchset/ output looks like as follows: 178329381464 0x138 [0x180]: PERF_RECORD_SAMPLE(IP, 0x1): 7803/7803: 0xc000fd9c period: 1 addr: 0 ... intr regs: mask 0x3ff ABI 64-bit gpr0 0xc01a6420 gpr1 0xc01e4df039b0 gpr2 0xc0cdd100 gpr3 0x1 gpr4 0xc01e4a96d000 gpr5 0x29854255ba gpr6 0xc00ffa3050b8 gpr7 0x0 gpr8 0x0 gpr9 0x0 gpr10 0x0 gpr11 0x0 gpr12 0x24022822 gpr13 0xcfe03000 gpr14 0x0 gpr15 0xc0d763f8 gpr16 0x0 gpr17 0xc01e4ddcf000 gpr18 0x0 gpr19 0xc00ffa305000 gpr20 0xc01e4df038c0 gpr21 0xc01e40ed7a00 gpr22 0xc00aa28c gpr23 0xc0cdd100 gpr24 0x0 gpr25 0xc0cdd100 gpr26 0xc01e4df038b0 gpr27 0xfeae gpr28 0xc01e4df03880 gpr29 0xc0dce900 gpr30 0xc01e4df03890 gpr31 0xc01e355c7a30 nip 0xc01a62d8 msr 0x90009032 orig_r3 0xc01a6320 ctr 0xc00a7be0 lnk 0xc01a6428 xer 0x0 ccr 0x24022888 trap 0xf01 dar 0xc01e40ed7a00 dsisr 0x3000c006004 ... thread: :7803:7803 .. dso: /root/.debug/.build-id/d0/eb47b06c0d294143af13c50616f638c2d88658 :7803 7803 178.329381: 1 cycles: c000fd9c .arch_local_irq_restore (/boot/vmlinux) Changes from V5: - Enabled perf_sample_regs_user also in this patch set.Functions added in arch/powerpc/perf/perf_regs.c - Added Maddy's patch to this patchset for enabling -I? option which will list the supported register names. Changes from V4: - Removed the softe and MQ from all patches - Switch case is replaced with an array in the 3rd patch Changes from V3: - Addressed the comments by Sukadev regarding the nits in the descriptions. - Modified the subject of first patch. - Included the sample output in the 3rd patch also. Changes from V2: - tools/perf/config/Makefile is moved to the patch tools/perf. - The patchset is reordered. - perf_regs_load() function is used for the dwarf unwind test.Since it is not required here, it is removed from tools/perf/arch/powerpc/include/perf_regs.h - PERF_REGS_POWERPC_RESULT is removed. Changes from V1: - Solved the name missmatch issue in the from and signed-off field of the patch series. - Added necessary comments in the 3rd patch ie perf/powerpc ,as suggested by Maddy. Anju T (3): perf/powerpc: assign an id to each powerpc register perf/powerpc: add support for sampling intr machine state tools/perf: Map the ID values with register names Madhavan Srinivasan (1): tool/perf: Add sample_reg_mask to include all perf_regs regs arch/powerpc/Kconfig| 1 + arch/powerpc/include/uapi/asm/perf_regs.h | 49 + arch/powerpc/perf/Makefile | 1 + arch/powerpc/perf/perf_regs.c | 85 + tools/perf/arch/powerpc/include/perf_regs.h | 65 ++ tools/perf/arch/powerpc/util/Build | 1 + tools/perf/arch/powerpc/util/perf_regs.c| 48 tools/perf/config/Makefile | 5 ++ 8 files changed, 255 insertions(+) create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h create mode 100644 arch/powerpc/perf/perf_regs.c create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h create mode 100644 tools/perf/arch/powerpc/util/perf_regs.c -- 2.1.0 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 1/4] perf/powerpc: assign an id to each powerpc register
The enum definition assigns an 'id' to each register in "struct pt_regs"
of arch/powerpc. The order of these values in the enum definition are
based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h.
Signed-off-by: Anju T
Reviewed-by : Madhavan Srinivasan
---
arch/powerpc/include/uapi/asm/perf_regs.h | 49 +++
1 file changed, 49 insertions(+)
create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h
b/arch/powerpc/include/uapi/asm/perf_regs.h
new file mode 100644
index 000..cfbd068
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -0,0 +1,49 @@
+#ifndef _ASM_POWERPC_PERF_REGS_H
+#define _ASM_POWERPC_PERF_REGS_H
+
+enum perf_event_powerpc_regs {
+ PERF_REG_POWERPC_GPR0,
+ PERF_REG_POWERPC_GPR1,
+ PERF_REG_POWERPC_GPR2,
+ PERF_REG_POWERPC_GPR3,
+ PERF_REG_POWERPC_GPR4,
+ PERF_REG_POWERPC_GPR5,
+ PERF_REG_POWERPC_GPR6,
+ PERF_REG_POWERPC_GPR7,
+ PERF_REG_POWERPC_GPR8,
+ PERF_REG_POWERPC_GPR9,
+ PERF_REG_POWERPC_GPR10,
+ PERF_REG_POWERPC_GPR11,
+ PERF_REG_POWERPC_GPR12,
+ PERF_REG_POWERPC_GPR13,
+ PERF_REG_POWERPC_GPR14,
+ PERF_REG_POWERPC_GPR15,
+ PERF_REG_POWERPC_GPR16,
+ PERF_REG_POWERPC_GPR17,
+ PERF_REG_POWERPC_GPR18,
+ PERF_REG_POWERPC_GPR19,
+ PERF_REG_POWERPC_GPR20,
+ PERF_REG_POWERPC_GPR21,
+ PERF_REG_POWERPC_GPR22,
+ PERF_REG_POWERPC_GPR23,
+ PERF_REG_POWERPC_GPR24,
+ PERF_REG_POWERPC_GPR25,
+ PERF_REG_POWERPC_GPR26,
+ PERF_REG_POWERPC_GPR27,
+ PERF_REG_POWERPC_GPR28,
+ PERF_REG_POWERPC_GPR29,
+ PERF_REG_POWERPC_GPR30,
+ PERF_REG_POWERPC_GPR31,
+ PERF_REG_POWERPC_NIP,
+ PERF_REG_POWERPC_MSR,
+ PERF_REG_POWERPC_ORIG_R3,
+ PERF_REG_POWERPC_CTR,
+ PERF_REG_POWERPC_LNK,
+ PERF_REG_POWERPC_XER,
+ PERF_REG_POWERPC_CCR,
+ PERF_REG_POWERPC_TRAP,
+ PERF_REG_POWERPC_DAR,
+ PERF_REG_POWERPC_DSISR,
+ PERF_REG_POWERPC_MAX,
+};
+#endif /* _ASM_POWERPC_PERF_REGS_H */
--
2.1.0
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[PATCH V6 3/4] tools/perf: Map the ID values with register names
Map ID values with corresponding register names. These names are then
displayed when user issues perf record with the -I option
followed by perf report/script with -D option.
To test this patchset,
Eg:
$ perf record -I ls # record machine state at interrupt
$ perf script -D # read the perf.data file
Sample output obtained for this patch / output looks like as follows:
178329381464 0x138 [0x180]: PERF_RECORD_SAMPLE(IP, 0x1): 7803/7803:
0xc000fd9c period: 1 addr: 0
... intr regs: mask 0x3ff ABI 64-bit
gpr0 0xc01a6420
gpr1 0xc01e4df039b0
gpr2 0xc0cdd100
gpr3 0x1
gpr4 0xc01e4a96d000
gpr5 0x29854255ba
gpr6 0xc00ffa3050b8
gpr7 0x0
gpr8 0x0
gpr9 0x0
gpr10 0x0
gpr11 0x0
gpr12 0x24022822
gpr13 0xcfe03000
gpr14 0x0
gpr15 0xc0d763f8
gpr16 0x0
gpr17 0xc01e4ddcf000
gpr18 0x0
gpr19 0xc00ffa305000
gpr20 0xc01e4df038c0
gpr21 0xc01e40ed7a00
gpr22 0xc00aa28c
gpr23 0xc0cdd100
gpr24 0x0
gpr25 0xc0cdd100
gpr26 0xc01e4df038b0
gpr27 0xfeae
gpr28 0xc01e4df03880
gpr29 0xc0dce900
gpr30 0xc01e4df03890
gpr31 0xc01e355c7a30
nip 0xc01a62d8
msr 0x90009032
orig_r3 0xc01a6320
ctr 0xc00a7be0
lnk 0xc01a6428
xer 0x0
ccr 0x24022888
trap 0xf01
dar 0xc01e40ed7a00
dsisr 0x3000c006004
... thread: :7803:7803
.. dso: /root/.debug/.build-id/d0/eb47b06c0d294143af13c50616f638c2d88658
:7803 7803 178.329381: 1 cycles: c000fd9c
.arch_local_irq_restore (/boot/vmlinux)
Signed-off-by: Anju T
Reviewed-by : Madhavan Srinivasan
---
tools/perf/arch/powerpc/include/perf_regs.h | 65 +
tools/perf/config/Makefile | 5 +++
2 files changed, 70 insertions(+)
create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
diff --git a/tools/perf/arch/powerpc/include/perf_regs.h
b/tools/perf/arch/powerpc/include/perf_regs.h
new file mode 100644
index 000..b4f62a3
--- /dev/null
+++ b/tools/perf/arch/powerpc/include/perf_regs.h
@@ -0,0 +1,65 @@
+#ifndef ARCH_PERF_REGS_H
+#define ARCH_PERF_REGS_H
+
+#include
+#include
+#include
+
+#define PERF_REGS_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
+#define PERF_REGS_MAX PERF_REG_POWERPC_MAX
+#define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_64
+
+#define PERF_REG_IP PERF_REG_POWERPC_NIP
+#define PERF_REG_SP PERF_REG_POWERPC_R1
+
+static const char *perf_reg_names[] = {
+ [PERF_REG_POWERPC_GPR0] = "gpr0",
+ [PERF_REG_POWERPC_GPR1] = "gpr1",
+ [PERF_REG_POWERPC_GPR2] = "gpr2",
+ [PERF_REG_POWERPC_GPR3] = "gpr3",
+ [PERF_REG_POWERPC_GPR4] = "gpr4",
+ [PERF_REG_POWERPC_GPR5] = "gpr5",
+ [PERF_REG_POWERPC_GPR6] = "gpr6",
+ [PERF_REG_POWERPC_GPR7] = "gpr7",
+ [PERF_REG_POWERPC_GPR8] = "gpr8",
+ [PERF_REG_POWERPC_GPR9] = "gpr9",
+ [PERF_REG_POWERPC_GPR10] = "gpr10",
+ [PERF_REG_POWERPC_GPR11] = "gpr11",
+ [PERF_REG_POWERPC_GPR12] = "gpr12",
+ [PERF_REG_POWERPC_GPR13] = "gpr13",
+ [PERF_REG_POWERPC_GPR14] = "gpr14",
+ [PERF_REG_POWERPC_GPR15] = "gpr15",
+ [PERF_REG_POWERPC_GPR16] = "gpr16",
+ [PERF_REG_POWERPC_GPR17] = "gpr17",
+ [PERF_REG_POWERPC_GPR18] = "gpr18",
+ [PERF_REG_POWERPC_GPR19] = "gpr19",
+ [PERF_REG_POWERPC_GPR20] = "gpr20",
+ [PERF_REG_POWERPC_GPR21] = "gpr21",
+ [PERF_REG_POWERPC_GPR22] = "gpr22",
+ [PERF_REG_POWERPC_GPR23] = "gpr23",
+ [PERF_REG_POWERPC_GPR24] = "gpr24",
+ [PERF_REG_POWERPC_GPR25] = "gpr25",
+ [PERF_REG_POWERPC_GPR26] = "gpr26",
+ [PERF_REG_POWERPC_GPR27] = "gpr27",
+ [PERF_REG_POWERPC_GPR28] = "gpr28",
+ [PERF_REG_POWERPC_GPR29] = "gpr29",
+ [PERF_REG_POWERPC_GPR30] = "gpr30",
+ [PERF_REG_POWERPC_GPR31] = "gpr31",
+ [PERF_REG_POWERPC_NIP] = "nip",
+ [PERF_REG_POWERPC_MSR] = "msr",
+ [PERF_REG_POWERPC_ORIG_R3] = "orig_r3",
+ [PERF_REG_POWERPC_CTR] = "ctr",
+ [PERF_REG_POWERPC_LNK] = "lnk",
+ [PERF_REG_POWERPC_XER] = "xer",
+ [PERF_REG_POWERPC_CCR] = "ccr",
+ [PERF_REG_POWERPC_TRAP] = "trap",
+ [PERF_REG_POWERPC_DAR] = "dar",
+ [PERF_REG_POWERPC_DSISR] = "dsisr"
+};
+
+static inline const char *perf_reg_name(int id)
+{
+
+ return perf_reg_names[id];
+}
+#endif /* ARCH_PERF_REGS_H */
diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile
index 38a0853..acf0302 100644
--- a/tools/perf/config/Makefile
+++ b/tools/perf/config/Makefile
@@ -23,6 +23,11 @@ $(call detected_var,ARCH)
NO_PERF_REGS := 1
+# Additional ARCH settings for ppc64
+ifeq ($(ARCH),powerpc)
+ NO_PERF_REGS := 0
+endif
+
# Addition
[PATCH V1 4/4] tool/perf: Add sample_reg_mask to include all perf_regs regs
From: Madhavan Srinivasan
Add sample_reg_mask array with pt_regs registers.
This is needed for printing supported regs ( -I? option).
Signed-off-by: Madhavan Srinivasan
---
tools/perf/arch/powerpc/util/Build | 1 +
tools/perf/arch/powerpc/util/perf_regs.c | 48
2 files changed, 49 insertions(+)
create mode 100644 tools/perf/arch/powerpc/util/perf_regs.c
diff --git a/tools/perf/arch/powerpc/util/Build
b/tools/perf/arch/powerpc/util/Build
index 7b8b0d1..3deb1bc 100644
--- a/tools/perf/arch/powerpc/util/Build
+++ b/tools/perf/arch/powerpc/util/Build
@@ -1,5 +1,6 @@
libperf-y += header.o
libperf-y += sym-handling.o
+libperf-y += perf_regs.o
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_DWARF) += skip-callchain-idx.o
diff --git a/tools/perf/arch/powerpc/util/perf_regs.c
b/tools/perf/arch/powerpc/util/perf_regs.c
new file mode 100644
index 000..0b0ec65
--- /dev/null
+++ b/tools/perf/arch/powerpc/util/perf_regs.c
@@ -0,0 +1,48 @@
+#include "../../perf.h"
+#include "../../util/perf_regs.h"
+
+const struct sample_reg sample_reg_masks[] = {
+ SMPL_REG(gpr0, PERF_REG_POWERPC_GPR0),
+ SMPL_REG(gpr1, PERF_REG_POWERPC_GPR1),
+ SMPL_REG(gpr2, PERF_REG_POWERPC_GPR2),
+ SMPL_REG(gpr3, PERF_REG_POWERPC_GPR3),
+ SMPL_REG(gpr4, PERF_REG_POWERPC_GPR4),
+ SMPL_REG(gpr5, PERF_REG_POWERPC_GPR5),
+ SMPL_REG(gpr6, PERF_REG_POWERPC_GPR6),
+ SMPL_REG(gpr7, PERF_REG_POWERPC_GPR7),
+ SMPL_REG(gpr8, PERF_REG_POWERPC_GPR8),
+ SMPL_REG(gpr9, PERF_REG_POWERPC_GPR9),
+ SMPL_REG(gpr10, PERF_REG_POWERPC_GPR10),
+ SMPL_REG(gpr11, PERF_REG_POWERPC_GPR11),
+ SMPL_REG(gpr12, PERF_REG_POWERPC_GPR12),
+ SMPL_REG(gpr13, PERF_REG_POWERPC_GPR13),
+ SMPL_REG(gpr14, PERF_REG_POWERPC_GPR14),
+ SMPL_REG(gpr15, PERF_REG_POWERPC_GPR15),
+ SMPL_REG(gpr16, PERF_REG_POWERPC_GPR16),
+ SMPL_REG(gpr17, PERF_REG_POWERPC_GPR17),
+ SMPL_REG(gpr18, PERF_REG_POWERPC_GPR18),
+ SMPL_REG(gpr19, PERF_REG_POWERPC_GPR19),
+ SMPL_REG(gpr20, PERF_REG_POWERPC_GPR20),
+ SMPL_REG(gpr21, PERF_REG_POWERPC_GPR21),
+ SMPL_REG(gpr22, PERF_REG_POWERPC_GPR22),
+ SMPL_REG(gpr23, PERF_REG_POWERPC_GPR23),
+ SMPL_REG(gpr24, PERF_REG_POWERPC_GPR24),
+ SMPL_REG(gpr25, PERF_REG_POWERPC_GPR25),
+ SMPL_REG(gpr26, PERF_REG_POWERPC_GPR26),
+ SMPL_REG(gpr27, PERF_REG_POWERPC_GPR27),
+ SMPL_REG(gpr28, PERF_REG_POWERPC_GPR28),
+ SMPL_REG(gpr29, PERF_REG_POWERPC_GPR29),
+ SMPL_REG(gpr30, PERF_REG_POWERPC_GPR30),
+ SMPL_REG(gpr31, PERF_REG_POWERPC_GPR31),
+ SMPL_REG(nip, PERF_REG_POWERPC_NIP),
+ SMPL_REG(msr, PERF_REG_POWERPC_MSR),
+ SMPL_REG(orig_r3, PERF_REG_POWERPC_ORIG_R3),
+ SMPL_REG(ctr, PERF_REG_POWERPC_CTR),
+ SMPL_REG(link, PERF_REG_POWERPC_LNK),
+ SMPL_REG(xer, PERF_REG_POWERPC_XER),
+ SMPL_REG(ccr, PERF_REG_POWERPC_CCR),
+ SMPL_REG(trap, PERF_REG_POWERPC_TRAP),
+ SMPL_REG(dar, PERF_REG_POWERPC_DAR),
+ SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
+ SMPL_REG_END
+};
--
2.1.0
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V6 2/4] perf/powerpc: add support for sampling intr machine state
The perf infrastructure uses a bit mask to find out valid
registers to display. Define a register mask for supported
registers defined in asm/perf_regs.h. The bit positions also
correspond to register IDs which is used by perf infrastructure
to fetch the register values. CONFIG_HAVE_PERF_REGS enables
sampling of the interrupted machine state.
Signed-off-by: Anju T
Reviewed-by : Madhavan Srinivasan
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/perf/Makefile| 1 +
arch/powerpc/perf/perf_regs.c | 85 +++
3 files changed, 87 insertions(+)
create mode 100644 arch/powerpc/perf/perf_regs.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9a7057e..c4ce60d 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -119,6 +119,7 @@ config PPC
select GENERIC_ATOMIC64 if PPC32
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select HAVE_PERF_EVENTS
+ select HAVE_PERF_REGS
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
select ARCH_WANT_IPC_PARSE_VERSION
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index f9c083a..2f2d3d2 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -8,6 +8,7 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o
power5-pmu.o \
power8-pmu.o
obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
+obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
new file mode 100644
index 000..d32581763
--- /dev/null
+++ b/arch/powerpc/perf/perf_regs.c
@@ -0,0 +1,85 @@
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
+
+#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
+
+static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR3, gpr[3]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR4, gpr[4]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR5, gpr[5]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR6, gpr[6]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR7, gpr[7]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR8, gpr[8]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR9, gpr[9]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR10, gpr[10]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR11, gpr[11]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR12, gpr[12]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR13, gpr[13]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR14, gpr[14]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR15, gpr[15]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR16, gpr[16]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR17, gpr[17]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR18, gpr[18]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR19, gpr[19]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR20, gpr[20]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR21, gpr[21]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR22, gpr[22]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR23, gpr[23]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR24, gpr[24]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR25, gpr[25]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR26, gpr[26]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR27, gpr[27]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR28, gpr[28]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR29, gpr[29]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR30, gpr[30]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR31, gpr[31]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_NIP, nip),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_MSR, msr),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_ORIG_R3, orig_gpr3),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_LNK, link),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_XER, xer),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_CCR, ccr),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
+};
+
+u64 perf_reg_value(struct pt_regs *regs, int idx)
+{
+ if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))
+ return 0;
+
+ return regs_get_register(regs, pt_regs_offset[idx]);
+}
+
+int perf_reg_validate(u64 mask)
+{
+ if (!mask || mask & REG_RESERVED)
+ return -EINVAL;
+ return 0;
+}
+
+u64 perf_reg_abi(struct task_struct *task)
+{
+ return PERF_SAMPLE_REGS_ABI_64;
+}
+
+void perf_get_regs_user(struct perf_regs *regs_user,
+ struct pt_regs *regs,
+
Re: [PATCH] cxl: Set endianess of kernel contexts
Acked-by: Ian Munsie ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
