Re: [PATCH 2/2] [PowerPC Book3E] Introduce new ptrace debug feature flag

2011-12-22 Thread K.Prasad 
On Wed, Dec 21, 2011 at 11:55:02AM +1100, David Gibson wrote:
> On Thu, Dec 08, 2011 at 04:53:30PM +0530, K.Prasad wrote:
> > While PPC_PTRACE_SETHWDEBUG ptrace flag in PowerPC accepts
> > PPC_BREAKPOINT_MODE_EXACT mode of breakpoint, the same is not intimated to 
> > the
> > user-space debuggers (like GDB) who may want to use it. Hence we introduce a
> > new PPC_DEBUG_FEATURE_DATA_BP_EXACT flag which will be populated on the
> > "features" member of "struct ppc_debug_info" to advertise support for the
> > same on Book3E PowerPC processors.
> 
> Hrm.  I had assumed the reason there wasn't a feature bit for EXACT
> originally was that EXACT breakpoints were *always* supposed to be
> supported by the new interface.
>

Okay. Although BookS doesn't support EXACT breakpoints, it is possible
(after the introduction of new hw-breakpoint interfaces) to request for
a breakpoint of length 1 Byte.

The hw-breakpoint infrastructure would take care of filtering the
extraneous interrupts arising out of accesses in the neighbourhood, in
such a case.

David,
Can you Ack this patch too, if you find the changes acceptable?

Thanks,
K.Prasad
 

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RE: [PATCH 1/2] mtd/nand: fixup for fmr initialization of Freescale NAND controller

2011-12-22 Thread Artem Bityutskiy 
On Tue, 2011-12-20 at 06:40 +, Liu Shengzhou-B36685 wrote:
> > -Original Message-
> > From: Artem Bityutskiy [mailto:dedeki...@gmail.com]
> > Sent: Saturday, December 17, 2011 10:45 PM
> > To: Liu Shengzhou-B36685
> > Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
> > dw...@infradead.org; Gala Kumar-B11780; linux-...@lists.infradead.org
> > Subject: Re: [PATCH 1/2] mtd/nand: fixup for fmr initialization of
> > Freescale NAND controller
> > 
> > On Mon, 2011-12-12 at 17:40 +0800, Shengzhou Liu wrote:
> > > There was a bug for fmr initialization, which lead to  fmr was always
> > > 0x100 in fsl_elbc_chip_init() and caused FCM command timeout before
> > > calling fsl_elbc_chip_init_tail(), now we initialize CWTO to maximum
> > > timeout value and not relying on the setting of bootloader.
> > >
> > > Signed-off-by: Shengzhou Liu 
> > 
> > Pushed both to l2-mtd-2.6.git, thanks!
> > 
> > --
> > Best Regards,
> > Artem Bityutskiy
> 
> I noted it had been applied in linux-next.git tree.
> Does it still need to l2-mtd-2.6.git? 
> Thanks.

It is in linux-next because it is pulled there from l2-mtd-2.6.git.
Thanks for head up, but no, it should stay in the l2-mtd-2.6.git.
David Woodhouse then should take care of merging the l2 tree upstream.

-- 
Best Regards,
Artem Bityutskiy


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[PATCH v3 1/4] powerpc/85xx: add HOTPLUG_CPU support

2011-12-22 Thread Zhao Chenhui 
From: Li Yang 

Add support to disable and re-enable individual cores at runtime
on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core.

MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off.
This patch uses the boot page from bootloader to boot core at runtime.
It supports 32-bit and 36-bit physical address.

Add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE in kick_cpu().

Signed-off-by: Li Yang 
Signed-off-by: Jin Qing 
Signed-off-by: Zhao Chenhui 
---
changes for v3
 * Move "out_be32(&spin_table->pir, hw_cpu)" after core reset.
 * Keep the default value of the BPTR register. Don't change it.
 * Merge the timebase patch.
 * Don't support e500mc for HOTPLUG_CPU.

 arch/powerpc/Kconfig  |5 +-
 arch/powerpc/include/asm/cacheflush.h |2 +
 arch/powerpc/include/asm/smp.h|2 +
 arch/powerpc/kernel/head_fsl_booke.S  |   28 +++
 arch/powerpc/kernel/smp.c |   10 +++
 arch/powerpc/platforms/85xx/smp.c |  145 +
 6 files changed, 154 insertions(+), 38 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7c93c7e..bf942b1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -213,7 +213,7 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
-  (PPC_85xx && !SMP) || PPC_86xx || PPC_PSERIES || 44x || 40x
+  PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x
 
 config PPC_DCR_NATIVE
bool
@@ -324,7 +324,8 @@ config SWIOTLB
 
 config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
-   depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC 
|| PPC_POWERNV)
+   depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || \
+   PPC_PMAC || PPC_POWERNV || (E500 && !PPC_E500MC))
---help---
  Say Y here to be able to disable and re-enable individual
  CPUs at runtime on SMP machines.
diff --git a/arch/powerpc/include/asm/cacheflush.h 
b/arch/powerpc/include/asm/cacheflush.h
index ab9e402..dd41442 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -30,6 +30,8 @@ extern void flush_dcache_page(struct page *page);
 #define flush_dcache_mmap_lock(mapping)do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)  do { } while (0)
 
+extern void flush_disable_L1(void);
+
 extern void __flush_icache_range(unsigned long, unsigned long);
 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index adba970..7517863 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -65,6 +65,7 @@ int generic_cpu_disable(void);
 void generic_cpu_die(unsigned int cpu);
 void generic_mach_cpu_die(void);
 void generic_set_cpu_dead(unsigned int cpu);
+void generic_set_cpu_up(unsigned int cpu);
 int generic_check_cpu_restart(unsigned int cpu);
 #endif
 
@@ -191,6 +192,7 @@ extern unsigned long __secondary_hold_spinloop;
 extern unsigned long __secondary_hold_acknowledge;
 extern char __secondary_hold;
 
+extern void __early_start(void);
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/kernel/head_fsl_booke.S 
b/arch/powerpc/kernel/head_fsl_booke.S
index 9f5d210..1d93272 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -1004,6 +1004,34 @@ _GLOBAL(flush_dcache_L1)
 
blr
 
+/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
+_GLOBAL(flush_disable_L1)
+   mflrr10
+   bl  flush_dcache_L1 /* Flush L1 d-cache */
+   mtlrr10
+
+   mfspr   r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
+   li  r5, 2
+   rlwimi  r4, r5, 0, 3
+
+   msync
+   isync
+   mtspr   SPRN_L1CSR0, r4
+   isync
+
+1: mfspr   r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */
+   andi.   r4, r4, 2
+   bne 1b
+
+   mfspr   r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */
+   li  r5, 2
+   rlwimi  r4, r5, 0, 3
+
+   mtspr   SPRN_L1CSR1, r4
+   isync
+
+   blr
+
 #ifdef CONFIG_SMP
 /* When we get here, r24 needs to hold the CPU # */
.globl __secondary_start
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index f0abe92..7b675bb 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -423,6 +423,16 @@ void generic_set_cpu_dead(unsigned int cpu)
per_cpu(cpu_state, cpu) = CPU_DEAD;
 }
 
+/*
+ * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
+ * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
+ * which makes the delay in generic_cpu_die() not happen.
+ */
+void generic_set_cpu_up(unsigned int cpu)
+{
+   per_cpu(cpu_stat

[PATCH v3 3/4] fsl_pmc: Add API to enable device as wakeup event source

2011-12-22 Thread Zhao Chenhui 
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.

Signed-off-by: Dave Liu 
Signed-off-by: Li Yang 
Signed-off-by: Jin Qing 
Signed-off-by: Zhao Chenhui 
---
 arch/powerpc/sysdev/fsl_pmc.c |   70 -
 arch/powerpc/sysdev/fsl_soc.h |9 +
 2 files changed, 78 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 618a52c..0c99591 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -32,6 +32,7 @@ struct pmc_regs {
__be32 powmgtcsr;
 #define POWMGTCSR_SLP_MASK 0x0002
 #define POWMGTCSR_DPSLP_MASK0x0010
+#define POWMGTCSR_LOSSLESS_MASK0x0040
__be32 res3[2];
__be32 pmcdr;
 };
@@ -41,6 +42,73 @@ static unsigned int pmc_flag;
 
 #define PMC_SLEEP  0x1
 #define PMC_DEEP_SLEEP 0x2
+#define PMC_LOSSLESS   0x4
+
+/**
+ * mpc85xx_pmc_set_wake - enable devices as wakeup event source
+ * @pdev: platform device affected
+ * @enable: True to enable event generation; false to disable
+ *
+ * This enables the device as a wakeup event source, or disables it.
+ *
+ * RETURN VALUE:
+ * 0 is returned on success
+ * -EINVAL is returned if device is not supposed to wake up the system
+ * Error code depending on the platform is returned if both the platform and
+ * the native mechanism fail to enable the generation of wake-up events
+ */
+int mpc85xx_pmc_set_wake(struct platform_device *pdev, bool enable)
+{
+   int ret = 0;
+   struct device_node *clk_np;
+   u32 pmcdr_mask;
+
+   if (!pmc_regs) {
+   pr_err("%s: PMC is unavailable\n", __func__);
+   return -ENODEV;
+   }
+
+   if (enable && !device_may_wakeup(&pdev->dev))
+   return -EINVAL;
+
+   clk_np = of_parse_phandle(pdev->dev.of_node, "clk-handle", 0);
+   if (!clk_np)
+   return -EINVAL;
+
+   if (of_property_read_u32(clk_np, "fsl,pmcdr-mask", &pmcdr_mask)) {
+   ret = -EINVAL;
+   goto out;
+   }
+
+   if (enable)
+   /* clear to enable clock in low power mode */
+   clrbits32(&pmc_regs->pmcdr, pmcdr_mask);
+   else
+   setbits32(&pmc_regs->pmcdr, pmcdr_mask);
+
+out:
+   of_node_put(clk_np);
+   return ret;
+}
+EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_wake);
+
+/**
+ * mpc85xx_pmc_set_lossless_ethernet - enable lossless ethernet
+ * in (deep) sleep mode
+ * @enable: True to enable event generation; false to disable
+ */
+void mpc85xx_pmc_set_lossless_ethernet(int enable)
+{
+   if (pmc_flag & PMC_LOSSLESS) {
+   if (enable)
+   setbits32(&pmc_regs->powmgtcsr,
+   POWMGTCSR_LOSSLESS_MASK);
+   else
+   clrbits32(&pmc_regs->powmgtcsr,
+   POWMGTCSR_LOSSLESS_MASK);
+   }
+}
+EXPORT_SYMBOL_GPL(mpc85xx_pmc_set_lossless_ethernet);
 
 static int pmc_suspend_enter(suspend_state_t state)
 {
@@ -117,7 +185,7 @@ static int pmc_probe(struct platform_device *pdev)
pmc_flag |= PMC_DEEP_SLEEP;
 
if (of_device_is_compatible(np, "fsl,p1022-pmc"))
-   pmc_flag |= PMC_DEEP_SLEEP;
+   pmc_flag |= PMC_DEEP_SLEEP | PMC_LOSSLESS;
 
suspend_set_ops(&pmc_suspend_ops);
 
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 949377d..29a87ee 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include 
+#include 
 
 struct spi_device;
 
@@ -21,6 +22,14 @@ struct device_node;
 
 extern void fsl_rstcr_restart(char *cmd);
 
+#ifdef CONFIG_FSL_PMC
+int mpc85xx_pmc_set_wake(struct platform_device *pdev, bool enable);
+void mpc85xx_pmc_set_lossless_ethernet(int enable);
+#else
+#define mpc85xx_pmc_set_wake(pdev, enable)
+#define mpc85xx_pmc_set_lossless_ethernet(enable)
+#endif
+
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 
 /* The different ports that the DIU can be connected to */
-- 
1.6.4.1


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[PATCH v3 2/4] powerpc/85xx: add sleep and deep sleep support

2011-12-22 Thread Zhao Chenhui 
From: Li Yang 

In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.

Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.

While in deep sleep PM mode, additionally, the power supply is
removed from e500 core and most IP blocks. Only the blocks needed
to wake up the chip out of deep sleep are ON.

This patch supports 32-bit and 36-bit address space.

The sleep mode is equal to the Standby state in Linux. The deep sleep
mode is equal to the Suspend-to-RAM state of Linux Power Management.

Command to enter sleep mode.
  echo standby > /sys/power/state
Command to enter deep sleep mode.
  echo mem > /sys/power/state

Signed-off-by: Dave Liu 
Signed-off-by: Li Yang 
Signed-off-by: Jin Qing 
Signed-off-by: Jerry Huang 
Cc: Scott Wood 
Signed-off-by: Zhao Chenhui 
---
 arch/powerpc/kernel/Makefile |3 +
 arch/powerpc/kernel/l2cache_85xx.S   |   53 +++
 arch/powerpc/platforms/85xx/Makefile |3 +
 arch/powerpc/platforms/85xx/sleep.S  |  609 ++
 arch/powerpc/sysdev/fsl_pmc.c|   91 -
 arch/powerpc/sysdev/fsl_soc.h|5 +
 6 files changed, 746 insertions(+), 18 deletions(-)
 create mode 100644 arch/powerpc/kernel/l2cache_85xx.S
 create mode 100644 arch/powerpc/platforms/85xx/sleep.S

diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index ce4f7f1..bfd687b 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -63,6 +63,9 @@ obj-$(CONFIG_CRASH_DUMP)  += crash_dump.o
 ifeq ($(CONFIG_PPC32),y)
 obj-$(CONFIG_E500) += idle_e500.o
 endif
+ifneq ($(CONFIG_PPC_E500MC),y)
+obj-$(CONFIG_PPC_85xx) += l2cache_85xx.o
+endif
 obj-$(CONFIG_6xx)  += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
 obj-$(CONFIG_TAU)  += tau_6xx.o
 obj-$(CONFIG_HIBERNATION)  += swsusp.o suspend.o
diff --git a/arch/powerpc/kernel/l2cache_85xx.S 
b/arch/powerpc/kernel/l2cache_85xx.S
new file mode 100644
index 000..95dfef0
--- /dev/null
+++ b/arch/powerpc/kernel/l2cache_85xx.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All rights reserved.
+ * Scott Wood 
+ * Dave Liu 
+ * implement the L2 cache operations of e500 based L2 controller
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+   .section .text
+
+   /* r3 = virtual address of L2 controller, WIMG = 01xx */
+_GLOBAL(flush_disable_L2)
+   /* It's a write-through cache, so only invalidation is needed. */
+   mbar
+   isync
+   lwz r4, 0(r3)
+   li  r5, 1
+   rlwimi  r4, r5, 30, 0xc000
+   stw r4, 0(r3)
+
+   /* Wait for the invalidate to finish */
+1: lwz r4, 0(r3)
+   andis.  r4, r4, 0x4000
+   bne 1b
+   mbar
+
+   blr
+
+   /* r3 = virtual address of L2 controller, WIMG = 01xx */
+_GLOBAL(invalidate_enable_L2)
+   mbar
+   isync
+   lwz r4, 0(r3)
+   li  r5, 3
+   rlwimi  r4, r5, 30, 0xc000
+   stw r4, 0(r3)
+
+   /* Wait for the invalidate to finish */
+1: lwz r4, 0(r3)
+   andis.  r4, r4, 0x4000
+   bne 1b
+   mbar
+
+   blr
diff --git a/arch/powerpc/platforms/85xx/Makefile 
b/arch/powerpc/platforms/85xx/Makefile
index 9cb2d43..f9fcbf4 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -2,6 +2,9 @@
 # Makefile for the PowerPC 85xx linux kernel.
 #
 obj-$(CONFIG_SMP) += smp.o
+ifneq ($(CONFIG_PPC_E500MC),y)
+obj-$(CONFIG_SUSPEND)  += sleep.o
+endif
 
 obj-y += common.o
 
diff --git a/arch/powerpc/platforms/85xx/sleep.S 
b/arch/powerpc/platforms/85xx/sleep.S
new file mode 100644
index 000..763d2f2
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/sleep.S
@@ -0,0 +1,609 @@
+/*
+ * Enter and leave deep sleep/sleep state on MPC85xx
+ *
+ * Author: Scott Wood 
+ *
+ * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define SS_TB  0x00
+#define SS_HID 0x08 /* 2 HIDs */
+#define SS_IAC 0x10 /* 2 IACs */
+#define SS_DAC 0x18 /* 2 DACs */
+#define SS_DBCR0x20 /* 3 DBCRs */
+#define SS_PID 0x2c /* 3 PIDs */
+#define SS_SPRG0x38 /* 8 SPRGs */
+#define SS_IVOR0x58 /* 20 interrupt vectors */
+#define SS_TCR 0xa8
+#define SS_BUCSR   0xac
+

[PATCH v3 4/4] fsl_pmc: update device bindings

2011-12-22 Thread Zhao Chenhui 
From: Li Yang 

Signed-off-by: Li Yang 
---
 .../devicetree/bindings/powerpc/fsl/pmc.txt|   63 +++
 1 files changed, 36 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
index 07256b7..d84b4f8 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
@@ -9,22 +9,27 @@ Properties:
 
   "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
   compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
-  whose PMC is compatible, and implies deep-sleep capability.
+  whose PMC is compatible, and implies deep-sleep capability and
+  wake on user defined packet(wakeup on ARP).
+
+  "fsl,p1022-pmc" should be listed for any chip whose PMC is
+  compatible, and implies lossless Ethernet capability during sleep.
 
   "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
   compatible; all statements below that apply to "fsl,mpc8548-pmc" also
   apply to "fsl,mpc8641d-pmc".
 
   Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
-  bit assignments are indicated via the sleep specifier in each device's
-  sleep property.
+  bit assignments are indicated via the clock nodes.  Device which has a
+  controllable clock source should have a "clk-handle" property pointing
+  to the clock node.
 
 - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
   is the PMC block, and the second resource is the Clock Configuration
   block.
 
-  For devices compatible with "fsl,mpc8548-pmc", the first resource
-  is a 32-byte block beginning with DEVDISR.
+  For devices compatible with "fsl,mpc8548-pmc", the second resource
+  is a 32-byte block beginning with DEVDISR if supported.
 
 - interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
   resource is the PMC block interrupt.
@@ -33,31 +38,35 @@ Properties:
   this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
   a wakeup source from deep sleep.
 
-Sleep specifiers:
+Clock nodes:
+The clock nodes are to describe the masks in PM controller registers for each
+soc clock.
+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
+  ORed into PMCDR before suspend if the device using this clock is the wake-up
+  source and need to be running during low power mode; clear the mask if
+  otherwise.
 
-  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
-  that is set in the cell, the corresponding bit in SCCR will be saved
-  and cleared on suspend, and restored on resume.  This sleep controller
-  supports disabling and resuming devices at any time.
+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
+  bit specified by the mask in SCCR will be saved and cleared on suspend, and
+  restored on resume.
 
-  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
-  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
-  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
-  This sleep controller only supports disabling devices during system
-  sleep, or permanently.
-
-  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
-  first of which will be ORed into DEVDISR (and the second into
-  DEVDISR2, if present -- this cell should be zero or absent if the
-  hardware does not have DEVDISR2) upon a request for permanent device
-  disabling.  This sleep controller does not support configuring devices
-  to disable during system sleep (unless supported by another compatible
-  match), or dynamically.
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
+  DEVDISR2 register.  For compatible devices, the mask will be ORed into 
DEVDISR
+  or DEVDISR2 when the clock should be permenently disabled.
 
 Example:
 
-   power@b00 {
-   compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
-   reg = <0xb00 0x100 0xa00 0x100>;
-   interrupts = <80 8>;
+   power@e0070 {
+   compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+   reg = <0xe0070 0x20>;
+
+   etsec1_clk: soc-clk@24 {
+   fsl,pmcdr-mask = <0x0080>;
+   };
+   etsec2_clk: soc-clk@25 {
+   fsl,pmcdr-mask = <0x0040>;
+   };
+   etsec3_clk: soc-clk@26 {
+   fsl,pmcdr-mask = <0x0020>;
+   };
};
-- 
1.6.4.1


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Re: next BUG: using smp_processor_id() in preemptible

2011-12-22 Thread Hugh Dickins 
On Mon, 5 Dec 2011, Hugh Dickins wrote:

> 3.2.0-rc3-next-20111202 with CONFIG_DEBUG_PREEMPT=y gives me lots of
> 
> Dec  4 20:03:19 thorn kernel: BUG: using smp_processor_id() in preemptible 
> [] code: startpar/1365
> Dec  4 20:03:19 thorn kernel: caller is .arch_local_irq_restore+0x44/0x90
> Dec  4 20:03:19 thorn kernel: Call Trace:
> Dec  4 20:03:19 thorn kernel: [c001b45a7c60] [c0011fe8] 
> .show_stack+0x6c/0x16c (unreliable)
> Dec  4 20:03:19 thorn kernel: [c001b45a7d10] [c024318c] 
> .debug_smp_processor_id+0xe4/0x11c
> Dec  4 20:03:19 thorn kernel: [c001b45a7da0] [c000e2e8] 
> .arch_local_irq_restore+0x44/0x90
> Dec  4 20:03:19 thorn kernel: [c001b45a7e30] [c0005870] 
> .do_hash_page+0x70/0x74
> Dec  4 20:03:21 thorn kernel: debug_smp_processor_id: 21950 callbacks 
> suppressed
> 
> from the u64 *next_tb = &__get_cpu_var(decrementers_next_tb)
> in decrementer_check_overflow(): I've no idea whether it's safe
> just to use get_cpu_var then put_cpu_var there instead,
> but no hurry, I can survive with DEBUG_PREEMPT off.

Still a problem in 3.2.0-rc6-next-20111222

Hugh
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AUTO: Michael Barry is out of the office (returning 04/01/2012)

2011-12-22 Thread Michael Barry 

I am out of the office until 04/01/2012.




Note: This is an automated response to your message  "Linuxppc-dev Digest,
Vol 88, Issue 109" sent on 20/12/2011 19:28:09.

This is the only notification you will receive while this person is away.

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[PATCH] arch/powerpc/kvm/e500: Additional module.h => export.h fixup

2011-12-22 Thread Kyle Moffett 
This file, like many others, needs to include .

Signed-off-by: Kyle Moffett 
---
 arch/powerpc/kvm/e500.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index 26d2090..387c383 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -13,6 +13,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
-- 
1.7.7.3

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[PATCH] powerpc/currituck: Fix up missing MPIC_PRIMARY flag

2011-12-22 Thread Kyle Moffett 
The 44x/currituck platform didn't get updated when the MPIC code
inverted the flag from MPIC_PRIMARY => !MPIC_SECONDARY.  Fix it up.

Signed-off-by: Kyle Moffett 
---
 arch/powerpc/platforms/44x/currituck.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/44x/currituck.c 
b/arch/powerpc/platforms/44x/currituck.c
index 1fdf569..3f6229b 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -83,7 +83,7 @@ static void __init ppc47x_init_irq(void)
 * device-tree, just pass 0 to all arguments
 */
struct mpic *mpic =
-   mpic_alloc(np, 0, MPIC_PRIMARY, 0, 0, " MPIC ");
+   mpic_alloc(np, 0, 0, 0, 0, " MPIC ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
ppc_md.get_irq = mpic_get_irq;
-- 
1.7.7.3

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[PATCH] fsl/mpic: Document and use the "big-endian" device-tree flag

2011-12-22 Thread Kyle Moffett 
The MPIC code checks for a "big-endian" property and sets the flag
MPIC_BIG_ENDIAN if one is present.  Unfortunately, the PowerQUICC-III
compatible device-tree does not specify it, so all of the board ports
need to manually set that flag when calling mpic_alloc().

Document the flag and add it to the pq3 device tree.  Existing code
will still need to pass the MPIC_BIG_ENDIAN flag because their dtb may
not have this property, but new platforms shouldn't need to do so.

Signed-off-by: Kyle Moffett 
---
 .../devicetree/bindings/powerpc/fsl/mpic.txt   |9 -
 arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi|1 +
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index 2cf38bd..ebafba2 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -56,7 +56,14 @@ PROPERTIES
   to the client.  The presence of this property also mandates
   that any initialization related to interrupt sources shall
   be limited to sources explicitly referenced in the device tree.
-   
+
+  - big-endian
+  Usage: optional
+  Value type: 
+  If present the MPIC will be assumed to be big-endian.  Some
+  device-trees omit this property on MPIC nodes even when the MPIC is
+  in fact big-endian, so certain boards override this property.
+
 INTERRUPT SPECIFIER DEFINITION
 
   Interrupt specifiers consists of 4 cells encoded as
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 5c80460..47f2b67 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -39,6 +39,7 @@ mpic: pic@4 {
reg = <0x4 0x4>;
compatible = "fsl,mpic";
device_type = "open-pic";
+   big-endian;
 };
 
 timer@41100 {
-- 
1.7.7.3

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Re: [PATCH] powerpc/currituck: Fix up missing MPIC_PRIMARY flag

2011-12-22 Thread Josh Boyer 
On Thu, Dec 22, 2011 at 11:21 AM, Kyle Moffett
 wrote:
> The 44x/currituck platform didn't get updated when the MPIC code
> inverted the flag from MPIC_PRIMARY => !MPIC_SECONDARY.  Fix it up.
>
> Signed-off-by: Kyle Moffett 

I already included this fixup in my 4xx tree 'next' branch.  A pull
request was sent to Ben as well.

http://git.infradead.org/users/jwboyer/powerpc-4xx.git/commitdiff/eb975652b8fa0c4f08a52744d34bdebf66589d4b

josh
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Re: [PATCH v3 4/4] fsl_pmc: update device bindings

2011-12-22 Thread Scott Wood 
On 12/22/2011 05:43 AM, Zhao Chenhui wrote:
>Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
> -  bit assignments are indicated via the sleep specifier in each device's
> -  sleep property.
> +  bit assignments are indicated via the clock nodes.  Device which has a
> +  controllable clock source should have a "clk-handle" property pointing
> +  to the clock node.

fsl,pmc-handle

>  - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
>is the PMC block, and the second resource is the Clock Configuration
>block.
>  
> -  For devices compatible with "fsl,mpc8548-pmc", the first resource
> -  is a 32-byte block beginning with DEVDISR.
> +  For devices compatible with "fsl,mpc8548-pmc", the second resource
> +  is a 32-byte block beginning with DEVDISR if supported.

What's going on here?

-Scott

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Re: [PATCH v3 4/4] fsl_pmc: update device bindings

2011-12-22 Thread Scott Wood 
On 12/22/2011 05:43 AM, Zhao Chenhui wrote:
> From: Li Yang 
> 
> Signed-off-by: Li Yang 
> ---
>  .../devicetree/bindings/powerpc/fsl/pmc.txt|   63 +++
>  1 files changed, 36 insertions(+), 27 deletions(-)

Pleace CC devicetree-disc...@lists.ozlabs.org on all changes to device
tree bindings.

-Scott

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[PATCH 0/6] powerpc/mpic: More general cleanups and fixups

2011-12-22 Thread Kyle Moffett 
Hello all,

With the following series of patches, most new MPC85xx platforms should
be able to get away with just this code (assuming updated dtb):

  struct mpic *mpic = mpic_alloc(NULL, 0, 0, 0, "OpenPIC");
  mpic_init(mpic);

Several of the hard-coded flags can now be provided as properties in
the device-tree, and hopefully future tweaks can be hooked in the same
way.

Cheers,
Kyle Moffett

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[PATCH 1/6] powerpc/mpic: Fix use of "flags" variable in mpic_alloc()

2011-12-22 Thread Kyle Moffett 
The mpic_alloc() function takes a "flags" parameter and assigns it into
the mpic->flags variable fairly early on, but several later pieces of
code detect various device-tree properties and save them into the
"mpic->flags" variable (EG: "big-endian" => MPIC_BIG_ENDIAN).

Unfortunately, a number of codepaths (including several which test the
flag MPIC_BIG_ENDIAN!) test "flags" instead of "mpic->flags", and get
wrong answers as a result.

Consolidate the device-tree flag tests early in mpic_alloc() and change
all of the checks after "mpic->flags" is init'ed to use "mpic->flags".

Signed-off-by: Kyle Moffett 
---
 arch/powerpc/sysdev/mpic.c |   46 +--
 1 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 4e9ccb1..9dd7f76 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1182,6 +1182,14 @@ struct mpic * __init mpic_alloc(struct device_node *node,
}
}
 
+   /* Read extra device-tree properties into the flags variable */
+   if (of_get_property(mpic->node, "big-endian", NULL))
+   flags |= MPIC_BIG_ENDIAN;
+   if (of_get_property(mpic->node, "pic-no-reset", NULL))
+   flags |= MPIC_NO_RESET;
+   if (of_device_is_compatible(mpic->node, "fsl,mpic"))
+   flags |= MPIC_FSL;
+
mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
if (mpic == NULL)
goto err_of_node_put;
@@ -1189,15 +1197,16 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
mpic->name = name;
mpic->node = node;
mpic->paddr = phys_addr;
+   mpic->flags = flags;
 
mpic->hc_irq = mpic_irq_chip;
mpic->hc_irq.name = name;
-   if (!(flags & MPIC_SECONDARY))
+   if (!(mpic->flags & MPIC_SECONDARY))
mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
mpic->hc_ht_irq = mpic_irq_ht_chip;
mpic->hc_ht_irq.name = name;
-   if (!(flags & MPIC_SECONDARY))
+   if (!(mpic->flags & MPIC_SECONDARY))
mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 
@@ -1209,12 +1218,11 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
mpic->hc_tm = mpic_tm_chip;
mpic->hc_tm.name = name;
 
-   mpic->flags = flags;
mpic->isu_size = isu_size;
mpic->irq_count = irq_count;
mpic->num_sources = 0; /* so far */
 
-   if (flags & MPIC_LARGE_VECTORS)
+   if (mpic->flags & MPIC_LARGE_VECTORS)
intvec_top = 2047;
else
intvec_top = 255;
@@ -1233,12 +1241,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic->ipi_vecs[3]   = intvec_top - 1;
mpic->spurious_vec  = intvec_top;
 
-   /* Check for "big-endian" in device-tree */
-   if (of_get_property(mpic->node, "big-endian", NULL) != NULL)
-   mpic->flags |= MPIC_BIG_ENDIAN;
-   if (of_device_is_compatible(mpic->node, "fsl,mpic"))
-   mpic->flags |= MPIC_FSL;
-
/* Look for protected sources */
psrc = of_get_property(mpic->node, "protected-sources", &psize);
if (psrc) {
@@ -1254,11 +1256,11 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
}
 
 #ifdef CONFIG_MPIC_WEIRD
-   mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
+   mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
 #endif
 
/* default register type */
-   if (flags & MPIC_BIG_ENDIAN)
+   if (mpic->flags & MPIC_BIG_ENDIAN)
mpic->reg_type = mpic_access_mmio_be;
else
mpic->reg_type = mpic_access_mmio_le;
@@ -1268,10 +1270,10 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
 * only if the kernel includes DCR support.
 */
 #ifdef CONFIG_PPC_DCR
-   if (flags & MPIC_USES_DCR)
+   if (mpic->flags & MPIC_USES_DCR)
mpic->reg_type = mpic_access_dcr;
 #else
-   BUG_ON(flags & MPIC_USES_DCR);
+   BUG_ON(mpic->flags & MPIC_USES_DCR);
 #endif
 
/* Map the global registers */
@@ -1283,10 +1285,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
/* When using a device-node, reset requests are only honored if the MPIC
 * is allowed to reset.
 */
-   if (of_get_property(mpic->node, "pic-no-reset", NULL))
-   mpic->flags |= MPIC_NO_RESET;
-
-   if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
+   if ((mpic->flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) 
{
printk(KERN_DEBUG "mpic: Resetting\n");
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
@@ -1297,12 +1296,12 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,

[PATCH 2/6] fsl/mpic: Document and use the "big-endian" device-tree flag

2011-12-22 Thread Kyle Moffett 
The MPIC code checks for a "big-endian" property and sets the flag
MPIC_BIG_ENDIAN if one is present, although prior to the "mpic->flags"
fixup that would never have worked anways.

Unfortunately, even now that it works properly, the Freescale mpic
device-node (the "PowerQUICC-III"-compatible one) does not specify it,
so all of the board ports need to manually pass it to mpic_alloc().

Document the flag and add it to the pq3 device tree.  Existing code will
still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not
have this property, but new platforms shouldn't need to do so.

Signed-off-by: Kyle Moffett 
---
 .../devicetree/bindings/powerpc/fsl/mpic.txt   |9 -
 arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi|1 +
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index 2cf38bd..ebafba2 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -56,7 +56,14 @@ PROPERTIES
   to the client.  The presence of this property also mandates
   that any initialization related to interrupt sources shall
   be limited to sources explicitly referenced in the device tree.
-   
+
+  - big-endian
+  Usage: optional
+  Value type: 
+  If present the MPIC will be assumed to be big-endian.  Some
+  device-trees omit this property on MPIC nodes even when the MPIC is
+  in fact big-endian, so certain boards override this property.
+
 INTERRUPT SPECIFIER DEFINITION
 
   Interrupt specifiers consists of 4 cells encoded as
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 5c80460..47f2b67 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -39,6 +39,7 @@ mpic: pic@4 {
reg = <0x4 0x4>;
compatible = "fsl,mpic";
device_type = "open-pic";
+   big-endian;
 };
 
 timer@41100 {
-- 
1.7.7.3

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[PATCH 3/6] fsl/mpic: Create and document the "single-cpu-affinity" device-tree flag

2011-12-22 Thread Kyle Moffett 
The Freescale MPIC (and perhaps others in the future) is incapable of
routing non-IPI interrupts to more than once CPU at a time.  Currently
all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to
mpic_alloc(), but that information should really be present in the
device-tree.

Older board code can't rely on the device-tree having the property set,
but newer platforms won't need it manually specified in the code.

Signed-off-by: Kyle Moffett 
---
 .../devicetree/bindings/powerpc/fsl/mpic.txt   |6 ++
 arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi|1 +
 arch/powerpc/sysdev/mpic.c |8 +---
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index ebafba2..b393ccf 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -64,6 +64,12 @@ PROPERTIES
   device-trees omit this property on MPIC nodes even when the MPIC is
   in fact big-endian, so certain boards override this property.
 
+  - single-cpu-affinity
+  Usage: optional
+  Value type: 
+  If present the MPIC will be assumed to only be able to route
+  non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
+
 INTERRUPT SPECIFIER DEFINITION
 
   Interrupt specifiers consists of 4 cells encoded as
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 47f2b67..658bd81 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -40,6 +40,7 @@ mpic: pic@4 {
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
+   single-cpu-affinity;
 };
 
 timer@41100 {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9dd7f76..c297a52 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1183,11 +1183,13 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
}
 
/* Read extra device-tree properties into the flags variable */
-   if (of_get_property(mpic->node, "big-endian", NULL))
+   if (of_get_property(node, "big-endian", NULL))
flags |= MPIC_BIG_ENDIAN;
-   if (of_get_property(mpic->node, "pic-no-reset", NULL))
+   if (of_get_property(node, "pic-no-reset", NULL))
flags |= MPIC_NO_RESET;
-   if (of_device_is_compatible(mpic->node, "fsl,mpic"))
+   if (of_get_property(node, "single-cpu-affinity", NULL))
+   flags |= MPIC_SINGLE_DEST_CPU;
+   if (of_device_is_compatible(node, "fsl,mpic"))
flags |= MPIC_FSL;
 
mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
-- 
1.7.7.3

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[PATCH 4/6] powerpc/mpic: Remove MPIC_BROKEN_FRR_NIRQS and duplicate irq_count

2011-12-22 Thread Kyle Moffett 
The mpic->irq_count variable is only used as a software error-checking
limit to determine whether or not an IRQ number is valid.  In board code
which does not manually specify an IRQ count to mpic_alloc(), i.e. 0, it
is automatically detected from the number of ISUs and the ISU size.

In practice, all hardware ends up with irq_count == num_sources, so all
of the runtime checks on mpic->irq_count should just check the value of
mpic->num_sources instead.

When platform hardware does not correctly report the number of IRQs,
which only happens on the MPC85xx/MPC86xx, the MPIC_BROKEN_FRR_NIRQS
flag is used to override the detected value of num_sources with the
manual irq_count parameter.  Since there's no need to manually specify
the number of IRQs except in this case, the extra flag can be eliminated
and the test changed to "irq_count != 0".

Signed-off-by: Kyle Moffett 
---
 arch/powerpc/include/asm/mpic.h   |3 ---
 arch/powerpc/platforms/85xx/corenet_ds.c  |3 +--
 arch/powerpc/platforms/85xx/mpc8536_ds.c  |2 +-
 arch/powerpc/platforms/85xx/mpc85xx_ds.c  |4 ++--
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |2 +-
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c |4 ++--
 arch/powerpc/platforms/85xx/p1010rdb.c|2 +-
 arch/powerpc/platforms/85xx/p1022_ds.c|2 +-
 arch/powerpc/platforms/85xx/p1023_rds.c   |2 +-
 arch/powerpc/platforms/85xx/xes_mpc85xx.c |2 +-
 arch/powerpc/platforms/86xx/pic.c |2 +-
 arch/powerpc/platforms/embedded6xx/holly.c|3 +--
 arch/powerpc/platforms/embedded6xx/linkstation.c  |2 +-
 arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c |3 +--
 arch/powerpc/platforms/embedded6xx/storcenter.c   |2 +-
 arch/powerpc/platforms/pseries/setup.c|4 +---
 arch/powerpc/sysdev/mpic.c|   17 ++---
 arch/powerpc/sysdev/mpic_msi.c|4 ++--
 18 files changed, 25 insertions(+), 38 deletions(-)

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 67b4d98..2ebac31 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -273,7 +273,6 @@ struct mpic
unsigned intisu_size;
unsigned intisu_shift;
unsigned intisu_mask;
-   unsigned intirq_count;
/* Number of sources */
unsigned intnum_sources;
/* default senses array */
@@ -363,8 +362,6 @@ struct mpic
 #define MPIC_ENABLE_MCK0x0200
 /* Disable bias among target selection, spread interrupts evenly */
 #define MPIC_NO_BIAS   0x0400
-/* Ignore NIRQS as reported by FRR */
-#define MPIC_BROKEN_FRR_NIRQS  0x0800
 /* Destination only supports a single CPU at a time */
 #define MPIC_SINGLE_DEST_CPU   0x1000
 /* Enable CoreInt delivery of interrupts */
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c 
b/arch/powerpc/platforms/85xx/corenet_ds.c
index 07e3e6c..768479b 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -36,8 +36,7 @@
 void __init corenet_ds_pic_init(void)
 {
struct mpic *mpic;
-   unsigned int flags = MPIC_BIG_ENDIAN |
-   MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
+   unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU;
 
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c 
b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index cf26682..d5373e0 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -38,7 +38,7 @@ void __init mpc8536_ds_pic_init(void)
 {
struct mpic *mpic = mpic_alloc(NULL, 0,
  MPIC_WANTS_RESET |
- MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+ MPIC_BIG_ENDIAN,
0, 256, " OpenPIC  ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c 
b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index eefbb91..528b9a0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -72,13 +72,13 @@ void __init mpc85xx_ds_pic_init(void)
 
if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
mpic = mpic_alloc(NULL, 0,
-   MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+   MPIC_BIG_ENDIAN |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC  ");
} else {
mpic = mpic_alloc(NULL, 0,
  MPIC_WANTS_RESET |
- MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+ MP

[PATCH 5/6] powerpc/mpic: Add "last-interrupt-source" property to override hardware

2011-12-22 Thread Kyle Moffett 
The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not
correctly report the number of hardware interrupt sources, so software
needs to override the detected value with "256".

To avoid needing to write custom board-specific code to detect that
scenario, allow it to be easily overridden in the device-tree.

Signed-off-by: Kyle Moffett 
---
 .../devicetree/bindings/powerpc/fsl/mpic.txt   |7 +++
 arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi|1 +
 arch/powerpc/sysdev/mpic.c |   46 +++-
 3 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt 
b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
index b393ccf..dc57446 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
@@ -70,6 +70,13 @@ PROPERTIES
   If present the MPIC will be assumed to only be able to route
   non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
 
+  - last-interrupt-source
+  Usage: optional
+  Value type: 
+  Some MPICs do not correctly report the number of hardware sources
+  in the global feature registers.  If specified, this field will
+  override the value read from MPIC_GREG_FEATURE_LAST_SRC.
+
 INTERRUPT SPECIFIER DEFINITION
 
   Interrupt specifiers consists of 4 cells encoded as
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi 
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 658bd81..fdedf7b 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -41,6 +41,7 @@ mpic: pic@4 {
device_type = "open-pic";
big-endian;
single-cpu-affinity;
+   last-interrupt-source = <255>;
 };
 
 timer@41100 {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index cbffeb7..90171d4 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1149,6 +1149,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
u32 greg_feature;
const char *vers;
const u32 *psrc;
+   u32 last_irq;
 
/* Default MPIC search parameters */
static const struct of_device_id __initconst mpic_device_id[] = {
@@ -1220,7 +1221,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic->hc_tm = mpic_tm_chip;
mpic->hc_tm.name = name;
 
-   mpic->isu_size = isu_size;
mpic->num_sources = 0; /* so far */
 
if (mpic->flags & MPIC_LARGE_VECTORS)
@@ -1308,20 +1308,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
   | MPIC_GREG_GCONF_MCK);
 
/*
-* Read feature register.  For non-ISU MPICs, num sources as well. On
-* ISU MPICs, sources are counted as ISUs are added
-*/
-   greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
-   if (isu_size == 0) {
-   if (irq_count)
-   mpic->num_sources = irq_count;
-   else
-   mpic->num_sources =
-   ((greg_feature & 
MPIC_GREG_FEATURE_LAST_SRC_MASK)
->> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
-   }
-
-   /*
 * The MPIC driver will crash if there are more cores than we
 * can initialize, so we may as well catch that problem here.
 */
@@ -1336,18 +1322,38 @@ struct mpic * __init mpic_alloc(struct device_node 
*node,
 0x1000);
}
 
+   /*
+* Read feature register.  For non-ISU MPICs, num sources as well. On
+* ISU MPICs, sources are counted as ISUs are added
+*/
+   greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
+
+   /*
+* By default, the last source number comes from the MPIC, but the
+* device-tree and board support code can override it on buggy hw.
+*/
+   last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
+   >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
+   of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
+   if (irq_count)
+   last_irq = irq_count - 1;
+
/* Initialize main ISU if none provided */
-   if (mpic->isu_size == 0) {
-   mpic->isu_size = mpic->num_sources;
+   if (!isu_size) {
+   isu_size = last_irq + 1;
+   mpic->num_sources = isu_size;
mpic_map(mpic, mpic->paddr, &mpic->isus[0],
-MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * 
mpic->isu_size);
+   MPIC_INFO(IRQ_BASE),
+   MPIC_INFO(IRQ_STRIDE) * isu_size);
}
+
+   mpic->isu_size = isu_size;
mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
mpic->isu_mask = (1 << mpic->isu_shift) - 1;
 
mpic->irqhost

[PATCH 6/6] powerpc/mpic: Remove duplicate MPIC_WANTS_RESET flag

2011-12-22 Thread Kyle Moffett 
There are two separate flags controlling whether or not the MPIC is
reset during initialization, which is completely unnecessary, and only
one of them can be specified in the device tree.

Also, most platforms in-tree right now do actually want to reset the
MPIC during initialization anyways, which means lots of duplicate code
passing the MPIC_WANTS_RESET flag.

Fix all of the callers which currently do not pass the MPIC_WANTS_RESET
flag to pass the MPIC_NO_RESET flag, then remove the MPIC_WANTS_RESET
flag and make the code reset the MPIC by default.

Signed-off-by: Kyle Moffett 
---
 arch/powerpc/include/asm/mpic.h   |6 +-
 arch/powerpc/platforms/44x/currituck.c|2 +-
 arch/powerpc/platforms/44x/iss4xx.c   |3 +--
 arch/powerpc/platforms/85xx/corenet_ds.c  |3 ++-
 arch/powerpc/platforms/85xx/ksi8560.c |3 +--
 arch/powerpc/platforms/85xx/mpc8536_ds.c  |4 +---
 arch/powerpc/platforms/85xx/mpc85xx_ads.c |3 +--
 arch/powerpc/platforms/85xx/mpc85xx_cds.c |3 +--
 arch/powerpc/platforms/85xx/mpc85xx_ds.c  |2 +-
 arch/powerpc/platforms/85xx/mpc85xx_mds.c |3 +--
 arch/powerpc/platforms/85xx/mpc85xx_rdb.c |3 +--
 arch/powerpc/platforms/85xx/p1010rdb.c|3 +--
 arch/powerpc/platforms/85xx/p1022_ds.c|4 +---
 arch/powerpc/platforms/85xx/p1023_rds.c   |3 +--
 arch/powerpc/platforms/85xx/sbc8548.c |3 +--
 arch/powerpc/platforms/85xx/sbc8560.c |3 +--
 arch/powerpc/platforms/85xx/socrates.c|3 +--
 arch/powerpc/platforms/85xx/stx_gp3.c |3 +--
 arch/powerpc/platforms/85xx/tqm85xx.c |2 +-
 arch/powerpc/platforms/85xx/xes_mpc85xx.c |4 +---
 arch/powerpc/platforms/86xx/pic.c |3 +--
 arch/powerpc/platforms/cell/setup.c   |3 ++-
 arch/powerpc/platforms/chrp/setup.c   |3 ++-
 arch/powerpc/platforms/embedded6xx/holly.c|3 +--
 arch/powerpc/platforms/embedded6xx/linkstation.c  |3 +--
 arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c |3 +--
 arch/powerpc/platforms/embedded6xx/storcenter.c   |3 +--
 arch/powerpc/platforms/maple/setup.c  |2 +-
 arch/powerpc/platforms/pasemi/setup.c |2 +-
 arch/powerpc/platforms/powermac/pic.c |1 -
 arch/powerpc/platforms/pseries/setup.c|3 ++-
 arch/powerpc/sysdev/mpic.c|2 +-
 32 files changed, 35 insertions(+), 59 deletions(-)

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 2ebac31..d7e3fec 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -348,8 +348,6 @@ struct mpic
 #define MPIC_U3_HT_IRQS0x0004
 /* Broken IPI registers (autodetected) */
 #define MPIC_BROKEN_IPI0x0008
-/* MPIC wants a reset */
-#define MPIC_WANTS_RESET   0x0010
 /* Spurious vector requires EOI */
 #define MPIC_SPV_EOI   0x0020
 /* No passthrough disable */
@@ -366,9 +364,7 @@ struct mpic
 #define MPIC_SINGLE_DEST_CPU   0x1000
 /* Enable CoreInt delivery of interrupts */
 #define MPIC_ENABLE_COREINT0x2000
-/* Disable resetting of the MPIC.
- * NOTE: This flag trumps MPIC_WANTS_RESET.
- */
+/* Do not reset the MPIC during initialization */
 #define MPIC_NO_RESET  0x4000
 /* Freescale MPIC (compatible includes "fsl,mpic") */
 #define MPIC_FSL   0x8000
diff --git a/arch/powerpc/platforms/44x/currituck.c 
b/arch/powerpc/platforms/44x/currituck.c
index 3f6229b..583e67f 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -83,7 +83,7 @@ static void __init ppc47x_init_irq(void)
 * device-tree, just pass 0 to all arguments
 */
struct mpic *mpic =
-   mpic_alloc(np, 0, 0, 0, 0, " MPIC ");
+   mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " MPIC ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
ppc_md.get_irq = mpic_get_irq;
diff --git a/arch/powerpc/platforms/44x/iss4xx.c 
b/arch/powerpc/platforms/44x/iss4xx.c
index 5b8cdbb..a28a862 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -71,8 +71,7 @@ static void __init iss4xx_init_irq(void)
/* The MPIC driver will get everything it needs from the
 * device-tree, just pass 0 to all arguments
 */
-   struct mpic *mpic = mpic_alloc(np, 0, 0, 0, 0,
-  " MPIC ");
+   struct mpic *mpic = mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " 
MPIC ");
BUG_ON(mpic == NULL);

Re: next BUG: using smp_processor_id() in preemptible

2011-12-22 Thread Benjamin Herrenschmidt 
On Thu, 2011-12-22 at 04:07 -0800, Hugh Dickins wrote:
> On Mon, 5 Dec 2011, Hugh Dickins wrote:
> 
> > 3.2.0-rc3-next-20111202 with CONFIG_DEBUG_PREEMPT=y gives me lots of
> > 
> > Dec  4 20:03:19 thorn kernel: BUG: using smp_processor_id() in preemptible 
> > [] code: startpar/1365
> > Dec  4 20:03:19 thorn kernel: caller is .arch_local_irq_restore+0x44/0x90
> > Dec  4 20:03:19 thorn kernel: Call Trace:
> > Dec  4 20:03:19 thorn kernel: [c001b45a7c60] [c0011fe8] 
> > .show_stack+0x6c/0x16c (unreliable)
> > Dec  4 20:03:19 thorn kernel: [c001b45a7d10] [c024318c] 
> > .debug_smp_processor_id+0xe4/0x11c
> > Dec  4 20:03:19 thorn kernel: [c001b45a7da0] [c000e2e8] 
> > .arch_local_irq_restore+0x44/0x90
> > Dec  4 20:03:19 thorn kernel: [c001b45a7e30] [c0005870] 
> > .do_hash_page+0x70/0x74
> > Dec  4 20:03:21 thorn kernel: debug_smp_processor_id: 21950 callbacks 
> > suppressed
> > 
> > from the u64 *next_tb = &__get_cpu_var(decrementers_next_tb)
> > in decrementer_check_overflow(): I've no idea whether it's safe
> > just to use get_cpu_var then put_cpu_var there instead,
> > but no hurry, I can survive with DEBUG_PREEMPT off.
> 
> Still a problem in 3.2.0-rc6-next-20111222

Ah forgot about that, I'll have a look. Thanks for the reminder.

Cheers,
Ben.


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OpenPIC warnings on P1022RDK AMP configuration

2011-12-22 Thread Arshad, Farrukh 
Greetings All

I am running dual linux on P1022RDK in AMP configuration. My memory 
partitioning is as below

-
Core  | Base Address  |Size |
--|---|-|
Core 0 (MEL RT Kernel)| 0x,   | 0x0C00, - 192 (MB)  |
Core 1 (LTIB Kernel)  |0x0C00,| 0x1000, - 256 (MB)  |
MCAPI - Shared Mem| 0x1C00,   | 0x0400, - 64  (MB)  |
-

My kernel command lines are for both cores

setenv core0bootargs root=/dev/mmcblk0p3 rootdelay=5 rw mem=192M
setenv core1bootargs root=/dev/nfs nfsroot=:/ ip=dhcp mem=256M

I have also partitioned my hardware among both cores and supplied appropriate 
"protected-sources" in mpic node of both DTS files. The problem is, I receive 
following warning continuously only on Core 0 console, but Core 1 is running 
smooth. In following warnings source irqs are mostly which I have assigned to 
Core 1, but they are present in Core 0 mpic node "protected-sources" list, then 
why I am getting these messages.

[6.219204] __ratelimit: 5796 callbacks suppressed
[6.223996]  OpenPIC  : Got protected source 30 !
[7.005809]  OpenPIC  : Got protected source 30 !
[8.005906]  OpenPIC  : Got protected source 30 !
[8.433053]  OpenPIC  : Got protected source 29 !
[8.437942]  OpenPIC  : Got protected source 30 !
[8.443101]  OpenPIC  : Got protected source 30 !
[8.448428]  OpenPIC  : Got protected source 30 !

Any thoughts ?

Best Regards

Farrukh Arshad
Sr. Software Development Engineer
Mentor Graphics Pakistan
Ph:   +92 - 423 - 609 - 92 - 09
Cell: +92 - 303 - 444 - 77 - 05

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[PATCH] DTS: fix the bug and add the chip compatible for eSDHC

2011-12-22 Thread r66093 
From: Jerry Huang 

Accordint to latest kernel, the auto-cmd12 property should be
"sdhci,auto-cmd12", and according to the SDHC binding and the workaround for
the special chip, add the chip compatible for eSDHC: "fsl,p1022-esdhc",
"fsl,mpc8536-esdhc", "fsl,p2020-esdhc" and "fsl,p1010-esdhc".

Signed-off-by: Jerry Huang 
---
 arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi |4 
 arch/powerpc/boot/dts/fsl/p1010si-post.dtsi   |3 ++-
 arch/powerpc/boot/dts/fsl/p1022si-post.dtsi   |3 ++-
 arch/powerpc/boot/dts/fsl/p2020si-post.dtsi   |4 
 4 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index 89af626..44e0ed9 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -236,6 +236,10 @@
};
 
 /include/ "pq3-esdhc-0.dtsi"
+   sdhc@2e000 {
+   compatible = "fsl,esdhc", "fsl,mpc8536-esdhc";
+   };
+
 /include/ "pq3-sec3.0-0.dtsi"
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index bd9e163..8ebe79c 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -158,7 +158,8 @@
 /include/ "pq3-usb2-dr-0.dtsi"
 /include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
-   fsl,sdhci-auto-cmd12;
+   compatible = "fsl,esdhc", "fsl,p1010-esdhc";
+   sdhci,auto-cmd12;
};
 
 /include/ "pq3-sec4.4-0.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index 16239b1..e56 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -203,7 +203,8 @@
 
 /include/ "pq3-esdhc-0.dtsi"
sdhc@2e000 {
-   fsl,sdhci-auto-cmd12;
+   compatible = "fsl,esdhc", "fsl,p1022-esdhc";
+   sdhci,auto-cmd12;
};
 
 /include/ "pq3-sec3.3-0.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
index c041050..8ec1b13 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -182,6 +182,10 @@
 /include/ "pq3-etsec1-1.dtsi"
 /include/ "pq3-etsec1-2.dtsi"
 /include/ "pq3-esdhc-0.dtsi"
+   sdhc@2e000 {
+   compatible = "fsl,esdhc", "fsl,p2020-esdhc";
+   };
+
 /include/ "pq3-sec3.1-0.dtsi"
 /include/ "pq3-mpic.dtsi"
 /include/ "pq3-mpic-timer-B.dtsi"
-- 
1.7.5.4


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