[PATCH v2 0/2] ARM: shmobile: add USB3.0 device node on r8a7790

2014-10-24 Thread Yoshihiro Shimoda
 This series is based on Simon's renesas.git branch and
renesas-devel-20141024-v3.18-rc1 tag. If we use the generic phy
driver for R-Car Gen2 (drivers/phy/phy-rcar-gen2.c), we can use
the USB3.0 on lager.

Changes from v1:
 - rebase the repository.

Yoshihiro Shimoda (2):
  ARM: shmobile: r8a7790: add USB3.0 device node
  ARM: shmobile: lager: enable USB3.0

 arch/arm/boot/dts/r8a7790-lager.dts |6 ++
 arch/arm/boot/dts/r8a7790.dtsi  |   10 ++
 2 files changed, 16 insertions(+)

-- 
1.7.9.5

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[PATCH v2 1/2] ARM: shmobile: r8a7790: add USB3.0 device node

2014-10-24 Thread Yoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm/boot/dts/r8a7790.dtsi |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 3f1e4b3..776f1c4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1147,6 +1147,16 @@
status = "disabled";
};
 
+   xhci: usb@ee00 {
+   compatible = "renesas,xhci-r8a7790";
+   reg = <0 0xee00 0 0xc00>;
+   interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+   phys = <&usb2 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
pci0: pci@ee09 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
-- 
1.7.9.5

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[PATCH v2 2/2] ARM: shmobile: lager: enable USB3.0

2014-10-24 Thread Yoshihiro Shimoda
Since the PHY of USB3.0 and EHCI/OHCI ch2 are the same, the USB3.0
driver cannot use the phy driver when the EHCI/OHCI ch2 already used it:

phy phy-e6590100.usb-phy.3: phy init failed --> -16
xhci-hcd: probe of ee00.usb failed with error -16

If so, we have to unbind the EHCI/OHCI ch2, and then we have to bind
the USB3.0 driver as the following:

  echo :02:02.0 > /sys/bus/pci/drivers/ehci-pci/unbind
  echo :02:01.0 > /sys/bus/pci/drivers/ohci-pci/unbind
  echo ee00.usb > /sys/bus/platform/drivers/xhci-hcd/bind

Note that there will be pinctrl-related error messages if both
internal PCI and USB3.0 are enabled but they should be just ignored:

sh-pfc e606.pfc: pin GP_5_22 already requested by ee0d.pci; cannot 
claim for ee00.usb
sh-pfc e606.pfc: pin-182 (ee00.usb) status -22
ata1: SATA link down (SStatus 0 SControl 300)
sh-pfc e606.pfc: could not request pin 182 (GP_5_22) from group usb2  on 
device sh-pfc

Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm/boot/dts/r8a7790-lager.dts |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts 
b/arch/arm/boot/dts/r8a7790-lager.dts
index 2115de2..b48173b 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -419,6 +419,12 @@
pinctrl-names = "default";
 };
 
+&xhci {
+   status = "okay";
+   pinctrl-0 = <&usb2_pins>;
+   pinctrl-names = "default";
+};
+
 &pci2 {
status = "okay";
pinctrl-0 = <&usb2_pins>;
-- 
1.7.9.5

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[PATCH v2 0/1] ARM: shmobile: add USB3.0 device node on r8a7791

2014-10-24 Thread Yoshihiro Shimoda
 This patch is based on Simon's renesas.git branch and
renesas-devel-20141024-v3.18-rc1 tag.
Since koelsch and henninger doesn't have a USB3.0 connector,
I submit a patch for r8a7791.dtsi only.

Changes from v1:
 - rebase the repository.

Yoshihiro Shimoda (1):
  ARM: shmobile: r8a7791: add USB3.0 device node

 arch/arm/boot/dts/r8a7791.dtsi |   10 ++
 1 file changed, 10 insertions(+)

-- 
1.7.9.5

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[PATCH v2 1/1] ARM: shmobile: r8a7791: add USB3.0 device node

2014-10-24 Thread Yoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda 
---
 arch/arm/boot/dts/r8a7791.dtsi |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 74f18d8..1f4b6db 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1152,6 +1152,16 @@
status = "disabled";
};
 
+   xhci: usb@ee00 {
+   compatible = "renesas,xhci-r8a7791";
+   reg = <0 0xee00 0 0xc00>;
+   interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+   phys = <&usb2 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
pci0: pci@ee09 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
-- 
1.7.9.5

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[PATCH v5 0/2] Add HS-USB device tree support for R8A7790/Lager board

2014-10-24 Thread Yoshihiro Shimoda
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20141024-v3.18-rc1' tag. Here we add the HS-USB device tree
support on the R8A7790/Lager reference board. The patchset requires the USB PHY
driver (already merged by Kishon and Greg) and the generic PHY support patches
for the HS-USB driver posted by Yoshihiro Shimoda in order to work...

Changes from v4:
 - rebase the repository.

Yoshihiro Shimoda (2):
  ARM: shmobile: r8a7790: add HS-USB device node
  ARM: shmobile: lager: enable HS-USB

 arch/arm/boot/dts/r8a7790-lager.dts |   12 
 arch/arm/boot/dts/r8a7790.dtsi  |   11 +++
 2 files changed, 23 insertions(+)

-- 
1.7.9.5

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[PATCH v5 1/2] ARM: shmobile: r8a7790: add HS-USB device node

2014-10-24 Thread Yoshihiro Shimoda
Define the R8A7790 generic part of the HS-USB device node.
It is up to the board file to enable the device.

Signed-off-by: Yoshihiro Shimoda 
[Sergei: fixed summary, added changelog]
Signed-off-by: Sergei Shtylyov 
---
 arch/arm/boot/dts/r8a7790.dtsi |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 776f1c4..42a90c3 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -600,6 +600,17 @@
status = "disabled";
};
 
+   hsusb: usb@e659 {
+   compatible = "renesas,usbhs-r8a7790";
+   reg = <0 0xe659 0 0x100>;
+   interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+   renesas,buswait = <4>;
+   phys = <&usb0 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7790";
reg = <0 0xe6590100 0 0x100>;
-- 
1.7.9.5

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[PATCH v5 2/2] ARM: shmobile: lager: enable HS-USB

2014-10-24 Thread Yoshihiro Shimoda
Enable HS-USB device for the Lager board, defining the GPIO that the driver
should check when probing. Since this board doesn't have the OTG ID pin, we
assume that GP5_18 (USB0_PWEN) is an ID pin because it is 1 when the SW5 is
in position 2-3 (meaning USB function) and 0 in other positions.

Note that there will be pinctrl-related error messages if both internal PCI
and HS-USB drivers are enabled but they should be just ignored.

Signed-off-by: Yoshihiro Shimoda 
[Sergei: added pin node and prop, moved device node, fixed summary, supplemented
changelog]
Signed-off-by: Sergei Shtylyov 
---
 arch/arm/boot/dts/r8a7790-lager.dts |   12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-lager.dts 
b/arch/arm/boot/dts/r8a7790-lager.dts
index b48173b..e5ade61 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -221,6 +221,11 @@
renesas,function = "iic3";
};
 
+   hsusb_pins: hsusb {
+   renesas,groups = "usb0_ovc_vbus";
+   renesas,function = "usb0";
+   };
+
usb0_pins: usb0 {
renesas,groups = "usb0";
renesas,function = "usb0";
@@ -431,6 +436,13 @@
pinctrl-names = "default";
 };
 
+&hsusb {
+   status = "okay";
+   pinctrl-0 = <&hsusb_pins>;
+   pinctrl-names = "default";
+   renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
+
 &usbphy {
status = "okay";
 };
-- 
1.7.9.5

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[PATCH v4 1/3] ARM: shmobile: r8a7791: add HS-USB device node

2014-10-24 Thread Yoshihiro Shimoda
Define the R8A7791 generic part of the HS-USB device node. It is up to the board
file to enable the device.

Signed-off-by: Yoshihiro Shimoda 
[Sergei: fixed summary, added changelog]
Signed-off-by: Sergei Shtylyov 
---
 arch/arm/boot/dts/r8a7791.dtsi |   11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1f4b6db..51a1b84 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -637,6 +637,17 @@
status = "disabled";
};
 
+   hsusb: usb@e659 {
+   compatible = "renesas,usbhs-r8a7791";
+   reg = <0 0xe659 0 0x100>;
+   interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+   clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
+   renesas,buswait = <4>;
+   phys = <&usb0 1>;
+   phy-names = "usb";
+   status = "disabled";
+   };
+
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7791";
reg = <0 0xe6590100 0 0x100>;
-- 
1.7.9.5

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[PATCH v4 3/3] ARM: shmobile: henninger: enable HS-USB

2014-10-24 Thread Yoshihiro Shimoda
Enable HS-USB device for the Henninger board, defining the GPIO that the driver
should check when probing (which is the ID output from MAX3355 OTG chip).

Note that there will be pinctrl-related error messages if both internal PCI
and HS-USB drivers are enabled but they should be just ignored.

Signed-off-by: Yoshihiro Shimoda 
[Sergei: added pin function/group and prop, moved device node, fixed summary,
added changelog]
Signed-off-by: Sergei Shtylyov 
---
 arch/arm/boot/dts/r8a7791-henninger.dts |7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts 
b/arch/arm/boot/dts/r8a7791-henninger.dts
index ef2cb92..740e386 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -272,6 +272,13 @@
pinctrl-names = "default";
 };
 
+&hsusb {
+   status = "okay";
+   pinctrl-0 = <&usb0_pins>;
+   pinctrl-names = "default";
+   renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+
 &usbphy {
status = "okay";
 };
-- 
1.7.9.5

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[PATCH v4 0/3] HS-USB device tree support for R8A7791/Koelsch/Henninger board

2014-10-24 Thread Yoshihiro Shimoda
   Here's the set of 3 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20141024-v3.18-rc1' tag. Here we add the HS-USB device tree
support on the R8A7791/Koelsch/Henninger reference boards. The patchset
requires the USB PHY driver (already merged by Kishon and Greg) and the
generic PHY support patches for the HS-USB driver posted by Yoshihiro Shimoda
in order to work...

Changes from v3:
 - rebase the repository.

Yoshihiro Shimoda (3):
  ARM: shmobile: r8a7791: add HS-USB device node
  ARM: shmobile: koelsch: enable HS-USB
  ARM: shmobile: henninger: enable HS-USB

 arch/arm/boot/dts/r8a7791-henninger.dts |7 +++
 arch/arm/boot/dts/r8a7791-koelsch.dts   |7 +++
 arch/arm/boot/dts/r8a7791.dtsi  |   11 +++
 3 files changed, 25 insertions(+)

-- 
1.7.9.5

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[PATCH v4 2/3] ARM: shmobile: koelsch: enable HS-USB

2014-10-24 Thread Yoshihiro Shimoda
Enable HS-USB device for the Koelsch board, defining the GPIO that the driver
should check when probing (which is the ID output from MAX3355 OTG chip).

Note that there will be pinctrl-related error messages if both internal PCI
and HS-USB drivers are enabled but they should be just ignored.

Signed-off-by: Yoshihiro Shimoda 
[Sergei: added pin function/group and prop, moved device node, fixed summary,
added changelog]
Signed-off-by: Sergei Shtylyov 
---
 arch/arm/boot/dts/r8a7791-koelsch.dts |7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts 
b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 5318463..6e63200 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -464,6 +464,13 @@
pinctrl-names = "default";
 };
 
+&hsusb {
+   status = "okay";
+   pinctrl-0 = <&usb0_pins>;
+   pinctrl-names = "default";
+   renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
+};
+
 &usbphy {
status = "okay";
 };
-- 
1.7.9.5

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Re: [3.16.1 BISECTED REGRESSION]: Simtec Entropy Key (cdc-acm) broken in 3.16

2014-10-24 Thread Johan Hovold
[ +CC: linux-usb ]

On Wed, Oct 22, 2014 at 04:36:59PM +0100, Nix wrote:
> On 22 Oct 2014, Johan Hovold outgrape:
> 
> > On Wed, Oct 22, 2014 at 10:31:17AM +0100, Nix wrote:
> >> On 14 Oct 2014, Johan Hovold verbalised:
> >> 
> >> > On Sun, Oct 12, 2014 at 10:36:30PM +0100, Nix wrote:
> >> >> I have checked: this code is being executed against a symlink that
> >> >> points to /dev/ttyACM0, and the tcsetattr() succeeds. (At least, it's
> >> >> succeeding on the kernel I'm running now, but of course that's 3.16.5
> >> >> with this commit reverted...)
> >> >
> >> > You could verify that by enabling debugging in the cdc-acm driver and
> >> > making sure that the corresponding control messages are indeed sent on
> >> > close.
> >> 
> >> I have a debugging dump at
> >> ; it's fairly
> >
> > What kernel were you using here? The log seems to suggest that it was
> > generated with the commit in question reverted.
> 
> Look now :) (the previous log is still there in cdc-acm-reverted.log.)

Unfortunately, it seems the logs are incomplete. There are lots of
entries missing (e.g. "acm_tty_install" when opening, but also some
"acm_submit_read_urb"), some of which were there in your first log.

Also you can disable the "acm_tty_write - count" output, which isn't
really useful here.

> This contains two boots -- one on which the USB key worked, and the next
> (with an identical kernel) with which the key was broken. (I'm not sure
> whether this problem happens at startup or shutdown time, so it seemed
> best to provide both.)

That's a good idea.

Is it only after reboot you've seen the device fail? What if you
physically disconnect and reconnect the device instead, or simply
repeatedly open and close it?

Johan
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Re: [PATCH 18/28] usb: dwc3: ep0: fix Data Phase for transfer sizes aligned to wMaxPacketSize

2014-10-24 Thread Felipe Balbi
Hi,

On Fri, Oct 24, 2014 at 12:50:44PM +0900, Anton Tikhomirov wrote:
> > > > > > dwc3_ep0_stall_and_restart(dwc);
> > > > > > } else {
> > > > > > -   /*
> > > > > > -* handle the case where we have to send a zero
> > packet.
> > > > > This
> > > > > > -* seems to be case when req.length > maxpacket.
> > Could it
> > > > > be?
> > > > > > -*/
> > > > > > -   if (r)
> > > > > > -   dwc3_gadget_giveback(ep0, r, 0);
> > > > > > +   dwc3_gadget_giveback(ep0, r, 0);
> > > > >
> > > > > Don't you want to wait until the ZLP has completed before doing
> > the
> > > > > giveback?
> > > > >
> > > > > In fact, shouldn't all this ZLP code run when the transfer is
> > > > > submitted, rather than when it completes?  The idea is that you
> > get a
> > > > > request, you queue up all the necessary TRBs or whatever, and if
> > an
> > > > > extra ZLP is needed then you queue up an extra TRB.
> > > >
> > > > You may want to check my patch one more time. I sent it for review
> > 10
> > > > monthes ago:
> > > >
> > > > [PATCH] usb: dwc3: ep0: Handle variable-length Data Stage
> > > >
> > > > It works just fine for us in our custom kernel.
> > >
> > > you also said you'd send another version (see [1]) and never did. 10
> > > months passed and I had even forgotten about this issue until I
> > decided
> > > to run all gadget drivers through USB[23]0CV and found that g_ncm
> > falls
> > > into this same bug, so I wrote the patch above.
> 
> I'm sorry about this. I was busy with current project at that time and
> finally forgot about this issue too.

I also apologize that I completely forgot about your patch, I should've
at least mentioned your work. Anyway, I'll send Greg a pull request
today. Finally finished testing everything on top of v3.18-rc1.

-- 
balbi


signature.asc
Description: Digital signature


[GIT PULL] USB fixes for v3.18-rc2

2014-10-24 Thread Felipe Balbi
Hi Greg,

Here's our first set of fixes for v3.18-rc cycle.

Quite a few goodies here but the most important is that most gadget drivers
(except for g_hid, g_midi and g_webcam) pass USB[23]0CV with MUSB and DWC3.

All patches have been tested for weeks (since v3.18 merge window opened) and
they have also been tested for a few days on top of v3.18-rc1.

Let me know if you want anything to be changed.

cheers


The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:

  Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git 
tags/fixes-for-v3.18-rc2

for you to fetch changes up to 9b1763553a89b2a84881119eeabfccdb803bb468:

  usb: gadget: function: Fixed the return value on error path (2014-10-23 
14:49:35 -0500)


usb: fixes for v3.18-rc2

Here's the first set of fixes for v3.18-rc cycle. It includes
a whole bunch of bug fixes related to USB20CV and USB30CV when
running on DWC3 and MUSB. After this series, we have clean chapter 9
and MSC tests for all gadget drivers.

We also have a new PCI ID for Intel Braswell platform so they can use
DWC3 out-of-the-box.

A regression on functionfs wrt quirk_ep_out_aligned_size flag has also
been fixed.

DWC2 got a couple of fixes for the gadget role. The first of which fixes
rmmod followed by modprobe while the second makes sure to disable PHYs
before killing the regulators powering them.

These are the most important fixes worth mentioning, there are a few
other minor fixes as well.

Signed-off-by: Felipe Balbi 


Alan Cox (1):
  usb: dwc3: pci: Add PCI ID for Intel Braswell

Charles Manning (1):
  usb: dwc2: Bits in bitfield should add up to 32

David Cohen (1):
  usb: ffs: fix regression when quirk_ep_out_aligned_size flag is set

Felipe Balbi (20):
  usb: dwc3: trace: don't dereference pointers
  usb: dwc3: ep0: hold our lock in dwc3_gadget_ep0_set_halt
  usb: dwc3: gadget: move isoc endpoint check to unlocked set_halt
  usb: dwc3: gadget: hold the lock through set_wedge()'s life
  usb: dwc3: gadget: fix set_halt() bug with pending transfers
  usb: gadget: function: uvc: conditionally dequeue
  usb: gadget: function: uvc: make sure to balance ep enable/disable
  usb: gadget: function: uvc: return correct alt-setting
  usb: gadget: function: acm: make f_acm pass USB20CV Chapter9
  usb: gadget: function: uvc: manage our video control endpoint
  usb: gadget: function: uvc: disable endpoints on ->disable()
  usb: gadget: function: uac2: add wMaxPacketSize to ep desc
  usb: gadget: function: uac2: prevent double ep disable
  usb: gadget: function: uac2: add a release method
  usb: gadget: function: f_obex: fix Interface Descriptor Test
  usb: dwc3: ep0: return early on NULL requests
  usb: dwc3: ep0: fix Data Phase for transfer sizes aligned to 
wMaxPacketSize
  usb: gadget: composite: enable BESL support
  usb: gadget: loopback: don't queue requests to bogus endpoints
  usb: gadget: udc: core: fix kernel oops with soft-connect

Geert Uytterhoeven (1):
  usb: gadget: udc: USB_GADGET_XILINX should depend on HAS_DMA

Jack Pham (1):
  usb: dwc3: gadget: Properly initialize LINK TRB

Marek Szyprowski (2):
  usb: dwc2: gadget: fix gadget unregistration in udc_stop() function
  usb: dwc2: gadget: disable phy before turning off power regulators

Pavitrakumar Managutte (2):
  usb: gadget: function: Remove redundant usb_free_all_descriptors
  usb: gadget: function: Fixed the return value on error path

Robert Baldyga (1):
  usb: gadget: f_fs: remove redundant ffs_data_get()

Roger Quadros (1):
  Revert "usb: dwc3: dwc3-omap: Disable/Enable only wrapper interrupts in 
prepare/complete"

Sebastian Andrzej Siewior (2):
  usb: musb: dsps: start OTG timer on resume again
  usb: musb: musb_dsps: fix NULL pointer in suspend

Sudip Mukherjee (1):
  usb: dwc2: gadget: sparse warning of context imbalance

Thomas Gleixner (1):
  usb: musb: cppi41: restart hrtimer only if not yet done

 drivers/usb/dwc2/core.h  |  2 +-
 drivers/usb/dwc2/gadget.c| 14 ++---
 drivers/usb/dwc3/dwc3-omap.c | 15 +-
 drivers/usb/dwc3/dwc3-pci.c  |  2 +
 drivers/usb/dwc3/ep0.c   | 48 +-
 drivers/usb/dwc3/gadget.c| 39 --
 drivers/usb/dwc3/gadget.h|  3 +-
 drivers/usb/dwc3/trace.h | 53 +--
 drivers/usb/gadget/composite.c   |  2 +-
 drivers/usb/gadget/function/f_acm.c  |  8 +--
 drivers/usb/gadget/function/f_eem.c  |  1 -
 drivers/usb/gadget/function/f_fs.c   | 42 ---
 drivers/usb/gadget/function/f_hid.c  |  5 +-
 drivers/usb/gadget/function/f_loo

Re: [3.16.1 BISECTED REGRESSION]: Simtec Entropy Key (cdc-acm) broken in 3.16

2014-10-24 Thread Nix
On 24 Oct 2014, Johan Hovold told this:

> [ +CC: linux-usb ]
> On Wed, Oct 22, 2014 at 04:36:59PM +0100, Nix wrote:
>> On 22 Oct 2014, Johan Hovold outgrape:
>> 
>> > On Wed, Oct 22, 2014 at 10:31:17AM +0100, Nix wrote:
>> >> On 14 Oct 2014, Johan Hovold verbalised:
>> >> 
>> >> > On Sun, Oct 12, 2014 at 10:36:30PM +0100, Nix wrote:
>> >> >> I have checked: this code is being executed against a symlink that
>> >> >> points to /dev/ttyACM0, and the tcsetattr() succeeds. (At least, it's
>> >> >> succeeding on the kernel I'm running now, but of course that's 3.16.5
>> >> >> with this commit reverted...)
>> >> >
>> >> > You could verify that by enabling debugging in the cdc-acm driver and
>> >> > making sure that the corresponding control messages are indeed sent on
>> >> > close.
>> >> 
>> >> I have a debugging dump at
>> >> ; it's fairly
>> >
>> > What kernel were you using here? The log seems to suggest that it was
>> > generated with the commit in question reverted.
>> 
>> Look now :) (the previous log is still there in cdc-acm-reverted.log.)
>
> Unfortunately, it seems the logs are incomplete. There are lots of
> entries missing (e.g. "acm_tty_install" when opening, but also some
> "acm_submit_read_urb"), some of which were there in your first log.

Curious. It's a straight cut-and-paste from the syslog. Maybe the kmsg
buffer overflowed, but I start the ekey daemon *after* I start syslogd,
so that seems unlikely.

I'll have another look.

> Is it only after reboot you've seen the device fail?

Yes (though sometimes after reboot of an unaffected kernel into an
affected one! i.e. sometimes the first boot into an affected kernel is
broken).

>  What if you
> physically disconnect and reconnect the device instead,

That makes it work.

> or simply
> repeatedly open and close it?

IIRC -- but I'll have to check this tomorrow when I look at the log
problem, so don't take it as gospel -- that doesn't affect it: I can
stop and restart the daemon repeatedly and, if it wasn't working before,
it's not working afterwards: if it was working before, it'll be working
afterwards.

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Re: [PATCH v2 05/16] usb: dwc3: add quirks support to be compatible for kinds of SoCs

2014-10-24 Thread Felipe Balbi
On Mon, Oct 20, 2014 at 02:02:17PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:41:44AM -0500, Felipe Balbi wrote:
> > HI,
> > 
> > On Fri, Oct 17, 2014 at 04:53:30PM +0800, Huang Rui wrote:
> > > This patch adds a quirks flag at dwc3 structure, and SoCs platform vendor 
> > > is
> > > able to define this flag in platform data at bus glue layer. Then do some
> > > independent behaviors at dwc3 core level.
> > > 
> > > Signed-off-by: Huang Rui 
> > > ---
> > >  drivers/usb/dwc3/core.c  | 2 ++
> > >  drivers/usb/dwc3/core.h  | 3 +++
> > >  drivers/usb/dwc3/dwc3-pci.c  | 9 +
> > >  drivers/usb/dwc3/platform_data.h | 2 ++
> > >  4 files changed, 16 insertions(+)
> > > 
> 
> 
> 
> > > diff --git a/drivers/usb/dwc3/platform_data.h 
> > > b/drivers/usb/dwc3/platform_data.h
> > > index 7db34f0..1d3d65f 100644
> > > --- a/drivers/usb/dwc3/platform_data.h
> > > +++ b/drivers/usb/dwc3/platform_data.h
> > > @@ -24,4 +24,6 @@ struct dwc3_platform_data {
> > >   enum usb_device_speed maximum_speed;
> > >   enum usb_dr_mode dr_mode;
> > >   bool tx_fifo_resize;
> > > +
> > > + u32 quirks;
> > 
> > I prefer to have one-bit fields like we already have for delayed_status,
> > ep0_bounced, ep0_expect_in, and so on. That makes it easier to support
> > the same quirks through devicetree as well.
> > 
> 
> So it should define like below:
> 
> struct dwc3_platform_data {
> ...
> unsigned one_quirk:1;
> }
> 
> Then also defined it in dwc3 structure. And when dwc3 probed, put this
> value from glue layer to dwc3, right?

that's correct.

-- 
balbi


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Re: [PATCH v2 08/16] usb: dwc3: add u2exit lfps quirk

2014-10-24 Thread Felipe Balbi
On Mon, Oct 20, 2014 at 02:43:31PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:50:00AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:33PM +0800, Huang Rui wrote:
> > > AMD NL needs to enable u2exit lfps quirk.
> > > 
> > > Signed-off-by: Huang Rui 
> > > ---
> > >  drivers/usb/dwc3/core.c  | 4 
> > >  drivers/usb/dwc3/core.h  | 1 +
> > >  drivers/usb/dwc3/dwc3-pci.c  | 3 ++-
> > >  drivers/usb/dwc3/platform_data.h | 1 +
> > >  4 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 25db533..7322d85 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -467,6 +467,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >   reg |= DWC3_GCTL_DISSCRAMBLE;
> > >   else
> > >   reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > > +
> > > + if (dwc->quirks & DWC3_QUIRK_U2EXIT_LFPS)
> > 
> > this should be:
> > 
> > if (dwc->u2_exit_lfps_quirk)
> > 
> 
> OK, will update it in V3.
> 
> > > + reg |= DWC3_GCTL_U2EXIT_LFPS;
> > > +
> > >   /*
> > >* WORKAROUND: DWC3 revisions <1.90a have a bug
> > >* where the device can fail to connect at SuperSpeed
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index d58479e..3d27f10 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -166,6 +166,7 @@
> > >  #define DWC3_GCTL_SCALEDOWN(n)   ((n) << 4)
> > >  #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
> > >  #define DWC3_GCTL_DISSCRAMBLE(1 << 3)
> > > +#define DWC3_GCTL_U2EXIT_LFPS(1 << 2)
> > >  #define DWC3_GCTL_GBLHIBERNATIONEN   (1 << 1)
> > >  #define DWC3_GCTL_DSBLCLKGTNG(1 << 0)
> > >  
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index bbe946c..cdb9b04 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -149,7 +149,8 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >   if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > >   PCI_DEVICE_ID_AMD_NL) {
> > >   dwc3_pdata.has_lpm_erratum = true;
> > > - dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > > + dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL
> > > + | DWC3_QUIRK_U2EXIT_LFPS;
> > >   }
> > 
> > should be combined and the last patch in the series.
> > 
> 
> You want to make all the AMD quirks enablement info and device id at
> last patch, right?

Correct, that way we avoid bisection points were AMD is "supported" but
not working.

-- 
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Re: [PATCH v2 06/16] usb: dwc3: add disscramble quirk

2014-10-24 Thread Felipe Balbi
On Mon, Oct 20, 2014 at 02:38:28PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:45:32AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:31PM +0800, Huang Rui wrote:
> > > AMD NL fpga needs to enable disscramble quirk. And this quirk doesn't 
> > > need on
> > > the true soc.
> > > 
> > > Signed-off-by: Huang Rui 
> > > ---
> > >  drivers/usb/dwc3/core.c  | 8 +++-
> > >  drivers/usb/dwc3/dwc3-pci.c  | 5 +
> > >  drivers/usb/dwc3/platform_data.h | 4 
> > >  3 files changed, 16 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 50c0eae..819e501 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -422,7 +422,6 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >  
> > >   reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> > >   reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> > > - reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > >  
> > >   switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
> > >   case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
> > > @@ -461,6 +460,13 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > >   dwc->is_fpga = true;
> > >   }
> > >  
> > > + if ((dwc->quirks & DWC3_QUIRK_AMD_NL) && dwc->is_fpga)
> > > + dwc->quirks |= DWC3_QUIRK_DISSCRAMBLE;
> > > +
> > > + if (dwc->quirks & DWC3_QUIRK_DISSCRAMBLE)
> > 
> > this should only be set if is_fpga, and this quirk should be a 1-bit
> > flag, so here's what you should do:
> > 
> > WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
> > "disable_scramble cannot be used on non-FPGA builds\n");
> > 
> > if (dwc->disable_scramble && dwc->is_fpga)
> > reg |= DWC3_GCTL_DISSCRAMBLE;
> > else
> > reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > 
> 
> OK, will update it in V3.
> 
> > > + reg |= DWC3_GCTL_DISSCRAMBLE;
> > > + else
> > > + reg &= ~DWC3_GCTL_DISSCRAMBLE;
> > 
> > add a blank line here, to aid readability.
> > 
> 
> OK, will add it.
> 
> > >   /*
> > >* WORKAROUND: DWC3 revisions <1.90a have a bug
> > >* where the device can fail to connect at SuperSpeed
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index 18569a4..a89db6c 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -146,6 +146,11 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >   res[1].name = "dwc_usb3";
> > >   res[1].flags= IORESOURCE_IRQ;
> > >  
> > > + if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > > + PCI_DEVICE_ID_AMD_NL) {
> > > + dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > > + }
> > 
> > should be part of another patch and the quirk is
> > "disable_scramble_quirk", not AMD.
> > 
> 
> Got it, you would like to keep this patch just for fpga disscramble
> quirk and do not add any 3rd platform info, right?

right. So far only FPGA-based systems need this :-)

-- 
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Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

2014-10-24 Thread Felipe Balbi
Hi,

On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 06:41:04PM +, Paul Zimmerman wrote:
> > > > From: Felipe Balbi [mailto:ba...@ti.com]
> > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > 
> > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on 
> > > > > simulation
> > > > > board.
> > > > >
> > > > > Signed-off-by: Huang Rui 
> > > > > ---
> > > > >  drivers/usb/dwc3/core.c  | 7 ++-
> > > > >  drivers/usb/dwc3/dwc3-pci.c  | 3 ++-
> > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index 3ccfe41..4a98696 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > >   if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > >   reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > >
> > > > > + if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > 
> > > > should be:
> > > > 
> > > > if (!dwc->suspend_usb3_phy_quirk)
> > > > 
> > > > > + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > 
> > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > that bit. Am I missing something ? Paul ?
> > > 
> > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > it.
> > 
> > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > 
> > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > series you just posted). According to the databook, both of those
> > > bits should be set to 1 after the core initialization has completed.
> > 
> > there you go. So unless that quirk bit flag is set, we're safe of
> > setting SUSPHY bit for everybody.
> > 
> 
> So I can update to set these two suspend phy bits defaultly in my next
> patch set, is it OK? :)

We need to split this into two patches:

patch 1 adds missing SUSPHY bit for all cores above revision 1.94a at
the end of probe()

patch 2 adds a quirk which AMD needs so that setting USB3_SUSPHY bit is
conditional on that quirk.

-- 
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Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

2014-10-24 Thread Felipe Balbi
On Mon, Oct 20, 2014 at 05:01:25PM +0800, Huang Rui wrote:
> On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> > On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > > Hi,
> > > 
> > > On Fri, Oct 17, 2014 at 06:41:04PM +, Paul Zimmerman wrote:
> > > > > From: Felipe Balbi [mailto:ba...@ti.com]
> > > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > > 
> > > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on 
> > > > > > simulation
> > > > > > board.
> > > > > >
> > > > > > Signed-off-by: Huang Rui 
> > > > > > ---
> > > > > >  drivers/usb/dwc3/core.c  | 7 ++-
> > > > > >  drivers/usb/dwc3/dwc3-pci.c  | 3 ++-
> > > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index 3ccfe41..4a98696 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > > > if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > > > reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > > >
> > > > > > +   if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > > 
> > > > > should be:
> > > > > 
> > > > >   if (!dwc->suspend_usb3_phy_quirk)
> > > > > 
> > > > > > +   reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > > 
> > > > > IIRC, databook asks us to set that bit anyway, so the quirk is 
> > > > > disabling
> > > > > that bit. Am I missing something ? Paul ?
> > > > 
> > > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > > it.
> > > 
> > > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > > 
> > > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > > series you just posted). According to the databook, both of those
> > > > bits should be set to 1 after the core initialization has completed.
> > > 
> > > there you go. So unless that quirk bit flag is set, we're safe of
> > > setting SUSPHY bit for everybody.
> > > 
> > 
> 
> I read the databook again, below words (DWC3_GUSB3PIPECTL_SUSPHY) is
> copied from databook:
> 
> For DRD/OTG configurations, it is recommended that this bit is set to‘
> 0’ during coreConsultant configuration. If it is set to ’1’, then the
> application should clear this bit after power-on reset. Application
> needs to set it to ’1’ after the core initialization is completed.
> For all other configurations, this bit can be set to ’1’ during core
> configuration.
> 
> I see it's recommended to set '0' if on DRD/OTG configuration.

0 at the beginning of probe() sequence so core can communicate with its
PHYs, then set it to one at the end of probe().

-- 
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Re: [PATCH v2 00/16] usb: dwc3: add support for AMD NL SoC

2014-10-24 Thread Felipe Balbi
Hi,

On Mon, Oct 20, 2014 at 11:38:23PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote:
> > > The series of patches add AMD NL SoC support for DesignWare USB3 OTG
> > > IP with PCI bus glue layer. This controller supported hibernation, LPM
> > > erratum and used the 2.80a IP version and amd own phy. Current
> > > implementation support both simulation and SoC platform. And already
> > > tested with gadget zero and msc tool.  It works well on file storage
> > > gadget.
> > 
> > patches look much, much nicer there are still a few things to fix. A
> > global set of issues which I see:
> > 
> > 1) Let's get confirmation that all those quirks will be needed in
> > production as well, I have a feeling quite a few of them won't be.
> > 
> > 2) All quirks should become 1-bit fields insteads of single-bits on a
> > 32-bit variable.
> > 
> > 3) All quirks should have DeviceTree counterparts. They should all
> > become boolean properties should we can:
> > 
> > dwc->tx_deemphasis_quirk = of_property_read_bool(node,
> > "snps,tx_deemphasis_quirk");
> > 
> 
> Thanks to summarize them. Will update in V3.

hey, no problem.

> > > These patches are generated on balbi/testing/next
> > > 
> > > Changes from v1 -> v2
> > > - remove dual role function temporarily
> > > - add pci quirk to avoid to bind with xhci driver
> > > - distinguish between simulation board and soc
> > > - break down all the special quirks
> > > 
> > > 
> > > Patch 1:
> > > - add PCI device id into pci bus glue
> > 
> > this guy should be the last in the series, with all AMD quirks being
> > enabled at once. This will avoid bisection points where AMD's platforms
> > don't work.
> > 
> 
> So all the AMD special configuration and device id should be in one
> patch, right?

correct :-)

-- 
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Re: [PATCH v2 02/16] pci: quirks: add quirk to avoid AMD NL to bind with xhci

2014-10-24 Thread Bjorn Helgaas
On Fri, Oct 17, 2014 at 04:53:27PM +0800, Huang Rui wrote:
> The dwc3 controller is the PCI-E device in AMD NL platform, but the class code
> of PCI header is 0x0c0330, the same with xHC. That's because it needs to meet
> the windows enviroment. The dwc3 controller acted as only host mode to bind 
> with
> windows xhci driver.
> But on linux, sometimes, it would auto-bind with xhci driver as well (class 
> code
> 0x0c0330) despite it uses Pid/Vid on dwc3 driver.

This changelog really doesn't make any sense unless the reader already
knows everything.  I think you mean something like this:

  The AMD NL (please explain what "NL" is; Google has no clue) SoC contains
  a DesignWare USB3 Dual-Role Device that can be operated either as a USB
  Host or a USB Device.  In the AMD NL platform, this device ([1022:7912])
  has a class code of PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the
  xhci driver will claim it.

  But the dwc3 driver is a more specific driver for this device, and we'd
  prefer to use it instead of xhci.  To prevent xhci from claiming the
  device, change the class code to 0x0c03fe, which the PCI r3.0 spec
  defines as "USB device (not host controller)".  The dwc3 driver can then
  claim it based on its Vendor and Device ID.

Obviously, this means the device won't work at all unless dwc3 is enabled.
Previously, it probably would work as a host controller with the xhci
driver.  I assume this change is what you want.

> Heikki suggested to use the quirk to fix this issue, and the detailed 
> discussion
> is at below thread:
> http://marc.info/?l=linux-usb&m=141197934712824&w=2

This changelog needs to be wrapped so no line is longer than 75 characters.

Please run "git log --oneline --no-merges drivers/pci/quirks.c" and make
your subject line match the rest.  In particular, "PCI" (not "pci"), drop
the "quirks:" part, and capitalize "Add".

> Suggested-by: Heikki Krogerus 
> Cc: Bjorn Helgaas 
> Signed-off-by: Huang Rui 
> ---
>  drivers/pci/quirks.c | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 90acb32..3c911b7 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -378,6 +378,26 @@ static void quirk_ati_exploding_mce(struct pci_dev *dev)
>  }
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,   PCI_DEVICE_ID_ATI_RS100,   
> quirk_ati_exploding_mce);
>  
> +/* FIXME should define in  */
> +#define PCI_DEVICE_ID_AMD_NL 0x7912

If you KNOW this should be in linux/pci_ids.h (and it looks like it COULD
go there, since you do use the same definition in patch [01/16]), why don't
you just do it?  Why are you wasting our time reviewing trivial stuff like
this?

> +
> +/*
> + * AMD NL SoC 7912 PCI device is dwc3 controller, but the class code of PCI
> + * header is 0x0c0330, the same with xHC. That's because it need to meet the
> + * windows enviroment. The dwc3 controller acted as only host mode to bind 
> with
> + * windows xhci driver. But on linux, sometimes, we auto-bind with xhci 
> driver
> + * as well (class code 0x0c0330) despite we use Pid/Vid on dwc3 driver. So 
> this
> + * quirk used a dummy class code to avoid to bind with xhci driver at booting
> + * phase.
> + */
> +static void quirk_amd_nl_class(struct pci_dev *pdev)
> +{
> + /* Use a dummy class value instead of PCI header provided */

When you say "dummy class value," that makes it sound like you just chose
a random invalid value.  But this value is actually defined by the spec, so
you should use the description from the spec, namely, "USB device (not host
controller)".

Bjorn

> + pdev->class = 0x0c03fe;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL,
> + quirk_amd_nl_class);
> +
>  /*
>   * Let's make the southbridge information explicit instead
>   * of having to worry about people probing the ACPI areas,
> -- 
> 1.9.1
> 
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Re: [PATCH v2 07/16] usb: dwc3: add lpm erratum support

2014-10-24 Thread Huang Rui
On Fri, Oct 17, 2014 at 09:48:59AM -0500, Felipe Balbi wrote:
> On Fri, Oct 17, 2014 at 04:53:32PM +0800, Huang Rui wrote:
> > When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced 
> > Configuration
> > of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is 
> > enabled
> > in host mode. In device mode it adds the capability to send NYET response 
> > based
> > on the BESL value received in the LPM token.
> > 
> > This patch add an entry that soc platform is able to define the lpm capacity
> > with their own device tree or bus glue layer.
> > 
> > Suggested-by: Felipe Balbi 
> > Signed-off-by: Huang Rui 
> > ---
> >  drivers/usb/dwc3/core.c  |  2 ++
> >  drivers/usb/dwc3/core.h  | 24 +++-
> >  drivers/usb/dwc3/dwc3-pci.c  |  1 +
> >  drivers/usb/dwc3/gadget.c|  7 +++
> >  drivers/usb/dwc3/platform_data.h |  1 +
> >  5 files changed, 26 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index 819e501..25db533 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
> >  
> > if (node) {
> > dwc->maximum_speed = of_usb_get_maximum_speed(node);
> > +   dwc->has_lpm_erratum = of_property_read_bool(node, 
> > "snps,has-lpm-erratum");
> >  
> > dwc->needs_fifo_resize = of_property_read_bool(node, 
> > "tx-fifo-resize");
> > dwc->dr_mode = of_usb_get_dr_mode(node);
> > } else if (pdata) {
> > dwc->maximum_speed = pdata->maximum_speed;
> > +   dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> >  
> > dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> > dwc->dr_mode = pdata->dr_mode;
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index cfe0d57..d58479e 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -246,16 +246,19 @@
> >  #define DWC3_DCTL_TRGTULST_SS_INACT(DWC3_DCTL_TRGTULST(6))
> >  
> >  /* These apply for core versions 1.94a and later */
> > -#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
> > -#define DWC3_DCTL_L1_HIBER_EN  (1 << 18)
> > -#define DWC3_DCTL_CRS  (1 << 17)
> > -#define DWC3_DCTL_CSS  (1 << 16)
> > +#define DWC3_DCTL_LPM_ERRATA_MASK  DWC3_DCTL_LPM_ERRATA(0xf)
> > +#define DWC3_DCTL_LPM_ERRATA(n)((n) << 20)
> > -#define DWC3_DCTL_INITU2ENA(1 << 12)
> > -#define DWC3_DCTL_ACCEPTU2ENA  (1 << 11)
> > -#define DWC3_DCTL_INITU1ENA(1 << 10)
> > -#define DWC3_DCTL_ACCEPTU1ENA  (1 << 9)
> > -#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
> > +#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
> > +#define DWC3_DCTL_L1_HIBER_EN  (1 << 18)
> > +#define DWC3_DCTL_CRS  (1 << 17)
> > +#define DWC3_DCTL_CSS  (1 << 16)
> > +
> > +#define DWC3_DCTL_INITU2ENA(1 << 12)
> > +#define DWC3_DCTL_ACCEPTU2ENA  (1 << 11)
> > +#define DWC3_DCTL_INITU1ENA(1 << 10)
> > +#define DWC3_DCTL_ACCEPTU1ENA  (1 << 9)
> > +#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
> >  
> >  #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
> >  #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
> > @@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
> >   * @ep0_bounced: true when we used bounce buffer
> >   * @ep0_expect_in: true when we expect a DATA IN transfer
> >   * @has_hibernation: true when dwc3 was configured with Hibernation
> > + * @has_lpm_erratum: true when core was configured with LPM Erratum. Note 
> > that
> > + * there's now way for software to detect this in runtime.
> >   * @is_selfpowered: true when we are selfpowered
> >   * @is_fpga: true when we are using the FPGA board
> >   * @needs_fifo_resize: not all users might want fifo resizing, flag it
> > @@ -771,6 +776,7 @@ struct dwc3 {
> > unsignedep0_bounced:1;
> > unsignedep0_expect_in:1;
> > unsignedhas_hibernation:1;
> > +   unsignedhas_lpm_erratum:1;
> > unsignedis_selfpowered:1;
> > unsignedis_fpga:1;
> > unsignedneeds_fifo_resize:1;
> > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > index a89db6c..bbe946c 100644
> > --- a/drivers/usb/dwc3/dwc3-pci.c
> > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > @@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> >  
> > if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > PCI_DEVICE_ID_AMD_NL) {
> > +   dwc3_pdata.has_lpm_erratum = true;
> > dwc3_pdata.quirks |= DWC3_QUIRK_AMD_NL;
> > }
> >  
> 
> let's combine all AMD patches as the last patch in the series so we add
> AMD support with all quirks in one place.
> 

Re: [PATCH v2 07/16] usb: dwc3: add lpm erratum support

2014-10-24 Thread Felipe Balbi
Hi,

On Sat, Oct 25, 2014 at 01:01:28AM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 09:48:59AM -0500, Felipe Balbi wrote:
> > On Fri, Oct 17, 2014 at 04:53:32PM +0800, Huang Rui wrote:
> > > When parameter DWC_USB3_LPM_ERRATA_ENABLE is enabled in Andvanced 
> > > Configuration
> > > of coreConsultant, it supports of xHCI BESL Errata Dated 10/19/2011 is 
> > > enabled
> > > in host mode. In device mode it adds the capability to send NYET response 
> > > based
> > > on the BESL value received in the LPM token.
> > > 
> > > This patch add an entry that soc platform is able to define the lpm 
> > > capacity
> > > with their own device tree or bus glue layer.
> > > 
> > > Suggested-by: Felipe Balbi 
> > > Signed-off-by: Huang Rui 
> > > ---
> > >  drivers/usb/dwc3/core.c  |  2 ++
> > >  drivers/usb/dwc3/core.h  | 24 +++-
> > >  drivers/usb/dwc3/dwc3-pci.c  |  1 +
> > >  drivers/usb/dwc3/gadget.c|  7 +++
> > >  drivers/usb/dwc3/platform_data.h |  1 +
> > >  5 files changed, 26 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 819e501..25db533 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -708,11 +708,13 @@ static int dwc3_probe(struct platform_device *pdev)
> > >  
> > >   if (node) {
> > >   dwc->maximum_speed = of_usb_get_maximum_speed(node);
> > > + dwc->has_lpm_erratum = of_property_read_bool(node, 
> > > "snps,has-lpm-erratum");
> > >  
> > >   dwc->needs_fifo_resize = of_property_read_bool(node, 
> > > "tx-fifo-resize");
> > >   dwc->dr_mode = of_usb_get_dr_mode(node);
> > >   } else if (pdata) {
> > >   dwc->maximum_speed = pdata->maximum_speed;
> > > + dwc->has_lpm_erratum = pdata->has_lpm_erratum;
> > >  
> > >   dwc->needs_fifo_resize = pdata->tx_fifo_resize;
> > >   dwc->dr_mode = pdata->dr_mode;
> > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > > index cfe0d57..d58479e 100644
> > > --- a/drivers/usb/dwc3/core.h
> > > +++ b/drivers/usb/dwc3/core.h
> > > @@ -246,16 +246,19 @@
> > >  #define DWC3_DCTL_TRGTULST_SS_INACT  (DWC3_DCTL_TRGTULST(6))
> > >  
> > >  /* These apply for core versions 1.94a and later */
> > > -#define DWC3_DCTL_KEEP_CONNECT   (1 << 19)
> > > -#define DWC3_DCTL_L1_HIBER_EN(1 << 18)
> > > -#define DWC3_DCTL_CRS(1 << 17)
> > > -#define DWC3_DCTL_CSS(1 << 16)
> > > +#define DWC3_DCTL_LPM_ERRATA_MASKDWC3_DCTL_LPM_ERRATA(0xf)
> > > +#define DWC3_DCTL_LPM_ERRATA(n)  ((n) << 20)
> > > -#define DWC3_DCTL_INITU2ENA  (1 << 12)
> > > -#define DWC3_DCTL_ACCEPTU2ENA(1 << 11)
> > > -#define DWC3_DCTL_INITU1ENA  (1 << 10)
> > > -#define DWC3_DCTL_ACCEPTU1ENA(1 << 9)
> > > -#define DWC3_DCTL_TSTCTRL_MASK   (0xf << 1)
> > > +#define DWC3_DCTL_KEEP_CONNECT   (1 << 19)
> > > +#define DWC3_DCTL_L1_HIBER_EN(1 << 18)
> > > +#define DWC3_DCTL_CRS(1 << 17)
> > > +#define DWC3_DCTL_CSS(1 << 16)
> > > +
> > > +#define DWC3_DCTL_INITU2ENA  (1 << 12)
> > > +#define DWC3_DCTL_ACCEPTU2ENA(1 << 11)
> > > +#define DWC3_DCTL_INITU1ENA  (1 << 10)
> > > +#define DWC3_DCTL_ACCEPTU1ENA(1 << 9)
> > > +#define DWC3_DCTL_TSTCTRL_MASK   (0xf << 1)
> > >  
> > >  #define DWC3_DCTL_ULSTCHNGREQ_MASK   (0x0f << 5)
> > >  #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & 
> > > DWC3_DCTL_ULSTCHNGREQ_MASK)
> > > @@ -665,6 +668,8 @@ struct dwc3_scratchpad_array {
> > >   * @ep0_bounced: true when we used bounce buffer
> > >   * @ep0_expect_in: true when we expect a DATA IN transfer
> > >   * @has_hibernation: true when dwc3 was configured with Hibernation
> > > + * @has_lpm_erratum: true when core was configured with LPM Erratum. 
> > > Note that
> > > + *   there's now way for software to detect this in 
> > > runtime.
> > >   * @is_selfpowered: true when we are selfpowered
> > >   * @is_fpga: true when we are using the FPGA board
> > >   * @needs_fifo_resize: not all users might want fifo resizing, flag it
> > > @@ -771,6 +776,7 @@ struct dwc3 {
> > >   unsignedep0_bounced:1;
> > >   unsignedep0_expect_in:1;
> > >   unsignedhas_hibernation:1;
> > > + unsignedhas_lpm_erratum:1;
> > >   unsignedis_selfpowered:1;
> > >   unsignedis_fpga:1;
> > >   unsignedneeds_fifo_resize:1;
> > > diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> > > index a89db6c..bbe946c 100644
> > > --- a/drivers/usb/dwc3/dwc3-pci.c
> > > +++ b/drivers/usb/dwc3/dwc3-pci.c
> > > @@ -148,6 +148,7 @@ static int dwc3_pci_probe(struct pci_dev *pci,
> > >  
> > >   if (pci->vendor == PCI_VENDOR_ID_AMD && pci->device ==
> > >   PCI_DEVICE_ID_AMD_NL) {
> > > + dwc

RE: [PATCH v2 02/10] usb: dwc2/gadget: fix enumeration issues

2014-10-24 Thread Paul Zimmerman


> -Original Message-
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> Excessive debug messages might cause timing issues that prevent correct
> usb enumeration. This patch hides information about USB bus reset to let
> driver enumerate fast enough to avoid making host angry. This fixes
> endless enumeration and usb reset loop observed with some Linux hosts.
> 
> Signed-off-by: Marek Szyprowski 
> Reviewed-by: Felipe Balbi 
> ---
>  drivers/usb/dwc2/gadget.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 119c8a3effc2..8870e38c1d82 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2333,7 +2333,7 @@ irq_retry:
> 
>   u32 usb_status = readl(hsotg->regs + GOTGCTL);
> 
> - dev_info(hsotg->dev, "%s: USBRst\n", __func__);
> + dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
>   dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
>   readl(hsotg->regs + GNPTXSTS));
> 

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 05/10] usb: dwc2/gadget: move setting last reset time to s3c_hsotg_core_init

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch removes duplicated code and sets last_rst variable in the
> function which does the hardware reset.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index fd52a8b23649..c1dad46bbbdd 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2247,6 +2247,8 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
>   /* must be at-least 3ms to allow bus to see disconnect */
>   mdelay(3);
> 
> + hsotg->last_rst = jiffies;
> +
>   /* remove the soft-disconnect and let's go */
>   __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
>  }
> @@ -2347,7 +2349,6 @@ irq_retry:
> -ECONNRESET, true);
> 
>   s3c_hsotg_core_init(hsotg);
> - hsotg->last_rst = jiffies;
>   }
>   }
>   }
> @@ -2908,7 +2909,6 @@ static int s3c_hsotg_udc_start(struct usb_gadget 
> *gadget,
>   goto err;
>   }
> 
> - hsotg->last_rst = jiffies;
>   dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
>   return 0;
> 
> @@ -3667,7 +3667,6 @@ static int s3c_hsotg_resume(struct platform_device 
> *pdev)
>   }
> 
>   spin_lock_irqsave(&hsotg->lock, flags);
> - hsotg->last_rst = jiffies;
>   s3c_hsotg_phy_enable(hsotg);
>   s3c_hsotg_core_init(hsotg);
>   spin_unlock_irqrestore(&hsotg->lock, flags);

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 06/10] usb: dwc2/gadget: decouple setting soft-disconnect from s3c_hsotg_core_init

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch changes s3c_hsotg_core_init function to leave hardware in
> soft disconnect mode, so the moment of coupling the hardware to the usb
> bus can be later controlled by the separate functions for enabling and
> disabling soft disconnect mode. This patch is a preparation to rework
> pullup() method.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 22 +-
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index c1dad46bbbdd..5eb2473031c4 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2124,7 +2124,7 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
>   *
>   * Issue a soft reset to the core, and await the core finishing it.
>   */
> -static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
> +static void s3c_hsotg_core_init_disconnected(struct s3c_hsotg *hsotg)
>  {
>   s3c_hsotg_corereset(hsotg);
> 
> @@ -2241,14 +2241,23 @@ static void s3c_hsotg_core_init(struct s3c_hsotg 
> *hsotg)
>   readl(hsotg->regs + DOEPCTL0));
> 
>   /* clear global NAKs */
> - writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
> + writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON,
>  hsotg->regs + DCTL);
> 
>   /* must be at-least 3ms to allow bus to see disconnect */
>   mdelay(3);
> 
>   hsotg->last_rst = jiffies;
> +}
> +
> +static void s3c_hsotg_core_disconnect(struct s3c_hsotg *hsotg)
> +{
> + /* set the soft-disconnect bit */
> + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);

I'm not really happy with adding more uses of these __orr32, __bic32
functions. When I first saw those, I went 'wtf?", because with the
assembly-sounding names, they look like some special ARM instruction
or something.

But I guess cleaning that up can wait for a future patch series, so OK.

> +}
> 
> +static void s3c_hsotg_core_connect(struct s3c_hsotg *hsotg)
> +{
>   /* remove the soft-disconnect and let's go */
>   __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
>  }
> @@ -2348,7 +2357,8 @@ irq_retry:
>   kill_all_requests(hsotg, &hsotg->eps[0],
> -ECONNRESET, true);
> 
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
>   }
>   }
>   }
> @@ -2981,7 +2991,8 @@ static int s3c_hsotg_pullup(struct usb_gadget *gadget, 
> int is_on)
>   if (is_on) {
>   s3c_hsotg_phy_enable(hsotg);
>   clk_enable(hsotg->clk);
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
>   } else {
>   clk_disable(hsotg->clk);
>   s3c_hsotg_phy_disable(hsotg);
> @@ -3668,7 +3679,8 @@ static int s3c_hsotg_resume(struct platform_device 
> *pdev)
> 
>   spin_lock_irqsave(&hsotg->lock, flags);
>   s3c_hsotg_phy_enable(hsotg);
> - s3c_hsotg_core_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + s3c_hsotg_core_connect(hsotg);
>   spin_unlock_irqrestore(&hsotg->lock, flags);
> 
>   return ret;

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 07/10] usb: dwc2/gadget: move phy control calls out of pullup() method

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch moves phy enable/disable calls from pullup() method to
> udc_start/stop functions. This solves the issue related to limited caller
> context for PHY functions, because they cannot be called from non-sleeping
> context. This is also a preparation for using soft-disconnect feature of
> udc controller in pullup() method.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 5eb2473031c4..98adf8d17493 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2919,6 +2919,8 @@ static int s3c_hsotg_udc_start(struct usb_gadget 
> *gadget,
>   goto err;
>   }
> 
> + s3c_hsotg_phy_enable(hsotg);
> +
>   dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
>   return 0;
> 
> @@ -2955,6 +2957,8 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
> 
>   spin_unlock_irqrestore(&hsotg->lock, flags);
> 
> + s3c_hsotg_phy_disable(hsotg);
> +
>   regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
> 
>   clk_disable(hsotg->clk);
> @@ -2989,13 +2993,11 @@ static int s3c_hsotg_pullup(struct usb_gadget 
> *gadget, int is_on)
> 
>   spin_lock_irqsave(&hsotg->lock, flags);
>   if (is_on) {
> - s3c_hsotg_phy_enable(hsotg);
>   clk_enable(hsotg->clk);
>   s3c_hsotg_core_init_disconnected(hsotg);
>   s3c_hsotg_core_connect(hsotg);
>   } else {
>   clk_disable(hsotg->clk);
> - s3c_hsotg_phy_disable(hsotg);
>   }
> 
>   hsotg->gadget.speed = USB_SPEED_UNKNOWN;

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 08/10] usb: dwc2/gadget: use soft-disconnect udc feature in pullup() method

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch moves udc initialization from pullup() method to
> s3c_hsotg_udc_start(), so that method ends with hardware fully
> initialized and left in soft-disconnected state. After this change, the
> pullup() method simply clears soft-disconnect start() when called with
> is_on=1. For completeness, a call to s3c_hsotg_core_disconnect() has
> been added when pullup() method is called with is_on=0, what puts the
> udc hardware back to soft-disconnected state.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 98adf8d17493..e8ffc080e6c7 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2883,6 +2883,7 @@ static int s3c_hsotg_udc_start(struct usb_gadget 
> *gadget,
>  struct usb_gadget_driver *driver)
>  {
>   struct s3c_hsotg *hsotg = to_hsotg(gadget);
> + unsigned long flags;
>   int ret;
> 
>   if (!hsotg) {
> @@ -2921,7 +2922,13 @@ static int s3c_hsotg_udc_start(struct usb_gadget 
> *gadget,
> 
>   s3c_hsotg_phy_enable(hsotg);
> 
> + spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_init(hsotg);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + spin_unlock_irqrestore(&hsotg->lock, flags);
> +
>   dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
> +
>   return 0;
> 
>  err:
> @@ -2994,9 +3001,9 @@ static int s3c_hsotg_pullup(struct usb_gadget *gadget, 
> int is_on)
>   spin_lock_irqsave(&hsotg->lock, flags);
>   if (is_on) {
>   clk_enable(hsotg->clk);
> - s3c_hsotg_core_init_disconnected(hsotg);
>   s3c_hsotg_core_connect(hsotg);
>   } else {
> + s3c_hsotg_core_disconnect(hsotg);
>   clk_disable(hsotg->clk);
>   }
> 

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 09/10] usb: dwc2/gadget: fix calls to phy control functions in suspend/resume code

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch moves calls to phy enable/disable out of spinlock protected
> blocks in device suspend/resume to fix incorrect caller context. Phy
> related functions must not be called from atomic context. To protect
> device internal state from a race during suspend, a call to
> s3c_hsotg_core_disconnect() is added under a spinlock, what prevents any
> further activity on the usb bus.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index e8ffc080e6c7..0d34cfc71bfb 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -3653,11 +3653,13 @@ static int s3c_hsotg_suspend(struct platform_device 
> *pdev, pm_message_t state)
>hsotg->driver->driver.name);
> 
>   spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_core_disconnect(hsotg);
>   s3c_hsotg_disconnect(hsotg);
> - s3c_hsotg_phy_disable(hsotg);
>   hsotg->gadget.speed = USB_SPEED_UNKNOWN;
>   spin_unlock_irqrestore(&hsotg->lock, flags);
> 
> + s3c_hsotg_phy_disable(hsotg);
> +
>   if (hsotg->driver) {
>   int ep;
>   for (ep = 0; ep < hsotg->num_of_eps; ep++)
> @@ -3686,8 +3688,9 @@ static int s3c_hsotg_resume(struct platform_device 
> *pdev)
> hsotg->supplies);
>   }
> 
> - spin_lock_irqsave(&hsotg->lock, flags);
>   s3c_hsotg_phy_enable(hsotg);
> +
> + spin_lock_irqsave(&hsotg->lock, flags);
>   s3c_hsotg_core_init_disconnected(hsotg);
>   s3c_hsotg_core_connect(hsotg);
>   spin_unlock_irqrestore(&hsotg->lock, flags);

Acked-by: Paul Zimmerman 

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RE: [PATCH v2 10/10] usb: dwc2/gadget: rework suspend/resume code to correctly restore gadget state

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> Suspend/resume code assumed that the gadget was always enabled and
> connected to usb bus. This means that the actual state of the gadget
> (soft-enabled/disabled or connected/disconnected) was not correctly
> preserved on suspend/resume cycle. This patch fixes this issue.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/core.h   |  4 +++-
>  drivers/usb/dwc2/gadget.c | 43 +++
>  2 files changed, 30 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
> index bf015ab3b44c..3648b76a18b4 100644
> --- a/drivers/usb/dwc2/core.h
> +++ b/drivers/usb/dwc2/core.h
> @@ -210,7 +210,9 @@ struct s3c_hsotg {
>   u8  ctrl_buff[8];
> 
>   struct usb_gadget   gadget;
> - unsigned intsetup;
> + unsigned intsetup:1;
> + unsigned intconnected:1;
> + unsigned intenabled:1;
>   unsigned long   last_rst;
>   struct s3c_hsotg_ep *eps;
>  };
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 0d34cfc71bfb..c6c6cf982c90 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2925,6 +2925,8 @@ static int s3c_hsotg_udc_start(struct usb_gadget 
> *gadget,
>   spin_lock_irqsave(&hsotg->lock, flags);
>   s3c_hsotg_init(hsotg);
>   s3c_hsotg_core_init_disconnected(hsotg);
> + hsotg->enabled = 1;
> + hsotg->connected = 0;
>   spin_unlock_irqrestore(&hsotg->lock, flags);
> 
>   dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
> @@ -2961,6 +2963,8 @@ static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
> 
>   hsotg->driver = NULL;
>   hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + hsotg->enabled = 0;
> + hsotg->connected = 0;
> 
>   spin_unlock_irqrestore(&hsotg->lock, flags);
> 
> @@ -2999,11 +3003,14 @@ static int s3c_hsotg_pullup(struct usb_gadget 
> *gadget, int is_on)
>   dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
> 
>   spin_lock_irqsave(&hsotg->lock, flags);
> +
>   if (is_on) {
>   clk_enable(hsotg->clk);
> + hsotg->connected = 1;
>   s3c_hsotg_core_connect(hsotg);
>   } else {
>   s3c_hsotg_core_disconnect(hsotg);
> + hsotg->connected = 0;
>   clk_disable(hsotg->clk);
>   }
> 
> @@ -3652,16 +3659,18 @@ static int s3c_hsotg_suspend(struct platform_device 
> *pdev, pm_message_t state)
>   dev_info(hsotg->dev, "suspending usb gadget %s\n",
>hsotg->driver->driver.name);
> 
> - spin_lock_irqsave(&hsotg->lock, flags);
> - s3c_hsotg_core_disconnect(hsotg);
> - s3c_hsotg_disconnect(hsotg);
> - hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> - spin_unlock_irqrestore(&hsotg->lock, flags);
> + if (hsotg->enabled) {

Hmm. Are you sure it's safe to check ->enabled outside of the spinlock?
What happens if s3c_hsotg_udc_stop() runs right after this, before the
spinlock is taken, and disables stuff? Sure, it's a tiny window, but
still...

-- 
Paul

> + int ep;
> 
> - s3c_hsotg_phy_disable(hsotg);
> + spin_lock_irqsave(&hsotg->lock, flags);
> + if (hsotg->connected)
> + s3c_hsotg_core_disconnect(hsotg);
> + s3c_hsotg_disconnect(hsotg);
> + hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + spin_unlock_irqrestore(&hsotg->lock, flags);
> +
> + s3c_hsotg_phy_disable(hsotg);
> 
> - if (hsotg->driver) {
> - int ep;
>   for (ep = 0; ep < hsotg->num_of_eps; ep++)
>   s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
> 
> @@ -3679,21 +3688,23 @@ static int s3c_hsotg_resume(struct platform_device 
> *pdev)
>   unsigned long flags;
>   int ret = 0;
> 
> - if (hsotg->driver) {
> + if (hsotg->driver)
>   dev_info(hsotg->dev, "resuming usb gadget %s\n",
>hsotg->driver->driver.name);
> 
> + if (hsotg->enabled) {
>   clk_enable(hsotg->clk);
>   ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
> -   hsotg->supplies);
> - }
> + hsotg->supplies);
> 
> - s3c_hsotg_phy_enable(hsotg);
> + s3c_hsotg_phy_enable(hsotg);
> 
> - spin_lock_irqsave(&hsotg->lock, flags);
> - s3c_hsotg_core_init_disconnected(hsotg);
> - s3c_hsotg_core_connect(hsotg);
> - spin_unlock_irqrestore(&hsotg->lock, flags);
> + spin_lock_irqsave(&hsotg->lock, flags);
> + s3c_hsotg_core_init_disconnected(hsotg);
> + if (hsotg->connected)
> + s3c_hsotg_core_connect(hsotg);
> + spin_unlock_irqrestore(&hsotg->lock, flags)

RE: [PATCH v2 01/10] usb: dwc2/gadget: report disconnect event from 'end session' irq

2014-10-24 Thread Paul Zimmerman
> From: Marek Szyprowski [mailto:m.szyprow...@samsung.com]
> Sent: Monday, October 20, 2014 3:46 AM
> 
> This patch adds a call to s3c_hsotg_disconnect() from 'end session'
> interrupt (GOTGINT_SES_END_DET) to correctly notify gadget subsystem
> about unplugged usb cable. 'disconnected' interrupt (DISCONNINT) might
> look a bit more suitable for this event, but it is asserted only in
> host mode, so in device mode we need to use something else.
> 
> Signed-off-by: Marek Szyprowski 
> ---
>  drivers/usb/dwc2/gadget.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
> index 7b5856fadd93..119c8a3effc2 100644
> --- a/drivers/usb/dwc2/gadget.c
> +++ b/drivers/usb/dwc2/gadget.c
> @@ -2279,6 +2279,12 @@ irq_retry:
>   dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
> 
>   writel(otgint, hsotg->regs + GOTGINT);
> +
> + if (otgint & GOTGINT_SES_END_DET) {
> + if (hsotg->gadget.speed != USB_SPEED_UNKNOWN)
> + s3c_hsotg_disconnect(hsotg);
> + hsotg->gadget.speed = USB_SPEED_UNKNOWN;
> + }
>   }
> 
>   if (gintsts & GINTSTS_SESSREQINT) {

Does this mean we can get rid of the call to s3c_hsotg_disconnect in
s3c_hsotg_process_control after a SET_ADDRESS is received? If not,
then s3c_hsotg_disconnect will be called twice, once here after the
disconnect, and once again after the reconnect and SET_ADDRESS.

-- 
Paul

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Re: [GIT PULL] USB fixes for v3.18-rc2

2014-10-24 Thread Greg KH
On Fri, Oct 24, 2014 at 10:14:12AM -0500, Felipe Balbi wrote:
> Hi Greg,
> 
> Here's our first set of fixes for v3.18-rc cycle.
> 
> Quite a few goodies here but the most important is that most gadget drivers
> (except for g_hid, g_midi and g_webcam) pass USB[23]0CV with MUSB and DWC3.
> 
> All patches have been tested for weeks (since v3.18 merge window opened) and
> they have also been tested for a few days on top of v3.18-rc1.
> 
> Let me know if you want anything to be changed.
> 
> cheers
> 
> 
> The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:
> 
>   Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git 
> tags/fixes-for-v3.18-rc2

Pulled and pushed out, thanks.

greg k-h
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