[PATCHv4 7/7] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

[tthayer]

From: Thor Thayer 

Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer 
---
v2  No change
v3  Add interrupts for SBERR and DBERR.
v4  No change
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 21f6c3c..5cf4dc5 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -628,6 +628,22 @@
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 <33 IRQ_TYPE_LEVEL_HIGH>;
};
+
+   emac0-rx-ecc@ff8c0800 {
+   compatible = "altr,socfpga-eth-mac-ecc";
+   reg = <0xff8c0800 0x400>;
+   parent = <&gmac0>;
+   interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+<36 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   emac0-tx-ecc@ff8c0c00 {
+   compatible = "altr,socfpga-eth-mac-ecc";
+   reg = <0xff8c0c00 0x400>;
+   parent = <&gmac0>;
+   interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+<37 IRQ_TYPE_LEVEL_HIGH>;
+   };
};
 
rst: rstmgr@ffd05000 {
-- 
1.7.9.5

[PATCHv4 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions

[tthayer]

From: Thor Thayer 

In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.

Signed-off-by: Thor Thayer 
---
v2  New patch. Move shared functions outside OCRAM only area.
v3  Change title line - check_deps & IRQ.
v4  Replace #ifdeffery with __maybe_unused macro.
---
 drivers/edac/altera_edac.c |   62 +++-
 1 file changed, 33 insertions(+), 29 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 14c9248..5f01974 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -825,16 +825,16 @@ static struct platform_driver altr_edac_device_driver = {
 };
 module_platform_driver(altr_edac_device_driver);
 
-/*** OCRAM EDAC Device Functions */
+/*** Arria10 Device ECC Shared Functions */
 
-#ifdef CONFIG_EDAC_ALTERA_OCRAM
 /*
  *  Test for memory's ECC dependencies upon entry because platform specific
  *  startup should have initialized the memory and enabled the ECC.
  *  Can't turn on ECC here because accessing un-initialized memory will
  *  cause CE/UE errors possibly causing an ABORT.
  */
-static int altr_check_ecc_deps(struct altr_edac_device_dev *device)
+static int __maybe_unused
+altr_check_ecc_deps(struct altr_edac_device_dev *device)
 {
void __iomem  *base = device->base;
const struct edac_device_prv_data *prv = device->data;
@@ -848,6 +848,36 @@ static int altr_check_ecc_deps(struct altr_edac_device_dev 
*device)
return -ENODEV;
 }
 
+static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
+{
+   struct altr_edac_device_dev *dci = dev_id;
+   void __iomem  *base = dci->base;
+
+   if (irq == dci->sb_irq) {
+   writel(ALTR_A10_ECC_SERRPENA,
+  base + ALTR_A10_ECC_INTSTAT_OFST);
+   edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
+
+   return IRQ_HANDLED;
+   } else if (irq == dci->db_irq) {
+   writel(ALTR_A10_ECC_DERRPENA,
+  base + ALTR_A10_ECC_INTSTAT_OFST);
+   edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
+   if (dci->data->panic)
+   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+
+   return IRQ_HANDLED;
+   }
+
+   WARN_ON(1);
+
+   return IRQ_NONE;
+}
+
+/*** OCRAM EDAC Device Functions */
+
+#ifdef CONFIG_EDAC_ALTERA_OCRAM
+
 static void *ocram_alloc_mem(size_t size, void **other)
 {
struct device_node *np;
@@ -882,32 +912,6 @@ static void ocram_free_mem(void *p, size_t size, void 
*other)
gen_pool_free((struct gen_pool *)other, (u32)p, size);
 }
 
-static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
-{
-   struct altr_edac_device_dev *dci = dev_id;
-   void __iomem  *base = dci->base;
-
-   if (irq == dci->sb_irq) {
-   writel(ALTR_A10_ECC_SERRPENA,
-  base + ALTR_A10_ECC_INTSTAT_OFST);
-   edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
-
-   return IRQ_HANDLED;
-   } else if (irq == dci->db_irq) {
-   writel(ALTR_A10_ECC_DERRPENA,
-  base + ALTR_A10_ECC_INTSTAT_OFST);
-   edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
-   if (dci->data->panic)
-   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
-
-   return IRQ_HANDLED;
-   }
-
-   WARN_ON(1);
-
-   return IRQ_NONE;
-}
-
 static const struct edac_device_prv_data ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
-- 
1.7.9.5

[PATCHv4 2/7] EDAC, altera: Make all private data structures static const.

[tthayer]

From: Thor Thayer 

The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.

Signed-off-by: Thor Thayer 
---
v4  New patch added for conversion.
---
 drivers/edac/altera_edac.c |   16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index ced7c55..14c9248 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -550,10 +550,10 @@ module_platform_driver(altr_edac_driver);
  * trigger testing are different for each memory.
  */
 
-const struct edac_device_prv_data ocramecc_data;
-const struct edac_device_prv_data l2ecc_data;
-const struct edac_device_prv_data a10_ocramecc_data;
-const struct edac_device_prv_data a10_l2ecc_data;
+static const struct edac_device_prv_data ocramecc_data;
+static const struct edac_device_prv_data l2ecc_data;
+static const struct edac_device_prv_data a10_ocramecc_data;
+static const struct edac_device_prv_data a10_l2ecc_data;
 
 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
 {
@@ -908,7 +908,7 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void 
*dev_id)
return IRQ_NONE;
 }
 
-const struct edac_device_prv_data ocramecc_data = {
+static const struct edac_device_prv_data ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
@@ -924,7 +924,7 @@ const struct edac_device_prv_data ocramecc_data = {
.inject_fops = &altr_edac_device_inject_fops,
 };
 
-const struct edac_device_prv_data a10_ocramecc_data = {
+static const struct edac_device_prv_data a10_ocramecc_data = {
.setup = altr_check_ecc_deps,
.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
@@ -1028,7 +1028,7 @@ static irqreturn_t altr_edac_a10_l2_irq(int irq, void 
*dev_id)
return IRQ_NONE;
 }
 
-const struct edac_device_prv_data l2ecc_data = {
+static const struct edac_device_prv_data l2ecc_data = {
.setup = altr_l2_check_deps,
.ce_clear_mask = 0,
.ue_clear_mask = 0,
@@ -1043,7 +1043,7 @@ const struct edac_device_prv_data l2ecc_data = {
.inject_fops = &altr_edac_device_inject_fops,
 };
 
-const struct edac_device_prv_data a10_l2ecc_data = {
+static const struct edac_device_prv_data a10_l2ecc_data = {
.setup = altr_l2_check_deps,
.ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
.ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
-- 
1.7.9.5

[PATCHv4 5/7] EDAC, altera: Add Arria10 ECC memory init functions

[tthayer]

From: Thor Thayer 

In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.

Signed-off-by: Thor Thayer 
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific functions so that function
declarations are not required.
Use ERRINTENS & ERRINTENR registers instead of read/modify/write.
v3: Changes for common compatibility string:
- Pass node instead of compatibility string.
- New altr_init_a10_ecc_device_type() for peripherals.
- Add __init to altr_init_a10_ecc_block().
- Add a10_get_irq_mask().
v4  Replace ifdefs with __maybe_unused macro
Improve if,else statement in altr_init_memory_port()
Remove confusing comment about shared function.
---
 drivers/edac/altera_edac.c |  192 
 drivers/edac/altera_edac.h |8 ++
 2 files changed, 200 insertions(+)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 5f01974..d97f22e 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -19,6 +19,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -874,6 +875,197 @@ static irqreturn_t __maybe_unused 
altr_edac_a10_ecc_irq(int irq, void *dev_id)
return IRQ_NONE;
 }
 
+/*** Arria10 Memory Buffer Functions */
+
+static inline int a10_get_irq_mask(struct device_node *np)
+{
+   int irq;
+   const u32 *handle = of_get_property(np, "interrupts", NULL);
+
+   if (!handle)
+   return -ENODEV;
+   irq = be32_to_cpup(handle);
+   return irq;
+}
+
+static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+   u32 value = readl(ioaddr);
+
+   value |= bit_mask;
+   writel(value, ioaddr);
+}
+
+static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+   u32 value = readl(ioaddr);
+
+   value &= ~bit_mask;
+   writel(value, ioaddr);
+}
+
+static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
+{
+   u32 value = readl(ioaddr);
+
+   return (value & bit_mask) ? 1 : 0;
+}
+
+/*
+ * This function uses the memory initialization block in the Arria10 ECC
+ * controller to initialize/clear the entire memory data and ECC data.
+ */
+static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
+{
+   int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
+   u32 init_mask, stat_mask, clear_mask;
+   int ret = 0;
+
+   if (port) {
+   init_mask = ALTR_A10_ECC_INITB;
+   stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
+   clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
+   } else {
+   init_mask = ALTR_A10_ECC_INITA;
+   stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
+   clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
+   }
+
+   ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
+   while (limit--) {
+   if (ecc_test_bits(stat_mask,
+ (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
+   break;
+   udelay(1);
+   }
+   if (limit < 0)
+   ret = -EBUSY;
+
+   /* Clear any pending ECC interrupts */
+   writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
+
+   return ret;
+}
+
+static __init int __maybe_unused
+altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
+   u32 ecc_ctrl_en_mask, bool dual_port)
+{
+   int ret = 0;
+   void __iomem *ecc_block_base;
+   struct regmap *ecc_mgr_map;
+   char *ecc_name;
+   struct device_node *np_eccmgr;
+
+   ecc_name = (char *)np->name;
+
+   /* Get the ECC Manager - parent of the device EDACs */
+   np_eccmgr = of_get_parent(np);
+   ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
+ "altr,sysmgr-syscon");
+   of_node_put(np_eccmgr);
+   if (IS_ERR(ecc_mgr_map)) {
+   edac_printk(KERN_ERR, EDAC_DEVICE,
+   "Unable to get syscon altr,sysmgr-syscon\n");
+   return -ENODEV;
+   }
+
+   /* Map the ECC Block */
+   ecc_block_base = of_iomap(np, 0);
+   if (!ecc_block_base) {
+   edac_printk(KERN_ERR, EDAC_DEVICE,
+   "Unable to map %s ECC block\n", ecc_name);
+   return -ENODEV;
+   }
+
+   /* Disable ECC */
+   regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
+   writel(ALTR_A10_ECC_SERRINTEN,
+  (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
+   ecc_clear_bits(ecc_ctrl_en_mask,
+  (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
+   /* Ensure all writes complete */
+   wmb();
+   /* Use HW initialization block to initialize memory for ECC */
+   ret = altr_init_memory_port(ec

[PATCHv4 1/7] EDAC, altera: Add panic flag check to A10 IRQ

[tthayer]

From: Thor Thayer 

In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.

OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.

ECCs on peripheral FIFO buffers will not cause a kernel panic
on DBERRs because the packet can be retried and therefore
recovered.

Signed-off-by: Thor Thayer 
---
v2  New patch. Add panic flag to IRQ function.
v3  No change
v4  Add reasons to panic on DBERR in OCRAM.
---
 drivers/edac/altera_edac.c |9 -
 drivers/edac/altera_edac.h |1 +
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 926bcaf..ced7c55 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -897,7 +897,8 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void 
*dev_id)
writel(ALTR_A10_ECC_DERRPENA,
   base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
-   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+   if (dci->data->panic)
+   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
 
return IRQ_HANDLED;
}
@@ -936,6 +937,12 @@ const struct edac_device_prv_data a10_ocramecc_data = {
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject_fops,
+   /*
+* OCRAM panic on uncorrectable error because sleep/resume
+* functions and FPGA contents are stored in OCRAM. Prefer
+* a kernel panic over executing/loading corrupted data.
+*/
+   .panic = true,
 };
 
 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 62b0fa0..cf4e8cb 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -298,6 +298,7 @@ struct edac_device_prv_data {
irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
int trig_alloc_sz;
const struct file_operations *inject_fops;
+   bool panic;
 };
 
 struct altr_edac_device_dev {
-- 
1.7.9.5

[PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

[tthayer]

From: Thor Thayer 

Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.

Signed-off-by: Thor Thayer 
---
v2  No Change
v3  Change to common compatible string based on maintainer comments
Add local IRQ values.
v4  Add compatible string for parent node.
---
 .../bindings/arm/altera/socfpga-eccmgr.txt |   24 
 1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 15eb0df..7c714ba 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -82,6 +82,14 @@ Required Properties:
 - interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
 
+Ethernet FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-eth-mac-ecc"
+- reg: Address and size for ECC block registers.
+- parent : phandle to parent (altr,socfpga-stmmac) Ethernet node.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt, in this order.
+
 Example:
 
eccmgr: eccmgr@ffd06000 {
@@ -108,4 +116,20 @@ Example:
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 <33 IRQ_TYPE_LEVEL_HIGH> ;
};
+
+   emac0-rx-ecc@ff8c0800 {
+   compatible = "altr,socfpga-eth-mac-ecc";
+   reg = <0xff8c0800 0x400>;
+   parent = <&gmac0>;
+   interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+<36 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
+   emac0-tx-ecc@ff8c0c00 {
+   compatible = "altr,socfpga-eth-mac-ecc";
+   reg = <0xff8c0c00 0x400>;
+   parent = <&gmac0>;
+   interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+<37 IRQ_TYPE_LEVEL_HIGH>;
+   };
};
-- 
1.7.9.5

[PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions

[tthayer]

From: Thor Thayer 

This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).

Thor Thayer (7):
  EDAC, altera: Add panic flag check to A10 IRQ
  EDAC, altera: Make all private data structures static const.
  EDAC, altera: Share Arria10 check_deps & IRQ functions
  Documentation: dt: socfpga: Add Arria10 Ethernet binding
  EDAC, altera: Add Arria10 ECC memory init functions
  EDAC, altera: Add Arria10 Ethernet EDAC support
  ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

 .../bindings/arm/altera/socfpga-eccmgr.txt |   24 ++
 arch/arm/boot/dts/socfpga_arria10.dtsi |   16 +
 drivers/edac/Kconfig   |7 +
 drivers/edac/altera_edac.c |  312 +---
 drivers/edac/altera_edac.h |   12 +
 5 files changed, 333 insertions(+), 38 deletions(-)

-- 
1.7.9.5

[PATCHv4 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support

[tthayer]

From: Thor Thayer 

Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.

Signed-off-by: Thor Thayer 
---
v2  Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
v3  Use common compatiblity string.
Simplify socfpga_init_ethernet_ecc().
v4  Make private data static.
Rename Ethernet private data to more generic name.
Remove panic field initialization.
Rename EN mask field to ALTR_A10_COMMON_ECC_EN_CTL
---
 drivers/edac/Kconfig   |7 +++
 drivers/edac/altera_edac.c |   37 +++--
 drivers/edac/altera_edac.h |3 +++
 3 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 6ca7474..d0c1dab 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM
  Support for error detection and correction on the
  Altera On-Chip RAM Memory for Altera SoCs.
 
+config EDAC_ALTERA_ETHERNET
+   bool "Altera Ethernet FIFO ECC"
+   depends on EDAC_ALTERA=y
+   help
+ Support for error detection and correction on the
+ Altera Ethernet FIFO Memory for Altera SoCs.
+
 config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index d97f22e..c4e3d0f 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1258,6 +1258,33 @@ static const struct edac_device_prv_data a10_l2ecc_data 
= {
 
 #endif /* CONFIG_EDAC_ALTERA_L2C */
 
+/* Ethernet Device Functions /
+
+#ifdef CONFIG_EDAC_ALTERA_ETHERNET
+
+static const struct edac_device_prv_data a10_enetecc_data = {
+   .setup = altr_check_ecc_deps,
+   .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
+   .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
+   .dbgfs_name = "altr_trigger",
+   .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
+   .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
+   .ce_set_mask = ALTR_A10_ECC_TSERRA,
+   .ue_set_mask = ALTR_A10_ECC_TDERRA,
+   .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
+   .ecc_irq_handler = altr_edac_a10_ecc_irq,
+   .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+
+static int __init socfpga_init_ethernet_ecc(void)
+{
+   return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
+}
+
+early_initcall(socfpga_init_ethernet_ecc);
+
+#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
+
 /* Arria10 EDAC Device Functions */
 static const struct of_device_id altr_edac_a10_device_of_match[] = {
 #ifdef CONFIG_EDAC_ALTERA_L2C
@@ -1267,6 +1294,10 @@ static const struct of_device_id 
altr_edac_a10_device_of_match[] = {
{ .compatible = "altr,socfpga-a10-ocram-ecc",
  .data = &a10_ocramecc_data },
 #endif
+#ifdef CONFIG_EDAC_ALTERA_ETHERNET
+   { .compatible = "altr,socfpga-eth-mac-ecc",
+ .data = &a10_enetecc_data },
+#endif
{},
 };
 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1555,8 +1586,10 @@ static int altr_edac_a10_probe(struct platform_device 
*pdev)
continue;
if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
altr_edac_a10_device_add(edac, child);
-   else if (of_device_is_compatible(child,
-"altr,socfpga-a10-ocram-ecc"))
+   else if ((of_device_is_compatible(child,
+   "altr,socfpga-a10-ocram-ecc")) ||
+(of_device_is_compatible(child,
+   "altr,socfpga-eth-mac-ecc")))
altr_edac_a10_device_add(edac, child);
else if (of_device_is_compatible(child,
 "altr,sdram-edac-a10"))
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index aa7c690..687d8e7 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -285,6 +285,9 @@ struct altr_sdram_mc_data {
 /* Arria 10 OCRAM ECC Management Group Defines */
 #define ALTR_A10_OCRAM_ECC_EN_CTL   (BIT(1) | BIT(0))
 
+/* Arria 10 Ethernet ECC Management Group Defines */
+#define ALTR_A10_COMMON_ECC_EN_CTL  BIT(0)
+
 /* A10 ECC Controller memory initialization timeout */
 #define ALTR_A10_ECC_INIT_WATCHDOG_10US  1
 
-- 
1.7.9.5

[PATCHv2 2/4] serial: 8250: of: Load TX FIFO Threshold from DT

[tthayer]

From: Thor Thayer 

Initialize the tx_loadsz parameter from passed in devicetree
tx-threshold parameter.
The tx_loadsz is calculated as the number of bytes to fill FIFO
when tx-threshold is triggered.

Signed-off-by: Thor Thayer 
---
v2  Change from reading tx-loadsz parameter to reading
tx-threshold and calculating tx_loadsz.
---
 drivers/tty/serial/8250/8250_of.c |7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c 
b/drivers/tty/serial/8250/8250_of.c
index 38963d7..7a8b5fc 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -195,6 +195,7 @@ static int of_platform_serial_probe(struct platform_device 
*ofdev)
switch (port_type) {
case PORT_8250 ... PORT_MAX_8250:
{
+   u32 tx_threshold;
struct uart_8250_port port8250;
memset(&port8250, 0, sizeof(port8250));
port8250.port = port;
@@ -202,6 +203,12 @@ static int of_platform_serial_probe(struct platform_device 
*ofdev)
if (port.fifosize)
port8250.capabilities = UART_CAP_FIFO;
 
+   /* Check for TX FIFO threshold & set tx_loadsz */
+   if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
+ &tx_threshold) == 0) &&
+   (tx_threshold < port.fifosize))
+   port8250.tx_loadsz = port.fifosize - tx_threshold;
+
if (of_property_read_bool(ofdev->dev.of_node,
  "auto-flow-control"))
port8250.capabilities |= UART_CAP_AFE;
-- 
1.7.9.5

[PATCHv2 4/4] nios2: dts: 10m50: Add tx-threshold parameter

[tthayer]

From: Thor Thayer 

The tx-threshold parameter sets the TX FIFO low water threshold
trigger for the Altera 16550-FIFO32 soft IP.

Signed-off-by: Thor Thayer 
---
v2   Change from tx-loadsz to tx-threshold
---
 arch/nios2/boot/dts/10m50_devboard.dts |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/nios2/boot/dts/10m50_devboard.dts 
b/arch/nios2/boot/dts/10m50_devboard.dts
index 3e411c6..f362b22 100755
--- a/arch/nios2/boot/dts/10m50_devboard.dts
+++ b/arch/nios2/boot/dts/10m50_devboard.dts
@@ -83,6 +83,7 @@
fifo-size = <32>;
reg-io-width = <4>;
reg-shift = <2>;
+   tx-threshold = <16>;
};
 
sysid: sysid@18001528 {
-- 
1.7.9.5

[PATCHv2 0/4] Add TX FIFO Threshold for Altera 16550-FIFOxx

[tthayer]

From: Thor Thayer 

Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.

This patch series adds the tx-threshold parameter to the device tree.
The tx_loadsz variable is amount of data that can be loaded into the
FIFO on an IRQ and is updated based on the tx-threshold value.

This patch series also adds support for the TX FIFO threshold registers
in the Altera 16550-FIFOxx soft IP.

Thor Thayer (4):
  Documentation: dt: serial: Add TX FIFO threshold parameter
  serial: 8250: of: Load TX FIFO Threshold from DT
  serial: 8250: Set Altera 16550 TX FIFO Threshold
  nios2: dts: 10m50: Add tx-threshold parameter

 Documentation/devicetree/bindings/serial/8250.txt |2 +
 arch/nios2/boot/dts/10m50_devboard.dts|1 +
 drivers/tty/serial/8250/8250_of.c |7 
 drivers/tty/serial/8250/8250_port.c   |   43 +
 include/uapi/linux/serial_reg.h   |8 
 5 files changed, 61 insertions(+)

-- 
1.7.9.5

[PATCHv2 1/4] Documentation: dt: serial: Add TX FIFO threshold parameter

[tthayer]

From: Thor Thayer 

Add the device tree binding needed to support the TX FIFO threshold
parameter.

Signed-off-by: Thor Thayer 
---
v2  Change parameter name from tx-loadsz to tx-threshold
---
 Documentation/devicetree/bindings/serial/8250.txt |2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.txt 
b/Documentation/devicetree/bindings/serial/8250.txt
index 936ab5b..f86bb06 100644
--- a/Documentation/devicetree/bindings/serial/8250.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
@@ -42,6 +42,8 @@ Optional properties:
 - auto-flow-control: one way to enable automatic flow control support. The
   driver is allowed to detect support for the capability even without this
   property.
+- tx-threshold: Specify the TX FIFO low water indication for parts with
+  programmable TX FIFO thresholds.
 
 Note:
 * fsl,ns16550:
-- 
1.7.9.5

[PATCHv2 3/4] serial: 8250: Set Altera 16550 TX FIFO Threshold

[tthayer]

From: Thor Thayer 

The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
Set the TX FIFO threshold to the FIFO size - tx_loadsz.

Signed-off-by: Thor Thayer 
---
v2  Add bounds checking of tx threshold value.
---
 drivers/tty/serial/8250/8250_port.c |   43 +++
 include/uapi/linux/serial_reg.h |8 +++
 2 files changed, 51 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_port.c 
b/drivers/tty/serial/8250/8250_port.c
index ae3a104..24ef65a 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1870,6 +1870,30 @@ static int exar_handle_irq(struct uart_port *port)
return ret;
 }
 
+/*
+ * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
+ * have a programmable TX threshold that triggers the THRE interrupt in
+ * the IIR register. In this case, the THRE interrupt indicates the FIFO
+ * has space available. Load it up with tx_loadsz bytes.
+ */
+static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
+{
+   unsigned long flags;
+   unsigned int iir = serial_port_in(port, UART_IIR);
+
+   /* TX Threshold IRQ triggered so load up FIFO */
+   if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
+   struct uart_8250_port *up = up_to_u8250p(port);
+
+   spin_lock_irqsave(&port->lock, flags);
+   serial8250_tx_chars(up);
+   spin_unlock_irqrestore(&port->lock, flags);
+   }
+
+   iir = serial_port_in(port, UART_IIR);
+   return serial8250_handle_irq(port, iir);
+}
+
 static unsigned int serial8250_tx_empty(struct uart_port *port)
 {
struct uart_8250_port *up = up_to_u8250p(port);
@@ -2158,6 +2182,25 @@ int serial8250_do_startup(struct uart_port *port)
serial_port_out(port, UART_LCR, 0);
}
 
+   /*
+* For the Altera 16550 variants, set TX threshold trigger level.
+*/
+   if (((port->type == PORT_ALTR_16550_F32) ||
+(port->type == PORT_ALTR_16550_F64) ||
+(port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
+   /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
+   if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
+   pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
+  serial_index(port));
+   } else {
+   serial_port_out(port, UART_ALTR_AFR,
+   UART_ALTR_EN_TXFIFO_LW);
+   serial_port_out(port, UART_ALTR_TX_LOW,
+   port->fifosize - up->tx_loadsz);
+   port->handle_irq = serial8250_tx_threshold_handle_irq;
+   }
+   }
+
if (port->irq) {
unsigned char iir1;
/*
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index 1e5ac4e7..b4c0484 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -376,5 +376,13 @@
 #define UART_EXAR_TXTRG0x0a/* Tx FIFO trigger level 
write-only */
 #define UART_EXAR_RXTRG0x0b/* Rx FIFO trigger level 
write-only */
 
+/*
+ * These are definitions for the Altera ALTR_16550_F32/F64/F128
+ * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
+ */
+#define UART_ALTR_AFR  0x40/* Additional Features Register */
+#define UART_ALTR_EN_TXFIFO_LW 0x01/* Enable the TX FIFO Low Watermark */
+#define UART_ALTR_TX_LOW   0x41/* Tx FIFO Low Watermark */
+
 #endif /* _LINUX_SERIAL_REG_H */
 
-- 
1.7.9.5

[PATCH 1/2] EDAC, altera: Correct EDAC IRQ error message.

[tthayer]

From: Thor Thayer 

Correct the error message sent out in the case of a single
bit error IRQ allocation.

Signed-off-by: Thor Thayer 
---
 drivers/edac/altera_edac.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 817e891..afe6305 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1749,7 +1749,7 @@ static int altr_edac_a10_device_add(struct 
altr_arria10_edac *edac,
  prv->ecc_irq_handler,
  IRQF_SHARED, ecc_name, altdev);
if (rc) {
-   edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
+   edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
goto err_release_group1;
}
 
-- 
1.7.9.5

[PATCH 2/2] EDAC, altera: Add IRQ Flags to disable IRQ while handling

[tthayer]

From: Thor Thayer 

Add the IRQF_ONESHOT and IRQF_TRIGGER_HIGH flags to disable the
IRQ while executing the IRQ handler. Remove the IRQF_SHARED because
these are not shared IRQs in the domain. Exposed when flooding IRQs.

Signed-off-by: Thor Thayer 
---
 drivers/edac/altera_edac.c |   18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index afe6305..58d3e2b 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1445,7 +1445,8 @@ static int altr_portb_setup(struct altr_edac_device_dev 
*device)
}
rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
  prv->ecc_irq_handler,
- IRQF_SHARED, ecc_name, altdev);
+ IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+ ecc_name, altdev);
if (rc) {
edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
goto err_release_group_1;
@@ -1459,7 +1460,8 @@ static int altr_portb_setup(struct altr_edac_device_dev 
*device)
}
rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
  prv->ecc_irq_handler,
- IRQF_SHARED, ecc_name, altdev);
+ IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+ ecc_name, altdev);
if (rc) {
edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
goto err_release_group_1;
@@ -1745,9 +1747,9 @@ static int altr_edac_a10_device_add(struct 
altr_arria10_edac *edac,
rc = -ENODEV;
goto err_release_group1;
}
-   rc = devm_request_irq(edac->dev, altdev->sb_irq,
- prv->ecc_irq_handler,
- IRQF_SHARED, ecc_name, altdev);
+   rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
+ IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+ ecc_name, altdev);
if (rc) {
edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
goto err_release_group1;
@@ -1759,9 +1761,9 @@ static int altr_edac_a10_device_add(struct 
altr_arria10_edac *edac,
rc = -ENODEV;
goto err_release_group1;
}
-   rc = devm_request_irq(edac->dev, altdev->db_irq,
- prv->ecc_irq_handler,
- IRQF_SHARED, ecc_name, altdev);
+   rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
+ IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
+ ecc_name, altdev);
if (rc) {
edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
goto err_release_group1;
-- 
1.7.9.5

[PATCH 0/4] Add TX FIFO Threshold for Altera 16550-FIFOxx

[tthayer]

From: Thor Thayer 

Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.

This patch series adds the tx_loadsz to the device tree. The tx_loadsz
variable is amount of data that can be loaded into the FIFO on an IRQ.

This patch series also adds support for the TX FIFO threshold registers
in the Altera 16550-FIFOxx soft IP.

Thor Thayer (4):
  Documentation: dt: serial: Add TX FIFO load size
  serial: 8250: of: Load TX FIFO Load Size from DT
  serial: 8250: Set Altera 16550 TX FIFO Threshold
  nios2: dts: 10m50: Add tx-loadsz parameter

 Documentation/devicetree/bindings/serial/8250.txt |1 +
 arch/nios2/boot/dts/10m50_devboard.dts|1 +
 drivers/tty/serial/8250/8250_of.c |6 
 drivers/tty/serial/8250/8250_port.c   |   36 +
 include/uapi/linux/serial_reg.h   |8 +
 5 files changed, 52 insertions(+)

-- 
1.7.9.5

[PATCH 4/4] nios2: dts: 10m50: Add tx-loadsz parameter

[tthayer]

From: Thor Thayer 

The tx-loadsz parameter sets the TX FIFO threshold level of
the Altera 16550-FIFO32 soft IP.

Signed-off-by: Thor Thayer 
---
 arch/nios2/boot/dts/10m50_devboard.dts |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/nios2/boot/dts/10m50_devboard.dts 
b/arch/nios2/boot/dts/10m50_devboard.dts
index 3e411c6..6be1502 100755
--- a/arch/nios2/boot/dts/10m50_devboard.dts
+++ b/arch/nios2/boot/dts/10m50_devboard.dts
@@ -83,6 +83,7 @@
fifo-size = <32>;
reg-io-width = <4>;
reg-shift = <2>;
+   tx-loadsz = <16>;
};
 
sysid: sysid@18001528 {
-- 
1.7.9.5

[PATCH 3/4] serial: 8250: Set Altera 16550 TX FIFO Threshold

[tthayer]

From: Thor Thayer 

The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
These registers are initialized in serial8350_do_startup(). Set
the TX FIFO threshold to the FIFO size - tx_loadsz.

Signed-off-by: Thor Thayer 
---
 drivers/tty/serial/8250/8250_port.c |   36 +++
 include/uapi/linux/serial_reg.h |8 
 2 files changed, 44 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_port.c 
b/drivers/tty/serial/8250/8250_port.c
index 7481b95..35a3e2c 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1880,6 +1880,30 @@ static int exar_handle_irq(struct uart_port *port)
return ret;
 }
 
+/*
+ * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
+ * have a programmable TX threshold that triggers the THRE interrupt in
+ * the IIR register. In this case, the THRE interrupt indicates the FIFO
+ * has space available. Load it up with tx_loadsz bytes.
+ */
+static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
+{
+   unsigned long flags;
+   unsigned int iir = serial_port_in(port, UART_IIR);
+
+   /* TX Threshold IRQ triggered so load up FIFO */
+   if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
+   struct uart_8250_port *up = up_to_u8250p(port);
+
+   spin_lock_irqsave(&port->lock, flags);
+   serial8250_tx_chars(up);
+   spin_unlock_irqrestore(&port->lock, flags);
+   }
+
+   iir = serial_port_in(port, UART_IIR);
+   return serial8250_handle_irq(port, iir);
+}
+
 static unsigned int serial8250_tx_empty(struct uart_port *port)
 {
struct uart_8250_port *up = up_to_u8250p(port);
@@ -2169,6 +2193,18 @@ int serial8250_do_startup(struct uart_port *port)
serial_port_out(port, UART_LCR, 0);
}
 
+   /*
+* For the Altera 16550 variants, set TX threshold trigger level.
+*/
+   if (((port->type == PORT_ALTR_16550_F32) ||
+(port->type == PORT_ALTR_16550_F64) ||
+(port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
+   serial_port_out(port, UART_ALTR_AFR, UART_ALTR_EN_TXFIFO_LW);
+   serial_port_out(port, UART_ALTR_TX_LOW,
+   port->fifosize - up->tx_loadsz);
+   port->handle_irq = serial8250_tx_threshold_handle_irq;
+   }
+
if (port->irq) {
unsigned char iir1;
/*
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index 1e5ac4e7..b4c0484 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -376,5 +376,13 @@
 #define UART_EXAR_TXTRG0x0a/* Tx FIFO trigger level 
write-only */
 #define UART_EXAR_RXTRG0x0b/* Rx FIFO trigger level 
write-only */
 
+/*
+ * These are definitions for the Altera ALTR_16550_F32/F64/F128
+ * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs).
+ */
+#define UART_ALTR_AFR  0x40/* Additional Features Register */
+#define UART_ALTR_EN_TXFIFO_LW 0x01/* Enable the TX FIFO Low Watermark */
+#define UART_ALTR_TX_LOW   0x41/* Tx FIFO Low Watermark */
+
 #endif /* _LINUX_SERIAL_REG_H */
 
-- 
1.7.9.5

[PATCH 1/4] Documentation: dt: serial: Add TX FIFO load size

[tthayer]

From: Thor Thayer 

Add the device tree bindings needed to support the TX FIFO
load size.

Signed-off-by: Thor Thayer 
---
 Documentation/devicetree/bindings/serial/8250.txt |1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.txt 
b/Documentation/devicetree/bindings/serial/8250.txt
index f5561ac..93de5ef 100644
--- a/Documentation/devicetree/bindings/serial/8250.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
@@ -45,6 +45,7 @@ Optional properties:
 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
   line respectively. It will use specified GPIO instead of the peripheral
   function pin for the UART feature. If unsure, don't specify this property.
+- tx-loadsz: the number of bytes that can be loaded into the TX FIFO.
 
 Note:
 * fsl,ns16550:
-- 
1.7.9.5

[PATCH 2/4] serial: 8250: of: Load TX FIFO Load Size from DT

[tthayer]

From: Thor Thayer 

Initialize the tx_loadsz parameter if it is defined in the
device tree.

Signed-off-by: Thor Thayer 
---
 drivers/tty/serial/8250/8250_of.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c 
b/drivers/tty/serial/8250/8250_of.c
index 38963d7..3e4be2f 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -195,6 +195,7 @@ static int of_platform_serial_probe(struct platform_device 
*ofdev)
switch (port_type) {
case PORT_8250 ... PORT_MAX_8250:
{
+   u32 prop;
struct uart_8250_port port8250;
memset(&port8250, 0, sizeof(port8250));
port8250.port = port;
@@ -202,6 +203,11 @@ static int of_platform_serial_probe(struct platform_device 
*ofdev)
if (port.fifosize)
port8250.capabilities = UART_CAP_FIFO;
 
+   /* Check for TX fifo load size */
+   if (of_property_read_u32(ofdev->dev.of_node,
+"tx-loadsz", &prop) == 0)
+   port8250.tx_loadsz = prop;
+
if (of_property_read_bool(ofdev->dev.of_node,
  "auto-flow-control"))
port8250.capabilities |= UART_CAP_AFE;
-- 
1.7.9.5

[PATCHv6 1/5] arm: socfpga: Enable L2 Cache ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for L2 cache on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM initialization into separate patch.

v3/4: No change

v5: Remove l2cache.h, use io.h instead of clk-provider.h
Make copyright header inclusive. Remove MAINTAINERS entry.

v6: Remove pr_debug() & update year in header.
---
 arch/arm/mach-socfpga/Makefile   |1 +
 arch/arm/mach-socfpga/core.h |2 ++
 arch/arm/mach-socfpga/l2_cache.c |   39 ++
 arch/arm/mach-socfpga/socfpga.c  |4 +++-
 4 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..142609e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
+obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 483cb46..28c8a15 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -47,4 +47,6 @@ extern unsigned long socfpga_cpu1start_addr;
 
 #define SOCFPGA_SCU_VIRT_BASE   0xfffec000
 
+void socfpga_init_l2_ecc(void);
+
 #endif
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 000..047759d
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+void socfpga_init_l2_ecc(void)
+{
+   struct device_node *np;
+   void __iomem  *mapped_l2_edac_addr;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
+   return;
+   }
+
+   mapped_l2_edac_addr = of_iomap(np, 0);
+   if (!mapped_l2_edac_addr) {
+   pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
+   return;
+   }
+
+   /* Enable ECC */
+   writel(0x01, mapped_l2_edac_addr);
+}
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 383d61e..ce04313 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation
+ *  Copyright (C) 2012-2015 Altera Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -83,6 +83,8 @@ static void __init socfpga_init_irq(void)
 {
irqchip_init();
socfpga_sysmgr_init();
+   if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
+   socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

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[PATCHv6 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC entries

[tthayer]

From: Thor Thayer 

Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html

Signed-off-by: Thor Thayer 
---
v2: Remove OCRAM declaration and reference prior patch.

v3-5: No Change

v6: Change to nested EDAC device nodes based on community
feedback. Remove L2 syscon. Use consolidated binding.
---
 .../bindings/arm/altera/socfpga-edac.txt   |   46 
 arch/arm/boot/dts/socfpga.dtsi |   20 +
 2 files changed, 66 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-edac.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-edac.txt
new file mode 100644
index 000..4bf32e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-edac.txt
@@ -0,0 +1,46 @@
+Altera SoCFPGA Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be "altr,edac"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+L2 Cache ECC
+Required Properties:
+- compatible : Should be "altr,l2-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+On Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,ocram-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+
+   soc_ecc {
+   compatible = "altr,edac";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 252c3d1..e546e47 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -618,6 +618,26 @@
interrupts = <0 39 4>;
};
 
+   soc_ecc {
+   compatible = "altr,edac";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+   };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
-- 
1.7.9.5

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[PATCHv6 0/5] Add Altera peripheral memories to EDAC framework

[tthayer]

From: Thor Thayer 

This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.

v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
  L2 ECC platform initialization.
- Fix L2 cache dependency comments.
- Remove OCRAM node from dts and reference prior patch.

v3 changes:
- Move L2 cache & On-Chip RAM EDAC code into altera_edac.c
- Remove SDRAM module compile.

v4 changes:
- Change mask defines to use BIT().
- Fix comment style to agree with kernel coding style.
- Better printk description for read != write in trigger.
- Remove SysFS debugging message.
- Better dci->mod_name
- Move gen_pool pointer assignment to end of function.
- Invert logic to reduce indent in ocram depenency check.
- Change from dev_err() to edac_printk()
- Replace magic numbers with defines & comments.
- Improve error injection test.
- Change Makefile intermediary name to altr (from alt)

v5 changes:
- Remove l2cache.h by using if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
- Remove ocram.h by using if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
- Check prop variable before using. Include io.h.
- Add defines for better readability. Remove MAINTAINERS changes.

v6 changes:
- Simplify OCRAM initialization. Remove be32_to_cpup() calls.
- Remove syscon from L2 Cache. Force L2 Cache on if ECC enabled.
- Convert to nested ECC in device tree. 
- Additional comments to clarify debug error injection.

Thor Thayer (5):
  arm: socfpga: Enable L2 Cache ECC on startup.
  arm: socfpga: Enable OCRAM ECC on startup.
  edac: altera: Remove SDRAM module compile
  edac: altera: Add Altera L2 Cache and OCRAM EDAC Support
  arm: dts: Add Altera L2 Cache and OCRAM EDAC entries

 .../bindings/arm/altera/socfpga-edac.txt   |   46 ++
 arch/arm/boot/dts/socfpga.dtsi |   20 +
 arch/arm/mach-socfpga/Makefile |2 +
 arch/arm/mach-socfpga/core.h   |2 +
 arch/arm/mach-socfpga/l2_cache.c   |   39 ++
 arch/arm/mach-socfpga/ocram.c  |   97 
 arch/arm/mach-socfpga/socfpga.c|4 +-
 drivers/edac/Kconfig   |   20 +-
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  506 +++-
 10 files changed, 735 insertions(+), 6 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-edac.txt
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/ocram.c

-- 
1.7.9.5

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[PATCHv6 2/5] arm: socfpga: Enable OCRAM ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for On-Chip RAM on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganization of gen_pool_free. Remove defconfig from patch.

v3/4: No change

v5: Remove ocram.h, use io.h instead of clk-provider.h
Check prop in correct place. Add ECC EN defines.

v6: Implement OCRAM discovery changes from community. Add
of_node_put(). Remove be32_to_cpup(). Use __init() which
allows removal of .init_machine(). Update year in header.
---
 arch/arm/mach-socfpga/Makefile |1 +
 arch/arm/mach-socfpga/ocram.c  |   97 
 2 files changed, 98 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/ocram.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 142609e..1552ca5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -5,3 +5,4 @@
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
 obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
new file mode 100644
index 000..1f12a38
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ALTR_OCRAM_CLEAR_ECC  0x0018
+#define ALTR_OCRAM_ECC_EN 0x0019
+
+static int __init socfpga_init_ocram_ecc(void)
+{
+   struct device_node *np;
+   struct resourceres;
+   u32iram_addr;
+   void __iomem   *mapped_ocr_edac_addr;
+   resource_size_tsize;
+   struct gen_pool*gp;
+   intret;
+
+   /* Get the size of the on-chip RAM */
+   np = of_find_compatible_node(NULL, NULL, "mmio-sram");
+   if (!np) {
+   pr_err("%s: Unable to find mmio-sram in dtb\n", __func__);
+   return -ENODEV;
+   }
+
+   ret = of_address_to_resource(np, 0, &res);
+   if (ret) {
+   of_node_put(np);
+   pr_err("%s: Problem getting SRAM address in dtb\n", __func__);
+   return -ENODEV;
+   }
+   size = resource_size(&res);
+   of_node_put(np);
+
+   /* Find the OCRAM EDAC device tree node */
+   np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
+   if (!np) {
+   pr_err("%s: Unable to find altr,ocram-edac\n", __func__);
+   return -ENODEV;
+   }
+
+   mapped_ocr_edac_addr = of_iomap(np, 0);
+   if (!mapped_ocr_edac_addr) {
+   of_node_put(np);
+   pr_err("%s: Unable to map OCRAM ecc regs.\n", __func__);
+   return -ENODEV;
+   }
+
+   gp = of_get_named_gen_pool(np, "iram", 0);
+   if (!gp) {
+   of_node_put(np);
+   pr_err("%s: OCRAM cannot find gen pool\n", __func__);
+   return -ENODEV;
+   }
+   of_node_put(np);
+
+   iram_addr = gen_pool_alloc(gp, size / sizeof(size_t));
+   if (iram_addr == 0) {
+   pr_err("%s: cannot alloc from gen pool\n", __func__);
+   return -ENODEV;
+   }
+
+   /* Clear any pending OCRAM ECC interrupts, then enable ECC */
+   writel(ALTR_OCRAM_CLEAR_ECC, mapped_ocr_edac_addr);
+   writel(ALTR_OCRAM_ECC_EN, mapped_ocr_edac_addr);
+
+   memset((void *)iram_addr, 0, size);
+
+   gen_pool_free(gp, iram_addr, size / sizeof(size_t));
+
+   iounmap(mapped_ocr_edac_addr);
+
+   return 0;
+}
+
+static void __exit socfpga_exit_ocram_ecc(void)
+{
+}
+
+module_init(socfpga_init_ocram_ecc);
+module_exit(socfpga_exit_ocram_ecc);
-- 
1.7.9.5

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[PATCHv6 3/5] edac: altera: Remove SDRAM module compile

[tthayer]

From: Thor Thayer 

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer 
---
v3: Added in this version as a separate patch.

v4-6: No change.
---
 drivers/edac/Kconfig |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 49c2652..4d7285e 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-   tristate "Altera SDRAM Memory Controller EDAC"
-   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
help
  Support for error detection and correction on the
  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5

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[PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[tthayer]

From: Thor Thayer 

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device  model. The SDRAM
controller is using the Memory Controller model.

Each type of ECC is individually configurable.

The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster boot time.
2) the SDRAM has an ECC initialization dependency on the preloader
which is outside the kernel. It is desirable to be able to turn the
SDRAM on & off separately.

Signed-off-by: Thor Thayer 
---
v2: Fix L2 dependency comments.

v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c
instead of separate files.

v4: Change mask defines to use BIT().
Fix comment style to agree with kernel coding style.
Better printk description for read != write in trigger.
Remove SysFS debugging message.
Better dci->mod_name
Move gen_pool pointer assignment to end of function.
Invert logic to reduce indent in ocram depenency check.
Change from dev_err() to edac_printk()
Replace magic numbers with defines & comments.
Improve error injection test.
Change Makefile intermediary name to altr (from alt)

v5: No change.

v6: Convert to nested EDAC in device tree. Force L2 cache
on for L2Cache ECC & remove L2 cache syscon for checking
enable bit. Update year in header.
---
 drivers/edac/Kconfig   |   16 ++
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  506 +++-
 3 files changed, 524 insertions(+), 3 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 4d7285e..edf97ed 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -385,4 +385,20 @@ config EDAC_ALTERA_MC
  preloader must initialize the SDRAM before loading
  the kernel.
 
+config EDAC_ALTERA_L2C
+   bool "Altera L2 Cache EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
+   select CACHE_L2X0
+   help
+ Support for error detection and correction on the
+ Altera L2 cache Memory for Altera SoCs. This option
+  requires L2 cache so it will force that selection.
+
+config EDAC_ALTERA_OCRAM
+   bool "Altera On-Chip RAM EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && SRAM && GENERIC_ALLOCATOR
+   help
+ Support for error detection and correction on the
+ Altera On-Chip RAM Memory for Altera SoCs.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index d40c69a..b9a67c0 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -66,4 +66,7 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
 
-obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
+altr_edac-y:= altera_edac.o
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)  += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)+= altr_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3c4929f..083cd20 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright Altera Corporation (C) 2014-2015. All rights reserved.
  *  Copyright 2011-2012 Calxeda, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -17,8 +17,10 @@
  * Adapted from the highbank_mc_edac driver.
  */
 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -33,6 +35,7 @@
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
+#define EDAC_DEVICE"ALTR_MEM"
 
 /* SDRAM Controller CtrlCfg Register */
 #define CTLCFG_OFST 0x00
@@ -107,6 +110,33 @@ struct altr_sdram_mc_data {
struct regmap *mc_vbase;
 };
 
+/** EDAC Device Defines **/
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN_MASKBIT(0)
+#define ALTR_OCR_ECC_INJS_MASK  BIT(1)
+#define ALTR_OCR_ECC_INJD_MASK  BIT(2)
+#define ALTR_OCR_ECC_SERR_MASK  BIT(3)
+#define ALTR_OCR_ECC_DERR_MASK  BIT(4)
+
+/* L2 ECC Management Group Defines */
+#define ALTR_MAN_GRP_L2_ECC_OFFSET  0x00
+#define ALTR_L2_ECC_EN_MASK BIT(0)
+#define ALTR_L2_ECC_INJS_MASK   BIT(1)
+#define ALTR_L2_ECC_INJD_MASK   BIT(2)
+
+#define ALTR_UE_TRIGGER_CHAR'U'   /* Trigger for UE */
+#define ALTR_TRIGGER_READ_WRD_CNT   32/* Line size x 4 */
+#define ALTR_TRIG_OCRAM_BYTE_SIZE   128   /* Line size x 4 */
+#define ALTR_TRIG_L2C_BYTE_SIZE 4096  /* Full Page */
+
+/*** EDAC Memory Controller Functions **

[PATCHv2 0/4] Add Altera Arria10 EDAC Support

[tthayer]

From: Thor Thayer 

This series of patches adds support for the Arria10 EDAC. The
SDRAM controller and ECC registers are significantly different
from the CycloneV/ArriaV but common areas could be abstracted.

Thor Thayer (4):
  edac, altera: Generalize driver to use DT Memory size
  edac, altera: Refactor EDAC for Altera CycloneV SoC.
  edac, altera: Addition of Arria10 EDAC
  arm: socfpga: dts: Arria10 SDRAM EDAC DTS additions.

 .../bindings/arm/altera/socfpga-sdram-edac.txt |2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi |   11 +
 drivers/edac/altera_edac.c |  364 
 drivers/edac/altera_edac.h |  201 +++
 4 files changed, 437 insertions(+), 141 deletions(-)
 create mode 100644 drivers/edac/altera_edac.h

-- 
1.7.9.5

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[PATCHv2 4/4] arm: socfpga: dts: Arria10 SDRAM EDAC DTS additions.

[tthayer]

From: Thor Thayer 

Support for the Arria10 SDRAM EDAC is added to the device tree.
Update the bindings document for the new match string.

Signed-off-by: Thor Thayer 
---
v2: Change subject description format.
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |2 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi |   11 +++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
index d0ce01d..f5ad0ff 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -2,7 +2,7 @@ Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
 The EDAC accesses a range of registers in the SDRAM controller.
 
 Required properties:
-- compatible : should contain "altr,sdram-edac";
+- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
 - altr,sdr-syscon : phandle of the sdr module
 - interrupts : Should contain the SDRAM ECC IRQ in the
appropriate format for the IRQ controller.
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index f5bebdd..4779b07 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -548,6 +548,17 @@
status = "disabled";
};
 
+   sdr: sdr@ffc25000 {
+   compatible = "syscon";
+   reg = <0xffcfb100 0x80>;
+   };
+
+   sdramedac {
+   compatible = "altr,sdram-edac-a10";
+   altr,sdr-syscon = <&sdr>;
+   interrupts = <0 2 4>, <0 0 4>;
+   };
+
L2: l2-cache@f000 {
compatible = "arm,pl310-cache";
reg = <0xf000 0x1000>;
-- 
1.7.9.5

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[PATCHv2 3/4] edac, altera: Addition of Arria10 EDAC

[tthayer]

From: Thor Thayer 

The Arria10 SDRAM and ECC system differs significantly from the
Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10
SoC.
1) IRQ handler needs to support SHARED IRQ
2) Support sberr and dberr address reporting.

Signed-off-by: Thor Thayer 
---
v2: Reposition a10_unmask_irq(). Use simple request_mem_region(), ioremap()
instead of devm versions. Make a10_data static.
---
 drivers/edac/altera_edac.c |  135 ++--
 drivers/edac/altera_edac.h |   85 
 2 files changed, 204 insertions(+), 16 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index a8350f6..bee475b 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -42,6 +42,7 @@ static const struct altr_sdram_prv_data c5_data = {
.ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
.ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
.ecc_saddr_offset   = CV_ERRADDR_OFST,
+   .ecc_daddr_offset   = CV_ERRADDR_OFST,
.ecc_cecnt_offset   = CV_SBECOUNT_OFST,
.ecc_uecnt_offset   = CV_DBECOUNT_OFST,
.ecc_irq_en_offset  = CV_DRAMINTR_OFST,
@@ -57,37 +58,62 @@ static const struct altr_sdram_prv_data c5_data = {
 #endif
 };
 
+static const struct altr_sdram_prv_data a10_data = {
+   .ecc_ctrl_offset= A10_ECCCTRL1_OFST,
+   .ecc_ctl_en_mask= A10_ECCCTRL1_ECC_EN,
+   .ecc_stat_offset= A10_INTSTAT_OFST,
+   .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
+   .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
+   .ecc_saddr_offset   = A10_SERRADDR_OFST,
+   .ecc_daddr_offset   = A10_DERRADDR_OFST,
+   .ecc_irq_en_offset  = A10_ERRINTEN_OFST,
+   .ecc_irq_en_mask= A10_ECC_IRQ_EN_MASK,
+   .ecc_irq_clr_offset = A10_INTSTAT_OFST,
+   .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
+   .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
+   .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
+#ifdef CONFIG_EDAC_DEBUG
+   .ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
+   .ce_set_mask= A10_DIAGINT_TSERRA_MASK,
+   .ue_set_mask= A10_DIAGINT_TDERRA_MASK,
+#endif
+};
+
 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
 {
struct mem_ctl_info *mci = dev_id;
struct altr_sdram_mc_data *drvdata = mci->pvt_info;
const struct altr_sdram_prv_data *priv = drvdata->data;
-   u32 status, err_count, err_addr;
-
-   /* Error Address is shared by both SBE & DBE */
-   regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);
+   u32 status, err_count = 1, err_addr;
 
regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
 
if (status & priv->ecc_stat_ue_mask) {
-   regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
-   &err_count);
+   regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
+   &err_addr);
+   if (priv->ecc_uecnt_offset)
+   regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
+   &err_count);
panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  err_count, err_addr);
}
if (status & priv->ecc_stat_ce_mask) {
-   regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
-   &err_count);
+   regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
+   &err_addr);
+   if (priv->ecc_uecnt_offset)
+   regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
+   &err_count);
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
 err_addr >> PAGE_SHIFT,
 err_addr & ~PAGE_MASK, 0,
 0, 0, -1, mci->ctl_name, "");
-   }
-
-   regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
-priv->ecc_irq_clr_mask);
+   /* Clear IRQ to resume */
+   regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
+priv->ecc_irq_clr_mask);
 
-   return IRQ_HANDLED;
+   return IRQ_HANDLED;
+   }
+   return IRQ_NONE;
 }
 
 #ifdef CONFIG_EDAC_DEBUG
@@ -203,10 +229,60 @@ static unsigned long get_total_mem(void)
 
 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
{ .compatible = "altr,sdram-edac", .data = (void *)&c5_data},
+   { .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data},
{},
 };
 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
 
+static int a10_init(struct regmap *mc_vbase)
+{
+   if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
+  A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
+   edac_printk(KERN_ERR, EDAC_M

[PATCHv2 2/4] edac, altera: Refactor EDAC for Altera CycloneV SoC.

[tthayer]

From: Thor Thayer 

The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits
for the CycloneV/ArriaV SoCs in preparation for the Arria10 support.

Signed-off-by: Thor Thayer 
---
v2: Make c5_data static.
---
 drivers/edac/altera_edac.c |  194 
 drivers/edac/altera_edac.h |  116 ++
 2 files changed, 206 insertions(+), 104 deletions(-)
 create mode 100644 drivers/edac/altera_edac.h

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index a9e7c69..a8350f6 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright Altera Corporation (C) 2014-2015. All rights reserved.
  *  Copyright 2011-2012 Calxeda, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -28,111 +28,64 @@
 #include 
 #include 
 
+#include "altera_edac.h"
 #include "edac_core.h"
 #include "edac_module.h"
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
 
-/* SDRAM Controller CtrlCfg Register */
-#define CTLCFG_OFST 0x00
-
-/* SDRAM Controller CtrlCfg Register Bit Masks */
-#define CTLCFG_ECC_EN   0x400
-#define CTLCFG_ECC_CORR_EN  0x800
-#define CTLCFG_GEN_SB_ERR   0x2000
-#define CTLCFG_GEN_DB_ERR   0x4000
-
-#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
-CTLCFG_ECC_CORR_EN)
-
-/* SDRAM Controller Address Width Register */
-#define DRAMADDRW_OFST  0x2C
-
-/* SDRAM Controller Address Widths Field Register */
-#define DRAMADDRW_COLBIT_MASK   0x001F
-#define DRAMADDRW_COLBIT_SHIFT  0
-#define DRAMADDRW_ROWBIT_MASK   0x03E0
-#define DRAMADDRW_ROWBIT_SHIFT  5
-#define DRAMADDRW_BANKBIT_MASK 0x1C00
-#define DRAMADDRW_BANKBIT_SHIFT 10
-#define DRAMADDRW_CSBIT_MASK   0xE000
-#define DRAMADDRW_CSBIT_SHIFT   13
-
-/* SDRAM Controller Interface Data Width Register */
-#define DRAMIFWIDTH_OFST0x30
-
-/* SDRAM Controller Interface Data Width Defines */
-#define DRAMIFWIDTH_16B_ECC 24
-#define DRAMIFWIDTH_32B_ECC 40
-
-/* SDRAM Controller DRAM Status Register */
-#define DRAMSTS_OFST0x38
-
-/* SDRAM Controller DRAM Status Register Bit Masks */
-#define DRAMSTS_SBEERR  0x04
-#define DRAMSTS_DBEERR  0x08
-#define DRAMSTS_CORR_DROP   0x10
-
-/* SDRAM Controller DRAM IRQ Register */
-#define DRAMINTR_OFST   0x3C
-
-/* SDRAM Controller DRAM IRQ Register Bit Masks */
-#define DRAMINTR_INTREN 0x01
-#define DRAMINTR_SBEMASK0x02
-#define DRAMINTR_DBEMASK0x04
-#define DRAMINTR_CORRDROPMASK   0x08
-#define DRAMINTR_INTRCLR0x10
-
-/* SDRAM Controller Single Bit Error Count Register */
-#define SBECOUNT_OFST   0x40
-
-/* SDRAM Controller Single Bit Error Count Register Bit Masks */
-#define SBECOUNT_MASK   0x0F
-
-/* SDRAM Controller Double Bit Error Count Register */
-#define DBECOUNT_OFST   0x44
-
-/* SDRAM Controller Double Bit Error Count Register Bit Masks */
-#define DBECOUNT_MASK   0x0F
-
-/* SDRAM Controller ECC Error Address Register */
-#define ERRADDR_OFST0x48
-
-/* SDRAM Controller ECC Error Address Register Bit Masks */
-#define ERRADDR_MASK0x
-
-/* Altera SDRAM Memory Controller data */
-struct altr_sdram_mc_data {
-   struct regmap *mc_vbase;
+static const struct altr_sdram_prv_data c5_data = {
+   .ecc_ctrl_offset= CV_CTLCFG_OFST,
+   .ecc_ctl_en_mask= CV_CTLCFG_ECC_AUTO_EN,
+   .ecc_stat_offset= CV_DRAMSTS_OFST,
+   .ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
+   .ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
+   .ecc_saddr_offset   = CV_ERRADDR_OFST,
+   .ecc_cecnt_offset   = CV_SBECOUNT_OFST,
+   .ecc_uecnt_offset   = CV_DBECOUNT_OFST,
+   .ecc_irq_en_offset  = CV_DRAMINTR_OFST,
+   .ecc_irq_en_mask= CV_DRAMINTR_INTREN,
+   .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
+   .ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
+   .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
+   .ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
+#ifdef CONFIG_EDAC_DEBUG
+   .ce_ue_trgr_offset  = CV_CTLCFG_OFST,
+   .ce_set_mask= CV_CTLCFG_GEN_SB_ERR,
+   .ue_set_mask= CV_CTLCFG_GEN_DB_ERR,
+#endif
 };
 
 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
 {
struct mem_ctl_info *mci = dev_id;
struct altr_sdram_mc_data *drvdata = mci->pvt_info;
+   const struct altr_sdram_prv_data *priv = drvdata->data;
u32 status, err_count, err_addr;
 
/* Error Address is shared by both SBE & DBE */
-   regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr);
+   regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, &err_addr);
 
-   regmap_read(drvdata->mc_vbase,

[PATCHv2 1/4] edac, altera: Generalize driver to use DT Memory size

[tthayer]

From: Thor Thayer 

The Arria10 SOC uses a completely different SDRAM controller from the
earlier CycloneV and ArriaV SoCs. The memory size is calculated in
the bootloader and passed via the device tree. Using this device
tree size is more generic than using the register fields to
calculate the memory size for different SDRAM controllers.

Signed-off-by: Thor Thayer 
---
v2: Use edac_dbg() for memory size print. Use loop for DT memory.
---
 drivers/edac/altera_edac.c |   55 
 1 file changed, 25 insertions(+), 30 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 806b63b..a9e7c69 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -219,36 +219,31 @@ static void altr_sdr_mc_create_debugfs_nodes(struct 
mem_ctl_info *mci)
 {}
 #endif
 
-/* Get total memory size in bytes */
-static u32 altr_sdram_get_total_mem_size(struct regmap *mc_vbase)
+/* Get total memory size from Open Firmware DTB */
+static unsigned long get_total_mem(void)
 {
-   u32 size, read_reg, row, bank, col, cs, width;
-
-   if (regmap_read(mc_vbase, DRAMADDRW_OFST, &read_reg) < 0)
-   return 0;
-
-   if (regmap_read(mc_vbase, DRAMIFWIDTH_OFST, &width) < 0)
-   return 0;
-
-   col = (read_reg & DRAMADDRW_COLBIT_MASK) >>
-   DRAMADDRW_COLBIT_SHIFT;
-   row = (read_reg & DRAMADDRW_ROWBIT_MASK) >>
-   DRAMADDRW_ROWBIT_SHIFT;
-   bank = (read_reg & DRAMADDRW_BANKBIT_MASK) >>
-   DRAMADDRW_BANKBIT_SHIFT;
-   cs = (read_reg & DRAMADDRW_CSBIT_MASK) >>
-   DRAMADDRW_CSBIT_SHIFT;
-
-   /* Correct for ECC as its not addressible */
-   if (width == DRAMIFWIDTH_32B_ECC)
-   width = 32;
-   if (width == DRAMIFWIDTH_16B_ECC)
-   width = 16;
-
-   /* calculate the SDRAM size base on this info */
-   size = 1 << (row + bank + col);
-   size = size * cs * (width / 8);
-   return size;
+   struct device_node *np = NULL;
+   const unsigned int *reg, *reg_end;
+   int len, sw, aw;
+   unsigned long start, size, total_mem = 0;
+
+   for_each_node_by_type(np, "memory") {
+   aw = of_n_addr_cells(np);
+   sw = of_n_size_cells(np);
+   reg = (const unsigned int *)of_get_property(np, "reg", &len);
+   reg_end = reg + (len / sizeof(u32));
+
+   total_mem = 0;
+   do {
+   start = of_read_number(reg, aw);
+   reg += aw;
+   size = of_read_number(reg, sw);
+   reg += sw;
+   total_mem += size;
+   } while (reg < reg_end);
+   }
+   edac_dbg(0, "total_mem 0x%lx\n", total_mem);
+   return total_mem;
 }
 
 static int altr_sdram_probe(struct platform_device *pdev)
@@ -280,7 +275,7 @@ static int altr_sdram_probe(struct platform_device *pdev)
}
 
/* Grab memory size from device tree. */
-   mem_size = altr_sdram_get_total_mem_size(mc_vbase);
+   mem_size = get_total_mem();
if (!mem_size) {
edac_printk(KERN_ERR, EDAC_MC,
"Unable to calculate memory size\n");
-- 
1.7.9.5

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[PATCH 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   12 
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..9348c53
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdr-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6ce912e..a0ea69b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -681,6 +681,11 @@
reg = <0xffc25000 0x1000>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   14 ++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..525cb76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+Note that syscon is invoked for this device to support the FPGA
+   bridge driver, EDAC driver and other devices that share the
+   registers.
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

[tthayer]

From: Thor Thayer 

Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
  these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC framework
  is discovered from the memory node of the device tree.
- Documentation of the bindings in devicetree/bindings/arm/altera/
  socfpga-sdram-edac.txt
- Correction of single bit errors, detection of double bit errors.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Doug Thompson 
To: Grant Likely 
Cc: Dinh Nguyen 
Cc: devicet...@vger.kernel.org
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/edac/Kconfig  |9 ++
 drivers/edac/Makefile |2 +
 drivers/edac/altera_mc_edac.c |  360 +
 3 files changed, 371 insertions(+)
 create mode 100644 drivers/edac/altera_mc_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..e15d05f 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_mc_edac.o
diff --git a/drivers/edac/altera_mc_edac.c b/drivers/edac/altera_mc_edac.c
new file mode 100644
index 000..7d15196
--- /dev/null
+++ b/drivers/edac/altera_mc_edac.c
@@ -0,0 +1,360 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define ALTR_EDAC_MOD_STR  "altera_edac"
+
+/* SDRAM Controller CtrlCfg Register */
+#define ALTR_SDR_CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define ALTR_SDR_CTLCFG_ECC_EN  0x400
+#define ALTR_SDR_CTLCFG_ECC_CORR_EN 0x800
+#define ALTR_SDR_CTLCFG_GEN_SB_ERR  0x2000
+#define ALTR_SDR_CTLCFG_GEN_DB_ERR  0x4000
+
+#define ALTR_SDR_CTLCFG_ECC_AUTO_EN (ALTR_SDR_CTLCFG_ECC_EN | \
+   ALTR_SDR_CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller DRAM Status Register */
+#define ALTR_SDR_DRAMSTS0x38
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define ALTR_SDR_DRAMSTS_SBEERR 0x04
+#define ALTR_SDR_DRAMSTS_DBEERR 0x08
+#define ALTR_SDR_DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define ALTR_SDR_DRAMINTR0x3C
+
+/* SDRAM Controller DRAM IRQ Register Bit Masks */
+#define ALTR_SDR_DRAMINTR_INTREN0x01
+#define ALTR_SDR_DRAMINTR_SBEMASK   0x02
+#define ALTR_SDR_DRAMINTR_DBEMASK   0x04
+#define ALTR_SDR_DRAMINTR_CORRDROPMASK  0x08
+#define ALTR_SDR_DRAMINTR_INTRCLR   0x10
+
+/* SDRAM Controller Single Bit Error Count Register */
+#define ALTR_SDR_SBECOUNT   0x40
+
+/* SDRAM Controller Single Bit Error Count Register Bit Masks */
+#define ALTR_SDR_SBECOUNT_COUNT 0x0F
+
+/* SDRAM Controller Double Bit Error Count Register */
+#define ALTR_SDR_DBECOUNT   0x44
+
+/* SDRAM Controller Double Bit Error Count Register Bit Masks */
+#define ALTR_SDR_DBECOUNT_COUNT 0x0F
+
+/* SDRAM Controller ECC Error Address Register */
+#define ALTR_SDR_ERRADDR0x48
+
+/* SDRAM Controller ECC Error Address Register Bit Masks */
+#define ALTR_SDR_ERRADDR_ADDR   

[PATCHv9 0/3] Addition of Altera EDAC support.

[tthayer]

From: Thor Thayer 

The Altera SDRAM controller and EDAC support are added in this
patch series. The SDRAM controller is an MFD so that multiple
drivers can access it's registers.

Thor Thayer (3):
  mfd: altera: Add Altera SDRAM Controller
  edac: altera: Add Altera EDAC support.
  arm: dts: Add Altera SDRAM controller bindings

 .../devicetree/bindings/arm/altera/socfpga-sdr.txt |   13 +
 MAINTAINERS|6 +
 arch/arm/boot/dts/socfpga.dtsi |   10 +
 drivers/edac/Kconfig   |   10 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  293 
 drivers/mfd/Kconfig|7 +
 drivers/mfd/Makefile   |1 +
 drivers/mfd/altera-sdr.c   |  162 +++
 include/linux/mfd/altera-sdr.h |  102 +++
 10 files changed, 606 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdr.txt
 create mode 100644 drivers/edac/altera_edac.c
 create mode 100644 drivers/mfd/altera-sdr.c
 create mode 100644 include/linux/mfd/altera-sdr.h

-- 
1.7.9.5

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[PATCHv9 1/3] mfd: altera: Add Altera SDRAM Controller

[tthayer]

From: Thor Thayer 

Add a simple MFD for the Altera SDRAM Controller.

Signed-off-by: Alan Tull 
Signed-off-by: Thor Thayer 
---
v1-8: The MFD implementation was not included in the original series.

v9: New MFD implementation.
---
 MAINTAINERS|5 ++
 drivers/mfd/Kconfig|7 ++
 drivers/mfd/Makefile   |1 +
 drivers/mfd/altera-sdr.c   |  162 
 include/linux/mfd/altera-sdr.h |  102 +
 5 files changed, 277 insertions(+)
 create mode 100644 drivers/mfd/altera-sdr.c
 create mode 100644 include/linux/mfd/altera-sdr.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 86efa7e..48a8923 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1340,6 +1340,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA SDRAM CONTROLLER SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/mfd/altera-sdr.c
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Maxime Coquelin 
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6cc4b6a..8ce4961 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -719,6 +719,13 @@ config MFD_STMPE
Keypad: stmpe-keypad
Touchscreen: stmpe-ts
 
+config MFD_ALTERA_SDR
+   bool "Altera SDRAM Controller MFD"
+   depends on ARCH_SOCFPGA
+   select MFD_CORE
+   help
+ Support for Altera SDRAM Controller (SDR) MFD.
+
 menu "STMicroelectronics STMPE Interface Drivers"
 depends on MFD_STMPE
 
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8afedba..24cc2b7 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -169,3 +169,4 @@ obj-$(CONFIG_MFD_AS3711)+= as3711.o
 obj-$(CONFIG_MFD_AS3722)   += as3722.o
 obj-$(CONFIG_MFD_STW481X)  += stw481x.o
 obj-$(CONFIG_MFD_IPAQ_MICRO)   += ipaq-micro.o
+obj-$(CONFIG_MFD_ALTERA_SDR)   += altera-sdr.o
diff --git a/drivers/mfd/altera-sdr.c b/drivers/mfd/altera-sdr.c
new file mode 100644
index 000..b5c6646
--- /dev/null
+++ b/drivers/mfd/altera-sdr.c
@@ -0,0 +1,162 @@
+/*
+ * SDRAM Controller (SDR) MFD
+ *
+ * Copyright (C) 2014 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct mfd_cell altera_sdr_devs[] = {
+#if defined(CONFIG_EDAC_ALTERA_MC)
+   {
+   .name = "altr_sdram_edac",
+   .of_compatible = "altr,sdram-edac",
+   },
+#endif
+};
+
+u32 altera_sdr_readl(struct altera_sdr *sdr, u32 reg_offset)
+{
+   return readl(sdr->reg_base + reg_offset);
+}
+EXPORT_SYMBOL_GPL(altera_sdr_readl);
+
+void altera_sdr_writel(struct altera_sdr *sdr, u32 reg_offset, u32 value)
+{
+   writel(value, sdr->reg_base + reg_offset);
+}
+EXPORT_SYMBOL_GPL(altera_sdr_writel);
+
+/* Get total memory size in bytes */
+u32 altera_sdr_mem_size(struct altera_sdr *sdr)
+{
+   u32 size;
+   u32 read_reg, row, bank, col, cs, width;
+
+   read_reg = altera_sdr_readl(sdr, SDR_DRAMADDRW_OFST);
+   if (read_reg < 0)
+   return 0;
+
+   width = altera_sdr_readl(sdr, SDR_DRAMIFWIDTH_OFST);
+   if (width < 0)
+   return 0;
+
+   col = (read_reg & SDR_DRAMADDRW_COLBITS_MASK) >>
+   SDR_DRAMADDRW_COLBITS_LSB;
+   row = (read_reg & SDR_DRAMADDRW_ROWBITS_MASK) >>
+   SDR_DRAMADDRW_ROWBITS_LSB;
+   bank = (read_reg & SDR_DRAMADDRW_BANKBITS_MASK) >>
+   SDR_DRAMADDRW_BANKBITS_LSB;
+   cs = (read_reg & SDR_DRAMADDRW_CSBITS_MASK) >>
+   SDR_DRAMADDRW_CSBITS_LSB;
+
+   /* Correct for ECC as its not addressible */
+   if (width == SDR_DRAMIFWIDTH_32B_ECC)
+   width = 32;
+   if (width == SDR_DRAMIFWIDTH_16B_ECC)
+   width = 16;
+
+   /* calculate the SDRAM size base on this info */
+   size = 1 << (row + bank + col);
+   size = size * cs * (width / 8);
+   return size;
+}
+EXPORT_SYMBOL_GPL(altera_sdr_mem_size);
+
+static int altera_sdr_probe(struct platform_device *pdev)
+{
+   struct device *dev = &pdev->dev;
+   struct altera_sdr *sdr;
+   struct resource *res;
+   void __iomem *base;
+   int ret;
+
+   sdr = devm_kzalloc(dev, sizeof(*sdr), GFP_KERNEL);
+   if (!sdr)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_ME

[PATCHv9 3/3] arm: dts: Add Altera SDRAM controller bindings

[tthayer]

From: Thor Thayer 

Add the Altera SDRAM controller bindings and device tree changes to the Altera 
SoC project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

v7: No change. Bump for consistency.

v8: No change. Bump for consistency.

v9: Changes to support a MFD SDRAM controller with nested EDAC.
---
 .../devicetree/bindings/arm/altera/socfpga-sdr.txt |   13 +
 arch/arm/boot/dts/socfpga.dtsi |   10 ++
 2 files changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdr.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdr.txt
new file mode 100644
index 000..2bb1ddf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdr.txt
@@ -0,0 +1,13 @@
+Altera SOCFPGA SDRAM Controller
+The SDRAM controller is implemented as a MFD so various drivers may
+nest under this main SDRAM controller binding.
+
+Required properties:
+- compatible : "altr,sdr";
+- reg : Should contain 1 register range(address and length)
+
+Example:
+   sdr@0xffc25000 {
+   compatible = "altr,sdr";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..ecb306d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -603,6 +603,16 @@
};
};
 
+   sdr@0xffc25000 {
+   compatible = "altr,sdr";
+   reg = <0xffc25000 0x1000>;
+
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+   };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
-- 
1.7.9.5

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[PATCHv9 2/3] edac: altera: Add Altera EDAC support.

[tthayer]

From: Thor Thayer 

This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.

Signed-off-by: Thor Thayer 
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

v7: No changes. Bump for consistency.

v8: Alphabetize headers.

v9: Move Altera EDAC driver to use SDRAM MFD device since controller
registers are shared between different drivers.
---
 MAINTAINERS|1 +
 drivers/edac/Kconfig   |   10 ++
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  293 
 4 files changed, 306 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 48a8923..7fde28b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1344,6 +1344,7 @@ ARM/SOCFPGA SDRAM CONTROLLER SUPPORT
 M: Thor Thayer 
 S: Maintained
 F: drivers/mfd/altera-sdr.c
+F: drivers/edac/altera_edac.c
 
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..429e244 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,14 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   select MFD_ALTERA_SDR
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..70845c4 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..602ae62
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,293 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ * Adapted from the highbank_mc_edac driver.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* Altera SDRAM Memory Controller data */
+struct altr_sdram_mc_data {
+   struct altera_sdr *sdr;
+};
+
+static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
+{
+   struct mem_ctl_info *mci = dev_id;
+   struct altr_sdram_mc_data *drvdata = mci->pvt_info;
+   u32 status, err_count, err_addr;
+
+   /* Error Address is shared by both SBE & DBE */
+   err_addr = altera_sdr_readl(drvdata->sdr, SDR_ERRADDR_OFST);
+   status = altera_sdr_readl(drvdata->sdr, SDR_DRAMSTS_OFST);
+
+   if (status & SDR_DRAMSTS_DBEERR) {
+   err_count = altera_sdr_readl(drvdata->sdr, SDR_DBECOUNT_OFST);
+   panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
+ err_count, err_addr);
+   }
+   if (status & SDR_DRAMSTS_SBEERR) {
+   err_count = altera_sdr_readl(drvdata->sdr, SDR_SBECOUNT_OFST);
+   edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
+err_addr >> PAGE_SHIFT,
+err_addr & ~PAGE_MASK, 0,
+ 

Add EDAC support for Altera SoC SDRAM Controller

[tthayer]

[PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv5 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
--
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[PATCHv5 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.

v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4,v5: No changes - bump version for consistency.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   12 
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..431e98b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6ce912e..a0ea69b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -681,6 +681,11 @@
reg = <0xffc25000 0x1000>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

--
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[PATCHv5 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller

[tthayer]

From: Thor Thayer 

v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

Signed-off-by: Thor Thayer 
---
 MAINTAINERS|5 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  419 
 4 files changed, 435 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index e67ea24..ecd1277 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1290,6 +1290,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA SDRAM EDAC SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/edac/altera_edac.c
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Maxime Coquelin 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..39d3dd4
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,419 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  0x2C
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH0x30
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS0x38
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   0x3C
+
+/* SDRAM Controller DRAM IRQ Register Bit Masks */
+#define DRAMINTR_INTREN0x01
+#define DRAMINT

[PATCHv5 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.

v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..8f8746b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv4 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller

[tthayer]

From: Thor Thayer 

This patch adds EDAC support for reporting ECC errors of CycloneV 
and ArriaV SDRAM controllers. 
- The SDRAM Controller registers are shared with the FPGA bridge so   
  these are accessed through the syscon interface. 
- The configuration of the SDRAM memory size for the EDAC framework
  is discovered from the SDRAM Controller registers. 
- Documentation of the bindings in devicetree/bindings/arm/altera/
  socfpga-sdram-edac.txt
- Correction & reporting of single bit errors, panic on double bit
  errors.

v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

Signed-off-by: Thor Thayer 
---
 MAINTAINERS|5 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  416 
 4 files changed, 432 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index e67ea24..ecd1277 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1290,6 +1290,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA SDRAM EDAC SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/edac/altera_edac.c
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Maxime Coquelin 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..3f6e23b
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,416 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  0x2C
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH0x30
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Contro

[PATCHv4 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.

v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..8f8746b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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Please read the FAQ at  http://www.tux.org/lkml/

[PATCHv4 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.

v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4: No changes - bump version for consistency.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   12 
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..431e98b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6ce912e..a0ea69b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -681,6 +681,11 @@
reg = <0xffc25000 0x1000>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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Addition of EDAC for Altera SoC SDRAM Controller

[tthayer]

[PATCHv4 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv4 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv4 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller 
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More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCHv2 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.

---
v2: Update the mailing list to include the EDAC mailing list.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
To: Doug Thompson 
To: Grant Likely 
Cc: Borislav Petkov 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   12 
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..9348c53
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdr-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6ce912e..a0ea69b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -681,6 +681,11 @@
reg = <0xffc25000 0x1000>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Please read the FAQ at  http://www.tux.org/lkml/

[PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

[tthayer]

From: Thor Thayer 

Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
  these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC framework
  is discovered from the SDRAM Controller registers.
- Documentation of the bindings in devicetree/bindings/arm/altera/
  socfpga-sdram-edac.txt
- Correction of single bit errors, detection of double bit errors.

---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer 
information.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Doug Thompson 
To: Grant Likely 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
Cc: Borislav Petkov 
Cc: devicet...@vger.kernel.org
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 MAINTAINERS   |5 +
 drivers/edac/Kconfig  |9 +
 drivers/edac/Makefile |2 +
 drivers/edac/altera_mc_edac.c |  393 +
 4 files changed, 409 insertions(+)
 create mode 100644 drivers/edac/altera_mc_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index b8af16d..aee0746 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1249,6 +1249,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA SDRAM EDAC SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/edac/altera_mc_edac.c
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Stuart Menefy 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..e15d05f 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_mc_edac.o
diff --git a/drivers/edac/altera_mc_edac.c b/drivers/edac/altera_mc_edac.c
new file mode 100644
index 000..811b712
--- /dev/null
+++ b/drivers/edac/altera_mc_edac.c
@@ -0,0 +1,393 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define ALTR_EDAC_MOD_STR  "altera_edac"
+
+/* SDRAM Controller CtrlCfg Register */
+#define ALTR_SDR_CTLCFG0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define ALTR_SDR_CTLCFG_ECC_EN 0x400
+#define ALTR_SDR_CTLCFG_ECC_CORR_EN0x800
+#define ALTR_SDR_CTLCFG_GEN_SB_ERR 0x2000
+#define ALTR_SDR_CTLCFG_GEN_DB_ERR 0x4000
+
+#define ALTR_SDR_CTLCFG_ECC_AUTO_EN(ALTR_SDR_CTLCFG_ECC_EN | \
+   ALTR_SDR_CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller Address Width Register */
+#define ALTR_SDR_DRAMADDRW 0x2C
+
+/* SDRAM Controller Address Widths Field Register */
+#define ALTR_SDR_DRAMADDRW_COLBIT_MASK 0x001F
+#define ALTR_SDR_DRAMADDRW_COLBIT_LSB  0
+#define ALTR_SDR_DRAMADDRW_ROWBIT_MASK 0x03E0
+#define ALTR_SDR_DRAMADDRW_ROWBIT_LSB  5
+#define ALTR_SDR_DRAMADDRW_BANKBIT_MASK0x1C00
+#define ALTR_SDR_DRAMADDRW_BANKBIT_LSB 10
+#define ALTR_SDR_DRAMADDRW_CSBIT_MASK  0xE000
+#define ALTR_SDR_DRAMADDRW_CSBIT_LSB   13
+
+/* SDRAM Controller Interface Data Width Register */
+#define ALTR_SDR_DRAMIFWIDT

[PATCHv2 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.

---
v2: Update the mailing list to include the EDAC mailing list.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
To: Doug Thompson 
To: Grant Likely 
Cc: Borislav Petkov 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-e...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   14 ++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..525cb76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+Note that syscon is invoked for this device to support the FPGA
+   bridge driver, EDAC driver and other devices that share the
+   registers.
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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Add EDAC support for Altera SDRAM Controller

[tthayer]

[PATCHv6 1/3] dt: bindings: Addition of the Altera SDRAM controller
[PATCHv6 2/3] dt: bindings: Addition of the Altera SDRAM EDAC 
[PATCHv6 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM
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[PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller

[tthayer]

From: Thor Thayer 

v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..5027026
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..310292e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -682,6 +682,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv6 0/3] Addition of Altera SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller to the EDAC driver.

Thor Thayer (3):
  Addition of the Altera SDRAM controller bindings and device tree
changes to the Altera SoC project.
  Addition of the Altera SDRAM EDAC bindings and device tree
changes to the Altera SoC project.
  edac: altera: Add EDAC support for Altera SoC SDRAM Controller.
This patch adds support for the CycloneV and ArriaV SDRAM
controllers. Correction and reporting of SBEs, Panic on DBEs.

 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +
 arch/arm/boot/dts/socfpga.dtsi |   11 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  448 
 6 files changed, 496 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
 create mode 100644 drivers/edac/altera_edac.c

-- 
1.7.9.5

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[PATCHv6 2/3] devicetree: Addition of the Altera SDRAM EDAC

[tthayer]

From: Thor Thayer 

v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4,v5: No changes - bump version for consistency.

v6: Assign ECC registers in SDRAM controller to EDAC

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +++
 arch/arm/boot/dts/socfpga.dtsi |6 ++
 2 files changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..540c9cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- reg : should contain the ECC register range in sdram
+controller (address and length).
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502C 0x28>;
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 310292e..fe9832e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,12 @@
reg = <0xffc25000 0x4>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502C 0x28>;
+   interrupts = <0 39 4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv6 3/3] edac: altera: Add EDAC support for SDRAM Ctlr

[tthayer]

From: Thor Thayer 

v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

Signed-off-by: Thor Thayer 
---
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  448 
 3 files changed, 459 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..e3fcd27
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,448 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller ECC Register Offset */
+#define ECC_REG_OFFSET 0x2C
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  (0x2C-ECC_REG_OFFSET)
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH(0x30-ECC_REG_OFFSET)
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS(0x38-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   (0x3C-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM IRQ Register Bit Masks */
+#define DRAMINTR_INTREN0x01
+#define DRAMINTR_SBEMASK   0x02
+#define DRAMINTR_DBEMASK   0x04
+#define DRAMINTR_CORRDROPMASK  0x08
+#define DRAMI

[PATCHv6 2/3] devicetree: Addition of the Altera SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device tree changes

v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4,v5: No changes - bump version for consistency.

v6: Assign ECC registers in SDRAM controller to EDAC

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +++
 arch/arm/boot/dts/socfpga.dtsi |6 ++
 2 files changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..540c9cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- reg : should contain the ECC register range in sdram
+controller (address and length).
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502C 0x28>;
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 310292e..fe9832e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,12 @@
reg = <0xffc25000 0x4>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502C 0x28>;
+   interrupts = <0 39 4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv6 3/3] edac: altera: Add EDAC support for SDRAM Ctlr

[tthayer]

From: Thor Thayer 

Addition of the driver to support the Altera SDRAM Controller. 
This patch adds support for the CycloneV and ArriaV SDRAM controllers. 
Correction and reporting of SBEs, Panic on DBEs.

v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

Signed-off-by: Thor Thayer 
---
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  448 
 3 files changed, 459 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..e3fcd27
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,448 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller ECC Register Offset */
+#define ECC_REG_OFFSET 0x2C
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  (0x2C-ECC_REG_OFFSET)
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH(0x30-ECC_REG_OFFSET)
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS(0x38-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   (0x3C-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM IRQ Regist

[PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM Controller bindings and device tree changes.

v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..5027026
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..310292e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -682,6 +682,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv8 3/3] edac: altera: Add Altera SDRAM Controller EDAC support.

[tthayer]

From: Thor Thayer 

This patch adds support for the CycloneV and ArriaV SDRAM controllers. 
Correction and reporting of SBEs, Panic on DBEs.

Signed-off-by: Thor Thayer 
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

v7: No changes. Bump for consistency.

v8: Alphabetize headers.
---
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  449 
 3 files changed, 460 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..73254f9
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,449 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller ECC Register Offset */
+#define ECC_REG_OFFSET 0x2C
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  (0x2C-ECC_REG_OFFSET)
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH(0x30-ECC_REG_OFFSET)
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS(0x38-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   (0x3C-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM IRQ 

[PATCHv8 0/3] Addition of Altera SDRAM Controller

[tthayer]

From: Thor Thayer 

Thor Thayer (3):
  devicetree: Addition of the Altera SDRAM Controller. Add the
Altera SDRAM controller bindings and device tree changes to the
Altera SoC project.
  devicetree: Addition of the Altera SDRAM EDAC. Add the Altera
SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
  edac: altera: Add EDAC support for Altera SoC SDRAM Controller.
This patch adds support for the CycloneV and ArriaV SDRAM
controllers. Correction and reporting of SBEs, Panic on DBEs.

 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +
 arch/arm/boot/dts/socfpga.dtsi |   11 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  449 
 6 files changed, 497 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
 create mode 100644 drivers/edac/altera_edac.c

-- 
1.7.9.5

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[PATCHv8 2/3] devicetree: Addition of the Altera SDRAM EDAC. Add the

[tthayer]

From: Thor Thayer 

Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4,v5: No changes - bump version for consistency.

v6: Assign ECC registers in SDRAM controller to EDAC

v7: Fix SDRAM EDAC base address.

v8: No change. Bump version for consistency.
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +++
 arch/arm/boot/dts/socfpga.dtsi |6 ++
 2 files changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..d68e033
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- reg : should contain the ECC register range in sdram
+controller (address and length).
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@ffc2502c {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502c 0x28>;
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 310292e..da0785d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,12 @@
reg = <0xffc25000 0x4>;
};
 
+   sdramedac@ffc2502c {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502c 0x28>;
+   interrupts = <0 39 4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv8 1/3] devicetree: Addition of the Altera SDRAM Controller.

[tthayer]

From: Thor Thayer 

Add the Altera SDRAM controller bindings and device tree changes to the Altera 
SoC project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

v7: No change. Bump for consistency.

v8: No change. Bump for consistency.
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..5027026
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..310292e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -682,6 +682,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv2] net: c_can: Add support for D_CAN Module RAM Init

[tthayer]

From: Thor Thayer 

The D_CAN driver was written to support the TI D_CAN implementation
which placed the D_CAN RAM reset in a separate register. In the
standard D_CAN module the RAM Init is in the D_CAN module so
handle the RAM Init differently.
This patch has only been tested on the standard D_CAN module (but not
on the TI D_CAN module).

Signed-off-by: Thor Thayer 
---
Changes in v2:
-Rename raminit_type_flag to raminit_type
-New constants for raminit_type
---
---
 drivers/net/can/c_can/c_can.h  |3 ++
 drivers/net/can/c_can/c_can_platform.c |   51 +---
 2 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
index faa8404..73c6c88 100644
--- a/drivers/net/can/c_can/c_can.h
+++ b/drivers/net/can/c_can/c_can.h
@@ -88,6 +88,7 @@ enum reg {
C_CAN_INTPND2_REG,
C_CAN_MSGVAL1_REG,
C_CAN_MSGVAL2_REG,
+   C_CAN_FUNCTION_REG,
 };
 
 static const u16 reg_map_c_can[] = {
@@ -139,6 +140,7 @@ static const u16 reg_map_d_can[] = {
[C_CAN_BRPEXT_REG]  = 0x0E,
[C_CAN_INT_REG] = 0x10,
[C_CAN_TEST_REG]= 0x14,
+   [C_CAN_FUNCTION_REG]= 0x18,
[C_CAN_TXRQST1_REG] = 0x88,
[C_CAN_TXRQST2_REG] = 0x8A,
[C_CAN_NEWDAT1_REG] = 0x9C,
@@ -201,6 +203,7 @@ struct c_can_priv {
unsigned int instance;
void (*raminit) (const struct c_can_priv *priv, bool enable);
u32 dlc[C_CAN_MSG_OBJ_TX_NUM];
+   u32 raminit_type;
 };
 
 struct net_device *alloc_c_can_dev(void);
diff --git a/drivers/net/can/c_can/c_can_platform.c 
b/drivers/net/can/c_can/c_can_platform.c
index 806d927..af3366f 100644
--- a/drivers/net/can/c_can/c_can_platform.c
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -41,6 +41,14 @@
 #define CAN_RAMINIT_DONE_MASK(i)   (0x100 << (i))
 #define CAN_RAMINIT_ALL_MASK(i)(0x101 << (i))
 static DEFINE_SPINLOCK(raminit_lock);
+#define DCAN_RAM_INIT_BIT  (1 << 3)
+struct c_can_ram_init_masks {
+   u32 start;
+   u32 done;
+   u32 all;
+};
+#define CAN_RAMINIT_TYPE_STANDARD  0
+#define CAN_RAMINIT_TYPE_TI1
 /*
  * 16-bit c_can registers can be arranged differently in the memory
  * architecture of different implementations. For example: 16-bit
@@ -82,9 +90,19 @@ static void c_can_hw_raminit_wait(const struct c_can_priv 
*priv, u32 mask,
 
 static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
 {
-   u32 mask = CAN_RAMINIT_ALL_MASK(priv->instance);
+   struct c_can_ram_init_masks ram_init_masks;
u32 ctrl;
 
+   if (priv->raminit_type == CAN_RAMINIT_TYPE_TI) {
+   ram_init_masks.start = CAN_RAMINIT_START_MASK(priv->instance);
+   ram_init_masks.done = CAN_RAMINIT_DONE_MASK(priv->instance);
+   ram_init_masks.all = CAN_RAMINIT_ALL_MASK(priv->instance);
+   } else {
+   ram_init_masks.start = DCAN_RAM_INIT_BIT;
+   ram_init_masks.done = 0;
+   ram_init_masks.all = 0;
+   }
+
spin_lock(&raminit_lock);
 
ctrl = readl(priv->raminit_ctrlreg);
@@ -92,18 +110,18 @@ static void c_can_hw_raminit(const struct c_can_priv 
*priv, bool enable)
 * looking at the 0 -> transition, but is not self clearing;
 * And we clear the init done bit as well.
 */
-   ctrl &= ~CAN_RAMINIT_START_MASK(priv->instance);
-   ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
+   ctrl &= ~ram_init_masks.start;
+   ctrl |= ram_init_masks.done;
writel(ctrl, priv->raminit_ctrlreg);
-   ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-   c_can_hw_raminit_wait(priv, ctrl, mask);
+   ctrl &= ~ram_init_masks.done;
+   c_can_hw_raminit_wait(priv, ctrl, ram_init_masks.all);
 
if (enable) {
/* Set start bit and wait for the done bit. */
-   ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
+   ctrl |= ram_init_masks.start;
writel(ctrl, priv->raminit_ctrlreg);
-   ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-   c_can_hw_raminit_wait(priv, ctrl, mask);
+   ctrl |= ram_init_masks.done;
+   c_can_hw_raminit_wait(priv, ctrl, ram_init_masks.all);
}
spin_unlock(&raminit_lock);
 }
@@ -221,11 +239,24 @@ static int c_can_plat_probe(struct platform_device *pdev)
priv->instance = pdev->id;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+   /* Not all D_CAN module have a separate register for the D_CAN
+* RAM initialization. Use default RAM init bit in D_CAN module
+* if not specified in DT.
+*/
+   if (!res) {
+   priv->raminit = c_can_hw_raminit;
+   priv->raminit_type = CAN_RAMINIT_TYPE_STANDARD;
+ 

[PATCHv2] Add support for standard D_CAN module RAM Init Bit

[tthayer]

The standard D_CAN module includes the RAM Init bit in one of the 
D_CAN registers. This patch will properly initialize the RAM Init
bit which is self-clearing when the RAM Init is complete.
This patch fixes a boot message reporting an invalid resource as
well as the message saying control memory is not used for raminit.

[PATCHv2] net: c_can: Add support for D_CAN RAM Init bit in D_CAN

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[PATCH 1/2] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   14 ++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..351ab7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+Note that syscon is invoked for this device to support the FPGA
+   bridge driver and possibly other devices in the future.  See
+   also Documentation/devicetree/bindings/mfd/syscon.txt
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@0xffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9e78c1d..3634de7 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -528,6 +528,11 @@
reg-io-width = <4>;
};
 
+   sdrctl@0xffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCH 2/2] arm: socfpga: Add support for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller registers to the
Altera SoC project. These registers are shared by future
drivers such as ECC and the FPGA bridge.

Signed-off-by: Thor Thayer 
To: Rob Herring 
To: Pawel Moll 
To: Mark Rutland 
To: Ian Campbell 
To: Kumar Gala 
To: Rob Landley 
To: Russell King 
To: Dinh Nguyen 
Cc: devicet...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
---
 arch/arm/mach-socfpga/socfpga.c |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 21d6026..d514e8a 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -32,6 +32,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem 
*)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+void __iomem *sdr_ctl_base_addr;
 void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
@@ -150,6 +151,15 @@ void __init socfpga_sysmgr_init(void)
 
np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_base_addr = of_iomap(np, 0);
+
+   np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find sdr-ctl\n");
+   return;
+   }
+
+   sdr_ctl_base_addr = of_iomap(np, 0);
+   WARN_ON(!sdr_ctl_base_addr);
 }
 
 static void __init socfpga_init_irq(void)
-- 
1.7.9.5

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[PATCHv3 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM EDAC bindings and device
tree changes to the Altera SoC project.
---
v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   12 
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..431e98b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,12 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6ce912e..a0ea69b 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -681,6 +681,11 @@
reg = <0xffc25000 0x1000>;
};
 
+   sdramedac@0 {
+   compatible = "altr,sdram-edac";
+   interrupts = <0 39 4>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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edac: altera: Add EDAC support for Altera SDRAM Controller

[tthayer]

This patch adds EDAC support for the Altera CycloneV and ArriaV
SoC SDRAM Controller.

[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM
[PATCHv3 2/3] dts: socfpga: Add bindings for Altera SoC SDRAM EDAC
[PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM
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[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

[tthayer]

From: Thor Thayer 

Addition of the Altera SDRAM controller bindings and device
tree changes to the Altera SoC project. The "syscon" parameter
is included here because the SDRAM EDAC bits are shared with the SDRAM
configuration bits.
---
v2: Changes to SoC SDRAM EDAC code.

V3: Implement code suggestions for SDRAM EDAC code.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   14 ++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 19 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..525cb76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,14 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl", "syscon";
+Note that syscon is invoked for this device to support the FPGA
+   bridge driver, EDAC driver and other devices that share the
+   registers.
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index df43702..6ce912e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -676,6 +676,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv3 3/3] edac: altera: Add EDAC support for Altera SDRAM

[tthayer]

From: Thor Thayer 

---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

Signed-off-by: Thor Thayer 
---
 MAINTAINERS|5 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  411 
 4 files changed, 427 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index e67ea24..ecd1277 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1290,6 +1290,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA SDRAM EDAC SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/edac/altera_edac.c
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Maxime Coquelin 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..e8a3de7
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,411 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  0x2C
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH0x30
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS0x38
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   0x3C
+
+/* SDRAM Controller DRAM IRQ Register Bit Masks */
+#define DRAMINTR_INTREN0x01
+#define DRAMINTR_SBEMASK   0x02
+#define DRAMINTR_DBEMASK   0x04
+#define DRAMINTR_CORRDROPMASK  0x08
+#define DRAMINTR_INTRCLR   0x10
+
+/* SDRAM Controller Single Bit Error Count Register */
+#define SBECOUNT   0x40
+
+/* SDRAM Controller Si

[PATCHv7 0/3] Addition of Altera SDRAM Controller Summary

[tthayer]

From: Thor Thayer 

This patch series adds Altera SDRAM EDAC support.

The one sticky issue seems to be the use of "syscon". One register
in the SDRAM controller shares bitfields with different functionality.
In this series the devicetree includes the "syscon" designation
for the SDRAM Controller [patch 1] but the bindings document does not.
This flexibility means future generations of SDRAM controller may
correct this sharing of bitfields without changes to the bindings.

Thor Thayer (3):
  devicetree: Addition of the Altera SDRAM Controller. 
Add the Altera SDRAM controller bindings and device tree 
changes to the Altera SoC project.
  devicetree: Addition of the Altera SDRAM EDAC. 
Add the Altera SDRAM EDAC bindings and device tree changes 
to the Altera SoC project.
  edac: altera: Add EDAC support for Altera SoC SDRAM Controller.
This patch adds support for the CycloneV and ArriaV SDRAM
controllers. Correction and reporting of SBEs, Panic on DBEs.

 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +
 arch/arm/boot/dts/socfpga.dtsi |   11 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  448 
 6 files changed, 496 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
 create mode 100644 drivers/edac/altera_edac.c

-- 
1.7.9.5

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[PATCHv7 2/3] devicetree: Addition of the Altera SDRAM EDAC.

[tthayer]

From: Thor Thayer 

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC 
project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC EDAC source code.

v3: Fix typo in device tree documentation.

v4,v5: No changes - bump version for consistency.

v6: Assign ECC registers in SDRAM controller to EDAC

v7: Fix SDRAM EDAC base address.
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +++
 arch/arm/boot/dts/socfpga.dtsi |6 ++
 2 files changed, 21 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..d68e033
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- reg : should contain the ECC register range in sdram
+controller (address and length).
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac@ffc2502c {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502c 0x28>;
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 310292e..da0785d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,12 @@
reg = <0xffc25000 0x4>;
};
 
+   sdramedac@ffc2502c {
+   compatible = "altr,sdram-edac";
+   reg = <0xffc2502c 0x28>;
+   interrupts = <0 39 4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv7 1/3] devicetree: Addition of the Altera SDRAM Controller.

[tthayer]

From: Thor Thayer 

Add the Altera SDRAM controller bindings and device tree changes to the Altera 
SoC project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

v7: No change. Bump for consistency.
---
 .../bindings/arm/altera/socfpga-sdram.txt  |   11 +++
 arch/arm/boot/dts/socfpga.dtsi |5 +
 2 files changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
new file mode 100644
index 000..5027026
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA SDRAM Controller
+
+Required properties:
+- compatible : "altr,sdr-ctl";
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl";
+   reg = <0xffc25000 0x4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..310292e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -682,6 +682,11 @@
clocks = <&l4_sp_clk>;
};
 
+   sdrctl@ffc25000 {
+   compatible = "altr,sdr-ctl", "syscon";
+   reg = <0xffc25000 0x4>;
+   };
+
rst: rstmgr@ffd05000 {
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
-- 
1.7.9.5

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[PATCHv7 3/3] edac: altera: Add EDAC support for Altera SoC SDRAM Controller.

[tthayer]

From: Thor Thayer 

This patch adds support for the CycloneV and ArriaV SDRAM controllers. 
Correction and reporting of SBEs, Panic on DBEs.

Signed-off-by: Thor Thayer 
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

v7: No change. Bump version for consistency.
---
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  448 
 3 files changed, 459 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..9741336 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..e3fcd27
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,448 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+
+ *
+ * Adapted from the highbank_mc_edac driver
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN  0x400
+#define CTLCFG_ECC_CORR_EN 0x800
+#define CTLCFG_GEN_SB_ERR  0x2000
+#define CTLCFG_GEN_DB_ERR  0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller ECC Register Offset */
+#define ECC_REG_OFFSET 0x2C
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW  (0x2C-ECC_REG_OFFSET)
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK  0x001F
+#define DRAMADDRW_COLBIT_LSB   0
+#define DRAMADDRW_ROWBIT_MASK  0x03E0
+#define DRAMADDRW_ROWBIT_LSB   5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_LSB  10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_LSB13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH(0x30-ECC_REG_OFFSET)
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC24
+#define DRAMIFWIDTH_32B_ECC40
+
+/* SDRAM Controller DRAM Status Register */
+#define DRAMSTS(0x38-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM Status Register Bit Masks */
+#define DRAMSTS_SBEERR 0x04
+#define DRAMSTS_DBEERR 0x08
+#define DRAMSTS_CORR_DROP  0x10
+
+/* SDRAM Controller DRAM IRQ Register */
+#define DRAMINTR   (0x3C-ECC_REG_OFFSET)
+
+/* SDRAM Controller DRAM IRQ Register Bit Masks */

[PATCHv10 0/2] Addition of Altera EDAC support

[tthayer]

From: Thor Thayer 

The Altera SDRAM controller EDAC support is added in this
patch series. The SDRAM controller shares its registers with
the EDAC, and 2 upcoming drivers (fpga bridge and power control).
This series of patches started using the syscon driver to share
the SDRAM controller registers but met with resistance. 

In the last series of patches, this was changed to using an
MFD for the SDRAM but the suggested changes began to look more 
like the syscon interface. As a result, I'm resubmitting this
with syscon and addressing some of the objections to the use
of syscon. 

Thor Thayer (2):
  edac: altera: Add Altera SDRAM EDAC support.
  arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.

 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +
 MAINTAINERS|5 +
 arch/arm/boot/dts/socfpga.dtsi |   11 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  410 
 6 files changed, 452 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
 create mode 100644 drivers/edac/altera_edac.c

-- 
1.7.9.5

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[PATCHv10 1/2] edac: altera: Add Altera SDRAM EDAC support.

[tthayer]

From: Thor Thayer 

This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.

Signed-off-by: Thor Thayer 
---
v2: Use the SDRAM controller registers to calculate memory size
instead of the Device Tree. Update To & Cc list. Add maintainer
information.

v3: EDAC driver cleanup based on comments from Mailing list.

v4: Panic on DBE. Add macro around inject-error reads to prevent
them from being optimized out. Remove of_match_ptr since this
will always use Device Tree.

v5: Addition of printk to trigger function to ensure read vars
are not optimized out.

v6: Changes to split out shared SDRAM controller reg (offset 0x00)
as a syscon device and allocate ECC specific SDRAM registers
to EDAC.

v7: No changes. Bump for consistency.

v8: Alphabetize headers.

v9: Changes to support a MFD SDRAM controller with nested EDAC.

v10: Revert to version 5 (syscon) and fix errors found in v5.
---
 MAINTAINERS|5 +
 drivers/edac/Kconfig   |9 +
 drivers/edac/Makefile  |2 +
 drivers/edac/altera_edac.c |  410 
 4 files changed, 426 insertions(+)
 create mode 100644 drivers/edac/altera_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 86efa7e..2d0bf75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1340,6 +1340,11 @@ M:   Dinh Nguyen 
 S: Maintained
 F: drivers/clk/socfpga/
 
+ARM/SOCFPGA EDAC SUPPORT
+M: Thor Thayer 
+S: Maintained
+F: drivers/edac/altera_edac.
+
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
 M: Maxime Coquelin 
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 878f090..4f4d379 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -368,4 +368,13 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
+config EDAC_ALTERA_MC
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   help
+ Support for error detection and correction on the
+ Altera SDRAM memory controller. Note that the
+ preloader must initialize the SDRAM before loading
+ the kernel.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 4154ed6..70845c4 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -64,3 +64,5 @@ obj-$(CONFIG_EDAC_OCTEON_PC)  += octeon_edac-pc.o
 obj-$(CONFIG_EDAC_OCTEON_L2C)  += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
+
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
new file mode 100644
index 000..3c4929f
--- /dev/null
+++ b/drivers/edac/altera_edac.c
@@ -0,0 +1,410 @@
+/*
+ *  Copyright Altera Corporation (C) 2014. All rights reserved.
+ *  Copyright 2011-2012 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ *
+ * Adapted from the highbank_mc_edac driver.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "edac_core.h"
+#include "edac_module.h"
+
+#define EDAC_MOD_STR   "altera_edac"
+#define EDAC_VERSION   "1"
+
+/* SDRAM Controller CtrlCfg Register */
+#define CTLCFG_OFST 0x00
+
+/* SDRAM Controller CtrlCfg Register Bit Masks */
+#define CTLCFG_ECC_EN   0x400
+#define CTLCFG_ECC_CORR_EN  0x800
+#define CTLCFG_GEN_SB_ERR   0x2000
+#define CTLCFG_GEN_DB_ERR   0x4000
+
+#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN | \
+CTLCFG_ECC_CORR_EN)
+
+/* SDRAM Controller Address Width Register */
+#define DRAMADDRW_OFST  0x2C
+
+/* SDRAM Controller Address Widths Field Register */
+#define DRAMADDRW_COLBIT_MASK   0x001F
+#define DRAMADDRW_COLBIT_SHIFT  0
+#define DRAMADDRW_ROWBIT_MASK   0x03E0
+#define DRAMADDRW_ROWBIT_SHIFT  5
+#define DRAMADDRW_BANKBIT_MASK 0x1C00
+#define DRAMADDRW_BANKBIT_SHIFT 10
+#define DRAMADDRW_CSBIT_MASK   0xE000
+#define DRAMADDRW_CSBIT_SHIFT   13
+
+/* SDRAM Controller Interface Data Width Register */
+#define DRAMIFWIDTH_OFST0x30
+
+/* SDRAM Controller Interface Data Width Defines */
+#define DRAMIFWIDTH_16B_ECC 24
+#define DRAMIFWIDTH_32B_ECC 40
+
+/

[PATCHv10 2/2] arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.

[tthayer]

From: Thor Thayer 

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC 
project.

Signed-off-by: Thor Thayer 
---
v2: Changes to SoC SDRAM EDAC code.

v3: Implement code suggestions for SDRAM EDAC code.

v4: Remove syscon from SDRAM controller bindings.

v5: No Change, bump version for consistency.

v6: Only map the ctrlcfg register as syscon.

v7: No change. Bump for consistency.

v8: No change. Bump for consistency.

v9: Changes to support a MFD SDRAM controller with nested EDAC.

v10: Revert to using syscon based on feedback.
---
 .../bindings/arm/altera/socfpga-sdram-edac.txt |   15 +++
 arch/arm/boot/dts/socfpga.dtsi |   11 +++
 2 files changed, 26 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt

diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000..d0ce01d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+The EDAC accesses a range of registers in the SDRAM controller.
+
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- altr,sdr-syscon : phandle of the sdr module
+- interrupts : Should contain the SDRAM ECC IRQ in the
+   appropriate format for the IRQ controller.
+
+Example:
+   sdramedac {
+   compatible = "altr,sdram-edac";
+   altr,sdr-syscon = <&sdr>;
+   interrupts = <0 39 4>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4676f25..45b361e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -603,6 +603,17 @@
};
};
 
+   sdr: sdr@ffc25000 {
+   compatible = "syscon";
+   reg = <0xffc25000 0x1000>;
+   };
+
+   sdramedac {
+   compatible = "altr,sdram-edac";
+   altr,sdr-syscon = <&sdr>;
+   interrupts = <0 39 4>;
+   };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
-- 
1.7.9.5

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[PATCHv3 0/5] Add Altera peripheral memories to EDAC framework

[tthayer]

From: Thor Thayer 

This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.

v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
  L2 ECC platform initialization.
- Fix L2 cache dependency comments.
- Remove OCRAM node from dts and reference prior patch.

v3 changes:
- Move L2 cache & On-Chip RAM EDAC code into altera_edac.c
- Remove SDRAM module compile.


Thor Thayer (5):
  arm: socfpga: Enable L2 Cache ECC on startup.
  arm: socfpga: Enable OCRAM ECC on startup.
  edac: altera: Remove SDRAM module compile
  edac: altera: Add Altera L2 Cache and OCRAM EDAC Support
  arm: dts: Add Altera L2 Cache and OCRAM EDAC

 .../bindings/arm/altera/socfpga-l2-edac.txt|   15 +
 .../bindings/arm/altera/socfpga-ocram-edac.txt |   16 +
 MAINTAINERS|2 +
 arch/arm/boot/dts/socfpga.dtsi |   15 +-
 arch/arm/mach-socfpga/Makefile |2 +
 arch/arm/mach-socfpga/l2_cache.c   |   44 ++
 arch/arm/mach-socfpga/l2_cache.h   |   28 ++
 arch/arm/mach-socfpga/ocram.c  |   90 
 arch/arm/mach-socfpga/ocram.h  |   28 ++
 arch/arm/mach-socfpga/socfpga.c|   13 +-
 drivers/edac/Kconfig   |   18 +-
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  475 +++-
 13 files changed, 745 insertions(+), 6 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h

-- 
1.7.9.5

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[PATCHv3 2/5] arm: socfpga: Enable OCRAM ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for On-Chip RAM on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganization of gen_pool_free. Remove defconfig from patch.

v3: No change
---
 MAINTAINERS |1 +
 arch/arm/mach-socfpga/Makefile  |1 +
 arch/arm/mach-socfpga/ocram.c   |   90 +++
 arch/arm/mach-socfpga/ocram.h   |   28 
 arch/arm/mach-socfpga/socfpga.c |8 
 5 files changed, 128 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d0c7752..c6d390e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1408,6 +1408,7 @@ M:Thor Thayer 
 S: Maintained
 F: drivers/edac/altera_edac.
 F: arch/arm/mach-socfpga/l2_cache.*
+F: arch/arm/mach-socfpga/ocram.*
 
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 142609e..1552ca5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -5,3 +5,4 @@
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
 obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
new file mode 100644
index 000..9136009
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+#include "ocram.h"
+
+void socfpga_init_ocram_ecc(void)
+{
+   struct device_node *np;
+   const __be32 *prop;
+   u32 ocr_edac_addr, iram_addr, len;
+   void __iomem  *mapped_ocr_edac_addr;
+   size_t size;
+   struct gen_pool *gp;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
+   return;
+   }
+
+   prop = of_get_property(np, "reg", &size);
+   ocr_edac_addr = be32_to_cpup(prop++);
+   len = be32_to_cpup(prop);
+   if (!prop || size < sizeof(*prop)) {
+   pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
+   return;
+   }
+
+   gp = of_get_named_gen_pool(np, "iram", 0);
+   if (!gp) {
+   pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
+   return;
+   }
+
+   np = of_find_compatible_node(NULL, NULL, "mmio-sram");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
+   return;
+   }
+   /* Determine the OCRAM address and size */
+   prop = of_get_property(np, "reg", &size);
+   iram_addr = be32_to_cpup(prop++);
+   len = be32_to_cpup(prop);
+
+   if (!prop || size < sizeof(*prop)) {
+   pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
+   return;
+   }
+
+   iram_addr = gen_pool_alloc(gp, len);
+   if (iram_addr == 0) {
+   pr_err("SOCFPGA: cannot alloc from gen pool\n");
+   return;
+   }
+
+   memset((void *)iram_addr, 0, len);
+
+   gen_pool_free(gp, iram_addr, len);
+
+   mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
+   if (!mapped_ocr_edac_addr) {
+   pr_err("SOCFPGA: Unable to map OCRAM ecc regs.\n");
+   return;
+   }
+
+   /* Clear any pending OCRAM ECC interrupts, then enable ECC */
+   writel(0x18, mapped_ocr_edac_addr);
+   writel(0x19, mapped_ocr_edac_addr);
+
+   iounmap(mapped_ocr_edac_addr);
+
+   pr_debug("SOCFPGA: Success Initializing OCRAM\n");
+}
+
diff --git a/arch/arm/mach-socfpga/ocram.h b/arch/arm/mach-socfpga/ocram.h
new file mode 100644
index 000..f93cf84
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free 

[PATCHv3 3/5] edac: altera: Remove SDRAM module compile

[tthayer]

From: Thor Thayer 

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer 
---
v3: Added in this version as a separate patch.
---
 drivers/edac/Kconfig |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7072c28..1719975 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-   tristate "Altera SDRAM Memory Controller EDAC"
-   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
help
  Support for error detection and correction on the
  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5

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[PATCHv3 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[tthayer]

From: Thor Thayer 

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device  model. The SDRAM
controller is using the Memory Controller model. All
Altera EDAC functions live in altera_edac.c.

Signed-off-by: Thor Thayer 
---
v2: Fix L2 dependency comments.

v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c
instead of separate files.
---
 drivers/edac/Kconfig   |   14 ++
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  475 +++-
 3 files changed, 492 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 1719975..b145a52 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -385,4 +385,18 @@ config EDAC_ALTERA_MC
  preloader must initialize the SDRAM before loading
  the kernel.
 
+config EDAC_ALTERA_L2C
+   bool "Altera L2 Cache EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && CACHE_L2X0
+   help
+ Support for error detection and correction on the
+ Altera L2 cache Memory for Altera SoCs.
+
+config EDAC_ALTERA_OCRAM
+   bool "Altera On-Chip RAM EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && SRAM && GENERIC_ALLOCATOR
+   help
+ Support for error detection and correction on the
+ Altera On-Chip RAM Memory for Altera SoCs.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 359aa49..fa8aebc 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -66,4 +66,7 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
 
-obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
+alt_edac-y := altera_edac.o
+obj-$(CONFIG_EDAC_ALTERA_MC)   += alt_edac.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)  += alt_edac.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)+= alt_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3c4929f..1ee8d94 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -17,8 +17,10 @@
  * Adapted from the highbank_mc_edac driver.
  */
 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -33,6 +35,7 @@
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
+#define EDAC_DEVICE"DEVICE"
 
 /* SDRAM Controller CtrlCfg Register */
 #define CTLCFG_OFST 0x00
@@ -107,6 +110,30 @@ struct altr_sdram_mc_data {
struct regmap *mc_vbase;
 };
 
+/** EDAC Device Defines **/
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN_MASK0x0001
+#define ALTR_OCR_ECC_INJS_MASK  0x0002
+#define ALTR_OCR_ECC_INJD_MASK  0x0004
+#define ALTR_OCR_ECC_SERR_MASK  0x0008
+#define ALTR_OCR_ECC_DERR_MASK  0x0010
+
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET   0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASK0x0001
+
+/* L2 ECC Management Group Defines */
+#define ALTR_MAN_GRP_L2_ECC_OFFSET  0x00
+#define ALTR_L2_ECC_EN_MASK 0x0001
+#define ALTR_L2_ECC_INJS_MASK   0x0002
+#define ALTR_L2_ECC_INJD_MASK   0x0004
+
+/*** EDAC Memory Controller Functions /
+
+/* The SDRAM controller uses the EDAC Memory Controller framework.   */
+
 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
 {
struct mem_ctl_info *mci = dev_id;
@@ -405,6 +432,452 @@ static struct platform_driver altr_sdram_edac_driver = {
 
 module_platform_driver(altr_sdram_edac_driver);
 
+/* EDAC Device Functions */
+
+/*
+ * EDAC Device Functions (shared between various IPs).
+ * The discrete memories use the EDAC Device framework. The probe
+ * and error handling functions are very similar between memories
+ * so they are shared. The memory allocation and free for EDAC trigger
+ * testing are different for each memory.
+ */
+
+const struct edac_device_prv_data ocramecc_data;
+const struct edac_device_prv_data l2ecc_data;
+
+struct edac_device_prv_data {
+   int (*setup)(struct platform_device *pdev, void __iomem *base);
+   int ce_clear_mask;
+   int ue_clear_mask;
+#ifdef CONFIG_EDAC_DEBUG
+   struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
+   void * (*alloc_mem)(size_t size, void **other);
+   void (*free_mem)(void *p, size_t size, void *other);
+   int ecc_enable_mask;
+   int ce_set_mask;
+   int ue_set_mask;
+   int trig_alloc_sz;
+#endif
+};
+
+struct altr_edac_device_dev {
+   void __iomem *base;
+   int sb_irq;
+   int db_irq;
+   const struct edac_device_prv_data *data;
+   char 

[PATCHv3 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

[tthayer]

From: Thor Thayer 

Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html

Signed-off-by: Thor Thayer 
---
v2: Remove OCRAM declaration and reference prior patch.

v3: No Change
---
 .../bindings/arm/altera/socfpga-l2-edac.txt|   15 +++
 .../bindings/arm/altera/socfpga-ocram-edac.txt |   16 
 arch/arm/boot/dts/socfpga.dtsi |   15 ++-
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
new file mode 100644
index 000..35b19e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
@@ -0,0 +1,15 @@
+Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be "altr,l2-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
new file mode 100644
index 000..31ab205
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
@@ -0,0 +1,16 @@
+Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
+
+OCRAM ECC Required Properties:
+- compatible : Should be "altr,ocram-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6af96ed..32c63a3 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -618,8 +618,21 @@
interrupts = <0 39 4>;
};
 
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+
L2: l2-cache@fffef000 {
-   compatible = "arm,pl310-cache";
+   compatible = "arm,pl310-cache", "syscon";
reg = <0xfffef000 0x1000>;
interrupts = <0 38 0x04>;
cache-unified;
-- 
1.7.9.5

--
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[PATCHv3 1/5] arm: socfpga: Enable L2 Cache ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for L2 cache on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM initialization into separate patch.

v3: No change
---
 MAINTAINERS  |1 +
 arch/arm/mach-socfpga/Makefile   |1 +
 arch/arm/mach-socfpga/l2_cache.c |   44 ++
 arch/arm/mach-socfpga/l2_cache.h |   28 
 arch/arm/mach-socfpga/socfpga.c  |5 -
 5 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h

diff --git a/MAINTAINERS b/MAINTAINERS
index ee1bc5b..d0c7752 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1407,6 +1407,7 @@ ARM/SOCFPGA EDAC SUPPORT
 M: Thor Thayer 
 S: Maintained
 F: drivers/edac/altera_edac.
+F: arch/arm/mach-socfpga/l2_cache.*
 
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..142609e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
+obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 000..8e109f3
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+#include "l2_cache.h"
+
+void socfpga_init_l2_ecc(void)
+{
+   struct device_node *np;
+   void __iomem  *mapped_l2_edac_addr;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
+   return;
+   }
+
+   mapped_l2_edac_addr = of_iomap(np, 0);
+   if (!mapped_l2_edac_addr) {
+   pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
+   return;
+   }
+
+   /* Enable ECC */
+   writel(0x01, mapped_l2_edac_addr);
+
+   pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
+}
+
diff --git a/arch/arm/mach-socfpga/l2_cache.h b/arch/arm/mach-socfpga/l2_cache.h
new file mode 100644
index 000..58e140d
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef MACH_SOCFPGA_L2_CACHE_H
+#define MACH_SOCFPGA_L2_CACHE_H
+
+#ifdef CONFIG_EDAC_ALTERA_L2C
+void socfpga_init_l2_ecc(void);
+#else
+inline void socfpga_init_l2_ecc(void)
+{
+}
+#endif
+
+#endif /* #ifndef MACH_SOCFPGA_L2_CACHE_H */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..af6413a 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation
+ *  Copyright (C) 2012;2014 Altera Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +25,8 @@
 #include 
 
 #include "core.h"
+#include "l2_cache.h"
+#include "ocram.h"
 
 void __iomem *socfpga_scu_base_addr = ((void __iomem 
*)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
@@ -83,6 +85,7 @@ static void __init socfpga_init_irq(void)
 {
irqchip_init();
socfpga_sysmgr_init();
+   socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

--
To unsubs

[PATCHv4 0/5] Add Altera peripheral memories to EDAC framework

[tthayer]

From: Thor Thayer 

This patch adds the L2 cache and OCRAM peripherals to the EDAC framework
using the EDAC device framework. The ECC is enabled early in the boot
process in the platform specific code.

v2 changes:
- Split On-Chip RAM ECC platform initialization into separate patch from
  L2 ECC platform initialization.
- Fix L2 cache dependency comments.
- Remove OCRAM node from dts and reference prior patch.

v3 changes:
- Move L2 cache & On-Chip RAM EDAC code into altera_edac.c
- Remove SDRAM module compile.

v4 changes:
- Change mask defines to use BIT().
- Fix comment style to agree with kernel coding style.
- Better printk description for read != write in trigger.
- Remove SysFS debugging message.
- Better dci->mod_name
- Move gen_pool pointer assignment to end of function.
- Invert logic to reduce indent in ocram depenency check.
- Change from dev_err() to edac_printk()
- Replace magic numbers with defines & comments.
- Improve error injection test.
- Change Makefile intermediary name to altr (from alt)

Thor Thayer (5):
  arm: socfpga: Enable L2 Cache ECC on startup.
  arm: socfpga: Enable OCRAM ECC on startup.
  edac: altera: Remove SDRAM module compile
  edac: altera: Add Altera L2 Cache and OCRAM EDAC Support
  arm: dts: Add Altera L2 Cache and OCRAM EDAC

 .../bindings/arm/altera/socfpga-l2-edac.txt|   15 +
 .../bindings/arm/altera/socfpga-ocram-edac.txt |   16 +
 MAINTAINERS|2 +
 arch/arm/boot/dts/socfpga.dtsi |   15 +-
 arch/arm/mach-socfpga/Makefile |2 +
 arch/arm/mach-socfpga/l2_cache.c   |   44 ++
 arch/arm/mach-socfpga/l2_cache.h   |   28 ++
 arch/arm/mach-socfpga/ocram.c  |   90 
 arch/arm/mach-socfpga/ocram.h  |   28 ++
 arch/arm/mach-socfpga/socfpga.c|   13 +-
 drivers/edac/Kconfig   |   18 +-
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  481 +++-
 13 files changed, 751 insertions(+), 6 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h

-- 
1.7.9.5

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCHv4 1/5] arm: socfpga: Enable L2 Cache ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for L2 cache on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM initialization into separate patch.

v3/4: No change
---
 MAINTAINERS  |1 +
 arch/arm/mach-socfpga/Makefile   |1 +
 arch/arm/mach-socfpga/l2_cache.c |   44 ++
 arch/arm/mach-socfpga/l2_cache.h |   28 
 arch/arm/mach-socfpga/socfpga.c  |5 -
 5 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c
 create mode 100644 arch/arm/mach-socfpga/l2_cache.h

diff --git a/MAINTAINERS b/MAINTAINERS
index ee1bc5b..d0c7752 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1407,6 +1407,7 @@ ARM/SOCFPGA EDAC SUPPORT
 M: Thor Thayer 
 S: Maintained
 F: drivers/edac/altera_edac.
+F: arch/arm/mach-socfpga/l2_cache.*
 
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..142609e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
+obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 000..8e109f3
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+#include "l2_cache.h"
+
+void socfpga_init_l2_ecc(void)
+{
+   struct device_node *np;
+   void __iomem  *mapped_l2_edac_addr;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
+   return;
+   }
+
+   mapped_l2_edac_addr = of_iomap(np, 0);
+   if (!mapped_l2_edac_addr) {
+   pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
+   return;
+   }
+
+   /* Enable ECC */
+   writel(0x01, mapped_l2_edac_addr);
+
+   pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
+}
+
diff --git a/arch/arm/mach-socfpga/l2_cache.h b/arch/arm/mach-socfpga/l2_cache.h
new file mode 100644
index 000..58e140d
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef MACH_SOCFPGA_L2_CACHE_H
+#define MACH_SOCFPGA_L2_CACHE_H
+
+#ifdef CONFIG_EDAC_ALTERA_L2C
+void socfpga_init_l2_ecc(void);
+#else
+inline void socfpga_init_l2_ecc(void)
+{
+}
+#endif
+
+#endif /* #ifndef MACH_SOCFPGA_L2_CACHE_H */
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..af6413a 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation
+ *  Copyright (C) 2012;2014 Altera Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +25,8 @@
 #include 
 
 #include "core.h"
+#include "l2_cache.h"
+#include "ocram.h"
 
 void __iomem *socfpga_scu_base_addr = ((void __iomem 
*)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
@@ -83,6 +85,7 @@ static void __init socfpga_init_irq(void)
 {
irqchip_init();
socfpga_sysmgr_init();
+   socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

--
To unsu

[PATCHv4 2/5] arm: socfpga: Enable OCRAM ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for On-Chip RAM on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM ECC portion separately. Addition of iounmap()
and reorganization of gen_pool_free. Remove defconfig from patch.

v3/4: No change
---
 MAINTAINERS |1 +
 arch/arm/mach-socfpga/Makefile  |1 +
 arch/arm/mach-socfpga/ocram.c   |   90 +++
 arch/arm/mach-socfpga/ocram.h   |   28 
 arch/arm/mach-socfpga/socfpga.c |8 
 5 files changed, 128 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/ocram.c
 create mode 100644 arch/arm/mach-socfpga/ocram.h

diff --git a/MAINTAINERS b/MAINTAINERS
index d0c7752..c6d390e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1408,6 +1408,7 @@ M:Thor Thayer 
 S: Maintained
 F: drivers/edac/altera_edac.
 F: arch/arm/mach-socfpga/l2_cache.*
+F: arch/arm/mach-socfpga/ocram.*
 
 ARM/STI ARCHITECTURE
 M: Srinivas Kandagatla 
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 142609e..1552ca5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -5,3 +5,4 @@
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
 obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM) += ocram.o
diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
new file mode 100644
index 000..9136009
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+#include "ocram.h"
+
+void socfpga_init_ocram_ecc(void)
+{
+   struct device_node *np;
+   const __be32 *prop;
+   u32 ocr_edac_addr, iram_addr, len;
+   void __iomem  *mapped_ocr_edac_addr;
+   size_t size;
+   struct gen_pool *gp;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n");
+   return;
+   }
+
+   prop = of_get_property(np, "reg", &size);
+   ocr_edac_addr = be32_to_cpup(prop++);
+   len = be32_to_cpup(prop);
+   if (!prop || size < sizeof(*prop)) {
+   pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n");
+   return;
+   }
+
+   gp = of_get_named_gen_pool(np, "iram", 0);
+   if (!gp) {
+   pr_err("SOCFPGA: OCRAM cannot find gen pool\n");
+   return;
+   }
+
+   np = of_find_compatible_node(NULL, NULL, "mmio-sram");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n");
+   return;
+   }
+   /* Determine the OCRAM address and size */
+   prop = of_get_property(np, "reg", &size);
+   iram_addr = be32_to_cpup(prop++);
+   len = be32_to_cpup(prop);
+
+   if (!prop || size < sizeof(*prop)) {
+   pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n");
+   return;
+   }
+
+   iram_addr = gen_pool_alloc(gp, len);
+   if (iram_addr == 0) {
+   pr_err("SOCFPGA: cannot alloc from gen pool\n");
+   return;
+   }
+
+   memset((void *)iram_addr, 0, len);
+
+   gen_pool_free(gp, iram_addr, len);
+
+   mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4);
+   if (!mapped_ocr_edac_addr) {
+   pr_err("SOCFPGA: Unable to map OCRAM ecc regs.\n");
+   return;
+   }
+
+   /* Clear any pending OCRAM ECC interrupts, then enable ECC */
+   writel(0x18, mapped_ocr_edac_addr);
+   writel(0x19, mapped_ocr_edac_addr);
+
+   iounmap(mapped_ocr_edac_addr);
+
+   pr_debug("SOCFPGA: Success Initializing OCRAM\n");
+}
+
diff --git a/arch/arm/mach-socfpga/ocram.h b/arch/arm/mach-socfpga/ocram.h
new file mode 100644
index 000..f93cf84
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Fre

[PATCHv4 3/5] edac: altera: Remove SDRAM module compile

[tthayer]

From: Thor Thayer 

The SDRAM EDAC requires SDRAM configuration/initialization before
SDRAM is accessed (in the preloader). Having a module compile is
not desired so force to be built into kernel.

Signed-off-by: Thor Thayer 
---
v3: Added in this version as a separate patch.

v4: No change.
---
 drivers/edac/Kconfig |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 7072c28..1719975 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -377,8 +377,8 @@ config EDAC_OCTEON_PCI
  Cavium Octeon family of SOCs.
 
 config EDAC_ALTERA_MC
-   tristate "Altera SDRAM Memory Controller EDAC"
-   depends on EDAC_MM_EDAC && ARCH_SOCFPGA
+   bool "Altera SDRAM Memory Controller EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
help
  Support for error detection and correction on the
  Altera SDRAM memory controller. Note that the
-- 
1.7.9.5

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[PATCHv4 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

[tthayer]

From: Thor Thayer 

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device  model. The SDRAM
controller is using the Memory Controller model.

The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster boot time.
2) the SDRAM has an ECC initialization dependency on the preloader
which is outside the kernel. It is desirable to be able to turn the
SDRAM on & off separately.

Signed-off-by: Thor Thayer 
---
v2: Fix L2 dependency comments.

v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c
instead of separate files.

v4: Change mask defines to use BIT().
Fix comment style to agree with kernel coding style.
Better printk description for read != write in trigger.
Remove SysFS debugging message.
Better dci->mod_name
Move gen_pool pointer assignment to end of function.
Invert logic to reduce indent in ocram depenency check.
Change from dev_err() to edac_printk()
Replace magic numbers with defines & comments.
Improve error injection test.
Change Makefile intermediary name to altr (from alt)
---
 drivers/edac/Kconfig   |   14 ++
 drivers/edac/Makefile  |5 +-
 drivers/edac/altera_edac.c |  481 +++-
 3 files changed, 498 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 1719975..b145a52 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -385,4 +385,18 @@ config EDAC_ALTERA_MC
  preloader must initialize the SDRAM before loading
  the kernel.
 
+config EDAC_ALTERA_L2C
+   bool "Altera L2 Cache EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && CACHE_L2X0
+   help
+ Support for error detection and correction on the
+ Altera L2 cache Memory for Altera SoCs.
+
+config EDAC_ALTERA_OCRAM
+   bool "Altera On-Chip RAM EDAC"
+   depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA && SRAM && GENERIC_ALLOCATOR
+   help
+ Support for error detection and correction on the
+ Altera On-Chip RAM Memory for Altera SoCs.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 359aa49..20e9b6f 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -66,4 +66,7 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
 
-obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
+altr_edac-y:= altera_edac.o
+obj-$(CONFIG_EDAC_ALTERA_MC)   += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)  += altr_edac.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)+= altr_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3c4929f..1655dd3 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -17,8 +17,10 @@
  * Adapted from the highbank_mc_edac driver.
  */
 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -33,6 +35,7 @@
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
+#define EDAC_DEVICE"ALTR_MEM"
 
 /* SDRAM Controller CtrlCfg Register */
 #define CTLCFG_OFST 0x00
@@ -107,6 +110,35 @@ struct altr_sdram_mc_data {
struct regmap *mc_vbase;
 };
 
+/** EDAC Device Defines **/
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN_MASKBIT(0)
+#define ALTR_OCR_ECC_INJS_MASK  BIT(1)
+#define ALTR_OCR_ECC_INJD_MASK  BIT(2)
+#define ALTR_OCR_ECC_SERR_MASK  BIT(3)
+#define ALTR_OCR_ECC_DERR_MASK  BIT(4)
+
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET   0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASKBIT(0)
+
+/* L2 ECC Management Group Defines */
+#define ALTR_MAN_GRP_L2_ECC_OFFSET  0x00
+#define ALTR_L2_ECC_EN_MASK BIT(0)
+#define ALTR_L2_ECC_INJS_MASK   BIT(1)
+#define ALTR_L2_ECC_INJD_MASK   BIT(2)
+
+#define ALTR_UE_TRIGGER_CHAR'U'   /* Trigger for UE */
+#define ALTR_TRIGGER_READ_WRD_CNT   16/* Line size x 2 */
+#define ALTR_TRIG_OCRAM_BYTE_SIZE   128   /* Line size x 4 */
+#define ALTR_TRIG_L2C_BYTE_SIZE 4096  /* Full Page */
+
+/*** EDAC Memory Controller Functions /
+
+/* The SDRAM controller uses the EDAC Memory Controller framework.   */
+
 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
 {
struct mem_ctl_info *mci = dev_id;
@@ -405,6 +437,453 @@ static struct platform_driver altr_sdram_edac_driver = {
 
 module_platform_driver(altr_sdram_edac_driver);
 
+/* EDAC Device Functions */
+
+/*
+ * EDAC Device Functions (s

[PATCHv4 5/5] arm: dts: Add Altera L2 Cache and OCRAM EDAC

[tthayer]

From: Thor Thayer 

Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html

Signed-off-by: Thor Thayer 
---
v2: Remove OCRAM declaration and reference prior patch.

v3/4: No Change
---
 .../bindings/arm/altera/socfpga-l2-edac.txt|   15 +++
 .../bindings/arm/altera/socfpga-ocram-edac.txt |   16 
 arch/arm/boot/dts/socfpga.dtsi |   15 ++-
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
new file mode 100644
index 000..35b19e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-l2-edac.txt
@@ -0,0 +1,15 @@
+Altera SoCFPGA L2 cache Error Detection and Correction [EDAC]
+
+Required Properties:
+- compatible : Should be "altr,l2-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
diff --git 
a/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
new file mode 100644
index 000..31ab205
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-ocram-edac.txt
@@ -0,0 +1,16 @@
+Altera SoCFPGA On-Chip RAM Error Detection and Correction [EDAC]
+
+OCRAM ECC Required Properties:
+- compatible : Should be "altr,ocram-edac"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6af96ed..32c63a3 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -618,8 +618,21 @@
interrupts = <0 39 4>;
};
 
+   l2edac@ffd08140 {
+   compatible = "altr,l2-edac";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocramedac@ffd08144 {
+   compatible = "altr,ocram-edac";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+
L2: l2-cache@fffef000 {
-   compatible = "arm,pl310-cache";
+   compatible = "arm,pl310-cache", "syscon";
reg = <0xfffef000 0x1000>;
interrupts = <0 38 0x04>;
cache-unified;
-- 
1.7.9.5

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[PATCH 0/5] Set Arria10 ECC Manager IRQ Controller

[tthayer]

From: Thor Thayer 

The Arria10 IRQs for each peripheral ECC block funnel into 2 IRQs
[1 for single bit errors (SBERR) and 1 for double bit errors (DBERR)]
which are better handled by the IRQ controller and IRQ domain
framework than the IRQ handler in the current implementation.

The IRQ numbers (hwirq) in each peripheral ECC block (currently L2
and OCRAM) device tree node cannot be parsed using of_ functions
in the current implementation because these functions attach the
IRQ to an IRQ domain.

This patch set adds the IRQ controller/IRQ domain framework but
requires some device tree and binding changes as a result.

Thor Thayer (5):
  Documentation: dt: socfpga: Add interrupt-controller to ecc-manager
  EDAC, altera: ECC Manager IRQ controller support
  EDAC, altera: Handle Arria10 SDRAM child node.
  ARM: dts: Arria10 ECC Manager IRQ controller changes
  ARM: dts: Move Arria10 SDRAM as child of ECC Manager

 .../bindings/arm/altera/socfpga-eccmgr.txt |   14 +-
 arch/arm/boot/dts/socfpga_arria10.dtsi |   19 +-
 drivers/edac/altera_edac.c |  182 +++-
 drivers/edac/altera_edac.h |5 +-
 4 files changed, 168 insertions(+), 52 deletions(-)

-- 
1.7.9.5

[PATCH 2/5] EDAC, altera: ECC Manager IRQ controller support

[tthayer]

From: Thor Thayer 

To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.

Signed-off-by: Thor Thayer 
---
 drivers/edac/altera_edac.c |  162 +---
 drivers/edac/altera_edac.h |5 +-
 2 files changed, 125 insertions(+), 42 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 5b4d223..3eb73bc 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -22,9 +22,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -882,22 +884,27 @@ static void ocram_free_mem(void *p, size_t size, void 
*other)
gen_pool_free((struct gen_pool *)other, (u32)p, size);
 }
 
-static irqreturn_t altr_edac_a10_ecc_irq(struct altr_edac_device_dev *dci,
-bool sberr)
+static irqreturn_t altr_edac_a10_ecc_irq(int irq, void *dev_id)
 {
+   irqreturn_t ret_value = IRQ_NONE;
+   struct altr_edac_device_dev *dci = dev_id;
void __iomem  *base = dci->base;
 
-   if (sberr) {
+   if (irq == dci->sb_irq) {
+   ret_value = IRQ_HANDLED;
writel(ALTR_A10_ECC_SERRPENA,
   base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
-   } else {
+   } else if (irq == dci->db_irq) {
+   ret_value = IRQ_HANDLED;
writel(ALTR_A10_ECC_DERRPENA,
   base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+   } else {
+   WARN_ON(1);
}
-   return IRQ_HANDLED;
+   return ret_value;
 }
 
 const struct edac_device_prv_data ocramecc_data = {
@@ -988,22 +995,28 @@ static int altr_l2_check_deps(struct altr_edac_device_dev 
*device)
return -ENODEV;
 }
 
-static irqreturn_t altr_edac_a10_l2_irq(struct altr_edac_device_dev *dci,
-   bool sberr)
+static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
 {
-   if (sberr) {
+   irqreturn_t ret_value = IRQ_NONE;
+   struct altr_edac_device_dev *dci = dev_id;
+
+   if (irq == dci->sb_irq) {
+   ret_value = IRQ_HANDLED;
regmap_write(dci->edac->ecc_mgr_map,
 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
-   } else {
+   } else if (irq == dci->db_irq) {
+   ret_value = IRQ_HANDLED;
regmap_write(dci->edac->ecc_mgr_map,
 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+   } else {
+   WARN_ON(1);
}
-   return IRQ_HANDLED;
+   return ret_value;
 }
 
 const struct edac_device_prv_data l2ecc_data = {
@@ -1075,28 +1088,27 @@ static ssize_t altr_edac_a10_device_trig(struct file 
*file,
return count;
 }
 
-static irqreturn_t altr_edac_a10_irq_handler(int irq, void *dev_id)
+static void altr_edac_a10_irq_handler(struct irq_desc *desc)
 {
-   irqreturn_t rc = IRQ_NONE;
-   struct altr_arria10_edac *edac = dev_id;
-   struct altr_edac_device_dev *dci;
-   int irq_status;
-   bool sberr = (irq == edac->sb_irq) ? 1 : 0;
-   int sm_offset = sberr ? A10_SYSMGR_ECC_INTSTAT_SERR_OFST :
-   A10_SYSMGR_ECC_INTSTAT_DERR_OFST;
+   int dberr, bit, sm_offset, irq_status;
+   struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   int irq = irq_desc_get_irq(desc);
+
+   chained_irq_enter(chip, desc);
+   dberr = (irq == edac->db_irq) ? 1 : 0;
+   sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
+   A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
 
regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
 
-   if ((irq != edac->sb_irq) && (irq != edac->db_irq)) {
-   WARN_ON(1);
-   } else {
-   list_for_each_entry(dci, &edac->a10_ecc_devices, next) {
-   if (irq_status & dci->data->irq_status_mask)
-   rc = dci->data->ecc_irq_handler(dci, sberr);
-   }
+   for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
+   irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
+   if (irq)
+   generic_handle_irq(irq);
}
 
-   return rc;
+   chained_irq_exit(chip, desc);
 }
 
 static int altr_edac_a10_

[PATCH 5/5] ARM: dts: Move Arria10 SDRAM as child of ECC Manager

[tthayer]

From: Thor Thayer 

Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.

Signed-off-by: Thor Thayer 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |   13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 0901090..605c21e 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -568,12 +568,6 @@
reg = <0xffcfb100 0x80>;
};
 
-   sdramedac {
-   compatible = "altr,sdram-edac-a10";
-   altr,sdr-syscon = <&sdr>;
-   interrupts = <0 2 4>, <0 0 4>;
-   };
-
L2: l2-cache@f000 {
compatible = "arm,pl310-cache";
reg = <0xf000 0x1000>;
@@ -610,6 +604,13 @@
#interrupt-cells = <2>;
ranges;
 
+   sdramedac {
+   compatible = "altr,sdram-edac-a10";
+   altr,sdr-syscon = <&sdr>;
+   interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+<49 IRQ_TYPE_LEVEL_HIGH>;
+   };
+
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
-- 
1.7.9.5

[PATCH 4/5] ARM: dts: Arria10 ECC Manager IRQ controller changes

[tthayer]

From: Thor Thayer 

Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.

Signed-off-by: Thor Thayer 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 27cc497..0901090 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -606,16 +606,22 @@
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 <0 0 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
ranges;
 
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
+   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+<32 IRQ_TYPE_LEVEL_HIGH>;
};
 
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x400>;
+   interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+<33 IRQ_TYPE_LEVEL_HIGH>;
};
};
 
-- 
1.7.9.5

[PATCH 1/5] Documentation: dt: socfpga: Add interrupt-controller to ecc-manager

[tthayer]

From: Thor Thayer 

Designate the ECC Manager as an interrupt controller and add child
interrupts.

Signed-off-by: Thor Thayer 
---
 .../bindings/arm/altera/socfpga-eccmgr.txt |   14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 5a6b160..15eb0df 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -61,7 +61,9 @@ Required Properties:
 - #address-cells: must be 1
 - #size-cells: must be 1
 - interrupts : Should be single bit error interrupt, then double bit error
-   interrupt. Note the rising edge type.
+   interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt 
controller
+- #interrupt-cells : must be set to 2.
 - ranges : standard definition, should translate from local addresses
 
 Subcomponents:
@@ -70,11 +72,15 @@ L2 Cache ECC
 Required Properties:
 - compatible : Should be "altr,socfpga-a10-l2-ecc"
 - reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt, in this order.
 
 On-Chip RAM ECC
 Required Properties:
 - compatible : Should be "altr,socfpga-a10-ocram-ecc"
 - reg: Address and size for ECC block registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt, in this order.
 
 Example:
 
@@ -85,15 +91,21 @@ Example:
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 <0 0 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
ranges;
 
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
+   interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+<32 IRQ_TYPE_LEVEL_HIGH>;
};
 
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x90>;
+   interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+<33 IRQ_TYPE_LEVEL_HIGH> ;
};
};
-- 
1.7.9.5

[PATCH 3/5] EDAC, altera: Handle Arria10 SDRAM child node.

[tthayer]

From: Thor Thayer 

Separate the device match arrays for each platform to prevent
CycloneV matches when calling of_platform_populate() on the
Arria10 ECC manager node.
If the SDRAM is a child node of ECC manager, call probe function
via of_platform_populate().

Signed-off-by: Thor Thayer 
---
 drivers/edac/altera_edac.c |   20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 3eb73bc..dfd5d1b 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -688,11 +688,9 @@ static void altr_create_edacdev_dbgfs(struct 
edac_device_ctl_info *edac_dci,
 static const struct of_device_id altr_edac_device_of_match[] = {
 #ifdef CONFIG_EDAC_ALTERA_L2C
{ .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
-   { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
 #endif
 #ifdef CONFIG_EDAC_ALTERA_OCRAM
{ .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
-   { .compatible = "altr,socfpga-a10-ocram-ecc", .data = 
&a10_ocramecc_data },
 #endif
{},
 };
@@ -1054,6 +1052,17 @@ const struct edac_device_prv_data a10_l2ecc_data = {
 #endif /* CONFIG_EDAC_ALTERA_L2C */
 
 /* Arria10 EDAC Device Functions */
+static const struct of_device_id altr_edac_a10_device_of_match[] = {
+#ifdef CONFIG_EDAC_ALTERA_L2C
+   { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
+#endif
+#ifdef CONFIG_EDAC_ALTERA_OCRAM
+   { .compatible = "altr,socfpga-a10-ocram-ecc",
+ .data = &a10_ocramecc_data },
+#endif
+   {},
+};
+MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
 
 /*
  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
@@ -1123,7 +1132,7 @@ static int altr_edac_a10_device_add(struct 
altr_arria10_edac *edac,
const struct edac_device_prv_data *prv;
/* Get matching node and check for valid result */
const struct of_device_id *pdev_id =
-   of_match_node(altr_edac_device_of_match, np);
+   of_match_node(altr_edac_a10_device_of_match, np);
if (IS_ERR_OR_NULL(pdev_id))
return -ENODEV;
 
@@ -1324,6 +1333,11 @@ static int altr_edac_a10_probe(struct platform_device 
*pdev)
else if (of_device_is_compatible(child,
 "altr,socfpga-a10-ocram-ecc"))
altr_edac_a10_device_add(edac, child);
+   else if (of_device_is_compatible(child,
+"altr,sdram-edac-a10"))
+   of_platform_populate(pdev->dev.of_node,
+altr_sdram_ctrl_of_match,
+NULL, &pdev->dev);
}
 
return 0;
-- 
1.7.9.5

[PATCHv8 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

[tthayer]

From: Thor Thayer 

Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device  model. The SDRAM
controller is using the Memory Controller model.

Each type of ECC is individually configurable.

Signed-off-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
---
v8: Remove MASK from single bit mask names.
s/altr,edac/altr,socfpga-ecc-manager
Use debugfs instead of sysfs.
Add chip family name to match string.
Fix header year.
Fix build dependencies & change commit accordingly.
s/CONFIG_EDAC_ALTERA_MC/CONFIG_EDAC_ALTERA
v7: s/of_get_named_gen_pool/of_gen_pool_get
Remove #ifdef for EDAC_DEBUG
Use -ENODEV instead of EPROBE_DEFER
v6: Convert to nested EDAC in device tree. Force L2 cache
on for L2Cache ECC & remove L2 cache syscon for checking
enable bit. Update year in header.
v5: No change.
v4: Change mask defines to use BIT().
Fix comment style to agree with kernel coding style.
Better printk description for read != write in trigger.
Remove SysFS debugging message.
Better dci->mod_name
Move gen_pool pointer assignment to end of function.
Invert logic to reduce indent in ocram depenency check.
Change from dev_err() to edac_printk()
Replace magic numbers with defines & comments.
Improve error injection test.
Change Makefile intermediary name to altr (from alt)
v3: Move OCRAM and L2 cache EDAC functions into altera_edac.c
instead of separate files.
v2: Fix L2 dependency comments.
---
 drivers/edac/Kconfig   |   26 ++-
 drivers/edac/Makefile  |2 +-
 drivers/edac/altera_edac.c |  484 +++-
 3 files changed, 504 insertions(+), 8 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index ef25000..15a6df4 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -367,14 +367,30 @@ config EDAC_OCTEON_PCI
  Support for error detection and correction on the
  Cavium Octeon family of SOCs.
 
-config EDAC_ALTERA_MC
-   bool "Altera SDRAM Memory Controller EDAC"
+config EDAC_ALTERA
+   bool "Altera SOCFPGA ECC"
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
help
  Support for error detection and correction on the
- Altera SDRAM memory controller. Note that the
- preloader must initialize the SDRAM before loading
- the kernel.
+ Altera SOCs. This must be selected for SDRAM ECC.
+ Note that the preloader must initialize the SDRAM
+ before loading the kernel.
+
+config EDAC_ALTERA_L2C
+   bool "Altera L2 Cache ECC"
+   depends on EDAC_ALTERA=y
+   select CACHE_L2X0
+   help
+ Support for error detection and correction on the
+ Altera L2 cache Memory for Altera SoCs. This option
+  requires L2 cache so it will force that selection.
+
+config EDAC_ALTERA_OCRAM
+   bool "Altera On-Chip RAM ECC"
+   depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
+   help
+ Support for error detection and correction on the
+ Altera On-Chip RAM Memory for Altera SoCs.
 
 config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index be163e2..f9e4a3e 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -67,6 +67,6 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
 obj-$(CONFIG_EDAC_OCTEON_LMC)  += octeon_edac-lmc.o
 obj-$(CONFIG_EDAC_OCTEON_PCI)  += octeon_edac-pci.o
 
-obj-$(CONFIG_EDAC_ALTERA_MC)   += altera_edac.o
+obj-$(CONFIG_EDAC_ALTERA)  += altera_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)   += xgene_edac.o
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 9296409..728e736 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright Altera Corporation (C) 2014-2015. All rights reserved.
+ *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
  *  Copyright 2011-2012 Calxeda, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -17,8 +17,10 @@
  * Adapted from the highbank_mc_edac driver.
  */
 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -34,6 +36,7 @@
 
 #define EDAC_MOD_STR   "altera_edac"
 #define EDAC_VERSION   "1"
+#define EDAC_DEVICE"Altera"
 
 static const struct altr_sdram_prv_data c5_data = {
.ecc_ctrl_offset= CV_CTLCFG_OFST,
@@ -75,6 +78,31 @@ static const struct altr_sdram_prv_data a10_data = {
.ue_set_mask= A10_DIAGINT_TDERRA_MASK,
 };
 
+/** EDAC Device Defines **/
+
+/* OCRAM ECC Management Group Defines */
+#define ALTR_MAN_GRP_OCRAM_ECC_OFFSET   0x04
+#define ALTR_OCR_ECC_EN BIT(0)
+#define ALTR_OCR_ECC_INJS   BIT

[PATCHv8 4/4] ARM: socfpga: Enable OCRAM ECC on startup

[tthayer]

From: Dinh Nguyen 

This patch enables the ECC for On-Chip RAM on machine startup. The ECC
has to be enabled before data is stored in memory otherwise the ECC will
fail on reads.

Signed-off-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
---
v8: Address community comments on strings. Fix match strings based
on maintainer feedback. Update year in header.
v7: enable OCRAM ECC during platform init
v6: Implement OCRAM discovery changes from community. Add
of_node_put(). Remove be32_to_cpup(). Use __init() which
allows removal of .init_machine(). Update year in header.
---
 arch/arm/mach-socfpga/Makefile  |1 +
 arch/arm/mach-socfpga/core.h|1 +
 arch/arm/mach-socfpga/ocram.c   |   50 +++
 arch/arm/mach-socfpga/socfpga.c |3 +++
 4 files changed, 55 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/ocram.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e9ab7c9..ed15db1 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -6,3 +6,4 @@ obj-y   := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
 obj-$(CONFIG_SOCFPGA_SUSPEND)  += pm.o self-refresh.o
 obj-$(CONFIG_EDAC_ALTERA_L2C)  += l2_cache.o
+obj-$(CONFIG_EDAC_ALTERA_OCRAM)+= ocram.o
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index eb55d66..575195b 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -37,6 +37,7 @@
 extern void socfpga_init_clocks(void);
 extern void socfpga_sysmgr_init(void);
 void socfpga_init_l2_ecc(void);
+void socfpga_init_ocram_ecc(void);
 
 extern void __iomem *sys_manager_base_addr;
 extern void __iomem *rst_manager_base_addr;
diff --git a/arch/arm/mach-socfpga/ocram.c b/arch/arm/mach-socfpga/ocram.c
new file mode 100644
index 000..3791335
--- /dev/null
+++ b/arch/arm/mach-socfpga/ocram.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright Altera Corporation (C) 2016. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ALTR_OCRAM_CLEAR_ECC  0x0018
+#define ALTR_OCRAM_ECC_EN 0x0019
+
+void socfpga_init_ocram_ecc(void)
+{
+   struct device_node *np;
+   void __iomem *mapped_ocr_edac_addr;
+
+   /* Find the OCRAM EDAC device tree node */
+   np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
+   if (!np) {
+   pr_err("Unable to find socfpga-ocram-ecc\n");
+   return;
+   }
+
+   mapped_ocr_edac_addr = of_iomap(np, 0);
+   if (!mapped_ocr_edac_addr) {
+   of_node_put(np);
+   pr_err("Unable to map OCRAM ecc regs.\n");
+   return;
+   }
+
+   /* Clear any pending OCRAM ECC interrupts, then enable ECC */
+   writel(ALTR_OCRAM_CLEAR_ECC, mapped_ocr_edac_addr);
+   writel(ALTR_OCRAM_ECC_EN, mapped_ocr_edac_addr);
+
+   iounmap(mapped_ocr_edac_addr);
+   of_node_put(np);
+}
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index dd1ff07..7e0aad2 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -61,6 +61,9 @@ static void __init socfpga_init_irq(void)
socfpga_sysmgr_init();
if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
socfpga_init_l2_ecc();
+
+   if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
+   socfpga_init_ocram_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

[PATCHv8 2/4] ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries

[tthayer]

From: Thor Thayer 

Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html

Signed-off-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
---
v8: Fix node names to include chip family and use ecc manager
to better describe the driver. Rename socfpga-edac.txt to
socfpga-eccmgr.txt.
v7: No Change
v6: Change to nested EDAC device nodes based on community
feedback. Remove L2 syscon. Use consolidated binding.
v3-5: No Change
v2: Remove OCRAM declaration and reference prior patch.
---
 .../bindings/arm/altera/socfpga-eccmgr.txt |   49 
 arch/arm/boot/dts/socfpga.dtsi |   20 
 2 files changed, 69 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
new file mode 100644
index 000..4f45690
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -0,0 +1,49 @@
+Altera SoCFPGA ECC Manager
+This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
+The ECC Manager counts and corrects single bit errors and counts/handles
+double bit errors which are uncorrectable.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-ecc-manager"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+L2 Cache ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-l2-ecc"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+On Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-ocram-ecc"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt. Note the rising edge type.
+
+Example:
+
+   eccmgr: eccmgr@0xffd08140 {
+   compatible = "altr,socfpga-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   l2-ecc@ffd08140 {
+   compatible = "altr,socfpga-l2-ecc";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocram-ecc@ffd08144 {
+   compatible = "altr,socfpga-ocram-ecc";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+   };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 39c470e..9bb383e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -656,6 +656,26 @@
status = "disabled";
};
 
+   eccmgr: eccmgr@0xffd08140 {
+   compatible = "altr,socfpga-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   l2-ecc@ffd08140 {
+   compatible = "altr,socfpga-l2-ecc";
+   reg = <0xffd08140 0x4>;
+   interrupts = <0 36 1>, <0 37 1>;
+   };
+
+   ocram-ecc@ffd08144 {
+   compatible = "altr,socfpga-ocram-ecc";
+   reg = <0xffd08144 0x4>;
+   iram = <&ocram>;
+   interrupts = <0 178 1>, <0 179 1>;
+   };
+   };
+
L2: l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
-- 
1.7.9.5

[PATCHv8 3/4] ARM: socfpga: enable L2 cache ECC on startup

[tthayer]

From: Dinh Nguyen 

This patch enables the ECC for L2 cache on machine startup. The ECC has to
be enabled before data is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
---
v8: Address community suggestions for strings. Fix string based on
maintainer feedback. Update year in header.
v7: unmap locally scoped mapped_l2_edac_addr and add of_node_put(np)
v6: Remove pr_debug() & update year in header.
---
 arch/arm/mach-socfpga/Makefile   |1 +
 arch/arm/mach-socfpga/core.h |1 +
 arch/arm/mach-socfpga/l2_cache.c |   43 ++
 arch/arm/mach-socfpga/socfpga.c  |2 ++
 4 files changed, 47 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index b8f9e23..e9ab7c9 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -5,3 +5,4 @@
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
 obj-$(CONFIG_SOCFPGA_SUSPEND)  += pm.o self-refresh.o
+obj-$(CONFIG_EDAC_ALTERA_L2C)  += l2_cache.o
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 5bc6ea8..eb55d66 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -36,6 +36,7 @@
 
 extern void socfpga_init_clocks(void);
 extern void socfpga_sysmgr_init(void);
+void socfpga_init_l2_ecc(void);
 
 extern void __iomem *sys_manager_base_addr;
 extern void __iomem *rst_manager_base_addr;
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 000..d390602
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright Altera Corporation (C) 2016. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+void socfpga_init_l2_ecc(void)
+{
+   struct device_node *np;
+   void __iomem *mapped_l2_edac_addr;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
+   if (!np) {
+   pr_err("Unable to find socfpga-l2-ecc in dtb\n");
+   return;
+   }
+
+   mapped_l2_edac_addr = of_iomap(np, 0);
+   if (!mapped_l2_edac_addr) {
+   of_node_put(np);
+   pr_err("Unable to find L2 ECC mapping in dtb\n");
+   return;
+   }
+
+   /* Enable ECC */
+   writel(0x01, mapped_l2_edac_addr);
+   iounmap(mapped_l2_edac_addr);
+
+   of_node_put(np);
+}
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index a1c0efa..dd1ff07 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -59,6 +59,8 @@ static void __init socfpga_init_irq(void)
 {
irqchip_init();
socfpga_sysmgr_init();
+   if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
+   socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

[PATCH] EDAC: Use edac_debugfs_remove_recursive() in edac_debugfs_exit()

[tthayer]

From: Thor Thayer 

debugfs_remove() is used to remove a file or a directory from the
debugfs filesystem on an EDAC device exit. However edac_debugfs
might not be empty. This is similar to another patch [1] that
changed the EDAC MCI code to use edac_debugfs_remove_recursive().

[1] https://lkml.org/lkml/2015/10/13/974

Suggested-by: Borislav Petkov 
Signed-off-by: Thor Thayer 
---
---
 drivers/edac/debugfs.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/debugfs.c b/drivers/edac/debugfs.c
index 54d2f66..92dbb7e 100644
--- a/drivers/edac/debugfs.c
+++ b/drivers/edac/debugfs.c
@@ -53,7 +53,7 @@ int __init edac_debugfs_init(void)
 
 void edac_debugfs_exit(void)
 {
-   debugfs_remove(edac_debugfs);
+   debugfs_remove_recursive(edac_debugfs);
 }
 
 int edac_create_debugfs_nodes(struct mem_ctl_info *mci)
-- 
1.7.9.5

[PATCHv5 1/5] arm: socfpga: Enable L2 Cache ECC on startup.

[tthayer]

From: Thor Thayer 

This patch enables the ECC for L2 cache on machine
startup.  The ECC has to be enabled before data is
is stored in memory otherwise the ECC will fail on
reads.

Signed-off-by: Thor Thayer 
---
v2: Split OCRAM initialization into separate patch.

v3/4: No change

v5: Remove l2cache.h, use io.h instead of clk-provider.h
Make copyright header inclusive. Remove MAINTAINERS entry.
---
 arch/arm/mach-socfpga/Makefile   |1 +
 arch/arm/mach-socfpga/core.h |2 ++
 arch/arm/mach-socfpga/l2_cache.c |   41 ++
 arch/arm/mach-socfpga/socfpga.c  |4 +++-
 4 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/l2_cache.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 6dd7a93..142609e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,3 +4,4 @@
 
 obj-y  := socfpga.o
 obj-$(CONFIG_SMP)  += headsmp.o platsmp.o
+obj-$(CONFIG_EDAC_ALTERA_L2C) += l2_cache.o
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f7..385baba 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -44,4 +44,6 @@ extern unsigned long cpu1start_addr;
 
 #define SOCFPGA_SCU_VIRT_BASE   0xfffec000
 
+void socfpga_init_l2_ecc(void);
+
 #endif
diff --git a/arch/arm/mach-socfpga/l2_cache.c b/arch/arm/mach-socfpga/l2_cache.c
new file mode 100644
index 000..3461745
--- /dev/null
+++ b/arch/arm/mach-socfpga/l2_cache.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include 
+#include 
+#include 
+
+void socfpga_init_l2_ecc(void)
+{
+   struct device_node *np;
+   void __iomem  *mapped_l2_edac_addr;
+
+   np = of_find_compatible_node(NULL, NULL, "altr,l2-edac");
+   if (!np) {
+   pr_err("SOCFPGA: Unable to find altr,l2-edac in dtb\n");
+   return;
+   }
+
+   mapped_l2_edac_addr = of_iomap(np, 0);
+   if (!mapped_l2_edac_addr) {
+   pr_err("SOCFPGA: Unable to find L2 ECC mapping in dtb\n");
+   return;
+   }
+
+   /* Enable ECC */
+   writel(0x01, mapped_l2_edac_addr);
+
+   pr_debug("SOCFPGA: Success Initializing L2 cache ECC\n");
+}
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf383..0954011 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2012 Altera Corporation
+ *  Copyright (C) 2012-2014 Altera Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -83,6 +83,8 @@ static void __init socfpga_init_irq(void)
 {
irqchip_init();
socfpga_sysmgr_init();
+   if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
+   socfpga_init_l2_ecc();
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
-- 
1.7.9.5

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