[PATCH v0] clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
From: Levin Du
PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.
But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.
By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.
This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.
Signed-off-by: Levin Du
---
drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 2a8634a..5a62814 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1523,6 +1523,7 @@ static const char *const rk3399_pmucru_critical_clocks[]
__initconst = {
"pclk_pmu_src",
"fclk_cm0s_src_pmu",
"clk_timer_src_pmu",
+ "pclk_rkpwm_pmu",
};
static void __init rk3399_clk_init(struct device_node *np)
--
2.7.4
[PATCH v1] arm64: dts: rockchip: add support for ROC-RK3399-PC board
From: Levin Du
ROC-RK3399-PC is a power efficient 4GB LPDDR4 single board
computer with USB 3.0 and Gigabit Ethernet in a form factor
compatible with the Raspberry Pi. It is based on the Rockchip
RK3399 SoC, powered by the Type-C port.
The devicetree currently supports peripherals of:
- Ethernet
- HDMI
- SD Card
- UART2 debug
- TYPE-C
- eMMC
USB3 in type-c port currently only works with normal orientation,
not flip one.
Signed-off-by: Levin Du
---
Changes in v1:
- remove bootargs
- use interpolation for brightness level
- add vcc_vbus_typec1 regulator
- fix phy-supply of u2phy0_otg and u2phy1_otg
- remove vcc_hub_en dummy regualtor
- add hub_rst (changed to output high) to pinctrl status of vcc5v0_host
- remove vsel-gpios props in fan53xx
- remove mp8859 in i2c
- fusb302: fix interrupt setting
- fusb302: add vbus-supply
- remove extcon in tcphy0 and tcphy1
- remove #sound-dai-cells in i2s*
- use RK_PXX style bit number for cd-gpios in SDMMC
- clean commented status lines
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 687 +
3 files changed, 692 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt
b/Documentation/devicetree/bindings/arm/rockchip.txt
index acfd3c7..ab5fde8 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -59,6 +59,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+- Firefly ROC-RK3399-PC board:
+Required root node properties:
+ - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index b0092d9..06028db 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
new file mode 100644
index 000..7d41a91
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Board";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+
+ brightness-levels = <0 255>;
+ default-brightness-level = <200>;
+ num-interpolated-steps = <1>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_vbus_typec0: vcc-vbus-typec0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_vbus_typec0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ /*
+* should be placed inside mp8859, but not until mp8859 has
+* its own dt-binding.
+*/
+ vcc12v_sys: mp8859-dcdc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_sys";
+ regulator-always-on;
+ regulator-boot-on;
+
Re: [PATCH v1] arm64: dts: rockchip: add support for ROC-RK3399-PC board
Ezequiel Garcia writes: > On Thu, 2018-07-26 at 15:13 +0800, d...@t-chip.com.cn wrote: >> From: Levin Du >> >> ROC-RK3399-PC is a power efficient 4GB LPDDR4 single board >> computer with USB 3.0 and Gigabit Ethernet in a form factor >> compatible with the Raspberry Pi. It is based on the Rockchip >> RK3399 SoC, powered by the Type-C port. >> >> The devicetree currently supports peripherals of: >> >> - Ethernet >> - HDMI >> - SD Card >> - UART2 debug >> - TYPE-C > > Hi Levin, > > Last time I tried to make the mainline fusb driver work, it really didn't. > Is USB 3.0 Type-C actually working with mainline on this board? > > Thanks! > Eze That's what I added in the end: USB3 in type-c port currently only works with normal orientation, not flip one. Adding 'extcon=<&fusb0>' to make the dwc3 core failed to initialize. Regards, Levin
[PATCH v2] arm64: dts: rockchip: add support for ROC-RK3399-PC board
From: Levin Du
ROC-RK3399-PC is a power efficient 4GB LPDDR4 single board
computer with USB 3.0 and Gigabit Ethernet in a form factor
compatible with the Raspberry Pi. It is based on the Rockchip
RK3399 SoC, powered by the Type-C port.
The devicetree currently supports peripherals of:
- Ethernet
- HDMI
- SD Card
- UART2 debug
- Type-C
- eMMC
USB3 in Type-C port currently only works with normal orientation,
not flip one.
Signed-off-by: Levin Du
---
Changes in v2:
- remove custom brightness-levels (use calculated one in pwm_bl driver)
- remove redundant 'dr_mode="otg"' in usbdrd_dwc3_0
Changes in v1:
- remove bootargs
- use interpolation for brightness level
- add vcc_vbus_typec1 regulator
- fix phy-supply of u2phy0_otg and u2phy1_otg
- remove vcc_hub_en dummy regualtor
- add hub_rst (changed to output high) to pinctrl status of vcc5v0_host
- remove vsel-gpios props in fan53xx
- remove mp8859 in i2c
- fusb302: fix interrupt setting
- fusb302: add vbus-supply
- remove extcon in tcphy0 and tcphy1
- remove #sound-dai-cells in i2s*
- use RK_PXX style bit number for cd-gpios in SDMMC
- clean commented status lines
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 682 +
3 files changed, 687 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt
b/Documentation/devicetree/bindings/arm/rockchip.txt
index acfd3c7..ab5fde8 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -59,6 +59,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+- Firefly ROC-RK3399-PC board:
+Required root node properties:
+ - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index b0092d9..06028db 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
new file mode 100644
index 000..13dc99c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
@@ -0,0 +1,682 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Board";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+ chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm0 0 25000 0>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk808 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+* On the module itself this is one of these (depending
+* on the actual card populated):
+* - SDIO_RESET_L_WL_REG_ON
+* - PDN (power down when low)
+*/
+ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc_vbus_typec0: vcc-vbus-typec0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_vbus_typec0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ /*
+* should be placed inside mp8859, but not until mp8859 has
+* its own dt-binding.
+*/
+ vcc12v_sys: mp8859-dcdc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_sys";
+ regulator-always-on;
+ regulator-boot-on;
+
[PATCH v0] arm64: dts: rockchip: add support for ROC-RK3399-PC board
From: Levin Du
ROC-RK3399-PC is the first power efficient 4GB DDR4 single board
computer with USB 3.0 and Gigabit Ethernet in a form factor compatible
with the Raspberry Pi. It is based on the Rockchip RK3399 SoC, powered
by the Type-C port.
The devicetree currently supports peripherals of:
- Ethernet
- HDMI
- SD Card
- UART2 debug
- USB3
- eMMC
Signed-off-by: Levin Du
---
Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts | 717 +
3 files changed, 722 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt
b/Documentation/devicetree/bindings/arm/rockchip.txt
index acfd3c7..ab5fde8 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -59,6 +59,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+- Firefly ROC-RK3399-PC board:
+Required root node properties:
+ - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
diff --git a/arch/arm64/boot/dts/rockchip/Makefile
b/arch/arm64/boot/dts/rockchip/Makefile
index b0092d9..06028db 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
new file mode 100644
index 000..207f2e3
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
@@ -0,0 +1,717 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3399-PC Board";
+ compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32,0xff1a swiotlb=1";
+ stdout-path = "serial2:150n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pwms = <&pwm0 0 25000 0>;
+ brightness-levels = <
+ 0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100 101 102 103
+ 104 105 106 107 108 109 110 111
+ 112 113 114 115 116 117 118 119
+ 120 121 122 123 124 125 126 127
+ 128 129 130 131 132 133 134 135
+ 136 137 138 139 140 141 142 143
+ 144 145 146 147 148 149 150 151
+ 152 153 154 155 156 157 158 159
+ 160 161 162 163 164 165 166 167
+ 168 169 170 171 172 173 174 175
+ 176 177 178 179 180 181 182 183
+ 184 185 186 187 188 189 190 191
+ 192 193 194 195 196 197 198 199
+ 200 201 202 203 204 205 206 207
+ 208 209 210 211 212 213 214 215
+ 216 217 218 219 220 221 222 223
+ 224 225 226 227 228 229 230 231
+ 232 233 234 235 236 237 238 239
+ 240 241 242 243 244 245 246 247
+ 248 249 250 251 252 253 254 255>;
+ default-brightness-level = <200>;
+ };
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0
[PATCH v4 2/4] arm64: dts: rockchip: add GRF GPIO controller to rk3328
From: Levin Du
Adding a GRF GPIO controller labled "grf_gpio" to rk3328, currently
providing access to the GPIO_MUTE pin, which is manupulated by the
GRF_SOC_CON10 register.
The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
Signed-off-by: Levin Du
---
Changes in v4:
- Use binding of "rockchip,rk3328-grf-gpio"
Changes in v3:
- Use dedicated "rockchip,rk3328-gpio-mute" driver
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328.dtsi
Changes in v1:
- Split from V0 and add to rk3328.dtsi for general use.
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 3f5a294..bf5656d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -275,6 +275,12 @@
mode-loader = ;
};
+ grf_gpio: grf-gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
};
uart0: serial@ff11 {
--
2.7.4
[PATCH v4 0/4] Add sdmmc UHS support to ROC-RK3328-CC board.
From: Levin Du Hi all, this is an attemp to add sdmmc UHS support to the ROC-RK3328-CC board. This patch series adds a new compatible `rockchip,rk3328-grf-gpio` to the gpio-syscon driver, which currently only support for the access of the GPIO_MUTE pin in RK3328. Support for HDMI pins can be added later on perhaps by writing a standalone driver. A new GRF GPIO controller named `grf_gpio` is defined in rk3328.dtsi so that all RK3328 boards has access to it. The ROC-RK3328-CC board use the new gpio <&grf_gpio 0> in gpio-regulator to control the signal voltage of the sdmmc. It is essential for UHS support which requires 1.8V signal voltage. Many thanks to the Linux people! Changes in v4: - Use binding of "rockchip,rk3328-grf-gpio" - Use <&grf_gpio 0> to refer to the GPIO_MUTE pin. Changes in v3: - Change from general gpio-syscon to specific rk3328-gpio-mute - Use dedicated "rockchip,rk3328-gpio-mute" driver - Use <&gpio_mute 0> instead of <&gpio_mute 1> to refer to the GPIO_MUTE pin. Changes in v2: - Rename gpio_syscon10 to gpio_mute in doc - Rename gpio_syscon10 to gpio_mute in rk3328.dtsi - Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts Changes in v1: - Refactured for general gpio-syscon usage for Rockchip SoCs. - Add doc rockchip,gpio-syscon.txt - Split from V0 and add to rk3328.dtsi for general use. - Split from V0. - Split into small patches - Sort dts properties in sdmmc node Levin Du (4): gpio: syscon: rockchip: add GRF GPIO support for rk3328 arm64: dts: rockchip: add GRF GPIO controller to rk3328 arm64: dts: rockchip: add io-domain to roc-rk3328-cc arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc .../bindings/gpio/rockchip,rk3328-grf-gpio.txt | 32 arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 34 ++ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 drivers/gpio/gpio-syscon.c | 31 4 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt -- 2.7.4
[PATCH v4 1/4] gpio: syscon: rockchip: add GRF GPIO support for rk3328
From: Levin Du
In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec
mute control, can also be used for general purpose. It is manipulated by
the GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI
pins can also be set in the same way.
Currently this GRF GPIO controller only supports the mute pin. If needed
in the future, the HDMI pins support can also be added.
Signed-off-by: Levin Du
---
Changes in v4:
- Rename the GPIO binding to "rockchip,rk3328-grf-gpio"
Changes in v3:
- Change from general gpio-syscon to specific rk3328-gpio-mute
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in doc
Changes in v1:
- Refactured for general gpio-syscon usage for Rockchip SoCs.
- Add doc rockchip,gpio-syscon.txt
.../bindings/gpio/rockchip,rk3328-grf-gpio.txt | 32 ++
drivers/gpio/gpio-syscon.c | 31 +
2 files changed, 63 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt
diff --git
a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt
b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt
new file mode 100644
index 000..f9231df
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-grf-gpio.txt
@@ -0,0 +1,32 @@
+Rockchip RK3328 GRF (General Register Files) GPIO controller.
+
+In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
+control, can also be used for general purpose. It is manipulated by the
+GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can
+also be set in the same way.
+
+Currently this GPIO controller only supports the mute pin. If needed in the
+future, the HDMI pins support can also be added.
+
+Required properties:
+- compatible: Should contain "rockchip,rk3328-grf-gpio".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be 2. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+0 = Active high,
+1 = Active low.
+
+Example:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+
+ grf_gpio: grf-gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+Note: The grf_gpio node should be declared as the child of the GRF (General
+Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 8b0a69c..b9b5842 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -135,6 +135,33 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio =
{
.dat_bit_offset = 0x40 * 8 + 8,
};
+static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int val)
+{
+ struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
+ unsigned int offs;
+ u8 bit;
+ u32 data;
+ int ret;
+
+ offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
+ bit = offs % SYSCON_REG_BITS;
+ data = (val ? BIT(bit) : 0) | BIT(bit + 16);
+ ret = regmap_write(priv->syscon,
+ (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
+ data);
+ if (ret < 0)
+ dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+}
+
+static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
+ /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
+ .flags = GPIO_SYSCON_FEAT_OUT,
+ .bit_count = 1,
+ .dat_bit_offset = 0x0428 * 8 + 1,
+ .set= rockchip_gpio_set,
+};
+
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -175,6 +202,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
+ {
+ .compatible = "rockchip,rk3328-grf-gpio",
+ .data = &rockchip_rk3328_gpio_mute,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
--
2.7.4
[PATCH v4 3/4] arm64: dts: rockchip: add io-domain to roc-rk3328-cc
From: Levin Du
It is necessary for the io domain setting of the SoC to match the voltage
supplied by the regulators.
Signed-off-by: Levin Du
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
Changes in v1:
- Split from V0.
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..b983abd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -208,6 +208,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
--
2.7.4
[PATCH v4 4/4] arm64: dts: rockchip: add sdmmc UHS support for roc-rk3328-cc
From: Levin Du
In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by the
vcc_sdio regulator, which is a mux between 1.8V and 3.3V, controlled by
a special output only gpio pin labeled "gpiomut_pmuio_iout",
corresponding bit 1 of the syscon GRF_SOC_CON10.
This special pin can now be reference as <&grf_gpio 0>, thanks to the
gpio-syscon driver, which makes writing regulator-gpio possible.
If the signal voltage changes, the io domain needs to change
correspondingly.
To use this feature, the following options are required in kernel config:
- CONFIG_GPIO_SYSCON=y
- CONFIG_POWER_AVS=y
- CONFIG_ROCKCHIP_IODOMAIN=y
Signed-off-by: Levin Du
---
Changes in v4:
- Use <&grf_gpio 0> to refer to the GPIO_MUTE pin.
Changes in v3:
- Use <&gpio_mute 0> instead of <&gpio_mute 1> to refer to the GPIO_MUTE pin.
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts
Changes in v1:
- Split into small patches
- Sort dts properties in sdmmc node
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index b983abd..1edb39a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
vin-supply = <&vcc_io>;
};
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -213,7 +226,7 @@
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
+ vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
@@ -242,7 +255,12 @@
max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
@@ -277,3 +295,7 @@
&usb_host0_ohci {
status = "okay";
};
+
+&grf_gpio {
+ status = "okay";
+};
--
2.7.4
Re: [PATCH v0] arm64: dts: rockchip: add support for ROC-RK3399-PC board
Hi Heiko,
Heiko Stuebner writes:
> Hi Levin,
>
> Am Samstag, 21. Juli 2018, 10:30:26 CEST schrieb d...@t-chip.com.cn:
>> From: Levin Du
>>
>> ROC-RK3399-PC is the first power efficient 4GB DDR4 single board
>
> maybe "is a power efficient" instead of "the first" ;-)
>
> [...]
>
ok :)
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> new file mode 100644
>> index 000..207f2e3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> @@ -0,0 +1,717 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
>> + */
>> +
>> +/dts-v1/;
>> +#include
>> +#include "rk3399.dtsi"
>> +#include "rk3399-opp.dtsi"
>> +
>> +/ {
>> +model = "Firefly ROC-RK3399-PC Board";
>> +compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
>> +
>> +chosen {
>> +bootargs = "earlycon=uart8250,mmio32,0xff1a swiotlb=1";
>
> I don't think we want to hard-code linux bootargs in the generic devicetree
>
removed. though I think that earlycon is useful in debugging.
>> +stdout-path = "serial2:150n8";
>> +};
>> +
>> +backlight: backlight {
>> +compatible = "pwm-backlight";
>> +enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
>> +pwms = <&pwm0 0 25000 0>;
>> +brightness-levels = <
>> + 0 1 2 3 4 5 6 7
>
> As Rob noted in the px30 evb patch, there is now a property helping
> to drop these long lists of brightness levels, see
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=1e5e7cc794b5a332c23216dade0a2e937d694b7f
adapted.
>> + 8 9 10 11 12 13 14 15
>> + 16 17 18 19 20 21 22 23
>> + 24 25 26 27 28 29 30 31
>> + 32 33 34 35 36 37 38 39
>> + 40 41 42 43 44 45 46 47
>> + 48 49 50 51 52 53 54 55
>> + 56 57 58 59 60 61 62 63
>> + 64 65 66 67 68 69 70 71
>> + 72 73 74 75 76 77 78 79
>> + 80 81 82 83 84 85 86 87
>> + 88 89 90 91 92 93 94 95
>> + 96 97 98 99 100 101 102 103
>> +104 105 106 107 108 109 110 111
>> +112 113 114 115 116 117 118 119
>> +120 121 122 123 124 125 126 127
>> +128 129 130 131 132 133 134 135
>> +136 137 138 139 140 141 142 143
>> +144 145 146 147 148 149 150 151
>> +152 153 154 155 156 157 158 159
>> +160 161 162 163 164 165 166 167
>> +168 169 170 171 172 173 174 175
>> +176 177 178 179 180 181 182 183
>> +184 185 186 187 188 189 190 191
>> +192 193 194 195 196 197 198 199
>> +200 201 202 203 204 205 206 207
>> +208 209 210 211 212 213 214 215
>> +216 217 218 219 220 221 222 223
>> +224 225 226 227 228 229 230 231
>> +232 233 234 235 236 237 238 239
>> +240 241 242 243 244 245 246 247
>> +248 249 250 251 252 253 254 255>;
>> +default-brightness-level = <200>;
>> +};
>
> [...]
>
>> +vcc_vbus_typec0: vcc-vbus-typec0 {
>> +compatible = "regulator-fixed";
>> +regulator-name = "vcc_vbus_typec0";
>> +regulator-always-on;
>> +regulator-boot-on;
>> +regulator-min-microvolt = <500>;
>> +regulator-max-microvolt = <500>;
>> +};
>> +
>> +vcc12v_sys: mp8859-dcdc1 {
>
> The mp8859 seems to be an i2c-device, as also shown by the
> nearly empty mp8859 entry below, so shouldn't this regulator
> be defined there?
Question here. Since mp8859 driver is not mainlined yet. Shall I leave
the regulator here (mp8859 defaults to output 5V) and remove the
mp8859 from the i2c?
>
>
>> +compatible = "regulator-fixed";
>> +regulator-name = "vcc12v_sys";
>> +regulator-always-on;
>> +regulator-boot-on;
>> +regulator-min-microvolt = <1200>;
>> +regulator-max-microvolt = <1200>;
>> +vin-supply = <&vcc_vbus_typec0>;
>> +};
>
> [...]
>
>> +vcc_hub_en: vcc_hub_en-regulator {
>> +compatible = "regulator-fixed";
>> +enable-active-high;
>> +gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
>> +pinctrl-names = "default";
>> +pinctrl-0 = <&hub_rst>;
>> +regulator-name = "vcc_hub_en";
>> +regulator-always-on;
>
> missing vin-supply
This just comes in need of setting GPIO2_A4
Re: [PATCH v0] arm64: dts: rockchip: add support for ROC-RK3399-PC board
Enric Balletbo Serra writes:
> Hi Levin,
>
> Missatge de Heiko Stuebner del dia dt., 24 de jul.
> 2018 a les 11:29:
>>
>> Hi Levin,
>>
>> Am Samstag, 21. Juli 2018, 10:30:26 CEST schrieb d...@t-chip.com.cn:
>> > From: Levin Du
>> >
>> > ROC-RK3399-PC is the first power efficient 4GB DDR4 single board
>>
>> maybe "is a power efficient" instead of "the first" ;-)
>>
>> [...]
>>
>> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> > b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> > new file mode 100644
>> > index 000..207f2e3
>> > --- /dev/null
>> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
>> > @@ -0,0 +1,717 @@
>> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> > +/*
>> > + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
>> > + */
>> > +
>> > +/dts-v1/;
>> > +#include
>> > +#include "rk3399.dtsi"
>> > +#include "rk3399-opp.dtsi"
>> > +
>> > +/ {
>> > + model = "Firefly ROC-RK3399-PC Board";
>> > + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
>> > +
>> > + chosen {
>> > + bootargs = "earlycon=uart8250,mmio32,0xff1a swiotlb=1";
>>
>> I don't think we want to hard-code linux bootargs in the generic devicetree
>>
>> > + stdout-path = "serial2:150n8";
>> > + };
>> > +
>> > + backlight: backlight {
>> > + compatible = "pwm-backlight";
>> > + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
>> > + pwms = <&pwm0 0 25000 0>;
>> > + brightness-levels = <
>> > + 0 1 2 3 4 5 6 7
>>
>> As Rob noted in the px30 evb patch, there is now a property helping
>> to drop these long lists of brightness levels, see
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=1e5e7cc794b5a332c23216dade0a2e937d694b7f
>
> Adding to the Heiko information. Did you try to just remove brightness-levels?
> Without this property, the driver computes a default table with the
> brightness levels filled with the numbers provided by the CIE 1931
> algorithm. That algorithm is used to dim a led for human perception.
>
> Note that the patches needed did not land yet, are in linux-next, and
> you will also be interested in apply this patch [1].
>
> [1] https://lkml.org/lkml/2018/7/24/116
>
>
> Best regards,
> Enric
>
Thanks you for the note, Enric. I'll test that later.
Regards,
Levin
Re: [PATCH v3 2/5] gpio: syscon: rockchip: add GPIO_MUTE support for rk3328
Levin writes:
> Rob Herring writes:
>
>> On Sat, Jun 02, 2018 at 04:40:09PM +0800, Levin Du wrote:
>>>
>>> Rob Herring writes:
>>>
>>> > On Thu, May 31, 2018 at 9:05 PM, Levin wrote:
>>> > > Hi Rob,
>>> > >
>>> > >
>>> > > On 2018-05-31 10:45 PM, Rob Herring wrote:
>>> > > >
>>> > > > On Wed, May 30, 2018 at 10:27 PM, wrote:
>>> > > > >
>>> > > > > From: Levin Du
>>> > > > >
>>> > > > > In Rockchip RK3328, the output only GPIO_MUTE pin,
>>> > > > > originally for codec
>>> > > > > mute control, can also be used for general purpose. It is
>>> > > > > manipulated by
>>> > > > > the GRF_SOC_CON10 register.
>>> > > > >
>>> > > > > Signed-off-by: Levin Du
>>> > > > >
>>> > > > > ---
>>> > > > >
>>> > > > > Changes in v3:
>>> > > > > - Change from general gpio-syscon to specific
>>> > > > > rk3328-gpio-mute
>>> > > > >
>>> > > > > Changes in v2:
>>> > > > > - Rename gpio_syscon10 to gpio_mute in doc
>>> > > > >
>>> > > > > Changes in v1:
>>> > > > > - Refactured for general gpio-syscon usage for Rockchip SoCs.
>>> > > > > - Add doc rockchip,gpio-syscon.txt
>>> > > > >
>>> > > > > .../bindings/gpio/rockchip,rk3328-gpio-mute.txt| 28
>>> > > > > +++
>>> > > > > drivers/gpio/gpio-syscon.c | 31
>>> > > > > ++
>>> > > > > 2 files changed, 59 insertions(+)
>>> > > > > create mode 100644
>>> > > > > Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>>> > > > >
>>> > > > > diff --git
>>> > > > > a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>>> > > > > b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>>> > > > > new file mode 100644
>>> > > > > index 000..10bc632
>>> > > > > --- /dev/null
>>> > > > > +++
>>> > > > > b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>>> > > > > @@ -0,0 +1,28 @@
>>> > > > > +Rockchip RK3328 GPIO controller dedicated for the GPIO_MUTE
>>> > > > > pin.
>>> > > > > +
>>> > > > > +In Rockchip RK3328, the output only GPIO_MUTE pin,
>>> > > > > originally for codec
>>> > > > > mute
>>> > > > > +control, can also be used for general purpose. It is
>>> > > > > manipulated by the
>>> > > > > +GRF_SOC_CON10 register.
>>> > > > > +
>>> > > > > +Required properties:
>>> > > > > +- compatible: Should contain "rockchip,rk3328-gpio-mute".
>>> > > > > +- gpio-controller: Marks the device node as a gpio
>>> > > > > controller.
>>> > > > > +- #gpio-cells: Should be 2. The first cell is the pin
>>> > > > > number and
>>> > > > > + the second cell is used to specify the gpio polarity:
>>> > > > > +0 = Active high,
>>> > > > > +1 = Active low.
>>> > > > > +
>>> > > > > +Example:
>>> > > > > +
>>> > > > > + grf: syscon@ff10 {
>>> > > > > + compatible = "rockchip,rk3328-grf", "syscon",
>>> > > > > "simple-mfd";
>>> > > > > +
>>> > > > > + gpio_mute: gpio-mute {
>>> > > >
>>> > > > Node names should be generic:
>>> > > >
>>> > > > gpio {
>>> > > >
>>> > > > This also means you can't add another GPIO node in the future
>>> > > > and
>>> > > > you'll have to live with "rockchip,rk3328-gpio-mute" covering
>>> > > > more
>>> > > > than 1 GPIO if you do need to add more GPIOs.
>>> > >
>>> > >
>>> > > As the first line describes, this GPIO controller is dedicated for
>>> > > the
>>> > > GPIO_MUTE pin.
>>> > > There's only one GPIO pin in the GRF_SOC_CON10 register. Therefore
>>> > > the
>>> > > gpio_mute
>>> > > name is proper IMHO.
>>> >
>>> > It's how many GPIOs in the GRF, not this register. What I'm saying is
>>> > when you come along later to add another GPIO in the GRF, you had
>>> > better just add it to this same node. I'm not going to accept another
>>> > GPIO controller node within the GRF. You have the cells to support
>>> > more than 1, so it would only be a driver change. The compatible
>>> > string would then not be ideally named at that point. But compatible
>>> > strings are just unique identifiers, so it doesn't really matter what
>>> > the string is.
>>> >
>>>
>>> I'll try my best to introduce the situation here. The GRF, GPIO0~GPIO3
>>> are register blocks in the RK3328 Soc. The GPIO0~GPIO3 contain registers
>>> for GPIO operations like reading/writing data, setting direction,
>>> interruption etc, which corresponds to the GPIO banks (gpio0~gpio3)
>>> defined in rk3328.dtsi:
>>
>> I'm only talking about GRF functions, not "regular" GPIOs.
>>
>>> pinctrl: pinctrl {
>>> compatible = "rockchip,rk3328-pinctrl";
>>> rockchip,grf = <&grf>;
>>> #address-cells = <2>;
>>> #size-cells = <2>;
>>> ranges;
>>>
>>> gpio0: gpio0@ff21 {
>>> compatible = "rockchip,gpio-bank";
>>> reg = <0x0 0xff21 0x0 0x100>;
>>> interrupts = >> IRQ_TYPE_LEVEL_HIGH>;
>>> clocks = <&cru PCLK_GPIO0>;
>>>
>>> gpio-con
[PATCH v3 2/5] gpio: syscon: rockchip: add GPIO_MUTE support for rk3328
From: Levin Du
In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec
mute control, can also be used for general purpose. It is manipulated by
the GRF_SOC_CON10 register.
Signed-off-by: Levin Du
---
Changes in v3:
- Change from general gpio-syscon to specific rk3328-gpio-mute
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in doc
Changes in v1:
- Refactured for general gpio-syscon usage for Rockchip SoCs.
- Add doc rockchip,gpio-syscon.txt
.../bindings/gpio/rockchip,rk3328-gpio-mute.txt| 28 +++
drivers/gpio/gpio-syscon.c | 31 ++
2 files changed, 59 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
diff --git
a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
new file mode 100644
index 000..10bc632
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
@@ -0,0 +1,28 @@
+Rockchip RK3328 GPIO controller dedicated for the GPIO_MUTE pin.
+
+In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
+control, can also be used for general purpose. It is manipulated by the
+GRF_SOC_CON10 register.
+
+Required properties:
+- compatible: Should contain "rockchip,rk3328-gpio-mute".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be 2. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+0 = Active high,
+1 = Active low.
+
+Example:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+
+ gpio_mute: gpio-mute {
+ compatible = "rockchip,rk3328-gpio-mute";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+Note: The gpio_mute node should be declared as the child of the GRF (General
+Register File) node. The GPIO_MUTE pin is referred to as <&gpio_mute 0>.
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 7325b86..49a142a 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -135,6 +135,33 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio =
{
.dat_bit_offset = 0x40 * 8 + 8,
};
+static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int val)
+{
+ struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
+ unsigned int offs;
+ u8 bit;
+ u32 data;
+ int ret;
+
+ offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
+ bit = offs % SYSCON_REG_BITS;
+ data = (val ? BIT(bit) : 0) | BIT(bit + 16);
+ ret = regmap_write(priv->syscon,
+ (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
+ data);
+ if (ret < 0)
+ dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+}
+
+static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
+ /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
+ .flags = GPIO_SYSCON_FEAT_OUT,
+ .bit_count = 1,
+ .dat_bit_offset = 0x0428 * 8 + 1,
+ .set= rockchip_gpio_set,
+};
+
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -175,6 +202,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
+ {
+ .compatible = "rockchip,rk3328-gpio-mute",
+ .data = &rockchip_rk3328_gpio_mute,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
--
2.7.4
[PATCH v3 3/5] arm64: dts: rockchip: Add GPIO_MUTE pin support to rk3328
From: Levin Du
Adding a new gpio controller named "gpio_mute" to rk3328, providing
access to the GPIO_MUTE pin, which is manupulated by the GRF_SOC_CON10
register.
The GPIO_MUTE pin is referred to as <&gpio_mute 0>.
Signed-off-by: Levin Du
---
Changes in v3:
- Use dedicated "rockchip,rk3328-gpio-mute" driver
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328.dtsi
Changes in v1:
- Split from V0 and add to rk3328.dtsi for general use.
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index be2bfbc..2ee0fa3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -309,6 +309,13 @@
mode-loader = ;
};
+ /* Use <&gpio_mute 0> to refer to GPIO_MUTE pin */
+ gpio_mute: gpio-mute {
+ compatible = "rockchip,rk3328-gpio-mute";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
};
uart0: serial@ff11 {
--
2.7.4
[PATCH v3 1/5] gpio: syscon: allow fetching syscon from parent node
From: Heiko Stuebner
Syscon nodes can be a simple-mfd and the syscon-users then be declared
as children of this node. That way the parent-child structure can be
better represented for devices that are fully embedded in the syscon.
Therefore allow getting the syscon from the parent if neither
a special compatible nor a gpio,syscon-dev property is defined.
Signed-off-by: Heiko Stuebner
Signed-off-by: Levin Du
---
Changes in v3: None
Changes in v2: None
Changes in v1:
- New: allow fetching syscon from parent node in gpio-syscon driver
drivers/gpio/gpio-syscon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 537cec7..7325b86 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -205,6 +205,8 @@ static int syscon_gpio_probe(struct platform_device *pdev)
} else {
priv->syscon =
syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
+ if (IS_ERR(priv->syscon) && np->parent)
+ priv->syscon = syscon_node_to_regmap(np->parent);
if (IS_ERR(priv->syscon))
return PTR_ERR(priv->syscon);
--
2.7.4
[PATCH v3 0/5] Add sdmmc UHS support to ROC-RK3328-CC board.
From: Levin Du Hi all, this is an attemp to add sdmmc UHS support to the ROC-RK3328-CC board. This patch series adds a new compatible `rockchip,rk3328-gpio-mute` to the gpio-syscon driver for the access of the GPIO_MUTE pin in rk3328. A new gpio controller named `gpio_mute` is defined in rk3328.dtsi and so that all rk3328 boards has access to it. The ROC-RK3328-CC board use the new gpio <&gpio_mute 0> in gpio-regulator to control the signal voltage of the sdmmc. It is essential for UHS support which requires 1.8V signal voltage. Many thanks to the Linux people! Changes in v3: - Change from general gpio-syscon to specific rk3328-gpio-mute - Use dedicated "rockchip,rk3328-gpio-mute" driver - Use <&gpio_mute 0> instead of <&gpio_mute 1> to refer to the GPIO_MUTE pin. Changes in v2: - Rename gpio_syscon10 to gpio_mute in doc - Rename gpio_syscon10 to gpio_mute in rk3328.dtsi - Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts Changes in v1: - New: allow fetching syscon from parent node in gpio-syscon driver - Refactured for general gpio-syscon usage for Rockchip SoCs. - Add doc rockchip,gpio-syscon.txt - Split from V0 and add to rk3328.dtsi for general use. - Split from V0. - Split into small patches - Sort dts properties in sdmmc node Heiko Stuebner (1): gpio: syscon: allow fetching syscon from parent node Levin Du (4): gpio: syscon: rockchip: add GPIO_MUTE support for rk3328 arm64: dts: rockchip: Add GPIO_MUTE pin support to rk3328 arm64: dts: rockchip: Add io-domain to roc-rk3328-cc arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc .../bindings/gpio/rockchip,rk3328-gpio-mute.txt| 28 ++ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 34 ++ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 + drivers/gpio/gpio-syscon.c | 33 + 4 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt -- 2.7.4
[PATCH v3 4/5] arm64: dts: rockchip: Add io-domain to roc-rk3328-cc
From: Levin Du
It is necessary for the io domain setting of the SoC to match
the voltage supplied by the regulators.
Signed-off-by: Levin Du
---
Changes in v3: None
Changes in v2: None
Changes in v1:
- Split from V0.
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..b983abd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -208,6 +208,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
--
2.7.4
[PATCH v3 5/5] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc
From: Levin Du
In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by
the vcc_sdio regulator, which is a mux between 1.8V and 3.3V,
controlled by a special output only gpio pin labeled
"gpiomut_pmuio_iout", corresponding bit 1 of the syscon GRF_SOC_CON10.
This special pin can now be reference as <&gpio_mute 0>, thanks
to the gpio-syscon driver, which makes writing regulator-gpio possible.
If the signal voltage changes, the io domain needs to change
correspondingly.
To use this feature, the following options are required in kernel config:
- CONFIG_GPIO_SYSCON=y
- CONFIG_POWER_AVS=y
- CONFIG_ROCKCHIP_IODOMAIN=y
Signed-off-by: Levin Du
---
Changes in v3:
- Use <&gpio_mute 0> instead of <&gpio_mute 1> to refer to the GPIO_MUTE pin.
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts
Changes in v1:
- Split into small patches
- Sort dts properties in sdmmc node
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index b983abd..25c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
vin-supply = <&vcc_io>;
};
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio_mute 0 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -213,7 +226,7 @@
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
+ vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
@@ -242,7 +255,12 @@
max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
@@ -277,3 +295,7 @@
&usb_host0_ohci {
status = "okay";
};
+
+&gpio_mute {
+ status = "okay";
+};
--
2.7.4
[PATCH v2 0/5] Add sdmmc UHS support to ROC-RK3328-CC board.
From: Levin Du Hi all, this is an attemp to add sdmmc UHS support to the ROC-RK3328-CC board. This patch series adds a new compatible `rockchip,gpio-syscon` to the gpio-syscon driver for general Rockchip SoC usage. A new gpio controller named `gpio_mute` is defined in rk3328.dtsi so that all rk3328 boards has access to it. The ROC-RK3328-CC board use the new gpio <&gpio_mute 1> in gpio-regulator to control the signal voltage of the sdmmc. It is essential for UHS support which requires 1.8V signal voltage. Many thanks to Heiko's great advice! Changes in v2: - Rename gpio_syscon10 to gpio_mute in doc - Rename gpio_syscon10 to gpio_mute in rk3328.dtsi - Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts Changes in v1: - New: allow fetching syscon from parent node in gpio-syscon driver - Refactured for general gpio-syscon usage for Rockchip SoCs. - Add doc rockchip,gpio-syscon.txt - Split from V0 into small patches - Sort dts properties in sdmmc node Heiko Stuebner (1): gpio: syscon: allow fetching syscon from parent node Levin Du (4): gpio: syscon: Add gpio-syscon for rockchip arm64: dts: rockchip: Add gpio-mute to rk3328 arm64: dts: rockchip: Add io-domain to roc-rk3328-cc arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc .../bindings/gpio/rockchip,gpio-syscon.txt | 41 ++ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 30 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 drivers/gpio/gpio-syscon.c | 32 + 4 files changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt -- 2.7.4
[PATCH v2 3/5] arm64: dts: rockchip: Add gpio-mute to rk3328
From: Levin Du
Adding a new gpio controller named "gpio-mute" to rk3328, providing
access to the GPIO_MUTE pin defined in the syscon GRF_SOC_CON10.
The GPIO_MUTE pin is referred to as <&gpio-mute 1>.
Signed-off-by: Levin Du
---
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328.dtsi
Changes in v1:
- Split from V0 and add to rk3328.dtsi for general use.
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index b8e9da1..5ba29d3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -309,6 +309,13 @@
mode-loader = ;
};
+ /* The GPIO_MUTE pin is referred to as <&gpio-mute 1>.*/
+ gpio_mute: gpio-mute {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <0 0x0428 0>;
+ };
};
uart0: serial@ff11 {
--
2.7.4
[PATCH v2 4/5] arm64: dts: rockchip: Add io-domain to roc-rk3328-cc
From: Levin Du
It is necessary for the io domain setting of the SoC to match
the voltage supplied by the regulators.
Signed-off-by: Levin Du
---
Changes in v2: None
Changes in v1:
- Split from V0.
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..b983abd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -208,6 +208,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
--
2.7.4
[PATCH v2 1/5] gpio: syscon: allow fetching syscon from parent node
From: Heiko Stuebner
Syscon nodes can be a simple-mfd and the syscon-users then be declared
as children of this node. That way the parent-child structure can be
better represented for devices that are fully embedded in the syscon.
Therefore allow getting the syscon from the parent if neither
a special compatible nor a gpio,syscon-dev property is defined.
Signed-off-by: Heiko Stuebner
Signed-off-by: Levin Du
---
Changes in v2: None
Changes in v1:
- New: allow fetching syscon from parent node in gpio-syscon driver
drivers/gpio/gpio-syscon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 537cec7..7325b86 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -205,6 +205,8 @@ static int syscon_gpio_probe(struct platform_device *pdev)
} else {
priv->syscon =
syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
+ if (IS_ERR(priv->syscon) && np->parent)
+ priv->syscon = syscon_node_to_regmap(np->parent);
if (IS_ERR(priv->syscon))
return PTR_ERR(priv->syscon);
--
2.7.4
[PATCH v2 2/5] gpio: syscon: Add gpio-syscon for rockchip
From: Levin Du
Some GPIOs sit in the GRF_SOC_CON registers of Rockchip SoCs,
which do not belong to the general pinctrl.
Adding gpio-syscon support makes controlling regulator or
LED using these special pins very easy by reusing existing
drivers, such as gpio-regulator and led-gpio.
Signed-off-by: Levin Du
---
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in doc
Changes in v1:
- Refactured for general gpio-syscon usage for Rockchip SoCs.
- Add doc rockchip,gpio-syscon.txt
.../bindings/gpio/rockchip,gpio-syscon.txt | 41 ++
drivers/gpio/gpio-syscon.c | 30
2 files changed, 71 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
new file mode 100644
index 000..b1b2a67
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
@@ -0,0 +1,41 @@
+* Rockchip GPIO support for GRF_SOC_CON registers
+
+Required properties:
+- compatible: Should contain "rockchip,gpio-syscon".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+0 = Active high,
+1 = Active low.
+- gpio,syscon-dev: Should contain .
+ If declared as child of the grf node, the grf_phandle can be 0.
+
+Example:
+
+1. As child of grf node:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+
+ gpio_mute: gpio-mute {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <0 0x0428 0>;
+ };
+ };
+
+
+2. Not child of grf node:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ //...
+ };
+
+ gpio_mute: gpio-mute {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&grf 0x0428 0>;
+ };
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 7325b86..e24b408 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -135,6 +135,32 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio =
{
.dat_bit_offset = 0x40 * 8 + 8,
};
+static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int val)
+{
+ struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
+ unsigned int offs;
+ u8 bit;
+ u32 data;
+ int ret;
+
+ offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
+ bit = offs % SYSCON_REG_BITS;
+ data = (val ? BIT(bit) : 0) | BIT(bit + 16);
+ ret = regmap_write(priv->syscon,
+ (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
+ data);
+ if (ret < 0)
+ dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+}
+
+static const struct syscon_gpio_data rockchip_gpio_syscon = {
+ /* Rockchip GRF_SOC_CON Bits 0-15 */
+ .flags = GPIO_SYSCON_FEAT_OUT,
+ .bit_count = 16,
+ .set= rockchip_gpio_set,
+};
+
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -175,6 +201,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
+ {
+ .compatible = "rockchip,gpio-syscon",
+ .data = &rockchip_gpio_syscon,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
--
2.7.4
[PATCH v2 5/5] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc
From: Levin Du
In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by
the vcc_sdio regulator, which is a mux between 1.8V and 3.3V,
controlled by a special output only gpio pin labeled
"gpiomut_pmuio_iout", corresponding bit 1 of the syscon GRF_SOC_CON10.
This special pin can now be reference as <&gpio_mute 1>, thanks
to the gpio-syscon driver, which makes writing regulator-gpio possible.
If the signal voltage changes, the io domain needs to change
correspondingly.
To use this feature, the following options are required in kernel config:
- CONFIG_GPIO_SYSCON=y
- CONFIG_POWER_AVS=y
- CONFIG_ROCKCHIP_IODOMAIN=y
Signed-off-by: Levin Du
---
Changes in v2:
- Rename gpio_syscon10 to gpio_mute in rk3328-roc-cc.dts
Changes in v1:
- Split into small patches
- Sort dts properties in sdmmc node
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index b983abd..e3162bb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
vin-supply = <&vcc_io>;
};
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio_mute 1 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -213,7 +226,7 @@
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
+ vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
@@ -242,7 +255,12 @@
max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
--
2.7.4
Re: [PATCH 1/6] arm64: dts: rockchip: Fix rk3399-roc-pc pwm2 pin
Jagan Teki writes:
> Hi Heiko,
>
> On Mon, Sep 30, 2019 at 2:51 AM Heiko Stuebner wrote:
>>
>> Hi Jagan,
>>
>> Am Donnerstag, 19. September 2019, 07:28:17 CEST schrieb Jagan Teki:
>> > ROC-PC is not able to boot linux console if PWM2_d is
>> > unattached to any pinctrl logic.
>> >
>> > To be precise the linux boot hang with last logs as,
>> > ...
>> > .
>> > [0.003367] Console: colour dummy device 80x25
>> > [0.003788] printk: console [tty0] enabled
>> > [0.004178] printk: bootconsole [uart8250] disabled
>> >
>> > In ROC-PC the PWM2_d pin is connected to LOG_DVS_PWM of
>> > VDD_LOG. So, for normal working operations this needs to
>> > active and pull-down.
>> >
>> > This patch fix, by attaching pinctrl active and pull-down
>> > the pwm2.
>>
>> This looks highly dubious on first glance. The pwm subsystem nor
>> the Rockchip pwm driver do not do any pinctrl handling.
>>
>> So I don't really see where that "active" pinctrl state is supposed
>> to come from.
>>
>> Comparing with the pwm driver in the vendor tree I see that there
>> is such a state defined there. But that code there also looks strange
>> as that driver never again leaves this active state after entering it.
>>
>> Also for example all the Gru devices run with quite a number of pwm-
>> regulators without needing additional fiddling with the pwm itself, so
>> I don't really see why that should be different here.
>
> I deed, I was supposed to think the same. but the vendor kernel dts
> from firefly do follow the pwm2 pinctrl [1]. I wouldn't find any
> information other than this vensor information, ie one of the reason I
> have marked "Levin Du" who initially supported this board.
>
> One, think I have seen was this pinctrl active fixed the boot hang.
> any inputs from would be very helpful.
>
> Levin Du, any inputs?
>
> [1]
> https://github.com/FireflyTeam/kernel/blob/stable-4.4-rk3399-linux/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi#L1184
>
A grep of the `pwm2` shows that there's such block in rk3399-nanopi4.dtsi:
&pwm2 {
pinctrl-names = "active";
pinctrl-0 = <&pwm2_pin_pull_down>;
status = "okay";
};
But last time I checked, using the mainline U-Boot (the roc-rk3399-pc is
in mainline now) with mainline linux v5.2-rc7, no such setting is
necessary, and the board boots happily.
I cannot find the use of "active" pinctrl state in the
`drivers/pwm/pwm-rockchip.c`. If the pinctrl state needs to be setup as
default, the `pinctrl-names` needs to be "default" or "init" (see
`drivers/base/pinctrl.c`) .
Jagan, what version of board do you use? I checked with
"ROC-RK3399-PC-V1.0-A 2018-07-12".
Thanks
--
Levin Du
Re: [PATCH 1/6] arm64: dts: rockchip: Fix rk3399-roc-pc pwm2 pin
Sorry for the late reply, been stung by the mismatch use of ATF and U-Boot. If you're using U-Boot version before v2019.10, make sure to use the ATF version before this commit: commit 0aad563c74807195cc7fe2208d17e2d889157f1e (HEAD, tag: blacksheep, refs/bisect/bad) Author: Kever Yang Date: Thu Sep 19 10:37:36 2019 +0800 rockchip: Update BL31_BASE to 0x4 or use the master branch in git://git.denx.de/u-boot-rockchip.git . This is very important, or you'll be stuck at: U-Boot TPL 2019.10-djw (Oct 22 2019 - 03:08:48) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.10-djw (Oct 22 2019 - 03:08:48 +) Trying to boot from MMC1 I have tried the following combination: - U-Boot: v2019.10 - ATF: 382ddb3dd46a rockchip: Fix typo for TF content text - Kernel: 5.4.0-rc3-next-20191017 *Without* the pwm patch, all boot fine. Here's the full log: #+begin_src text U-Boot TPL 2019.10-djw (Oct 22 2019 - 03:51:17) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2019.10-djw (Oct 22 2019 - 03:51:17 +) Trying to boot from MMC1 U-Boot 2019.10-djw (Oct 22 2019 - 03:51:20 +) Model: Firefly ROC-RK3399-PC Board DRAM: 3.9 GiB MMC: dwmmc@fe32: 1, sdhci@fe33: 0 Loading Environment from EXT4... Card did not respond to voltage select! In:serial@ff1a Out: serial@ff1a Err: serial@ff1a Model: Firefly ROC-RK3399-PC Board rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: Error: ethernet@fe30 address not set. eth-1: ethernet@fe30 Hit any key to stop autoboot: 0 Card did not respond to voltage select! switch to partitions #0, OK mmc1 is current device Scanning mmc 1:1... Found U-Boot script /boot/boot.scr 2995 bytes read in 5 ms (585 KiB/s) ## Executing script at 0050 Boot script loaded from mmc 1 186 bytes read in 4 ms (44.9 KiB/s) 6748991 bytes read in 290 ms (22.2 MiB/s) 26163712 bytes read in 1110 ms (22.5 MiB/s) 53831 bytes read in 10 ms (5.1 MiB/s) 2698 bytes read in 8 ms (329.1 KiB/s) Applying kernel provided DT fixup script (rockchip-fixup.scr) ## Executing script at 3900 ## Loading init Ramdisk from Legacy Image at 0400 ... Image Name: uInitrd Image Type: AArch64 Linux RAMDisk Image (gzip compressed) Data Size:6748927 Bytes = 6.4 MiB Load Address: Entry Point: Verifying Checksum ... OK ## Flattened Device Tree blob at 01f0 Booting using the fdt blob at 0x1f0 Loading Ramdisk to f58b, end f5f1faff ... OK Loading Device Tree to f583a000, end f58a ... OK Starting kernel ... [0.00] Booting Linux on physical CPU 0x00 [0x410fd034] [0.00] Linux version 5.4.0-rc3-next-20191017-05460-g3ef845da3c3b-dirty (dujw@tchip14) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #8 SMP PREEMPT Tue Oct 22 12:08:35 CST 2019 [0.00] Machine model: Firefly ROC-RK3399-PC Board [0.00] earlycon: uart8250 at MMIO32 0xff1a (options '') [0.00] printk: bootconsole [uart8250] enabled [0.00] efi: Getting EFI parameters from FDT: [0.00] efi: UEFI not found. [0.00] cma: Reserved 32 MiB at 0x3e00 [0.00] NUMA: No NUMA configuration found [0.00] NUMA: Faking a node at [mem 0x0020-0xf7ff] [0.00] NUMA: NODE_DATA [mem 0xf77ef100-0xf77f0fff] [0.00] Zone ranges: [0.00] DMA [mem 0x0020-0x3fff] [0.00] DMA32[mem 0x4000-0xf7ff] [0.00] Normal empty [0.00] Movable zone start for each node [0.00] Early memory node ranges [0.00] node 0: [mem 0x0020-0xf7ff] [0.00] Initmem setup node 0 [mem 0x0020-0xf7ff] [0.00] psci: probing for conduit method from DT. [0.00] psci: PSCIv1.1 detected in firmware. [0.00] psci: Using standard PSCI v0.2 function IDs [0.00] psci: MIGRATE_INFO_TYPE not supported. [0.00] psci: SMC Calling Convention v1.1 [0.00] percpu: Embedded 22 pages/cpu s52952 r8192 d28968 u90112 [0.00] Detected VIPT I-cache on CPU0 [0.00] CPU features: detected: ARM erratum 845719 [0.00] CPU features: detected: GIC system register CPU interface [0.00] Speculative Store Bypass Disable mitigation not required [0.00] Built 1 zonelists, mobility grouping on. Total pages: 999432 [0.00] Policy zone: DMA32 [0.00] Kernel command line: root=UUID=78f156fe-c41f-4fdc-93f1-5d30f67659c8 rootwait rootfstype=ext4 console=ttyS2,150 earlycon=uart8250,mmio32,0xff1a swiotlb=1 console=tty1 panic=10 consoleblank=0 loglevel=7 ubootpart=e636e926-01 usb-storage.quirks=0x2537:0x1066:u,0x2537:0x1068:u cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory swapaccount=1 [0.
[PATCH v1 1/5] gpio: syscon: allow fetching syscon from parent node
From: Heiko Stuebner
Syscon nodes can be a simple-mfd and the syscon-users then be declared
as children of this node. That way the parent-child structure can be
better represented for devices that are fully embedded in the syscon.
Therefore allow getting the syscon from the parent if neither
a special compatible nor a gpio,syscon-dev property is defined.
Signed-off-by: Heiko Stuebner
Signed-off-by: Levin Du
---
Changes in v1:
- New
drivers/gpio/gpio-syscon.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 537cec7..7325b86 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -205,6 +205,8 @@ static int syscon_gpio_probe(struct platform_device *pdev)
} else {
priv->syscon =
syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
+ if (IS_ERR(priv->syscon) && np->parent)
+ priv->syscon = syscon_node_to_regmap(np->parent);
if (IS_ERR(priv->syscon))
return PTR_ERR(priv->syscon);
--
2.7.4
[PATCH v1 0/5] Add sdmmc UHS support to ROC-RK3328-CC board.
From: Levin Du Hi all, this is an attemp to add sdmmc UHS support to the ROC-RK3328-CC board. This patch series adds a new compatible `rockchip,gpio-syscon` to the gpio-syscon driver for general Rockchip SoC usage.. A new gpio controller named `gpio_syscon10` is defined in rk3328.dtsi so that all rk3328 boards has access to it. The ROC-RK3328-CC board use the new gpio <&gpio_syscon10 1> in gpio-regulator to control the signal voltage of the sdmmc. It is essential for UHS support which requires 1.8V signal voltage. Many thanks to Heiko's great advice! Changes in v1: - Refactured for general gpio-syscon usage for Rockchip SoCs. - Add doc rockchip,gpio-syscon.txt . - Split into small patches. - Add gpio-syscon10 to rk3328 for general use. - Sort dts properties in sdmmc node. Heiko Stuebner (1): gpio: syscon: allow fetching syscon from parent node Levin Du (4): gpio: syscon: Add gpio-syscon for rockchip arm64: dts: rockchip: Add gpio-syscon10 to rk3328 arm64: dts: rockchip: Add io-domain to roc-rk3328-cc arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc .../bindings/gpio/rockchip,gpio-syscon.txt | 41 ++ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 30 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 drivers/gpio/gpio-syscon.c | 32 + 4 files changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt -- 2.7.4
[PATCH v1 3/5] arm64: dts: rockchip: Add gpio-syscon10 to rk3328
From: Levin Du
Adding a new gpio controller named "gpio-syscon10" to rk3328, providing
access to the pins defined in the syscon GRF_SOC_CON10.
Boards using these special pins to control regulators or LEDs, can now
utilize existing drivers like gpio-regulator and leds-gpio.
Signed-off-by: Levin Du
---
Changes in v1:
- Split from V0 and add to rk3328.dtsi for general use.
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index b8e9da1..73a822d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -309,6 +309,12 @@
mode-loader = ;
};
+ gpio_syscon10: gpio-syscon10 {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <0 0x0428 0>;
+ };
};
uart0: serial@ff11 {
--
2.7.4
[PATCH v1 4/5] arm64: dts: rockchip: Add io-domain to roc-rk3328-cc
From: Levin Du
It is necessary for the io domain setting of the SoC to match
the voltage supplied by the regulators.
Signed-off-by: Levin Du
---
Changes in v1:
- Split from V0.
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..b983abd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -208,6 +208,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
--
2.7.4
[PATCH v1 2/5] gpio: syscon: Add gpio-syscon for rockchip
From: Levin Du
Some GPIOs sit in the GRF_SOC_CON registers of Rockchip SoCs,
which do not belong to the general pinctrl.
Adding gpio-syscon support makes controlling regulator or
LED using these special pins very easy by reusing existing
drivers, such as gpio-regulator and led-gpio.
Signed-off-by: Levin Du
---
Changes in v1:
- Refactured for general gpio-syscon usage for Rockchip SoCs.
- Add doc rockchip,gpio-syscon.txt
.../bindings/gpio/rockchip,gpio-syscon.txt | 41 ++
drivers/gpio/gpio-syscon.c | 30
2 files changed, 71 insertions(+)
create mode 100644
Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
new file mode 100644
index 000..e4c1650
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-syscon.txt
@@ -0,0 +1,41 @@
+* Rockchip GPIO support for GRF_SOC_CON registers
+
+Required properties:
+- compatible: Should contain "rockchip,gpio-syscon".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+0 = Active high,
+1 = Active low.
+- gpio,syscon-dev: Should contain .
+ If declared as child of the grf node, the grf_phandle can be 0.
+
+Example:
+
+1. As child of grf node:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+
+ gpio_syscon10: gpio-syscon10 {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <0 0x0428 0>;
+ };
+ };
+
+
+2. Not child of grf node:
+
+ grf: syscon@ff10 {
+ compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
+ //...
+ };
+
+ gpio_syscon10: gpio-syscon10 {
+ compatible = "rockchip,gpio-syscon";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio,syscon-dev = <&grf 0x0428 0>;
+ };
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 7325b86..e24b408 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -135,6 +135,32 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio =
{
.dat_bit_offset = 0x40 * 8 + 8,
};
+static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int val)
+{
+ struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
+ unsigned int offs;
+ u8 bit;
+ u32 data;
+ int ret;
+
+ offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
+ bit = offs % SYSCON_REG_BITS;
+ data = (val ? BIT(bit) : 0) | BIT(bit + 16);
+ ret = regmap_write(priv->syscon,
+ (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
+ data);
+ if (ret < 0)
+ dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+}
+
+static const struct syscon_gpio_data rockchip_gpio_syscon = {
+ /* Rockchip GRF_SOC_CON Bits 0-15 */
+ .flags = GPIO_SYSCON_FEAT_OUT,
+ .bit_count = 16,
+ .set= rockchip_gpio_set,
+};
+
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -175,6 +201,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
+ {
+ .compatible = "rockchip,gpio-syscon",
+ .data = &rockchip_gpio_syscon,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
--
2.7.4
[PATCH v1 5/5] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc
From: Levin Du
In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by
the vcc_sdio regulator, which is a mux between 1.8V and 3.3V,
controlled by a special output only gpio pin labeled
"gpiomut_pmuio_iout", corresponding bit 1 of the syscon GRF_SOC_CON10.
This special pin can now be reference as <&gpio_syscon10 1>, thanks
to the gpio-syscon driver, which makes writing regulator-gpio possible.
If the signal voltage changes, the io domain needs to change
correspondingly.
To use this feature, the following options are required in kernel config:
- CONFIG_GPIO_SYSCON=y
- CONFIG_POWER_AVS=y
- CONFIG_ROCKCHIP_IODOMAIN=y
Signed-off-by: Levin Du
---
Changes in v1:
- Split into small patches
- Sort dts properties in sdmmc node
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index b983abd..3f33e42 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
vin-supply = <&vcc_io>;
};
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio_syscon10 1 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -213,7 +226,7 @@
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_io>;
+ vccio3-supply = <&vcc_sdio>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
@@ -242,7 +255,12 @@
max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
--
2.7.4
[PATCH v1 4/5] arm64: dts: rockchip: Add io-domain to roc-rk3328-cc
From: Levin Du
It is necessary for the io domain setting of the SoC to match
the voltage supplied by the regulators.
Signed-off-by: Levin Du
---
Changes in v1:
- Split from V0.
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..b983abd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -208,6 +208,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
--
2.7.4
[PATCH v0 0/2] Add sdmmc UHS support to ROC-RK3328-CC board
From: Levin Du Hi all, This is an attemp to add sdmmc UHS support to the ROC-RK3328-CC board. It adds a new compatible `rockchip,rk3328-gpio-syscon10` to the gpio-syscon driver, so that a new gpio controller named `gpio_syscon10` can be defined and used in the regulator-gpio. This regulator controls the signal voltage of the sdmmc. It is essential for UHS support which requires 1.8V signal voltage. Levin Du (2): gpio: syscon: Add gpio-syscon for rk3328 arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 36 ++ drivers/gpio/gpio-syscon.c | 32 +++ 2 files changed, 68 insertions(+) -- 2.7.4
[PATCH v0 2/2] arm64: dts: rockchip: Add sdmmc UHS support for roc-rk3328-cc
From: Levin Du
In roc-rk3328-cc board, the signal voltage of sdmmc is supplied by
the vcc_sdio regulator, which is a mux between 1.8V and 3.3V,
controlled by a special output only gpio pin.
However, this pin, not being a normal gpio in the rockchip pinctrl,
is set by bit 1 of system register GRF_SOC_CON10. Therefore a new
gpio controller using gpio-syscon driver is defined in order to use
regulator-gpio.
If the signal voltage changes, the io domain needs to change
correspondingly.
To use this feature, the following options are required in kernel config:
- CONFIG_GPIO_SYSCON=y
- CONFIG_POWER_AVS=y
- CONFIG_ROCKCHIP_IODOMAIN=y
Signed-off-by: Levin Du
---
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 36 ++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317..792cb04 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -14,6 +14,12 @@
stdout-path = "serial2:150n8";
};
+ gpio_syscon10: gpio-syscon10 {
+ compatible = "rockchip,rk3328-gpio-syscon10";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <12500>;
@@ -41,6 +47,19 @@
vin-supply = <&vcc_io>;
};
+ vcc_sdio: sdmmcio-regulator {
+ compatible = "regulator-gpio";
+ gpios = <&gpio_syscon10 1 GPIO_ACTIVE_HIGH>;
+ states = <180 0x1
+ 330 0x0>;
+ regulator-name = "vcc_sdio";
+ regulator-type = "voltage";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -208,6 +227,18 @@
};
};
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc18_emmc>;
+ vccio3-supply = <&vcc_sdio>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
@@ -227,10 +258,15 @@
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
max-frequency = <15000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
status = "okay";
};
--
2.7.4
[PATCH v0 1/2] gpio: syscon: Add gpio-syscon for rk3328
From: Levin Du
In Rockchip RK3328 Soc, there's a output only gpio pin labeled
`gpiomut_pmuio_iout`, which can be set by bit[1] of GRF_SOC_CON10.
(bit[0] controls the enable state of the pin and defaults to enabled.)
This pin is used by the roc-rk3328-cc board to switch sdmmc io signal
voltage between 1.8V and 3.3V, which is essential to the SD card UHS
support.
Signed-off-by: Levin Du
---
drivers/gpio/gpio-syscon.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpio/gpio-syscon.c b/drivers/gpio/gpio-syscon.c
index 537cec7..b69f65f 100644
--- a/drivers/gpio/gpio-syscon.c
+++ b/drivers/gpio/gpio-syscon.c
@@ -135,6 +135,34 @@ static const struct syscon_gpio_data clps711x_mctrl_gpio =
{
.dat_bit_offset = 0x40 * 8 + 8,
};
+static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int val)
+{
+ struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
+ unsigned int offs;
+ u8 bit;
+ u32 data;
+ int ret;
+
+ offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
+ bit = offs % SYSCON_REG_BITS;
+ data = (val ? BIT(bit) : 0) | BIT(bit + 16);
+ ret = regmap_write(priv->syscon,
+ (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
+ data);
+ if (ret < 0)
+ dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+}
+
+static const struct syscon_gpio_data rk3328_gpio_syscon10 = {
+ /* Rockchip RK3328 GRF_SOC_CON10 Bits 0-1 */
+ .compatible = "rockchip,rk3328-grf",
+ .flags = GPIO_SYSCON_FEAT_OUT,
+ .bit_count = 2,
+ .dat_bit_offset = 0x0428 * 8,
+ .set= rockchip_gpio_set,
+};
+
#define KEYSTONE_LOCK_BIT BIT(0)
static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
@@ -175,6 +203,10 @@ static const struct of_device_id syscon_gpio_ids[] = {
.compatible = "ti,keystone-dsp-gpio",
.data = &keystone_dsp_gpio,
},
+ {
+ .compatible = "rockchip,rk3328-gpio-syscon10",
+ .data = &rk3328_gpio_syscon10,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
--
2.7.4
