Re: [PATCH] Revert "MIPS: make userspace mapping young by default".

[Zhou Yanjie]

Hi,

On 2021/4/20 上午10:48, Huang Pei wrote:

Hi,
On Mon, Apr 19, 2021 at 10:21:40PM +0800, Zhou Yanjie wrote:

Hi

On 2021/4/19 下午12:56, Huang Pei wrote:

On Sat, Apr 17, 2021 at 12:45:59AM +0800, Zhou Yanjie wrote:

On 2021/4/16 下午5:20, 黄沛 wrote:

Is there any log about the panic?

Yes, below is the log:


[  195.436017] CPU 0 Unable to handle kernel paging request at virtual
address 77eb8000, epc == 80117868, ra == 80118208
[  195.446709] Oops[#1]:
[  195.448977] CPU: 0 PID: 1461 Comm: Xsession Not tainted
5.12.0-rc6-00227-gc8fc6defbd2e-dirty #1
[  195.457661] $ 0   :  0001 80117864 77eb9000
[  195.462888] $ 4   : 77eb8000 82419600 838ea000 82482ba0
[  195.468116] $ 8   : 826f8b18 8306f800 72d5 8306f800
[  195.473343] $12   : 0002 0a03 0001 0402
[  195.478568] $16   : 77eb8000 809faf60 0004 82482ba0
[  195.483794] $20   : 77eb8000 82419600 82482ba0 8086
[  195.489021] $24   : 8086121c 80117864
[  195.494248] $28   : 838ea000 838ebd70  80118208
[  195.499475] Hi    : 8c4e
[  195.502343] Lo    : 4627
[  195.505212] epc   : 80117868 r4k_blast_dcache_page_dc32+0x4/0x9c
[  195.511217] ra    : 80118208 local_r4k_flush_cache_page+0x120/0x1b8
[  195.517476] Status: 10001403 KERNEL EXL IE
[  195.521657] Cause : 4080800c (ExcCode 03)
[  195.525654] BadVA : 77eb8000
[  195.528523] PrId  : 00d00100 (Ingenic XBurst)
[  195.532866] Modules linked in:
[  195.535911] Process Xsession (pid: 1461, threadinfo=00975a3e,
task=3724fd66, tls=77ebd690)
[  195.544162] Stack : 808a05ec f7edcbfd 8306f800  8086 809faf60
80990a3c 80117f90
[  195.552524] 809faf60 82419600 8306f800 801fd84c  801180b4
838ebe80 80110b7c
[  195.560887] 80990a3c 82482ba0 82482ba0 77eb8000 4627 f7edcbfd
838ebe80 801cbc08
[  195.569249] 0001 181b2000  801fa06c  83999ae0
8086 0004
[  195.577610] 80990a3c f7edcbfd 80990a3c 838ebe80 0004 80990a3c
82482ba0 04627685
[  195.585973] ...
[  195.588413] Call Trace:
[  195.590849] [<80117868>] r4k_blast_dcache_page_dc32+0x4/0x9c
[  195.596501] [<80118208>] local_r4k_flush_cache_page+0x120/0x1b8
[  195.602413] [<80117f90>] r4k_on_each_cpu.isra.8+0x24/0x58
[  195.607805] [<801180b4>] r4k_flush_cache_page+0x34/0x58
[  195.613023] [<801cbc08>] wp_page_copy+0x3a8/0x56c
[  195.617723] [<801ce944>] do_swap_page+0x4cc/0x558
[  195.622419] [<801cf3f8>] handle_mm_fault+0x790/0x93c
[  195.627374] [<8011025c>] do_page_fault+0x19c/0x540
[  195.632159] [<801142f0>] tlb_do_page_fault_1+0x10c/0x11c
[  195.637465]
[  195.638947] Code: 03e8    24831000  bc950020
bc950040  bc950060  bc950080  bc9500a0
[  195.648706]
[  195.650243] ---[ end trace 7cc7d7f611932c42 ]---
[  195.654857] Kernel panic - not syncing: Fatal exception
[  195.660072] Rebooting in 10 seconds..


this problem can be triggered stably (by use Microsoft Remote Desktop client
to login to debian9 running on CU1830-Neo).


Could you print out the PTE value at 0x77eb8000 ?


Here is the new log:


[   33.681712] CPU 0 Unable to handle kernel paging request at virtual
address 77ea4000, epc == 801178ac, ra == 80118250
[   33.692395] Oops[#1]:
[   33.694662] CPU: 0 PID: 1389 Comm: Xsession Not tainted 5.12.0-rc8-dirty
#2
[   33.701612] $ 0   :  0001 801178a8 77ea5000
[   33.706839] $ 4   : 77ea4000 81bcd220 80118130 856712a0
[   33.712066] $ 8   : 833e4a80 8544b800 70a8 8544b800
[   33.717293] $12   : 0002 05b7 0001 
[   33.722518] $16   : 81bcd220 77ea4000 80a11ad8 0004
[   33.727745] $20   : 77ea4000 81bcd220 856712a0 8086
[   33.732972] $24   : 001c 801178a8
[   33.738197] $28   : 82564000 82565d68  80118250
[   33.743424] Hi    : f0cc
[   33.746293] Lo    : 7866
[   33.749162] epc   : 801178ac r4k_blast_dcache_page_dc32+0x4/0x9c
[   33.755166] ra    : 80118250 local_r4k_flush_cache_page+0x120/0x2c8
[   33.761425] Status: 10001403 KERNEL EXL IE
[   33.765605] Cause : 4080800c (ExcCode 03)
[   33.769603] BadVA : 77ea4000
[   33.772472] PrId  : 00d00100 (Ingenic XBurst)
[   33.776816] Modules linked in:
[   33.779861] Process Xsession (pid: 1389, threadinfo=c8bdf64c,
task=2372d853, tls=77ea9690)
[   33.788111] Stack : 808a256c  808a256c bfa6939a 8544b800 8086
8094d308 80a11ad8
[   33.796474] 856712a0 80117fd8 8094d308 81bcd220 8544b800 801fdb10
80945ce8 801180fc
[   33.804838] 82565e80 80110b8c 80a11ad8 856712a0 856712a0 77ea4000
7866 bfa6939a
[   33.813201] 82565e80 801cbe38  bfa6939a 80863494 801fa2c0
856712a0 82562a90
[   33.821564] 8086  80a11ad8 bfa6939a 80a11ad8 82565e80
 80a11ad8
[   33.829927] ...
[   33.832367] Call Trace:
[   33.834803] [<801178ac>] r4k_blast_dcache_page_dc32+0x4/0x9c
[   33.840455] [<80118250>] local_r4k_flush_cache_page+0x120/0x2c8
[   33.846367] [<8

Re: [PATCH] Revert "MIPS: make userspace mapping young by default".

[Zhou Yanjie]

On 2021/4/20 上午10:48, Huang Pei wrote:

Hi,
On Mon, Apr 19, 2021 at 10:21:40PM +0800, Zhou Yanjie wrote:

Hi

On 2021/4/19 下午12:56, Huang Pei wrote:

On Sat, Apr 17, 2021 at 12:45:59AM +0800, Zhou Yanjie wrote:

On 2021/4/16 下午5:20, 黄沛 wrote:

Is there any log about the panic?

Yes, below is the log:


[  195.436017] CPU 0 Unable to handle kernel paging request at virtual
address 77eb8000, epc == 80117868, ra == 80118208
[  195.446709] Oops[#1]:
[  195.448977] CPU: 0 PID: 1461 Comm: Xsession Not tainted
5.12.0-rc6-00227-gc8fc6defbd2e-dirty #1
[  195.457661] $ 0   :  0001 80117864 77eb9000
[  195.462888] $ 4   : 77eb8000 82419600 838ea000 82482ba0
[  195.468116] $ 8   : 826f8b18 8306f800 72d5 8306f800
[  195.473343] $12   : 0002 0a03 0001 0402
[  195.478568] $16   : 77eb8000 809faf60 0004 82482ba0
[  195.483794] $20   : 77eb8000 82419600 82482ba0 8086
[  195.489021] $24   : 8086121c 80117864
[  195.494248] $28   : 838ea000 838ebd70  80118208
[  195.499475] Hi    : 8c4e
[  195.502343] Lo    : 4627
[  195.505212] epc   : 80117868 r4k_blast_dcache_page_dc32+0x4/0x9c
[  195.511217] ra    : 80118208 local_r4k_flush_cache_page+0x120/0x1b8
[  195.517476] Status: 10001403 KERNEL EXL IE
[  195.521657] Cause : 4080800c (ExcCode 03)
[  195.525654] BadVA : 77eb8000
[  195.528523] PrId  : 00d00100 (Ingenic XBurst)
[  195.532866] Modules linked in:
[  195.535911] Process Xsession (pid: 1461, threadinfo=00975a3e,
task=3724fd66, tls=77ebd690)
[  195.544162] Stack : 808a05ec f7edcbfd 8306f800  8086 809faf60
80990a3c 80117f90
[  195.552524] 809faf60 82419600 8306f800 801fd84c  801180b4
838ebe80 80110b7c
[  195.560887] 80990a3c 82482ba0 82482ba0 77eb8000 4627 f7edcbfd
838ebe80 801cbc08
[  195.569249] 0001 181b2000  801fa06c  83999ae0
8086 0004
[  195.577610] 80990a3c f7edcbfd 80990a3c 838ebe80 0004 80990a3c
82482ba0 04627685
[  195.585973] ...
[  195.588413] Call Trace:
[  195.590849] [<80117868>] r4k_blast_dcache_page_dc32+0x4/0x9c
[  195.596501] [<80118208>] local_r4k_flush_cache_page+0x120/0x1b8
[  195.602413] [<80117f90>] r4k_on_each_cpu.isra.8+0x24/0x58
[  195.607805] [<801180b4>] r4k_flush_cache_page+0x34/0x58
[  195.613023] [<801cbc08>] wp_page_copy+0x3a8/0x56c
[  195.617723] [<801ce944>] do_swap_page+0x4cc/0x558
[  195.622419] [<801cf3f8>] handle_mm_fault+0x790/0x93c
[  195.627374] [<8011025c>] do_page_fault+0x19c/0x540
[  195.632159] [<801142f0>] tlb_do_page_fault_1+0x10c/0x11c
[  195.637465]
[  195.638947] Code: 03e8    24831000  bc950020
bc950040  bc950060  bc950080  bc9500a0
[  195.648706]
[  195.650243] ---[ end trace 7cc7d7f611932c42 ]---
[  195.654857] Kernel panic - not syncing: Fatal exception
[  195.660072] Rebooting in 10 seconds..


this problem can be triggered stably (by use Microsoft Remote Desktop client
to login to debian9 running on CU1830-Neo).


Could you print out the PTE value at 0x77eb8000 ?


Here is the new log:


[   33.681712] CPU 0 Unable to handle kernel paging request at virtual
address 77ea4000, epc == 801178ac, ra == 80118250
[   33.692395] Oops[#1]:
[   33.694662] CPU: 0 PID: 1389 Comm: Xsession Not tainted 5.12.0-rc8-dirty
#2
[   33.701612] $ 0   :  0001 801178a8 77ea5000
[   33.706839] $ 4   : 77ea4000 81bcd220 80118130 856712a0
[   33.712066] $ 8   : 833e4a80 8544b800 70a8 8544b800
[   33.717293] $12   : 0002 05b7 0001 
[   33.722518] $16   : 81bcd220 77ea4000 80a11ad8 0004
[   33.727745] $20   : 77ea4000 81bcd220 856712a0 8086
[   33.732972] $24   : 001c 801178a8
[   33.738197] $28   : 82564000 82565d68  80118250
[   33.743424] Hi    : f0cc
[   33.746293] Lo    : 7866
[   33.749162] epc   : 801178ac r4k_blast_dcache_page_dc32+0x4/0x9c
[   33.755166] ra    : 80118250 local_r4k_flush_cache_page+0x120/0x2c8
[   33.761425] Status: 10001403 KERNEL EXL IE
[   33.765605] Cause : 4080800c (ExcCode 03)
[   33.769603] BadVA : 77ea4000
[   33.772472] PrId  : 00d00100 (Ingenic XBurst)
[   33.776816] Modules linked in:
[   33.779861] Process Xsession (pid: 1389, threadinfo=c8bdf64c,
task=2372d853, tls=77ea9690)
[   33.788111] Stack : 808a256c  808a256c bfa6939a 8544b800 8086
8094d308 80a11ad8
[   33.796474] 856712a0 80117fd8 8094d308 81bcd220 8544b800 801fdb10
80945ce8 801180fc
[   33.804838] 82565e80 80110b8c 80a11ad8 856712a0 856712a0 77ea4000
7866 bfa6939a
[   33.813201] 82565e80 801cbe38  bfa6939a 80863494 801fa2c0
856712a0 82562a90
[   33.821564] 8086  80a11ad8 bfa6939a 80a11ad8 82565e80
 80a11ad8
[   33.829927] ...
[   33.832367] Call Trace:
[   33.834803] [<801178ac>] r4k_blast_dcache_page_dc32+0x4/0x9c
[   33.840455] [<80118250>] local_r4k_flush_cache_page+0x120/0x2c8
[   33.846367] [<80117fd8>] r4k_on_eac

Re: [PATCH RESEND 4/4] Pinctrl: Ingenic: Fix const declaration.

[Zhou Yanjie]

My fault, I checked it again, the reason for this problem is that the
member "pins" in structure "group_desc" is not a const type.
It did not report this warning when I used gcc-5.2.0.
After switching to gcc-6.3.0, the warning appeared.
Should we ignore the warning information given by checkpatch.pl?

On 2019年01月26日 01:59, Paul Cercueil wrote:

Hi,

On Fri, Jan 25, 2019 at 6:59 AM, Zhou Yanjie  wrote:

Warning is reported when checkpatch indicates that
"static const char * array" should be changed to
"static const char * const".

Signed-off-by: Zhou Yanjie <mailto:zhouyan...@zoho.com>>

---
 drivers/pinctrl/pinctrl-ingenic.c | 136 
+-

 1 file changed, 76 insertions(+), 60 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index 2b3f7e4..e982896 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -172,23 +172,25 @@ static const struct group_desc jz4740_groups[] = {
 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
 };

-static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
-static const char *jz4740_uart0_groups[] = { "uart0-data", 
"uart0-hwflow", };

-static const char *jz4740_uart1_groups[] = { "uart1-data", };
-static const char *jz4740_lcd_groups[] = {
+static const char * const jz4740_mmc_groups[] = { "mmc-1bit", 
"mmc-4bit", };

+static const char * const jz4740_uart0_groups[] = {
+"uart0-data", "uart0-hwflow",
+};
+static const char * const jz4740_uart1_groups[] = { "uart1-data", };
+static const char * const jz4740_lcd_groups[] = {
 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", 
"lcd-no-pins",

 };
-static const char *jz4740_nand_groups[] = {
+static const char * const jz4740_nand_groups[] = {
 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 };
-static const char *jz4740_pwm0_groups[] = { "pwm0", };
-static const char *jz4740_pwm1_groups[] = { "pwm1", };
-static const char *jz4740_pwm2_groups[] = { "pwm2", };
-static const char *jz4740_pwm3_groups[] = { "pwm3", };
-static const char *jz4740_pwm4_groups[] = { "pwm4", };
-static const char *jz4740_pwm5_groups[] = { "pwm5", };
-static const char *jz4740_pwm6_groups[] = { "pwm6", };
-static const char *jz4740_pwm7_groups[] = { "pwm7", };
+static const char * const jz4740_pwm0_groups[] = { "pwm0", };
+static const char * const jz4740_pwm1_groups[] = { "pwm1", };
+static const char * const jz4740_pwm2_groups[] = { "pwm2", };
+static const char * const jz4740_pwm3_groups[] = { "pwm3", };
+static const char * const jz4740_pwm4_groups[] = { "pwm4", };
+static const char * const jz4740_pwm5_groups[] = { "pwm5", };
+static const char * const jz4740_pwm6_groups[] = { "pwm6", };
+static const char * const jz4740_pwm7_groups[] = { "pwm7", };

 static const struct function_desc jz4740_functions[] = {
 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },


With this patch applied I get this:

drivers/pinctrl/pinctrl-ingenic.c:196:11: attention : initialization 
discards

‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
  ^

@@ -272,19 +274,19 @@ static const struct group_desc jz4725b_groups[] 
= {

 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
 };

-static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", 
"mmc0-4bit", };
-static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", 
"mmc1-4bit", };

-static const char *jz4725b_uart_groups[] = { "uart-data", };
-static const char *jz4725b_nand_groups[] = {
+static const char * const jz4725b_mmc0_groups[] = { "mmc0-1bit", 
"mmc0-4bit", };
+static const char * const jz4725b_mmc1_groups[] = { "mmc1-1bit", 
"mmc1-4bit", };

+static const char * const jz4725b_uart_groups[] = { "uart-data", };
+static const char * const jz4725b_nand_groups[] = {
 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 "nand-cle-ale", "nand-fre-fwe",
 };
-static const char *jz4725b_pwm0_groups[] = { "pwm0", };
-static const char *jz4725b_pwm1_groups[] = { "pwm1", };
-static const char *jz4725b_pwm2_groups[] = { "pwm2", };
-static const char *jz4725b_pwm3_groups[] = { "pwm3", };
-static const char *jz4725b_pwm4_groups[] = { "pwm4", };
-static const char *jz4725b_pwm5_groups[] = { "pwm5", };
+sta

Add Ingenic X1000 irqchip support.

[Zhou Yanjie]

Add Ingenic X1000 irqchip support.

[PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.

[Zhou Yanjie]

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 49 ++-
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2ff0898..2713ec4 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen 
- *  JZ4740 platform IRQ support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General Public License as published by 
the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include 
@@ -19,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -41,22 +33,35 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING0x10
 #define CHIP_SIZE  0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-   struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-   uint32_t irq_reg;
+   struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   bool have_irq = false;
+   u32 pending;
unsigned i;
 
+   chained_irq_enter(chip, desc);
for (i = 0; i < intc->num_chips; i++) {
-   irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+   pending = readl(intc->base + (i * CHIP_SIZE) +
JZ_REG_INTC_PENDING);
-   if (!irq_reg)
+   if (!pending)
continue;
 
-   generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+   have_irq = true;
+   while (pending) {
+   int bit = __ffs(pending);
+
+   generic_handle_irq(__fls(pending) + (i * 32) +
+   JZ4740_IRQ_BASE);
+   pending &= ~BIT(bit);
+   }
}
 
-   return IRQ_HANDLED;
+   if (!have_irq)
+   spurious_interrupt();
+
+   chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -79,11 +84,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-   .handler = intc_cascade,
-   .name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
   unsigned num_chips)
 {
@@ -148,7 +148,8 @@ static int __init ingenic_intc_of_init(struct device_node 
*node,
if (!domain)
pr_warn("unable to register IRQ domain\n");
 
-   setup_irq(parent_irq, &intc_cascade_action);
+   irq_set_chained_handler_and_data(parent_irq,
+   ingenic_chained_handle_irq, intc);
return 0;
 
 out_unmap_irq:
-- 
2.7.4

[PATCH 3/4] Irqchip: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 69be219..0b643c7 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node 
*node,
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
-- 
2.7.4

[PATCH 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".

[Zhou Yanjie]

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2713ec4..69be219 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -64,7 +64,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+   uint32_t mask)
 {
struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -75,13 +76,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, 
uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-   intc_irq_set_mask(gc, gc->wake_active);
+   ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-   intc_irq_set_mask(gc, gc->mask_cache);
+   ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4

[PATCH 4/4] Irqchip: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa69b3f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -8,6 +8,7 @@ Required properties:
 ingenic,jz4770-intc
 ingenic,jz4775-intc
 ingenic,jz4780-intc
+ingenic,x1000-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4

Re: [PATCH 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.

[Zhou Yanjie]

My fault, in the function "generic_handle_irq" should use "bit" instead 
of "__fls(irq_reg)".

It will be fixed in the v2.

On 2019年01月27日 18:21, Marc Zyngier wrote:

On Sat, 26 Jan 2019 15:38:40 +,
Zhou Yanjie  wrote:

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie 
---
  drivers/irqchip/irq-ingenic.c | 49 ++-
  1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2ff0898..2713ec4 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
  /*
   *  Copyright (C) 2009-2010, Lars-Peter Clausen 
- *  JZ4740 platform IRQ support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General Public License as published by 
the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *  Ingenic XBurst platform IRQ support
   */
  
  #include 

@@ -19,6 +10,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -41,22 +33,35 @@ struct ingenic_intc_data {
  #define JZ_REG_INTC_PENDING   0x10
  #define CHIP_SIZE 0x20
  
-static irqreturn_t intc_cascade(int irq, void *data)

+static void ingenic_chained_handle_irq(struct irq_desc *desc)
  {
-   struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-   uint32_t irq_reg;
+   struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   bool have_irq = false;
+   u32 pending;
unsigned i;
  
+	chained_irq_enter(chip, desc);

for (i = 0; i < intc->num_chips; i++) {
-   irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+   pending = readl(intc->base + (i * CHIP_SIZE) +
JZ_REG_INTC_PENDING);
-   if (!irq_reg)
+   if (!pending)
continue;
  
-		generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);

+   have_irq = true;
+   while (pending) {
+   int bit = __ffs(pending);

So 'bit' is the least significant bit in the pending word,


+
+   generic_handle_irq(__fls(pending) + (i * 32) +

and here you handle the *most significant* bit,


+   JZ4740_IRQ_BASE);
+   pending &= ~BIT(bit);

yet it is the least significant bit that you clear. I am tempted to
say that you have never tested this code with more than a single
interrupt.

Thanks,

M.

Re: [PATCH 3/4] Irqchip: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Thanks for your suggestions, It will be deleted in the v2.

On 2019年01月27日 18:14, Marc Zyngier wrote:

On Sat, 26 Jan 2019 15:38:42 +,
Zhou Yanjie  wrote:

Add support for probing the irq-ingenic driver on the X1000 Soc.
X1000 is a 1.0GHz processor for IoT. It has MIPS32 XBurst RISC core
with double precision hardware float point unit.

I don't think we need the marketing spiel, as none of the advertised
target market, ISA or feature set of this SoC is relevant for this
patch. Put it in the cover letter if you must.

Instead, explaining that it behaves just like any of the other "2chip"
Ingenic SoCs makes is much more relevant.


Signed-off-by: Zhou Yanjie 
---
  drivers/irqchip/irq-ingenic.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 69be219..0b643c7 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -177,3 +177,4 @@ static int __init intc_2chip_of_init(struct device_node 
*node,
  IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
  IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
  IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
--
2.7.4



Thanks,

M.

Add Ingenic X1000 irqchip support v2.

[Zhou Yanjie]

vi->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".

[PATCH v2 1/4] Irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.

[Zhou Yanjie]

The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 48 +--
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 2ff0898..5f775a1 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen 
- *  JZ4740 platform IRQ support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General Public License as published by 
the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include 
@@ -19,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -41,22 +33,34 @@ struct ingenic_intc_data {
 #define JZ_REG_INTC_PENDING0x10
 #define CHIP_SIZE  0x20
 
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
 {
-   struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-   uint32_t irq_reg;
+   struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   bool have_irq = false;
+   uint32_t pending;
unsigned i;
 
+   chained_irq_enter(chip, desc);
for (i = 0; i < intc->num_chips; i++) {
-   irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+   pending = readl(intc->base + (i * CHIP_SIZE) +
JZ_REG_INTC_PENDING);
-   if (!irq_reg)
+   if (!pending)
continue;
 
-   generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+   have_irq = true;
+   while (pending) {
+   int bit = __fls(pending);
+
+   generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+   pending &= ~BIT(bit);
+   }
}
 
-   return IRQ_HANDLED;
+   if (!have_irq)
+   spurious_interrupt();
+
+   chained_irq_exit(chip, desc);
 }
 
 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -79,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
intc_irq_set_mask(gc, gc->mask_cache);
 }
 
-static struct irqaction intc_cascade_action = {
-   .handler = intc_cascade,
-   .name = "SoC intc cascade interrupt",
-};
-
 static int __init ingenic_intc_of_init(struct device_node *node,
   unsigned num_chips)
 {
@@ -148,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node 
*node,
if (!domain)
pr_warn("unable to register IRQ domain\n");
 
-   setup_irq(parent_irq, &intc_cascade_action);
+   irq_set_chained_handler_and_data(parent_irq,
+   ingenic_chained_handle_irq, intc);
return 0;
 
 out_unmap_irq:
-- 
2.7.4

[PATCH v2 2/4] Irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".

[Zhou Yanjie]

For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 5f775a1..32d090a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+   uint32_t mask)
 {
struct irq_chip_regs *regs = &gc->chip_types->regs;
 
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, 
uint32_t mask)
 void ingenic_intc_irq_suspend(struct irq_data *data)
 {
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-   intc_irq_set_mask(gc, gc->wake_active);
+   ingenic_intc_irq_set_mask(gc, gc->wake_active);
 }
 
 void ingenic_intc_irq_resume(struct irq_data *data)
 {
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-   intc_irq_set_mask(gc, gc->mask_cache);
+   ingenic_intc_irq_set_mask(gc, gc->mask_cache);
 }
 
 static int __init ingenic_intc_of_init(struct device_node *node,
-- 
2.7.4

[PATCH v2 3/4] Irqchip: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the irq-ingenic driver on the X1000 Soc.

Signed-off-by: Zhou Yanjie 
---
 drivers/irqchip/irq-ingenic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 32d090a..814c68c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -176,3 +176,4 @@ static int __init intc_2chip_of_init(struct device_node 
*node,
 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
-- 
2.7.4

[PATCH v2 4/4] Irqchip: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the irq-ingenic driver on the X1000 Soc.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa69b3f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -8,6 +8,7 @@ Required properties:
 ingenic,jz4770-intc
 ingenic,jz4775-intc
 ingenic,jz4780-intc
+ingenic,x1000-intc
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.7.4

Add Ingenic X1000 serial support.

[Zhou Yanjie]

Add Ingenic X1000 serial support.

[PATCH 2/2] Serial: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt 
b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
index c3c6406..24ed876 100644
--- a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
+++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
@@ -6,7 +6,8 @@ Required properties:
   - "ingenic,jz4760-uart",
   - "ingenic,jz4770-uart",
   - "ingenic,jz4775-uart",
-  - "ingenic,jz4780-uart".
+  - "ingenic,jz4780-uart",
+  - "ingenic,x1000-uart".
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
 - clocks : phandles to the module & baud clocks.
-- 
2.7.4

[PATCH 1/2] Serial: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 drivers/tty/serial/8250/8250_ingenic.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_ingenic.c 
b/drivers/tty/serial/8250/8250_ingenic.c
index 15a8c8d..1999e3b 100644
--- a/drivers/tty/serial/8250/8250_ingenic.c
+++ b/drivers/tty/serial/8250/8250_ingenic.c
@@ -145,6 +145,10 @@ EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
ingenic_early_console_setup);
 
+EARLYCON_DECLARE(x1000_uart, ingenic_early_console_setup);
+OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
+   ingenic_early_console_setup);
+
 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 {
int ier;
@@ -328,12 +332,18 @@ static const struct ingenic_uart_config 
jz4780_uart_config = {
.fifosize = 64,
 };
 
+static const struct ingenic_uart_config x1000_uart_config = {
+   .tx_loadsz = 32,
+   .fifosize = 64,
+};
+
 static const struct of_device_id of_match[] = {
{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
+   { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_match);
-- 
2.7.4

Re: [PATCH 1/2] Serial: Ingenic: Add support for the X1000.

[Zhou Yanjie]

My fault, I will fix these in v2.

On 2019年01月28日 17:30, Greg KH wrote:

On Mon, Jan 28, 2019 at 05:19:35PM +0800, Zhou Yanjie wrote:

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
  drivers/tty/serial/8250/8250_ingenic.c | 10 ++
  1 file changed, 10 insertions(+)

You sent two different patches with the same subject: line, yet they did
totally different things.

Please fix this up and resend with a better set of subject lines.

thanks,

greg k-h

Serial: Ingenic: Add X1000 suppor for the UART driver.

[Zhou Yanjie]

v1->v2: Remove unnecessary "EARLYCON_DECLARE".

[PATCH v2 1/2] Serial: Ingenic: Add X1000 suppor for the UART driver.

[Zhou Yanjie]

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 drivers/tty/serial/8250/8250_ingenic.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_ingenic.c 
b/drivers/tty/serial/8250/8250_ingenic.c
index 15a8c8d..424c07c 100644
--- a/drivers/tty/serial/8250/8250_ingenic.c
+++ b/drivers/tty/serial/8250/8250_ingenic.c
@@ -129,22 +129,21 @@ static int __init ingenic_early_console_setup(struct 
earlycon_device *dev,
return 0;
 }
 
-EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4770_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
ingenic_early_console_setup);
 
+OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
+   ingenic_early_console_setup);
+
 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 {
int ier;
@@ -328,12 +327,18 @@ static const struct ingenic_uart_config 
jz4780_uart_config = {
.fifosize = 64,
 };
 
+static const struct ingenic_uart_config x1000_uart_config = {
+   .tx_loadsz = 32,
+   .fifosize = 64,
+};
+
 static const struct of_device_id of_match[] = {
{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
+   { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_match);
-- 
2.7.4

[PATCH v2 2/2] Serial: Ingenic: Add X1000 suppor for the UART driver.

[Zhou Yanjie]

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt 
b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
index c3c6406..24ed876 100644
--- a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
+++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
@@ -6,7 +6,8 @@ Required properties:
   - "ingenic,jz4760-uart",
   - "ingenic,jz4770-uart",
   - "ingenic,jz4775-uart",
-  - "ingenic,jz4780-uart".
+  - "ingenic,jz4780-uart",
+  - "ingenic,x1000-uart".
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
 - clocks : phandles to the module & baud clocks.
-- 
2.7.4

Re: [PATCH RESEND 1/4] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.

[Zhou Yanjie]

Thank you for your reply. I am working on v2, and I have removed the 
fourth patch in v2,
so there will be no warnings at compile time. But this will cause some 
warning messages

when checkpatch, I am confused whether I can ignore these warnings.

On 2019年01月28日 21:59, Linus Walleij wrote:

This series looks good to me, but it would be nice if you could
fix the warning pointed out by Paul, and I would also
like some ACK from Paul C on the patches so I know this is
fine with him.

Yours,
Linus Walleij

Ingenic pinctrl fixes.

[Zhou Yanjie]

Fix compile-time warnings.

[PATCH v2 1/3] Pinctrl: Ingenic: Fix bugs caused by differences between JZ4770 and JZ4780.

[Zhou Yanjie]

From: Zhou Yanjie 

Delete uart4 and i2c3/4 from JZ4770:
According to the datasheet, only JZ4780 have uart4 and i2c3/4. So we
remove it from the JZ4770 code and add a section corresponding the JZ4780.

Fix bugs in i2c0/1:
The pin number was wrong in the original code.

Fix bugs in uart2:
JZ4770 and JZ4780 have different uart2 pins. So the original section JZ4770
has been modified and the corresponding section of JZ4780 has been added.

Fix bugs in mmc0:
JZ4770 and JZ4780 assigned different pins to mmc0's 4~7 data lines. So the
original section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in mmc1:
JZ4770's mmc1 has 8bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in nemc:
JZ4770's nemc has 16bit mode, while JZ4780 doesn't. So the original section
JZ4770 has been modified and the corresponding section of JZ4780 has been
added. And add missing cs2~5 groups for JZ4770 and JZ4780.

Fix bugs in cim:
JZ4770's cim has 12bit mode, while JZ4780 doesn't. So the original
section JZ4770 has been modified and the corresponding section of
JZ4780 has been added.

Fix bugs in lcd:
Both JZ4770 and JZ4780 lcd should be 24bit instead of 32bit.

Signed-off-by: Zhou Yanjie 
---
 drivers/pinctrl/pinctrl-ingenic.c | 249 +-
 1 file changed, 191 insertions(+), 58 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index db6b48e..710062b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -321,23 +321,26 @@ static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
-static int jz4770_uart2_data_pins[] = { 0x66, 0x67, };
-static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, };
+static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
+static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
-static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, };
-static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
-static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
-static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
-static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
-static int jz4770_nemc_data_pins[] = {
+static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
+static int jz4770_nemc_16bit_data_pins[] = {
+   0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+};
 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
@@ -348,20 +351,21 @@ static int jz4770_nemc_cs3_pins[] = { 0x17, };
 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
-static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, };
-static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, };
+static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
-static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, };
-static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, };
-static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, };
-static int jz4770_cim_pins[] = {
-   0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+static int jz4770_cim_8bit_pins[] = {
+   0x26, 0x27, 0x28, 0x29,
+   0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4770_cim_12bit_pins[] = {
+   0x32, 0x33, 0xb0, 0xb1,
 };
-static int jz4770_lcd_32bit_pins[] = {
+static int jz4770_lcd_24bit_pins[] = {
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-   0x58, 0x59, 0x51,
+   0x58, 0x59, 0x5a, 0x5b,
 };
 static int jz4770_p

[PATCH v2 2/3] Pinctrl: Ingenic: Add missing parts for JZ4770 and JZ4780.

[Zhou Yanjie]

From: Zhou Yanjie 

Add mmc2 for JZ4770 and JZ4780:
According to the datasheet, both JZ4770 and JZ4780 have mmc2. But this
part of the original code is missing. It is worth noting that JZ4770's
mmc2 supports 8bit mode while JZ4780's does not, so we added the
corresponding code for both models.

Add nemc-wait for JZ4770 and JZ4780:
Both JZ4770 and JZ4780 have a nemc-wait pin. But this part of the
original code is missing.

Add mac for JZ4770:
JZ4770 have a mac. But this part of the original code is missing.

Signed-off-by: Zhou Yanjie 
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 710062b..6501f35 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -335,6 +335,11 @@ static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, 
};
 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
+static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 static int jz4770_nemc_8bit_data_pins[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 };
@@ -345,6 +350,7 @@ static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4770_nemc_wait_pins[] = { 0x1b, };
 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 static int jz4770_nemc_cs3_pins[] = { 0x17, };
@@ -375,6 +381,10 @@ static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
+static int jz4770_mac_rmii_pins[] = {
+   0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 
 static int jz4770_uart0_data_funcs[] = { 0, 0, };
 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
@@ -394,12 +404,18 @@ static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
+static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
+static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
+static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
+static int jz4770_nemc_wait_funcs[] = { 0, };
 static int jz4770_nemc_cs1_funcs[] = { 0, };
 static int jz4770_nemc_cs2_funcs[] = { 0, };
 static int jz4770_nemc_cs3_funcs[] = { 0, };
@@ -425,6 +441,8 @@ static int jz4770_pwm_pwm4_funcs[] = { 0, };
 static int jz4770_pwm_pwm5_funcs[] = { 0, };
 static int jz4770_pwm_pwm6_funcs[] = { 0, };
 static int jz4770_pwm_pwm7_funcs[] = { 0, };
+static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int jz4770_mac_mii_funcs[] = { 0, 0, };
 
 static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -445,12 +463,18 @@ static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
+   INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
+   INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
+   INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
+   INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
+   INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
INGENIC

[PATCH v2 3/3] Pinctrl: Ingenic: Unify the function name prefix to "ingenic_gpio_".

[Zhou Yanjie]

From: Zhou Yanjie 

In the original code, some function names begin with "ingenic_gpio_",
and some with "gpio_ingenic_". For the sake of uniform style,
all of them are changed to the beginning of "ingenic_gpio_".

Signed-off-by: Zhou Yanjie 
---
 drivers/pinctrl/pinctrl-ingenic.c | 46 +++
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 6501f35..2b3f7e4 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -715,7 +715,7 @@ static const struct ingenic_chip_info jz4780_chip_info = {
.pull_downs = jz4770_pull_downs,
 };
 
-static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
+static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
 {
unsigned int val;
 
@@ -724,7 +724,7 @@ static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip 
*jzgc, u8 reg)
return (u32) val;
 }
 
-static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc,
+static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
u8 reg, u8 offset, bool set)
 {
if (set)
@@ -738,7 +738,7 @@ static void gpio_ingenic_set_bit(struct ingenic_gpio_chip 
*jzgc,
 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
  u8 offset)
 {
-   unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN);
+   unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
 
return !!(val & BIT(offset));
 }
@@ -747,9 +747,9 @@ static void ingenic_gpio_set_value(struct ingenic_gpio_chip 
*jzgc,
   u8 offset, int value)
 {
if (jzgc->jzpc->version >= ID_JZ4770)
-   gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
+   ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
else
-   gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
+   ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
 }
 
 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
@@ -767,21 +767,21 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc,
 
switch (type) {
case IRQ_TYPE_EDGE_RISING:
-   gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-   gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+   ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+   ingenic_gpio_set_bit(jzgc, reg1, offset, true);
break;
case IRQ_TYPE_EDGE_FALLING:
-   gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-   gpio_ingenic_set_bit(jzgc, reg1, offset, true);
+   ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+   ingenic_gpio_set_bit(jzgc, reg1, offset, true);
break;
case IRQ_TYPE_LEVEL_HIGH:
-   gpio_ingenic_set_bit(jzgc, reg2, offset, true);
-   gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+   ingenic_gpio_set_bit(jzgc, reg2, offset, true);
+   ingenic_gpio_set_bit(jzgc, reg1, offset, false);
break;
case IRQ_TYPE_LEVEL_LOW:
default:
-   gpio_ingenic_set_bit(jzgc, reg2, offset, false);
-   gpio_ingenic_set_bit(jzgc, reg1, offset, false);
+   ingenic_gpio_set_bit(jzgc, reg2, offset, false);
+   ingenic_gpio_set_bit(jzgc, reg1, offset, false);
break;
}
 }
@@ -791,7 +791,7 @@ static void ingenic_gpio_irq_mask(struct irq_data *irqd)
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-   gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
+   ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
 }
 
 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
@@ -799,7 +799,7 @@ static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
 
-   gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
+   ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
 }
 
 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
@@ -809,9 +809,9 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd)
int irq = irqd->hwirq;
 
if (jzgc->jzpc->version >= ID_JZ4770)
-   gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
+   ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
else
-   gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
+   ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
 
ingenic_gpio_irq_unmask(irqd);
 }
@@ -825,9 +

Re: [PATCH v2 1/2] Serial: Ingenic: Add X1000 suppor for the UART driver.

[Zhou Yanjie]

I am very sorry, I understood wrong before.

On 2019年01月29日 00:22, Greg KH wrote:

On Mon, Jan 28, 2019 at 09:57:00PM +0800, Zhou Yanjie wrote:

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
  drivers/tty/serial/8250/8250_ingenic.c | 13 +
  1 file changed, 9 insertions(+), 4 deletions(-)

Your subject lines are still identical for both patches :(

Add Ingenic X1000 serial support

[Zhou Yanjie]

v1->v2: Remove unnecessary "EARLYCON_DECLARE".
v2->v3: Use different subject line for each patch.

[PATCH v3 1/2] Serial: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the 8250_ingenic driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 drivers/tty/serial/8250/8250_ingenic.c | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_ingenic.c 
b/drivers/tty/serial/8250/8250_ingenic.c
index 15a8c8d..424c07c 100644
--- a/drivers/tty/serial/8250/8250_ingenic.c
+++ b/drivers/tty/serial/8250/8250_ingenic.c
@@ -129,22 +129,21 @@ static int __init ingenic_early_console_setup(struct 
earlycon_device *dev,
return 0;
 }
 
-EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4770_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
ingenic_early_console_setup);
 
-EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
ingenic_early_console_setup);
 
+OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
+   ingenic_early_console_setup);
+
 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
 {
int ier;
@@ -328,12 +327,18 @@ static const struct ingenic_uart_config 
jz4780_uart_config = {
.fifosize = 64,
 };
 
+static const struct ingenic_uart_config x1000_uart_config = {
+   .tx_loadsz = 32,
+   .fifosize = 64,
+};
+
 static const struct of_device_id of_match[] = {
{ .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
{ .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
{ .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
+   { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_match);
-- 
2.7.4

[PATCH v3 2/2] Dt-bindings: Serial: Add X1000 serial bindings.

[Zhou Yanjie]

Add the serial bindings for the X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/serial/ingenic,uart.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.txt 
b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
index c3c6406..24ed876 100644
--- a/Documentation/devicetree/bindings/serial/ingenic,uart.txt
+++ b/Documentation/devicetree/bindings/serial/ingenic,uart.txt
@@ -6,7 +6,8 @@ Required properties:
   - "ingenic,jz4760-uart",
   - "ingenic,jz4770-uart",
   - "ingenic,jz4775-uart",
-  - "ingenic,jz4780-uart".
+  - "ingenic,jz4780-uart",
+  - "ingenic,x1000-uart".
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
 - clocks : phandles to the module & baud clocks.
-- 
2.7.4

Add Ingenic X1000 RTC support.

[Zhou Yanjie]

Add Ingenic X1000 RTC support.

[PATCH 1/3] RTC: Ingenic: Add support for the X1000.

[Zhou Yanjie]

Add support for probing the rtc-jz4740 driver on the
X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 drivers/rtc/rtc-jz4740.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
index d0a8917..0c7ae65 100644
--- a/drivers/rtc/rtc-jz4740.c
+++ b/drivers/rtc/rtc-jz4740.c
@@ -34,7 +34,7 @@
 #define JZ_REG_RTC_RESET_COUNTER   0x28
 #define JZ_REG_RTC_SCRATCHPAD  0x34
 
-/* The following are present on the jz4780 */
+/* The following are present on the jz4780 and x1000 */
 #define JZ_REG_RTC_WENR0x3C
 #define JZ_RTC_WENR_WENBIT(31)
 
@@ -46,7 +46,7 @@
 #define JZ_RTC_CTRL_AE BIT(2)
 #define JZ_RTC_CTRL_ENABLE BIT(0)
 
-/* Magic value to enable writes on jz4780 */
+/* Magic value to enable writes on jz4780 and x1000 */
 #define JZ_RTC_WENR_MAGIC  0xA55A
 
 #define JZ_RTC_WAKEUP_FILTER_MASK  0xFFE0
@@ -55,6 +55,7 @@
 enum jz4740_rtc_type {
ID_JZ4740,
ID_JZ4780,
+   ID_X1000,
 };
 
 struct jz4740_rtc {
@@ -301,6 +302,7 @@ static void jz4740_rtc_power_off(void)
 static const struct of_device_id jz4740_rtc_of_match[] = {
{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
+   { .compatible = "ingenic,x1000-rtc", .data = (void *)ID_X1000 },
{},
 };
 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
@@ -429,6 +431,7 @@ static const struct dev_pm_ops jz4740_pm_ops = {
 static const struct platform_device_id jz4740_rtc_ids[] = {
{ "jz4740-rtc", ID_JZ4740 },
{ "jz4780-rtc", ID_JZ4780 },
+   { "x1000-rtc", ID_X1000 },
{}
 };
 MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
-- 
2.7.4

[PATCH 2/3] Dt-bindings: RTC: Add X1000 RTC bindings.

[Zhou Yanjie]

Add the RTC bindings for the X1000 Soc from Ingenic.

Signed-off-by: Zhou Yanjie 
---
 Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt 
b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt
index 41c7ae1..7ce0018 100644
--- a/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt
@@ -5,6 +5,7 @@ Required properties:
 - compatible: One of:
   - "ingenic,jz4740-rtc" - for use with the JZ4740 SoC
   - "ingenic,jz4780-rtc" - for use with the JZ4780 SoC
+  - "ingenic,x1000-rtc" - for use with the X1000 SoC
 - reg: Address range of rtc register set
 - interrupts: IRQ number for the alarm interrupt
 - clocks: phandle to the "rtc" clock
-- 
2.7.4

[PATCH 3/3] RTC: Ingenic: Replace jz47xx with XBurst.

[Zhou Yanjie]

Ingenic had changed their product code name.
Latest SoCs had divided to several series such as
T30/M200/X1000 and no longer called JZ47xx.

Signed-off-by: Zhou Yanjie 
---
 drivers/rtc/Kconfig  |  4 ++--
 drivers/rtc/rtc-jz4740.c | 15 +++
 2 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 225b0b8..8b41853 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1576,10 +1576,10 @@ config RTC_DRV_MPC5121
  will be called rtc-mpc5121.
 
 config RTC_DRV_JZ4740
-   tristate "Ingenic JZ4740 SoC"
+   tristate "Ingenic XBurst SoC"
depends on MIPS || COMPILE_TEST
help
- If you say yes here you get support for the Ingenic JZ47xx SoCs RTC
+ If you say yes here you get support for the Ingenic XBurst SoCs RTC
  controllers.
 
  This driver can also be built as a module. If so, the module
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
index 0c7ae65..a262632 100644
--- a/drivers/rtc/rtc-jz4740.c
+++ b/drivers/rtc/rtc-jz4740.c
@@ -1,17 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen 
  *  Copyright (C) 2010, Paul Cercueil 
- *  JZ4740 SoC RTC driver
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of  the GNU General Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ * Ingenic XBurst platform RTC support
  */
 
 #include 
@@ -450,5 +441,5 @@ module_platform_driver(jz4740_rtc_driver);
 
 MODULE_AUTHOR("Lars-Peter Clausen ");
 MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
+MODULE_DESCRIPTION("RTC driver for Ingenic XBurst platform\n");
 MODULE_ALIAS("platform:jz4740-rtc");
-- 
2.7.4

[PATCH 0/2] Add USB PHY support for Ingenic X1000 and X1830.

[Zhou Yanjie]

1.Add the USB PHY bindings for the X1000 SoC and
  the X1830 SoC from Ingenic.
2.Add support for probing the phy-jz4770 driver on the
  X1000 SoC and the X1830 SoC from Ingenic.

周琰杰 (Zhou Yanjie) (2):
  dt-bindings: USB: Add Ingenic X1000 and X1830 bindings.
  USB: PHY: JZ4770: Add support for Ingenic X1000 and X1830.

 .../bindings/usb/ingenic,jz4770-phy.yaml   |   5 +-
 drivers/usb/phy/Kconfig|   4 +-
 drivers/usb/phy/phy-jz4770.c   | 250 ++---
 3 files changed, 173 insertions(+), 86 deletions(-)

-- 
2.11.0

[PATCH 1/2] dt-bindings: USB: Add Ingenic X1000 and X1830 bindings.

[Zhou Yanjie]

Add the USB PHY bindings for the X1000 SoC and
the X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---
 Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml 
b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
index a81b0b1a2226..95ba3b9aa801 100644
--- a/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
+++ b/Documentation/devicetree/bindings/usb/ingenic,jz4770-phy.yaml
@@ -4,10 +4,11 @@
 $id: http://devicetree.org/schemas/usb/ingenic,jz4770-phy.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Ingenic JZ4770 USB PHY devicetree bindings
+title: Ingenic SoCs USB PHY devicetree bindings
 
 maintainers:
   - Paul Cercueil 
+  - 周琰杰 (Zhou Yanjie) 
 
 properties:
   $nodename:
@@ -16,6 +17,8 @@ properties:
   compatible:
 enum:
   - ingenic,jz4770-phy
+  - ingenic,x1000-phy
+  - ingenic,x1830-phy
 
   reg:
 maxItems: 1
-- 
2.11.0

[PATCH 2/2] USB: PHY: JZ4770: Add support for Ingenic X1000 and X1830.

[Zhou Yanjie]

Add support for probing the phy-jz4770 driver on the
X1000 SoC and the X1830 SoC from Ingenic.

Signed-off-by: qipengzhen 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---
 drivers/usb/phy/Kconfig  |   4 +-
 drivers/usb/phy/phy-jz4770.c | 250 +--
 2 files changed, 169 insertions(+), 85 deletions(-)

diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 4b3fa78995cf..fb7e32d07646 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -185,11 +185,11 @@ config USB_ULPI_VIEWPORT
  controllers with a viewport register (e.g. Chipidea/ARC controllers).
 
 config JZ4770_PHY
-   tristate "Ingenic JZ4770 Transceiver Driver"
+   tristate "Ingenic SOCs Transceiver Driver"
depends on MIPS || COMPILE_TEST
select USB_PHY
help
  This driver provides PHY support for the USB controller found
- on the JZ4770 SoC from Ingenic.
+ on the JZ4770/X1000/X1830 SoC from Ingenic.
 
 endmenu
diff --git a/drivers/usb/phy/phy-jz4770.c b/drivers/usb/phy/phy-jz4770.c
index 3ea1f5b9bcf8..b31d70bb778c 100644
--- a/drivers/usb/phy/phy-jz4770.c
+++ b/drivers/usb/phy/phy-jz4770.c
@@ -1,77 +1,111 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Ingenic JZ4770 USB PHY driver
+ * Ingenic SoCs USB PHY driver
  * Copyright (c) Paul Cercueil 
+ * Copyright (c) qipengzhen 
+ * Copyright (c) 周琰杰 (Zhou Yanjie) 
  */
 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 
-#define REG_USBPCR_OFFSET  0x00
-#define REG_USBRDT_OFFSET  0x04
-#define REG_USBVBFIL_OFFSET0x08
-#define REG_USBPCR1_OFFSET 0x0c
-
-/* USBPCR */
-#define USBPCR_USB_MODEBIT(31)
-#define USBPCR_AVLD_REGBIT(30)
-#define USBPCR_INCRM   BIT(27)
-#define USBPCR_CLK12_ENBIT(26)
-#define USBPCR_COMMONONN   BIT(25)
-#define USBPCR_VBUSVLDEXT  BIT(24)
-#define USBPCR_VBUSVLDEXTSEL   BIT(23)
-#define USBPCR_POR BIT(22)
-#define USBPCR_SIDDQ   BIT(21)
-#define USBPCR_OTG_DISABLE BIT(20)
-#define USBPCR_TXPREEMPHTUNE   BIT(6)
-
-#define USBPCR_IDPULLUP_LSB28
-#define USBPCR_IDPULLUP_MASK   GENMASK(29, USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_ALWAYS (3 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_SUSPEND(1 << USBPCR_IDPULLUP_LSB)
-#define USBPCR_IDPULLUP_OTG(0 << USBPCR_IDPULLUP_LSB)
-
-#define USBPCR_COMPDISTUNE_LSB 17
-#define USBPCR_COMPDISTUNE_MASKGENMASK(19, USBPCR_COMPDISTUNE_LSB)
-#define USBPCR_COMPDISTUNE_DFT 4
-
-#define USBPCR_OTGTUNE_LSB 14
-#define USBPCR_OTGTUNE_MASKGENMASK(16, USBPCR_OTGTUNE_LSB)
-#define USBPCR_OTGTUNE_DFT 4
-
-#define USBPCR_SQRXTUNE_LSB11
-#define USBPCR_SQRXTUNE_MASK   GENMASK(13, USBPCR_SQRXTUNE_LSB)
-#define USBPCR_SQRXTUNE_DFT3
-
-#define USBPCR_TXFSLSTUNE_LSB  7
-#define USBPCR_TXFSLSTUNE_MASK GENMASK(10, USBPCR_TXFSLSTUNE_LSB)
-#define USBPCR_TXFSLSTUNE_DFT  3
-
-#define USBPCR_TXRISETUNE_LSB  4
-#define USBPCR_TXRISETUNE_MASK GENMASK(5, USBPCR_TXRISETUNE_LSB)
-#define USBPCR_TXRISETUNE_DFT  3
-
-#define USBPCR_TXVREFTUNE_LSB  0
-#define USBPCR_TXVREFTUNE_MASK GENMASK(3, USBPCR_TXVREFTUNE_LSB)
-#define USBPCR_TXVREFTUNE_DFT  5
-
-/* USBRDT */
-#define USBRDT_VBFIL_LD_EN BIT(25)
-#define USBRDT_IDDIG_ENBIT(24)
-#define USBRDT_IDDIG_REG   BIT(23)
-
-#define USBRDT_USBRDT_LSB  0
-#define USBRDT_USBRDT_MASK GENMASK(22, USBRDT_USBRDT_LSB)
-
-/* USBPCR1 */
-#define USBPCR1_UHC_POWON  BIT(5)
+#define REG_USBPCR_OFFSET  0x00
+#define REG_USBRDT_OFFSET  0x04
+#define REG_USBVBFIL_OFFSET0x08
+#define REG_USBPCR1_OFFSET 0x0c
+
+/*USB Parameter Control Register*/
+#define USBPCR_USB_MODEBIT(31)
+#define USBPCR_AVLD_REGBIT(30)
+#define USBPCR_INCR_MASK   BIT(27)
+#define USBPCR_COMMONONN   BIT(25)
+#define USBPCR_VBUSVLDEXT  BIT(24)
+#define USBPCR_VBUSVLDEXTSEL   BIT(23)
+#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ   BIT(21)
+#define USBPCR_OTG_DISABLE BIT(20)
+#define USBPCR_TXPREEMPHTUNE   BIT(6)
+
+#define USBPCR_IDPULLUP_LSB28
+#define USBPCR_IDPULLUP_MASK   GENMASK(29, USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_ALWAYS (0x2 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_SUSPEND(0x1 << USBPCR_IDPULLUP_LSB)
+#define USBPCR_IDPULLUP_OTG(0x0 << USBPCR_IDPULLUP_LSB)
+
+#define USBPCR_COMPDISTUNE_LSB 17
+#define USBPCR_COMPDISTUNE_MASKGENMASK(19, 
USBPCR_COMPDISTUNE_LSB)
+#define USBPCR_COMPDISTUNE_DFT (0x4 << USBPCR_COMPDISTUNE_LSB)

[PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs.

[Zhou Yanjie]

Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi
and x1000.dtsi files.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
No change.

v2->v3:
No change.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
No change.

v5->v6:
No change.

v6->v7:
Update compatible strings.

v7->v8:
No change.

 arch/mips/boot/dts/ingenic/jz4740.dtsi | 14 ++
 arch/mips/boot/dts/ingenic/jz4770.dtsi | 15 ++-
 arch/mips/boot/dts/ingenic/jz4780.dtsi | 23 +++
 arch/mips/boot/dts/ingenic/x1000.dtsi  | 14 ++
 4 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi 
b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index a3301ba..1f2f896 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -7,6 +7,20 @@
#size-cells = <1>;
compatible = "ingenic,jz4740";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-mxu1.0";
+   reg = <0>;
+
+   clocks = <&cgu JZ4740_CLK_CCLK>;
+   clock-names = "cpu";
+   };
+   };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi 
b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index 0bfb9ed..12c7101 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -1,5 +1,4 @@
 // SPDX-License-Identifier: GPL-2.0
-
 #include 
 
 / {
@@ -7,6 +6,20 @@
#size-cells = <1>;
compatible = "ingenic,jz4770";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <0>;
+
+   clocks = <&cgu JZ4770_CLK_CCLK>;
+   clock-names = "cpu";
+   };
+   };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi 
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index bb89653..03aeeff 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -8,6 +8,29 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <0>;
+
+   clocks = <&cgu JZ4780_CLK_CPU>;
+   clock-names = "cpu";
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <1>;
+
+   clocks = <&cgu JZ4780_CLK_CORE1>;
+   clock-names = "cpu";
+   };
+   };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 147f7d5..2205e1b 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -8,6 +8,20 @@
#size-cells = <1>;
compatible = "ingenic,x1000", "ingenic,x1000e";
 
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <0>;
+
+   clocks = <&cgu X1000_CLK_CPU>;
+   clock-names = "cpu";
+   };
+   };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
-- 
2.7.4

[PATCH v8 2/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP.

[Zhou Yanjie]

Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
per core local timer, #2 for clocksource.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
No change.

v2->v3:
No change.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
Move [5/6] in v4 to this patch, to ensure that we can
git-bisect without ending up with a broken kernel.

v5->v6:
No change.

v6->v7:
Remove unnecessary "ingenic,pwm-channels-mask".

v7->v8:
No change.

 arch/mips/boot/dts/ingenic/ci20.dts | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts 
b/arch/mips/boot/dts/ingenic/ci20.dts
index db0ca25..06e3186 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -486,7 +486,12 @@
 };
 
 &tcu {
-   /* 3 MHz for the system timer and clocksource */
-   assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
-   assigned-clock-rates = <300>, <300>;
+   /*
+* 750 kHz for the system timers and clocksource,
+* use channel #0 and #1 for the per cpu system timers,
+* and use channel #2 for the clocksource.
+*/
+   assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>;
+   assigned-clock-rates = <75>, <75>, <75>;
 };
-- 
2.7.4

[PATCH v8 6/6] MIPS: CI20: Update defconfig to support SMP.

[Zhou Yanjie]

Add "CONFIG_SMP=y" and "CONFIG_NR_CPUS=2" to support SMP.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
No change.

v2->v3:
No change.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
No change.

v5->v6:
No change.

v6->v7:
No change.

v7->v8:
No change.

 arch/mips/configs/ci20_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index 0db0088..c8dd136 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -1,3 +1,5 @@
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_MODULES=y
 CONFIG_KERNEL_XZ=y
-- 
2.7.4

[PATCH v8 3/6] clocksource: Ingenic: Add high resolution timer support for SMP.

[Zhou Yanjie]

Enable clock event handling on per CPU core basis.
Make sure that interrupts raised on the first core execute
event handlers on the correct CPU core.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
1.Adjust function naming to make it more reasonable.
2.Replace function smp_call_function_single() with
  smp_call_function_single_async() in order to resolve
  the warning below:

[0.350942] smp: Brought up 1 node, 2 CPUs
[0.365497] [ cut here ]
[0.365522] WARNING: CPU: 0 PID: 1 at kernel/smp.c:300 
smp_call_function_single+0x110/0x200
[0.365533] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc1+ #5
[0.365537] Stack :  59c73bcd 0037 80074e80 8000 
8067 805a 80620590
[0.365557] 8065ce38 8fc0dc8c 806d  8067 
0001 8fc0dc20 59c73bcd
[0.365574]   806f 8067  
806dab00  2d302e35
[0.365591] 203a6d6d 806e 806e 70617773 8067 
  0009
[0.365610]  8fc94e20 8fc0de30 8069 0018 
803592dc  806d
[0.365627] ...
[0.365634] Call Trace:
[0.365647] [<8001b9a0>] show_stack+0x6c/0x12c
[0.365663] [<804aed20>] dump_stack+0x98/0xc8
[0.365673] [<8003044c>] __warn+0xc4/0xe8
[0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8
[0.365690] [<800a886c>] smp_call_function_single+0x110/0x200
[0.365703] ---[ end trace 5785856ca39c79d5 ]---
[0.365557] 8065ce38 8fc0dc8c 806d  8067 
0001 8fc0dc20 59c73bcd
[0.365574]   806f 8067  
806dab00  2d302e35
[0.365591] 203a6d6d 806e 806e 70617773 8067 
  0009
[0.365610]  8fc94e20 8fc0de30 8069 0018 
803592dc  806d
[0.365627] ...
[0.365634] Call Trace:
[0.365647] [<8001b9a0>] show_stack+0x6c/0x12c
[0.365663] [<804aed20>] dump_stack+0x98/0xc8
[0.365673] [<8003044c>] __warn+0xc4/0xe8
[0.365682] [<800304f4>] warn_slowpath_fmt+0x84/0xb8
[0.365690] [<800a886c>] smp_call_function_single+0x110/0x200
[0.365703] ---[ end trace 5785856ca39c79d5 ]---

v2->v3:
No Change.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
Move the check for (evt->event_handler) from "ingenic_per_cpu_event_handler"
to "ingenic_tcu_cevt_cb".

v5->v6:
No change.

v6->v7:
Remove unnecessary check for "NR_CPUS > 1".

v7->v8:
Use "num_possible_cpus()" instead "NR_CPUS".
Reported-by: kbuild test robot 

 drivers/clocksource/ingenic-timer.c | 103 
 1 file changed, 82 insertions(+), 21 deletions(-)

diff --git a/drivers/clocksource/ingenic-timer.c 
b/drivers/clocksource/ingenic-timer.c
index 4963336..230e996 100644
--- a/drivers/clocksource/ingenic-timer.c
+++ b/drivers/clocksource/ingenic-timer.c
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * JZ47xx SoCs TCU IRQ driver
+ * XBurst SoCs TCU IRQ driver
  * Copyright (C) 2019 Paul Cercueil 
+ * Copyright (C) 2020 周琰杰 (Zhou Yanjie) 
  */
 
 #include 
@@ -21,18 +22,23 @@
 
 #include 
 
+static DEFINE_PER_CPU(call_single_data_t, ingenic_cevt_csd);
+
 struct ingenic_soc_info {
unsigned int num_channels;
 };
 
 struct ingenic_tcu {
struct regmap *map;
+   struct device_node *np;
struct clk *timer_clk, *cs_clk;
+   unsigned int timer_local[NR_CPUS];
unsigned int timer_channel, cs_channel;
struct clock_event_device cevt;
struct clocksource cs;
-   char name[4];
+   char name[8];
unsigned long pwm_channels_mask;
+   int cpu;
 };
 
 static struct ingenic_tcu *ingenic_tcu;
@@ -81,6 +87,24 @@ static int ingenic_tcu_cevt_set_next(unsigned long next,
return 0;
 }
 
+static void ingenic_per_cpu_event_handler(void *info)
+{
+   struct clock_event_device *cevt = (struct clock_event_device *) info;
+
+   cevt->event_handler(cevt);
+}
+
+static void ingenic_tcu_per_cpu_cb(struct clock_event_device *evt)
+{
+   struct ingenic_tcu *tcu = to_ingenic_tcu(evt);
+   call_single_data_t *csd;
+
+   csd = &per_cpu(ingenic_cevt_csd, tcu->cpu);
+   csd->info = (void *) evt;
+   csd->func = ingenic_per_cpu_event_handler;
+   smp_call_function_single_async(tcu->cpu, csd);
+}
+
 static irqreturn_t ingenic_tcu_cevt_cb(int irq, void *dev_id)
 {
struct clock_event_device *evt = dev_id;
@@ -89,7 +113,7 @@ static irqreturn_t ingenic_tcu_cevt_cb(int irq, v

Introduce SMP support for CI20 (based on JZ4780) v8.

[Zhou Yanjie]

Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.

[PATCH v8 0/6] Introduce SMP support for CI20 (based on JZ4780).

[Zhou Yanjie]

Introduce SMP support for MIPS Creator CI20, which is
based on Ingenic JZ4780 SoC.

周琰杰 (Zhou Yanjie) (6):
  MIPS: JZ4780: Introduce SMP support.
  MIPS: CI20: Modify DTS to support high resolution timer for SMP.
  clocksource: Ingenic: Add high resolution timer support for SMP.
  dt-bindings: MIPS: Document Ingenic SoCs binding.
  MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs.
  MIPS: CI20: Update defconfig to support SMP.

 .../bindings/mips/ingenic/ingenic,cpu.yaml |  57 +
 arch/mips/boot/dts/ingenic/ci20.dts|  11 +-
 arch/mips/boot/dts/ingenic/jz4740.dtsi |  14 ++
 arch/mips/boot/dts/ingenic/jz4770.dtsi |  15 +-
 arch/mips/boot/dts/ingenic/jz4780.dtsi |  23 ++
 arch/mips/boot/dts/ingenic/x1000.dtsi  |  14 ++
 arch/mips/configs/ci20_defconfig   |   2 +
 arch/mips/include/asm/mach-jz4740/smp.h|  87 +++
 arch/mips/jz4740/Kconfig   |   2 +
 arch/mips/jz4740/Makefile  |   5 +
 arch/mips/jz4740/prom.c|   4 +
 arch/mips/jz4740/smp-entry.S   |  57 +
 arch/mips/jz4740/smp.c | 258 +
 arch/mips/kernel/idle.c|  35 ++-
 drivers/clocksource/ingenic-timer.c| 103 ++--
 15 files changed, 661 insertions(+), 26 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
 create mode 100644 arch/mips/include/asm/mach-jz4740/smp.h
 create mode 100644 arch/mips/jz4740/smp-entry.S
 create mode 100644 arch/mips/jz4740/smp.c

-- 
2.7.4

[PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding.

[Zhou Yanjie]

Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
Change the two Document from txt to yaml.

v2->v3:
Fix formatting errors.

v3->v4:
Fix bugs in the two yaml files.

v4->v5:
No change.

v5->v6:
Rewrite the two yaml files.

v6->v7:
1.Update compatible strings in "ingenic,cpu.yaml".
2.Fix formatting errors, and enum for compatible strings.
3.Remove unnecessary "ingenic,soc.yaml".

v7->v8:
No change.

 .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++
 1 file changed, 57 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml

diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml 
b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
new file mode 100644
index ..afb0207
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic XBurst family CPUs
+
+maintainers:
+  - 周琰杰 (Zhou Yanjie) 
+
+description:
+  Ingenic XBurst family CPUs shall have the following properties.
+
+properties:
+  compatible:
+oneOf:
+
+  - description: Ingenic XBurst®1 CPU Cores
+items:
+  enum:
+- ingenic,xburst-mxu1.0
+- ingenic,xburst-fpu1.0-mxu1.1
+- ingenic,xburst-fpu2.0-mxu2.0
+
+  - description: Ingenic XBurst®2 CPU Cores
+items:
+  enum:
+- ingenic,xburst2-fpu2.1-mxu2.1-smt
+
+  reg:
+maxItems: 1
+
+required:
+  - device_type
+  - compatible
+  - reg
+
+examples:
+  - |
+cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <0>;
+   };
+
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "ingenic,xburst-fpu1.0-mxu1.1";
+   reg = <1>;
+   };
+};
+...
-- 
2.7.4

[PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support.

[Zhou Yanjie]

Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Jiaxun Yang 
---

Notes:
v1->v2:
1.Remove unnecessary "plat_irq_dispatch(void)" in irq-ingenic.c.
2.Add a timeout check for "jz4780_boot_secondary()" to avoid a dead loop.
3.Replace hard code in smp.c with macro.

v2->v3:
1.Remove unnecessary "extern void (*r4k_blast_dcache)(void)" in smp.c.
2.Use "for_each_of_cpu_node" instead "for_each_compatible_node" in smp.c.
3.Use "of_cpu_node_to_id" instead "of_property_read_u32_index" in smp.c.
4.Move LCR related operations to jz4780-cgu.c.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
1.Splitting changes involving "jz4780-cgu.c" into separate commit.
2.Use "request_irq()" replace "setup_irq()".

v5->v6:
In order to have a kernel that works on multiple SoCs at the same
time, use "IS_ENABLED()" replace "#ifdef".

v6->v7:
1.SMP has be decoupled from the SoC version.
2.Add mailboxes 3 and 4 for XBurst.
3.Adjust code in "jz4780_smp_prepare_cpus()".
4."jz4780_smp_init()" has be marked "__init".

v7->v8:
No change.

 arch/mips/include/asm/mach-jz4740/smp.h |  87 +++
 arch/mips/jz4740/Kconfig|   2 +
 arch/mips/jz4740/Makefile   |   5 +
 arch/mips/jz4740/prom.c |   4 +
 arch/mips/jz4740/smp-entry.S|  57 +++
 arch/mips/jz4740/smp.c  | 258 
 arch/mips/kernel/idle.c |  35 -
 7 files changed, 447 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/include/asm/mach-jz4740/smp.h
 create mode 100644 arch/mips/jz4740/smp-entry.S
 create mode 100644 arch/mips/jz4740/smp.c

diff --git a/arch/mips/include/asm/mach-jz4740/smp.h 
b/arch/mips/include/asm/mach-jz4740/smp.h
new file mode 100644
index ..86f660f
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/smp.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Copyright (C) 2013, Paul Burton 
+ *  JZ4780 SMP definitions
+ */
+
+#ifndef __MIPS_ASM_MACH_JZ4740_SMP_H__
+#define __MIPS_ASM_MACH_JZ4740_SMP_H__
+
+#define read_c0_corectrl() __read_32bit_c0_register($12, 2)
+#define write_c0_corectrl(val) __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_corestatus()   __read_32bit_c0_register($12, 3)
+#define write_c0_corestatus(val)   __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_reim() __read_32bit_c0_register($12, 4)
+#define write_c0_reim(val) __write_32bit_c0_register($12, 4, val)
+
+#define read_c0_mailbox0() __read_32bit_c0_register($20, 0)
+#define write_c0_mailbox0(val) __write_32bit_c0_register($20, 0, val)
+
+#define read_c0_mailbox1() __read_32bit_c0_register($20, 1)
+#define write_c0_mailbox1(val) __write_32bit_c0_register($20, 1, val)
+
+#define read_c0_mailbox2() __read_32bit_c0_register($20, 2)
+#define write_c0_mailbox2(val) __write_32bit_c0_register($20, 2, val)
+
+#define read_c0_mailbox3() __read_32bit_c0_register($20, 3)
+#define write_c0_mailbox3(val) __write_32bit_c0_register($20, 3, val)
+
+#define smp_clr_pending(mask) do { \
+   unsigned int stat;  \
+   stat = read_c0_corestatus();\
+   stat &= ~((mask) & 0xff);   \
+   write_c0_corestatus(stat);  \
+   } while (0)
+
+/*
+ * Core Control register
+ */
+#define CORECTRL_SLEEP1M_SHIFT 17
+#define CORECTRL_SLEEP1M   (_ULCAST_(0x1) << CORECTRL_SLEEP1M_SHIFT)
+#define CORECTRL_SLEEP0M_SHIFT 16
+#define CORECTRL_SLEEP0M   (_ULCAST_(0x1) << CORECTRL_SLEEP0M_SHIFT)
+#define CORECTRL_RPC1_SHIFT9
+#define CORECTRL_RPC1  (_ULCAST_(0x1) << CORECTRL_RPC1_SHIFT)
+#define CORECTRL_RPC0_SHIFT8
+#define CORECTRL_RPC0  (_ULCAST_(0x1) << CORECTRL_RPC0_SHIFT)
+#define CORECTRL_SWRST1_SHIFT  1
+#define CORECTRL_SWRST1(_ULCAST_(0x1) << CORECTRL_SWRST1_SHIFT)
+#define CORECTRL_SWRST0_SHIFT  0
+#define CORECTRL_SWRST0(_ULCAST_(0x1) << CORECTRL_SWRST0_SHIFT)
+
+/*
+ * Core Status register
+ */
+#define CORESTATUS_SLEEP1_SHIFT17
+#define CORESTATUS_SLEEP1  (_ULCAST_(0x1) << CORESTATUS_SLEEP1_SHIFT)
+#define CORESTATUS_SLEEP0_SHIFT16
+#define CORESTATUS_SLEEP0  (_ULCAST_(0x1) << CORESTATUS_SLEEP0_SHIFT)
+#define CORESTATUS_IRQ1P_SHIFT 9
+#define CORESTATUS_IRQ1P   (_ULCAST_(0x1) << CORESTATUS_IRQ1P_SHIFT)
+#define CORESTATUS_IRQ0P_SHIFT 8

Re: [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support.

[Zhou Yanjie]

Hi Paul,

On 2020年05月20日 03:41, Paul Cercueil wrote:

Hi Zhou,

Le mar. 19 mai 2020 à 22:35, 周琰杰 (Zhou Yanjie) 
 a écrit :

Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Jiaxun Yang 
---

Notes:
v1->v2:
1.Remove unnecessary "plat_irq_dispatch(void)" in irq-ingenic.c.
2.Add a timeout check for "jz4780_boot_secondary()" to avoid a 
dead loop.

3.Replace hard code in smp.c with macro.

v2->v3:
1.Remove unnecessary "extern void (*r4k_blast_dcache)(void)" in 
smp.c.
2.Use "for_each_of_cpu_node" instead "for_each_compatible_node" 
in smp.c.
3.Use "of_cpu_node_to_id" instead "of_property_read_u32_index" in 
smp.c.

4.Move LCR related operations to jz4780-cgu.c.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
1.Splitting changes involving "jz4780-cgu.c" into separate commit.
2.Use "request_irq()" replace "setup_irq()".

v5->v6:
In order to have a kernel that works on multiple SoCs at the same
time, use "IS_ENABLED()" replace "#ifdef".

v6->v7:
1.SMP has be decoupled from the SoC version.
2.Add mailboxes 3 and 4 for XBurst.
3.Adjust code in "jz4780_smp_prepare_cpus()".
4."jz4780_smp_init()" has be marked "__init".

v7->v8:
No change.

 arch/mips/include/asm/mach-jz4740/smp.h |  87 +++
 arch/mips/jz4740/Kconfig|   2 +
 arch/mips/jz4740/Makefile   |   5 +
 arch/mips/jz4740/prom.c |   4 +
 arch/mips/jz4740/smp-entry.S|  57 +++
 arch/mips/jz4740/smp.c  | 258 


 arch/mips/kernel/idle.c |  35 -
 7 files changed, 447 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/include/asm/mach-jz4740/smp.h
 create mode 100644 arch/mips/jz4740/smp-entry.S
 create mode 100644 arch/mips/jz4740/smp.c

diff --git a/arch/mips/include/asm/mach-jz4740/smp.h 
b/arch/mips/include/asm/mach-jz4740/smp.h

new file mode 100644
index ..86f660f
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/smp.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Copyright (C) 2013, Paul Burton 
+ *  JZ4780 SMP definitions
+ */
+
+#ifndef __MIPS_ASM_MACH_JZ4740_SMP_H__
+#define __MIPS_ASM_MACH_JZ4740_SMP_H__
+
+#define read_c0_corectrl()__read_32bit_c0_register($12, 2)
+#define write_c0_corectrl(val) __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_corestatus() __read_32bit_c0_register($12, 3)
+#define write_c0_corestatus(val) __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_reim()__read_32bit_c0_register($12, 4)
+#define write_c0_reim(val) __write_32bit_c0_register($12, 4, val)
+
+#define read_c0_mailbox0()__read_32bit_c0_register($20, 0)
+#define write_c0_mailbox0(val) __write_32bit_c0_register($20, 0, val)
+
+#define read_c0_mailbox1()__read_32bit_c0_register($20, 1)
+#define write_c0_mailbox1(val) __write_32bit_c0_register($20, 1, val)
+
+#define read_c0_mailbox2()__read_32bit_c0_register($20, 2)
+#define write_c0_mailbox2(val) __write_32bit_c0_register($20, 2, val)
+
+#define read_c0_mailbox3()__read_32bit_c0_register($20, 3)
+#define write_c0_mailbox3(val) __write_32bit_c0_register($20, 3, val)
+
+#define smp_clr_pending(mask) do {\
+unsigned int stat;\
+stat = read_c0_corestatus();\
+stat &= ~((mask) & 0xff);\
+write_c0_corestatus(stat);\
+} while (0)
+
+/*
+ * Core Control register
+ */
+#define CORECTRL_SLEEP1M_SHIFT17
+#define CORECTRL_SLEEP1M(_ULCAST_(0x1) << CORECTRL_SLEEP1M_SHIFT)
+#define CORECTRL_SLEEP0M_SHIFT16
+#define CORECTRL_SLEEP0M(_ULCAST_(0x1) << CORECTRL_SLEEP0M_SHIFT)
+#define CORECTRL_RPC1_SHIFT9
+#define CORECTRL_RPC1(_ULCAST_(0x1) << CORECTRL_RPC1_SHIFT)
+#define CORECTRL_RPC0_SHIFT8
+#define CORECTRL_RPC0(_ULCAST_(0x1) << CORECTRL_RPC0_SHIFT)
+#define CORECTRL_SWRST1_SHIFT1
+#define CORECTRL_SWRST1(_ULCAST_(0x1) << CORECTRL_SWRST1_SHIFT)
+#define CORECTRL_SWRST0_SHIFT0
+#define CORECTRL_SWRST0(_ULCAST_(0x1) << CORECTRL_SWRST0_SHIFT)
+
+/*
+ * Core Status register
+ */
+#define CORESTATUS_SLEEP1_SHIFT17
+#define CORESTATUS_SLEEP1(_ULCAST_(0x1) << CORESTATUS_SLEEP1_SHIFT)
+#define CORESTATUS_SLEEP0_SHIFT16
+#define CORESTATUS_SLEEP0(_ULCAST_(0x1) << CORESTATUS_SLEEP0_SHIFT)
+#define CORESTATUS_IRQ1P_SHIFT9
+#define CORESTATUS_IRQ1P(_ULCAST_(0x1) << CORESTATUS_IRQ1P_SHIFT)
+#define CORESTATUS_IRQ0P_SHIFT8
+#define CORESTATUS_IRQ0P(_ULCAST_(0x1) << CORES

Re: [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support.

[Zhou Yanjie]

On 2020年05月20日 00:09, Paul Cercueil wrote:

Hi Zhou,

Le mar. 19 mai 2020 à 22:35, 周琰杰 (Zhou Yanjie) 
 a écrit :

Forward port smp support from kernel 3.18.3 of CI20_linux
to upstream kernel 5.6.

Tested-by: H. Nikolaus Schaller 
Tested-by: Paul Boddie 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Jiaxun Yang 
---

Notes:
v1->v2:
1.Remove unnecessary "plat_irq_dispatch(void)" in irq-ingenic.c.
2.Add a timeout check for "jz4780_boot_secondary()" to avoid a 
dead loop.

3.Replace hard code in smp.c with macro.

v2->v3:
1.Remove unnecessary "extern void (*r4k_blast_dcache)(void)" in 
smp.c.
2.Use "for_each_of_cpu_node" instead "for_each_compatible_node" 
in smp.c.
3.Use "of_cpu_node_to_id" instead "of_property_read_u32_index" in 
smp.c.

4.Move LCR related operations to jz4780-cgu.c.

v3->v4:
Rebase on top of kernel 5.6-rc1.

v4->v5:
1.Splitting changes involving "jz4780-cgu.c" into separate commit.
2.Use "request_irq()" replace "setup_irq()".

v5->v6:
In order to have a kernel that works on multiple SoCs at the same
time, use "IS_ENABLED()" replace "#ifdef".

v6->v7:
1.SMP has be decoupled from the SoC version.
2.Add mailboxes 3 and 4 for XBurst.
3.Adjust code in "jz4780_smp_prepare_cpus()".
4."jz4780_smp_init()" has be marked "__init".

v7->v8:
No change.

 arch/mips/include/asm/mach-jz4740/smp.h |  87 +++
 arch/mips/jz4740/Kconfig|   2 +
 arch/mips/jz4740/Makefile   |   5 +
 arch/mips/jz4740/prom.c |   4 +
 arch/mips/jz4740/smp-entry.S|  57 +++
 arch/mips/jz4740/smp.c  | 258 


 arch/mips/kernel/idle.c |  35 -
 7 files changed, 447 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/include/asm/mach-jz4740/smp.h
 create mode 100644 arch/mips/jz4740/smp-entry.S
 create mode 100644 arch/mips/jz4740/smp.c

diff --git a/arch/mips/include/asm/mach-jz4740/smp.h 
b/arch/mips/include/asm/mach-jz4740/smp.h

new file mode 100644
index ..86f660f
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/smp.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ *  Copyright (C) 2013, Paul Burton 
+ *  JZ4780 SMP definitions
+ */
+
+#ifndef __MIPS_ASM_MACH_JZ4740_SMP_H__
+#define __MIPS_ASM_MACH_JZ4740_SMP_H__
+
+#define read_c0_corectrl()__read_32bit_c0_register($12, 2)
+#define write_c0_corectrl(val) __write_32bit_c0_register($12, 2, val)
+
+#define read_c0_corestatus() __read_32bit_c0_register($12, 3)
+#define write_c0_corestatus(val) __write_32bit_c0_register($12, 3, val)
+
+#define read_c0_reim()__read_32bit_c0_register($12, 4)
+#define write_c0_reim(val) __write_32bit_c0_register($12, 4, val)
+
+#define read_c0_mailbox0()__read_32bit_c0_register($20, 0)
+#define write_c0_mailbox0(val) __write_32bit_c0_register($20, 0, val)
+
+#define read_c0_mailbox1()__read_32bit_c0_register($20, 1)
+#define write_c0_mailbox1(val) __write_32bit_c0_register($20, 1, val)
+
+#define read_c0_mailbox2()__read_32bit_c0_register($20, 2)
+#define write_c0_mailbox2(val) __write_32bit_c0_register($20, 2, val)
+
+#define read_c0_mailbox3()__read_32bit_c0_register($20, 3)
+#define write_c0_mailbox3(val) __write_32bit_c0_register($20, 3, val)
+
+#define smp_clr_pending(mask) do {\
+unsigned int stat;\
+stat = read_c0_corestatus();\
+stat &= ~((mask) & 0xff);\
+write_c0_corestatus(stat);\
+} while (0)
+
+/*
+ * Core Control register
+ */
+#define CORECTRL_SLEEP1M_SHIFT17
+#define CORECTRL_SLEEP1M(_ULCAST_(0x1) << CORECTRL_SLEEP1M_SHIFT)
+#define CORECTRL_SLEEP0M_SHIFT16
+#define CORECTRL_SLEEP0M(_ULCAST_(0x1) << CORECTRL_SLEEP0M_SHIFT)
+#define CORECTRL_RPC1_SHIFT9
+#define CORECTRL_RPC1(_ULCAST_(0x1) << CORECTRL_RPC1_SHIFT)
+#define CORECTRL_RPC0_SHIFT8
+#define CORECTRL_RPC0(_ULCAST_(0x1) << CORECTRL_RPC0_SHIFT)
+#define CORECTRL_SWRST1_SHIFT1
+#define CORECTRL_SWRST1(_ULCAST_(0x1) << CORECTRL_SWRST1_SHIFT)
+#define CORECTRL_SWRST0_SHIFT0
+#define CORECTRL_SWRST0(_ULCAST_(0x1) << CORECTRL_SWRST0_SHIFT)
+
+/*
+ * Core Status register
+ */
+#define CORESTATUS_SLEEP1_SHIFT17
+#define CORESTATUS_SLEEP1(_ULCAST_(0x1) << CORESTATUS_SLEEP1_SHIFT)
+#define CORESTATUS_SLEEP0_SHIFT16
+#define CORESTATUS_SLEEP0(_ULCAST_(0x1) << CORESTATUS_SLEEP0_SHIFT)
+#define CORESTATUS_IRQ1P_SHIFT9
+#define CORESTATUS_IRQ1P(_ULCAST_(0x1) << CORESTATUS_IRQ1P_SHIFT)
+#define CORESTATUS_IRQ0P_SHIFT8
+#define CORESTATUS_IRQ0P(_ULCAST_(0x1) << CORES

Re: [PATCH] MIPS: Provide Kconfig option for default IEEE754 conformance mode

[Zhou Yanjie]

在 2020/8/3 下午5:01, Jiaxun Yang 写道:



在 2020/8/3 上午5:46, Maciej W. Rozycki 写道:

On Fri, 31 Jul 2020, Serge Semin wrote:


Requested by downstream distros, a Kconfig option for default
IEEE754 conformance mode allows them to set their mode to
relaxed by default.

That's what should have been here in the first place. Thanks!

  Well, originally plans were there to have NaN interlinking implemented
and no such mess or desire for hacks like one here would result.  Cf.:

,
,

and then:

,
,
,
.

You could well pick this work up and complete it if you like. Final
conclusions for further work were made here:

,
,
.

  In the relaxed mode math programs may produce wrong results unless you
rebuild all your software for the correct NaN mode for the hardware used


Unfortunately most of the hardware guys didn't understood the 
difficulty here.
They decided to implement their hardware (P5600 & LS3A4000) as NaN2008 
only.




All SoCs based on Ingenic XBurst2 CPU core are also NaN2008 only.


I was thinking about let Kernel drop SIGFPE exception was caused by 
mismatched NaN,
as most applications don't rely on signaling NaN, but it is still a 
dirty hack. Not a good

idea in general.

Thanks.

- Jiaxun


(in which case you don't need the relaxed setting in the first place).




   Maciej

Re: [PATCH] MIPS: CI20: Update defconfig for EFUSE.

[Zhou Yanjie]

Hi Paul,

在 2020/7/28 下午11:40, Paul Cercueil 写道:

Hi Zhou,

Le sam. 25 juil. 2020 à 16:02, Zhou Yanjie  
a écrit :

Hi Paul,

在 2020/7/23 下午4:47, Paul Cercueil 写道:

Hi Zhou,

Le jeu. 23 juil. 2020 à 15:19, 周琰杰 (Zhou Yanjie) 
 a écrit :

The commit 19c968222934 ("MIPS: DTS: CI20: make DM9000 Ethernet
controller use NVMEM to find the default MAC address") add EFUSE
node for DM9000 in CI20, however, the EFUSE driver is not selected,
which will cause the DM9000 to fail to read the MAC address from
EFUSE, causing the following issue:

[FAILED] Failed to start Raise network interfaces.

Fix this problem by select CONFIG_JZ4780_EFUSE by default in the
ci20_defconfig.


Does it actually fix it on a clean 5.8-rc kernel?

From what I know, the efuse driver cannot probe, because the nemc 
driver requests the complete memory resource, so the efuse driver's 
devm_platform_ioremap_resource() fails.


I did send a patch to fix this 
(https://lore.kernel.org/lkml/551a8560261543c1decb1d4d1671ec4b7fa52fdb.1582905653.git@goldelico.com/),
but it's hard to have somebody merge it, because nobody maintains 
drivers/memory/.


You are right, I cleaned up the changes made to support X1000's EFUSE 
and rebase to clean 5.8-RC6, it still does not work properly, I think 
we should drop this fix patch.


The patch I mentioned was merged, so starting from 5.9-rc1 the efuse 
driver should work. Please resend this patch after 5.9-rc1 then.




Sure, I will resent when 5.9-rc1 is released.

Thanks and best regards!


Thanks,
-Paul




Fixes: 19c968222934 ("MIPS: DTS: CI20: make DM9000 Ethernet
controller use NVMEM to find the default MAC address").


That shouldn't be a fix IMHO - the devicetree was updated in one 
commit, the config should be updated in another. The "bug" here is 
that it wasn't done right away.



Okay.

Signed-off-by: 周琰杰 (Zhou Yanjie) 


Btw - when you add a Fixes: tag to fix a commit that is not for the 
kernel currently in RC phase, you need to Cc linux-stable as well.



Sure, I will pay attention next time.

Thanks and best regards!



Cheers,
-Paul


---
 arch/mips/configs/ci20_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/configs/ci20_defconfig 
b/arch/mips/configs/ci20_defconfig

index f433fad16073..ba26ba4de09a 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -140,6 +140,7 @@ CONFIG_INGENIC_OST=y
 CONFIG_MEMORY=y
 CONFIG_PWM=y
 CONFIG_PWM_JZ4740=m
+CONFIG_JZ4780_EFUSE=y
 CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_AUTOFS_FS=y
--
2.11.0

Re: [PATCH v2] MIPS: Provide Kconfig option for default IEEE 754 conformance mode

[Zhou Yanjie]

Hello Jiaxun,

Reviewed-by: 周琰杰 (Zhou Yanjie) 

在 2020/8/1 下午2:11, Jiaxun Yang 写道:

Requested by downstream distros, a Kconfig option for default
IEEE 754 conformance mode allows them to set their mode to
relaxed by default.

Signed-off-by: Jiaxun Yang 
Reviewed-by: WANG Xuerui 
Reviewed-by: Serge Semin 
Reviewed-by: Huacai Chen 

--
v2: Reword according to Xuerui's suggestion.
---
  arch/mips/Kconfig| 22 ++
  arch/mips/kernel/cpu-probe.c | 12 +++-
  2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index eaf7519e3033..ac35df2b9133 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2899,6 +2899,28 @@ config MIPS_NR_CPU_NR_MAP
default 1024 if MIPS_NR_CPU_NR_MAP_1024
default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024
  
+choice

+   prompt "Default IEEE 754 conformance mode"
+   default IEEE754_DEFAULT_STRICT
+   help
+ Sets the default IEEE 754 conformance mode, same as overriding the
+ default value for the ieee754= kernel parameter. See the kernel
+ parameter for details.
+
+   config IEEE754_DEFAULT_STRICT
+   bool "Strict"
+
+   config IEEE754_DEFAULT_LEGACY
+   bool "Legacy"
+
+   config IEEE754_DEFAULT_STD2008
+   bool "2008"
+
+   config IEEE754_DEFAULT_RELAXED
+   bool "Relaxed"
+
+endchoice
+
  #
  # Timer Interrupt Frequency Configuration
  #
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c231c1b67889..a5b8fe019afc 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -157,7 +157,17 @@ static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
   * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
   * ABS.fmt/NEG.fmt execution mode.
   */
-static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
+enum ieee754_mode { STRICT, LEGACY, STD2008, RELAXED };
+
+#if defined(CONFIG_IEEE754_DEFAULT_STRICT)
+static enum ieee754_mode ieee754 = STRICT;
+#elif defined(CONFIG_IEEE754_DEFAULT_LEGACY)
+static enum ieee754_mode ieee754 = LEGACY;
+#elif defined(CONFIG_IEEE754_DEFAULT_STD2008)
+static enum ieee754_mode ieee754 = STD2008;
+#elif defined(CONFIG_IEEE754_DEFAULT_RELAXED)
+static enum ieee754_mode ieee754 = RELAXED;
+#endif
  
  /*

   * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes

Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board

[Zhou Yanjie]

Hi Paul,

I'm not too sure if remove "cpu-feature-overrides.h" will cause some 
problems for X2000, because according to my current test on X2000, I 
found that it is somewhat different from the SoCs using XBurst1 CPU 
core, with the kernel source code provided by Ingenic, for example, we 
must configure "#define cpu_has_tlbinv 1" in "cpu-feature-overrides.h" 
to make the X2000 work normally, otherwise the kernel will get stuck. 
And X2000's interrupt controller has also been redesigned. If these 
differences make it impossible to share code, should we set a 
subdirectory of "xburst" and "xburst2" in "arch/mips/ingenic"? (I am 
just worried about this situation, so far I have not been able to 
successfully run the mainline kernel on X2000).


I have added some related engineers from Ingenic to CC

Thanks and best regards!

在 2020/8/4 上午1:01, Paul Cercueil 写道:

Hi Thomas & list,

Here is a set of patches for 5.10 (no rush) to move Ingenic support from
arch/mips/jz4740/ to arch/mips/generic/.

There are some Kconfig changes that I think should be reviewed in detail
to avoid breakages elsewhere. The idea behind these changes is to allow
the Ingenic "generic" code to be built in a non-generic kernel, since
generic kernels bring lots of dependencies which result in a +7% size
increase.

Support for booting the generic kernel with a built-in and/or appended
devicetree, as well as support for compressed (vmlinuz) kernels, has
been added as well.

Cheers,
-Paul

Paul Cercueil (13):
   MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
   MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches
   MIPS: cpu-probe: ingenic: Fix broken BUG_ON
   MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol
   MIPS: machine: Add get_system_type callback
   MIPS: generic: Call the machine's .get_system_type callback if
 provided
   MIPS: generic: Support booting with built-in or appended DTB
   MIPS: generic: Add support for zboot
   MIPS: generic: Increase NR_IRQS to 256
   MIPS: generic: Add support for Ingenic SoCs
   MIPS: jz4740: Drop folder
   MIPS: configs: Regenerate configs of Ingenic boards
   MAINTAINERS: Update paths to Ingenic platform code

  MAINTAINERS   |   4 +-
  arch/mips/Kbuild.platforms|   1 -
  arch/mips/Kconfig |  43 --
  arch/mips/configs/ci20_defconfig  |   4 +-
  arch/mips/configs/cu1000-neo_defconfig|  16 +-
  arch/mips/configs/gcw0_defconfig  |   2 +-
  arch/mips/configs/qi_lb60_defconfig   |   5 +-
  arch/mips/configs/rs90_defconfig  |   4 +-
  arch/mips/generic/Kconfig |   8 +-
  arch/mips/generic/Makefile|   2 +-
  arch/mips/generic/Platform|   1 +
  arch/mips/generic/board-ingenic.c | 108 +
  arch/mips/generic/init.c  |  28 +++-
  arch/mips/generic/proc.c  |  25 ---
  arch/mips/include/asm/mach-generic/irq.h  |   2 +-
  .../asm/mach-jz4740/cpu-feature-overrides.h   |  50 --
  arch/mips/include/asm/mach-jz4740/irq.h   |  13 --
  arch/mips/include/asm/machine.h   |   1 +
  arch/mips/include/asm/pgtable-bits.h  |   5 -
  arch/mips/{jz4740 => ingenic}/Kconfig |  16 +-
  arch/mips/jz4740/Makefile |   9 --
  arch/mips/jz4740/Platform |   3 -
  arch/mips/jz4740/setup.c  | 145 --
  arch/mips/kernel/cpu-probe.c  |   8 +-
  24 files changed, 198 insertions(+), 305 deletions(-)
  create mode 100644 arch/mips/generic/board-ingenic.c
  delete mode 100644 arch/mips/generic/proc.c
  delete mode 100644 arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
  delete mode 100644 arch/mips/include/asm/mach-jz4740/irq.h
  rename arch/mips/{jz4740 => ingenic}/Kconfig (91%)
  delete mode 100644 arch/mips/jz4740/Makefile
  delete mode 100644 arch/mips/jz4740/Platform
  delete mode 100644 arch/mips/jz4740/setup.c

Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board

[Zhou Yanjie]

Hi Paul,

在 2020/8/8 上午12:45, Paul Cercueil 写道:

Hi Zhou,

Le sam. 8 août 2020 à 0:23, Zhou Yanjie  a 
écrit :

Hi Paul,

I'm not too sure if remove "cpu-feature-overrides.h" will cause some 
problems for X2000, because according to my current test on X2000, I 
found that it is somewhat different from the SoCs using XBurst1 CPU 
core, with the kernel source code provided by Ingenic, for example, 
we must configure "#define cpu_has_tlbinv 1" in 
"cpu-feature-overrides.h" to make the X2000 work normally, otherwise 
the kernel will get stuck. And X2000's interrupt controller has also 
been redesigned. If these differences make it impossible to share 
code, should we set a subdirectory of "xburst" and "xburst2" in 
"arch/mips/ingenic"? (I am just worried about this situation, so far 
I have not been able to successfully run the mainline kernel on X2000).


The  is kind of a hack, to hardcode settings 
in case the CPU is not properly detected. The cpu-probe.c should be 
able to auto-detect these settings, including the inverted TLB that 
the X2000 has, reading from the CPU config registers ("TLB INV" info 
should be in config4). Right now cpu_probe_ingenic() doesn't read 
config4 (not present on older SoCs) but that's trivial to add.


As for your other question, I don't see any reason why we wouldn't be 
able to support the X2000 aside the others in a generic kernel, so 
don't worry :)



OK, this is good news for me.



Cheers,
-Paul



I have added some related engineers from Ingenic to CC

Thanks and best regards!

在 2020/8/4 上午1:01, Paul Cercueil 写道:

Hi Thomas & list,

Here is a set of patches for 5.10 (no rush) to move Ingenic support 
from

arch/mips/jz4740/ to arch/mips/generic/.

There are some Kconfig changes that I think should be reviewed in 
detail

to avoid breakages elsewhere. The idea behind these changes is to allow
the Ingenic "generic" code to be built in a non-generic kernel, since
generic kernels bring lots of dependencies which result in a +7% size
increase.

Support for booting the generic kernel with a built-in and/or appended
devicetree, as well as support for compressed (vmlinuz) kernels, has
been added as well.

Cheers,
-Paul

Paul Cercueil (13):
   MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
   MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches
   MIPS: cpu-probe: ingenic: Fix broken BUG_ON
   MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol
   MIPS: machine: Add get_system_type callback
   MIPS: generic: Call the machine's .get_system_type callback if
 provided
   MIPS: generic: Support booting with built-in or appended DTB
   MIPS: generic: Add support for zboot
   MIPS: generic: Increase NR_IRQS to 256
   MIPS: generic: Add support for Ingenic SoCs
   MIPS: jz4740: Drop folder
   MIPS: configs: Regenerate configs of Ingenic boards
   MAINTAINERS: Update paths to Ingenic platform code

  MAINTAINERS   |   4 +-
  arch/mips/Kbuild.platforms    |   1 -
  arch/mips/Kconfig |  43 --
  arch/mips/configs/ci20_defconfig  |   4 +-
  arch/mips/configs/cu1000-neo_defconfig    |  16 +-
  arch/mips/configs/gcw0_defconfig  |   2 +-
  arch/mips/configs/qi_lb60_defconfig   |   5 +-
  arch/mips/configs/rs90_defconfig  |   4 +-
  arch/mips/generic/Kconfig |   8 +-
  arch/mips/generic/Makefile    |   2 +-
  arch/mips/generic/Platform    |   1 +
  arch/mips/generic/board-ingenic.c | 108 +
  arch/mips/generic/init.c  |  28 +++-
  arch/mips/generic/proc.c  |  25 ---
  arch/mips/include/asm/mach-generic/irq.h  |   2 +-
  .../asm/mach-jz4740/cpu-feature-overrides.h   |  50 --
  arch/mips/include/asm/mach-jz4740/irq.h   |  13 --
  arch/mips/include/asm/machine.h   |   1 +
  arch/mips/include/asm/pgtable-bits.h  |   5 -
  arch/mips/{jz4740 => ingenic}/Kconfig |  16 +-
  arch/mips/jz4740/Makefile |   9 --
  arch/mips/jz4740/Platform |   3 -
  arch/mips/jz4740/setup.c  | 145 
--

  arch/mips/kernel/cpu-probe.c  |   8 +-
  24 files changed, 198 insertions(+), 305 deletions(-)
  create mode 100644 arch/mips/generic/board-ingenic.c
  delete mode 100644 arch/mips/generic/proc.c
  delete mode 100644 
arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h

  delete mode 100644 arch/mips/include/asm/mach-jz4740/irq.h
  rename arch/mips/{jz4740 => ingenic}/Kconfig (91%)
  delete mode 100644 arch/mips/jz4740/Makefile
  delete mode 100644 arch/mips/jz4740/Platform
  delete mode 100644 arch/mips/jz4740/setup.c

Re: [PATCH 13/13] MAINTAINERS: Update paths to Ingenic platform code

[Zhou Yanjie]

Hi Paul,

在 2020/8/4 上午1:01, Paul Cercueil 写道:

Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.


The modification to "cu1830-neo_defconfig" seems to be missed here.

Thanks and best regards!



Signed-off-by: Paul Cercueil 
---
  MAINTAINERS | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index bddc79ae76e6..1d89029cb89a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8508,8 +8508,8 @@ INGENIC JZ47xx SoCs
  M:Paul Cercueil 
  S:Maintained
  F:arch/mips/boot/dts/ingenic/
-F: arch/mips/include/asm/mach-jz4740/
-F: arch/mips/jz4740/
+F: arch/mips/generic/board-ingenic.c
+F: arch/mips/ingenic/Kconfig
  F:drivers/clk/ingenic/
  F:drivers/dma/dma-jz4780.c
  F:drivers/gpu/drm/ingenic/

Re: [PATCH 13/13] MAINTAINERS: Update paths to Ingenic platform code

[Zhou Yanjie]

在 2020/8/8 上午1:22, Zhou Yanjie 写道:

Hi Paul,

在 2020/8/4 上午1:01, Paul Cercueil 写道:

Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.


The modification to "cu1830-neo_defconfig" seems to be missed here.


Sorry, this should be a reply to [12/13]  :(

Thanks and best regards!



Signed-off-by: Paul Cercueil 
---
  MAINTAINERS | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index bddc79ae76e6..1d89029cb89a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8508,8 +8508,8 @@ INGENIC JZ47xx SoCs
  M:    Paul Cercueil 
  S:    Maintained
  F:    arch/mips/boot/dts/ingenic/
-F:    arch/mips/include/asm/mach-jz4740/
-F:    arch/mips/jz4740/
+F:    arch/mips/generic/board-ingenic.c
+F:    arch/mips/ingenic/Kconfig
  F:    drivers/clk/ingenic/
  F:    drivers/dma/dma-jz4780.c
  F:    drivers/gpu/drm/ingenic/

Re: [PATCH v2 00/13] Convert Ingenic to a generic board v2

[Zhou Yanjie]

Hi Paul,

I have some good news and some bad news.

Good news is:

I tested this series of patches on CU1000-Neo & CU1830-Neo, and it can 
boot normally and log in to  debian normally.


Bad news is:

1. Because we dropped arch/mips/jz4740/setup.c, so it did not return 
MACH_INGENIC_ correctly, which caused the correction of the L2 cache 
probe in arch/mips/mm/sc-mips.c to fail, causing JZ4770/X1000 to detect 
the L2 cache capacity incorrect.


2. When I did some heavy work (compiled docker source code after logging 
in with ssh), the following message appeared:


message1:

[ 4694.290776] warn_alloc: 25 callbacks suppressed
[ 4694.290791] containerd-shim: page allocation failure: order:4, 
mode:0x40cc0(GFP_KERNEL|__GFP_COMP), nodemask=(null)
[ 4694.315266] CPU: 0 PID: 19817 Comm: containerd-shim Not tainted 
5.8.0-00013-g192f2fd7b678 #15
[ 4694.317993] Stack : 80ae 80a5 8086 809b8fb0 809e4a30 
850dfcb4  
[ 4694.320818] 80a5 80a576c7 809c4374 4d69 80ad348c 
0001 850dfc58 7750292a
[ 4694.322695]   809c4374 00fe 850dffe0 
1400 0199 
[ 4694.325083]  866f7600 80a5 878bd778 80a5 
8000 809c2b50 
[ 4694.326957] 00040cc0  01d2  80a53220 
7750292a a098 80ad

[ 4694.327750] ...
[ 4694.340943] Call Trace:
[ 4694.341181] [<8001ae08>] show_stack+0x6c/0x12c
[ 4694.355233] [<800f64b0>] warn_alloc+0xa8/0x130
[ 4694.361283] [<800f6dfc>] __alloc_pages_nodemask+0x8a4/0x8d8
[ 4694.362839] [<80103110>] cache_alloc+0x324/0x8fc
[ 4694.367439] [<801038e4>] __kmalloc+0x78/0xd8
[ 4694.376798] [<80195b28>] proc_sys_call_handler+0xf4/0x1d8
[ 4694.377229] [<80195c44>] proc_sys_read+0x14/0x20
[ 4694.384090] [<80116274>] vfs_read+0xac/0x108
[ 4694.385654] [<801165d4>] ksys_read+0x80/0xe0
[ 4694.395277] [<8001ec8c>] syscall_common+0x34/0x58
[ 4694.394544] Mem-Info:
[ 4694.396828] active_anon:661 inactive_anon:942 isolated_anon:0
[ 4694.396828]  active_file:10515 inactive_file:9667 isolated_file:0
[ 4694.396828]  unevictable:0 dirty:2003 writeback:0
[ 4694.396828]  slab_reclaimable:1609 slab_unreclaimable:3103
[ 4694.396828]  mapped:2182 shmem:156 pagetables:207 bounce:0
[ 4694.396828]  free:1635 free_pcp:7 free_cma:0
[ 4694.405770] Node 0 active_anon:2644kB inactive_anon:3768kB 
active_file:42060kB inactive_file:38668kB unevictable:0kB 
isolated(anon):0kB isolated(file):0kB mapped:8728kB dirty:8048kB 
writeback:0kB shmem:624kB writeback_tmp:0kB all_unreclaimable? no
[ 4694.408349] Normal free:6484kB min:1376kB low:1720kB high:2064kB 
reserved_highatomic:0KB active_anon:2644kB inactive_anon:3768kB 
active_file:42064kB inactive_file:38724kB unevictable:0kB 
writepending:8060kB present:131072kB managed:118804kB mlocked:0kB 
kernel_stack:584kB pagetables:828kB bounce:0kB free_pcp:32kB 
local_pcp:32kB free_cma:0kB

[ 4694.409607] lowmem_reserve[]: 0 0 0
[ 4694.410382] Normal: 117*4kB (UM) 406*8kB (UM) 149*16kB (UME) 12*32kB 
(UME) 0*64kB 0*128kB 0*256kB 0*512kB 0*1024kB 0*2048kB 0*4096kB = 6484kB

[ 4694.418673] 20618 total pagecache pages
[ 4694.423125] 226 pages in swap cache
[ 4694.423912] Swap cache stats: add 535090, delete 534864, find 
234586/366812

[ 4694.431304] Free swap  = 774396kB
[ 4694.431900] Total swap = 786428kB
[ 4694.432480] 32768 pages RAM
[ 4694.432537] 0 pages HighMem/MovableOnly
[ 4694.441338] 3067 pages reserved
[ 4694.441770] 0 pages cma reserved

-

message2:

[ 4426.473667] warn_alloc: 27 callbacks suppressed
[ 4426.473681] kswapd0: page allocation failure: order:0, 
mode:0xa20(GFP_ATOMIC), nodemask=(null)
[ 4426.475946] CPU: 0 PID: 439 Comm: kswapd0 Not tainted 
5.8.0-00013-g192f2fd7b678 #15
[ 4426.478136] Stack : 80ae 80a5 8086 809b8fb0 809e4a30 
87c0dccc  
[ 4426.478301] 80a5 80a576c7 809c4374 01b7 80ad348c 
0001 87c0dc70 b7c290ba
[ 4426.478464]   809c4374  000f 
 019f 
[ 4426.478626] bff4ffd7 1c5e5f3c 80ae 31672d33 80a5 
 809c2b50 
[ 4426.478787] 0a20    0002 
804d392c  80ad

[ 4426.478940] ...
[ 4426.481390] Call Trace:
[ 4426.483842] [<8001ae08>] show_stack+0x6c/0x12c
[ 4426.48] [<800f64b0>] warn_alloc+0xa8/0x130
[ 4426.487275] [<800f6dfc>] __alloc_pages_nodemask+0x8a4/0x8d8
[ 4426.487382] [<800f6f80>] page_frag_alloc+0x74/0x144
[ 4426.489534] [<805fc1a4>] __napi_alloc_skb+0x88/0x118
[ 4426.491769] [<8052ed8c>] stmmac_napi_poll_rx+0x434/0xa94
[ 4426.494354] [<80613eb0>] net_rx_action+0x11c/0x310
[ 4426.496414] [<807ecd0c>] __do_softirq+0x10c/0x258
[ 4426.498395] [<800320c0>] __irq_exit_rcu+0x68/0xbc
[ 4426.500365] [<80032324>] irq_exit+0x10/0x1c
[ 4426.501844] [<804876b4>] plat_irq_dispatch+0x8c/0xb8
[ 4426.504076] [<800154f8>] handle_int+0x138/0x144
[ 4426.505883] [<8005280c>] ar

Re: [PATCH v2 12/13] MIPS: configs: Regenerate configs of Ingenic boards

[Zhou Yanjie]

在 2020/8/12 上午8:15, Paul Cercueil 写道:

For each board the MACH_INGENIC_SOC option was selected instead of
MACH_INGENIC. Nothing else was changed in the menuconfig.

Signed-off-by: Paul Cercueil 
---

Notes:
 v2: Update cu1830-neo board config as well.

  arch/mips/configs/ci20_defconfig   |  4 ++--
  arch/mips/configs/cu1000-neo_defconfig | 16 ++--
  arch/mips/configs/cu1830-neo_defconfig | 15 ++-
  arch/mips/configs/gcw0_defconfig   |  2 +-
  arch/mips/configs/qi_lb60_defconfig|  5 ++---
  arch/mips/configs/rs90_defconfig   |  4 ++--
  6 files changed, 11 insertions(+), 35 deletions(-)

diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index 0a46199fdc3f..052c5ad0f2b1 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -22,7 +22,7 @@ CONFIG_EMBEDDED=y
  # CONFIG_VM_EVENT_COUNTERS is not set
  # CONFIG_COMPAT_BRK is not set
  CONFIG_SLAB=y
-CONFIG_MACH_INGENIC=y
+CONFIG_MACH_INGENIC_SOC=y
  CONFIG_JZ4780_CI20=y
  CONFIG_HIGHMEM=y
  CONFIG_HZ_100=y
@@ -42,7 +42,7 @@ CONFIG_IP_PNP_DHCP=y
  # CONFIG_IPV6 is not set
  # CONFIG_WIRELESS is not set
  CONFIG_DEVTMPFS=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
  # CONFIG_ALLOW_DEV_COREDUMP is not set
  CONFIG_MTD=y
  CONFIG_MTD_RAW_NAND=y
diff --git a/arch/mips/configs/cu1000-neo_defconfig 
b/arch/mips/configs/cu1000-neo_defconfig
index 6b471cdb16cf..55d0690a3ffe 100644
--- a/arch/mips/configs/cu1000-neo_defconfig
+++ b/arch/mips/configs/cu1000-neo_defconfig
@@ -1,5 +1,3 @@
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_KERNEL_GZIP=y
  CONFIG_SYSVIPC=y
  CONFIG_NO_HZ_IDLE=y
  CONFIG_HIGH_RES_TIMERS=y
@@ -9,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y
  CONFIG_LOG_BUF_SHIFT=14
  CONFIG_CGROUPS=y
  CONFIG_MEMCG=y
-CONFIG_MEMCG_KMEM=y
  CONFIG_CGROUP_SCHED=y
  CONFIG_CGROUP_FREEZER=y
  CONFIG_CGROUP_DEVICE=y
@@ -17,13 +14,12 @@ CONFIG_CGROUP_CPUACCT=y
  CONFIG_NAMESPACES=y
  CONFIG_USER_NS=y
  CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL_SYSCALL=y

This has already been dropped in the current mips-next tree.

  CONFIG_KALLSYMS_ALL=y
  CONFIG_EMBEDDED=y
  # CONFIG_VM_EVENT_COUNTERS is not set
  # CONFIG_COMPAT_BRK is not set
  CONFIG_SLAB=y
-CONFIG_MACH_INGENIC=y
+CONFIG_MACH_INGENIC_SOC=y
  CONFIG_X1000_CU1000_NEO=y
  CONFIG_HIGHMEM=y
  CONFIG_HZ_100=y
@@ -32,7 +28,6 @@ CONFIG_HZ_100=y
  # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
  # CONFIG_COMPACTION is not set
  CONFIG_CMA=y
-CONFIG_CMA_AREAS=7
  CONFIG_NET=y
  CONFIG_PACKET=y
  CONFIG_UNIX=y
@@ -41,19 +36,16 @@ CONFIG_CFG80211=y
  CONFIG_UEVENT_HELPER=y
  CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
  CONFIG_DEVTMPFS=y
-# CONFIG_FW_LOADER is not set
  # CONFIG_ALLOW_DEV_COREDUMP is not set
  CONFIG_NETDEVICES=y
  CONFIG_STMMAC_ETH=y
  CONFIG_SMSC_PHY=y
  CONFIG_BRCMFMAC=y
-# CONFIG_INPUT_MOUSEDEV is not set
  # CONFIG_INPUT_KEYBOARD is not set
  # CONFIG_INPUT_MOUSE is not set
  # CONFIG_SERIO is not set
  CONFIG_VT_HW_CONSOLE_BINDING=y
  CONFIG_LEGACY_PTY_COUNT=2
-CONFIG_SERIAL_EARLYCON=y
  CONFIG_SERIAL_8250=y
  CONFIG_SERIAL_8250_CONSOLE=y
  CONFIG_SERIAL_8250_NR_UARTS=3
@@ -67,8 +59,6 @@ CONFIG_GPIO_SYSFS=y
  CONFIG_SENSORS_ADS7828=y
  CONFIG_WATCHDOG=y
  CONFIG_JZ4740_WDT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
  # CONFIG_VGA_CONSOLE is not set
  # CONFIG_HID is not set
  # CONFIG_USB_SUPPORT is not set
@@ -83,8 +73,6 @@ CONFIG_RTC_DRV_JZ4740=y
  CONFIG_DMADEVICES=y
  CONFIG_DMA_JZ4780=y
  # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
  CONFIG_EXT4_FS=y
  # CONFIG_DNOTIFY is not set
  CONFIG_AUTOFS_FS=y
@@ -109,8 +97,8 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=15
  CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
  CONFIG_DEBUG_INFO=y
  CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_FS=y
  CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
  CONFIG_PANIC_ON_OOPS=y
  CONFIG_PANIC_TIMEOUT=10
  # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/mips/configs/cu1830-neo_defconfig 
b/arch/mips/configs/cu1830-neo_defconfig
index cbfb62900273..e7064851a47a 100644
--- a/arch/mips/configs/cu1830-neo_defconfig
+++ b/arch/mips/configs/cu1830-neo_defconfig
@@ -1,5 +1,3 @@
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_KERNEL_GZIP=y
  CONFIG_SYSVIPC=y
  CONFIG_NO_HZ_IDLE=y
  CONFIG_HIGH_RES_TIMERS=y
@@ -9,7 +7,6 @@ CONFIG_IKCONFIG_PROC=y
  CONFIG_LOG_BUF_SHIFT=14
  CONFIG_CGROUPS=y
  CONFIG_MEMCG=y
-CONFIG_MEMCG_KMEM=y
  CONFIG_CGROUP_SCHED=y
  CONFIG_CGROUP_FREEZER=y
  CONFIG_CGROUP_DEVICE=y
@@ -22,7 +19,7 @@ CONFIG_EMBEDDED=y
  # CONFIG_VM_EVENT_COUNTERS is not set
  # CONFIG_COMPAT_BRK is not set
  CONFIG_SLAB=y
-CONFIG_MACH_INGENIC=y
+CONFIG_MACH_INGENIC_SOC=y
  CONFIG_X1830_CU1830_NEO=y
  CONFIG_HIGHMEM=y
  CONFIG_HZ_100=y
@@ -31,7 +28,6 @@ CONFIG_HZ_100=y
  # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
  # CONFIG_COMPACTION is not set
  CONFIG_CMA=y
-CONFIG_CMA_AREAS=7
  CONFIG_NET=y
  CONFIG_PACKET=y
  CONFIG_UNIX=y
@@ -40,7 +36,6 @@ CONFIG_CFG80211=y
  CONFIG_UEVENT_HELPER=y
  CONFIG_UEVENT_HEL

[PATCH v4 1/5] clk: JZ4780: Add function for disable the second core.

[Zhou Yanjie]

Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Paul Cercueil 
---

Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.

v2->v3:
No change.

v3->v4:
No change.

 drivers/clk/ingenic/jz4780-cgu.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 0268d23..dcca74e 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -252,8 +252,29 @@ static int jz4780_core1_enable(struct clk_hw *hw)
return 0;
 }
 
+static void jz4780_core1_disable(struct clk_hw *hw)
+{
+   struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
+   struct ingenic_cgu *cgu = ingenic_clk->cgu;
+   unsigned long flags;
+   u32 lcr, clkgr1;
+
+   spin_lock_irqsave(&cgu->lock, flags);
+
+   lcr = readl(cgu->base + CGU_REG_LCR);
+   lcr |= LCR_PD_SCPU;
+   writel(lcr, cgu->base + CGU_REG_LCR);
+
+   clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
+   clkgr1 |= CLKGR1_CORE1;
+   writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
+
+   spin_unlock_irqrestore(&cgu->lock, flags);
+}
+
 static const struct clk_ops jz4780_core1_ops = {
.enable = jz4780_core1_enable,
+   .disable = jz4780_core1_disable,
 };
 
 static const s8 pll_od_encoding[16] = {
-- 
2.7.4

[PATCH v4 2/5] dt-bindings: clock: Add missing clocks for Ingenic SoCs.

[Zhou Yanjie]

Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC
and the X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Paul Cercueil 
Acked-by: Rob Herring 
---

Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercueil's Reviewed-by and Rob Herring's Acked-by.

v2->v3:
No change.

v3->v4:
No change.

 include/dt-bindings/clock/x1000-cgu.h | 5 +
 include/dt-bindings/clock/x1830-cgu.h | 5 +
 2 files changed, 10 insertions(+)

diff --git a/include/dt-bindings/clock/x1000-cgu.h 
b/include/dt-bindings/clock/x1000-cgu.h
index f187e07..3e79f36 100644
--- a/include/dt-bindings/clock/x1000-cgu.h
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -50,5 +50,10 @@
 #define X1000_CLK_PDMA 35
 #define X1000_CLK_EXCLK_DIV512 36
 #define X1000_CLK_RTC  37
+#define X1000_CLK_MACPHY   38
+#define X1000_CLK_CIM  39
+#define X1000_CLK_AIC  40
+#define X1000_CLK_DMIC 41
+#define X1000_CLK_I2S  42
 
 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
diff --git a/include/dt-bindings/clock/x1830-cgu.h 
b/include/dt-bindings/clock/x1830-cgu.h
index 8845537..8da2997 100644
--- a/include/dt-bindings/clock/x1830-cgu.h
+++ b/include/dt-bindings/clock/x1830-cgu.h
@@ -53,5 +53,10 @@
 #define X1830_CLK_OST  38
 #define X1830_CLK_EXCLK_DIV512 39
 #define X1830_CLK_RTC  40
+#define X1830_CLK_MACPHY   41
+#define X1830_CLK_CIM  42
+#define X1830_CLK_AIC  43
+#define X1830_CLK_DMIC 44
+#define X1830_CLK_I2S  45
 
 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
-- 
2.7.4

[PATCH v4 3/5] clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830.

[Zhou Yanjie]

X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v2:
New patch.

v2->v3:
No change.

v3->v4:
No change.

 drivers/clk/ingenic/x1000-cgu.c | 11 ---
 drivers/clk/ingenic/x1830-cgu.c | 11 ---
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 9aa20b5..53e5fe0 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -296,12 +296,11 @@ static const struct ingenic_cgu_clk_info 
x1000_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR, 31 },
},
 
-   [X1000_CLK_MAC] = {
-   "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+   [X1000_CLK_MACPHY] = {
+   "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
.mux = { CGU_REG_MACCDR, 31, 1 },
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
-   .gate = { CGU_REG_CLKGR, 25 },
},
 
[X1000_CLK_LCD] = {
@@ -452,6 +451,12 @@ static const struct ingenic_cgu_clk_info 
x1000_cgu_clocks[] = {
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 21 },
},
+
+   [X1000_CLK_MAC] = {
+   "mac", CGU_CLK_GATE,
+   .parents = { X1000_CLK_AHB2 },
+   .gate = { CGU_REG_CLKGR, 25 },
+   },
 };
 
 static void __init x1000_cgu_init(struct device_node *np)
diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c
index 950aee2..59342bc 100644
--- a/drivers/clk/ingenic/x1830-cgu.c
+++ b/drivers/clk/ingenic/x1830-cgu.c
@@ -270,13 +270,12 @@ static const struct ingenic_cgu_clk_info 
x1830_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR0, 31 },
},
 
-   [X1830_CLK_MAC] = {
-   "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+   [X1830_CLK_MACPHY] = {
+   "mac_phy", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
 X1830_CLK_VPLL, X1830_CLK_EPLL },
.mux = { CGU_REG_MACCDR, 30, 2 },
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
-   .gate = { CGU_REG_CLKGR1, 4 },
},
 
[X1830_CLK_LCD] = {
@@ -428,6 +427,12 @@ static const struct ingenic_cgu_clk_info 
x1830_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR1, 1 },
},
 
+   [X1830_CLK_MAC] = {
+   "mac", CGU_CLK_GATE,
+   .parents = { X1830_CLK_AHB2 },
+   .gate = { CGU_REG_CLKGR1, 4 },
+   },
+
[X1830_CLK_OST] = {
"ost", CGU_CLK_GATE,
.parents = { X1830_CLK_EXCLK, -1, -1, -1 },
-- 
2.7.4

[PATCH v4 5/5] clk: Ingenic: Clean up and reformat the code.

[Zhou Yanjie]

1.When the clock does not have "CGU_CLK_MUX", the 2/3/4 bits in
  parents do not need to be filled with -1. When the clock have
  a "CGU_CLK_MUX" has only one bit, the 3/4 bits of parents do
  not need to be filled with -1. Clean up these unnecessary -1
  from all the -cgu.c files.
2.Reformat code, add missing blank lines, remove unnecessary
  commas and tabs, and align code.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
Remove unnecessary -1 and commas.

v2->v3:
No change.

v3->v4:
1.The -1 used for placeholders on the unused bits of the
  parents in the custom clock should not be removed.
2.Move "JZ4780_CLK_CORE1" from the "Gate-only clocks"
  class to the "Custom (SoC-specific)" class, because
  it belongs to the custom clock.

 drivers/clk/ingenic/jz4725b-cgu.c |  50 +++---
 drivers/clk/ingenic/jz4740-cgu.c  |  50 +++---
 drivers/clk/ingenic/jz4770-cgu.c  |  79 +++---
 drivers/clk/ingenic/jz4780-cgu.c  | 135 +++---
 drivers/clk/ingenic/x1000-cgu.c   | 120 -
 drivers/clk/ingenic/x1830-cgu.c   | 133 ++---
 6 files changed, 286 insertions(+), 281 deletions(-)

diff --git a/drivers/clk/ingenic/jz4725b-cgu.c 
b/drivers/clk/ingenic/jz4725b-cgu.c
index 8c38e72..f41cd76 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -17,7 +17,7 @@
 
 /* CGU register offsets */
 #define CGU_REG_CPCCR  0x00
-#define CGU_REG_LCR0x04
+#define CGU_REG_LCR0x04
 #define CGU_REG_CPPCR  0x10
 #define CGU_REG_CLKGR  0x20
 #define CGU_REG_OPCR   0x24
@@ -28,7 +28,7 @@
 #define CGU_REG_CIMCDR 0x78
 
 /* bits within the LCR register */
-#define LCR_SLEEP  BIT(0)
+#define LCR_SLEEP  BIT(0)
 
 static struct ingenic_cgu *cgu;
 
@@ -53,7 +53,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] 
= {
 
[JZ4725B_CLK_PLL] = {
"pll", CGU_CLK_PLL,
-   .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR,
.rate_multiplier = 1,
@@ -78,7 +78,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] 
= {
 
[JZ4725B_CLK_PLL_HALF] = {
"pll half", CGU_CLK_DIV,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
jz4725b_cgu_pll_half_div_table,
@@ -87,7 +87,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] 
= {
 
[JZ4725B_CLK_CCLK] = {
"cclk", CGU_CLK_DIV,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
@@ -96,7 +96,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] 
= {
 
[JZ4725B_CLK_HCLK] = {
"hclk", CGU_CLK_DIV,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
@@ -105,7 +105,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {
 
[JZ4725B_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
@@ -114,7 +114,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {
 
[JZ4725B_CLK_MCLK] = {
"mclk", CGU_CLK_DIV,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
@@ -123,7 +123,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {
 
[JZ4725B_CLK_IPU] = {
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
-   .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+   .parents = { JZ4725B_CLK_PLL },
.div = {
CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
jz4725b_cgu_cpccr_div_table,
@@ -133,14 +133,14 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {
 
 

[PATCH v4 4/5] clk: Ingenic: Add missing clocks for Ingenic SoCs.

[Zhou Yanjie]

Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
Add I2S clock for X1000.

v2->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY" to "Custom (SoC-specific)",
since there is more than just the "OTG PHY" clock.

v3->v4:
No change.

 drivers/clk/ingenic/x1000-cgu.c | 207 +++-
 drivers/clk/ingenic/x1830-cgu.c | 207 +++-
 2 files changed, 412 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 53e5fe0..f03dd47 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -58,6 +58,17 @@
 #define USBPCR1_REFCLKDIV_24   (0x1 << USBPCR1_REFCLKDIV_SHIFT)
 #define USBPCR1_REFCLKDIV_12   (0x0 << USBPCR1_REFCLKDIV_SHIFT)
 
+/* bits within the I2SCDR register */
+#define I2SCDR_I2PCS_SHIFT 31
+#define I2SCDR_I2PCS_MASK  (0x1 << I2SCDR_I2PCS_SHIFT)
+#define I2SCDR_I2CS_SHIFT  30
+#define I2SCDR_I2CS_MASK   (0x1 << I2SCDR_I2CS_SHIFT)
+#define I2SCDR_I2SDIV_M_SHIFT  13
+#define I2SCDR_I2SDIV_M_MASK   (0x1ff << I2SCDR_I2SDIV_M_SHIFT)
+#define I2SCDR_I2SDIV_N_SHIFT  0
+#define I2SCDR_I2SDIV_N_MASK   (0x1fff << I2SCDR_I2SDIV_N_SHIFT)
+#define I2SCDR_CE_I2S  BIT(29)
+
 static struct ingenic_cgu *cgu;
 
 static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
@@ -168,6 +179,175 @@ static const struct clk_ops x1000_otg_phy_ops = {
.is_enabled = x1000_usb_phy_is_enabled,
 };
 
+static u8 x1000_i2s_get_parent(struct clk_hw *hw)
+{
+   u32 i2scdr;
+
+   i2scdr = readl(cgu->base + CGU_REG_I2SCDR);
+
+   return (i2scdr & (I2SCDR_I2PCS_MASK | I2SCDR_I2CS_MASK)) >> 
I2SCDR_I2CS_SHIFT;
+}
+
+static int x1000_i2s_set_parent(struct clk_hw *hw, u8 idx)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(&cgu->lock, flags);
+   writel(idx << I2SCDR_I2CS_SHIFT, cgu->base + CGU_REG_I2SCDR);
+   spin_unlock_irqrestore(&cgu->lock, flags);
+
+   return 0;
+}
+
+static unsigned long x1000_i2s_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   unsigned m, n;
+   u32 i2scdr;
+
+   i2scdr = readl(cgu->base + CGU_REG_I2SCDR);
+
+   m = (i2scdr & I2SCDR_I2SDIV_M_MASK) >> I2SCDR_I2SDIV_M_SHIFT;
+   n = (i2scdr & I2SCDR_I2SDIV_N_MASK) >> I2SCDR_I2SDIV_N_SHIFT;
+
+   return div_u64((u64)parent_rate * m, n);
+}
+
+static unsigned long x1000_i2s_calc(unsigned long rate, unsigned long 
parent_rate,
+   unsigned *pm, unsigned *pn)
+{
+   u64 curr_delta, curr_m, curr_n, delta, m, n;
+
+   if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) {
+   m = 1;
+   n = parent_rate / rate;
+   goto out;
+   }
+
+   delta = rate;
+
+   /*
+* The length of M is 9 bits, its value must be between 1 and 511.
+* The length of N is 13 bits, its value must be between 2 and 8191,
+* and must not be less than 2 times of the value of M.
+*/
+   for (curr_m = 511; curr_m >= 1; curr_m--) {
+   curr_n = parent_rate * curr_m;
+   curr_delta = do_div(curr_n, rate);
+
+   if (curr_n < 2 * curr_m || curr_n > 8191)
+   continue;
+
+   if (curr_delta == 0)
+   break;
+
+   if (curr_delta < delta) {
+   m = curr_m;
+   n = curr_n;
+   delta = curr_delta;
+   }
+   }
+
+out:
+   if (pm)
+   *pm = m;
+   if (pn)
+   *pn = n;
+
+   return div_u64((u64)parent_rate * m, n);
+}
+
+static long x1000_i2s_round_rate(struct clk_hw *hw, unsigned long req_rate,
+   unsigned long *prate)
+{
+   return x1000_i2s_calc(req_rate, *prate, NULL, NULL);
+}
+
+static int x1000_i2s_set_rate(struct clk_hw *hw, unsigned long req_rate,
+   unsigned long parent_rate)
+{
+   unsigned long rate, flags;
+   unsigned m, n;
+   u32 ctl;
+
+   /*
+* The parent clock rate of I2S must not be lower than 2 times
+* of the target clock rate.
+*/
+   if (parent_rate < 2 * req_rate)
+   return -EINVAL;
+
+   rate = x1000_i2s_calc(req_rate, parent_rate, &m, &n);
+   if (rate != req_rate)
+   pr_info("%s: request I2S rate %luHz, actual %luHz\n", __func__,
+   req_rate, rate);
+
+   spi

[PATCH v4 0/5] Add new clocks and fix bugs for Ingenic SoCs.

[Zhou Yanjie]

v1->v2:
1.Add Paul Cercueil's Reviewed-by for [1/5] & [2/5],
  add Rob Herring's Acked-by for [2/5].
2.Add MACPHY and I2S for X1000, add MACPHY for X1830,
  and fix bugs in MAC clock.
3.Clean up code, remove unnecessary -1 and commas and
  tabs from all the -cgu.c files.

v2->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY" to "Custom (SoC-specific)",
since there is more than just the "OTG PHY" clock.

v3->v4:
1.The -1 used for placeholders on the unused bits of the
  parents in the custom clock should not be removed.
2.Move "JZ4780_CLK_CORE1" from the "Gate-only clocks"
  class to the "Custom (SoC-specific)" class, because
  it belongs to the custom clock.

周琰杰 (Zhou Yanjie) (5):
  clk: JZ4780: Add function for disable the second core.
  dt-bindings: clock: Add missing clocks for Ingenic SoCs.
  clk: Ingenic: Fix problem of MAC clock in Ingenic X1000 and X1830.
  clk: Ingenic: Add missing clocks for Ingenic SoCs.
  clk: Ingenic: Clean up and reformat the code.

 drivers/clk/ingenic/jz4725b-cgu.c |  50 ++---
 drivers/clk/ingenic/jz4740-cgu.c  |  50 ++---
 drivers/clk/ingenic/jz4770-cgu.c  |  79 
 drivers/clk/ingenic/jz4780-cgu.c  | 156 +---
 drivers/clk/ingenic/x1000-cgu.c   | 332 +++--
 drivers/clk/ingenic/x1830-cgu.c   | 341 +++---
 include/dt-bindings/clock/x1000-cgu.h |   5 +
 include/dt-bindings/clock/x1830-cgu.h |   5 +
 8 files changed, 737 insertions(+), 281 deletions(-)

-- 
2.7.4

Re: [PATCH v4 4/5] clk: Ingenic: Add missing clocks for Ingenic SoCs.

[Zhou Yanjie]

Hi Paul,

On 2020/12/23 下午8:29, Paul Cercueil wrote:

Hi Zhou,

Le lun. 21 déc. 2020 à 23:52, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v1->v2:
    Add I2S clock for X1000.

    v2->v3:
    Correct the comment in x1000-cgu.c, change it from
    "Custom (SoC-specific) OTG PHY" to "Custom (SoC-specific)",
    since there is more than just the "OTG PHY" clock.

    v3->v4:
    No change.

 drivers/clk/ingenic/x1000-cgu.c | 207 
+++-
 drivers/clk/ingenic/x1830-cgu.c | 207 
+++-

 2 files changed, 412 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/ingenic/x1000-cgu.c 
b/drivers/clk/ingenic/x1000-cgu.c

index 53e5fe0..f03dd47 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -58,6 +58,17 @@
 #define USBPCR1_REFCLKDIV_24    (0x1 << USBPCR1_REFCLKDIV_SHIFT)
 #define USBPCR1_REFCLKDIV_12    (0x0 << USBPCR1_REFCLKDIV_SHIFT)

+/* bits within the I2SCDR register */
+#define I2SCDR_I2PCS_SHIFT    31
+#define I2SCDR_I2PCS_MASK    (0x1 << I2SCDR_I2PCS_SHIFT)
+#define I2SCDR_I2CS_SHIFT    30
+#define I2SCDR_I2CS_MASK    (0x1 << I2SCDR_I2CS_SHIFT)
+#define I2SCDR_I2SDIV_M_SHIFT    13
+#define I2SCDR_I2SDIV_M_MASK    (0x1ff << I2SCDR_I2SDIV_M_SHIFT)
+#define I2SCDR_I2SDIV_N_SHIFT    0
+#define I2SCDR_I2SDIV_N_MASK    (0x1fff << I2SCDR_I2SDIV_N_SHIFT)
+#define I2SCDR_CE_I2S    BIT(29)
+
 static struct ingenic_cgu *cgu;

 static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
@@ -168,6 +179,175 @@ static const struct clk_ops x1000_otg_phy_ops = {
 .is_enabled    = x1000_usb_phy_is_enabled,
 };

+static u8 x1000_i2s_get_parent(struct clk_hw *hw)
+{
+    u32 i2scdr;
+
+    i2scdr = readl(cgu->base + CGU_REG_I2SCDR);
+
+    return (i2scdr & (I2SCDR_I2PCS_MASK | I2SCDR_I2CS_MASK)) >> 
I2SCDR_I2CS_SHIFT;

+}
+
+static int x1000_i2s_set_parent(struct clk_hw *hw, u8 idx)
+{
+    unsigned long flags;
+
+    spin_lock_irqsave(&cgu->lock, flags);
+    writel(idx << I2SCDR_I2CS_SHIFT, cgu->base + CGU_REG_I2SCDR);
+    spin_unlock_irqrestore(&cgu->lock, flags);
+
+    return 0;
+}
+
+static unsigned long x1000_i2s_recalc_rate(struct clk_hw *hw,
+    unsigned long parent_rate)
+{
+    unsigned m, n;
+    u32 i2scdr;
+
+    i2scdr = readl(cgu->base + CGU_REG_I2SCDR);
+
+    m = (i2scdr & I2SCDR_I2SDIV_M_MASK) >> I2SCDR_I2SDIV_M_SHIFT;
+    n = (i2scdr & I2SCDR_I2SDIV_N_MASK) >> I2SCDR_I2SDIV_N_SHIFT;
+
+    return div_u64((u64)parent_rate * m, n);
+}
+
+static unsigned long x1000_i2s_calc(unsigned long rate, unsigned 
long parent_rate,

+    unsigned *pm, unsigned *pn)
+{
+    u64 curr_delta, curr_m, curr_n, delta, m, n;
+
+    if ((parent_rate % rate == 0) && ((parent_rate / rate) > 1)) {
+    m = 1;
+    n = parent_rate / rate;
+    goto out;
+    }
+
+    delta = rate;
+
+    /*
+ * The length of M is 9 bits, its value must be between 1 and 511.
+ * The length of N is 13 bits, its value must be between 2 and 
8191,

+ * and must not be less than 2 times of the value of M.
+ */
+    for (curr_m = 511; curr_m >= 1; curr_m--) {
+    curr_n = parent_rate * curr_m;
+    curr_delta = do_div(curr_n, rate);
+
+    if (curr_n < 2 * curr_m || curr_n > 8191)
+    continue;
+
+    if (curr_delta == 0)
+    break;
+
+    if (curr_delta < delta) {
+    m = curr_m;
+    n = curr_n;
+    delta = curr_delta;
+    }
+    }
+
+out:
+    if (pm)
+    *pm = m;
+    if (pn)
+    *pn = n;
+
+    return div_u64((u64)parent_rate * m, n);
+}
+
+static long x1000_i2s_round_rate(struct clk_hw *hw, unsigned long 
req_rate,

+    unsigned long *prate)
+{
+    return x1000_i2s_calc(req_rate, *prate, NULL, NULL);
+}
+
+static int x1000_i2s_set_rate(struct clk_hw *hw, unsigned long 
req_rate,

+    unsigned long parent_rate)
+{
+    unsigned long rate, flags;
+    unsigned m, n;
+    u32 ctl;
+
+    /*
+ * The parent clock rate of I2S must not be lower than 2 times
+ * of the target clock rate.
+ */
+    if (parent_rate < 2 * req_rate)
+    return -EINVAL;
+
+    rate = x1000_i2s_calc(req_rate, parent_rate, &m, &n);
+    if (rate != req_rate)
+    pr_info("%s: request I2S rate %luHz, actual %luHz\n", __func__,
+    req_rate, rate);
+
+    spin_lock_irqsave(&cgu->lock, flags);
+
+    ctl = readl(cgu->base + CGU_REG_I2SCDR);
+    ctl &= ~I2SCDR_I2SDIV_M_MASK;
+    ctl |= m << I2SCDR_I2SDIV_M_SHIFT;
+    ctl &= ~I2SCDR_I2SDIV_N_MASK;
+    ctl |= n << I2SCDR_I2SDIV_N_SHIFT;

Re: [PATCH v4 5/5] clk: Ingenic: Clean up and reformat the code.

[Zhou Yanjie]

Hi Paul,

On 2020/12/23 下午8:39, Paul Cercueil wrote:

Hi Zhou,

Le lun. 21 déc. 2020 à 23:52, 周琰杰 (Zhou Yanjie) 
 a écrit :

1.When the clock does not have "CGU_CLK_MUX", the 2/3/4 bits in
  parents do not need to be filled with -1. When the clock have
  a "CGU_CLK_MUX" has only one bit, the 3/4 bits of parents do
  not need to be filled with -1. Clean up these unnecessary -1
  from all the -cgu.c files.
2.Reformat code, add missing blank lines, remove unnecessary
  commas and tabs, and align code.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v1->v2:
    Remove unnecessary -1 and commas.

    v2->v3:
    No change.

    v3->v4:
    1.The -1 used for placeholders on the unused bits of the
  parents in the custom clock should not be removed.
    2.Move "JZ4780_CLK_CORE1" from the "Gate-only clocks"
  class to the "Custom (SoC-specific)" class, because
  it belongs to the custom clock.

 drivers/clk/ingenic/jz4725b-cgu.c |  50 +++---
 drivers/clk/ingenic/jz4740-cgu.c  |  50 +++---
 drivers/clk/ingenic/jz4770-cgu.c  |  79 +++---
 drivers/clk/ingenic/jz4780-cgu.c  | 135 
+++---
 drivers/clk/ingenic/x1000-cgu.c   | 120 
-
 drivers/clk/ingenic/x1830-cgu.c   | 133 
++---

 6 files changed, 286 insertions(+), 281 deletions(-)

diff --git a/drivers/clk/ingenic/jz4725b-cgu.c 
b/drivers/clk/ingenic/jz4725b-cgu.c

index 8c38e72..f41cd76 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -17,7 +17,7 @@

 /* CGU register offsets */
 #define CGU_REG_CPCCR    0x00
-#define CGU_REG_LCR    0x04
+#define CGU_REG_LCR    0x04
 #define CGU_REG_CPPCR    0x10
 #define CGU_REG_CLKGR    0x20
 #define CGU_REG_OPCR    0x24
@@ -28,7 +28,7 @@
 #define CGU_REG_CIMCDR    0x78

 /* bits within the LCR register */
-#define LCR_SLEEP    BIT(0)
+#define LCR_SLEEP    BIT(0)

 static struct ingenic_cgu *cgu;

@@ -53,7 +53,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_PLL] = {
 "pll", CGU_CLK_PLL,
-    .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_EXT },
 .pll = {
 .reg = CGU_REG_CPPCR,
 .rate_multiplier = 1,
@@ -78,7 +78,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_PLL_HALF] = {
 "pll half", CGU_CLK_DIV,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
 jz4725b_cgu_pll_half_div_table,
@@ -87,7 +87,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_CCLK] = {
 "cclk", CGU_CLK_DIV,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
 jz4725b_cgu_cpccr_div_table,
@@ -96,7 +96,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_HCLK] = {
 "hclk", CGU_CLK_DIV,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
 jz4725b_cgu_cpccr_div_table,
@@ -105,7 +105,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_PCLK] = {
 "pclk", CGU_CLK_DIV,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
 jz4725b_cgu_cpccr_div_table,
@@ -114,7 +114,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_MCLK] = {
 "mclk", CGU_CLK_DIV,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
 jz4725b_cgu_cpccr_div_table,
@@ -123,7 +123,7 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_IPU] = {
 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
-    .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL },
 .div = {
 CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
 jz4725b_cgu_cpccr_div_table,
@@ -133,14 +133,14 @@ static const struct ingenic_cgu_clk_info 
jz4725b_cgu_clocks[] = {


 [JZ4725B_CLK_LCD] = {
 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
-    .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+    .parents = { JZ4725B_CLK_PLL_HALF },
 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
 .gate = { CGU_REG_CLKGR, 9 },
 },

 

Re: [PATCH] phy: ingenic: Remove useless field .version

[Zhou Yanjie]

Hi Paul,

On 2020/12/23 下午8:45, Paul Cercueil wrote:

Remove the useless field .version from the private structure, which is
set but never read.

Signed-off-by: Paul Cercueil 
---
  drivers/phy/ingenic/phy-ingenic-usb.c | 23 ---
  1 file changed, 23 deletions(-)



Reviewed-by: 周琰杰 (Zhou Yanjie) 


Thanks and best regards!




diff --git a/drivers/phy/ingenic/phy-ingenic-usb.c 
b/drivers/phy/ingenic/phy-ingenic-usb.c
index 4d1587d82286..ea127b177f46 100644
--- a/drivers/phy/ingenic/phy-ingenic-usb.c
+++ b/drivers/phy/ingenic/phy-ingenic-usb.c
@@ -82,18 +82,7 @@
  #define USBPCR1_PORT_RST  BIT(21)
  #define USBPCR1_WORD_IF_16BIT BIT(19)
  
-enum ingenic_usb_phy_version {

-   ID_JZ4770,
-   ID_JZ4775,
-   ID_JZ4780,
-   ID_X1000,
-   ID_X1830,
-   ID_X2000,
-};
-
  struct ingenic_soc_info {
-   enum ingenic_usb_phy_version version;
-
void (*usb_phy_init)(struct phy *phy);
  };
  
@@ -300,38 +289,26 @@ static void x2000_usb_phy_init(struct phy *phy)

  }
  
  static const struct ingenic_soc_info jz4770_soc_info = {

-   .version = ID_JZ4770,
-
.usb_phy_init = jz4770_usb_phy_init,
  };
  
  static const struct ingenic_soc_info jz4775_soc_info = {

-   .version = ID_JZ4775,
-
.usb_phy_init = jz4775_usb_phy_init,
  };
  
  static const struct ingenic_soc_info jz4780_soc_info = {

-   .version = ID_JZ4780,
-
.usb_phy_init = jz4780_usb_phy_init,
  };
  
  static const struct ingenic_soc_info x1000_soc_info = {

-   .version = ID_X1000,
-
.usb_phy_init = x1000_usb_phy_init,
  };
  
  static const struct ingenic_soc_info x1830_soc_info = {

-   .version = ID_X1830,
-
.usb_phy_init = x1830_usb_phy_init,
  };
  
  static const struct ingenic_soc_info x2000_soc_info = {

-   .version = ID_X2000,
-
.usb_phy_init = x2000_usb_phy_init,
  };
  

Re: [PATCH phy] PHY: Ingenic: fix unconditional build of phy-ingenic-usb

[Zhou Yanjie]

Hi Alexander,

On 2020/12/22 下午9:10, Alexander Lobakin wrote:

Currently drivers/phy/ingenic/Makefile adds phy-ingenic-usb to targets
not depending on actual Kconfig symbol CONFIG_PHY_INGENIC_USB, so this
driver always gets built[-in] on every system.
Add missing dependency.

Fixes: 31de313dfdcf ("PHY: Ingenic: Add USB PHY driver using generic PHY 
framework.")
Signed-off-by: Alexander Lobakin 
---
  drivers/phy/ingenic/Makefile | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)



Apologize for my carelessness, and

Tested-by: 周琰杰 (Zhou Yanjie) 


Thanks and best regards!



diff --git a/drivers/phy/ingenic/Makefile b/drivers/phy/ingenic/Makefile
index 65d5ea00fc9d..1cb158d7233f 100644
--- a/drivers/phy/ingenic/Makefile
+++ b/drivers/phy/ingenic/Makefile
@@ -1,2 +1,2 @@
  # SPDX-License-Identifier: GPL-2.0
-obj-y  += phy-ingenic-usb.o
+obj-$(CONFIG_PHY_INGENIC_USB)  += phy-ingenic-usb.o

Re: [PATCH v3 05/10] dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.

[Zhou Yanjie]

On 2021/3/23 上午2:01, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v2:
    New patch.

    v2->v3:
    No change.

 .../bindings/pinctrl/ingenic,pinctrl.yaml  | 23 
++

 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml 
b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml

index 44c04d1..60604fc 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -17,10 +17,12 @@ description: >
   naming scheme "PxN" where x is a character identifying the GPIO 
port with
   which the pin is associated and N is an integer from 0 to 31 
identifying the
   pin within that GPIO port. For example PA0 is the first pin in 
GPIO port A,
-  and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and 
the X1830
-  contains 4 GPIO ports, PA to PD, for a total of 128 pins. The 
JZ4760, the
-  JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total 
of 192

-  pins.
+  and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, 
the X1000
+  and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128 
pins. The
+  X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins. 
The JZ4750,
+  the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO 
ports, PA
+  to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports, 
PA to PG,

+  for a total of 224 pins.


While we're at it, the JZ4725B has also 4 GPIO ports.



OK, I will add it.




 maintainers:
   - Paul Cercueil 
@@ -32,20 +34,28 @@ properties:
   compatible:
 oneOf:
   - enum:
+  - ingenic,jz4730-pinctrl
   - ingenic,jz4740-pinctrl
   - ingenic,jz4725b-pinctrl
+  - ingenic,jz4750-pinctrl
+  - ingenic,jz4755-pinctrl
   - ingenic,jz4760-pinctrl
   - ingenic,jz4770-pinctrl
+  - ingenic,jz4775-pinctrl
   - ingenic,jz4780-pinctrl
   - ingenic,x1000-pinctrl
   - ingenic,x1500-pinctrl
   - ingenic,x1830-pinctrl
+  - ingenic,x2000-pinctrl
   - items:
   - const: ingenic,jz4760b-pinctrl
   - const: ingenic,jz4760-pinctrl
   - items:
   - const: ingenic,x1000e-pinctrl
   - const: ingenic,x1000-pinctrl
+  - items:
+  - const: ingenic,x2000e-pinctrl
+  - const: ingenic,x2000-pinctrl

   reg:
 maxItems: 1
@@ -62,14 +72,19 @@ patternProperties:
 properties:
   compatible:
 enum:
+  - ingenic,jz4730-gpio
   - ingenic,jz4740-gpio
   - ingenic,jz4725b-gpio
+  - ingenic,jz4750-gpio
+  - ingenic,jz4755-gpio
   - ingenic,jz4760-gpio
   - ingenic,jz4770-gpio
+  - ingenic,jz4775-gpio
   - ingenic,jz4780-gpio
   - ingenic,x1000-gpio
   - ingenic,x1500-gpio
   - ingenic,x1830-gpio
+  - ingenic,x2000-gpio

   reg:
 items:
--
2.7.4

Re: [PATCH v3 06/10] pinctrl: Ingenic: Add pinctrl driver for JZ4730.

[Zhou Yanjie]

On 2021/3/23 上午2:17, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4730 SoC from Ingenic.

This driver is derived from Paul Boddie. It is worth to
noting that the JZ4730 SoC is special in having two control
registers (upper/lower), so add code to handle the JZ4730
specific register offsets and some register pairs which have
2 bits for each GPIO pin.

Tested-by: H. Nikolaus Schaller   # on Letux400
Co-developed-by: Paul Boddie 
Signed-off-by: Paul Boddie 
Signed-off-by: H. Nikolaus Schaller 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 222 
+++---

 1 file changed, 206 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index b8165f5..25458d6 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -3,8 +3,8 @@
  * Ingenic SoCs pinctrl driver
  *
  * Copyright (c) 2017 Paul Cercueil 
- * Copyright (c) 2019 周琰杰 (Zhou Yanjie) 
  * Copyright (c) 2017, 2019 Paul Boddie 
+ * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) 


  */

 #include 
@@ -29,6 +29,17 @@
 #define GPIO_PIN    0x00
 #define GPIO_MSK    0x20

+#define JZ4730_GPIO_DATA    0x00
+#define JZ4730_GPIO_GPDIR    0x04
+#define JZ4730_GPIO_GPPUR    0x0c
+#define JZ4730_GPIO_GPALR    0x10
+#define JZ4730_GPIO_GPAUR    0x14
+#define JZ4730_GPIO_GPIDLR    0x18
+#define JZ4730_GPIO_GPIDUR    0x1c
+#define JZ4730_GPIO_GPIER    0x20
+#define JZ4730_GPIO_GPIMR    0x24
+#define JZ4730_GPIO_GPFR    0x28
+
 #define JZ4740_GPIO_DATA    0x10
 #define JZ4740_GPIO_PULL_DIS    0x30
 #define JZ4740_GPIO_FUNC    0x40
@@ -57,6 +68,7 @@
 #define GPIO_PULL_DOWN    2

 #define PINS_PER_GPIO_CHIP    32
+#define JZ4730_PINS_PER_PAIRED_REG    16

 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)    \
 {    \
@@ -70,6 +82,7 @@
 INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))

 enum jz_version {
+    ID_JZ4730,
 ID_JZ4740,
 ID_JZ4725B,
 ID_JZ4760,
@@ -110,6 +123,96 @@ struct ingenic_gpio_chip {
 unsigned int irq, reg_base;
 };

+static const u32 jz4730_pull_ups[4] = {
+    0x3fa3320f, 0xf200, 0x, 0x,
+};
+
+static const u32 jz4730_pull_downs[4] = {
+    0x0df0, 0x0dff, 0x, 0x,
+};
+
+static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
+static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
+static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
+static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
+static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
+static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
+static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
+static int jz4730_lcd_8bit_pins[] = {
+    0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x3a, 0x39, 0x38,
+};
+static int jz4730_lcd_16bit_pins[] = {
+    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x3b,
+};
+static int jz4730_lcd_16bit_tft_pins[] = { 0x3e, 0x3f, 0x3d, 0x3c, };
+static int jz4730_nand_cs1_pins[] = { 0x53, };
+static int jz4730_nand_cs2_pins[] = { 0x54, };
+static int jz4730_nand_cs3_pins[] = { 0x55, };
+static int jz4730_nand_cs4_pins[] = { 0x56, };
+static int jz4730_nand_cs5_pins[] = { 0x57, };
+static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
+static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
+
+static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 
2, };

+
+static const struct group_desc jz4730_groups[] = {
+    INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
+    INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
+    INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
+    INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
+    INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
+    INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
+    INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
+    INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, 
jz4730_lcd_8bit_funcs),

+    INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
+    INGENIC_PIN_GROUP("lcd-16bit-tft", jz4730_lcd_16bit_tft, 1),
+    INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
+    INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
+    INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
+    INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
+    INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
+    INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
+    INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
+};
+
+static const char *jz4730_mmc_groups[] = { "mmc-1bit", 

Re: [PATCH v3 07/10] pinctrl: Ingenic: Add pinctrl driver for JZ4750.

[Zhou Yanjie]

On 2021/3/23 上午2:20, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 137 
++

 1 file changed, 137 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index 25458d6..d98767b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -85,6 +85,7 @@ enum jz_version {
 ID_JZ4730,
 ID_JZ4740,
 ID_JZ4725B,
+    ID_JZ4750,
 ID_JZ4760,
 ID_JZ4770,
 ID_JZ4780,
@@ -424,6 +425,138 @@ static const struct ingenic_chip_info 
jz4725b_chip_info = {

 .pull_downs = jz4740_pull_downs,
 };

+static const u32 jz4750_pull_ups[6] = {
+    0x, 0x, 0x3fff, 0x7fff, 0x1fff3fff, 
0x00ff,

+};
+
+static const u32 jz4750_pull_downs[6] = {
+    0x, 0x, 0x, 0x, 0x, 
0x,

+};
+
+static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
+static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
+static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
+static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
+static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
+static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
+static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
+static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
+static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
+static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
+static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
+static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
+static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4750_cim_pins[] = {
+    0x89, 0x8b, 0x8a, 0x88,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4750_lcd_8bit_pins[] = {
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x72, 0x73, 0x74,
+};
+static int jz4750_lcd_16bit_pins[] = {
+    0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x75,
+};
+static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4750_lcd_18bit_tft_pins[] = { 0x78, 0x79, 0x76, 0x77, };
+static int jz4750_nand_cs1_pins[] = { 0x55, };
+static int jz4750_nand_cs2_pins[] = { 0x56, };
+static int jz4750_nand_cs3_pins[] = { 0x57, };
+static int jz4750_nand_cs4_pins[] = { 0x58, };
+static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4750_pwm_pwm0_pins[] = { 0x94, };
+static int jz4750_pwm_pwm1_pins[] = { 0x95, };
+static int jz4750_pwm_pwm2_pins[] = { 0x96, };
+static int jz4750_pwm_pwm3_pins[] = { 0x97, };
+static int jz4750_pwm_pwm4_pins[] = { 0x98, };
+static int jz4750_pwm_pwm5_pins[] = { 0x99, };
+
+static const struct group_desc jz4750_groups[] = {
+    INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
+    INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
+    INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
+    INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
+    INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
+    INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
+    INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
+    INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
+    INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
+    INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
+    INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
+    INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
+    INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
+    INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
+    INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+    INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+    INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
+    INGENIC_PIN_GROUP("lcd-18bit-tft", jz4750_lcd_18bit_tft, 0),
+    { "lcd-no-pins", },


Please drop "lcd-no-pins" from your patches, it is pointless.



Sure.



Cheers,
-Paul


+    INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
+    INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
+    INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
+    INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
+    INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
+    INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
+    INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
+    INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
+    INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
+    INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
+    INGENIC_PIN_GROUP("pwm5", jz4750_p

Re: [PATCH v3 01/10] pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.

[Zhou Yanjie]

Hi Paul,

On 2021/3/23 上午1:53, Paul Cercueil wrote:

Hi Zhou,


Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie) 
 a écrit :

The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.

Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 
and JZ4780.")


This fixes a commit that was introduced in an older kernel (than the 
one in -rc phase). Therefore you need to Cc linux-stable. Like this:


Cc:  # v5.0



Sure, I will add it in the next version.



Signed-off-by: 周琰杰 (Zhou Yanjie) 


With that said:

Reviewed-by: Paul Cercueil 

Cheers,
-Paul


---

Notes:
    v2:
    New patch.

    v2->v3:
    Add fixes tag.

 drivers/pinctrl/pinctrl-ingenic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index f274612..05dfa0a 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -667,7 +667,9 @@ static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
 static int jz4770_mac_rmii_pins[] = {
 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
 };
-static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
+static int jz4770_mac_mii_pins[] = {
+    0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
+};

 static const struct group_desc jz4770_groups[] = {
 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
--
2.7.4

Re: [PATCH v3 02/10] pinctrl: Ingenic: Add support for read the pin configuration of X1830.

[Zhou Yanjie]

Hi,

On 2021/3/23 上午1:58, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:57, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.

Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v2:
    New patch.

    v2->v3:
    1.Add fixes tag.
    2.Adjust the code, simplify the ingenic_pinconf_get() function.

 drivers/pinctrl/pinctrl-ingenic.c | 38 
++

 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index 05dfa0a..1d43b98 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -2109,26 +2109,48 @@ static int ingenic_pinconf_get(struct 
pinctrl_dev *pctldev,

 enum pin_config_param param = pinconf_to_config_param(*config);
 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
-    bool pull;
+    unsigned int bias;
+    bool pull, pullup, pulldown;

-    if (jzpc->info->version >= ID_JZ4770)
-    pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
-    else
-    pull = !ingenic_get_pin_config(jzpc, pin, 
JZ4740_GPIO_PULL_DIS);

+    if (jzpc->info->version >= ID_X1830) {
+    unsigned int half = PINS_PER_GPIO_CHIP / 2;
+    unsigned int idxh = pin % half * 2;


I had to look up operator precedence in C, '*' and '%' have the same 
priority so this reads left-to-right.


I'd suggest adding parentheses around the '%' to make it more obvious.



Sure.



With that:

Reviewed-by: Paul Cercueil 

Cheers,
-Paul


+
+    if (idx < half)
+    regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
+    X1830_GPIO_PEL, &bias);
+    else
+    regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
+    X1830_GPIO_PEH, &bias);
+
+    bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
+
+    pullup = (bias == GPIO_PULL_UP) && 
(jzpc->info->pull_ups[offt] & BIT(idx));
+    pulldown = (bias == GPIO_PULL_DOWN) && 
(jzpc->info->pull_downs[offt] & BIT(idx));

+
+    } else {
+    if (jzpc->info->version >= ID_JZ4770)
+    pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
+    else
+    pull = !ingenic_get_pin_config(jzpc, pin, 
JZ4740_GPIO_PULL_DIS);

+
+    pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
+    pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
+    }

 switch (param) {
 case PIN_CONFIG_BIAS_DISABLE:
-    if (pull)
+    if (pullup || pulldown)
 return -EINVAL;
 break;

 case PIN_CONFIG_BIAS_PULL_UP:
-    if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
+    if (!pullup)
 return -EINVAL;
 break;

 case PIN_CONFIG_BIAS_PULL_DOWN:
-    if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
+    if (!pulldown)
 return -EINVAL;
 break;

--
2.7.4

Re: [PATCH v3 08/10] pinctrl: Ingenic: Add pinctrl driver for JZ4755.

[Zhou Yanjie]

Hi,

On 2021/3/23 上午2:24, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 132 
++

 1 file changed, 132 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index d98767b..d8b37fa 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -86,6 +86,7 @@ enum jz_version {
 ID_JZ4740,
 ID_JZ4725B,
 ID_JZ4750,
+    ID_JZ4755,
 ID_JZ4760,
 ID_JZ4770,
 ID_JZ4780,
@@ -557,6 +558,131 @@ static const struct ingenic_chip_info 
jz4750_chip_info = {

 .pull_downs = jz4750_pull_downs,
 };

+static const u32 jz4755_pull_ups[6] = {
+    0x, 0x, 0x0fff, 0x, 0x33dc3fff, 
0xfc00,

+};
+
+static const u32 jz4755_pull_downs[6] = {
+    0x, 0x, 0x, 0x, 0x, 
0x,

+};
+
+static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
+static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
+static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
+static int jz4755_uart2_data_pins[] = { 0x9f, };
+static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
+static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
+static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
+static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
+static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4755_cim_pins[] = {
+    0x89, 0x8b, 0x8a, 0x88,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4755_lcd_24bit_pins[] = {
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+    0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+    0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+    0x78, 0x79, 0x7a, 0x7b,
+};
+static int jz4755_nand_cs1_pins[] = { 0x55, };
+static int jz4755_nand_cs2_pins[] = { 0x56, };
+static int jz4755_nand_cs3_pins[] = { 0x57, };
+static int jz4755_nand_cs4_pins[] = { 0x58, };
+static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4755_pwm_pwm0_pins[] = { 0x94, };
+static int jz4755_pwm_pwm1_pins[] = { 0xab, };
+static int jz4755_pwm_pwm2_pins[] = { 0x96, };
+static int jz4755_pwm_pwm3_pins[] = { 0x97, };
+static int jz4755_pwm_pwm4_pins[] = { 0x98, };
+static int jz4755_pwm_pwm5_pins[] = { 0x99, };
+
+static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
+static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
+static u8 jz4755_lcd_24bit_funcs[] = {
+    0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 1, 1,
+    1, 1, 0, 0,
+};
+
+static const struct group_desc jz4755_groups[] = {
+    INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
+    INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
+    INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
+    INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
+    INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
+    jz4755_mmc0_1bit_funcs),
+    INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
+    jz4755_mmc0_4bit_funcs),
+    INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
+    INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
+    INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
+    INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
+    INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
+    jz4755_lcd_24bit_funcs),


Coud you either split this into several groups (lcd-8bit, lcd-16bit, 
lcd-18bit, lcd-24bit, lcd-special, lcd-generic) like it is done for 
the JZ4725B? Same for the other SoCs.




Sure, and do we need to change the JZ4740 (and the previous JZ4750) to 
the lcd-special + lcd-generic model? It looks more reasonable than the 
original lcd-tft and makes the style more uniform.




Alternatively just remove the "lcd" function for now.


+    { "lcd-no-pins", },


And remove this.

Cheers,
-Paul


+    INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
+    INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
+    INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
+    INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
+    INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
+    INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
+    INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
+    INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
+    INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
+    INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
+    INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
+};
+
+static const char *jz4755_uart0_groups[] = { "uart0-da

Re: [PATCH v3 09/10] pinctrl: Ingenic: Add pinctrl driver for JZ4775.

[Zhou Yanjie]

On 2021/3/23 上午2:25, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 259 
++

 1 file changed, 259 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index d8b37fa..eb4912d 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -89,6 +89,7 @@ enum jz_version {
 ID_JZ4755,
 ID_JZ4760,
 ID_JZ4770,
+    ID_JZ4775,
 ID_JZ4780,
 ID_X1000,
 ID_X1500,
@@ -1237,6 +1238,259 @@ static const struct ingenic_chip_info 
jz4770_chip_info = {

 .pull_downs = jz4770_pull_downs,
 };

+static const u32 jz4775_pull_ups[7] = {
+    0x28ff00ff, 0xf030f3fc, 0x0fff, 0xfffe4000, 0xf0fc, 
0xf00f, 0xf3c0,

+};
+
+static const u32 jz4775_pull_downs[7] = {
+    0x, 0x00030c03, 0x, 0x8000, 0x0403, 
0x0ff0, 0x00030c00,

+};
+
+static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
+static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
+static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
+static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
+static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
+static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
+static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
+static int jz4775_ssi_dt_a_pins[] = { 0x13, };
+static int jz4775_ssi_dt_d_pins[] = { 0x75, };
+static int jz4775_ssi_dr_a_pins[] = { 0x14, };
+static int jz4775_ssi_dr_d_pins[] = { 0x74, };
+static int jz4775_ssi_clk_a_pins[] = { 0x12, };
+static int jz4775_ssi_clk_d_pins[] = { 0x78, };
+static int jz4775_ssi_gpc_pins[] = { 0x76, };
+static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
+static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
+static int jz4775_ssi_ce1_pins[] = { 0x77, };
+static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
+static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
+static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
+static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
+static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_nemc_8bit_data_pins[] = {
+    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+};
+static int jz4775_nemc_16bit_data_pins[] = {
+    0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
+};
+static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
+static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
+static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
+static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4775_nemc_wait_pins[] = { 0x1b, };
+static int jz4775_nemc_cs1_pins[] = { 0x15, };
+static int jz4775_nemc_cs2_pins[] = { 0x16, };
+static int jz4775_nemc_cs3_pins[] = { 0x17, };
+static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
+static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
+static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
+static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
+static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
+static int jz4775_i2s_sysclk_pins[] = { 0x83, };
+static int jz4775_cim_pins[] = {
+    0x26, 0x27, 0x28, 0x29,
+    0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4775_lcd_24bit_pins[] = {
+    0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+    0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
+    0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
+    0x58, 0x59, 0x5a, 0x5b,
+};
+static int jz4775_pwm_pwm0_pins[] = { 0x80, };
+static int jz4775_pwm_pwm1_pins[] = { 0x81, };
+static int jz4775_pwm_pwm2_pins[] = { 0x82, };
+static int jz4775_pwm_pwm3_pins[] = { 0x83, };
+static int jz4775_mac_rmii_pins[] = {
+    0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4775_mac_mii_pins[] = {
+    0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
+};
+static int jz4775_mac_rgmii_pins[] = {
+    0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
+    0xad, 0xae, 0xa7, 0xa6,
+};
+static int jz4775_mac_gmii_pins[] = {
+    0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
+    0xa8, 0x28, 0x24, 0xaf,
+};
+static int jz4775_otg_pins[] = { 0x8a, };
+
+static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
+static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0

Fix bug for Ingenic X1000.

[Zhou Yanjie]

For SoCs after X1000, only send "X1000_I2C_DC_STOP" when last byte,
or it will cause error when I2C write operation.

周琰杰 (Zhou Yanjie) (1):
  I2C: JZ4780: Fix bug for Ingenic X1000.

 drivers/i2c/busses/i2c-jz4780.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

-- 
2.7.4

[PATCH] I2C: JZ4780: Fix bug for Ingenic X1000.

[Zhou Yanjie]

Only send "X1000_I2C_DC_STOP" when last byte, or it will cause
error when I2C write operation.

Fixes: 21575a7a8d4c ("I2C: JZ4780: Add support for the X1000.")

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---
 drivers/i2c/busses/i2c-jz4780.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c
index 8509c5f..1ad093a 100644
--- a/drivers/i2c/busses/i2c-jz4780.c
+++ b/drivers/i2c/busses/i2c-jz4780.c
@@ -520,13 +520,12 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
 
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
 
-   while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
-   (i2c->wt_len > 0)) {
+   while ((i2c_sta & JZ4780_I2C_STA_TFNF) && (i2c->wt_len 
> 0)) {
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
data = *i2c->wbuf;
data &= ~JZ4780_I2C_DC_READ;
-   if ((!i2c->stop_hold) && (i2c->cdata->version >=
-   ID_X1000))
+   if ((i2c->wt_len == 1) && (!i2c->stop_hold) &&
+   (i2c->cdata->version >= 
ID_X1000))
data |= X1000_I2C_DC_STOP;
jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data);
i2c->wbuf++;
-- 
2.7.4

Re: [PATCH] I2C: JZ4780: Fix bug for Ingenic X1000.

[Zhou Yanjie]

Hi Wolfram,


Sorry, please forgive my carefulness, I wrongly sent the version that 
did not clean up, resulting in missing the reporter's information and 
some errors in formats.



On 2021/3/19 上午1:06, Wolfram Sang wrote:

On Fri, Mar 19, 2021 at 12:25:43AM +0800, 周琰杰 (Zhou Yanjie) wrote:

Only send "X1000_I2C_DC_STOP" when last byte, or it will cause
error when I2C write operation.

Any write operation? I wonder then why nobody noticed before?



The standard I2C communication should look like this:

Read:

device_addr + w, reg_addr, device_addr + r, data;

Write:

device_addr + w, reg_addr, data;


But without this patch, it looks like this:

Read:

device_addr + w, reg_addr, device_addr + r, data;

Write:

device_addr + w, reg_addr, device_addr + w, data;

This is clearly not correct.


When I added support for X1000 to this driver, the hardware used was 
CU1000-Neo. On this hardware, there was an ADS7830 that communicated 
through I2C, but the operation of ADS7830 only involved read operations, 
so I was at that time failed to realize the problem with the write 
operation.
In addition, because X1000 did not implement relatively complete support 
in the mainline until the second half of 2020, there are still a large 
number of users who are still using the old SDK (kernel 3.10 and 
kernel4.4) provided by Ingenics, which may also be indirectly delayed 
exposure of this problem.




-   while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
-   (i2c->wt_len > 0)) {
+   while ((i2c_sta & JZ4780_I2C_STA_TFNF) && (i2c->wt_len 
> 0)) {

This is a cosmetic change only IIUC. Shouldn't be in a bugfix.



My fault, I will remove it in the next version.


Thanks and best regards!

[PATCH v2] I2C: JZ4780: Fix bug for Ingenic X1000.

[Zhou Yanjie]

Only send "X1000_I2C_DC_STOP" when last byte, or it will cause
error when I2C write operation.

Fixes: 21575a7a8d4c ("I2C: JZ4780: Add support for the X1000.")

Reported-by: 杨文龙 (Yang Wenlong) 
Tested-by: 杨文龙 (Yang Wenlong) 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v1->v2:
1.Add missing Reported-by and Tested-by.
2.Remove change which not related to the bugfix.

 drivers/i2c/busses/i2c-jz4780.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-jz4780.c b/drivers/i2c/busses/i2c-jz4780.c
index 8509c5f..55177eb 100644
--- a/drivers/i2c/busses/i2c-jz4780.c
+++ b/drivers/i2c/busses/i2c-jz4780.c
@@ -525,8 +525,8 @@ static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
data = *i2c->wbuf;
data &= ~JZ4780_I2C_DC_READ;
-   if ((!i2c->stop_hold) && (i2c->cdata->version >=
-   ID_X1000))
+   if ((i2c->wt_len == 1) && (!i2c->stop_hold) &&
+   (i2c->cdata->version >= 
ID_X1000))
data |= X1000_I2C_DC_STOP;
jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data);
i2c->wbuf++;
-- 
2.7.4

Fix bug for Ingenic X1000 v2.

[Zhou Yanjie]

For SoCs after X1000, only send "X1000_I2C_DC_STOP" when last byte,
or it will cause error when I2C write operation.

v1->v2:
1.Add missing Reported-by and Tested-by.
2.Remove change which not related to the bugfix.

周琰杰 (Zhou Yanjie) (1):
  I2C: JZ4780: Fix bug for Ingenic X1000.

 drivers/i2c/busses/i2c-jz4780.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH] USB: DWC2: Add VBUS overcurrent detection control.

[Zhou Yanjie]

Introduce configurable option for enabling GOTGCTL register
bits VbvalidOvEn and VbvalidOvVal. Once selected it disables
VBUS overcurrent detection.

This patch is derived from Dragan Čečavac (in the kernel 3.18
tree of CI20). It is very useful for the MIPS Creator CI20(r1).
Without this patch, CI20's OTG port has a great probability to
face overcurrent warning, which breaks the OTG functionality.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Signed-off-by: Dragan Čečavac 
---
 drivers/usb/dwc2/Kconfig | 6 ++
 drivers/usb/dwc2/core.c  | 9 +
 2 files changed, 15 insertions(+)

diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig
index c131719..e40d187 100644
--- a/drivers/usb/dwc2/Kconfig
+++ b/drivers/usb/dwc2/Kconfig
@@ -94,4 +94,10 @@ config USB_DWC2_DEBUG_PERIODIC
  non-periodic transfers, but of course the debug logs will be
  incomplete. Note that this also disables some debug messages
  for which the transfer type cannot be deduced.
+
+config USB_DWC2_DISABLE_VOD
+   bool "Disable VBUS overcurrent detection"
+   help
+ Say Y here to switch off VBUS overcurrent detection. It enables USB
+ functionality blocked by overcurrent detection.
 endif
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index fec17a2..c629dc97 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -1200,6 +1200,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, 
bool select_phy)
 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 {
u32 usbcfg;
+   u32 otgctl;
int retval = 0;
 
if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
@@ -1231,6 +1232,14 @@ int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool 
select_phy)
dwc2_writel(hsotg, usbcfg, GUSBCFG);
}
 
+   if (IS_ENABLED(CONFIG_USB_DWC2_DISABLE_VOD)) {
+   if (dwc2_is_host_mode(hsotg)) {
+   otgctl = readl(hsotg->regs + GOTGCTL);
+   otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
+   writel(otgctl, hsotg->regs + GOTGCTL);
+   }
+   }
+
return retval;
 }
 
-- 
2.7.4

Re: [PATCH 6/6] clk: ingenic: Add support for the JZ4760

[Zhou Yanjie]

Hi Paul,

On 2021/3/23 上午1:40, Paul Cercueil wrote:

Hi Zhou,

Le mer. 17 mars 2021 à 20:41, Zhou Yanjie  
a écrit :

Hi Paul,

On 2021/3/7 下午10:17, Paul Cercueil wrote:

Add the CGU code and the compatible string to the TCU driver to support
the JZ4760 SoC.

Signed-off-by: Paul Cercueil 
---
  drivers/clk/ingenic/Kconfig    |  10 +
  drivers/clk/ingenic/Makefile   |   1 +
  drivers/clk/ingenic/jz4760-cgu.c   | 433 
+

  drivers/clk/ingenic/tcu.c  |   2 +
  include/dt-bindings/clock/jz4760-cgu.h |  54 +++
  5 files changed, 500 insertions(+)
  create mode 100644 drivers/clk/ingenic/jz4760-cgu.c
  create mode 100644 include/dt-bindings/clock/jz4760-cgu.h

diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 580b0cf69ed5..898f1bc478c9 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -25,6 +25,16 @@ config INGENIC_CGU_JZ4725B
      If building for a JZ4725B SoC, you want to say Y here.
  +config INGENIC_CGU_JZ4760
+    bool "Ingenic JZ4760 CGU driver"
+    default MACH_JZ4760
+    select INGENIC_CGU_COMMON
+    help
+  Support the clocks provided by the CGU hardware on Ingenic 
JZ4760

+  and compatible SoCs.
+
+  If building for a JZ4760 SoC, you want to say Y here.
+
  config INGENIC_CGU_JZ4770
  bool "Ingenic JZ4770 CGU driver"
  default MACH_JZ4770
diff --git a/drivers/clk/ingenic/Makefile 
b/drivers/clk/ingenic/Makefile

index aaa4bffe03c6..9edfaf4610b9 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -2,6 +2,7 @@
  obj-$(CONFIG_INGENIC_CGU_COMMON)    += cgu.o pm.o
  obj-$(CONFIG_INGENIC_CGU_JZ4740)    += jz4740-cgu.o
  obj-$(CONFIG_INGENIC_CGU_JZ4725B)    += jz4725b-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4760)    += jz4760-cgu.o
  obj-$(CONFIG_INGENIC_CGU_JZ4770)    += jz4770-cgu.o
  obj-$(CONFIG_INGENIC_CGU_JZ4780)    += jz4780-cgu.o
  obj-$(CONFIG_INGENIC_CGU_X1000)    += x1000-cgu.o
diff --git a/drivers/clk/ingenic/jz4760-cgu.c 
b/drivers/clk/ingenic/jz4760-cgu.c

new file mode 100644
index ..a45327cba7d1
--- /dev/null
+++ b/drivers/clk/ingenic/jz4760-cgu.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ4760 SoC CGU driver
+ * Copyright 2018, Paul Cercueil 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+#include "cgu.h"
+#include "pm.h"
+
+#define MHZ (1000 * 1000)
+
+/*
+ * CPM registers offset address definition
+ */
+#define CGU_REG_CPCCR    0x00
+#define CGU_REG_LCR    0x04
+#define CGU_REG_CPPCR0    0x10
+#define CGU_REG_CLKGR0    0x20
+#define CGU_REG_OPCR    0x24
+#define CGU_REG_CLKGR1    0x28
+#define CGU_REG_CPPCR1    0x30
+#define CGU_REG_USBPCR    0x3c
+#define CGU_REG_USBCDR    0x50
+#define CGU_REG_I2SCDR    0x60
+#define CGU_REG_LPCDR    0x64
+#define CGU_REG_MSCCDR    0x68
+#define CGU_REG_UHCCDR    0x6c
+#define CGU_REG_SSICDR    0x74
+#define CGU_REG_CIMCDR    0x7c
+#define CGU_REG_GPSCDR    0x80
+#define CGU_REG_PCMCDR    0x84
+#define CGU_REG_GPUCDR    0x88
+
+static const s8 pll_od_encoding[8] = {
+    0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const u8 jz4760_cgu_cpccr_div_table[] = {
+    1, 2, 3, 4, 6, 8,
+};
+
+static const u8 jz4760_cgu_pll_half_div_table[] = {
+    2, 1,
+};
+
+static void
+jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
+   unsigned long rate, unsigned long parent_rate,
+   unsigned int *pm, unsigned int *pn, unsigned int *pod)
+{
+    unsigned int m, n, od;
+
+    /* The output of the PLL must be between 500 and 1500 MHz. */
+    rate = clamp_val(rate, 500ul * MHZ, 1500ul * MHZ);
+
+    /* The frequency after the N divider must be between 1 and 50 
MHz. */

+    n = parent_rate / (1 * MHZ);
+
+    /* The N divider must be >= 2. */
+    n = clamp_val(n, 2, 1 << pll_info->n_bits);
+
+    for (;;) {
+    od = 0;
+
+    do {
+    m = (rate / MHZ) * ++od * n / (parent_rate / MHZ);



Please correct me if I am wrong, according to the PM, when the 
register value of OD is 0, 1, 2, 3, the value corresponding 
participating PL frequency calculation is 1, 2, 4, 8. Therefore, change


m = (rate / MHZ) * ++od * n / (parent_rate / MHZ); to m = (rate / 
MHZ) * (2 ^ od++) * n / (parent_rate / MHZ); seems to be more 
appropriate, it can avoid 3, 5, 6, and 7 that should not exist.




I found a mistake. My brain must have been broken at that time. The 2 ^ 
od here I intended to express the meaning of od power of 2, but it 
should be written as 1 << od, otherwise it becomes a XOR operation.




You are totally correct. I will send a revised version.

Thanks!

Cheers,
-Paul


+    } while (m < pll_info->m_offset || m & 1);
+
+    if (m <= (1 << pll_info->m_bits) - 2)
+    break;
+
+    n >>= 1;

Re: exec error: BUG: Bad rss-counter

[Zhou Yanjie]

Hi Ilya,

On 2021/3/3 下午11:55, Ilya Lipnitskiy wrote:

On Wed, Mar 3, 2021 at 7:50 AM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


On Tue, Mar 2, 2021 at 11:37 AM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


On Mon, Mar 1, 2021 at 12:43 PM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


Eric, All,

The following error appears when running Linux 5.10.18 on an embedded
MIPS mt7621 target:
[0.301219] BUG: Bad rss-counter state mm:(ptrval) type:MM_ANONPAGES val:1

Being a very generic error, I started digging and added a stack dump
before the BUG:
Call Trace:
[<80008094>] show_stack+0x30/0x100
[<8033b238>] dump_stack+0xac/0xe8
[<800285e8>] __mmdrop+0x98/0x1d0
[<801a6de8>] free_bprm+0x44/0x118
[<801a86a8>] kernel_execve+0x160/0x1d8
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194
[<80003198>] ret_from_kernel_thread+0x14/0x1c

So that's how I got to looking at fs/exec.c and noticed quite a few
changes last year. Turns out this message only occurs once very early
at boot during the very first call to kernel_execve. current->mm is
NULL at this stage, so acct_arg_size() is effectively a no-op.

If you believe this is a new error you could bisect the kernel
to see which change introduced the behavior you are seeing.


More digging, and I traced the RSS counter increment to:
[<8015adb4>] add_mm_counter_fast+0xb4/0xc0
[<80160d58>] handle_mm_fault+0x6e4/0xea0
[<80158aa4>] __get_user_pages.part.78+0x190/0x37c
[<8015992c>] __get_user_pages_remote+0x128/0x360
[<801a6d9c>] get_arg_page+0x34/0xa0
[<801a7394>] copy_string_kernel+0x194/0x2a4
[<801a880c>] kernel_execve+0x11c/0x298
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194
[<80003198>] ret_from_kernel_thread+0x14/0x1c

In fact, I also checked vma_pages(bprm->vma) and lo and behold it is set to 1.

How is fs/exec.c supposed to handle implied RSS increments that happen
due to page faults when discarding the bprm structure? In this case,
the bug-generating kernel_execve call never succeeded, it returned -2,
but I didn't trace exactly what failed.

Unless I am mistaken any left over pages should be purged by exit_mmap
which is called by mmput before mmput calls mmdrop.

Good to know. Some more digging and I can say that we hit this error
when trying to unmap PFN 0 (is_zero_pfn(pfn) returns TRUE,
vm_normal_page returns NULL, zap_pte_range does not decrement
MM_ANONPAGES RSS counter). Is my understanding correct that PFN 0 is
usable, but special? Or am I totally off the mark here?

It would be good to know if that is the page that get_user_pages_remote
returned to copy_string_kernel.  The zero page that is always zero,
should never be returned when a writable mapping is desired.

Indeed, pfn 0 is returned from get_arg_page: (page is 0x809cf000,
page_to_pfn(page) is 0) and it is the same page that is being freed and not
refcounted in mmput/zap_pte_range. Confirmed with good old printk. Also,
ZERO_PAGE(0)==0x809fc000 -> PFN 5120.

I think I have found the problem though, after much digging and thanks to all
the information provided. init_zero_pfn() gets called too late (after
the call to
is_zero_pfn(0) from mmput returns true), until then zero_pfn == 0, and after,
zero_pfn == 5120. Boom.

So PFN 0 is special, but only for a little bit, enough for something
on my system
to call kernel_execve :)

Question: is my system not supposed to be calling kernel_execve this
early or does
init_zero_pfn() need to happen earlier? init_zero_pfn is currently a
core_initcall.

Looking quickly it seems that init_zero_pfn() is in mm/memory.c and is
common for both mips and x86.  Further it appears init_zero_pfn() has
been that was since 2009 a13ea5b75964 ("mm: reinstate ZERO_PAGE").

Given the testing that x86 gets and that nothing like this has been
reported it looks like whatever driver is triggering the kernel_execve
is doing something wrong.
Because honestly.  If the zero page isn't working there is not a chance
that anything in userspace is working so it is clearly much too early.

I suspect there is some driver that is initialized very early that is
doing something that looks innocuous (like triggering a hotplug event)
and that happens to cause a call_usermode_helper which then calls
kernel_execve.

I will investigate the offenders more closely. However, I do not
notice this behavior on the same system based on the 5.4 kernel. Is it



I also encountered this problem on Ingenic X1000 and X1830. This is the 
printed information:


[    0.120715] BUG: Bad rss-counter state mm:(ptrval) 
type:MM_ANONPAGES val:1


I tested kernel 5.9, kernel 5.10, kernel 5.11, and kernel 5.12, only 
kernel 5.9 did not have this problem, so we can know that this problem 
was introduced in kernel 5.10, have you found any effective solution?



Thanks and best regards!



possible that last year's exec changes have exposed this issue? Not
blaming exec at all, just making sure I understand the problem better.

Ilya

Re: [PATCH v3 08/10] pinctrl: Ingenic: Add pinctrl driver for JZ4755.

[Zhou Yanjie]

Hi Paul,

On 2021/3/28 上午2:30, Paul Cercueil wrote:

Hi Zhou,

Le jeu. 25 mars 2021 à 16:38, Zhou Yanjie  
a écrit :

Hi,

On 2021/3/23 上午2:24, Paul Cercueil wrote:



Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
    v3:
    New patch.

 drivers/pinctrl/pinctrl-ingenic.c | 132 
++

 1 file changed, 132 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

index d98767b..d8b37fa 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -86,6 +86,7 @@ enum jz_version {
 ID_JZ4740,
 ID_JZ4725B,
 ID_JZ4750,
+    ID_JZ4755,
 ID_JZ4760,
 ID_JZ4770,
 ID_JZ4780,
@@ -557,6 +558,131 @@ static const struct ingenic_chip_info 
jz4750_chip_info = {

 .pull_downs = jz4750_pull_downs,
 };

+static const u32 jz4755_pull_ups[6] = {
+    0x, 0x, 0x0fff, 0x, 0x33dc3fff, 
0xfc00,

+};
+
+static const u32 jz4755_pull_downs[6] = {
+    0x, 0x, 0x, 0x, 0x, 
0x,

+};
+
+static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
+static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
+static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
+static int jz4755_uart2_data_pins[] = { 0x9f, };
+static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
+static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
+static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
+static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
+static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4755_cim_pins[] = {
+    0x89, 0x8b, 0x8a, 0x88,
+    0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4755_lcd_24bit_pins[] = {
+    0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+    0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+    0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+    0x78, 0x79, 0x7a, 0x7b,
+};
+static int jz4755_nand_cs1_pins[] = { 0x55, };
+static int jz4755_nand_cs2_pins[] = { 0x56, };
+static int jz4755_nand_cs3_pins[] = { 0x57, };
+static int jz4755_nand_cs4_pins[] = { 0x58, };
+static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4755_pwm_pwm0_pins[] = { 0x94, };
+static int jz4755_pwm_pwm1_pins[] = { 0xab, };
+static int jz4755_pwm_pwm2_pins[] = { 0x96, };
+static int jz4755_pwm_pwm3_pins[] = { 0x97, };
+static int jz4755_pwm_pwm4_pins[] = { 0x98, };
+static int jz4755_pwm_pwm5_pins[] = { 0x99, };
+
+static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
+static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
+static u8 jz4755_lcd_24bit_funcs[] = {
+    0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 1, 1,
+    1, 1, 0, 0,
+};
+
+static const struct group_desc jz4755_groups[] = {
+    INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
+    INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
+    INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
+    INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
+    INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
+    jz4755_mmc0_1bit_funcs),
+    INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
+    jz4755_mmc0_4bit_funcs),
+    INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
+    INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
+    INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
+    INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
+    INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
+    jz4755_lcd_24bit_funcs),


Coud you either split this into several groups (lcd-8bit, lcd-16bit, 
lcd-18bit, lcd-24bit, lcd-special, lcd-generic) like it is done for 
the JZ4725B? Same for the other SoCs.




Sure, and do we need to change the JZ4740 (and the previous JZ4750) 
to the lcd-special + lcd-generic model? It looks more reasonable than 
the original lcd-tft and makes the style more uniform.


Yes, please change it for the JZ4750 too.

For the JZ4740, in theory it is too late - these are ABI and we 
shouldn't change them.


With that said - the only board that has a JZ4740 and is still 
supported (although untested, so it's not even sure it still boots) is 
the Ben Nanonote, which only uses the "lcd-8bit" group. So it's 
probably fine.




Sure, I will do it.



Cheers,
-Paul


Alternatively just remove the "lcd" function for now.


+    { "lcd-no-pins", },


And remove this.

Cheers,
-Paul


+    INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
+    INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
+    INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
+    INGENIC_PIN_GROUP("nand-cs

Re: [PATCH v3 10/10] pinctrl: Ingenic: Add pinctrl driver for X2000.

[Zhou Yanjie]

Hi Paul,

On 2021/3/28 上午3:58, Paul Cercueil wrote:

Hi Zhou,

Le jeu. 25 mars 2021 à 17:03, Zhou Yanjie  
a écrit :

Hi Paul,

On 2021/3/23 上午2:39, Paul Cercueil wrote:



 Le mer. 17 mars 2021 à 17:58, 周琰杰 (Zhou Yanjie) 
 a écrit :

Add support for probing the pinctrl-ingenic driver on the
 X2000 SoC from Ingenic.

 Signed-off-by: 周琰杰 (Zhou Yanjie) 
 ---

 Notes:
 v3:
 New patch.

  drivers/pinctrl/pinctrl-ingenic.c | 502 
+-

  1 file changed, 493 insertions(+), 9 deletions(-)

 diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c

 index eb4912d..538d1b5 100644
 --- a/drivers/pinctrl/pinctrl-ingenic.c
 +++ b/drivers/pinctrl/pinctrl-ingenic.c
 @@ -57,6 +57,10 @@
  #define X1830_GPIO_PEL    0x110
  #define X1830_GPIO_PEH    0x120

 +#define X2000_GPIO_EDG    0x70
 +#define X2000_GPIO_PEPU    0x80
 +#define X2000_GPIO_PEPD    0x90
 +
  #define REG_SET(x)    ((x) + 0x4)
  #define REG_CLEAR(x)    ((x) + 0x8)

 @@ -94,6 +98,7 @@ enum jz_version {
  ID_X1000,
  ID_X1500,
  ID_X1830,
 +    ID_X2000,
  };

  struct ingenic_chip_info {
 @@ -2273,6 +2278,439 @@ static const struct ingenic_chip_info 
x1830_chip_info = {

  .pull_downs = x1830_pull_downs,
  };

 +static const u32 x2000_pull_ups[5] = {
 +    0x0003, 0x, 0x1ff0, 0xc7fe3f3f, 0x8fff003f,
 +};
 +
 +static const u32 x2000_pull_downs[5] = {
 +    0x0003, 0x, 0x1ff0, 0x, 0x8fff003f,
 +};
 +
 +static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
 +static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
 +static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
 +static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
 +static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
 +static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
 +static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
 +static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
 +static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
 +static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
 +static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
 +static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
 +static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
 +static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
 +static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
 +static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
 +static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
 +static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
 +static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
 +static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
 +static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
 +static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 
0x72, };
 +static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 
0x91, };

 +static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
 +static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
 +static int x2000_ssi0_dt_d_pins[] = { 0x69, };
 +static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
 +static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
 +static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
 +static int x2000_ssi0_clk_d_pins[] = { 0x68, };
 +static int x2000_ssi0_ce0_b_pins[] = { 0x3c, };
 +static int x2000_ssi0_ce0_d_pins[] = { 0x6d, };
 +static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
 +static int x2000_ssi1_dt_d_pins[] = { 0x72, };
 +static int x2000_ssi1_dt_e_pins[] = { 0x91, };
 +static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
 +static int x2000_ssi1_dr_d_pins[] = { 0x73, };
 +static int x2000_ssi1_dr_e_pins[] = { 0x92, };
 +static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
 +static int x2000_ssi1_clk_d_pins[] = { 0x71, };
 +static int x2000_ssi1_clk_e_pins[] = { 0x90, };
 +static int x2000_ssi1_ce0_c_pins[] = { 0x49, };
 +static int x2000_ssi1_ce0_d_pins[] = { 0x76, };
 +static int x2000_ssi1_ce0_e_pins[] = { 0x95, };
 +static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
 +static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
 +static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
 +static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
 +static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
 +static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
 +static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
 +static int x2000_emc_8bit_data_pins[] = {
 +    0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
 +};
 +static int x2000_emc_16bit_data_pins[] = {
 +    0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
 +};
 +static int x2000_emc_addr_pins[] = {
 +    0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
 +    0x28, 0x29, 0x2a, 0x2b, 0x2c,
 +};
 +static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
 +static int x2000_emc_wait_pins[] = { 0x2f, };
 +static int x2000_emc_cs1_pins[] = { 0x57, };
 +static int x2000_emc_cs2_pins[] = { 0x58, };
 +static int

Re: exec error: BUG: Bad rss-counter

[Zhou Yanjie]

Hi Ilya,

On 2021/3/29 上午10:48, Ilya Lipnitskiy wrote:

On Sat, Mar 20, 2021 at 8:59 AM Zhou Yanjie  wrote:

Hi Ilya,

On 2021/3/3 下午11:55, Ilya Lipnitskiy wrote:

On Wed, Mar 3, 2021 at 7:50 AM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


On Tue, Mar 2, 2021 at 11:37 AM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


On Mon, Mar 1, 2021 at 12:43 PM Eric W. Biederman  wrote:

Ilya Lipnitskiy  writes:


Eric, All,

The following error appears when running Linux 5.10.18 on an embedded
MIPS mt7621 target:
[0.301219] BUG: Bad rss-counter state mm:(ptrval) type:MM_ANONPAGES val:1

Being a very generic error, I started digging and added a stack dump
before the BUG:
Call Trace:
[<80008094>] show_stack+0x30/0x100
[<8033b238>] dump_stack+0xac/0xe8
[<800285e8>] __mmdrop+0x98/0x1d0
[<801a6de8>] free_bprm+0x44/0x118
[<801a86a8>] kernel_execve+0x160/0x1d8
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194
[<80003198>] ret_from_kernel_thread+0x14/0x1c

So that's how I got to looking at fs/exec.c and noticed quite a few
changes last year. Turns out this message only occurs once very early
at boot during the very first call to kernel_execve. current->mm is
NULL at this stage, so acct_arg_size() is effectively a no-op.

If you believe this is a new error you could bisect the kernel
to see which change introduced the behavior you are seeing.


More digging, and I traced the RSS counter increment to:
[<8015adb4>] add_mm_counter_fast+0xb4/0xc0
[<80160d58>] handle_mm_fault+0x6e4/0xea0
[<80158aa4>] __get_user_pages.part.78+0x190/0x37c
[<8015992c>] __get_user_pages_remote+0x128/0x360
[<801a6d9c>] get_arg_page+0x34/0xa0
[<801a7394>] copy_string_kernel+0x194/0x2a4
[<801a880c>] kernel_execve+0x11c/0x298
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194
[<80003198>] ret_from_kernel_thread+0x14/0x1c

In fact, I also checked vma_pages(bprm->vma) and lo and behold it is set to 1.

How is fs/exec.c supposed to handle implied RSS increments that happen
due to page faults when discarding the bprm structure? In this case,
the bug-generating kernel_execve call never succeeded, it returned -2,
but I didn't trace exactly what failed.

Unless I am mistaken any left over pages should be purged by exit_mmap
which is called by mmput before mmput calls mmdrop.

Good to know. Some more digging and I can say that we hit this error
when trying to unmap PFN 0 (is_zero_pfn(pfn) returns TRUE,
vm_normal_page returns NULL, zap_pte_range does not decrement
MM_ANONPAGES RSS counter). Is my understanding correct that PFN 0 is
usable, but special? Or am I totally off the mark here?

It would be good to know if that is the page that get_user_pages_remote
returned to copy_string_kernel.  The zero page that is always zero,
should never be returned when a writable mapping is desired.

Indeed, pfn 0 is returned from get_arg_page: (page is 0x809cf000,
page_to_pfn(page) is 0) and it is the same page that is being freed and not
refcounted in mmput/zap_pte_range. Confirmed with good old printk. Also,
ZERO_PAGE(0)==0x809fc000 -> PFN 5120.

I think I have found the problem though, after much digging and thanks to all
the information provided. init_zero_pfn() gets called too late (after
the call to
is_zero_pfn(0) from mmput returns true), until then zero_pfn == 0, and after,
zero_pfn == 5120. Boom.

So PFN 0 is special, but only for a little bit, enough for something
on my system
to call kernel_execve :)

Question: is my system not supposed to be calling kernel_execve this
early or does
init_zero_pfn() need to happen earlier? init_zero_pfn is currently a
core_initcall.

Looking quickly it seems that init_zero_pfn() is in mm/memory.c and is
common for both mips and x86.  Further it appears init_zero_pfn() has
been that was since 2009 a13ea5b75964 ("mm: reinstate ZERO_PAGE").

Given the testing that x86 gets and that nothing like this has been
reported it looks like whatever driver is triggering the kernel_execve
is doing something wrong.
Because honestly.  If the zero page isn't working there is not a chance
that anything in userspace is working so it is clearly much too early.

I suspect there is some driver that is initialized very early that is
doing something that looks innocuous (like triggering a hotplug event)
and that happens to cause a call_usermode_helper which then calls
kernel_execve.

I will investigate the offenders more closely. However, I do not
notice this behavior on the same system based on the 5.4 kernel. Is it


I also encountered this problem on Ingenic X1000 and X1830. This is the
printed information:

[0.120715] BUG: Bad rss-counter state mm:(ptrval)
   type:MM_ANONPAGES val:1

I tested kernel 5.9, kernel 5.10, kernel 5.11, and kernel 5.12, only
kernel 5.9 did not have this problem, so we can know that this problem
was introduced in kernel 5.10, have you found any effective solution?

Re: [PATCH v3] mm: fix race by making init_zero_pfn() early_initcall

[Zhou Yanjie]

Hi Ilya,

On 2021/3/30 下午12:42, Ilya Lipnitskiy wrote:

There are code paths that rely on zero_pfn to be fully initialized
before core_initcall. For example, wq_sysfs_init() is a core_initcall
function that eventually results in a call to kernel_execve, which
causes a page fault with a subsequent mmput. If zero_pfn is not
initialized by then it may not get cleaned up properly and result in an
error:
   BUG: Bad rss-counter state mm:(ptrval) type:MM_ANONPAGES val:1

Here is an analysis of the race as seen on a MIPS device. On this
particular MT7621 device (Ubiquiti ER-X), zero_pfn is PFN 0 until
initialized, at which point it becomes PFN 5120:
   1. wq_sysfs_init calls into kobject_uevent_env at core_initcall:
[<80340dc8>] kobject_uevent_env+0x7e4/0x7ec
[<8033f8b8>] kset_register+0x68/0x88
[<803cf824>] bus_register+0xdc/0x34c
[<803cfac8>] subsys_virtual_register+0x34/0x78
[<8086afb0>] wq_sysfs_init+0x1c/0x4c
[<80001648>] do_one_initcall+0x50/0x1a8
[<8086503c>] kernel_init_freeable+0x230/0x2c8
[<8066bca0>] kernel_init+0x10/0x100
[<80003038>] ret_from_kernel_thread+0x14/0x1c

   2. kobject_uevent_env() calls call_usermodehelper_exec() which executes
  kernel_execve asynchronously.

   3. Memory allocations in kernel_execve cause a page fault, bumping the
  MM reference counter:
[<8015adb4>] add_mm_counter_fast+0xb4/0xc0
[<80160d58>] handle_mm_fault+0x6e4/0xea0
[<80158aa4>] __get_user_pages.part.78+0x190/0x37c
[<8015992c>] __get_user_pages_remote+0x128/0x360
[<801a6d9c>] get_arg_page+0x34/0xa0
[<801a7394>] copy_string_kernel+0x194/0x2a4
[<801a880c>] kernel_execve+0x11c/0x298
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194

   4. In case zero_pfn has not been initialized yet, zap_pte_range does
  not decrement the MM_ANONPAGES RSS counter and the BUG message is
  triggered shortly afterwards when __mmdrop checks the ref counters:
[<800285e8>] __mmdrop+0x98/0x1d0
[<801a6de8>] free_bprm+0x44/0x118
[<801a86a8>] kernel_execve+0x160/0x1d8
[<800420f4>] call_usermodehelper_exec_async+0x114/0x194
[<80003198>] ret_from_kernel_thread+0x14/0x1c

To avoid races such as described above, initialize init_zero_pfn at
early_initcall level. Depending on the architecture, ZERO_PAGE is either
constant or gets initialized even earlier, at paging_init, so there is
no issue with initializing zero_pfn earlier.

Discussion: 
https://lkml.kernel.org/r/CALCv0x2YqOXEAy2Q=hafjhHCtTHVodChv1qpM=niaxopqeb...@mail.gmail.com

Signed-off-by: Ilya Lipnitskiy 
Cc: Hugh Dickins 
Cc: "Eric W. Biederman" 
Cc: sta...@vger.kernel.org
---
  mm/memory.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)



Tested-by: 周琰杰 (Zhou Yanjie) # on 
CU1000-Neo/X1000E and CU1830-Neo/X1830




diff --git a/mm/memory.c b/mm/memory.c
index 5c3b29d3af66..e66b11ac1659 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -166,7 +166,7 @@ static int __init init_zero_pfn(void)
zero_pfn = page_to_pfn(ZERO_PAGE(0));
return 0;
  }
-core_initcall(init_zero_pfn);
+early_initcall(init_zero_pfn);
  
  void mm_trace_rss_stat(struct mm_struct *mm, int member, long count)

  {

[PATCH] Revert "MIPS: make userspace mapping young by default".

[Zhou Yanjie]

This reverts commit f685a533a7fab35c5d069dcd663f59c8e4171a75.

It cause kernel panic on Ingenic X1830, so let's revert it.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---
 arch/mips/mm/cache.c | 31 ++-
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 7719d63..9cfd432 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -21,7 +21,6 @@
 #include 
 #include 
 #include 
-#include 
 
 /* Cache operations. */
 void (*flush_cache_all)(void);
@@ -157,31 +156,29 @@ unsigned long _page_cachable_default;
 EXPORT_SYMBOL(_page_cachable_default);
 
 #define PM(p)  __pgprot(_page_cachable_default | (p))
-#define PVA(p) PM(_PAGE_VALID | _PAGE_ACCESSED | (p))
 
 static inline void setup_protection_map(void)
 {
protection_map[0]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
-   protection_map[1]  = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC);
-   protection_map[2]  = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
-   protection_map[3]  = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC);
-   protection_map[4]  = PVA(_PAGE_PRESENT);
-   protection_map[5]  = PVA(_PAGE_PRESENT);
-   protection_map[6]  = PVA(_PAGE_PRESENT);
-   protection_map[7]  = PVA(_PAGE_PRESENT);
+   protection_map[1]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
+   protection_map[2]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
+   protection_map[3]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
+   protection_map[4]  = PM(_PAGE_PRESENT);
+   protection_map[5]  = PM(_PAGE_PRESENT);
+   protection_map[6]  = PM(_PAGE_PRESENT);
+   protection_map[7]  = PM(_PAGE_PRESENT);
 
protection_map[8]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
-   protection_map[9]  = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC);
-   protection_map[10] = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE |
+   protection_map[9]  = PM(_PAGE_PRESENT | _PAGE_NO_EXEC);
+   protection_map[10] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE |
_PAGE_NO_READ);
-   protection_map[11] = PVA(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
-   protection_map[12] = PVA(_PAGE_PRESENT);
-   protection_map[13] = PVA(_PAGE_PRESENT);
-   protection_map[14] = PVA(_PAGE_PRESENT);
-   protection_map[15] = PVA(_PAGE_PRESENT);
+   protection_map[11] = PM(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
+   protection_map[12] = PM(_PAGE_PRESENT);
+   protection_map[13] = PM(_PAGE_PRESENT);
+   protection_map[14] = PM(_PAGE_PRESENT | _PAGE_WRITE);
+   protection_map[15] = PM(_PAGE_PRESENT | _PAGE_WRITE);
 }
 
-#undef _PVA
 #undef PM
 
 void cpu_cache_init(void)
-- 
2.7.4

[PATCH v5 01/11] pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.

[Zhou Yanjie]

The MII group of JZ4770's MAC should have 7 pins, add missing
pins to the MII group.

Fixes: 5de1a73e78ed ("Pinctrl: Ingenic: Add missing parts for JZ4770 and 
JZ4780.")
Cc: 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Paul Cercueil 
---

Notes:
v2:
New patch.

v2->v3:
Add fixes tag.

v3->v4:
1.Add Cc: .
2.Add Andy Shevchenko's Reviewed-by.
3.Add Paul Cercueil's Reviewed-by.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index f274612..05dfa0a 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -667,7 +667,9 @@ static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
 static int jz4770_mac_rmii_pins[] = {
0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
 };
-static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
+static int jz4770_mac_mii_pins[] = {
+   0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
+};
 
 static const struct group_desc jz4770_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
-- 
2.7.4

[PATCH v5 02/11] pinctrl: Ingenic: Add support for read the pin configuration of X1830.

[Zhou Yanjie]

Add X1830 support in "ingenic_pinconf_get()", so that it can read the
configuration of X1830 SoC correctly.

Fixes: d7da2a1e4e08 ("pinctrl: Ingenic: Add pinctrl driver for X1830.")
Cc: 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Paul Cercueil 
---

Notes:
v2:
New patch.

v2->v3:
1.Add fixes tag.
2.Adjust the code, simplify the ingenic_pinconf_get() function.

v3->v4:
1.Add parentheses around the '%' to make it more obvious.
2.Add Cc: .
3.Add Andy Shevchenko's Reviewed-by.
4.Add Paul Cercueil's Reviewed-by.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 40 ++-
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 05dfa0a..3de0f76 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -2109,26 +2109,48 @@ static int ingenic_pinconf_get(struct pinctrl_dev 
*pctldev,
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
-   bool pull;
+   unsigned int bias;
+   bool pull, pullup, pulldown;
 
-   if (jzpc->info->version >= ID_JZ4770)
-   pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
-   else
-   pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
+   if (jzpc->info->version >= ID_X1830) {
+   unsigned int half = PINS_PER_GPIO_CHIP / 2;
+   unsigned int idxh = (pin % half) * 2;
+
+   if (idx < half)
+   regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
+   X1830_GPIO_PEL, &bias);
+   else
+   regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
+   X1830_GPIO_PEH, &bias);
+
+   bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
+
+   pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] 
& BIT(idx));
+   pulldown = (bias == GPIO_PULL_DOWN) && 
(jzpc->info->pull_downs[offt] & BIT(idx));
+
+   } else {
+   if (jzpc->info->version >= ID_JZ4770)
+   pull = !ingenic_get_pin_config(jzpc, pin, 
JZ4770_GPIO_PEN);
+   else
+   pull = !ingenic_get_pin_config(jzpc, pin, 
JZ4740_GPIO_PULL_DIS);
+
+   pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
+   pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
+   }
 
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
-   if (pull)
+   if (pullup || pulldown)
return -EINVAL;
break;
 
case PIN_CONFIG_BIAS_PULL_UP:
-   if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
+   if (!pullup)
return -EINVAL;
break;
 
case PIN_CONFIG_BIAS_PULL_DOWN:
-   if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
+   if (!pulldown)
return -EINVAL;
break;
 
@@ -2146,7 +2168,7 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
if (jzpc->info->version >= ID_X1830) {
unsigned int idx = pin % PINS_PER_GPIO_CHIP;
unsigned int half = PINS_PER_GPIO_CHIP / 2;
-   unsigned int idxh = pin % half * 2;
+   unsigned int idxh = (pin % half) * 2;
unsigned int offt = pin / PINS_PER_GPIO_CHIP;
 
if (idx < half) {
-- 
2.7.4

[PATCH v5 03/11] pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.

[Zhou Yanjie]

Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Paul Cercueil 
---

Notes:
v2:
New patch.

v2->v3:
Add Paul Cercueil's Reviewed-by.

v3->v4:
Add Andy Shevchenko's Reviewed-by.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 3de0f76..72d9daa 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -1473,16 +1473,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, };
 static int x1830_ssi0_ce0_pins[] = { 0x50, };
 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
-static int x1830_ssi1_dr_c_pins[] = { 0x54, };
-static int x1830_ssi1_clk_c_pins[] = { 0x57, };
-static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
-static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
-static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
+static int x1830_ssi1_dr_c_pins[] = { 0x54, };
 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
+static int x1830_ssi1_clk_c_pins[] = { 0x57, };
 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
+static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
+static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
+static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
-- 
2.7.4

[PATCH v5 04/11] pinctrl: Ingenic: Improve LCD pins related code.

[Zhou Yanjie]

1.In the JZ4740 part, remove pointless "lcd-no-pins", use "lcd-special"
  and "lcd-generic" instead "lcd-18bit-tft". Currently, in the mainline,
  no other devicetree out there is using the "lcd-18bit-tft" ABI, so we
  should be able to replace it safely.
2.In the JZ4725B part, adjust the location of the LCD pins related code
  to keep them consistent with the style of other parts.
3.In the JZ4760 part, add the missing comma and adjust element order in
  "jz4760_lcd_special_pins[]", keep them in the order of CLS/SPL/PS/REV
  like other "lcd_special_pins" arrays. And adjust the location of the
  "jz4760_lcd_generic" related code to keep them consistent with the
  style of other parts.
4.In the JZ4770 part, remove pointless "lcd-no-pins", add the missing
  "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic".
5.In the X1000 part and the X1500 part, remove pointless "lcd-no-pins".
6.In the X1830 part, replace "lcd-rgb-18bit" with "lcd-tft-8bit" and
  "lcd-tft-24bit", because of the description of the TRANS_CONFIG.MODE
  register bits in the PM manual of the X1830, shows that the X1830 only
  supppots 24bit mode and 8bit mode for tft interface, only 18 pins in
  the GPIO table are because of the data[17:16], the data[9:8], and the
  data[1:0] has not been connected. And according to the description,
  the two interfaces supported by X1830 are respectively referred to as
  "TFT interface" and "SLCD interface", so the "lcd-rgb-xxx" is replaced
  with "lcd-tft-xxx" to avoid confusion.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
---

Notes:
v4:
New patch.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 110 +-
 1 file changed, 61 insertions(+), 49 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 72d9daa..8ed62a4 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -113,13 +113,15 @@ static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
 static int jz4740_lcd_8bit_pins[] = {
-   0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
+   0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
+   0x52, 0x53, 0x54,
 };
 static int jz4740_lcd_16bit_pins[] = {
-   0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
+   0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 };
 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
-static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
+static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
+static int jz4740_lcd_generic_pins[] = { 0x55, };
 static int jz4740_nand_cs1_pins[] = { 0x39, };
 static int jz4740_nand_cs2_pins[] = { 0x3a, };
 static int jz4740_nand_cs3_pins[] = { 0x3b, };
@@ -155,8 +157,8 @@ static const struct group_desc jz4740_groups[] = {
INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
-   INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0),
-   { "lcd-no-pins", },
+   INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
+   INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
@@ -176,7 +178,7 @@ static const char *jz4740_mmc_groups[] = { "mmc-1bit", 
"mmc-4bit", };
 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 static const char *jz4740_uart1_groups[] = { "uart1-data", };
 static const char *jz4740_lcd_groups[] = {
-   "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
+   "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
 };
 static const char *jz4740_nand_groups[] = {
"nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
@@ -223,6 +225,17 @@ static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, 
};
 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
+static int jz4725b_lcd_8bit_pins[] = {
+   0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+   0x72, 0x73, 0x74,
+};
+static int 

[PATCH v5 08/11] pinctrl: Ingenic: Add pinctrl driver for JZ4750.

[Zhou Yanjie]

Add support for probing the pinctrl-ingenic driver on the
JZ4750 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
---

Notes:
v3:
New patch.

v3->v4:
1.Use "lcd-special" and "lcd-generic" instead "lcd-18bit-tft".
2.Drop "lcd-no-pins" which is pointless.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 139 ++
 1 file changed, 139 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 4c48250..02fe3bf 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -85,6 +85,7 @@ enum jz_version {
ID_JZ4730,
ID_JZ4740,
ID_JZ4725B,
+   ID_JZ4750,
ID_JZ4760,
ID_JZ4770,
ID_JZ4780,
@@ -427,6 +428,140 @@ static const struct ingenic_chip_info jz4725b_chip_info = 
{
.pull_downs = jz4740_pull_downs,
 };
 
+static const u32 jz4750_pull_ups[6] = {
+   0x, 0x, 0x3fff, 0x7fff, 0x1fff3fff, 0x00ff,
+};
+
+static const u32 jz4750_pull_downs[6] = {
+   0x, 0x, 0x, 0x, 0x, 0x,
+};
+
+static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
+static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
+static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
+static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
+static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
+static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
+static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
+static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
+static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
+static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
+static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
+static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
+static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4750_cim_pins[] = {
+   0x89, 0x8b, 0x8a, 0x88,
+   0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4750_lcd_8bit_pins[] = {
+   0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+   0x72, 0x73, 0x74,
+};
+static int jz4750_lcd_16bit_pins[] = {
+   0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+};
+static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
+static int jz4750_lcd_generic_pins[] = { 0x75, };
+static int jz4750_nand_cs1_pins[] = { 0x55, };
+static int jz4750_nand_cs2_pins[] = { 0x56, };
+static int jz4750_nand_cs3_pins[] = { 0x57, };
+static int jz4750_nand_cs4_pins[] = { 0x58, };
+static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4750_pwm_pwm0_pins[] = { 0x94, };
+static int jz4750_pwm_pwm1_pins[] = { 0x95, };
+static int jz4750_pwm_pwm2_pins[] = { 0x96, };
+static int jz4750_pwm_pwm3_pins[] = { 0x97, };
+static int jz4750_pwm_pwm4_pins[] = { 0x98, };
+static int jz4750_pwm_pwm5_pins[] = { 0x99, };
+
+static const struct group_desc jz4750_groups[] = {
+   INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
+   INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
+   INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
+   INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
+   INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
+   INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
+   INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
+   INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
+   INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
+   INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
+   INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
+   INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
+   INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
+   INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
+   INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
+   INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
+   INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
+   INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
+   INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
+   INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
+   INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
+   INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
+   INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
+   INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
+   INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
+   INGE

[PATCH v5 05/11] pinctrl: Ingenic: Reformat the code.

[Zhou Yanjie]

1.Move the "INGENIC_PIN_GROUP_FUNCS" to the macro definition section.
2.Add tabs before values to align the code in the macro definition section.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Paul Cercueil 
---

Notes:
v2:
New patch.

v2->v3:
Add Paul Cercueil's Reviewed-by.

v3->v4:
Add Andy Shevchenko's Reviewed-by.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 71 +++
 1 file changed, 35 insertions(+), 36 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 8ed62a4..009901b 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -26,37 +26,48 @@
 #include "pinconf.h"
 #include "pinmux.h"
 
-#define GPIO_PIN   0x00
-#define GPIO_MSK   0x20
+#define GPIO_PIN   0x00
+#define GPIO_MSK   0x20
 
-#define JZ4740_GPIO_DATA   0x10
-#define JZ4740_GPIO_PULL_DIS   0x30
-#define JZ4740_GPIO_FUNC   0x40
-#define JZ4740_GPIO_SELECT 0x50
-#define JZ4740_GPIO_DIR0x60
-#define JZ4740_GPIO_TRIG   0x70
-#define JZ4740_GPIO_FLAG   0x80
+#define JZ4740_GPIO_DATA   0x10
+#define JZ4740_GPIO_PULL_DIS   0x30
+#define JZ4740_GPIO_FUNC   0x40
+#define JZ4740_GPIO_SELECT 0x50
+#define JZ4740_GPIO_DIR0x60
+#define JZ4740_GPIO_TRIG   0x70
+#define JZ4740_GPIO_FLAG   0x80
 
-#define JZ4770_GPIO_INT0x10
-#define JZ4770_GPIO_PAT1   0x30
-#define JZ4770_GPIO_PAT0   0x40
-#define JZ4770_GPIO_FLAG   0x50
-#define JZ4770_GPIO_PEN0x70
+#define JZ4770_GPIO_INT0x10
+#define JZ4770_GPIO_PAT1   0x30
+#define JZ4770_GPIO_PAT0   0x40
+#define JZ4770_GPIO_FLAG   0x50
+#define JZ4770_GPIO_PEN0x70
 
-#define X1830_GPIO_PEL 0x110
-#define X1830_GPIO_PEH 0x120
+#define X1830_GPIO_PEL 0x110
+#define X1830_GPIO_PEH 0x120
 
-#define REG_SET(x) ((x) + 0x4)
-#define REG_CLEAR(x) ((x) + 0x8)
+#define REG_SET(x) ((x) + 0x4)
+#define REG_CLEAR(x)   ((x) + 0x8)
 
-#define REG_PZ_BASE(x) ((x) * 7)
-#define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
+#define REG_PZ_BASE(x) ((x) * 7)
+#define REG_PZ_GID2LD(x)   ((x) * 7 + 0xf0)
 
-#define GPIO_PULL_DIS  0
-#define GPIO_PULL_UP   1
-#define GPIO_PULL_DOWN 2
+#define GPIO_PULL_DIS  0
+#define GPIO_PULL_UP   1
+#define GPIO_PULL_DOWN 2
 
-#define PINS_PER_GPIO_CHIP 32
+#define PINS_PER_GPIO_CHIP 32
+
+#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)   \
+   {   \
+   name,   \
+   id##_pins,  \
+   ARRAY_SIZE(id##_pins),  \
+   funcs,  \
+   }
+
+#define INGENIC_PIN_GROUP(name, id, func)  \
+   INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
 
 enum jz_version {
ID_JZ4740,
@@ -136,18 +147,6 @@ static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
 
-
-#define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)   \
-   {   \
-   name,   \
-   id##_pins,  \
-   ARRAY_SIZE(id##_pins),  \
-   funcs,  \
-   }
-
-#define INGENIC_PIN_GROUP(name, id, func)  \
-   INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
-
 static const struct group_desc jz4740_groups[] = {
INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
-- 
2.7.4

[PATCH v5 06/11] dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.

[Zhou Yanjie]

Add the pinctrl bindings for the JZ4730 SoC, the JZ4750 SoC,
the JZ4755 SoC, the JZ4775 SoC and the X2000 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Rob Herring 
---

Notes:
v2:
New patch.

v2->v3:
No change.

v3->v4:
1.Add a description of JZ4725B.
2.Add Rob Herring's Reviewed-by.

v4->v5:
No change.

 .../bindings/pinctrl/ingenic,pinctrl.yaml  | 23 ++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml 
b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
index 44c04d1..a4846d78 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -17,10 +17,12 @@ description: >
   naming scheme "PxN" where x is a character identifying the GPIO port with
   which the pin is associated and N is an integer from 0 to 31 identifying the
   pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
-  and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
-  contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
-  JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
-  pins.
+  and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
+  the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
+  pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
+  The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
+  ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
+  PA to PG, for a total of 224 pins.
 
 maintainers:
   - Paul Cercueil 
@@ -32,20 +34,28 @@ properties:
   compatible:
 oneOf:
   - enum:
+  - ingenic,jz4730-pinctrl
   - ingenic,jz4740-pinctrl
   - ingenic,jz4725b-pinctrl
+  - ingenic,jz4750-pinctrl
+  - ingenic,jz4755-pinctrl
   - ingenic,jz4760-pinctrl
   - ingenic,jz4770-pinctrl
+  - ingenic,jz4775-pinctrl
   - ingenic,jz4780-pinctrl
   - ingenic,x1000-pinctrl
   - ingenic,x1500-pinctrl
   - ingenic,x1830-pinctrl
+  - ingenic,x2000-pinctrl
   - items:
   - const: ingenic,jz4760b-pinctrl
   - const: ingenic,jz4760-pinctrl
   - items:
   - const: ingenic,x1000e-pinctrl
   - const: ingenic,x1000-pinctrl
+  - items:
+  - const: ingenic,x2000e-pinctrl
+  - const: ingenic,x2000-pinctrl
 
   reg:
 maxItems: 1
@@ -62,14 +72,19 @@ patternProperties:
 properties:
   compatible:
 enum:
+  - ingenic,jz4730-gpio
   - ingenic,jz4740-gpio
   - ingenic,jz4725b-gpio
+  - ingenic,jz4750-gpio
+  - ingenic,jz4755-gpio
   - ingenic,jz4760-gpio
   - ingenic,jz4770-gpio
+  - ingenic,jz4775-gpio
   - ingenic,jz4780-gpio
   - ingenic,x1000-gpio
   - ingenic,x1500-gpio
   - ingenic,x1830-gpio
+  - ingenic,x2000-gpio
 
   reg:
 items:
-- 
2.7.4

[PATCH v5 00/11] Fix bugs and add support for new Ingenic SoCs.

[Zhou Yanjie]

v1->v2:
1.Split [1/3] in v1 to [1/6] [2/6] [3/6] [4/6] in v2.
2.Fix the uninitialized warning.

v2->v3:
Split [6/6] in v2 to [6/10] [7/10] [8/10] [9/10] [10/10] in v3.

v3->v4:
1.Modify the format of comment.
2.Split lcd pins into several groups.
3.Drop "lcd-no-pins" which is pointless.
4.Improve the structure of some functions.
5.Adjust function names to avoid confusion.
6.Use "lcd-special" and "lcd-generic" instead "lcd-xxbit-tft".
7.Replace "lcd-rgb-xxx" with "lcd-tft-xxx" to avoid confusion.

v4->v5:
Add support for schmitt and slew.

周琰杰 (Zhou Yanjie) (11):
  pinctrl: Ingenic: Add missing pins to the JZ4770 MAC MII group.
  pinctrl: Ingenic: Add support for read the pin configuration of X1830.
  pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.
  pinctrl: Ingenic: Improve LCD pins related code.
  pinctrl: Ingenic: Reformat the code.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for X2000.

 .../bindings/pinctrl/ingenic,pinctrl.yaml  |   23 +-
 drivers/pinctrl/pinctrl-ingenic.c  | 1619 ++--
 2 files changed, 1507 insertions(+), 135 deletions(-)

-- 
2.7.4

[PATCH v5 09/11] pinctrl: Ingenic: Add pinctrl driver for JZ4755.

[Zhou Yanjie]

Add support for probing the pinctrl-ingenic driver on the
JZ4755 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
---

Notes:
v3:
New patch.

v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointless.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 139 ++
 1 file changed, 139 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 02fe3bf..3b649fb 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -86,6 +86,7 @@ enum jz_version {
ID_JZ4740,
ID_JZ4725B,
ID_JZ4750,
+   ID_JZ4755,
ID_JZ4760,
ID_JZ4770,
ID_JZ4780,
@@ -562,6 +563,138 @@ static const struct ingenic_chip_info jz4750_chip_info = {
.pull_downs = jz4750_pull_downs,
 };
 
+static const u32 jz4755_pull_ups[6] = {
+   0x, 0x, 0x0fff, 0x, 0x33dc3fff, 0xfc00,
+};
+
+static const u32 jz4755_pull_downs[6] = {
+   0x, 0x, 0x, 0x, 0x, 0x,
+};
+
+static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
+static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
+static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
+static int jz4755_uart2_data_pins[] = { 0x9f, };
+static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
+static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
+static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
+static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
+static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
+static int jz4755_cim_pins[] = {
+   0x89, 0x8b, 0x8a, 0x88,
+   0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+};
+static int jz4755_lcd_8bit_pins[] = {
+   0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+   0x72, 0x73, 0x74,
+};
+static int jz4755_lcd_16bit_pins[] = {
+   0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+};
+static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
+static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
+static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
+static int jz4755_lcd_generic_pins[] = { 0x75, };
+static int jz4755_nand_cs1_pins[] = { 0x55, };
+static int jz4755_nand_cs2_pins[] = { 0x56, };
+static int jz4755_nand_cs3_pins[] = { 0x57, };
+static int jz4755_nand_cs4_pins[] = { 0x58, };
+static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
+static int jz4755_pwm_pwm0_pins[] = { 0x94, };
+static int jz4755_pwm_pwm1_pins[] = { 0xab, };
+static int jz4755_pwm_pwm2_pins[] = { 0x96, };
+static int jz4755_pwm_pwm3_pins[] = { 0x97, };
+static int jz4755_pwm_pwm4_pins[] = { 0x98, };
+static int jz4755_pwm_pwm5_pins[] = { 0x99, };
+
+static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
+static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
+static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
+
+static const struct group_desc jz4755_groups[] = {
+   INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
+   INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
+   INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
+   INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
+   INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
+   jz4755_mmc0_1bit_funcs),
+   INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
+   jz4755_mmc0_4bit_funcs),
+   INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
+   INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
+   INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
+   INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
+   INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
+   INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
+   INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
+   INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
+   jz4755_lcd_24bit_funcs),
+   INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
+   INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
+   INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
+   INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
+   INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
+   INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
+   INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
+   INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
+   INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
+   INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
+   INGENIC_PIN_GROUP("pwm3", jz4755_

[PATCH v5 07/11] pinctrl: Ingenic: Add pinctrl driver for JZ4730.

[Zhou Yanjie]

Add support for probing the pinctrl-ingenic driver on the
JZ4730 SoC from Ingenic.

This driver is derived from Paul Boddie. It is worth to
noting that the JZ4730 SoC is special in having two control
registers (upper/lower), so add code to handle the JZ4730
specific register offsets and some register pairs which have
2 bits for each GPIO pin.

Tested-by: H. Nikolaus Schaller   # on Letux400
Co-developed-by: Paul Boddie 
Signed-off-by: Paul Boddie 
Signed-off-by: H. Nikolaus Schaller 
Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
---

Notes:
v3:
New patch.

v3->v4:
1.Use "lcd-special" and "lcd-generic" instead "lcd-16bit-tft".
2.Adjust function names to avoid confusion.
3.Improve the structure of some functions.
4.Modify the format of comment.
5.Simplify code using GENMASK.
6.Drop unnecessary mask.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 232 +++---
 1 file changed, 216 insertions(+), 16 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 009901b..4c48250 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -3,8 +3,8 @@
  * Ingenic SoCs pinctrl driver
  *
  * Copyright (c) 2017 Paul Cercueil 
- * Copyright (c) 2019 周琰杰 (Zhou Yanjie) 
  * Copyright (c) 2017, 2019 Paul Boddie 
+ * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) 
  */
 
 #include 
@@ -29,6 +29,17 @@
 #define GPIO_PIN   0x00
 #define GPIO_MSK   0x20
 
+#define JZ4730_GPIO_DATA   0x00
+#define JZ4730_GPIO_GPDIR  0x04
+#define JZ4730_GPIO_GPPUR  0x0c
+#define JZ4730_GPIO_GPALR  0x10
+#define JZ4730_GPIO_GPAUR  0x14
+#define JZ4730_GPIO_GPIDLR 0x18
+#define JZ4730_GPIO_GPIDUR 0x1c
+#define JZ4730_GPIO_GPIER  0x20
+#define JZ4730_GPIO_GPIMR  0x24
+#define JZ4730_GPIO_GPFR   0x28
+
 #define JZ4740_GPIO_DATA   0x10
 #define JZ4740_GPIO_PULL_DIS   0x30
 #define JZ4740_GPIO_FUNC   0x40
@@ -57,6 +68,7 @@
 #define GPIO_PULL_DOWN 2
 
 #define PINS_PER_GPIO_CHIP 32
+#define JZ4730_PINS_PER_PAIRED_REG 16
 
 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)   \
{   \
@@ -70,6 +82,7 @@
INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
 
 enum jz_version {
+   ID_JZ4730,
ID_JZ4740,
ID_JZ4725B,
ID_JZ4760,
@@ -110,6 +123,99 @@ struct ingenic_gpio_chip {
unsigned int irq, reg_base;
 };
 
+static const u32 jz4730_pull_ups[4] = {
+   0x3fa3320f, 0xf200, 0x, 0x,
+};
+
+static const u32 jz4730_pull_downs[4] = {
+   0x0df0, 0x0dff, 0x, 0x,
+};
+
+static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
+static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
+static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
+static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
+static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
+static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
+static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
+static int jz4730_lcd_8bit_pins[] = {
+   0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
+   0x3a, 0x39, 0x38,
+};
+static int jz4730_lcd_16bit_pins[] = {
+   0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+};
+static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
+static int jz4730_lcd_generic_pins[] = { 0x3b, };
+static int jz4730_nand_cs1_pins[] = { 0x53, };
+static int jz4730_nand_cs2_pins[] = { 0x54, };
+static int jz4730_nand_cs3_pins[] = { 0x55, };
+static int jz4730_nand_cs4_pins[] = { 0x56, };
+static int jz4730_nand_cs5_pins[] = { 0x57, };
+static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
+static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
+
+static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
+
+static const struct group_desc jz4730_groups[] = {
+   INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
+   INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
+   INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
+   INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
+   INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
+   INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
+   INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
+   INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, 
jz4730_lcd_8bit_funcs),
+   INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
+

[PATCH v5 11/11] pinctrl: Ingenic: Add pinctrl driver for X2000.

[Zhou Yanjie]

Add support for probing the pinctrl-ingenic driver on the
X2000 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
---

Notes:
v3:
New patch.

v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointless.
3.Replace "lcd-rgb-xxx" with "lcd-tft-xxx" to avoid confusion.

v4->v5:
Add support for schmitt and slew.

 drivers/pinctrl/pinctrl-ingenic.c | 593 +-
 1 file changed, 581 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 9bf9100..f5573af 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -56,6 +56,14 @@
 
 #define X1830_GPIO_PEL 0x110
 #define X1830_GPIO_PEH 0x120
+#define X1830_GPIO_SR  0x150
+#define X1830_GPIO_SMT 0x160
+
+#define X2000_GPIO_EDG 0x70
+#define X2000_GPIO_PEPU0x80
+#define X2000_GPIO_PEPD0x90
+#define X2000_GPIO_SR  0xd0
+#define X2000_GPIO_SMT 0xe0
 
 #define REG_SET(x) ((x) + 0x4)
 #define REG_CLEAR(x)   ((x) + 0x8)
@@ -94,6 +102,7 @@ enum jz_version {
ID_X1000,
ID_X1500,
ID_X1830,
+   ID_X2000,
 };
 
 struct ingenic_chip_info {
@@ -2313,6 +2322,449 @@ static const struct ingenic_chip_info x1830_chip_info = 
{
.pull_downs = x1830_pull_downs,
 };
 
+static const u32 x2000_pull_ups[5] = {
+   0x0003, 0x, 0x1ff0, 0xc7fe3f3f, 0x8fff003f,
+};
+
+static const u32 x2000_pull_downs[5] = {
+   0x0003, 0x, 0x1ff0, 0x, 0x8fff003f,
+};
+
+static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
+static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
+static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
+static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
+static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
+static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
+static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
+static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
+static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
+static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
+static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
+static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
+static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
+static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
+static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
+static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
+static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
+static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
+static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
+static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
+static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
+static int x2000_sfc0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, 0x71, 0x72, };
+static int x2000_sfc0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, 0x90, 0x91, };
+static int x2000_sfc1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
+static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
+static int x2000_ssi0_dt_d_pins[] = { 0x69, };
+static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
+static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
+static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
+static int x2000_ssi0_clk_d_pins[] = { 0x68, };
+static int x2000_ssi0_ce0_b_pins[] = { 0x3c, };
+static int x2000_ssi0_ce0_d_pins[] = { 0x6d, };
+static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
+static int x2000_ssi1_dt_d_pins[] = { 0x72, };
+static int x2000_ssi1_dt_e_pins[] = { 0x91, };
+static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
+static int x2000_ssi1_dr_d_pins[] = { 0x73, };
+static int x2000_ssi1_dr_e_pins[] = { 0x92, };
+static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
+static int x2000_ssi1_clk_d_pins[] = { 0x71, };
+static int x2000_ssi1_clk_e_pins[] = { 0x90, };
+static int x2000_ssi1_ce0_c_pins[] = { 0x49, };
+static int x2000_ssi1_ce0_d_pins[] = { 0x76, };
+static int x2000_ssi1_ce0_e_pins[] = { 0x95, };
+static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
+static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
+static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
+static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
+static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
+static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
+static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
+static int x2000_emc_8bit_data_pins[] = {
+   0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
+};
+static int x2000_emc_16bit_data_pins[] = {
+   0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+};
+static int x2000_emc_addr_pins[] = {
+   0x20, 0x21

[PATCH v5 10/11] pinctrl: Ingenic: Add pinctrl driver for JZ4775.

[Zhou Yanjie]

Add support for probing the pinctrl-ingenic driver on the
JZ4775 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) 
Reviewed-by: Andy Shevchenko 
---

Notes:
v3:
New patch.

v3->v4:
1.Split lcd pins into several groups.
2.Drop "lcd-no-pins" which is pointless.

v4->v5:
No change.

 drivers/pinctrl/pinctrl-ingenic.c | 275 ++
 1 file changed, 275 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ingenic.c 
b/drivers/pinctrl/pinctrl-ingenic.c
index 3b649fb..9bf9100 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -89,6 +89,7 @@ enum jz_version {
ID_JZ4755,
ID_JZ4760,
ID_JZ4770,
+   ID_JZ4775,
ID_JZ4780,
ID_X1000,
ID_X1500,
@@ -1261,6 +1262,275 @@ static const struct ingenic_chip_info jz4770_chip_info 
= {
.pull_downs = jz4770_pull_downs,
 };
 
+static const u32 jz4775_pull_ups[7] = {
+   0x28ff00ff, 0xf030f3fc, 0x0fff, 0xfffe4000, 0xf0fc, 0xf00f, 
0xf3c0,
+};
+
+static const u32 jz4775_pull_downs[7] = {
+   0x, 0x00030c03, 0x, 0x8000, 0x0403, 0x0ff0, 
0x00030c00,
+};
+
+static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
+static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
+static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
+static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
+static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
+static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
+static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
+static int jz4775_ssi_dt_a_pins[] = { 0x13, };
+static int jz4775_ssi_dt_d_pins[] = { 0x75, };
+static int jz4775_ssi_dr_a_pins[] = { 0x14, };
+static int jz4775_ssi_dr_d_pins[] = { 0x74, };
+static int jz4775_ssi_clk_a_pins[] = { 0x12, };
+static int jz4775_ssi_clk_d_pins[] = { 0x78, };
+static int jz4775_ssi_gpc_pins[] = { 0x76, };
+static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
+static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
+static int jz4775_ssi_ce1_pins[] = { 0x77, };
+static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
+static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
+static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
+static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
+static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
+static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
+static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
+static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
+static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4775_nemc_8bit_data_pins[] = {
+   0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+};
+static int jz4775_nemc_16bit_data_pins[] = {
+   0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
+};
+static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
+static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
+static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
+static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
+static int jz4775_nemc_wait_pins[] = { 0x1b, };
+static int jz4775_nemc_cs1_pins[] = { 0x15, };
+static int jz4775_nemc_cs2_pins[] = { 0x16, };
+static int jz4775_nemc_cs3_pins[] = { 0x17, };
+static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
+static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
+static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
+static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
+static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
+static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
+static int jz4775_i2s_sysclk_pins[] = { 0x83, };
+static int jz4775_cim_pins[] = {
+   0x26, 0x27, 0x28, 0x29,
+   0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
+};
+static int jz4775_lcd_8bit_pins[] = {
+   0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
+   0x48, 0x52, 0x53,
+};
+static int jz4775_lcd_16bit_pins[] = {
+   0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
+};
+static int jz4775_lcd_18bit_pins[] = {
+   0x5a, 0x5b,
+};
+static int jz4775_lcd_24bit_pins[] = {
+   0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
+};
+static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
+static int jz4775_lcd_generic_pins[] = { 0x49, };
+static int jz4775_pwm_pwm0_pins[] = { 0x80, };
+static int jz4775_pwm_pwm1_pins[] = { 0x81, };
+static int jz4775_pwm_pwm2_pins[] = { 0x82, };
+static int jz4775_pwm_pwm3_pins[] = { 0x83, };
+static int jz4775_mac_rmii_pins[] = {
+   0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
+};
+static int jz4775_mac_mii_pins[] = {
+   0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
+};
+static int jz4775_mac_rgmii_pins[] = {
+ 

Re: [PATCH] I2C: JZ4780: Fix bug for Ingenic X1000.

[Zhou Yanjie]

Hi Wolfram,

On 2021/3/31 下午3:18, Wolfram Sang wrote:

Hi,


Any write operation? I wonder then why nobody noticed before?


The standard I2C communication should look like this:

Read:

device_addr + w, reg_addr, device_addr + r, data;

Write:

device_addr + w, reg_addr, data;


But without this patch, it looks like this:

Read:

device_addr + w, reg_addr, device_addr + r, data;

Write:

device_addr + w, reg_addr, device_addr + w, data;

This is clearly not correct.

Thanks for the additional information! I understand now. I added a bit
of this to the commit message of v2 to explain the situation.



Thanks!


Best regards!