[PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
.../bindings/sound/rockchip,rk3399-gru-sound.txt |6 ++
sound/soc/rockchip/rk3399_gru_sound.c | 14 ++
2 files changed, 20 insertions(+)
diff --git
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
connected to the codecs
- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+Optional properties:
+- dmic-delay : specify delay time for DMIC ready.
+ If this option is specified, which means it's required dmic need
+ delay for DMIC to ready so that rt5514 can avoid recording before
+ DMIC send valid data
+
Example:
sound {
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
#define SOUND_FS 256
+unsigned int rt5514_dmic_delay;
+
static struct snd_soc_jack rockchip_sound_jack;
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct
snd_pcm_substream *substream,
return ret;
}
+ /* Wait for DMIC stable */
+ msleep(rt5514_dmic_delay);
+
return 0;
}
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device
*pdev)
return -ENODEV;
}
+ /* Set DMIC delay */
+ ret = device_property_read_u32(&pdev->dev, "dmic-delay",
+ &rt5514_dmic_delay);
+ if (ret) {
+ rt5514_dmic_delay = 0;
+ dev_dbg(&pdev->dev,
+ "no optional property 'dmic-delay' found, default: no
delay\n");
+ }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.7.9.5
[PATCH v2] ASoC: rk3399_gru_sound: fix recording pop at first attempt
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms
.../bindings/sound/rockchip,rk3399-gru-sound.txt | 7 +++
sound/soc/rockchip/rk3399_gru_sound.c | 14 ++
2 files changed, 21 insertions(+)
diff --git
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..eac91db 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,10 +6,17 @@ Required properties:
connected to the codecs
- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+Optional properties:
+- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready.
+ If this option is specified, which means it's required dmic need
+ delay for DMIC to ready so that rt5514 can avoid recording before
+ DMIC send valid data
+
Example:
sound {
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <&i2s0>;
rockchip,codec = <&max98357a &rt5514 &da7219>;
+ dmic-wakeup-delay-ms = <20>;
};
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c
b/sound/soc/rockchip/rk3399_gru_sound.c
index ee06489..9ed735a 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -38,6 +38,8 @@
#define SOUND_FS 256
+unsigned int rt5514_dmic_delay;
+
static struct snd_soc_jack rockchip_sound_jack;
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -123,6 +125,9 @@ static int rockchip_sound_rt5514_hw_params(struct
snd_pcm_substream *substream,
return ret;
}
+ /* Wait for DMIC stable */
+ msleep(rt5514_dmic_delay);
+
return 0;
}
@@ -343,6 +348,15 @@ static int rockchip_sound_probe(struct platform_device
*pdev)
return -ENODEV;
}
+ /* Set DMIC delay */
+ ret = device_property_read_u32(&pdev->dev, "dmic-delay",
+ &rt5514_dmic_delay);
+ if (ret) {
+ rt5514_dmic_delay = 0;
+ dev_dbg(&pdev->dev,
+ "no optional property 'dmic-delay' found, default: no
delay\n");
+ }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.9.1
Re: [PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt
Hi Mark,
On 2016年09月19日 22:44, Mark Rutland wrote:
On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:
From: Wonjoon Lee
Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working
Signed-off-by: Wonjoon Lee
Signed-off-by: Xing Zheng
---
.../bindings/sound/rockchip,rk3399-gru-sound.txt |6 ++
sound/soc/rockchip/rk3399_gru_sound.c | 14 ++
2 files changed, 20 insertions(+)
diff --git
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
connected to the codecs
- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+Optional properties:
+- dmic-delay : specify delay time for DMIC ready.
+ If this option is specified, which means it's required dmic need
+ delay for DMIC to ready so that rt5514 can avoid recording before
+ DMIC send valid data
What units is this in? Per the code it looks like ms, so if we follow
Documentation/devicetree/bindings/property-units.txt, thous should be
named something like dmic-enable-delay-ms.
OK, the "dmic-wakeup-delay-ms" have been done.
That said, do we even need a property for this? Does this vary much in
practice?
If it does, can we not derive this delay from other information (e.g.
the rates of input clocks and so on)? What exactly determines the
necessary delay?
Yeah, the DMIC spec indicates wake-up time as 15ms max, so we need to
start recording 15ms after MCLK after testing.
@Woojoo, please correct me if I was wrong.
Thanks.
Thanks,
Mark.
sound {
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
#define SOUND_FS 256
+unsigned int rt5514_dmic_delay;
+
static struct snd_soc_jack rockchip_sound_jack;
static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct
snd_pcm_substream *substream,
return ret;
}
+ /* Wait for DMIC stable */
+ msleep(rt5514_dmic_delay);
+
return 0;
}
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device *pdev)
return -ENODEV;
}
+ /* Set DMIC delay */
+ ret = device_property_read_u32(&pdev->dev, "dmic-delay",
+ &rt5514_dmic_delay);
+ if (ret) {
+ rt5514_dmic_delay = 0;
+ dev_dbg(&pdev->dev,
+ "no optional property 'dmic-delay' found, default: no
delay\n");
+ }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name =
kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.7.9.5
--
- Xing Zheng
[PATCH 0/5] Fix and improve clock controller for the RK322x SoCs
Hi, These patchset fix some clocks bugs, and improve clock configuration for i2s/spdif/MAC on RK322x SoCs. Thanks. Xing Zheng (5): clk: rockchip: rk3228: fix incorrect clock node names clk: rockchip: rk3228: include downstream muxes into fractional dividers clk: rockchip: rk3228: export related i2s/spdif clocks clk: rockchip: rk3228: rename sclk_macphy_50m to sclk_mac_extclk clk: rockchip: rk3228: export related MAC clocks drivers/clk/rockchip/clk-rk3228.c | 125 +++- include/dt-bindings/clock/rk3228-cru.h | 15 2 files changed, 89 insertions(+), 51 deletions(-) -- 1.7.9.5
[PATCH 2/5] clk: rockchip: rk3228: include downstream muxes into fractional dividers
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 79 -
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 2f1442f..72bcdba 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -170,6 +170,34 @@ static struct rockchip_pll_clock rk3228_pll_clks[]
__initdata = {
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
+ MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
+ MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
+ MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
+ MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
+ MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
+ MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
+ MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
+
static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
/*
* Clock-Architecture Diagram 1
@@ -379,22 +407,21 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
- COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(8), 0,
- RK2928_CLKGATE_CON(0), 4, GFLAGS),
- COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
- RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
+ RK2928_CLKGATE_CON(0), 4, GFLAGS,
+ &rk3228_i2s0_fracmux),
+ GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 10, GFLAGS),
- COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(7), 0,
RK2928_CLKGATE_CON(0), 11, GFLAGS,
- MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
- RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
- GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
+ &rk3228_i2s1_fracmux),
+ GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
@@ -403,21 +430,20 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
- COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(30), 0,
- RK2928_CLKGATE_CON(0), 8, GFLAGS),
- COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
- RK2928
[PATCH 1/5] clk: rockchip: rk3228: fix incorrect clock node names
Due to copy and paste carelessly, RK3288_CLKxxx nodes are incorrect,
we need to fix them.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 016bdb0..2f1442f 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -335,7 +335,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKGATE_CON(2), 6, GFLAGS),
GATE(0, "sclk_hsadc", "ext_hsadc", 0,
- RK3288_CLKGATE_CON(10), 12, GFLAGS),
+ RK2928_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
@@ -380,8 +380,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
- RK3288_CLKSEL_CON(8), 0,
- RK3288_CLKGATE_CON(0), 4, GFLAGS),
+ RK2928_CLKSEL_CON(8), 0,
+ RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
@@ -390,8 +390,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
- RK3288_CLKSEL_CON(7), 0,
- RK3288_CLKGATE_CON(0), 11, GFLAGS),
+ RK2928_CLKSEL_CON(7), 0,
+ RK2928_CLKGATE_CON(0), 11, GFLAGS,
MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
@@ -404,8 +404,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
- RK3288_CLKSEL_CON(30), 0,
- RK3288_CLKGATE_CON(0), 8, GFLAGS),
+ RK2928_CLKSEL_CON(30), 0,
+ RK2928_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
@@ -414,8 +414,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
- RK3288_CLKSEL_CON(20), 0,
- RK3288_CLKGATE_CON(2), 12, GFLAGS),
+ RK2928_CLKSEL_CON(20), 0,
+ RK2928_CLKGATE_CON(2), 12, GFLAGS),
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
--
1.7.9.5
[PATCH 3/5] clk: rockchip: rk3228: export related i2s/spdif clocks
This patch exports related i2s/spdif clocks for dts reference.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c |8
include/dt-bindings/clock/rk3228-cru.h |4
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 72bcdba..79a3db1 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -581,10 +581,10 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(10), 1, GFLAGS),
GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
- GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7,
GFLAGS),
- GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8,
GFLAGS),
- GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9,
GFLAGS),
- GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10,
GFLAGS),
+ GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0,
RK2928_CLKGATE_CON(8), 7, GFLAGS),
+ GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0,
RK2928_CLKGATE_CON(8), 8, GFLAGS),
+ GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0,
RK2928_CLKGATE_CON(8), 9, GFLAGS),
+ GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0,
RK2928_CLKGATE_CON(8), 10, GFLAGS),
GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11,
GFLAGS),
GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12,
GFLAGS),
diff --git a/include/dt-bindings/clock/rk3228-cru.h
b/include/dt-bindings/clock/rk3228-cru.h
index 5d43ed9..c992f3e 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -84,6 +84,10 @@
#define PCLK_HDMI_PHY 365
/* hclk gates */
+#define HCLK_I2S0_8CH 442
+#define HCLK_I2S1_8CH 443
+#define HCLK_I2S2_2CH 444
+#define HCLK_SPDIF_8CH 445
#define HCLK_VOP 452
#define HCLK_NANDC 453
#define HCLK_SDMMC 456
--
1.7.9.5
[PATCH 4/5] clk: rockchip: rk3228: rename sclk_macphy_50m to sclk_mac_extclk
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes
a external clock clearly.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 79a3db1..980d0da 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -151,8 +151,8 @@ PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac",
"xin24m" };
PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
-PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
-PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
+PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
+PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
@@ -502,7 +502,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
- MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
+ MUX(0, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
--
1.7.9.5
[PATCH 5/5] clk: rockchip: rk3228: export related MAC clocks
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3228.c | 22 +++---
include/dt-bindings/clock/rk3228-cru.h | 11 +++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 980d0da..db6e5a9 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -499,25 +499,25 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 0, GFLAGS),
- COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
+ COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
- MUX(0, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
+ MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
- MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
+ MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
- GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
+ GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 4, GFLAGS),
- GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
+ GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 3, GFLAGS),
- GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
+ GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 5, GFLAGS),
- GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
+ GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
RK2928_CLKGATE_CON(5), 6, GFLAGS),
- COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
+ COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
RK2928_CLKGATE_CON(5), 7, GFLAGS),
- COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
+ COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 2, GFLAGS),
@@ -551,7 +551,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
/* PD_PERI */
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(12), 0, GFLAGS),
- GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4,
GFLAGS),
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11),
0, GFLAGS),
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1,
GFLAGS),
@@ -567,7 +567,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[]
__initdata = {
GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14,
GFLAGS),
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(12), 1, GFLAGS),
- GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5,
GFLAGS),
GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(12), 2, GFLAGS),
/* PD_GPU */
diff --git a/include/dt-bindings/clock/rk3228-cru.h
b/include/dt-bindings/clock/rk3228-cru.h
index c992f3e..b27e2b1 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -52,6 +52,15 @@
#define SCLK_EMMC_SAMPLE 121
#define SCLK_VOP 122
#define SCLK_HDMI_HDCP 123
+#define SCLK_MAC_SRC 124
+#define SCLK_MAC_EXTCLK125
+#define SCLK_MAC 126
+#define SCLK_MAC_REFOUT127
+#define SCLK_MAC_REF 128
+#define SCLK_MAC_RX129
+#define SCLK_MAC_TX130
+#define SCLK_MAC_PHY 131
+#define SCLK_MAC_OUT 132
/* dclk gates */
#define DCLK_VOP 190
@@ -61,6 +70,7 @@
#define ACLK_DMAC 194
#define ACLK_PERI 210
#define ACLK_VOP 211
+#define ACLK_GMAC 212
/* pclk gates */
#define PCLK_GPIO0 320
@@ -82,6 +92,7 @@
#define PCLK_PERI 363
#define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365
+#define PCLK_GMAC 367
/* hclk gates */
#define HCLK_I2S0_8CH 442
--
1.7.9.5
[PATCH] net: stmmac: dwmac-rk: add rk322x-specific data
Add constants and callback functions for the dwmac on rk322x socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.
Signed-off-by: Xing Zheng
---
.../devicetree/bindings/net/rockchip-dwmac.txt |3 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 117
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 93eac7c..5040ed4 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,8 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
The device node has following properties.
Required properties:
- - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac"
+ - compatible: Can be one of "rockchip,rk322x-gmac", "rockchip,rk3288-gmac",
+ "rockchip,rk3368-gmac"
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 0cd3ecf..7f045db 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -72,6 +72,122 @@ struct rk_priv_data {
#define GRF_BIT(nr)(BIT(nr) | BIT(nr+16))
#define GRF_CLR_BIT(nr)(BIT(nr+16))
+#define RK322X_GRF_MAC_CON00x0900
+#define RK322X_GRF_MAC_CON10x0904
+
+/* RK322X_GRF_MAC_CON0 */
+#define RK322X_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK322X_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* RK322X_GRF_MAC_CON1 */
+#define RK322X_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK322X_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK322X_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK322X_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK322X_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define RK322X_GMAC_SPEED_100M GRF_BIT(2)
+#define RK322X_GMAC_RMII_CLK_25M GRF_BIT(7)
+#define RK322X_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
+#define RK322X_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
+#define RK322X_GMAC_CLK_25M(GRF_BIT(8) | GRF_BIT(9))
+#define RK322X_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
+#define RK322X_GMAC_RMII_MODE GRF_BIT(10)
+#define RK322X_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
+#define RK322X_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK322X_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RK322X_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK322X_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+
+static void rk322x_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON1,
+RK322X_GMAC_PHY_INTF_SEL_RGMII |
+RK322X_GMAC_RMII_MODE_CLR |
+RK322X_GMAC_RXCLK_DLY_ENABLE |
+RK322X_GMAC_TXCLK_DLY_ENABLE);
+
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON0,
+RK322X_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK322X_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk322x_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON1,
+RK322X_GMAC_PHY_INTF_SEL_RMII |
+RK322X_GMAC_RMII_MODE);
+
+ /* set MAC to RMII mode */
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON1, GRF_BIT(11));
+}
+
+static void rk322x_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON1,
+RK322X_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf, RK322X_GRF_MAC_CON1,
+RK322X_GMAC_CLK_25M);
+ else if (speed == 1000)
+ regmap_write(bsp_priv->
[PATCH 3/3] ARM: dts: rockchip: add support rk3229 evb board
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3229-evb.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d..5e0833f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -602,6 +602,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-rayeager.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
+ rk3229-evb.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
new file mode 100644
index 000..bb97de9
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -0,0 +1,90 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3228.dtsi"
+
+/ {
+ model = "Rockchip RK3229 Evaluation board";
+ compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
+ memory {
+ device_type = "memory";
+ reg = <0x6000 0x4000>;
+ };
+
+ ext_gmac: ext_gmac {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+ assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
1.7.9.5
[PATCH 1/3] ARM: dts: rockchip: add i2s nodes for RK3228 SoCs
This patch add the i2s dt nodes for rk3228 SoCs.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/rk3228.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e23a22e..e224147 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -239,6 +239,47 @@
status = "disabled";
};
+ i2s1: i2s1@100b {
+ compatible = "rockchip,rk3229-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100b 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ dmas = <&pdma 14>, <&pdma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_bus>;
+ status = "disabled";
+ };
+
+ i2s0: i2s0@100c {
+ compatible = "rockchip,rk3229-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100c 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ dmas = <&pdma 11>, <&pdma 12>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s2@100e {
+ compatible = "rockchip,rk3229-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100e 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
pwm0: pwm@110b {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b 0x10>;
@@ -509,6 +550,20 @@
};
};
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
+ <0 9 RK_FUNC_1 &pcfg_pull_none>,
+ <0 11 RK_FUNC_1
&pcfg_pull_none>,
+ <0 12 RK_FUNC_1
&pcfg_pull_none>,
+ <0 13 RK_FUNC_1
&pcfg_pull_none>,
+ <0 14 RK_FUNC_1
&pcfg_pull_none>,
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,
+ <1 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 21 RK_FUNC_1
&pcfg_pull_none>;
--
1.7.9.5
[PATCH 2/3] ARM: dts: rockchip: add GMAC nodes for RK3228 SoCs
This patch add the GMAC dt nodes for rk3228 SoCs.
Signed-off-by: Xing Zheng
---
arch/arm/boot/dts/rk3228.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e224147..4c0223c 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -417,6 +417,28 @@
status = "disabled";
};
+ gmac: eth@3020 {
+ compatible = "rockchip,rk322x-gmac";
+ reg = <0x3020 0x1>;
+ rockchip,grf = <&grf>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@3201 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -501,6 +523,10 @@
bias-disable;
};
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -522,6 +548,44 @@
};
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 22 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 23 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 9 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 21 RK_FUNC_2
&pcfg_pull_none>,
+ <2 20 RK_FUNC_2
&pcfg_pull_none>,
+ <2 11 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>,
+ <2 15 RK_FUNC_1
&pcfg_pull_none>;
+ };
+
+ phy_pins: phy-pins {
+ rockchip,pins = <2 14 RK_FUNC_2
&pcfg_pull_none>,
+ <2 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
[PATCH 0/3] Add i2s/gmac dts nodes for RK322x SoCs
Hi, These patchset add i2s/gmac dts nodes for RK322x SoCs, and add the new dts file of the rk3229 evb board. Thanks. Xing Zheng (3): ARM: dts: rockchip: add i2s nodes for RK3228 SoCs ARM: dts: rockchip: add GMAC nodes for RK3228 SoCs ARM: dts: rockchip: add support rk3229 evb board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3228.dtsi| 119 ++ arch/arm/boot/dts/rk3229-evb.dts | 90 3 files changed, 210 insertions(+) create mode 100644 arch/arm/boot/dts/rk3229-evb.dts -- 1.7.9.5
Re: [PATCH] net: stmmac: dwmac-rk: add rk322x-specific data
Hi Heiko, On 2016年06月21日 17:43, Heiko Stübner wrote: devicetree names are normally expected to be real, aka no "x" as catchall. So I guess either just add compatibles for both the rk3228 and rk3229 which point to the same structure in the driver. (So driver-side can stay as it is below, just add a second compatible). OK, I try to just use "rockchip,rk3228-gmac" to point to "rk322x_ops" which is the same structure in MAC driver, and both rk3228 and rk3229 use it. Thanks -- - Xing Zheng
[PATCH v2] net: stmmac: dwmac-rk: add rk3228-specific data
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Xing Zheng
---
Changes in v2:
- the "rk322x" is not clear to SoC decription, rename it to "rk3228"
.../devicetree/bindings/net/rockchip-dwmac.txt |3 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 117
2 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 93eac7c..cccd945 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -3,7 +3,8 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
The device node has following properties.
Required properties:
- - compatible: Can be one of "rockchip,rk3288-gmac", "rockchip,rk3368-gmac"
+ - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
+ "rockchip,rk3368-gmac"
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 0cd3ecf..25eb797 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -72,6 +72,122 @@ struct rk_priv_data {
#define GRF_BIT(nr)(BIT(nr) | BIT(nr+16))
#define GRF_CLR_BIT(nr)(BIT(nr+16))
+#define RK3228_GRF_MAC_CON00x0900
+#define RK3228_GRF_MAC_CON10x0904
+
+/* RK3228_GRF_MAC_CON0 */
+#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
+#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/* RK3228_GRF_MAC_CON1 */
+#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
+ (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3228_GMAC_PHY_INTF_SEL_RMII \
+ (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
+#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
+#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
+#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
+#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
+#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
+#define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
+#define RK3228_GMAC_CLK_25M(GRF_BIT(8) | GRF_BIT(9))
+#define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
+#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
+#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
+#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+
+static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+RK3228_GMAC_PHY_INTF_SEL_RGMII |
+RK3228_GMAC_RMII_MODE_CLR |
+RK3228_GMAC_RXCLK_DLY_ENABLE |
+RK3228_GMAC_TXCLK_DLY_ENABLE);
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
+RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+RK3228_GMAC_PHY_INTF_SEL_RMII |
+RK3228_GMAC_RMII_MODE);
+
+ /* set MAC to RMII mode */
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
+}
+
+static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "Missing rockchip,grf property\n");
+ return;
+ }
+
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+RK3228_GMAC_CLK_2_5M);
+ else if (speed == 100)
+ regmap_write(bsp_priv->grf,
Re: [PATCH 0/5] Fix and improve clock controller for the RK322x SoCs
Hi Heiko, On 2016年06月22日 07:07, Heiko Stuebner wrote: Am Dienstag, 21. Juni 2016, 12:53:26 schrieb Xing Zheng: Hi, These patchset fix some clocks bugs, and improve clock configuration for i2s/spdif/MAC on RK322x SoCs. applied to my clock-branch with the following changes: - fixed the error in patch1 - missing ")" in COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, - RK3288_CLKSEL_CON(7), 0, - RK3288_CLKGATE_CON(0), 11, GFLAGS), + RK2928_CLKSEL_CON(7), 0, + RK2928_CLKGATE_CON(0), 11, GFLAGS, - adapted patch2 accordingly - split out clock id addition into separate patches, as they need a shared branch. Xing please remember to add clock-ids to the header in separate patches. So sorry to miss it... OK, I will add clock-ids to the header in separate patches. Thanks. -- - Xing Zheng
[PATCH v2 2/4] ARM: dts: rockchip: add i2s nodes for RK322x SoCs
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index a68fdcaf..d5626705 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -237,6 +237,47 @@
status = "disabled";
};
+ i2s1: i2s1@100b {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100b 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ dmas = <&pdma 14>, <&pdma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_bus>;
+ status = "disabled";
+ };
+
+ i2s0: i2s0@100c {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100c 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ dmas = <&pdma 11>, <&pdma 12>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s2@100e {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100e 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
pwm0: pwm@110b {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b 0x10>;
@@ -507,6 +548,20 @@
};
};
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
+ <0 9 RK_FUNC_1 &pcfg_pull_none>,
+ <0 11 RK_FUNC_1
&pcfg_pull_none>,
+ <0 12 RK_FUNC_1
&pcfg_pull_none>,
+ <0 13 RK_FUNC_1
&pcfg_pull_none>,
+ <0 14 RK_FUNC_1
&pcfg_pull_none>,
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,
+ <1 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 21 RK_FUNC_1
&pcfg_pull_none>;
--
1.7.9.5
[PATCH v2 1/4] ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk3228.dtsi | 548 +-
arch/arm/boot/dts/rk322x.dtsi | 589 +
2 files changed, 590 insertions(+), 547 deletions(-)
create mode 100644 arch/arm/boot/dts/rk322x.dtsi
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e23a22e..e10f0b3 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -38,554 +38,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include
-#include
-#include
-#include
-#include
-#include
-#include "skeleton.dtsi"
+#include "rk322x.dtsi"
/ {
compatible = "rockchip,rk3228";
-
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHzuV */
-816000 100
- >;
- #cooling-cells = <2>; /* min followed by max */
- clock-latency = <4>;
- clocks = <&cru ARMCLK>;
- };
-
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- resets = <&cru SRST_CORE1>;
- };
-
- cpu2: cpu@f02 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf02>;
- resets = <&cru SRST_CORE2>;
- };
-
- cpu3: cpu@f03 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf03>;
- resets = <&cru SRST_CORE3>;
- };
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@110f {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x110f 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = ,
-,
-,
-;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- arm,cpu-registers-not-fw-configured;
- interrupts = ,
-,
-,
-;
- clock-frequency = <2400>;
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- grf: syscon@1100 {
- compatible = "syscon";
- reg = <0x1100 0x1000>;
- };
-
- uart0: serial@1101 {
- compatible = "snps,dw-apb-uart";
- reg = <0x1101 0x100>;
- interrupts = ;
- clock-frequency = <2400>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- reg-shift = <2
[PATCH v2 4/4] ARM: dts: rockchip: add support rk3229 evb board
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229.dtsi| 45 +++
3 files changed, 136 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3229-evb.dts
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d..5e0833f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -602,6 +602,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-rayeager.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
+ rk3229-evb.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
new file mode 100644
index 000..77a46c7
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -0,0 +1,90 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3229.dtsi"
+
+/ {
+ model = "Rockchip RK3229 Evaluation board";
+ compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
+ memory {
+ device_type = "memory";
+ reg = <0x6000 0x4000>;
+ };
+
+ ext_gmac: ext_gmac {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+ assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
new file mode 100644
index 000..35ca047
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229.dtsi
@@ -0,0 +1,45 @@
+/*
+ * This file is dual-licen
[PATCH v2 3/4] ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index d5626705..a9cbef9 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -415,6 +415,28 @@
status = "disabled";
};
+ gmac: eth@3020 {
+ compatible = "rockchip,rk3228-gmac";
+ reg = <0x3020 0x1>;
+ rockchip,grf = <&grf>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@3201 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -499,6 +521,10 @@
bias-disable;
};
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -520,6 +546,44 @@
};
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 22 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 23 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 9 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 21 RK_FUNC_2
&pcfg_pull_none>,
+ <2 20 RK_FUNC_2
&pcfg_pull_none>,
+ <2 11 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>,
+ <2 15 RK_FUNC_1
&pcfg_pull_none>;
+ };
+
+ phy_pins: phy-pins {
+ rockchip,pins = <2 14 RK_FUNC_2
&pcfg_pull_none>,
+ <2 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
[PATCH v2 0/4] Fix and add support i2s/spdif/gmac features for RK322x SoCs
Hi, We have the brother chipset product that RK3228 and RK3229, They have many common configuration, but there are a number of different features. In order to develop the future when they are easy to distinguish, we need them to be independent. And, these patchset add i2s/gmac dts nodes for RK322x SoCs, and add the new dts file of the rk3229 evb board. Thanks. Changes in v2: - rename rk3228.dtsi to rk322x.dtsi Xing Zheng (4): ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi ARM: dts: rockchip: add i2s nodes for RK322x SoCs ARM: dts: rockchip: add GMAC nodes for RK322x SoCs ARM: dts: rockchip: add support rk3229 evb board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3228.dtsi| 548 + arch/arm/boot/dts/rk3229-evb.dts | 90 + arch/arm/boot/dts/rk3229.dtsi| 45 +++ arch/arm/boot/dts/rk322x.dtsi| 708 ++ 5 files changed, 845 insertions(+), 547 deletions(-) create mode 100644 arch/arm/boot/dts/rk3229-evb.dts create mode 100644 arch/arm/boot/dts/rk3229.dtsi create mode 100644 arch/arm/boot/dts/rk322x.dtsi -- 1.7.9.5
[RESEND PATCH v2 2/4] ARM: dts: rockchip: add i2s nodes for RK322x SoCs
This patch add the i2s dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index a68fdcaf..d5626705 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -237,6 +237,47 @@
status = "disabled";
};
+ i2s1: i2s1@100b {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100b 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ dmas = <&pdma 14>, <&pdma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_bus>;
+ status = "disabled";
+ };
+
+ i2s0: i2s0@100c {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100c 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ dmas = <&pdma 11>, <&pdma 12>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s2@100e {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100e 0x4000>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
pwm0: pwm@110b {
compatible = "rockchip,rk3288-pwm";
reg = <0x110b 0x10>;
@@ -507,6 +548,20 @@
};
};
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
+ <0 9 RK_FUNC_1 &pcfg_pull_none>,
+ <0 11 RK_FUNC_1
&pcfg_pull_none>,
+ <0 12 RK_FUNC_1
&pcfg_pull_none>,
+ <0 13 RK_FUNC_1
&pcfg_pull_none>,
+ <0 14 RK_FUNC_1
&pcfg_pull_none>,
+ <1 2 RK_FUNC_1 &pcfg_pull_none>,
+ <1 4 RK_FUNC_1 &pcfg_pull_none>,
+ <1 5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <3 21 RK_FUNC_1
&pcfg_pull_none>;
--
1.7.9.5
[RESEND PATCH v2 1/4] ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk3228.dtsi | 548 +-
arch/arm/boot/dts/rk322x.dtsi | 589 +
2 files changed, 590 insertions(+), 547 deletions(-)
create mode 100644 arch/arm/boot/dts/rk322x.dtsi
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi
index e23a22e..e10f0b3 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk3228.dtsi
@@ -38,554 +38,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include
-#include
-#include
-#include
-#include
-#include
-#include "skeleton.dtsi"
+#include "rk322x.dtsi"
/ {
compatible = "rockchip,rk3228";
-
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHzuV */
-816000 100
- >;
- #cooling-cells = <2>; /* min followed by max */
- clock-latency = <4>;
- clocks = <&cru ARMCLK>;
- };
-
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- resets = <&cru SRST_CORE1>;
- };
-
- cpu2: cpu@f02 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf02>;
- resets = <&cru SRST_CORE2>;
- };
-
- cpu3: cpu@f03 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf03>;
- resets = <&cru SRST_CORE3>;
- };
- };
-
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@110f {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x110f 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = ,
-,
-,
-;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- arm,cpu-registers-not-fw-configured;
- interrupts = ,
-,
-,
-;
- clock-frequency = <2400>;
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <2400>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- grf: syscon@1100 {
- compatible = "syscon";
- reg = <0x1100 0x1000>;
- };
-
- uart0: serial@1101 {
- compatible = "snps,dw-apb-uart";
- reg = <0x1101 0x100>;
- interrupts = ;
- clock-frequency = <2400>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- reg-shift = <2
[RESEND PATCH v2 4/4] ARM: dts: rockchip: add support rk3229 evb board
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename rk3228.dtsi to rk322x.dtsi
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3229-evb.dts | 90 ++
arch/arm/boot/dts/rk3229.dtsi| 45 +++
3 files changed, 136 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3229-evb.dts
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 06b6c2d..5e0833f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -602,6 +602,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-rayeager.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
+ rk3229-evb.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
new file mode 100644
index 000..77a46c7
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -0,0 +1,90 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3229.dtsi"
+
+/ {
+ model = "Rockchip RK3229 Evaluation board";
+ compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
+ memory {
+ device_type = "memory";
+ reg = <0x6000 0x4000>;
+ };
+
+ ext_gmac: ext_gmac {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+ assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
new file mode 100644
index 000..35ca047
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229.dtsi
@@ -0,0 +1,45 @@
+/*
+ * This file is dual-licen
[RESEND PATCH v2 0/4] Add support i2s/spdif/gmac features for RK322x SoCs
Hi, We have the brother chipset product that RK3228 and RK3229, They have many common configuration, but there are a number of different features. In order to develop the future when they are easy to distinguish, we need them to be independent. And, these patchset add i2s/gmac dts nodes for RK322x SoCs, and add the new dts file of the rk3229 evb board. Thanks. Changes in v2: - rename rk3228.dtsi to rk322x.dtsi Xing Zheng (4): ARM: dts: rockchip: rename rk3228.dtsi to rk322x.dtsi ARM: dts: rockchip: add i2s nodes for RK322x SoCs ARM: dts: rockchip: add GMAC nodes for RK322x SoCs ARM: dts: rockchip: add support rk3229 evb board arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3228.dtsi| 548 + arch/arm/boot/dts/rk3229-evb.dts | 90 + arch/arm/boot/dts/rk3229.dtsi| 45 +++ arch/arm/boot/dts/rk322x.dtsi| 708 ++ 5 files changed, 845 insertions(+), 547 deletions(-) create mode 100644 arch/arm/boot/dts/rk3229-evb.dts create mode 100644 arch/arm/boot/dts/rk3229.dtsi create mode 100644 arch/arm/boot/dts/rk322x.dtsi -- 1.7.9.5
[RESEND PATCH v2 3/4] ARM: dts: rockchip: add GMAC nodes for RK322x SoCs
This patch add the GMAC dt nodes for rk322x SoCs.
Signed-off-by: Xing Zheng
---
Changes in v2: None
arch/arm/boot/dts/rk322x.dtsi | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index d5626705..a9cbef9 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -415,6 +415,28 @@
status = "disabled";
};
+ gmac: eth@3020 {
+ compatible = "rockchip,rk3228-gmac";
+ reg = <0x3020 0x1>;
+ rockchip,grf = <&grf>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@3201 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -499,6 +521,10 @@
bias-disable;
};
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -520,6 +546,44 @@
};
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 22 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 23 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 9 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 21 RK_FUNC_2
&pcfg_pull_none>,
+ <2 20 RK_FUNC_2
&pcfg_pull_none>,
+ <2 11 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <2 14 RK_FUNC_1
&pcfg_pull_none>,
+ <2 12 RK_FUNC_1
&pcfg_pull_none>,
+ <2 25 RK_FUNC_1
&pcfg_pull_none>,
+ <2 19 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 18 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 13 RK_FUNC_1
&pcfg_pull_none_drv_12ma>,
+ <2 17 RK_FUNC_1
&pcfg_pull_none>,
+ <2 16 RK_FUNC_1
&pcfg_pull_none>,
+ <2 8 RK_FUNC_1 &pcfg_pull_none>,
+ <2 15 RK_FUNC_1
&pcfg_pull_none>;
+ };
+
+ phy_pins: phy-pins {
+ rockchip,pins = <2 14 RK_FUNC_2
&pcfg_pull_none>,
+ <2 8 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
--
1.7.9.5
[PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 7425, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
--
1.7.9.5
[PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng --- include/dt-bindings/clock/rk3399-cru.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
[PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
1.7.9.5
[PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 4a15ce5b..3daa164 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco =
2967032965 */
+ RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco =
2967032970 */
+ RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco =
2967032960 */
+ RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0, 4194304), /* vco =
298200 */
+ RK3036_PLL_RATE( 7425, 1, 129, 7, 6, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco =
3115384608 */
+ RK3036_PLL_RATE( 6500, 1, 113, 7, 6, 0, 12582912), /* vco =
273000 */
+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco =
2907692291 */
+ RK3036_PLL_RATE( 5400, 1, 110, 7, 7, 0, 4194304), /* vco =
264600 */
+ RK3036_PLL_RATE( 2700, 1, 55, 7, 7, 0, 2097152), /* vco =
132300 */
+ RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco =
1321678323 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[]
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0,
RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0,
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_frates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
--
1.7.9.5
[PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Hi: In the development work, we found that some of the previous incorrect clock configuration on the RK3399 platform, we should fix and optimize them. Elaine Zhang (1): clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng (5): clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI clk: rockchip: rk3399: Add support frac mode frequencies drivers/clk/rockchip/clk-rk3399.c | 35 +--- include/dt-bindings/clock/rk3399-cru.h |2 ++ 2 files changed, 30 insertions(+), 7 deletions(-) -- 1.7.9.5
[PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(6), 12, GFLAGS),
- GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
--
1.7.9.5
[PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 74afec0..4a15ce5b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
- GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
- GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
--
1.7.9.5
[RESEND PATCH 4/6] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ad3860a..74afec0 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 7425, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
--
1.7.9.5
[RESEND PATCH 2/6] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
1.7.9.5
[RESEND PATCH 5/6] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 74afec0..4a15ce5b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
- GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
- GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
--
1.7.9.5
[RESEND PATCH 0/6] fix and optimize some clock configuration for the RK3399 platfom
Hi: In the development work, we found that some of the previous incorrect clock configuration on the RK3399 platform, we should fix and optimize them. Elaine Zhang (1): clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng (5): clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI clk: rockchip: rk3399: Add support frac mode frequencies drivers/clk/rockchip/clk-rk3399.c | 35 +--- include/dt-bindings/clock/rk3399-cru.h |2 ++ 2 files changed, 30 insertions(+), 7 deletions(-) -- 1.7.9.5
[RESEND PATCH 6/6] clk: rockchip: rk3399: Add support frac mode frequencies
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 4a15ce5b..3daa164 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco =
2967032965 */
+ RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco =
2967032970 */
+ RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco =
2967032960 */
+ RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0, 4194304), /* vco =
298200 */
+ RK3036_PLL_RATE( 7425, 1, 129, 7, 6, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco =
3115384608 */
+ RK3036_PLL_RATE( 6500, 1, 113, 7, 6, 0, 12582912), /* vco =
273000 */
+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco =
2907692291 */
+ RK3036_PLL_RATE( 5400, 1, 110, 7, 7, 0, 4194304), /* vco =
264600 */
+ RK3036_PLL_RATE( 2700, 1, 55, 7, 7, 0, 2097152), /* vco =
132300 */
+ RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco =
1321678323 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[]
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0,
RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0,
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_frates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
--
1.7.9.5
[RESEND PATCH 1/6] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng --- include/dt-bindings/clock/rk3399-cru.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
[RESEND PATCH 3/6] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..ad3860a 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(6), 12, GFLAGS),
- GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
--
1.7.9.5
[PATCH v2 0/7] fix and optimize some clock configuration for the RK3399 platfom
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (6):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
g}pll_aclk_perihp_src
clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
clk: rockchip: rk3399: Add support frac mode frequencies
drivers/clk/rockchip/clk-rk3399.c | 41
include/dt-bindings/clock/rk3399-cru.h |2 ++
2 files changed, 33 insertions(+), 10 deletions(-)
--
1.7.9.5
[PATCH v2 3/7] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src
There was a typo, swapping 'c' <--> 'g'.
And sorry to refer incorrect clock diagram, we double check it that
the bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by: Xing Zheng
Signed-off-by: Brian Norris
Reviewed-by: Douglas Anderson
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..8bf0d19 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,10 +832,10 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(13), 1, GFLAGS),
/* perihp */
- GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(5), 0, GFLAGS),
- GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+ GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
+ GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 2, GFLAGS),
--
1.7.9.5
[PATCH v2 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
1.7.9.5
[PATCH v2 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 8bf0d19..44e673e 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(6), 12, GFLAGS),
- GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
--
1.7.9.5
[PATCH v2 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng --- Changes in v2: None include/dt-bindings/clock/rk3399-cru.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
[PATCH v2 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 44e673e..580abf1 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 7425, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
--
1.7.9.5
[PATCH v2 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 580abf1..071eb96 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
- GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
- GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
--
1.7.9.5
[PATCH v2 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
drivers/clk/rockchip/clk-rk3399.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 071eb96..db8394b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco =
2967032965 */
+ RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco =
2967032970 */
+ RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco =
2967032960 */
+ RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0, 4194304), /* vco =
298200 */
+ RK3036_PLL_RATE( 7425, 1, 129, 7, 6, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco =
3115384608 */
+ RK3036_PLL_RATE( 6500, 1, 113, 7, 6, 0, 12582912), /* vco =
273000 */
+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco =
2907692291 */
+ RK3036_PLL_RATE( 5400, 1, 110, 7, 7, 0, 4194304), /* vco =
264600 */
+ RK3036_PLL_RATE( 2700, 1, 55, 7, 7, 0, 2097152), /* vco =
132300 */
+ RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco =
1321678323 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[]
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0,
RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0,
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_frates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
--
1.7.9.5
[RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src
There was a typo, swapping 'c' <--> 'g'.
(This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
Signed-off-by: Xing Zheng
Signed-off-by: Brian Norris
Reviewed-by: Douglas Anderson
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..2182391 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(13), 1, GFLAGS),
/* perihp */
- GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 0, GFLAGS),
- GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+ GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
--
1.7.9.5
[RESEND PATCH v2 2/8] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
Export these source clocks for usbphy.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
- GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+ GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m",
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
--
1.7.9.5
[RESEND PATCH v2 1/8] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
We export some clock IDs for the usb phy 480m source clocks. Signed-off-by: Xing Zheng --- Changes in v2: None include/dt-bindings/clock/rk3399-cru.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..c4d8311 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,8 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_USBPHY0_480M_SRC 168 +#define SCLK_USBPHY1_480M_SRC 169 #define DCLK_VOP0 180 #define DCLK_VOP1 181 -- 1.7.9.5
[RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.
Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
- add the patch "fix incorrect GATE bits for {c, g}pll_aclk_perihp_src"
Elaine Zhang (1):
clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
Xing Zheng (7):
clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
g}pll_aclk_perihp_src
clk: rockchip: rk3399: fix incorrect GATE bits for {c,
g}pll_aclk_perihp_src
clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
clk: rockchip: rk3399: Add support frac mode frequencies
drivers/clk/rockchip/clk-rk3399.c | 41
include/dt-bindings/clock/rk3399-cru.h |2 ++
2 files changed, 33 insertions(+), 10 deletions(-)
--
1.7.9.5
[RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src
Sorry to refer incorrect clock diagram, we double check it that the
bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 2182391..8bf0d19 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
/* perihp */
GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(5), 0, GFLAGS),
- GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
+ GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 2, GFLAGS),
--
1.7.9.5
Re: [PATCH 2/2] clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src
Hi Doug,
It is so sorry that our IC folks re-correct these bits, they need
to be recovered like these:
In the definition of CRU_CLKGATE_CON5:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
And the new TRM will be updated.
FYI.
Thanks.
On 2016年05月16日 23:49, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 8:36 PM, Xing Zheng wrote:
Hi Doug,
On 2016年05月14日 04:10, Doug Anderson wrote:
Hi,
On Fri, May 13, 2016 at 11:42 AM, Brian Norris
wrote:
From: Xing Zheng
There was a typo, swapping 'c' <--> 'g'.
Signed-off-by: Xing Zheng
Signed-off-by: Brian Norris
---
drivers/clk/rockchip/clk-rk3399.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 145756c4f3c8..9f86bfef70f7 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch
rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(13), 1, GFLAGS),
/* perihp */
- GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+ GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 0, GFLAGS),
- GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+ GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5,
DFLAGS,
Definitely there was a bug since this table itself was inconsistent.
...and I _think_ this fix is correct, but I'll note that the TRM has
more inconsistency here.
In the big clock table 'CRU Clock Architecture Diagram', I see:
CLK 4 is CPLL
CLK 5 is GPLL
CLK 125 is aclk_perihp_cpll_src and has 4 (CPLL) as source, with
g5[0] as the bit
CLK 126 is aclk_perihp_gpll_src and has 5 (GPLL) as source, with
g5[1] as the bit
In the definition of CRU_CLKGATE_CON5:
bit 0 shows aclk_perihp_gpll_src_en
bit 1 shows aclk_perihp_cpll_src_en
Thus the table shows CPLL as gate5[0] and GPLL as gate5[1]. The
register definition shows the opposite. I'll tend to believe the
table over the register definition, but I figured I'd bring it up
anyway.
Xing Zheng: can you confirm that the table is correct and ask
documentation folks to fix the register definition for
CRU_CLKGATE_CON5?
Yes, previously, our IC & DOC partner confirmed that the definition of
CRU_CLKGATE_CON5 should be:
bit 0 shows aclk_perihp_cpll_src_en
bit 1 shows aclk_perihp_gpll_src_en
Sorry to the incorrect register definition, we will fix them and review the
TRM again.
Great!
Since we now have extra confirmation that Brian's patch is indeed correct:
Reviewed-by: Douglas Anderson
--
- Xing Zheng
[RESEND PATCH v2 6/8] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 44e673e..580abf1 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 7425, 2, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE( 6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
--
1.7.9.5
[RESEND PATCH v2 5/8] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 8bf0d19..44e673e 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
- RK3399_CLKGATE_CON(6), 12, GFLAGS),
- GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+ GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+ RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p,
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
--
1.7.9.5
[RESEND PATCH v2 8/8] clk: rockchip: rk3399: Add support frac mode frequencies
We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.
Signed-off-by: Xing Zheng
---
Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
- add the patch "fix incorrect GATE bits for {c, g}pll_aclk_perihp_src"
drivers/clk/rockchip/clk-rk3399.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 071eb96..db8394b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] =
{
{ /* sentinel */ },
};
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco =
2967032965 */
+ RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912), /* vco =
297000 */
+ RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco =
2967032970 */
+ RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco =
2967032960 */
+ RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0, 4194304), /* vco =
298200 */
+ RK3036_PLL_RATE( 7425, 1, 129, 7, 6, 0, 15728640), /* vco =
311850 */
+ RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco =
3115384608 */
+ RK3036_PLL_RATE( 6500, 1, 113, 7, 6, 0, 12582912), /* vco =
273000 */
+ RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco =
2907692291 */
+ RK3036_PLL_RATE( 5400, 1, 110, 7, 7, 0, 4194304), /* vco =
264600 */
+ RK3036_PLL_RATE( 2700, 1, 55, 7, 7, 0, 2097152), /* vco =
132300 */
+ RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco =
1321678323 */
+ { /* sentinel */ },
+};
+
/* CRU parents */
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[]
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0,
RK3399_PLL_CON(40),
RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0,
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE,
rk3399_pll_frates),
};
static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
--
1.7.9.5
[RESEND PATCH v2 7/8] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie
From: Elaine Zhang
allow aclk_pcie and aclk_perf_pcie disabled when unused.
Signed-off-by: Elaine Zhang
Signed-off-by: Xing Zheng
---
Changes in v2: None
drivers/clk/rockchip/clk-rk3399.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index 580abf1..071eb96 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[]
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
- GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
- GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+ GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
--
1.7.9.5
[PATCH] ASoC: da7219: software reset codec at probe
From: Hsin-Yu Chao
On some platform da7219 codec has persistent power across reboot
so it doesn't reset and cause abnormal jack detection.
Workaround this issue by doing software reset at probe.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
sound/soc/codecs/da7219.c | 8
1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
+ /* Software reset codec. */
+ regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+ regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+ regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_da7219,
&da7219_dai, 1);
if (ret < 0) {
--
1.9.1
[PATCH v2] ASoC: da7219: software reset codec at probe
From: Hsin-Yu Chao
Da7219 does not trigger interrupt to report jack status
when system boots from warm reset because its power
remains on during warm reset.
Doing software reset at probe to handle this.
Signed-off-by: Hsin-Yu Chao
Signed-off-by: Xing Zheng
---
Changes in v2:
- change the commit message for more clear explain
sound/soc/codecs/da7219.c | 8
1 file changed, 8 insertions(+)
diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
+ /* Software reset codec. */
+ regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+ regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+ regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_da7219,
&da7219_dai, 1);
if (ret < 0) {
--
1.9.1
Re: [PATCH] clk: rockchip: add 2016M to big cpu clk rate table
Hi Shunqian,
On 2016年09月01日 07:06, Shunqian Zheng wrote:
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.
Signed-off-by: Shunqian Zheng
---
drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index ede6c47..a6a15c6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -375,6 +375,7 @@ static struct rockchip_cpuclk_rate_table
rk3399_cpuclkb_rates[] __initdata = {
RK3399_CPUCLKB_RATE(218400, 1, 11, 11),
RK3399_CPUCLKB_RATE(208800, 1, 10, 10),
RK3399_CPUCLKB_RATE(204000, 1, 10, 10),
+ RK3399_CPUCLKB_RATE(201600, 1, 9, 9),
RK3399_CPUCLKB_RATE(199200, 1, 9, 9),
RK3399_CPUCLKB_RATE(189600, 1, 9, 9),
RK3399_CPUCLKB_RATE(18, 1, 8, 8),
It looks good to me.
Reviewed-by: Xing Zheng
Thanks.
--
- Xing Zheng
Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
Hi Heiko, On 2016年08月05日 03:19, Heiko Stübner wrote: Hi Xing, Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng: We need to support various display resolutions for external display devices like HDMI/DP, the frac mode can help us to acquire almost any frequencies, and need higher VCOs to reduce clock jitters. Signed-off-by: Xing Zheng why does this need to be a separate rate array and cannot live in the general pll rate array? The plls are general purpose, so we shouldn't limit them arbitarily. Yes, I understand your mean. :-) I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present in both arrays but have different settings. As your patch description says that these settings reduce clock jitter, wouldn't the general frequencies also profit from merging these new values into the general rate array? and here are some of our ideas: "WIth the frac mode and higher VCO to reduce clock jitters" that suggestion is from IC designer. There are many and various kinds resolution and needed frequencies for external disaplay devices. For example, the DP needs: 3840x2160 533250KHz 3840x2160 297000KHz 3840x2160 296703KHz 2560x1440 241500KHz 1920x1080 148500KHz 1920x1080 148352KHz 1680x1050 146250KHz 1600x900 108000KHz 1280x1024 135000KHz 1280x1024 108000KHz ... and so on There some frequencies must be allocated with frac mode. We separate these frequencies that are only used for display (VPLL) from the general rate table, and put them to be classified into a frac mode table, we can reduce the frequency of the query time, the two rate tables will not interfere with each other. Because other PLLs don't need to assgin these various frequencies with frac mode. Thanks -- - Xing Zheng
Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
Hi Heiko, On 2016年08月05日 16:48, Heiko Stübner wrote: Hi Xing, Am Freitag, 5. August 2016, 10:26:57 schrieb Xing Zheng: On 2016年08月05日 03:19, Heiko Stübner wrote: Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng: We need to support various display resolutions for external display devices like HDMI/DP, the frac mode can help us to acquire almost any frequencies, and need higher VCOs to reduce clock jitters. Signed-off-by: Xing Zheng why does this need to be a separate rate array and cannot live in the general pll rate array? The plls are general purpose, so we shouldn't limit them arbitarily. Yes, I understand your mean. :-) I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present in both arrays but have different settings. As your patch description says that these settings reduce clock jitter, wouldn't the general frequencies also profit from merging these new values into the general rate array? and here are some of our ideas: "WIth the frac mode and higher VCO to reduce clock jitters" that suggestion is from IC designer. There are many and various kinds resolution and needed frequencies for external disaplay devices. For example, the DP needs: 3840x2160 533250KHz 3840x2160 297000KHz 3840x2160 296703KHz 2560x1440 241500KHz 1920x1080 148500KHz 1920x1080 148352KHz 1680x1050 146250KHz 1600x900 108000KHz 1280x1024 135000KHz 1280x1024 108000KHz ... and so on There some frequencies must be allocated with frac mode. We separate these frequencies that are only used for display (VPLL) from the general rate table, and put them to be classified into a frac mode table, we can reduce the frequency of the query time, the two rate tables will not interfere with each other. Because other PLLs don't need to assgin these various frequencies with frac mode. Hmm, you're adding 14 frequencies to that new table (4 or so of them duplicating existing frequencies). So even if the effective number of new frequencies goes from now 10 to 20, I don't think walking that table will take an excessive time longer than now. After the patch introducing the automatic rate calculation, the rate table we need to walk, will even get smaller. Other components might also profit from the updated standard frequencies with less jitter you're introducing here. And of course there is also the possibility somebody might want to build some rk3399 device without any graphics output at all [arm-server seem to be the new hype :-) ], so may want to use the vpll for something else completely. So I still don't see an argument why it needs to be a separate table, as I currently don't see a case were it will really hurt the other PLLs. Heiko Yes, sorry to this idea is not comprehensive. I will try to find a better way. Thanks for your comments. :-) -- - Xing Zheng
Re: [PATCH 2/3] dmaengine: pl330: enable burst mode by parsing dt
Hi Shawn, On 2016年08月05日 10:53, Shawn Lin wrote: Currently pl330 use single mode defaultly. But burst mode can improve efficiency of memory accessing. We couldn't enable it by defalut in case of breaking any Socs which don't support it. With burst mode supported, we could see the improvement significantly when tesing SPI transfer etc. default single mode [ 88.292550] spi write 65536*1 cost 32402us speed:2022KB/S After applied with burst mode(len 16) [ 17.625296] spi write 65536*1 cost 17830us speed:3675KB/S Cc: Huibin Hong Cc: Xing Zheng Signed-off-by: Shawn Lin --- Tested-by: Xing Zheng Thanks -- - Xing Zheng
Re: [PATCH 3/3] dmaengine: pl330: support transfer unaligned with (burst len * burst size)
Hi Shawn On 2016年08月05日 10:53, Shawn Lin wrote: Currently pl330 doesn't support transfer which doesn't align with burst len * burst size. This should be only for single mode. Let's allow it for busrt mode if available. e.g. transfers 0x10002 bytes: First loop 256*16*16=0x1, burst size is 1, burst length is 16. Then the second loop 2 bytes, burst size is 1, burst length is 1. f0041000:DMAMOV CCR 0xbc02f1 f0041006:DMAMOV SAR 0xdd6c f004100c:DMAMOV DAR 0xff1d0400 f0041012:DMALP_0 15 f0041014:DMALP_1 255 f0041016:DMAWFPB 12 f0041018:DMALDA f0041019:DMASTPB 12 f004101b:DMAFLUSHP 12 f004101d:DMALPENDA_1 bjmpto_7 f004101f:DMALPENDA_0 bjmpto_b f0041021:DMAMOV CCR 0x800201 f0041027:DMALP_1 1 f0041029:DMAWFPB 12 f004102b:DMALDA f004102c:DMASTPB 12 f004102e:DMAFLUSHP 12 f0041030:DMALPENDA_1 bjmpto_7 f0041032:DMASEV 0 f0041034:DMAEND Signed-off-by: Shawn Lin Tested-by: Xing Zheng Thanks. -- - Xing Zheng
[PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
- watchdog@ff84 {
+ watchdog@ff848000 {
compatible = "snps,dw-wdt";
- reg = <0x0 0xff84 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = ;
};
--
1.9.1
Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1
Hi Shawn,
On 2016年08月26日 17:41, Shawn Lin wrote:
On 2016/8/26 14:22, Xing Zheng wrote:
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.
Signed-off-by: Xing Zheng
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
- watchdog@ff84 {
+ watchdog@ff848000 {
Just a nit, should we mark this explicitly as "watchdog0" ?
I still need to look up for which wdt you are using.:)
Done.
Thanks.
compatible = "snps,dw-wdt";
- reg = <0x0 0xff84 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = ;
};
--
- Xing Zheng
[PATCH v2] arm64: dts: rockchip: fix the address map for WDT0 and WDT1
To rename "watchdog" to "watchdog0" explicitly for looking up.
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84
And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.
Signed-off-by: Xing Zheng
---
Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly
arch/arm64/boot/dts/rockchip/rk3399.dtsi |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..1e714a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
- watchdog@ff84 {
+ watchdog0@ff848000 {
compatible = "snps,dw-wdt";
- reg = <0x0 0xff84 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = ;
};
--
1.7.9.5
[PATCH v1 2/3] pinctrl: rockchip: add support for the rk3036
Many parts of pinctrl rk3036 are similar to rk2928's.
Signed-off-by: Xing Zheng
---
Changes in v1: None
drivers/pinctrl/pinctrl-rockchip.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index cc2843a..d06631d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2042,6 +2042,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
};
+static struct rockchip_pin_bank rk3036_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+};
+
+static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+ .pin_banks = rk3036_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .label = "RK3036-GPIO",
+ .type = RK2928,
+ .grf_mux_offset = 0xa8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -2160,6 +2175,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
.data = (void *)&rk2928_pin_ctrl },
+ { .compatible = "rockchip,rk3036-pinctrl",
+ .data = (void *)&rk3036_pin_ctrl },
{ .compatible = "rockchip,rk3066a-pinctrl",
.data = (void *)&rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
--
1.7.9.5
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[PATCH v1 0/3] Port and support rk3036 SoC platform
Hi, We need to support rk3036 soc platform via upstream, there are 3 parts for the initial release of minimum system: dts, pinctrl, and clock tree for rk3036, startup and run to init processs. Thanks. Changes in v1: Signed-off-by: Xing Zheng Xing Zheng (3): ARM: dts: rockchip: add core rk3036 dts pinctrl: rockchip: add support for the rk3036 clk: rockchip: add clock controller for rk3036 arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3036-sdk.dts | 362 + drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-pll.c | 247 ++- drivers/clk/rockchip/clk-rk3036.c | 539 drivers/clk/rockchip/clk.h | 30 ++ drivers/pinctrl/pinctrl-rockchip.c | 17 + include/dt-bindings/clock/rk3036-cru.h | 247 +++ 8 files changed, 1443 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts create mode 100644 drivers/clk/rockchip/clk-rk3036.c create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 3/3] clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume should be done
in clk-rk3036.c
---
Changes in v1:
Signed-off-by: Xing Zheng
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-pll.c | 247 ++-
drivers/clk/rockchip/clk-rk3036.c | 539
drivers/clk/rockchip/clk.h | 30 ++
include/dt-bindings/clock/rk3036-cru.h | 247 +++
5 files changed, 1063 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/rockchip/clk-rk3036.c
create mode 100644 include/dt-bindings/clock/rk3036-cru.h
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
obj-y += clk-mmc-phase.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-y += clk-rk3036.o
obj-y += clk-rk3188.o
obj-y += clk-rk3288.o
obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 96903ae..cf56826 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner
*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -48,6 +51,8 @@ struct rockchip_clk_pll {
#define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll);
+
static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
struct rockchip_clk_pll *pll, unsigned long rate)
{
@@ -90,6 +95,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll
*pll)
unsigned int val;
int delay = 2400, ret;
+ /* the plls of rk3036 wait lock */
+ if (pll->type == pll_rk3036 || pll->lock_offset == -1) {
+ return rockchip_rk3036_pll_wait_lock(pll);
+ }
+
while (delay > 0) {
ret = regmap_read(grf, pll->lock_offset, &val);
if (ret) {
@@ -305,6 +315,235 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw)
rockchip_rk3066_pll_set_rate(hw, drate, prate);
}
}
+/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
+
+#define RK3036_PLLCON(i) (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK 0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
+#define RK3036_PLLCON1_DSMPD_MASK 0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK 0xff
+#define RK3036_PLLCON2_FRAC_SHIFT 0
+
+#define RK3036_MODECON 0x40
+#define RK3036_MODECON_AWM (1 << 0) /* apll work mode */
+
+#define RK3036_PLLCON0_BYPASS (1 << 15)
+#define RK3036_PLLCON1_LOCK_STATUS (1 << 10)
+#define RK3036_PLLCON1_RESET (1 << 14)
+
+static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
+{
+ u32 pllcon;
+ int delay = 2400;
+
+ /* poll check the lock status in rk3036 xPLLCON1 */
+ while (delay > 0) {
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
+ if (pllcon & RK3036_PLLCON1_LOCK_STATUS)
+ return 0;
+
+ delay--;
+ }
+
+ pr_err("%s: timeout waiting for pll to lock\n", __func__);
+ return -ETIMEDOUT;
+}
+
+static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+unsigned long prate)
+{
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;
+ u64 rate64 = prate;
+ u32 pllcon;
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
+ fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) &
RK3036_PLLCON0_FBDIV_MASK);
+ postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) &
RK3036_PLLCON0_POSTDIV1_MASK);
+
+ pllcon = readl_relaxed(pll->
[PATCH v1 1/3] ARM: dts: rockchip: add core rk3036 dts
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
---
Changes in v1: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-sdk.dts | 362 ++
2 files changed, 363 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6d7cec1..7014a3b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -501,6 +501,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
+ rk3036-sdk.dtb \
rk3188-radxarock.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts
new file mode 100644
index 000..0149c9a
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -0,0 +1,362 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "rockchip,rk3036";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ reg = <0x6000 0x4000>;
+ };
+
+arm-pmu {
+compatible = "arm,cortex-a7-pmu";
+interrupts = ,
+ ;
+};
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ //enable-method = "rockchip,rk3066-smp";
+
+ cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ operating-points = <
+ /* KHzuV */
+816000 100
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <4>;
+ clocks = <&cru ARMCLK>;
+ resets = <&cru SRST_CORE0>;
+ };
+ cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ resets = <&cru SRST_CORE1>;
+ };
+ };
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+pdma: pdma@20078000 {
+compatible = "arm,pl330", "arm,primecell";
+reg = <
Re: [PATCH v1 0/3] Port and support rk3036 SoC platform
HI Heiko, Thank you for your reply. I will improve them as quickly as possible. Thanks. :) On 2015年08月28日 17:59, Heiko Stuebner wrote: Hi, Am Freitag, 28. August 2015, 13:46:45 schrieb Xing Zheng: We need to support rk3036 soc platform via upstream, there are 3 parts for the initial release of minimum system: dts, pinctrl, and clock tree for rk3036, startup and run to init processs. this is really cool that you're working on supporting the rk3036. I had some comments to the individual patches, but overall it looks quite nice already. So, thanks for working on this Heiko -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/8] Build and support rk3036 SoC platform
Hi, We need to support rk3036 soc platform via upstream, there are 3 primary parts for the initial release of minimum system: dts, pinctrl, and clock tree for rk3036, and additional, we can use these startup and run to init processs. Thanks. Changed in v4: - add some basic IP modules on rk3036.dtsi - optimized supporting smp codes Changed in v3: - optimized some codes based on v2 - removed the patch "initial set time for rtc-hym8563" (useless) - removed the patch "pinctrl" (approved) Changed in v2: - based on v1, add clock controller documentation - enable timer5 startup - add smp for cpu1 - initial set time for rtc-hym8563 Changes in v1: - add dts, pinctrl and clock tree for rk3036 soc platform The patchset (8): 8) rockchip: make sure timer5 is enabled on rk3036 platforms 7) ARM: dts: enable smp for rk3036 6) ARM: rockchip: add support smp for rk3036 5) ARM: dts: rockchip: add core rk3036 dts 4) clk: rockchip: add new pll-type for rk3036 and similar socs 3) clk: rockchip: add clock controller for rk3036 2) clk: rockchip: add dt-binding header for rk3036 1) dt-bindings: add documentation of rk3036 clock controller Changes in v4: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Heiko Stuebner (1): ARM: rockchip: add support smp for rk3036 Xing Zheng (7): dt-bindings: add documentation of rk3036 clock controller clk: rockchip: add dt-binding header for rk3036 clk: rockchip: add clock controller for rk3036 clk: rockchip: add new pll-type for rk3036 and similar socs ARM: dts: rockchip: add core rk3036 dts ARM: dts: enable smp for rk3036 rockchip: make sure timer5 is enabled on rk3036 platforms Documentation/devicetree/bindings/arm/cpus.txt |1 + .../bindings/clock/rockchip,rk3036-cru.txt | 56 ++ arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3036-evb.dts | 64 +++ arch/arm/boot/dts/rk3036.dtsi | 541 arch/arm/mach-rockchip/platsmp.c | 45 +- arch/arm/mach-rockchip/rockchip.c | 44 +- drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-pll.c | 243 - drivers/clk/rockchip/clk-rk3036.c | 500 ++ drivers/clk/rockchip/clk.h | 30 ++ include/dt-bindings/clock/rk3036-cru.h | 195 +++ 12 files changed, 1691 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt create mode 100644 arch/arm/boot/dts/rk3036-evb.dts create mode 100644 arch/arm/boot/dts/rk3036.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3036.c create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/8] clk: rockchip: add dt-binding header for rk3036
Add the dt-bindings header for the rk3036, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v4: None include/dt-bindings/clock/rk3036-cru.h | 195 1 file changed, 195 insertions(+) create mode 100644 include/dt-bindings/clock/rk3036-cru.h diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 000..b0da216 --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER085 +#define SCLK_TIMER186 +#define SCLK_TIMER287 +#define SCLK_TIMER388 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS(HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG13 +#define SRST_STRC_SYS_A14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER216 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER320 +#define SRST_INTMEM21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER027 +#define SRST_TIMER128 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P
[PATCH v4 4/8] clk: rockchip: add new pll-type for rk3036 and similar socs
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
drivers/clk/rockchip/clk-pll.c | 243 +++-
1 file changed, 242 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4881eb8..a435503 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner
*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@
#include
#include
#include
+#include
#include "clk.h"
#define PLL_MODE_MASK 0x3
@@ -108,6 +112,237 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll
*pll)
}
/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLLCON(i) (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK 0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
+#define RK3036_PLLCON1_DSMPD_MASK 0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK 0xff
+#define RK3036_PLLCON2_FRAC_SHIFT 0
+
+#define RK3036_PLLCON1_PWRDOWN (1 << 13)
+
+static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+unsigned long prate)
+{
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ unsigned int fbdiv, postdiv1, refdiv, postdiv2, dsmpd, frac;
+ u64 rate64 = prate;
+ u32 pllcon;
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
+ fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) &
RK3036_PLLCON0_FBDIV_MASK);
+ postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) &
RK3036_PLLCON0_POSTDIV1_MASK);
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
+ refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) &
RK3036_PLLCON1_REFDIV_MASK);
+ postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) &
RK3036_PLLCON1_POSTDIV2_MASK);
+ dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) &
RK3036_PLLCON1_DSMPD_MASK);
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
+ frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) &
RK3036_PLLCON2_FRAC_MASK);
+
+ rate64 *= fbdiv;
+ do_div(rate64, refdiv);
+
+ if (dsmpd == 0) {
+ /* fractional mode */
+ u64 frac_rate64 = prate * frac;
+
+ do_div(frac_rate64, refdiv);
+ rate64 += frac_rate64 >> 24;
+ }
+
+ do_div(rate64, postdiv1);
+ do_div(rate64, postdiv2);
+
+ return (unsigned long)rate64;
+}
+
+static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long prate)
+{
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ const struct rockchip_pll_rate_table *rate;
+ unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
+ struct regmap *grf = rockchip_clk_get_grf();
+ struct clk_mux *pll_mux = &pll->pll_mux;
+ const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
+ u32 pllcon;
+ int rate_change_remuxed = 0;
+ int cur_parent;
+ int ret;
+
+ if (IS_ERR(grf)) {
+ pr_debug("%s: grf regmap not available, aborting rate change\n",
+__func__);
+ return PTR_ERR(grf);
+ }
+
+ pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
+__func__, __clk_get_name(hw->clk), old_rate, drate, prate);
+
+ /* Get required rate settings from table */
+ rate = rockchip_get_pll_settings(pll, drate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+ drate, __clk_get_name(hw->clk));
+ return -EINVAL;
+ }
+
+ pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv:
%d, postdiv2: %d, dsmpd: %d, frac: %d\n",
+
[PATCH v4 3/8] clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 500 +
drivers/clk/rockchip/clk.h| 30 +++
3 files changed, 531 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk3036.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
obj-y += clk-mmc-phase.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-y += clk-rk3036.o
obj-y += clk-rk3188.o
obj-y += clk-rk3288.o
obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000..6f49df3
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3036_GRF_SOC_STATUS0 0x14c
+
+enum rk3036_plls {
+ apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+ RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT 8
+
+#define RK3036_DIV_PERI_MASK 0xf
+#define RK3036_DIV_PERI_SHIFT 0
+#define RK3036_DIV_ACLK_MASK 0x7
+#define RK3036_DIV_ACLK_SHIFT 4
+#define RK3036_DIV_HCLK_MASK 0x3
+#define RK3036_DIV_HCLK_SHIFT 8
+#define RK3036_DIV_PCLK_MASK 0x7
+#define RK3036_DIV_PCLK_SHIFT 12
+
+#define RK3036_CLKSEL1(_core_periph_div)
\
+ {
\
+ .reg = RK2928_
[PATCH v4 1/8] dt-bindings: add documentation of rk3036 clock controller
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+ cru: cru@2000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x2000 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@2006 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2006 0x100>;
+ interrupts = ;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>;
+ };
--
1.7.9.5
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[PATCH v4 5/8] ARM: dts: rockchip: add core rk3036 dts
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/arm/boot/dts/rk3036.dtsi| 536 ++
3 files changed, 601 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
create mode 100644 arch/arm/boot/dts/rk3036.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7d3e495..3e4e089 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -510,6 +510,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+ model = "Rockchip RK3036 Evaluation board";
+ compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..8f3a069
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,536 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen
[PATCH v4 6/8] ARM: rockchip: add support smp for rk3036
From: Heiko Stuebner
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner
Tested-by: Xing Zheng
Signed-off-by: Xing Zheng
---
Changes in v4: None
Documentation/devicetree/bindings/arm/cpus.txt |1 +
arch/arm/mach-rockchip/platsmp.c | 45 +---
2 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..261cc27 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -198,6 +198,7 @@ nodes to be present and contain the properties described
below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+ "rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 3e7a4b7..5c138f9 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -42,6 +42,7 @@ static int ncores;
#define PMU_PWRDN_SCU 4
static struct regmap *pmu;
+static int has_pmu = true;
static int pmu_power_domain_is_on(int pd)
{
@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
- ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
- if (ret < 0) {
- pr_err("%s: could not update power domain\n", __func__);
- return ret;
- }
-
- ret = -1;
- while (ret != on) {
- ret = pmu_power_domain_is_on(pd);
+ if (has_pmu) {
+ ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
- pr_err("%s: could not read power domain state\n",
+ pr_err("%s: could not update power domain\n",
__func__);
return ret;
}
+
+ ret = -1;
+ while (ret != on) {
+ ret = pmu_power_domain_is_on(pd);
+ if (ret < 0) {
+ pr_err("%s: could not read power domain
state\n",
+ __func__);
+ return ret;
+ }
+ }
}
if (!IS_ERR(rstc)) {
@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct
task_struct *idle)
{
int ret;
- if (!sram_base_addr || !pmu) {
+ if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int
max_cpus)
return;
}
- if (rockchip_smp_prepare_pmu())
+ if (has_pmu && rockchip_smp_prepare_pmu())
return;
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int
max_cpus)
pmu_set_power_domain(0 + i, false);
}
+static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
+{
+ has_pmu = false;
+
+ rockchip_smp_prepare_cpus(max_cpus);
+}
+
#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
}
#endif
+static struct smp_operations rk3036_smp_ops __initdata = {
+ .smp_prepare_cpus = rk3036_smp_prepare_cpus,
+ .smp_boot_secondary = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_kill = rockchip_cpu_kill,
+ .cpu_die= rockchip_cpu_die,
+#endif
+};
+
static struct smp_operations rockchip_smp_ops __initdata = {
.smp_prepare_cpus = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
#endif
};
+CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
[PATCH v4 7/8] ARM: dts: enable smp for rk3036
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v4: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 8f3a069..61352be 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -72,6 +72,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "rockchip,rk3036-smp";
cpu0: cpu@f00 {
device_type = "cpu";
@@ -146,6 +147,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+ smp-sram@0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x00 0x10>;
+ };
};
cru: clock-controller@2000 {
--
1.7.9.5
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[PATCH v4 8/8] rockchip: make sure timer5 is enabled on rk3036 platforms
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v4:
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
arch/arm/mach-rockchip/rockchip.c | 44 +++--
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-rockchip/rockchip.c
b/arch/arm/mach-rockchip/rockchip.c
index 251c7b9..608b31c 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,31 +29,38 @@
#include "core.h"
#include "pm.h"
+#define RK3036_TIMER_PHYS 0x20044000
+
#define RK3288_GRF_SOC_CON0 0x244
#define RK3288_TIMER6_7_PHYS 0xff81
+static void rockchip_init_arch_timer_supply(resource_size_t phys, int offs)
+{
+ void __iomem *reg_base = ioremap(phys, SZ_16K);
+
+ /*
+* Most/all uboot versions for Rockchip SoCs don't enable
+* timer which is needed for the architected timer to work.
+* So make sure it is running during early boot.
+*/
+ if (reg_base) {
+ writel(0, reg_base + offs + 0x10);
+ writel(0x, reg_base + offs);
+ writel(0x, reg_base + offs + 0x04);
+ writel(1, reg_base + offs + 0x10);
+ dsb();
+ iounmap(reg_base);
+ } else {
+ pr_err("rockchip: could not map timer registers\n");
+ }
+}
+
static void __init rockchip_timer_init(void)
{
if (of_machine_is_compatible("rockchip,rk3288")) {
struct regmap *grf;
- void __iomem *reg_base;
- /*
-* Most/all uboot versions for rk3288 don't enable timer7
-* which is needed for the architected timer to work.
-* So make sure it is running during early boot.
-*/
- reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
- if (reg_base) {
- writel(0, reg_base + 0x30);
- writel(0x, reg_base + 0x20);
- writel(0x, reg_base + 0x24);
- writel(1, reg_base + 0x30);
- dsb();
- iounmap(reg_base);
- } else {
- pr_err("rockchip: could not map timer7 registers\n");
- }
+ rockchip_init_arch_timer_supply(RK3288_TIMER6_7_PHYS, 0x20);
/*
* Disable auto jtag/sdmmc switching that causes issues
@@ -64,6 +71,8 @@ static void __init rockchip_timer_init(void)
regmap_write(grf, RK3288_GRF_SOC_CON0, 0x1000);
else
pr_err("rockchip: could not get grf syscon\n");
+ } else if (of_machine_is_compatible("rockchip,rk3036")) {
+ rockchip_init_arch_timer_supply(RK3036_TIMER_PHYS, 0xa0);
}
of_clk_init(NULL);
@@ -79,6 +88,7 @@ static void __init rockchip_dt_init(void)
static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk2928",
+ "rockchip,rk3036",
"rockchip,rk3066a",
"rockchip,rk3066b",
"rockchip,rk3188",
--
1.7.9.5
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[PATCH v5 1/8] dt-bindings: add documentation of rk3036 clock controller
Add the devicetree binding for the cru on the rk3036 which quite similar
structured as previous clock controllers.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000..ace0599
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
+* Rockchip RK3036 Clock and Reset Unit
+
+The RK3036 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3036-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+ cru: cru@2000 {
+ compatible = "rockchip,rk3036-cru";
+ reg = <0x2000 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@2006 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2006 0x100>;
+ interrupts = ;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>;
+ };
--
1.7.9.5
--
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[PATCH v5 4/8] clk: rockchip: add new pll-type for rk3036 and similar socs
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
drivers/clk/rockchip/clk-pll.c | 249 +++-
1 file changed, 248 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4881eb8..83ba1e9 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner
*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@
#include
#include
#include
+#include
#include "clk.h"
#define PLL_MODE_MASK 0x3
@@ -108,6 +112,243 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll
*pll)
}
/**
+ * PLL used in RK3036
+ */
+
+#define RK3036_PLLCON(i) (i * 0x4)
+#define RK3036_PLLCON0_FBDIV_MASK 0xfff
+#define RK3036_PLLCON0_FBDIV_SHIFT 0
+#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
+#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
+#define RK3036_PLLCON1_REFDIV_MASK 0x3f
+#define RK3036_PLLCON1_REFDIV_SHIFT0
+#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
+#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
+#define RK3036_PLLCON1_DSMPD_MASK 0x1
+#define RK3036_PLLCON1_DSMPD_SHIFT 12
+#define RK3036_PLLCON2_FRAC_MASK 0xff
+#define RK3036_PLLCON2_FRAC_SHIFT 0
+
+#define RK3036_PLLCON1_PWRDOWN (1 << 13)
+
+static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
+ struct rockchip_pll_rate_table *rate)
+{
+ u32 pllcon;
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
+ rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) &
RK3036_PLLCON0_FBDIV_MASK);
+ rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) &
RK3036_PLLCON0_POSTDIV1_MASK);
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
+ rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) &
RK3036_PLLCON1_REFDIV_MASK);
+ rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) &
RK3036_PLLCON1_POSTDIV2_MASK);
+ rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) &
RK3036_PLLCON1_DSMPD_MASK);
+
+ pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
+ rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) &
RK3036_PLLCON2_FRAC_MASK);
+}
+
+static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+unsigned long prate)
+{
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ struct rockchip_pll_rate_table cur;
+ u64 rate64 = prate;
+
+ rockchip_rk3036_pll_get_params(pll, &cur);
+
+ rate64 *= cur.fbdiv;
+ do_div(rate64, cur.refdiv);
+
+ if (cur.dsmpd == 0) {
+ /* fractional mode */
+ u64 frac_rate64 = prate * cur.frac;
+
+ do_div(frac_rate64, cur.refdiv);
+ rate64 += frac_rate64 >> 24;
+ }
+
+ do_div(rate64, cur.postdiv1);
+ do_div(rate64, cur.postdiv2);
+
+ return (unsigned long)rate64;
+}
+
+static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
+ const struct rockchip_pll_rate_table *rate)
+{
+ const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
+ struct clk_mux *pll_mux = &pll->pll_mux;
+ struct rockchip_pll_rate_table cur;
+ u32 pllcon;
+ int rate_change_remuxed = 0;
+ int cur_parent;
+ int ret;
+
+ pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv:
%d, postdiv2: %d, dsmpd: %d, frac: %d\n",
+ __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
+ rate->postdiv2, rate->dsmpd, rate->frac);
+
+ rockchip_rk3036_pll_get_params(pll, &cur);
+ cur.rate = 0;
+
+ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
+ if (cur_parent == PLL_MODE_NORM) {
+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
+ rate_change_remuxed = 1;
+ }
+
+ /* update pll values */
+ writel_relaxed(HIWORD_UPDATE(rate->fb
[PATCH v5 0/8] Build and support rk3036 SoC platform
Hi, We need to support rk3036 soc platform via upstream, there are 3 primary parts for the initial release of minimum system: dts, pinctrl, and clock tree for rk3036, and additional, we can use these startup and run to init processs. Thanks. Changed in v5: - don't use clk_ APIs in the pll init-callback Changed in v4: - add some basic IP modules on rk3036.dtsi - optimized supporting smp codes Changed in v3: - optimized some codes based on v2 - removed the patch "initial set time for rtc-hym8563" (useless) - removed the patch "pinctrl" (approved) Changed in v2: - based on v1, add clock controller documentation - enable timer5 startup - add smp for cpu1 - initial set time for rtc-hym8563 Changes in v1: - add dts, pinctrl and clock tree for rk3036 soc platform The patchset (8): 8) rockchip: make sure timer5 is enabled on rk3036 platforms 7) ARM: dts: enable smp for rk3036 6) ARM: rockchip: add support smp for rk3036 5) ARM: dts: rockchip: add core rk3036 dts 4) clk: rockchip: add new pll-type for rk3036 and similar socs 3) clk: rockchip: add clock controller for rk3036 2) clk: rockchip: add dt-binding header for rk3036 1) dt-bindings: add documentation of rk3036 clock controller Changes in v5: Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner Heiko Stuebner (1): ARM: rockchip: add support smp for rk3036 Xing Zheng (7): dt-bindings: add documentation of rk3036 clock controller clk: rockchip: add dt-binding header for rk3036 clk: rockchip: add clock controller for rk3036 clk: rockchip: add new pll-type for rk3036 and similar socs ARM: dts: rockchip: add core rk3036 dts ARM: dts: enable smp for rk3036 rockchip: make sure timer5 is enabled on rk3036 platforms Documentation/devicetree/bindings/arm/cpus.txt |1 + .../bindings/clock/rockchip,rk3036-cru.txt | 56 ++ arch/arm/boot/dts/Makefile |1 + arch/arm/boot/dts/rk3036-evb.dts | 64 +++ arch/arm/boot/dts/rk3036.dtsi | 541 arch/arm/mach-rockchip/platsmp.c | 45 +- arch/arm/mach-rockchip/rockchip.c | 44 +- drivers/clk/rockchip/Makefile |1 + drivers/clk/rockchip/clk-pll.c | 249 - drivers/clk/rockchip/clk-rk3036.c | 500 ++ drivers/clk/rockchip/clk.h | 30 ++ include/dt-bindings/clock/rk3036-cru.h | 195 +++ 12 files changed, 1697 insertions(+), 30 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt create mode 100644 arch/arm/boot/dts/rk3036-evb.dts create mode 100644 arch/arm/boot/dts/rk3036.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3036.c create mode 100644 include/dt-bindings/clock/rk3036-cru.h -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 3/8] clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 500 +
drivers/clk/rockchip/clk.h| 30 +++
3 files changed, 531 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rk3036.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6..d599829 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o
obj-y += clk-mmc-phase.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-y += clk-rk3036.o
obj-y += clk-rk3188.o
obj-y += clk-rk3288.o
obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000..6f49df3
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,500 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner
+ *
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Xing Zheng
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "clk.h"
+
+#define RK3036_GRF_SOC_STATUS0 0x14c
+
+enum rk3036_plls {
+ apll, dpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(160800, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(158400, 1, 66, 1, 1, 1, 0),
+ RK3036_PLL_RATE(156000, 1, 65, 1, 1, 1, 0),
+ RK3036_PLL_RATE(153600, 1, 64, 1, 1, 1, 0),
+ RK3036_PLL_RATE(151200, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(148800, 1, 62, 1, 1, 1, 0),
+ RK3036_PLL_RATE(146400, 1, 61, 1, 1, 1, 0),
+ RK3036_PLL_RATE(144000, 1, 60, 1, 1, 1, 0),
+ RK3036_PLL_RATE(141600, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(139200, 1, 58, 1, 1, 1, 0),
+ RK3036_PLL_RATE(136800, 1, 57, 1, 1, 1, 0),
+ RK3036_PLL_RATE(134400, 1, 56, 1, 1, 1, 0),
+ RK3036_PLL_RATE(132000, 1, 55, 1, 1, 1, 0),
+ RK3036_PLL_RATE(129600, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(127200, 1, 53, 1, 1, 1, 0),
+ RK3036_PLL_RATE(124800, 1, 52, 1, 1, 1, 0),
+ RK3036_PLL_RATE(12, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(118800, 2, 99, 1, 1, 1, 0),
+ RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
+ RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
+ RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 91200, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 9, 4, 300, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 88800, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 59400, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
+ RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 31200, 1, 52, 2, 2, 1, 0),
+ RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE( 9600, 1, 64, 4, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RK3036_DIV_CPU_MASK0x1f
+#define RK3036_DIV_CPU_SHIFT 8
+
+#define RK3036_DIV_PERI_MASK 0xf
+#define RK3036_DIV_PERI_SHIFT 0
+#define RK3036_DIV_ACLK_MASK 0x7
+#define RK3036_DIV_ACLK_SHIFT 4
+#define RK3036_DIV_HCLK_MASK 0x3
+#define RK3036_DIV_HCLK_SHIFT 8
+#define RK3036_DIV_PCLK_MASK 0x7
+#define RK3036_DIV_PCLK_SHIFT 12
+
+#define RK3036_CLKSEL1(_core_periph_div)
\
+ {
\
+ .reg = RK2928_
[PATCH v5 2/8] clk: rockchip: add dt-binding header for rk3036
Add the dt-bindings header for the rk3036, that gets shared between the clock controller and the clock references in the dts. Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v5: None include/dt-bindings/clock/rk3036-cru.h | 195 1 file changed, 195 insertions(+) create mode 100644 include/dt-bindings/clock/rk3036-cru.h diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h new file mode 100644 index 000..b0da216 --- /dev/null +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Xing Zheng + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER085 +#define SCLK_TIMER186 +#define SCLK_TIMER287 +#define SCLK_TIMER388 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF152 +#define SCLK_SFC 160 + +#define DCLK_LCDC 190 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS(HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG13 +#define SRST_STRC_SYS_A14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER216 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER320 +#define SRST_INTMEM21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER027 +#define SRST_TIMER128 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P
[PATCH v5 5/8] ARM: dts: rockchip: add core rk3036 dts
Initial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
arch/arm/boot/dts/Makefile |1 +
arch/arm/boot/dts/rk3036-evb.dts | 64 +
arch/arm/boot/dts/rk3036.dtsi| 536 ++
3 files changed, 601 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3036-evb.dts
create mode 100644 arch/arm/boot/dts/rk3036.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7d3e495..3e4e089 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -510,6 +510,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk3036-evb.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-rayeager.dtb \
diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts
new file mode 100644
index 000..28a0336
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036-evb.dts
@@ -0,0 +1,64 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3036.dtsi"
+
+/ {
+ model = "Rockchip RK3036 Evaluation board";
+ compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
+};
+
+&i2c1 {
+ status = "okay";
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
new file mode 100644
index 000..8f3a069
--- /dev/null
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -0,0 +1,536 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicen
[PATCH v5 6/8] ARM: rockchip: add support smp for rk3036
From: Heiko Stuebner
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow
to control the actual powerdomain of the cpu cores, while the rest of the
smp-bringup like reset control and entry address handling stays the same.
Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply
disables powerdomain handling in the common code.
Signed-off-by: Heiko Stuebner
Tested-by: Xing Zheng
Signed-off-by: Xing Zheng
---
Changes in v5: None
Documentation/devicetree/bindings/arm/cpus.txt |1 +
arch/arm/mach-rockchip/platsmp.c | 45 +---
2 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/devicetree/bindings/arm/cpus.txt
index 91e6e5c..261cc27 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -198,6 +198,7 @@ nodes to be present and contain the properties described
below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
+ "rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 3e7a4b7..5c138f9 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -42,6 +42,7 @@ static int ncores;
#define PMU_PWRDN_SCU 4
static struct regmap *pmu;
+static int has_pmu = true;
static int pmu_power_domain_is_on(int pd)
{
@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)
if (!IS_ERR(rstc) && !on)
reset_control_assert(rstc);
- ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
- if (ret < 0) {
- pr_err("%s: could not update power domain\n", __func__);
- return ret;
- }
-
- ret = -1;
- while (ret != on) {
- ret = pmu_power_domain_is_on(pd);
+ if (has_pmu) {
+ ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
if (ret < 0) {
- pr_err("%s: could not read power domain state\n",
+ pr_err("%s: could not update power domain\n",
__func__);
return ret;
}
+
+ ret = -1;
+ while (ret != on) {
+ ret = pmu_power_domain_is_on(pd);
+ if (ret < 0) {
+ pr_err("%s: could not read power domain
state\n",
+ __func__);
+ return ret;
+ }
+ }
}
if (!IS_ERR(rstc)) {
@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct
task_struct *idle)
{
int ret;
- if (!sram_base_addr || !pmu) {
+ if (!sram_base_addr || (has_pmu && !pmu)) {
pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
return -ENXIO;
}
@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int
max_cpus)
return;
}
- if (rockchip_smp_prepare_pmu())
+ if (has_pmu && rockchip_smp_prepare_pmu())
return;
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int
max_cpus)
pmu_set_power_domain(0 + i, false);
}
+static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
+{
+ has_pmu = false;
+
+ rockchip_smp_prepare_cpus(max_cpus);
+}
+
#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu)
}
#endif
+static struct smp_operations rk3036_smp_ops __initdata = {
+ .smp_prepare_cpus = rk3036_smp_prepare_cpus,
+ .smp_boot_secondary = rockchip_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_kill = rockchip_cpu_kill,
+ .cpu_die= rockchip_cpu_die,
+#endif
+};
+
static struct smp_operations rockchip_smp_ops __initdata = {
.smp_prepare_cpus = rockchip_smp_prepare_cpus,
.smp_boot_secondary = rockchip_boot_secondary,
@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {
#endif
};
+CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
[PATCH v5 7/8] ARM: dts: enable smp for rk3036
Enable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
---
Changes in v5: None
arch/arm/boot/dts/rk3036.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 8f3a069..61352be 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -72,6 +72,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "rockchip,rk3036-smp";
cpu0: cpu@f00 {
device_type = "cpu";
@@ -146,6 +147,10 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1008 0x2000>;
+ smp-sram@0 {
+ compatible = "rockchip,rk3066-smp-sram";
+ reg = <0x00 0x10>;
+ };
};
cru: clock-controller@2000 {
--
1.7.9.5
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[PATCH v5 8/8] rockchip: make sure timer5 is enabled on rk3036 platforms
The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
---
Changes in v5:
Signed-off-by: Xing Zheng
Reviewed-by: Heiko Stuebner
arch/arm/mach-rockchip/rockchip.c | 44 +++--
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-rockchip/rockchip.c
b/arch/arm/mach-rockchip/rockchip.c
index 251c7b9..608b31c 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,31 +29,38 @@
#include "core.h"
#include "pm.h"
+#define RK3036_TIMER_PHYS 0x20044000
+
#define RK3288_GRF_SOC_CON0 0x244
#define RK3288_TIMER6_7_PHYS 0xff81
+static void rockchip_init_arch_timer_supply(resource_size_t phys, int offs)
+{
+ void __iomem *reg_base = ioremap(phys, SZ_16K);
+
+ /*
+* Most/all uboot versions for Rockchip SoCs don't enable
+* timer which is needed for the architected timer to work.
+* So make sure it is running during early boot.
+*/
+ if (reg_base) {
+ writel(0, reg_base + offs + 0x10);
+ writel(0x, reg_base + offs);
+ writel(0x, reg_base + offs + 0x04);
+ writel(1, reg_base + offs + 0x10);
+ dsb();
+ iounmap(reg_base);
+ } else {
+ pr_err("rockchip: could not map timer registers\n");
+ }
+}
+
static void __init rockchip_timer_init(void)
{
if (of_machine_is_compatible("rockchip,rk3288")) {
struct regmap *grf;
- void __iomem *reg_base;
- /*
-* Most/all uboot versions for rk3288 don't enable timer7
-* which is needed for the architected timer to work.
-* So make sure it is running during early boot.
-*/
- reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
- if (reg_base) {
- writel(0, reg_base + 0x30);
- writel(0x, reg_base + 0x20);
- writel(0x, reg_base + 0x24);
- writel(1, reg_base + 0x30);
- dsb();
- iounmap(reg_base);
- } else {
- pr_err("rockchip: could not map timer7 registers\n");
- }
+ rockchip_init_arch_timer_supply(RK3288_TIMER6_7_PHYS, 0x20);
/*
* Disable auto jtag/sdmmc switching that causes issues
@@ -64,6 +71,8 @@ static void __init rockchip_timer_init(void)
regmap_write(grf, RK3288_GRF_SOC_CON0, 0x1000);
else
pr_err("rockchip: could not get grf syscon\n");
+ } else if (of_machine_is_compatible("rockchip,rk3036")) {
+ rockchip_init_arch_timer_supply(RK3036_TIMER_PHYS, 0xa0);
}
of_clk_init(NULL);
@@ -79,6 +88,7 @@ static void __init rockchip_dt_init(void)
static const char * const rockchip_board_dt_compat[] = {
"rockchip,rk2928",
+ "rockchip,rk3036",
"rockchip,rk3066a",
"rockchip,rk3066b",
"rockchip,rk3188",
--
1.7.9.5
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[PATCH v1] ASoC: rockchip: fix a misjudgement by return
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rockchip_rt5645.c
b/sound/soc/rockchip/rockchip_rt5645.c
index 3c6bb1e..adfe98c 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -118,7 +118,7 @@ static int rk_init(struct snd_soc_pcm_runtime *runtime)
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&headset_jack, NULL, 0);
- if (!ret) {
+ if (ret) {
dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
return ret;
}
--
1.7.9.5
--
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[PATCH v1 0/1] A misjudgement should be fixed
Hi, Being careless, judge the return value of snd_soc_card_jack_new is opposite, so it should be fixed. Thanks. Changes in v1: Signed-off-by: Xing Zheng Reviewed-by: Dylan Reid Xing Zheng (1): ASoC: rockchip: fix a misjudgement by return sound/soc/rockchip/rockchip_rt5645.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RESEND PATCH v1 0/1] A misjudgement should be fixed
Hi, Being careless, judge the return value of snd_soc_card_jack_new is opposite, so it should be fixed. Thanks. Changes in v1: Signed-off-by: Xing Zheng Reviewed-by: Dylan Reid Xing Zheng (1): ASoC: rockchip: fix a misjudgement by return sound/soc/rockchip/rockchip_rt5645.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RESEND PATCH v1] ASoC: rockchip: fix a misjudgement by return
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v1:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rockchip_rt5645.c
b/sound/soc/rockchip/rockchip_rt5645.c
index 3c6bb1e..adfe98c 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -118,7 +118,7 @@ static int rk_init(struct snd_soc_pcm_runtime *runtime)
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&headset_jack, NULL, 0);
- if (!ret) {
+ if (ret) {
dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
return ret;
}
--
1.7.9.5
--
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[PATCH v2] ASoC: rockchip: fix a misjudgement by return
Being careless, judge the return value of snd_soc_card_jack_new
is opposite, so it should be fixed.
---
Changes in v2:
Signed-off-by: Xing Zheng
Reviewed-by: Dylan Reid
sound/soc/rockchip/rockchip_rt5645.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/rockchip/rockchip_rt5645.c
b/sound/soc/rockchip/rockchip_rt5645.c
index 3c6bb1e..adfe98c 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -118,7 +118,7 @@ static int rk_init(struct snd_soc_pcm_runtime *runtime)
SND_JACK_BTN_0 | SND_JACK_BTN_1 |
SND_JACK_BTN_2 | SND_JACK_BTN_3,
&headset_jack, NULL, 0);
- if (!ret) {
+ if (ret) {
dev_err(card->dev, "New Headset Jack failed! (%d)\n", ret);
return ret;
}
--
1.7.9.5
--
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[PATCH v2 2/2] ASoC: rockchip: Add machine driver for rt5645/rt5650 codec
er card failed %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static int snd_rk_mc_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *soc_card = platform_get_drvdata(pdev);
+
+ snd_soc_unregister_card(soc_card);
+
+ return 0;
+}
+
+static const struct of_device_id rockchip_rt5645_of_match[] = {
+ { .compatible = "rockchip,rockchip-audio-rt5645", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_rt5645_of_match);
+
+static struct platform_driver snd_rk_mc_driver = {
+ .probe = snd_rk_mc_probe,
+ .remove = snd_rk_mc_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = rockchip_rt5645_of_match,
+ },
+};
+
+module_platform_driver(snd_rk_mc_driver);
+
+MODULE_AUTHOR("Xing Zheng ");
+MODULE_DESCRIPTION("Rockchip rt5645 machine ASoC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
--
1.7.9.5
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[PATCH v2 0/2] Add codec machine driver for rockchip platform
From: zhengxing Hi, The simple-card is not common at present, soc maybe need own machine driver for jack detection. Add drivers for two families of rockchip-bases chromebooks. These machine drives don't use simplecard because we need custom jack detection plumbing. - use ts3a227e for ext jack detection with max98090 - call rt5645_set_jack_detect function via rt5645 codec driver Thanks. Changes in v2: Signed-off-by: zhengxing zhengxing (2): ASoC: rockchip: Add machine driver for max98090 codec ASoC: rockchip: Add machine driver for rt5645/rt5650 codec .../bindings/sound/rockchip-max98090.txt | 19 ++ .../devicetree/bindings/sound/rockchip-rt5645.txt | 17 ++ sound/soc/rockchip/Kconfig | 19 ++ sound/soc/rockchip/Makefile|6 + sound/soc/rockchip/rockchip_max98090.c | 247 sound/soc/rockchip/rockchip_rt5645.c | 236 +++ 6 files changed, 544 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/rockchip-max98090.txt create mode 100644 Documentation/devicetree/bindings/sound/rockchip-rt5645.txt create mode 100644 sound/soc/rockchip/rockchip_max98090.c create mode 100644 sound/soc/rockchip/rockchip_rt5645.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/2] ASoC: rockchip: Add machine driver for max98090 codec
From: zhengxing
The driver is used for rockchip board using a max98090.
Reviewed-by: Dylan Reid
Signed-off-by: zhengxing
---
Changes in v2: None
.../bindings/sound/rockchip-max98090.txt | 19 ++
sound/soc/rockchip/Kconfig | 10 +
sound/soc/rockchip/Makefile|4 +
sound/soc/rockchip/rockchip_max98090.c | 247
4 files changed, 280 insertions(+)
create mode 100644
Documentation/devicetree/bindings/sound/rockchip-max98090.txt
create mode 100644 sound/soc/rockchip/rockchip_max98090.c
diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
new file mode 100644
index 000..a805aa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
@@ -0,0 +1,19 @@
+ROCKCHIP with MAX98090 CODEC
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-max98090"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+ connected to the CODEC
+- rockchip,audio-codec: The phandle of the MAX98090 audio codec
+- rockchip,headset-codec: The phandle of Ext chip for jack detection
+
+Example:
+
+sound {
+ compatible = "rockchip,rockchip-audio-max98090";
+ rockchip,model = "ROCKCHIP-I2S";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&max98090>;
+ rockchip,headset-codec = <&headsetcodec>;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index e181826..d123566 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -14,3 +14,13 @@ config SND_SOC_ROCKCHIP_I2S
Say Y or M if you want to add support for I2S driver for
Rockchip I2S device. The device supports upto maximum of
8 channels each for play and record.
+
+config SND_SOC_ROCKCHIP_MAX98090
+ tristate "ASoC support for Rockchip boards using a MAX98090 codec"
+ depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB
+ select SND_SOC_ROCKCHIP_I2S
+ select SND_SOC_MAX98090
+ select SND_SOC_TS3A227E
+ help
+ Say Y or M here if you want to add support for SoC audio on Rockchip
+ boards using the MAX98090 codec, such as Veyron.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index b921909..df3445b 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -2,3 +2,7 @@
snd-soc-i2s-objs := rockchip_i2s.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-i2s.o
+
+snd-soc-rockchip-max98090-objs := rockchip_max98090.o
+
+obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
diff --git a/sound/soc/rockchip/rockchip_max98090.c
b/sound/soc/rockchip/rockchip_max98090.c
new file mode 100644
index 000..f6644b3
--- /dev/null
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -0,0 +1,247 @@
+/*
+ * Rockchip machine ASoC driver for boards using a MAX90809 CODEC.
+ *
+ * Copyright (c) 2014, ROCKCHIP CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see
