[PATCH] dmaengine: xgene-dma: Disable memcpy operation due to performance drop
The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other computations. But the bandwidth of the entire DMA engine is shared among all channels. This patch re-configures operations availability such that one can achieve maximum performance for XOR and PQ computation by removing the memory offload operations. Signed-off-by: Rameshwar Prasad Sahu --- drivers/dma/xgene-dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c index 8d57b1b..2998fcb 100644 --- a/drivers/dma/xgene-dma.c +++ b/drivers/dma/xgene-dma.c @@ -154,6 +154,7 @@ #define XGENE_DMA_MAX_XOR_SRC 5 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0 #define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL +#undef XGENE_DMA_MEMCPY_ENABLE /* X-Gene DMA descriptor error codes */ #define ERR_DESC_AXI 0x01 @@ -1707,7 +1708,9 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan, dma_cap_zero(dma_dev->cap_mask); /* Set DMA device capability */ +#ifdef XGENE_DMA_MEMCPY_ENABLE dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); +#endif dma_cap_set(DMA_SG, dma_dev->cap_mask); /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] dmaengine: xgene-dma: Disable memcpy operation due to performance drop
The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other computations. But the bandwidth of the entire DMA engine is shared among all channels. This patch re-configures operations availability such that one can achieve maximum performance for XOR and PQ computation by removing the memory offload operations. Signed-off-by: Rameshwar Prasad Sahu --- drivers/dma/xgene-dma.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c index 8d57b1b..cd38022 100644 --- a/drivers/dma/xgene-dma.c +++ b/drivers/dma/xgene-dma.c @@ -1707,7 +1707,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan, dma_cap_zero(dma_dev->cap_mask); /* Set DMA device capability */ - dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); dma_cap_set(DMA_SG, dma_dev->cap_mask); /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] dmaengine: xgene-dma: Remove memcpy offload support due to performance drop
The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other
computations. But the bandwidth of the entire DMA engine is shared
among all channels. This patch re-configures operations availability
such that one can achieve maximum performance for XOR and PQ
computation by removing the memory offload operations.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 59 +
1 file changed, 1 insertion(+), 58 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 8d57b1b..b291733 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -894,60 +894,6 @@ static void xgene_dma_free_chan_resources(struct dma_chan
*dchan)
chan->desc_pool = NULL;
}
-static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy(
- struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
- size_t len, unsigned long flags)
-{
- struct xgene_dma_desc_sw *first = NULL, *new;
- struct xgene_dma_chan *chan;
- size_t copy;
-
- if (unlikely(!dchan || !len))
- return NULL;
-
- chan = to_dma_chan(dchan);
-
- do {
- /* Allocate the link descriptor from DMA pool */
- new = xgene_dma_alloc_descriptor(chan);
- if (!new)
- goto fail;
-
- /* Create the largest transaction possible */
- copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
-
- /* Prepare DMA descriptor */
- xgene_dma_prep_cpy_desc(chan, new, dst, src, copy);
-
- if (!first)
- first = new;
-
- new->tx.cookie = 0;
- async_tx_ack(&new->tx);
-
- /* Update metadata */
- len -= copy;
- dst += copy;
- src += copy;
-
- /* Insert the link descriptor to the LD ring */
- list_add_tail(&new->node, &first->tx_list);
- } while (len);
-
- new->tx.flags = flags; /* client is in control of this ack */
- new->tx.cookie = -EBUSY;
- list_splice(&first->tx_list, &new->tx_list);
-
- return &new->tx;
-
-fail:
- if (!first)
- return NULL;
-
- xgene_dma_free_desc_list(chan, &first->tx_list);
- return NULL;
-}
-
static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
struct dma_chan *dchan, struct scatterlist *dst_sg,
u32 dst_nents, struct scatterlist *src_sg,
@@ -1707,7 +1653,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan
*chan,
dma_cap_zero(dma_dev->cap_mask);
/* Set DMA device capability */
- dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
dma_cap_set(DMA_SG, dma_dev->cap_mask);
/* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
@@ -1734,7 +1679,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan
*chan,
dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
dma_dev->device_issue_pending = xgene_dma_issue_pending;
dma_dev->device_tx_status = xgene_dma_tx_status;
- dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;
dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
@@ -1787,8 +1731,7 @@ static int xgene_dma_async_register(struct xgene_dma
*pdma, int id)
/* DMA capability info */
dev_info(pdma->dev,
-"%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan),
-dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",
+"%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan),
dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
--
1.8.2.1
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[PATCH v1 0/3] dmaengine: APM X-Gene SoC DMA driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gathering. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS node Documentation: dma: Add APM X-Gene SoC DMA driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 25 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1506 5 files changed, 1589 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100644 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/3] dmaengine: Add support for APM X-Gene SoC DMA driver
This patch implements the APM X-Gene SoC DMA driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1506 +++ 3 files changed, 1515 insertions(+) create mode 100644 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100644 index 000..e00c062 --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1506 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_ID0x0008 +#define RING_ID_BUF0x000c +#define RING_CONFIG0x006c +#define RING_WR_BASE 0x0070 +#define RING_NE_INT_MODE 0x017c +#define RING_NUM_CONFIG5 +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_QCOHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RINNG_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v + +/* DMA device csr registers and bit definitions */ +#define DMA_MEM_RAM_SHUTDOWN 0xD070 +#define DMA_BLK_MEM_RDY0xD074 +#define DMA_BLK_MEM_RDY_DEFAULT0x +#define DMA_RING_INT0_MASK 0x90A0 +#define DMA_RING_INT1_MASK 0x90A8 +#define DMA_RING_INT2_MASK 0x90B0 +#define DMA_RING_INT3_MASK 0x90B8 +#define DMA_RING_INT4_MASK 0x90C0 +#define DMA_CFG_RING_WQ_ASSOC 0x90E0 +#define DMA_WQ_ASSOC_RING_MNGR10x +#define DMA_CFG_RING_HOLD 0x90F8 +#define DMA_RING_MNGR1_HOLD_EN BIT(1) +#define DMA_IPBRR 0x0 +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_DEVICE_ID_RD(v)((v) & 0x0FFF) +#define DMA_INT0x70 +#define DMA_INT_MASK 0x74 +#define DMA_INT_ALL_UNMASK 0x0 +#define DMA_INT_MASK_SHIFT 0x14 +#define DMA_GCR
[PATCH v1 1/3] dmaengine: Add support for APM X-Gene SoC DMA driver
This patch implements the APM X-Gene SoC DMA driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1506 +++ 3 files changed, 1515 insertions(+) create mode 100644 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100644 index 000..e00c062 --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1506 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_ID0x0008 +#define RING_ID_BUF0x000c +#define RING_CONFIG0x006c +#define RING_WR_BASE 0x0070 +#define RING_NE_INT_MODE 0x017c +#define RING_NUM_CONFIG5 +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_QCOHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RINNG_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v + +/* DMA device csr registers and bit definitions */ +#define DMA_MEM_RAM_SHUTDOWN 0xD070 +#define DMA_BLK_MEM_RDY0xD074 +#define DMA_BLK_MEM_RDY_DEFAULT0x +#define DMA_RING_INT0_MASK 0x90A0 +#define DMA_RING_INT1_MASK 0x90A8 +#define DMA_RING_INT2_MASK 0x90B0 +#define DMA_RING_INT3_MASK 0x90B8 +#define DMA_RING_INT4_MASK 0x90C0 +#define DMA_CFG_RING_WQ_ASSOC 0x90E0 +#define DMA_WQ_ASSOC_RING_MNGR10x +#define DMA_CFG_RING_HOLD 0x90F8 +#define DMA_RING_MNGR1_HOLD_EN BIT(1) +#define DMA_IPBRR 0x0 +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_DEVICE_ID_RD(v)((v) & 0x0FFF) +#define DMA_INT0x70 +#define DMA_INT_MASK 0x74 +#define DMA_INT_ALL_UNMASK 0x0 +#define DMA_INT_MASK_SHIFT 0x14 +#define DMA_GCR
[PATCH v1 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS node
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..95b30c2 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -352,6 +352,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +665,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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[PATCH v1 3/3] Documentation: dma: Add APM X-Gene SoC DMA driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..e2cf0bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1500 +++ 3 files changed, 1509 insertions(+) create mode 100644 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100644 index 000..ba8001a --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1500 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_ID0x0008 +#define RING_ID_BUF0x000c +#define RING_CONFIG0x006c +#define RING_WR_BASE 0x0070 +#define RING_NE_INT_MODE 0x017c +#define RING_NUM_CONFIG5 +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_QCOHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RINNG_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v + +/* DMA device csr registers and bit definitions */ +#define DMA_MEM_RAM_SHUTDOWN 0xD070 +#define DMA_BLK_MEM_RDY0xD074 +#define DMA_BLK_MEM_RDY_DEFAULT0x +#define DMA_RING_INT0_MASK 0x90A0 +#define DMA_RING_INT1_MASK 0x90A8 +#define DMA_RING_INT2_MASK 0x90B0 +#define DMA_RING_INT3_MASK 0x90B8 +#define DMA_RING_INT4_MASK 0x90C0 +#define DMA_CFG_RING_WQ_ASSOC 0x90E0 +#define DMA_WQ_ASSOC_RING_MNGR10x +#define DMA_CFG_RING_HOLD 0x90F8 +#define DMA_RING_MNGR1_HOLD_EN BIT(1) +#define DMA_IPBRR 0x0 +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_DEVICE_ID_RD(v)((v) & 0x0FFF) +#define DMA_INT0x70 +#define DMA_INT_MASK 0x74 +#define DMA_INT_ALL_UNMASK 0x0 +#define DMA_INT_MASK_SHIFT 0x14 +#define DMA_GCR
[PATCH v2 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gathering. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 25 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1500 5 files changed, 1583 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100644 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..e2cf0bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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[PATCH v2 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..95b30c2 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -352,6 +352,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +665,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gathering. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 28 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1566 5 files changed, 1652 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100644 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..e20da23 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -103,6 +103,9 @@
#size-cells = <2>;
ranges;
+ /* DDR range is 42-bit addressing */
+ dma-ranges = <0x40 0x0 0x40 0x0 0x1ff 0x>;
+
clocks {
#address-cells = <2>;
#size-cells = <2>;
@@ -352,6 +355,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +668,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..c661cc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1566 +++ 3 files changed, 1575 insertions(+) create mode 100644 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100644 index 000..3cc622c --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1566 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_CONFIG0x04 +#define RING_ENABLEBIT(31) +#define RING_ID0x08 +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF0x0C +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_THRESLD0_SET1 0x30 +#define RING_THRESLD0_SET1_VAL 0X64 +#define RING_THRESLD1_SET1 0x34 +#define RING_THRESLD1_SET1_VAL 0xC8 +#define RING_HYSTERESIS0x68 +#define RING_HYSTERESIS_VAL0x +#define RING_STATE 0x6C +#define RING_STATE_WR_BASE 0x70 +#define RING_NE_INT_MODE 0x017C +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define RING_CLKEN 0xC208 +#define RING_SRST 0xC200 +#define RING_MEM_RAM_SHUTDOWN 0xD070 +#define RING_BLK_MEM_RDY 0xD074 +#define RING_BLK_MEM_RDY_VAL 0x +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_NUM_CONFIG5 +#define RING_QCOHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RINNG_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) + +/* DMA device csr registers and bit definitions */ +#define DMA_IPBRR 0x0 +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_DEVICE_ID_RD(v)((v) & 0x0FFF) +#define DMA_GCR0x10 +#define DMA_CH_SETUP(m)((m) = ((m) & ~0x000F) | 0x000AAFFF) +#define DMA_ENABLE(m) ((m) = ((m) & ~B
[PATCH] dmaengine: xgene-dma: Fix sparse wannings incorrect type in assignment (different base types)
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc.
This patch is based on slave-dma / for-linus branch.
(commit: 9f2fd0dfa594d857fbdaeda523ff7a46f16567f5 [26/28]
dmaengine: Add support for APM X-Gene SoC DMA engine driver)
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 43 +--
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index aa61935..a89287f 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -238,10 +238,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,12 +388,12 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
+static void xgene_dma_cpu_to_le64(struct xgene_dma_desc_hw *desc)
{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
+ desc->m0 = cpu_to_le64(((u64 *)desc)[0]);
+ desc->m1 = cpu_to_le64(((u64 *)desc)[1]);
+ desc->m2 = cpu_to_le64(((u64 *)desc)[2]);
+ desc->m3 = cpu_to_le64(((u64 *)desc)[3]);
}
static u16 xgene_dma_encode_len(u32 len)
@@ -499,9 +499,9 @@ static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan
*chan,
skip_additional_src:
/* Hardware stores descriptor in little endian format */
- xgene_dma_cpu_to_le64(desc1, 4);
+ xgene_dma_cpu_to_le64(desc1);
if (desc2)
- xgene_dma_cpu_to_le64(desc2, 4);
+ xgene_dma_cpu_to_le64(desc2);
}
static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
@@ -540,8 +540,8 @@ static void xgene_dma_prep_xor_desc(struct xgene_dma_chan
*chan,
}
/* Hardware stores descriptor in little endian format */
- xgene_dma_cpu_to_le64(desc1, 4);
- xgene_dma_cpu_to_le64(desc2, 4);
+ xgene_dma_cpu_to_le64(desc1);
+ xgene_dma_cpu_to_le64(desc2);
/* Update meta data */
*nbytes = len;
@@ -1895,9 +1895,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_dma)) {
+ if (!pdma->csr_dma) {
dev_err(&pdev->dev, "Failed to ioremap csr region");
- return PTR_ERR(pdma->csr_dma);
+ return -ENOMEM;
}
/* Get DMA ring csr region */
@@ -1909,9 +1909,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_ring)) {
+ if (!pdma->csr_ring) {
dev_err(&pdev->dev, "Failed to ioremap ring csr region");
- return PTR_ERR(pdma->csr_ring);
+ return -ENOMEM;
}
/* Get DMA ring cmd csr region */
@@ -1923,9 +1923,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_ring_cmd)) {
+ if (!pdma->csr_ring_cmd) {
dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
- return PTR_ERR(pdma->csr_ring_cmd);
+ return -ENOMEM;
}
/* Get efuse csr region */
@@ -1937,9 +1937,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_efuse)) {
+ if (!pdma->csr_efuse) {
dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
- return PTR_ERR(pdma->csr_efuse);
+ return -ENOMEM;
}
/* Get DMA error interrupt */
@@ -2085,6 +2085,5 @@ module_platform_driver(xgene_dma_driver);
MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
MODULE_AUTHOR("Rameshwar Prasad Sahu ");
-MODULE_AUTHOR("Loc Ho ");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.0");
--
1.8.2.1
--
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[PATCH v5] dmaengine: xgene-dma: Fix sparse wannings warnings
v5 changes:
* Re-pull v3 changes that I missed in v4
v4 changes:
* Re-generate patch on top of latest for-linux git
v3 changes:
* Minor changes in length setting in DMA descriptor
v2 changes:
* Code cleanup
* Changed way of setting DMA descriptors for big-endian
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc.
This patch is based on slave-dma / for-linus branch.
(commit: 11ebe4c067c7f95adff73594cb5c23f7a5c6d69e
dmaengine: fix platform_no_drv_owner.cocci warnings
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 174 ++--
1 file changed, 66 insertions(+), 108 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index f52e3750..856610c 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -124,32 +124,8 @@
#define XGENE_DMA_DESC_ELERR_POS 46
#define XGENE_DMA_DESC_RTYPE_POS 56
#define XGENE_DMA_DESC_LERR_POS60
-#define XGENE_DMA_DESC_FLYBY_POS 4
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
-
-#define XGENE_DMA_DESC_NV_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_NV_BIT)
-#define XGENE_DMA_DESC_IN_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_IN_BIT)
-#define XGENE_DMA_DESC_RTYPE_SET(m, v) \
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_RTYPE_POS))
-#define XGENE_DMA_DESC_BUFADDR_SET(m, v) \
- (((u64 *)(m))[0] |= (v))
-#define XGENE_DMA_DESC_BUFLEN_SET(m, v)\
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_BUFLEN_POS))
-#define XGENE_DMA_DESC_C_SET(m)\
- (((u64 *)(m))[1] |= XGENE_DMA_DESC_C_BIT)
-#define XGENE_DMA_DESC_FLYBY_SET(m, v) \
- (((u64 *)(m))[2] |= ((v) << XGENE_DMA_DESC_FLYBY_POS))
-#define XGENE_DMA_DESC_MULTI_SET(m, v, i) \
- (((u64 *)(m))[2] |= ((u64)(v) << (((i) + 1) * 8)))
-#define XGENE_DMA_DESC_DR_SET(m) \
- (((u64 *)(m))[2] |= XGENE_DMA_DESC_DR_BIT)
-#define XGENE_DMA_DESC_DST_ADDR_SET(m, v) \
- (((u64 *)(m))[3] |= (v))
-#define XGENE_DMA_DESC_H0ENQ_NUM_SET(m, v) \
- (((u64 *)(m))[3] |= ((u64)(v) << XGENE_DMA_DESC_HOENQ_NUM_POS))
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -158,14 +134,7 @@
(((elerr) << 4) | (lerr))
/* X-Gene DMA descriptor empty s/w signature */
-#define XGENE_DMA_DESC_EMPTY_INDEX 0
#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
-#define XGENE_DMA_DESC_SET_EMPTY(m)\
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] = \
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
-#define XGENE_DMA_DESC_IS_EMPTY(m) \
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] ==\
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
@@ -184,7 +153,7 @@
#define XGENE_DMA_XOR_ALIGNMENT6 /* 64 Bytes */
#define XGENE_DMA_MAX_XOR_SRC 5
#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
-#define XGENE_DMA_INVALID_LEN_CODE 0x7800
+#define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
/* X-Gene DMA descriptor error codes */
#define ERR_DESC_AXI 0x01
@@ -214,10 +183,10 @@
#define ERR_DESC_SRC_INT 0xB
/* X-Gene DMA flyby operation code */
-#define FLYBY_2SRC_XOR 0x8
-#define FLYBY_3SRC_XOR 0x9
-#define FLYBY_4SRC_XOR 0xA
-#define FLYBY_5SRC_XOR 0xB
+#define FLYBY_2SRC_XOR 0x80
+#define FLYBY_3SRC_XOR 0x90
+#define FLYBY_4SRC_XOR 0xA0
+#define FLYBY_5SRC_XOR 0xB0
/* X-Gene DMA SW descriptor flags */
#define XGENE_DMA_FLAG_64B_DESCBIT(0)
@@ -238,10 +207,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,18 +357,11 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
-}
-
-static u16 xgene_dma_encode_len(u32 len)
+static u64 xgene_dma_encode_len(size_t len)
{
return (len
[PATCH] dmaengine: xgene-dma: Fix sparse wannings and coccinelle warnings
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc and
coccinelle warnings (No need to set .owner here. The core will do it.)
This patch is based on slave-dma / for-linus branch.
(commit: 9f2fd0dfa594d857fbdaeda523ff7a46f16567f5 [26/28]
dmaengine: Add support for APM X-Gene SoC DMA engine driver)
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 44 +---
1 file changed, 21 insertions(+), 23 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index aa61935..59f95db 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -238,10 +238,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,12 +388,12 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
+static void xgene_dma_cpu_to_le64(struct xgene_dma_desc_hw *desc)
{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
+ desc->m0 = cpu_to_le64(((u64 *)desc)[0]);
+ desc->m1 = cpu_to_le64(((u64 *)desc)[1]);
+ desc->m2 = cpu_to_le64(((u64 *)desc)[2]);
+ desc->m3 = cpu_to_le64(((u64 *)desc)[3]);
}
static u16 xgene_dma_encode_len(u32 len)
@@ -499,9 +499,9 @@ static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan
*chan,
skip_additional_src:
/* Hardware stores descriptor in little endian format */
- xgene_dma_cpu_to_le64(desc1, 4);
+ xgene_dma_cpu_to_le64(desc1);
if (desc2)
- xgene_dma_cpu_to_le64(desc2, 4);
+ xgene_dma_cpu_to_le64(desc2);
}
static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
@@ -540,8 +540,8 @@ static void xgene_dma_prep_xor_desc(struct xgene_dma_chan
*chan,
}
/* Hardware stores descriptor in little endian format */
- xgene_dma_cpu_to_le64(desc1, 4);
- xgene_dma_cpu_to_le64(desc2, 4);
+ xgene_dma_cpu_to_le64(desc1);
+ xgene_dma_cpu_to_le64(desc2);
/* Update meta data */
*nbytes = len;
@@ -1895,9 +1895,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_dma)) {
+ if (!pdma->csr_dma) {
dev_err(&pdev->dev, "Failed to ioremap csr region");
- return PTR_ERR(pdma->csr_dma);
+ return -ENOMEM;
}
/* Get DMA ring csr region */
@@ -1909,9 +1909,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_ring)) {
+ if (!pdma->csr_ring) {
dev_err(&pdev->dev, "Failed to ioremap ring csr region");
- return PTR_ERR(pdma->csr_ring);
+ return -ENOMEM;
}
/* Get DMA ring cmd csr region */
@@ -1923,9 +1923,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_ring_cmd)) {
+ if (!pdma->csr_ring_cmd) {
dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
- return PTR_ERR(pdma->csr_ring_cmd);
+ return -ENOMEM;
}
/* Get efuse csr region */
@@ -1937,9 +1937,9 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(pdma->csr_efuse)) {
+ if (!pdma->csr_efuse) {
dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
- return PTR_ERR(pdma->csr_efuse);
+ return -ENOMEM;
}
/* Get DMA error interrupt */
@@ -2076,7 +2076,6 @@ static struct platform_driver xgene_dma_driver = {
.remove = xgene_dma_remove,
.driver = {
.name = "X-Gene-DMA",
- .owner = THIS_MODULE,
.of_match_table = xgene_dma_of_match_ptr,
},
};
@@ -2085,6 +2084,5 @@ module_platform_driver(xgene
[PATCH v2] dmaengine: xgene-dma: Fix sparse wannings and coccinelle warnings
v2 changes:
* Code cleanup
* Changed way of setting DMA descriptors for big-endian
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc and
coccinelle warnings (No need to set .owner here. The core will do it.)
This patch is based on slave-dma / for-linus branch.
(commit: 9f2fd0dfa594d857fbdaeda523ff7a46f16567f5 [26/28]
dmaengine: Add support for APM X-Gene SoC DMA engine driver)
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 178 +++-
1 file changed, 69 insertions(+), 109 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index aa61935..d28830e 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -127,29 +127,6 @@
#define XGENE_DMA_DESC_FLYBY_POS 4
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
-
-#define XGENE_DMA_DESC_NV_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_NV_BIT)
-#define XGENE_DMA_DESC_IN_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_IN_BIT)
-#define XGENE_DMA_DESC_RTYPE_SET(m, v) \
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_RTYPE_POS))
-#define XGENE_DMA_DESC_BUFADDR_SET(m, v) \
- (((u64 *)(m))[0] |= (v))
-#define XGENE_DMA_DESC_BUFLEN_SET(m, v)\
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_BUFLEN_POS))
-#define XGENE_DMA_DESC_C_SET(m)\
- (((u64 *)(m))[1] |= XGENE_DMA_DESC_C_BIT)
-#define XGENE_DMA_DESC_FLYBY_SET(m, v) \
- (((u64 *)(m))[2] |= ((v) << XGENE_DMA_DESC_FLYBY_POS))
-#define XGENE_DMA_DESC_MULTI_SET(m, v, i) \
- (((u64 *)(m))[2] |= ((u64)(v) << (((i) + 1) * 8)))
-#define XGENE_DMA_DESC_DR_SET(m) \
- (((u64 *)(m))[2] |= XGENE_DMA_DESC_DR_BIT)
-#define XGENE_DMA_DESC_DST_ADDR_SET(m, v) \
- (((u64 *)(m))[3] |= (v))
-#define XGENE_DMA_DESC_H0ENQ_NUM_SET(m, v) \
- (((u64 *)(m))[3] |= ((u64)(v) << XGENE_DMA_DESC_HOENQ_NUM_POS))
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -158,14 +135,7 @@
(((elerr) << 4) | (lerr))
/* X-Gene DMA descriptor empty s/w signature */
-#define XGENE_DMA_DESC_EMPTY_INDEX 0
#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
-#define XGENE_DMA_DESC_SET_EMPTY(m)\
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] = \
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
-#define XGENE_DMA_DESC_IS_EMPTY(m) \
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] ==\
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
@@ -238,10 +208,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,14 +358,6 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
-}
-
static u16 xgene_dma_encode_len(u32 len)
{
return (len < XGENE_DMA_MAX_BYTE_CNT) ?
@@ -424,34 +386,52 @@ static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring
*ring)
return XGENE_DMA_RING_DESC_CNT(ring_state);
}
-static void xgene_dma_set_src_buffer(void *ext8, size_t *len,
+static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
dma_addr_t *paddr)
{
size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
*len : XGENE_DMA_MAX_BYTE_CNT;
- XGENE_DMA_DESC_BUFADDR_SET(ext8, *paddr);
- XGENE_DMA_DESC_BUFLEN_SET(ext8, xgene_dma_encode_len(nbytes));
+ *ext8 |= cpu_to_le64(*paddr);
+ *ext8 |= cpu_to_le64((u64)xgene_dma_encode_len(nbytes) <<
+XGENE_DMA_DESC_BUFLEN_POS);
*len -= nbytes;
*paddr += nbytes;
}
-static void xgene_dma_invalidate_buffer(void *ext8)
+static void xgene_dma_invalidate_buffer(__le64 *ext8)
{
- XGENE_DMA_DESC_BUFLEN_SET(ext8, XGENE_DMA_INVALID_LEN_CODE);
+ *ext8 |= cpu_to_le64((u64)XGENE_DMA_INVALID_LEN_CODE <<
+XGENE_DMA_DESC_BUFLEN_POS);
}
-static void *xgene_dma_lookup_ext8(u64 *desc, int idx)
+static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc
[PATCH v3] dmaengine: xgene-dma: Fix sparse wannings and coccinelle warnings
v3 changes:
* Minor changes in length setting in DMA descriptor
v2 changes:
* Code cleanup
* Changed way of setting DMA descriptors for big-endian
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc and
coccinelle warnings (No need to set .owner here. The core will do it.)
This patch is based on slave-dma / for-linus branch.
(commit: 9f2fd0dfa594d857fbdaeda523ff7a46f16567f5 [26/28]
dmaengine: Add support for APM X-Gene SoC DMA engine driver)
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 191 +++-
1 file changed, 74 insertions(+), 117 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index aa61935..722c684 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -124,32 +124,8 @@
#define XGENE_DMA_DESC_ELERR_POS 46
#define XGENE_DMA_DESC_RTYPE_POS 56
#define XGENE_DMA_DESC_LERR_POS60
-#define XGENE_DMA_DESC_FLYBY_POS 4
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
-
-#define XGENE_DMA_DESC_NV_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_NV_BIT)
-#define XGENE_DMA_DESC_IN_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_IN_BIT)
-#define XGENE_DMA_DESC_RTYPE_SET(m, v) \
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_RTYPE_POS))
-#define XGENE_DMA_DESC_BUFADDR_SET(m, v) \
- (((u64 *)(m))[0] |= (v))
-#define XGENE_DMA_DESC_BUFLEN_SET(m, v)\
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_BUFLEN_POS))
-#define XGENE_DMA_DESC_C_SET(m)\
- (((u64 *)(m))[1] |= XGENE_DMA_DESC_C_BIT)
-#define XGENE_DMA_DESC_FLYBY_SET(m, v) \
- (((u64 *)(m))[2] |= ((v) << XGENE_DMA_DESC_FLYBY_POS))
-#define XGENE_DMA_DESC_MULTI_SET(m, v, i) \
- (((u64 *)(m))[2] |= ((u64)(v) << (((i) + 1) * 8)))
-#define XGENE_DMA_DESC_DR_SET(m) \
- (((u64 *)(m))[2] |= XGENE_DMA_DESC_DR_BIT)
-#define XGENE_DMA_DESC_DST_ADDR_SET(m, v) \
- (((u64 *)(m))[3] |= (v))
-#define XGENE_DMA_DESC_H0ENQ_NUM_SET(m, v) \
- (((u64 *)(m))[3] |= ((u64)(v) << XGENE_DMA_DESC_HOENQ_NUM_POS))
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -158,14 +134,7 @@
(((elerr) << 4) | (lerr))
/* X-Gene DMA descriptor empty s/w signature */
-#define XGENE_DMA_DESC_EMPTY_INDEX 0
#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
-#define XGENE_DMA_DESC_SET_EMPTY(m)\
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] = \
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
-#define XGENE_DMA_DESC_IS_EMPTY(m) \
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] ==\
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
@@ -184,7 +153,7 @@
#define XGENE_DMA_XOR_ALIGNMENT6 /* 64 Bytes */
#define XGENE_DMA_MAX_XOR_SRC 5
#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
-#define XGENE_DMA_INVALID_LEN_CODE 0x7800
+#define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
/* X-Gene DMA descriptor error codes */
#define ERR_DESC_AXI 0x01
@@ -214,10 +183,10 @@
#define ERR_DESC_SRC_INT 0xB
/* X-Gene DMA flyby operation code */
-#define FLYBY_2SRC_XOR 0x8
-#define FLYBY_3SRC_XOR 0x9
-#define FLYBY_4SRC_XOR 0xA
-#define FLYBY_5SRC_XOR 0xB
+#define FLYBY_2SRC_XOR 0x80
+#define FLYBY_3SRC_XOR 0x90
+#define FLYBY_4SRC_XOR 0xA0
+#define FLYBY_5SRC_XOR 0xB0
/* X-Gene DMA SW descriptor flags */
#define XGENE_DMA_FLAG_64B_DESCBIT(0)
@@ -238,10 +207,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,18 +357,11 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
-}
-
-static u16 xgene_dma_encode_len(u32 len)
+static u64 xgene_dma_encode_len(size_t len)
{
return (len < XGENE_DMA_MAX_BYTE_CNT) ?
- len : XGE
[PATCH v4] dmaengine: xgene-dma: Fix sparse wannings and coccinelle warnings
v4 changes:
* Re-generate patch on top of latest for-linux git
v3 changes:
* Minor changes in length setting in DMA descriptor
v2 changes:
* Code cleanup
* Changed way of setting DMA descriptors for big-endian
This patch fixes compilation sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64, symbol
'__UNIQUE_ID_author__COUNTER__' has multiple initializers etc and
coccinelle warnings (No need to set .owner here. The core will do it.)
This patch is based on slave-dma / for-linus branch.
(commit: 9f2fd0dfa594d857fbdaeda523ff7a46f16567f5 [26/28]
dmaengine: Add support for APM X-Gene SoC DMA engine driver)
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 161 ++--
1 file changed, 61 insertions(+), 100 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index f52e3750..063c835 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -127,29 +127,6 @@
#define XGENE_DMA_DESC_FLYBY_POS 4
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
-
-#define XGENE_DMA_DESC_NV_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_NV_BIT)
-#define XGENE_DMA_DESC_IN_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_IN_BIT)
-#define XGENE_DMA_DESC_RTYPE_SET(m, v) \
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_RTYPE_POS))
-#define XGENE_DMA_DESC_BUFADDR_SET(m, v) \
- (((u64 *)(m))[0] |= (v))
-#define XGENE_DMA_DESC_BUFLEN_SET(m, v)\
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_BUFLEN_POS))
-#define XGENE_DMA_DESC_C_SET(m)\
- (((u64 *)(m))[1] |= XGENE_DMA_DESC_C_BIT)
-#define XGENE_DMA_DESC_FLYBY_SET(m, v) \
- (((u64 *)(m))[2] |= ((v) << XGENE_DMA_DESC_FLYBY_POS))
-#define XGENE_DMA_DESC_MULTI_SET(m, v, i) \
- (((u64 *)(m))[2] |= ((u64)(v) << (((i) + 1) * 8)))
-#define XGENE_DMA_DESC_DR_SET(m) \
- (((u64 *)(m))[2] |= XGENE_DMA_DESC_DR_BIT)
-#define XGENE_DMA_DESC_DST_ADDR_SET(m, v) \
- (((u64 *)(m))[3] |= (v))
-#define XGENE_DMA_DESC_H0ENQ_NUM_SET(m, v) \
- (((u64 *)(m))[3] |= ((u64)(v) << XGENE_DMA_DESC_HOENQ_NUM_POS))
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -158,14 +135,7 @@
(((elerr) << 4) | (lerr))
/* X-Gene DMA descriptor empty s/w signature */
-#define XGENE_DMA_DESC_EMPTY_INDEX 0
#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
-#define XGENE_DMA_DESC_SET_EMPTY(m)\
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] = \
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
-#define XGENE_DMA_DESC_IS_EMPTY(m) \
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] ==\
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
@@ -238,10 +208,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,14 +358,6 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
-}
-
static u16 xgene_dma_encode_len(u32 len)
{
return (len < XGENE_DMA_MAX_BYTE_CNT) ?
@@ -424,34 +386,52 @@ static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring
*ring)
return XGENE_DMA_RING_DESC_CNT(ring_state);
}
-static void xgene_dma_set_src_buffer(void *ext8, size_t *len,
+static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
dma_addr_t *paddr)
{
size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
*len : XGENE_DMA_MAX_BYTE_CNT;
- XGENE_DMA_DESC_BUFADDR_SET(ext8, *paddr);
- XGENE_DMA_DESC_BUFLEN_SET(ext8, xgene_dma_encode_len(nbytes));
+ *ext8 |= cpu_to_le64(*paddr);
+ *ext8 |= cpu_to_le64((u64)xgene_dma_encode_len(nbytes) <<
+XGENE_DMA_DESC_BUFLEN_POS);
*len -= nbytes;
*paddr += nbytes;
}
-static void xgene_dma_invalidate_buffer(void *ext8)
+static void xgene_dma_invalidate_buffer(__le64 *ext8)
{
- XGENE_DMA_DESC_BUFLEN_SET(ext8, XGENE_DMA_INVALID_LEN_CODE);
+ *ext8 |= cpu_to_le64((u64)XGENE_DMA_INVALID_LEN_CODE <<
+XGENE
[PATCH] dmaengine: xgene-dma: Fix "incorrect type in assignement" warnings
This patch fixes sparse warnings like incorrect type in assignment
(different base types), cast to restricted __le64.
Reported-by: kbuild test robot
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 173 ++--
1 file changed, 66 insertions(+), 107 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index f52e3750..620fd55ec 100755
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -124,32 +124,8 @@
#define XGENE_DMA_DESC_ELERR_POS 46
#define XGENE_DMA_DESC_RTYPE_POS 56
#define XGENE_DMA_DESC_LERR_POS60
-#define XGENE_DMA_DESC_FLYBY_POS 4
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
-
-#define XGENE_DMA_DESC_NV_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_NV_BIT)
-#define XGENE_DMA_DESC_IN_SET(m) \
- (((u64 *)(m))[0] |= XGENE_DMA_DESC_IN_BIT)
-#define XGENE_DMA_DESC_RTYPE_SET(m, v) \
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_RTYPE_POS))
-#define XGENE_DMA_DESC_BUFADDR_SET(m, v) \
- (((u64 *)(m))[0] |= (v))
-#define XGENE_DMA_DESC_BUFLEN_SET(m, v)\
- (((u64 *)(m))[0] |= ((u64)(v) << XGENE_DMA_DESC_BUFLEN_POS))
-#define XGENE_DMA_DESC_C_SET(m)\
- (((u64 *)(m))[1] |= XGENE_DMA_DESC_C_BIT)
-#define XGENE_DMA_DESC_FLYBY_SET(m, v) \
- (((u64 *)(m))[2] |= ((v) << XGENE_DMA_DESC_FLYBY_POS))
-#define XGENE_DMA_DESC_MULTI_SET(m, v, i) \
- (((u64 *)(m))[2] |= ((u64)(v) << (((i) + 1) * 8)))
-#define XGENE_DMA_DESC_DR_SET(m) \
- (((u64 *)(m))[2] |= XGENE_DMA_DESC_DR_BIT)
-#define XGENE_DMA_DESC_DST_ADDR_SET(m, v) \
- (((u64 *)(m))[3] |= (v))
-#define XGENE_DMA_DESC_H0ENQ_NUM_SET(m, v) \
- (((u64 *)(m))[3] |= ((u64)(v) << XGENE_DMA_DESC_HOENQ_NUM_POS))
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -158,14 +134,7 @@
(((elerr) << 4) | (lerr))
/* X-Gene DMA descriptor empty s/w signature */
-#define XGENE_DMA_DESC_EMPTY_INDEX 0
#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
-#define XGENE_DMA_DESC_SET_EMPTY(m)\
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] = \
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
-#define XGENE_DMA_DESC_IS_EMPTY(m) \
- (((u64 *)(m))[XGENE_DMA_DESC_EMPTY_INDEX] ==\
-XGENE_DMA_DESC_EMPTY_SIGNATURE)
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
@@ -184,7 +153,7 @@
#define XGENE_DMA_XOR_ALIGNMENT6 /* 64 Bytes */
#define XGENE_DMA_MAX_XOR_SRC 5
#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
-#define XGENE_DMA_INVALID_LEN_CODE 0x7800
+#define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
/* X-Gene DMA descriptor error codes */
#define ERR_DESC_AXI 0x01
@@ -214,10 +183,10 @@
#define ERR_DESC_SRC_INT 0xB
/* X-Gene DMA flyby operation code */
-#define FLYBY_2SRC_XOR 0x8
-#define FLYBY_3SRC_XOR 0x9
-#define FLYBY_4SRC_XOR 0xA
-#define FLYBY_5SRC_XOR 0xB
+#define FLYBY_2SRC_XOR 0x80
+#define FLYBY_3SRC_XOR 0x90
+#define FLYBY_4SRC_XOR 0xA0
+#define FLYBY_5SRC_XOR 0xB0
/* X-Gene DMA SW descriptor flags */
#define XGENE_DMA_FLAG_64B_DESCBIT(0)
@@ -238,10 +207,10 @@
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
struct xgene_dma_desc_hw {
- u64 m0;
- u64 m1;
- u64 m2;
- u64 m3;
+ __le64 m0;
+ __le64 m1;
+ __le64 m2;
+ __le64 m3;
};
enum xgene_dma_ring_cfgsize {
@@ -388,18 +357,11 @@ static bool is_pq_enabled(struct xgene_dma *pdma)
return !(val & XGENE_DMA_PQ_DISABLE_MASK);
}
-static void xgene_dma_cpu_to_le64(u64 *desc, int count)
-{
- int i;
-
- for (i = 0; i < count; i++)
- desc[i] = cpu_to_le64(desc[i]);
-}
-
-static u16 xgene_dma_encode_len(u32 len)
+static u64 xgene_dma_encode_len(size_t len)
{
return (len < XGENE_DMA_MAX_BYTE_CNT) ?
- len : XGENE_DMA_16K_BUFFER_LEN_CODE;
+ ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
+ XGENE_DMA_16K_BUFFER_LEN_CODE;
}
static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
@@ -424,34 +386,50 @@ static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring
*ring)
return XGENE_DMA_RING_DESC_CNT(ring_state);
}
-static void xgene_dma_set_src_buffer(void *ext8, size_t *len,
+static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
[PATCH v1 2/4] dmaengine: xgene-dma: Add support for CRC32C calculation via DMA engine
This patch implements CRC32C support to APM X-Gene SoC DMA engine driver.
Basically we have DMA engine in SoC capable of doing CRC32C calculations.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 317 +---
1 file changed, 302 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index d0a148d..b7c8813 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -22,6 +22,7 @@
*/
#include
+#include
#include
#include
#include
@@ -41,6 +42,7 @@
#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
#define XGENE_DMA_RING_ID_BUF 0x0C
#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
+#define XGENE_DMA_RING_IS_BUFPOOL BIT(20)
#define XGENE_DMA_RING_THRESLD0_SET1 0x30
#define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
#define XGENE_DMA_RING_THRESLD1_SET1 0x34
@@ -70,6 +72,8 @@
(((u32 *)(m))[2] |= (((v) >> 8) << 5))
#define XGENE_DMA_RING_ADDRH_SET(m, v) \
(((u32 *)(m))[3] |= ((v) >> 35))
+#define XGENE_DMA_RING_BUFMODE_SET(m) \
+ (((u32 *)(m))[3] |= ((0x3) << 20))
#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
(((u32 *)(m))[3] |= BIT(19))
#define XGENE_DMA_RING_SIZE_SET(m, v) \
@@ -107,6 +111,7 @@
#define XGENE_DMA_RING_INT2_MASK 0x90B0
#define XGENE_DMA_RING_INT3_MASK 0x90B8
#define XGENE_DMA_RING_INT4_MASK 0x90C0
+#define XGENE_DMA_CFG_RING_FQ_ASSOC0x90DC
#define XGENE_DMA_CFG_RING_WQ_ASSOC0x90E0
#define XGENE_DMA_ASSOC_RING_MNGR1 0x
#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
@@ -128,6 +133,10 @@
#define XGENE_DMA_DESC_LERR_POS60
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
+#define XGENE_DMA_DESC_BD_BIT BIT(0)
+#define XGENE_DMA_DESC_SD_BIT BIT(1)
+#define XGENE_DMA_DESC_CRCSEED_POS 8
+#define XGENE_DMA_DESC_FPQ_NUM_POS 32
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -141,21 +150,26 @@
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
#define XGENE_DMA_BUFNUM 0x0
+#define XGENE_DMA_BUFPOOL_BUFNUM 0x20
#define XGENE_DMA_CPU_BUFNUM 0x18
#define XGENE_DMA_RING_OWNER_DMA 0x03
#define XGENE_DMA_RING_OWNER_CPU 0x0F
#define XGENE_DMA_RING_TYPE_REGULAR0x01
+#define XGENE_DMA_RING_TYPE_BUFPOOL0x02
#define XGENE_DMA_RING_WQ_DESC_SIZE32 /* 32 Bytes */
+#define XGENE_DMA_BUFPOOL_DESC_SIZE16 /* 16 Bytes */
#define XGENE_DMA_RING_NUM_CONFIG 5
#define XGENE_DMA_MAX_CHANNEL 4
#define XGENE_DMA_XOR_CHANNEL 0
#define XGENE_DMA_PQ_CHANNEL 1
+#define XGENE_DMA_FLYBY_CHANNEL2
#define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
#define XGENE_DMA_MAX_64B_DESC_BYTE_CNT0x14000 /* 80 KB */
#define XGENE_DMA_XOR_ALIGNMENT6 /* 64 Bytes */
#define XGENE_DMA_MAX_XOR_SRC 5
#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
#define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT 0x7FFF /* (32 KB - 1) */
/* X-Gene DMA descriptor error codes */
#define ERR_DESC_AXI 0x01
@@ -189,9 +203,14 @@
#define FLYBY_3SRC_XOR 0x90
#define FLYBY_4SRC_XOR 0xA0
#define FLYBY_5SRC_XOR 0xB0
+#define FLYBY_CRC160x10
+#define FLYBY_ISCSI_CRC32C 0x20
+#define FLYBY_CRC320x30
+#define FLYBY_CHECKSUM 0x40
/* X-Gene DMA SW descriptor flags */
#define XGENE_DMA_FLAG_64B_DESCBIT(0)
+#define XGENE_DMA_FLAG_FLYBY_ACTIVEBIT(1)
/* Define to dump X-Gene DMA descriptor */
#define XGENE_DMA_DESC_DUMP(desc, m) \
@@ -208,6 +227,11 @@
#define chan_err(chan, fmt, arg...)\
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
+struct xgene_dma_desc16 {
+ __le64 m0;
+ __le64 m1;
+};
+
struct xgene_dma_desc_hw {
__le64 m0;
__le64 m1;
@@ -234,6 +258,7 @@ struct xgene_dma_ring {
u16 slots;
u16 dst_ring_num;
u32 size;
+ bool is_bufpool;
void __iomem *cmd;
void __iomem *cmd_base;
dma_addr_t desc_paddr;
@@ -241,6 +266,7 @@ struct xgene_dma_ring {
enum xgene_dma_ring_cfgsize cfgsize;
union {
void *desc_vaddr;
+ struct xgene_dma_desc16 *desc16;
struct xgene_dma_desc_hw *desc_hw;
};
};
@@ -249,6 +275,7 @@ struct xgene_dma_desc_sw
[PATCH v1 4/4] Crypto: tcrypt: Add test case for APM X-Gene SoC CRC32C algo
This patch adds test case for APM X-Gene SoC CRC32C algorithm.
Signed-off-by: Rameshwar Prasad Sahu
---
crypto/tcrypt.c | 4
crypto/testmgr.c | 9 +
2 files changed, 13 insertions(+)
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 9f6f10b..0bbb1e2 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -1465,6 +1465,10 @@ static int do_test(const char *alg, u32 type, u32 mask,
int m)
ret += tcrypt_test("crct10dif");
break;
+ case 48:
+ ret += tcrypt_test("xgene(crc32c)");
+ break;
+
case 100:
ret += tcrypt_test("hmac(md5)");
break;
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index d0a42bd..a65860e 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -3748,6 +3748,15 @@ static const struct alg_test_desc alg_test_descs[] = {
}
}
}, {
+ .alg = "xgene(crc32c)",
+ .test = alg_test_hash,
+ .suite = {
+ .hash = {
+ .vecs = crc32c_tv_template,
+ .count = CRC32C_TEST_VECTORS
+ }
+ }
+ }, {
.alg = "xts(aes)",
.test = alg_test_skcipher,
.fips_allowed = 1,
--
1.8.2.1
--
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[PATCH v1 0/4] Crypto: tcrypt: Add test case for APM X-Gene SoC CRC32C algo
This patch adds test case for APM X-Gene SoC CRC32C algorithm. Signed-off-by: Rameshwar Prasad Sahu --- Rameshwar Prasad Sahu (4): dmaengine: Add support for new feature CRC32C dmaengine: xgene-dma: Add support for CRC32C calculation via DMA engine Crypto: Add support for APM X-Gene SoC CRC32C h/w accelerator driver Crypto: tcrypt: Add test case for APM X-Gene SoC CRC32C algo crypto/tcrypt.c | 4 + crypto/testmgr.c | 9 ++ drivers/crypto/Kconfig| 8 ++ drivers/crypto/Makefile | 1 + drivers/crypto/xgene-crc32c.c | 244 drivers/dma/dmaengine.c | 2 + drivers/dma/xgene-dma.c | 317 -- include/linux/dmaengine.h | 5 + 8 files changed, 575 insertions(+), 15 deletions(-) create mode 100755 drivers/crypto/xgene-crc32c.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/4] dmaengine: Add support for new feature CRC32C
This patch adds support for new feature CRC32C calculation in
dmaengine framework.
Signed-of-by: Rameshwar Prasad Sahu
---
drivers/dma/dmaengine.c | 2 ++
include/linux/dmaengine.h | 5 +
2 files changed, 7 insertions(+)
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 4a4cce1..55ba799 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -853,6 +853,8 @@ int dma_async_device_register(struct dma_device *device)
!device->device_prep_dma_cyclic);
BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
!device->device_prep_interleaved_dma);
+ BUG_ON(dma_has_cap(DMA_CRC32C, device->cap_mask) &&
+ !device->device_prep_dma_crc32c);
BUG_ON(!device->device_tx_status);
BUG_ON(!device->device_issue_pending);
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index e2f5eb4..9da70b6 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -73,6 +73,7 @@ enum dma_transaction_type {
DMA_SLAVE,
DMA_CYCLIC,
DMA_INTERLEAVE,
+ DMA_CRC32C,
/* last transaction type for creation of the capabilities mask */
DMA_TX_TYPE_END,
};
@@ -622,6 +623,7 @@ struct dma_tx_state {
* The function takes a buffer of size buf_len. The callback function will
* be called after period_len bytes have been transferred.
* @device_prep_interleaved_dma: Transfer expression in a generic way.
+ * @device_prep_dma_crc32c: prepares a crc32c operation
* @device_config: Pushes a new configuration to a channel, return 0 or an
error
* code
* @device_pause: Pauses any transfer happening on a channel. Returns
@@ -701,6 +703,9 @@ struct dma_device {
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
struct dma_chan *chan, struct dma_interleaved_template *xt,
unsigned long flags);
+ struct dma_async_tx_descriptor *(*device_prep_dma_crc32c)(
+ struct dma_chan *chan, struct scatterlist *src_sg, size_t len,
+ unsigned int seed, u8 *result, unsigned long flags);
int (*device_config)(struct dma_chan *chan,
struct dma_slave_config *config);
--
1.8.2.1
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[PATCH v1 3/4] Crypto: Add support for APM X-Gene SoC CRC32C h/w accelerator driver
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator.
DMA engine in APM X-Gene SoC is capable of doing CRC32C calculations.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/crypto/Kconfig| 8 ++
drivers/crypto/Makefile | 1 +
drivers/crypto/xgene-crc32c.c | 244 ++
3 files changed, 253 insertions(+)
create mode 100755 drivers/crypto/xgene-crc32c.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4044125..bd6eff5 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -480,4 +480,12 @@ config CRYPTO_DEV_IMGTEC_HASH
hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
hashing algorithms.
+config CRYPTO_DEV_XGENE_CRC32C
+ tristate "Support for APM SoC X-Gene CRC32C HW accelerator"
+ depends on XGENE_DMA
+ select CRYPTO_HASH
+ help
+ This option enables support for CRC32C offload by using
+ APM X-Gene SoC DMA engine.
+
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index e35c07a..2cc3f4f 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
+obj-$(CONFIG_CRYPTO_DEV_XGENE_CRC32C) += xgene-crc32c.o
diff --git a/drivers/crypto/xgene-crc32c.c b/drivers/crypto/xgene-crc32c.c
new file mode 100755
index 000..c0a483b
--- /dev/null
+++ b/drivers/crypto/xgene-crc32c.c
@@ -0,0 +1,244 @@
+/*
+ * Applied Micro X-Gene SoC CRC32C HW acceleration by using DMA engine
+ *
+ * Copyright (c) 2015, Applied Micro Circuits Corporation
+ * Authors: Rameshwar Prasad Sahu
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CRC32C_DIGEST_SIZE 4
+#define CRC32C_BLOCK_SIZE 1
+#define XGENE_DMA_MAX_FLYBY_SRC_CNT5
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT 0x7FFF /* (32 KB - 1) */
+
+struct xgene_crc32c_session_ctx {
+ struct dma_chan *dchan;
+ u32 key;
+};
+
+struct xgene_crc32c_reqctx {
+ struct device *dev;
+ u32 nents;
+ u32 seed;
+};
+
+static void xgene_crc32c_callback(void *ctx)
+{
+ struct ahash_request *req = ctx;
+ struct xgene_crc32c_reqctx *reqctx = ahash_request_ctx(req);
+
+ if (req->base.complete)
+ req->base.complete(&req->base, 0);
+
+ dma_unmap_sg(reqctx->dev, req->src,
+reqctx->nents, DMA_TO_DEVICE);
+}
+
+static int xgene_crc32c_handle_req(struct ahash_request *req,
+ struct dma_chan *dchan)
+{
+ struct xgene_crc32c_reqctx *reqctx = ahash_request_ctx(req);
+ struct device *dev = dchan->device->dev;
+ struct dma_async_tx_descriptor *tx;
+ enum dma_ctrl_flags flags;
+ u32 nents, sg_count;
+ dma_cookie_t cookie;
+
+ if (req->nbytes > XGENE_DMA_MAX_FLYBY_BYTE_CNT) {
+ dev_err(dev, "Src len is too long 0x%X\n", req->nbytes);
+ return -EINVAL;
+ }
+
+ nents = sg_nents(req->src);
+ sg_count = dma_map_sg(dev, req->src, nents, DMA_TO_DEVICE);
+ if (!sg_count) {
+ dev_err(dev, "Failed to map src sg");
+ return -ENOMEM;
+ }
+
+ if (sg_count > XGENE_DMA_MAX_FLYBY_SRC_CNT) {
+ dev_err(dev, "Unsupported src sg len\n");
+ goto err;
+ }
+
+ flags = DMA_CTRL_ACK;
+
+ tx = dchan->device->device_prep_dma_crc32c(dchan, req->src,
+ req->nbytes,
+ reqctx->seed,
+ req->result,
+ flags);
+ if (!tx)
+ goto err;
+
+ /* Set callback parameters */
+ reqctx->dev = dev;
+ reqctx->nents = nents;
+ tx->callback_param = req;
+ tx->callback = xgene_crc32c_callback;
+
+ cookie = tx->tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+
[PATCH v1 0/4] dmaengine: Add supports for APM X-Gene SoC CRC32C accerlerator driver
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator driver and adds CRC32C support in dmaengine framework. APM X-Gene SoC has DMA engine capable of performing CRC32C. Signed-off-by: Rameshwar Prasad Sahu --- Rameshwar Prasad Sahu (4): dmaengine: Add support for new feature CRC32C dmaengine: xgene-dma: Add support for CRC32C calculation via DMA engine Crypto: Add support for APM X-Gene SoC CRC32C h/w accelerator driver Crypto: tcrypt: Add test case for APM X-Gene SoC CRC32C algo crypto/tcrypt.c | 4 + crypto/testmgr.c | 9 ++ drivers/crypto/Kconfig| 8 ++ drivers/crypto/Makefile | 1 + drivers/crypto/xgene-crc32c.c | 244 drivers/dma/dmaengine.c | 2 + drivers/dma/xgene-dma.c | 317 -- include/linux/dmaengine.h | 5 + 8 files changed, 575 insertions(+), 15 deletions(-) create mode 100755 drivers/crypto/xgene-crc32c.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] dmaengine: xgene-dma: Fix holding lock while calling tx callback in cleanup path
This patch fixes the an locking issue where client callback performs
further submission.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index d1c8809..0b82bc0 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -763,12 +763,17 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
struct xgene_dma_ring *ring = &chan->rx_ring;
struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
struct xgene_dma_desc_hw *desc_hw;
+ struct list_head ld_completed;
u8 status;
+ INIT_LIST_HEAD(&ld_completed);
+
+ spin_lock_bh(&chan->lock);
+
/* Clean already completed and acked descriptors */
xgene_dma_clean_completed_descriptor(chan);
- /* Run the callback for each descriptor, in order */
+ /* Move all completed descriptors to ld completed queue, in order */
list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
/* Get subsequent hw descriptor from DMA rx ring */
desc_hw = &ring->desc_hw[ring->head];
@@ -811,15 +816,17 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
/* Mark this hw descriptor as processed */
desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
- xgene_dma_run_tx_complete_actions(chan, desc_sw);
-
- xgene_dma_clean_running_descriptor(chan, desc_sw);
-
/*
* Decrement the pending transaction count
* as we have processed one
*/
chan->pending--;
+
+ /*
+* Delete this node from ld running queue and append it to
+* ld completed queue for further processing
+*/
+ list_move_tail(&desc_sw->node, &ld_completed);
}
/*
@@ -828,6 +835,14 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
* ahead and free the descriptors below.
*/
xgene_chan_xfer_ld_pending(chan);
+
+ spin_unlock_bh(&chan->lock);
+
+ /* Run the callback for each descriptor, in order */
+ list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
+ xgene_dma_run_tx_complete_actions(chan, desc_sw);
+ xgene_dma_clean_running_descriptor(chan, desc_sw);
+ }
}
static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
@@ -876,11 +891,11 @@ static void xgene_dma_free_chan_resources(struct dma_chan
*dchan)
if (!chan->desc_pool)
return;
- spin_lock_bh(&chan->lock);
-
/* Process all running descriptor */
xgene_dma_cleanup_descriptors(chan);
+ spin_lock_bh(&chan->lock);
+
/* Clean all link descriptor queues */
xgene_dma_free_desc_list(chan, &chan->ld_pending);
xgene_dma_free_desc_list(chan, &chan->ld_running);
@@ -1200,15 +1215,11 @@ static void xgene_dma_tasklet_cb(unsigned long data)
{
struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
- spin_lock_bh(&chan->lock);
-
/* Run all cleanup for descriptors which have been completed */
xgene_dma_cleanup_descriptors(chan);
/* Re-enable DMA channel IRQ */
enable_irq(chan->rx_irq);
-
- spin_unlock_bh(&chan->lock);
}
static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
--
1.8.2.1
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[PATCH] dmaengine: xgene-dma: Add ACPI support for X-Gene DMA engine driver
This patch adds ACPI support for the APM X-Gene DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index dff22ab..d0a148d 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -21,6 +21,7 @@
* NOTE: PM support is currently not available.
*/
+#include
#include
#include
#include
@@ -1944,16 +1945,18 @@ static int xgene_dma_probe(struct platform_device *pdev)
return ret;
pdma->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(pdma->clk)) {
+ if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
dev_err(&pdev->dev, "Failed to get clk\n");
return PTR_ERR(pdma->clk);
}
/* Enable clk before accessing registers */
- ret = clk_prepare_enable(pdma->clk);
- if (ret) {
- dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
- return ret;
+ if (!IS_ERR(pdma->clk)) {
+ ret = clk_prepare_enable(pdma->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
+ return ret;
+ }
}
/* Remove DMA RAM out of shutdown */
@@ -1998,7 +2001,8 @@ err_request_irq:
err_dma_mask:
err_clk_enable:
- clk_disable_unprepare(pdma->clk);
+ if (!IS_ERR(pdma->clk))
+ clk_disable_unprepare(pdma->clk);
return ret;
}
@@ -2022,11 +2026,20 @@ static int xgene_dma_remove(struct platform_device
*pdev)
xgene_dma_delete_chan_rings(chan);
}
- clk_disable_unprepare(pdma->clk);
+ if (!IS_ERR(pdma->clk))
+ clk_disable_unprepare(pdma->clk);
return 0;
}
+#ifdef CONFIG_ACPI
+static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
+ {"APMC0D43", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
+#endif
+
static const struct of_device_id xgene_dma_of_match_ptr[] = {
{.compatible = "apm,xgene-storm-dma",},
{},
@@ -2039,6 +2052,7 @@ static struct platform_driver xgene_dma_driver = {
.driver = {
.name = "X-Gene-DMA",
.of_match_table = xgene_dma_of_match_ptr,
+ .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
},
};
--
1.8.2.1
--
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[PATCH v6 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gather memory copy. v6 changes: 1. Maintained sw queue for pending, running, and completed requests. Used link list as queue. 2. Fixed issue_pending and tx_submit routines. 3. Fixed prep_dma routines. 4. Fixed free_irqs. v5 changes: 1. Minor changes in coding style. 2. Added DMA_CTRL_ACK flag initialization v4 changes: 1. Fixed dma-ranges property on DTS. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1738 5 files changed, 1822 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100755 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..cfbdcdb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd_csr": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd_csr";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter-gather memory copy offloading. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1738 +++ 3 files changed, 1747 insertions(+) create mode 100755 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index a874b6e..0e05831 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -425,6 +425,14 @@ config IMG_MDC_DMA help Enable support for the IMG multi-threaded DMA controller (MDC). +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f915f61..06c1576 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100755 index 000..e736c2e --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1738 @@ +/* + * Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2015, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * NOTE: PM support is currently not available. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define DMA_RING_CONFIG0x04 +#define DMA_RING_ENABLEBIT(31) +#define DMA_RING_ID0x08 +#define DMA_RING_ID_SETUP(v) ((v) | BIT(31)) +#define DMA_RING_ID_BUF0x0C +#define DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define DMA_RING_THRESLD0_SET1 0x30 +#define DMA_RING_THRESLD0_SET1_VAL 0X64 +#define DMA_RING_THRESLD1_SET1 0x34 +#define DMA_RING_THRESLD1_SET1_VAL 0xC8 +#define DMA_RING_HYSTERESIS0x68 +#define DMA_RING_HYSTERESIS_VAL0x +#define DMA_RING_STATE 0x6C +#define DMA_RING_STATE_WR_BASE 0x70 +#define DMA_RING_NE_INT_MODE 0x017C +#define DMA_RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define DMA_RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define DMA_RING_CLKEN 0xC208 +#define DMA_RING_SRST 0xC200 +#define DMA_RING_MEM_RAM_SHUTDOWN 0xD070 +#define DMA_RING_BLK_MEM_RDY 0xD074 +#define DMA_RING_BLK_MEM_RDY_VAL 0x +#define DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1) +#define DMA_RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define DMA_RING_DST_ID(v) ((1 << 10) | (v)) +#define DMA_RING_CMD_OFFSET0x2C +#define DMA_RING_CMD_BASE_OFFSET(v)((v) << 6) +#define DMA_RING_COHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define DMA_RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define DMA_RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define DMA_RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define DMA_RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define DMA_RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define DMA_RING_RECOMTIMEOUTL_SET(m) (((u32 *)(m))[3] |= (0x7 << 28)) +#define DMA_RING_RECOMTIMEOUTH_SET(m) (((u32 *)(m))[4] |= 0x3) +#define DMA_RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define DMA_RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) + +/* DMA device csr registers and
[PATCH v6 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..5bf39f3 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
@@ -352,6 +353,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +666,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd_csr";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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[PATCH v7 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gather memory copy, raid5 xor and raid6 p+q. v7 changes: 1. Added raid5 xor offload support. 2. Added raid6 p+q offload support. v6 changes: 1. Maintained sw queue for pending, running, and completed requests. Used link list as queue. 2. Fixed issue_pending and tx_submit routines. 3. Fixed prep_dma routines. 4. Fixed free_irqs. v5 changes: 1. Minor changes in coding style. 2. Added DMA_CTRL_ACK flag initialization v4 changes: 1. Fixed dma-ranges property on DTS. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 47 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 + drivers/dma/Kconfig|9 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 2156 5 files changed, 2239 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100755 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..9471770 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
@@ -352,6 +353,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +666,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-storm-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1054a000 0x0 0x100>;
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v7 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy, scatter-gather memory copy, raid5 xor, and raid6 p+q offloading. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |9 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 2156 +++ 3 files changed, 2166 insertions(+) create mode 100755 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index a874b6e..22c20cb 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -425,6 +425,15 @@ config IMG_MDC_DMA help Enable support for the IMG multi-threaded DMA controller (MDC). +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select DMA_ENGINE_RAID + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f915f61..06c1576 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100755 index 000..b0a86dce --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,2156 @@ +/* + * Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2015, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * NOTE: PM support is currently not available. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define DMA_RING_CONFIG0x04 +#define DMA_RING_ENABLEBIT(31) +#define DMA_RING_ID0x08 +#define DMA_RING_ID_SETUP(v) ((v) | BIT(31)) +#define DMA_RING_ID_BUF0x0C +#define DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define DMA_RING_THRESLD0_SET1 0x30 +#define DMA_RING_THRESLD0_SET1_VAL 0X64 +#define DMA_RING_THRESLD1_SET1 0x34 +#define DMA_RING_THRESLD1_SET1_VAL 0xC8 +#define DMA_RING_HYSTERESIS0x68 +#define DMA_RING_HYSTERESIS_VAL0x +#define DMA_RING_STATE 0x6C +#define DMA_RING_STATE_WR_BASE 0x70 +#define DMA_RING_NE_INT_MODE 0x017C +#define DMA_RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define DMA_RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define DMA_RING_CLKEN 0xC208 +#define DMA_RING_SRST 0xC200 +#define DMA_RING_MEM_RAM_SHUTDOWN 0xD070 +#define DMA_RING_BLK_MEM_RDY 0xD074 +#define DMA_RING_BLK_MEM_RDY_VAL 0x +#define DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1) +#define DMA_RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define DMA_RING_DST_ID(v) ((1 << 10) | (v)) +#define DMA_RING_CMD_OFFSET0x2C +#define DMA_RING_CMD_BASE_OFFSET(v)((v) << 6) +#define DMA_RING_COHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define DMA_RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define DMA_RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define DMA_RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define DMA_RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define DMA_RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define DMA_RING_RECOMTIMEOUTL_SET(m) (((u32 *)(m))[3] |= (0x7 << 28)) +#define DMA_RING_RECOMTIMEOUTH_SET(m) (((u32 *)(m))[4] |= 0x3) +#define DMA_RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define DMA_RING_TYPE_SET(m, v)(((u32
[PATCH v7 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 47 ++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..d305876
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,47 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the following order:
+ 1st - DMA control and status register address space.
+ 2nd - Descriptor ring control and status register address space.
+ 3rd - Descriptor ring command register address space.
+ 4th - Soc efuse register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-storm-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1054a000 0x0 0x100>;
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 2/3] arm64: dts: Add APM X-Gene SoC DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..9471770 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
@@ -352,6 +353,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +666,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-storm-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1054a000 0x0 0x100>;
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gather memory copy, raid5 xor and raid6 p+q. v8 changes: 1. Fixed macro namespace issues. 2. Fixed tx status check issues. v7 changes: 1. Added raid5 xor offload support. 2. Added raid6 p+q offload support. v6 changes: 1. Maintained sw queue for pending, running, and completed requests. Used link list as queue. 2. Fixed issue_pending and tx_submit routines. 3. Fixed prep_dma routines. 4. Fixed free_irqs. v5 changes: 1. Minor changes in coding style. 2. Added DMA_CTRL_ACK flag initialization v4 changes: 1. Fixed dma-ranges property on DTS. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene SoC DMA device and DMA clock DTS nodes Documentation: dma: Add documentation for the APM X-Gene SoC DMA device DTS binding .../devicetree/bindings/dma/apm-xgene-dma.txt | 47 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 2090 5 files changed, 2172 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100755 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v8 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy, scatter-gather memory copy, raid5 xor, and raid6 p+q offloading. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 2090 +++ 3 files changed, 2099 insertions(+) create mode 100755 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index a874b6e..a271346 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -425,6 +425,14 @@ config IMG_MDC_DMA help Enable support for the IMG multi-threaded DMA controller (MDC). +config XGENE_DMA + tristate "APM X-Gene DMA support" + select DMA_ENGINE + select DMA_ENGINE_RAID + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f915f61..06c1576 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -51,3 +51,4 @@ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100755 index 000..2383528 --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,2090 @@ +/* + * Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2015, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * NOTE: PM support is currently not available. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* X-Gene DMA ring csr registers and bit definations */ +#define XGENE_DMA_RING_CONFIG 0x04 +#define XGENE_DMA_RING_ENABLE BIT(31) +#define XGENE_DMA_RING_ID 0x08 +#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31)) +#define XGENE_DMA_RING_ID_BUF 0x0C +#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define XGENE_DMA_RING_THRESLD0_SET1 0x30 +#define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64 +#define XGENE_DMA_RING_THRESLD1_SET1 0x34 +#define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8 +#define XGENE_DMA_RING_HYSTERESIS 0x68 +#define XGENE_DMA_RING_HYSTERESIS_VAL 0x +#define XGENE_DMA_RING_STATE 0x6C +#define XGENE_DMA_RING_STATE_WR_BASE 0x70 +#define XGENE_DMA_RING_NE_INT_MODE 0x017C +#define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define XGENE_DMA_RING_CLKEN 0xC208 +#define XGENE_DMA_RING_SRST0xC200 +#define XGENE_DMA_RING_MEM_RAM_SHUTDOWN0xD070 +#define XGENE_DMA_RING_BLK_MEM_RDY 0xD074 +#define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0x +#define XGENE_DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1) +#define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num)) +#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v)) +#define XGENE_DMA_RING_CMD_OFFSET 0x2C +#define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6) +#define XGENE_DMA_RING_COHERENT_SET(m) \ + (((u32 *)(m))[2] |= BIT(4)) +#define XGENE_DMA_RING_ADDRL_SET(m, v) \ + (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define XGENE_DMA_RING_ADDRH_SET(m, v) \ + (((u32 *)(m))[3] |= ((v) >> 35)) +#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \ + (((u32 *)(m))[3] |= BIT(19)) +#define XGENE_DMA_RING_SIZE_SET(m, v) \ + (((u32 *)(m))[3] |= ((v) << 23)) +#define XGENE_DMA_RING_RECOMBBUF_SET(m)\ + (((u32 *)(m))[3] |= BIT(27)) +#defin
[PATCH v8 3/3] Documentation: dma: Add documentation for the APM X-Gene SoC DMA device DTS binding
This patch adds documentation for the APM X-Gene SoC DMA device DTS binding
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 47 ++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..d305876
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,47 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the following order:
+ 1st - DMA control and status register address space.
+ 2nd - Descriptor ring control and status register address space.
+ 3rd - Descriptor ring command register address space.
+ 4th - Soc efuse register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-storm-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1054a000 0x0 0x100>;
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gathering. v5 changes: 1. Minor changes in coding style. 2. Added DMA_CTRL_ACK flag initialization v4 changes: 1. Fixed dma-ranges property on DTS. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1597 5 files changed, 1681 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100755 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..5bf39f3 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
@@ -352,6 +353,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +666,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd_csr";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..cfbdcdb
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd_csr": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd_csr";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1597 +++ 3 files changed, 1606 insertions(+) create mode 100755 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100755 index 000..0736a51 --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1597 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_CONFIG0x04 +#define RING_ENABLEBIT(31) +#define RING_ID0x08 +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF0x0C +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_THRESLD0_SET1 0x30 +#define RING_THRESLD0_SET1_VAL 0X64 +#define RING_THRESLD1_SET1 0x34 +#define RING_THRESLD1_SET1_VAL 0xC8 +#define RING_HYSTERESIS0x68 +#define RING_HYSTERESIS_VAL0x +#define RING_STATE 0x6C +#define RING_STATE_WR_BASE 0x70 +#define RING_NE_INT_MODE 0x017C +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define RING_CLKEN 0xC208 +#define RING_SRST 0xC200 +#define RING_MEM_RAM_SHUTDOWN 0xD070 +#define RING_BLK_MEM_RDY 0xD074 +#define RING_BLK_MEM_RDY_VAL 0x +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_COHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RING_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) + +/* DMA device csr registers and bit definitions */ +#define DMA_IPBRR 0x0 +#define DMA_DEV_ID_RD(v) ((v) & 0x0FFF) +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_GCR0x10 +#define DMA_CH_SETUP(m)((m) = ((m) & ~0x000F) | 0x000AAFFF) +#define DMA_ENABLE(m) ((m) = ((m) & ~BIT(31)) | BIT(31)) +#define DMA_INT
[PATCH v4 3/3] Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000..c661cc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,49 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+ It contains the information of registers in the same order
+ as described by reg-names.
+- reg-names: Should contain the register set names.
+ - "dma_csr": DMA control and status register address space.
+ - "ring_csr": Descriptor ring control and status register
+address space.
+ - "ring_cmd": Descriptor ring command register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+ DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+ are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>,
+<0x0 0x82 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
--
1.8.2.1
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/3] arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu
Signed-off-by: Loc Ho
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f1ad9c2..1c0c8ca 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -102,6 +102,7 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
clocks {
#address-cells = <2>;
@@ -352,6 +353,15 @@
reg-names = "csr-reg";
clock-output-names = "pcie4clk";
};
+
+ dmaclk: dmaclk@1f27c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f27c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
};
pcie0: pcie@1f2b {
@@ -656,5 +666,21 @@
interrupts = <0x0 0x41 0x4>;
clocks = <&rngpkaclk 0>;
};
+
+ dma: dma@1f27 {
+ compatible = "apm,xgene-dma";
+ device_type = "dma";
+ reg = <0x0 0x1f27 0x0 0x1>,
+ <0x0 0x1f20 0x0 0x1>,
+ <0x0 0x1b008000 0x0 0x2000>;
+ reg-names = "dma_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x82 0x4>,
+<0x0 0xb8 0x4>,
+<0x0 0xb9 0x4>,
+<0x0 0xba 0x4>,
+<0x0 0xbb 0x4>;
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
};
};
--
1.8.2.1
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[PATCH v4 1/3] dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy and scatter gathering offload. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- drivers/dma/Kconfig |8 + drivers/dma/Makefile|1 + drivers/dma/xgene-dma.c | 1566 +++ 3 files changed, 1575 insertions(+) create mode 100644 drivers/dma/xgene-dma.c diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index f2b2c4e..251ce60 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -416,6 +416,14 @@ config NBPFAXI_DMA help Support for "Type-AXI" NBPF DMA IPs from Renesas +config XGENE_DMA + tristate "APM X-Gene DMA support" + depends on ARCH_XGENE + select DMA_ENGINE + select ASYNC_TX_ENABLE_CHANNEL_SWITCH + help + Enable support for the APM X-Gene SoC DMA engine. + config DMA_ENGINE bool diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 2022b54..0567e69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -50,3 +50,4 @@ obj-y += xilinx/ obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o +obj-$(CONFIG_XGENE_DMA) += xgene-dma.o diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c new file mode 100644 index 000..3cc622c --- /dev/null +++ b/drivers/dma/xgene-dma.c @@ -0,0 +1,1566 @@ +/* Applied Micro X-Gene SoC DMA engine Driver + * + * Copyright (c) 2014, Applied Micro Circuits Corporation + * Authors: Rameshwar Prasad Sahu + * Loc Ho + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +/* DMA ring csr registers and bit definations */ +#define RING_CONFIG0x04 +#define RING_ENABLEBIT(31) +#define RING_ID0x08 +#define RING_ID_SETUP(v) ((v) | BIT(31)) +#define RING_ID_BUF0x0C +#define RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) +#define RING_THRESLD0_SET1 0x30 +#define RING_THRESLD0_SET1_VAL 0X64 +#define RING_THRESLD1_SET1 0x34 +#define RING_THRESLD1_SET1_VAL 0xC8 +#define RING_HYSTERESIS0x68 +#define RING_HYSTERESIS_VAL0x +#define RING_STATE 0x6C +#define RING_STATE_WR_BASE 0x70 +#define RING_NE_INT_MODE 0x017C +#define RING_NE_INT_MODE_SET(m, v) \ + ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) +#define RING_NE_INT_MODE_RESET(m, v) \ + ((m) &= (~BIT(31 - (v +#define RING_CLKEN 0xC208 +#define RING_SRST 0xC200 +#define RING_MEM_RAM_SHUTDOWN 0xD070 +#define RING_BLK_MEM_RDY 0xD074 +#define RING_BLK_MEM_RDY_VAL 0x +#define RING_ID_GET(owner, num)(((owner) << 6) | (num)) +#define RING_DST_RING_ID(v)((1 << 10) | (v)) +#define RING_CMD_OFFSET(v) (((v) << 6) + 0x2C) +#define RING_NUM_CONFIG5 +#define RING_QCOHERENT_SET(m) (((u32 *)(m))[2] |= BIT(4)) +#define RING_ADDRL_SET(m, v) (((u32 *)(m))[2] |= (((v) >> 8) << 5)) +#define RING_ADDRH_SET(m, v) (((u32 *)(m))[3] |= ((v) >> 35)) +#define RING_ACCEPTLERR_SET(m) (((u32 *)(m))[3] |= BIT(19)) +#define RING_SIZE_SET(m, v)(((u32 *)(m))[3] |= ((v) << 23)) +#define RING_RECOMBBUF_SET(m) (((u32 *)(m))[3] |= BIT(27)) +#define RING_RECOMTIMEOUTL_SET(m) \ + (((u32 *)(m))[3] |= (0x7 << 28)) +#define RINNG_RECOMTIMEOUTH_SET(m) \ + (((u32 *)(m))[4] |= 0x3) +#define RING_SELTHRSH_SET(m) (((u32 *)(m))[4] |= BIT(3)) +#define RING_TYPE_SET(m, v)(((u32 *)(m))[4] |= ((v) << 19)) + +/* DMA device csr registers and bit definitions */ +#define DMA_IPBRR 0x0 +#define DMA_BUS_ID_RD(v) (((v) >> 12) & 3) +#define DMA_REV_NO_RD(v) (((v) >> 14) & 3) +#define DMA_DEVICE_ID_RD(v)((v) & 0x0FFF) +#define DMA_GCR0x10 +#define DMA_CH_SETUP(m)((m) = ((m) & ~0x000F) | 0x000AAFFF) +#define DMA_ENABLE(m) ((m) = ((m) & ~B
[PATCH v4 0/3] dmaengine: APM X-Gene SoC DMA engine driver support
This patch set implements the APM X-Gene SoC DMA driver support to offload the DMA operations such as memory copy(memcpy), scatter gathering. v4 changes: 1. Fixed dma-ranges property on DTS. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Loc Ho --- Rameshwar Prasad Sahu (3): dmaengine: Add support for APM X-Gene SoC DMA engine driver arm64: dts: Add APM X-Gene DMA device and DMA clock DTS nodes Documentation: dma: Add APM X-Gene SoC DMA engine driver documentation .../devicetree/bindings/dma/apm-xgene-dma.txt | 49 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 + drivers/dma/Kconfig|8 + drivers/dma/Makefile |1 + drivers/dma/xgene-dma.c| 1566 5 files changed, 1650 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/apm-xgene-dma.txt create mode 100644 drivers/dma/xgene-dma.c -- 1.8.2.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/3] dmaengine: Add supports for APM X-Gene SoC CRC32C accerlerator driver
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator driver and adds CRC32C computations support in dmaengine framework. APM X-Gene SoC has DMA engine capable of performing CRC32C computations. v2 changes: 1. Added helper function in dmaengine framework 2. Documented CRC32C support in Documentations/dmaengine/provider.txt 3. Fixed algo name 4. Fixed coding style issues Signed-off-by: Rameshwar Prasad Sahu --- Rameshwar Prasad Sahu (3): dmaengine: Add support for new feature CRC32C computations dmaengine: xgene-dma: Add support for CRC32C computations via DMA engine Crypto: Add support for APM X-Gene SoC CRC32C h/w accelerator driver Documentation/dmaengine/provider.txt |3 + drivers/crypto/Kconfig |8 + drivers/crypto/Makefile |1 + drivers/crypto/xgene-crc32c.c| 234 + drivers/dma/dmaengine.c |2 + drivers/dma/xgene-dma.c | 314 -- include/linux/dmaengine.h| 13 ++ 7 files changed, 560 insertions(+), 15 deletions(-) create mode 100755 drivers/crypto/xgene-crc32c.c -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/3] dmaengine: Add support for new feature CRC32C computations
This patch adds support for new feature CRC32C computations in
dmaengine framework.
Signed-of-by: Rameshwar Prasad Sahu
---
Documentation/dmaengine/provider.txt |3 +++
drivers/dma/dmaengine.c |2 ++
include/linux/dmaengine.h| 13 +
3 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/Documentation/dmaengine/provider.txt
b/Documentation/dmaengine/provider.txt
index 67d4ce4..2399d6f 100644
--- a/Documentation/dmaengine/provider.txt
+++ b/Documentation/dmaengine/provider.txt
@@ -224,6 +224,9 @@ Currently, the types available are:
want to transfer a portion of uncompressed data directly to the
display to print it
+ * DMA_CRC32C
+- The device is able to perform CRC32C computations
+
These various types will also affect how the source and destination
addresses change over time.
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index 09479d4..8cd0365 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -865,6 +865,8 @@ int dma_async_device_register(struct dma_device *device)
!device->device_prep_dma_cyclic);
BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
!device->device_prep_interleaved_dma);
+ BUG_ON(dma_has_cap(DMA_CRC32C, device->cap_mask) &&
+ !device->device_prep_dma_crc32c);
BUG_ON(!device->device_tx_status);
BUG_ON(!device->device_issue_pending);
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 7ea9184..7108d7c 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -74,6 +74,7 @@ enum dma_transaction_type {
DMA_SLAVE,
DMA_CYCLIC,
DMA_INTERLEAVE,
+ DMA_CRC32C,
/* last transaction type for creation of the capabilities mask */
DMA_TX_TYPE_END,
};
@@ -645,6 +646,7 @@ enum dmaengine_alignment {
* The function takes a buffer of size buf_len. The callback function will
* be called after period_len bytes have been transferred.
* @device_prep_interleaved_dma: Transfer expression in a generic way.
+ * @device_prep_dma_crc32c: prepares a crc32c operation
* @device_config: Pushes a new configuration to a channel, return 0 or an
error
* code
* @device_pause: Pauses any transfer happening on a channel. Returns
@@ -727,6 +729,9 @@ struct dma_device {
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
struct dma_chan *chan, struct dma_interleaved_template *xt,
unsigned long flags);
+ struct dma_async_tx_descriptor *(*device_prep_dma_crc32c)(
+ struct dma_chan *chan, struct scatterlist *src_sg, size_t len,
+ unsigned int seed, u8 *result, unsigned long flags);
int (*device_config)(struct dma_chan *chan,
struct dma_slave_config *config);
@@ -824,6 +829,14 @@ static inline struct dma_async_tx_descriptor
*dmaengine_prep_dma_sg(
src_sg, src_nents, flags);
}
+static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_crc3c(
+ struct dma_chan *chan, struct scatterlist *src_sg,
+ size_t len, unsigned int seed, u8 *result, unsigned long flags)
+{
+ return chan->device->device_prep_dma_crc32c(chan, src_sg, len,
+ seed, result, flags);
+}
+
static inline int dmaengine_terminate_all(struct dma_chan *chan)
{
if (chan->device->device_terminate_all)
--
1.7.1
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[PATCH v2 3/3] Crypto: Add support for APM X-Gene SoC CRC32C h/w accelerator driver
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator.
DMA engine in APM X-Gene SoC is capable of doing CRC32C computations.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/crypto/Kconfig|8 ++
drivers/crypto/Makefile |1 +
drivers/crypto/xgene-crc32c.c | 234 +
3 files changed, 243 insertions(+), 0 deletions(-)
create mode 100755 drivers/crypto/xgene-crc32c.c
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index d234719..5d90b64 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -497,4 +497,12 @@ config CRYPTO_DEV_SUN4I_SS
To compile this driver as a module, choose M here: the module
will be called sun4i-ss.
+config CRYPTO_DEV_XGENE_CRC32C
+ tristate "Support for APM SoC X-Gene CRC32C HW accelerator"
+ depends on XGENE_DMA
+ select CRYPTO_HASH
+ help
+ This option enables support for CRC32C offload by using
+ APM X-Gene SoC DMA engine.
+
endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index c3ced6f..199d4e4 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
+obj-$(CONFIG_CRYPTO_DEV_XGENE_CRC32C) += xgene-crc32c.o
diff --git a/drivers/crypto/xgene-crc32c.c b/drivers/crypto/xgene-crc32c.c
new file mode 100755
index 000..142c681
--- /dev/null
+++ b/drivers/crypto/xgene-crc32c.c
@@ -0,0 +1,234 @@
+/*
+ * Applied Micro X-Gene SoC CRC32C HW acceleration by using DMA engine
+ *
+ * Copyright (c) 2015, Applied Micro Circuits Corporation
+ * Authors: Rameshwar Prasad Sahu
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CRC32C_DIGEST_SIZE 4
+#define CRC32C_BLOCK_SIZE 1
+#define XGENE_DMA_MAX_FLYBY_SRC_CNT5
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT 0x7FFF /* (32 KB - 1) */
+
+struct xgene_crc32c_session_ctx {
+ struct dma_chan *dchan;
+ u32 key;
+};
+
+struct xgene_crc32c_reqctx {
+ struct device *dev;
+ u32 nents;
+ u32 seed;
+};
+
+static void xgene_crc32c_callback(void *ctx)
+{
+ struct ahash_request *req = ctx;
+ struct xgene_crc32c_reqctx *reqctx = ahash_request_ctx(req);
+
+ if (req->base.complete)
+ req->base.complete(&req->base, 0);
+
+ dma_unmap_sg(reqctx->dev, req->src,
+reqctx->nents, DMA_TO_DEVICE);
+}
+
+static int xgene_crc32c_handle_req(struct ahash_request *req,
+ struct dma_chan *dchan)
+{
+ struct xgene_crc32c_reqctx *reqctx = ahash_request_ctx(req);
+ struct device *dev = dchan->device->dev;
+ struct dma_async_tx_descriptor *tx;
+ enum dma_ctrl_flags flags;
+ u32 nents, sg_count;
+ dma_cookie_t cookie;
+
+ if (req->nbytes > XGENE_DMA_MAX_FLYBY_BYTE_CNT) {
+ dev_err(dev, "Src len is too long %u\n", req->nbytes);
+ return -EINVAL;
+ }
+
+ nents = sg_nents(req->src);
+ sg_count = dma_map_sg(dev, req->src, nents, DMA_TO_DEVICE);
+ if (!sg_count) {
+ dev_err(dev, "Failed to map src sg");
+ return -EIO;
+ }
+
+ if (sg_count > XGENE_DMA_MAX_FLYBY_SRC_CNT) {
+ dev_err(dev, "Unsupported src sg count %d\n", sg_count);
+ goto err;
+ }
+
+ flags = DMA_CTRL_ACK;
+
+ tx = dmaengine_prep_dma_crc3c(dchan, req->src, req->nbytes,
+ reqctx->seed, req->result, flags);
+ if (!tx)
+ goto err;
+
+ /* Set callback parameters */
+ reqctx->dev = dev;
+ reqctx->nents = nents;
+ tx->callback_param = req;
+ tx->callback = xgene_crc32c_callback;
+
+ cookie = tx->tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(dev, "Failed to submit descriptor\n");
+ goto err;
+ }
+
+ dma_async_issue_pending(dchan);
+
+ return -EINPROGRE
[PATCH v2 2/3] dmaengine: xgene-dma: Add support for CRC32C computations via DMA engine
This patch implements CRC32C support to APM X-Gene SoC DMA engine driver.
Basically we have DMA engine in SoC capable of doing CRC32C computations.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 314 ---
1 files changed, 299 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 9dfa2b0..d95dc72 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -22,6 +22,7 @@
*/
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@
#define XGENE_DMA_RING_ENABLE BIT(31)
#define XGENE_DMA_RING_ID 0x08
#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
+#define XGENE_DMA_RING_IS_BUFPOOL BIT(20)
#define XGENE_DMA_RING_ID_BUF 0x0C
#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
#define XGENE_DMA_RING_THRESLD0_SET1 0x30
@@ -69,6 +71,8 @@
(((u32 *)(m))[2] |= (((v) >> 8) << 5))
#define XGENE_DMA_RING_ADDRH_SET(m, v) \
(((u32 *)(m))[3] |= ((v) >> 35))
+#define XGENE_DMA_RING_BUFMODE_SET(m) \
+ (((u32 *)(m))[3] |= ((0x3) << 20))
#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
(((u32 *)(m))[3] |= BIT(19))
#define XGENE_DMA_RING_SIZE_SET(m, v) \
@@ -106,6 +110,7 @@
#define XGENE_DMA_RING_INT2_MASK 0x90B0
#define XGENE_DMA_RING_INT3_MASK 0x90B8
#define XGENE_DMA_RING_INT4_MASK 0x90C0
+#define XGENE_DMA_CFG_RING_FQ_ASSOC0x90DC
#define XGENE_DMA_CFG_RING_WQ_ASSOC0x90E0
#define XGENE_DMA_ASSOC_RING_MNGR1 0x
#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
@@ -127,6 +132,10 @@
#define XGENE_DMA_DESC_LERR_POS60
#define XGENE_DMA_DESC_BUFLEN_POS 48
#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
+#define XGENE_DMA_DESC_BD_BIT BIT(0)
+#define XGENE_DMA_DESC_SD_BIT BIT(1)
+#define XGENE_DMA_DESC_CRCSEED_POS 8
+#define XGENE_DMA_DESC_FPQ_NUM_POS 32
#define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
#define XGENE_DMA_DESC_LERR_RD(m) \
@@ -140,20 +149,25 @@
/* X-Gene DMA configurable parameters defines */
#define XGENE_DMA_RING_NUM 512
#define XGENE_DMA_BUFNUM 0x0
+#define XGENE_DMA_BUFPOOL_BUFNUM 0x20
#define XGENE_DMA_CPU_BUFNUM 0x18
#define XGENE_DMA_RING_OWNER_DMA 0x03
#define XGENE_DMA_RING_OWNER_CPU 0x0F
#define XGENE_DMA_RING_TYPE_REGULAR0x01
+#define XGENE_DMA_RING_TYPE_BUFPOOL0x02
#define XGENE_DMA_RING_WQ_DESC_SIZE32 /* 32 Bytes */
+#define XGENE_DMA_BUFPOOL_DESC_SIZE16 /* 16 Bytes */
#define XGENE_DMA_RING_NUM_CONFIG 5
#define XGENE_DMA_MAX_CHANNEL 4
#define XGENE_DMA_XOR_CHANNEL 0
#define XGENE_DMA_PQ_CHANNEL 1
+#define XGENE_DMA_FLYBY_CHANNEL2
#define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
#define XGENE_DMA_MAX_64B_DESC_BYTE_CNT0x14000 /* 80 KB */
#define XGENE_DMA_MAX_XOR_SRC 5
#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
#define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT 0x7FFF /* (32 KB - 1) */
/* X-Gene DMA descriptor error codes */
#define ERR_DESC_AXI 0x01
@@ -187,9 +201,14 @@
#define FLYBY_3SRC_XOR 0x90
#define FLYBY_4SRC_XOR 0xA0
#define FLYBY_5SRC_XOR 0xB0
+#define FLYBY_CRC160x10
+#define FLYBY_CRC32C 0x20
+#define FLYBY_CRC320x30
+#define FLYBY_CHECKSUM 0x40
/* X-Gene DMA SW descriptor flags */
#define XGENE_DMA_FLAG_64B_DESCBIT(0)
+#define XGENE_DMA_FLAG_FLYBY_ACTIVEBIT(1)
/* Define to dump X-Gene DMA descriptor */
#define XGENE_DMA_DESC_DUMP(desc, m) \
@@ -206,6 +225,11 @@
#define chan_err(chan, fmt, arg...)\
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
+struct xgene_dma_desc16 {
+ __le64 m0;
+ __le64 m1;
+};
+
struct xgene_dma_desc_hw {
__le64 m0;
__le64 m1;
@@ -232,6 +256,7 @@ struct xgene_dma_ring {
u16 slots;
u16 dst_ring_num;
u32 size;
+ bool is_bufpool;
void __iomem *cmd;
void __iomem *cmd_base;
dma_addr_t desc_paddr;
@@ -239,6 +264,7 @@ struct xgene_dma_ring {
enum xgene_dma_ring_cfgsize cfgsize;
union {
void *desc_vaddr;
+ struct xgene_dma_desc16 *desc16;
struct xgene_dma_desc_hw *desc_hw;
};
};
@@ -247,6 +273,7 @@ struct xgene_dma_desc_sw {
struct xgene_dma_desc_hw desc1;
struct xgene_dma_de
[PATCH] dmaengine: xgene-dma: Fix overwritting DMA tx ring
This patch fixes an over flow issue with the TX ring descriptor. Each
descriptor is 32B in size and an operation requires 2 of these
descriptors.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 37 +++--
1 file changed, 11 insertions(+), 26 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index b23e8d5..21ba2cc 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -59,7 +59,6 @@
#define XGENE_DMA_RING_MEM_RAM_SHUTDOWN0xD070
#define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
#define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0x
-#define XGENE_DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1)
#define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
#define XGENE_DMA_RING_CMD_OFFSET 0x2C
@@ -379,14 +378,6 @@ static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
return flyby_type[src_cnt];
}
-static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring)
-{
- u32 __iomem *cmd_base = ring->cmd_base;
- u32 ring_state = ioread32(&cmd_base[1]);
-
- return XGENE_DMA_RING_DESC_CNT(ring_state);
-}
-
static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
dma_addr_t *paddr)
{
@@ -659,15 +650,12 @@ static void xgene_dma_clean_running_descriptor(struct
xgene_dma_chan *chan,
dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
}
-static int xgene_chan_xfer_request(struct xgene_dma_ring *ring,
- struct xgene_dma_desc_sw *desc_sw)
+static void xgene_chan_xfer_request(struct xgene_dma_chan *chan,
+ struct xgene_dma_desc_sw *desc_sw)
{
+ struct xgene_dma_ring *ring = &chan->tx_ring;
struct xgene_dma_desc_hw *desc_hw;
- /* Check if can push more descriptor to hw for execution */
- if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2))
- return -EBUSY;
-
/* Get hw descriptor from DMA tx ring */
desc_hw = &ring->desc_hw[ring->head];
@@ -694,11 +682,13 @@ static int xgene_chan_xfer_request(struct xgene_dma_ring
*ring,
memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
}
+ /* Increment the pending transaction count */
+ chan->pending += ((desc_sw->flags &
+ XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
+
/* Notify the hw that we have descriptor ready for execution */
iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
2 : 1, ring->cmd);
-
- return 0;
}
/**
@@ -710,7 +700,6 @@ static int xgene_chan_xfer_request(struct xgene_dma_ring
*ring,
static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
{
struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
- int ret;
/*
* If the list of pending descriptors is empty, then we
@@ -735,18 +724,13 @@ static void xgene_chan_xfer_ld_pending(struct
xgene_dma_chan *chan)
if (chan->pending >= chan->max_outstanding)
return;
- ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw);
- if (ret)
- return;
+ xgene_chan_xfer_request(chan, desc_sw);
/*
* Delete this element from ld pending queue and append it to
* ld running queue
*/
list_move_tail(&desc_sw->node, &chan->ld_running);
-
- /* Increment the pending transaction count */
- chan->pending++;
}
}
@@ -821,7 +805,8 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
* Decrement the pending transaction count
* as we have processed one
*/
- chan->pending--;
+ chan->pending -= ((desc_sw->flags &
+ XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
/*
* Delete this node from ld running queue and append it to
@@ -1482,7 +1467,7 @@ static int xgene_dma_create_chan_rings(struct
xgene_dma_chan *chan)
tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
/* Set the max outstanding request possible to this channel */
- chan->max_outstanding = rx_ring->slots;
+ chan->max_outstanding = tx_ring->slots;
return ret;
}
--
1.8.2.1
--
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[PATCH v2] dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests
This patch provides the fix in the cleanup routing such that client can perform
further submission by releasing the lock before calling client's callback
function.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index d1c8809..0b82bc0 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -763,12 +763,17 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
struct xgene_dma_ring *ring = &chan->rx_ring;
struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
struct xgene_dma_desc_hw *desc_hw;
+ struct list_head ld_completed;
u8 status;
+ INIT_LIST_HEAD(&ld_completed);
+
+ spin_lock_bh(&chan->lock);
+
/* Clean already completed and acked descriptors */
xgene_dma_clean_completed_descriptor(chan);
- /* Run the callback for each descriptor, in order */
+ /* Move all completed descriptors to ld completed queue, in order */
list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
/* Get subsequent hw descriptor from DMA rx ring */
desc_hw = &ring->desc_hw[ring->head];
@@ -811,15 +816,17 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
/* Mark this hw descriptor as processed */
desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
- xgene_dma_run_tx_complete_actions(chan, desc_sw);
-
- xgene_dma_clean_running_descriptor(chan, desc_sw);
-
/*
* Decrement the pending transaction count
* as we have processed one
*/
chan->pending--;
+
+ /*
+* Delete this node from ld running queue and append it to
+* ld completed queue for further processing
+*/
+ list_move_tail(&desc_sw->node, &ld_completed);
}
/*
@@ -828,6 +835,14 @@ static void xgene_dma_cleanup_descriptors(struct
xgene_dma_chan *chan)
* ahead and free the descriptors below.
*/
xgene_chan_xfer_ld_pending(chan);
+
+ spin_unlock_bh(&chan->lock);
+
+ /* Run the callback for each descriptor, in order */
+ list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
+ xgene_dma_run_tx_complete_actions(chan, desc_sw);
+ xgene_dma_clean_running_descriptor(chan, desc_sw);
+ }
}
static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
@@ -876,11 +891,11 @@ static void xgene_dma_free_chan_resources(struct dma_chan
*dchan)
if (!chan->desc_pool)
return;
- spin_lock_bh(&chan->lock);
-
/* Process all running descriptor */
xgene_dma_cleanup_descriptors(chan);
+ spin_lock_bh(&chan->lock);
+
/* Clean all link descriptor queues */
xgene_dma_free_desc_list(chan, &chan->ld_pending);
xgene_dma_free_desc_list(chan, &chan->ld_running);
@@ -1200,15 +1215,11 @@ static void xgene_dma_tasklet_cb(unsigned long data)
{
struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
- spin_lock_bh(&chan->lock);
-
/* Run all cleanup for descriptors which have been completed */
xgene_dma_cleanup_descriptors(chan);
/* Re-enable DMA channel IRQ */
enable_irq(chan->rx_irq);
-
- spin_unlock_bh(&chan->lock);
}
static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
--
1.8.2.1
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[PATCH] dmaengine: xgene-dma: Fix the resource map to handle overlapping
There is an overlap in dma ring cmd csr region due to sharing of ethernet
ring cmd csr region. This patch fix the resource overlapping by mapping
the entire dma ring cmd csr region.
Signed-off-by: Rameshwar Prasad Sahu
---
Documentation/devicetree/bindings/dma/apm-xgene-dma.txt | 2 +-
arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +-
drivers/dma/xgene-dma.c | 3 +++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
index d305876..c53e0b0 100644
--- a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -35,7 +35,7 @@ Example:
device_type = "dma";
reg = <0x0 0x1f27 0x0 0x1>,
<0x0 0x1f20 0x0 0x1>,
- <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1b00 0x0 0x40>,
<0x0 0x1054a000 0x0 0x100>;
interrupts = <0x0 0x82 0x4>,
<0x0 0xb8 0x4>,
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 0689c3f..58093ed 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -823,7 +823,7 @@
device_type = "dma";
reg = <0x0 0x1f27 0x0 0x1>,
<0x0 0x1f20 0x0 0x1>,
- <0x0 0x1b008000 0x0 0x2000>,
+ <0x0 0x1b00 0x0 0x40>,
<0x0 0x1054a000 0x0 0x100>;
interrupts = <0x0 0x82 0x4>,
<0x0 0xb8 0x4>,
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 620fd55ec..dff22ab 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -111,6 +111,7 @@
#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
#define XGENE_DMA_BLK_MEM_RDY 0xD074
#define XGENE_DMA_BLK_MEM_RDY_VAL 0x
+#define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
/* X-Gene SoC EFUSE csr register and bit defination */
#define XGENE_SOC_JTAG1_SHADOW 0x18
@@ -1887,6 +1888,8 @@ static int xgene_dma_get_resources(struct platform_device
*pdev,
return -ENOMEM;
}
+ pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
+
/* Get efuse csr region */
res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
if (!res) {
--
1.8.2.1
--
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[PATCH] dmaengine: xgene-dma: Fix double IRQ issue by setting IRQ_DISABLE_UNLAZY flag
For interrupt controller that doesn't support irq_disable and hardware
with level interrupt, an extra interrupt can be pending. This patch fixes
the issue by setting IRQ_DISABLE_UNLAZY flag for the interrupt line.
Reference: http://git.kernel.org/tip/e9849777d0e27cdd2902805be51da73e7c79578c
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 9dfa2b0..6363e84 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
@@ -1610,6 +1611,7 @@ static int xgene_dma_request_irqs(struct xgene_dma *pdma)
/* Register DMA channel rx irq */
for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
chan = &pdma->chan[i];
+ irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
ret = devm_request_irq(chan->dev, chan->rx_irq,
xgene_dma_chan_ring_isr,
0, chan->name, chan);
@@ -1620,6 +1622,7 @@ static int xgene_dma_request_irqs(struct xgene_dma *pdma)
for (j = 0; j < i; j++) {
chan = &pdma->chan[i];
+ irq_clear_status_flags(chan->rx_irq,
IRQ_DISABLE_UNLAZY);
devm_free_irq(chan->dev, chan->rx_irq, chan);
}
@@ -1640,6 +1643,7 @@ static void xgene_dma_free_irqs(struct xgene_dma *pdma)
for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
chan = &pdma->chan[i];
+ irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
devm_free_irq(chan->dev, chan->rx_irq, chan);
}
}
--
1.7.1
--
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[PATCH] dmaengine: xgene-dma: Fix double IRQ issue by setting IRQ_DISABLE_UNLAZY flag
For interrupt controller that doesn't support irq_disable and hardware
with level interrupt, an extra interrupt can be pending. This patch fixes
the issue by setting IRQ_DISABLE_UNLAZY flag for the interrupt line.
Reference: http://git.kernel.org/tip/e9849777d0e27cdd2902805be51da73e7c79578c
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 9dfa2b0..6363e84 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
@@ -1610,6 +1611,7 @@ static int xgene_dma_request_irqs(struct xgene_dma *pdma)
/* Register DMA channel rx irq */
for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
chan = &pdma->chan[i];
+ irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
ret = devm_request_irq(chan->dev, chan->rx_irq,
xgene_dma_chan_ring_isr,
0, chan->name, chan);
@@ -1620,6 +1622,7 @@ static int xgene_dma_request_irqs(struct xgene_dma *pdma)
for (j = 0; j < i; j++) {
chan = &pdma->chan[i];
+ irq_clear_status_flags(chan->rx_irq,
IRQ_DISABLE_UNLAZY);
devm_free_irq(chan->dev, chan->rx_irq, chan);
}
@@ -1640,6 +1643,7 @@ static void xgene_dma_free_irqs(struct xgene_dma *pdma)
for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
chan = &pdma->chan[i];
+ irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
devm_free_irq(chan->dev, chan->rx_irq, chan);
}
}
--
1.7.1
--
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[PATCH] mmc: host: arasan: sdhci-of-arasan: Remove no-hispd and no-cmd23 quirks for sdhci-arasan4.9a
The Arason SD host controller supports set block count command (cmd23)
and high speed mode. This patch re-enable both of these features that
was disabled. For device that doesn't support high speed, it should
configure its capability register accordingly instead disables it
explicitly.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/mmc/host/sdhci-of-arasan.c |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-arasan.c
index 75379cb..5d9fdb3 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -172,11 +172,6 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
goto clk_disable_all;
}
- if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-4.9a")) {
- host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
- host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
- }
-
sdhci_get_of_property(pdev);
pltfm_host = sdhci_priv(host);
pltfm_host->priv = sdhci_arasan;
--
1.7.1
--
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