[PATCH v3 2/6] drm/rockchip/dsi: correct phy parameter setting

[Nickey Yang]

As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency,so fix it.

Reviewed-by: Sean Paul 
Reviewed-by: Matthias Kaehlcke 
Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 98 --
 1 file changed, 70 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 95ce253..09e7bfe 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -217,10 +217,21 @@
 #define VCO_IN_CAP_CON_HIGH(0x2 << 1)
 #define REF_BIAS_CUR_SEL   BIT(0)
 
-#define CP_CURRENT_3MA BIT(3)
+#define CP_CURRENT_1_5UA   0x1
+#define CP_CURRENT_4_5UA   0x2
+#define CP_CURRENT_7_5UA   0x6
+#define CP_CURRENT_6UA 0x9
+#define CP_CURRENT_12UA0xb
+#define CP_CURRENT_SEL(val)((val) & 0xf)
 #define CP_PROGRAM_EN  BIT(7)
+
+#define LPF_RESISTORS_15_5KOHM 0x1
+#define LPF_RESISTORS_13KOHM   0x2
+#define LPF_RESISTORS_11_5KOHM 0x4
+#define LPF_RESISTORS_10_5KOHM 0x8
+#define LPF_RESISTORS_8KOHM0x10
 #define LPF_PROGRAM_EN BIT(6)
-#define LPF_RESISTORS_20_KOHM  0
+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
 
 #define HSFREQRANGE_SEL(val)   (((val) & 0x3f) << 1)
 
@@ -339,32 +350,63 @@ enum dw_mipi_dsi_mode {
DW_MIPI_DSI_VID_MODE,
 };
 
-struct dphy_pll_testdin_map {
+struct dphy_pll_parameter_map {
unsigned int max_mbps;
-   u8 testdin;
+   u8 hsfreqrange;
+   u8 icpctrl;
+   u8 lpfctrl;
 };
 
 /* The table is based on 27MHz DPHY pll reference clock. */
-static const struct dphy_pll_testdin_map dptdin_map[] = {
-   {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
-   { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
-   { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
-   { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
-   { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
-   { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
-   { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
-   {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
-   {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
-   {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+static const struct dphy_pll_parameter_map dppa_map[] = {
+   {  89, 0x00, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   {  99, 0x10, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   { 109, 0x20, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   { 129, 0x01, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 139, 0x11, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 149, 0x21, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+   { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+   { 329, 0x05, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 359, 0x15, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 399, 0x25, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+   { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+   { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}
 };
 
-static int max_mbps_to_testdin(unsigned int max_mbps)
+static int max_mbps_to_parameter(unsigned int max_mbps)
 {
int i;
 
-   for (

[PATCH v3 1/6] drm/rockchip/dsi: Define and use macros for PHY register addresses

[Nickey Yang]

Replace the hardcoded register address numerical values with macros to
clarify the code.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 129 ++---
 1 file changed, 85 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index b15755b..95ce253 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -254,6 +254,28 @@
 #define DW_MIPI_NEEDS_PHY_CFG_CLK  BIT(0)
 #define DW_MIPI_NEEDS_GRF_CLK  BIT(1)
 
+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL   0x10
+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
+#define PLL_LPF_AND_CP_CONTROL 0x12
+#define PLL_INPUT_DIVIDER_RATIO0x17
+#define PLL_LOOP_DIVIDER_RATIO 0x18
+#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL  0x19
+#define BANDGAP_AND_BIAS_CONTROL   0x20
+#define TERMINATION_RESISTER_CONTROL   0x21
+#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY0x22
+#define HS_RX_CONTROL_OF_LANE_00x44
+#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL0x60
+#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL0x61
+#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL0x62
+#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL  0x63
+#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL   0x64
+#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
+#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
+#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
+#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
+#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL   0x73
+#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL0x74
+
 enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -447,53 +469,72 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
return ret;
}
 
-   dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
-VCO_RANGE_CON_SEL(vco) |
-VCO_IN_CAP_CON_LOW |
-REF_BIAS_CUR_SEL);
-
-   dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
-   dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
-LPF_RESISTORS_20_KOHM);
-
-   dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
-
-   dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
-LOW_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
-HIGH_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
-
-   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-BIASEXTR_SEL(BIASEXTR_127_7));
-   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-BANDGAP_SEL(BANDGAP_96_10));
-
-   dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
-BIAS_BLOCK_ON | BANDGAP_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
-SETRD_MAX | TER_RESISTORS_ON);
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
-SETRD_MAX | POWER_MANAGE |
-TER_RESISTORS_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
-   dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
-   dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
-
-   dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x71,
+   dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
+ BYPASS_VCO_RANGE |
+ VCO_RANGE_CON_SEL(vco) |
+ VCO_IN_CAP_CON_LOW |
+ REF_BIAS_CUR_SEL);
+
+   dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
+ CP_CURRENT_3MA);
+   dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
+ CP_PROGRAM_EN | LPF_PROGRAM_EN |
+ LPF_RESISTORS_20_KOHM);
+
+   dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
+ HSFREQRANGE_SEL(testdin));
+
+   dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
+ INPUT_DIVIDER(dsi-&

[PATCH v3 4/6] drm/rockchip/dsi: add dual mipi channel support

[Nickey Yang]

This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 377 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   2 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   3 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |   1 +
 5 files changed, 279 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 589b420..25e7b77 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -39,8 +39,42 @@
 #define RK3399_DSI1_SEL_VOP_LITBIT(4)
 
 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
+#define RK3399_GRF_SOC_CON22   0x6258
+#define DPHY_TX0_TURNREQUEST_ENABLE(0xf << 12)
+#define DPHY_TX0_TURNREQUEST_SET   (DPHY_TX0_TURNREQUEST_ENABLE << 
16)
+#define DPHY_TX0_TURNDISABLE_ENABLE(0xf << 8)
+#define DPHY_TX0_TURNDISABLE_SET   (DPHY_TX0_TURNDISABLE_ENABLE << 
16)
+#define DPHY_TX0_FORCETXSTOPMODE_ENABLE(0xf << 4)
+#define DPHY_TX0_FORCETXSTOPMODE_SET   
(DPHY_TX0_FORCETXSTOPMODE_ENABLE << 16)
+#define DPHY_TX0_FORCETRXMODE_ENABLE   0xf
+#define DPHY_TX0_FORCETRXMODE_SET  (DPHY_TX0_FORCETRXMODE_ENABLE 
<< 16)
+#define RK3399_GRF_DSI_MODE(DPHY_TX0_TURNREQUEST_SET | \
+DPHY_TX0_TURNDISABLE_SET | \
+DPHY_TX0_FORCETXSTOPMODE_SET | 
\
+DPHY_TX0_FORCETRXMODE_SET)
+
+
+/* disable turndisable, forcetxstopmode, forcerxmode, enable */
+#define RK3399_GRF_SOC_CON23   0x625c
+#define DPHY_TX1RX1_TURNDISABLE_ENABLE (0xf << 12)
+#define DPHY_TX1RX1_TURNDISABLE_SET(DPHY_TX1RX1_TURNDISABLE_ENABLE 
<< 16)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_ENABLE (0xf << 8)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_SET
(DPHY_TX1RX1_FORCETXSTOPMODE_ENABLE << 16)
+#define DPHY_TX1RX1_FORCERXMODE_ENABLE (0xf << 4)
+#define DPHY_TX1RX1_FORCERXMODE_SET(DPHY_TX1RX1_FORCERXMODE_ENABLE 
<< 16)
+#define DPHY_TX1RX1_ENABLE_ENABLE  0xf
+#define DPHY_TX1RX1_ENABLE_SET (DPHY_TX1RX1_ENABLE_ENABLE << 
16)
+#define RK3399_GRF_DSI1_MODE   (DPHY_TX1RX1_TURNDISABLE_SET | \
+
DPHY_TX1RX1_FORCETXSTOPMODE_SET | \
+DPHY_TX1RX1_FORCERXMODE_SET | \
+DPHY_TX1RX1_ENABLE_SET)
+#define RK3399_GRF_DSI1_ENABLE ((DPHY_TX1RX1_ENABLE_SET | \
+ DPHY_TX1RX1_ENABLE_ENABLE))
+
+#define RK3399_GRF_SOC_CON24   0x6260
+#define RK3399_TXRX_MASTERSLAVEZ   BIT(7)
+#define RK3399_TXRX_ENABLECLK  BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
 
 #define DSI_VERSION0x00
 #define DSI_PWR_UP 0x04
@@ -315,6 +349,13 @@ struct dw_mipi_dsi_plat_data {
u32 grf_switch_reg;
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
+   u32 grf_dsi1_mode;
+   u32 grf_dsi1_enable;
+   u32 grf_dsi1_mode_reg1;
+   u32 dsi1_basedir;
+   u32 dsi1_masterslavez;
+   u32 dsi1_enableclk;
+   u32 grf_dsi1_mode_reg2;
unsigned int flags;
unsigned int max_data_lanes;
 };
@@ -333,6 +374,10 @@ struct dw_mipi_dsi {
struct clk *pclk;
struct clk *phy_cfg_clk;
 
+   /* dual-channel */
+   struct dw_mipi_dsi *master;
+   struct dw_mipi_dsi *slave;
+
int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -617,6 +662,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
int bpp;
unsigned long best_freq = 0;
+   int lanes = dsi->lanes;
unsigned long fvco_min, fvco_max, fin, fout;
unsigned int min_prediv, max_prediv;
unsigned int _prediv, uninitialized_var(best_prediv);
@@ -631,10 +677,13 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi 
*dsi,
return bpp;
}
 
+   if (dsi->slave || dsi->master)
+   lanes = dsi->lanes * 2;
+
mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
if (mpclk) {
/* take 1 / 0.8, since mbps must big than bandwid

[PATCH v3 6/6] arm64: dts: rockchip: add mipi_dsi1 support for rk3399

[Nickey Yang]

This patch adds the mipi_dsi1 related needed information.
e.g.: interrupts, grf, clocks, ports and so on.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 39 
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index a65f7f7..48e2695 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1515,6 +1515,11 @@
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
+
+   vopl_out_mipi1: endpoint@3 {
+   reg = <3>;
+   remote-endpoint = <&mipi1_in_vopl>;
+   };
};
};
 
@@ -1562,6 +1567,11 @@
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
+
+   vopb_out_mipi1: endpoint@3 {
+   reg = <3>;
+   remote-endpoint = <&mipi1_in_vopb>;
+   };
};
};
 
@@ -1657,6 +1667,35 @@
};
};
 
+   mipi_dsi1: mipi@ff968000 {
+   compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+   reg = <0x0 0xff968000 0x0 0x8000>;
+   interrupts = ;
+   clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
+   clock-names = "ref", "pclk", "phy_cfg", "grf";
+   power-domains = <&power RK3399_PD_VIO>;
+   rockchip,grf = <&grf>;
+   status = "disabled";
+
+   ports {
+   mipi1_in: port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi1_in_vopb: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&vopb_out_mipi1>;
+   };
+
+   mipi1_in_vopl: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = <&vopl_out_mipi1>;
+   };
+   };
+   };
+   };
+
edp: edp@ff97 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff97 0x0 0x8000>;
-- 
1.9.1

[PATCH v3 3/6] drm/rockchip/dsi: correct Feedback divider setting

[Nickey Yang]

This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
3、Make the previously configured Feedback divider(LSB)
factors effective

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 93 ++
 1 file changed, 62 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 09e7bfe..589b420 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -239,7 +239,7 @@
 #define LOW_PROGRAM_EN 0
 #define HIGH_PROGRAM_ENBIT(7)
 #define LOOP_DIV_LOW_SEL(val)  (((val) - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0xf)
 #define PLL_LOOP_DIV_ENBIT(5)
 #define PLL_INPUT_DIV_EN   BIT(4)
 
@@ -531,6 +531,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
  LOOP_DIV_LOW_SEL(dsi->feedback_div) |
  LOW_PROGRAM_EN);
+   /*
+* we need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
+* to make the configrued LSB effective according to IP simulation
+* and lab test results.
+* Only in this way can we get correct mipi phy pll frequency.
+*/
+   dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
+ PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
  LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
  HIGH_PROGRAM_EN);
@@ -604,11 +612,16 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
 {
-   unsigned int i, pre;
-   unsigned long mpclk, pllref, tmp;
-   unsigned int m = 1, n = 1, target_mbps = 1000;
+   unsigned long mpclk, tmp;
+   unsigned int target_mbps = 1000;
unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
int bpp;
+   unsigned long best_freq = 0;
+   unsigned long fvco_min, fvco_max, fin, fout;
+   unsigned int min_prediv, max_prediv;
+   unsigned int _prediv, uninitialized_var(best_prediv);
+   unsigned long _fbdiv, uninitialized_var(best_fbdiv);
+   unsigned long min_delta = ULONG_MAX;
 
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
if (bpp < 0) {
@@ -629,35 +642,53 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi 
*dsi,
  "DPHY clock frequency is out of range\n");
}
 
-   pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
-   tmp = pllref;
-
-   /*
-* The limits on the PLL divisor are:
-*
-*  5MHz <= (pllref / n) <= 40MHz
-*
-* we walk over these values in descreasing order so that if we hit
-* an exact match for target_mbps it is more likely that "m" will be
-* even.
-*
-* TODO: ensure that "m" is even after this loop.
-*/
-   for (i = pllref / 5; i > (pllref / 40); i--) {
-   pre = pllref / i;
-   if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
-   tmp = target_mbps % pre;
-   n = i;
-   m = target_mbps / pre;
+   fin = clk_get_rate(dsi->pllref_clk);
+   fout = target_mbps * USEC_PER_SEC;
+
+   /* constraint: 5Mhz <= Fref / N <= 40MHz */
+   min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
+   max_prediv = fin / (5 * USEC_PER_SEC);
+
+   /* constraint: 80MHz <= Fvco <= 1500Mhz */
+   fvco_min = 80 * USEC_PER_SEC;
+   fvco_max = 1500 * USEC_PER_SEC;
+
+   for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
+   u64 tmp;
+   u32 delta;
+   /* Fvco = Fref * M / N */
+   tmp = (u64)fout * _prediv;
+   do_div(tmp, fin);
+   _fbdiv = tmp;
+   /*
+* Due to the use of a "by 2 pre-scaler," the range of the
+* feedback multiplication value M is limited to even division
+* numbers, and m must be greater than 12, less than 1000.
+*/
+   if (_fbdiv <= 12 || _fbdiv >= 1000)
+   continue;
+
+   _fbdiv += _fbdiv % 

[PATCH v3 5/6] dt-bindings: add the rockchip,dual-channel for dw-mipi-dsi

[Nickey Yang]

Configure dsi slave channel when driving a panel
which needs 2 DSI links.

Signed-off-by: Nickey Yang 
---
 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt   | 2 ++
 1 file changed, 2 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..a2bea22 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -19,6 +19,8 @@ Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
 - resets: list of phandle + reset specifier pairs, as described in [3].
 - reset-names: string reset name, must be "apb".
+- rockchip,dual-channel: phandle to a 2nd DSI channel, useful as a slave
+channel when driving a panel which needs 2 DSI links.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
-- 
1.9.1

[PATCH v2] drm/bridge: dw_hdmi: support i2c extended read mode

[Nickey Yang]

"I2C Master Interface Extended Read Mode" implements a segment
pointer-based read operation using the Special Register configuration.

This patch fix https://patchwork.kernel.org/patch/7098101/ mentioned
"The current implementation does not support "I2C Master Interface
Extended Read Mode" to read data addressed by non-zero segment
pointer, this means that if EDID has more than 1 extension blocks"

With this patch,dw-hdmi can read EDID data with 1/2/4 blocks.

Signed-off-by: Nickey Yang 
Reviewed-by: Douglas Anderson 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 38 --
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 9a9ec27..3b93655 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -32,6 +32,7 @@
 #include "dw-hdmi.h"
 #include "dw-hdmi-audio.h"
 
+#define DDC_SEGMENT_ADDR   0x30
 #define HDMI_EDID_LEN  512
 
 #define RGB0
@@ -111,6 +112,7 @@ struct dw_hdmi_i2c {
 
u8  slave_reg;
boolis_regaddr;
+   boolis_segment;
 };
 
 struct dw_hdmi_phy_data {
@@ -258,8 +260,12 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
reinit_completion(&i2c->cmp);
 
hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
-   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
-   HDMI_I2CM_OPERATION);
+   if (i2c->is_segment)
+   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
+   HDMI_I2CM_OPERATION);
+   else
+   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
+   HDMI_I2CM_OPERATION);
 
stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
if (!stat)
@@ -271,6 +277,7 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 
*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
}
+   i2c->is_segment = false;
 
return 0;
 }
@@ -320,12 +327,6 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 
for (i = 0; i < num; i++) {
-   if (msgs[i].addr != addr) {
-   dev_warn(hdmi->dev,
-"unsupported transfer, changed slave 
address\n");
-   return -EOPNOTSUPP;
-   }
-
if (msgs[i].len == 0) {
dev_dbg(hdmi->dev,
"unsupported transfer %d/%d, no data\n",
@@ -345,15 +346,24 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
/* Set slave device register address on transfer */
i2c->is_regaddr = false;
 
+   /* Set segment pointer for I2C extended read mode operation */
+   i2c->is_segment = false;
+
for (i = 0; i < num; i++) {
dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
i + 1, num, msgs[i].len, msgs[i].flags);
-
-   if (msgs[i].flags & I2C_M_RD)
-   ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
-   else
-   ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
-
+   if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
+   i2c->is_segment = true;
+   hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
+   hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
+   } else {
+   if (msgs[i].flags & I2C_M_RD)
+   ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
+  msgs[i].len);
+   else
+   ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
+   msgs[i].len);
+   }
if (ret < 0)
break;
}
-- 
1.9.1

[PATCH] drm: bridge: dw-hdmi: add HDMI vendor specific infoframe config

[Nickey Yang]

Vendor specific infoframe is mandatory for 4K2K resolution.
Without this, the HDMI protocol compliance fails.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 50 
 drivers/gpu/drm/bridge/dw-hdmi.h |  4 
 2 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 9a9ec27..79e2e48 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -1195,6 +1195,55 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
 }
 
+static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
+struct drm_display_mode *mode)
+{
+   struct hdmi_vendor_infoframe frame;
+   u8 buffer[10];
+   ssize_t err;
+
+   err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
+   if (err) {
+   dev_err(hdmi->dev,
+   "Failed to get vendor infoframe from mode: %zd\n", err);
+   return;
+   }
+
+   err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
+   if (!err) {
+   dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
+   err);
+   return;
+   }
+   hdmi_modb(hdmi, 0 << HDMI_FC_DATAUTO0_VSD_OFFSET,
+ HDMI_FC_DATAUTO0_VSD_MASK, HDMI_FC_DATAUTO0);
+
+   /* Set the length of HDMI vendor specific InfoFrame payload */
+   hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
+
+   /* Set 24bit IEEE Registration Identifier */
+   hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
+   hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
+   hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
+
+   /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
+   hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
+   hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
+
+   if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
+   hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
+
+   /* Packet frame interpolation */
+   hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
+
+   /* Auto packets per frame and line spacing */
+   hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
+
+   /* Configures the Frame Composer On RDRB mode */
+   hdmi_modb(hdmi, 1 << HDMI_FC_DATAUTO0_VSD_OFFSET,
+ HDMI_FC_DATAUTO0_VSD_MASK, HDMI_FC_DATAUTO0);
+}
+
 static void hdmi_av_composer(struct dw_hdmi *hdmi,
 const struct drm_display_mode *mode)
 {
@@ -1446,6 +1495,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
 
/* HDMI Initialization Step F - Configure AVI InfoFrame */
hdmi_config_AVI(hdmi, mode);
+   hdmi_config_vendor_specific_infoframe(hdmi, mode);
} else {
dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
}
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h
index 325b0b8..c59f87e 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/dw-hdmi.h
@@ -854,6 +854,10 @@ enum {
HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
 
+/* FC_DATAUTO0 field values */
+   HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
+   HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
+
 /* PHY_CONF0 field values */
HDMI_PHY_CONF0_PDZ_MASK = 0x80,
HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-- 
1.9.1

[PATCH v2] drm: bridge: dw-hdmi: add HDMI vendor specific infoframe config

[Nickey Yang]

Vendor specific infoframe is mandatory for 4K2K resolution.
Without this, the HDMI protocol compliance fails.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 47 
 drivers/gpu/drm/bridge/dw-hdmi.h |  4 
 2 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 9a9ec27..07a16b1 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -1195,6 +1195,52 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
 }
 
+static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
+struct drm_display_mode *mode)
+{
+   struct hdmi_vendor_infoframe frame;
+   u8 buffer[10];
+   ssize_t err;
+
+   err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
+   if (err)
+   return;
+
+   err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
+   if (!err) {
+   dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
+   err);
+   return;
+   }
+   hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
+   HDMI_FC_DATAUTO0_VSD_MASK);
+
+   /* Set the length of HDMI vendor specific InfoFrame payload */
+   hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
+
+   /* Set 24bit IEEE Registration Identifier */
+   hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
+   hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
+   hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
+
+   /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
+   hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
+   hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
+
+   if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
+   hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
+
+   /* Packet frame interpolation */
+   hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
+
+   /* Auto packets per frame and line spacing */
+   hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
+
+   /* Configures the Frame Composer On RDRB mode */
+   hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
+   HDMI_FC_DATAUTO0_VSD_MASK);
+}
+
 static void hdmi_av_composer(struct dw_hdmi *hdmi,
 const struct drm_display_mode *mode)
 {
@@ -1446,6 +1492,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
 
/* HDMI Initialization Step F - Configure AVI InfoFrame */
hdmi_config_AVI(hdmi, mode);
+   hdmi_config_vendor_specific_infoframe(hdmi, mode);
} else {
dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
}
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h
index 325b0b8..c59f87e 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/dw-hdmi.h
@@ -854,6 +854,10 @@ enum {
HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
 
+/* FC_DATAUTO0 field values */
+   HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
+   HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
+
 /* PHY_CONF0 field values */
HDMI_PHY_CONF0_PDZ_MASK = 0x80,
HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-- 
1.9.1

[PATCH v3] drm: bridge: dw-hdmi: add HDMI vendor specific infoframe config

[Nickey Yang]

Vendor specific infoframe is mandatory for 4K2K resolution.
Without this, the HDMI protocol compliance fails.

Signed-off-by: Nickey Yang 
Reviewed-by: Jose Abreu 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 53 
 drivers/gpu/drm/bridge/dw-hdmi.h |  4 +++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 9a9ec27..6b29d1a 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -1195,6 +1195,58 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
 }
 
+static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
+struct drm_display_mode *mode)
+{
+   struct hdmi_vendor_infoframe frame;
+   u8 buffer[10];
+   ssize_t err;
+
+   err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
+   if (err < 0)
+   /*
+* Going into that statement does not means vendor infoframe
+* fails. It just informed us that vendor infoframe is not
+* needed for the selected mode. Only 4k or stereoscopic 3D
+* mode requires vendor infoframe. So just simply return.
+*/
+   return;
+
+   err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
+   if (err < 0) {
+   dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
+   err);
+   return;
+   }
+   hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
+   HDMI_FC_DATAUTO0_VSD_MASK);
+
+   /* Set the length of HDMI vendor specific InfoFrame payload */
+   hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
+
+   /* Set 24bit IEEE Registration Identifier */
+   hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
+   hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
+   hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
+
+   /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
+   hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
+   hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
+
+   if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
+   hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
+
+   /* Packet frame interpolation */
+   hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
+
+   /* Auto packets per frame and line spacing */
+   hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
+
+   /* Configures the Frame Composer On RDRB mode */
+   hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
+   HDMI_FC_DATAUTO0_VSD_MASK);
+}
+
 static void hdmi_av_composer(struct dw_hdmi *hdmi,
 const struct drm_display_mode *mode)
 {
@@ -1446,6 +1498,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
 
/* HDMI Initialization Step F - Configure AVI InfoFrame */
hdmi_config_AVI(hdmi, mode);
+   hdmi_config_vendor_specific_infoframe(hdmi, mode);
} else {
dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
}
diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h
index 325b0b8..c59f87e 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.h
+++ b/drivers/gpu/drm/bridge/dw-hdmi.h
@@ -854,6 +854,10 @@ enum {
HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
 
+/* FC_DATAUTO0 field values */
+   HDMI_FC_DATAUTO0_VSD_MASK = 0x08,
+   HDMI_FC_DATAUTO0_VSD_OFFSET = 3,
+
 /* PHY_CONF0 field values */
HDMI_PHY_CONF0_PDZ_MASK = 0x80,
HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-- 
1.9.1

[PATCH] drm/mediatek: fix mtk_hdmi_setup_vendor_specific_infoframe mistake

[Nickey Yang]

mtk_hdmi_setup_vendor_specific_infoframe will return before handle
mtk_hdmi_hw_send_info_frame.Because hdmi_vendor_infoframe_pack
returns the number of bytes packed into the binary buffer or
a negative error code on failure.
So correct it.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c 
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index c262512..b43aa29 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1062,7 +1062,7 @@ static int 
mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
}
 
err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
-   if (err) {
+   if (err < 0) {
dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
err);
return err;
-- 
1.9.1

[PATCH] drm: bridge: dw-hdmi: support i2c extended read mode

[Nickey Yang]

"I2C Master Interface Extended Read Mode" implements a segment
pointer-based read operation using the Special Register configuration.

This patch fix https://patchwork.kernel.org/patch/7098101/ mentioned
"The current implementation does not support "I2C Master Interface
Extended Read Mode" to read data addressed by non-zero segment
pointer, this means that if EDID has more than 1 extension blocks"

With this patch,dw-hdmi can read EDID data with 1/2/4 blocks.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/bridge/dw-hdmi.c | 38 --
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c
index 9a9ec27..6ad7b87 100644
--- a/drivers/gpu/drm/bridge/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/dw-hdmi.c
@@ -33,6 +33,7 @@
 #include "dw-hdmi-audio.h"
 
 #define HDMI_EDID_LEN  512
+#define DDC_SEGMENT_ADDR   0x30
 
 #define RGB0
 #define YCBCR444   1
@@ -111,6 +112,7 @@ struct dw_hdmi_i2c {
 
u8  slave_reg;
boolis_regaddr;
+   boolis_segment;
 };
 
 struct dw_hdmi_phy_data {
@@ -258,8 +260,12 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
reinit_completion(&i2c->cmp);
 
hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
-   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
-   HDMI_I2CM_OPERATION);
+   if (i2c->is_segment)
+   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
+   HDMI_I2CM_OPERATION);
+   else
+   hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
+   HDMI_I2CM_OPERATION);
 
stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
if (!stat)
@@ -271,6 +277,7 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 
*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
}
+   i2c->is_segment = false;
 
return 0;
 }
@@ -320,12 +327,6 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 
for (i = 0; i < num; i++) {
-   if (msgs[i].addr != addr) {
-   dev_warn(hdmi->dev,
-"unsupported transfer, changed slave 
address\n");
-   return -EOPNOTSUPP;
-   }
-
if (msgs[i].len == 0) {
dev_dbg(hdmi->dev,
"unsupported transfer %d/%d, no data\n",
@@ -345,15 +346,24 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
/* Set slave device register address on transfer */
i2c->is_regaddr = false;
 
+   /* Set segment pointer for I2C extended read mode operation */
+   i2c->is_segment = false;
+
for (i = 0; i < num; i++) {
dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
i + 1, num, msgs[i].len, msgs[i].flags);
-
-   if (msgs[i].flags & I2C_M_RD)
-   ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
-   else
-   ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
-
+   if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
+   i2c->is_segment = true;
+   hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
+   hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
+   } else {
+   if (msgs[i].flags & I2C_M_RD)
+   ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
+  msgs[i].len);
+   else
+   ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
+   msgs[i].len);
+   }
if (ret < 0)
break;
}
-- 
1.9.1

Re: [PATCH v4 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

Hi Philippe,


On 2017年12月01日 18:07, Philippe CORNU wrote:

Hi Nickey,

On 12/01/2017 10:11 AM, Nickey Yang wrote:

Hi Philippe,


On 2017年12月01日 16:32, Philippe CORNU wrote:

Dear Nickey,

Many thanks for your patch.

I am sorry to say that but you can not add my "Acked-by" to this patch
because this code is different from the "original" one from Brian (which
got my "Acked-by").

I'm sorry I didn't think much about it, Thank you for correcting me.

Sometimes it is not an issue because differences are not important but
in this particular case, the code is really different: you have remove
platform_set_drvdata() & platform_get_drvdata() in the stm part.

Could you please go back to the original code or propose me an updated
version of this code.

Could you help update new version of this code(stm part) and then test on
stm platform?

I think you can simply goes back to the original version from Brian (see
the discussion thread in https://patchwork.kernel.org/patch/10078493/)
unless you have specific/good reasons for modifying the code as you did.

mmm,I'm sorry, I feel a little puzzled. Do you means we should abandon
Brian's patch (https://patchwork.kernel.org/patch/10078493/)?
I think we need to adjust stm part because  dw_mipi_dsi_stm.c calls
bridge's drivers if we want merge Brian's patch.


Thanks

Many thanks,
Philippe :)


Thanks,
Nickey.

Many thanks,

Philippe :-)


On 12/01/2017 04:58 AM, Nickey Yang wrote:

From: Brian Norris

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris
Signed-off-by: Nickey Yang
Reviewed-by: Matthias Kaehlcke
Reviewed-by: Archit Taneja
Acked-by: Philippe Cornu
Link:https://patchwork.kernel.org/patch/10078493/

---
Changes in v4:
- Add From tag,update subject line
- keep patch "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
 in this piece together.

drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 
++-
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  8 +++---
include/drm/bridge/dw_mipi_dsi.h  | 17 -
3 files changed, 29 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
#endif

-	dev_set_drvdata(dev, dsi);

-
return dsi;
}

@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)

/*
 * Probe/remove API, used from platforms based on the DRM bridge API.
 */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
{
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
}
EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);

-void dw_mipi_dsi_remove(struct platform_device *pdev)

+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
{
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);

	__dw_mipi_dsi_remove(dsi);

@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
/*
 * Bind/unbind API, used from platforms based on the component framework.
 */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
{
struct dw_mipi_dsi *dsi;
int ret;

	dsi = __dw_mipi_dsi_probe(pdev, plat_data);

if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;

	ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);

if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}

-	return 0;

+   return dsi;
}
EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);

-void dw_mipi_dsi_unbind(struct device *dev)

+void dw_mipi_dsi_unbi

Re: [PATCH v4 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

Hi Brian,


On 2017年12月06日 02:56, Brian Norris wrote:

Hi Nickey,

On Tue, Dec 05, 2017 at 05:14:11PM +0800, Nickey Yang wrote:

On 2017年12月01日 18:07, Philippe CORNU wrote:

On 12/01/2017 10:11 AM, Nickey Yang wrote:

On 2017年12月01日 16:32, Philippe CORNU wrote:

I am sorry to say that but you can not add my "Acked-by" to this patch
because this code is different from the "original" one from Brian (which
got my "Acked-by").

I'm sorry I didn't think much about it, Thank you for correcting me.

Sometimes it is not an issue because differences are not important but
in this particular case, the code is really different: you have remove
platform_set_drvdata() & platform_get_drvdata() in the stm part.

Could you please go back to the original code or propose me an updated
version of this code.

Could you help update new version of this code(stm part) and then test on
stm platform?

I think you can simply goes back to the original version from Brian (see
the discussion thread in https://patchwork.kernel.org/patch/10078493/)
unless you have specific/good reasons for modifying the code as you did.

mmm,I'm sorry, I feel a little puzzled. Do you means we should abandon
Brian's patch (https://patchwork.kernel.org/patch/10078493/)?
I think we need to adjust stm part because  dw_mipi_dsi_stm.c calls
bridge's drivers if we want merge Brian's patch.

It's really simple. Your code is different from the patch I sent, and in
a way that Philippe did not like. I'll highlight it again below:


diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..80f9950 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
};
static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -318,10 +319,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(dsi->dmd);
}
return ret;
@@ -332,7 +334,7 @@ static int dw_mipi_dsi_stm_remove(struct platform_device 
*pdev)
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
clk_disable_unprepare(dsi->pllref_clk);
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi->dmd);
return 0;
}
  
Above is your diff for dw_mipi_dsi-stm.c. Particularly, notice that

remove() is directly referencing the static dw_mipi_dsi_stm_plat_data
struct.

If you look back at my patch [1] you'll see that you're missing hunks
like this:


Thank you for pointing out my mistake.
I will fix this in next version.

Nickey.

  static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
  {
-   struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+   struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
  
  	clk_disable_unprepare(dsi->pllref_clk);

[...]

Brian

[1] https://patchwork.kernel.org/patch/10078493/

[PATCH v5 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

From: Brian Norris 

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris 
Signed-off-by: Nickey Yang 
Link:https://patchwork.kernel.org/patch/10078493/

---
Changes

v4:
- Add From tag,update subject line
- keep patch "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
  in this piece together.

v5:
- remove Review & Ack tag(just bridge part v1)
- fix stm part remove() directly referencing the static
  dw_mipi_dsi_stm_plat_data struct.

 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 ++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 10 +---
 include/drm/bridge/dw_mipi_dsi.h  | 17 -
 3 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   dev_set_drvdata(dev, dsi);
-
return dsi;
 }
 
@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 /*
  * Probe/remove API, used from platforms based on the DRM bridge API.
  */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
 {
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 
-void dw_mipi_dsi_remove(struct platform_device *pdev)
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);
 
__dw_mipi_dsi_remove(dsi);
@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
 {
struct dw_mipi_dsi *dsi;
int ret;
 
dsi = __dw_mipi_dsi_probe(pdev, plat_data);
if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;
 
ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}
 
-   return 0;
+   return dsi;
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 
-void dw_mipi_dsi_unbind(struct device *dev)
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
-
__dw_mipi_dsi_remove(dsi);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..05787fa 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
 struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
 };
 
 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -318,10 +319,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(dsi->dmd);
}
 
return ret;
@@ -329,10 +331,10 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
 
 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
 {
-   struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+   struct dw_mipi_dsi_stm *dsi = platform_get

[PATCH v5 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref、remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   add Brian's patch "drm/bridge/synopsys: stop clobbering drvdata"
   (Link:https://patchwork.kernel.org/patch/10078493/)
   adjust drm/stm/dsi code for above
   drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
   keep "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
   into Brians "drm/bridge/synopsys: stop clobbering drvdata"
   add review tag and add some comments 

v5:
  1/3: fix stm part remove() directly referencing the static
  dw_mipi_dsi_stm_plat_data struct.
  3/3: keep our power domain enabled while touching GRF
   
Nickey Yang (3):
  drm/bridge/synopsys: dsi: stop clobbering drvdata
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  |   36 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  786 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |   10 +-
 include/drm/bridge/dw_mipi_dsi.h   |   17 +-
 10 files changed, 841 insertions(+), 1388 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH v5 2/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
Reviewed-by: Brian Norris 

---
Changes

v5:
-  add review tag

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 --
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..ce4c1fc 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,12 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
+   mipi_in: port@0 {
+   reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +57,16 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +77,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v5 3/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
Signed-off-by: Brian Norris 
Reviewed-by: Brian Norris 
Reviewed-by: Sean Paul 
---
Changes:

v2:
   add err_pllref, remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
  return -EINVAL when can not get best_freq
  add a clarifying comment when get vco
  add review tag
v5:
  keep our power domain enabled while touching GRF

 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  785 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 789 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define H

[PATCH v6 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref、remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   add Brian's patch "drm/bridge/synopsys: stop clobbering drvdata"
   (Link:https://patchwork.kernel.org/patch/10078493/)
   adjust drm/stm/dsi code for above
   drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
   keep "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
   into Brians "drm/bridge/synopsys: stop clobbering drvdata"
   add review tag and add some comments 
v5:
  1/3: fix stm part remove() directly referencing the static
   dw_mipi_dsi_stm_plat_data struct.
  3/3: keep our power domain enabled while touching GRF
v6:
  3/3: just change func dw_mipi_encoder_disable name to
   dw_mipi_dsi_encoder_disable

Nickey Yang (3):
  drm/bridge/synopsys: dsi: stop clobbering drvdata
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  |   36 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  785 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |   10 +-
 include/drm/bridge/dw_mipi_dsi.h   |   17 +-
 10 files changed, 840 insertions(+), 1388 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH v6 2/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
Reviewed-by: Brian Norris 
---
 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 --
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..ce4c1fc 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,12 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
+   mipi_in: port@0 {
+   reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +57,16 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +77,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v6 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

From: Brian Norris 

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris 
Signed-off-by: Nickey Yang 
Link:https://patchwork.kernel.org/patch/10078493/

---
Changes

v4:
- Add From tag,update subject line
- keep patch "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
  in this piece together.

v5:
- remove Review & Ack tag
- fix remove() directly referencing the static
  dw_mipi_dsi_stm_plat_data struct.

 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 ++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 10 +---
 include/drm/bridge/dw_mipi_dsi.h  | 17 -
 3 files changed, 30 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   dev_set_drvdata(dev, dsi);
-
return dsi;
 }
 
@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 /*
  * Probe/remove API, used from platforms based on the DRM bridge API.
  */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
 {
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 
-void dw_mipi_dsi_remove(struct platform_device *pdev)
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);
 
__dw_mipi_dsi_remove(dsi);
@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
 {
struct dw_mipi_dsi *dsi;
int ret;
 
dsi = __dw_mipi_dsi_probe(pdev, plat_data);
if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;
 
ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}
 
-   return 0;
+   return dsi;
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 
-void dw_mipi_dsi_unbind(struct device *dev)
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
-
__dw_mipi_dsi_remove(dsi);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..05787fa 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
 struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
 };
 
 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -318,10 +319,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(dsi->dmd);
}
 
return ret;
@@ -329,10 +331,10 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
 
 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev)
 {
-   struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
+   struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev);
 
clk_disable_

[PATCH v6 3/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
Signed-off-by: Brian Norris 
Reviewed-by: Brian Norris 
Reviewed-by: Sean Paul 
---
change:

v2:
   add err_pllref, remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
  return -EINVAL when can not get best_freq
  add a clarifying comment when get vco
  add review tag
v5:
  keep our power domain enabled while touching GRF
v6:
  change func dw_mipi_encoder_disable name to
  dw_mipi_dsi_encoder_disable

 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  785 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 789 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW 

[PATCH v7 2/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
Reviewed-by: Brian Norris 
---
 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 --
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..ce4c1fc 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,12 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
+   mipi_in: port@0 {
+   reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +57,16 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +77,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v7 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref、remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   add Brian's patch "drm/bridge/synopsys: stop clobbering drvdata"
   (Link:https://patchwork.kernel.org/patch/10078493/)
   adjust drm/stm/dsi code for above
   drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
   keep "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
   into Brians "drm/bridge/synopsys: stop clobbering drvdata"
   add review tag and add some comments 
v5:
  1/3: fix stm part remove() directly referencing the static
   dw_mipi_dsi_stm_plat_data struct.
  3/3: keep our power domain enabled while touching GRF
v6:
  3/3: just change func dw_mipi_encoder_disable name to
   dw_mipi_dsi_encoder_disable
v7:
  1/3: add missing platform_set_drvdata in stm part.

Nickey Yang (3):
  drm/bridge/synopsys: dsi: stop clobbering drvdata
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  |   36 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  785 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |   12 +-
 include/drm/bridge/dw_mipi_dsi.h   |   17 +-
 10 files changed, 842 insertions(+), 1388 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH v7 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

From: Brian Norris 

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris 
Signed-off-by: Nickey Yang 
Link:https://patchwork.kernel.org/patch/10078493/

---
Changes

v4:
- Add From tag,update subject line
- keep patch "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
  in this piece together.

v5:
- remove Review & Ack tag
- fix remove() directly referencing the static
  dw_mipi_dsi_stm_plat_data struct.

v7:
- add missing platform_set_drvdata in stm part.

 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 ++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 ++---
 include/drm/bridge/dw_mipi_dsi.h  | 17 -
 3 files changed, 32 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   dev_set_drvdata(dev, dsi);
-
return dsi;
 }
 
@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 /*
  * Probe/remove API, used from platforms based on the DRM bridge API.
  */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
 {
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 
-void dw_mipi_dsi_remove(struct platform_device *pdev)
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);
 
__dw_mipi_dsi_remove(dsi);
@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
 {
struct dw_mipi_dsi *dsi;
int ret;
 
dsi = __dw_mipi_dsi_probe(pdev, plat_data);
if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;
 
ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}
 
-   return 0;
+   return dsi;
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 
-void dw_mipi_dsi_unbind(struct device *dev)
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
-
__dw_mipi_dsi_remove(dsi);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..c1ed691 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
 struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
 };
 
 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -290,6 +291,8 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
if (!dsi)
return -ENOMEM;
 
+   platform_set_drvdata(pdev, dsi);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
DRM_ERROR("Unable to get resource\n");
@@ -318,10 +321,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(

[PATCH v7 3/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
Signed-off-by: Brian Norris 
Reviewed-by: Brian Norris 
Reviewed-by: Sean Paul 
---
changes:

v2:
   add err_pllref, remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
  return -EINVAL when can not get best_freq
  add a clarifying comment when get vco
  add review tag
v5:
  keep our power domain enabled while touching GRF
v6:
  change func name dw_mipi_encoder_disable to
  dw_mipi_dsi_encoder_disable

 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  785 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 789 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW 

Re: [PATCH v6 3/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Hi Brian,


On 2017年12月07日 05:52, Brian Norris wrote:

Hi Nickey, others,

I just want to highlight a thing or two here. Otherwise, my
'Reviewed-by' still basically stands (FWIW).

On Wed, Dec 06, 2017 at 05:08:21PM +0800, Nickey Yang wrote:

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
Signed-off-by: Brian Norris 
Reviewed-by: Brian Norris 
Reviewed-by: Sean Paul 
---
change:

v2:
add err_pllref, remove unnecessary encoder.enable & disable
correct spelling mistakes
v3:
call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
fix typo, use of_device_get_match_data(),
change some ‘bind()’ logic into 'probe()'
add 'dev_set_drvdata()'
v4:
   return -EINVAL when can not get best_freq
   add a clarifying comment when get vco
   add review tag
v5:
   keep our power domain enabled while touching GRF
v6:
   change func dw_mipi_encoder_disable name to
   dw_mipi_dsi_encoder_disable

We noticed a regression w.r.t. pm_runtime_*() handling using this patch,
hence the pm_runtime changes in v5/v6. We actually need to keep our
power domain enabled in the mode_set() function, where we start to
configure some Rockchip-specific registers (GRF). More on that below.


  drivers/gpu/drm/rockchip/Kconfig|2 +-
  drivers/gpu/drm/rockchip/Makefile   |2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
  drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  785 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
  6 files changed, 789 insertions(+), 1353 deletions(-)
  delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
  create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c


...


diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
new file mode 100644
index 000..66ab6fe
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
@@ -0,0 +1,785 @@

...


+static void dw_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+struct drm_display_mode *mode,
+struct drm_display_mode *adjusted)
+{
+   struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
+   const struct rockchip_dw_dsi_chip_data *cdata = dsi->cdata;
+   int val, ret, mux;
+
+   mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
+   &dsi->encoder);
+   if (mux < 0)
+   return;
+   /*
+* For the RK3399, the clk of grf must be enabled before writing grf
+* register. And for RK3288 or other soc, this grf_clk must be NULL,
+* the clk_prepare_enable return true directly.
+*/
+   ret = clk_prepare_enable(dsi->grf_clk);
+   if (ret) {
+   DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
+   return;
+   }
+   pm_runtime_get_sync(dsi->dev);

What happens if there's a clk_prepare_enable() failure or failure to
retrieve the endpoint ID earlier in this function? You won't call
pm_runtime_get_*()...but might we still see a call to
dw_mipi_dsi_encoder_disable(), which would mean we get unbalanced
runtime PM status?

So should we change this to
1、remove dw_mipi_dsi_encoder_disable, and in
dw_mipi_dsi_encoder_mode_set:
   drm_of_encoder_active_endpoint_id  ->
      clk_prepare_enable ->
     pm_runtime_get_sync ->
   grf_config ->
     pm_runtime_put_sync ->
      clk_prepare_disable?
or
2、use dw_mipi_dsi_encoder_disable, and in
dw_mipi_dsi_encoder_mode_set:
   pm_runtime_get_sync ->
 drm_of_encoder_active_endpoint_id  ->
        clk_prepare_enable ->
   grf_config ->
    clk_prepare_disable?
and call pm_runtime_put_sync if there is a failure in
drm_of_encoder_active_endpoint_id or clk_prepare_enable


Also (and more importantly), is it fair to do all of this in mode_set()?
I believe Archit asked about this before, and the reason we're doing
this stuff in mode_set() now (where previously, the Rockchip driver was
doing it in ->enable()) is because when Philippe extracted the synopsys
bridge driver, that code migrated to ->mode_set().

But, I'm reading the comments on drm_encoder_helper_funcs::mode_set, and
I see:

 /**
  * @mode_set:
  *
  * This callback is used to update the display mode of an encoder.
  *
  * Note that the display pipe is completely off when this function is
  * called. Drivers which need hardware to be running before they 
program
  * the new display mode (because they implement runtime PM) should not
  * use this hook, because 

[PATCH 1/3] of: Add vendor prefix for kingdisplay

[Nickey Yang]

Kingdisplay Technology Co., Ltd, established in
China Shenzhen in 2006, is a national high-tech
enterprise specializing in the R&D, manufacturing
and marketing of TFT-LCM and touch panel.

Signed-off-by: Nickey Yang 
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt 
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 1ea1fd4..506aaa3 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -173,6 +173,7 @@ keithkoep   Keith & Koep GmbH
 keymileKeymile GmbH
 khadas Khadas
 kinetic Kinetic Technologies
+kingdisplayKing & Display Technology Co., Ltd.
 kingnovel  Kingnovel Technology Co., Ltd.
 kosagi Sutajio Ko-Usagi PTE Ltd.
 kyoKyocera Corporation
-- 
1.9.1

[PATCH 2/3] drm/panel: add Kingdisplay kd097d04 panel driver

[Nickey Yang]

Support Kingdisplay kd097d04 9.7" 1536x2048 TFT LCD panel,
it is a MIPI DSI panel.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/panel/Kconfig  |  11 +
 drivers/gpu/drm/panel/Makefile |   1 +
 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c | 485 +
 3 files changed, 497 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d84a031..8b1f0bd 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -50,6 +50,17 @@ config DRM_PANEL_JDI_LT070ME05000
  The panel has a 1200(RGB)??1920 (WUXGA) resolution and uses
  24 bit per pixel.
 
+config DRM_PANEL_KINGDISPLAY_KD097D04
+   tristate "Kingdisplay kd097d04 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to enable support for Kingdisplay kd097d04
+ TFT-LCD modules. The panel has a 1536x2048 resolution and uses
+ 24 bit RGB per pixel. It provides a MIPI DSI interface to
+ the host and has a built-in LED backlight.
+
 config DRM_PANEL_SAMSUNG_LD9040
tristate "Samsung LD9040 RGB/SPI panel"
depends on OF && SPI
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 9f6610d..2548931 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
 obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
+obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
 obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
 obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += 
panel-panasonic-vvx10f034n00.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
diff --git a/drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c 
b/drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c
new file mode 100644
index 000..359cd34
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct kingdisplay_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *link;
+
+   struct backlight_device *backlight;
+   struct regulator *supply;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+};
+
+struct kingdisplay_pannel_cmd {
+   char cmd;
+   char data;
+};
+
+static const struct kingdisplay_pannel_cmd init_code[] = {
+   /* voltage setting */
+   { 0xB0, 0x00 },
+   { 0xB2, 0x02 },
+   { 0xB3, 0x11 },
+   { 0xB4, 0x00 },
+   { 0xB6, 0x80 },
+   /* VCOM disable */
+   { 0xB8, 0x80 },
+   { 0xBA, 0x43 },
+   /* VCOM setting */
+   { 0xBB, 0x53 },
+   /* VSP setting */
+   { 0xBC, 0x0A },
+   /* VSN setting */
+   { 0xBD, 0x4A },
+   /* VGH setting */
+   { 0xBE, 0x2F },
+   /* VGL setting */
+   { 0xBF, 0x1A },
+   { 0xF0, 0x39 },
+   { 0xF1, 0x21 },
+   /* Gamma setting */
+   { 0xB0, 0x02 },
+   { 0xC0, 0x00 },
+   { 0xC1, 0x01 },
+   { 0xC2, 0x0B },
+   { 0xC3, 0x15 },
+   { 0xC4, 0x22 },
+   { 0xC5, 0x11 },
+   { 0xC6, 0x15 },
+   { 0xC7, 0x19 },
+   { 0xC8, 0x1A },
+   { 0xC9, 0x16 },
+   { 0xCA, 0x18 },
+   { 0xCB, 0x13 },
+   { 0xCC, 0x18 },
+   { 0xCD, 0x13 },
+   { 0xCE, 0x1C },
+   { 0xCF, 0x19 },
+   { 0xD0, 0x21 },
+   { 0xD1, 0x2C },
+   { 0xD2, 0x2F },
+   { 0xD3, 0x30 },
+   { 0xD4, 0x19 },
+   { 0xD5, 0x1F },
+   { 0xD6, 0x00 },
+   { 0xD7, 0x01 },
+   { 0xD8, 0x0B },
+   { 0xD9, 0x15 },
+   { 0xDA, 0x22 },
+   { 0xDB, 0x11 },
+   { 0xDC, 0x15 },
+   { 0xDD, 0x19 },
+   { 0xDE, 0x1A },
+   { 0xDF, 0x16 },
+   { 0xE0, 0x18 },
+   { 0xE1, 0x13 },
+   { 0xE2, 0x18 },
+   { 0xE3, 0x13 },
+   { 0xE4, 0x1C },
+   { 0xE5, 0x19 },
+   { 0xE6, 0x21 },
+   { 0xE7, 0x2C },
+   { 0xE8, 0x2F },
+   { 0xE9, 0x30 },
+   { 0xEA, 0x19 },
+   { 0xEB, 0x1F },
+   /* GOA MUX setting */
+   { 0xB0, 0x01 },
+   { 0xC0, 0x10 },
+   { 0xC1, 0x0F },
+   { 0xC2, 0x0E },
+   { 0xC3, 0x0D },
+   { 0xC4, 0x0C },
+   { 0

[PATCH 3/3] dt-bindings: Add KINGDISPLAY KD097D04 panel bindings

[Nickey Yang]

The KINGDISPLAY KD097D04 is a 9.7" panel with a 1536x2048
resolution and connected to DSI using 8 lanes.

Signed-off-by: Nickey Yang 
---
 .../display/panel/kingdisplay,kd097d04.txt | 22 ++
 1 file changed, 22 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt 
b/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt
new file mode 100644
index 000..164a5fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/kingdisplay,kd097d04.txt
@@ -0,0 +1,22 @@
+Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel
+
+Required properties:
+- compatible: should be "kingdisplay,kd097d04"
+- reg: DSI virtual channel of the peripheral
+- power-supply: phandle of the regulator that provides the supply voltage
+- enable-gpios: panel enable gpio
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+   &mipi_dsi {
+   panel {
+   compatible = "kingdisplay,kd097d04";
+   reg = <0>;
+   power-supply = <...>;
+   backlight = <&backlight>;
+   enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+   };
+   };
-- 
1.9.1

[PATCH 1/7] drm/rockchip/dsi: correct Feedback divider setting

[Nickey Yang]

This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
3、Make the previously configured Feedback divider(LSB)
factors effective

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 83 ++
 1 file changed, 54 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9a20b9d..52698b7 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -228,7 +228,7 @@
 #define LOW_PROGRAM_EN 0
 #define HIGH_PROGRAM_ENBIT(7)
 #define LOOP_DIV_LOW_SEL(val)  (((val) - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0xf)
 #define PLL_LOOP_DIV_ENBIT(5)
 #define PLL_INPUT_DIV_EN   BIT(4)
 
@@ -461,6 +461,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
 LOW_PROGRAM_EN);
+   dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
 HIGH_PROGRAM_EN);
dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
@@ -521,11 +522,16 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
struct drm_display_mode *mode)
 {
-   unsigned int i, pre;
-   unsigned long mpclk, pllref, tmp;
-   unsigned int m = 1, n = 1, target_mbps = 1000;
+   unsigned long mpclk, tmp;
+   unsigned int target_mbps = 1000;
unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
int bpp;
+   unsigned long best_freq = 0;
+   unsigned long fvco_min, fvco_max, fin ,fout;
+   unsigned int min_prediv, max_prediv;
+   unsigned int _prediv, uninitialized_var(best_prediv);
+   unsigned long _fbdiv, uninitialized_var(best_fbdiv);
+   unsigned long min_delta = UINT_MAX;
 
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
if (bpp < 0) {
@@ -544,34 +550,53 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi 
*dsi,
dev_err(dsi->dev, "DPHY clock frequency is out of 
range\n");
}
 
-   pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
-   tmp = pllref;
-
-   /*
-* The limits on the PLL divisor are:
-*
-*  5MHz <= (pllref / n) <= 40MHz
-*
-* we walk over these values in descreasing order so that if we hit
-* an exact match for target_mbps it is more likely that "m" will be
-* even.
-*
-* TODO: ensure that "m" is even after this loop.
-*/
-   for (i = pllref / 5; i > (pllref / 40); i--) {
-   pre = pllref / i;
-   if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
-   tmp = target_mbps % pre;
-   n = i;
-   m = target_mbps / pre;
+   fin = clk_get_rate(dsi->pllref_clk);
+   fout = target_mbps * USEC_PER_SEC;
+
+   /* constraint: 5Mhz < Fref / N < 40MHz */
+   min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
+   max_prediv = fin / (5 * USEC_PER_SEC);
+
+   /* constraint: 80MHz < Fvco < 1500Mhz */
+   fvco_min = 80 * USEC_PER_SEC;
+   fvco_max = 1500 * USEC_PER_SEC;
+
+   for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
+   u32 delta;
+   /* Fvco = Fref * M / N */
+   tmp = fout * _prediv;
+   do_div(tmp, fin);
+   _fbdiv = tmp;
+   /*
+* Due to the use of a "by 2 pre-scaler," the range of the
+* feedback multiplication value M is limited to even division
+* numbers, and m must be greater than 12, less than 1000.
+*/
+   if (_fbdiv < 12 || _fbdiv > 1000)
+   continue;
+
+   if (_fbdiv % 2)
+   ++_fbdiv;
+
+   tmp = (u64)_fbdiv * fin;
+   do_div(tmp, _prediv);
+   if (tmp < fvco_min || tmp > fvco_max)
+   continue;
+
+   delta = abs(fout - tmp);
+   if (delta < min_delta) {
+

[PATCH 3/7] dt-bindings: add the rockchip,dual-channel for dw-mipi-dsi

[Nickey Yang]

Configure dsi slave channel when driving a panel
which needs 2 DSI links.

Signed-off-by: Nickey Yang 
---
 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt   | 2 ++
 1 file changed, 2 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..e13e1a3 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -19,6 +19,8 @@ Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
 - resets: list of phandle + reset specifier pairs, as described in [3].
 - reset-names: string reset name, must be "apb".
+- rockchip,dual-channel: configure dsi slave channel when driving a panel
+  which needs 2 DSI links.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
-- 
1.9.1

[PATCH 4/7] drm/rockchip/dsi: correct phy parameter setting

[Nickey Yang]

As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency,so fix it.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 70 +++---
 1 file changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9265b7f..d5250e8 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -228,10 +228,10 @@
 #define VCO_IN_CAP_CON_HIGH(0x2 << 1)
 #define REF_BIAS_CUR_SEL   BIT(0)
 
-#define CP_CURRENT_3MA BIT(3)
+#define CP_CURRENT_SEL(val)((val) & 0xf)
 #define CP_PROGRAM_EN  BIT(7)
 #define LPF_PROGRAM_EN BIT(6)
-#define LPF_RESISTORS_20_KOHM  0
+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
 
 #define HSFREQRANGE_SEL(val)   (((val) & 0x3f) << 1)
 
@@ -340,32 +340,44 @@ enum dw_mipi_dsi_mode {
DW_MIPI_DSI_VID_MODE,
 };
 
-struct dphy_pll_testdin_map {
+struct dphy_pll_parameter_map {
unsigned int max_mbps;
-   u8 testdin;
+   u8 hsfreqrange;
+   u8 icpctrl;
+   u8 lpfctrl;
 };
 
 /* The table is based on 27MHz DPHY pll reference clock. */
-static const struct dphy_pll_testdin_map dptdin_map[] = {
-   {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
-   { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
-   { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
-   { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
-   { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
-   { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
-   { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
-   {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
-   {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
-   {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+static const struct dphy_pll_parameter_map dppa_map[] = {
+   {  90, 0x00, 0x1 ,0x02}, { 100, 0x10 ,0x1, 0x02},
+   { 110, 0x20, 0x1, 0x02}, { 130, 0x01, 0x1, 0x01},
+   { 140, 0x11, 0x1, 0x01}, { 150, 0x21, 0x1, 0x01},
+   { 170, 0x02, 0x9, 0x02}, { 180, 0x12, 0x9, 0x02},
+   { 200, 0x22, 0x9, 0x02}, { 220, 0x03, 0x2, 0x02},
+   { 240, 0x13, 0x2, 0x02}, { 250, 0x23, 0x2, 0x02},
+   { 270, 0x04, 0x9, 0x04}, { 300, 0x14, 0x9, 0x04},
+   { 330, 0x05, 0x1, 0x01}, { 360, 0x15, 0x1, 0x01},
+   { 400, 0x25, 0x1, 0x01}, { 450, 0x06, 0x6, 0x04},
+   { 500, 0x16, 0x6, 0x04}, { 550, 0x07, 0x6, 0x08},
+   { 600, 0x17, 0x6, 0x08}, { 650, 0x08, 0x6, 0x04},
+   { 700, 0x18, 0x6, 0x04}, { 750, 0x09, 0x6, 0x04},
+   { 800, 0x19, 0x6, 0x04}, { 850, 0x29, 0x6, 0x04},
+   { 900, 0x39, 0x6, 0x04}, { 950, 0x0a, 0xb, 0x10},
+   {1000, 0x1a, 0xb, 0x10}, {1050, 0x2a, 0xb, 0x10},
+   {1100, 0x3a, 0xb, 0x10}, {1150, 0x0b, 0xb, 0x08},
+   {1200, 0x1b, 0xb, 0x08}, {1250, 0x2b, 0xb, 0x08},
+   {1300, 0x3b, 0xb, 0x08}, {1350, 0x0c, 0xb, 0x08},
+   {1400, 0x1c, 0xb, 0x08}, {1450, 0x2c, 0xb, 0x08},
+   {1500, 0x3c, 0xb, 0x08}
 };
 
-static int max_mbps_to_testdin(unsigned int max_mbps)
+static int max_mbps_to_parameter(unsigned int max_mbps)
 {
int i;
 
-   for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
-   if (dptdin_map[i].max_mbps > max_mbps)
-   return dptdin_map[i].testdin;
+   for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
+   if (dppa_map[i].max_mbps > max_mbps)
+   return i;
 
return -EINVAL;
 }
@@ -447,16 +459,16 @@ static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, 
int ns)
 
 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 {
-   int ret, testdin, vco, val;
+   int ret, i, vco, val;
 
vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
 
-   testdin = max_mbps_to_testdin(dsi->lane_mbps);
-   if (testdin < 0) {
+   i = max_mbps_to_parameter(dsi->lane_mbps);
+   if (i < 0) {
dev_err(dsi->dev,
-   "failed to get testdin for %dmbps lane clock\n",
+   "failed to get parameter for %dmbps lane clock\n",
dsi->lane_mbps);
-   return testdin;
+   return i;
}
 
/* Start by clearing PHY state */
@@ -475,12 +487,10 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 VCO_IN_CAP_CON_LOW |
 REF_BIAS_CUR_SEL);
 
-   dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
+   dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_SEL(dppa_map[i].icpctrl));
dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
-LPF_RESISTORS_20_KOHM);
-
-   dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_S

[PATCH 2/7] drm/rockchip/dsi: add dual mipi channel support

[Nickey Yang]

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 353 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   2 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   3 +
 4 files changed, 257 insertions(+), 102 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 52698b7..9265b7f 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -42,6 +42,17 @@
 #define RK3399_GRF_SOC_CON22   0x6258
 #define RK3399_GRF_DSI_MODE0x
 
+/* disable turndisable, forcetxstopmode, forcerxmode, enable */
+#define RK3399_GRF_SOC_CON23   0x625c
+#define RK3399_GRF_DSI1_MODE1  0x
+#define RK3399_GRF_DSI1_ENABLE 0x000f000f
+/* disable basedir and enable clk*/
+#define RK3399_GRF_SOC_CON24   0x6260
+#define RK3399_TXRX_MASTERSLAVEZ   BIT(7)
+#define RK3399_TXRX_ENABLECLK  BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
+#define RK3399_GRF_DSI1_MODE2  0x00e00080
+
 #define DSI_VERSION0x00
 #define DSI_PWR_UP 0x04
 #define RESET  0
@@ -282,6 +293,12 @@ struct dw_mipi_dsi_plat_data {
u32 grf_switch_reg;
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
+   u32 grf_dsi1_mode;
+   u32 grf_dsi1_mode_reg1;
+   u32 dsi1_basedir;
+   u32 dsi1_masterslavez;
+   u32 dsi1_enableclk;
+   u32 grf_dsi1_mode_reg2;
unsigned int flags;
unsigned int max_data_lanes;
 };
@@ -300,6 +317,12 @@ struct dw_mipi_dsi {
struct clk *pclk;
struct clk *phy_cfg_clk;
 
+   /* dual-channel */
+   struct dw_mipi_dsi *master;
+   struct dw_mipi_dsi *slave;
+   struct device_node *panel_node;
+   int id;
+
int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
@@ -526,6 +549,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
unsigned int target_mbps = 1000;
unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
int bpp;
+   int lanes = dsi->lanes;
unsigned long best_freq = 0;
unsigned long fvco_min, fvco_max, fin ,fout;
unsigned int min_prediv, max_prediv;
@@ -540,10 +564,13 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi 
*dsi,
return bpp;
}
 
+   if (dsi->slave || dsi->master)
+   lanes = dsi->lanes * 2;
+
mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
if (mpclk) {
/* take 1 / 0.8, since mbps must big than bandwidth of RGB */
-   tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
+   tmp = mpclk * (bpp / lanes) * 10 / 8;
if (tmp < max_mbps)
target_mbps = tmp;
else
@@ -605,17 +632,26 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
   struct mipi_dsi_device *device)
 {
struct dw_mipi_dsi *dsi = host_to_dsi(host);
+   int lanes = dsi->slave ? device->lanes / 2 : device->lanes;
 
-   if (device->lanes > dsi->pdata->max_data_lanes) {
+   if (lanes > dsi->pdata->max_data_lanes) {
dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
-   device->lanes);
+   lanes);
return -EINVAL;
}
 
-   dsi->lanes = device->lanes;
+   dsi->lanes = lanes;
dsi->channel = device->channel;
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;
+
+   if (dsi->slave) {
+   dsi->slave->lanes = lanes;
+   dsi->slave->channel = device->channel;
+   dsi->slave->format = device->format;
+   dsi->slave->mode_flags = device->mode_flags;
+   }
+
dsi->panel = of_drm_find_panel(device->dev.of_node);
if (dsi->panel)
return drm_panel_attach(dsi->panel, &dsi->connector);
@@ -745,15 +781,22 @@ static ssize_t dw_mipi_dsi_host_transfer(struct 
mipi_dsi_host *host,
int ret;
 
dw_mipi_message_config(dsi, msg);
+   if (dsi->slave)
+   dw_mipi_message_config(dsi->slave, msg);
 
switch (msg->type) {
case MIPI_DSI_DCS_SHORT_WRITE:
case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+   case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
+   if (dsi->slave)
+   ret = dw_mipi_dsi_dcs_short_write(dsi->slave, msg);
break;
case MIPI_DSI_DCS_LONG_WR

[PATCH 5/7] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock

[Nickey Yang]

clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d79e9b3..6aa43fd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1629,7 +1629,7 @@
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff96 0x0 0x8000>;
interrupts = ;
-   clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+   clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
 <&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
power-domains = <&power RK3399_PD_VIO>;
-- 
1.9.1

[PATCH v2 5/8] drm/rockchip/dsi: Use DRM_DEV_ERROR instead of dev_err

[Nickey Yang]

Rockchip driver has been moved to using the
DRM_DEV_ERROR log messages, so change all
instances of dev_err.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 62 +-
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 20d3f36..2ff5da6 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -555,7 +555,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 
i = max_mbps_to_parameter(dsi->lane_mbps);
if (i < 0) {
-   dev_err(dsi->dev,
+   DRM_DEV_ERROR(dsi->dev,
"failed to get parameter for %dmbps lane clock\n",
dsi->lane_mbps);
return i;
@@ -568,7 +568,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 
ret = clk_prepare_enable(dsi->phy_cfg_clk);
if (ret) {
-   dev_err(dsi->dev, "Failed to enable phy_cfg_clk\n");
+   DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
return ret;
}
 
@@ -652,7 +652,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
if (ret < 0) {
-   dev_err(dsi->dev, "failed to wait for phy lock state\n");
+   DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n");
goto phy_init_end;
}
 
@@ -660,7 +660,7 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 val, val & STOP_STATE_CLK_LANE, 1000,
 PHY_STATUS_TIMEOUT_US);
if (ret < 0)
-   dev_err(dsi->dev,
+   DRM_DEV_ERROR(dsi->dev,
"failed to wait for phy clk lane stop state\n");
 
 phy_init_end:
@@ -686,7 +686,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
 
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
if (bpp < 0) {
-   dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
+   DRM_DEV_ERROR(dsi->dev, "failed to get bpp for pixel format 
%d\n",
dsi->format);
return bpp;
}
@@ -701,7 +701,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
if (tmp < max_mbps)
target_mbps = tmp;
else
-   dev_err(dsi->dev, "DPHY clock frequency is out of 
range\n");
+   DRM_DEV_ERROR(dsi->dev, "DPHY clock frequency is out of 
range\n");
}
 
fin = clk_get_rate(dsi->pllref_clk);
@@ -751,7 +751,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
dsi->input_div = best_prediv;
dsi->feedback_div = best_fbdiv;
} else
-   dev_err(dsi->dev, "Can not find best_freq for DPHY\n");
+   DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
 
return 0;
 }
@@ -763,7 +763,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
int lanes = dsi->slave ? device->lanes / 2 : device->lanes;
 
if (lanes > dsi->pdata->max_data_lanes) {
-   dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
+   DRM_DEV_ERROR(dsi->dev, "the number of data lanes(%u) is too 
many\n",
lanes);
return -EINVAL;
}
@@ -821,7 +821,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
*dsi, u32 hdr_val)
 val, !(val & GEN_CMD_FULL), 1000,
 CMD_PKT_STATUS_TIMEOUT_US);
if (ret < 0) {
-   dev_err(dsi->dev, "failed to get available command FIFO\n");
+   DRM_DEV_ERROR(dsi->dev, "failed to get available command 
FIFO\n");
return ret;
}
 
@@ -832,7 +832,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
*dsi, u32 hdr_val)
 val, (val & mask) == mask,
 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret < 0) {
-   dev_err(dsi->dev, "failed to write command FIFO\n");
+   DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n");
return ret;
}
 
@@ -852,7 +852,7 @@ static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi 
*dsi,
data |= tx_buf[1] << 8;
 
if (

[PATCH v2 2/8] drm/rockchip/dsi: add dual mipi channel support

[Nickey Yang]

This patch add dual mipi channel support:
1.add definition of dsi1 register and grf operation.
2.dsi0 and dsi1 will work in master and slave mode
when driving dual mipi panel.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 390 
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   1 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |   2 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   3 +
 4 files changed, 292 insertions(+), 104 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index c933a3a..191037c 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -39,8 +39,58 @@
 #define RK3399_DSI1_SEL_VOP_LITBIT(4)
 
 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
+#define RK3399_GRF_SOC_CON22   0x6258
+#define DPHY_TX0_TURNREQUEST_SET   ((0xf << 12) << 16)
+#define DPHY_TX0_TURNREQUEST_DISABLE   (0x0 << 12)
+#define DPHY_TX0_TURNREQUEST_ENABLE(0xf << 12)
+#define DPHY_TX0_TURNDISABLE_SET   ((0xf << 8) << 16)
+#define DPHY_TX0_TURNDISABLE_DISABLE   (0x0 << 8)
+#define DPHY_TX0_TURNDISABLE_ENABLE(0xf << 8)
+#define DPHY_TX0_FORCETXSTOPMODE_SET   ((0xf << 4) << 16)
+#define DPHY_TX0_FORCETXSTOPMODE_DISABLE   (0x0 << 4)
+#define DPHY_TX0_FORCETXSTOPMODE_ENABLE(0xf << 4)
+#define DPHY_TX0_FORCETRXMODE_SET  ((0xf << 0) << 16)
+#define DPHY_TX0_FORCETRXMODE_DISABLE  0x0
+#define DPHY_TX0_FORCETRXMODE_ENABLE   0xf
+#define RK3399_GRF_DSI_MODE((DPHY_TX0_TURNREQUEST_SET | \
+DPHY_TX0_TURNDISABLE_SET | \
+DPHY_TX0_FORCETXSTOPMODE_SET | 
\
+DPHY_TX0_FORCETRXMODE_SET) | \
+(DPHY_TX0_TURNREQUEST_DISABLE 
| \
+DPHY_TX0_TURNDISABLE_DISABLE | 
\
+
DPHY_TX0_FORCETXSTOPMODE_DISABLE | \
+DPHY_TX0_FORCETRXMODE_DISABLE))
+
+
+/* disable turndisable, forcetxstopmode, forcerxmode, enable */
+#define RK3399_GRF_SOC_CON23   0x625c
+#define DPHY_TX1RX1_TURNDISABLE_SET((0xf << 12) << 16)
+#define DPHY_TX1RX1_TURNDISABLE_DISABLE(0x0 << 12)
+#define DPHY_TX1RX1_TURNDISABLE_ENABLE (0xf << 12)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_SET((0xf << 8) << 16)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_DISABLE(0x0 << 8)
+#define DPHY_TX1RX1_FORCETXSTOPMODE_ENABLE (0xf << 8)
+#define DPHY_TX1RX1_FORCERXMODE_SET((0xf << 4) << 16)
+#define DPHY_TX1RX1_FORCERXMODE_DISABLE(0x0 << 4)
+#define DPHY_TX1RX1_FORCERXMODE_ENABLE (0xf << 4)
+#define DPHY_TX1RX1_ENABLE_SET ((0xf << 0) << 16)
+#define DPHY_TX1RX1_ENABLE_DISABLE 0x0
+#define DPHY_TX1RX1_ENABLE_ENABLE  0xf
+#define RK3399_GRF_DSI1_MODE   ((DPHY_TX1RX1_TURNDISABLE_SET | 
\
+
DPHY_TX1RX1_FORCETXSTOPMODE_SET | \
+DPHY_TX1RX1_FORCERXMODE_SET | \
+DPHY_TX1RX1_ENABLE_SET) | \
+(DPHY_TX0_TURNREQUEST_DISABLE 
| \
+DPHY_TX0_TURNDISABLE_DISABLE | 
\
+
DPHY_TX0_FORCETXSTOPMODE_DISABLE | \
+DPHY_TX0_FORCETRXMODE_DISABLE))
+#define RK3399_GRF_DSI1_ENABLE ((DPHY_TX1RX1_ENABLE_SET | \
+ DPHY_TX1RX1_ENABLE_ENABLE))
+
+#define RK3399_GRF_SOC_CON24   0x6260
+#define RK3399_TXRX_MASTERSLAVEZ   BIT(7)
+#define RK3399_TXRX_ENABLECLK  BIT(6)
+#define RK3399_TXRX_BASEDIRBIT(5)
 
 #define DSI_VERSION0x00
 #define DSI_PWR_UP 0x04
@@ -304,6 +354,13 @@ struct dw_mipi_dsi_plat_data {
u32 grf_switch_reg;
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
+   u32 grf_dsi1_mode;
+   u32 grf_dsi1_enable;
+   u32 grf_dsi1_mode_reg1;
+   u32 dsi1_basedir;
+   u32 dsi1_masterslavez;
+   u32 dsi1_enableclk;
+   u32 grf_dsi1_mode_reg2;
unsigned int flags;
unsigned int max_data_lanes;
 };
@@ -322,6 +379,10 @@ struct dw_

[PATCH v2 1/8] drm/rockchip/dsi: correct Feedback divider setting

[Nickey Yang]

This patch correct Feedback divider setting:
1、Set Feedback divider [8:5] when HIGH_PROGRAM_EN
2、Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
3、Make the previously configured Feedback divider(LSB)
factors effective
4、Add the definition of the MIPI PHY register.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 219 ++---
 1 file changed, 146 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 9a20b9d..c933a3a 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -228,7 +228,7 @@
 #define LOW_PROGRAM_EN 0
 #define HIGH_PROGRAM_ENBIT(7)
 #define LOOP_DIV_LOW_SEL(val)  (((val) - 1) & 0x1f)
-#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0xf)
 #define PLL_LOOP_DIV_ENBIT(5)
 #define PLL_INPUT_DIV_EN   BIT(4)
 
@@ -254,6 +254,28 @@
 #define DW_MIPI_NEEDS_PHY_CFG_CLK  BIT(0)
 #define DW_MIPI_NEEDS_GRF_CLK  BIT(1)
 
+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
+#define PLL_LPF_AND_CP_CONTROL 0x12
+#define PLL_INPUT_DIVIDER_RATIO 0x17
+#define PLL_LOOP_DIVIDER_RATIO 0x18
+#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
+#define BANDGAP_AND_BIAS_CONTROL 0x20
+#define TERMINATION_RESISTER_CONTROL 0x21
+#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
+#define HS_RX_CONTROL_OF_LANE_0 0x44
+#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
+#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
+#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
+#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
+#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
+#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
+#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
+#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
+#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
+#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
+#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
+
 enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -447,53 +469,79 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
return ret;
}
 
-   dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE |
-VCO_RANGE_CON_SEL(vco) |
-VCO_IN_CAP_CON_LOW |
-REF_BIAS_CUR_SEL);
-
-   dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA);
-   dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
-LPF_RESISTORS_20_KOHM);
-
-   dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
-
-   dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div));
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) |
-LOW_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
-HIGH_PROGRAM_EN);
-   dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
-
-   dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN |
-BIASEXTR_SEL(BIASEXTR_127_7));
-   dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN |
-BANDGAP_SEL(BANDGAP_96_10));
-
-   dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
-BIAS_BLOCK_ON | BANDGAP_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
-SETRD_MAX | TER_RESISTORS_ON);
-   dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
-SETRD_MAX | POWER_MANAGE |
-TER_RESISTORS_ON);
-
-   dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
-   dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
-   dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
-   dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
-
-   dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
-   dw_mipi_dsi_phy_write(dsi, 0x71,
+   dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
+ BYPASS_VCO_RANGE |
+   

[PATCH v2 3/8] dt-bindings: add the rockchip,dual-channel for dw-mipi-dsi

[Nickey Yang]

Configure dsi slave channel when driving a panel
which needs 2 DSI links.

Signed-off-by: Nickey Yang 
---
 .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt   | 2 ++
 1 file changed, 2 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..a2bea22 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -19,6 +19,8 @@ Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
 - resets: list of phandle + reset specifier pairs, as described in [3].
 - reset-names: string reset name, must be "apb".
+- rockchip,dual-channel: phandle to a 2nd DSI channel, useful as a slave
+channel when driving a panel which needs 2 DSI links.
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
-- 
1.9.1

[PATCH v2 4/8] drm/rockchip/dsi: correct phy parameter setting

[Nickey Yang]

As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0>
should depend on frequency,so fix it.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 98 --
 1 file changed, 70 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 191037c..20d3f36 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -267,10 +267,21 @@
 #define VCO_IN_CAP_CON_HIGH(0x2 << 1)
 #define REF_BIAS_CUR_SEL   BIT(0)
 
-#define CP_CURRENT_3MA BIT(3)
+#define CP_CURRENT_1_5UA   0x1
+#define CP_CURRENT_4_5UA   0x2
+#define CP_CURRENT_7_5UA   0x6
+#define CP_CURRENT_6UA 0x9
+#define CP_CURRENT_12UA0xb
+#define CP_CURRENT_SEL(val)((val) & 0xf)
 #define CP_PROGRAM_EN  BIT(7)
+
+#define LPF_RESISTORS_15_5KOHM 0x1
+#define LPF_RESISTORS_13KOHM   0x2
+#define LPF_RESISTORS_11_5KOHM 0x4
+#define LPF_RESISTORS_10_5KOHM 0x8
+#define LPF_RESISTORS_8KOHM0x10
 #define LPF_PROGRAM_EN BIT(6)
-#define LPF_RESISTORS_20_KOHM  0
+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
 
 #define HSFREQRANGE_SEL(val)   (((val) & 0x3f) << 1)
 
@@ -400,32 +411,63 @@ enum dw_mipi_dsi_mode {
DW_MIPI_DSI_VID_MODE,
 };
 
-struct dphy_pll_testdin_map {
+struct dphy_pll_parameter_map {
unsigned int max_mbps;
-   u8 testdin;
+   u8 hsfreqrange;
+   u8 icpctrl;
+   u8 lpfctrl;
 };
 
 /* The table is based on 27MHz DPHY pll reference clock. */
-static const struct dphy_pll_testdin_map dptdin_map[] = {
-   {  90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
-   { 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
-   { 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
-   { 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
-   { 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
-   { 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
-   { 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
-   {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
-   {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
-   {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
+static const struct dphy_pll_parameter_map dppa_map[] = {
+   {  90, 0x00, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   { 100, 0x10, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   { 110, 0x20, CP_CURRENT_1_5UA, LPF_RESISTORS_13KOHM},
+   { 130, 0x01, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 140, 0x11, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 150, 0x21, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 170, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 180, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 200, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
+   { 220, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 240, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 250, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
+   { 270, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+   { 300, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
+   { 330, 0x05, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 360, 0x15, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 400, 0x25, CP_CURRENT_1_5UA, LPF_RESISTORS_15_5KOHM},
+   { 450, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 500, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 550, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+   { 600, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
+   { 650, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 700, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 750, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 800, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 850, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 900, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
+   { 950, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1000, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1050, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1100, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
+   {1150, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1200, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1250, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1300, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1350, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1400, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1450, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
+   {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}
 };
 
-static int max_mbps_to_testdin(unsigned int max_mbps)
+static int max_mbps_to_parameter(unsigned int max_mbps)
 {
int i;
 
-   for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
- 

[PATCH v2 8/8] arm64: dts: rockchip: add mipi_dsi1 support for rk3399

[Nickey Yang]

This patch adds the mipi_dsi1 related needed information.
e.g.: interrupts, grf, clocks, ports and so on.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 39 
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index ab7629c..82c03fa 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1515,6 +1515,11 @@
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
+
+   vopl_out_mipi1: endpoint@3 {
+   reg = <3>;
+   remote-endpoint = <&mipi1_in_vopl>;
+   };
};
};
 
@@ -1562,6 +1567,11 @@
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
+
+   vopb_out_mipi1: endpoint@3 {
+   reg = <3>;
+   remote-endpoint = <&mipi1_in_vopb>;
+   };
};
};
 
@@ -1653,6 +1663,35 @@
};
};
 
+   mipi_dsi1: mipi@ff968000 {
+   compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+   reg = <0x0 0xff968000 0x0 0x8000>;
+   interrupts = ;
+   clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
+   clock-names = "ref", "pclk", "phy_cfg", "grf";
+   power-domains = <&power RK3399_PD_VIO>;
+   rockchip,grf = <&grf>;
+   status = "disabled";
+
+   ports {
+   mipi1_in: port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi1_in_vopb: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&vopb_out_mipi1>;
+   };
+
+   mipi1_in_vopl: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = <&vopl_out_mipi1>;
+   };
+   };
+   };
+   };
+
edp: edp@ff97 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff97 0x0 0x8000>;
-- 
1.9.1

[PATCH v2 7/8] arm64: dts: rockchip: add a grf clk for dw-mipi-dsi

[Nickey Yang]

The clk of grf must be enabled before writing grf
register for rk3399.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6aa43fd..ab7629c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1630,8 +1630,8 @@
reg = <0x0 0xff96 0x0 0x8000>;
interrupts = ;
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
-<&cru SCLK_DPHY_TX0_CFG>;
-   clock-names = "ref", "pclk", "phy_cfg";
+<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
+   clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
-- 
1.9.1

[PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock

[Nickey Yang]

Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399.
clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll
So correct it.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d79e9b3..6aa43fd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1629,7 +1629,7 @@
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff96 0x0 0x8000>;
interrupts = ;
-   clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+   clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
 <&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
power-domains = <&power RK3399_PD_VIO>;
-- 
1.9.1

[PATCH 1/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update documentation of device tree bindings for the rockchip
DSI controller based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 ++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..336909d 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,10 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   mipi_in: port@0 {
+   reg = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +55,14 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +73,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH 3/3] arm64: dts: rockchip: update mipi node for RK3399

[Nickey Yang]

This patch update mipi node for RK3399 DSI controller
based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d340b58a..0ac67a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1652,9 +1652,11 @@
status = "disabled";
 
ports {
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_in: port@0 {
+   reg = <0>;
 
mipi_in_vopb: endpoint@0 {
reg = <0>;
-- 
1.9.1

[PATCH 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

Nickey Yang (3):
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver
  arm64: dts: rockchip: update mipi node for RK3399

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 arch/arm64/boot/dts/rockchip/rk3399.dtsi   |8 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  756 +++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 8 files changed, 784 insertions(+), 1360 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH 2/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  756 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 760 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
-
-#define DSI_DPI_LP_CMD_TIM 0x18
-#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
-#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
-
-#define DSI_DBI_CFG0x20
-#define DSI_DBI_CMDSIZE0x28
-
-#define DSI_PCKHDL_CFG 0x2c
-#define EN_CRC_RX  BIT(4)
-#define EN_ECC_RX  BIT(3)
-#define E

[PATCH v2 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref???remove unnecessary encoder.enable & disable
   correct spelling mistakes


Nickey Yang (3):
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver
  arm64: dts: rockchip: update mipi node for RK3399

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 arch/arm64/boot/dts/rockchip/rk3399.dtsi   |8 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  756 +++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 8 files changed, 784 insertions(+), 1360 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH v2 1/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update documentation of device tree bindings for the rockchip
DSI controller based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 ++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..336909d 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,10 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   mipi_in: port@0 {
+   reg = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +55,14 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +73,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v2 2/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  756 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 760 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
-
-#define DSI_DPI_LP_CMD_TIM 0x18
-#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
-#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
-
-#define DSI_DBI_CFG0x20
-#define DSI_DBI_CMDSIZE0x28
-
-#define DSI_PCKHDL_CFG 0x2c
-#define EN_CRC_RX  BIT(4)
-#define EN_ECC_RX  BIT(3)
-#define E

[PATCH v2 3/3] arm64: dts: rockchip: update mipi node for RK3399

[Nickey Yang]

This patch update mipi node for RK3399 DSI controller
based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d340b58a..0ac67a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1652,9 +1652,11 @@
status = "disabled";
 
ports {
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_in: port@0 {
+   reg = <0>;
 
mipi_in_vopb: endpoint@0 {
reg = <0>;
-- 
1.9.1

Re: [PATCH 2/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Hi Brian,


Below comments fixed in 
patch-v2：https://patchwork.kernel.org/patch/10078527/

but ："get_drvdata()"

Thanks for review.
Nickey.

On 2017年11月28日 09:51, Brian Norris wrote:

Hi Nickey,

Several people already made comments on the initial version of this
patch [1], and I don't think you've caught them all here yet. I'll
repeat a few. Not sure if I've caught them all.

[1] 
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/780120

On Tue, Nov 28, 2017 at 09:13:35AM +0800, Nickey Yang wrote:

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
---
  drivers/gpu/drm/rockchip/Kconfig|2 +-
  drivers/gpu/drm/rockchip/Makefile   |2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
  drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  756 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
  6 files changed, 760 insertions(+), 1353 deletions(-)
  delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
  create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c


...


diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
new file mode 100644
index 000..32be430
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c
@@ -0,0 +1,756 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author:
+ *  Chris Zhong 
+ *  Nickey Yang 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DSI_PHY_TST_CTRL0  0xb4
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0xb8
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN   0
+#define PHY_TESTDOUT(n)(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+#define BYPASS_VCO_RANGE   BIT(7)
+#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
+#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
+#define VCO_IN_CAP_CON_LOW (0x1 << 1)
+#define VCO_IN_CAP_CON_HIGH(0x2 << 1)
+#define REF_BIAS_CUR_SEL   BIT(0)
+
+#define CP_CURRENT_3UA 0x1
+#define CP_CURRENT_4_5UA   0x2
+#define CP_CURRENT_7_5UA   0x6
+#define CP_CURRENT_6UA 0x9
+#define CP_CURRENT_12UA0xb
+#define CP_CURRENT_SEL(val)((val) & 0xf)
+#define CP_PROGRAM_EN  BIT(7)
+
+#define LPF_RESISTORS_15_5KOHM 0x1
+#define LPF_RESISTORS_13KOHM   0x2
+#define LPF_RESISTORS_11_5KOHM 0x4
+#define LPF_RESISTORS_10_5KOHM 0x8
+#define LPF_RESISTORS_8KOHM0x10
+#define LPF_PROGRAM_EN BIT(6)
+#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
+
+#define HSFREQRANGE_SEL(val)   (((val) & 0x3f) << 1)
+
+#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
+#define LOW_PROGRAM_EN 0
+#define HIGH_PROGRAM_ENBIT(7)
+#define LOOP_DIV_LOW_SEL(val)  (((val) - 1) & 0x1f)
+#define LOOP_DIV_HIGH_SEL(val) val) - 1) >> 5) & 0xf)
+#define PLL_LOOP_DIV_ENBIT(5)
+#define PLL_INPUT_DIV_EN   BIT(4)
+
+#define POWER_CONTROL  BIT(6)
+#define INTERNAL_REG_CURRENT   BIT(3)
+#define BIAS_BLOCK_ON  BIT(2)
+#define BANDGAP_ON BIT(0)
+
+#define TER_RESISTOR_HIGH  BIT(7)
+#defineTER_RESISTOR_LOW0
+#define LEVEL_SHIFTERS_ON  BIT(6)
+#define TER_CAL_DONE   BIT(5)
+#define SETRD_MAX  (0x7 << 2)
+#define POWER_MANAGE   BIT(1)
+#define TER_RESISTORS_ON   BIT(0)
+
+#define BIASEXTR_SEL(val)  ((val) & 0x7)
+#define BANDGAP_SEL(val)   ((val) & 0x7)
+#define TLP_PROGRAM_EN BIT(7)
+#define THS_PRE_PROGRAM_EN BIT(7)
+#define THS_ZERO_PROGRAM_ENBIT(6)
+
+#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL   0x10
+#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
+#define PLL_LPF_AND_CP_CONTROL 0x12
+#define PLL_INPUT_DIVIDER_RATIO0x17
+#define PLL_LOOP_DIVIDER_RATIO 0x18
+#define PL

[PATCH v3 1/5] drm/bridge/synopsys: stop clobbering drvdata

[Nickey Yang]

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris 
Reviewed-by: Matthias Kaehlcke 
Reviewed-by: Archit Taneja 
Acked-by: Philippe Cornu 
Link:https://patchwork.kernel.org/patch/10078493/
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 ++-
 include/drm/bridge/dw_mipi_dsi.h  | 17 -
 2 files changed, 24 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   dev_set_drvdata(dev, dsi);
-
return dsi;
 }
 
@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 /*
  * Probe/remove API, used from platforms based on the DRM bridge API.
  */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
 {
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 
-void dw_mipi_dsi_remove(struct platform_device *pdev)
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);
 
__dw_mipi_dsi_remove(dsi);
@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
 {
struct dw_mipi_dsi *dsi;
int ret;
 
dsi = __dw_mipi_dsi_probe(pdev, plat_data);
if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;
 
ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}
 
-   return 0;
+   return dsi;
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 
-void dw_mipi_dsi_unbind(struct device *dev)
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
-
__dw_mipi_dsi_remove(dsi);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index 9b30fec..d9c6d54 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -10,6 +10,8 @@
 #ifndef __DW_MIPI_DSI__
 #define __DW_MIPI_DSI__
 
+struct dw_mipi_dsi;
+
 struct dw_mipi_dsi_phy_ops {
int (*init)(void *priv_data);
int (*get_lane_mbps)(void *priv_data, struct drm_display_mode *mode,
@@ -29,11 +31,14 @@ struct dw_mipi_dsi_plat_data {
void *priv_data;
 };
 
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data);
-void dw_mipi_dsi_remove(struct platform_device *pdev);
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data);
-void dw_mipi_dsi_unbind(struct device *dev);
+struct dw_mipi_dsi *dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data
+ *plat_data);
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi);
+struct dw_mipi_dsi *dw_mipi_dsi_bind(struct platform_device *pdev,
+struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data
+*plat_data);
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi);
 
 #endif /* __DW_MIPI_DSI__ */
-- 
1.9.1

[PATCH v3 0/5] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref、remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   add Brian's patch "drm/bridge/synopsys: stop clobbering drvdata"
   (Link:https://patchwork.kernel.org/patch/10078493/)
   adjust drm/stm/dsi code for above
   drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'

Nickey Yang (5):
  drm/bridge/synopsys: stop clobbering drvdata
  drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver
  arm64: dts: rockchip: update mipi node for RK3399

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 arch/arm64/boot/dts/rockchip/rk3399.dtsi   |8 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  |   36 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  764 +++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |8 +-
 include/drm/bridge/dw_mipi_dsi.h   |   17 +-
 11 files changed, 821 insertions(+), 1392 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

[PATCH v3 3/5] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update documentation of device tree bindings for the rockchip
DSI controller based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 ++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..336909d 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,10 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   mipi_in: port@0 {
+   reg = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +55,14 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +73,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v3 4/5] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

v2:
   add err_pllref, remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  764 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 768 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
-
-#define DSI_DPI_LP_CMD_TIM 0x18
-#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
-#defi

[PATCH v3 2/5] drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove

[Nickey Yang]

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.
So adjust it.

Signed-off-by: Nickey Yang 
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..80f9950 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
 struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
 };
 
 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -318,10 +319,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(dsi->dmd);
}
 
return ret;
@@ -332,7 +334,7 @@ static int dw_mipi_dsi_stm_remove(struct platform_device 
*pdev)
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
 
clk_disable_unprepare(dsi->pllref_clk);
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi->dmd);
 
return 0;
 }
-- 
1.9.1

[PATCH v3 5/5] arm64: dts: rockchip: update mipi node for RK3399

[Nickey Yang]

This patch update mipi node for RK3399 DSI controller
based on the Synopsys DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d340b58a..0ac67a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1652,9 +1652,11 @@
status = "disabled";
 
ports {
-   mipi_in: port {
-   #address-cells = <1>;
-   #size-cells = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_in: port@0 {
+   reg = <0>;
 
mipi_in_vopb: endpoint@0 {
reg = <0>;
-- 
1.9.1

Re: [PATCH v2 2/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Hi Archit,


On 2017年11月28日 14:27, Archit Taneja wrote:

Hi,

Thanks a lot for working on this. Some comments below.

Those comments have fixed in patch_v3 
https://patchwork.kernel.org/patch/10079857/

Thanks for review.

On 11/28/2017 07:25 AM, Nickey Yang wrote:

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
---
  drivers/gpu/drm/rockchip/Kconfig    |    2 +-
  drivers/gpu/drm/rockchip/Makefile   |    2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 
---

  drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  756 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |    2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |    2 +-
  6 files changed, 760 insertions(+), 1353 deletions(-)
  delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
  create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig 
b/drivers/gpu/drm/rockchip/Kconfig

index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
  select VIDEOMODE_HELPERS
  select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
  select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-    select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+    select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
  select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
  help
    Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile

index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o

  rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
  rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
  diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c

deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME    "dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON6    0x025c
-#define RK3288_DSI0_SEL_VOP_LIT    BIT(6)
-#define RK3288_DSI1_SEL_VOP_LIT    BIT(9)
-
-#define RK3399_GRF_SOC_CON20    0x6250
-#define RK3399_DSI0_SEL_VOP_LIT    BIT(0)
-#define RK3399_DSI1_SEL_VOP_LIT    BIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22    0x6258
-#define RK3399_GRF_DSI_MODE    0x
-
-#define DSI_VERSION    0x00
-#define DSI_PWR_UP    0x04
-#define RESET    0
-#define POWERUP    BIT(0)
-
-#define DSI_CLKMGR_CFG    0x08
-#define TO_CLK_DIVIDSION(div)    (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)    (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID    0x0c
-#define DPI_VID(vid)    (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING    0x10
-#define EN18_LOOSELY    BIT(8)
-#define DPI_COLOR_CODING_16BIT_1    0x0
-#define DPI_COLOR_CODING_16BIT_2    0x1
-#define DPI_COLOR_CODING_16BIT_3    0x2
-#define DPI_COLOR_CODING_18BIT_1    0x3
-#define DPI_COLOR_CODING_18BIT_2    0x4
-#define DPI_COLOR_CODING_24BIT    0x5
-
-#define DSI_DPI_CFG_POL    0x14
-#define COLORM_ACTIVE_LOW    BIT(4)
-#define SHUTD_ACTIVE_LOW    BIT(3)
-#define HSYNC_ACTIVE_LOW    BIT(2)
-#define VSYNC_ACTIVE_LOW    BIT(1)
-#define DATAEN_ACTIVE_LOW    BIT(0)
-
-#define DSI_DPI_LP_CMD_TIM    0x18
-#define OUTVACT_LPCMD_TIME(p)    (((p) & 0xff) << 16)
-#define INVACT_LPCMD_TIME(p)    ((p) & 0xff)
-
-#define DSI_DBI_CFG    0x20
-#define DSI_DBI_CMDSIZE    0x28
-
-#define DSI_PCKHDL_CFG    0x2c
-#define EN_CRC_RX    BIT(4)
-#define EN_

[PATCH v4 2/3] dt-bindings: display: rockchip: update DSI controller

[Nickey Yang]

This patch update describe panel/port links, including
unit addresses in documentation of device tree bindings
for the rockchip DSI controller based on the Synopsys
DesignWare MIPI DSI host controller.

Signed-off-by: Nickey Yang 

---
Changes in v4:
- keep the -cells properties

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  | 23 --
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 6bb59ab..ce4c1fc 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -14,6 +14,8 @@ Required properties:
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
 
 Optional properties:
 - power-domains: a phandle to mipi dsi power domain node.
@@ -40,11 +42,12 @@ Example:
ports {
#address-cells = <1>;
#size-cells = <0>;
-   reg = <1>;
 
-   mipi_in: port {
+   mipi_in: port@0 {
+   reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
+
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
@@ -54,6 +57,16 @@ Example:
remote-endpoint = <&vopl_out_mipi>;
};
};
+
+   mipi_out: port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi_out_panel: endpoint {
+   remote-endpoint = <&panel_in_mipi>;
+   };
+   };
};
 
panel {
@@ -64,5 +77,11 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+   port {
+   panel_in_mipi: endpoint {
+   remote-endpoint = <&mipi_out_panel>;
+   };
+   };
};
};
-- 
1.9.1

[PATCH v4 3/3] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: Nickey Yang 
Reviewed-by: Brian Norris 
Reviewed-by: Sean Paul 
---
Changes log:
v2:
   add err_pllref, remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
  return -EINVAL when can not get best_freq
  add a clarifying comment when get vco
  add review tag

 drivers/gpu/drm/rockchip/Kconfig|2 +-
 drivers/gpu/drm/rockchip/Makefile   |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  777 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
 6 files changed, 781 insertions(+), 1353 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
 rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-

[PATCH v4 1/3] drm/bridge/synopsys: dsi: stop clobbering drvdata

[Nickey Yang]

From: Brian Norris 

Bridge drivers/helpers shouldn't be clobbering the drvdata, since a
parent driver might need to own this. Instead, let's return our
'dw_mipi_dsi' object and have callers pass that back to us for removal.

Signed-off-by: Brian Norris 
Signed-off-by: Nickey Yang 
Reviewed-by: Matthias Kaehlcke 
Reviewed-by: Archit Taneja 
Acked-by: Philippe Cornu 
Link:https://patchwork.kernel.org/patch/10078493/

---
Changes in v4:
- Add From tag,update subject line
- keep patch "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
  in this piece together.

 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 36 ++-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  8 +++---
 include/drm/bridge/dw_mipi_dsi.h  | 17 -
 3 files changed, 29 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d9cca4f..c39c7dc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -922,8 +922,6 @@ static int dw_mipi_dsi_bridge_attach(struct drm_bridge 
*bridge)
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   dev_set_drvdata(dev, dsi);
-
return dsi;
 }
 
@@ -935,23 +933,16 @@ static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 /*
  * Probe/remove API, used from platforms based on the DRM bridge API.
  */
-int dw_mipi_dsi_probe(struct platform_device *pdev,
- const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_probe(struct platform_device *pdev,
+ const struct dw_mipi_dsi_plat_data *plat_data)
 {
-   struct dw_mipi_dsi *dsi;
-
-   dsi = __dw_mipi_dsi_probe(pdev, plat_data);
-   if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
-
-   return 0;
+   return __dw_mipi_dsi_probe(pdev, plat_data);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 
-void dw_mipi_dsi_remove(struct platform_device *pdev)
+void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
-
mipi_dsi_host_unregister(&dsi->dsi_host);
 
__dw_mipi_dsi_remove(dsi);
@@ -961,31 +952,30 @@ void dw_mipi_dsi_remove(struct platform_device *pdev)
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
-const struct dw_mipi_dsi_plat_data *plat_data)
+struct dw_mipi_dsi *
+dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
+const struct dw_mipi_dsi_plat_data *plat_data)
 {
struct dw_mipi_dsi *dsi;
int ret;
 
dsi = __dw_mipi_dsi_probe(pdev, plat_data);
if (IS_ERR(dsi))
-   return PTR_ERR(dsi);
+   return dsi;
 
ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
if (ret) {
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi);
DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
+   return ERR_PTR(ret);
}
 
-   return 0;
+   return dsi;
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 
-void dw_mipi_dsi_unbind(struct device *dev)
+void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 {
-   struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
-
__dw_mipi_dsi_remove(dsi);
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index e5b6310..80f9950 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -66,6 +66,7 @@ enum dsi_color {
 struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+   struct dw_mipi_dsi *dmd;
 };
 
 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
@@ -318,10 +319,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
-   ret = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
-   if (ret) {
+   dsi->dmd = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
+   if (IS_ERR(dsi->dmd)) {
DRM_ERROR("Failed to initialize mipi dsi host\n");
clk_disable_unprepare(dsi->pllref_clk);
+   return PTR_ERR(dsi->dmd);
}
 
return ret;
@@ -332,7 +334,7 @@ static int dw_mipi_dsi_stm_remove(struct platform_device 
*pdev)
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
 
clk_disable_unprepare(dsi->pllref_clk);
-   dw_mipi_dsi_remove(pdev);
+   dw_mipi_dsi_remove(dsi->dmd);
 
return 0;
 }
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/in

[PATCH v4 0/3] Update ROCKCHIP DSI driver that uses dw-mipi-dsi bridge

[Nickey Yang]

We now have a generic dw-mipi-dsi bridge driver.So we send
this patchs to moving rockchip dw-mipi-dsi driver to that
in order to add new features(dual mipi support).
Update ROCKCHIP DSI controller driver that uses the Synopsys
DesignWare MIPI DSI host controller bridge.

ChangeLog:
v2:
   add err_pllref、remove unnecessary encoder.enable & disable
   correct spelling mistakes
v3:
   add Brian's patch "drm/bridge/synopsys: stop clobbering drvdata"
   (Link:https://patchwork.kernel.org/patch/10078493/)
   adjust drm/stm/dsi code for above
   drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver:
   call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
   fix typo, use of_device_get_match_data(),
   change some ‘bind()’ logic into 'probe()'
   add 'dev_set_drvdata()'
v4:
   keep "drm/stm: dsi: Adjust dw_mipi_dsi_probe and remove"
   into Brians "drm/bridge/synopsys: stop clobbering drvdata"
   add review tag and add some comments 

Nickey Yang (3):
  drm/bridge/synopsys: dsi: stop clobbering drvdata
  dt-bindings: display: rockchip: update DSI controller
  drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

 .../display/rockchip/dw_mipi_dsi_rockchip.txt  |   23 +-
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  |   36 +-
 drivers/gpu/drm/rockchip/Kconfig   |2 +-
 drivers/gpu/drm/rockchip/Makefile  |2 +-
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1349 
 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c|  777 +++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c|2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h|2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |8 +-
 include/drm/bridge/dw_mipi_dsi.h   |   17 +-
 10 files changed, 831 insertions(+), 1387 deletions(-)
 delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

-- 
1.9.1

Re: [PATCH v3 4/5] drm/rockchip: Add ROCKCHIP DW MIPI DSI controller driver

[Nickey Yang]

Hi Matthias,


On 2017年11月29日 04:48, Matthias Kaehlcke wrote:

El Tue, Nov 28, 2017 at 07:20:05PM +0800 Nickey Yang ha dit:


Add the ROCKCHIP DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

v2:
add err_pllref, remove unnecessary encoder.enable & disable
correct spelling mistakes
v3:
call dw_mipi_dsi_unbind() in dw_mipi_dsi_rockchip_unbind()
fix typo, use of_device_get_match_data(),
change some ‘bind()’ logic into 'probe()'
add 'dev_set_drvdata()'

Signed-off-by: Nickey Yang 
---
  drivers/gpu/drm/rockchip/Kconfig|2 +-
  drivers/gpu/drm/rockchip/Makefile   |2 +-
  drivers/gpu/drm/rockchip/dw-mipi-dsi.c  | 1349 ---
  drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c |  764 +
  drivers/gpu/drm/rockchip/rockchip_drm_drv.c |2 +-
  drivers/gpu/drm/rockchip/rockchip_drm_drv.h |2 +-
  6 files changed, 768 insertions(+), 1353 deletions(-)
  delete mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c
  create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi_rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 0ccc762..9eb4795 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -7,7 +7,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
-   select DRM_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+   select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
  Choose this option if you have a Rockchip soc chipset.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index a314e21..c05fe47 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -11,7 +11,7 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += 
rockchip_drm_fbdev.o
  rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
  rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi_rockchip.o
  rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
  rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
  
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c

deleted file mode 100644
index b15755b..000
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ /dev/null
@@ -1,1349 +0,0 @@
-/*
- * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "rockchip_drm_drv.h"
-#include "rockchip_drm_vop.h"
-
-#define DRIVER_NAME"dw-mipi-dsi"
-
-#define RK3288_GRF_SOC_CON60x025c
-#define RK3288_DSI0_SEL_VOP_LITBIT(6)
-#define RK3288_DSI1_SEL_VOP_LITBIT(9)
-
-#define RK3399_GRF_SOC_CON20   0x6250
-#define RK3399_DSI0_SEL_VOP_LITBIT(0)
-#define RK3399_DSI1_SEL_VOP_LITBIT(4)
-
-/* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
-#define RK3399_GRF_SOC_CON22   0x6258
-#define RK3399_GRF_DSI_MODE0x
-
-#define DSI_VERSION0x00
-#define DSI_PWR_UP 0x04
-#define RESET  0
-#define POWERUPBIT(0)
-
-#define DSI_CLKMGR_CFG 0x08
-#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
-#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
-
-#define DSI_DPI_VCID   0x0c
-#define DPI_VID(vid)   (((vid) & 0x3) << 0)
-
-#define DSI_DPI_COLOR_CODING   0x10
-#define EN18_LOOSELY   BIT(8)
-#define DPI_COLOR_CODING_16BIT_1   0x0
-#define DPI_COLOR_CODING_16BIT_2   0x1
-#define DPI_COLOR_CODING_16BIT_3   0x2
-#define DPI_COLOR_CODING_18BIT_1   0x3
-#define DPI_COLOR_CODING_18BIT_2   0x4
-#define DPI_COLOR_CODING_24BIT 0x5
-
-#define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define D

Re: [PATCH v3 5/6] dt-bindings: add the rockchip, dual-channel for dw-mipi-dsi

[Nickey Yang]

Hi Archit,


On 2017年10月26日 12:53, Archit Taneja wrote:



On 10/25/2017 09:21 AM, Nickey Yang wrote:

Configure dsi slave channel when driving a panel
which needs 2 DSI links.

Signed-off-by: Nickey Yang 
---
.../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 ++
  1 file changed, 2 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt 


index 6bb59ab..a2bea22 100644
--- 
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ 
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

@@ -19,6 +19,8 @@ Optional properties:
  - power-domains: a phandle to mipi dsi power domain node.
  - resets: list of phandle + reset specifier pairs, as described in 
[3].

  - reset-names: string reset name, must be "apb".
+- rockchip,dual-channel: phandle to a 2nd DSI channel, useful as a 
slave

+channel when driving a panel which needs 2 DSI links.
The example below is how dual DSI bindings could look like. Let me 
know what

you think of it.

If both DSI outputs drive the same device (i.e, point to the same 
panel DT

node), then I think it's reasonable enough to assume that the DSIs are
operating in a 'dual-channel' mode. That being said, we still need DT to
describe which of the DSIs generates the clock for both the channels. 
This

is done with the 'clock-master' DT binding.

Thanks,
Archit

mipi_dsi: mipi@ff96 {
...
...

clock-master;    /* implies that this DSI instance drivers the clock
 * for both the DSIs.
 */

ports {
    mipi_in: port {
    ...
    ...
    };

    /* add extra output ports for both DSIs */
    mipi_out: port {
    mipi_panel_out: endpoint {
    remote-endpoint = <&panel_in_channel0>;
    };
    };
};

panel {
    ...
    ...
    /*
 * panel node can describe its input ports, if both the DSIs 
output
 * ports are connected to the same device (i.e, the same DSI 
panel),

 * we can assume that the DSIs need to operate in dual DSI mode
 */
    ports {
    ...
    port@0 {
    panel_in_channel0: endpoint {
    remote-endpoint = <&mipi_panel_out>;
    };
    };

    port@1 {
    panel_in_channel1: endpoint {
    remote-endpoint = <&mipi1_panel_out>;
    };

    };
    };
};
};


mipi_dsi1: mipi@ff968000 {
...
...

ports {
    mipi1_in: port {
    ...
    ...
    };

    mipi1_out: port {
    mipi1_panel_out: endpoint {
    remote-endpoint = <&panel_in_channel1>;
    };
    };
};
};


I try to follow as you suggested,use

mipi_dsi: mipi@ff96 {
    ...
    ...
    clock-master;    /* implies that this DSI instance drivers the clock
             * for both the DSIs.
             */
    ports {
        mipi_in: port {
            ...
            ...
        };
        /* add extra output ports for both DSIs */
        mipi_out: port {
            mipi_panel_out: endpoint {
                remote-endpoint = <&panel_in_channel0>;
            };
        };
    };
    panel {
        ...
        ...
        /*
         * panel node can describe its input ports, if both the DSIs output
         * ports are connected to the same device (i.e, the same DSI 
panel),

         * we can assume that the DSIs need to operate in dual DSI mode
         */
        ports {
            ...
            port@0 {
                panel_in_channel0: endpoint {
                    remote-endpoint = <&mipi_panel_out>;
                };
            };
            port@1 {
                panel_in_channel1: endpoint {
                    remote-endpoint = <&mipi1_panel_out>;
                };

            };
        };
    };
};

mipi_dsi1: mipi@ff968000 {
    ...
    ...
    ports {
        mipi1_in: port {
            ...
            ...
        };
        mipi1_out: port {
            mipi1_panel_out: endpoint {
                remote-endpoint = <&panel_in_channel1>;
            };
        };
    };
}

But it seems we can not use of_drm_find_panel(like below)

/*
    port = of_graph_get_port_by_id(dev->of_node, 1);
    if (port) {
    endpoint = of_get_child_by_name(port, "endpoint");
    of_node_put(port);
    if (!endpoint) {
    dev_err(dev, "no output endpoint found\n");
    return -EINVAL;
    }
    panel_node = of_graph_get_remote_port_parent(endpoint);
    of_node_put(endpoint);