[PATCH v2 0/3] Add support for Hisilicon Hi3521A SoC
Patched up with suggestions from Rob Herring, resend. Marty E. Plummer (3): clk: hisilicon: add CRG driver Hi3521A SoC arm: hisi: enable Hi3521A SoC arm: dts: add Hi3521A dts arch/arm/boot/dts/Makefile| 2 + arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 41 arch/arm/boot/dts/hi3521a.dtsi| 308 ++ arch/arm/mach-hisi/Kconfig| 6 + drivers/clk/hisilicon/Kconfig | 7 + drivers/clk/hisilicon/Makefile| 1 + drivers/clk/hisilicon/crg-hi3521a.c | 196 +++ include/dt-bindings/clock/hi3521a-clock.h | 23 +++ 8 files changed, 584 insertions(+) create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts create mode 100644 arch/arm/boot/dts/hi3521a.dtsi create mode 100644 drivers/clk/hisilicon/crg-hi3521a.c create mode 100644 include/dt-bindings/clock/hi3521a-clock.h -- 2.14.2
[PATCH v2 1/3] clk: hisilicon: add CRG driver Hi3521A SoC
Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
generates clock and reset signals used by other module blocks on SoC.
Signed-off-by: Marty E. Plummer
---
Changes in v2:
- Switched to SPDX tags and GPL-2.0+
drivers/clk/hisilicon/Kconfig | 7 ++
drivers/clk/hisilicon/Makefile| 1 +
drivers/clk/hisilicon/crg-hi3521a.c | 196 ++
include/dt-bindings/clock/hi3521a-clock.h | 23
4 files changed, 227 insertions(+)
create mode 100644 drivers/clk/hisilicon/crg-hi3521a.c
create mode 100644 include/dt-bindings/clock/hi3521a-clock.h
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 7098bfd32b1b..d93e3180a04f 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -14,6 +14,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3521A
+ bool "Hi3521A/Hi3520DV300 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3521a/hi3520dv300
+
config COMMON_CLK_HI3660
bool "Hi3660 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 1e4c3ddbad84..46f8d619c923 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_HIP04)+= clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
+obj-$(CONFIG_COMMON_CLK_HI3521A)+= crg-hi3521a.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/crg-hi3521a.c
b/drivers/clk/hisilicon/crg-hi3521a.c
new file mode 100644
index ..aea00fecdff3
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3521a.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2017 Marty E. Plummer
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include "clk.h"
+#include "reset.h"
+
+#define HI3521A_INNER_CLK_OFFSET 64
+#define HI3521A_FIXED_2M 65
+#define HI3521A_FIXED_24M 66
+#define HI3521A_FIXED_50M 67
+#define HI3521A_FIXED_83M 68
+#define HI3521A_FIXED_100M 69
+#define HI3521A_FIXED_150M 70
+#define HI3521A_FMC_MUX71
+#define HI3521A_UART_MUX 72
+
+#define HI3521A_NR_CLKS128
+
+struct hi3521a_crg_data {
+ struct hisi_clock_data *clk_data;
+ struct hisi_reset_controller *rstc;
+};
+
+static const struct hisi_fixed_rate_clock hi3521a_fixed_rate_clks[] = {
+ { HI3521A_FIXED_2M, "2m", NULL, 0, 200, },
+ { HI3521A_FIXED_24M, "24m", NULL, 0, 2400, },
+ { HI3521A_FIXED_50M, "50m", NULL, 0, 5000, },
+ { HI3521A_FIXED_83M, "83m", NULL, 0, 8300, },
+ { HI3521A_FIXED_100M, "100m", NULL, 0, 1, },
+ { HI3521A_FIXED_150M, "150m", NULL, 0, 15000, },
+};
+
+static const char *const uart_mux_p[] = { "50m", "2m", "24m", };
+static const char *const fmc_mux_p[] = { "24m", "83m", "150m", };
+
+static u32 uart_mux_table[] = {0, 1, 2};
+static u32 fmc_mux_table[] = {0, 1, 2};
+
+static const struct hisi_mux_clock hi3521a_mux_clks[] = {
+ { HI3521A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
+ CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table, },
+ { HI3521A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3521a_gate_clks[] = {
+ { HI3521A_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
+ 0x74, 1, 0, },
+ { HI3521A_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 15, 0, },
+ { HI3521A_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 16, 0, },
+ { HI3521A_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 17, 0, },
+ { HI3521A_SPI0_CLK, "clk_spi0", "50m", CLK_SET_RATE_PARENT,
+ 0x84, 13, 0, },
+ /* { HI3521A_ETH_CLK, "clk_eth", NULL, */
+ /* 0, 0x78, 1, 0, }, */
+ /* { HI3521A_ETH_MACIF_CLK, "clk_eth_macif", NULL, */
+ /* 0, 0x78, 3, 0 }, */
+};
+
+static struct hisi_clock_data *hi3521
[PATCH v2 3/3] arm: dts: add Hi3521A dts
Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
marketed under the name Samsung SDR-B74301N
Signed-off-by: Marty E. Plummer
---
Chages in v2:
- Use SPDX tag and GPL-2.0+
- Add memory addresses to some nodes
- Add arm arch timer
- Add more specific compatible strings to a few nodes.
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 41 +
arch/arm/boot/dts/hi3521a.dtsi | 308
3 files changed, 351 insertions(+)
create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts
create mode 100644 arch/arm/boot/dts/hi3521a.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faf46abaa4a2..e7b9b5dde20f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-sq201.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
+dtb-$(CONFIG_ARCH_HI3521A) += \
+ hi3521a-rs-dm290e.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
new file mode 100644
index ..3634fe96399e
--- /dev/null
+++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 Marty Plummer
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "hi3521a.dtsi"
+
+/ {
+ model = "RaySharp RS-DM-290E DVR Board";
+ compatible = "raysharp,rs-dm-290e", "hisilicon,hi3521a";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory@8 {
+ device_type = "memory";
+ reg = <0x8000 0xf0>;
+ };
+};
+
+&hi_sfc {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "mxicy,mx25l25635e","jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10400>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&dual_timer0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi
new file mode 100644
index ..49111272fd76
--- /dev/null
+++ b/arch/arm/boot/dts/hi3521a.dtsi
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) 2017 Marty Plummer
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <1 13 0xf08>,
+<1 14 0xf08>,
+<1 11 0xf08>,
+<1 10 0xf08>;
+ };
+
+ clk_3m: clk_3m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ hi_sfc: spi-nor-controller@1000 {
+ compatible = "hisilicon,hi3521a-spi-nor",
"hisilicon,fmc-spi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1000 0x1>, <0x1400 0x100>;
+ reg-names = "control", "memory";
+ clocks = <&crg HI3521A_FMC_CLK>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@10301000 {
+ compatible = "arm,pl390";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+ };
+
+ dmac: dma-controller@1006 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x1006 0x1000>;
+ interrupts = ;
+ status = "disabled";
+ };
+
+
[PATCH v2 2/3] arm: hisi: enable Hi3521A SoC
Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes hardware mutlimedia codec cores, commonly used in consumer cctv/dvr security systems and ipcameras. The arm core is a Cortex A7. Signed-off-by: Marty E. Plummer --- arch/arm/mach-hisi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 65a048fa08ec..26755414f862 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -12,6 +12,12 @@ if ARCH_HISI menu "Hisilicon platform type" +config ARCH_HI3521A + bool "Hisilicon Hi3521A/Hi3520DCV300 family" + depends on ARCH_MULTI_V7 + help + Support for Hisilicon Hi3521A/Hi3520DCV300 SoC family + config ARCH_HI3xxx bool "Hisilicon Hi36xx family" depends on ARCH_MULTI_V7 -- 2.14.2
[PATCH] drm/rockchip: typo: selet->select
Signed-off-by: Marty E. Plummer --- drivers/gpu/drm/rockchip/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 0ccc76217ee4..7d1ccc9efc76 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -23,7 +23,7 @@ config ROCKCHIP_ANALOGIX_DP help This selects support for Rockchip SoC specific extensions for the Analogix Core DP driver. If you want to enable DP - on RK3288 based SoC, you should selet this option. + on RK3288 based SoC, you should select this option. config ROCKCHIP_CDN_DP bool "Rockchip cdn DP" @@ -39,7 +39,7 @@ config ROCKCHIP_DW_HDMI help This selects support for Rockchip SoC specific extensions for the Synopsys DesignWare HDMI driver. If you want to - enable HDMI on RK3288 based SoC, you should selet this + enable HDMI on RK3288 based SoC, you should select this option. config ROCKCHIP_DW_MIPI_DSI @@ -47,7 +47,7 @@ config ROCKCHIP_DW_MIPI_DSI help This selects support for Rockchip SoC specific extensions for the Synopsys DesignWare HDMI driver. If you want to -enable MIPI DSI on RK3288 based SoC, you should selet this +enable MIPI DSI on RK3288 based SoC, you should select this option. config ROCKCHIP_INNO_HDMI -- 2.19.0
Re: [PATCH v2 1/3] clk: hisilicon: add CRG driver Hi3521A SoC
On Tue, Oct 24, 2017 at 01:42:50PM -0500, Rob Herring wrote: > On Tue, Oct 17, 2017 at 05:38:52PM -0500, Marty E. Plummer wrote: > > Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module > > generates clock and reset signals used by other module blocks on SoC. > > > > Signed-off-by: Marty E. Plummer > > --- > > Changes in v2: > > - Switched to SPDX tags and GPL-2.0+ > > > > drivers/clk/hisilicon/Kconfig | 7 ++ > > drivers/clk/hisilicon/Makefile| 1 + > > drivers/clk/hisilicon/crg-hi3521a.c | 196 > > ++ > > > include/dt-bindings/clock/hi3521a-clock.h | 23 > > Acked-by: Rob Herring Actually nack this for now. I need to change some stuff over to use a different clock for the sp804 timer@1200, apparently I'm going to need to use CLK_OF_DECLARE to get the clock in question working that early in boot.
[RFC RESEND 3/3] arm: dts: add Hi3521A dts
Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
marketed under the name Samsung SDR-B74301N
Signed-off-by: Marty E. Plummer
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++
arch/arm/boot/dts/hi3521a.dtsi | 310
3 files changed, 364 insertions(+)
create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts
create mode 100644 arch/arm/boot/dts/hi3521a.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index faf46abaa4a2..e7b9b5dde20f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-sq201.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
+dtb-$(CONFIG_ARCH_HI3521A) += \
+ hi3521a-rs-dm290e.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
new file mode 100644
index ..b32c8392c93f
--- /dev/null
+++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 Marty Plummer
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "hi3521a.dtsi"
+
+/ {
+ model = "RaySharp RS-DM-290E DVR Board";
+ compatible = "hisilicon,hi3521a";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0xf0>;
+ };
+};
+
+&hi_sfc {
+ status = "okay";
+ spi-nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10400>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&dual_timer0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi
new file mode 100644
index ..2af746fdec46
--- /dev/null
+++ b/arch/arm/boot/dts/hi3521a.dtsi
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2017 Marty Plummer
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ chosen { };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+ };
+
+ hi_sfc: spi-nor-controller@1000 {
+ compatible = "hisilicon,hi3521a-spi-nor",
"hisilicon,fmc-spi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1000 0x1>, <0x1400 0x100>;
+ reg-names = "control", "memory";
+ clocks = <&crg HI3521A_FMC_CLK>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@1030 {
+ compatible = "arm,pl390";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+ };
+
+ clk_3m: clk_3m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300>;
+ }
[RFC RESEND 0/3] Add support for Hisilicon Hi3521A SoC
Greetings, I'd like the community's feedback on the following patchset. I've attempted to split my changes up in what I believe to be a sensible setup. The device I'm working against is the 'SamsungSV SDR-B74301' HD CCTV surveillance system, which uses a Hisilicon Hi3521A arm SoC as its basis. Resending due to a typo, s/primcell/primecell/ Marty E. Plummer (3): clk: hisilicon: add CRG driver Hi3521A SoC arm: hisi: enable Hi3521A SoC arm: dts: add Hi3521A dts arch/arm/boot/dts/Makefile| 2 + arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 + arch/arm/boot/dts/hi3521a.dtsi| 310 ++ arch/arm/mach-hisi/Kconfig| 6 + drivers/clk/hisilicon/Kconfig | 7 + drivers/clk/hisilicon/Makefile| 1 + drivers/clk/hisilicon/crg-hi3521a.c | 207 include/dt-bindings/clock/hi3521a-clock.h | 34 8 files changed, 619 insertions(+) create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts create mode 100644 arch/arm/boot/dts/hi3521a.dtsi create mode 100644 drivers/clk/hisilicon/crg-hi3521a.c create mode 100644 include/dt-bindings/clock/hi3521a-clock.h -- 2.14.1
[RFC RESEND 2/3] arm: hisi: enable Hi3521A SoC
Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes hardware mutlimedia codec cores, commonly used in consumer cctv/dvr security systems and ipcameras. The arm core is a Cortex A7. Signed-off-by: Marty E. Plummer --- arch/arm/mach-hisi/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 65a048fa08ec..26755414f862 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -12,6 +12,12 @@ if ARCH_HISI menu "Hisilicon platform type" +config ARCH_HI3521A + bool "Hisilicon Hi3521A/Hi3520DCV300 family" + depends on ARCH_MULTI_V7 + help + Support for Hisilicon Hi3521A/Hi3520DCV300 SoC family + config ARCH_HI3xxx bool "Hisilicon Hi36xx family" depends on ARCH_MULTI_V7 -- 2.14.1
[RFC RESEND 1/3] clk: hisilicon: add CRG driver Hi3521A SoC
Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
generates clock and reset signals used by other module blocks on SoC.
Signed-off-by: Marty E. Plummer
---
drivers/clk/hisilicon/Kconfig | 7 +
drivers/clk/hisilicon/Makefile| 1 +
drivers/clk/hisilicon/crg-hi3521a.c | 207 ++
include/dt-bindings/clock/hi3521a-clock.h | 34 +
4 files changed, 249 insertions(+)
create mode 100644 drivers/clk/hisilicon/crg-hi3521a.c
create mode 100644 include/dt-bindings/clock/hi3521a-clock.h
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 7098bfd32b1b..d93e3180a04f 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -14,6 +14,13 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3521A
+ bool "Hi3521A/Hi3520DV300 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3521a/hi3520dv300
+
config COMMON_CLK_HI3660
bool "Hi3660 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 1e4c3ddbad84..46f8d619c923 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_HIP04)+= clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519)+= clk-hi3519.o
+obj-$(CONFIG_COMMON_CLK_HI3521A)+= crg-hi3521a.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220)+= clk-hi6220.o
diff --git a/drivers/clk/hisilicon/crg-hi3521a.c
b/drivers/clk/hisilicon/crg-hi3521a.c
new file mode 100644
index ..8c03ce2694c1
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3521a.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2017 Marty E. Plummer
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include
+#include
+#include
+#include
+#include "clk.h"
+#include "reset.h"
+
+#define HI3521A_INNER_CLK_OFFSET 64
+#define HI3521A_FIXED_2M 65
+#define HI3521A_FIXED_24M 66
+#define HI3521A_FIXED_50M 67
+#define HI3521A_FIXED_83M 68
+#define HI3521A_FIXED_100M 69
+#define HI3521A_FIXED_150M 70
+#define HI3521A_FMC_MUX71
+#define HI3521A_UART_MUX 72
+
+#define HI3521A_NR_CLKS128
+
+struct hi3521a_crg_data {
+ struct hisi_clock_data *clk_data;
+ struct hisi_reset_controller *rstc;
+};
+
+static const struct hisi_fixed_rate_clock hi3521a_fixed_rate_clks[] = {
+ { HI3521A_FIXED_2M, "2m", NULL, 0, 200, },
+ { HI3521A_FIXED_24M, "24m", NULL, 0, 2400, },
+ { HI3521A_FIXED_50M, "50m", NULL, 0, 5000, },
+ { HI3521A_FIXED_83M, "83m", NULL, 0, 8300, },
+ { HI3521A_FIXED_100M, "100m", NULL, 0, 1, },
+ { HI3521A_FIXED_150M, "150m", NULL, 0, 15000, },
+};
+
+static const char *const uart_mux_p[] = { "50m", "2m", "24m", };
+static const char *const fmc_mux_p[] = { "24m", "83m", "150m", };
+
+static u32 uart_mux_table[] = {0, 1, 2};
+static u32 fmc_mux_table[] = {0, 1, 2};
+
+static const struct hisi_mux_clock hi3521a_mux_clks[] = {
+ { HI3521A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
+ CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table, },
+ { HI3521A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3521a_gate_clks[] = {
+ { HI3521A_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
+ 0x74, 1, 0, },
+ { HI3521A_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 15, 0, },
+ { HI3521A_UART1_CLK, "clk_uart1", "uart_mux", CL
Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts
On Wed, Sep 20, 2017 at 08:53:03PM +, Rob Herring wrote:
> On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:
> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> > marketed under the name Samsung SDR-B74301N
> >
> > Signed-off-by: Marty E. Plummer
> > ---
> > arch/arm/boot/dts/Makefile | 2 +
> > arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++
> > arch/arm/boot/dts/hi3521a.dtsi | 310
> >
> > 3 files changed, 364 insertions(+)
> > create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> > create mode 100644 arch/arm/boot/dts/hi3521a.dtsi
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index faf46abaa4a2..e7b9b5dde20f 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> > gemini-sq201.dtb \
> > gemini-wbd111.dtb \
> > gemini-wbd222.dtb
> > +dtb-$(CONFIG_ARCH_HI3521A) += \
> > + hi3521a-rs-dm290e.dtb
> > dtb-$(CONFIG_ARCH_HI3xxx) += \
> > hi3620-hi4511.dtb
> > dtb-$(CONFIG_ARCH_HIGHBANK) += \
> > diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> > b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> > new file mode 100644
> > index ..b32c8392c93f
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> > @@ -0,0 +1,52 @@
> > +/*
> > + * Copyright (C) 2017 Marty Plummer
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 3 of the License, or
> > + * (at your option) any later version.
>
> Should be version 2 or later? Doesn't really matter to me from a DT
> perspective, but it is in the kernel tree.
>
> You can use SPDX tags if you want.
>
Oh, that's a good idea. I hadn't seen any SPDX tags in the tree that I
noticed before. I ended up just using the :Gpl command from neovim.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +/dts-v1/;
> > +#include "hi3521a.dtsi"
> > +
> > +/ {
> > + model = "RaySharp RS-DM-290E DVR Board";
> > + compatible = "hisilicon,hi3521a";
>
> Needs a board compatible too.
>
Something like `compatible = "hisilicon,hi3521a", "raysharp,rs-dm-290e";` ?
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + serial1 = &uart1;
> > + serial2 = &uart2;
> > + };
> > +
> > + memory {
>
> Needs a unit-address.
>
Could you explain what you mean here? As in, memory@someaddr? What would
I use here?
> > + device_type = "memory";
> > + reg = <0x8000 0xf0>;
> > + };
> > +};
> > +
> > +&hi_sfc {
> > + status = "okay";
> > + spi-nor@0 {
> > + compatible = "jedec,spi-nor";
>
> I don't remember offhand, but I think this should have a device specific
> compatible too.
>
Instead of "jedec,spi-nor" ? Specific to the SPI chip?
> > + reg = <0>;
> > + spi-max-frequency = <10400>;
> > + };
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > +
> > +&dual_timer0 {
> > + status = "okay";
> > +};
> > diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi
> > new file mode 100644
> > index ..2af746fdec46
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/hi3521a.dtsi
> > @@ -0,0 +1,310 @@
> > +/*
> > + * Copyright (C) 2017 Marty Plummer
> > + *
> > + * This program is free software: you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation, either version 3 of the License, or
> > + * (at your option) any later version.
> >
Re: [RFC RESEND 3/3] arm: dts: add Hi3521A dts
On Thu, Sep 21, 2017 at 01:08:39AM +, Rob Herring wrote:
> On Wed, Sep 20, 2017 at 6:04 PM, Marty E. Plummer
> wrote:
> > On Wed, Sep 20, 2017 at 08:53:03PM +, Rob Herring wrote:
> >> On Sun, Sep 17, 2017 at 03:23:27AM -0500, Marty E. Plummer wrote:
> >> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> >> > marketed under the name Samsung SDR-B74301N
> >> >
> >> > Signed-off-by: Marty E. Plummer
> >> > ---
> >> > arch/arm/boot/dts/Makefile | 2 +
> >> > arch/arm/boot/dts/hi3521a-rs-dm290e.dts | 52 ++
> >> > arch/arm/boot/dts/hi3521a.dtsi | 310
> >> >
> >> > 3 files changed, 364 insertions(+)
> >> > create mode 100644 arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> >> > create mode 100644 arch/arm/boot/dts/hi3521a.dtsi
> >> >
> >> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> >> > index faf46abaa4a2..e7b9b5dde20f 100644
> >> > --- a/arch/arm/boot/dts/Makefile
> >> > +++ b/arch/arm/boot/dts/Makefile
> >> > @@ -189,6 +189,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> >> > gemini-sq201.dtb \
> >> > gemini-wbd111.dtb \
> >> > gemini-wbd222.dtb
> >> > +dtb-$(CONFIG_ARCH_HI3521A) += \
> >> > + hi3521a-rs-dm290e.dtb
> >> > dtb-$(CONFIG_ARCH_HI3xxx) += \
> >> > hi3620-hi4511.dtb
> >> > dtb-$(CONFIG_ARCH_HIGHBANK) += \
> >> > diff --git a/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> >> > b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> >> > new file mode 100644
> >> > index ..b32c8392c93f
> >> > --- /dev/null
> >> > +++ b/arch/arm/boot/dts/hi3521a-rs-dm290e.dts
> >> > @@ -0,0 +1,52 @@
> >> > +/*
> >> > + * Copyright (C) 2017 Marty Plummer
> >> > + *
> >> > + * This program is free software: you can redistribute it and/or modify
> >> > + * it under the terms of the GNU General Public License as published by
> >> > + * the Free Software Foundation, either version 3 of the License, or
> >> > + * (at your option) any later version.
> >>
> >> Should be version 2 or later? Doesn't really matter to me from a DT
> >> perspective, but it is in the kernel tree.
> >>
> >> You can use SPDX tags if you want.
> >>
> > Oh, that's a good idea. I hadn't seen any SPDX tags in the tree that I
> > noticed before. I ended up just using the :Gpl command from neovim.
> >> > + *
> >> > + * This program is distributed in the hope that it will be useful,
> >> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> > + * GNU General Public License for more details.
> >> > + *
> >> > + * You should have received a copy of the GNU General Public License
> >> > + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> >> > + */
> >> > +
> >> > +/dts-v1/;
> >> > +#include "hi3521a.dtsi"
> >> > +
> >> > +/ {
> >> > + model = "RaySharp RS-DM-290E DVR Board";
> >> > + compatible = "hisilicon,hi3521a";
> >>
> >> Needs a board compatible too.
> >>
> > Something like `compatible = "hisilicon,hi3521a", "raysharp,rs-dm-290e";` ?
>
> Yes, but flip the order. Most specific compatible first.
>
> >> > +
> >> > + aliases {
> >> > + serial0 = &uart0;
> >> > + serial1 = &uart1;
> >> > + serial2 = &uart2;
> >> > + };
> >> > +
> >> > + memory {
> >>
> >> Needs a unit-address.
> >>
> > Could you explain what you mean here? As in, memory@someaddr? What would
> > I use here?
>
> "memory@8000". Building with W=2 will tell you.
>
Ah, nice trick. Suppose that makes sense, as every other thing was the
same on that sort of thing. Not sure if I've ever seen memory@addr
before.
> >> > + device_type = "memory";
> >> > + reg = <0x8000 0xf0>;
> >> > + };
> >> > +};
> >> > +
> >> > +&hi_sfc {
> >> > + status = "ok
hi3521a syscon-reboot issue, reboot fails oddly.
Greetings,
Having a slight issue with getting reboot to work on the board I'm tinkering
with; according to the documentation writing any value to 0x12050004 should
reset the system, as such I have the following snippet in my dts to make it
work:
sysctrl: system-controller@1205 {
compatible = "hisilicon,hi3521a-sysctrl", "syscon";
reg = <0x1205 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
The above is primarily based on the hi3519.dtsi setup, whose docs indicate
it resets in the same manner.
However, issuing a `reboot' ends up putting the cpu into a wierd state, with
the serial port getting spammed with '0x0a2020202020...0a20202020...' in what
appears to be an infinite amount of time (let it sit in this state overnight,
remaining in this state.
It doesn't make much sense to me, as I can't find anything in the bsp regarding
reset excluding a small bit in linux-3.10.y/arch/arm/mach-hi3521a/core.c:
void hi3521a_restart(char mode, const char *cmd)
{
writel(~0, __io_address(REG_BASE_SCTL + REG_SC_SYSRES));
}
which effectively does the same thing as syscon-reboot.
This happens whether I reboot via command or by killing the process feeding the
watchdog (procd on lede's initramfs).
Was hoping you guys could perhaps provide some guidance regarding this matter.
Regards,
Marty
--
2.15.0
