Re: [PATCH 2/2] serial: of_serial: Handle fifosize property

[Ley Foon Tan]

On Thu, 2013-03-21 at 12:48 +0200, Heikki Krogerus wrote:
> fifosize property is already used with a number of serial
> devices. This should reduce the need for extra types in
> 8250.c just in case the fifosize differs from the standard.
> 
> Signed-off-by: Heikki Krogerus 
> ---
>  Documentation/devicetree/bindings/tty/serial/of-serial.txt |1 +
>  drivers/tty/serial/of_serial.c |4 
>  2 files changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt 
> b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> index 8f01cb1..55fe4e7 100644
> --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> @@ -33,6 +33,7 @@ Optional properties:
>RTAS and should not be registered.
>  - no-loopback-test: set to indicate that the port does not implements 
> loopback
>test mode
> +- fifosize: the fifo size of the UART.
>  
>  Example:
>  
> diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
> index b025d54..4f89761 100644
> --- a/drivers/tty/serial/of_serial.c
> +++ b/drivers/tty/serial/of_serial.c
> @@ -97,6 +97,10 @@ static int of_platform_serial_setup(struct platform_device 
> *ofdev,
>   if (of_property_read_u32(np, "reg-shift", &prop) == 0)
>   port->regshift = prop;
>  
> + /* Check for fifo size */
> + if (of_property_read_u32(np, "fifosize", &prop) == 0)
> + port->fifosize = prop;
> +
Suggest to use "fifo-size" for the device tree property, to align with
other DT properties.

>   port->irq = irq_of_parse_and_map(np, 0);
>   port->iotype = UPIO_MEM;
>   if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {

I think you need to remove the UPF_FIXED_TYPE from port-flags as well to
use the fifo size from device tree. Otherwise, it will get from the
static array in 8250.c.

LFTan


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH] of/fdt: Add FDT address translation

[Ley Foon Tan]

Any comment or feedback for this patch?


On Fri, 2013-05-24 at 17:36 +0800, Ley Foon Tan wrote:
> This patch adds address translation to fdt. It is needed when the early
> console is connected to a simple-bus (bridge) that has address translation
> enabled.
> 
> Walter Goossens have submitted first version of patch previously. This
> patch resolved the feedback from first submission and some enhancements
> on translation functions.
> 
> Reviewed-by: Walter Goossens 
> Signed-off-by: Ley Foon Tan 
> ---
>  drivers/of/fdt.c   |  188 
> 
>  include/linux/of_fdt.h |2 +
>  2 files changed, 190 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 808be06..74cc1bc 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -695,6 +695,194 @@ int __init early_init_dt_scan_chosen(unsigned long 
> node, const char *uname,
>   /* break now */
>   return 1;
>  }
> +/**
> + * flat_dt_translate_address - Translate an address using the ranges property
> + *
> + * This function converts address from "node address-space" to "parent 
> address-
> + * space"
> + */
> +static int __init flat_dt_translate_address(unsigned long node,
> + unsigned long parent, u64 *address)
> +{
> + unsigned long size = 0;
> + __be32 *prop;
> + __be32 *ranges;
> + int size_cells = 0;
> + int addr_cells = 0;
> + int paddr_cells = OF_ROOT_NODE_ADDR_CELLS_DEFAULT;
> +
> + ranges = of_get_flat_dt_prop(node, "ranges", &size);
> +
> + if (!ranges) {
> + pr_warn("Address cannot be translated\n");
> + return -EINVAL;
> + }
> +
> + if (!size) {
> + pr_debug("No translation possible/necessary\n");
> + return 0;
> + }
> +
> + prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
> + if (!prop)
> + return -EINVAL;
> + size_cells = be32_to_cpup(prop);
> +
> + prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
> + if (!prop)
> + return -EINVAL;
> + addr_cells = be32_to_cpup(prop);
> +
> + if (parent) {
> + prop = of_get_flat_dt_prop(parent, "#address-cells", NULL);
> + if (prop)
> + paddr_cells = be32_to_cpup(prop);
> + }
> + if ((addr_cells <= 0) || (size_cells <= 0) ||
> + (addr_cells > 2) || (size_cells > 2) || (paddr_cells > 2)) {
> + pr_warn("Translation not possible in fdt. Invalid address.\n");
> + *address = 0;
> + return -1;
> + }
> +
> + while (size > 0) {
> + u64 from, to, tsize;
> + from = be32_to_cpup(ranges++);
> + size -= 4;
> + if (addr_cells == 2) {
> + from += (((u64)be32_to_cpup(ranges++)) << 32);
> + size -= 4;
> + }
> + to = be32_to_cpup(ranges++);
> + size -= 4;
> + if (paddr_cells == 2) {
> + to += (((u64)be32_to_cpup(ranges++)) << 32);
> + size -= 4;
> + }
> + tsize = be32_to_cpup(ranges++);
> + size -= 4;
> + if (size_cells == 2) {
> + tsize += (((u64)be32_to_cpup(ranges++)) << 32);
> + size -= 4;
> + }
> + pr_debug("  From %llX To %llX Size %llX\n", from, to, tsize);
> + if ((*address >= from) && (*address < (from + tsize)))
> + *address += (to - from);
> + }
> + return 1;
> +}
> +
> +static int __init of_scan_flat_dt_ranges(unsigned long *pnode,
> + unsigned long parent, unsigned long target,
> + u64 *address, int ignore)
> +{
> + int rc = 0;
> + int depth = -1;
> + const char *pathp;
> + unsigned long p = *pnode;
> + do {
> + u32 tag = be32_to_cpup((__be32 *)p);
> +
> + p += 4;
> + if (tag == OF_DT_END_NODE) {
> + if (depth--)
> + break;
> + else
> + continue;
> + }
> + if (tag == OF_DT_NOP)
> + continue;
> + if (tag == OF_DT_END)
> + break;
> + if (tag == OF_DT_PROP) {
> + u32 sz = be32_to

Re: [PATCH 2/2] serial: of_serial: Handle fifosize property

[Ley Foon Tan]

On Thu, 2013-03-21 at 15:24 +0200, Heikki Krogerus wrote:
> Hi,
> 
> On Thu, Mar 21, 2013 at 07:41:39PM +0800, Ley Foon Tan wrote:
> > On Thu, 2013-03-21 at 12:48 +0200, Heikki Krogerus wrote:
> > > + /* Check for fifo size */
> > > + if (of_property_read_u32(np, "fifosize", &prop) == 0)
> > > + port->fifosize = prop;
> > > +
> > Suggest to use "fifo-size" for the device tree property, to align with
> > other DT properties.
> 
> I was going to, but then I noticed that in some .dtsi files "fifosize"
> is used with uarts. Should I still change it?
I just make the grep for "fifosize" in arch/. It is used by other serial
drivers (not of_serial.c). So, you are safe to change it to "fifo-size".

> 
> > >   port->irq = irq_of_parse_and_map(np, 0);
> > >   port->iotype = UPIO_MEM;
> > >   if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
> > 
> > I think you need to remove the UPF_FIXED_TYPE from port-flags as well to
> > use the fifo size from device tree. Otherwise, it will get from the
> > static array in 8250.c.
> 
> No, it's the other way around. It is picked from the array
> conditionally, only in case it was not already set. However, if
> UPF_FIXED_TYPE is removed then autoconfig() will override it.
> 
> Thanks,
> 
Okay, I got what you means now. I think someone updated the 8250.c
recently, previously it is always take from static array.
Thanks.



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCHv2 2/2] serial: of_serial: Handle fifo-size property

[Ley Foon Tan]

On Fri, 2013-03-22 at 10:05 +0200, Heikki Krogerus wrote:
> This will reduce the need for extra types in 8250.c just
> in case the fifo size differs from the standard.
Besides the fifo size, we need to have hardware flow control setting
from device tree as well.
Thanks.
> 
> Signed-off-by: Heikki Krogerus 
> ---
>  Documentation/devicetree/bindings/tty/serial/of-serial.txt |1 +
>  drivers/tty/serial/of_serial.c |4 
>  2 files changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt 
> b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> index 8f01cb1..c13f0ce 100644
> --- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> +++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
> @@ -33,6 +33,7 @@ Optional properties:
>RTAS and should not be registered.
>  - no-loopback-test: set to indicate that the port does not implements 
> loopback
>test mode
> +- fifo-size: the fifo size of the UART.
>  



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 1/1] drivers/misc: Add Altera System ID driver

[Ley Foon Tan]

This patch is to add Altera System ID driver.
User can obtain the system ID and timestamp of the system by
reading the sysfs entry.

Usage:
cat /sys/bus/platform/devices/[addr].sysid/sysid/id
cat /sys/bus/platform/devices/[addr].sysid/sysid/timestamp

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/misc/altera_sysid.txt  |   18 +++
 drivers/misc/Kconfig   |6 +
 drivers/misc/Makefile  |3 +-
 drivers/misc/altera_sysid.c|  142 
 4 files changed, 168 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/misc/altera_sysid.txt
 create mode 100644 drivers/misc/altera_sysid.c

diff --git a/Documentation/devicetree/bindings/misc/altera_sysid.txt 
b/Documentation/devicetree/bindings/misc/altera_sysid.txt
new file mode 100644
index 000..463dc15
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/altera_sysid.txt
@@ -0,0 +1,18 @@
+Altera Sysid IP core driver
+
+Required properties:
+- compatible: altr,sysid-1.0
+
+Optional properties:
+- id:  A unique 32-bit value that is based on the contents of the system.
+- timestamp: A unique 32-bit value that is based on the system generation time.
+
+Example:
+
+sysid_qsys: sysid@0x1 {
+   compatible = "altr,sysid-1.0";
+   reg = < 0x1 0x0008 >;
+   id = < 1 >;
+   timestamp = < 1359538782 >;
+};
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index e83fdfe..0e783af 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -510,6 +510,12 @@ config LATTICE_ECP3_CONFIG
 
  If unsure, say N.
 
+config ALTERA_SYSID
+   tristate "Altera System ID"
+   help
+   This enables Altera System ID soft core driver.
+
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 35a1463..dc7142d 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -47,7 +47,8 @@ obj-y += ti-st/
 obj-y  += lis3lv02d/
 obj-y  += carma/
 obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
-obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/
+obj-$(CONFIG_ALTERA_STAPL) += altera-stapl/
+obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_INTEL_MEI)+= mei/
 obj-$(CONFIG_MAX8997_MUIC) += max8997-muic.o
 obj-$(CONFIG_VMWARE_VMCI)  += vmw_vmci/
diff --git a/drivers/misc/altera_sysid.c b/drivers/misc/altera_sysid.c
new file mode 100644
index 000..7472a4b
--- /dev/null
+++ b/drivers/misc/altera_sysid.c
@@ -0,0 +1,142 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Credit:
+ * Walter Goossens
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME   "altera_sysid"
+
+struct altera_sysid {
+   void __iomem*regs;
+};
+
+/* System ID Registers*/
+#define SYSID_REG_ID   (0x0)
+#define SYSID_REG_TIMESTAMP(0x4)
+
+static ssize_t altera_sysid_show_id(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   struct altera_sysid *sysid = dev_get_drvdata(dev);
+
+   return sprintf(buf, "%u\n", readl(sysid->regs + SYSID_REG_ID));
+}
+
+static ssize_t altera_sysid_show_timestamp(struct device *dev,
+   struct device_attribute *attr, char *buf)
+{
+   unsigned int reg;
+   struct tm timestamp;
+   struct altera_sysid *sysid = dev_get_drvdata(dev);
+
+   reg = readl(sysid->regs + SYSID_REG_TIMESTAMP);
+
+   time_to_tm(reg, 0, ×tamp);
+
+   return sprintf(buf, "%u (%u-%u-%u %u:%u:%u UTC)\n", reg,
+   (unsigned int)(timestamp.tm_year + 1900),
+   timestamp.tm_mon + 1, timestamp.tm_mday, timestamp.tm_hour,
+   timestamp.tm_min, timestamp.tm_sec);
+}
+
+static DEVICE_ATTR(id, S_IRUGO, altera_sysid_show_id, NULL);
+static DEVICE_ATTR(timestamp, S_IRUGO, altera_sysid_show_timestamp, NULL);
+
+static struct attribute *altera_sysid_attrs[] = {
+   &dev_attr_id.attr,
+   &dev_attr_timestamp.attr,
+   NULL,
+};
+
+struct attri

Re: [PATCH 1/1] drivers/misc: Add Altera System ID driver

[Ley Foon Tan]

On Mon, 2013-03-04 at 11:44 +0800, Greg Kroah-Hartman wrote:
> On Mon, Mar 04, 2013 at 03:32:19AM +, Arnd Bergmann wrote:
> > On Monday 04 March 2013, Ley Foon Tan wrote:
> > > This patch is to add Altera System ID driver.
> > > User can obtain the system ID and timestamp of the system by
> > > reading the sysfs entry.
> > > 
> > > Usage:
> > > cat /sys/bus/platform/devices/[addr].sysid/sysid/id
> > > cat /sys/bus/platform/devices/[addr].sysid/sysid/timestamp
> > > 
> > > Signed-off-by: Ley Foon Tan 
> > 
> > All sysfs files need documentation in Documentation/ABI/.
Okay, I will add document in this directory.

> > 
> > This driver looks like it should instead be using the infrastructure we
> > have for identifying an SoC in drivers/base/soc.c, which is currently
> > only used by the ARM u8500 platform but was introduced as a generic
> > interface for this a while ago.
> 
> I agree, this shouldn't be a one-off sysfs file.
> 
> greg k-h
> 
This IP core is not in the SoC. This core is in the FPGA and can be
accessed by the Nios II processor or accessed by SOCFPGA processor (ARM
based) via its interface to FPGA. Due to this, I think it shouldn't use
infrastructure in drivers/base/soc.c.
What do you think?

Thanks for the comments.

lftan

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 1/1] drivers/misc: Add Altera System ID driver

[Ley Foon Tan]

On Mon, 2013-03-04 at 12:55 +, Arnd Bergmann wrote:
> On Monday 04 March 2013, Ley Foon Tan wrote:
> > This IP core is not in the SoC. This core is in the FPGA and can be
> > accessed by the Nios II processor or accessed by SOCFPGA processor (ARM
> > based) via its interface to FPGA. Due to this, I think it shouldn't use
> > infrastructure in drivers/base/soc.c.
> > What do you think?
> 
> The sysid component gives a version for the entire FPGA part and all
> components inside it, right?
> 
> I think you should use the drivers/base/soc.c interface to describe the
> SOCFPGA SoC components as well as the actual FPGA. You basically
> end up having one device node that acts as the parent for the SoC
> components, and a way to retrieve version information about it.
> 
> Depending on how it fits the actual hardware layout more closely,
> you could have one node as the parent for all devices, or the
> FPGA SoC node as a child of the main one, or two SoC nodes side by
> side from the top-level.
> 
>   Arnd
> 
The sysid give the unique system ID and system generation timestamp of
the system.

CASE 1:
SOCFPGA SoC + Sysid component in FPGA

CASE 2
Nios II soft core CPU + Sysid  (All in FPGA and no SoC is involved)

>From example use cases above, Case 2 doesn't involve SoC component. 
To support both cases, do you think drivers/base/soc.c is still
suitable?

Thanks.

LFTan




--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Linux kernel support -O0 optimization flag?

[Ley Foon Tan]

Change KBUILD_CFLAGS to -O0 in Makefile and got the compilation error as
below.
Is the Linux kernel support -O0 optimization flag?
Note, I have tried 2 architecture compilers and got the same error.



In function 'zap_pmd_range',

inlined from 'zap_pud_range' at mm/memory.c:1288:8,

inlined from 'unmap_page_range' at mm/memory.c:1313:8:

mm/memory.c:1243:23: error: call to '__build_bug_failed' declared with
attribute error: BUILD_BUG failed

make[1]: *** [mm/memory.o] Error 1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: Linux kernel support -O0 optimization flag?

[Ley Foon Tan]

On Mon, 2013-04-15 at 13:16 +0200, richard -rw- weinberger wrote:

> No. If I'm not mistaken we need this to make sure that the compiler
> inlines some functions.
> 
> In your case the compiler failed to compute the BUILD_BUG() macro correctly.
> It depends also on optimization.
> 
Thank you.
So, the supported optimization flags are -O1, -O2, -O3 and -Os?

Regards
LFTAN

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH] of/fdt: Add FDT address translation

[Ley Foon Tan]

This patch adds address translation to fdt. It is needed when the early
console is connected to a simple-bus (bridge) that has address translation
enabled.

Walter Goossens have submitted first version of patch previously. This
patch resolved the feedback from first submission and some enhancements
on translation functions.

Reviewed-by: Walter Goossens 
Signed-off-by: Ley Foon Tan 
---
 drivers/of/fdt.c   |  188 
 include/linux/of_fdt.h |2 +
 2 files changed, 190 insertions(+), 0 deletions(-)

diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 808be06..74cc1bc 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -695,6 +695,194 @@ int __init early_init_dt_scan_chosen(unsigned long node, 
const char *uname,
/* break now */
return 1;
 }
+/**
+ * flat_dt_translate_address - Translate an address using the ranges property
+ *
+ * This function converts address from "node address-space" to "parent address-
+ * space"
+ */
+static int __init flat_dt_translate_address(unsigned long node,
+   unsigned long parent, u64 *address)
+{
+   unsigned long size = 0;
+   __be32 *prop;
+   __be32 *ranges;
+   int size_cells = 0;
+   int addr_cells = 0;
+   int paddr_cells = OF_ROOT_NODE_ADDR_CELLS_DEFAULT;
+
+   ranges = of_get_flat_dt_prop(node, "ranges", &size);
+
+   if (!ranges) {
+   pr_warn("Address cannot be translated\n");
+   return -EINVAL;
+   }
+
+   if (!size) {
+   pr_debug("No translation possible/necessary\n");
+   return 0;
+   }
+
+   prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
+   if (!prop)
+   return -EINVAL;
+   size_cells = be32_to_cpup(prop);
+
+   prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
+   if (!prop)
+   return -EINVAL;
+   addr_cells = be32_to_cpup(prop);
+
+   if (parent) {
+   prop = of_get_flat_dt_prop(parent, "#address-cells", NULL);
+   if (prop)
+   paddr_cells = be32_to_cpup(prop);
+   }
+   if ((addr_cells <= 0) || (size_cells <= 0) ||
+   (addr_cells > 2) || (size_cells > 2) || (paddr_cells > 2)) {
+   pr_warn("Translation not possible in fdt. Invalid address.\n");
+   *address = 0;
+   return -1;
+   }
+
+   while (size > 0) {
+   u64 from, to, tsize;
+   from = be32_to_cpup(ranges++);
+   size -= 4;
+   if (addr_cells == 2) {
+   from += (((u64)be32_to_cpup(ranges++)) << 32);
+   size -= 4;
+   }
+   to = be32_to_cpup(ranges++);
+   size -= 4;
+   if (paddr_cells == 2) {
+   to += (((u64)be32_to_cpup(ranges++)) << 32);
+   size -= 4;
+   }
+   tsize = be32_to_cpup(ranges++);
+   size -= 4;
+   if (size_cells == 2) {
+   tsize += (((u64)be32_to_cpup(ranges++)) << 32);
+   size -= 4;
+   }
+   pr_debug("  From %llX To %llX Size %llX\n", from, to, tsize);
+   if ((*address >= from) && (*address < (from + tsize)))
+   *address += (to - from);
+   }
+   return 1;
+}
+
+static int __init of_scan_flat_dt_ranges(unsigned long *pnode,
+   unsigned long parent, unsigned long target,
+   u64 *address, int ignore)
+{
+   int rc = 0;
+   int depth = -1;
+   const char *pathp;
+   unsigned long p = *pnode;
+   do {
+   u32 tag = be32_to_cpup((__be32 *)p);
+
+   p += 4;
+   if (tag == OF_DT_END_NODE) {
+   if (depth--)
+   break;
+   else
+   continue;
+   }
+   if (tag == OF_DT_NOP)
+   continue;
+   if (tag == OF_DT_END)
+   break;
+   if (tag == OF_DT_PROP) {
+   u32 sz = be32_to_cpup((__be32 *)p);
+   p += 8;
+   if (be32_to_cpu(initial_boot_params->version) < 0x10)
+   p = ALIGN(p, sz >= 8 ? 8 : 4);
+   p += sz;
+   p = ALIGN(p, 4);
+   continue;
+   }
+   if (tag != OF_DT_BEGIN_NODE) {
+   pr_err("Invalid tag %x in flat device tree!\n", tag);
+   return -EINVAL;
+   }
+   pathp = (char *)p;
+   

Generic syscall ABI support

[Ley Foon Tan]

Need advise regarding the generic syscall ABI support.

We are planning to upstream our Nios II kernel (arch/nios2) to mainline.
But it doesn't support generic syscall ABI yet (It requires an updated
Glibc port as well). 

The question is, is it a requirement for new arch to support generic
syscall ABI when upstreaming? Can we upstream a non-generic syscall ABI
first and migrate to generic syscall ABI in future?
Thanks.

Regards
LFTAN



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: Generic syscall ABI support

[Ley Foon Tan]

On Thu, 2013-03-28 at 07:44 +, Arnd Bergmann wrote:

> Yes, absolutely. What a couple of the previous architectures have done is
> to keep out of tree patches for their old ABI for a while, and to submit
> only code that follows the generic ABI upstream. Usually it doesn't take
> long for users to migrate to a new user space after that, but it gives
> people a migration strategy. Normally you have other patches that are
> required on top of the stuff that is already upstream while you are
> getting everything merged, so this is not much different to a device
> driver that needs to get rewritten to adapt to a new kernel subsystem.
> 
>   Arnd
> 
Thanks for the reply. 
We will working on generic ABI for kernel and Glibc. This might take
some times.

Regards
LFTAN

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: Generic syscall ABI support

[Ley Foon Tan]

On Thu, 2013-03-28 at 10:40 +, Arnd Bergmann wrote:
> On Thursday 28 March 2013, Ley Foon Tan wrote:
> > We will working on generic ABI for kernel and Glibc. This might take
> > some times.
> 
> Ok. Don't let that hold you up from submitting the kernel patches
> for review though.
> 
>   Arnd
> 
Do you mean we can submit the patches for review before we got the
generic ABI support?

Regards
LFTAN

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: Generic syscall ABI support

[Ley Foon Tan]

On Thu, 2013-03-28 at 21:53 -0700, H. Peter Anvin wrote:
> On 03/28/2013 09:41 PM, Rob Landley wrote:
> > 
> > You don't need a new glibc port, you need a new klibc or musl port.
> > 
> >   http://www.openwall.com/lists/musl/2012/07/08/1
> > 
> > Way less work than getting glibc working for your basic smoketest...
> > 
> 
> Good point.  Average time to port klibc to a new architecture is about
> four hours as long as the person porting knows the calling conventions
> and assembly language involved.
> 
>   -hpa
> 
> 
Thanks for the suggestion.
Too bad we don't have in-house expert in klibc and musl port. 

Hi HPA,
I knew you are the developer of klibc. Do you have any documentation to
port a new architecture and also how to replace glibc with klibc in
build?

By the way, klibc or musl is easier to port?
Thanks.

Regards
lftan

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH] tty/serial: Add support for Altera serial port

[Ley Foon Tan]

Add support for Altera 8250/16550 compatible serial port.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/tty/serial/of-serial.txt   |3 ++
 drivers/tty/serial/8250/8250.c |   23 +++-
 drivers/tty/serial/of_serial.c |6 +
 include/uapi/linux/serial_core.h   |5 +++-
 4 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt 
b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
index 1e1145c..8f01cb1 100644
--- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
@@ -11,6 +11,9 @@ Required properties:
- "nvidia,tegra20-uart"
- "nxp,lpc3220-uart"
- "ibm,qpace-nwp-serial"
+   - "altr,16550-FIFO32"
+   - "altr,16550-FIFO64"
+   - "altr,16550-FIFO128"
- "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
index 0efc815..661096d 100644
--- a/drivers/tty/serial/8250/8250.c
+++ b/drivers/tty/serial/8250/8250.c
@@ -301,7 +301,28 @@ static const struct serial8250_config uart_config[] = {
},
[PORT_8250_CIR] = {
.name   = "CIR port"
-   }
+   },
+   [PORT_ALTR_16550_F32] = {
+   .name   = "Altera 16550 FIFO32",
+   .fifo_size  = 32,
+   .tx_loadsz  = 32,
+   .fcr= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+   .flags  = UART_CAP_FIFO | UART_CAP_AFE,
+   },
+   [PORT_ALTR_16550_F64] = {
+   .name   = "Altera 16550 FIFO64",
+   .fifo_size  = 64,
+   .tx_loadsz  = 64,
+   .fcr= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+   .flags  = UART_CAP_FIFO | UART_CAP_AFE,
+   },
+   [PORT_ALTR_16550_F128] = {
+   .name   = "Altera 16550 FIFO128",
+   .fifo_size  = 128,
+   .tx_loadsz  = 128,
+   .fcr= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+   .flags  = UART_CAP_FIFO | UART_CAP_AFE,
+   },
 };
 
 /* Uart divisor latch read */
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index d587460..b025d54 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -241,6 +241,12 @@ static struct of_device_id of_platform_serial_table[] = {
{ .compatible = "ns16850",  .data = (void *)PORT_16850, },
{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
+   { .compatible = "altr,16550-FIFO32",
+   .data = (void *)PORT_ALTR_16550_F32, },
+   { .compatible = "altr,16550-FIFO64",
+   .data = (void *)PORT_ALTR_16550_F64, },
+   { .compatible = "altr,16550-FIFO128",
+   .data = (void *)PORT_ALTR_16550_F128, },
 #ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
{ .compatible = "ibm,qpace-nwp-serial",
.data = (void *)PORT_NWPSERIAL, },
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index b6a23a4..74c2bf7 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -51,7 +51,10 @@
 #define PORT_8250_CIR  23  /* CIR infrared port, has its own driver */
 #define PORT_XR17V35X  24  /* Exar XR17V35x UARTs */
 #define PORT_BRCM_TRUMANAGE25
-#define PORT_MAX_8250  25  /* max port ID */
+#define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
+#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
+#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
+#define PORT_MAX_8250  28  /* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
-- 
1.7.7.4


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 1/1] drivers/misc: Add Altera System ID driver

[Ley Foon Tan]

On Tue, 2013-03-05 at 21:59 +, Arnd Bergmann wrote:
> On Tuesday 05 March 2013, Ley Foon Tan wrote:
> > The sysid give the unique system ID and system generation timestamp of
> > the system.
> > 
> > CASE 1:
> > SOCFPGA SoC + Sysid component in FPGA
> > 
> > CASE 2
> > Nios II soft core CPU + Sysid  (All in FPGA and no SoC is involved)
> > 
> > From example use cases above, Case 2 doesn't involve SoC component. 
> > To support both cases, do you think drivers/base/soc.c is still
> > suitable?
> 
> Yes, I think so. I would consider the second case still a SoC, because
> you have a single chip that contains the CPU and peripherals. From
> the OS point of view, it does not matter that they are in an FPGA.
> 
>   Arnd

Thanks for your input. I will go with your suggestion.

LFTan


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 0/2] PCI: altera: fix link retrain

[Ley Foon Tan]

On Tue, Jul 12, 2016 at 6:19 PM, Ley Foon Tan  wrote:
>
> On Tue, Jun 21, 2016 at 4:53 PM, Ley Foon Tan  wrote:
> >
> > This 2 patches fix the issue before and after retrain link.
> >
> > Ley Foon Tan (2):
> >   PCI: altera: check link status before retrain link
> >   PCI: altera: Polling for link up status after retrain the link
> >
> >  drivers/pci/host/pcie-altera.c | 48 
> > +++---
> >  1 file changed, 31 insertions(+), 17 deletions(-)
> >
>
> Hi Bjorn
>
> Do you any comment on these 2 patches?
>
> Regards
> Ley Foon

Hi Bjorn

Do you have any chance take a look these 2 patches? Hope they can go
into 4.8-rc1.
Thanks.


Regards
Ley Foon

[PATCH 1/2] PCI: altera: check link status before retrain link

[Ley Foon Tan]

Checking for link up status before retrain link.

Note, moves altera_pcie_link_is_up() and its dependency functions
to top of file.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/pcie-altera.c | 36 
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index dbac6fb..78f77e1 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -81,9 +81,29 @@ struct tlp_rp_regpair_t {
u32 reg1;
 };
 
+static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
+ const u32 reg)
+{
+   writel_relaxed(value, pcie->cra_base + reg);
+}
+
+static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
+{
+   return readl_relaxed(pcie->cra_base + reg);
+}
+
+static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
+{
+   return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
+}
+
 static void altera_pcie_retrain(struct pci_dev *dev)
 {
u16 linkcap, linkstat;
+   struct altera_pcie *pcie = dev->bus->sysdata;
+
+   if(!altera_pcie_link_is_up(pcie))
+   return;
 
/*
 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
@@ -120,17 +140,6 @@ static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, 
unsigned int  devfn,
return false;
 }
 
-static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
- const u32 reg)
-{
-   writel_relaxed(value, pcie->cra_base + reg);
-}
-
-static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
-{
-   return readl_relaxed(pcie->cra_base + reg);
-}
-
 static void tlp_write_tx(struct altera_pcie *pcie,
 struct tlp_rp_regpair_t *tlp_rp_regdata)
 {
@@ -139,11 +148,6 @@ static void tlp_write_tx(struct altera_pcie *pcie,
cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
 }
 
-static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
-{
-   return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
-}
-
 static bool altera_pcie_valid_config(struct altera_pcie *pcie,
 struct pci_bus *bus, int dev)
 {
-- 
1.8.2.1

[PATCH 2/2] PCI: altera: Polling for link up status after retrain the link

[Ley Foon Tan]

Some PCIe devices take longer time to reach link up state after retrain.
This patch polling for link up status after retrain the link. This is to
make sure the link is stable and up before we access to configuration space
registers after this.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/pcie-altera.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 78f77e1..a9de2a0 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -61,6 +61,8 @@
 #define TLP_LOOP   500
 #define RP_DEVFN   0
 
+#define LINK_UP_TIMEOUT5000
+
 #define INTX_NUM   4
 
 #define DWORD_MASK 3
@@ -101,6 +103,7 @@ static void altera_pcie_retrain(struct pci_dev *dev)
 {
u16 linkcap, linkstat;
struct altera_pcie *pcie = dev->bus->sysdata;
+   int timeout =  0;
 
if(!altera_pcie_link_is_up(pcie))
return;
@@ -115,9 +118,16 @@ static void altera_pcie_retrain(struct pci_dev *dev)
return;
 
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
-   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
+   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
 PCI_EXP_LNKCTL_RL);
+   while(!altera_pcie_link_is_up(pcie)) {
+   timeout++;
+   if (timeout > LINK_UP_TIMEOUT)
+   break;
+   udelay(5);
+   }
+   }
 }
 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
 
-- 
1.8.2.1

[PATCH 0/2] PCI: altera: fix link retrain

[Ley Foon Tan]

This 2 patches fix the issue before and after retrain link.

Ley Foon Tan (2):
  PCI: altera: check link status before retrain link
  PCI: altera: Polling for link up status after retrain the link

 drivers/pci/host/pcie-altera.c | 48 +++---
 1 file changed, 31 insertions(+), 17 deletions(-)

-- 
1.8.2.1

Re: [PATCH v4 0/2] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

On Fri, Aug 26, 2016 at 9:47 AM, Ley Foon Tan  wrote:
> Altera PCIe IP can be configured as rootport or device and they might have
> same vendor ID. It will cause the system hang issue if Altera PCIe is in
> endpoint mode and work with other PCIe rootport that from other vendors.
>
> This series of patch rework configs accessors and move retrain function
> from _FIXUP to altera_pcie_host_init().
>
> History:
> v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
> v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
> v4: Split patch to 2 patches
>
> Ley Foon Tan (2):
>   PCI: altera: Rework configs accessors
>   PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init()
>
>  drivers/pci/host/pcie-altera.c | 215 
> +
>  1 file changed, 132 insertions(+), 83 deletions(-)
>
Hi Bjorn

Do you have further comment on this patch series?
Thanks.

Regards
Ley Foon

Re: [PATCH v2] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas  wrote:
> On Fri, Aug 19, 2016 at 04:24:38PM +0800, Ley Foon Tan wrote:
>> Altera PCIe IP can be configured as rootport or device and they might have
>> same vendor ID. It will cause the system hang issue if Altera PCIe is in
>> endpoint mode and work with other PCIe rootport that from other vendors.
>> So, add the rootport mode checking in link retrain fixup function.
>>
>> Signed-off-by: Ley Foon Tan 
>> ---
>> v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
>> ---
>>  drivers/pci/host/pcie-altera.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
>> index 58eef99..33b6968 100644
>> --- a/drivers/pci/host/pcie-altera.c
>> +++ b/drivers/pci/host/pcie-altera.c
>> @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev)
>>   u16 linkcap, linkstat;
>>   struct altera_pcie *pcie = dev->bus->sysdata;
>>
>> + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
>> + return;
>> +
>>   if (!altera_pcie_link_is_up(pcie))
>>   return;
>
> Instead of making this a PCI fixup, can you make an
> altera_pcie_host_init() function, call it from altera_pcie_probe(),
> and do the link retrain there?  Then you wouldn't need to worry about
> whether this is a Root Port or an Endpoint, plus it would make the
> altera driver structure more like the other drivers.
>
> You would call altera_pcie_host_init() before pci_scan_root_bus(), so
> you wouldn't have a pci_dev yet, so you wouldn't be able to use
> pcie_capability_set_word() to set the PCI_EXP_LNKCTL_RL bit.  But I
> assume there's some device-dependent way to access it using
> cra_writel()?
We can't use cra_write() to set PCI_EXP_LNKCTL_RL bit. We can use
pci_bus_find_capability() and pci_bus_read_config_word() with struct
pci_bus instead.
But this only can be called after pci_scan_root_bus(). Found
iproc_pcie_check_link() have similar implementation.
Tested this method is working. Do you think it is okay? If yes, then I
will send in next revision.

Thanks.

Regards
Ley Foon

Re: [PATCH v2] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

On Thu, Aug 25, 2016 at 1:54 AM, Bjorn Helgaas  wrote:
> [+cc Ray, Scott, Jon, bcm-kernel-feedback-list]
>
> On Wed, Aug 24, 2016 at 03:07:52PM +0800, Ley Foon Tan wrote:
>> On Mon, Aug 22, 2016 at 11:47 PM, Bjorn Helgaas  wrote:
>> > On Fri, Aug 19, 2016 at 04:24:38PM +0800, Ley Foon Tan wrote:
>> >> Altera PCIe IP can be configured as rootport or device and they might have
>> >> same vendor ID. It will cause the system hang issue if Altera PCIe is in
>> >> endpoint mode and work with other PCIe rootport that from other vendors.
>> >> So, add the rootport mode checking in link retrain fixup function.
>> >>
>> >> Signed-off-by: Ley Foon Tan 
>> >> ---
>> >> v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
>> >> ---
>> >>  drivers/pci/host/pcie-altera.c | 3 +++
>> >>  1 file changed, 3 insertions(+)
>> >>
>> >> diff --git a/drivers/pci/host/pcie-altera.c 
>> >> b/drivers/pci/host/pcie-altera.c
>> >> index 58eef99..33b6968 100644
>> >> --- a/drivers/pci/host/pcie-altera.c
>> >> +++ b/drivers/pci/host/pcie-altera.c
>> >> @@ -139,6 +139,9 @@ static void altera_pcie_retrain(struct pci_dev *dev)
>> >>   u16 linkcap, linkstat;
>> >>   struct altera_pcie *pcie = dev->bus->sysdata;
>> >>
>> >> + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
>> >> + return;
>> >> +
>> >>   if (!altera_pcie_link_is_up(pcie))
>> >>   return;
>> >
>> > Instead of making this a PCI fixup, can you make an
>> > altera_pcie_host_init() function, call it from altera_pcie_probe(),
>> > and do the link retrain there?  Then you wouldn't need to worry about
>> > whether this is a Root Port or an Endpoint, plus it would make the
>> > altera driver structure more like the other drivers.
>> >
>> > You would call altera_pcie_host_init() before pci_scan_root_bus(), so
>> > you wouldn't have a pci_dev yet, so you wouldn't be able to use
>> > pcie_capability_set_word() to set the PCI_EXP_LNKCTL_RL bit.  But I
>> > assume there's some device-dependent way to access it using
>> > cra_writel()?
>> We can't use cra_write() to set PCI_EXP_LNKCTL_RL bit.
>
> Why not?  I don't mean it has to be cra_write(), but isn't there some
> way you can write that bit before we scan the root bus?  It doesn't
> make sense that we have to scan the bus before we can train the link.
>
> We want to be able to tell the PCI core "all the device-specific root
> complex initialization has been done, here are the config accessors
> you need, please scan for devices."  I want to keep device-specific
> things like this quirk directly in the driver and out of the
> enumeration process.
We don't have internal register bit to trigger link retrain, but need to set
PCI_EXP_LNKCTL_RL bit in Link Control register of PCIe Capabilities Structure.
So, this requires the altera_pcie_cfg_read() and altera_pcie_cfg_write().
I can restructure the altera_pcie_cfg_read() and
altera_pcie_cfg_write() and have
new _altera_pcie_cfg_read() and _altera_pcie_cfg_write() that avoid
the dependency of struct pci_bus. By doing this, we can retrain the link before
pci_scan_root_bus and remove _FIXUP()

Will send new v3 patch, please take a look.

>
>> We can use
>> pci_bus_find_capability() and pci_bus_read_config_word() with struct
>> pci_bus instead.
>> But this only can be called after pci_scan_root_bus().
>
>> Found
>> iproc_pcie_check_link() have similar implementation.
>
> You're right, and I don't like iproc_pcie_check_link() either, for the
> same reasons.
>
> The iproc_pcie_check_link() is a little better because it's called
> before enumeration:
>
>   pci_create_root_bus()
>   iproc_pcie_check_link()
>   pci_scan_child_bus()
>
> But it would be a lot better if iproc_pcie_check_link() were done
> first, before pci_create_root_bus().  Then it would be more like the
> structure of other drivers, and we could use pci_scan_root_bus()
> instead.
>
> Comments, iproc folks?
>
> Bjorn
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

Altera PCIe IP can be configured as rootport or device and they might have
same vendor ID. It will cause the system hang issue if Altera PCIe is in
endpoint mode and work with other PCIe rootport that from other vendors.
Moved retrain function to before pci_scan_root_bus and removed _FIXUP.
Add _altera_pcie_cfg_read() and _altera_pcie_cfg_write() to use struct
altera_pcie as argument instead of struct pci_bus.

Signed-off-by: Ley Foon Tan 
---
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
---
 drivers/pci/host/pcie-altera.c | 217 +
 1 file changed, 134 insertions(+), 83 deletions(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..4ce6d86 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -43,6 +43,8 @@
 #define RP_LTSSM_MASK  0x1f
 #define LTSSM_L0   0xf
 
+#define PCIE_CAP_OFFSET0x80
+
 /* TLP configuration type 0 and 1 */
 #define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
 #define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -100,66 +102,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie 
*pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 }
 
-static void altera_wait_link_retrain(struct pci_dev *dev)
-{
-   u16 reg16;
-   unsigned long start_jiffies;
-   struct altera_pcie *pcie = dev->bus->sysdata;
-
-   /* Wait for link training end. */
-   start_jiffies = jiffies;
-   for (;;) {
-   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
-   if (!(reg16 & PCI_EXP_LNKSTA_LT))
-   break;
-
-   if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
-   dev_err(&pcie->pdev->dev, "link retrain timeout\n");
-   break;
-   }
-   udelay(100);
-   }
-
-   /* Wait for link is up */
-   start_jiffies = jiffies;
-   for (;;) {
-   if (altera_pcie_link_is_up(pcie))
-   break;
-
-   if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
-   dev_err(&pcie->pdev->dev, "link up timeout\n");
-   break;
-   }
-   udelay(100);
-   }
-}
-
-static void altera_pcie_retrain(struct pci_dev *dev)
-{
-   u16 linkcap, linkstat;
-   struct altera_pcie *pcie = dev->bus->sysdata;
-
-   if (!altera_pcie_link_is_up(pcie))
-   return;
-
-   /*
-* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
-* current speed is 2.5 GB/s.
-*/
-   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
-
-   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
-   return;
-
-   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
-   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
-   pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
-PCI_EXP_LNKCTL_RL);
-   altera_wait_link_retrain(dev);
-   }
-}
-DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-
 /*
  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
@@ -330,22 +272,14 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, 
u8 bus, u32 devfn,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
-   int where, int size, u32 *value)
+static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int where, int size,
+u32 *value)
 {
-   struct altera_pcie *pcie = bus->sysdata;
int ret;
u32 data;
u8 byte_en;
 
-   if (altera_pcie_hide_rc_bar(bus, devfn, where))
-   return PCIBIOS_BAD_REGISTER_NUMBER;
-
-   if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
-   *value = 0x;
-   return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
switch (size) {
case 1:
byte_en = 1 << (where & 3);
@@ -358,7 +292,7 @@ static int altera_pcie_cfg_read(struct pci_bus *bus, 
unsigned int devfn,
break;
}
 
-   ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
+   ret = tlp_cfg_dword_read(pcie, busno, devfn,
 (where & ~DWORD_MASK), byte_en, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;

Re: [PATCH v3] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

On Thu, Aug 25, 2016 at 9:56 PM, Bjorn Helgaas  wrote:
> On Thu, Aug 25, 2016 at 01:59:56PM +0800, Ley Foon Tan wrote:
>> Altera PCIe IP can be configured as rootport or device and they might have
>> same vendor ID. It will cause the system hang issue if Altera PCIe is in
>> endpoint mode and work with other PCIe rootport that from other vendors.
>> Moved retrain function to before pci_scan_root_bus and removed _FIXUP.
>> Add _altera_pcie_cfg_read() and _altera_pcie_cfg_write() to use struct
>> altera_pcie as argument instead of struct pci_bus.
>
> I think this makes sense.  Can you split this into two patches:
>
>   - Rework the config accessors
>   - Move retrain from the quirk to altera_pcie_host_init()
Okay, will resend this.
Thanks.

> I also want to look through the other host bridge drivers and see if
> there's any consistency in naming and structure of the config accessors.
> The pattern of a wrapper that takes "struct pci_bus *, unsigned int devfn,
> ..." that calls an internal function that takes the driver structure
> instead of the "struct pci_bus *" might be useful in other drivers as well.

[PATCH v4 2/2] PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init()

[Ley Foon Tan]

Altera PCIe IP can be configured as rootport or device and they might have
same vendor ID. It will cause the system hang issue if Altera PCIe is in
endpoint mode and work with other PCIe rootport that from other vendors.

Move link retrain function from _FIXUP to altera_pcie_host_init().

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/pcie-altera.c | 151 +
 1 file changed, 91 insertions(+), 60 deletions(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 34e6258..4ca50a2 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -43,6 +43,7 @@
 #define RP_LTSSM_MASK  0x1f
 #define LTSSM_L0   0xf
 
+#define PCIE_CAP_OFFSET0x80
 /* TLP configuration type 0 and 1 */
 #define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
 #define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -100,66 +101,6 @@ static bool altera_pcie_link_is_up(struct altera_pcie 
*pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
 }
 
-static void altera_wait_link_retrain(struct pci_dev *dev)
-{
-   u16 reg16;
-   unsigned long start_jiffies;
-   struct altera_pcie *pcie = dev->bus->sysdata;
-
-   /* Wait for link training end. */
-   start_jiffies = jiffies;
-   for (;;) {
-   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, ®16);
-   if (!(reg16 & PCI_EXP_LNKSTA_LT))
-   break;
-
-   if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
-   dev_err(&pcie->pdev->dev, "link retrain timeout\n");
-   break;
-   }
-   udelay(100);
-   }
-
-   /* Wait for link is up */
-   start_jiffies = jiffies;
-   for (;;) {
-   if (altera_pcie_link_is_up(pcie))
-   break;
-
-   if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
-   dev_err(&pcie->pdev->dev, "link up timeout\n");
-   break;
-   }
-   udelay(100);
-   }
-}
-
-static void altera_pcie_retrain(struct pci_dev *dev)
-{
-   u16 linkcap, linkstat;
-   struct altera_pcie *pcie = dev->bus->sysdata;
-
-   if (!altera_pcie_link_is_up(pcie))
-   return;
-
-   /*
-* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
-* current speed is 2.5 GB/s.
-*/
-   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
-
-   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
-   return;
-
-   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
-   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
-   pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
-PCI_EXP_LNKCTL_RL);
-   altera_wait_link_retrain(dev);
-   }
-}
-DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
-
 /*
  * Altera PCIe port uses BAR0 of RC's configuration space as the translation
  * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
@@ -434,6 +375,90 @@ static struct pci_ops altera_pcie_ops = {
.write = altera_pcie_cfg_write,
 };
 
+static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
+   unsigned int devfn, int offset, u16 *value)
+{
+   u32 data;
+   int ret;
+
+   ret = _altera_pcie_cfg_read(pcie, busno, devfn,
+   PCIE_CAP_OFFSET + offset, sizeof(*value),
+   &data);
+   *value = data;
+   return ret;
+}
+
+static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int offset, u16 value)
+{
+   return _altera_pcie_cfg_write(pcie, busno, devfn,
+ PCIE_CAP_OFFSET + offset, sizeof(value),
+ value);
+}
+
+static void altera_wait_link_retrain(struct altera_pcie *pcie)
+{
+   u16 reg16;
+   unsigned long start_jiffies;
+
+   /* Wait for link training end. */
+   start_jiffies = jiffies;
+   for (;;) {
+   altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
+PCI_EXP_LNKSTA, ®16);
+   if (!(reg16 & PCI_EXP_LNKSTA_LT))
+   break;
+
+   if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
+   dev_err(&pcie->pdev->dev, "link retrain timeout\n");
+   break;
+   }
+   udelay(100);
+   }
+
+   /* Wait

[PATCH v4 0/2] PCI: altera: Retrain link in rootport mode only

[Ley Foon Tan]

Altera PCIe IP can be configured as rootport or device and they might have
same vendor ID. It will cause the system hang issue if Altera PCIe is in
endpoint mode and work with other PCIe rootport that from other vendors.

This series of patch rework configs accessors and move retrain function
from _FIXUP to altera_pcie_host_init().

History:
v2: change to check PCIe type is PCI_EXP_TYPE_ROOT_PORT
v3: Move retrain function to before pci_scan_root_bus and remove _FIXUP
v4: Split patch to 2 patches

Ley Foon Tan (2):
  PCI: altera: Rework configs accessors
  PCI: altera: Move retrain from _FIXUP to altera_pcie_host_init()

 drivers/pci/host/pcie-altera.c | 215 +
 1 file changed, 132 insertions(+), 83 deletions(-)

-- 
1.8.2.1

Re: [Nios2-dev] [PATCH] nios2: use of_property_read_bool

[Ley Foon Tan]

On Wed, Aug 10, 2016 at 8:27 PM, Tobias Klauser  wrote:
> Use of_property_read_bool instead of open-coding it as fpcu_has. Convert
> the members of struct cpuinfo from u32 to bool accordingly as they are
> only used as boolean anyhow.
>
> Signed-off-by: Tobias Klauser 
Acked-by: Ley Foon Tan 

Thanks.

> ---
>  arch/nios2/include/asm/cpuinfo.h |  8 
>  arch/nios2/kernel/cpuinfo.c  | 15 +--
>  2 files changed, 9 insertions(+), 14 deletions(-)
>

[PATCH v4 1/2] PCI: altera: Rework configs accessors

[Ley Foon Tan]

Rework configs accessors so a future patch can use them in _probe()
with struct altera_pcie instead of struct pci_bus.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/pcie-altera.c | 64 +++---
 1 file changed, 41 insertions(+), 23 deletions(-)

diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index 58eef99..34e6258 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -330,22 +330,14 @@ static int tlp_cfg_dword_write(struct altera_pcie *pcie, 
u8 bus, u32 devfn,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
-   int where, int size, u32 *value)
+static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
+unsigned int devfn, int where, int size,
+u32 *value)
 {
-   struct altera_pcie *pcie = bus->sysdata;
int ret;
u32 data;
u8 byte_en;
 
-   if (altera_pcie_hide_rc_bar(bus, devfn, where))
-   return PCIBIOS_BAD_REGISTER_NUMBER;
-
-   if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
-   *value = 0x;
-   return PCIBIOS_DEVICE_NOT_FOUND;
-   }
-
switch (size) {
case 1:
byte_en = 1 << (where & 3);
@@ -358,7 +350,7 @@ static int altera_pcie_cfg_read(struct pci_bus *bus, 
unsigned int devfn,
break;
}
 
-   ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
+   ret = tlp_cfg_dword_read(pcie, busno, devfn,
 (where & ~DWORD_MASK), byte_en, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
@@ -378,20 +370,14 @@ static int altera_pcie_cfg_read(struct pci_bus *bus, 
unsigned int devfn,
return PCIBIOS_SUCCESSFUL;
 }
 
-static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
-int where, int size, u32 value)
+static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
+ unsigned int devfn, int where, int size,
+ u32 value)
 {
-   struct altera_pcie *pcie = bus->sysdata;
u32 data32;
u32 shift = 8 * (where & 3);
u8 byte_en;
 
-   if (altera_pcie_hide_rc_bar(bus, devfn, where))
-   return PCIBIOS_BAD_REGISTER_NUMBER;
-
-   if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
-   return PCIBIOS_DEVICE_NOT_FOUND;
-
switch (size) {
case 1:
data32 = (value & 0xff) << shift;
@@ -407,8 +393,40 @@ static int altera_pcie_cfg_write(struct pci_bus *bus, 
unsigned int devfn,
break;
}
 
-   return tlp_cfg_dword_write(pcie, bus->number, devfn,
-   (where & ~DWORD_MASK), byte_en, data32);
+   return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
+  byte_en, data32);
+}
+
+static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
+   int where, int size, u32 *value)
+{
+   struct altera_pcie *pcie = bus->sysdata;
+
+   if (altera_pcie_hide_rc_bar(bus, devfn, where))
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
+   *value = 0x;
+   return PCIBIOS_DEVICE_NOT_FOUND;
+   }
+
+   return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
+value);
+}
+
+static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
+int where, int size, u32 value)
+{
+   struct altera_pcie *pcie = bus->sysdata;
+
+   if (altera_pcie_hide_rc_bar(bus, devfn, where))
+   return PCIBIOS_BAD_REGISTER_NUMBER;
+
+   if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
+   return PCIBIOS_DEVICE_NOT_FOUND;
+
+   return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
+value);
 }
 
 static struct pci_ops altera_pcie_ops = {
-- 
1.8.2.1

[PATCH v6 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 6th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Marc Zyngier in v5 and minor fixes.

It is based on patch series from Marc Zyngier "Per-device MSI domain &
platform MSI" [1] to get rid of struct msi_controller.

v5->v6 changes:
- altera-msi: remove irq_enable and irq_disable
- pcie-altera: change to PCI_VENDOR_ID_ALTERA for fixup
- pcie-altera: change to use switch case method
- update interrupt handling
- include: pci: add Altera PCI vendor ID

[1]: https://lkml.org/lkml/2015/7/23/172

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238

Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  16 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 311 +++
 drivers/pci/host/pcie-altera.c | 593 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1018 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v6 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 30b3bc1..362b053 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -15,6 +15,7 @@ generic-y += local64.h
 generic-y += mcs_spinlock.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v6 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index fcff8f8..9e62bcc 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v6 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 593 +
 3 files changed, 602 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 675c2d1..43867d7 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,12 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   tristate "Altera PCIe controller"
+   depends on ARCH_SOCFPGA
+   select PCI_DOMAINS
+   help
+ Say Y here if you want to enable PCIe controller support for Altera
+ SoCFPGA family of SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..f73c499
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,593 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define A2P_ADDR_MAP_LO0   0x1000
+#define A2P_ADDR_MAP_HI0   0x1004
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xF
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xF
+#define RP_LTSSM   0x3C64
+#define LTSSM_L0   0xF
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1D
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag)(((reqid) << 16) | (tag << 8) | 
0xF)
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_COMPL_STATUS(hdr)  (((hdr) & 0xE0) >> 13)
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   10
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability

[PATCH v6 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..53ad2388
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller = <1>;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..4440db1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs" or "txs": TX slave port region
+   "Cra" or "cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v6 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 311 +
 3 files changed, 320 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 43867d7..b50df1e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -153,4 +153,12 @@ config PCIE_ALTERA
  Say Y here if you want to enable PCIe controller support for Altera
  SoCFPGA family of SoCs.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera SocFPGA SoC.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..5a042ea
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, u32 value, u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(unsigned int irq, struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_

[PATCH v6 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b60e2b2..d70fe18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7780,6 +7780,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -7881,6 +7889,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v8 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Mon, Oct 12, 2015 at 8:03 PM, Arnd Bergmann  wrote:
>
> On Friday 09 October 2015 18:15:40 Bjorn Helgaas wrote:
> >
> > I don't know if this should be a kernel taint, a simple warning in
> > dmesg, or what.  I guess the tainting mechanism is probably too
> > general-purpose for this, and add_taint() doesn't give any dmesg
> > indication.  We wouldn't see the taint unless the problem actually
> > caused an oops or panic.  In this case, I think I want a clue in dmesg
> > so we have a chance of seeing it even if there is no oops.  So
> > probably something like a dev_warn("non-compliant config accesses")
> > would work.
> >
> > You really should double-check with the hardware guys, because it's
> > pretty obvious that the PCI spec requires 1- and 2-byte config
> > accesses to work correctly.  For example, if you read/modify/write to
> > update PCI_COMMAND, you will inadvertently clear the RW1C bits in
> > PCI_STATUS.
>
> Would it help to require a DT property here that flags the device
> as having a broken config space?
>
> Then we could implement both in the driver, and only use the
> RMW based implementation if the firmware describes the device
> as "altera,broken-pci-config-space".
>

I have checked the PCI/TLP specification, the address needs to be
4-byte aligned. But, we can use "byte enable" field to update specific
bytes.
For example, if byte enable is 0x3 (0011b), that mean it only update
lower 2 bytes. By doing this, we can resolve the RW1C issue here.
I will update the driver with this in next revision.

Thanks for reviewing.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v9 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 9th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly update the config read and write functions to support read/write
specific bytes to avoid read-modify-write and minor fixes.

This patchset is based on v4.3-rc5.

v8->v9 changes:
- altera-pcie-msi: fix missing mutex_unlock when error return
- altera-pcie: update config read and write functions to support read/write
   specific bytes

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238
[v6]: https://lkml.org/lkml/2015/9/1/177
[v7]: https://lkml.org/lkml/2015/9/20/193
[v8]: http://www.kernelhub.org/?msg=853553&p=2

Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  15 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 313 +++
 drivers/pci/host/pcie-altera.c | 592 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1018 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v9 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..08e4462 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v9 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   7 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 592 +
 3 files changed, 600 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..f956206 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,11 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   bool "Altera PCIe controller"
+   select PCI_DOMAINS
+   help
+Say Y here if you want to enable PCIe controller support on Altera
+FPGA.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..e714e95
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,592 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define A2P_ADDR_MAP_LO0   0x1000
+#define A2P_ADDR_MAP_HI0   0x1004
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xF
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xF
+#define RP_LTSSM   0x3C64
+#define LTSSM_L0   0xF
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1D
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag, be)(((reqid) << 16) | (tag << 8) | (be))
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_COMPL_STATUS(hdr)  (((hdr) & 0xE0) >> 13)
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   500
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
+
+

[PATCH v9 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 313 +
 3 files changed, 322 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f956206..56daa1e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -152,4 +152,12 @@ config PCIE_ALTERA
 Say Y here if you want to enable PCIe controller support on Altera
 FPGA.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera FPGA.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..1d8a1b6
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, const u32 value,
+ const u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, const u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_

[PATCH v9 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5f46784..0f55f38 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7943,6 +7943,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -8044,6 +8052,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v9 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index be648eb..bd42530 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += local.h
 generic-y += local64.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v9 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..09cd3bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..2951a6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs": TX slave port region
+   "Cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 1/4] asm-generic: add pci required defines and functions

[Ley Foon Tan]

Add the generic #define and functions that required by the PCI framework.
Architecture pci.h can overwrite with their implementation if needed.

Signed-off-by: Ley Foon Tan 
---
 include/asm-generic/pci.h | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/include/asm-generic/pci.h b/include/asm-generic/pci.h
index f24bc51..2771b32 100644
--- a/include/asm-generic/pci.h
+++ b/include/asm-generic/pci.h
@@ -21,4 +21,38 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev 
*dev, int channel)
 #define PCI_DMA_BUS_IS_PHYS(1)
 #endif
 
+#ifdef CONFIG_PCI
+
+#ifndef PCIBIOS_MIN_IO
+#define PCIBIOS_MIN_IO (0UL)
+#endif
+
+#ifndef PCIBIOS_MIN_MEM
+#define PCIBIOS_MIN_MEM(0UL)
+#endif
+
+#ifndef pcibios_assign_all_busses
+#define pcibios_assign_all_busses()(pci_has_flag(PCI_REASSIGN_ALL_BUS))
+#endif
+
+#ifndef pci_proc_domain
+#define pci_proc_domain pci_proc_domain
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+#ifdef CONFIG_PCI_DOMAINS_GENERIC
+   return pci_domain_nr(bus);
+#else
+   return 1;
+#endif
+}
+#endif
+
+extern int isa_dma_bridge_buggy;
+
+#else
+
+#define isa_dma_bridge_buggy   (0)
+
+#endif /* CONFIG_PCI */
+
 #endif /* _ASM_GENERIC_PCI_H */
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 0/4] Add PCI support on nios2 architecture

[Ley Foon Tan]

This is 2nd version of patch to add pci support for nios2 architecture.
This patchset also update asm-generic/pci.h to include PCI generic 
define/function
as suggested by Arnd.
It requires pci_fixup_irqs() from setup-irq.c.

v1->v2 changes:
- nios2: remove PCI_SYSCALL from Kconfig
- nios2: set IO_SPACE_LIMIT to 0x
- nios2: remove arch/nios2/include/asm/pci.h and use asm-generic pci.h
- pci: add include  to pci.c
- asm-generic: add pci generic functions/defines to pci.h

History
---
[v1]: https://lkml.org/lkml/2015/9/22/44

Ley Foon Tan (4):
  asm-generic: add pci required defines and functions
  pci: add include 
  PCI: Build setup-irq.o for nios2
  nios2: Add architectural support for PCIe

 arch/nios2/Kconfig| 21 +
 arch/nios2/include/asm/Kbuild |  1 +
 arch/nios2/include/asm/io.h   | 12 ++--
 arch/nios2/kernel/Makefile|  1 +
 arch/nios2/kernel/pci.c   | 33 +
 drivers/pci/Makefile  |  1 +
 drivers/pci/pci.c |  1 +
 include/asm-generic/pci.h | 34 ++
 8 files changed, 102 insertions(+), 2 deletions(-)
 create mode 100644 arch/nios2/kernel/pci.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 2/4] pci: add include

[Ley Foon Tan]

Include  explicitly, it depends on architecture's pci.h
to include it before this. It cause compilation error when we move to
asm-generic pci.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 6a9a111..ef2f09e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "pci.h"
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 3/4] PCI: Build setup-irq.o for nios2

[Ley Foon Tan]

nios2 requires setup-irq.o to provide pci_fixup_irqs() implementation.

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index be3f631..282b1b4 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MIPS) += setup-irq.o
 obj-$(CONFIG_TILE) += setup-irq.o
 obj-$(CONFIG_SPARC_LEON) += setup-irq.o
 obj-$(CONFIG_M68K) += setup-irq.o
+obj-$(CONFIG_NIOS2) += setup-irq.o
 
 #
 # ACPI Related PCI FW Functions
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v2 4/4] nios2: Add architectural support for PCIe

[Ley Foon Tan]

This patch add pcie support on nios2 platform.

Signed-off-by: Ley Foon Tan 
---
 arch/nios2/Kconfig| 21 +
 arch/nios2/include/asm/Kbuild |  1 +
 arch/nios2/include/asm/io.h   | 12 ++--
 arch/nios2/kernel/Makefile|  1 +
 arch/nios2/kernel/pci.c   | 33 +
 5 files changed, 66 insertions(+), 2 deletions(-)
 create mode 100644 arch/nios2/kernel/pci.c

diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
index 4375554..bde323f 100644
--- a/arch/nios2/Kconfig
+++ b/arch/nios2/Kconfig
@@ -11,6 +11,7 @@ config NIOS2
select HAVE_ARCH_KGDB
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
+   select MIGHT_HAVE_PCI
select OF
select OF_EARLY_FLATTREE
select SOC_BUS
@@ -194,6 +195,26 @@ config NIOS2_IO_REGION_BASE
 
 endmenu
 
+menu "Bus support"
+config PCI
+   bool "PCI support"
+   select GENERIC_PCI_IOMAP
+   help
+ This feature enables support for PCIe bus system. If you say Y
+ here, the kernel will include drivers and infrastructure code
+ to support PCIe bus devices.
+
+config PCI_DOMAINS
+   def_bool PCI
+
+config PCI_DOMAINS_GENERIC
+   def_bool PCI
+
+source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
+
+endmenu
+
 menu "Executable file formats"
 
 source "fs/Kconfig.binfmt"
diff --git a/arch/nios2/include/asm/Kbuild b/arch/nios2/include/asm/Kbuild
index d63330e..a7cace1 100644
--- a/arch/nios2/include/asm/Kbuild
+++ b/arch/nios2/include/asm/Kbuild
@@ -34,6 +34,7 @@ generic-y += mm-arch-hooks.h
 generic-y += mman.h
 generic-y += module.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += pci.h
 generic-y += percpu.h
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index c5a62da..0ba8388 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -14,8 +14,7 @@
 #include 
 #include 
 
-/* PCI is not supported in nios2, set this to 0. */
-#define IO_SPACE_LIMIT 0
+#define IO_SPACE_LIMIT 0x
 
 #define readb_relaxed(addr)readb(addr)
 #define readw_relaxed(addr)readw(addr)
@@ -45,6 +44,15 @@ static inline void iounmap(void __iomem *addr)
__iounmap(addr);
 }
 
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+   return NULL;
+}
+
+static inline void ioport_unmap(void __iomem *p)
+{
+}
+
 #define ioremap_wc ioremap_nocache
 #define ioremap_wt ioremap_nocache
 
diff --git a/arch/nios2/kernel/Makefile b/arch/nios2/kernel/Makefile
index 1aae257..bb1ef81 100644
--- a/arch/nios2/kernel/Makefile
+++ b/arch/nios2/kernel/Makefile
@@ -10,6 +10,7 @@ obj-y += entry.o
 obj-y  += insnemu.o
 obj-y  += irq.o
 obj-y  += nios2_ksyms.o
+obj-y  += pci.o
 obj-y  += process.o
 obj-y  += prom.o
 obj-y  += ptrace.o
diff --git a/arch/nios2/kernel/pci.c b/arch/nios2/kernel/pci.c
new file mode 100644
index 000..d28aed7
--- /dev/null
+++ b/arch/nios2/kernel/pci.c
@@ -0,0 +1,33 @@
+/* Copyright Altera Corporation (C) 2015. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2,
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include 
+
+/*
+ * Called after each bus is probed, but before its children are examined
+ */
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+   /* nothing to do, expected to be removed in the future */
+}
+
+/*
+ * We don't have to worry about legacy ISA devices, so nothing to do here
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+   resource_size_t size, resource_size_t align)
+{
+   return res->start;
+}
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v9 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Wed, Oct 14, 2015 at 4:20 PM, Arnd Bergmann  wrote:
> On Wednesday 14 October 2015 10:41:29 Ley Foon Tan wrote:
>> +static int altera_pcie_remove(struct platform_device *pdev)
>> +{
>> + struct altera_pcie *pcie = platform_get_drvdata(pdev);
>> +
>> + altera_pcie_free_irq_domain(pcie);
>> + platform_set_drvdata(pdev, NULL);
>> + return 0;
>> +}
>
> I just noticed this. Does it actually work to unload the module
> and tear down all the pci_dev structures in a safe way?
Good catch. It only can be compiled as builtin-moduley now, so we can
remove this _remove callback function.
Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v9 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Wed, Oct 14, 2015 at 5:09 PM, Arnd Bergmann  wrote:
> On Wednesday 14 October 2015 16:32:25 Ley Foon Tan wrote:
>> On Wed, Oct 14, 2015 at 4:20 PM, Arnd Bergmann  wrote:
>> > On Wednesday 14 October 2015 10:41:29 Ley Foon Tan wrote:
>> >> +static int altera_pcie_remove(struct platform_device *pdev)
>> >> +{
>> >> + struct altera_pcie *pcie = platform_get_drvdata(pdev);
>> >> +
>> >> + altera_pcie_free_irq_domain(pcie);
>> >> + platform_set_drvdata(pdev, NULL);
>> >> + return 0;
>> >> +}
>> >
>> > I just noticed this. Does it actually work to unload the module
>> > and tear down all the pci_dev structures in a safe way?
>> Good catch. It only can be compiled as builtin-moduley now, so we can
>> remove this _remove callback function.
>
> I think we should change both: make it possible to load the
> driver dynamically, and remove the altera_pcie_remove function.
This driver depends on the pci fixups to work correctly. But, fixups
callback functions in this driver are not being call if the driver is
loadable module.
The linker script keeps all pci fixup callbacks in pci fixup regions
during kernel compile time. So, it needs to be builtin module. Do you
know any way we can update those fixup regions?

>
> You can prevent the module from being unloaded if you also remove
> the module_platform_driver() directive and add a module_init()
> without a matching module_exit().
>
> Please also add a '.suppress_bind_attrs = true,' flag in the driver
> struct to prevent manual unbinding.
I think we don't need these if it only can work as builtin module.

Thanks for reviewing.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v9 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Wed, Oct 14, 2015 at 5:36 PM, Arnd Bergmann  wrote:
> On Wednesday 14 October 2015 17:28:45 Ley Foon Tan wrote:
>> On Wed, Oct 14, 2015 at 5:09 PM, Arnd Bergmann  wrote:
>> > On Wednesday 14 October 2015 16:32:25 Ley Foon Tan wrote:
>> >> On Wed, Oct 14, 2015 at 4:20 PM, Arnd Bergmann  wrote:
>> >> > On Wednesday 14 October 2015 10:41:29 Ley Foon Tan wrote:
>> >> >> +static int altera_pcie_remove(struct platform_device *pdev)
>> >> >> +{
>> >> >> + struct altera_pcie *pcie = platform_get_drvdata(pdev);
>> >> >> +
>> >> >> + altera_pcie_free_irq_domain(pcie);
>> >> >> + platform_set_drvdata(pdev, NULL);
>> >> >> + return 0;
>> >> >> +}
>> >> >
>> >> > I just noticed this. Does it actually work to unload the module
>> >> > and tear down all the pci_dev structures in a safe way?
>> >> Good catch. It only can be compiled as builtin-moduley now, so we can
>> >> remove this _remove callback function.
>> >
>> > I think we should change both: make it possible to load the
>> > driver dynamically, and remove the altera_pcie_remove function.
>> This driver depends on the pci fixups to work correctly. But, fixups
>> callback functions in this driver are not being call if the driver is
>> loadable module.
>
> Ah, I see. We should find a better way to deal with this, as we
> are getting an increasing number of host driver specific fixups.
>
> Bjorn, do you have any idea here?
>
> Could we perhaps have a helper function that lets us register
> fixups dynamically?
>
>> The linker script keeps all pci fixup callbacks in pci fixup regions
>> during kernel compile time. So, it needs to be builtin module. Do you
>> know any way we can update those fixup regions?
>
> The only method I'm aware of at the moment is move the fixups to
> drivers/pci/quirks.c and enclose them in an #ifdef if you want them
> to not appear in kernels that don't support your SoC.
By looking at the drivers/pci/quirks.c, it looks like it is mainly for
the pci endpoint devices.
Fixups for host controller are in the driver itself.

>
>> > You can prevent the module from being unloaded if you also remove
>> > the module_platform_driver() directive and add a module_init()
>> > without a matching module_exit().
>> >
>> > Please also add a '.suppress_bind_attrs = true,' flag in the driver
>> > struct to prevent manual unbinding.
>> I think we don't need these if it only can work as builtin module.
>
> No, this is orthogonal, you need it either way, as built-in drivers
> can still be unbound by writing to sysfs. Try writing the device name
> to /sys/bus/platform/drivers/altera-pcie/unbind and watch it blow up ;-)
Oh I see. Will update with your suggestion.

Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v6 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Tue, Sep 8, 2015 at 5:19 PM, Lorenzo Pieralisi
 wrote:
> On Fri, Sep 04, 2015 at 09:29:14AM +0100, Ley Foon Tan wrote:
>> On Wed, Sep 2, 2015 at 12:33 AM, Lorenzo Pieralisi
>>  wrote:
>
> [...]
>
>> > > +static bool altera_pcie_valid_config(struct altera_pcie *pcie,
>> > > +struct pci_bus *bus, int dev)
>> > > +{
>> > > +   /* If there is no link, then there is no device */
>> > > +   if (bus->number != pcie->root_bus_nr) {
>> > > +   if (!altera_pcie_link_is_up(pcie))
>> > > +   return false;
>> > > +   }
>> >
>> > Can you explain to pls me why you have to check this for every config
>> > transaction ? Isn't it something that can prevent probing the
>> > host controller altogether ?
>> In our PCIe hardware spec, it stated that software should check the
>> link status before issuing a configuration request to downstream
>> ports.
>> BTW, other pci controllers have similar implementation as well, eg: dw
>> pci, mvebu pci.
>
> Understood, thanks.
>
> [...]
>
>> > > +static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
>> > > +{
>> > > +   u8 loop;
>> > > +   struct tlp_rp_regpair_t tlp_rp_regdata;
>> > > +
>> > > +   for (loop = 0; loop < TLP_LOOP; loop++) {
>> > > +   tlp_read_rx(pcie, &tlp_rp_regdata);
>> > > +   if (tlp_rp_regdata.ctrl & RP_RXCPL_EOP) {
>> > > +   if (value)
>> > > +   *value = tlp_rp_regdata.reg0;
>> > > +   return PCIBIOS_SUCCESSFUL;
>> > > +   }
>> > > +   udelay(5);
>> >
>> > Could you comment please on the chosen udelay/TLP_LOOP values (ie how
>> > did you come up with them) ?
>> For udelay value, we just want to have small delay between each read.
>
> I would explain how you chose the value, in particular if it can
> affect next generation hosts sharing the same driver.
Actually, we don't have any calculation to choose the value. Just want
to give small relaxation between each read.
It is request from Marc in previous review.
>
>> For TLP_LOOP value, minimum 2 loops to read tlp headers and 1 loop to
>> read data payload. So, we choose to poll 10 loops for maximum.
>
> Add it to a comment.
Okay.
>
[...]
>> >
>> > > +
>> > > +   /* clear all interrupts */
>> > > +   cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
>> > > +   /* enable all interrupts */
>> > > +   cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
>> > > +
>> > > +   bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, 
>> > > &altera_pcie_ops,
>> > > +   pcie, &pcie->resources);
>> > > +   if (!bus)
>> > > +   return -ENOMEM;
>> > > +
>> > > +   pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
>> > > +   pci_assign_unassigned_bus_resources(bus);
>> >
>> > I think you are missing a call to pcie_bus_configure_settings(),
>> > see drivers/pci/host/pci-host-generic.c
>> Other pci controller drivers like xgene and iproc don't call to this
>> function, but it call in
>> arch/arm/kernel/bios32.c:pci_common_init_dev().
>> Do we really need this?
>
> It is there to provide a way to configure the system MPS, through
> command line parameters, it is always a good idea to have it and
> it should be part of your driver so that you can tune it in case
> the MPS is misconfigured or you want to apply a specific configuration
> for a given system.
>
> Have a look at pcie_bus_config and how it is used in
> pcie_bus_configure_settings(), that would clarify further.
Thanks for explanation. I will add it.

Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[GIT PULL] arch/nios2 update for 4.3-rc1

[Ley Foon Tan]

Hi Linus,

Here are the nios2 updates for v4.3.

- add defconfig and device tree for MAX 10 development kit
- migrate to new 'set-state' interface for timer
- fix unaligned handler
- MAINTAINERS: update nios2 git repo

Please consider pulling.

Regards
Ley Foon


The following changes since commit 64291f7db5bd8150a74ad2036f1037e6a0428df2:

  Linux 4.2 (2015-08-30 11:34:09 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git 
tags/nios2-v4.3-rc1

for you to fetch changes up to 08441d462ebdc64df79b392f877e26522616bad5:

  nios2: add Max10 defconfig (2015-09-08 18:16:02 +0800)


nios2 update for v4.3-rc1

- add defconfig and device tree for max 10 support
- migrate to new 'set-state' interface for timer
- fix unaligned handler
- MAINTAINERS: update nios2 git repo


Bernd Weiberg (2):
  nios2: fixed variable imm16 to s16
  nios2: remove unused statistic counters

Chee Nouk Phoon (2):
  nios2: Add Max10 device tree
  nios2: add Max10 defconfig

Ley Foon Tan (1):
  MAINTAINERS: update nios2 git repo

Viresh Kumar (1):
  nios2/time: Migrate to new 'set-state' interface

 MAINTAINERS|   2 +-
 arch/nios2/boot/dts/10m50_devboard.dts | 248 +
 arch/nios2/configs/10m50_defconfig |  81 +++
 arch/nios2/kernel/misaligned.c |  20 +--
 arch/nios2/kernel/time.c   |  49 ---
 5 files changed, 360 insertions(+), 40 deletions(-)
 create mode 100755 arch/nios2/boot/dts/10m50_devboard.dts
 create mode 100755 arch/nios2/configs/10m50_defconfig
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v9 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Wed, Oct 14, 2015 at 9:32 PM, Arnd Bergmann  wrote:
> On Wednesday 14 October 2015 18:01:46 Ley Foon Tan wrote:
>> On Wed, Oct 14, 2015 at 5:36 PM, Arnd Bergmann  wrote:
>> > On Wednesday 14 October 2015 17:28:45 Ley Foon Tan wrote:
>> >> On Wed, Oct 14, 2015 at 5:09 PM, Arnd Bergmann  wrote:
>> >
>> > Could we perhaps have a helper function that lets us register
>> > fixups dynamically?
>> >
>> >> The linker script keeps all pci fixup callbacks in pci fixup regions
>> >> during kernel compile time. So, it needs to be builtin module. Do you
>> >> know any way we can update those fixup regions?
>> >
>> > The only method I'm aware of at the moment is move the fixups to
>> > drivers/pci/quirks.c and enclose them in an #ifdef if you want them
>> > to not appear in kernels that don't support your SoC.
>> By looking at the drivers/pci/quirks.c, it looks like it is mainly for
>> the pci endpoint devices.
>> Fixups for host controller are in the driver itself.
>>
>
> But if it's for the host itself, there are usually other ways to
> do this without needing a fixup: you already have the device structure
> present in the driver, so you should just be able to modify it there.
Thanks for your suggestion. You are right, I have tested this can work as well.
So, I can remove those 2 PCI_FIXUP* in the driver.
>
>
> I'm looking at the code in your fixups now:
>
> +static void altera_pcie_retrain(struct pci_dev *dev)
> +{
> +   u16 linkcap, linkstat;
> +
> +   /*
> +* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
> +* current speed is 2.5 GB/s.
> +*/
> +   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
> +
> +   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
> +   return;
> +
> +   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
> +   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
> +   pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
> +PCI_EXP_LNKCTL_RL);
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID, 
> altera_pcie_retrain);
>
> This looks related to the code in pci_set_bus_speed(). What is
> missing from that code?
This fixup is different from pci_set_bus_speed(). This fixup is to set
the retrain bit in the LNKCTL register if the host can support higher
speed than current speed, this is required by our hardware. But,
pci_set_bus_speed() is just read the LNKCAP and LNKSTA registers and
store in data structure.

>
> +static void altera_pcie_fixup_res(struct pci_dev *dev)
> +{
> +   /*
> +* Prevent enumeration of root port.
> +*/
> +   if (!dev->bus->parent && dev->devfn == 0) {
> +   int i;
> +
> +   for (i = 0; i < PCI_NUM_RESOURCES; i++) {
> +   dev->resource[i].start = 0;
> +   dev->resource[i].end   = 0;
> +   dev->resource[i].flags   = 0;
> +   }
> +   }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID,
> +altera_pcie_fixup_res);
>
> This seems really odd, too. Why is this needed?
> I think I've seen similar code in other host drivers, so
> it might be time to teach the PCI core about this kind of
> device.
Yes, some host drivers have similar code as well. Some host controller
have the BAR configuration enabled, but it doesn't fit to kernel
resources. Example the BAR is 64-bit, but the processor is 32-bit. It
will fail at the host driver probing stage.

pci :00:00.0: BAR 0: [mem 0x-0x 64bit pref] has
bogus alignment

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v2 0/4] Add PCI support on nios2 architecture

[Ley Foon Tan]

On Thu, Oct 22, 2015 at 4:44 AM, Bjorn Helgaas  wrote:
> Hi Ley,
>
> I'm ignoring this series for now because of the build errors reported by
> the kbuild test robot.
>
> Bjorn
>
Hi Bjorn

I'm working on the newer version to fix the build errors.
Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v11 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b8577ad9..96b9fac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7958,6 +7958,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -8059,6 +8067,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v11 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..08e4462 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v11 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..09cd3bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..2951a6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs": TX slave port region
+   "Cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v11 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 11th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resovle the warning/error caught by kbuild test.

Hi Bjorn,
Do you have further comment on this patchset? Any chance this can go into 4.4?
Thanks.

This patchset is based on v4.3-rc6.

v10->v11 changes:
- altera-pcie: change altera_pcie_fixups to static function
- Kconfig: add depends on ARM || NIOS2 for PCIE_ALTERA

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238
[v6]: https://lkml.org/lkml/2015/9/1/177
[v7]: https://lkml.org/lkml/2015/9/20/193
[v8]: http://www.kernelhub.org/?msg=853553&p=2
[v9]: https://lkml.org/lkml/2015/10/13/998
[v10]: https://lkml.org/lkml/2015/10/19/139

Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  16 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 314 +++
 drivers/pci/host/pcie-altera.c | 579 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1007 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v11 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 314 +
 3 files changed, 323 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a67c9de..101208f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -153,4 +153,12 @@ config PCIE_ALTERA
  Say Y here if you want to enable PCIe controller support on Altera
  FPGA.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera FPGA.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..367b462
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,314 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, const u32 value,
+ const u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, const u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_data_get

[PATCH v11 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 579 +
 3 files changed, 588 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..a67c9de 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,12 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   tristate "Altera PCIe controller"
+   depends on ARM || NIOS2
+   select PCI_DOMAINS
+   help
+ Say Y here if you want to enable PCIe controller support on Altera
+ FPGA.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..3503d9c
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,579 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xf
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xf
+#define RP_LTSSM   0x3c64
+#define LTSSM_L0   0xf
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1d
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag, be)(((reqid) << 16) | (tag << 8) | (be))
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   500
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
+
+   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+   return;

[PATCH v11 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index be648eb..bd42530 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += local.h
 generic-y += local64.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v6 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Wed, Sep 2, 2015 at 12:33 AM, Lorenzo Pieralisi
 wrote:
>
> On Tue, Sep 01, 2015 at 11:30:05AM +0100, Ley Foon Tan wrote:
>
> [...]
>
> > +static void altera_pcie_retrain(struct pci_dev *dev)
> > +{
> > +   u16 linkcap, linkstat;
> > +
> > +   /*
> > +* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
> > +* current speed is 2.5 GB/s.
> > +*/
> > +   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
> > +
> > +   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
> > +   return;
> > +
> > +   pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
> > +   if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
> > +   pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
> > +PCI_EXP_LNKCTL_RL);
> > +}
> > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID, 
> > altera_pcie_retrain);
>
> This filtering is still arguable, since it unconditionally applies to
> all Altera PCI devices (I guess there are not any apart from this
> host controller).
This fixup is required for all Altera PCIe controller in all device families.
>
> > +
> > +static void altera_pcie_fixup_res(struct pci_dev *dev)
> > +{
> > +   /*
> > +* Prevent enumeration of root port.
> > +*/
> > +   if (!dev->bus->parent && dev->devfn == 0) {
> > +   int i;
> > +
> > +   for (i = 0; i < PCI_NUM_RESOURCES; i++) {
> > +   dev->resource[i].start = 0;
> > +   dev->resource[i].end   = 0;
> > +   dev->resource[i].flags   = 0;
> > +   }
> > +   }
> > +}
> > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ALTERA, PCI_ANY_ID,
> > +altera_pcie_fixup_res);
>
> Ditto, it is a quirk of your host controller, not a quirk for
> all Altera PCI devices.
Same here.

>
> > +static inline void cra_writel(struct altera_pcie *pcie, u32 value, u32 reg)
> > +{
> > +   writel_relaxed(value, pcie->cra_base + reg);
> > +}
> > +
> > +static inline u32 cra_readl(struct altera_pcie *pcie, u32 reg)
> > +{
> > +   return readl_relaxed(pcie->cra_base + reg);
> > +}
> > +
> > +static void tlp_read_rx(struct altera_pcie *pcie,
> > +   struct tlp_rp_regpair_t *tlp_rp_regdata)
> > +{
> > +   tlp_rp_regdata->ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
> > +   tlp_rp_regdata->reg0 = cra_readl(pcie, RP_RXCPL_REG0);
> > +   tlp_rp_regdata->reg1 = cra_readl(pcie, RP_RXCPL_REG1);
> > +}
> > +
> > +static void tlp_write_tx(struct altera_pcie *pcie,
> > +struct tlp_rp_regpair_t *tlp_rp_regdata)
> > +{
> > +   cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
> > +   cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
> > +   cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
> > +}
> > +
> > +static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
> > +{
> > +   return !!(cra_readl(pcie, RP_LTSSM) & LTSSM_L0);
> > +}
> > +
> > +static bool altera_pcie_valid_config(struct altera_pcie *pcie,
> > +struct pci_bus *bus, int dev)
> > +{
> > +   /* If there is no link, then there is no device */
> > +   if (bus->number != pcie->root_bus_nr) {
> > +   if (!altera_pcie_link_is_up(pcie))
> > +   return false;
> > +   }
>
> Can you explain to pls me why you have to check this for every config
> transaction ? Isn't it something that can prevent probing the
> host controller altogether ?
In our PCIe hardware spec, it stated that software should check the
link status before issuing a configuration request to downstream
ports.
BTW, other pci controllers have similar implementation as well, eg: dw
pci, mvebu pci.
>
> > +
> > +   /* access only one slot on each root port */
> > +   if (bus->number == pcie->root_bus_nr && dev > 0)
> > +   return false;
> > +
> > +   /*
> > +* Do not read more than one device on the bus directly attached
> > +* to RC.
>
> You should also explain why.
Okay.

>
> > +*/
> > +   if (bus->primary == pcie->root_bus_nr && dev > 0)
> > +   return false;
>

[PATCH v10 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..08e4462 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v10 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index be648eb..bd42530 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += local.h
 generic-y += local64.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v10 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b8577ad9..96b9fac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7958,6 +7958,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -8059,6 +8067,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v10 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..09cd3bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..2951a6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs": TX slave port region
+   "Cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v10 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 313 +
 3 files changed, 322 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index a9f6db4..35eba16 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -152,4 +152,12 @@ config PCIE_ALTERA
  Say Y here if you want to enable PCIe controller support on Altera
  FPGA.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera FPGA.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..1d8a1b6
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, const u32 value,
+ const u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, const u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_

[PATCH v10 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   7 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 581 +
 3 files changed, 589 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..a9f6db4 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,11 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   tristate "Altera PCIe controller"
+   select PCI_DOMAINS
+   help
+ Say Y here if you want to enable PCIe controller support on Altera
+ FPGA.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..b5e7bc2
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,581 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define A2P_ADDR_MAP_LO0   0x1000
+#define A2P_ADDR_MAP_HI0   0x1004
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xF
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xF
+#define RP_LTSSM   0x3C64
+#define LTSSM_L0   0xF
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1D
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag, be)(((reqid) << 16) | (tag << 8) | (be))
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   500
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
+
+   if ((linkcap & PCI_EXP_

[PATCH v10 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 10th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resolve comments from Arnd to support loadable module and implement
fixups within driver instead of calling *PCI_FIXUP* macro. Only PATCH 3/6 has
changes, others unchanged.

This patchset is based on v4.3-rc6.

v9->v10 changes:
- altera-pcie: support loadable module
- altera-pcie: implement fixups within driver instead of calling *PCI_FIXUP* 
macro
- altera-pcie: remove altera_pcie_remove and add suppress_bind_attrs = true

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238
[v6]: https://lkml.org/lkml/2015/9/1/177
[v7]: https://lkml.org/lkml/2015/9/20/193
[v8]: http://www.kernelhub.org/?msg=853553&p=2
[v9]: https://lkml.org/lkml/2015/10/13/998

Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  15 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 313 +++
 drivers/pci/host/pcie-altera.c | 581 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1007 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v11 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

On Fri, Oct 23, 2015 at 6:13 AM, Bjorn Helgaas  wrote:
> On Thu, Oct 22, 2015 at 05:27:27PM +0800, Ley Foon Tan wrote:
>> Signed-off-by: Ley Foon Tan 
>> ---
>>  include/linux/pci_ids.h | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
>> index d9ba49c..08e4462 100644
>> --- a/include/linux/pci_ids.h
>> +++ b/include/linux/pci_ids.h
>> @@ -1550,6 +1550,8 @@
>>  #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
>>  #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
>>
>> +#define PCI_VENDOR_ID_ALTERA 0x1172
>> +
>
> This doesn't seem to be used anywhere, so I'll drop this patch.
Okay.

Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v11 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

On Fri, Oct 23, 2015 at 1:31 PM, Bjorn Helgaas  wrote:
> Hi Ley,
>
> On Thu, Oct 22, 2015 at 05:27:28PM +0800, Ley Foon Tan wrote:
>> This patch adds the Altera PCIe host controller driver.
>
>> +static void altera_pcie_fixups(struct pci_bus *bus)
>> +{
>> + struct pci_dev *dev;
>> +
>> + list_for_each_entry(dev, &bus->devices, bus_list) {
>> + altera_pcie_retrain(dev);
>> + altera_pcie_fixup_res(dev);
>> + }
>> +}
>
> I'd really like to avoid this particular fixup because it's done
> between pci_scan_root_bus() and pci_assign_unassigned_bus_resources()
> and pci_bus_add_devices().  That path is almost 100% arch-independent,
> and someday we should be able to pull all that out into one PCI core
> interface.
>
> You might be able to do the link retrain fixup as a header quirk.
> That's not really ideal either, but I don't think we have a good
> mechanism of inserting per-host bridge hooks in the enumeration path.
> There are some pcibios_*() hooks, but those are per-arch, not per-host
> bridge, so they're not really what you want here.
Okay, will change the retrain fixup to use *PCI_FIXUP* macro.
By doing this, we need [PATCH v11 2/6] pci: add Altera PCI vendor ID patch.

>
> I think other host drivers have handled the "prevent enumeration of
> root complex resources" problem by adding a similar check in the
> config accessors.
Okay, will handle this in config accessors.

>
>> +static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
>> +  int where, int size, u32 value)
>
> This needs a comment to the effect that this hardware can only generate
> 32-bit config accesses.  We also need a printk in the probe routine so
> there's a note in dmesg so we have a clue that RW1C bits in config space
> may be corrupted.
I have checked the PCIe/TLP spec, we can use the "First BE" (byte
enable) field in TLP packet to write
specific bytes only. And I have update driver to support this "First
BE" feature.
So, we don't have corrupted RW1C bit issue now.

>
>> +{
>> + struct altera_pcie *pcie = bus->sysdata;
>> + u32 data32;
>> + u32 shift = 8 * (where & 3);
>> + u8 byte_en;
>> +
>> + if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
>> + return PCIBIOS_DEVICE_NOT_FOUND;
>> +
>> + switch (size) {
>> + case 1:
>> + data32 = (value & 0xff) << shift;
>> + byte_en = 1 << (where & 3);
>> + break;
>> + case 2:
>> + data32 = (value & 0x) << shift;
>> + byte_en = 3 << (where & 3);
>> + break;
>> + default:
>> + data32 = value;
>> + byte_en = 0xf;
>> + break;
>> + }
>> +
>> + return tlp_cfg_dword_write(pcie, bus->number, devfn,
>> + (where & ~DWORD_MASK), byte_en, data32);
>> +}
>
>> +static void altera_pcie_isr(struct irq_desc *desc)
>> +{
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct altera_pcie *pcie;
>> + unsigned long status;
>> + u32 bit;
>> + u32 virq;
>> +
>> + chained_irq_enter(chip, desc);
>> + pcie = irq_desc_get_handler_data(desc);
>> +
>> + while ((status = cra_readl(pcie, P2A_INT_STATUS)
>> + & P2A_INT_STS_ALL) != 0) {
>> + for_each_set_bit(bit, &status, INTX_NUM) {
>> + /* clear interrupts */
>> + cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
>> +
>> + virq = irq_find_mapping(pcie->irq_domain, bit + 1);
>> + if (virq)
>> + generic_handle_irq(virq);
>> + else
>> + dev_err(&pcie->pdev->dev, "unexpected IRQ\n");
>
> Include the bit number here.  A printk string with no % substitutions
> is rarely as useful as it could be.
Okay.
>
>> ...
>> + bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, 
>> &altera_pcie_ops,
>> + pcie, &pcie->resources);
>> + if (!bus)
>> + return -ENOMEM;
>> +
>> + altera_pcie_fixups(bus);
>> + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
>> + pci_assign_unassigned_bus_resources(bus);
>> + pci_bus_add_devices(bus);
>> +
>> + /* Configure PCI Express setting. */
>> + list_for_each_entry(child, &bus->children, node)
>> + pcie_bus_configure_settings(child);
>
> This loop should be before pci_bus_add_devices().  When we call
> pci_bus_add_devices(), drivers may claim devices immediately, and the
> PCI core shouldn't be changing device configuration while a driver
> owns the device.
Okay, will move this before pci_bus_add_devices().

Thanks.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v12 1/6] arm: add msi.h to Kbuild

[Ley Foon Tan]

Include asm-generic/msi.h to support CONFIG_GENERIC_MSI_IRQ_DOMAIN.
This to fix compilation error:
"include/linux/msi.h:123:21: fatal error: asm/msi.h:
No such file or directory"

Signed-off-by: Ley Foon Tan 
---
 arch/arm/include/asm/Kbuild | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index be648eb..bd42530 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -14,6 +14,7 @@ generic-y += local.h
 generic-y += local64.h
 generic-y += mm-arch-hooks.h
 generic-y += msgbuf.h
+generic-y += msi.h
 generic-y += param.h
 generic-y += parport.h
 generic-y += poll.h
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v12 3/6] pci:host: Add Altera PCIe host controller driver

[Ley Foon Tan]

This patch adds the Altera PCIe host controller driver.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera.c | 580 +
 3 files changed, 589 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..e569a64 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -145,4 +145,12 @@ config PCIE_IPROC_BCMA
  Say Y here if you want to use the Broadcom iProc PCIe controller
  through the BCMA bus interface
 
+config PCIE_ALTERA
+   bool "Altera PCIe controller"
+   depends on ARM || NIOS2
+   select PCI_DOMAINS
+   help
+ Say Y here if you want to enable PCIe controller support on Altera
+ FPGA.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 140d66f..6954f76 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
new file mode 100644
index 000..d03158d
--- /dev/null
+++ b/drivers/pci/host/pcie-altera.c
@@ -0,0 +1,580 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define RP_TX_REG0 0x2000
+#define RP_TX_REG1 0x2004
+#define RP_TX_CNTRL0x2008
+#define RP_TX_EOP  0x2
+#define RP_TX_SOP  0x1
+#define RP_RXCPL_STATUS0x2010
+#define RP_RXCPL_EOP   0x2
+#define RP_RXCPL_SOP   0x1
+#define RP_RXCPL_REG0  0x2014
+#define RP_RXCPL_REG1  0x2018
+#define P2A_INT_STATUS 0x3060
+#define P2A_INT_STS_ALL0xf
+#define P2A_INT_ENABLE 0x3070
+#define P2A_INT_ENA_ALL0xf
+#define RP_LTSSM   0x3c64
+#define LTSSM_L0   0xf
+
+/* TLP configuration type 0 and 1 */
+#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
+#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
+#define TLP_FMTTYPE_CFGRD1 0x05/* Configuration Read Type 1 */
+#define TLP_FMTTYPE_CFGWR1 0x45/* Configuration Write Type 1 */
+#define TLP_PAYLOAD_SIZE   0x01
+#define TLP_READ_TAG   0x1d
+#define TLP_WRITE_TAG  0x10
+#define TLP_CFG_DW0(fmttype)   (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
+#define TLP_CFG_DW1(reqid, tag, be)(((reqid) << 16) | (tag << 8) | (be))
+#define TLP_CFG_DW2(bus, devfn, offset)\
+   (((bus) << 24) | ((devfn) << 16) | (offset))
+#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
+#define TLP_HDR_SIZE   3
+#define TLP_LOOP   500
+
+#define INTX_NUM   4
+
+#define DWORD_MASK 3
+
+struct altera_pcie {
+   struct platform_device  *pdev;
+   void __iomem*cra_base;
+   int irq;
+   u8  root_bus_nr;
+   struct irq_domain   *irq_domain;
+   struct resource bus_range;
+   struct list_headresources;
+};
+
+struct tlp_rp_regpair_t {
+   u32 ctrl;
+   u32 reg0;
+   u32 reg1;
+};
+
+static void altera_pcie_retrain(struct pci_dev *dev)
+{
+   u16 linkcap, linkstat;
+
+   /*
+* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
+* current speed is 2.5 GB/s.
+*/
+   pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
+
+   if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
+   return;

[PATCH v12 0/6] Altera PCIe host controller driver with MSI support

[Ley Foon Tan]

This is the 12th version of patch set to add support for Altera PCIe host
controller with MSI feature on Altera FPGA device families. This patchset
mainly resovle the comments from Bjorn.


This patchset is based on v4.3-rc6.

v11->v12 changes:
- pcie-altera: use DECLARE_PCI_FIXUP_EARLY for pcie retrain fixup
- pcie-altera: move pcie_bus_configure_settings before pci_bus_add_devices
- pcie-altera: add %d for irq bit in dev_err()
- pcie-altera: prevent enumeration of root complex resources in config accessors
- Documentation: add Acked-by from Rob Herring

History:
---
[v1]: https://lkml.org/lkml/2015/7/28/395
[v2]: https://lkml.org/lkml/2015/7/31/267
[v3]: http://www.kernelhub.org/?msg=811940&p=2
[v4]: https://lkml.org/lkml/2015/8/17/141
[v5]: https://lkml.org/lkml/2015/8/25/238
[v6]: https://lkml.org/lkml/2015/9/1/177
[v7]: https://lkml.org/lkml/2015/9/20/193
[v8]: http://www.kernelhub.org/?msg=853553&p=2
[v9]: https://lkml.org/lkml/2015/10/13/998
[v10]: https://lkml.org/lkml/2015/10/19/139
[v11]: https://lkml.org/lkml/2015/10/22/206


Ley Foon Tan (6):
  arm: add msi.h to Kbuild
  pci: add Altera PCI vendor ID
  pci:host: Add Altera PCIe host controller driver
  pci: altera: Add Altera PCIe MSI driver
  Documentation: dt-bindings: pci: altera pcie device tree binding
  MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

 .../devicetree/bindings/pci/altera-pcie-msi.txt|  28 +
 .../devicetree/bindings/pci/altera-pcie.txt|  49 ++
 MAINTAINERS|  16 +
 arch/arm/include/asm/Kbuild|   1 +
 drivers/pci/host/Kconfig   |  16 +
 drivers/pci/host/Makefile  |   2 +
 drivers/pci/host/pcie-altera-msi.c | 314 +++
 drivers/pci/host/pcie-altera.c | 580 +
 include/linux/pci_ids.h|   2 +
 9 files changed, 1008 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 drivers/pci/host/pcie-altera-msi.c
 create mode 100644 drivers/pci/host/pcie-altera.c

-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v12 4/6] pci: altera: Add Altera PCIe MSI driver

[Ley Foon Tan]

This patch adds Altera PCIe MSI driver. This soft IP supports configurable
number of vectors, which is a dts parameter.

Signed-off-by: Ley Foon Tan 
Reviewed-by: Marc Zyngier 
---
 drivers/pci/host/Kconfig   |   8 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-altera-msi.c | 314 +
 3 files changed, 323 insertions(+)
 create mode 100644 drivers/pci/host/pcie-altera-msi.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index e569a64..b06c2d9 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -153,4 +153,12 @@ config PCIE_ALTERA
  Say Y here if you want to enable PCIe controller support on Altera
  FPGA.
 
+config PCIE_ALTERA_MSI
+   bool "Altera PCIe MSI feature"
+   depends on PCI_MSI
+   select PCI_MSI_IRQ_DOMAIN
+   help
+ Say Y here if you want PCIe MSI support for the Altera FPGA.
+ This MSI driver supports Altera MSI to GIC controller IP.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 6954f76..6c4913d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
 obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
 obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
+obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
diff --git a/drivers/pci/host/pcie-altera-msi.c 
b/drivers/pci/host/pcie-altera-msi.c
new file mode 100644
index 000..367b462
--- /dev/null
+++ b/drivers/pci/host/pcie-altera-msi.c
@@ -0,0 +1,314 @@
+/*
+ * Copyright Altera Corporation (C) 2013-2015. All rights reserved
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MSI_STATUS 0x0
+#define MSI_ERROR  0x4
+#define MSI_INTMASK0x8
+
+#define MAX_MSI_VECTORS32
+
+struct altera_msi {
+   DECLARE_BITMAP(used, MAX_MSI_VECTORS);
+   struct mutexlock;   /* proctect used variable */
+   struct platform_device  *pdev;
+   struct irq_domain   *msi_domain;
+   struct irq_domain   *inner_domain;
+   void __iomem*csr_base;
+   void __iomem*vector_base;
+   phys_addr_t vector_phy;
+   u32 num_of_vectors;
+   int irq;
+};
+
+static inline void msi_writel(struct altera_msi *msi, const u32 value,
+ const u32 reg)
+{
+   writel_relaxed(value, msi->csr_base + reg);
+}
+
+static inline u32 msi_readl(struct altera_msi *msi, const u32 reg)
+{
+   return readl_relaxed(msi->csr_base + reg);
+}
+
+static void altera_msi_isr(struct irq_desc *desc)
+{
+   struct irq_chip *chip = irq_desc_get_chip(desc);
+   struct altera_msi *msi;
+   unsigned long status;
+   u32 num_of_vectors;
+   u32 bit;
+   u32 virq;
+
+   chained_irq_enter(chip, desc);
+   msi = irq_desc_get_handler_data(desc);
+   num_of_vectors = msi->num_of_vectors;
+
+   while ((status = msi_readl(msi, MSI_STATUS)) != 0) {
+   for_each_set_bit(bit, &status, msi->num_of_vectors) {
+   /* Dummy read from vector to clear the interrupt */
+   readl_relaxed(msi->vector_base + (bit * sizeof(u32)));
+
+   virq = irq_find_mapping(msi->inner_domain, bit);
+   if (virq)
+   generic_handle_irq(virq);
+   else
+   dev_err(&msi->pdev->dev, "unexpected MSI\n");
+   }
+   }
+
+   chained_irq_exit(chip, desc);
+}
+
+static struct irq_chip altera_msi_irq_chip = {
+   .name = "Altera PCIe MSI",
+   .irq_mask = pci_msi_mask_irq,
+   .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info altera_msi_domain_info = {
+   .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+MSI_FLAG_PCI_MSIX),
+   .chip   = &altera_msi_irq_chip,
+};
+
+static void altera_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+   struct altera_msi *msi = irq_data_get

[PATCH v12 6/6] MAINTAINERS: Add Altera PCIe and MSI drivers maintainer

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 MAINTAINERS | 16 
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b8577ad9..96b9fac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7958,6 +7958,14 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI DRIVER FOR ALTERA PCIE IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie.txt
+F: drivers/pci/host/pcie-altera.c
+
 PCI DRIVER FOR ARM VERSATILE PLATFORM
 M: Rob Herring 
 L: linux-...@vger.kernel.org
@@ -8059,6 +8067,14 @@ L:   linux-...@vger.kernel.org
 S: Maintained
 F: drivers/pci/host/*spear*
 
+PCI MSI DRIVER FOR ALTERA MSI IP
+M: Ley Foon Tan 
+L: r...@lists.rocketboards.org (moderated for non-subscribers)
+L: linux-...@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
+F: drivers/pci/host/pcie-altera-msi.c
+
 PCI MSI DRIVER FOR APPLIEDMICRO XGENE
 M: Duc Dang 
 L: linux-...@vger.kernel.org
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v12 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

This patch adds the bindings for Altera PCIe host controller driver and
Altera PCIe MSI driver.

Signed-off-by: Ley Foon Tan 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/pci/altera-pcie-msi.txt| 28 +
 .../devicetree/bindings/pci/altera-pcie.txt| 49 ++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
new file mode 100644
index 000..09cd3bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
@@ -0,0 +1,28 @@
+* Altera PCIe MSI controller
+
+Required properties:
+- compatible:  should contain "altr,msi-1.0"
+- reg: specifies the physical base address of the controller and
+   the length of the memory mapped region.
+- reg-names:   must include the following entries:
+   "csr": CSR registers
+   "vector_slave": vectors slave port region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt
+   controller. The format of the interrupt specifier depends on the
+   parent interrupt controller.
+- num-vectors: number of vectors, range 1 to 32.
+- msi-controller:  indicates that this is MSI controller node
+
+
+Example
+msi0: msi@0xFF20 {
+   compatible = "altr,msi-1.0";
+   reg = <0xFF20 0x0010
+   0xFF200010 0x0080>;
+   reg-names = "csr", "vector_slave";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 42 4>;
+   msi-controller;
+   num-vectors = <32>;
+};
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
b/Documentation/devicetree/bindings/pci/altera-pcie.txt
new file mode 100644
index 000..2951a6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -0,0 +1,49 @@
+* Altera PCIe controller
+
+Required properties:
+- compatible : should contain "altr,pcie-root-port-1.0"
+- reg: a list of physical base address and length for TXS and CRA.
+- reg-names:   must include the following entries:
+   "Txs": TX slave port region
+   "Cra": Control register access region
+- interrupt-parent:interrupt source phandle.
+- interrupts:  specifies the interrupt source of the parent interrupt 
controller.
+   The format of the interrupt specifier depends on the parent 
interrupt
+   controller.
+- device_type: must be "pci"
+- #address-cells:  set to <3>
+- #size-cells: set to <2>
+- #interrupt-cells:set to <1>
+- ranges:  describes the translation of addresses for root ports 
and standard
+   PCI regions.
+- interrupt-map-mask and interrupt-map: standard PCI properties to define the
+   mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- msi-parent:  Link to the hardware entity that serves as the MSI controller 
for this PCIe
+   controller.
+- bus-range:   PCI bus numbers covered
+
+Example
+   pcie_0: pcie@0xc {
+   compatible = "altr,pcie-root-port-1.0";
+   reg = <0xc000 0x2000>,
+   <0xff22 0x4000>;
+   reg-names = "Txs", "Cra";
+   interrupt-parent = <&hps_0_arm_gic_0>;
+   interrupts = <0 40 4>;
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   bus-range = <0x0 0xFF>;
+   device_type = "pci";
+   msi-parent = <&msi_to_gic_gen_0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1 &pcie_0 1>,
+   <0 0 0 2 &pcie_0 2>,
+   <0 0 0 3 &pcie_0 3>,
+   <0 0 0 4 &pcie_0 4>;
+   ranges = <0x8200 0x 0x 0xc000 
0x 0x1000
+   0x8200 0x 0x1000 0xd000 
0x 0x1000>;
+   };
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH v12 2/6] pci: add Altera PCI vendor ID

[Ley Foon Tan]

Signed-off-by: Ley Foon Tan 
---
 include/linux/pci_ids.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d9ba49c..08e4462 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1550,6 +1550,8 @@
 #define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
 #define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
 
+#define PCI_VENDOR_ID_ALTERA   0x1172
+
 #define PCI_VENDOR_ID_SBE  0x1176
 #define PCI_DEVICE_ID_SBE_WANXL100 0x0301
 #define PCI_DEVICE_ID_SBE_WANXL200 0x0302
-- 
1.8.2.1

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH] nios2: Fix unused variable warning

[Ley Foon Tan]

On Tue, Sep 22, 2015 at 11:22 PM, Tobias Klauser  wrote:
> On 2015-09-19 at 06:40:51 +0200, Marek Vasut  wrote:
>> Fix the following compiler splat by adding __maybe_unused annotation
>> to the variable. Using this particular annotation has the least ugly
>> impact on the code compared to using ifdeffery.
>>
>> arch/nios2/kernel/setup.c: In function 'nios2_boot_init':
>> arch/nios2/kernel/setup.c:107:7: warning: unused variable 'cmdline_passed' 
>> [-Wunused-variable]
>>   char cmdline_passed[COMMAND_LINE_SIZE] = { 0, };
>>^
>>
>> Signed-off-by: Marek Vasut 
>
> Reviewed-by: Tobias Klauser 
> --
Acked-by: Ley Foon Tan 
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH] nios2: Switch to generic __xchg()

[Ley Foon Tan]

On Sat, Sep 19, 2015 at 12:41 PM, Marek Vasut  wrote:
> The generic __xchg() implementation present in asm-generic/cmpxchg.h
> is correct on nios2 and even generates the same code. Switch to this
> generic implementation to trim down the amount of ad-hoc copies of
> the code.
>
> Signed-off-by: Marek Vasut 

Acked-by: Ley Foon Tan 
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH] asm-generic: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations

[Ley Foon Tan]

On Sat, Sep 19, 2015 at 12:42 PM, Marek Vasut  wrote:
> This change is similar to e001bbae7147b111fe1aa42beaf835635f3c016e
> ARM: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations
>
> A recent change in kernel/acct.c added a new warning for many
> configurations using generic __xchg() implementation:
>
> In file included from ./arch/nios2/include/asm/cmpxchg.h:12:0,
>  from include/asm-generic/atomic.h:18,
>  from arch/nios2/include/generated/asm/atomic.h:1,
>  from include/linux/atomic.h:4,
>  from include/linux/spinlock.h:406,
>  from include/linux/mmzone.h:7,
>  from include/linux/gfp.h:5,
>  from include/linux/mm.h:9,
>  from kernel/acct.c:46:
> kernel/acct.c: In function 'acct_pin_kill':
> include/asm-generic/cmpxchg.h:94:3: warning: value computed is not used 
> [-Wunused-value]
>   ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
>^
> include/asm-generic/cmpxchg.h:102:28: note: in expansion of macro 
> 'cmpxchg_local'
>  #define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n))
> ^
> kernel/acct.c:177:2: note: in expansion of macro 'cmpxchg'
>   cmpxchg(&acct->ns->bacct, pin, NULL);
>   ^
>
> The code is in fact correct, it's just a cmpxchg() call that
> intentionally ignores the result, and no other code does that.  The
> warning does not show up on x86 because of the way that its cmpxchg()
> macro is written. This changes the asm-ggeneric implementation to use
> a similar construct with a compound expression instead of a typecast,
> which causes the compiler to not complain about an unused result.
>
> Fix the other macros in this file in a similar way, and place them
> just below their function implementations.
>
> Signed-off-by: Marek Vasut 
> Cc: Russell King 
> ---
Tested with arch/nios2.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v7 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

On Tue, Sep 29, 2015 at 1:31 AM, Rob Herring  wrote:
> On Mon, Sep 28, 2015 at 12:38 AM, Ley Foon Tan  wrote:
>> On Sat, Sep 26, 2015 at 11:55 AM, Rob Herring  wrote:
>>>
>>> On 09/20/2015 09:13 PM, Ley Foon Tan wrote:
>>> > This patch adds the bindings for Altera PCIe host controller driver and
>>> > Altera PCIe MSI driver.
>
> [...]
>
>>> > + num-vectors = <32>;
>>> > +};
>>> > diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt 
>>> > b/Documentation/devicetree/bindings/pci/altera-pcie.txt
>>> > new file mode 100644
>>> > index 000..4440db1
>>> > --- /dev/null
>>> > +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
>>> > @@ -0,0 +1,49 @@
>>> > +* Altera PCIe controller
>>> > +
>>> > +Required properties:
>>> > +- compatible :   should contain "altr,pcie-root-port-1.0"
>>> > +- reg:   a list of physical base address and length for TXS 
>>> > and CRA.
>>> > +- reg-names: must include the following entries:
>>> > + "Txs" or "txs": TX slave port region
>>> > + "Cra" or "cra": Control register access region
>>>
>>> Why both cases? Can we please just have one (or none is better IMO).
>> The PCIe IP on different device families use different register names.
>> And our device tree generator will auto generate the register names
>> based on the hardware description name. Too bad we can't change the
>> hardware description names now.
>
> Okay, your problem to maintain. Hopefully the driver just goes by index then.
Okay, we will fix our generator tool to standardize one reg-name case
and driver  just use one reg-name case as well.
>
> Strictly speaking, if you have undocumented bindings downstream that
> is your problem and we don't have to accept them as-is upstream. I'm
> not going to worry about that here.
>
>>> txs contains the config space?
>> It is not the config space, but a memory slave port.
>
> Then where is the config space? It should not be part of "ranges" is
> all I care about.
The config space is not part of "ranges". Our IP uses TLP packet to
access config space.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v7 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

On Tue, Sep 29, 2015 at 3:38 AM, Arnd Bergmann  wrote:
> On Monday 28 September 2015 12:31:36 Rob Herring wrote:
>> >> > +
>> >> > +Required properties:
>> >> > +- compatible :   should contain "altr,pcie-root-port-1.0"
>> >> > +- reg:   a list of physical base address and length for 
>> >> > TXS and CRA.
>> >> > +- reg-names: must include the following entries:
>> >> > + "Txs" or "txs": TX slave port region
>> >> > + "Cra" or "cra": Control register access region
>> >>
>> >> Why both cases? Can we please just have one (or none is better IMO).
>> > The PCIe IP on different device families use different register names.
>> > And our device tree generator will auto generate the register names
>> > based on the hardware description name. Too bad we can't change the
>> > hardware description names now.
>>
>> Okay, your problem to maintain. Hopefully the driver just goes by index then.
>>
>> Strictly speaking, if you have undocumented bindings downstream that
>> is your problem and we don't have to accept them as-is upstream. I'm
>> not going to worry about that here.
>
> Are they always in the same order? If you don't mandate any names for the
> registers in the binding but just use them by index, we can keep that
> bit of ugliness out of the binding and the driver and still be compatible
> with all the devices.
Too bad the order might change in future devices. We will fix the
tool, so only have one reg-name case.

Regards
Ley Foon
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v7 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

[Ley Foon Tan]

On Sat, Oct 3, 2015 at 5:56 AM, Arnd Bergmann  wrote:
> On Friday 02 October 2015 15:53:44 Ley Foon Tan wrote:
>> > Strictly speaking, if you have undocumented bindings downstream that
>> > is your problem and we don't have to accept them as-is upstream. I'm
>> > not going to worry about that here.
>> >
>> >>> txs contains the config space?
>> >> It is not the config space, but a memory slave port.
>> >
>> > Then where is the config space? It should not be part of "ranges" is
>> > all I care about.
>> The config space is not part of "ranges". Our IP uses TLP packet to
>> access config space.
>>
>
> It took me a bit to figure out what you mean here. To save others
> from reading the source, here is what I found:
>
> * The config space is accessed indirectly through registers from the
>   "cra" register range, which is the right approach according to the
>   point that Rob made.
You are right.

> * hardware-wise this basically looks like bit-banged PCIe, which is
>   both awesome and scary ;-)
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH v2] PCI: controller: Move PCI_DOMAINS selection to arch Kconfig

[Ley Foon Tan]

On Thu, 2018-06-21 at 22:08 -0700, Scott Branden wrote:
> 
> 
> On 18-06-21 09:54 AM, Lorenzo Pieralisi wrote:
> > 
> > 
> > On Wed, Jun 20, 2018 at 10:07:33AM +0200, Jan Kiszka wrote:
> > > 
> > > 
> > > On 2018-06-19 13:21, Lorenzo Pieralisi wrote:
> > > > 
> > > > 
> > > > Commit 51bc085d6454 ("PCI: Improve host drivers compile test
> > > > coverage")
> > > > added configuration options to allow PCI host controller
> > > > drivers to be
> > > > compile tested on all architectures.
> > > > 
> > > > Some host controller drivers (eg PCIE_ALTERA) config entries
> > > > select
> > > > the PCI_DOMAINS config option to enable PCI domains management
> > > > in
> > > > the kernel. Now that host controller drivers can be compiled on
> > > > all architectures, this triggers build regressions on arches
> > > > that
> > > > do not implement the PCI_DOMAINS required API (ie
> > > > pci_domain_nr()):
> > > > 
> > > > drivers/ata/pata_ali.c: In function 'ali_init_chipset':
> > > > drivers/ata/pata_ali.c:469:38: error:
> > > >  implicit declaration of function 'pci_domain_nr';
> > > >    did you mean
> > > > 'pci_iomap_wc'?
> > > > 
> > > > Furthemore, some software configurations (ie Jailhouse) require
> > > > a
> > > > PCI_DOMAINS enabled kernel to configure multiple host
> > > > controllers
> > > > without having an explicit dependency on the ARM platform on
> > > > which
> > > > they run.
> > > > 
> > > > Make PCI_DOMAINS a visible configuration option on ARM so that
> > > > software
> > > > configurations that need it can manually select it and move the
> > > > PCI_DOMAINS selection from PCI controllers configuration file
> > > > to ARM
> > > > sub-arch config entries that currently require it, fixing the
> > > > issue.
> > > > 
> > > > Fixes: 51bc085d6454 ("PCI: Improve host drivers compile test
> > > > coverage")
> > > > Link: https://lkml.kernel.org/r/20180612170229.GA10141@roeck-us
> > > > .net
> > > > Reported-by: Guenter Roeck 
> > > > Signed-off-by: Lorenzo Pieralisi 
> > > > Cc: Scott Branden 
> > > > Cc: Will Deacon 
> > > > Cc: Bjorn Helgaas 
> > > > Cc: Rob Herring 
> > > > Cc: Russell King 
> > > > Cc: Jan Kiszka 
> > > > Cc: Guenter Roeck 
> > > > Cc: Ley Foon Tan 
> > > > ---
> > > > v1 -> v2
> > > > - Removed ARCH_VIRT PCI_DOMAINS selection
> > > > - Added PCI_DOMAINS visible config option
> > > > 
> > > > v1: https://marc.info/?l=linux-pci&m=152932092612352&w=2
> > > > 
> > > >   arch/arm/Kconfig   | 8 +++-
> > > >   arch/arm/mach-bcm/Kconfig  | 1 +
> > > >   arch/arm/mach-socfpga/Kconfig  | 1 +
> > > >   drivers/pci/controller/Kconfig | 3 ---
> > > >   4 files changed, 9 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 54eeb8d00bc6..843edfd000be 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -1245,8 +1245,14 @@ config PCI
> > > >   VESA. If you have PCI, say Y, otherwise N.
> > > > 
> > > >   config PCI_DOMAINS
> > > > -   bool
> > > > +   bool "Support for multiple PCI domains"
> > > > depends on PCI
> > > > +   help
> > > > + Enable PCI domains kernel management. Say Y if your
> > > > machine
> > > > + has a PCI bus hierarchy that requires more than one PCI
> > > > + domain (aka segment) to be correctly managed. Say N
> > > > otherwise.
> > > > +
> > > > + If you don't know what to do here, say N.
> > > > 
> > > >   config PCI_DOMAINS_GENERIC
> > > > def_bool PCI_DOMAINS
> > > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-
> > > > bcm/Kconfig
> > > > index c46a728df44e..25aac6ee2ab1 100644
> > > > --- a/arch/arm/mach-bcm/Kconfig
> > > > +++ b/arch/arm/mach

Re: [PATCH v4] MAINTAINERS: Add file patterns for nios2 device tree bindings

[Ley Foon Tan]

On Fri, 2018-06-22 at 12:08 +0200, Geert Uytterhoeven wrote:
> Submitters of device tree binding documentation may forget to CC
> the subsystem maintainer if this is missing.
> 
> Signed-off-by: Geert Uytterhoeven 
> ---
> v3:
>   - Update for next-20180622,
> 
> v2:
>   - No changes.
> 
> Impact on "scripts/get_maintainer.pl -f
> Documentation/devicetree/bindings/nios2/":
> 
> -Rob Herring  (maintainer:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE
> BINDINGS,commit_signer:2/2=100%,authored:1/2=50%)
> +Ley Foon Tan  (maintainer:NIOS2 ARCHITECTURE)
> +Rob Herring  (maintainer:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS)
>  Mark Rutland  (maintainer:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS)
> -Mathieu Malaterre 
> (commit_signer:1/2=50%,authored:1/2=50%)
> -Thierry Reding  (commit_signer:1/2=50%)
> +nios2-...@lists.rocketboards.org (moderated list:NIOS2 ARCHITECTURE)
>  devicet...@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS)
>  linux-kernel@vger.kernel.org (open list)
> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index baa4dc046daf9cdc..dd72b804b9b8bab3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10074,6 +10074,7 @@ M:  Ley Foon Tan 
>  L: nios2-...@lists.rocketboards.org (moderated for non-
> subscribers)
>  T: git
> git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git
>  S: Maintained
> +F: Documentation/devicetree/bindings/nios2/
>  F: arch/nios2/
> 
>  NOHZ, DYNTICKS SUPPORT
> --
> 2.17.1
> 
> 
Reviewed-by: Ley Foon Tan 

Re: [PATCH] nios2: Convert to using %pOFn instead of device_node.name

[Ley Foon Tan]

On Mon, 2018-08-27 at 20:52 -0500, Rob Herring wrote:
> In preparation to remove the node name pointer from struct
> device_node,
> convert printf users to use the %pOFn format specifier.
> 
> Cc: Ley Foon Tan 
> Cc: nios2-...@lists.rocketboards.org
> Signed-off-by: Rob Herring 
Acked-by: Ley Foon Tan 

> ---
>  arch/nios2/kernel/time.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/nios2/kernel/time.c b/arch/nios2/kernel/time.c
> index ab88b6dd4679..54467d0085a1 100644
> --- a/arch/nios2/kernel/time.c
> +++ b/arch/nios2/kernel/time.c
> @@ -214,12 +214,12 @@ static int __init
> nios2_timer_get_base_and_freq(struct device_node *np,
>  {
> *base = of_iomap(np, 0);
> if (!*base) {
> -   pr_crit("Unable to map reg for %s\n", np->name);
> +   pr_crit("Unable to map reg for %pOFn\n", np);
> return -ENXIO;
> }
> 
> if (of_property_read_u32(np, "clock-frequency", freq)) {
> -   pr_crit("Unable to get %s clock frequency\n", np-
> >name);
> +   pr_crit("Unable to get %pOFn clock frequency\n", np);
> return -EINVAL;
> }
> 
> --
> 2.17.1
> 
> 
> 
> 
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.

[GIT PULL] arch/nios2 update for v4.19-rc2

[Ley Foon Tan]

Hi Linus

There is one arch/nios2 update for v4.19-rc2.
Please consider pulling.

Regards
Ley Foon

The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:

  Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git 
tags/nios2-v4.19-rc2

for you to fetch changes up to c7c09dc187f0323ad40b5b6c57a6db673a386a7f:

  nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions 
(2018-08-27 09:47:20 +0800)


nios2 fix for v4.19-rc2

nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions


Tobias Klauser (1):
  nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions

 arch/nios2/Kconfig.debug | 9 -
 1 file changed, 9 deletions(-)

Re: [PATCH 3/3] nios2: switch to NO_BOOTMEM

[Ley Foon Tan]

On Wed, 2018-07-04 at 16:18 +0300, Mike Rapoport wrote:
> Remove bootmem bitmap initialization and replace reserve_bootmem()
> with
> memblock_reserve().
> 
> Signed-off-by: Mike Rapoport 
> ---
>  arch/nios2/Kconfig|  2 ++
>  arch/nios2/kernel/prom.c  |  7 ---
>  arch/nios2/kernel/setup.c | 37 +
>  3 files changed, 7 insertions(+), 39 deletions(-)
> 
> diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
> index 5db8fa1..661f7f9 100644
> --- a/arch/nios2/Kconfig
> +++ b/arch/nios2/Kconfig
> @@ -20,6 +20,8 @@ config NIOS2
> select USB_ARCH_HAS_HCD if USB_SUPPORT
> select CPU_NO_EFFICIENT_FFS
> select HAVE_MEMBLOCK
> +   select ARCH_DISCARD_MEMBLOCK
> +   select NO_BOOTMEM
> 
>  config GENERIC_CSUM
> def_bool y
> diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
> index ba96a49..a6d4f75 100644
> --- a/arch/nios2/kernel/prom.c
> +++ b/arch/nios2/kernel/prom.c
> @@ -32,13 +32,6 @@
> 
>  #include 
> 
> -int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
> phys_addr_t size,
> -bool nomap)
> -{
> -   reserve_bootmem(base, size, BOOTMEM_DEFAULT);
> -   return 0;
> -}
> -
>  void __init early_init_devtree(void *params)
>  {
> __be32 *dtb = (u32 *)__dtb_start;
> diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
> index 0946840..2d0011d 100644
> --- a/arch/nios2/kernel/setup.c
> +++ b/arch/nios2/kernel/setup.c
> @@ -144,10 +144,11 @@ asmlinkage void __init nios2_boot_init(unsigned
> r4, unsigned r5, unsigned r6,
> 
>  void __init setup_arch(char **cmdline_p)
>  {
> -   int bootmap_size;
> +   int dram_start;
> 
> console_verbose();
> 
> +   dram_start = memblock_start_of_DRAM();
> memory_size = memblock_phys_mem_size();
> memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
> memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE +
> memory_size;
> @@ -165,39 +166,11 @@ void __init setup_arch(char **cmdline_p)
> max_low_pfn = PFN_DOWN(memory_end);
> max_mapnr = max_low_pfn;
> 
> -   /*
> -* give all the memory to the bootmap allocator,  tell it to
> put the
> -* boot mem_map at the start of memory
> -*/
> -   pr_debug("init_bootmem_node(?,%#lx, %#x, %#lx)\n",
> -   min_low_pfn, PFN_DOWN(PHYS_OFFSET), max_low_pfn);
> -   bootmap_size = init_bootmem_node(NODE_DATA(0),
> -   min_low_pfn,
> PFN_DOWN(PHYS_OFFSET),
> -   max_low_pfn);
> -
> -   /*
> -* free the usable memory,  we have to make sure we do not
> free
> -* the bootmem bitmap so we then reserve it after freeing it
> :-)
> -*/
> -   pr_debug("free_bootmem(%#lx, %#lx)\n",
> -   memory_start, memory_end - memory_start);
> -   free_bootmem(memory_start, memory_end - memory_start);
> -
> -   /*
> -* Reserve the bootmem bitmap itself as well. We do this in
> two
> -* steps (first step was init_bootmem()) because this catches
> -* the (very unlikely) case of us accidentally initializing
> the
> -* bootmem allocator with an invalid RAM area.
> -*
> -* Arguments are start, size
> -*/
> -   pr_debug("reserve_bootmem(%#lx, %#x)\n", memory_start,
> bootmap_size);
> -   reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
> -
> +   memblock_reserve(dram_start, memory_start - dram_start);
>  #ifdef CONFIG_BLK_DEV_INITRD
> if (initrd_start) {
> -       reserve_bootmem(virt_to_phys((void *)initrd_start),
> -   initrd_end - initrd_start,
> BOOTMEM_DEFAULT);
> +   memblock_reserve(virt_to_phys((void *)initrd_start),
> +   initrd_end - initrd_start);
> }
>  #endif /* CONFIG_BLK_DEV_INITRD */
> 
> --
> 2.7.4

Acked-by: Ley Foon Tan 

Re: [PATCH 2/3] nios2: use generic early_init_dt_add_memory_arch

[Ley Foon Tan]

On Wed, 2018-07-04 at 16:18 +0300, Mike Rapoport wrote:
> All we have to do is to enable memblock, the generic FDT code will
> take
> care of the rest.
> 
> Signed-off-by: Mike Rapoport 
> ---
>  arch/nios2/Kconfig|  1 +
>  arch/nios2/kernel/prom.c  | 10 --
>  arch/nios2/kernel/setup.c |  2 ++
>  3 files changed, 3 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
> index 3d4ec88..5db8fa1 100644
> --- a/arch/nios2/Kconfig
> +++ b/arch/nios2/Kconfig
> @@ -19,6 +19,7 @@ config NIOS2
> select SPARSE_IRQ
> select USB_ARCH_HAS_HCD if USB_SUPPORT
> select CPU_NO_EFFICIENT_FFS
> +   select HAVE_MEMBLOCK
> 
>  config GENERIC_CSUM
> def_bool y
> diff --git a/arch/nios2/kernel/prom.c b/arch/nios2/kernel/prom.c
> index 8d7446a..ba96a49 100644
> --- a/arch/nios2/kernel/prom.c
> +++ b/arch/nios2/kernel/prom.c
> @@ -32,16 +32,6 @@
> 
>  #include 
> 
> -void __init early_init_dt_add_memory_arch(u64 base, u64 size)
> -{
> -   u64 kernel_start = (u64)virt_to_phys(_text);
> -
> -   if (!memory_size &&
> -   (kernel_start >= base) && (kernel_start < (base + size)))
> -   memory_size = size;
> -
> -}
> -
>  int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
> phys_addr_t size,
>  bool nomap)
>  {
> diff --git a/arch/nios2/kernel/setup.c b/arch/nios2/kernel/setup.c
> index 926a02b..0946840 100644
> --- a/arch/nios2/kernel/setup.c
> +++ b/arch/nios2/kernel/setup.c
> @@ -17,6 +17,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -147,6 +148,7 @@ void __init setup_arch(char **cmdline_p)
> 
> console_verbose();
> 
> +   memory_size = memblock_phys_mem_size();
> memory_start = PAGE_ALIGN((unsigned long)__pa(_end));
> memory_end = (unsigned long) CONFIG_NIOS2_MEM_BASE +
> memory_size;
> 
> --
Acked-by: Ley Foon Tan 

[GIT PULL] arch/nios2 update for v4.12

[Ley Foon Tan]

Hi Linus

Here is nios2 update for v4.12.

This including nios2 fixes/enhancements and adding nios2 R2 support.

Regards
Ley Foon


The following changes since commit 13e0988140374123bead1dd27c287354cb95108e:

  docs: complete bumping minimal GNU Make version to 3.81 (2017-05-06 18:49:09 
-0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git 
tags/nios2-v4.12-rc1

for you to fetch changes up to e118c3fec9c0d8d2a96462c4c035305dc952e402:

  nios2: remove custom early console implementation (2017-05-11 17:44:21 +0800)


nios2 update for v4.12-rc1

nios2: remove custom early console implementation
nios2: use generic strncpy_from_user() and strnlen_user()
nios2: Add CDX support
nios2: Add BMX support
nios2: Add NIOS2_ARCH_REVISION to select between R1 and R2
nios2: implement flush_dcache_mmap_lock/unlock
nios2: enable earlycon support
nios2: constify irq_domain_ops
nios2: remove wrapper header for cmpxchg.h
nios2: add .gitignore entries for auto-generated files


Julien Beraud (1):
  nios2: implement flush_dcache_mmap_lock/unlock

Ley Foon Tan (1):
  nios2: use generic strncpy_from_user() and strnlen_user()

Marek Vasut (3):
  nios2: Add NIOS2_ARCH_REVISION to select between R1 and R2
  nios2: Add BMX support
  nios2: Add CDX support

Tobias Klauser (5):
  nios2: add .gitignore entries for auto-generated files
  nios2: remove wrapper header for cmpxchg.h
  nios2: constify irq_domain_ops
  nios2: enable earlycon support
  nios2: remove custom early console implementation

 arch/nios2/Kconfig |   2 +
 arch/nios2/Kconfig.debug   |   1 -
 arch/nios2/Makefile|   5 ++
 arch/nios2/boot/.gitignore |   2 +
 arch/nios2/boot/dts/10m50_devboard.dts |   3 +-
 arch/nios2/include/asm/Kbuild  |   1 +
 arch/nios2/include/asm/cacheflush.h|   6 +-
 arch/nios2/include/asm/cmpxchg.h   |  14 
 arch/nios2/include/asm/cpuinfo.h   |   2 +
 arch/nios2/include/asm/prom.h  |  22 --
 arch/nios2/include/asm/setup.h |   2 -
 arch/nios2/include/asm/uaccess.h   |   7 +-
 arch/nios2/kernel/.gitignore   |   1 +
 arch/nios2/kernel/Makefile |   1 -
 arch/nios2/kernel/cpuinfo.c|  18 -
 arch/nios2/kernel/early_printk.c   | 118 -
 arch/nios2/kernel/irq.c|   2 +-
 arch/nios2/kernel/prom.c   |  49 --
 arch/nios2/kernel/setup.c  |   6 +-
 arch/nios2/mm/uaccess.c|  33 -
 arch/nios2/platform/Kconfig.platform   |  26 
 21 files changed, 69 insertions(+), 252 deletions(-)
 create mode 100644 arch/nios2/boot/.gitignore
 delete mode 100644 arch/nios2/include/asm/cmpxchg.h
 delete mode 100644 arch/nios2/include/asm/prom.h
 create mode 100644 arch/nios2/kernel/.gitignore
 delete mode 100644 arch/nios2/kernel/early_printk.c

Re: [PATCH] PCI: altera: Fix bool initialization in tlp_read_packet

[Ley Foon Tan]

On Fri, 2018-01-19 at 21:26 -0600, Gustavo A. R. Silva wrote:
> Bool initializations should use true and false.
> 
> This issue was detected with the help of Coccinelle.
> 
> Fixes: eaa6111b70a7 ("PCI: altera: Add Altera PCIe host controller
> driver")
> Signed-off-by: Gustavo A. R. Silva 
> ---
>  drivers/pci/host/pcie-altera.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-
> altera.c
> index 5cc4f59..f9ee090 100644
> --- a/drivers/pci/host/pcie-altera.c
> +++ b/drivers/pci/host/pcie-altera.c
> @@ -156,7 +156,7 @@ static bool altera_pcie_valid_device(struct
> altera_pcie *pcie,
>  static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
>  {
> int i;
> -   bool sop = 0;
> +   bool sop = false;
> u32 ctrl;
>         u32 reg0, reg1;
> u32 comp_status = 1;
> --
> 2.7.4

Acked-by: Ley Foon Tan 

[GIT PULL] arch/nios2 update for v4.17-rc1

[Ley Foon Tan]

Hi Linus

Here is nios2 update for v4.17-rc1.

Please consider pulling.

Regards
Ley Foon


The following changes since commit 0adb32858b0bddf4ada5f364a84ed60b196dbcda:

  Linux 4.16 (2018-04-01 14:20:27 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/lftan/nios2.git 
tags/nios2-v4.17-rc1

for you to fetch changes up to 3d9644ef9a0f6c3ca0c1bd2aea1d82e7ea0a7f24:

  nios2: Use read_persistent_clock64() instead of read_persistent_clock() 
(2018-04-03 00:36:55 +0800)


nios2 update for v4.17-rc1

nios2: Use read_persistent_clock64() instead of read_persistent_clock()


Baolin Wang (1):
  nios2: Use read_persistent_clock64() instead of read_persistent_clock()

 arch/nios2/kernel/time.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH] nios2: ksyms: Add missing symbol exports

[Ley Foon Tan]

On Sun, 2018-10-07 at 07:53 -0700, Guenter Roeck wrote:
> Building nios2:allmodconfig fails as follows (each symbol is only
> listed
> once).
> 
> ERROR: "__ashldi3" [drivers/md/dm-writecache.ko] undefined!
> ERROR: "__ashrdi3" [fs/xfs/xfs.ko] undefined!
> ERROR: "__ucmpdi2" [drivers/media/i2c/adv7842.ko] undefined!
> ERROR: "__lshrdi3" [drivers/md/dm-zoned.ko] undefined!
> ERROR: "flush_icache_range" [drivers/misc/lkdtm/lkdtm.ko] undefined!
> ERROR: "empty_zero_page" [drivers/md/dm-mod.ko] undefined!
> 
> The problem is seen with gcc 7.3.0.
> 
> Export the missing symbols.
> 
> Fixes: 2fc8483fdcde ("nios2: Build infrastructure")
> Signed-off-by: Guenter Roeck 
Acked-by: Ley Foon Tan 

> ---
>  arch/nios2/kernel/nios2_ksyms.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/nios2/kernel/nios2_ksyms.c
> b/arch/nios2/kernel/nios2_ksyms.c
> index bf2f55d10a4d..4e704046a150 100644
> --- a/arch/nios2/kernel/nios2_ksyms.c
> +++ b/arch/nios2/kernel/nios2_ksyms.c
> @@ -9,12 +9,20 @@
>  #include 
>  #include 
> 
> +#include 
> +#include 
> +
>  /* string functions */
> 
>  EXPORT_SYMBOL(memcpy);
>  EXPORT_SYMBOL(memset);
>  EXPORT_SYMBOL(memmove);
> 
> +/* memory management */
> +
> +EXPORT_SYMBOL(empty_zero_page);
> +EXPORT_SYMBOL(flush_icache_range);
> +
>  /*
>   * libgcc functions - functions that are used internally by the
>   * compiler...  (prototypes are not correct though, but that
> @@ -31,3 +39,7 @@ DECLARE_EXPORT(__udivsi3);
>  DECLARE_EXPORT(__umoddi3);
>  DECLARE_EXPORT(__umodsi3);
>  DECLARE_EXPORT(__muldi3);
> +DECLARE_EXPORT(__ucmpdi2);
> +DECLARE_EXPORT(__lshrdi3);
> +DECLARE_EXPORT(__ashldi3);
> +DECLARE_EXPORT(__ashrdi3);
> --
> 2.7.4
> 
> 
> 
> 
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.

Re: [PATCH] nios2: remove redundant 'default n' from Kconfig-s

[Ley Foon Tan]

On Wed, 2018-10-10 at 17:00 +0200, Bartlomiej Zolnierkiewicz wrote:
> 'default n' is the default value for any bool or tristate Kconfig
> setting so there is no need to write it explicitly.
> 
> Also since commit f467c5640c29 ("kconfig: only write '# CONFIG_FOO
> is not set' for visible symbols") the Kconfig behavior is the same
> regardless of 'default n' being present or not:
> 
> ...
> One side effect of (and the main motivation for) this change is
> making
> the following two definitions behave exactly the same:
> 
> config FOO
> bool
> 
> config FOO
> bool
> default n
> 
> With this change, neither of these will generate a
> '# CONFIG_FOO is not set' line (assuming FOO isn't
> selected/implied).
> That might make it clearer to people that a bare 'default n' is
> redundant.
> ...
> 
> Signed-off-by: Bartlomiej Zolnierkiewicz 
Acked-by: Ley Foon Tan 
> ---
>  arch/nios2/Kconfig   |1 -
>  arch/nios2/platform/Kconfig.platform |9 -
>  2 files changed, 10 deletions(-)
> 
> Index: b/arch/nios2/Kconfig
> ===
> --- a/arch/nios2/Kconfig2018-10-09 15:58:36.543122877 +0200
> +++ b/arch/nios2/Kconfig2018-10-10 16:57:50.411927641 +0200
> @@ -126,7 +126,6 @@ config NIOS2_CMDLINE_IGNORE_DTB
> 
>  config NIOS2_PASS_CMDLINE
> bool "Passed kernel command line from u-boot"
> -   default n
> help
>   Use bootargs env variable from u-boot for kernel command
> line.
>   will override "Default kernel command string".
> Index: b/arch/nios2/platform/Kconfig.platform
> ===
> --- a/arch/nios2/platform/Kconfig.platform  2018-09-03
> 18:11:12.057792442 +0200
> +++ b/arch/nios2/platform/Kconfig.platform  2018-10-10
> 16:58:37.951928838 +0200
> @@ -17,7 +17,6 @@ comment "Device tree"
> 
>  config NIOS2_DTB_AT_PHYS_ADDR
> bool "DTB at physical address"
> -   default n
> help
>   When enabled you can select a physical address to load the
> dtb from.
>   Normally this address is passed by a bootloader such as u-
> boot but
> @@ -37,7 +36,6 @@ config NIOS2_DTB_PHYS_ADDR
> 
>  config NIOS2_DTB_SOURCE_BOOL
> bool "Compile and link device tree into kernel image"
> -   default n
> help
>   This allows you to specify a dts (device tree source) file
>   which will be compiled and linked into the kernel image.
> @@ -62,21 +60,18 @@ config NIOS2_ARCH_REVISION
> 
>  config NIOS2_HW_MUL_SUPPORT
> bool "Enable MUL instruction"
> -   default n
> help
>   Set to true if you configured the Nios II to include the
> MUL
>   instruction.  This will enable the -mhw-mul compiler flag.
> 
>  config NIOS2_HW_MULX_SUPPORT
> bool "Enable MULX instruction"
> -   default n
> help
>   Set to true if you configured the Nios II to include the
> MULX
>   instruction.  Enables the -mhw-mulx compiler flag.
> 
>  config NIOS2_HW_DIV_SUPPORT
> bool "Enable DIV instruction"
> -   default n
> help
>   Set to true if you configured the Nios II to include the
> DIV
>   instruction.  Enables the -mhw-div compiler flag.
> @@ -84,7 +79,6 @@ config NIOS2_HW_DIV_SUPPORT
>  config NIOS2_BMX_SUPPORT
> bool "Enable BMX instructions"
> depends on NIOS2_ARCH_REVISION = 2
> -   default n
> help
>   Set to true if you configured the Nios II R2 to include
>   the BMX Bit Manipulation Extension instructions. Enables
> @@ -93,7 +87,6 @@ config NIOS2_BMX_SUPPORT
>  config NIOS2_CDX_SUPPORT
> bool "Enable CDX instructions"
> depends on NIOS2_ARCH_REVISION = 2
> -   default n
> help
>   Set to true if you configured the Nios II R2 to include
>   the CDX Bit Manipulation Extension instructions. Enables
> @@ -101,13 +94,11 @@ config NIOS2_CDX_SUPPORT
> 
>  config NIOS2_FPU_SUPPORT
> bool "Custom floating point instr support"
> -   default n
> help
>   Enables the -mcustom-fpu-cfg=60-1 compiler flag.
> 
>  config NIOS2_CI_SWAB_SUPPORT
> bool "Byteswap custom instruction"
> -   default n
> help
>   Use the byteswap (en

Re: [PATCH] nios2: kconfig: remove duplicate DEBUG_STACK_USAGE symbol defintions

[Ley Foon Tan]

On Tue, 2018-08-21 at 01:15 +0900, Masahiro Yamada wrote:
> 2018-08-16 16:05 GMT+09:00 Tobias Klauser :
> > 
> > DEBUG_STACK_USAGE is already defined in lib/Kconfig.debug
> > 
> > Signed-off-by: Tobias Klauser 
> 
> Reviewed-by: Masahiro Yamada 
> 
Acked-by: Ley Foon Tan 

> 
> > 
> > ---
> >  arch/nios2/Kconfig.debug | 9 -
> >  1 file changed, 9 deletions(-)
> > 
> > diff --git a/arch/nios2/Kconfig.debug b/arch/nios2/Kconfig.debug
> > index 7a49f0d28d14..f1da8a7b17ff 100644
> > --- a/arch/nios2/Kconfig.debug
> > +++ b/arch/nios2/Kconfig.debug
> > @@ -3,15 +3,6 @@
> >  config TRACE_IRQFLAGS_SUPPORT
> > def_bool y
> > 
> > -config DEBUG_STACK_USAGE
> > -   bool "Enable stack utilization instrumentation"
> > -   depends on DEBUG_KERNEL
> > -   help
> > - Enables the display of the minimum amount of free stack
> > which each
> > - task has ever had available in the sysrq-T and sysrq-P
> > debug output.
> > -
> > - This option will slow down process creation somewhat.
> > -
> >  config EARLY_PRINTK
> > bool "Activate early kernel debugging"
> > default y
> > --
> > 2.18.0.130.g98da2f6b3e4a
> > 
> > 
> 
> 
> --
> Best Regards
> Masahiro Yamada
> 
> 
> 
> Confidentiality Notice.
> This message may contain information that is confidential or
> otherwise protected from disclosure. If you are not the intended
> recipient, you are hereby notified that any use, disclosure,
> dissemination, distribution, or copying of this message, or any
> attachments, is strictly prohibited. If you have received this
> message in error, please advise the sender by reply e-mail, and
> delete the message and any attachments. Thank you.

[PATCH v2 0/2] Add Stratix10 PCIe Root Port support

[Ley Foon Tan]

Add PCIe Root Port support for Stratix10 device and also update
device tree binding documentation.

v1 -> v2:
-
- Add define S10_TLP_FMTTYPE_* macros.
- Remove initialize structure members to NULL/zero.
- Rename *_funcs to *_data.
- Update comment and fix coding style warning from checkpatch.pl.
- Rename StratixXX to stratix10.

History:

[v1]: https://lkml.org/lkml/2018/12/26/68

Ley Foon Tan (2):
  pci: altera: Add Stratix10 PCIe support
  Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0

 .../devicetree/bindings/pci/altera-pcie.txt|4 +-
 drivers/pci/controller/Kconfig |2 +-
 drivers/pci/controller/pcie-altera.c   |  240 ++--
 3 files changed, 220 insertions(+), 26 deletions(-)

[PATCH v2 1/2] pci: altera: Add Stratix10 PCIe support

[Ley Foon Tan]

Add PCIe Root Port support for Stratix10 device.

Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
  - One REG0 register
  - Don't need to check alignment

Signed-off-by: Ley Foon Tan 
---
 drivers/pci/controller/Kconfig   |2 +-
 drivers/pci/controller/pcie-altera.c |  240 ++
 2 files changed, 217 insertions(+), 25 deletions(-)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6671946..6012f30 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -175,7 +175,7 @@ config PCIE_IPROC_MSI
 
 config PCIE_ALTERA
bool "Altera PCIe controller"
-   depends on ARM || NIOS2 || COMPILE_TEST
+   depends on ARM || NIOS2 || ARM64 || COMPILE_TEST
help
  Say Y here if you want to enable PCIe controller support on Altera
  FPGA.
diff --git a/drivers/pci/controller/pcie-altera.c 
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..385b822 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -37,7 +38,12 @@
 #define RP_LTSSM_MASK  0x1f
 #define LTSSM_L0   0xf
 
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG   0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+   (((pcie)->hip_base) + (reg) + (1 << 20))
+
 /* TLP configuration type 0 and 1 */
 #define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
 #define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
 #define RP_DEVFN   0
 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
 #define TLP_CFGRD_DW0(pcie, bus)   \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
-   : TLP_FMTTYPE_CFGRD1) << 24) |  \
- TLP_PAYLOAD_SIZE)
+   bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+   : pcie->pcie_data->cfgrd1) << 24) | \
+   TLP_PAYLOAD_SIZE)
 #define TLP_CFGWR_DW0(pcie, bus)   \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
-   : TLP_FMTTYPE_CFGWR1) << 24) |  \
- TLP_PAYLOAD_SIZE)
+   bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+   : pcie->pcie_data->cfgwr1) << 24) | \
+   TLP_PAYLOAD_SIZE)
 #define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
+   (((TLP_REQ_ID(pcie->root_bus_nr,  RP_DEVFN)) << 16) | (tag << 8) | (be))
 #define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
 #define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s)  (((s) >> 0) & 0xfff)
 #define TLP_HDR_SIZE   3
 #define TLP_LOOP   500
 
@@ -69,14 +76,38 @@
 
 #define DWORD_MASK 3
 
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
 struct altera_pcie {
struct platform_device  *pdev;
-   void __iomem*cra_base;  /* DT Cra */
+   void __iomem*cra_base;
+   void __iomem*hip_base;
int irq;
u8  root_bus_nr;
struct irq_domain   *irq_domain;
struct resource bus_range;
struct list_headresources;
+   const struct altera_pcie_data   *pcie_data;
+};
+
+struct altera_pcie_data {
+   int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+   void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+   bool (*get_link_status)(struct altera_pcie *pcie);
+   int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+  int size, u32 *value);
+   int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+   int size, u32 value);
+   bool s10_flag;  /* Stratix 10 */
+   u32 cap_offset; /* PCIe capability structure register offset */
+   u32 cfgrd0;
+   u32 cfgrd1;
+   u32 cfgwr0;
+   u32 cfgwr1;
 };
 
 struct tlp_rp