[PATCH] perf vendor events intel: Add Tremontx event file v1.02

2019-08-14 Thread Haiyan Song 
Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
---
 tools/perf/pmu-events/arch/x86/mapfile.csv |   1 +
 tools/perf/pmu-events/arch/x86/tremontx/cache.json | 111 ++
 .../pmu-events/arch/x86/tremontx/frontend.json |  26 ++
 .../perf/pmu-events/arch/x86/tremontx/memory.json  |  26 ++
 tools/perf/pmu-events/arch/x86/tremontx/other.json |  26 ++
 .../pmu-events/arch/x86/tremontx/pipeline.json | 111 ++
 .../arch/x86/tremontx/uncore-memory.json   |  73 
 .../pmu-events/arch/x86/tremontx/uncore-other.json | 431 +
 .../pmu-events/arch/x86/tremontx/uncore-power.json |  11 +
 .../arch/x86/tremontx/virtual-memory.json  |  86 
 10 files changed, 902 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/uncore-power.json
 create mode 100644 tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv 
b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b90e5fec2f32..745ced083844 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -35,4 +35,5 @@ GenuineIntel-6-55-[01234],v1,skylakex,core
 GenuineIntel-6-55-[56789ABCDEF],v1,cascadelakex,core
 GenuineIntel-6-7D,v1,icelake,core
 GenuineIntel-6-7E,v1,icelake,core
+GenuineIntel-6-86,v1,tremontx,core
 AuthenticAMD-23-[[:xdigit:]]+,v1,amdfam17h,core
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json 
b/tools/perf/pmu-events/arch/x86/tremontx/cache.json
new file mode 100644
index ..f88040171b4d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json
@@ -0,0 +1,111 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts cacheable memory requests that miss in 
the the Last Level Cache.  Requests include Demand Loads, Reads for 
Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has 
an L3 cache, last level cache is the L3, otherwise it is the L2.",
+"EventCode": "0x2e",
+"Counter": "0,1,2,3",
+"UMask": "0x41",
+"PEBScounters": "0,1,2,3",
+"EventName": "LONGEST_LAT_CACHE.MISS",
+"PDIR_COUNTER": "na",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts memory requests originating from the core 
that miss in the last level cache. If the platform has an L3 cache, last level 
cache is the L3, otherwise it is the L2."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts cacheable memory requests that access the 
Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), 
Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last 
level cache is the L3, otherwise it is the L2.",
+"EventCode": "0x2e",
+"Counter": "0,1,2,3",
+"UMask": "0x4f",
+"PEBScounters": "0,1,2,3",
+"EventName": "LONGEST_LAT_CACHE.REFERENCE",
+"PDIR_COUNTER": "na",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts memory requests originating from the core 
that reference a cache line in the last level cache. If the platform has an L3 
cache, last level cache is the L3, otherwise it is the L2."
+},
+{
+"PEBS": "1",
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of load uops retired. This 
event is Precise Event capable",
+"EventCode": "0xd0",
+"Counter": "0,1,2,3",
+"UMask": "0x81",
+"PEBScounters": "0,1,2,3",
+"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts the number of load uops retired.",
+"Data_LA": "1"
+},
+{
+"PEBS": "1",
+"CollectPEBSRecor

[PATCH v2] perf vendor events: Add Icelake V1.00 event file

2019-07-23 Thread Haiyan Song 
Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
---
 tools/perf/pmu-events/arch/x86/icelake/cache.json  | 552 +
 .../arch/x86/icelake/floating-point.json   | 102 +++
 .../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
 tools/perf/pmu-events/arch/x86/icelake/memory.json | 410 ++
 tools/perf/pmu-events/arch/x86/icelake/other.json  | 121 +++
 .../perf/pmu-events/arch/x86/icelake/pipeline.json | 892 +
 .../arch/x86/icelake/virtual-memory.json   | 236 ++
 tools/perf/pmu-events/arch/x86/mapfile.csv |   2 +
 8 files changed, 2739 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json 
b/tools/perf/pmu-events/arch/x86/icelake/cache.json
new file mode 100644
index ..3529fc338c17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -0,0 +1,552 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
that miss L2 cache. Only not rejected loads are counted.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x21",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand Data Read miss L2, no rejects"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the RFO (Read-for-Ownership) requests 
that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x22",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.RFO_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "RFO requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts L2 cache misses when fetching 
instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x24",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.CODE_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "L2 cache misses when fetching instructions"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts demand requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x27",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts Software prefetch requests that miss the 
L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x28",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.SWPF_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "SW prefetch requests that miss L2 cache."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
initiated by load instructions that hit L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0xc1",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.

[PATCH v2] perf vendor events: Add Icelake V1.00 event file

2019-06-26 Thread Haiyan Song 

Hi Arnaldo,

Since this patch contains lines longer than 998 characters, I can't
send the big patch via 'git send-email'.

We will apply for an account on kernel.org to provide git pull request.
But it need to wait for long time.

Could you let me to send this patch by attachment to you?
I attached the v2 patch as an attachment in this mail.
Thanks very much for accepting it.

--
Best regards,
Haiyan Song
From e87c547be14f42434b2a8c8f7f207a6036f033db Mon Sep 17 00:00:00 2001
From: Haiyan Song 
Date: Wed, 12 Jun 2019 16:15:42 +0800
Subject: [PATCH v2] perf vendor events: Add Icelake V1.00 event file

Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
---
 tools/perf/pmu-events/arch/x86/icelake/cache.json  | 552 +
 .../arch/x86/icelake/floating-point.json   | 102 +++
 .../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
 tools/perf/pmu-events/arch/x86/icelake/memory.json | 410 ++
 tools/perf/pmu-events/arch/x86/icelake/other.json  | 121 +++
 .../perf/pmu-events/arch/x86/icelake/pipeline.json | 892 +
 .../arch/x86/icelake/virtual-memory.json   | 236 ++
 tools/perf/pmu-events/arch/x86/mapfile.csv |   2 +
 8 files changed, 2739 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json
new file mode 100644
index ..3529fc338c17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -0,0 +1,552 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x21",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand Data Read miss L2, no rejects"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x22",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.RFO_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "RFO requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts L2 cache misses when fetching instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x24",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.CODE_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "L2 cache misses when fetching instructions"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts demand requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x27",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x28",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.SWPF_MISS",
+"

Re: [PATCH v12 00/31] Speculative page faults

2019-06-05 Thread Haiyan Song 
Hi Laurent,

Regression test for v12 patch serials have been run on Intel 2s skylake 
platform,
some regressions were found by LKP-tools (linux kernel performance). Only 
tested the
cases that have been run and found regressions on v11 patch serials.

Get the patch serials from https://github.com/ldu4/linux/tree/spf-v12.
Kernel commit:
  base: a297558ad4479e0c9c5c14f3f69fe43113f72d1c 
(v5.1-rc4-mmotm-2019-04-09-17-51)
  head: 02c5a1f984a8061d075cfd74986ac8aa01d81064 (spf-v12)

Benchmark: will-it-scale
Download link: https://github.com/antonblanchard/will-it-scale/tree/master
Metrics: will-it-scale.per_thread_ops=threads/nr_cpu
test box: lkp-skl-2sp8(nr_cpu=72,memory=192G)
THP: enable / disable
nr_task: 100%

The following is benchmark results, tested 4 times for every case.

a). Enable THP
base  %stddev   changehead   
%stddev
will-it-scale.page_fault3.per_thread_ops63216  ±3%  -16.9%52537   
±4%
will-it-scale.page_fault2.per_thread_ops36862   -9.8% 33256

b). Disable THP
base  %stddev   changehead   
%stddev
will-it-scale.page_fault3.per_thread_ops65111   -18.6%53023  ±2%
will-it-scale.page_fault2.per_thread_ops38164   -12.0%33565

Best regards,
Haiyan Song

On Tue, Apr 16, 2019 at 03:44:51PM +0200, Laurent Dufour wrote:
> This is a port on kernel 5.1 of the work done by Peter Zijlstra to handle
> page fault without holding the mm semaphore [1].
> 
> The idea is to try to handle user space page faults without holding the
> mmap_sem. This should allow better concurrency for massively threaded
> process since the page fault handler will not wait for other threads memory
> layout change to be done, assuming that this change is done in another part
> of the process's memory space. This type of page fault is named speculative
> page fault. If the speculative page fault fails because a concurrency has
> been detected or because underlying PMD or PTE tables are not yet
> allocating, it is failing its processing and a regular page fault is then
> tried.
> 
> The speculative page fault (SPF) has to look for the VMA matching the fault
> address without holding the mmap_sem, this is done by protecting the MM RB
> tree with RCU and by using a reference counter on each VMA. When fetching a
> VMA under the RCU protection, the VMA's reference counter is incremented to
> ensure that the VMA will not freed in our back during the SPF
> processing. Once that processing is done the VMA's reference counter is
> decremented. To ensure that a VMA is still present when walking the RB tree
> locklessly, the VMA's reference counter is incremented when that VMA is
> linked in the RB tree. When the VMA is unlinked from the RB tree, its
> reference counter will be decremented at the end of the RCU grace period,
> ensuring it will be available during this time. This means that the VMA
> freeing could be delayed and could delay the file closing for file
> mapping. Since the SPF handler is not able to manage file mapping, file is
> closed synchronously and not during the RCU cleaning. This is safe since
> the page fault handler is aborting if a file pointer is associated to the
> VMA.
> 
> Using RCU fixes the overhead seen by Haiyan Song using the will-it-scale
> benchmark [2].
> 
> The VMA's attributes checked during the speculative page fault processing
> have to be protected against parallel changes. This is done by using a per
> VMA sequence lock. This sequence lock allows the speculative page fault
> handler to fast check for parallel changes in progress and to abort the
> speculative page fault in that case.
> 
> Once the VMA has been found, the speculative page fault handler would check
> for the VMA's attributes to verify that the page fault has to be handled
> correctly or not. Thus, the VMA is protected through a sequence lock which
> allows fast detection of concurrent VMA changes. If such a change is
> detected, the speculative page fault is aborted and a *classic* page fault
> is tried.  VMA sequence lockings are added when VMA attributes which are
> checked during the page fault are modified.
> 
> When the PTE is fetched, the VMA is checked to see if it has been changed,
> so once the page table is locked, the VMA is valid, so any other changes
> leading to touching this PTE will need to lock the page table, so no
> parallel change is possible at this time.
> 
> The locking of the PTE is done with interrupts disabled, this allows
> checking for the PMD to ensure that there is not an ongoing collapsing
> operation. Since khugepaged is firstly set the PMD to pmd_none and then is
> waiting for the other CPU to have caught the IPI interrupt, if the pmd is
> valid at the ti

Re: [PATCH v12 00/31] Speculative page faults

2019-06-20 Thread Haiyan Song 
Hi Laurent,

I downloaded your script and run it on Intel 2s skylake platform with spf-v12 
patch
serials.

Here attached the output results of this script.

The following comparison result is statistics from the script outputs.

a). Enable THP
SPF_0  change   SPF_1
will-it-scale.page_fault2.per_thread_ops2664190.8  -11.7%   
2353637.6  
will-it-scale.page_fault3.per_thread_ops4480027.2  -14.7%   
3819331.9 


b). Disable THP
SPF_0   change  SPF_1
will-it-scale.page_fault2.per_thread_ops2653260.7   -10%
2385165.8
will-it-scale.page_fault3.per_thread_ops4436330.1   -12.4%  
3886734.2 


Thanks,
Haiyan Song


On Fri, Jun 14, 2019 at 10:44:47AM +0200, Laurent Dufour wrote:
> Le 14/06/2019 à 10:37, Laurent Dufour a écrit :
> > Please find attached the script I run to get these numbers.
> > This would be nice if you could give it a try on your victim node and share 
> > the result.
> 
> Sounds that the Intel mail fitering system doesn't like the attached shell 
> script.
> Please find it there: 
> https://gist.github.com/ldu4/a5cc1a93f293108ea387d43d5d5e7f44
> 
> Thanks,
> Laurent.
> 
 THP always
 SPF 0
average:2628818
average:2732209
average:2728392
average:2550695
average:2689873
average:2691963
average:2627612
average:2558295
average:2707877
average:2726174
 SPF 1
average:2426260
average:2145674
average:2117769
average:2292502
average:2350403
average:2483327
average:2467324
average:2335393
average:2437859
average:2479865
 THP never
 SPF 0
average:2712575
average:2711447
average:2672362
average:2701981
average:2668073
average:2579296
average:2662048
average:2637422
average:2579143
average:2608260
 SPF 1
average:2348782
average:2203349
average:2312960
average:2402995
average:2318914
average:2543129
average:2390337
average:2490178
average:2416798
average:2424216
 THP always
 SPF 0
average:4370143
average:4245754
average:4678884
average:4665759
average:4665809
average:4639132
average:4210755
average:4330552
average:4290469
average:4703015
 SPF 1
average:3810608
average:3918890
average:3758003
average:3965024
average:3578151
average:3822748
average:3687293
average:3998701
average:3915771
average:3738130
 THP never
 SPF 0
average:4505598
average:4672023
average:4701787
average:4355885
average:4338397
average:4446350
average:4360811
average:4653767
average:4016352
average:4312331
 SPF 1
average:3685383
average:4029413
average:4051615
average:3747588
average:4058557
average:4042340
average:3971295
average:3752943
average:3750626
average:3777582

[PATCH] perf vendor events: Add Icelake V1.00 event file

2019-06-13 Thread Haiyan Song 
Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
---
 tools/perf/pmu-events/arch/x86/icelake/cache.json  | 552 +
 .../arch/x86/icelake/floating-point.json   | 102 +++
 .../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
 tools/perf/pmu-events/arch/x86/icelake/memory.json | 410 ++
 tools/perf/pmu-events/arch/x86/icelake/other.json  | 121 +++
 .../perf/pmu-events/arch/x86/icelake/pipeline.json | 892 +
 .../arch/x86/icelake/virtual-memory.json   | 236 ++
 tools/perf/pmu-events/arch/x86/mapfile.csv |   1 +
 8 files changed, 2738 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json 
b/tools/perf/pmu-events/arch/x86/icelake/cache.json
new file mode 100644
index ..3529fc338c17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -0,0 +1,552 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
that miss L2 cache. Only not rejected loads are counted.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x21",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand Data Read miss L2, no rejects"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the RFO (Read-for-Ownership) requests 
that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x22",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.RFO_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "RFO requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts L2 cache misses when fetching 
instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x24",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.CODE_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "L2 cache misses when fetching instructions"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts demand requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x27",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts Software prefetch requests that miss the 
L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x28",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.SWPF_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "SW prefetch requests that miss L2 cache."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
initiated by load instructions that hit L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0xc1",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.

[PATCH v2] perf vendor events: Add Icelake V1.00 event file

2019-06-16 Thread Haiyan Song 
Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
---
 tools/perf/pmu-events/arch/x86/icelake/cache.json  | 552 +
 .../arch/x86/icelake/floating-point.json   | 102 +++
 .../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
 tools/perf/pmu-events/arch/x86/icelake/memory.json | 410 ++
 tools/perf/pmu-events/arch/x86/icelake/other.json  | 121 +++
 .../perf/pmu-events/arch/x86/icelake/pipeline.json | 892 +
 .../arch/x86/icelake/virtual-memory.json   | 236 ++
 tools/perf/pmu-events/arch/x86/mapfile.csv |   2 +
 8 files changed, 2739 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/cache.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/floating-point.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/frontend.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/memory.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/other.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/pipeline.json
 create mode 100644 tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json 
b/tools/perf/pmu-events/arch/x86/icelake/cache.json
new file mode 100644
index ..3529fc338c17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -0,0 +1,552 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
that miss L2 cache. Only not rejected loads are counted.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x21",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand Data Read miss L2, no rejects"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the RFO (Read-for-Ownership) requests 
that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x22",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.RFO_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "RFO requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts L2 cache misses when fetching 
instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x24",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.CODE_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "L2 cache misses when fetching instructions"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts demand requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x27",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts Software prefetch requests that miss the 
L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x28",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.SWPF_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "SW prefetch requests that miss L2 cache."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
initiated by load instructions that hit L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0xc1",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.

[tip:perf/core] perf vendor events intel: Add Icelake V1.00 event file

2019-08-15 Thread tip-bot for Haiyan Song 
Commit-ID:  b115df076d337a727017538d11d7d46f5bcbff15
Gitweb: https://git.kernel.org/tip/b115df076d337a727017538d11d7d46f5bcbff15
Author: Haiyan Song 
AuthorDate: Wed, 12 Jun 2019 16:15:42 +0800
Committer:  Arnaldo Carvalho de Melo 
CommitDate: Mon, 12 Aug 2019 16:26:02 -0300

perf vendor events intel: Add Icelake V1.00 event file

Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
Reviewed-by: Kan Liang 
Cc: Alexander Shishkin 
Cc: Andi Kleen 
Cc: Jin Yao 
Cc: Jiri Olsa 
Cc: Peter Zijlstra 
Link: https://lkml.kernel.org/r/8859095e-5b02-d6b7-fbdc-3f42b714b...@intel.com
Signed-off-by: Arnaldo Carvalho de Melo 
---
 tools/perf/pmu-events/arch/x86/icelake/cache.json  | 552 +
 .../arch/x86/icelake/floating-point.json   | 102 +++
 .../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
 tools/perf/pmu-events/arch/x86/icelake/memory.json | 410 ++
 tools/perf/pmu-events/arch/x86/icelake/other.json  | 121 +++
 .../perf/pmu-events/arch/x86/icelake/pipeline.json | 892 +
 .../arch/x86/icelake/virtual-memory.json   | 236 ++
 tools/perf/pmu-events/arch/x86/mapfile.csv |   2 +
 8 files changed, 2739 insertions(+)

diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json 
b/tools/perf/pmu-events/arch/x86/icelake/cache.json
new file mode 100644
index ..3529fc338c17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -0,0 +1,552 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
that miss L2 cache. Only not rejected loads are counted.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x21",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand Data Read miss L2, no rejects"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the RFO (Read-for-Ownership) requests 
that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x22",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.RFO_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "RFO requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts L2 cache misses when fetching 
instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x24",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.CODE_RD_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "L2 cache misses when fetching instructions"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts demand requests that miss L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x27",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "Demand requests that miss L2 cache"
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts Software prefetch requests that miss the 
L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0x28",
+"PEBScounters": "0,1,2,3",
+"EventName": "L2_RQSTS.SWPF_MISS",
+"SampleAfterValue": "23",
+"BriefDescription": "SW prefetch requests that miss L2 cache."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of demand Data Read requests 
initiated by load instructions that hit L2 cache.",
+"EventCode": "0x24",
+"Counter": "0,1,2,3",
+"UMask": "0xc1",
+"PEBScounters": "0,1,2,3"

[tip:perf/core] perf vendor events intel: Add Tremontx event file v1.02

2019-08-16 Thread tip-bot for Haiyan Song 
Commit-ID:  11e54d35e6d5c3533b706753224ef38ea235684b
Gitweb: https://git.kernel.org/tip/11e54d35e6d5c3533b706753224ef38ea235684b
Author: Haiyan Song 
AuthorDate: Thu, 15 Aug 2019 11:59:42 +0800
Committer:  Arnaldo Carvalho de Melo 
CommitDate: Thu, 15 Aug 2019 12:04:04 -0300

perf vendor events intel: Add Tremontx event file v1.02

Add a Intel event file for perf.

Signed-off-by: Haiyan Song 
Reviewed-by: Kan Liang 
Cc: Alexander Shishkin 
Cc: Andi Kleen 
Cc: Jin Yao 
Cc: Jiri Olsa 
Cc: Peter Zijlstra 
Link: http://lkml.kernel.org/r/20190815035942.30602-1-haiyanx.s...@intel.com
Signed-off-by: Arnaldo Carvalho de Melo 
---
 tools/perf/pmu-events/arch/x86/mapfile.csv |   1 +
 tools/perf/pmu-events/arch/x86/tremontx/cache.json | 111 ++
 .../pmu-events/arch/x86/tremontx/frontend.json |  26 ++
 .../perf/pmu-events/arch/x86/tremontx/memory.json  |  26 ++
 tools/perf/pmu-events/arch/x86/tremontx/other.json |  26 ++
 .../pmu-events/arch/x86/tremontx/pipeline.json | 111 ++
 .../arch/x86/tremontx/uncore-memory.json   |  73 
 .../pmu-events/arch/x86/tremontx/uncore-other.json | 431 +
 .../pmu-events/arch/x86/tremontx/uncore-power.json |  11 +
 .../arch/x86/tremontx/virtual-memory.json  |  86 
 10 files changed, 902 insertions(+)

diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv 
b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b90e5fec2f32..745ced083844 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -35,4 +35,5 @@ GenuineIntel-6-55-[01234],v1,skylakex,core
 GenuineIntel-6-55-[56789ABCDEF],v1,cascadelakex,core
 GenuineIntel-6-7D,v1,icelake,core
 GenuineIntel-6-7E,v1,icelake,core
+GenuineIntel-6-86,v1,tremontx,core
 AuthenticAMD-23-[[:xdigit:]]+,v1,amdfam17h,core
diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json 
b/tools/perf/pmu-events/arch/x86/tremontx/cache.json
new file mode 100644
index ..f88040171b4d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json
@@ -0,0 +1,111 @@
+[
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts cacheable memory requests that miss in 
the the Last Level Cache.  Requests include Demand Loads, Reads for 
Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has 
an L3 cache, last level cache is the L3, otherwise it is the L2.",
+"EventCode": "0x2e",
+"Counter": "0,1,2,3",
+"UMask": "0x41",
+"PEBScounters": "0,1,2,3",
+"EventName": "LONGEST_LAT_CACHE.MISS",
+"PDIR_COUNTER": "na",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts memory requests originating from the core 
that miss in the last level cache. If the platform has an L3 cache, last level 
cache is the L3, otherwise it is the L2."
+},
+{
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts cacheable memory requests that access the 
Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), 
Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last 
level cache is the L3, otherwise it is the L2.",
+"EventCode": "0x2e",
+"Counter": "0,1,2,3",
+"UMask": "0x4f",
+"PEBScounters": "0,1,2,3",
+"EventName": "LONGEST_LAT_CACHE.REFERENCE",
+"PDIR_COUNTER": "na",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts memory requests originating from the core 
that reference a cache line in the last level cache. If the platform has an L3 
cache, last level cache is the L3, otherwise it is the L2."
+},
+{
+"PEBS": "1",
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of load uops retired. This 
event is Precise Event capable",
+"EventCode": "0xd0",
+"Counter": "0,1,2,3",
+"UMask": "0x81",
+"PEBScounters": "0,1,2,3",
+"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
+"SampleAfterValue": "23",
+"BriefDescription": "Counts the number of load uops retired.",
+"Data_LA": "1"
+},
+{
+"PEBS": "1",
+"CollectPEBSRecord": "2",
+"PublicDescription": "Counts the number of store uops retired. This 
event i