Re: [PATCH v4 5/5] ARM: dts: mt2701: add iommu/smi dtsi node for mt2701
On Tue, 2016-06-21 at 17:57 +0800, Joerg Roedel wrote: > On Wed, Jun 08, 2016 at 05:51:01PM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang > > > > Add the dtsi node of iommu and smi for mt2701. > > > > Signed-off-by: Honghui Zhang > > --- > > arch/arm/boot/dts/mt2701.dtsi | 51 > > +++ > > 1 file changed, 51 insertions(+) > > Okay, I pushed my arm/mediatek branch to my tree at > > git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git > > Please base the patch on that branch and re-send. > I think it is better let Mediatek SoC maintainer Matthias to accept dtsi patch like other drivers. This can avoid dtsi conflict. As I remember,last time MT8173 IOMMU dtsi patch accepted in iommu tree and mt8173.dtsi had conflict with arm soc tree at the merge window. Honghui should resend this patch to Matthias, and elaborate your dependency with clock and power domain dtsi, then Matthias know the merge sequence. Eddie Thanks
[PATCH] i2c: mediatek: add i2c resume support
From: Liguo Zhang
mt65xx i2c controller initial setting will be cleared after system suspend,
so we should init mt65xx i2c controller again when system resume.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index c02e6c0..9b86716 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -728,11 +728,27 @@ static int mtk_i2c_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int mtk_i2c_resume(struct device *dev)
+{
+ struct mtk_i2c *i2c = dev_get_drvdata(dev);
+
+ mtk_i2c_init_hw(i2c);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops mtk_i2c_pm = {
+ SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
+};
+
static struct platform_driver mtk_i2c_driver = {
.probe = mtk_i2c_probe,
.remove = mtk_i2c_remove,
.driver = {
.name = I2C_DRV_NAME,
+ .pm = &mtk_i2c_pm,
.of_match_table = of_match_ptr(mtk_i2c_of_match),
},
};
--
1.9.1
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Re: [PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
Hi Kevin, On Mon, 2015-10-26 at 17:06 +0900, Kevin Hilman wrote: > On Mon, Oct 26, 2015 at 4:15 PM, Yingjoe Chen > wrote: > > On Mon, 2015-10-26 at 09:56 +0900, Kevin Hilman wrote: > >> Hello, > >> > >> On Sat, Oct 3, 2015 at 12:19 AM, Yingjoe Chen > >> wrote: > >> > Add arch timer node to enable arch-timer support. MT8135 firmware > >> > doesn't correctly setup arch-timer frequency and CNTVOFF, add > >> > properties to workaround this. > >> > > >> > This also set cpu enable-method to enable SMP. > >> > > >> > Signed-off-by: Yingjoe Chen > >> > >> kernelci.org started detecting new boot failures for the mt8135-evb in > >> the arm-soc tree[1], and the boot failures were bisected down to this > >> patch, which landed upstream in the form of commit d186a394bb98 (ARM: > >> dts: mt8135: enable basic SMP bringup for mt8135) > >> > >> Maybe this new SMP support requires updating the firmware on the board > >> as well? If so, the changelog should've been a bit more explicit > >> about firmware dependencies. > > > > Kevin, > > > > Thanks for testing. > > > > No, it doesn't need new firmware. Will test to see what's going wrong. > > Thanks for following up. I'll be glad to test any patches if you have > anything you'd like me to test. You need "clockevents/drivers/mtk: Fix spurious interrupt leading to crash" (https://lkml.org/lkml/2015/8/24/803) Daniel Lezcano already applied this patch in his tree for 4.4. (https://git.linaro.org/people/daniel.lezcano/linux.git) Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [GIT PULL] clk: mediatek: New clocks support and fixes
On Thu, 2015-10-01 at 12:29 -0700, Stephen Boyd wrote: > On 09/30, Daniel Kurtz wrote: > > Hi Mike, > > > > On Tue, Sep 22, 2015 at 5:53 PM, James Liao > > wrote: > > > This is a collection of new Mediatek clocks support and fixes. These > > > patches come from Joe [1], Pi-cheng [2] and me [3], including clock > > > support for subsystems, CPU, GPT and some minor fixes. > > > > > > [1] https://patchwork.kernel.org/patch/6777041/ > > > [2] https://patchwork.kernel.org/patch/7174721/ > > > [3] https://lkml.org/lkml/2015/8/10/194 > > > > > > > > > > > > The following changes since commit > > > 1f93e4a96c9109378204c147b3eec0d0e8100fde: > > > > > > Linux 4.3-rc2 (2015-09-20 14:32:34 -0700) > > > > > > are available in the git repository at: > > > > > > https://github.com/jamesjjliao/linux.git v4.3-rc2-clk > > > > > > for you to fetch changes up to 74219612bb7e25e64409171acada05d9949228f2: > > > > > > arm64: dts: mt8173: Add subsystem clock controller device nodes > > > (2015-07-09 12:58:14 +0800) > > > > > > > Will this be pulled for 4.3, or is it now destined for 4.4? > > (sorry if you are receiving a duplicate email, the previous had HTML > > and was rejected by the lists) > > This won't make v4.3. I see that there's a third pull request > now, with slightly different contents. Why? > Sorry not explain in pull request mail. Third pull request remove two patches: 1. arm64: dts: mt8173: Add subsystem clock controller device nodes I think this should pull by Matthias, so I suggest James remove this patch. 2. clk: mediatek: Export CPU mux clocks for CPU frequency control Mike said this patch is ok before (http://lists.infradead.org/pipermail/linux-arm-kernel/2015-August/364886.html) But he told Pi-cheng recently he is working on coordinate clock rate, he suggest Pi-cheng change this patch, other patches are ok. So James remove this patch. Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/4] arm64: dts: Add mediatek MT8173 SoC and evaluation board dts and Makefile
On Wed, 2014-12-10 at 15:50 +0100, Matthias Brugger wrote:
> 2014-12-10 15:27 GMT+01:00 Yingjoe Chen :
> >
> > Hi,
> >
> > On Wed, 2014-12-10 at 18:50 +0800, Eddie Huang wrote:
> > <...>
> >> diff --git a/arch/arm64/boot/dts/mt8173-evb.dts
> >> b/arch/arm64/boot/dts/mt8173-evb.dts
> >> new file mode 100644
> >> index 000..adf26dd
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/mt8173-evb.dts
> > <...>
> >> + timer {
> >> + compatible = "arm,armv8-timer";
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <1 13 0x8>,
> >> + <1 14 0x8>,
> >> + <1 11 0x8>,
> >> + <1 10 0x8>;
> >> + clock-frequency = <1300>;
> >
> > I believe our firmware doesn't need this line. Please remove it.
>
> The point here would be to know if you need to enable a special timer
> from the mtk-timer block to get the arch timer working.
> In any case, you will need some sort of timer. This dts does not
> describe the mtk-timer (may in the mt8173 it does not exist) but
> defines the clocks clk26m and clk32k. So if you don't use the
> mtk-timer, please remove the clocks as there isn't a block using them.
>
MT8173 has two timer set: CPUGPT and APBGPT, and use CPUGPT to enable
arch_timer. Previous series only have APBGPT. MT8173 still need enable
CPUGPT to get arch timer working, we put this in loader, and transparent
to kernel. So I will remove clk26m and clk32k in next version.
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[PATCH] ARM: mediatek: dts: Add UART dts for MT8127 and MT8135 boards
This patch enable UART for MT8127 moose board and MT8135 evalution board.
Adding the dts, these two boards can show log and shell prompts.
This patch base on my previous MT8135/MT8127 SoC UART dtsi patch [1] and
Matthias's modification to disable SoC UART by default.
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/312311.html
Signed-off-by: Eddie Huang
---
arch/arm/boot/dts/mt8127-moose.dts | 4
arch/arm/boot/dts/mt8135-evbp1.dts | 4
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127-moose.dts
b/arch/arm/boot/dts/mt8127-moose.dts
index 13cba0e..073e295 100644
--- a/arch/arm/boot/dts/mt8127-moose.dts
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -23,3 +23,7 @@
reg = <0 0x8000 0 0x4000>;
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts
b/arch/arm/boot/dts/mt8135-evbp1.dts
index a5adf97..3667738 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -23,3 +23,7 @@
reg = <0 0x8000 0 0x4000>;
};
};
+
+&uart3 {
+ status = "okay";
+};
--
1.8.1.1.dirty
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[PATCH 0/2] ARM: mediatek: Add MT8135 and MT8127 UART support
3.19-rc1 contains Joe's MT8135 & MT8127 basic support and sysirq driver patch. But still can not boot to shell due to lack UART device node in device tree. This patch enables MTK UART driver in multi_v7_defconfig and UART device node. This patch base on 3.19-rc1, and Joe's sysirq dts patch [1] [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/305812.html Eddie Huang (2): ARM: mediatek: add UART dts for mt8127 and mt8135 ARM: Add mediatek SoC UART support in defconfig arch/arm/boot/dts/mt8127.dtsi | 34 ++ arch/arm/boot/dts/mt8135.dtsi | 34 ++ arch/arm/configs/multi_v7_defconfig | 1 + 3 files changed, 69 insertions(+) -- 1.8.1.1.dirty * Email Confidentiality Notice The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. It is intended to be conveyed only to the designated recipient(s). Any use, dissemination, distribution, printing, retaining or copying of this e-mail (including its attachments) by unintended recipient(s) is strictly prohibited and may be unlawful. If you are not an intended recipient of this e-mail, or believe that you have received this e-mail in error, please notify the sender immediately (by replying to this e-mail), delete any and all copies of this e-mail (including any attachments) from your system, and do not disclose the content of this e-mail to any other person. Thank you! -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/2] ARM: Add mediatek SoC UART support in defconfig
Add mediatek SoC UART support in multi_v7_defconfig Signed-off-by: Eddie Huang --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2328fe7..fd0ff95 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -195,6 +195,7 @@ CONFIG_SERIO_AMBAKMI=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_MESON=y -- 1.8.1.1 * Email Confidentiality Notice The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. It is intended to be conveyed only to the designated recipient(s). Any use, dissemination, distribution, printing, retaining or copying of this e-mail (including its attachments) by unintended recipient(s) is strictly prohibited and may be unlawful. If you are not an intended recipient of this e-mail, or believe that you have received this e-mail in error, please notify the sender immediately (by replying to this e-mail), delete any and all copies of this e-mail (including any attachments) from your system, and do not disclose the content of this e-mail to any other person. Thank you! -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] ARM: mediatek: add UART dts for mt8127 and mt8135
This add dts support for mt8127 and mt8135 SoC UART
Signed-off-by: Eddie Huang
---
arch/arm/boot/dts/mt8127.dtsi | 34 ++
arch/arm/boot/dts/mt8135.dtsi | 34 ++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 93bca88..69b1c39 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -64,6 +64,12 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ #clock-cells = <0>;
+ };
};
soc {
@@ -99,5 +105,33 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11002000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11003000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11004000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11005000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
};
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index c5e04ef..ec83e69 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -86,6 +86,12 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ #clock-cells = <0>;
+ };
};
soc {
@@ -121,5 +127,33 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11006000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11006000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11007000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11007000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11008000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11008000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11009000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11009000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
};
};
--
1.8.1.1
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Re: [PATCH 1/2] tty: serial: 8250_mtk: Add earlycon
Hi Rob,
On Fri, 2014-12-26 at 15:24 -0600, Rob Herring wrote:
> On Thu, Dec 18, 2014 at 2:33 AM, Eddie Huang wrote:
> > Mediatek UART has highspeed register, but 8250_early.c doesn't
> > support this, so add earlycon in 8250_mtk.c
>
> I don't see any highspeed register setup here. More generically,
> aren't you just skipping any UART setup? That may be useful on other
> platforms with 8250s, too. With the kernel command line version, you
> could perhaps add a "noinit" flag. The DT case is harder, and I'm not
> sure how we should handle that. We could perhaps add a
> "stdout-path-initialized" flag to chosen.
>
Yes, I skipped UART setup same as msm_serial.c and amba-pl011.c
(although they are standalone serial driver). Just like earlyprintk, I
think earlycon should reuse UART setting in loader. Since some other
platforms with 8250 already depend on this, it's ok to add flags to
distinguish whether 8250 earlycon driver should init hw or not. As you
said, add "noinit" flag is simple, but "stdout-path-initialized" need
more discussion.
> >
> > Signed-off-by: Eddie Huang
> > ---
> > drivers/tty/serial/8250/8250_mtk.c | 33 +
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/drivers/tty/serial/8250/8250_mtk.c
> > b/drivers/tty/serial/8250/8250_mtk.c
> > index de7aae5..65dd569 100644
> > --- a/drivers/tty/serial/8250/8250_mtk.c
> > +++ b/drivers/tty/serial/8250/8250_mtk.c
> > @@ -23,6 +23,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > #include "8250.h"
> >
> > @@ -289,6 +290,38 @@ static struct platform_driver mtk8250_platform_driver
> > = {
> > };
> > module_platform_driver(mtk8250_platform_driver);
> >
> > +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
> > +
> > +static void __init mtk8250_serial_putc(struct uart_port *port, int c)
> > +{
> > + while ((readl(port->membase + (UART_LSR << 2)) & BOTH_EMPTY) !=
> > + BOTH_EMPTY)
> > + ;
> > + writel(c, port->membase + (UART_TX << 2));
> > +}
> > +
> > +static void __init early_mtk8250_write(struct console *console,
> > + const char *s, unsigned int count)
>
> Is there a reason early_serial8250_write can't work for you other than
> it is currently static?
>
> Rob
>
The reason is only static. I want to keep 8250_early.c untouchable, all
modifications in 8250_mtk.c
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Re: [PATCH v4 0/2] ARM: mediatek: Add watchdog driver
Hi Matthias, On Mon, 2015-01-12 at 16:34 +0100, Matthias Brugger wrote: > Mediatek SoCs have a watchdog driver. This patch set adds driver and DTS > binding. The driver also implements a restart handler to reboot the SoC. > > Changes for v4: > - fix indentation errors > - delete unused include > - reorganize while loop to eliminate code duplication > - eliminate indirection to watchdog_device structure > - delete unnecessary brackets > > Changes for v3: > - fix based on file name > - fix style problems > - fix error return value and warning message > - delete unnecessary watchdog_set_drvdata > - delete unused variable > > Changes for v2: > - we don't need to have the watchdog enabled to do a software reset > - disable dual mode and irq mode when starting the watchdog > - update commit message to name the SoCs the driver supports > > Matthias Brugger (2): > watchdog: Add driver for Mediatek watchdog > ARM: mediatek: dts: Add bindings for watchdog > > .../devicetree/bindings/watchdog/mtk-wdt.txt | 13 ++ > drivers/watchdog/Kconfig | 10 + > drivers/watchdog/Makefile | 1 + > drivers/watchdog/mtk_wdt.c | 252 > + > 4 files changed, 276 insertions(+) > create mode 100644 Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > create mode 100644 drivers/watchdog/mtk_wdt.c > Test OK on mt8173 platform. Tested-by: Eddie Huang -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [RFC 01/11] i2c: add quirk structure to describe adapter flaws
Hi Wolfram,
On Fri, 2015-01-09 at 18:21 +0100, Wolfram Sang wrote:
>
> + */
> +struct i2c_adapter_quirks {
> + u64 flags;
> + int max_num_msgs;
> + u16 max_write_len;
> + u16 max_read_len;
> + u16 max_comb_write_len;
> + u16 max_comb_read_len;
> +};
> +
> +#define I2C_ADAPTER_QUIRK_COMB_WRITE_FIRST BIT(0)
> +#define I2C_ADAPTER_QUIRK_COMB_READ_SECOND BIT(1)
> +#define I2C_ADAPTER_QUIRK_COMB_WRITE_THEN_READ
> (I2C_ADAPTER_QUIRK_COMB_WRITE_FIRST | \
> +
> I2C_ADAPTER_QUIRK_COMB_READ_SECOND)
> +
> /*
> * i2c_adapter is the structure used to identify a physical i2c bus along
> * with the access algorithms necessary to access it.
> @@ -472,6 +506,7 @@ struct i2c_adapter {
> struct list_head userspace_clients;
>
> struct i2c_bus_recovery_info *bus_recovery_info;
> + struct i2c_adapter_quirks *quirks;
> };
> #define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev)
>
I suggest to add const.
const struct i2c_adapter_quirks *quirks;
also, in i2c-core.c, should modify:
const struct i2c_adapter_quirks *q = adap->quirks;
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[PATCH v4 0/2] ARM: mediatek: Add driver for Mediatek I2C controller
This series is the fourth version of Mediatek SoCs I2C controller common bus driver. Change in v4: Modify to support i2c_adapter_quirks base on Wolfram's patch [1]. Remove check transfer size and WRRD combine code. Instead, fill quirk property and let i2c_check_for_quirks to do the filter. This driver is based on 3.19-rc1. MTK I2C HW has some limitations. 1. Only support one i2c_msg number. One exception is WRRD (write then read) mode. WRRD can have two i2c_msg numbers. 2. Mediatek I2C controller support WRRD(write then read) mode, in WRRD mode the Repeat Start will be issued between 2 messages. In this driver if 2 messages is first write then read, the driver will combine 2 messages using Write-Read mode so the RS will be issued between the 2 messages. 3. The max transfer data length is 255 in one message. In WRRD mode, the max data length of second msg is 31. MT8135 and MT6589 can control I2C pins on PMIC(MT6397) by setting the i2c registers in MT8135 side. In this case, driver should set OFFSET_PATH_DIR bit first, the operation on other registers are still the same. For now MT6589/MT8135 support this, MT6577/MT6595/MT8127 do not support. For example, If want to use I2C4/5/6 pins on MT8135 just need to enable the pinmux, else if want to use I2C pins on PMIC(MT6397) need to add "mediatek,have-pmic" property in the .dts file of each platform. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314804.html Xudong Chen (2): dt-bindings: Add I2C bindings for mt65xx/mt81xx. I2C: mediatek: Add driver for MediaTek I2C controller .../devicetree/bindings/i2c/i2c-mt6577.txt | 40 ++ drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-mt65xx.c| 710 + 4 files changed, 760 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt create mode 100644 drivers/i2c/busses/i2c-mt65xx.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/2] dt-bindings: Add I2C bindings for mt65xx/mt81xx.
From: Xudong Chen
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen
Signed-off-by: Eddie Huang
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
new file mode 100644
index 000..08f86c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
@@ -0,0 +1,40 @@
+* Mediatek's I2C controller
+
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+ - compatible: value should be either of the following.
+ (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
+ (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
+ (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
+ (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
+ - reg: physical base address of the controller and dma base, length of memory
+mapped region.
+ - interrupts: interrupt number to the cpu.
+ - clock-div: the fixed value for frequency divider of clock source in i2c
+module. Each IC may be different.
+ - clocks: clock name from clock manager
+ - clock-names: Must include "main" and "dma", if enable have-pmic need
include
+"pmic" extra.
+
+Optional properties:
+ - clock-frequency: Frequency in Hz of the bus when transfer, the default
value
+is 10.
+ - mediatek,have-pmic: platform can control i2c form special pmic side.
+Only mt6589 and mt8135 support this feature.
+ - mediatek,use-push-pull: IO config use push-pull mode.
+
+Example:
+
+ i2c0: i2c@1100d000 {
+ compatible = "mediatek,mt6577-i2c";
+ reg = <0x1100d000 0x70>,
+ <0x11000300 0x80>;
+ interrupts = ;
+ clock-frequency = <10>;
+ mediatek,have-pmic;
+ clock-div = <16>;
+ clocks = <&i2c0_ck>, <&ap_dma_ck>;
+ clock-names = "main", "dma";
+ };
+
--
1.8.1.1.dirty
--
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[PATCH v4 2/2] I2C: mediatek: Add driver for MediaTek I2C controller
From: Xudong Chen The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen Signed-off-by: Eddie Huang --- drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mt65xx.c | 710 3 files changed, 720 insertions(+) create mode 100644 drivers/i2c/busses/i2c-mt65xx.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 31e8308..7c76693 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -582,6 +582,15 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MT65XX + tristate "MediaTek I2C adapter" + depends on ARCH_MEDIATEK + help + This selects the MediaTek(R) Integrated Inter Circuit bus driver + for MT65xx and MT81xx. + If you want to use MediaTek(R) I2C interface, say Y or M here. + If unsure, say N. + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on MV64X60 || PLAT_ORION || ARCH_SUNXI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 56388f6..59cbb4b 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MESON)+= i2c-meson.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c new file mode 100644 index 000..21bbe3b --- /dev/null +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Xudong.chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_HS_NACKERR (1 << 2) +#define I2C_ACKERR (1 << 1) +#define I2C_TRANSAC_COMP (1 << 0) +#define I2C_TRANSAC_START (1 << 0) +#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) +#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) +#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) +#define I2C_TIMING_DATA_READ_MASK (0x7 << 12) +#define I2C_DCM_DISABLE0x +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 +#define I2C_IO_CONFIG_PUSH_PULL0x +#define I2C_SOFT_RST 0x0001 +#define I2C_FIFO_ADDR_CLR 0x0001 +#define I2C_DELAY_LEN 0x0002 +#define I2C_ST_START_CON 0x8001 +#define I2C_FS_START_CON 0x1800 +#define I2C_TIME_CLR_VALUE 0x +#define I2C_TIME_DEFAULT_VALUE 0x0003 +#define I2C_FS_TIME_INIT_VALUE 0x1303 +#define I2C_WRRD_TRANAC_VALUE 0x0002 +#define I2C_RD_TRANAC_VALUE0x0001 + +#define I2C_DMA_CON_TX 0x +#define I2C_DMA_CON_RX 0x0001 +#define I2C_DMA_START_EN 0x0001 +#define I2C_DMA_INT_FLAG_NONE 0x +#define I2C_DMA_CLR_FLAG 0x + +#define I2C_DEFAUT_SPEED 10 /* hz */ +#define MAX_FS_MODE_SPEED 40 +#define MAX_HS_MODE_SPEED 340 +#define MAX_DMA_TRANS_SIZE 255 +#define MAX_WRRD_TRANS_SIZE31 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV8 + +#define I2C_CONTROL_RS (0x1 << 1) +#define I2C_CONTROL_DMA_EN (0x1 << 2) +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) +#define I2C_CONTROL_WRAPPER (0x1 << 0) + +#define COMPAT_MT6577 (0x1 << 0) +#define COMPAT_MT6589 (0x1 << 1) + +#de
[PATCH v5 0/3] ARM: mediatek: Add driver for Mediatek I2C controller
This series is for Mediatek SoCs I2C controller common bus driver. Earlier MTK SoC ((for example, MT6589, MT8135)) I2C HW has some limitationes. New generation SoC like MT8173 fix these limitations. 1. Only support one i2c_msg number. One exception is WRRD (write then read) mode. WRRD can have two i2c_msg numbers. 2. Mediatek I2C controller support WRRD(write then read) mode, in WRRD mode the Repeat Start will be issued between 2 messages. In this driver if 2 messages is first write then read, the driver will combine 2 messages using Write-Read mode so the RS will be issued between the 2 messages. 3. The max transfer data length is 255 in one message. In WRRD mode, the max data length of second msg is 31. MT8135 and MT6589 can control I2C pins on PMIC(MT6397) by setting the i2c registers in MT8135 side. In this case, driver should set OFFSET_PATH_DIR bit first, the operation on other registers are still the same. For now MT6589/MT8135 support this, MT6577/MT6595/MT8127 do not support. For example, If want to use I2C4/5/6 pins on MT8135 just need to enable the pinmux, else if want to use I2C pins on PMIC(MT6397) need to add "mediatek,have-pmic" property in the .dts file of each platform. This driver is based on 4.0-rc1. Change in v5: Apply new i2c_adapter_quirks patch [2]. Change to use dam_map_single to map dma buffer. Add spinlock to fix race condition. Check of_property_read_u32 return value. Remove I2C_FUNC_10BIT_ADDR capability due to driver not implement. Add MT8173 I2C driver. Change in v4: Modify to support i2c_adapter_quirks base on Wolfram's patch [1]. Remove check transfer size and WRRD combine code. Instead, fill quirk property and let i2c_check_for_quirks to do the filter. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314804.html [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325744.html Eddie Huang (1): I2C: mediatek: Add driver for MediaTek MT8173 I2C controller Xudong Chen (2): dt-bindings: Add I2C bindings for mt65xx/mt81xx. I2C: mediatek: Add driver for MediaTek I2C controller .../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++ drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-mt65xx.c| 748 + 4 files changed, 799 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt create mode 100644 drivers/i2c/busses/i2c-mt65xx.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 3/3] I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Add mediatek MT8173 I2C controller driver. Compare to I2C controller
of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
also increase message size to 64kb.
Signed-off-by: Xudong Chen
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 107
1 file changed, 75 insertions(+), 32 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 3940112..17607c8 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -33,10 +33,13 @@
#include
#include
+#define I2C_RS_TRANSFER(1 << 4)
#define I2C_HS_NACKERR (1 << 2)
#define I2C_ACKERR (1 << 1)
#define I2C_TRANSAC_COMP (1 << 0)
#define I2C_TRANSAC_START (1 << 0)
+#define I2C_RS_MUL_CNFG(1 << 15)
+#define I2C_RS_MUL_TRIG(1 << 14)
#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
@@ -67,6 +70,9 @@
#define MAX_MSG_NUM_MT6577 1
#define MAX_DMA_TRANS_SIZE_MT6577 255
#define MAX_WRRD_TRANS_SIZE_MT6577 31
+#define MAX_MSG_NUM_MT8173 65535
+#define MAX_DMA_TRANS_SIZE_MT8173 65535
+#define MAX_WRRD_TRANS_SIZE_MT8173 65535
#define MAX_SAMPLE_CNT_DIV 8
#define MAX_STEP_CNT_DIV 64
#define MAX_HS_STEP_CNT_DIV8
@@ -81,6 +87,7 @@
#define COMPAT_MT6577 (0x1 << 0)
#define COMPAT_MT6589 (0x1 << 1)
+#define COMPAT_MT8173 (0x1 << 2)
#define I2C_DRV_NAME "mt-i2c"
@@ -172,6 +179,7 @@ struct mtk_i2c {
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt6577-i2c", .data = (void *)COMPAT_MT6577 },
{ .compatible = "mediatek,mt6589-i2c", .data = (void *)COMPAT_MT6589 },
+ { .compatible = "mediatek,mt8173-i2c", .data = (void *)COMPAT_MT8173 },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_match);
@@ -236,7 +244,7 @@ static inline void mtk_i2c_init_hw(struct mtk_i2c *i2c)
else
mtk_i2c_writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c, OFFSET_IO_CONFIG);
- if (i2c->platform_compat & COMPAT_MT6577)
+ if (i2c->platform_compat & (COMPAT_MT6577 | COMPAT_MT8173))
mtk_i2c_writew(I2C_DCM_DISABLE, i2c, OFFSET_DCM_EN);
mtk_i2c_writew(i2c->timing_reg, i2c, OFFSET_TIMING);
@@ -320,10 +328,12 @@ static int i2c_set_speed(struct mtk_i2c *i2c, unsigned
int clk_src_in_hz)
return 0;
}
-static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
+static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
+ int num, int left_num)
{
u16 addr_reg;
u16 control_reg;
+ u16 start_reg = 0;
u16 irqstat;
dma_addr_t rpaddr = 0;
dma_addr_t wpaddr = 0;
@@ -344,6 +354,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct
i2c_msg *msgs)
control_reg |= I2C_CONTROL_RS;
if (i2c->op == I2C_MASTER_WRRD)
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
+ if (left_num >= 1)
+ control_reg |= I2C_CONTROL_RS;
mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
/* set start condition */
@@ -361,13 +373,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c,
struct i2c_msg *msgs)
mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
/* Clear interrupt status */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_STAT);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
/* Enable interrupt */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_MASK);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK);
/* Set transfer and transaction len */
if (i2c->op == I2C_MASTER_WRRD) {
@@ -376,7 +388,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct
i2c_msg *msgs)
mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
} else {
mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
- mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
+ mtk_i2c_writew(num, i2c, OFFSET_TRANSAC_LEN);
}
/* Prepare buffer data to star
[PATCH v5 1/3] dt-bindings: Add I2C bindings for mt65xx/mt81xx.
From: Xudong Chen
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen
Signed-off-by: Eddie Huang
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
new file mode 100644
index 000..eff52c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
@@ -0,0 +1,41 @@
+* Mediatek's I2C controller
+
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+ - compatible: value should be either of the following.
+ (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
+ (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
+ (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
+ (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
+ (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
+ - reg: physical base address of the controller and dma base, length of memory
+mapped region.
+ - interrupts: interrupt number to the cpu.
+ - clock-div: the fixed value for frequency divider of clock source in i2c
+module. Each IC may be different.
+ - clocks: clock name from clock manager
+ - clock-names: Must include "main" and "dma", if enable have-pmic need
include
+"pmic" extra.
+
+Optional properties:
+ - clock-frequency: Frequency in Hz of the bus when transfer, the default
value
+is 10.
+ - mediatek,have-pmic: platform can control i2c form special pmic side.
+Only mt6589 and mt8135 support this feature.
+ - mediatek,use-push-pull: IO config use push-pull mode.
+
+Example:
+
+ i2c0: i2c@1100d000 {
+ compatible = "mediatek,mt6577-i2c";
+ reg = <0x1100d000 0x70>,
+ <0x11000300 0x80>;
+ interrupts = ;
+ clock-frequency = <10>;
+ mediatek,have-pmic;
+ clock-div = <16>;
+ clocks = <&i2c0_ck>, <&ap_dma_ck>;
+ clock-names = "main", "dma";
+ };
+
--
1.8.1.1.dirty
--
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[PATCH v5 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
From: Xudong Chen The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen Signed-off-by: Liguo Zhang Signed-off-by: Eddie Huang --- drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mt65xx.c | 705 3 files changed, 715 insertions(+) create mode 100644 drivers/i2c/busses/i2c-mt65xx.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 22da9c2..243c4ec 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -602,6 +602,15 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MT65XX + tristate "MediaTek I2C adapter" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + This selects the MediaTek(R) Integrated Inter Circuit bus driver + for MT65xx and MT81xx. + If you want to use MediaTek(R) I2C interface, say Y or M here. + If unsure, say N. + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on MV64X60 || PLAT_ORION || ARCH_SUNXI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 3638feb..372a711 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MESON)+= i2c-meson.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c new file mode 100644 index 000..3940112 --- /dev/null +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -0,0 +1,705 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Xudong.chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_HS_NACKERR (1 << 2) +#define I2C_ACKERR (1 << 1) +#define I2C_TRANSAC_COMP (1 << 0) +#define I2C_TRANSAC_START (1 << 0) +#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) +#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) +#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) +#define I2C_TIMING_DATA_READ_MASK (0x7 << 12) +#define I2C_DCM_DISABLE0x +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 +#define I2C_IO_CONFIG_PUSH_PULL0x +#define I2C_SOFT_RST 0x0001 +#define I2C_FIFO_ADDR_CLR 0x0001 +#define I2C_DELAY_LEN 0x0002 +#define I2C_ST_START_CON 0x8001 +#define I2C_FS_START_CON 0x1800 +#define I2C_TIME_CLR_VALUE 0x +#define I2C_TIME_DEFAULT_VALUE 0x0003 +#define I2C_FS_TIME_INIT_VALUE 0x1303 +#define I2C_WRRD_TRANAC_VALUE 0x0002 +#define I2C_RD_TRANAC_VALUE0x0001 + +#define I2C_DMA_CON_TX 0x +#define I2C_DMA_CON_RX 0x0001 +#define I2C_DMA_START_EN 0x0001 +#define I2C_DMA_INT_FLAG_NONE 0x +#define I2C_DMA_CLR_FLAG 0x + +#define I2C_DEFAUT_SPEED 10 /* hz */ +#define MAX_FS_MODE_SPEED 40 +#define MAX_HS_MODE_SPEED 340 +#define MAX_MSG_NUM_MT6577 1 +#define MAX_DMA_TRANS_SIZE_MT6577 255 +#define MAX_WRRD_TRANS_SIZE_MT6577 31 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV8 + +#define I2C_CONTROL_RS (0x1 << 1) +#define I2C_CONTROL_DMA_EN (0x1 << 2) +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) +#define I2C_CONTROL_WRAPPER (0x1 << 0) + +#define COMPAT_MT6577
Re: [PATCH v5 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
Hi Sascha, On Mon, 2015-03-30 at 19:23 +0200, Sascha Hauer wrote: > On Mon, Mar 30, 2015 at 04:14:12PM +0800, Eddie Huang wrote: > > Hi Sascha, > > > > > > > > [...] > > > > > > > + if (i2c->speed_hz > 40) > > > > + control_reg |= I2C_CONTROL_RS; > > > > + if (i2c->op == I2C_MASTER_WRRD) > > > > + control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; > > > > + mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL); > > > > + > > > > + /* set start condition */ > > > > + if (i2c->speed_hz <= 10) > > > > + mtk_i2c_writew(I2C_ST_START_CON, i2c, OFFSET_EXT_CONF); > > > > + else > > > > + mtk_i2c_writew(I2C_FS_START_CON, i2c, OFFSET_EXT_CONF); > > > > + > > > > + if (~control_reg & I2C_CONTROL_RS) > > > > + mtk_i2c_writew(I2C_DELAY_LEN, i2c, OFFSET_DELAY_LEN); > > > > > > speed <= 40 here to make this more obvious? > > There are two cases, not only speed<=40, but I2C_MASTER_WRRD. I tend > > to keep it. > > Still it looks strange. You only ever write this default value to the > register. Putting this register write under an if() seems bogus since > the same value will be in the register the next time this code is > executed. It looks like you should move this register write to some > initialization function. OK, move to mtk_i2c_init_hw function > > > > > + > > > > + /* Enable interrupt */ > > > > + mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, > > > > + i2c, OFFSET_INTR_MASK); > > > > > > Why do you enable/disable interrupts for each transfer? Enabling them > > > once and just acknowledge them in the interrupt handler should be > > > enough. > > This can avoid unwanted I2C interrupt. For example, I2C transfer error, > > and cause timeout, I2C driver report error to caller. Then I2C error > > interrupt happen. > > So isn't the same unwanted interrupt then just delayed until you enable > the interrupts again? Is this something that really happens or just > something you think that might happen? > Clear interrupt status before enable interrupt, so won't get unwanted interrupt again. I just think this might happen, and it's not harmful to enable/disable interrupt in transfer function and can get extra benefit to avoid unnecessary interrupt. Tegra I2C driver i2c-tegra.c also do the same thing. Eddie -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/3] rtc: mediatek: Add MT6397 RTC driver
Hi Tomasz,
On Mon, 2015-03-30 at 16:41 +0900, Tomasz Figa wrote:
> Hi Eddie,
>
> Please see my comments inline.
>
> On Wed, Mar 18, 2015 at 2:45 PM, Eddie Huang wrote:
> > From: Tianping Fang
> >
> > Add Mediatek MT6397 RTC driver
>
> [snip]
>
> > +#define RTC_BBPU 0x
> > +#define RTC_WRTGR 0x003c
> > +#define RTC_IRQ_EN 0x0004
> > +#define RTC_IRQ_STA0x0002
> > +
> > +#define RTC_BBPU_CBUSY (1 << 6)
> > +#define RTC_IRQ_STA_AL (1 << 0)
> > +#define RTC_IRQ_STA_LP (1 << 3)
>
> nit: Could you use BIT() macro for definitions of single bits? (+
> further occurrences in the patch)
Will fix it.
>
> [snip]
>
> > +
> > +static int mtk_rtc_read(struct mt6397_rtc *rtc, u32 offset, u32 *data)
> > +{
> > + u32 addr = rtc->addr_base + offset;
> > +
> > + if (offset < rtc->addr_range)
> > + return regmap_read(rtc->regmap, addr, data);
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int mtk_rtc_write(struct mt6397_rtc *rtc, u32 offset, u32 data)
> > +{
> > + u32 addr;
> > +
> > + addr = rtc->addr_base + offset;
> > +
> > + if (offset < rtc->addr_range)
> > + return regmap_write(rtc->regmap, addr, data);
> > +
> > + return -EINVAL;
> > +}
>
> Do you actually need these wrappers? Could you use regmap_write() and
> _read() directly? This would also enable you to use
> regmap_update_bits() instead of implicit read, modify and write.
These wrappers used to check register range. But I think the check is
redundant, I will bypass the check and use regmap API directly.
>
> > +
> > +static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
> > +{
> > + int ret;
> > + u32 data;
> > +
> > + ret = mtk_rtc_write(rtc, RTC_WRTGR, 1);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + ret = mtk_rtc_read(rtc, RTC_BBPU, &data);
> > + if (ret < 0)
> > + goto exit;
> > +
> > + while (data & RTC_BBPU_CBUSY) {
> > + cpu_relax();
> > + ret = mtk_rtc_read(rtc, RTC_BBPU, &data);
> > + if (ret < 0)
> > + goto exit;
> > + }
>
> The initial read and the loop could be folded into a do {} while loop?
> Also it would be safer to have a timeout here.
Because I need to check return value, so not put initial read in do { }.
Indeed, it is safer to add timeout here.
> > +
> > +static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
> > + struct rtc_time *tm, int *sec)
> > +{
> > + int ret;
> > +
> > + mutex_lock(&rtc->lock);
> > + ret = mtk_rtc_read(rtc, RTC_TC_SEC, &tm->tm_sec);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_MIN, &tm->tm_min);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_HOU, &tm->tm_hour);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_DOM, &tm->tm_mday);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_MTH, &tm->tm_mon);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_YEA, &tm->tm_year);
> > + if (ret < 0)
> > + goto exit;
> > + ret = mtk_rtc_read(rtc, RTC_TC_SEC, sec);
>
> Would the hardware allow this to be merged into single burst transfer
> reading all the registers into a buffer, so then you could just copy
> the values from that buffer into target struct instead of issuing
> multiple reads one by one?
OK, Sascha already mentioned this before, I think I should change to use
single burst reading.
>
> Also shouldn't the unused bits be masked out?
Hardware return zero in unused bits. So I think it not necessary to add
mask.
>
> > +
> > +exit:
> > + mutex_unlock(&rtc->lock);
> > + return ret;
> > +}
> > +
> > +static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
> > +{
> > + time64_t time;
> > + struct mt6397_rtc *rtc = dev_get_drvdata(dev);
> > + int sec, ret;
> > +
> > +
Re: [PATCH v5 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
Hi Sascha, On Tue, 2015-03-31 at 15:08 +0800, Eddie Huang wrote: > Hi Sascha, > > On Mon, 2015-03-30 at 19:23 +0200, Sascha Hauer wrote: > > On Mon, Mar 30, 2015 at 04:14:12PM +0800, Eddie Huang wrote: > > > Hi Sascha, > > > > > > > > > > > [...] > > > > > > > > > + if (i2c->speed_hz > 40) > > > > > + control_reg |= I2C_CONTROL_RS; > > > > > + if (i2c->op == I2C_MASTER_WRRD) > > > > > + control_reg |= I2C_CONTROL_DIR_CHANGE | > > > > > I2C_CONTROL_RS; > > > > > + mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL); > > > > > + > > > > > + /* set start condition */ > > > > > + if (i2c->speed_hz <= 10) > > > > > + mtk_i2c_writew(I2C_ST_START_CON, i2c, > > > > > OFFSET_EXT_CONF); > > > > > + else > > > > > + mtk_i2c_writew(I2C_FS_START_CON, i2c, > > > > > OFFSET_EXT_CONF); > > > > > + > > > > > + if (~control_reg & I2C_CONTROL_RS) > > > > > + mtk_i2c_writew(I2C_DELAY_LEN, i2c, OFFSET_DELAY_LEN); > > > > > > > > speed <= 40 here to make this more obvious? > > > There are two cases, not only speed<=40, but I2C_MASTER_WRRD. I tend > > > to keep it. > > > > Still it looks strange. You only ever write this default value to the > > register. Putting this register write under an if() seems bogus since > > the same value will be in the register the next time this code is > > executed. It looks like you should move this register write to some > > initialization function. > OK, move to mtk_i2c_init_hw function > Sorry for my negligence. Write-then-read (I2C_MASTER_WRRD) decides according to each I2C transfer, so I still need to judge whether set I2C_CONTROL_RS and DELAY_LEN here. Other control setting can move to init function. Eddie -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
Hi Sascha, On Tue, 2015-03-31 at 19:52 +0200, Sascha Hauer wrote: > On Tue, Mar 31, 2015 at 07:50:58PM +0800, Eddie Huang wrote: > > Hi Sascha, > > > > On Tue, 2015-03-31 at 15:08 +0800, Eddie Huang wrote: > > > Hi Sascha, > > > > > > > > > speed <= 40 here to make this more obvious? > > > > > There are two cases, not only speed<=40, but I2C_MASTER_WRRD. I > > > > > tend > > > > > to keep it. > > > > > > > > Still it looks strange. You only ever write this default value to the > > > > register. Putting this register write under an if() seems bogus since > > > > the same value will be in the register the next time this code is > > > > executed. It looks like you should move this register write to some > > > > initialization function. > > > OK, move to mtk_i2c_init_hw function > > > > > Sorry for my negligence. Write-then-read (I2C_MASTER_WRRD) decides > > according to each I2C transfer, so I still need to judge whether set > > I2C_CONTROL_RS and DELAY_LEN here. Other control setting can move to > > init function. > > You need to decide whether you have to set the I2C_CONTROL_RS bit, but > you don't need to write the same value to the DELAY_LEN register each > time. It won't change under your hood. > Yes, you are right. DELAY_LEN should only be set one time in init function. Thanks your correction. Eddie -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 0/3] ARM: mediatek: Add driver for Mediatek I2C controller
This series is for Mediatek SoCs I2C controller common bus driver. Earlier MTK SoC (for example, MT6589, MT8135) I2C HW has some limitationes. New generation SoC like MT8173 fix these limitations. 1. Only support one i2c_msg number. One exception is WRRD (write then read) mode. WRRD can have two i2c_msg numbers. 2. Mediatek I2C controller support WRRD(write then read) mode, in WRRD mode the Repeat Start will be issued between 2 messages. In this driver if 2 messages is first write then read, the driver will combine 2 messages using Write-Read mode so the RS will be issued between the 2 messages. 3. The max transfer data length is 255 in one message. In WRRD mode, the max data length of second msg is 31. MT8135 and MT6589 can control I2C pins on PMIC(MT6397) by setting the i2c registers in MT8135 side. In this case, driver should set OFFSET_PATH_DIR bit first, the operation on other registers are still the same. For now MT6589/MT8135 support this, MT6577/MT6595/MT8127 do not support. For example, If want to use I2C4/5/6 pins on MT8135 just need to enable the pinmux, else if want to use I2C pins on PMIC(MT6397) need to add "mediatek,have-pmic" property in the .dts file of each platform. This driver is based on 4.0-rc1. Change in v6: Add mtk_i2c_compatible struct to set driver capability, and pass by of_device_id. Change to use completion API instead of waitqueue. Remove unnecessary spinlock. Fix get default speed error bug. Fix Sascha's review comment. Change in v5: Apply new i2c_adapter_quirks patch [2]. Change to use dam_map_single to map dma buffer. Add spinlock to fix race condition. Check of_property_read_u32 return value. Remove I2C_FUNC_10BIT_ADDR capability due to driver not implement. Add MT8173 I2C driver. Change in v4: Modify to support i2c_adapter_quirks base on Wolfram's patch [1]. Remove check transfer size and WRRD combine code. Instead, fill quirk property and let i2c_check_for_quirks to do the filter. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314804.html [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325744.html Eddie Huang (1): I2C: mediatek: Add driver for MediaTek MT8173 I2C controller Xudong Chen (2): dt-bindings: Add I2C bindings for mt65xx/mt81xx. I2C: mediatek: Add driver for MediaTek I2C controller .../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++ drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-mt65xx.c| 748 + 4 files changed, 799 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt create mode 100644 drivers/i2c/busses/i2c-mt65xx.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
From: Xudong Chen The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen Signed-off-by: Liguo Zhang Signed-off-by: Eddie Huang --- drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mt65xx.c | 700 3 files changed, 710 insertions(+) create mode 100644 drivers/i2c/busses/i2c-mt65xx.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 22da9c2..243c4ec 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -602,6 +602,15 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MT65XX + tristate "MediaTek I2C adapter" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + This selects the MediaTek(R) Integrated Inter Circuit bus driver + for MT65xx and MT81xx. + If you want to use MediaTek(R) I2C interface, say Y or M here. + If unsure, say N. + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on MV64X60 || PLAT_ORION || ARCH_SUNXI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 3638feb..372a711 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MESON)+= i2c-meson.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c new file mode 100644 index 000..2ecf0d1 --- /dev/null +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Xudong.chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_HS_NACKERR (1 << 2) +#define I2C_ACKERR (1 << 1) +#define I2C_TRANSAC_COMP (1 << 0) +#define I2C_TRANSAC_START (1 << 0) +#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) +#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) +#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) +#define I2C_TIMING_DATA_READ_MASK (0x7 << 12) +#define I2C_DCM_DISABLE0x +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 +#define I2C_IO_CONFIG_PUSH_PULL0x +#define I2C_SOFT_RST 0x0001 +#define I2C_FIFO_ADDR_CLR 0x0001 +#define I2C_DELAY_LEN 0x0002 +#define I2C_ST_START_CON 0x8001 +#define I2C_FS_START_CON 0x1800 +#define I2C_TIME_CLR_VALUE 0x +#define I2C_TIME_DEFAULT_VALUE 0x0003 +#define I2C_FS_TIME_INIT_VALUE 0x1303 +#define I2C_WRRD_TRANAC_VALUE 0x0002 +#define I2C_RD_TRANAC_VALUE0x0001 + +#define I2C_DMA_CON_TX 0x +#define I2C_DMA_CON_RX 0x0001 +#define I2C_DMA_START_EN 0x0001 +#define I2C_DMA_INT_FLAG_NONE 0x +#define I2C_DMA_CLR_FLAG 0x + +#define I2C_DEFAUT_SPEED 10 /* hz */ +#define MAX_FS_MODE_SPEED 40 +#define MAX_HS_MODE_SPEED 340 +#define MAX_MSG_NUM_MT6577 1 +#define MAX_DMA_TRANS_SIZE_MT6577 255 +#define MAX_WRRD_TRANS_SIZE_MT6577 31 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV8 + +#define I2C_CONTROL_RS (0x1 << 1) +#define I2C_CONTROL_DMA_EN (0x1 << 2) +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) +#define I2C_CONTROL_WRAPPER (0x1 << 0) + +#define I2C_DRV_NAME &qu
[PATCH v6 1/3] dt-bindings: Add I2C bindings for mt65xx/mt81xx.
From: Xudong Chen
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen
Signed-off-by: Eddie Huang
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
new file mode 100644
index 000..0ce6fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
@@ -0,0 +1,41 @@
+* Mediatek's I2C controller
+
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+ - compatible: value should be either of the following.
+ (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
+ (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
+ (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
+ (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
+ (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
+ - reg: physical base address of the controller and dma base, length of memory
+mapped region.
+ - interrupts: interrupt number to the cpu.
+ - clock-div: the fixed value for frequency divider of clock source in i2c
+module. Each IC may be different.
+ - clocks: clock name from clock manager
+ - clock-names: Must include "main" and "dma", if enable have-pmic need
include
+"pmic" extra.
+
+Optional properties:
+ - clock-frequency: Frequency in Hz of the bus when transfer, the default
value
+is 10.
+ - mediatek,have-pmic: platform can control i2c form special pmic side.
+Only mt6589 and mt8135 support this feature.
+ - mediatek,use-push-pull: IO config use push-pull mode.
+
+Example:
+
+ i2c0: i2c@1100d000 {
+ compatible = "mediatek,mt6577-i2c";
+ reg = <0x1100d000 0x70>,
+ <0x11000300 0x80>;
+ interrupts = ;
+ clock-frequency = <40>;
+ mediatek,have-pmic;
+ clock-div = <16>;
+ clocks = <&i2c0_ck>, <&ap_dma_ck>;
+ clock-names = "main", "dma";
+ };
+
--
1.8.1.1.dirty
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[PATCH v6 3/3] I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Add mediatek MT8173 I2C controller driver. Compare to I2C controller
of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
also increase message size to 64kb.
Signed-off-by: Xudong Chen
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 104 +---
1 file changed, 76 insertions(+), 28 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 2ecf0d1..80df0df 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -33,10 +33,13 @@
#include
#include
+#define I2C_RS_TRANSFER(1 << 4)
#define I2C_HS_NACKERR (1 << 2)
#define I2C_ACKERR (1 << 1)
#define I2C_TRANSAC_COMP (1 << 0)
#define I2C_TRANSAC_START (1 << 0)
+#define I2C_RS_MUL_CNFG(1 << 15)
+#define I2C_RS_MUL_TRIG(1 << 14)
#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
@@ -67,6 +70,9 @@
#define MAX_MSG_NUM_MT6577 1
#define MAX_DMA_TRANS_SIZE_MT6577 255
#define MAX_WRRD_TRANS_SIZE_MT6577 31
+#define MAX_MSG_NUM_MT8173 65535
+#define MAX_DMA_TRANS_SIZE_MT8173 65535
+#define MAX_WRRD_TRANS_SIZE_MT8173 65535
#define MAX_SAMPLE_CNT_DIV 8
#define MAX_STEP_CNT_DIV 64
#define MAX_HS_STEP_CNT_DIV8
@@ -139,6 +145,7 @@ struct mtk_i2c_compatible {
const struct i2c_adapter_quirks *quirks;
unsigned char pmic_i2c;
unsigned char dcm;
+ unsigned char auto_restart;
};
struct mtk_i2c {
@@ -172,21 +179,39 @@ static const struct i2c_adapter_quirks mt6577_i2c_quirks
= {
.max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
};
+static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
+ .max_num_msgs = MAX_MSG_NUM_MT8173,
+ .max_write_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_read_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173,
+};
+
static const struct mtk_i2c_compatible mt6577_compat = {
.quirks = &mt6577_i2c_quirks,
.pmic_i2c = 0,
.dcm = 1,
+ .auto_restart = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
.quirks = &mt6577_i2c_quirks,
.pmic_i2c = 1,
.dcm = 0,
+ .auto_restart = 0,
+};
+
+static const struct mtk_i2c_compatible mt8173_compat = {
+ .quirks = &mt8173_i2c_quirks,
+ .pmic_i2c = 0,
+ .dcm = 1,
+ .auto_restart = 1,
};
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
{ .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
+ { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_match);
@@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned
int clk_src_in_hz)
return 0;
}
-static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
+static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
+ int num, int left_num)
{
u16 addr_reg;
+ u16 start_reg;
u16 control_reg;
dma_addr_t rpaddr = 0;
dma_addr_t wpaddr = 0;
@@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct
i2c_msg *msgs)
control_reg |= I2C_CONTROL_RS;
if (i2c->op == I2C_MASTER_WRRD)
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
+ if (left_num >= 1)
+ control_reg |= I2C_CONTROL_RS;
mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
/* set start condition */
@@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c,
struct i2c_msg *msgs)
mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
/* Clear interrupt status */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_STAT);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
/* Enable interrupt */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_MASK);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK);
/* Set transfer and transaction len */
if (i2c
[PATCH v3 0/3] Add Mediatek SoC RTC driver
RTC is one submodule of Mediatek MT6397 PMIC chip[1]. This series support RTC driver that work with Mediatek SoC like MT8135, MT8173. It implements second counter and also provide alarm function. This series base on 4.1-rc1, Test ok on MT8173 platform. [1] https://lkml.org/lkml/2015/1/23/325 Change in v3: 1. Replace magic number in mt6397-core.c 2. Add comment for some equation and write trigger. 3. Use regmap_bulk_read and regmap_bulk_write to avoid muliple regmap_read and regmap_write 4. Replace devm_request_threaded_irq with request_threaded_irq and add irq_dispose_mapping 5. Fix Tomasz Figa review comment. Change in v2: 1. Move RTC address and interrupt to mt6397-core.c, and register these resource in mfd_cell. http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/323239.html 2. Remove dt-binding document due to register resouce in mfd_cell, not from device tree. 3. Update MAINTAINER file to add Mediatek RTC mainainter. 4. Add prefix mtk_ to some internal functions. 5. Fix racy condition 6. Check return value of regmap_read and regmap_write 7. Remove some unnecessary register readback, clear, then write. 8. Add disable alarm in mtk_rtc_set_alarm function 9. Fix Uwe Kleine-König review comment Eddie Huang (2): mfd: provide RTC resource in MT6397 MFD MAINTAINERS: add Mediatek RTC driver Tianping Fang (1): rtc: mediatek: Add MT6397 RTC driver MAINTAINERS | 7 + drivers/mfd/mt6397-core.c | 18 +++ drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-mt6397.c | 388 ++ 5 files changed, 424 insertions(+) create mode 100644 drivers/rtc/rtc-mt6397.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/3] mfd: provide RTC resource in MT6397 MFD
Provide MT6397 RTC interrupt, base address, and register in
MT6397 MFD.
Signed-off-by: Eddie Huang
---
drivers/mfd/mt6397-core.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 09bc780..08cfbd1 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -21,9 +21,27 @@
#include
#include
+#define MT6397_RTC_BASE0xe000
+#define MT6397_RTC_SIZE0x3e
+
+static const struct resource mt6397_rtc_resources[] = {
+ {
+ .start = MT6397_RTC_BASE,
+ .end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MT6397_IRQ_RTC,
+ .end = MT6397_IRQ_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
+ .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
+ .resources = mt6397_rtc_resources,
.of_compatible = "mediatek,mt6397-rtc",
}, {
.name = "mt6397-regulator",
--
1.8.1.1.dirty
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[PATCH v3 3/3] MAINTAINERS: add Mediatek RTC driver
Add Mediatek RTC driver to maintainer entry. Signed-off-by: Eddie Huang --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2e5bbc0..eb80610 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1223,6 +1223,13 @@ W: http://www.digriz.org.uk/ts78xx/kernel S: Maintained F: arch/arm/mach-orion5x/ts78xx-* +ARM/Mediatek RTC DRIVER +M: Eddie Huang +L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) +L: linux-media...@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: drivers/rtc/rtc-mt* + ARM/Mediatek SoC support M: Matthias Brugger L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/3] rtc: mediatek: Add MT6397 RTC driver
From: Tianping Fang
Add Mediatek MT6397 RTC driver
Signed-off-by: Tianping Fang
Signed-off-by: Eddie Huang
---
drivers/rtc/Kconfig | 10 ++
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mt6397.c | 388 +++
3 files changed, 399 insertions(+)
create mode 100644 drivers/rtc/rtc-mt6397.c
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 6149ae0..9608fcb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1520,6 +1520,16 @@ config RTC_DRV_MOXART
This driver can also be built as a module. If so, the module
will be called rtc-moxart
+config RTC_DRV_MT6397
+ tristate "Mediatek Real Time Clock driver"
+ depends on MFD_MT6397 || COMPILE_TEST
+ help
+ This selects the Mediatek(R) RTC driver. RTC is part of Mediatek
+ MT6397 PMIC. You should enable MT6397 PMIC MFD before select
+ Mediatek(R) RTC driver.
+
+ If you want to use Mediatek(R) RTC interface, select Y or M here.
+
config RTC_DRV_XGENE
tristate "APM X-Gene RTC"
depends on HAS_IOMEM
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index c31731c..6ba0ce2 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -154,3 +154,4 @@ obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
obj-$(CONFIG_RTC_DRV_XGENE)+= rtc-xgene.o
obj-$(CONFIG_RTC_DRV_SIRFSOC) += rtc-sirfsoc.o
obj-$(CONFIG_RTC_DRV_MOXART) += rtc-moxart.o
+obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
new file mode 100644
index 000..0d96d02
--- /dev/null
+++ b/drivers/rtc/rtc-mt6397.c
@@ -0,0 +1,388 @@
+/*
+* Copyright (c) 2014-2015 MediaTek Inc.
+* Author: Tianping.Fang
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RTC_BBPU 0x
+#define RTC_BBPU_CBUSY BIT(6)
+
+#define RTC_WRTGR 0x003c
+
+#define RTC_IRQ_STA0x0002
+#define RTC_IRQ_STA_AL BIT(0)
+#define RTC_IRQ_STA_LP BIT(3)
+
+#define RTC_IRQ_EN 0x0004
+#define RTC_IRQ_EN_AL BIT(0)
+#define RTC_IRQ_EN_ONESHOT BIT(2)
+#define RTC_IRQ_EN_LP BIT(3)
+#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
+
+#define RTC_AL_MASK0x0008
+#define RTC_AL_MASK_DOWBIT(4)
+
+#define RTC_TC_SEC 0x000a
+/* Min, Hour, Dom... register offset to RTC_TC_SEC */
+#define RTC_OFFSET_SEC 0
+#define RTC_OFFSET_MIN 1
+#define RTC_OFFSET_HOUR2
+#define RTC_OFFSET_DOM 3
+#define RTC_OFFSET_DOW 4
+#define RTC_OFFSET_MTH 5
+#define RTC_OFFSET_YEAR6
+#define RTC_OFFSET_COUNT 7
+
+#define RTC_AL_SEC 0x0018
+
+#define RTC_PDN2 0x002e
+#define RTC_PDN2_PWRON_ALARM BIT(4)
+
+#define RTC_MIN_YEAR 1968
+#define RTC_BASE_YEAR 1900
+#define RTC_NUM_YEARS 128
+#define RTC_MIN_YEAR_OFFSET(RTC_MIN_YEAR - RTC_BASE_YEAR)
+
+struct mt6397_rtc {
+ struct device *dev;
+ struct rtc_device *rtc_dev;
+ struct mutexlock;
+ struct regmap *regmap;
+ int irq;
+ u32 addr_base;
+};
+
+static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
+{
+ unsigned long timeout = jiffies + HZ;
+ int ret;
+ u32 data;
+
+ ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
+ if (ret < 0)
+ return ret;
+
+ do {
+ cpu_relax();
+ ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_BBPU,
+ &data);
+ if (ret < 0)
+ goto exit;
+ } while ((data & RTC_BBPU_CBUSY) && time_after(timeout, jiffies));
+
+exit:
+ return ret;
+}
+
+static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
+{
+ struct mt6397_rtc *rtc = data;
+ u32 irqsta, irqen;
+ int ret;
+
+ ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
+ if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
+ rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
+ irqen = irqsta & ~RTC_IRQ_EN_AL;
+ mutex_lock(&rtc->lock);
+ if (regma
[PATCH v6 1/3] dt-bindings: Add I2C bindings for mt65xx/mt81xx.
From: Xudong Chen
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen
Signed-off-by: Eddie Huang
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
new file mode 100644
index 000..0ce6fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
@@ -0,0 +1,41 @@
+* Mediatek's I2C controller
+
+The Mediatek's I2C controller is used to interface with I2C devices.
+
+Required properties:
+ - compatible: value should be either of the following.
+ (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
+ (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
+ (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
+ (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
+ (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
+ - reg: physical base address of the controller and dma base, length of memory
+mapped region.
+ - interrupts: interrupt number to the cpu.
+ - clock-div: the fixed value for frequency divider of clock source in i2c
+module. Each IC may be different.
+ - clocks: clock name from clock manager
+ - clock-names: Must include "main" and "dma", if enable have-pmic need
include
+"pmic" extra.
+
+Optional properties:
+ - clock-frequency: Frequency in Hz of the bus when transfer, the default
value
+is 10.
+ - mediatek,have-pmic: platform can control i2c form special pmic side.
+Only mt6589 and mt8135 support this feature.
+ - mediatek,use-push-pull: IO config use push-pull mode.
+
+Example:
+
+ i2c0: i2c@1100d000 {
+ compatible = "mediatek,mt6577-i2c";
+ reg = <0x1100d000 0x70>,
+ <0x11000300 0x80>;
+ interrupts = ;
+ clock-frequency = <40>;
+ mediatek,have-pmic;
+ clock-div = <16>;
+ clocks = <&i2c0_ck>, <&ap_dma_ck>;
+ clock-names = "main", "dma";
+ };
+
--
1.8.1.1.dirty
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 3/3] I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Add mediatek MT8173 I2C controller driver. Compare to I2C controller
of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
also increase message size to 64kb.
Signed-off-by: Xudong Chen
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 106 +---
1 file changed, 77 insertions(+), 29 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 2ecf0d1..c501421 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -33,10 +33,13 @@
#include
#include
+#define I2C_RS_TRANSFER(1 << 4)
#define I2C_HS_NACKERR (1 << 2)
#define I2C_ACKERR (1 << 1)
#define I2C_TRANSAC_COMP (1 << 0)
#define I2C_TRANSAC_START (1 << 0)
+#define I2C_RS_MUL_CNFG(1 << 15)
+#define I2C_RS_MUL_TRIG(1 << 14)
#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
@@ -67,6 +70,9 @@
#define MAX_MSG_NUM_MT6577 1
#define MAX_DMA_TRANS_SIZE_MT6577 255
#define MAX_WRRD_TRANS_SIZE_MT6577 31
+#define MAX_MSG_NUM_MT8173 65535
+#define MAX_DMA_TRANS_SIZE_MT8173 65535
+#define MAX_WRRD_TRANS_SIZE_MT8173 65535
#define MAX_SAMPLE_CNT_DIV 8
#define MAX_STEP_CNT_DIV 64
#define MAX_HS_STEP_CNT_DIV8
@@ -139,6 +145,7 @@ struct mtk_i2c_compatible {
const struct i2c_adapter_quirks *quirks;
unsigned char pmic_i2c;
unsigned char dcm;
+ unsigned char auto_restart;
};
struct mtk_i2c {
@@ -172,24 +179,42 @@ static const struct i2c_adapter_quirks mt6577_i2c_quirks
= {
.max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
};
+static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
+ .max_num_msgs = MAX_MSG_NUM_MT8173,
+ .max_write_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_read_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173,
+ .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173,
+};
+
static const struct mtk_i2c_compatible mt6577_compat = {
.quirks = &mt6577_i2c_quirks,
.pmic_i2c = 0,
.dcm = 1,
+ .auto_restart = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
.quirks = &mt6577_i2c_quirks,
.pmic_i2c = 1,
.dcm = 0,
+ .auto_restart = 0,
+};
+
+static const struct mtk_i2c_compatible mt8173_compat = {
+ .quirks = &mt8173_i2c_quirks,
+ .pmic_i2c = 0,
+ .dcm = 1,
+ .auto_restart = 1,
};
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
{ .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
+ { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
{}
};
-MODULE_DEVICE_TABLE(of, mtk_i2c_match);
+MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
static inline void mtk_i2c_writew(u16 value, struct mtk_i2c *i2c, u8 offset)
{
@@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned
int clk_src_in_hz)
return 0;
}
-static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
+static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
+ int num, int left_num)
{
u16 addr_reg;
+ u16 start_reg;
u16 control_reg;
dma_addr_t rpaddr = 0;
dma_addr_t wpaddr = 0;
@@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct
i2c_msg *msgs)
control_reg |= I2C_CONTROL_RS;
if (i2c->op == I2C_MASTER_WRRD)
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
+ if (left_num >= 1)
+ control_reg |= I2C_CONTROL_RS;
mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
/* set start condition */
@@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c,
struct i2c_msg *msgs)
mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
/* Clear interrupt status */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_STAT);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
/* Enable interrupt */
- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
- i2c, OFFSET_INTR_MASK);
+ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR
+
[PATCH v6 2/3] I2C: mediatek: Add driver for MediaTek I2C controller
From: Xudong Chen The mediatek SoCs have I2C controller that handle I2C transfer. This patch include common I2C bus driver. This driver is compatible with I2C controller on mt65xx/mt81xx. Signed-off-by: Xudong Chen Signed-off-by: Liguo Zhang Signed-off-by: Eddie Huang --- drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-mt65xx.c | 700 3 files changed, 710 insertions(+) create mode 100644 drivers/i2c/busses/i2c-mt65xx.c diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 2255af2..14c7266 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -620,6 +620,15 @@ config I2C_MPC This driver can also be built as a module. If so, the module will be called i2c-mpc. +config I2C_MT65XX + tristate "MediaTek I2C adapter" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + This selects the MediaTek(R) Integrated Inter Circuit bus driver + for MT65xx and MT81xx. + If you want to use MediaTek(R) I2C interface, say Y or M here. + If unsure, say N. + config I2C_MV64XXX tristate "Marvell mv64xxx I2C Controller" depends on MV64X60 || PLAT_ORION || ARCH_SUNXI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index cdf941d..abbf422 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o obj-$(CONFIG_I2C_MESON)+= i2c-meson.o obj-$(CONFIG_I2C_MPC) += i2c-mpc.o +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c new file mode 100644 index 000..2ecf0d1 --- /dev/null +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Xudong.chen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define I2C_HS_NACKERR (1 << 2) +#define I2C_ACKERR (1 << 1) +#define I2C_TRANSAC_COMP (1 << 0) +#define I2C_TRANSAC_START (1 << 0) +#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) +#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) +#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) +#define I2C_TIMING_DATA_READ_MASK (0x7 << 12) +#define I2C_DCM_DISABLE0x +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 +#define I2C_IO_CONFIG_PUSH_PULL0x +#define I2C_SOFT_RST 0x0001 +#define I2C_FIFO_ADDR_CLR 0x0001 +#define I2C_DELAY_LEN 0x0002 +#define I2C_ST_START_CON 0x8001 +#define I2C_FS_START_CON 0x1800 +#define I2C_TIME_CLR_VALUE 0x +#define I2C_TIME_DEFAULT_VALUE 0x0003 +#define I2C_FS_TIME_INIT_VALUE 0x1303 +#define I2C_WRRD_TRANAC_VALUE 0x0002 +#define I2C_RD_TRANAC_VALUE0x0001 + +#define I2C_DMA_CON_TX 0x +#define I2C_DMA_CON_RX 0x0001 +#define I2C_DMA_START_EN 0x0001 +#define I2C_DMA_INT_FLAG_NONE 0x +#define I2C_DMA_CLR_FLAG 0x + +#define I2C_DEFAUT_SPEED 10 /* hz */ +#define MAX_FS_MODE_SPEED 40 +#define MAX_HS_MODE_SPEED 340 +#define MAX_MSG_NUM_MT6577 1 +#define MAX_DMA_TRANS_SIZE_MT6577 255 +#define MAX_WRRD_TRANS_SIZE_MT6577 31 +#define MAX_SAMPLE_CNT_DIV 8 +#define MAX_STEP_CNT_DIV 64 +#define MAX_HS_STEP_CNT_DIV8 + +#define I2C_CONTROL_RS (0x1 << 1) +#define I2C_CONTROL_DMA_EN (0x1 << 2) +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) +#define I2C_CONTROL_WRAPPER (0x1 << 0) + +#define I2C_DRV_NAME &qu
[PATCH v6 0/3] ARM: mediatek: Add driver for Mediatek I2C
This series is for Mediatek SoCs I2C controller common bus driver. Earlier MTK SoC ((for example, MT6589, MT8135)) I2C HW has some limitationes. New generation SoC like MT8173 fix following limitations: 1. Only support one i2c_msg number. One exception is WRRD (write then read) mode. WRRD can have two i2c_msg numbers. 2. Mediatek I2C controller support WRRD(write then read) mode, in WRRD mode the Repeat Start will be issued between 2 messages. In this driver if 2 messages is first write then read, the driver will combine 2 messages using Write-Read mode so the RS will be issued between the 2 messages. 3. The max transfer data length is 255 in one message. In WRRD mode, the max data length of second msg is 31. MT8135 and MT6589 can control I2C pins on PMIC(MT6397) by setting the i2c registers in MT8135 side. In this case, driver should set OFFSET_PATH_DIR bit first, the operation on other registers are still the same. For now MT6589/MT8135 support this, MT6577/MT6595/MT8127 do not support. For example, If want to use I2C4/5/6 pins on MT8135 just need to enable the pinmux, else if want to use I2C pins on PMIC(MT6397) need to add "mediatek,have-pmic" property in the .dts file of each platform. This driver is based on 4.1-rc1. Change in v6: 1. Update binding document not use default clock-frequency as example. 2. Add mtk_i2c_compatible struct and pass hardware capabilities through of_device_id 3. Remove some hardware setting in mtk_i2c_do_transfer to mtk_i2c_init_hw so just init one time. 4. Correct mtk_i2c_parse_dt don't set default clock bug. Change in v5: Apply new i2c_adapter_quirks patch [2]. Change to use dam_map_single to map dma buffer. Add spinlock to fix race condition. Check of_property_read_u32 return value. Remove I2C_FUNC_10BIT_ADDR capability due to driver not implement. Add MT8173 I2C driver. Change in v4: Modify to support i2c_adapter_quirks base on Wolfram's patch [1]. Remove check transfer size and WRRD combine code. Instead, fill quirk property and let i2c_check_for_quirks to do the filter. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314804.html [2] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/325744.html Eddie Huang (1): I2C: mediatek: Add driver for MediaTek MT8173 I2C controller Xudong Chen (2): dt-bindings: Add I2C bindings for mt65xx/mt81xx. I2C: mediatek: Add driver for MediaTek I2C controller .../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++ drivers/i2c/busses/Kconfig | 9 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-mt65xx.c| 748 + 4 files changed, 799 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt create mode 100644 drivers/i2c/busses/i2c-mt65xx.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v6 3/3] I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Hi Marc,
On Tue, 2015-04-28 at 10:36 +0200, Marc Kleine-Budde wrote:
> On 04/28/2015 10:31 AM, Eddie Huang wrote:
> > Add mediatek MT8173 I2C controller driver. Compare to I2C controller
> > of earlier mediatek SoC, MT8173 fix write-then-read limitation, and
> > also increase message size to 64kb.
> >
> > Signed-off-by: Xudong Chen
> > Signed-off-by: Liguo Zhang
> > Signed-off-by: Eddie Huang
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 106
> > +---
> > 1 file changed, 77 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c
> > b/drivers/i2c/busses/i2c-mt65xx.c
> > index 2ecf0d1..c501421 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> [...]
>
> > static const struct of_device_id mtk_i2c_of_match[] = {
> > { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
> > { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
> > + { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat },
> > {}
> > };
> > -MODULE_DEVICE_TABLE(of, mtk_i2c_match);
> > +MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
>
> This should go into the previous patch, as 2/3 will probably not compile
> without this change.
>
That's right, my mistake, should be in 2/3.
Eddie
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[PATCH v3 2/3] tty: serial: 8250_mtk: Add earlycon
Add 8250 MTK UART driver to support earlycon device tree.
Earlycon take effect by
add "earlycon" in kernel boot argument
add "linux,sdtout-path" property in device tree file
Signed-off-by: Eddie Huang
---
drivers/tty/serial/8250/8250_mtk.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mtk.c
b/drivers/tty/serial/8250/8250_mtk.c
index 7a11fac..8b2a666 100644
--- a/drivers/tty/serial/8250/8250_mtk.c
+++ b/drivers/tty/serial/8250/8250_mtk.c
@@ -289,6 +289,19 @@ static struct platform_driver mtk8250_platform_driver = {
};
module_platform_driver(mtk8250_platform_driver);
+static int __init early_mtk8250_setup(struct earlycon_device *device,
+ const char *options)
+{
+ if (!device->port.membase)
+ return -ENODEV;
+
+ device->port.iotype = UPIO_MEM32;
+
+ return early_serial8250_setup(device, NULL);
+}
+
+OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);
+
MODULE_AUTHOR("Matthias Brugger");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Mediatek 8250 serial port driver");
--
1.8.1.1.dirty
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[PATCH v3 3/3] arm64: dts: Add mediatek MT8173 earlycon support
Add earlycon support to mediatek MT8173 evaluation board dts.
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 43d5401..d4cf751 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -30,7 +30,9 @@
reg = <0 0x4000 0 0x8000>;
};
- chosen { };
+ chosen {
+ linux,stdout-path = &uart0;
+ };
};
&uart0 {
--
1.8.1.1.dirty
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[PATCH v3 0/3] tty: serial: Add earlycon support to MT8173 SoC
This patch add earlycon support to MT8173 SoC platform. To use earlycon, need 1. Add earlycon in boot parameters 2. Add "linux,sdtout-path" property in device tree file This patch based on 4.1-rc1. Change in v3: Remove noinit options, not necessary, because 8250_early.c will not init hardware if not provide baudrate. Change v2: 1. Add noinit options. 2. Remove duplicate code in 8250_mtk.c, reuse the 8250_early.c existed function. Eddie Huang (3): tty: serial: 8250: export early_serial8250_setup function tty: serial: 8250_mtk: Add earlycon arm64: dts: Add mediatek MT8173 earlycon support arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 +++- drivers/tty/serial/8250/8250_early.c| 2 +- drivers/tty/serial/8250/8250_mtk.c | 13 + include/linux/serial_8250.h | 2 ++ 4 files changed, 19 insertions(+), 2 deletions(-) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/3] tty: serial: 8250: export early_serial8250_setup function
8250-like uart driver may call early_serial8250_setup to
reuse 8250_early.c character output function.
Signed-off-by: Eddie Huang
---
drivers/tty/serial/8250/8250_early.c | 2 +-
include/linux/serial_8250.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_early.c
b/drivers/tty/serial/8250/8250_early.c
index 6c0fd8b..771dda2 100644
--- a/drivers/tty/serial/8250/8250_early.c
+++ b/drivers/tty/serial/8250/8250_early.c
@@ -131,7 +131,7 @@ static void __init init_port(struct earlycon_device *device)
serial8250_early_out(port, UART_LCR, c & ~UART_LCR_DLAB);
}
-static int __init early_serial8250_setup(struct earlycon_device *device,
+int __init early_serial8250_setup(struct earlycon_device *device,
const char *options)
{
if (!(device->port.membase || device->port.iobase))
diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h
index 78097e7..f0c68d8 100644
--- a/include/linux/serial_8250.h
+++ b/include/linux/serial_8250.h
@@ -137,6 +137,8 @@ extern int early_serial_setup(struct uart_port *port);
extern unsigned int serial8250_early_in(struct uart_port *port, int offset);
extern void serial8250_early_out(struct uart_port *port, int offset, int
value);
+extern int early_serial8250_setup(struct earlycon_device *device,
+const char *options);
extern void serial8250_do_set_termios(struct uart_port *port,
struct ktermios *termios, struct ktermios *old);
extern int serial8250_do_startup(struct uart_port *port);
--
1.8.1.1.dirty
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[PATCH v3 0/2] arm64: dts: Mediatek: MT8173 updtes
This series add MT8173 watchdog and I2C device nodes. Both device nodes are based on 4.1-rc1, but I2C need two extra CCF patches from Sascha [1][2]. [1] clk: Add common clock support for Mediatek MT8135 and MT8173 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/338763.html [2] ARM64: dts: mt8173: Add clock controller device nodes http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344753.html Change in v3: Move I2C pin from SoC dtsi to board dts file. Change in v2: Modify I2C device node accroding register address order. Eddie Huang (2): arm64: dts: mt8173: Add watchdog device node arm64: dts: mt8173: Add I2C device node arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 50 ++ arch/arm64/boot/dts/mediatek/mt8173.dtsi| 78 + 2 files changed, 128 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/2] arm64: dts: mt8173: Add I2C device node
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware between 5th and 6th I2C controller. So
SoC designer name 6th controller as "i2c6", not "i2c5".
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 50
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 72 +
2 files changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 43d5401..2e01988 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -33,6 +33,56 @@
chosen { };
};
+&pio {
+ i2c0_pins_a: i2c0@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6@0 {
+ pins1 {
+ pinmux = ,
+;
+ bias-disable;
+ };
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b52ec43..6d3dbbdd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -229,6 +229,78 @@
clocks = <&uart_clk>;
status = "disabled";
};
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c3: i2c3@1101 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x1101 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C3>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c4: i2c4@11011000 {
+ compatible = "mediatek,mt8173-i2c";
+
[PATCH v3 1/2] arm64: dts: mt8173: Add watchdog device node
Add MT8173 watchdog device node.
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 30ac8dd..b52ec43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -160,6 +160,12 @@
;
};
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8173-wdt",
+"mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
--
1.8.1.1.dirty
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Re: [PATCH v3 2/2] arm64: dts: mt8173: Add I2C device node
Hi Dan,
On Fri, 2015-06-12 at 20:28 +0800, Daniel Kurtz wrote:
> On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang wrote:
> >
> > Add MT8173 I2C device nodes, include I2C controllers and pins.
> > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> > The 6th I2C controller register base doesn't next to 5th I2C,
> > and there is a hardware between 5th and 6th I2C controller. So
> > SoC designer name 6th controller as "i2c6", not "i2c5".
>
>
> This is slightly misleading. There are in fact 7 I2C controllers, but
> "i2c5" is dedicated for use by HDMI for ddc & hdcp.
> Is there a reason why the HDMI I2C port cannot be controlled by the
> generic i2c driver?
>
We add some extra HW function to HDMI I2C port, we have special driver
to control this HW, not generic I2C driver. This is why I don't count
this hardware to generic I2C controllers.
> Of course the hdmiddc / i2c5 node can always be added in a later
> patch, so this is no reason to hold up this patch.
>
> > Signed-off-by: Eddie Huang
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 50
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi| 72
> > +
> > 2 files changed, 122 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > index 43d5401..2e01988 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > @@ -33,6 +33,56 @@
> > chosen { };
> > };
> >
> > +&pio {
>
> I don't think we needed to move these i2c pinmux descriptions from
> mt8173.dtsi to the board .dts file.
>
> AFAICT, the "i2cN_pins_a" nodes defined here are the pinctl
> configuration that the corresponding enabled i2c nodes would choose.
> Thus, they are generic to the MT8173 SoC, not specific to any board.
> By themselves, these nodes do not actually select a pin configuration.
>
> It is the nodes that *enable* the individual i2c nodes, and hence
> activate those pin settings, which is board specific.
>
> Hence, if your intent is to have the evb enable all i2c nodes, it
> would have a set of nodes like this:
>
>
> &i2c0 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c0_pins_a>;
> status = "okay";
> };
>
> &i2c1 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c1_pins_a>;
> status = "okay";
> };
>
> ...
>
I personally think put I2C pins in SoC dtsi is ok because it is basic
and fixed. Almost every platform need these pins, so not necessary to
care about dtb size. And these pins are fixed. We put pins that may
change by platforms to board dts, like mmc.
>
> > + i2c0_pins_a: i2c0@0 {
>
> Do these nodes need the "@0"?
>
Will remove.
> >
> > + pins1 {
> > + pinmux = ,
> > +;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c1_pins_a: i2c1@0 {
> > + pins1 {
> > + pinmux = ,
> > +;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c2_pins_a: i2c2@0 {
> > + pins1 {
> > + pinmux = ,
> > +;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c3_pins_a: i2c3@0 {
> > + pins1 {
> > + pinmux = ,
> > +;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c4_pins_a: i2c4@0 {
> > + pins1 {
> > + pinmux = ,
> > +;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c6_pins_a: i2c6@0 {
> > + pins1 {
> > + pinmux = ,
> > +;
>
> These are the SDA/SCL pins for i2c port 6, so they should really be
> _SDA6 / _SCL6.
> However... I checked, and these settings are labeled "SDA5 & SCL5" in
> the datasheet.
> I recommend marking them correctly as 6 here and fixing the datasheet :-).
>
We make mista
Re: [PATCH v3 2/2] arm64: dts: mt8173: Add I2C device node
Hi Sascha,
On Mon, 2015-06-15 at 08:12 +0200, Sascha Hauer wrote:
> On Fri, Jun 12, 2015 at 08:28:51PM +0800, Daniel Kurtz wrote:
> > On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang
> > wrote:
> > >
> > > Add MT8173 I2C device nodes, include I2C controllers and pins.
> > > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> > > The 6th I2C controller register base doesn't next to 5th I2C,
> > > and there is a hardware between 5th and 6th I2C controller. So
> > > SoC designer name 6th controller as "i2c6", not "i2c5".
> >
> >
> > This is slightly misleading. There are in fact 7 I2C controllers, but
> > "i2c5" is dedicated for use by HDMI for ddc & hdcp.
> > Is there a reason why the HDMI I2C port cannot be controlled by the
> > generic i2c driver?
> >
> > Of course the hdmiddc / i2c5 node can always be added in a later
> > patch, so this is no reason to hold up this patch.
> >
> > > Signed-off-by: Eddie Huang
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 50
> > > arch/arm64/boot/dts/mediatek/mt8173.dtsi| 72
> > > +
> > > 2 files changed, 122 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > > b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > > index 43d5401..2e01988 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> > > @@ -33,6 +33,56 @@
> > > chosen { };
> > > };
> > >
> > > +&pio {
> >
> > I don't think we needed to move these i2c pinmux descriptions from
> > mt8173.dtsi to the board .dts file.
> >
> > AFAICT, the "i2cN_pins_a" nodes defined here are the pinctl
> > configuration that the corresponding enabled i2c nodes would choose.
> > Thus, they are generic to the MT8173 SoC, not specific to any board.
> > By themselves, these nodes do not actually select a pin configuration.
>
> On i.MX we started with i2cN_pins_[abcde] groups in the SoC dtsi file
> aswell. At some point we realized that this does not scale anymore.
> The problems were:
>
> - Whenever a new board came along which needed some pin setting which
> didn't already exist a new group was created in the SoC dtsi file using
> the next free letter from the alphabet. The ordering of the group names
> was rather arbitrary and often enough there were merge conflicts to
> resolve when during one merge window two new boards showed up which both
> added i2cN_pin_x with different content.
> - When a new board needs the same pins but with different drive strength
> settings a new group was required
> - With SD/MMC we had groups for 4bit data, groups adding the remaining
> pins for 8bit data
> - With UARTs we had groups for RX/TX and additionally groups adding
> RTS/CTS
> - For graphics we had groups for 16bit data and 24bit data
> - There is no way to remove the unused nodes from the binary dtb, so
> every board contained all existing pingroups for every other board,
> so the dtbs became quite big
>
> So with only a few existing boards with very similar pinmux groups
> it may work fine to put the groups into the SoC dtsi, but this way
> may also explode quite fast with more and different boards.
> I don't know how much variation there will be with Mediatek boards, so
> I'm fine with either way. You may want to look at:
>
> 5a2a7d5 ARM: dts: imx51: make pinctrl nodes board specific
> 7ac0f70 ARM: dts: imx53: make pinctrl nodes board specific
> 817c27a ARM: dts: imx6qdl: make pinctrl nodes board specific
>
We tend to put basic and fixed pins in SoC dtsi, platform-variant pins
to board dts.Since these pins already move once, I hope we reach a
consensus that I put i2c pins back to SoC dtsi.
Eddie
Thanks
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Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
Hi Mark, On Wed, 2015-06-10 at 16:06 +0800, Eddie Huang wrote: > On Tue, 2015-06-09 at 11:39 +0100, Mark Brown wrote: > > On Tue, Jun 09, 2015 at 06:05:21PM +0800, Eddie Huang wrote: > > > > > --- a/drivers/spi/spi.c > > > +++ b/drivers/spi/spi.c > > > @@ -539,8 +539,8 @@ static int __spi_map_msg(struct spi_master *master, > > > struct spi_message *msg) > > > if (!master->can_dma) > > > return 0; > > > > > - tx_dev = master->dma_tx->device->dev; > > > - rx_dev = master->dma_rx->device->dev; > > > + tx_dev = master->dma_tx ? master->dma_tx->device->dev : > > > master->dev; > > > + rx_dev = master->dma_rx ? master->dma_rx->device->dev : master- > > > > > Is this what you want ? Actually, I don't like first one at all. > > > > Not quite what I'd been thinking of - we can't just pick the device in > > the core safely, the device might be a MFD or have some other > > restriction that needs us to use a separate struct device. However most > > of those cases are likely to point towards implementing a dmaengine > > device so probably the above will work for most cases and is fine. Can > > you send a proper patch please? > After further investigate, we found problem when use can_dma() to implement spi driver. If can_dma() return true in __spi_map_msg() function, it will map data buffer to sg_table, then pass this sg_table to transfer function. In transfer function, spi hardware can do tx and rx at the same time (full duplex), and the data size must be the same. Here comes the problem, although total length of tx, rx is the same, each entry in rx and tx scatterlist may not be the same (in the case data buffer allocate from vmalloc). Other vendor have dmaengine driver to send entry-by-entry automatically, so it is ok due to total length is the same.But mediatek hw can only send tx and rx scatterlist entry one by on, which means in full duplex, mediatek SPI hardware need send each entry separately, will cause full duplex fail because tx/rx entry size or entry number may not be the same. The problem is not dma map discuss earlier, it is mediatek spi hardware limitation that can't support scatterlist dma transfer in full-duplex mode. We can only support both tx and rx has the same size continuous memory data in full-duplex mode. I don't know whether should modify spi.c to support mediatek spi, or we just return can_dma() false and do transfer one continuous data in transfer function. By the way, I think maybe it is better to change can_dma() to can_dma_sg(). Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
On Wed, 2015-06-17 at 13:47 +0100, Mark Brown wrote: > On Wed, Jun 17, 2015 at 05:08:03PM +0800, Eddie Huang wrote: > > > Here comes the problem, although total length of tx, rx is the same, > > each entry in rx and tx scatterlist may not be the same (in the case > > data buffer allocate from vmalloc). Other vendor have dmaengine driver > > to send entry-by-entry automatically, so it is ok due to total length is > > the same.But mediatek hw can only send tx and rx scatterlist entry one > > by on, which means in full duplex, mediatek SPI hardware need send each > > entry separately, will cause full duplex fail because tx/rx entry size > > or entry number may not be the same. > > I don't see why this is a problem - your driver is going to have to do > more work to overcome the limitations of the hardware but surely it's > just a question of how you parse the scatterlists (or rewriting them if > that's appropriate)? > > > The problem is not dma map discuss earlier, it is mediatek spi hardware > > limitation that can't support scatterlist dma transfer in full-duplex > > mode. We can only support both tx and rx has the same size continuous > > memory data in full-duplex mode. I don't know whether should modify > > spi.c to support mediatek spi, or we just return can_dma() false and do > > transfer one continuous data in transfer function. > > > By the way, I think maybe it is better to change can_dma() to So > > can_dma_sg(). > > Don't you just need to handle the scatterlists in page sized chunks > here? There's nothing about passing information about the memory that > was mapped around in a scatterlist that means you have to pass the whole > list to the hardware at once - at heart the scatterlist is just a > convenient structure for passing around where the data to be transferred > is. Our hardware limitation is: we don't have separate dma tx, rx channel with transfer finish interrupt, only have spi trigger operation.So the mediatek SPI dma full duplex operation steps are: 1. Set TX DMA address. 2. Set RX DMA address. 3. Set length (this step assume TX, RX are the same size). 4. Set TX DMA enable, RX DMA enable bit in spi config register. (not trigger DMA, just told spi use dma) 5. Trigger spi operations. 6. Wait spi operations finish interrupt. If tx scatterlist per list data size are 128, 4096, 256. rx scatterlist per list data size are 128, 4096, 256. So we need to go through above steps three times. If tx scatterlists per list data size are 128, 4096, 256. rx scatterlists per list data size are 256, 4096, 128. If we start sending first entry, tx size is 128, rx size is 256, this will cause hardware malfunction because tx, rx data length are not the same. The solution I think is copy scatterlist data into one single buffer in mediatek spi transfer function, but I think this is odd because __spi_map_msg() map single buffer into scatterlist, then our driver map scatterlist into single buffer again. I hope this explaination is more clear than before. Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/2] arm64: dts: Mediatek: MT8173 updtes
This series add MT8173 watchdog and I2C device nodes. Both device nodes are based on 4.1-rc1, but I2C need two extra CCF patches from Sascha [1][2]. [1] clk: Add common clock support for Mediatek MT8135 and MT8173 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/338763.html [2] ARM64: dts: mt8173: Add clock controller device nodes http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344753.html Change in v4: Move I2C pin from board dts file back to SoC dtsi file after discussion. Add I2C default pin, address, size cell number in I2C controller node. But not clock-frequency because it is optional. (default value is 100) Change in v3: Move I2C pin from SoC dtsi to board dts file. Change in v2: Modify I2C device node accroding register address order. Eddie Huang (2): arm64: dts: mt8173: Add watchdog device node arm64: dts: mt8173: Add I2C device node arch/arm64/boot/dts/mediatek/mt8173.dtsi | 150 +++ 1 file changed, 150 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/2] arm64: dts: mt8173: Add I2C device node
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware between 5th and 6th I2C controller. So
SoC designer name 6th controller as "i2c6", not "i2c5".
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 144 +++
1 file changed, 144 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b52ec43..1816c8f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -158,6 +158,54 @@
interrupts = ,
,
;
+
+ i2c0_pins_a: i2c0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
};
watchdog: watchdog@10007000 {
@@ -229,6 +277,102 @@
clocks = <&uart_clk>;
status = "disabled";
};
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+<&per
[PATCH v4 1/2] arm64: dts: mt8173: Add watchdog device node
Add MT8173 watchdog device node.
Signed-off-by: Eddie Huang
Reviewed-by: Daniel Kurtz
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 30ac8dd..b52ec43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -160,6 +160,12 @@
;
};
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8173-wdt",
+"mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
--
1.8.1.1.dirty
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[PATCH] arm64: dts: mt8173: add clock_null
Add clk_null, which represents clocks that can not / need not
controlled by software.
There are many clocks' parent set to clk_null.
Signed-off-by: James Liao
Signed-off-by: Eddie Huang
---
Base on 4.1-rc1
Change-Id: I4db9b40d07e28f54f7bae9b676316cbd6a962124
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6..4798f44 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -81,6 +81,12 @@
cpu_on= <0x8403>;
};
+ clk_null: clk_null {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ #clock-cells = <0>;
+ };
+
uart_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <2600>;
--
1.8.1.1.dirty
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Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
On Wed, 2015-06-17 at 17:35 +0100, Mark Brown wrote: > On Wed, Jun 17, 2015 at 10:10:51PM +0800, Eddie Huang wrote: > > > Our hardware limitation is: we don't have separate dma tx, rx channel > > with transfer finish interrupt, only have spi trigger operation.So the > > mediatek SPI dma full duplex operation steps are: > > 1. Set TX DMA address. > > 2. Set RX DMA address. > > 3. Set length (this step assume TX, RX are the same size). > > 4. Set TX DMA enable, RX DMA enable bit in spi config register. (not > > trigger DMA, just told spi use dma) > > 5. Trigger spi operations. > > 6. Wait spi operations finish interrupt. > > Sure, that's what I understood. > > > If tx scatterlist per list data size are 128, 4096, 256. rx scatterlist > > per list data size are 128, 4096, 256. So we need to go through above > > steps three times. If tx scatterlists per list data size are 128, 4096, > > 256. rx scatterlists per list data size are 256, 4096, 128. If we start > > sending first entry, tx size is 128, rx size is 256, this will cause > > hardware malfunction because tx, rx data length are not the same. > > > The solution I think is copy scatterlist data into one single buffer in > > mediatek spi transfer function, but I think this is odd because > > __spi_map_msg() map single buffer into scatterlist, then our driver map > > scatterlist into single buffer again. I hope this explaination is more > > clear than before. > > To repeat what I said in my last mail: there's no need to use the > scatterlists as-is, your driver can do whatever set of DMA transfers it > likes to keep the lengths of each transfer the same. Attempting to > linearise the transfers in memory isn't going to work unless you > allocate physically contiguous memory (which could get painful) and will > add substantial overhead. > > For example with your above example you could split the transfers up to > be 128, 128, 3968, 128, 128. This is a workable way. Thanks your suggestion.We will try to implement this, Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
Hi Mark, On Fri, 2015-05-15 at 17:25 +0800, Mark Brown wrote: > On Fri, May 15, 2015 at 03:38:42PM +0800, leilk liu wrote: > > On Tue, 2015-05-12 at 17:05 +0100, Mark Brown wrote: > > > > Implement can_dma() - look for drivers providing that for examples. > > > MTK spi hardware uses the dmaengine in spi controller. According to > > datasheet, spi driver just need to enable dma register bit and write a > > physical address to relevant dma address register, so I think it may be > > complex while the driver supports can_dma. > > That's how a very large proportion of devices that work with DMA are > done - why would this be complicated? All can_dma() does is report if > DMA is possible. In include/linux/spi/spi.h, it describes if can_dma() exists and returns true, dma_tx and dma_rx must be set.But Medaitek SPI controller has its own dma hardware, which means this dma resides in the same base address range with SPI controller, and only used by SPI, so we don't implement generic DMA driver, such that can't provide dma channel and assign to dmx_tx, dmx_rx parameter. We think it's strange to implement generic dma driver for dma that only used by specific hardware.Can we just provide can_dma() function and return false ? But I think it's a little odd that there actually has dma. So can we just skip can_dma() function let it be NULL ? Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node
Hi Sascha,
On Mon, 2015-06-08 at 09:27 +0200, Sascha Hauer wrote:
> Hi Eddie,
>
> On Mon, Jun 01, 2015 at 09:08:27PM +0800, Eddie Huang wrote:
> > Add MT8173 I2C device nodes, include I2C controllers and pins.
> > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> > The 6th I2C controller register base doesn't next to 5th I2C,
> > and there is a hardware between 5th and 6th I2C controller. So
> > SoC designer name 6th controller as "i2c6", not "i2c5".
> >
> > Signed-off-by: Eddie Huang
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119
> > +++
> > 1 file changed, 119 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index b52ec43..7003ed2 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -158,6 +158,53 @@
> > interrupts = ,
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > IRQ_TYPE_LEVEL_HIGH>;
> > + i2c0_pins_a: i2c0@0 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
>
> The pinmux nodes should be in the board dts, not in the SoC dtsi.
>
These pins are fixed, and all boards using MT8173 SoC I2C controller
should use these pins. To reduce spread these to many board dts files,
so I put i2c pins in SoC dtsi.
Eddie
Thanks
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[PATCH 2/2] arm64: dts: mt8173: Add I2C device node
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware between 5th and 6th I2C controller. So
SoC designer name 6th controller as "i2c6", not "i2c5".
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b52ec43..72d9ab1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -158,6 +158,53 @@
interrupts = ,
,
;
+ i2c0_pins_a: i2c0@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
};
watchdog: watchdog@10007000 {
@@ -194,6 +241,78 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c3: i2c3@1101 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x1101 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = ;
+
[PATCH 0/2] arm64: dts: Mediatek: MT8173 updtes
This series add MT8173 watchdog and I2C device nodes. Both device nodes are based on 4.1-rc1, but I2C need two extra CCF patches from Sascha [1][2]. [1] clk: Add common clock support for Mediatek MT8135 and MT8173 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/338763.html [2] ARM64: dts: mt8173: Add clock controller device nodes http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344753.html Eddie Huang (2): arm64: dts: mt8173: Add watchdog device node arm64: dts: mt8173: Add I2C device node arch/arm64/boot/dts/mediatek/mt8173.dtsi | 125 +++ 1 file changed, 125 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] arm64: dts: mt8173: Add watchdog device node
Add MT8173 watchdog device node.
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 30ac8dd..b52ec43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -160,6 +160,12 @@
;
};
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8173-wdt",
+"mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
--
1.8.1.1.dirty
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[PATCH v2 1/2] arm64: dts: mt8173: Add watchdog device node
Add MT8173 watchdog device node.
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 30ac8dd..b52ec43 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -160,6 +160,12 @@
;
};
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8173-wdt",
+"mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
--
1.8.1.1.dirty
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[PATCH v2 2/2] arm64: dts: mt8173: Add I2C device node
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware between 5th and 6th I2C controller. So
SoC designer name 6th controller as "i2c6", not "i2c5".
Signed-off-by: Eddie Huang
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 119 +++
1 file changed, 119 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index b52ec43..7003ed2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -158,6 +158,53 @@
interrupts = ,
,
;
+ i2c0_pins_a: i2c0@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins_a: i2c3@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins_a: i2c4@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
+
+ i2c6_pins_a: i2c6@0 {
+ pins1 {
+ pinmux =
,
+
;
+ bias-disable;
+ };
+ };
};
watchdog: watchdog@10007000 {
@@ -229,6 +276,78 @@
clocks = <&uart_clk>;
status = "disabled";
};
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000100 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000180 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = ;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+<&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ status = "disabled";
+ };
+
+ i2c3: i2c3@1101 {
+ compatible = "mediatek,mt8173-i2c";
+ reg = <0 0x1101 0 0x70>,
+ <0 0x11000280 0 0x80&
[PATCH v2 0/2] arm64: dts: Mediatek: MT8173 updtes
This series add MT8173 watchdog and I2C device nodes. Both device nodes are based on 4.1-rc1, but I2C need two extra CCF patches from Sascha [1][2]. [1] clk: Add common clock support for Mediatek MT8135 and MT8173 http://lists.infradead.org/pipermail/linux-arm-kernel/2015-April/338763.html [2] ARM64: dts: mt8173: Add clock controller device nodes http://lists.infradead.org/pipermail/linux-arm-kernel/2015-May/344753.html Change in v2: Modify I2C device node accroding register address order. Eddie Huang (2): arm64: dts: mt8173: Add watchdog device node arm64: dts: mt8173: Add I2C device node arch/arm64/boot/dts/mediatek/mt8173.dtsi | 125 +++ 1 file changed, 125 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
Hi Mark,
On Mon, 2015-06-08 at 18:59 +0100, Mark Brown wrote:
> On Mon, Jun 08, 2015 at 06:15:46PM +0800, Eddie Huang wrote:
> > On Fri, 2015-05-15 at 17:25 +0800, Mark Brown wrote:
>
> > > That's how a very large proportion of devices that work with DMA are
> > > done - why would this be complicated? All can_dma() does is report if
> > > DMA is possible.
>
> > In include/linux/spi/spi.h, it describes if can_dma() exists and returns
> > true, dma_tx and dma_rx must be set.But Medaitek SPI controller has its
> > own dma hardware, which means this dma resides in the same base address
> > range with SPI controller, and only used by SPI, so we don't implement
> > generic DMA driver, such that can't provide dma channel and assign to
> > dmx_tx, dmx_rx parameter. We think it's strange to implement generic dma
> > driver for dma that only used by specific hardware.Can we just provide
> > can_dma() function and return false ? But I think it's a little odd that
> > there actually has dma. So can we just skip can_dma() function let it be
> > NULL ?
>
> If it's simply the unavailbility of a struct dma_chan we must be able to
> get a better solution than just open coding all the DMA mapping and
> unmapping in the driver. The only thing we actually use the channel for
> is to get the device we need to use to do the mapping and unmapping,
> either we need a way for devices to provide their own channels easily or
> a way for SPI drivers to specify a device here instead of a channel.
> The latter seems easier if a bit clunky (with having to work with both).
I list two ways you mention.
Pesudo code of your first suggestion:
static int mtk_spi_probe(struct platform_device *pdev) {
struct dma_chan *tx_chan;
struct dma_device *tx_dma;
tx_chan = devm_kzalloc(&pdev->dev, sizeof(*tx_chan), GFP_KERNEL);
tx_dma = devm_kzalloc(&pdev->dev, sizeof(*tx_dma), GFP_KERNEL);
tx_dma->dev = &pdev->dev;
tx_chan->device = tx_dma;
master->dma_tx = tx_chan;
...
}
Modification of your second suggestion:
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -539,8 +539,8 @@ static int __spi_map_msg(struct spi_master *master,
struct spi_message *msg)
if (!master->can_dma)
return 0;
- tx_dev = master->dma_tx->device->dev;
- rx_dev = master->dma_rx->device->dev;
+ tx_dev = master->dma_tx ? master->dma_tx->device->dev :
master->dev;
+ rx_dev = master->dma_rx ? master->dma_rx->device->dev : master-
Is this what you want ? Actually, I don't like first one at all.
Eddie
Thanks
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Re: [PATCH 2/3] spi: mediatek: Add spi bus for Mediatek MT8173
Hi Mark, On Tue, 2015-06-09 at 11:39 +0100, Mark Brown wrote: > On Tue, Jun 09, 2015 at 06:05:21PM +0800, Eddie Huang wrote: > > > --- a/drivers/spi/spi.c > > +++ b/drivers/spi/spi.c > > @@ -539,8 +539,8 @@ static int __spi_map_msg(struct spi_master *master, > > struct spi_message *msg) > > if (!master->can_dma) > > return 0; > > > - tx_dev = master->dma_tx->device->dev; > > - rx_dev = master->dma_rx->device->dev; > > + tx_dev = master->dma_tx ? master->dma_tx->device->dev : > > master->dev; > > + rx_dev = master->dma_rx ? master->dma_rx->device->dev : master- > > > Is this what you want ? Actually, I don't like first one at all. > > Not quite what I'd been thinking of - we can't just pick the device in > the core safely, the device might be a MFD or have some other > restriction that needs us to use a separate struct device. However most > of those cases are likely to point towards implementing a dmaengine > device so probably the above will work for most cases and is fine. Can > you send a proper patch please? Sure, we will send this with new MTK SPI driver, such that can verify it. > > Please don't use the ternery operator, though. OK, will fix it Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 2/2] arm64: dts: mt8173: Add I2C device node
Hi Dan,
On Thu, 2015-06-18 at 23:16 +0800, Daniel Kurtz wrote:
> On Wed, Jun 17, 2015 at 11:08 PM, Eddie Huang
> wrote:
> > Add MT8173 I2C device nodes, include I2C controllers and pins.
> > MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> > The 6th I2C controller register base doesn't next to 5th I2C,
> > and there is a hardware between 5th and 6th I2C controller. So
> > SoC designer name 6th controller as "i2c6", not "i2c5".
> >
> > Signed-off-by: Eddie Huang
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 144
> > +++
> > 1 file changed, 144 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index b52ec43..1816c8f 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -158,6 +158,54 @@
> > interrupts = ,
> > > IRQ_TYPE_LEVEL_HIGH>,
> > > IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + i2c0_pins_a: i2c0 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c1_pins_a: i2c1 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c2_pins_a: i2c2 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c3_pins_a: i2c3 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c4_pins_a: i2c4 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > +
> > + i2c6_pins_a: i2c6 {
> > + pins1 {
> > + pinmux =
> > ,
> > +
> > ;
> > + bias-disable;
> > + };
> > + };
> > };
> >
> > watchdog: watchdog@10007000 {
> > @@ -229,6 +277,102 @@
> > clocks = <&uart_clk>;
> > status = "disabled";
> > };
> > +
> > + i2c0: i2c@11007000 {
> > + compatible = "mediatek,mt8173-i2c";
> > + reg = <0 0x11007000 0 0x70>,
> > + <0 0x11000100 0 0x80>;
> > + interrupts = ;
> > + clock-div = <16>;
>
> According to the i2c-mt6577 dt binding:
>- clock-div: the fixed value for frequency divider of clock source in i2c
> module. Each IC may be different.
>
> For other drivers I've seen this kind of hardware-specific value
> implemented as a table in the driver that is indexed based on the
> compatible.
>
> Any particular reason to specify it here in every device tree node instead?
>
If put in device tree, it is not necessary to add new compatible if new
SoC has the same I2C controller hardware except clock-div.The benefit is
keep driver clean, but the side-effect is add clock-div in device node.I
assume clock-div has the same concept of clock, so I put in device tree.
Eddie
Thanks
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[PATCH 0/3] tty: serial: Add mediatek MT8127 and MT8135 UART support
This patch base on 3.18-rc1, which include mediatek MT65XX SOC UART driver developed by Matthias Brugger, and Joe.C's Mediatek MT8127 & MT8135 basic SOC support patch[1]. This patch fix one 8250_mtk.c bug that divisor maybe zero, and add device tree support. Test ok on MT8127 and MT8135 tablet platform. Eddie Huang (3): tty: serial: Fix mediatek UART driver setting baudrate issue ARM: mediatek: add UART dts for mt8127 and mt8135 DTS: serial: Add bindings document for the Mediatek UARTs .../devicetree/bindings/serial/mtk-uart.txt| 2 ++ arch/arm/boot/dts/mt8127.dtsi | 34 arch/arm/boot/dts/mt8135.dtsi | 36 ++ drivers/tty/serial/8250/8250_mtk.c | 4 +-- 4 files changed, 74 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/3] tty: serial: Fix mediatek UART driver setting baudrate issue
In mtk8250_set_termios function, calculating quot value can not be zero,
otherwise, using DIV_ROUND_CLOSEST(port->uartclk, quot * baud) will fail due to
divisor is zero.
Signed-off-by: Eddie Huang
---
drivers/tty/serial/8250/8250_mtk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_mtk.c
b/drivers/tty/serial/8250/8250_mtk.c
index 8f37d57..6f93123 100644
--- a/drivers/tty/serial/8250/8250_mtk.c
+++ b/drivers/tty/serial/8250/8250_mtk.c
@@ -74,14 +74,14 @@ mtk8250_set_termios(struct uart_port *port, struct ktermios
*termios,
/* Set to next lower baudrate supported */
if ((baud == 50) || (baud == 576000))
baud = 460800;
- quot = DIV_ROUND_CLOSEST(port->uartclk, 4 * baud);
+ quot = DIV_ROUND_UP(port->uartclk, 4 * baud);
} else {
serial_port_out(port, UART_MTK_HIGHS, 0x3);
/* Set to highest baudrate supported */
if (baud >= 1152000)
baud = 921600;
- quot = DIV_ROUND_CLOSEST(port->uartclk, 256 * baud);
+ quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
}
/*
--
1.8.1.1.dirty
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[PATCH 3/3] DTS: serial: Add bindings document for the Mediatek UARTs
This patch add s devicetree document for Mediatek UART. Signed-off-by: Eddie Huang --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 48358a3..0eebbfe 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -2,6 +2,8 @@ Required properties: - compatible should contain: + * "mediatek,mt8135-uart" for MT8135 compatible UARTS + * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/3] ARM: mediatek: add UART dts for mt8127 and mt8135
This add dts support for mt8127 and mt8135 SOC UART
Signed-off-by: Eddie Huang
---
arch/arm/boot/dts/mt8127.dtsi | 34 ++
arch/arm/boot/dts/mt8135.dtsi | 36
2 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index 25c9f69..249c218 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -64,6 +64,12 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ #clock-cells = <0>;
+};
};
soc {
@@ -89,5 +95,33 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11006000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11007000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11008000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11009000 {
+ compatible =
"mediatek,mt8127-uart","mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
};
};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..683b761 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -86,6 +86,13 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <2600>;
+ #clock-cells = <0>;
+ };
+
};
soc {
@@ -111,5 +118,34 @@
<0 0x10214000 0 0x2000>,
<0 0x10216000 0 0x2000>;
};
+
+ uart0: serial@11006000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11006000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart1: serial@11007000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11007000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart2: serial@11008000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11008000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
+ uart3: serial@11009000 {
+ compatible =
"mediatek,mt8135-uart","mediatek,mt6577-uart";
+ reg = <0 0x11009000 0 0x400>;
+ interrupts = ;
+ clocks = <&uart_clk>;
+ };
+
};
};
--
1.8.1.1.dirty
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Re: [PATCH RESEND] tty: serial: 8250_mtk: Fix quot calculation
On Fri, 2014-10-31 at 17:48 +0100, Arnd Bergmann wrote: > On Friday 31 October 2014 17:36:35 Matthias Brugger wrote: > > - quot = DIV_ROUND_CLOSEST(port->uartclk, 256 * baud); > > + quot = (port->uartclk / (256 * baud)) + 1; > > Should this be DIV_ROUND_UP then? > > Arnd > I think DIV_ROUND_UP is more suitable in this case, and I already do this and test OK on my MTK platform http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296149.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] watchdog: add wdt suspend/resume support
On Tue, 2015-07-21 at 20:45 -0700, Guenter Roeck wrote:
> On 07/21/2015 08:26 PM, Eddie Huang wrote:
> > From: Greta Zhang
> >
> > add wdt driver suspend/resume support
> >
> > Signed-off-by: Greta Zhang
> > Signed-off-by: Roger Lu
> > Signed-off-by: Eddie Huang
> > ---
> > drivers/watchdog/mtk_wdt.c | 38 ++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
> > index 938b987..5ef3910 100644
> > --- a/drivers/watchdog/mtk_wdt.c
> > +++ b/drivers/watchdog/mtk_wdt.c
> > @@ -65,6 +65,7 @@ struct mtk_wdt_dev {
> > struct watchdog_device wdt_dev;
> > void __iomem *wdt_base;
> > struct notifier_block restart_handler;
> > + bool started;
>
> Any reason why you can not use watchdog_active() ?
Will change to use watchdog_active()
>
> > };
> >
> > static int mtk_reset_handler(struct notifier_block *this, unsigned long
> > mode,
> > @@ -125,6 +126,8 @@ static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
> > reg &= ~WDT_MODE_EN;
> > iowrite32(reg, wdt_base + WDT_MODE);
> >
> > + mtk_wdt->started = false;
> > +
> > return 0;
> > }
> >
> > @@ -135,6 +138,8 @@ static int mtk_wdt_start(struct watchdog_device
> > *wdt_dev)
> > void __iomem *wdt_base = mtk_wdt->wdt_base;
> > int ret;
> >
> > + mtk_wdt->started = true;
> > +
> > ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
> > if (ret < 0)
> > return ret;
> > @@ -174,6 +179,8 @@ static int mtk_wdt_probe(struct platform_device *pdev)
> >
> > platform_set_drvdata(pdev, mtk_wdt);
> >
> > + mtk_wdt->started = false;
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > mtk_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
> > if (IS_ERR(mtk_wdt->wdt_base))
> > @@ -221,6 +228,35 @@ static int mtk_wdt_remove(struct platform_device *pdev)
> > return 0;
> > }
> >
> > +#ifdef CONFIG_PM
> > +static int mtk_wdt_suspend(struct platform_device *pdev, pm_message_t
> > state)
> > +{
> > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
> > +
> > + if (mtk_wdt->started) {
> > + mtk_wdt_stop(&mtk_wdt->wdt_dev);
> > + mtk_wdt->started = true;
>
> ?
>
Because mtk_wdt_stop() change mtk_wdt->started to false, so set
mtk_wdt->started back to true here. This code is not necessary if use
watchdog_active()
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_wdt_resume(struct platform_device *pdev)
> > +{
> > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
> > +
> > + if (mtk_wdt->started) {
> > + mtk_wdt_start(&mtk_wdt->wdt_dev);
> > + mtk_wdt_ping(&mtk_wdt->wdt_dev);
> > + }
> > +
> > + return 0;
> > +}
> > +#else
> > +#definemtk_wdt_suspend NULL
> > +#definemtk_wdt_resume NULL
> > +#endif
> > +
> > static const struct of_device_id mtk_wdt_dt_ids[] = {
> > { .compatible = "mediatek,mt6589-wdt" },
> > { /* sentinel */ }
> > @@ -230,6 +266,8 @@ MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
> > static struct platform_driver mtk_wdt_driver = {
> > .probe = mtk_wdt_probe,
> > .remove = mtk_wdt_remove,
> > + .suspend= mtk_wdt_suspend,
> > + .resume = mtk_wdt_resume,
> > .driver = {
> > .name = DRV_NAME,
> > .of_match_table = mtk_wdt_dt_ids,
>
> Typically drivers would use struct dev_pm_ops and
> .pm = &mtk_wdt_pm_ops,
>
> Any reason for not using the same mechanism ?
>
Will change to use dev_pm_ops
Eddie
Thanks
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[PATCH v2 1/2] watchdog: add wdt suspend/resume support
From: Greta Zhang
add wdt driver suspend/resume support
Signed-off-by: Greta Zhang
Signed-off-by: Roger Lu
Signed-off-by: Eddie Huang
---
drivers/watchdog/mtk_wdt.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 938b987..056412c 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -221,17 +221,47 @@ static int mtk_wdt_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int mtk_wdt_suspend(struct device *dev)
+{
+ struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev))
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+
+ return 0;
+}
+
+static int mtk_wdt_resume(struct device *dev)
+{
+ struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev)) {
+ mtk_wdt_start(&mtk_wdt->wdt_dev);
+ mtk_wdt_ping(&mtk_wdt->wdt_dev);
+ }
+
+ return 0;
+}
+#endif
+
static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt6589-wdt" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
+static const struct dev_pm_ops mtk_wdt_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
+ mtk_wdt_resume)
+};
+
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
.driver = {
.name = DRV_NAME,
+ .pm = &mtk_wdt_pm_ops,
.of_match_table = mtk_wdt_dt_ids,
},
};
--
1.8.1.1.dirty
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[PATCH v2 0/2] Add Mediatek watchdog suspend resume and shutdown
This series add Mediatek watchdog suspend, resume and shutdown support. These patches are based on v4.2-rc1 Change in v2: Use watchdog_active() to check whether watchdog been active. Change to register suspend,resume function to dev_pm_ops Greta Zhang (2): watchdog: add wdt suspend/resume support watchdog: add wdt shutdown callback to disable wdt if enabled drivers/watchdog/mtk_wdt.c | 39 +++ 1 file changed, 39 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/2] watchdog: add wdt shutdown callback to disable wdt if enabled
From: Greta Zhang
Without .shutdown(), watchdog might reset the system during power off.
For example, if watchdog's timeout is set to 30s, then it is reset to
zero by mtk_wdt_ping(). During power off, no app will ping watchdog,
but watchdog is still running and may trigger reset.
Signed-off-by: Greta Zhang
Signed-off-by: Eddie Huang
---
drivers/watchdog/mtk_wdt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 056412c..6ad9df9 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -210,6 +210,14 @@ static int mtk_wdt_probe(struct platform_device *pdev)
return 0;
}
+static void mtk_wdt_shutdown(struct platform_device *pdev)
+{
+ struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev))
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+}
+
static int mtk_wdt_remove(struct platform_device *pdev)
{
struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
@@ -259,6 +267,7 @@ static const struct dev_pm_ops mtk_wdt_pm_ops = {
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
+ .shutdown = mtk_wdt_shutdown,
.driver = {
.name = DRV_NAME,
.pm = &mtk_wdt_pm_ops,
--
1.8.1.1.dirty
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[PATCH] soc: mediatek: add scpsys support active_wakeup
Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.
Signed-off-by: Chunfeng Yun
Signed-off-by: Eddie Huang
---
drivers/soc/mediatek/mtk-scpsys.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 43a79ed..fc78b70 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -67,6 +67,7 @@ struct scp_domain_data {
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
enum clk_id clk_id;
+ bool active_wakeup;
};
static const struct scp_domain_data scp_domain_data[] __initconst = {
@@ -77,6 +78,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = MT8173_CLK_MM,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_VENC] = {
.name = "venc",
@@ -85,6 +87,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_MM,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_ISP] = {
.name = "isp",
@@ -93,6 +96,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = MT8173_CLK_MM,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_MM] = {
.name = "mm",
@@ -101,6 +105,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.clk_id = MT8173_CLK_MM,
+ .active_wakeup = false,
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
MT8173_TOP_AXI_PROT_EN_MM_M1,
},
@@ -111,6 +116,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_MM,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -119,6 +125,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_USB] = {
.name = "usb",
@@ -127,6 +134,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = true,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
@@ -135,6 +143,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
.clk_id = MT8173_CLK_MFG,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.name = "mfg_2d",
@@ -143,6 +152,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(13, 12),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = false,
},
[MT8173_POWER_DOMAIN_MFG] = {
.name = "mfg",
@@ -151,6 +161,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = false,
.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
MT8173_TOP_AXI_PROT_EN_MFG_M0 |
MT8173_TOP_AXI_PROT_EN_MFG_M1 |
@@ -171,6 +182,7 @@ struct scp_domain {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
+ bool active_wakeup;
};
struct scp {
@@ -370,6 +382,20 @@ out:
return ret;
}
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return false;
+
+
[PATCH v3 0/2] Add Mediatek watchdog suspend resume and shutdown
This series add Mediatek watchdog suspend, resume and shutdown support. These patches are based on v4.2-rc1 Change in v3: Add mtk_wdt in subject line Change in v2: Use watchdog_active() to check whether watchdog been active. Change to register suspend,resume function to dev_pm_ops -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/2] watchdog: mtk_wdt: add wdt shutdown callback to disable wdt if enabled
From: Greta Zhang
Without .shutdown(), watchdog might reset the system during power off.
For example, if watchdog's timeout is set to 30s, then it is reset to
zero by mtk_wdt_ping(). During power off, no app will ping watchdog,
but watchdog is still running and may trigger reset.
Signed-off-by: Greta Zhang
Signed-off-by: Eddie Huang
Acked-by: Matthias Brugger
Reviewed-by: Guenter Roeck
---
drivers/watchdog/mtk_wdt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 056412c..6ad9df9 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -210,6 +210,14 @@ static int mtk_wdt_probe(struct platform_device *pdev)
return 0;
}
+static void mtk_wdt_shutdown(struct platform_device *pdev)
+{
+ struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev))
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+}
+
static int mtk_wdt_remove(struct platform_device *pdev)
{
struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
@@ -259,6 +267,7 @@ static const struct dev_pm_ops mtk_wdt_pm_ops = {
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
+ .shutdown = mtk_wdt_shutdown,
.driver = {
.name = DRV_NAME,
.pm = &mtk_wdt_pm_ops,
--
1.8.1.1.dirty
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[PATCH v3 1/2] watchdog: mtk_wdt: add suspend/resume support
From: Greta Zhang
add mediatek watchdog driver suspend/resume support
Signed-off-by: Greta Zhang
Signed-off-by: Roger Lu
Signed-off-by: Eddie Huang
Acked-by: Matthias Brugger
Reviewed-by: Guenter Roeck
---
drivers/watchdog/mtk_wdt.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 938b987..056412c 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -221,17 +221,47 @@ static int mtk_wdt_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM_SLEEP
+static int mtk_wdt_suspend(struct device *dev)
+{
+ struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev))
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+
+ return 0;
+}
+
+static int mtk_wdt_resume(struct device *dev)
+{
+ struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
+
+ if (watchdog_active(&mtk_wdt->wdt_dev)) {
+ mtk_wdt_start(&mtk_wdt->wdt_dev);
+ mtk_wdt_ping(&mtk_wdt->wdt_dev);
+ }
+
+ return 0;
+}
+#endif
+
static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt6589-wdt" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
+static const struct dev_pm_ops mtk_wdt_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
+ mtk_wdt_resume)
+};
+
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
.driver = {
.name = DRV_NAME,
+ .pm = &mtk_wdt_pm_ops,
.of_match_table = mtk_wdt_dt_ids,
},
};
--
1.8.1.1.dirty
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Re: [PATCH] i2c: mediatek: fix transfer error handling
On Fri, 2015-07-31 at 13:00 +0200, Wolfram Sang wrote:
> On Tue, Jul 28, 2015 at 11:38:05AM +0800, Eddie Huang wrote:
> > From: Liguo Zhang
> >
> > Reset i2c dma engine in hw init function.
> > When occur i2c ack error, mtk_i2c_irq may is twice,
> > first is the ack error interrupt, then the complete interrupt,
> > so i2c->irq_stat need keep the two interrupt value, and only
> > call complete() for the complete interrupt.
> >
> > Signed-off-by: Liguo Zhang
> > Signed-off-by: Eddie Huang
>
> Looks to me this patch needs to be split up into one patch per issue?
OK, I can split
> And doesn't it kill the auto_restart functionality? Sascha?
No. restart_flag already set in mtk_i2c_do_transfer() function.It is not
necessary check restart_flag again in mtk_i2c_irq(). It is simpler to
just read status bit and write back to clear interrupt status.
Eddie
Thanks
>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 25 ++---
> > 1 file changed, 18 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c
> > b/drivers/i2c/busses/i2c-mt65xx.c
> > index 9920eef..57d11b7 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -59,6 +59,7 @@
> > #define I2C_DMA_START_EN 0x0001
> > #define I2C_DMA_INT_FLAG_NONE 0x
> > #define I2C_DMA_CLR_FLAG 0x
> > +#define I2C_DMA_HARD_RST 0x0002
> >
> > #define I2C_DEFAULT_SPEED 10 /* hz */
> > #define MAX_FS_MODE_SPEED 40
> > @@ -81,6 +82,7 @@ enum DMA_REGS_OFFSET {
> > OFFSET_INT_FLAG = 0x0,
> > OFFSET_INT_EN = 0x04,
> > OFFSET_EN = 0x08,
> > + OFFSET_RST = 0x0c,
> > OFFSET_CON = 0x18,
> > OFFSET_TX_MEM_ADDR = 0x1c,
> > OFFSET_RX_MEM_ADDR = 0x20,
> > @@ -262,6 +264,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
> > I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
> > writew(control_reg, i2c->base + OFFSET_CONTROL);
> > writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
> > +
> > + writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
> > + udelay(50);
> > + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
> > }
> >
> > /*
> > @@ -550,16 +556,20 @@ err_exit:
> > static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
> > {
> > struct mtk_i2c *i2c = dev_id;
> > - u16 restart_flag = 0;
> > + u16 intr_stat = 0;
> >
> > - if (i2c->dev_comp->auto_restart)
> > - restart_flag = I2C_RS_TRANSFER;
> > + intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
> > + writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
> >
> > - i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
> > - writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
> > - | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
> > + /*
> > +* when occurs i2c ack error, mtk_i2c_irq is called twice,
> > +* first is the ack error interrupt, then the complete interrupt,
> > +* i2c->irq_stat need keep the two interrupt value.
> > +*/
> > + i2c->irq_stat |= intr_stat;
> >
> > - complete(&i2c->msg_complete);
> > + if (i2c->irq_stat & I2C_TRANSAC_COMP)
> > + complete(&i2c->msg_complete);
> >
> > return IRQ_HANDLED;
> > }
> > @@ -729,3 +739,4 @@ module_platform_driver(mtk_i2c_driver);
> > MODULE_LICENSE("GPL v2");
> > MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
> > MODULE_AUTHOR("Xudong Chen ");
> > +MODULE_AUTHOR("Liguo Zhang ");
> > --
> > 1.7.9.5
> >
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[PATCH 2/2] i2c: mediatek: Fixup i2c ack error interrupt handling
When occur i2c ack error, mtk_i2c_irq is called twice,
first is the ack error interrupt, then the complete interrupt.
i2c interrupt handler should keep the two interrupt value, and only
call complete() for the complete interrupt.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 055159d..12ce7f8 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -558,16 +558,20 @@ err_exit:
static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
{
struct mtk_i2c *i2c = dev_id;
- u16 restart_flag = 0;
+ u16 intr_stat = 0;
- if (i2c->dev_comp->auto_restart)
- restart_flag = I2C_RS_TRANSFER;
+ intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
+ writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
- i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
- writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
- | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
+ /*
+* when occurs i2c ack error, mtk_i2c_irq is called twice,
+* first is the ack error interrupt, then the complete interrupt,
+* i2c->irq_stat need keep the two interrupt value.
+*/
+ i2c->irq_stat |= intr_stat;
- complete(&i2c->msg_complete);
+ if (i2c->irq_stat & I2C_TRANSAC_COMP)
+ complete(&i2c->msg_complete);
return IRQ_HANDLED;
}
--
1.7.9.5
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[PATCH 0/2] Mediatek I2C fixup
This series provide two patches to optimize mediatek i2c driver. The first patch will reset dma hardware in init function to make sure hardware work in good state. The second patch fix i2c interrupt handling for ACK error. All these patches base on v4.2-rc1. Eddie Huang (2): i2c: mediatek: Reset DMA engine in hardware init function i2c: mediatek: Fixup i2c ack error interrupt handling drivers/i2c/busses/i2c-mt65xx.c | 28 1 file changed, 20 insertions(+), 8 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] i2c: mediatek: Reset DMA engine in hardware init function
Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..055159d 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2014 MediaTek Inc.
- * Author: Xudong Chen
+ * Author:
+ * Xudong Chen
+ * Liguo Zhang
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -59,6 +61,7 @@
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x
#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_HARD_RST 0x0002
#define I2C_DEFAULT_SPEED 10 /* hz */
#define MAX_FS_MODE_SPEED 40
@@ -81,6 +84,7 @@ enum DMA_REGS_OFFSET {
OFFSET_INT_FLAG = 0x0,
OFFSET_INT_EN = 0x04,
OFFSET_EN = 0x08,
+ OFFSET_RST = 0x0c,
OFFSET_CON = 0x18,
OFFSET_TX_MEM_ADDR = 0x1c,
OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +266,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
writew(control_reg, i2c->base + OFFSET_CONTROL);
writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+ writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+ udelay(50);
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
}
/*
--
1.7.9.5
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[PATCH v2 0/2] Mediatek I2C fixup
This series provide two patches to optimize mediatek i2c driver. The first patch will reset dma hardware in init function to make sure hardware work in good state. The second patch fix i2c interrupt handling for ACK error. All these patches base on 4.2-rc1. Change in v2: Fix multi-transfer fail bug - in mtk_i2c_irq(), call complete() if get I2C_RS_TRANSFER interrupt Eddie Huang (2): i2c: mediatek: Reset DMA engine in hardware init function i2c: mediatek: Fixup i2c ack error interrupt handling drivers/i2c/busses/i2c-mt65xx.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/2] i2c: mediatek: Reset DMA engine in hardware init function
Reset DMA in hardware init function to avoid unknown hardware state
before do any I2C operation.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..e28ad4c 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -59,6 +59,7 @@
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x
#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_HARD_RST 0x0002
#define I2C_DEFAULT_SPEED 10 /* hz */
#define MAX_FS_MODE_SPEED 40
@@ -81,6 +82,7 @@ enum DMA_REGS_OFFSET {
OFFSET_INT_FLAG = 0x0,
OFFSET_INT_EN = 0x04,
OFFSET_EN = 0x08,
+ OFFSET_RST = 0x0c,
OFFSET_CON = 0x18,
OFFSET_TX_MEM_ADDR = 0x1c,
OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +264,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
writew(control_reg, i2c->base + OFFSET_CONTROL);
writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+ writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+ udelay(50);
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
}
/*
--
1.7.9.5
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[PATCH v2 2/2] i2c: mediatek: Fixup i2c ack error interrupt handling
When occur i2c ack error, i2c controller generate two interrupts,
first is the ack error interrupt, then the complete interrupt.
i2c interrupt handler should keep the two interrupt value, and only
call complete() for the complete interrupt.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e28ad4c..c02e6c0 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -557,15 +557,22 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
{
struct mtk_i2c *i2c = dev_id;
u16 restart_flag = 0;
+ u16 intr_stat;
if (i2c->dev_comp->auto_restart)
restart_flag = I2C_RS_TRANSFER;
- i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
- writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
- | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
+ intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
+ writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
- complete(&i2c->msg_complete);
+ /*
+* when occurs ack error, i2c controller generate two interrupts
+* first is the ack error interrupt, then the complete interrupt
+* i2c->irq_stat need keep the two interrupt value.
+*/
+ i2c->irq_stat |= intr_stat;
+ if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
+ complete(&i2c->msg_complete);
return IRQ_HANDLED;
}
--
1.7.9.5
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Re: [PATCH] arm64: dts: mt8173: add clock_null
On Tue, 2015-07-07 at 23:10 +0800, Daniel Kurtz wrote:
> On Tue, Jul 7, 2015 at 10:36 PM, Sascha Hauer wrote:
> > On Tue, Jul 07, 2015 at 10:15:29PM +0800, Daniel Kurtz wrote:
> >> On Tue, Jul 7, 2015 at 9:07 PM, Sascha Hauer
> >> wrote:
> >> > On Thu, Jun 18, 2015 at 01:29:11PM +0800, Eddie Huang wrote:
> >> >> Add clk_null, which represents clocks that can not / need not
> >> >> controlled by software.
> >> >> There are many clocks' parent set to clk_null.
> >> >>
> >> >> Signed-off-by: James Liao
> >> >> Signed-off-by: Eddie Huang
> >> >> ---
> >> >> Base on 4.1-rc1
> >> >>
> >> >> Change-Id: I4db9b40d07e28f54f7bae9b676316cbd6a962124
> >> >> ---
> >> >> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 6 ++
> >> >> 1 file changed, 6 insertions(+)
> >> >>
> >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >> >> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >> >> index 924fdb6..4798f44 100644
> >> >> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >> >> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> >> >> @@ -81,6 +81,12 @@
> >> >> cpu_on= <0x8403>;
> >> >> };
> >> >>
> >> >> + clk_null: clk_null {
> >> >> + compatible = "fixed-clock";
> >> >> + clock-frequency = <0>;
> >> >> + #clock-cells = <0>;
> >> >> + };
> >> >
> >> > The discussion around this patch shows that we don't want to have this
> >> > clock in the device tree as it is not a hardware description.
> >> >
> >> > Ok, fine. Eddie, you told us that the rate of the current clk_null
> >> > children
> >> > is not interesting. What's the motivation to send this patch anyway
> >> > then? Why can't you keep its children on the orphan list where they are
> >> > already now?
> >> >
> >> > Another possibility would be to instantiate the clk_null clock from C
> >> > code rather than from the device tree. This way we wouldn't put any
> >> > wrong descriptions into the device tree and still can implement the
> >> > support for the real parent clocks when we actually need them.
> >>
> >> Some device nodes, like mmc, use a clk_null phandle as one of their clocks:
> >>
> >> mmc1: mmc@1124 {
> >> compatible = "mediatek,mt8173-mmc",
> >> "mediatek,mt8135-mmc";
> >> reg = <0 0x1124 0 0x1000>;
> >> interrupts = ;
> >> clocks = <&pericfg CLK_PERI_MSDC30_1>,
> >> <&clk_null>;
> >> clock-names = "source", "hclk";
> >> status = "disabled";
> >> };
> >
> > This is another case than the one we discussed about. In the case above
> > I motivated using a dummy clock since the clock exists in the system,
> > but is not software controllable. To abstract this from the driver
> > (which needs this clock since it exists) we here have the dummy clock.
> > However, of course I can't prove the clock is indeed not software
> > controllable; that's only the information I have.
>
> I was trying to answer your question "What's the motivation to send
> this patch anyway?".
> The motivation is to send follow on patches that use the clk_null
> phandle. We need to provide some clock as the mmc1's hclk. I do not
> understand why this has to be "clk_null", though. It seems like this
> should be a real clock coming from one of the real clock_controller
> nodes. After all, the mmc driver is going to be enabling/disabling
> this clock for power savings at runtime. What does that even mean for
> clk_null ?
The original purpose of this patch is to provide a common dummy clock
for both software don't care clock and clock that is not software
controllable.I got comments that device tree should describe hardware
and should put exact clock in device tree. I think this is true. So we
will remove this clock_null patch, and:
1. For Mediatek SoC CCF driver, James will clarify clock usage further.
Actually, we still think it's not necessary to describe whole tree that
software don't care, James will deal this in clock driver.
2. For other module that use SW not controllable clock (mmc case
mentioned by Dan), because this is a real clock, we will put a dummy
clock in device tree, like
clk_mmchclk: dummyhclk {
compatible = "fixed-clock";
clock-frequency = <0>;
#clock-cells = <0>;
};
How about this modification ?
Thanks
Eddie
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[PATCH v2] soc: mediatek: add scpsys support active_wakeup
Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.
Signed-off-by: Chunfeng Yun
Signed-off-by: Eddie Huang
Acked-by: Sascha Hauer
---
Change in v2:
Drop .active_wakeup = false lines in scp_domain_data[] array
---
drivers/soc/mediatek/mtk-scpsys.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 43a79ed..df2f288 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -67,6 +67,7 @@ struct scp_domain_data {
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
enum clk_id clk_id;
+ bool active_wakeup;
};
static const struct scp_domain_data scp_domain_data[] __initconst = {
@@ -127,6 +128,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = true,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
@@ -171,6 +173,7 @@ struct scp_domain {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
+ bool active_wakeup;
};
struct scp {
@@ -370,6 +373,20 @@ out:
return ret;
}
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+ return false;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ scpd = container_of(genpd, struct scp_domain, genpd);
+
+ return scpd->active_wakeup;
+}
+
static int __init scpsys_probe(struct platform_device *pdev)
{
struct genpd_onecell_data *pd_data;
@@ -427,12 +444,14 @@ static int __init scpsys_probe(struct platform_device
*pdev)
scpd->sram_pdn_bits = data->sram_pdn_bits;
scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
scpd->bus_prot_mask = data->bus_prot_mask;
+ scpd->active_wakeup = data->active_wakeup;
if (data->clk_id != MT8173_CLK_NONE)
scpd->clk = clk[data->clk_id];
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
+ genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
/*
* Initially turn on all domains to make the domains usable
--
1.9.1
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Re: [PATCH v2] soc: mediatek: add scpsys support active_wakeup
On Wed, 2015-08-26 at 05:11 +0800, Daniel Kurtz wrote:
> Hi Eddie,
>
> On Tue, Aug 25, 2015 at 2:00 PM, Eddie Huang wrote:
> > Register gpd_dev_ops.active_wakeup function to support keep power
> > during suspend state. And add flag to each power domain to
> > decide whether keep power during suspend or not.
> >
> > Signed-off-by: Chunfeng Yun
> > Signed-off-by: Eddie Huang
> > Acked-by: Sascha Hauer
> >
> > ---
> > Change in v2:
> > Drop .active_wakeup = false lines in scp_domain_data[] array
> >
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 19 +++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.c
> > b/drivers/soc/mediatek/mtk-scpsys.c
> > index 43a79ed..df2f288 100644
> > --- a/drivers/soc/mediatek/mtk-scpsys.c
> > +++ b/drivers/soc/mediatek/mtk-scpsys.c
> > @@ -67,6 +67,7 @@ struct scp_domain_data {
> > u32 sram_pdn_ack_bits;
> > u32 bus_prot_mask;
> > enum clk_id clk_id;
> > + bool active_wakeup;
> > };
> >
> > static const struct scp_domain_data scp_domain_data[] __initconst = {
> > @@ -127,6 +128,7 @@ static const struct scp_domain_data scp_domain_data[]
> > __initconst = {
> > .sram_pdn_bits = GENMASK(11, 8),
> > .sram_pdn_ack_bits = GENMASK(15, 12),
> > .clk_id = MT8173_CLK_NONE,
> > + .active_wakeup = true,
> > },
> > [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> > .name = "mfg_async",
> > @@ -171,6 +173,7 @@ struct scp_domain {
> > u32 sram_pdn_bits;
> > u32 sram_pdn_ack_bits;
> > u32 bus_prot_mask;
> > + bool active_wakeup;
> > };
> >
> > struct scp {
> > @@ -370,6 +373,20 @@ out:
> > return ret;
> > }
> >
> > +static bool scpsys_active_wakeup(struct device *dev)
> > +{
> > + struct generic_pm_domain *genpd;
> > + struct scp_domain *scpd;
> > +
> > + if (IS_ERR_OR_NULL(dev->pm_domain))
> > + return false;
>
> Is it really possible to get here w/ pm_domain as an ERR or NULL?
> If the power core can ensure this cannot happen, then this function
> could be a bit simpler.
>
> Other than that, this patch is:
> Reviewed-by: Daniel Kurtz
>
> -Dan
>
After checking drivers/base/power/domain.c, I believe check
dev->pm_domain here is redundant, I will remove it.
Eddie
Thanks
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[PATCH v3] soc: mediatek: add scpsys support active_wakeup
Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.
Signed-off-by: Chunfeng Yun
Signed-off-by: Eddie Huang
Acked-by: Sascha Hauer
Reviewed-by: Daniel Kurtz
---
Change in v3:
Remove check dev->power_domain NULL or ERR. This will not happen
when call scpsys_active_wakeup function
Change in v2:
Drop .active_wakeup = false lines in scp_domain_data[] array
---
drivers/soc/mediatek/mtk-scpsys.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 43a79ed..3a00975 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -67,6 +67,7 @@ struct scp_domain_data {
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
enum clk_id clk_id;
+ bool active_wakeup;
};
static const struct scp_domain_data scp_domain_data[] __initconst = {
@@ -127,6 +128,7 @@ static const struct scp_domain_data scp_domain_data[]
__initconst = {
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.clk_id = MT8173_CLK_NONE,
+ .active_wakeup = true,
},
[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
.name = "mfg_async",
@@ -171,6 +173,7 @@ struct scp_domain {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
+ bool active_wakeup;
};
struct scp {
@@ -370,6 +373,17 @@ out:
return ret;
}
+static bool scpsys_active_wakeup(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ struct scp_domain *scpd;
+
+ genpd = pd_to_genpd(dev->pm_domain);
+ scpd = container_of(genpd, struct scp_domain, genpd);
+
+ return scpd->active_wakeup;
+}
+
static int __init scpsys_probe(struct platform_device *pdev)
{
struct genpd_onecell_data *pd_data;
@@ -427,12 +441,14 @@ static int __init scpsys_probe(struct platform_device
*pdev)
scpd->sram_pdn_bits = data->sram_pdn_bits;
scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
scpd->bus_prot_mask = data->bus_prot_mask;
+ scpd->active_wakeup = data->active_wakeup;
if (data->clk_id != MT8173_CLK_NONE)
scpd->clk = clk[data->clk_id];
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
+ genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
/*
* Initially turn on all domains to make the domains usable
--
1.9.1
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Re: [PATCH] rtc: mt6397: implement suspend/resume function in rtc-mt6397 driver
On Thu, 2015-07-30 at 22:53 +0800, Henry Chen wrote:
> Implement the suspend/resume function in order to control rtc's irq_wake flag
> and handle as wakeup source.
>
> Signed-off-by: Henry Chen
> ---
> drivers/rtc/rtc-mt6397.c | 26 ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
> index c0090b6..9f6c9f8 100644
> --- a/drivers/rtc/rtc-mt6397.c
> +++ b/drivers/rtc/rtc-mt6397.c
> @@ -373,6 +373,31 @@ static int mtk_rtc_remove(struct platform_device *pdev)
> return 0;
> }
>
> +#ifdef CONFIG_PM_SLEEP
> +static int mt6397_rtc_suspend(struct device *dev)
> +{
> + struct mt6397_rtc *rtc = dev_get_drvdata(dev);
> +
> + if (device_may_wakeup(dev))
> + enable_irq_wake(rtc->irq);
> +
> + return 0;
> +}
> +
> +static int mt6397_rtc_resume(struct device *dev)
> +{
> + struct mt6397_rtc *rtc = dev_get_drvdata(dev);
> +
> + if (device_may_wakeup(dev))
> + disable_irq_wake(rtc->irq);
> +
> + return 0;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
> + mt6397_rtc_resume);
> +
> static const struct of_device_id mt6397_rtc_of_match[] = {
> { .compatible = "mediatek,mt6397-rtc", },
> { }
> @@ -382,6 +407,7 @@ static struct platform_driver mtk_rtc_driver = {
> .driver = {
> .name = "mt6397-rtc",
> .of_match_table = mt6397_rtc_of_match,
> + .pm = &mt6397_pm_ops,
> },
> .probe = mtk_rtc_probe,
> .remove = mtk_rtc_remove,
It looks good to me.
Acked-by: Eddie Huang
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[PATCH] i2c: mediatek: fix transfer error handling
From: Liguo Zhang
Reset i2c dma engine in hw init function.
When occur i2c ack error, mtk_i2c_irq may is twice,
first is the ack error interrupt, then the complete interrupt,
so i2c->irq_stat need keep the two interrupt value, and only
call complete() for the complete interrupt.
Signed-off-by: Liguo Zhang
Signed-off-by: Eddie Huang
---
drivers/i2c/busses/i2c-mt65xx.c | 25 ++---
1 file changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 9920eef..57d11b7 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -59,6 +59,7 @@
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x
#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_HARD_RST 0x0002
#define I2C_DEFAULT_SPEED 10 /* hz */
#define MAX_FS_MODE_SPEED 40
@@ -81,6 +82,7 @@ enum DMA_REGS_OFFSET {
OFFSET_INT_FLAG = 0x0,
OFFSET_INT_EN = 0x04,
OFFSET_EN = 0x08,
+ OFFSET_RST = 0x0c,
OFFSET_CON = 0x18,
OFFSET_TX_MEM_ADDR = 0x1c,
OFFSET_RX_MEM_ADDR = 0x20,
@@ -262,6 +264,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
writew(control_reg, i2c->base + OFFSET_CONTROL);
writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+
+ writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
+ udelay(50);
+ writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
}
/*
@@ -550,16 +556,20 @@ err_exit:
static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
{
struct mtk_i2c *i2c = dev_id;
- u16 restart_flag = 0;
+ u16 intr_stat = 0;
- if (i2c->dev_comp->auto_restart)
- restart_flag = I2C_RS_TRANSFER;
+ intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
+ writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
- i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
- writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
- | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
+ /*
+* when occurs i2c ack error, mtk_i2c_irq is called twice,
+* first is the ack error interrupt, then the complete interrupt,
+* i2c->irq_stat need keep the two interrupt value.
+*/
+ i2c->irq_stat |= intr_stat;
- complete(&i2c->msg_complete);
+ if (i2c->irq_stat & I2C_TRANSAC_COMP)
+ complete(&i2c->msg_complete);
return IRQ_HANDLED;
}
@@ -729,3 +739,4 @@ module_platform_driver(mtk_i2c_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
MODULE_AUTHOR("Xudong Chen ");
+MODULE_AUTHOR("Liguo Zhang ");
--
1.7.9.5
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Re: [PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Wed, 2015-11-11 at 20:54 -0800, Kevin Hilman wrote: > Hi Eddie, > > Kevin Hilman writes: > > > Eddie Huang writes: > > > >> On Tue, 2015-11-10 at 17:16 -0800, Kevin Hilman wrote: > >>> Hi Eddie, > >>> > >>> [...] > >>> > >>> > I check the log [0], > >>> > >>> Thanks for checking into this boot failure. > >>> > >>> > it seems first time mt8135-evbp1 boot to kernel > >>> > shell successfully, then boot again. In the second time, mt8135 stay in > >>> > fastboot mode, waiting host send boot image, then timeout. > >>> > >>> Actually, it never gets to a shell the first time. If you look closely, > >>> the target reboots as soon as userspace starts. Look for the PYBOOT > >>> line which says "finished booting, starting userspace" > >>> > >>> Later on, pyboot thinks it finds a root shell due to finding '#' > >>> characters, but clearly it never got to a shell. > >>> > >>> > I download zImage and dtb in [1], and kernel run to shell successfully > >>> > on my platform. > >>> > >>> Are you can you try using a ramdisk as well? You can use the pre-built > >>> one here: > >>> http://storage.kernelci.org/images/rootfs/buildroot/armel/rootfs.cpio.gz > >>> > >> > >> Yes, I tried this ramdisk, and I can reproduce fail issue. > >> > > > > OK, good. Thanks for looking into it. > > > >>> Please check my boot logs to see how I'm generating the boot.img file > >>> (search for mkbootimg) with a kernel/dtb/ramdisk. It may be possible > >>> that the kernel image size with a ramdisk is breaking some of the > >>> assumptions in the fastboot mode. I've seen problems like this on other > >>> platforms due to hard-coded sizes/addresses in the boot firmware. > >>> > >> > >> MT8135 allocate 10MB for BOOT partition, but the test boot.img is 11MB, > >> thus cause user space fail. > > > > Aha, I was right! ;) > > Also notice in kernelci.org that the mt8173 board has also been failing > to boot in mainline[1]. I wonder if this same limitation exists in the > mt8173 boot firmware? > MT8173 is another case, the failure is due to following commit: 67e56c5 arm64: dts: mt8173: Add subsystem clock controller device nodes It is because this commit register MM subsystem clock, but kernel don't use MM clock yet, then CCF disable it. (My internal platform kernel command include clk_ignore_unused parameter, so don't have this problem).I will do further checking and release solution later. Thanks your testing. Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] soc: Mediatek: Enable SCPSYS power domain driver by default
If enable Mediatek 8173 SoC, it should also enable power domain driver. Otherwise access clk subsystem register will fail. Signed-off-by: Eddie Huang --- MT8173 clk driver is enabled by default, but power domain driver is not. If MM subsystem power on, mm_sel topckgen mux is off, then access any MM subsystem register will cause system hang. Enable SCPSYS driver to make sure both MM subsystem power and mm_sel to on/off together to avoid system hang. This patch fix current linux-next mt8173-evb boot to shell fail problem. --- drivers/soc/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 9d50682..0a4ea80 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -23,6 +23,7 @@ config MTK_PMIC_WRAP config MTK_SCPSYS bool "MediaTek SCPSYS Support" depends on ARCH_MEDIATEK || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK select REGMAP select MTK_INFRACFG select PM_GENERIC_DOMAINS if PM -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Thu, 2015-11-12 at 15:56 -0800, Kevin Hilman wrote: > Eddie Huang writes: > > > On Wed, 2015-11-11 at 20:54 -0800, Kevin Hilman wrote: > >> Hi Eddie, > >> > >> Kevin Hilman writes: > >> > >> > Eddie Huang writes: > >> > > >> >> On Tue, 2015-11-10 at 17:16 -0800, Kevin Hilman wrote: > >> >>> Hi Eddie, > >> >>> > >> >>> [...] > >> >>> > >> >>> > I check the log [0], > >> >>> > >> >>> Thanks for checking into this boot failure. > >> >>> > >> >>> > it seems first time mt8135-evbp1 boot to kernel > >> >>> > shell successfully, then boot again. In the second time, mt8135 stay > >> >>> > in > >> >>> > fastboot mode, waiting host send boot image, then timeout. > >> >>> > >> >>> Actually, it never gets to a shell the first time. If you look > >> >>> closely, > >> >>> the target reboots as soon as userspace starts. Look for the PYBOOT > >> >>> line which says "finished booting, starting userspace" > >> >>> > >> >>> Later on, pyboot thinks it finds a root shell due to finding '#' > >> >>> characters, but clearly it never got to a shell. > >> >>> > >> >>> > I download zImage and dtb in [1], and kernel run to shell > >> >>> > successfully > >> >>> > on my platform. > >> >>> > >> >>> Are you can you try using a ramdisk as well? You can use the pre-built > >> >>> one here: > >> >>> http://storage.kernelci.org/images/rootfs/buildroot/armel/rootfs.cpio.gz > >> >>> > >> >> > >> >> Yes, I tried this ramdisk, and I can reproduce fail issue. > >> >> > >> > > >> > OK, good. Thanks for looking into it. > >> > > >> >>> Please check my boot logs to see how I'm generating the boot.img file > >> >>> (search for mkbootimg) with a kernel/dtb/ramdisk. It may be possible > >> >>> that the kernel image size with a ramdisk is breaking some of the > >> >>> assumptions in the fastboot mode. I've seen problems like this on > >> >>> other > >> >>> platforms due to hard-coded sizes/addresses in the boot firmware. > >> >>> > >> >> > >> >> MT8135 allocate 10MB for BOOT partition, but the test boot.img is 11MB, > >> >> thus cause user space fail. > >> > > >> > Aha, I was right! ;) > >> > >> Also notice in kernelci.org that the mt8173 board has also been failing > >> to boot in mainline[1]. I wonder if this same limitation exists in the > >> mt8173 boot firmware? > >> > > > > MT8173 is another case, the failure is due to following commit: > > 67e56c5 arm64: dts: mt8173: Add subsystem clock controller device nodes > > > > It is because this commit register MM subsystem clock, but kernel don't > > use MM clock yet, then CCF disable it. (My internal platform kernel > > command include clk_ignore_unused parameter, so don't have this > > problem).I will do further checking and release solution later. Thanks > > your testing. > > OK, thanks for looking into it. > > However, since the merge window is very close to closing, unless you can > git a fix out soon (and one that doesn't introduce other bugs), > probablly the right solution is to just revert the above patch so things > are fixed for mainline ASAP. > I send one patch to fix this problem. Hope this patch can apply to 4.4. http://lists.infradead.org/pipermail/linux-arm-kernel/2015-November/384800.html Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 4/5] ARM: dts: mt8135: enable basic SMP bringup for mt8135
On Thu, 2015-10-29 at 02:12 -0700, Kevin Hilman wrote: > Eddie Huang writes: > > > Hi Kevin, > > > > On Mon, 2015-10-26 at 17:06 +0900, Kevin Hilman wrote: > >> On Mon, Oct 26, 2015 at 4:15 PM, Yingjoe Chen > >> wrote: > >> > On Mon, 2015-10-26 at 09:56 +0900, Kevin Hilman wrote: > >> >> Hello, > >> >> > >> >> On Sat, Oct 3, 2015 at 12:19 AM, Yingjoe Chen > >> >> wrote: > >> >> > Add arch timer node to enable arch-timer support. MT8135 firmware > >> >> > doesn't correctly setup arch-timer frequency and CNTVOFF, add > >> >> > properties to workaround this. > >> >> > > >> >> > This also set cpu enable-method to enable SMP. > >> >> > > >> >> > Signed-off-by: Yingjoe Chen > >> >> > >> >> kernelci.org started detecting new boot failures for the mt8135-evb in > >> >> the arm-soc tree[1], and the boot failures were bisected down to this > >> >> patch, which landed upstream in the form of commit d186a394bb98 (ARM: > >> >> dts: mt8135: enable basic SMP bringup for mt8135) > >> >> > >> >> Maybe this new SMP support requires updating the firmware on the board > >> >> as well? If so, the changelog should've been a bit more explicit > >> >> about firmware dependencies. > >> > > >> > Kevin, > >> > > >> > Thanks for testing. > >> > > >> > No, it doesn't need new firmware. Will test to see what's going wrong. > >> > >> Thanks for following up. I'll be glad to test any patches if you have > >> anything you'd like me to test. > > > > You need "clockevents/drivers/mtk: Fix spurious interrupt leading to > > crash" (https://lkml.org/lkml/2015/8/24/803) > > > > Daniel Lezcano already applied this patch in his tree for 4.4. > > (https://git.linaro.org/people/daniel.lezcano/linux.git) > > > > Thanks for letting us know. > > In the future, these kinds of cross-tree dependencies are important to > mention in the cover letter of the pull request so we can setup > dependency branches and keep arm-soc/for-next building and booting. > sorry, we will be more careful in the future Eddie Thanks -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/2] Add Mediatek watchdog suspend resume and shutdown
This series add Mediatek watchdog suspend, resume and shutdown support. These patches are based on v4.2-rc1 Greta Zhang (2): watchdog: add wdt suspend/resume support watchdog: add wdt shutdown callback to disable wdt if enabled drivers/watchdog/mtk_wdt.c | 47 ++ 1 file changed, 47 insertions(+) -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/2] watchdog: add wdt shutdown callback to disable wdt if enabled
From: Greta Zhang
Without .shutdown(), watchdog might reset the system during power off.
For example, if watchdog's timeout is set to 30s, then it is reset to
zero by mtk_wdt_ping(). During power off, no app will ping watchdog,
but watchdog is still running and may trigger reset.
Signed-off-by: Greta Zhang
Signed-off-by: Eddie Huang
---
drivers/watchdog/mtk_wdt.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 5ef3910..c6741a5 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -217,6 +217,14 @@ static int mtk_wdt_probe(struct platform_device *pdev)
return 0;
}
+static void mtk_wdt_shutdown(struct platform_device *pdev)
+{
+ struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
+
+ if (mtk_wdt->started)
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+}
+
static int mtk_wdt_remove(struct platform_device *pdev)
{
struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
@@ -266,6 +274,7 @@ MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
+ .shutdown = mtk_wdt_shutdown,
.suspend= mtk_wdt_suspend,
.resume = mtk_wdt_resume,
.driver = {
--
1.8.1.1.dirty
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[PATCH 1/2] watchdog: add wdt suspend/resume support
From: Greta Zhang
add wdt driver suspend/resume support
Signed-off-by: Greta Zhang
Signed-off-by: Roger Lu
Signed-off-by: Eddie Huang
---
drivers/watchdog/mtk_wdt.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
index 938b987..5ef3910 100644
--- a/drivers/watchdog/mtk_wdt.c
+++ b/drivers/watchdog/mtk_wdt.c
@@ -65,6 +65,7 @@ struct mtk_wdt_dev {
struct watchdog_device wdt_dev;
void __iomem *wdt_base;
struct notifier_block restart_handler;
+ bool started;
};
static int mtk_reset_handler(struct notifier_block *this, unsigned long mode,
@@ -125,6 +126,8 @@ static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
reg &= ~WDT_MODE_EN;
iowrite32(reg, wdt_base + WDT_MODE);
+ mtk_wdt->started = false;
+
return 0;
}
@@ -135,6 +138,8 @@ static int mtk_wdt_start(struct watchdog_device *wdt_dev)
void __iomem *wdt_base = mtk_wdt->wdt_base;
int ret;
+ mtk_wdt->started = true;
+
ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
if (ret < 0)
return ret;
@@ -174,6 +179,8 @@ static int mtk_wdt_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, mtk_wdt);
+ mtk_wdt->started = false;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtk_wdt->wdt_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(mtk_wdt->wdt_base))
@@ -221,6 +228,35 @@ static int mtk_wdt_remove(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_PM
+static int mtk_wdt_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
+
+ if (mtk_wdt->started) {
+ mtk_wdt_stop(&mtk_wdt->wdt_dev);
+ mtk_wdt->started = true;
+ }
+
+ return 0;
+}
+
+static int mtk_wdt_resume(struct platform_device *pdev)
+{
+ struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
+
+ if (mtk_wdt->started) {
+ mtk_wdt_start(&mtk_wdt->wdt_dev);
+ mtk_wdt_ping(&mtk_wdt->wdt_dev);
+ }
+
+ return 0;
+}
+#else
+#definemtk_wdt_suspend NULL
+#definemtk_wdt_resume NULL
+#endif
+
static const struct of_device_id mtk_wdt_dt_ids[] = {
{ .compatible = "mediatek,mt6589-wdt" },
{ /* sentinel */ }
@@ -230,6 +266,8 @@ MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
static struct platform_driver mtk_wdt_driver = {
.probe = mtk_wdt_probe,
.remove = mtk_wdt_remove,
+ .suspend= mtk_wdt_suspend,
+ .resume = mtk_wdt_resume,
.driver = {
.name = DRV_NAME,
.of_match_table = mtk_wdt_dt_ids,
--
1.8.1.1.dirty
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[PATCH] ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue
MT8173 E1 chip has one bug that if turn off USB power domain, vcore
power will also be off, thus cause modules using vcore power domain
fail, like MMC. The E1 chip only found on MT8173-evb board and this
board only has E1 chip, so implement this as a board specific
workaround.
Pwrapper use vcore power, so add pwrapper using USB power domain to
keep USB power domain not to zero and disabled.
Signed-off-by: Eddie Huang
---
Sascha sent similar patch before[0], but MMC support runtime-pm,
vcore power domain still be disabled after MMC and USB suspend.
This silicon bug already fix in MT8173 MP chip.
[0]:http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/358065.html
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index e427f04..7453a47 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -214,6 +214,9 @@
};
&pwrap {
+ /* Only MT8173 E1 needs USB power domain */
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
+
pmic: mt6397 {
compatible = "mediatek,mt6397";
interrupt-parent = <&pio>;
--
1.9.1
Re: [PATCH] rtc: mt6397: Add platform device ID table
On Tue, 2016-02-09 at 08:08 -0300, Javier Martinez Canillas wrote:
> The platform bus_type .match callback attempts to match the platform device
> name with an entry on the .id_table if provided and fallbacks to match with
> the driver's name if a table is not provided.
>
> Using a platform device ID to match is more explicit, allows the driver to
> support more than one device and also the MODULE_DEVICE_TABLE macro can be
> used to export the module aliases information instead of the MODULE_ALIAS.
>
> Signed-off-by: Javier Martinez Canillas
>
> ---
>
> drivers/rtc/rtc-mt6397.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c
> index 06a5c52b292f..46533f11f7fc 100644
> --- a/drivers/rtc/rtc-mt6397.c
> +++ b/drivers/rtc/rtc-mt6397.c
> @@ -404,6 +404,12 @@ static const struct of_device_id mt6397_rtc_of_match[] =
> {
> };
> MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
>
> +static const struct platform_device_id mt6397_rtc_id[] = {
> + {"mt6397-rtc", 0},
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(platform, mt6397_rtc_id);
> +
> static struct platform_driver mtk_rtc_driver = {
> .driver = {
> .name = "mt6397-rtc",
> @@ -412,6 +418,7 @@ static struct platform_driver mtk_rtc_driver = {
> },
> .probe = mtk_rtc_probe,
> .remove = mtk_rtc_remove,
> + .id_table = mt6397_rtc_id,
> };
>
> module_platform_driver(mtk_rtc_driver);
> @@ -419,4 +426,3 @@ module_platform_driver(mtk_rtc_driver);
> MODULE_LICENSE("GPL v2");
> MODULE_AUTHOR("Tianping Fang ");
> MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
> -MODULE_ALIAS("platform:mt6397-rtc");
This patch looks good to me, but I am wondering, since we tend to use
device tree method to match driver, do we still need support platform
device ID ?
Eddie
Re: [PATCH] rtc: mt6397: Add platform device ID table
On Tue, 2016-02-16 at 12:37 +0100, Arnd Bergmann wrote:
> On Monday 15 February 2016 11:50:48 Javier Martinez Canillas wrote:
> >
> > On 02/14/2016 10:58 PM, Eddie Huang wrote:
> >
> > [snip]
> >
> > >> @@ -412,6 +418,7 @@ static struct platform_driver mtk_rtc_driver = {
> > >> },
> > >> .probe = mtk_rtc_probe,
> > >> .remove = mtk_rtc_remove,
> > >> +.id_table = mt6397_rtc_id,
> > >> };
> > >>
> > >> module_platform_driver(mtk_rtc_driver);
> > >> @@ -419,4 +426,3 @@ module_platform_driver(mtk_rtc_driver);
> > >> MODULE_LICENSE("GPL v2");
> > >> MODULE_AUTHOR("Tianping Fang ");
> > >> MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
> > >> -MODULE_ALIAS("platform:mt6397-rtc");
> > >
> > > This patch looks good to me, but I am wondering, since we tend to use
> > > device tree method to match driver, do we still need support platform
> > > device ID ?
> > >
> >
> > I'm not familiar with neither this IP block nor the SoC so it is up to
> > you. I just noticed this issue when reviewing a regulator driver for a
> > similar PMIC posted by someone from mediatek.
> >
> > I thought platform device was needed since the driver has a MODULE_ALIAS()
> > but please let me know what you prefer and I can re-spin the patch and
> > just remove the MODULE_ALIAS() if that makes more sense for this platform.
> >
> >
>
> I agree. We can alway add a MODULE_DEVICE_TABLE() if we get multiple
> users of this driver on architectures that don't use devicetree yet.
>
Sure. Thanks the patch to add expandability to this driver.
Acked-by: Eddie Huang
Eddie
Re: [PATCH 1/2] watchdog: Add driver for Mediatek mt6589 watchdog
On Tue, 2014-11-11 at 19:29 +0800, Eddie Huang wrote:
> On Tue, 2014-10-28 at 00:41 +0800, Matthias Brugger wrote:
> > This patch adds a driver for the Mediatek mt6589 SoC integrated
> > watchdog.
> >
> > Signed-off-by: Matthias Brugger
> > ---
> > drivers/watchdog/Kconfig | 10 ++
> > drivers/watchdog/Makefile | 1 +
> > drivers/watchdog/mtk_wdt.c | 264
> > +
> > 3 files changed, 275 insertions(+)
> > create mode 100644 drivers/watchdog/mtk_wdt.c
> > +
> > +static int mtk_reset_handler(struct notifier_block *this, unsigned long
> > mode,
> > + void *cmd)
> > +{
> > + struct mtk_wdt_dev *mtk_wdt = container_of(this,
> > + struct mtk_wdt_dev,
> > + restart_handler);
> > + void __iomem *wdt_base = mtk_wdt->wdt_base;
> > + u32 reg;
> > +
> > + /* Enable watchdog */
> > + reg = readl(wdt_base + WDT_MODE);
> > + reg |= WDT_MODE_EN;
> > + writel(reg, wdt_base + WDT_MODE);
> > +
> > + /* Reload counter */
> > + writel(WDT_RST_RELOAD, wdt_base + WDT_RST);
> > +
> > + /* Reset system */
> > + writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
> > +
> > + while (1) {
> > + mdelay(5);
> > + writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
> > + }
> > + return NOTIFY_DONE;
> > +
> > +}
> > +
you can use "WDT_SWRST_KEY" to trigger reset signal. It is unnecessary
to enable watchdog and reload counter.
> +
> > +static int mtk_wdt_start(struct watchdog_device *wdt_dev)
> > +{
> > + u32 reg;
> > + struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
> > + void __iomem *wdt_base = mtk_wdt->wdt_base;
> > + u32 ret;
> > +
> > + ret = mtk_wdt_set_timeout(&mtk_wdt->wdt_dev,
> > + mtk_wdt->wdt_dev.timeout);
> > + if (ret < 0)
> > + return ret;
> > +
> > + reg = ioread32(wdt_base + WDT_MODE);
> > + reg |= (WDT_MODE_EN | WDT_MODE_KEY);
>
> According to datasheet, default value of register WDT_MODE bit6 is 1.
> Which means when reach timeout, still need another timeout time to
> restart the system. Should clear this bit to disable dual mode:
> reg &= ~(WDT_MODE_DUAL_EN);
>
> > + iowrite32(reg, wdt_base + WDT_MODE);
> > +
> > + return 0;
> > +}
According to datasheet, default value of register WDT_MODE bit3 and bit
6 is 1, 1'bit3 means trigger irq instead of reset, bit6 means open
dual_mode or not.
If you just set bit0 to 1 to enable watchdog, it will be irq +
dual_mode, which means it will trigger irq first when reach timeout,
still need another timeout time to trigger reset signal.
If you set bit bit6 to 0, it will be irq only, and when timeout
reaches,only irq happens, never reset.
So if want to trigger reset only,should clear bit3 and bit6 to disable
irq or dual_mode.
reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
I test this patch with above comment ok on my mt8135 tablet platform.
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