Re: MIPS Function Tracer question
On 11/29/2012 01:04 PM, Alan Cooper wrote:
I've been doing some testing of the MIPS Function Tracer functionality
on the 3.3 kernel. I was surprised to find that the option to generate
frame pointers was required for tracing.
It is not really required for MIPS function tracing, but the Kconfigs
for some reason set it.
When I don't enable
FRAME_POINTER along with FUNCTION_TRACER, the kernel hangs on boot. I
also noticed that a checkin to the 3.4 kernel
(b732d439cb43336cd6d7e804ecb2c81193ef63b0) no longer forces on
FRAME_POINTER when FUNCTION_TRACER is selected. I was wondering how it
works in 3.4 and beyond, so I built a Malta kernel from the latest
MIPS tree with FUNCTION_TRACING enabled and tested it with QEMU. The
kernel hung the same way. I can think of 2 reasons for this:
1. Function tracing is broken for MIPS in 3.4 and beyond.
2. The 4.5.3 GNU C compiler I'm using is generating different code for
function tracing.
Function tracing works best with recent versions of GCC (those that
support -mmcount-ra-address).
I was wondering if anyone has MIPS function tracing working in 3.4 or later?
Yes. Using GCC 4.7.0 on an octeon kernel (based on 3.4.14):
# tracer: function_graph
#
# CPU DURATION FUNCTION CALLS
# | | | | | | |
1) | __fsnotify_parent() {
1) 7.154 us| } /* __fsnotify_parent */
1) | fsnotify() {
1) |__srcu_read_lock() {
1) | add_preempt_count() {
1) 1.356 us| } /* add_preempt_count */
1) | sub_preempt_count() {
1) 1.385 us| } /* sub_preempt_count */
1) 6.747 us|} /* __srcu_read_lock */
1) |__srcu_read_unlock() {
1) | add_preempt_count() {
1) 1.383 us| } /* add_preempt_count */
1) | sub_preempt_count() {
1) 1.358 us| } /* sub_preempt_count */
1) 6.642 us|} /* __srcu_read_unlock */
1) + 17.861 us | } /* fsnotify */
.
.
.
I did figure out why it's hanging and I have some changes that will
allow the function tracer to run without frame pointers, but before I
proceed I want to rule out compiler differences.
Thanks
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Re: [PATCH V2 01/02] MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem
On 03/17/2013 05:49 AM, Huacai Chen wrote:
This and the next patch resolve memory corruption problems while CPU
hotplug. Without these patches, memory corruption can triggered easily
as below:
On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http://
code.google.com/p/byte-unixbench/) and a CPU hotplug script like this
(hotplug.sh):
while true; do
echo 0 >/sys/devices/system/cpu/cpu1/online
echo 0 >/sys/devices/system/cpu/cpu2/online
echo 0 >/sys/devices/system/cpu/cpu3/online
sleep 1
echo 1 >/sys/devices/system/cpu/cpu1/online
echo 1 >/sys/devices/system/cpu/cpu2/online
echo 1 >/sys/devices/system/cpu/cpu3/online
sleep 1
done
Run "hotplug.sh" and then run "spawn 1", spawn will get segfault
after a few minutes.
This patch:
Currently, clear_page()/copy_page() are generated by Micro-assembler
dynamically. But they are unavailable until uasm_resolve_relocs() has
finished because jump labels are illegal before that. Since these
functions are shared by every CPU, we only call build_clear_page()/
build_copy_page() only once at boot time. Without this patch, programs
will get random memory corruption (segmentation fault, bus error, etc.)
while CPU Hotplug (e.g. one CPU is using clear_page() while another is
generating it in cpu_cache_init()).
For similar reasons we modify build_tlb_refill_handler()'s invocation.
V2:
1, Rework the code to make CPU#0 can be online/offline.
2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU
need a per-CPU tlb_refill_handler().
Signed-off-by: Huacai Chen
Signed-off-by: Hongbing Hu
We were seeing the same crashes, this patch set seems to fix the problem.
Acked-by: David Daney
---
arch/mips/include/asm/cpu-features.h |3 +++
.../asm/mach-loongson/cpu-feature-overrides.h |1 +
arch/mips/mm/page.c| 10 ++
arch/mips/mm/tlbex.c | 10 --
4 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h
b/arch/mips/include/asm/cpu-features.h
index 1a57e8b..e5ec8fc 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -113,6 +113,9 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
+#ifndef cpu_has_local_ebase
+#define cpu_has_local_ebase1
+#endif
/*
* I-Cache snoops remote store.This only matters on SMP. Some
multiprocessors
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 75fd8c0..c0f3ef4 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -57,5 +57,6 @@
#define cpu_has_vint 0
#define cpu_has_vtag_icache 0
#define cpu_has_watch 1
+#define cpu_has_local_ebase0
#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index a29fba5..4eb8dcf 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -247,6 +247,11 @@ void __cpuinit build_clear_page(void)
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
int i;
+ static atomic_t run_once = ATOMIC_INIT(0);
+
+ if (atomic_xchg(&run_once, 1)) {
+ return;
+ }
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
@@ -389,6 +394,11 @@ void __cpuinit build_copy_page(void)
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
int i;
+ static atomic_t run_once = ATOMIC_INIT(0);
+
+ if (atomic_xchg(&run_once, 1)) {
+ return;
+ }
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 820e661..6bc28b4 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2162,8 +2162,11 @@ void __cpuinit build_tlb_refill_handler(void)
case CPU_TX3922:
case CPU_TX3927:
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
- build_r3000_tlb_refill_handler();
+ if (cpu_has_local_ebase)
+ build_r3000_tlb_refill_handler();
if (!run_once) {
+ if (!cpu_has_local_ebase)
+ build_r3000_tlb_refill_handler();
build_r3000_tlb_load_handler();
build_r3000_tlb_store_handler();
build_r3000_tlb_modify_handler();
@@ -2192,9 +2195,12 @@ void __cpuinit build_tlb_refill_handler(void)
build_r4000_tlb_load_handler();
build_r4000_tlb_store_handler();
build_r4000_tlb_m
Re: [PATCH V2 02/02] MIPS: Init new mmu_context for each possible CPU to avoid memory corruption
On 03/17/2013 05:50 AM, Huacai Chen wrote:
Currently, init_new_context() only for each online CPU, this may cause
memory corruption when CPU hotplug and fork() happens at the same time.
To avoid this, we make init_new_context() cover each possible CPU.
Scenario:
1, CPU#1 is being offline;
2, On CPU#0, do_fork() call dup_mm() and copy a mm_struct to the child;
3, On CPU#0, dup_mm() call init_new_context(), since CPU#1 is offline
and init_new_context() only covers the online CPUs, child has the
same asid as its parent on CPU#1 (however, child's asid should be 0);
4, CPU#1 is being online;
5, Now, if both parent and child run on CPU#1, memory corruption (e.g.
segfault, bus error, etc.) will occur.
Signed-off-by: Huacai Chen
We were seeing the same crashes, this patch set seems to fix the problem.
Acked-by: David Daney
---
arch/mips/include/asm/mmu_context.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/mmu_context.h
b/arch/mips/include/asm/mmu_context.h
index e81d719..49d220c 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -133,7 +133,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct
*mm)
{
int i;
- for_each_online_cpu(i)
+ for_each_possible_cpu(i)
cpu_context(i, mm) = 0;
return 0;
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Re: [PATCH V2 01/02] MIPS: Build uasm-generated code only once to avoid CPU Hotplug problem
On 03/20/2013 04:14 PM, David Daney wrote:
On 03/17/2013 05:49 AM, Huacai Chen wrote:
This and the next patch resolve memory corruption problems while CPU
hotplug. Without these patches, memory corruption can triggered easily
as below:
[...]
We were seeing the same crashes, this patch set seems to fix the problem.
Acked-by: David Daney
On second thought...
---
arch/mips/include/asm/cpu-features.h |3 +++
.../asm/mach-loongson/cpu-feature-overrides.h |1 +
arch/mips/mm/page.c| 10 ++
arch/mips/mm/tlbex.c | 10 --
4 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h
b/arch/mips/include/asm/cpu-features.h
index 1a57e8b..e5ec8fc 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -113,6 +113,9 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags &
MIPS_CACHE_PINDEX)
#endif
+#ifndef cpu_has_local_ebase
+#define cpu_has_local_ebase1
This really should default to 0 and only be set for (??who knows what??).
David Daney
+#endif
/*
* I-Cache snoops remote store. This only matters on SMP. Some
multiprocessors
diff --git
a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 75fd8c0..c0f3ef4 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -57,5 +57,6 @@
#define cpu_has_vint0
#define cpu_has_vtag_icache0
#define cpu_has_watch1
+#define cpu_has_local_ebase0
#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index a29fba5..4eb8dcf 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -247,6 +247,11 @@ void __cpuinit build_clear_page(void)
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
int i;
+static atomic_t run_once = ATOMIC_INIT(0);
+
+if (atomic_xchg(&run_once, 1)) {
+return;
+}
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
@@ -389,6 +394,11 @@ void __cpuinit build_copy_page(void)
struct uasm_label *l = labels;
struct uasm_reloc *r = relocs;
int i;
+static atomic_t run_once = ATOMIC_INIT(0);
+
+if (atomic_xchg(&run_once, 1)) {
+return;
+}
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 820e661..6bc28b4 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2162,8 +2162,11 @@ void __cpuinit build_tlb_refill_handler(void)
case CPU_TX3922:
case CPU_TX3927:
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
-build_r3000_tlb_refill_handler();
+if (cpu_has_local_ebase)
+build_r3000_tlb_refill_handler();
if (!run_once) {
+if (!cpu_has_local_ebase)
+build_r3000_tlb_refill_handler();
build_r3000_tlb_load_handler();
build_r3000_tlb_store_handler();
build_r3000_tlb_modify_handler();
@@ -2192,9 +2195,12 @@ void __cpuinit build_tlb_refill_handler(void)
build_r4000_tlb_load_handler();
build_r4000_tlb_store_handler();
build_r4000_tlb_modify_handler();
+if (!cpu_has_local_ebase)
+build_r4000_tlb_refill_handler();
run_once++;
}
-build_r4000_tlb_refill_handler();
+if (cpu_has_local_ebase)
+build_r4000_tlb_refill_handler();
}
}
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[PATCH] netdev/phy: Implement ieee802.3 clause 45 in mdio-octeon.c
From: David Daney
The Octeon SMI/MDIO interfaces can do clause 45 communications, so
implement this in the driver.
Signed-off-by: David Daney
---
drivers/net/phy/mdio-octeon.c | 89 +--
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c2c878d..f4f3abf 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2009,2011 Cavium, Inc.
+ * Copyright (C) 2009-2012 Cavium, Inc.
*/
#include
@@ -27,23 +27,93 @@
#define SMI_CLK0x18
#define SMI_EN 0x20
+enum octeon_mdiobus_mode {
+ UNINIT = 0,
+ C22,
+ C45
+};
+
struct octeon_mdiobus {
struct mii_bus *mii_bus;
u64 register_base;
resource_size_t mdio_phys;
resource_size_t regsize;
+ enum octeon_mdiobus_mode mode;
int phy_irq[PHY_MAX_ADDR];
};
+static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
+ enum octeon_mdiobus_mode m)
+{
+ union cvmx_smix_clk smi_clk;
+
+ if (m == p->mode)
+ return;
+
+ smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
+ smi_clk.s.mode = (m == C45) ? 1 : 0;
+ smi_clk.s.preamble = 1;
+ cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
+ p->mode = m;
+}
+
+static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
+ int phy_id, int regnum)
+{
+ union cvmx_smix_cmd smi_cmd;
+ union cvmx_smix_wr_dat smi_wr;
+ int timeout = 1000;
+
+ octeon_mdiobus_set_mode(p, C45);
+
+ smi_wr.u64 = 0;
+ smi_wr.s.dat = regnum & 0x;
+ cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
+
+ regnum = (regnum >> 16) & 0x1f;
+
+ smi_cmd.u64 = 0;
+ smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
+ smi_cmd.s.phy_adr = phy_id;
+ smi_cmd.s.reg_adr = regnum;
+ cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
+
+ do {
+ /*
+* Wait 1000 clocks so we don't saturate the RSL bus
+* doing reads.
+*/
+ __delay(1000);
+ smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
+ } while (smi_wr.s.pending && --timeout);
+
+ if (timeout <= 0)
+ return -EIO;
+ return 0;
+}
+
static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
+ unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
int timeout = 1000;
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 3; /* MDIO_CLAUSE_45_READ */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
+
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
+ smi_cmd.s.phy_op = op; /* MDIO_CLAUSE_22_READ */
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = regnum;
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
@@ -69,14 +139,27 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int
phy_id,
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_wr_dat smi_wr;
+ unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
int timeout = 1000;
+
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 1; /* MDIO_CLAUSE_45_WRITE */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
+ smi_cmd.s.phy_op = op;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = regnum;
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
--
1.7.11.7
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[PATCH v2] netdev/phy: Implement ieee802.3 clause 45 in mdio-octeon.c
From: David Daney
The Octeon SMI/MDIO interfaces can do clause 45 communications, so
implement this in the driver.
Also fix some comment formatting to make it consistent and to comply
with the netdev style.
Signed-off-by: David Daney
---
No code changes from v1, just fixed comment formatting snafu.
Sorry for the spam.
drivers/net/phy/mdio-octeon.c | 94 +++
1 file changed, 87 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c2c878d..39a081b 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2009,2011 Cavium, Inc.
+ * Copyright (C) 2009-2012 Cavium, Inc.
*/
#include
@@ -27,30 +27,98 @@
#define SMI_CLK0x18
#define SMI_EN 0x20
+enum octeon_mdiobus_mode {
+ UNINIT = 0,
+ C22,
+ C45
+};
+
struct octeon_mdiobus {
struct mii_bus *mii_bus;
u64 register_base;
resource_size_t mdio_phys;
resource_size_t regsize;
+ enum octeon_mdiobus_mode mode;
int phy_irq[PHY_MAX_ADDR];
};
+static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
+ enum octeon_mdiobus_mode m)
+{
+ union cvmx_smix_clk smi_clk;
+
+ if (m == p->mode)
+ return;
+
+ smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
+ smi_clk.s.mode = (m == C45) ? 1 : 0;
+ smi_clk.s.preamble = 1;
+ cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
+ p->mode = m;
+}
+
+static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
+ int phy_id, int regnum)
+{
+ union cvmx_smix_cmd smi_cmd;
+ union cvmx_smix_wr_dat smi_wr;
+ int timeout = 1000;
+
+ octeon_mdiobus_set_mode(p, C45);
+
+ smi_wr.u64 = 0;
+ smi_wr.s.dat = regnum & 0x;
+ cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
+
+ regnum = (regnum >> 16) & 0x1f;
+
+ smi_cmd.u64 = 0;
+ smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
+ smi_cmd.s.phy_adr = phy_id;
+ smi_cmd.s.reg_adr = regnum;
+ cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
+
+ do {
+ /* Wait 1000 clocks so we don't saturate the RSL bus
+* doing reads.
+*/
+ __delay(1000);
+ smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
+ } while (smi_wr.s.pending && --timeout);
+
+ if (timeout <= 0)
+ return -EIO;
+ return 0;
+}
+
static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
+ unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
int timeout = 1000;
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 3; /* MDIO_CLAUSE_45_READ */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
+
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
+ smi_cmd.s.phy_op = op; /* MDIO_CLAUSE_22_READ */
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = regnum;
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
do {
- /*
-* Wait 1000 clocks so we don't saturate the RSL bus
+ /* Wait 1000 clocks so we don't saturate the RSL bus
* doing reads.
*/
__delay(1000);
@@ -69,21 +137,33 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int
phy_id,
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_wr_dat smi_wr;
+ unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
int timeout = 1000;
+
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 1; /* MDIO_CLAUSE_45_WRITE */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
+ smi_cmd.s.phy_op = op;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = regnum;
cvmx_write_csr(
Re: [PATCH] netdev/phy: Implement ieee802.3 clause 45 in mdio-octeon.c
On 04/03/2013 12:08 PM, Ben Hutchings wrote:
On Wed, 2013-04-03 at 11:16 -0700, David Daney wrote:
From: David Daney
The Octeon SMI/MDIO interfaces can do clause 45 communications, so
implement this in the driver.
Signed-off-by: David Daney
---
drivers/net/phy/mdio-octeon.c | 89 +--
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c2c878d..f4f3abf 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
[...]
static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
+ unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
int timeout = 1000;
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 3; /* MDIO_CLAUSE_45_READ */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
+
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
+ smi_cmd.s.phy_op = op; /* MDIO_CLAUSE_22_READ */
[...]
This comment should now be removed.
You have very sharp eyes. I will send yet another version of the patch
with this removed.
David Daney
Ben.
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[PATCH v3] netdev/phy: Implement ieee802.3 clause 45 in mdio-octeon.c
From: David Daney
The Octeon SMI/MDIO interfaces can do clause 45 communications, so
implement this in the driver.
Also fix some comment formatting to make it consistent and to comply
with the netdev style.
Signed-off-by: David Daney
---
v3: Remove now bogus comment noted by Ben Huchings
v2: No code changes from v1, just fixed comment formatting snafu.
Sorry for the spam.
drivers/net/phy/mdio-octeon.c | 94 +++
1 file changed, 87 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c2c878d..b51fa1f 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2009,2011 Cavium, Inc.
+ * Copyright (C) 2009-2012 Cavium, Inc.
*/
#include
@@ -27,30 +27,98 @@
#define SMI_CLK0x18
#define SMI_EN 0x20
+enum octeon_mdiobus_mode {
+ UNINIT = 0,
+ C22,
+ C45
+};
+
struct octeon_mdiobus {
struct mii_bus *mii_bus;
u64 register_base;
resource_size_t mdio_phys;
resource_size_t regsize;
+ enum octeon_mdiobus_mode mode;
int phy_irq[PHY_MAX_ADDR];
};
+static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
+ enum octeon_mdiobus_mode m)
+{
+ union cvmx_smix_clk smi_clk;
+
+ if (m == p->mode)
+ return;
+
+ smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
+ smi_clk.s.mode = (m == C45) ? 1 : 0;
+ smi_clk.s.preamble = 1;
+ cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64);
+ p->mode = m;
+}
+
+static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,
+ int phy_id, int regnum)
+{
+ union cvmx_smix_cmd smi_cmd;
+ union cvmx_smix_wr_dat smi_wr;
+ int timeout = 1000;
+
+ octeon_mdiobus_set_mode(p, C45);
+
+ smi_wr.u64 = 0;
+ smi_wr.s.dat = regnum & 0x;
+ cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
+
+ regnum = (regnum >> 16) & 0x1f;
+
+ smi_cmd.u64 = 0;
+ smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
+ smi_cmd.s.phy_adr = phy_id;
+ smi_cmd.s.reg_adr = regnum;
+ cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
+
+ do {
+ /* Wait 1000 clocks so we don't saturate the RSL bus
+* doing reads.
+*/
+ __delay(1000);
+ smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
+ } while (smi_wr.s.pending && --timeout);
+
+ if (timeout <= 0)
+ return -EIO;
+ return 0;
+}
+
static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
{
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_rd_dat smi_rd;
+ unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
int timeout = 1000;
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 3; /* MDIO_CLAUSE_45_READ */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
+
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
+ smi_cmd.s.phy_op = op;
smi_cmd.s.phy_adr = phy_id;
smi_cmd.s.reg_adr = regnum;
cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
do {
- /*
-* Wait 1000 clocks so we don't saturate the RSL bus
+ /* Wait 1000 clocks so we don't saturate the RSL bus
* doing reads.
*/
__delay(1000);
@@ -69,21 +137,33 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int
phy_id,
struct octeon_mdiobus *p = bus->priv;
union cvmx_smix_cmd smi_cmd;
union cvmx_smix_wr_dat smi_wr;
+ unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
int timeout = 1000;
+
+ if (regnum & MII_ADDR_C45) {
+ int r = octeon_mdiobus_c45_addr(p, phy_id, regnum);
+ if (r < 0)
+ return r;
+
+ regnum = (regnum >> 16) & 0x1f;
+ op = 1; /* MDIO_CLAUSE_45_WRITE */
+ } else {
+ octeon_mdiobus_set_mode(p, C22);
+ }
+
smi_wr.u64 = 0;
smi_wr.s.dat = val;
cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
smi_cmd.u64 = 0;
- smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
+ smi_cmd.s.phy_op = op;
smi_cmd.s.phy_adr = phy_
Re: [PATCH 07/19] scripts/sortextable: silence script output
On 01/25/2013 06:14 AM, Arnd Bergmann wrote:
The exception table sorter outputs one line every time
it gets called, e.g. 'sort done marker at 66dc00', which
is slightly annoying when doing 'make -s' which is otherwise
completely silent. Since that output is not helpful to
most people building the kernel, turn it off by default.
Signed-off-by: Arnd Bergmann
Cc: David Daney
Cc: "H. Peter Anvin"
Leaving that enabled was an oversight. Thanks for fixing it...
Acked-by: David Daney
---
scripts/sortextable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/sortextable.h b/scripts/sortextable.h
index e4fd45b..f5eb43d 100644
--- a/scripts/sortextable.h
+++ b/scripts/sortextable.h
@@ -182,7 +182,7 @@ do_func(Elf_Ehdr *ehdr, char const *const fname,
table_sort_t custom_sort)
_r(&sort_needed_sym->st_value) -
_r(&sort_needed_sec->sh_addr);
-#if 1
+#if 0
printf("sort done marker at %lx\n",
(unsigned long)((char *)sort_done_location - (char *)ehdr));
#endif
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Re: I2C: Fix i2c fail problem when a process is terminated by a signal on octeon in 3.8
On 02/26/2013 12:54 PM, 송은봉 wrote:
> I've been debugging the abnormal operation of i2c on octeon.
> If a process is terminated by signal in the middle of i2c operation,
> next i2c read operation which is done by another process was failed.
> So i changed to ignore signal in the middle of i2c operation.
> After that the problem was not reproduced.
>
This is a known issue. However I don't think the solution you have is
correct...
> Signed-off-by: EunBong Song <mailto:eunb.s...@samsung.com>>
>
> diff -up drivers/i2c/busses/i2c-octeon.c{.orig,}
> --- drivers/i2c/busses/i2c-octeon.c.orig 2013-02-21 08:09:03.168018843 -0800
> +++ drivers/i2c/busses/i2c-octeon.c 2013-02-21 08:09:38.344018898 -0800
> @@ -183,7 +183,7 @@ static irqreturn_t octeon_i2c_isr(int ir
>struct octeon_i2c *i2c = dev_id;
>
>octeon_i2c_int_disable(i2c);
> - wake_up_interruptible(&i2c->queue);
> + wake_up(&i2c->queue);
>
>return IRQ_HANDLED;
> }
> @@ -206,7 +206,7 @@ static int octeon_i2c_wait(struct octeon
>
>octeon_i2c_int_enable(i2c);
>
> - result = wait_event_interruptible_timeout(i2c->queue,
> + result = wait_event_timeout(i2c->queue,
If the wait is not interruptible, I think you will not be able to 'kill
-9' a userspace process blocked here.
> octeon_i2c_test_iflg(i2c),
> i2c->adap.timeout);
>
The real solution is to move processing of the I2C protocol to a kernel
thread and communicate between the this thread and userspace via a
command queue mechanism, much like the way it is done in the mmc/host
driver infrastructure.
David Daney
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[PATCH] hrtimer/trivial: Fix comment text in hrtimer.c
From: David Daney The comments mention HRTIMER_ABS and HRTIMER_REL, these symbols don't exist, the proper names are HRTIMER_MODE_ABS and HRTIMER_MODE_REL. Signed-off-by: David Daney --- kernel/hrtimer.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c index 6db7a5e..f749bb9 100644 --- a/kernel/hrtimer.c +++ b/kernel/hrtimer.c @@ -1008,7 +1008,8 @@ int __hrtimer_start_range_ns(struct hrtimer *timer, ktime_t tim, * @timer: the timer to be added * @tim: expiry time * @delta_ns: "slack" range for the timer - * @mode: expiry mode: absolute (HRTIMER_ABS) or relative (HRTIMER_REL) + * @mode: expiry mode: absolute (HRTIMER_MODE_ABS) or + * relative (HRTIMER_MODE_REL) * * Returns: * 0 on success @@ -1025,7 +1026,8 @@ EXPORT_SYMBOL_GPL(hrtimer_start_range_ns); * hrtimer_start - (re)start an hrtimer on the current CPU * @timer: the timer to be added * @tim: expiry time - * @mode: expiry mode: absolute (HRTIMER_ABS) or relative (HRTIMER_REL) + * @mode: expiry mode: absolute (HRTIMER_MODE_ABS) or + * relative (HRTIMER_MODE_REL) * * Returns: * 0 on success -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 09/25] MIPS: Octeon: use ehci-platform driver
On 10/03/2012 08:03 AM, Florian Fainelli wrote: Signed-off-by: Florian Fainelli --- arch/mips/cavium-octeon/octeon-platform.c | 43 - 1 file changed, 42 insertions(+), 1 deletion(-) NACK. OCTEON uses device tree now (or as soon as I send in the corresponding patches), so this would just be churning the code. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 18/25] MIPS: Octeon: use OHCI platform driver
On 10/03/2012 08:03 AM, Florian Fainelli wrote: Signed-off-by: Florian Fainelli --- arch/mips/cavium-octeon/octeon-platform.c | 37 - 1 file changed, 36 insertions(+), 1 deletion(-) NACK. Same reason as for the EHCI one (09/25): OCTEON uses device tree now (or as soon as I send in the corresponding patches), so this would just be churning the code. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] Partially revert a1ce39288e6fbef (UAPI: (Scripted) Convert #include "..." to #include in kernel system headers)
From: David Daney Syntax errors were introduced into include/linux/libfdt.h by the offending commit, revert the changes made to this file. The kernel again compiles, thus restoring harmony and balance to the universe. Signed-off-by: David Daney Cc: David Howells Cc: Arnd Bergmann Cc: Thomas Gleixner Cc: Paul E. McKenney Cc: Dave Jones --- include/linux/libfdt.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h index a0c3bf6..4c0306c 100644 --- a/include/linux/libfdt.h +++ b/include/linux/libfdt.h @@ -2,7 +2,7 @@ #define _INCLUDE_LIBFDT_H_ #include -#include <> -#include <> +#include "../../scripts/dtc/libfdt/fdt.h" +#include "../../scripts/dtc/libfdt/libfdt.h" #endif /* _INCLUDE_LIBFDT_H_ */ -- 1.7.11.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RFT RESEND linux-next] mips: dma-mapping: support debug_dma_mapping_error
On 10/26/2012 09:01 AM, Shuah Khan wrote:
Add support for debug_dma_mapping_error() call to avoid warning from
debug_dma_unmap() interface when it checks for mapping error checked
status. Without this patch, device driver failed to check map error
warning is generated.
Signed-off-by: Shuah Khan
---
arch/mips/include/asm/dma-mapping.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/dma-mapping.h
b/arch/mips/include/asm/dma-mapping.h
index be39a12..006b43e 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -40,6 +40,8 @@ static inline int dma_supported(struct device *dev, u64 mask)
static inline int dma_mapping_error(struct device *dev, u64 mask)
{
struct dma_map_ops *ops = get_dma_ops(dev);
+
+ debug_dma_mapping_error(dev, mask);
return ops->mapping_error(dev, mask);
}
Although this is a start, I don't think it is sufficient.
As far as I can tell, there are many missing calls to debug_dma_*() in
the various MIPS commone and sub-architecture DMA code.
Really you (or someone) needs to look at *all* the functions in
arch/mips/asm/dma-mapping.h, and arch/mips/mm/dma-default.c and find
places missing a debug_dma_*().
Thanks,
David Daney
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Re: [PATCH RFT RESEND linux-next] mips: dma-mapping: support debug_dma_mapping_error
On 10/26/2012 10:06 AM, Shuah Khan wrote:
On Fri, 2012-10-26 at 09:45 -0700, David Daney wrote:
On 10/26/2012 09:01 AM, Shuah Khan wrote:
Add support for debug_dma_mapping_error() call to avoid warning from
debug_dma_unmap() interface when it checks for mapping error checked
status. Without this patch, device driver failed to check map error
warning is generated.
Signed-off-by: Shuah Khan
---
arch/mips/include/asm/dma-mapping.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/dma-mapping.h
b/arch/mips/include/asm/dma-mapping.h
index be39a12..006b43e 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -40,6 +40,8 @@ static inline int dma_supported(struct device *dev, u64 mask)
static inline int dma_mapping_error(struct device *dev, u64 mask)
{
struct dma_map_ops *ops = get_dma_ops(dev);
+
+ debug_dma_mapping_error(dev, mask);
return ops->mapping_error(dev, mask);
}
Although this is a start, I don't think it is sufficient.
As far as I can tell, there are many missing calls to debug_dma_*() in
the various MIPS commone and sub-architecture DMA code.
Really you (or someone) needs to look at *all* the functions in
arch/mips/asm/dma-mapping.h, and arch/mips/mm/dma-default.c and find
places missing a debug_dma_*().
Is it correct to assume that this patch is not needed on MIPS until
debug_dma interfaces get added to MIPS common and sub-architecture DMA
code.
No, you have a false predicate here.
debug_dma_* *is* already mostly added. The problem is that it is
incomplete. That is the nature of the problem. Your patch makes it
slightly better, but doesn't fully fix the problems.
When I didn't see dma_map_page() in arch/mips/include/asm/dma-mapping.h
defined, and just an extern, I incorrectly assumed, it is getting picked
up from , hence the need for this
patch in the first place.
-- Shuah
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Re: [PATCH RFT RESEND linux-next] mips: dma-mapping: support debug_dma_mapping_error
On 10/26/2012 02:51 PM, Shuah Khan wrote: On 10/26/2012 09:01 AM, Shuah Khan wrote: Add support for debug_dma_mapping_error() call to avoid warning from debug_dma_unmap() interface when it checks for mapping error checked status. Without this patch, device driver failed to check map error warning is generated. I'm confused. Your claim that a 'warning is generated' seems to be in conflict with... [...] Got it. Thanks. I would volunteer to look at fixing all the problems, but unfortunately I don't have a MIPS box handy This statement that you don't have hardware that exhibits the problem. How was the patch tested? How do you even know there is a problem? David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] i2c-EEPROM: Export memory accessor
On 10/31/2012 08:56 AM, Pantelis Antoniou wrote: Various platforms need access to the EEPROM in other places besides their platform registration callbacks. Export the memory accessor to the i2c_client i2c_clients are *not* intrinsically memory, so adding this to the generic i2c_client structure doesn't really make sense. What would the semantics of this interface be with respect to temperature sensors and GPIO expanders? NACK. and implement it for the at24 driver. And before you ask, no, the platform callback can't be used for anything that depends on DT. Why can't you just allocate (and populate) a struct at24_platform_data for the device if it isn't supplied by whatever created the device? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] i2c-EEPROM: Export memory accessor
On 10/30/2012 11:51 AM, Pantelis Antoniou wrote: Hi David, On Oct 30, 2012, at 8:46 PM, David Daney wrote: On 10/31/2012 08:56 AM, Pantelis Antoniou wrote: Various platforms need access to the EEPROM in other places besides their platform registration callbacks. Export the memory accessor to the i2c_client i2c_clients are *not* intrinsically memory, so adding this to the generic i2c_client structure doesn't really make sense. What would the semantics of this interface be with respect to temperature sensors and GPIO expanders? NACK. It's only filled in for EEPROM devices. There's no other I2C memory read interface for kernel clients. Basically you are tacking on a registery of memory devices to some random data structure that has nothing to do with memory. Instead ... and implement it for the at24 driver. And before you ask, no, the platform callback can't be used for anything that depends on DT. Why can't you just allocate (and populate) a struct at24_platform_data for the device if it isn't supplied by whatever created the device? There are no platform_data in the case of device tree only generic-boards. Everything is configured via the DT and there are no callbacks. DT is a purely data driver concept. I'm open to suggestions on how to read an EEPROM from another kernel client, when there's no such thing as platform_data anymore. ... you need some sort of collection memory devices that can be queried by phandle and/or some other handle. Any device that implements the struct memory_accessor interface could add itself to the collection, then code that needs to use the memory_accessor interface would look up the proper target for the operation by phandle or whatever other handle the system is using. Similar to how of_phy_find_device() works. I don't know if it would be possible to create a 'memory_accessor' bus, but that is one idea I had. David Daney Regards -- Pantelis -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] rwsem: add rwsem_is_contended
On 09/16/2013 05:05 PM, Josef Bacik wrote: On Mon, Sep 16, 2013 at 04:05:47PM -0700, Andrew Morton wrote: On Fri, 30 Aug 2013 10:14:01 -0400 Josef Bacik wrote: Btrfs uses an rwsem to control access to its extent tree. Threads will hold a read lock on this rwsem while they scan the extent tree, and if need_resched() they will drop the lock and schedule. The transaction commit needs to take a write lock for this rwsem for a very short period to switch out the commit roots. If there are a lot of threads doing this caching operation we can starve out the committers which slows everybody out. To address this we want to add this functionality to see if our rwsem has anybody waiting to take a write lock so we can drop it and schedule for a bit to allow the commit to continue. Thanks, This sounds rather nasty and hacky. Rather then working around a locking shortcoming in a caller it would be better to fix/enhance the core locking code. What would such a change need to do? Presently rwsem waiters are fifo-queued, are they not? So the commit thread will eventually get that lock. Apparently that's not working adequately for you but I don't fully understand what it is about these dynamics which is causing observable problems. So the problem is not that its normal lock starvation, it's more our particular use case that is causing the starvation. We can have lots of people holding readers and simply never give them up for long periods of time, which is why we need this is_contended helper so we know to drop things and let the committer through. Thanks, You could easily achieve the same thing by putting an "is_contending" flag in parallel with the rwsem and testing that: DECLARE_RWSEM(foo); atomic_t is_contended = ATOMIC_INIT(0); . . . /* writing context */ atomic_inc(&is_contended); down_write(&foo); do_writing_action(); up_write(&foo); atomic_dec(&is_contended); /* reading context */ down_read(&foo); while (!atomic_read(&is_contended)) do_reading_actions(); up_read(&foo); David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] rwsem: add rwsem_is_contended
On 09/16/2013 05:37 PM, Peter Hurley wrote: On 09/16/2013 08:29 PM, David Daney wrote: On 09/16/2013 05:05 PM, Josef Bacik wrote: On Mon, Sep 16, 2013 at 04:05:47PM -0700, Andrew Morton wrote: On Fri, 30 Aug 2013 10:14:01 -0400 Josef Bacik wrote: Btrfs uses an rwsem to control access to its extent tree. Threads will hold a read lock on this rwsem while they scan the extent tree, and if need_resched() they will drop the lock and schedule. The transaction commit needs to take a write lock for this rwsem for a very short period to switch out the commit roots. If there are a lot of threads doing this caching operation we can starve out the committers which slows everybody out. To address this we want to add this functionality to see if our rwsem has anybody waiting to take a write lock so we can drop it and schedule for a bit to allow the commit to continue. Thanks, This sounds rather nasty and hacky. Rather then working around a locking shortcoming in a caller it would be better to fix/enhance the core locking code. What would such a change need to do? Presently rwsem waiters are fifo-queued, are they not? So the commit thread will eventually get that lock. Apparently that's not working adequately for you but I don't fully understand what it is about these dynamics which is causing observable problems. So the problem is not that its normal lock starvation, it's more our particular use case that is causing the starvation. We can have lots of people holding readers and simply never give them up for long periods of time, which is why we need this is_contended helper so we know to drop things and let the committer through. Thanks, You could easily achieve the same thing by putting an "is_contending" flag in parallel with the rwsem and testing that: Which adds a bunch more bus-locked operations to contended over Would that be a problem in this particular case? Has it been measured? , when a unlocked if (list_empty()) is sufficient. I don't object to adding rwsem_is_contended() *if* it is required. I was just pointing out that there may be other options. The patch adds a bunch of new semantics to rwsem. There is a trade off between increased complexity of core code, and generalizing subsystem specific optimizations that may not be globally useful. Is it worth it in this case? I do not know. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 2/5] ARM64: Move some signal code to a seperate file to be reused by ILP32.
On 09/09/2013 02:38 PM, Andrew Pinski wrote: On Mon, Sep 9, 2013 at 2:32 PM, Andrew Pinski wrote: Since the ILP32 ABI uses similar signal code as the LP64 ABI, it makes sense to reuse rather than copy the same code. I just noticed that signal_template.c was not part of this patch but it is included with patch number 5. At a minimum, the patch set should be respun so that it builds, runs and has no unusable Kconfig options at all intermediate points in the set. You could also consider splitting out cosmetic changes unrelated to the meat of a change to a separate patches. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: Issue with BUG() in asm-gemeric/bug.h if CONFIG_BUG=n
On 09/30/2013 07:56 AM, Ralf Baechle wrote:
Lately I received several patches for build issues that only strike if
CONFIG_BUG is disabled. Here's a test case extracted from one of them:
/*
* Definition of BUG taken from asm-generic/bug.h for the CONFIG_BUG=n case
*/
#define BUG() do {} while(0)
int foo(int arg)
{
int res;
if (arg == 1)
res = 23;
else if (arg == 2)
res = 42;
else
BUG();
return res;
}
[ralf@h7 ~]$ gcc -O2 -Wall -c bug.c
bug.c: In function ‘foo’:
bug.c:17:2: warning: ‘res’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
return res;
^
It's fairly obvious to see what's happening here - GCC doesn't know that
the else case can not be reached, thus razorsharply concludes that res
may be used uninitialized.
There several locations where MIPS - possibly other architectures as well -
is affected by this.
I think the definition of BUG should be changed to something like
#define BUG() unreachable()
16304
unreachable() will depending on the compiler being used, expand either
into a call to __builtin_unreachable() or where that function is
unavailable, into do {} while (1).
The *only* reason we have CONFIG_BUG=n is to reduce code size.
Sticking in that empty loop, negates the entire point.
IMHO: We should do one of:
o Make CONFIG_BUG=y mandatory
o Ignore the warnings.
o Fix the warning sites so they quit Warning.
So I don't think the patch is really an improvement over the status quo.
David Daney
__builtin_unreachable() was introduce for GCC 4.5.0.
This means there'd be minor bloat for antique compilers - but probably
even better code generation for compilers supporting __builtin_unreachable().
Ralf
Signed-off-by: Ralf Baechle
include/asm-generic/bug.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..6f78771 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -108,7 +108,7 @@ extern void warn_slowpath_null(const char *file, const int
line);
#else /* !CONFIG_BUG */
#ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
+#define BUG() unreachable()
#endif
#ifndef HAVE_ARCH_BUG_ON
- End forwarded message -
Ralf
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Re: Issue with BUG() in asm-gemeric/bug.h if CONFIG_BUG=n
On 09/30/2013 10:15 AM, Pinski, Andrew wrote:
On Sep 30, 2013, at 9:20 AM, "David Daney" wrote:
On 09/30/2013 07:56 AM, Ralf Baechle wrote:
Lately I received several patches for build issues that only strike if
CONFIG_BUG is disabled. Here's a test case extracted from one of them:
/*
* Definition of BUG taken from asm-generic/bug.h for the CONFIG_BUG=n case
*/
#define BUG()do {} while(0)
int foo(int arg)
{
int res;
if (arg == 1)
res = 23;
else if (arg == 2)
res = 42;
else
BUG();
return res;
}
[ralf@h7 ~]$ gcc -O2 -Wall -c bug.c
bug.c: In function ‘foo’:
bug.c:17:2: warning: ‘res’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
return res;
^
It's fairly obvious to see what's happening here - GCC doesn't know that
the else case can not be reached, thus razorsharply concludes that res
may be used uninitialized.
There several locations where MIPS - possibly other architectures as well -
is affected by this.
I think the definition of BUG should be changed to something like
#define BUG()unreachable()
16304
unreachable() will depending on the compiler being used, expand either
into a call to __builtin_unreachable() or where that function is
unavailable, into do {} while (1).
The *only* reason we have CONFIG_BUG=n is to reduce code size.
Sticking in that empty loop, negates the entire point.
IMHO: We should do one of:
o Make CONFIG_BUG=y mandatory
o Ignore the warnings.
o Fix the warning sites so they quit Warning.
So I don't think the patch is really an improvement over the status quo.
What about using __builtin_unreachable when we can but turn off warnings and
use do{}while(0) when __builtin_unreachable does not exist? This seems the
both worlds. Newer compilers produce better code with unreachable anyways.
Simply not true.
do{}while(0) is a NOP it is no more useful than an ';' statement. It
doesn't serve as a magic uninitialized variable hiding mechanism.
David Daney
Thanks,
Andrew
David Daney
__builtin_unreachable() was introduce for GCC 4.5.0.
This means there'd be minor bloat for antique compilers - but probably
even better code generation for compilers supporting __builtin_unreachable().
Ralf
Signed-off-by: Ralf Baechle
include/asm-generic/bug.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 7d10f96..6f78771 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -108,7 +108,7 @@ extern void warn_slowpath_null(const char *file, const int
line);
#else /* !CONFIG_BUG */
#ifndef HAVE_ARCH_BUG
-#define BUG() do {} while(0)
+#define BUG() unreachable()
#endif
#ifndef HAVE_ARCH_BUG_ON
- End forwarded message -
Ralf
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Re: Issue with BUG() in asm-gemeric/bug.h if CONFIG_BUG=n
On 09/30/2013 12:03 PM, Geert Uytterhoeven wrote:
On Mon, Sep 30, 2013 at 7:45 PM, David Daney wrote:
What about using __builtin_unreachable when we can but turn off warnings
and use do{}while(0) when __builtin_unreachable does not exist? This seems
the both worlds. Newer compilers produce better code with unreachable
anyways.
Simply not true.
do{}while(0) is a NOP it is no more useful than an ';' statement. It
doesn't serve as a magic uninitialized variable hiding mechanism.
You missed the "turn off warnings" part of the "and".
You are correct, I did miss it.
The real problem here is that the kernel is written to expect that BUG()
never returns. Any implementation that has BUG() return, is almost
certainly *not* what we want.
But wieh people select CONFIG_BUG=n they expect the smallest possible code.
These two criteria are mutually exclusive, so something should change.
It is not just the uninitialized variable warning, there can be others
as well (control reaching the end of a non-void function comes to mind).
So I don't think turning off the warnings is a good solution.
That leaves:
1) Remove CONFIG_BUG and make it unconditionally enabled.
2) Make CONFIG_BUG=n imply "static inline void BUG(void){do{}while(1);}"
which might be bigger than with CONFIG_BUG=y
David Daney
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH] RapidIO: Fix trivial comment error.
From: Chad Reese The resource index for the mailboxes was incorrect. Signed-off-by: Chad Reese --- include/linux/rio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/rio.h b/include/linux/rio.h index dc0c755..dd418d1 100644 --- a/include/linux/rio.h +++ b/include/linux/rio.h @@ -58,7 +58,7 @@ * * 0 RapidIO inbound doorbells * 1 RapidIO inbound mailboxes - * 1 RapidIO outbound mailboxes + * 2 RapidIO outbound mailboxes */ #define RIO_DOORBELL_RESOURCE 0 #define RIO_INB_MBOX_RESOURCE 1 -- 1.7.11.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] MIPS: Avoid Machine Check by flushing entire page range in huge_ptep_set_access_flags().
From: David Daney
Problem:
1) Huge page mapping of anonymous memory is initially invalid. Will be
faulted in by copy-on-write mechanism.
2) Userspace attempts store at the end of the huge mapping.
3) TLB Refill exception handler fill TLB with a normal (4K sized)
invalid page at the end of the huge mapping virtual address range.
4) Userspace restarted, and re-attempts the store at the end of the
huge mapping.
5) Page from #3 is invalid, we get a fault and go to the hugepage
fault handler. This tries to map a huge page and calls
huge_ptep_set_access_flags() to install the mapping.
6) We just call the generic ptep_set_access_flags() to set up the page
tables, but the flush there assumes a normal (4K sized) page and
only tries to flush the first part of the huge page virtual address
out of the TLB, since the existing entry from step #3 doesn't
conflict, nothing is flushed.
7) We attempt to load the mapping into the TLB, but because it
conflicts with the entry from step #3, we get a Machine Check
exception.
The fix: Flush the entire rage covered by the huge page in
huge_ptep_set_access_flags(), and remove the optimization in
local_flush_tlb_range() so that the flush actually does the correct
thing.
Signed-off-by: David Daney
---
arch/mips/include/asm/hugetlb.h | 12 +++-
arch/mips/mm/tlb-r4k.c | 18 --
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index 58d3688..68670b1 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -95,7 +95,17 @@ static inline int huge_ptep_set_access_flags(struct
vm_area_struct *vma,
pte_t *ptep, pte_t pte,
int dirty)
{
- return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+ int changed = !pte_same(*ptep, pte);
+
+ if (changed) {
+ set_pte_at(vma->vm_mm, addr, ptep, pte);
+ /*
+* There could be some standard sized pages in there,
+* get them all.
+*/
+ flush_tlb_range(vma, addr, addr + HPAGE_SIZE);
+ }
+ return changed;
}
static inline pte_t huge_ptep_get(pte_t *ptep)
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index d2572cb..1df4d2f 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -120,18 +120,11 @@ void local_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start,
if (cpu_context(cpu, mm) != 0) {
unsigned long size, flags;
- int huge = is_vm_hugetlb_page(vma);
ENTER_CRITICAL(flags);
- if (huge) {
- start = round_down(start, HPAGE_SIZE);
- end = round_up(end, HPAGE_SIZE);
- size = (end - start) >> HPAGE_SHIFT;
- } else {
- start = round_down(start, PAGE_SIZE << 1);
- end = round_up(end, PAGE_SIZE << 1);
- size = (end - start) >> (PAGE_SHIFT + 1);
- }
+ start = round_down(start, PAGE_SIZE << 1);
+ end = round_up(end, PAGE_SIZE << 1);
+ size = (end - start) >> (PAGE_SHIFT + 1);
if (size <= current_cpu_data.tlbsize/2) {
int oldpid = read_c0_entryhi();
int newpid = cpu_asid(cpu, mm);
@@ -140,10 +133,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start,
int idx;
write_c0_entryhi(start | newpid);
- if (huge)
- start += HPAGE_SIZE;
- else
- start += (PAGE_SIZE << 1);
+ start += (PAGE_SIZE << 1);
mtc0_tlbw_hazard();
tlb_probe();
tlb_probe_hazard();
--
1.7.11.7
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Re: [RFC] MIPS: BCM63XX: add simple Device Tree includes for all SoCs
On 11/12/2012 08:54 PM, Stephen Warren wrote:
On 11/11/2012 05:50 AM, Jonas Gorski wrote:
Add simple Device Tree include files for all currently supported SoCs.
These will be populated with device definitions as driver support
gets added.
arch/mips/bcm63xx/dts/bcm6328.dtsi | 30 ++
arch/mips/bcm63xx/dts/bcm6338.dtsi | 30 ++
arch/mips/bcm63xx/dts/bcm6345.dtsi | 30 ++
arch/mips/bcm63xx/dts/bcm6348.dtsi | 30 ++
arch/mips/bcm63xx/dts/bcm6358.dtsi | 33 +
arch/mips/bcm63xx/dts/bcm6368.dtsi | 33 +
All of ARM, c6x, microblaze, openrisc, powerpc put device tree files
into arch/${arch}/boot/dts/ - should MIPS follow the same layout?
At this point, I don't see what the benefit of centralizing all of these
would be. Currently there is no concept of a single kernel image that
would work across multiple MIPS system implementations. So keeping the
DTS files with their users makes some organizational sense.
Similar arguments could be made for moving all the files in `find .
-name \*.dts\*` to a top level dts/ directory.
David Daney
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Re: [PATCH] scripts/sortextable: support objects with more than 64K sections.
On 11/05/2012 01:06 AM, Jamie Iles wrote: Building with a large config and -ffunction-sections results in a large number of sections and sortextable needs to be able to handle that. Implement support for > 64K sections as modpost does. Cc: David Daney Cc: H. Peter Anvin Signed-off-by: Jamie Iles --- scripts/sortextable.c | 24 scripts/sortextable.h | 26 +++--- 2 files changed, 47 insertions(+), 3 deletions(-) I don't plan on extensively testing this, but I have no objections. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: Why Cypress does not upstream its trackpad driver?
On 11/07/2012 03:30 PM, David Solda wrote:
Kamal,
My name is Dave Solda and I would be happy to answer any other questions that
you have. Troy's response is correct however as in order to support the default
Linux mouse class, our firmware would also have to be modified to do so, which
cannot be done in system. Our packet protocol maxes out at an 8 byte packet,
which requires a change to the Linux standard in this case.
Our goal in working with canonical was to provide something on Linux that would
support multi-touch and not only have default single finger movement supported.
If I am mistaken and he Linux kernel would accept this, then we can proceed to
upstream, however all indications we have is that this patch would be rejected.
If you (or others on from the locus alias) have any inputs, I would be happy
to receive them.
Really you should ask yourselves:
1) What benefit do you enjoy by keeping the code out of the upstream kernel?
2) What are the benefits of having a driver for your hardware in the
upstream kernel?
If 2 > 1, then the course of action seems obvious.
Doing nothing because of some perceived impediment doesn't help anybody.
David Daney
Dave
On Nov 8, 2012, at 7:13 AM, "Troy Abercrombia" wrote:
Hello Kamal
Unfortunately, We're not able to upstream the driver as it would be denied
because it changes the Linux mouse structure framework.
Thanks
Troy
-Original Message-
From: Kamal Mostafa [mailto:ka...@canonical.com]
Sent: Wednesday, November 07, 2012 10:32 AM
To: Ozan Çağlayan
Cc: linux-kernel@vger.kernel.org; linux-in...@vger.kernel.org;
dmitry.torok...@gmail.com; customercare; mario_limoncie...@dell.com
Subject: Re: Why Cypress does not upstream its trackpad driver?
On Tue, 2012-11-06 at 17:47 -0500, Ozan Çağlayan wrote:
Hi,
This driver [0] was written with a cooperation of Cypress, Dell and
Canonical Engineers within the last 3-4 months. It is very nice that
Cypress as a vendor cooperated with Canonical (Because Canonical works
with Dell for their Project Sputnik and Dell XPS13 is used as the main
hardware for that project and Dell XPS13 has this type of trackpad,
Bingo!), and I am also glad that Ubuntu users benefits from this
driver.
The driver brings multi-touch scrolling, disable-while-tapping and
makes Fn+Fx touchpad disable/enable work for not only Dell XPS13 but
for all laptops having this trackpad (My Lenovo Ultrabook U300s for
example, I tested the patches on fedora 17's 3.6 kernel and it works
quiet nice)
But what I am not getting that why NOBODY from Cypress/Canonical/Dell
isn't bothering to push this driver to upstream?
In fact, Canonical is working on preparing the Cypress PS/2 trackpad driver for
submitting upstream.
Is it too hard? I don't think so as the patches are quite non-invasive
and small.
Your estimate of the work/risk involved not withstanding, I chose to deploy this
experimental driver in stages -- first in the oem-specific "Sputnik project"
kernel, then (recently) in the main Ubuntu kernel, then finally (soon) upstream -- so as
to minimize regressions while shaking out the bugs. For example, the version to which
you linked does include a regression (breaks some ALPS touchpads) which we discovered
only after deploying in Ubuntu.
I expect to submit the Cypress driver upstream within two weeks. Of course, my
work on the driver is (and has been) publicly available[1].
-Kamal Mostafa
[1] The latest version of this driver is represented by the patch set:
http://kernel.ubuntu.com/git?p=ubuntu%2Fubuntu-quantal.git&a=search&h=HEAD&st=commit&s=Cypress+PS%2F2
Is the only distribution around is Ubuntu?
Is the only laptop sold in the world is Dell XPS13 with an Ubuntu?
I'm not trying to be impolite but it hurts me to see that a vendor
produces an open-source driver for its device but makes use of it only
through a specific distribution.
If Cypress is just beginning developing open-source drivers for their
devices, I hope that after this mail they will be much sensitive about
the issue and push their drivers even before the release of their
devices to make user experience flawless.
(I googled and searched the archives of LKML and linux-input but
couldn't find a discussion or patch series about the driver. If I
missed it, ignore the whole stuff above)
[0]: http://patchwork.ozlabs.org/patch/178903/
This message and any attachments may contain Cypress (or its subsidiaries)
confidential information. If it has been received in error, please advise the
sender and immediately delete this message.
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0��h��i
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Re: [RFC PATCH 3/3] x86,smp: auto tune spinlock backoff delay factor
On 12/21/2012 03:51 PM, Rik van Riel wrote:
Subject: x86,smp: auto tune spinlock backoff delay factor
Nice work,
A couple of comments...
Many spinlocks are embedded in data structures; having many CPUs
pounce on the cache line the lock is in will slow down the lock
holder, and can cause system performance to fall off a cliff.
The paper "Non-scalable locks are dangerous" is a good reference:
http://pdos.csail.mit.edu/papers/linux:lock.pdf
In the Linux kernel, spinlocks are optimized for the case of
there not being contention. After all, if there is contention,
the data structure can be improved to reduce or eliminate
lock contention.
Likewise, the spinlock API should remain simple, and the
common case of the lock not being contended should remain
as fast as ever.
However, since spinlock contention should be fairly uncommon,
we can add functionality into the spinlock slow path that keeps
system performance from falling off a cliff when there is lock
contention.
Proportional delay in ticket locks is delaying the time between
checking the ticket based on a delay factor, and the number of
CPUs ahead of us in the queue for this lock. Checking the lock
less often allows the lock holder to continue running, resulting
in better throughput and preventing performance from dropping
off a cliff.
Proportional spinlock delay with a high delay factor works well
when there is lots contention on a lock. Likewise, a smaller
delay factor works well when a lock is lightly contended.
Making the code auto-tune the delay factor results in a system
that performs well with both light and heavy lock contention.
Signed-off-by: Rik van Riel
---
arch/x86/kernel/smp.c | 49 ++---
1 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
index 1c1eb02..8786476 100644
--- a/arch/x86/kernel/smp.c
+++ b/arch/x86/kernel/smp.c
@@ -113,19 +113,62 @@ static atomic_t stopping_cpu = ATOMIC_INIT(-1);
static bool smp_no_nmi_ipi = false;
/*
- * Wait on a congested ticket spinlock.
+ * Wait on a congested ticket spinlock. Many spinlocks are embedded in
+ * data structures; having many CPUs pounce on the cache line with the
+ * spinlock simultaneously can slow down the lock holder, and the system
+ * as a whole.
+ *
+ * To prevent total performance collapse in case of bad spinlock contention,
+ * perform proportional backoff. The per-cpu value of delay is automatically
+ * tuned to limit the number of times spinning CPUs poll the lock before
+ * obtaining it. This limits the amount of cross-CPU traffic required to obtain
+ * a spinlock, and keeps system performance from dropping off a cliff.
+ *
+ * There is a tradeoff. If we poll too often, the whole system is slowed
+ * down. If we sleep too long, the lock will go unused for a period of
+ * time. Adjusting "delay" to poll, on average, 2.7 times before the
+ * lock is obtained seems to result in low bus traffic. The combination
+ * of aiming for a non-integer amount of average polls, and scaling the
+ * sleep period proportionally to how many CPUs are ahead of us in the
+ * queue for this ticket lock seems to reduce the amount of time spent
+ * "oversleeping" the release of the lock.
*/
+#define MIN_SPINLOCK_DELAY 1
+#define MAX_SPINLOCK_DELAY 1000
+DEFINE_PER_CPU(int, spinlock_delay) = { MIN_SPINLOCK_DELAY };
This gives the same delay for all locks in the system, but the amount of
work done under each lock is different. So, for any given lock, the
delay is not optimal.
This is an untested idea that came to me after looking at this:
o Assume that for any given lock, the optimal delay is the same for all
CPUs in the system.
o Store a per-lock delay value in arch_spinlock_t.
o Once a CPU owns the lock it can update the delay as you do for the
per_cpu version. Tuning the delay on fewer of the locking operations
reduces bus traffic, but makes it converge more slowly.
o Bonus points if you can update the delay as part of the releasing store.
void ticket_spin_lock_wait(arch_spinlock_t *lock, struct __raw_tickets inc)
{
+ /*
+* Use the raw per-cpu pointer; preemption is disabled in the
+* spinlock code. This avoids put_cpu_var once we have the lock.
+*/
+ int *delay_ptr = &per_cpu(spinlock_delay, smp_processor_id());
+ int delay = *delay_ptr;
+
for (;;) {
- int loops = 50 * (__ticket_t)(inc.tail - inc.head);
+ int loops = delay * (__ticket_t)(inc.tail - inc.head);
while (loops--)
cpu_relax();
inc.head = ACCESS_ONCE(lock->tickets.head);
- if (inc.head == inc.tail)
+ if (inc.head == inc.tail) {
+ /* Decrease the delay, since we may have overslept. */
+ if (delay > MIN_SPINLOCK_DELAY)
+ delay--;
br
Re: [PATCH] MIPS: Fix crash that occurs when function tracing is enabled
On 11/15/2012 03:16 PM, Al Cooper wrote:
A recent patch changed some irq routines from inlines to functions.
These routines are called by the tracer code. Now that they're functions,
if they are compiled for function tracing they will call the tracer
and crash the system due to infinite recursion. The fix disables
tracing in these functions by using "notrace" in the function
definition.
Signed-off-by: Al Cooper
Makes sense,
Reviewed-by: David Daney
---
arch/mips/lib/mips-atomic.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
index e091430..cd160be 100644
--- a/arch/mips/lib/mips-atomic.c
+++ b/arch/mips/lib/mips-atomic.c
@@ -56,7 +56,7 @@ __asm__(
" .setpop \n"
" .endm \n");
-void arch_local_irq_disable(void)
+notrace void arch_local_irq_disable(void)
{
.
.
.
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Re: [PATCH] mips: Fix invalid interrupt name in cavium-octeon
On 04/22/2013 06:22 AM, Ralf Baechle wrote:
On Thu, Apr 18, 2013 at 10:50:52PM +, EUNBONG SONG wrote:
Change interrupt name from "RML/RSL" to "RMLRSL".
This fixes following warning message.
[ 24.938793] WARNING: at fs/proc/generic.c:307 __xlate_proc_name+0x124/0x160()
[ 24.945926] name 'RML/RSL'
[ 24.948642] Modules linked in:
[ 24.951707] Call Trace:
[ 24.954157] [] dump_stack+0x8/0x34
[ 24.959136] [] warn_slowpath_common+0x78/0xa8
[ 24.965056] [] warn_slowpath_fmt+0x38/0x48
[ 24.970723] [] __xlate_proc_name+0x124/0x160
[ 24.976556] [] __proc_create+0x78/0x128
[ 24.981963] [] proc_mkdir_mode+0x2c/0x70
[ 24.987451] [] register_handler_proc+0x108/0x130
[ 24.993642] [] __setup_irq+0x210/0x540
[ 24.998963] [] request_threaded_irq+0x114/0x1a0
[ 25.005060] [] prom_free_prom_memory+0xd4/0x588
[ 25.011164] [] free_initmem+0x10/0xc0
[ 25.016390] [] kernel_init+0x20/0x100
[ 25.021624] [] ret_from_kernel_thread+0x10/0x18
Signed-off-by: Eunbong Song
---
arch/mips/cavium-octeon/setup.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b0baa29..92c3150 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1066,7 +1066,7 @@ void prom_free_prom_memory(void)
/* Add an interrupt handler for general failures. */
if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
- "RML/RSL", octeon_rlm_interrupt)) {
+ "RMLRSL", octeon_rlm_interrupt)) {
panic("Unable to request_irq(OCTEON_IRQ_RML)");
}
#endif
Interesting. While your patch certainly is correct, you seem to have
further modifications in your tree.
David, Above code is wrapped by #ifdef CONFIG_CAVIUM_DECODE_RSL but doesn't
seem to get defined anywhere. What shall we do about this?
It seems to be a vestige of the out-of-tree version. I was going to
send a patch to remove it all, and perhaps another to replace it with
something better.
David Daney
Ralf
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[PATCH] smp.h: Use local_irq_{save,restore}() in !SMP version of on_each_cpu().
From: David Daney
Thanks to commit f91eb62f71b (init: scream bloody murder if interrupts
are enabled too early), "bloody murder" is now being screamed.
With a MIPS OCTEON config, we use on_each_cpu() in our
irq_chip.irq_bus_sync_unlock() function. This gets called in early as
a result of the time_init() call. Because the !SMP version of
on_each_cpu() unconditionally enables irqs, we get:
[ cut here ]
WARNING: at init/main.c:560 start_kernel+0x250/0x410()
Interrupts were enabled early
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 3.10.0-rc5-Cavium-Octeon+ #801
Stack : 0046 808e 0006 0004
0001 0046
80a9 8015c020 8015c020
80a79f70 80a8 8072b9c0 808a7d77
80a79f70 808a8168 0004178a9948
000417801230 805f7610 1078 805fa01c
8089bd18 801595fc 8089bd28 8015d384
808a7e80 8089bc30 80159710
80139520 0009
...
Call Trace:
[] show_stack+0x68/0x80
[] warn_slowpath_common+0x78/0xb0
[] warn_slowpath_fmt+0x38/0x48
[] start_kernel+0x250/0x410
---[ end trace 139ce121c98e96c9 ]---
Suggested fix: Do what we already do in the SMP version of
on_each_cpu(), and use local_irq_save/local_irq_restore.
Signed-off-by: David Daney
---
include/linux/smp.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/linux/smp.h b/include/linux/smp.h
index e6564c1..d8fb04b 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -141,9 +141,10 @@ static inline int up_smp_call_function(smp_call_func_t
func, void *info)
(up_smp_call_function(func, info))
#define on_each_cpu(func,info,wait)\
({ \
- local_irq_disable();\
+ unsigned long flags;\
+ local_irq_save(flags); \
func(info); \
- local_irq_enable(); \
+ local_irq_restore(flags); \
0; \
})
/*
--
1.7.11.7
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Re: [PATCH v2] MIPS: Reduce _NSIG from 128 to 127 to avoid BUG_ON
On 06/14/2013 09:03 AM, James Hogan wrote:
MIPS has 128 signals, the highest of which has the number 128 (they
start from 1). The following command causes get_signal_to_deliver() to
pass this signal number straight through to do_group_exit() as the exit
code:
strace sleep 10 & sleep 1 && kill -128 `pidof sleep`
However do_group_exit() checks for the core dump bit (0x80) in the exit
code which matches in this particular case and the kernel panics:
BUG_ON(exit_code & 0x80); /* core dumps don't get here */
Lets avoid this by changing the ABI by reducing the number of signals to
127 (so that the maximum signal number is 127). Glibc incorrectly sets
[__]SIGRTMAX to 127 already. uClibc sets it to 128 so it's conceivable
that programs built against uClibc which intentionally uses RT signals
from the top (SIGRTMAX-n, n>=0) would need an updated uClibc (and a
rebuild if it's crazy enough to use __SIGRTMAX).
Note that the signals man page seems to make clear that signals should
be referred to from SIGRTMIN, and it seems unlikely that any portable
program would ever need to use 96 RT signals:
"programs should never refer to real-time signals using hard-coded
numbers, but instead should always refer to real-time signals using
the notation SIGRTMIN+n, and include suitable (run-time) checks that
SIGRTMIN+n does not exceed SIGRTMAX."
As previously discussed, I think this is the way to go,
Acked-by: David Daney
Signed-off-by: James Hogan
Cc: Ralf Baechle
Cc: David Daney
Cc: Oleg Nesterov
Cc: Al Viro
Cc: "Paul E. McKenney"
Cc: David Howells
Cc: Dave Jones
Cc: linux-m...@linux-mips.org
---
As discussed on IRC, another possibility is to reduce the number of
signals down to 64 to match other arches and reduce the number of
sigset_t words, but I think that's riskier as it would affect glibc too.
arch/mips/include/uapi/asm/signal.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/uapi/asm/signal.h
b/arch/mips/include/uapi/asm/signal.h
index addb9f5..40e944d 100644
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -11,9 +11,9 @@
#include
-#define _NSIG 128
+#define _NSIG 127
#define _NSIG_BPW (sizeof(unsigned long) * 8)
-#define _NSIG_WORDS(_NSIG / _NSIG_BPW)
+#define _NSIG_WORDS((_NSIG + _NSIG_BPW - 1) / _NSIG_BPW)
typedef struct {
unsigned long sig[_NSIG_WORDS];
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Re: [PATCH] smp.h: Use local_irq_{save,restore}() in !SMP version of on_each_cpu().
On 06/13/2013 10:46 PM, Linus Torvalds wrote: On Thu, Jun 13, 2013 at 6:07 PM, David Daney wrote: Suggested fix: Do what we already do in the SMP version of on_each_cpu(), and use local_irq_save/local_irq_restore. I was going to apply this, but started looking a bit more. Using "flags" as a variable name inside a macro like this is a *really* bad idea. Lookie here: [torvalds@pixel linux]$ git grep on_each_cpu.*flags arch/s390/kernel/perf_cpum_cf.c:on_each_cpu(setup_pmc_cpu, &flags, 1); arch/s390/kernel/perf_cpum_cf.c:on_each_cpu(setup_pmc_cpu, &flags, 1); and ask yourself what happens when the "info" argument expands to "&flags", and it all compiles perfectly fine, but the "&flags" takes the address of the new _inner_ variable called "flags" from the macro expansion. Not the one that the caller actually intends.. Oops. Not a good idea. Yeah, I think making it a static inline function may be the best approach. I am going to test doing that and send a new patch very soon. David Daney So I would suggest trivially renaming "flags" as "__flags" or something, or perhaps even just making it a real function and avoiding the whole namespace issue. And rather than doing that blindly by editing the patch at after -rc5, I'm just going to ask you to re-send a tested patch. Ok? Linus -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 6/7] MIPS: octeon: use irq_get_trigger_type() to get IRQ flags
On 06/14/2013 09:40 AM, Javier Martinez Canillas wrote:
Use irq_get_trigger_type() to get the IRQ trigger type flags
instead calling irqd_get_trigger_type(irq_desc_get_irq_data(irq))
Signed-off-by: Javier Martinez Canillas
Acked-by: David Daney
---
arch/mips/cavium-octeon/octeon-irq.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/cavium-octeon/octeon-irq.c
b/arch/mips/cavium-octeon/octeon-irq.c
index a22f06a..7181def 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -607,7 +607,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)
{
- if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) &
IRQ_TYPE_EDGE_BOTH)
+ if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH)
handle_edge_irq(irq, desc);
else
handle_level_irq(irq, desc);
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[PATCH v2] smp.h: Use local_irq_{save,restore}() in !SMP version of on_each_cpu().
From: David Daney
Thanks to commit f91eb62f71b (init: scream bloody murder if interrupts
are enabled too early), "bloody murder" is now being screamed.
With a MIPS OCTEON config, we use on_each_cpu() in our
irq_chip.irq_bus_sync_unlock() function. This gets called in early as
a result of the time_init() call. Because the !SMP version of
on_each_cpu() unconditionally enables irqs, we get:
[ cut here ]
WARNING: at init/main.c:560 start_kernel+0x250/0x410()
Interrupts were enabled early
Modules linked in:
CPU: 0 PID: 0 Comm: swapper Not tainted 3.10.0-rc5-Cavium-Octeon+ #801
Stack : 0046 808e 0006 0004
0001 0046
80a9 8015c020 8015c020
80a79f70 80a8 8072b9c0 808a7d77
80a79f70 808a8168 0004178a9948
000417801230 805f7610 1078 805fa01c
8089bd18 801595fc 8089bd28 8015d384
808a7e80 8089bc30 80159710
80139520 0009
...
Call Trace:
[] show_stack+0x68/0x80
[] warn_slowpath_common+0x78/0xb0
[] warn_slowpath_fmt+0x38/0x48
[] start_kernel+0x250/0x410
---[ end trace 139ce121c98e96c9 ]---
Suggested fix: Do what we already do in the SMP version of
on_each_cpu(), and use local_irq_save/local_irq_restore. Because we
need a flags variable, make it a static inline to avoid name space
issues.
Signed-off-by: David Daney
---
Change from v1: Convert on_each_cpu to a static inline function, add
#include to avoid build breakage on some files.
on_each_cpu_mask() and on_each_cpu_cond() suffer the same problem as
on_each_cpu(), but they are not causing !SMP bugs for me, so I will
defer changing them to a less urgent patch.
Thanks,
David Daney
include/linux/smp.h | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/include/linux/smp.h b/include/linux/smp.h
index e6564c1..c848876 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
extern void cpu_idle(void);
@@ -139,13 +140,17 @@ static inline int up_smp_call_function(smp_call_func_t
func, void *info)
}
#define smp_call_function(func, info, wait) \
(up_smp_call_function(func, info))
-#define on_each_cpu(func,info,wait)\
- ({ \
- local_irq_disable();\
- func(info); \
- local_irq_enable(); \
- 0; \
- })
+
+static inline int on_each_cpu(smp_call_func_t func, void *info, int wait)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ func(info);
+ local_irq_restore(flags);
+ return 0;
+}
+
/*
* Note we still need to test the mask even for UP
* because we actually can get an empty mask from
--
1.7.11.7
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Re: [PATCH RESEND] fix WARNING: at kernel/cpu/idle.c:96
On 06/14/2013 11:55 AM, James Bottomley wrote:
From 48bbf44a96676ce6f520a408378730c976e9a11e Mon Sep 17 00:00:00 2001
From: James Bottomley
Date: Wed, 8 May 2013 14:05:34 -0700
Subject: [PATCH] [PARISC] fix WARNING: at kernel/cpu/idle.c:96
On PA-RISC (and presumably any other arch that doesn't implement its own
arch_cpu_idle), we get this spurious boot warning. The problem is that the
way the idle task is selected initially using the weak arch_cpu_idle() in
idle.c causes us to enter this place once with interrupts enabled. Fix this
by disabling interrupts in the weak arch_cpu_idle() code.
Is this changelog correct? It looks to me like you are enabling
interrupts down there.
David Daney
Reviewed-by: Srivatsa S. Bhat
Cc: sta...@vger.kernel.org
Signed-off-by: James Bottomley
---
Thomas, I'm getting a bit impatient: this is a clear bug in the cpu idle
code and we keep getting reports of this as a boot crash on parisc. If
you don't push it through your tree, I'll take it through the parisc
one.
diff --git a/kernel/cpu/idle.c b/kernel/cpu/idle.c
index d5585f5..0a4d11e 100644
--- a/kernel/cpu/idle.c
+++ b/kernel/cpu/idle.c
@@ -58,6 +58,7 @@ void __weak arch_cpu_idle_dead(void) { }
void __weak arch_cpu_idle(void)
{
cpu_idle_force_poll = 1;
+ local_irq_enable();
Here
}
/*
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[PATCH] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
From: David Daney
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all. Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: David Daney
---
This patch depends somewhat on patches in Ralf's MIPS/Linux -next tree
where we have patches that enable the Kconfig CAVIUM_OCTEON_SOC and
ARCH_REQUIRE_GPIOLIB symbols. Apart from that it is stand-alone and
is probably suitable for merging via the GPIO tree.
Device tree binding defintions already exist for this device in
Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
drivers/gpio/Kconfig | 8 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-octeon.c | 153 +
3 files changed, 162 insertions(+)
create mode 100644 drivers/gpio/gpio-octeon.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 573c449..7b5df9a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -190,6 +190,14 @@ config GPIO_MXS
select GPIO_GENERIC
select GENERIC_IRQ_CHIP
+config GPIO_OCTEON
+ tristate "Cavium OCTEON GPIO"
+ depends on GPIOLIB && CAVIUM_OCTEON_SOC
+ default y
+ help
+ Say yes here to support the on-chip GPIO lines on the OCTEON
+ family of SOCs.
+
config GPIO_PL061
bool "PrimeCell PL061 GPIO support"
depends on ARM && ARM_AMBA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0cb2d65..b8487b6 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
obj-$(CONFIG_GPIO_MVEBU)+= gpio-mvebu.o
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
+obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
obj-$(CONFIG_ARCH_OMAP)+= gpio-omap.o
obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
diff --git a/drivers/gpio/gpio-octeon.c b/drivers/gpio/gpio-octeon.c
new file mode 100644
index 000..f5bd127
--- /dev/null
+++ b/drivers/gpio/gpio-octeon.c
@@ -0,0 +1,153 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011, 2012 Cavium Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define RX_DAT 0x80
+#define TX_SET 0x88
+#define TX_CLEAR 0x90
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int gpio)
+{
+ if (gpio < 16)
+ return 8 * gpio;
+ else
+ return 8 * (gpio - 16) + 0x100;
+}
+
+struct octeon_gpio {
+ struct gpio_chip chip;
+ u64 register_base;
+};
+
+static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+
+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
+ return 0;
+}
+
+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 mask = 1ull << offset;
+ u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
+ cvmx_write_csr(reg, mask);
+}
+
+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ union cvmx_gpio_bit_cfgx cfgx;
+
+ octeon_gpio_set(chip, offset, value);
+
+ cfgx.u64 = 0;
+ cfgx.s.tx_oe = 1;
+
+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
+ return 0;
+}
+
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
+}
+
+static int octeon_gpio_probe(struct platform_device *pdev)
+{
+ struct octeon_gpio *gpio;
+ struct gpio_chip *chip;
+ struct resource *res_mem;
+ int err = 0;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+ chip = &gpio->chip;
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res_mem == NULL) {
+ dev_err(&pdev->dev, "found no memory resource\n");
+ err = -ENXIO;
+ goto out;
+ }
+ if (!devm_request_mem_region(&pdev->dev, res_mem->start,
+
Re: [PATCH 2/2] mn10300: Fix include dependency in irqflags.h
On 06/17/2013 03:12 AM, Geert Uytterhoeven wrote:
On Mon, Jun 17, 2013 at 9:07 AM, Geert Uytterhoeven
wrote:
On Sun, Jun 16, 2013 at 10:06 PM, wrote:
From: David Daney
We need to pick up the definition of raw_smp_processor_id() from
asm/smp.h. For the !SMP case, we need to supply a definition of
raw_smp_processor_id().
Thanks, this fixes the build!
Signed-off-by: David Daney
Acked-by: Geert Uytterhoeven
Sorry, I acked to soon. While SMP=n is fine (asb2303_defconfig),
there's a new regression with asb2364_defconfig, which has SMP=y:
CC arch/mn10300/kernel/asm-offsets.s
In file included from
/scratch/geert/linux/linux/arch/mn10300/include/asm/irqflags.h:18:0,
from /scratch/geert/linux/linux/include/linux/irqflags.h:15,
from /scratch/geert/linux/linux/include/linux/spinlock.h:53,
from /scratch/geert/linux/linux/include/linux/seqlock.h:29,
from /scratch/geert/linux/linux/include/linux/time.h:5,
from /scratch/geert/linux/linux/include/uapi/linux/timex.h:56,
from /scratch/geert/linux/linux/include/linux/timex.h:56,
from /scratch/geert/linux/linux/include/linux/sched.h:17,
from
/scratch/geert/linux/linux/arch/mn10300/kernel/asm-offsets.c:7:
/scratch/geert/linux/linux/arch/mn10300/include/asm/smp.h:88:34:
error: unknown type name 'smp_call_func_t'
make[4]: *** [arch/mn10300/kernel/asm-offsets.s] Error 1
I am truly in Include Hell. I will attempt a better fix...
David Daney
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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Re: Linux 3.10-rc6
On 06/17/2013 01:30 PM, Andrew Morton wrote:
[...]
From: Andrew Morton
Subject: include/linux/smp.h:on_each_cpu(): switch back to a macro
f21afc25f9ed4 ("smp.h: Use local_irq_{save,restore}() in !SMP version of
on_each_cpu()") converted on_each_cpu() to a C function. This required
inclusion of irqflags.h, which broke ia64 and mn10300 (at least) due to
header ordering hell.
Switch on_each_cpu() back to a macro to fix this.
FYI: I have already sent a pair of patches that fix the include
dependencies:
https://lkml.org/lkml/2013/6/16/113
https://lkml.org/lkml/2013/6/17/422
Obviously, it is Linus' choice as to how best to handle the failure, but
I think it is important to know that there are two options (fixing ia64
and mn10300, or reverting the patch).
David Daney
Reported-by: Geert Uytterhoeven
Cc: David Daney
Cc: Ralf Baechle
Signed-off-by: Andrew Morton
---
include/linux/smp.h | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff -puN
include/linux/smp.h~include-linux-smph-on_each_cpu-switch-back-to-a-macro
include/linux/smp.h
--- a/include/linux/smp.h~include-linux-smph-on_each_cpu-switch-back-to-a-macro
+++ a/include/linux/smp.h
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
extern void cpu_idle(void);
@@ -140,17 +139,14 @@ static inline int up_smp_call_function(s
}
#define smp_call_function(func, info, wait) \
(up_smp_call_function(func, info))
-
-static inline int on_each_cpu(smp_call_func_t func, void *info, int wait)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- func(info);
- local_irq_restore(flags);
- return 0;
-}
-
+#define on_each_cpu(func,info,wait)\
+ ({ \
+ unsigned long flags;\
+ local_irq_save(flags); \
+ func(info); \
+ local_irq_restore(flags); \
+ 0; \
+ })
/*
* Note we still need to test the mask even for UP
* because we actually can get an empty mask from
_
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Re: Linux 3.10-rc6
On 06/17/2013 01:59 PM, Andrew Morton wrote:
On Mon, 17 Jun 2013 13:48:16 -0700 David Daney
wrote:
On 06/17/2013 01:30 PM, Andrew Morton wrote:
[...]
From: Andrew Morton
Subject: include/linux/smp.h:on_each_cpu(): switch back to a macro
f21afc25f9ed4 ("smp.h: Use local_irq_{save,restore}() in !SMP version of
on_each_cpu()") converted on_each_cpu() to a C function. This required
inclusion of irqflags.h, which broke ia64 and mn10300 (at least) due to
header ordering hell.
Switch on_each_cpu() back to a macro to fix this.
FYI: I have already sent a pair of patches that fix the include
dependencies:
https://lkml.org/lkml/2013/6/16/113
https://lkml.org/lkml/2013/6/17/422
I wasn't cc'ed.
Obviously, it is Linus' choice as to how best to handle the failure, but
I think it is important to know that there are two options (fixing ia64
and mn10300, or reverting the patch).
I certainly prefer the inline function over a crappy macro. The
additional nested include is regrettable - more complexity.
Also, it's good to have the SMP and non-SMP versions either both using
macros or both using C. Having them different can cause irritating
unused-variable compilation warnings when using the macro version.
Although all these points are true, they are not why I wrote the patch.
The key difference, for me, between the SMP and !SMP versions is that
the !SMP version unconditionally enables interrupts, and this enabling
interrupts breaks my kernel
I think switch-back-to-a-macro is simplest and safest for now. Perhaps
you can queue a 3.11 patch which restores the C function and fixes up
mn10300 and ia64?
If the patch is reverted, I will do that.
David Daney
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Re: Linux 3.10-rc6
On 06/17/2013 02:13 PM, Andrew Morton wrote: On Mon, 17 Jun 2013 14:08:13 -0700 David Daney wrote: I think switch-back-to-a-macro is simplest and safest for now. Perhaps you can queue a 3.11 patch which restores the C function and fixes up mn10300 and ia64? If the patch is reverted, I will do that. I'm not proposing that we revert f21afc25f9ed4. Retain its functionality, but do it via a macro for 3.10. I misread your patch. Your patch may be incorrect in that the flags variable you introduce has name space collisions with code using the macro. Linus found this exact problem with the first version of my patch (which was identical to your patch). Once you fix the name of 'flags', I hope you don't run into the same Include Hell on ia64 and mn10300 that I did. David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/5] Revert "MIPS: Octeon: Fix build error if CONFIG_SERIAL_8250=n"
From: David Daney This reverts commit fc0fcde2ea9740944acf6134d2c84983d1297bc1. --- arch/mips/cavium-octeon/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 643809f..e3fd50c 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -12,13 +12,12 @@ CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt -obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o +obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_MTD)+= flash_setup.o -obj-$(CONFIG_SERIAL_8250)+= serial.o obj-$(CONFIG_SMP)+= smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/5] MIPS/tty/8250: Use standard 8250 drivers for OCTEON
From: David Daney Get rid of the custom OCTEON UART probe code and use 8250_dw instead. The first patch just gets rid of Ralf's Kconfig workarounds for the real problem, which is OCTEON's inclomplete serial support. Then we just make minor patches to 8250_dw, and rip out all this OCTEON code. Since the patches are all interdependent, we might want to merge them via a single tree (perhaps Ralf's MIPS tree). David Daney (5): Revert "MIPS: Octeon: Fix build error if CONFIG_SERIAL_8250=n" MIPS: OCTEON: Set proper UART clock in internal device trees. tty/8250_dw: Add support for OCTEON UARTS. MIPS: OCTEON: Remove custom serial setup code. MIPS: Update cavium_octeon_defconfig arch/mips/cavium-octeon/Makefile | 1 - arch/mips/cavium-octeon/octeon-platform.c | 9 ++- arch/mips/cavium-octeon/serial.c | 109 -- arch/mips/configs/cavium_octeon_defconfig | 4 +- drivers/tty/serial/8250/8250_dw.c | 45 ++-- 5 files changed, 48 insertions(+), 120 deletions(-) delete mode 100644 arch/mips/cavium-octeon/serial.c -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 5/5] MIPS: Update cavium_octeon_defconfig
From: David Daney The serial port changes make it advisable to enable the proper UART drivers. Signed-off-by: David Daney --- arch/mips/configs/cavium_octeon_defconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 1888e5f..dace582 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -1,13 +1,11 @@ CONFIG_CAVIUM_OCTEON_SOC=y CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 -CONFIG_SPARSEMEM_MANUAL=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_HZ_100=y CONFIG_PREEMPT=y -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y @@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_DW=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_OCTEON=y -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/5] tty/8250_dw: Add support for OCTEON UARTS.
From: David Daney
A few differences needed by OCTEON:
o These are DWC UARTS, but have USR at a different offset.
o OCTEON must have 64-bit wide register accesses, so we have OCTEON
specific register accessors.
o No UCV register, so we hard code some properties.
Signed-off-by: David Daney
---
drivers/tty/serial/8250/8250_dw.c | 45 +--
1 file changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index d07b6af..a50c1d5 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -57,8 +57,30 @@ struct dw8250_data {
int last_lcr;
int line;
struct clk *clk;
+ u8 usr_reg;
+ boolno_ucv;
};
+static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
+{
+ offset <<= p->regshift;
+
+ return (u8)__raw_readq(p->membase + offset);
+}
+
+static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
+{
+ struct dw8250_data *d = p->private_data;
+
+ if (offset == UART_LCR)
+ d->last_lcr = value;
+
+ offset <<= p->regshift;
+ __raw_writeq(value, p->membase + offset);
+ dw8250_serial_inq(p, UART_LCR);
+}
+
+
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = p->private_data;
@@ -104,7 +126,7 @@ static int dw8250_handle_irq(struct uart_port *p)
return 1;
} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
/* Clear the USR and write the LCR again. */
- (void)p->serial_in(p, DW_UART_USR);
+ (void)p->serial_in(p, d->usr_reg);
p->serial_out(p, UART_LCR, d->last_lcr);
return 1;
@@ -125,12 +147,20 @@ dw8250_do_pm(struct uart_port *port, unsigned int state,
unsigned int old)
pm_runtime_put_sync_suspend(port->dev);
}
-static int dw8250_probe_of(struct uart_port *p)
+static int dw8250_probe_of(struct uart_port *p,
+ struct dw8250_data *data)
{
struct device_node *np = p->dev->of_node;
u32 val;
- if (!of_property_read_u32(np, "reg-io-width", &val)) {
+ if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+ p->serial_in = dw8250_serial_inq;
+ p->serial_out = dw8250_serial_outq;
+ p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ p->type = PORT_OCTEON;
+ data->usr_reg = 0x27;
+ data->no_ucv = true;
+ } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
switch (val) {
case 1:
break;
@@ -259,6 +289,7 @@ static int dw8250_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
+ data->usr_reg = DW_UART_USR;
data->clk = devm_clk_get(&pdev->dev, NULL);
if (!IS_ERR(data->clk)) {
clk_prepare_enable(data->clk);
@@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev)
uart.port.serial_out = dw8250_serial_out;
uart.port.private_data = data;
- dw8250_setup_port(&uart);
-
if (pdev->dev.of_node) {
- err = dw8250_probe_of(&uart.port);
+ err = dw8250_probe_of(&uart.port, data);
if (err)
return err;
} else if (ACPI_HANDLE(&pdev->dev)) {
@@ -284,6 +313,9 @@ static int dw8250_probe(struct platform_device *pdev)
return -ENODEV;
}
+ if (!data->no_ucv)
+ dw8250_setup_port(&uart);
+
data->line = serial8250_register_8250_port(&uart);
if (data->line < 0)
return data->line;
@@ -362,6 +394,7 @@ static const struct dev_pm_ops dw8250_pm_ops = {
static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart" },
+ { .compatible = "cavium,octeon-3860-uart" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
--
1.7.11.7
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[PATCH 2/5] MIPS: OCTEON: Set proper UART clock in internal device trees.
From: David Daney
Following patch to use generic 8250 drivers will need proper clock
information. So when using the internal device tree, populate the
"clock-frequency" property with the correct value.
Signed-off-by: David Daney
---
arch/mips/cavium-octeon/octeon-platform.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cavium-octeon/octeon-platform.c
b/arch/mips/cavium-octeon/octeon-platform.c
index 389512e..7b746e7 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
if (alias_prop) {
uart = fdt_path_offset(initial_boot_params, alias_prop);
- if (uart_mask & (1 << i))
+ if (uart_mask & (1 << i)) {
+ __be32 f;
+
+ f = cpu_to_be32(octeon_get_io_clock_rate());
+ fdt_setprop_inplace(initial_boot_params,
+ uart, "clock-frequency",
+ &f, sizeof(f));
continue;
+ }
pr_debug("Deleting uart%d\n", i);
fdt_nop_node(initial_boot_params, uart);
fdt_nop_property(initial_boot_params, aliases,
--
1.7.11.7
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[PATCH 4/5] MIPS: OCTEON: Remove custom serial setup code.
From: David Daney
We will use 8250_dw instead.
Signed-off-by: David Daney
---
arch/mips/cavium-octeon/Makefile | 2 +-
arch/mips/cavium-octeon/serial.c | 109 ---
2 files changed, 1 insertion(+), 110 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/serial.c
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index e3fd50c..4e95204 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,7 @@
CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
-obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o
obj-y += octeon-memcpy.o
obj-y += executive/
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
deleted file mode 100644
index f393f65..000
--- a/arch/mips/cavium-octeon/serial.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2007 Cavium Networks
- */
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include
-
-#define DEBUG_UART 1
-
-unsigned int octeon_serial_in(struct uart_port *up, int offset)
-{
- int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- if (offset == UART_IIR && (rv & 0xf) == 7) {
- /* Busy interrupt, read the USR (39) and try again. */
- cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
- rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- }
- return rv;
-}
-
-void octeon_serial_out(struct uart_port *up, int offset, int value)
-{
- /*
-* If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
-* working.
-*/
- if (offset == UART_LCR)
- value &= 0x9f;
- cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
-}
-
-static int octeon_serial_probe(struct platform_device *pdev)
-{
- int irq, res;
- struct resource *res_mem;
- struct uart_8250_port up;
-
- /* All adaptors have an irq. */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- memset(&up, 0, sizeof(up));
-
- up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
- up.port.type = PORT_OCTEON;
- up.port.iotype = UPIO_MEM;
- up.port.regshift = 3;
- up.port.dev = &pdev->dev;
-
- if (octeon_is_simulation())
- /* Make simulator output fast*/
- up.port.uartclk = 115200 * 16;
- else
- up.port.uartclk = octeon_get_io_clock_rate();
-
- up.port.serial_in = octeon_serial_in;
- up.port.serial_out = octeon_serial_out;
- up.port.irq = irq;
-
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res_mem == NULL) {
- dev_err(&pdev->dev, "found no memory resource\n");
- return -ENXIO;
- }
- up.port.mapbase = res_mem->start;
- up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
-
- res = serial8250_register_8250_port(&up);
-
- return res >= 0 ? 0 : res;
-}
-
-static struct of_device_id octeon_serial_match[] = {
- {
- .compatible = "cavium,octeon-3860-uart",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, octeon_serial_match);
-
-static struct platform_driver octeon_serial_driver = {
- .probe = octeon_serial_probe,
- .driver = {
- .owner = THIS_MODULE,
- .name = "octeon_serial",
- .of_match_table = octeon_serial_match,
- },
-};
-
-static int __init octeon_serial_init(void)
-{
- return platform_driver_register(&octeon_serial_driver);
-}
-late_initcall(octeon_serial_init);
--
1.7.11.7
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Re: [PATCH 0/5] MIPS/tty/8250: Use standard 8250 drivers for OCTEON
On 06/18/2013 12:36 PM, Ralf Baechle wrote: On Tue, Jun 18, 2013 at 12:12:50PM -0700, David Daney wrote: From: David Daney Get rid of the custom OCTEON UART probe code and use 8250_dw instead. The first patch just gets rid of Ralf's Kconfig workarounds for the real problem, which is OCTEON's inclomplete serial support. Then we just make minor patches to 8250_dw, and rip out all this OCTEON code. Since the patches are all interdependent, we might want to merge them via a single tree (perhaps Ralf's MIPS tree). Looks good - I was trying to come up with a kludge good enough for 3.10; this may be a bit too large ... At this point I think it is fine if some random configs for OCTEON fail to build in v3.10. I was thinking that this would be for 3.11 David Daney -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/5] tty/8250_dw: Add support for OCTEON UARTS.
On 06/19/2013 03:01 AM, Arnd Bergmann wrote:
On Tuesday 18 June 2013 12:12:53 David Daney wrote:
+static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
+{
+ offset <<= p->regshift;
+
+ return (u8)__raw_readq(p->membase + offset);
+}
+
+static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
+{
+ struct dw8250_data *d = p->private_data;
+
+ if (offset == UART_LCR)
+ d->last_lcr = value;
+
+ offset <<= p->regshift;
+ __raw_writeq(value, p->membase + offset);
+ dw8250_serial_inq(p, UART_LCR);
+}
This breaks building on 32 bit architectures as I found on my daily ARM
builds: __raw_writeq cannot be defined on architectures that don't have
native 64 bit data access instructions.
I will rework the patch to avoid this problem.
It's also wrong to use the
__raw_* variant, which is not guaranteed to be atomic and is not
endian-safe.
We do runtime probing and only use this function on platforms where it
is appropriate, so atomicity is not an issue. As for endianess, I used
the __raw_ variant precisely because it is correct for both big and
little endian kernels.
David Daney
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Re: [PATCH 3/5] tty/8250_dw: Add support for OCTEON UARTS.
On 06/19/2013 07:10 AM, Heikki Krogerus wrote:
On Tue, Jun 18, 2013 at 12:12:53PM -0700, David Daney wrote:
A few differences needed by OCTEON:
o These are DWC UARTS, but have USR at a different offset.
o OCTEON must have 64-bit wide register accesses, so we have OCTEON
specific register accessors.
o No UCV register, so we hard code some properties.
Signed-off-by: David Daney
@@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev)
uart.port.serial_out = dw8250_serial_out;
uart.port.private_data = data;
- dw8250_setup_port(&uart);
-
if (pdev->dev.of_node) {
- err = dw8250_probe_of(&uart.port);
+ err = dw8250_probe_of(&uart.port, data);
if (err)
return err;
} else if (ACPI_HANDLE(&pdev->dev)) {
@@ -284,6 +313,9 @@ static int dw8250_probe(struct platform_device *pdev)
return -ENODEV;
}
+ if (!data->no_ucv)
+ dw8250_setup_port(&uart);
Moving the dw8250_setup_port() call here breaks dw8250_probe_acpi(). It
expects values from the CPR register for the DMA burst size calculation.
The DMA support can be moved to a separate function. This way it can
be called after this point, and it will then be available for both DT
and ACPI. I can make a patch tomorrow. That should solve this issue.
I am reworking the patch because other problems were found. I will try
to get this part right in the next version.
David Daney
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Re: Linux 3.10-rc6
On 06/17/2013 02:38 PM, Andrew Morton wrote:
On Mon, 17 Jun 2013 14:26:01 -0700 David Daney
wrote:
On 06/17/2013 02:13 PM, Andrew Morton wrote:
On Mon, 17 Jun 2013 14:08:13 -0700 David Daney
wrote:
I think switch-back-to-a-macro is simplest and safest for now. Perhaps
you can queue a 3.11 patch which restores the C function and fixes up
mn10300 and ia64?
If the patch is reverted, I will do that.
I'm not proposing that we revert f21afc25f9ed4. Retain its
functionality, but do it via a macro for 3.10.
FYI, these two commits:
c0691143dfe (mn10300: Fix include dependency in irqflags.h et al.)
f75773103d2 ([IA64] Fix include dependency in asm/irqflags.h)
... seem to fix all known breakage related to this issue. So, the patch
(to convert back to a macro) may not be necessary.
Sorry to create all this late -rc churn,
David Daney
I misread your patch. Your patch may be incorrect in that the flags
variable you introduce has name space collisions with code using the
macro. Linus found this exact problem with the first version of my
patch (which was identical to your patch).
Sigh. Macros do so suck.
--- a/include/linux/smp.h~include-linux-smph-on_each_cpu-switch-back-to-a-macro
+++ a/include/linux/smp.h
@@ -11,7 +11,6 @@
#include
#include
#include
-#include
extern void cpu_idle(void);
@@ -140,17 +139,14 @@ static inline int up_smp_call_function(s
}
#define smp_call_function(func, info, wait) \
(up_smp_call_function(func, info))
-
-static inline int on_each_cpu(smp_call_func_t func, void *info, int wait)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- func(info);
- local_irq_restore(flags);
- return 0;
-}
-
+#define on_each_cpu(func, info, wait) \
+ ({ \
+ unsigned long __flags; \
+ local_irq_save(__flags);\
+ func(info); \
+ local_irq_restore(__flags); \
+ 0; \
+ })
/*
* Note we still need to test the mask even for UP
* because we actually can get an empty mask from
_
Once you fix the name of 'flags', I hope you don't run into the same
Include Hell on ia64 and mn10300 that I did.
I build-tested ia64. I don't have an mn10300 cross-compiler set up.
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Re: [PATCH 3/5] tty/8250_dw: Add support for OCTEON UARTS.
On 06/19/2013 11:52 AM, Arnd Bergmann wrote: On Wednesday 19 June 2013, David Daney wrote: On 06/19/2013 03:01 AM, Arnd Bergmann wrote: It's also wrong to use the __raw_* variant, which is not guaranteed to be atomic and is not endian-safe. We do runtime probing and only use this function on platforms where it is appropriate, so atomicity is not an issue. As for endianess, I used the __raw_ variant precisely because it is correct for both big and little endian kernels. You don't know what the compiler turns a __raw_writeq into, it could always to eight byte wise stores, that's why typically writeq is an inline assembly while __raw_writeq is just a pointer dereference. Well, I do know that for the cases of interest, it will be a single load or store, but it is moot, as I rewrote that part. __raw_* never do endian swaps, Yes, I know that. so it will be wrong on either big-endian CPUs or on little-endian CPUs, depending on what the MMIO register needs. Please see the instruction set reference manual (MD00087-2B-MIPS64BIS-AFP-03.51 or similar) available at: http://www.mips.com/products/architectures/mips64/#specifications ... for why you are mistaken. Pay particular attention to the low order address bit scrambling on narrow loads and stores and how this results in uniform (not affected by processor endian mode) load and store results for aligned 64-bit accesses. In effect, it is magic, and __raw_writeq yields correct results in both big and little endian modes of operation. David Daney. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/4] MIPS: OCTEON: Set proper UART clock in internal device trees.
From: David Daney
Following patch to use generic 8250 drivers will need proper clock
information. So when using the internal device tree, populate the
"clock-frequency" property with the correct value.
Signed-off-by: David Daney
---
arch/mips/cavium-octeon/octeon-platform.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/cavium-octeon/octeon-platform.c
b/arch/mips/cavium-octeon/octeon-platform.c
index 389512e..7b746e7 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -490,8 +490,15 @@ int __init octeon_prune_device_tree(void)
if (alias_prop) {
uart = fdt_path_offset(initial_boot_params, alias_prop);
- if (uart_mask & (1 << i))
+ if (uart_mask & (1 << i)) {
+ __be32 f;
+
+ f = cpu_to_be32(octeon_get_io_clock_rate());
+ fdt_setprop_inplace(initial_boot_params,
+ uart, "clock-frequency",
+ &f, sizeof(f));
continue;
+ }
pr_debug("Deleting uart%d\n", i);
fdt_nop_node(initial_boot_params, uart);
fdt_nop_property(initial_boot_params, aliases,
--
1.7.11.7
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[PATCH v2 3/4] MIPS: OCTEON: Remove custom serial setup code.
From: David Daney
We will use 8250_dw instead.
Signed-off-by: David Daney
---
arch/mips/cavium-octeon/Makefile | 2 +-
arch/mips/cavium-octeon/serial.c | 109 ---
2 files changed, 1 insertion(+), 110 deletions(-)
delete mode 100644 arch/mips/cavium-octeon/serial.c
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index e3fd50c..4e95204 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,7 @@
CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
-obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
+obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o
obj-y += octeon-memcpy.o
obj-y += executive/
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
deleted file mode 100644
index f393f65..000
--- a/arch/mips/cavium-octeon/serial.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004-2007 Cavium Networks
- */
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include
-
-#define DEBUG_UART 1
-
-unsigned int octeon_serial_in(struct uart_port *up, int offset)
-{
- int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- if (offset == UART_IIR && (rv & 0xf) == 7) {
- /* Busy interrupt, read the USR (39) and try again. */
- cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
- rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
- }
- return rv;
-}
-
-void octeon_serial_out(struct uart_port *up, int offset, int value)
-{
- /*
-* If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
-* working.
-*/
- if (offset == UART_LCR)
- value &= 0x9f;
- cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
-}
-
-static int octeon_serial_probe(struct platform_device *pdev)
-{
- int irq, res;
- struct resource *res_mem;
- struct uart_8250_port up;
-
- /* All adaptors have an irq. */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- memset(&up, 0, sizeof(up));
-
- up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
- up.port.type = PORT_OCTEON;
- up.port.iotype = UPIO_MEM;
- up.port.regshift = 3;
- up.port.dev = &pdev->dev;
-
- if (octeon_is_simulation())
- /* Make simulator output fast*/
- up.port.uartclk = 115200 * 16;
- else
- up.port.uartclk = octeon_get_io_clock_rate();
-
- up.port.serial_in = octeon_serial_in;
- up.port.serial_out = octeon_serial_out;
- up.port.irq = irq;
-
- res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res_mem == NULL) {
- dev_err(&pdev->dev, "found no memory resource\n");
- return -ENXIO;
- }
- up.port.mapbase = res_mem->start;
- up.port.membase = ioremap(res_mem->start, resource_size(res_mem));
-
- res = serial8250_register_8250_port(&up);
-
- return res >= 0 ? 0 : res;
-}
-
-static struct of_device_id octeon_serial_match[] = {
- {
- .compatible = "cavium,octeon-3860-uart",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, octeon_serial_match);
-
-static struct platform_driver octeon_serial_driver = {
- .probe = octeon_serial_probe,
- .driver = {
- .owner = THIS_MODULE,
- .name = "octeon_serial",
- .of_match_table = octeon_serial_match,
- },
-};
-
-static int __init octeon_serial_init(void)
-{
- return platform_driver_register(&octeon_serial_driver);
-}
-late_initcall(octeon_serial_init);
--
1.7.11.7
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[PATCH v2 2/4] tty/8250_dw: Add support for OCTEON UARTS.
From: David Daney
A few differences needed by OCTEON:
o These are DWC UARTS, but have USR at a different offset.
o Internal SoC buses require reading back from registers to maintain
write ordering.
o 8250 on OCTEON appears with 64-bit wide registers, so when using
readb/writeb in big endian mode we have to adjust the membase to hit
the proper part of the register.
o No UCV register, so we hard code some properties.
Because OCTEON doesn't have a UCV register, I change where
dw8250_setup_port(), which reads the UCV, is called by pushing it in
to the OF and ACPI probe functions, and move unchanged
dw8250_setup_port() earlier in the file.
Signed-off-by: David Daney
Acked-by: Greg Kroah-Hartman
Cc: Arnd Bergmann
Cc: Heikki Krogerus
---
drivers/tty/serial/8250/8250_dw.c | 108 --
1 file changed, 69 insertions(+), 39 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c
b/drivers/tty/serial/8250/8250_dw.c
index d07b6af..76a8daa 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -29,6 +29,8 @@
#include
#include
+#include
+
#include "8250.h"
/* Offsets for the DesignWare specific registers */
@@ -57,6 +59,7 @@ struct dw8250_data {
int last_lcr;
int line;
struct clk *clk;
+ u8 usr_reg;
};
static void dw8250_serial_out(struct uart_port *p, int offset, int value)
@@ -77,6 +80,13 @@ static unsigned int dw8250_serial_in(struct uart_port *p,
int offset)
return readb(p->membase + offset);
}
+/* Read Back (rb) version to ensure register access ording. */
+static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
+{
+ dw8250_serial_out(p, offset, value);
+ dw8250_serial_in(p, UART_LCR);
+}
+
static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
struct dw8250_data *d = p->private_data;
@@ -104,7 +114,7 @@ static int dw8250_handle_irq(struct uart_port *p)
return 1;
} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
/* Clear the USR and write the LCR again. */
- (void)p->serial_in(p, DW_UART_USR);
+ (void)p->serial_in(p, d->usr_reg);
p->serial_out(p, UART_LCR, d->last_lcr);
return 1;
@@ -125,12 +135,60 @@ dw8250_do_pm(struct uart_port *port, unsigned int state,
unsigned int old)
pm_runtime_put_sync_suspend(port->dev);
}
-static int dw8250_probe_of(struct uart_port *p)
+static void dw8250_setup_port(struct uart_8250_port *up)
+{
+ struct uart_port*p = &up->port;
+ u32 reg = readl(p->membase + DW_UART_UCV);
+
+ /*
+* If the Component Version Register returns zero, we know that
+* ADDITIONAL_FEATURES are not enabled. No need to go any further.
+*/
+ if (!reg)
+ return;
+
+ dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
+ (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
+
+ reg = readl(p->membase + DW_UART_CPR);
+ if (!reg)
+ return;
+
+ /* Select the type based on fifo */
+ if (reg & DW_UART_CPR_FIFO_MODE) {
+ p->type = PORT_16550A;
+ p->flags |= UPF_FIXED_TYPE;
+ p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
+ up->tx_loadsz = p->fifosize;
+ up->capabilities = UART_CAP_FIFO;
+ }
+
+ if (reg & DW_UART_CPR_AFCE_MODE)
+ up->capabilities |= UART_CAP_AFE;
+}
+
+static int dw8250_probe_of(struct uart_port *p,
+ struct dw8250_data *data)
{
struct device_node *np = p->dev->of_node;
u32 val;
-
- if (!of_property_read_u32(np, "reg-io-width", &val)) {
+ bool has_ucv = true;
+
+ if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+#ifdef __BIG_ENDIAN
+ /*
+* Low order bits of these 64-bit registers, when
+* accessed as a byte, are 7 bytes further down in the
+* address space in big endian mode.
+*/
+ p->membase += 7;
+#endif
+ p->serial_out = dw8250_serial_out_rb;
+ p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+ p->type = PORT_OCTEON;
+ data->usr_reg = 0x27;
+ has_ucv = false;
+ } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
switch (val) {
case 1:
break;
@@ -144,6 +202,8 @@ static int dw8250_probe_of(struct uart_port *p)
return -EINVAL;
[PATCH v2 4/4] MIPS: Update cavium_octeon_defconfig
From: David Daney The serial port changes make it advisable to enable the proper UART drivers. Signed-off-by: David Daney --- arch/mips/configs/cavium_octeon_defconfig | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig index 1888e5f..dace582 100644 --- a/arch/mips/configs/cavium_octeon_defconfig +++ b/arch/mips/configs/cavium_octeon_defconfig @@ -1,13 +1,11 @@ CONFIG_CAVIUM_OCTEON_SOC=y CONFIG_CAVIUM_CN63XXP1=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 -CONFIG_SPARSEMEM_MANUAL=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_SMP=y CONFIG_NR_CPUS=32 CONFIG_HZ_100=y CONFIG_PREEMPT=y -CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y @@ -50,7 +48,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_FW_LOADER is not set CONFIG_MTD=y # CONFIG_MTD_OF_PARTS is not set -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_AMDSTD=y @@ -114,6 +111,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_DW=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_OCTEON=y -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/4] MIPS/tty/8250: Use standard 8250 drivers for OCTEON
From: David Daney Changes from v1: Fix breakage in non-OCTEON builds of 8250_dw.c 1) Fix OCTEON's UART clock rate. 2) Make minor patches to 8250_dw so it can be used by OCTEON 3) Rip out the OCTEON serial code. 4) Update defconfig so we default to having a usable serial port. Since the patches are all interdependent, we might want to merge them via a single tree (perhaps Ralf's MIPS tree as OKed by Greg K-H). David Daney (4): MIPS: OCTEON: Set proper UART clock in internal device trees. tty/8250_dw: Add support for OCTEON UARTS. MIPS: OCTEON: Remove custom serial setup code. MIPS: Update cavium_octeon_defconfig arch/mips/cavium-octeon/Makefile | 2 +- arch/mips/cavium-octeon/octeon-platform.c | 9 ++- arch/mips/cavium-octeon/serial.c | 109 -- arch/mips/configs/cavium_octeon_defconfig | 4 +- drivers/tty/serial/8250/8250_dw.c | 108 ++--- 5 files changed, 79 insertions(+), 153 deletions(-) delete mode 100644 arch/mips/cavium-octeon/serial.c -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: Re: [PATCH] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
Sorry for not responding earlier, but my e-mail system seems to have
malfunctioned with respect to this message...
On 06/17/2013 01:51 AM, Linus Walleij wrote:
On Sat, Jun 15, 2013 at 1:18 AM, David Daney wrote:
From: David Daney
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all. Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: David Daney
This patch depends somewhat on patches in Ralf's MIPS/Linux -next tree
where we have patches that enable the Kconfig CAVIUM_OCTEON_SOC and
ARCH_REQUIRE_GPIOLIB symbols. Apart from that it is stand-alone and
is probably suitable for merging via the GPIO tree.
Really? You're using this:
+#include
+#include
I cannot find this in my tree.
Weird, I see them here:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/mips/include/asm/octeon/octeon.h
Do you not have these?
Further I ask why that second file is not part of *this* patch?
It surely seems GPIO-related, and would probably need to
go into include/linux/platform_data/gpio-octeon.h or something
rather than such platform dirs.
(...)
+config GPIO_OCTEON
+ tristate "Cavium OCTEON GPIO"
+ depends on GPIOLIB && CAVIUM_OCTEON_SOC
depend on OF as well right? Or does the CAVIUM_OCTEON_SOC already
imply that?
We already have 'select USE_OF', so I think adding OF here would be
redundant.
(...)
+++ b/drivers/gpio/gpio-octeon.c
+#define RX_DAT 0x80
+#define TX_SET 0x88
+#define TX_CLEAR 0x90
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int gpio)
Maybe the passed variable shall be named "offset" here, as it is named
offset on all call sites, and it surely local for this instance?
Well it is the gpio line, so perhaps it should universally be change to
"line" or "pin"
+{
+ if (gpio < 16)
+ return 8 * gpio;
+ else
+ return 8 * (gpio - 16) + 0x100;
Put this 0x100 in the #defines above with the name something like
STRIDE.
But it is not a 'STRIDE', it is a discontinuity compensation and used in
exactly one place.
+struct octeon_gpio {
+ struct gpio_chip chip;
+ u64 register_base;
+};
OMG everything is 64 bit. Well has to come to this I guess.
Not everything. This is custom logic in an SoC with 64-bit wide
internal address buses, what would you suggest?
+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 mask = 1ull << offset;
And now BIT(offset) does not work anymore because it is defined as
#define BIT(nr) (1UL << (nr))
OK we will have to live with this FTM I guess.
+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ union cvmx_gpio_bit_cfgx cfgx;
+
+ octeon_gpio_set(chip, offset, value);
+
+ cfgx.u64 = 0;
+ cfgx.s.tx_oe = 1;
This makes me want to review that magic header file of yours,
I guess this comes from ?
Not really magic, but yes that is where it comes from.
Should not this latter variable be a bool?
I don't think so, it is not the result of a comparison operator.
I'm not a fan of packed bitfields like this, I prefer if you just
OR | and AND & the bits together in the driver.
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
A common idiom we use for this is:
return !!(read_bits & (1ull << offset));
I hate that idiom, but if its use is a condition of accepting the patch,
I will change it.
+ pdev->dev.platform_data = chip;
+ chip->label = "octeon-gpio";
+ chip->dev = &pdev->dev;
+ chip->owner = THIS_MODULE;
+ chip->base = 0;
+ chip->can_sleep = 0;
+ chip->ngpio = 20;
+ chip->direction_input = octeon_gpio_dir_in;
+ chip->get = octeon_gpio_get;
+ chip->direction_output = octeon_gpio_dir_out;
+ chip->set = octeon_gpio_set;
+ err = gpiochip_add(chip);
+ if (err)
+ goto out;
+
+ dev_info(&pdev->dev, "OCTEON GPIO\n");
This is like shouting "REAL MADRID!" in the bootlog, be a bit more
p
Re: [PATCH] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
On 06/20/2013 11:18 AM, Joe Perches wrote:
On Thu, 2013-06-20 at 11:10 -0700, David Daney wrote:
Sorry for not responding earlier, but my e-mail system seems to have
malfunctioned with respect to this message...
[]
On 06/17/2013 01:51 AM, Linus Walleij wrote:
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
A common idiom we use for this is:
return !!(read_bits & (1ull << offset));
I hate that idiom, but if its use is a condition of accepting the patch,
I will change it.
Or use an even more common idiom and change the
function to return bool and let the compiler do it.
... but it is part of the gpiochip system interface, so it would have to
be done kernel wide.
Really I don't like the idea of GPIO lines having Boolean truth values
associated with them. Some represent things that are active-high and
others active-low. Converting the pin voltage being above or below a
given threshold to something other than zero or one would in my opinion
be confusing.
David Daney
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Re: [PATCH] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
On 06/20/2013 11:43 AM, Joe Perches wrote:
On Thu, 2013-06-20 at 11:27 -0700, David Daney wrote:
On 06/20/2013 11:18 AM, Joe Perches wrote:
On Thu, 2013-06-20 at 11:10 -0700, David Daney wrote:
Sorry for not responding earlier, but my e-mail system seems to have
malfunctioned with respect to this message...
[]
On 06/17/2013 01:51 AM, Linus Walleij wrote:
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
A common idiom we use for this is:
return !!(read_bits & (1ull << offset));
I hate that idiom, but if its use is a condition of accepting the patch,
I will change it.
Or use an even more common idiom and change the
function to return bool and let the compiler do it.
... but it is part of the gpiochip system interface, so it would have to
be done kernel wide.
Not really. It's a local static function.
... which we generate a pointer to, and then assign that pointer to a
variable with a type defined in the gpiochip system interface. So If we
do what you suggest, the result is:
CC drivers/gpio/gpio-octeon.o
drivers/gpio/gpio-octeon.c: In function 'octeon_gpio_probe':
drivers/gpio/gpio-octeon.c:113:12: warning: assignment from incompatible
pointer type [enabled by default]
Really I don't like the idea of GPIO lines having Boolean truth values
associated with them. Some represent things that are active-high and
others active-low. Converting the pin voltage being above or below a
given threshold to something other than zero or one would in my opinion
be confusing.
No worries, just offering options. Your code, your choice.
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Re: [RFC PATCH] kernel/signal.c: avoid BUG_ON with SIG128 (MIPS)
On 05/29/2013 10:01 AM, James Hogan wrote: MIPS has 128 signals, the highest of which has the number 128. The I wonder if we should change the ABI and reduce the number of signals to 127 instead of this patch. David Daney following command causes get_signal_to_deliver() to pass this signal number straight through to do_group_exit() as the exit code: strace sleep 10 & sleep 1 && kill -128 `pidof sleep` However do_group_exit() checks for the core dump bit (0x80) in the exit code which matches in this particular case and the kernel panics: BUG_ON(exit_code & 0x80); /* core dumps don't get here */ This is worked around by changing get_signal_to_deliver() to pass min(info->si_signo, 127) instead of info->si_signo, so that this highest of signal numbers get rounded down to 127. This makes the exit code technically incorrect, but it's better than killing the whole kernel. Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Al Viro Cc: Andrew Morton Cc: Oleg Nesterov Cc: Kees Cook --- This is based on v3.10-rc3. It's a little hacky, but aside from reducing the number of signals to 127 to avoid this case (which isn't backwards compatible) I'm not sure what else can be done. Any comments? kernel/signal.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/signal.c b/kernel/signal.c index 113411b..69bc00f 100644 --- a/kernel/signal.c +++ b/kernel/signal.c @@ -2366,8 +2366,12 @@ relock: /* * Death signals, no core dump. +* +* MIPS has a signal number 128 which clashes with the core dump +* bit. If this was the signal we still want to report a valid +* exit code, so round it down to 127. */ - do_group_exit(info->si_signo); + do_group_exit(min(info->si_signo, 127)); /* NOTREACHED */ } spin_unlock_irq(&sighand->siglock); -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] kernel/signal.c: fix BUG_ON with SIG128 (MIPS)
On 06/21/2013 06:39 AM, James Hogan wrote: MIPS has 128 signals, the highest of which has the number 128 (they start from 1). The following command causes get_signal_to_deliver() to pass this signal number straight through to do_group_exit() as the exit code: strace sleep 10 & sleep 1 && kill -128 `pidof sleep` However do_group_exit() checks for the core dump bit (0x80) in the exit code which matches in this particular case and the kernel panics: BUG_ON(exit_code & 0x80); /* core dumps don't get here */ Fundamentally the exit / wait status code cannot represent SIG128. In fact it cannot represent SIG127 either as 0x7f represents a stopped child. Therefore add sig_to_exitcode() and exitcode_to_sig() functions which map signal numbers > 126 to exit code 126 and puts the remainder (i.e. sig - 126) in higher bits. This allows WIFSIGNALED() to return true for both SIG127 and SIG128, and allows WTERMSIG to be later updated to read the correct signal number for SIG127 and SIG128. I really hate this approach. Can we just change the ABI to reduce the number of signals so that all the standard C library wait related macros don't have to be changed? Think about it, any user space program using signal numbers 127 and 128 doesn't work correctly as things exist today, so removing those two will be no great loss. David Daney Signed-off-by: James Hogan Cc: Ralf Baechle Cc: Al Viro Cc: Andrew Morton Cc: Oleg Nesterov Cc: Kees Cook Cc: David Daney Cc: "Paul E. McKenney" Cc: David Howells Cc: Dave Jones Cc: linux-m...@linux-mips.org --- v3: A slightly different approach this time, closer to the original patch I sent. This is because reducing _NSIG to 127 (like v2) still leaves incorrect exit status codes for SIG127. The only ABI this changes is the wait/waitpid status code, and it's in such a way that old binaries, as long as they use the macros defined in the wait manpage, should see a process terminated by signal 126 for SIG127 and SIG128 rather than !WIFSIGNALED(). Software rebuilt with updated libc wait status macros would see the correct terminating signal number. kernel/signal.c | 32 +--- 1 file changed, 29 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3] kernel/signal.c: fix BUG_ON with SIG128 (MIPS)
On 06/21/2013 01:22 PM, Oleg Nesterov wrote: On 06/21, David Daney wrote: On 06/21/2013 06:39 AM, James Hogan wrote: Therefore add sig_to_exitcode() and exitcode_to_sig() functions which map signal numbers > 126 to exit code 126 and puts the remainder (i.e. sig - 126) in higher bits. This allows WIFSIGNALED() to return true for both SIG127 and SIG128, and allows WTERMSIG to be later updated to read the correct signal number for SIG127 and SIG128. I really hate this approach. Can we just change the ABI to reduce the number of signals so that all the standard C library wait related macros don't have to be changed? Think about it, any user space program using signal numbers 127 and 128 doesn't work correctly as things exist today, so removing those two will be no great loss. Oh, I agree. Besides, this changes ABI anyway. And if we change it we can do this in a more clean way, afaics. MIPS should simply use 2 bytes in exit_code for signal number. Wouldn't that break *all* existing programs that use signals? Perhaps I misunderstand what you are suggesting. I am proposing that we just reduce the number of usable signals such that existing libc status checking macros/functions don't change in any way. Yes, this means we need replace 0x80/0x7f in exit.c by ifdef'ed numbers. And yes, this means that WIFSIGNALED/etc should be updated too, but this is also true with this patch. Oleg. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 25/45] staging/octeon: Use get/put_online_cpus_atomic() to prevent CPU offline
On 06/23/2013 11:55 AM, Srivatsa S. Bhat wrote:
On 06/23/2013 11:47 PM, Greg Kroah-Hartman wrote:
On Sun, Jun 23, 2013 at 07:13:33PM +0530, Srivatsa S. Bhat wrote:
Once stop_machine() is gone from the CPU offline path, we won't be able
to depend on disabling preemption to prevent CPUs from going offline
from under us.
Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
offline, while invoking from atomic context.
Cc: Greg Kroah-Hartman
Cc: de...@driverdev.osuosl.org
Signed-off-by: Srivatsa S. Bhat
---
drivers/staging/octeon/ethernet-rx.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/octeon/ethernet-rx.c
b/drivers/staging/octeon/ethernet-rx.c
index 34afc16..8588b4d 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
#ifdef CONFIG_XFRM
@@ -97,6 +98,7 @@ static void cvm_oct_enable_one_cpu(void)
return;
/* ... if a CPU is available, Turn on NAPI polling for that CPU. */
+ get_online_cpus_atomic();
for_each_online_cpu(cpu) {
if (!cpu_test_and_set(cpu, core_state.cpu_state)) {
v = smp_call_function_single(cpu, cvm_oct_enable_napi,
@@ -106,6 +108,7 @@ static void cvm_oct_enable_one_cpu(void)
break;
}
}
+ put_online_cpus_atomic();
Does this driver really need to be doing this in the first place? If
so, why? The majority of network drivers don't, why is this one
"special"?
It depends on your definition of "need".
The current driver receives packets from *all* network ports into a
single queue (in OCTEON speak this queue is called a POW group). Under
high packet rates, the CPU time required to process the packets may
exceed the capabilities of a single CPU.
In order to increase throughput beyond the single CPU limited rate, we
bring more than one CPUs into play for NAPI receive. The code being
patched here is part of the logic that controls which CPUs are used for
NAPI receive.
Just for the record: Yes I know that doing this may lead to packet
reordering when doing forwarding.
A further question that wasn't asked is: Will the code work at all if a
CPU is taken offline even if the race, the patch eliminates, is avoided?
I doubt it.
As far as the patch goes:
Acked-by: David Daney
David Daney
Honestly, I don't know. Let's CC the author of that code (David Daney).
I wonder why get_maintainer.pl didn't generate his name for this file,
even though the entire file is almost made up of his commits alone!
Regards,
Srivatsa S. Bhat
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Re: [PATCH] gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
Thanks for looking at this again.
I will be away from my office until the middle of July, so I will not be
able to generate and test a revised patch until then.
David Daney
On 06/24/2013 03:06 PM, Linus Walleij wrote:
On Thu, Jun 20, 2013 at 8:10 PM, David Daney wrote:
On 06/17/2013 01:51 AM, Linus Walleij wrote:
+#include
+#include
I cannot find this in my tree.
Weird, I see them here:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/mips/include/asm/octeon/octeon.h
Do you not have these?
Yeah no problem, I must have misgrepped.
Sorry for the fuzz...
depend on OF as well right? Or does the CAVIUM_OCTEON_SOC already
imply that?
We already have 'select USE_OF', so I think adding OF here would be
redundant.
OK.
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int gpio)
Maybe the passed variable shall be named "offset" here, as it is named
offset on all call sites, and it surely local for this instance?
Well it is the gpio line, so perhaps it should universally be change to
"line" or "pin"
We use "offset" to signify line enumerators in drivers/gpio/*
well atleaste if they are local to a piece of hardware.
(Check the GPIO siblings.)
+{
+ if (gpio < 16)
+ return 8 * gpio;
+ else
+ return 8 * (gpio - 16) + 0x100;
Put this 0x100 in the #defines above with the name something like
STRIDE.
But it is not a 'STRIDE', it is a discontinuity compensation and used in
exactly one place.
OK what about a comment or something, because it isn't
exactly intuitive right?
+struct octeon_gpio {
+ struct gpio_chip chip;
+ u64 register_base;
+};
OMG everything is 64 bit. Well has to come to this I guess.
Not everything. This is custom logic in an SoC with 64-bit wide internal
address buses, what would you suggest?
Yep that's what I meant, no big deal. Just first time
I really see it in driver bases.
I'm not a fan of packed bitfields like this, I prefer if you just
OR | and AND & the bits together in the driver.
I see you disregarded this comment, and looking at the header
files it seems the MIPS arch is a big fan if packed bitfields so
will live with it for this arch...
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio,
chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
A common idiom we use for this is:
return !!(read_bits & (1ull << offset));
I hate that idiom, but if its use is a condition of accepting the patch, I
will change it.
Nah. If a good rational reason like "hate" is given for not using a coding
idiom I will accept it as it stands ;-)
+ dev_info(&pdev->dev, "OCTEON GPIO\n");
This is like shouting "REAL MADRID!" in the bootlog, be a bit more
precise: "octeon GPIO driver probed\n" or something so we know what
is happening.
No, more akin to 'Real Madrid', as 'OCTEON' is the correct spelling of its
given name.
I will happily add "driver probed", and grudgingly switch to lower case if
it is a necessary condition of patch acceptance.
I don't know, does this rest of the MIPS drivers emit similar messages
such that the bootlog will say
OCTEON clocks
OCTEON irqchip
OCTEON I2C
OCTEON GPIO
then I guess it's convention and it can stay like this.
Yours,
Linus Walleij
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[PATCH 01/31] MIPS: Move allocate_kscratch to cpu-probe.c and make it public.
From: David Daney
Signed-off-by: David Daney
---
arch/mips/include/asm/mipsregs.h | 2 ++
arch/mips/kernel/cpu-probe.c | 29 +
arch/mips/mm/tlbex.c | 20 +---
3 files changed, 32 insertions(+), 19 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 87e6207..6e0da5aa 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1806,6 +1806,8 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
+int allocate_kscratch(void);
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c6568bf..ee1014e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1064,3 +1064,32 @@ __cpuinit void cpu_report(void)
if (c->options & MIPS_CPU_FPU)
printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
}
+
+static DEFINE_SPINLOCK(kscratch_used_lock);
+
+static unsigned int kscratch_used_mask;
+
+int allocate_kscratch(void)
+{
+ int r;
+ unsigned int a;
+
+ spin_lock(&kscratch_used_lock);
+
+ a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
+
+ r = ffs(a);
+
+ if (r == 0) {
+ r = -1;
+ goto out;
+ }
+
+ r--; /* make it zero based */
+
+ kscratch_used_mask |= (1 << r);
+out:
+ spin_unlock(&kscratch_used_lock);
+
+ return r;
+}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ce9818e..001b87c 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -30,6 +30,7 @@
#include
#include
+#include
#include
#include
#include
@@ -307,25 +308,6 @@ static int check_for_high_segbits __cpuinitdata;
static int check_for_high_segbits __cpuinitdata;
-static unsigned int kscratch_used_mask __cpuinitdata;
-
-static int __cpuinit allocate_kscratch(void)
-{
- int r;
- unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
-
- r = ffs(a);
-
- if (r == 0)
- return -1;
-
- r--; /* make it zero based */
-
- kscratch_used_mask |= (1 << r);
-
- return r;
-}
-
static int scratch_reg __cpuinitdata;
static int pgd_reg __cpuinitdata;
enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
--
1.7.11.7
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[PATCH 12/31] MIPS: Add instruction format information for WAIT, MTC0, MFC0, et al.
From: David Daney
---
arch/mips/include/uapi/asm/inst.h | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/uapi/asm/inst.h
b/arch/mips/include/uapi/asm/inst.h
index 0f4aec2..133abc1 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -117,7 +117,8 @@ enum bcop_op {
enum cop0_coi_func {
tlbr_op = 0x01, tlbwi_op = 0x02,
tlbwr_op = 0x06, tlbp_op = 0x08,
- rfe_op= 0x10, eret_op = 0x18
+ rfe_op= 0x10, eret_op = 0x18,
+ wait_op = 0x20
};
/*
@@ -567,6 +568,24 @@ struct b_format { /* BREAK and SYSCALL */
;)))
};
+struct c0_format { /* WAIT, TLB?? */
+ BITFIELD_FIELD(unsigned int opcode : 6,
+ BITFIELD_FIELD(unsigned int co : 1,
+ BITFIELD_FIELD(unsigned int code : 19,
+ BITFIELD_FIELD(unsigned int func : 6,
+ ;
+};
+
+struct c0m_format {/* MTC0, MFC0, ... */
+ BITFIELD_FIELD(unsigned int opcode : 6,
+ BITFIELD_FIELD(unsigned int func : 5,
+ BITFIELD_FIELD(unsigned int rt : 5,
+ BITFIELD_FIELD(unsigned int rd : 5,
+ BITFIELD_FIELD(unsigned int code : 8,
+ BITFIELD_FIELD(unsigned int sel : 3,
+ ;))
+};
+
struct ps_format { /* MIPS-3D / paired single format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
@@ -857,6 +876,8 @@ union mips_instruction {
struct f_format f_format;
struct ma_format ma_format;
struct b_format b_format;
+ struct c0_format c0_format;
+ struct c0m_format c0m_format;
struct ps_format ps_format;
struct v_format v_format;
struct fb_format fb_format;
--
1.7.11.7
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[PATCH 11/31] MIPS: Rearrange branch.c so it can be used by kvm code.
From: David Daney
Introduce __compute_return_epc_for_insn0() entry point.
Signed-off-by: David Daney
---
arch/mips/include/asm/branch.h | 7 +
arch/mips/kernel/branch.c | 63 +++---
2 files changed, 54 insertions(+), 16 deletions(-)
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index e28a3e0..b3de685 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -37,6 +37,13 @@ static inline unsigned long exception_epc(struct pt_regs
*regs)
#define BRANCH_LIKELY_TAKEN 0x0001
+extern int __compute_return_epc(struct pt_regs *regs);
+extern int __compute_return_epc_for_insn(struct pt_regs *regs,
+union mips_instruction insn);
+extern int __compute_return_epc_for_insn0(struct pt_regs *regs,
+ union mips_instruction insn,
+ unsigned int (*get_fcr31)(void));
+
static inline int compute_return_epc(struct pt_regs *regs)
{
if (get_isa16_mode(regs->cp0_epc)) {
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 46c2ad0..e47145b 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -195,17 +195,18 @@ int __MIPS16e_compute_return_epc(struct pt_regs *regs)
}
/**
- * __compute_return_epc_for_insn - Computes the return address and do emulate
+ * __compute_return_epc_for_insn0 - Computes the return address and do emulate
* branch simulation, if required.
*
* @regs: Pointer to pt_regs
* @insn: branch instruction to decode
- * @returns: -EFAULT on error and forces SIGBUS, and on success
+ * @returns: -EFAULT on error, and on success
* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
* evaluating the branch.
*/
-int __compute_return_epc_for_insn(struct pt_regs *regs,
- union mips_instruction insn)
+int __compute_return_epc_for_insn0(struct pt_regs *regs,
+ union mips_instruction insn,
+ unsigned int (*get_fcr31)(void))
{
unsigned int bit, fcr31, dspcontrol;
long epc = regs->cp0_epc;
@@ -281,7 +282,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case bposge32_op:
if (!cpu_has_dsp)
- goto sigill;
+ return -EFAULT;
dspcontrol = rddsp(0x01);
@@ -364,13 +365,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
* And now the FPA/cp1 branch instructions.
*/
case cop1_op:
- preempt_disable();
- if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
- else
- fcr31 = current->thread.fpu.fcr31;
- preempt_enable();
-
+ fcr31 = get_fcr31();
bit = (insn.i_format.rt >> 2);
bit += (bit != 0);
bit += 23;
@@ -434,11 +429,47 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
}
return ret;
+}
+EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn0);
-sigill:
- printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n",
current->comm);
- force_sig(SIGBUS, current);
- return -EFAULT;
+static unsigned int __get_fcr31(void)
+{
+ unsigned int fcr31;
+
+ preempt_disable();
+ if (is_fpu_owner())
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
+ else
+ fcr31 = current->thread.fpu.fcr31;
+ preempt_enable();
+ return fcr31;
+}
+
+/**
+ * __compute_return_epc_for_insn - Computes the return address and do emulate
+ * branch simulation, if required.
+ *
+ * @regs: Pointer to pt_regs
+ * @insn: branch instruction to decode
+ * @returns: -EFAULT on error and forces SIGBUS, and on success
+ * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
+ * evaluating the branch.
+ */
+int __compute_return_epc_for_insn(struct pt_regs *regs,
+ union mips_instruction insn)
+{
+ int r = __compute_return_epc_for_insn0(regs, insn, __get_fcr31);
+
+ if (r < 0) {
+ printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n",
current->comm);
+ force_sig(SIGBUS, current);
+ }
+
+ return r;
}
EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
--
1.7.11.7
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[PATCH 30/31] mips/kvm: Enable MIPSVZ in Kconfig/Makefile
From: David Daney Also let CPU_CAVIUM_OCTEON select KVM. Signed-off-by: David Daney --- arch/mips/Kconfig | 1 + arch/mips/kvm/Kconfig | 9 + arch/mips/kvm/Makefile | 1 + 3 files changed, 11 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7a58ab9..16e3d22 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1426,6 +1426,7 @@ config CPU_CAVIUM_OCTEON select LIBFDT select USE_OF select USB_EHCI_BIG_ENDIAN_MMIO + select HAVE_KVM help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/kvm/Kconfig b/arch/mips/kvm/Kconfig index 95c0d22..32a5016 100644 --- a/arch/mips/kvm/Kconfig +++ b/arch/mips/kvm/Kconfig @@ -48,6 +48,15 @@ config KVM_MIPS_DEBUG_COP0_COUNTERS If unsure, say N. +config KVM_MIPSVZ + bool "Kernel-based Virtual Machine (KVM) using hardware MIPS-VZ support" + depends on HAVE_KVM + select KVM + ---help--- + Support for hosting Guest kernels on hardware with the + MIPS-VZ hardware module. + + source drivers/vhost/Kconfig endif # VIRTUALIZATION diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile index 3377197..595358f 100644 --- a/arch/mips/kvm/Makefile +++ b/arch/mips/kvm/Makefile @@ -13,3 +13,4 @@ kvm_mipste-objs := kvm_mips_emul.o kvm_locore.o kvm_mips_int.o \ obj-$(CONFIG_KVM) += $(common-objs) kvm_mips.o obj-$(CONFIG_KVM_MIPSTE) += kvm_mipste.o +obj-$(CONFIG_KVM_MIPSVZ) += kvm_mipsvz.o kvm_mipsvz_guest.o -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 27/31] mips/kvm: Gate the use of kvm_local_flush_tlb_all() by KVM_MIPSTE
From: David Daney
Only the trap-and-emulate KVM code needs a Special tlb flusher. All
other configurations should use the regular version.
Signed-off-by: David Daney
---
arch/mips/include/asm/mmu_context.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mmu_context.h
b/arch/mips/include/asm/mmu_context.h
index 5609a32..04d0b74 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_asid(unsigned long cpu)
if (! ((asid += ASID_INC) & ASID_MASK) ) {
if (cpu_has_vtag_icache)
flush_icache_all();
-#ifdef CONFIG_VIRTUALIZATION
+#if IS_ENABLED(CONFIG_KVM_MIPSTE)
kvm_local_flush_tlb_all(); /* start new asid cycle */
#else
local_flush_tlb_all(); /* start new asid cycle */
--
1.7.11.7
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[PATCH 31/31] mips/kvm: Allow for upto 8 KVM vcpus per vm.
From: David Daney The mipsvz implementation allows for SMP, so let's be able to create all those vcpus. Signed-off-by: David Daney --- arch/mips/include/asm/kvm_host.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 9f209e1..0a5e218 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -20,7 +20,7 @@ #include -#define KVM_MAX_VCPUS 1 +#define KVM_MAX_VCPUS 8 #define KVM_USER_MEM_SLOTS 8 /* memory slots that does not exposed to userspace */ #define KVM_PRIVATE_MEM_SLOTS 0 -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 26/31] mips/kvm: Split up Kconfig and Makefile definitions in preperation for MIPSVZ.
From: David Daney Create the symbol KVM_MIPSTE, and use it to select the trap and emulate specific things. Signed-off-by: David Daney --- arch/mips/kvm/Kconfig | 14 +- arch/mips/kvm/Makefile | 14 -- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/mips/kvm/Kconfig b/arch/mips/kvm/Kconfig index 2c15590..95c0d22 100644 --- a/arch/mips/kvm/Kconfig +++ b/arch/mips/kvm/Kconfig @@ -16,18 +16,22 @@ menuconfig VIRTUALIZATION if VIRTUALIZATION config KVM - tristate "Kernel-based Virtual Machine (KVM) support" - depends on HAVE_KVM + tristate select PREEMPT_NOTIFIERS + +config KVM_MIPSTE + tristate "Kernel-based Virtual Machine (KVM) 32-bit trap-and-emulate" + depends on HAVE_KVM + select KVM select ANON_INODES select KVM_MMIO ---help--- - Support for hosting Guest kernels. + Support for hosting Guest kernels with modified address space layout. Currently supported on MIPS32 processors. config KVM_MIPS_DYN_TRANS bool "KVM/MIPS: Dynamic binary translation to reduce traps" - depends on KVM + depends on KVM_MIPSTE ---help--- When running in Trap & Emulate mode patch privileged instructions to reduce the number of traps. @@ -36,7 +40,7 @@ config KVM_MIPS_DYN_TRANS config KVM_MIPS_DEBUG_COP0_COUNTERS bool "Maintain counters for COP0 accesses" - depends on KVM + depends on KVM_MIPSTE ---help--- Maintain statistics for Guest COP0 accesses. A histogram of COP0 accesses is printed when the VM is diff --git a/arch/mips/kvm/Makefile b/arch/mips/kvm/Makefile index 78d87bb..3377197 100644 --- a/arch/mips/kvm/Makefile +++ b/arch/mips/kvm/Makefile @@ -1,13 +1,15 @@ # Makefile for KVM support for MIPS # -common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o) +common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o) EXTRA_CFLAGS += -Ivirt/kvm -Iarch/mips/kvm -kvm-objs := $(common-objs) kvm_mips.o kvm_mips_emul.o kvm_locore.o \ - kvm_mips_int.o kvm_mips_stats.o kvm_mips_commpage.o \ - kvm_mips_dyntrans.o kvm_trap_emul.o +kvm_mipste-objs:= kvm_mips_emul.o kvm_locore.o kvm_mips_int.o \ + kvm_mips_stats.o kvm_mips_commpage.o \ + kvm_mips_dyntrans.o kvm_trap_emul.o kvm_cb.o \ + kvm_tlb.o \ + $(addprefix ../../../virt/kvm/, coalesced_mmio.o) -obj-$(CONFIG_KVM) += kvm.o -obj-y += kvm_cb.o kvm_tlb.o +obj-$(CONFIG_KVM) += $(common-objs) kvm_mips.o +obj-$(CONFIG_KVM_MIPSTE) += kvm_mipste.o -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 23/31] mips/kvm: Hook into CP unusable exception handler.
From: David Daney
The MIPS VZ KVM code needs this to be able to manage the FPU.
Signed-off-by: David Daney
---
arch/mips/kernel/traps.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fca0a2f..2bdeb32 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -56,6 +56,7 @@
#include
#include
#include
+#include
extern void check_wait(void);
extern asmlinkage void rollback_handle_int(void);
@@ -1045,6 +1046,13 @@ asmlinkage void do_cpu(struct pt_regs *regs)
int status;
unsigned long __maybe_unused flags;
+#ifdef CONFIG_KVM_MIPSVZ
+ if (test_tsk_thread_flag(current, TIF_GUESTMODE)) {
+ if (mipsvz_cp_unusable(regs))
+ return;
+ }
+#endif
+
die_if_kernel("do_cpu invoked from kernel context!", regs);
cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
--
1.7.11.7
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[PATCH 24/31] mips/kvm: Add thread_struct fields used by MIPSVZ hosts.
From: David Daney
... and their accessors in asm-offsets.c
Signed-off-by: David Daney
---
arch/mips/include/asm/processor.h | 6 ++
arch/mips/kernel/asm-offsets.c| 5 +
2 files changed, 11 insertions(+)
diff --git a/arch/mips/include/asm/processor.h
b/arch/mips/include/asm/processor.h
index 1470b7b..e0aa198 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -198,6 +198,7 @@ typedef struct {
#define ARCH_MIN_TASKALIGN 8
struct mips_abi;
+struct kvm_vcpu;
/*
* If you change thread_struct remember to change the #defines below too!
@@ -230,6 +231,11 @@ struct thread_struct {
unsigned long cp0_badvaddr; /* Last user fault */
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
unsigned long error_code;
+#ifdef CONFIG_KVM_MIPSVZ
+ struct kvm_vcpu *vcpu;
+ unsigned int mm_asid;
+ unsigned int guest_asid;
+#endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON
struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index c5cc28f..37fd9e2 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -132,6 +132,11 @@ void output_thread_defines(void)
thread.cp0_baduaddr);
OFFSET(THREAD_ECODE, task_struct, \
thread.error_code);
+#ifdef CONFIG_KVM_MIPSVZ
+ OFFSET(THREAD_VCPU, task_struct, thread.vcpu);
+ OFFSET(THREAD_MM_ASID, task_struct, thread.mm_asid);
+ OFFSET(THREAD_GUEST_ASID, task_struct, thread.guest_asid);
+#endif
BLANK();
}
--
1.7.11.7
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[PATCH 25/31] mips/kvm: Add some asm-offsets constants used by MIPSVZ.
From: David Daney
Signed-off-by: David Daney
---
arch/mips/kernel/asm-offsets.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 37fd9e2..db09376 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -19,6 +19,7 @@
#include
#include
+#include
void output_ptreg_defines(void)
{
@@ -345,6 +346,8 @@ void output_pbe_defines(void)
void output_kvm_defines(void)
{
COMMENT(" KVM/MIPS Specfic offsets. ");
+ OFFSET(KVM_ARCH_IMPL, kvm, arch.impl);
+ OFFSET(KVM_VCPU_KVM, kvm_vcpu, kvm);
DEFINE(VCPU_ARCH_SIZE, sizeof(struct kvm_vcpu_arch));
OFFSET(VCPU_RUN, kvm_vcpu, run);
OFFSET(VCPU_HOST_ARCH, kvm_vcpu, arch);
@@ -411,5 +414,9 @@ void output_kvm_defines(void)
OFFSET(COP0_TLB_HI, mips_coproc, reg[MIPS_CP0_TLB_HI][0]);
OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
BLANK();
+
+ COMMENT(" Linux struct kvm mipsvz offsets. ");
+ OFFSET(KVM_MIPS_VZ_PGD, kvm_mips_vz, pgd);
+ BLANK();
}
#endif
--
1.7.11.7
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[PATCH 28/31] mips/kvm: Only use KVM_COALESCED_MMIO_PAGE_OFFSET with KVM_MIPSTE
From: David Daney The forthcoming MIPSVZ code doesn't currently use this, so it must only be enabled for KVM_MIPSTE. Signed-off-by: David Daney --- arch/mips/include/asm/kvm_host.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 505b804..9f209e1 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -25,7 +25,9 @@ /* memory slots that does not exposed to userspace */ #define KVM_PRIVATE_MEM_SLOTS 0 +#ifdef CONFIG_KVM_MIPSTE #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 +#endif /* Don't support huge pages */ #define KVM_HPAGE_GFN_SHIFT(x) 0 -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 18/31] mips/kvm: Add pt_regs slots for BadInstr and BadInstrP
From: David Daney
These save the instruction word to be used by MIPSVZ code for
instruction emulation.
Signed-off-by: David Daney
---
arch/mips/include/asm/ptrace.h | 4
arch/mips/kernel/asm-offsets.c | 4
2 files changed, 8 insertions(+)
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 5e6cd09..d080716 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -46,6 +46,10 @@ struct pt_regs {
unsigned long long mpl[3];/* MTM{0,1,2} */
unsigned long long mtp[3];/* MTP{0,1,2} */
#endif
+#ifdef CONFIG_KVM_MIPSVZ
+ unsigned int cp0_badinstr; /* Only populated on
do_page_fault_{0,1} */
+ unsigned int cp0_badinstrp; /* Only populated on
do_page_fault_{0,1} */
+#endif
} __aligned(8);
struct task_struct;
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 03bf363..c5cc28f 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -71,6 +71,10 @@ void output_ptreg_defines(void)
OFFSET(PT_MPL, pt_regs, mpl);
OFFSET(PT_MTP, pt_regs, mtp);
#endif /* CONFIG_CPU_CAVIUM_OCTEON */
+#ifdef CONFIG_KVM_MIPSVZ
+ OFFSET(PT_BADINSTR, pt_regs, cp0_badinstr);
+ OFFSET(PT_BADINSTRP, pt_regs, cp0_badinstrp);
+#endif
DEFINE(PT_SIZE, sizeof(struct pt_regs));
BLANK();
}
--
1.7.11.7
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[PATCH 19/31] mips/kvm: Add host definitions for MIPS VZ based host.
From: David Daney
Signed-off-by: David Daney
---
arch/mips/include/asm/kvm_mips_vz.h | 29 +
1 file changed, 29 insertions(+)
create mode 100644 arch/mips/include/asm/kvm_mips_vz.h
diff --git a/arch/mips/include/asm/kvm_mips_vz.h
b/arch/mips/include/asm/kvm_mips_vz.h
new file mode 100644
index 000..dfc6951
--- /dev/null
+++ b/arch/mips/include/asm/kvm_mips_vz.h
@@ -0,0 +1,29 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2013 Cavium, Inc.
+ */
+#ifndef _ASM_KVM_MIPS_VZ_H
+#define _ASM_KVM_MIPS_VZ_H
+
+struct kvm;
+
+struct kvm_mips_vz {
+ struct mutex guest_mm_lock;
+ pgd_t *pgd; /* Translations for this host. */
+ spinlock_t irq_chip_lock;
+ struct page *irq_chip;
+ unsigned int asid[NR_CPUS]; /* Per CPU ASIDs for pgd. */
+};
+
+bool mipsvz_page_fault(struct pt_regs *regs, unsigned long write,
+ unsigned long address);
+
+bool mipsvz_cp_unusable(struct pt_regs *regs);
+int mipsvz_arch_init(void *opaque);
+int mipsvz_arch_hardware_enable(void *garbage);
+int mipsvz_init_vm(struct kvm *kvm, unsigned long type);
+
+#endif /* _ASM_KVM_MIPS_VZ_H */
--
1.7.11.7
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[PATCH 20/31] mips/kvm: Hook into TLB fault handlers.
From: David Daney
If the CPU is operating in guest mode when a TLB related excpetion
occurs, give KVM a chance to do emulation.
Signed-off-by: David Daney
---
arch/mips/mm/fault.c | 8
arch/mips/mm/tlbex-fault.S | 6 ++
2 files changed, 14 insertions(+)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 0fead53..9391da49 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -26,6 +26,7 @@
#include
#include/* For VMALLOC_END */
#include
+#include
/*
* This routine handles page faults. It determines the address,
@@ -50,6 +51,13 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs
*regs, unsigned long writ
field, regs->cp0_epc);
#endif
+#ifdef CONFIG_KVM_MIPSVZ
+ if (test_tsk_thread_flag(current, TIF_GUESTMODE)) {
+ if (mipsvz_page_fault(regs, write, address))
+ return;
+ }
+#endif
+
#ifdef CONFIG_KPROBES
/*
* This is to notify the fault handler of the kprobes. The
diff --git a/arch/mips/mm/tlbex-fault.S b/arch/mips/mm/tlbex-fault.S
index 318855e..df0f70b 100644
--- a/arch/mips/mm/tlbex-fault.S
+++ b/arch/mips/mm/tlbex-fault.S
@@ -14,6 +14,12 @@
NESTED(tlb_do_page_fault_\write, PT_SIZE, sp)
SAVE_ALL
MFC0a2, CP0_BADVADDR
+#ifdef CONFIG_KVM_MIPSVZ
+ mfc0v0, CP0_BADINSTR
+ mfc0v1, CP0_BADINSTRP
+ sw v0, PT_BADINSTR(sp)
+ sw v1, PT_BADINSTRP(sp)
+#endif
KMODE
movea0, sp
REG_S a2, PT_BVADDR(sp)
--
1.7.11.7
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[PATCH 21/31] mips/kvm: Allow set_except_vector() to be used from MIPSVZ code.
From: David Daney
We need to move it out of __init so we don't have section mismatch problems.
Signed-off-by: David Daney
---
arch/mips/include/asm/uasm.h | 2 +-
arch/mips/kernel/traps.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 370d967..90b4f5e 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -11,7 +11,7 @@
#include
-#ifdef CONFIG_EXPORT_UASM
+#if defined(CONFIG_EXPORT_UASM) || IS_ENABLED(CONFIG_KVM_MIPSVZ)
#include
#define __uasminit
#define __uasminitdata
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f008795..fca0a2f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1457,7 +1457,7 @@ unsigned long ebase;
unsigned long exception_handlers[32];
unsigned long vi_handlers[64];
-void __init *set_except_vector(int n, void *addr)
+void __uasminit *set_except_vector(int n, void *addr)
{
unsigned long handler = (unsigned long) addr;
unsigned long old_handler;
--
1.7.11.7
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[PATCH 13/31] mips/kvm: Add accessors for MIPS VZ registers.
From: David Daney
There are accessors for both the guest control registers as well as
guest CP0 context.
Signed-off-by: David Daney
---
arch/mips/include/asm/mipsregs.h | 260 +++
1 file changed, 260 insertions(+)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 6f03c72..0addfec 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -50,10 +50,13 @@
#define CP0_WIRED $6
#define CP0_INFO $7
#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
+#define CP0_BADINSTRP $8, 2
#define CP0_COUNT $9
#define CP0_ENTRYHI $10
#define CP0_COMPARE $11
#define CP0_STATUS $12
+#define CP0_GUESTCTL0 $12, 6
#define CP0_CAUSE $13
#define CP0_EPC $14
#define CP0_PRID $15
@@ -623,6 +626,10 @@
#define MIPS_FPIR_L(_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
+/* Bits in the MIPS VZ GuestCtl0 Register */
+#define MIPS_GUESTCTL0B_GM 31
+#define MIPS_GUESTCTL0F_GM (_ULCAST_(1) << MIPS_GUESTCTL0B_GM)
+
#ifndef __ASSEMBLY__
/*
@@ -851,6 +858,144 @@ do {
\
local_irq_restore(__flags); \
} while (0)
+/*
+ * Macros to access the VZ Guest system control coprocessor
+ */
+
+#define __read_32bit_gc0_register(source, sel) \
+ ({ int __res; \
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t"\
+ ".ifeq 0-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 0\n\t" \
+ ".endif\n\t"\
+ ".ifeq 1-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 1\n\t" \
+ ".endif\n\t"\
+ ".ifeq 2-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 2\n\t" \
+ ".endif\n\t"\
+ ".ifeq 3-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 3\n\t" \
+ ".endif\n\t"\
+ ".ifeq 4-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 4\n\t" \
+ ".endif\n\t"\
+ ".ifeq 5-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 5\n\t" \
+ ".endif\n\t"\
+ ".ifeq 6-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 6\n\t" \
+ ".endif\n\t"\
+ ".ifeq 7-" #sel "\n\t" \
+ "mfgc0\t%0, " #source ", 7\n\t" \
+ ".endif\n\t"\
+ ".set\tmips0" \
+ : "=r" (__res));\
+ __res; \
+})
+
+#define __read_64bit_gc0_register(source, sel) \
+ ({ unsigned long long __res;\
+ __asm__ __volatile__( \
+ ".set mips64r2\n\t" \
+ ".set\tvirt\n\t"\
+ ".ifeq 0-" #sel "\n\t" \
+ "dmfgc0\t%0, " #source ", 0\n\t"\
+ ".endif\n\t"\
+ ".ifeq 1-" #sel "\n\t"
[PATCH 22/31] mips/kvm: Split get_new_mmu_context into two parts.
From: David Daney
The new function (part) get_new_asid() can now be used from MIPSVZ code.
Signed-off-by: David Daney
---
arch/mips/include/asm/mmu_context.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/mmu_context.h
b/arch/mips/include/asm/mmu_context.h
index 8201160..5609a32 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -108,8 +108,8 @@ static inline void enter_lazy_tlb(struct mm_struct *mm,
struct task_struct *tsk)
#ifndef CONFIG_MIPS_MT_SMTC
/* Normal, classic MIPS get_new_mmu_context */
-static inline void
-get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
+static inline unsigned long
+get_new_asid(unsigned long cpu)
{
extern void kvm_local_flush_tlb_all(void);
unsigned long asid = asid_cache(cpu);
@@ -125,7 +125,13 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long
cpu)
if (!asid) /* fix version if needed */
asid = ASID_FIRST_VERSION;
}
+ return asid;
+}
+static inline void
+get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
+{
+ unsigned long asid = get_new_asid(cpu);
cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}
--
1.7.11.7
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[PATCH 14/31] mips/kvm: Add thread_info flag to indicate operation in MIPS VZ Guest Mode.
From: David Daney Signed-off-by: David Daney --- arch/mips/include/asm/thread_info.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 895320e..a7a894a 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -109,6 +109,7 @@ static inline struct thread_info *current_thread_info(void) #define TIF_RESTORE_SIGMASK9 /* restore signal mask in do_signal() */ #define TIF_USEDFPU16 /* FPU was used by this task this quantum (SMP) */ #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ +#define TIF_GUESTMODE 19 /* If set, running in VZ Guest mode. */ #define TIF_FIXADE 20 /* Fix address errors in software */ #define TIF_LOGADE 21 /* Log address errors to syslog */ #define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ @@ -124,6 +125,7 @@ static inline struct thread_info *current_thread_info(void) #define _TIF_SECCOMP (1<http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 15/31] mips/kvm: Exception handling to leave and reenter guest mode.
From: David Daney Currently this is a little complex, here are the facts about how it works: o When running in Guest mode we set the high bit of CP0_XCONTEXT. If this bit is clear, we don't do anything special on an exception. o If we are in guest mode, upon an exception we: 1) load the stack pointer from the mips_kvm_rootsp array instead of kernelsp. 2) Clear GuestCtl[GM] and high bit of CP0_XCONTEXT. 3) Restore host ASID and PGD pointer. o Upon restarting from an exception we test the task TIF_GUESTMODE flag if it is clear, nothing special is done. o If Guest mode is active for the thread we: 1) Compare the stack pointer to mips_kvm_rootsp, if it doesn't match we are not reentering guest mode, so no more special processing is done. 2) If reentering guest mode: 2a) Set high bit of CP0_XCONTEXT and GuestCtl[GM]. 2b) Set Guest mode ASID and PGD pointer. This allows a single set of exception handlers to be used for both host and guest mode operation. Signed-off-by: David Daney --- arch/mips/include/asm/stackframe.h | 135 - 1 file changed, 132 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index 20627b2..bf2ec48 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -17,6 +17,7 @@ #include #include #include +#include /* * For SMTC kernel, global IE should be left set, and interrupts @@ -98,7 +99,9 @@ #define CPU_ID_REG CP0_CONTEXT #define CPU_ID_MFC0 MFC0 #endif - .macro get_saved_sp/* SMP variation */ +#define CPU_ID_MASK ((1 << 13) - 1) + + .macro get_saved_sp_for_save_some /* SMP variation */ CPU_ID_MFC0 k0, CPU_ID_REG #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) @@ -110,15 +113,49 @@ dsllk1, 16 #endif LONG_SRLk0, PTEBASE_SHIFT +#ifdef CONFIG_KVM_MIPSVZ + andik0, CPU_ID_MASK /* high bits indicate guest mode. */ +#endif LONG_ADDU k1, k0 LONG_L k1, %lo(kernelsp)(k1) .endm + .macro get_saved_sp + CPU_ID_MFC0 k0, CPU_ID_REG + get_saved_sp_for_save_some + .endm + + .macro get_mips_kvm_rootsp /* SMP variation */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(mips_kvm_rootsp) +#else + lui k1, %highest(mips_kvm_rootsp) + daddiu k1, %higher(mips_kvm_rootsp) + dsllk1, 16 + daddiu k1, %hi(mips_kvm_rootsp) + dsllk1, 16 +#endif + LONG_SRLk0, PTEBASE_SHIFT + andik0, CPU_ID_MASK /* high bits indicate guest mode. */ + LONG_ADDU k1, k0 + LONG_L k1, %lo(mips_kvm_rootsp)(k1) + .endm + .macro set_saved_sp stackp temp temp2 CPU_ID_MFC0 \temp, CPU_ID_REG LONG_SRL\temp, PTEBASE_SHIFT +#ifdef CONFIG_KVM_MIPSVZ + andik0, CPU_ID_MASK /* high bits indicate guest mode. */ +#endif LONG_S \stackp, kernelsp(\temp) .endm + + .macro set_mips_kvm_rootsp stackp temp + CPU_ID_MFC0 \temp, CPU_ID_REG + LONG_SRL\temp, PTEBASE_SHIFT + andik0, CPU_ID_MASK /* high bits indicate guest mode. */ + LONG_S \stackp, mips_kvm_rootsp(\temp) + .endm #else .macro get_saved_sp/* Uniprocessor variation */ #ifdef CONFIG_CPU_JUMP_WORKAROUNDS @@ -152,9 +189,27 @@ LONG_L k1, %lo(kernelsp)(k1) .endm + .macro get_mips_kvm_rootsp /* Uniprocessor variation */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(mips_kvm_rootsp) +#else + lui k1, %highest(mips_kvm_rootsp) + daddiu k1, %higher(mips_kvm_rootsp) + dsllk1, k1, 16 + daddiu k1, %hi(mips_kvm_rootsp) + dsllk1, k1, 16 +#endif + LONG_L k1, %lo(mips_kvm_rootsp)(k1) + .endm + + .macro set_saved_sp stackp temp temp2 LONG_S \stackp, kernelsp .endm + + .macro set_mips_kvm_rootsp stackp temp + LONG_S \stackp, mips_kvm_rootsp + .endm #endif .macro SAVE_SOME @@ -164,11 +219,21 @@ mfc0k0, CP0_STATUS sll k0, 3 /* extract cu0 bit */ .setnoreorder +#ifdef CONFIG_KVM_MIPSVZ + bgezk0, 7f +CPU_ID_MFC0k0, CPU_ID_REG +
[PATCH 16/31] mips/kvm: Add exception handler for MIPSVZ Guest exceptions.
From: David Daney Signed-off-by: David Daney --- arch/mips/kernel/genex.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 163e299..ce0be96 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -486,6 +486,9 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ BUILD_HANDLER mt mt sti silent /* #25 */ BUILD_HANDLER dsp dsp sti silent/* #26 */ +#ifdef CONFIG_KVM_MIPSVZ + BUILD_HANDLER hypervisor hypervisor cli silent /* #27 */ +#endif BUILD_HANDLER reserved reserved sti verbose /* others */ .align 5 -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 17/31] MIPS: Quit exposing Kconfig symbols in uapi headers.
From: David Daney
The kernel's struct pt_regs has many fields conditional on various
Kconfig variables, we cannot be exporting this garbage to user-space.
Move the kernel's definition to asm/ptrace.h, and put a uapi only
version in uapi/asm/ptrace.h gated by #ifndef __KERNEL__
Signed-off-by: David Daney
---
arch/mips/include/asm/ptrace.h | 32
arch/mips/include/uapi/asm/ptrace.h | 17 ++---
2 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index a3186f2..5e6cd09 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -16,6 +16,38 @@
#include
#include
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+ /* Pad bytes for argument save space on the stack. */
+ unsigned long pad0[6];
+#endif
+
+ /* Saved main processor registers. */
+ unsigned long regs[32];
+
+ /* Saved special registers. */
+ unsigned long cp0_status;
+ unsigned long hi;
+ unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+ unsigned long acx;
+#endif
+ unsigned long cp0_badvaddr;
+ unsigned long cp0_cause;
+ unsigned long cp0_epc;
+#ifdef CONFIG_MIPS_MT_SMTC
+ unsigned long cp0_tcstatus;
+#endif /* CONFIG_MIPS_MT_SMTC */
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+ unsigned long long mpl[3];/* MTM{0,1,2} */
+ unsigned long long mtp[3];/* MTP{0,1,2} */
+#endif
+} __aligned(8);
+
struct task_struct;
extern int ptrace_getregs(struct task_struct *child, __s64 __user *data);
diff --git a/arch/mips/include/uapi/asm/ptrace.h
b/arch/mips/include/uapi/asm/ptrace.h
index 4d58d84..b26f7e3 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -22,16 +22,12 @@
#define DSP_CONTROL77
#define ACX78
+#ifndef __KERNEL__
/*
* This struct defines the way the registers are stored on the stack during a
* system call/exception. As usual the registers k0/k1 aren't being saved.
*/
struct pt_regs {
-#ifdef CONFIG_32BIT
- /* Pad bytes for argument save space on the stack. */
- unsigned long pad0[6];
-#endif
-
/* Saved main processor registers. */
unsigned long regs[32];
@@ -39,20 +35,11 @@ struct pt_regs {
unsigned long cp0_status;
unsigned long hi;
unsigned long lo;
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
- unsigned long acx;
-#endif
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
- unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
- unsigned long long mpl[3];/* MTM{0,1,2} */
- unsigned long long mtp[3];/* MTP{0,1,2} */
-#endif
} __attribute__ ((aligned (8)));
+#endif /* __KERNEL__ */
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
#define PTRACE_GETREGS 12
--
1.7.11.7
--
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[PATCH 08/31] mips/kvm: Fix code formatting in arch/mips/kvm/kvm_locore.S
From: David Daney It was a completely inconsistent mix of spaces and tabs. Signed-off-by: David Daney --- arch/mips/kvm/kvm_locore.S | 921 +++-- 1 file changed, 464 insertions(+), 457 deletions(-) diff --git a/arch/mips/kvm/kvm_locore.S b/arch/mips/kvm/kvm_locore.S index 7a33ee7..7c2933a 100644 --- a/arch/mips/kvm/kvm_locore.S +++ b/arch/mips/kvm/kvm_locore.S @@ -1,13 +1,13 @@ /* -* This file is subject to the terms and conditions of the GNU General Public -* License. See the file "COPYING" in the main directory of this archive -* for more details. -* -* Main entry point for the guest, exception handling. -* -* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. -* Authors: Sanjay Lal -*/ + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Main entry point for the guest, exception handling. + * + * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. + * Authors: Sanjay Lal + */ #include #include @@ -57,172 +57,177 @@ */ FEXPORT(__kvm_mips_vcpu_run) -.setpush -.setnoreorder -.setnoat - -/* k0/k1 not being used in host kernel context */ - addiu k1,sp, -PT_SIZE -LONG_S $0, PT_R0(k1) -LONG_S $1, PT_R1(k1) -LONG_S $2, PT_R2(k1) -LONG_S $3, PT_R3(k1) - -LONG_S $4, PT_R4(k1) -LONG_S $5, PT_R5(k1) -LONG_S $6, PT_R6(k1) -LONG_S $7, PT_R7(k1) - -LONG_S $8, PT_R8(k1) -LONG_S $9, PT_R9(k1) -LONG_S $10, PT_R10(k1) -LONG_S $11, PT_R11(k1) -LONG_S $12, PT_R12(k1) -LONG_S $13, PT_R13(k1) -LONG_S $14, PT_R14(k1) -LONG_S $15, PT_R15(k1) -LONG_S $16, PT_R16(k1) -LONG_S $17, PT_R17(k1) - -LONG_S $18, PT_R18(k1) -LONG_S $19, PT_R19(k1) -LONG_S $20, PT_R20(k1) -LONG_S $21, PT_R21(k1) -LONG_S $22, PT_R22(k1) -LONG_S $23, PT_R23(k1) -LONG_S $24, PT_R24(k1) -LONG_S $25, PT_R25(k1) + .setpush + .setnoreorder + .setnoat + + /* k0/k1 not being used in host kernel context */ + addiu k1, sp, -PT_SIZE + LONG_S $0, PT_R0(k1) + LONG_S $1, PT_R1(k1) + LONG_S $2, PT_R2(k1) + LONG_S $3, PT_R3(k1) + + LONG_S $4, PT_R4(k1) + LONG_S $5, PT_R5(k1) + LONG_S $6, PT_R6(k1) + LONG_S $7, PT_R7(k1) + + LONG_S $8, PT_R8(k1) + LONG_S $9, PT_R9(k1) + LONG_S $10, PT_R10(k1) + LONG_S $11, PT_R11(k1) + LONG_S $12, PT_R12(k1) + LONG_S $13, PT_R13(k1) + LONG_S $14, PT_R14(k1) + LONG_S $15, PT_R15(k1) + LONG_S $16, PT_R16(k1) + LONG_S $17, PT_R17(k1) + + LONG_S $18, PT_R18(k1) + LONG_S $19, PT_R19(k1) + LONG_S $20, PT_R20(k1) + LONG_S $21, PT_R21(k1) + LONG_S $22, PT_R22(k1) + LONG_S $23, PT_R23(k1) + LONG_S $24, PT_R24(k1) + LONG_S $25, PT_R25(k1) /* XXXKYMA k0/k1 not saved, not being used if we got here through an ioctl() */ -LONG_S $28, PT_R28(k1) -LONG_S $29, PT_R29(k1) -LONG_S $30, PT_R30(k1) -LONG_S $31, PT_R31(k1) + LONG_S $28, PT_R28(k1) + LONG_S $29, PT_R29(k1) + LONG_S $30, PT_R30(k1) + LONG_S $31, PT_R31(k1) -/* Save hi/lo */ - mflov0 - LONG_S v0, PT_LO(k1) - mfhiv1 - LONG_S v1, PT_HI(k1) + /* Save hi/lo */ + mflov0 + LONG_S v0, PT_LO(k1) + mfhiv1 + LONG_S v1, PT_HI(k1) /* Save host status */ - mfc0v0, CP0_STATUS - LONG_S v0, PT_STATUS(k1) + mfc0v0, CP0_STATUS + LONG_S v0, PT_STATUS(k1) /* Save host ASID, shove it into the BVADDR location */ - mfc0v1,CP0_ENTRYHI - andiv1, 0xff - LONG_S v1, PT_HOST_ASID(k1) + mfc0v1, CP0_ENTRYHI + andiv1, 0xff + LONG_S v1, PT_HOST_ASID(k1) -/* Save DDATA_LO, will be used to store pointer to vcpu */ -mfc0v1, CP0_DDATA_LO -LONG_S v1, PT_HOST_USERLOCAL(k1) + /* Save DDATA_LO, will be used to store pointer to vcpu */ + mfc0v1, CP0_DDATA_LO + LONG_S v1, PT_HOST_USERLOCAL(k1) -/* DDATA_LO has pointer to vcpu */ -mtc0a1,CP0_DDATA_LO + /* DDATA_LO has pointer to vcpu */ + mtc0a1, CP0_DDATA_LO -/* Offset into vcpu->arch */ - addiu k1, a1, VCPU_HOST
[PATCH 07/31] mips/kvm: Rename VCPU_registername to KVM_VCPU_ARCH_registername
From: David Daney This makes it follow the pattern where the structure name is the symbol name prefix. Signed-off-by: David Daney --- arch/mips/kernel/asm-offsets.c | 68 +++--- arch/mips/kvm/kvm_locore.S | 206 - 2 files changed, 137 insertions(+), 137 deletions(-) diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index 22bf8f5..a0aa12c 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -351,40 +351,40 @@ void output_kvm_defines(void) OFFSET(VCPU_GUEST_INST, kvm_vcpu_arch, guest_inst); - OFFSET(VCPU_R0, kvm_vcpu_arch, gprs[0]); - OFFSET(VCPU_R1, kvm_vcpu_arch, gprs[1]); - OFFSET(VCPU_R2, kvm_vcpu_arch, gprs[2]); - OFFSET(VCPU_R3, kvm_vcpu_arch, gprs[3]); - OFFSET(VCPU_R4, kvm_vcpu_arch, gprs[4]); - OFFSET(VCPU_R5, kvm_vcpu_arch, gprs[5]); - OFFSET(VCPU_R6, kvm_vcpu_arch, gprs[6]); - OFFSET(VCPU_R7, kvm_vcpu_arch, gprs[7]); - OFFSET(VCPU_R8, kvm_vcpu_arch, gprs[8]); - OFFSET(VCPU_R9, kvm_vcpu_arch, gprs[9]); - OFFSET(VCPU_R10, kvm_vcpu_arch, gprs[10]); - OFFSET(VCPU_R11, kvm_vcpu_arch, gprs[11]); - OFFSET(VCPU_R12, kvm_vcpu_arch, gprs[12]); - OFFSET(VCPU_R13, kvm_vcpu_arch, gprs[13]); - OFFSET(VCPU_R14, kvm_vcpu_arch, gprs[14]); - OFFSET(VCPU_R15, kvm_vcpu_arch, gprs[15]); - OFFSET(VCPU_R16, kvm_vcpu_arch, gprs[16]); - OFFSET(VCPU_R17, kvm_vcpu_arch, gprs[17]); - OFFSET(VCPU_R18, kvm_vcpu_arch, gprs[18]); - OFFSET(VCPU_R19, kvm_vcpu_arch, gprs[19]); - OFFSET(VCPU_R20, kvm_vcpu_arch, gprs[20]); - OFFSET(VCPU_R21, kvm_vcpu_arch, gprs[21]); - OFFSET(VCPU_R22, kvm_vcpu_arch, gprs[22]); - OFFSET(VCPU_R23, kvm_vcpu_arch, gprs[23]); - OFFSET(VCPU_R24, kvm_vcpu_arch, gprs[24]); - OFFSET(VCPU_R25, kvm_vcpu_arch, gprs[25]); - OFFSET(VCPU_R26, kvm_vcpu_arch, gprs[26]); - OFFSET(VCPU_R27, kvm_vcpu_arch, gprs[27]); - OFFSET(VCPU_R28, kvm_vcpu_arch, gprs[28]); - OFFSET(VCPU_R29, kvm_vcpu_arch, gprs[29]); - OFFSET(VCPU_R30, kvm_vcpu_arch, gprs[30]); - OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]); - OFFSET(VCPU_LO, kvm_vcpu_arch, lo); - OFFSET(VCPU_HI, kvm_vcpu_arch, hi); + OFFSET(KVM_VCPU_ARCH_R0, kvm_vcpu_arch, gprs[0]); + OFFSET(KVM_VCPU_ARCH_R1, kvm_vcpu_arch, gprs[1]); + OFFSET(KVM_VCPU_ARCH_R2, kvm_vcpu_arch, gprs[2]); + OFFSET(KVM_VCPU_ARCH_R3, kvm_vcpu_arch, gprs[3]); + OFFSET(KVM_VCPU_ARCH_R4, kvm_vcpu_arch, gprs[4]); + OFFSET(KVM_VCPU_ARCH_R5, kvm_vcpu_arch, gprs[5]); + OFFSET(KVM_VCPU_ARCH_R6, kvm_vcpu_arch, gprs[6]); + OFFSET(KVM_VCPU_ARCH_R7, kvm_vcpu_arch, gprs[7]); + OFFSET(KVM_VCPU_ARCH_R8, kvm_vcpu_arch, gprs[8]); + OFFSET(KVM_VCPU_ARCH_R9, kvm_vcpu_arch, gprs[9]); + OFFSET(KVM_VCPU_ARCH_R10, kvm_vcpu_arch, gprs[10]); + OFFSET(KVM_VCPU_ARCH_R11, kvm_vcpu_arch, gprs[11]); + OFFSET(KVM_VCPU_ARCH_R12, kvm_vcpu_arch, gprs[12]); + OFFSET(KVM_VCPU_ARCH_R13, kvm_vcpu_arch, gprs[13]); + OFFSET(KVM_VCPU_ARCH_R14, kvm_vcpu_arch, gprs[14]); + OFFSET(KVM_VCPU_ARCH_R15, kvm_vcpu_arch, gprs[15]); + OFFSET(KVM_VCPU_ARCH_R16, kvm_vcpu_arch, gprs[16]); + OFFSET(KVM_VCPU_ARCH_R17, kvm_vcpu_arch, gprs[17]); + OFFSET(KVM_VCPU_ARCH_R18, kvm_vcpu_arch, gprs[18]); + OFFSET(KVM_VCPU_ARCH_R19, kvm_vcpu_arch, gprs[19]); + OFFSET(KVM_VCPU_ARCH_R20, kvm_vcpu_arch, gprs[20]); + OFFSET(KVM_VCPU_ARCH_R21, kvm_vcpu_arch, gprs[21]); + OFFSET(KVM_VCPU_ARCH_R22, kvm_vcpu_arch, gprs[22]); + OFFSET(KVM_VCPU_ARCH_R23, kvm_vcpu_arch, gprs[23]); + OFFSET(KVM_VCPU_ARCH_R24, kvm_vcpu_arch, gprs[24]); + OFFSET(KVM_VCPU_ARCH_R25, kvm_vcpu_arch, gprs[25]); + OFFSET(KVM_VCPU_ARCH_R26, kvm_vcpu_arch, gprs[26]); + OFFSET(KVM_VCPU_ARCH_R27, kvm_vcpu_arch, gprs[27]); + OFFSET(KVM_VCPU_ARCH_R28, kvm_vcpu_arch, gprs[28]); + OFFSET(KVM_VCPU_ARCH_R29, kvm_vcpu_arch, gprs[29]); + OFFSET(KVM_VCPU_ARCH_R30, kvm_vcpu_arch, gprs[30]); + OFFSET(KVM_VCPU_ARCH_R31, kvm_vcpu_arch, gprs[31]); + OFFSET(KVM_VCPU_ARCH_LO, kvm_vcpu_arch, lo); + OFFSET(KVM_VCPU_ARCH_HI, kvm_vcpu_arch, hi); OFFSET(KVM_VCPU_ARCH_EPC, kvm_vcpu_arch, epc); OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0); OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid); diff --git a/arch/mips/kvm/kvm_locore.S b/arch/mips/kvm/kvm_locore.S index a434bbe..7a33ee7 100644 --- a/arch/mips/kvm/kvm_locore.S +++ b/arch/mips/kvm/kvm_locore.S @@ -175,52 +175,52 @@ FEXPORT(__kvm_mips_load_asid) mtc0zero, CP0_HWRENA /* Now load up the Guest Context from VCPU */ -LONG_L $1, VCPU_R1(k1) -LONG_L $2, VCPU_R2(k1) -LONG_L $3, VCPU_R3(k1) - -LONG_L $4, VCPU_R4(k1) -LONG_L $5
[PATCH 10/31] mips/kvm: Implement ioctls to get and set FPU registers.
From: David Daney
The current implementation does nothing with them, but future MIPSVZ
work need them. Also add the asm-offsets accessors for the fields.
Signed-off-by: David Daney
---
arch/mips/include/asm/kvm_host.h | 8
arch/mips/kernel/asm-offsets.c | 8
arch/mips/kvm/kvm_mips.c | 26 --
3 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 16013c7..505b804 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -102,6 +102,14 @@ struct kvm_vcpu_arch {
unsigned long lo;
unsigned long epc;
+ /* FPU state */
+ u64 fpr[32];
+ u32 fir;
+ u32 fccr;
+ u32 fexr;
+ u32 fenr;
+ u32 fcsr;
+
void *impl;
};
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 5a9222e..03bf363 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -377,6 +377,14 @@ void output_kvm_defines(void)
OFFSET(KVM_VCPU_ARCH_HI, kvm_vcpu, arch.hi);
OFFSET(KVM_VCPU_ARCH_EPC, kvm_vcpu, arch.epc);
OFFSET(KVM_VCPU_ARCH_IMPL, kvm_vcpu, arch.impl);
+ BLANK();
+ OFFSET(KVM_VCPU_ARCH_FPR, kvm_vcpu, arch.fpr);
+ OFFSET(KVM_VCPU_ARCH_FIR, kvm_vcpu, arch.fir);
+ OFFSET(KVM_VCPU_ARCH_FCCR, kvm_vcpu, arch.fccr);
+ OFFSET(KVM_VCPU_ARCH_FEXR, kvm_vcpu, arch.fexr);
+ OFFSET(KVM_VCPU_ARCH_FENR, kvm_vcpu, arch.fenr);
+ OFFSET(KVM_VCPU_ARCH_FCSR, kvm_vcpu, arch.fcsr);
+ BLANK();
OFFSET(KVM_MIPS_VCPU_TE_HOST_EBASE, kvm_mips_vcpu_te, host_ebase);
OFFSET(KVM_MIPS_VCPU_TE_GUEST_EBASE, kvm_mips_vcpu_te, guest_ebase);
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index 041caad..18c8dc8 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -465,12 +465,34 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
{
- return -ENOIOCTLCMD;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
+ fpu->fpr[i] = vcpu->arch.fpr[i];
+
+ fpu->fir = vcpu->arch.fir;
+ fpu->fccr = vcpu->arch.fccr;
+ fpu->fexr = vcpu->arch.fexr;
+ fpu->fenr = vcpu->arch.fenr;
+ fpu->fcsr = vcpu->arch.fcsr;
+
+ return 0;
}
int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
{
- return -ENOIOCTLCMD;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
+ vcpu->arch.fpr[i] = fpu->fpr[i];
+
+ vcpu->arch.fir = fpu->fir;
+ vcpu->arch.fccr = fpu->fccr;
+ vcpu->arch.fexr = fpu->fexr;
+ vcpu->arch.fenr = fpu->fenr;
+ vcpu->arch.fcsr = fpu->fcsr;
+
+ return 0;
}
int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
--
1.7.11.7
--
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[PATCH 00/31] KVM/MIPS: Implement hardware virtualization via the MIPS-VZ extensions.
From: David Daney These patches take a somewhat different approach to MIPS virtualization via the MIPS-VZ extensions than the patches previously sent by Sanjay Lal. Several facts about the code: o Existing exception handlers are modified to hook in to KVM instead of intercepting all exceptions via the EBase register, and then chaining to real exception handlers. o Able to boot 64-bit SMP guests that use the FPU (I have booted 4-way SMP 64-bit MIPS/Linux). o Additional overhead on every exception even when *no* vCPU is running. o Lower interrupt overhead, than the EBase interception method, when vCPU *is* running. o This code is somewhat smaller than the existing trap/emulate implementation (about 2100 lines vs. about 5300 lines) o Currently probably only usable on the OCTEON III CPU model, as some MIPS-VZ implementation-defined behaviors were assumed to have the OCTEON III behavior. Note: I think Ralf already has the 17/31 (MIPS: Quit exposing Kconfig symbols in uapi headers.) queued, but I also include it here. David Daney (31): MIPS: Move allocate_kscratch to cpu-probe.c and make it public. MIPS: Save and restore K0/K1 when CONFIG_KVM_MIPSVZ mips/kvm: Fix 32-bitisms in kvm_locore.S mips/kvm: Add casts to avoid pointer width mismatch build failures. mips/kvm: Use generic cache flushing functions. mips/kvm: Rename kvm_vcpu_arch.pc to kvm_vcpu_arch.epc mips/kvm: Rename VCPU_registername to KVM_VCPU_ARCH_registername mips/kvm: Fix code formatting in arch/mips/kvm/kvm_locore.S mips/kvm: Factor trap-and-emulate support into a pluggable implementation. mips/kvm: Implement ioctls to get and set FPU registers. MIPS: Rearrange branch.c so it can be used by kvm code. MIPS: Add instruction format information for WAIT, MTC0, MFC0, et al. mips/kvm: Add accessors for MIPS VZ registers. mips/kvm: Add thread_info flag to indicate operation in MIPS VZ Guest Mode. mips/kvm: Exception handling to leave and reenter guest mode. mips/kvm: Add exception handler for MIPSVZ Guest exceptions. MIPS: Quit exposing Kconfig symbols in uapi headers. mips/kvm: Add pt_regs slots for BadInstr and BadInstrP mips/kvm: Add host definitions for MIPS VZ based host. mips/kvm: Hook into TLB fault handlers. mips/kvm: Allow set_except_vector() to be used from MIPSVZ code. mips/kvm: Split get_new_mmu_context into two parts. mips/kvm: Hook into CP unusable exception handler. mips/kvm: Add thread_struct fields used by MIPSVZ hosts. mips/kvm: Add some asm-offsets constants used by MIPSVZ. mips/kvm: Split up Kconfig and Makefile definitions in preperation for MIPSVZ. mips/kvm: Gate the use of kvm_local_flush_tlb_all() by KVM_MIPSTE mips/kvm: Only use KVM_COALESCED_MMIO_PAGE_OFFSET with KVM_MIPSTE mips/kvm: Add MIPSVZ support. mips/kvm: Enable MIPSVZ in Kconfig/Makefile mips/kvm: Allow for upto 8 KVM vcpus per vm. arch/mips/Kconfig |1 + arch/mips/include/asm/branch.h |7 + arch/mips/include/asm/kvm_host.h| 622 +--- arch/mips/include/asm/kvm_mips_te.h | 589 +++ arch/mips/include/asm/kvm_mips_vz.h | 29 + arch/mips/include/asm/mipsregs.h| 264 + arch/mips/include/asm/mmu_context.h | 12 +- arch/mips/include/asm/processor.h |6 + arch/mips/include/asm/ptrace.h | 36 + arch/mips/include/asm/stackframe.h | 150 ++- arch/mips/include/asm/thread_info.h |2 + arch/mips/include/asm/uasm.h|2 +- arch/mips/include/uapi/asm/inst.h | 23 +- arch/mips/include/uapi/asm/ptrace.h | 17 +- arch/mips/kernel/asm-offsets.c | 124 ++- arch/mips/kernel/branch.c | 63 +- arch/mips/kernel/cpu-probe.c| 34 + arch/mips/kernel/genex.S|8 + arch/mips/kernel/scall64-64.S | 12 + arch/mips/kernel/scall64-n32.S | 12 + arch/mips/kernel/traps.c| 15 +- arch/mips/kvm/Kconfig | 23 +- arch/mips/kvm/Makefile | 15 +- arch/mips/kvm/kvm_locore.S | 980 +- arch/mips/kvm/kvm_mips.c| 768 ++ arch/mips/kvm/kvm_mips_comm.h |1 + arch/mips/kvm/kvm_mips_commpage.c |9 +- arch/mips/kvm/kvm_mips_dyntrans.c |4 +- arch/mips/kvm/kvm_mips_emul.c | 312 +++--- arch/mips/kvm/kvm_mips_int.c| 53 +- arch/mips/kvm/kvm_mips_int.h|2 - arch/mips/kvm/kvm_mips_stats.c |6 +- arch/mips/kvm/kvm_mipsvz.c | 1894 +++ arch/mips/kvm/kvm_mipsvz_guest.S| 234 + arch/mips/kvm/kvm_tlb.c | 140 +-- arch/mips/kvm/kvm_trap_emul.c | 932 +++-- arch/mips/mm/fault.c|8 + arch/mips/mm/tlbex-fault.S |6 + arch/mips/mm/tlbex.c| 45 +- 39 files changed, 5299 insertions(+), 2161 deletions(-) create mode 100644 arch/mips/include/asm/kvm_mips_te.h create mode 100644 arch/mips/include
[PATCH 06/31] mips/kvm: Rename kvm_vcpu_arch.pc to kvm_vcpu_arch.epc
From: David Daney
The proper MIPS name for this register is EPC, so use that.
Change the asm-offsets name to KVM_VCPU_ARCH_EPC, so that the symbol
name prefix matches the structure name.
Signed-off-by: David Daney
---
arch/mips/include/asm/kvm_host.h | 2 +-
arch/mips/kernel/asm-offsets.c | 2 +-
arch/mips/kvm/kvm_locore.S | 6 +-
arch/mips/kvm/kvm_mips.c | 12 ++--
arch/mips/kvm/kvm_mips_emul.c| 140 +++
arch/mips/kvm/kvm_mips_int.c | 8 +--
arch/mips/kvm/kvm_trap_emul.c| 20 +++---
7 files changed, 95 insertions(+), 95 deletions(-)
diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h
index 4d6fa0b..d9ee320 100644
--- a/arch/mips/include/asm/kvm_host.h
+++ b/arch/mips/include/asm/kvm_host.h
@@ -363,7 +363,7 @@ struct kvm_vcpu_arch {
unsigned long gprs[32];
unsigned long hi;
unsigned long lo;
- unsigned long pc;
+ unsigned long epc;
/* FPU State */
struct mips_fpu_struct fpu;
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 0845091..22bf8f5 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -385,7 +385,7 @@ void output_kvm_defines(void)
OFFSET(VCPU_R31, kvm_vcpu_arch, gprs[31]);
OFFSET(VCPU_LO, kvm_vcpu_arch, lo);
OFFSET(VCPU_HI, kvm_vcpu_arch, hi);
- OFFSET(VCPU_PC, kvm_vcpu_arch, pc);
+ OFFSET(KVM_VCPU_ARCH_EPC, kvm_vcpu_arch, epc);
OFFSET(VCPU_COP0, kvm_vcpu_arch, cop0);
OFFSET(VCPU_GUEST_KERNEL_ASID, kvm_vcpu_arch, guest_kernel_asid);
OFFSET(VCPU_GUEST_USER_ASID, kvm_vcpu_arch, guest_user_asid);
diff --git a/arch/mips/kvm/kvm_locore.S b/arch/mips/kvm/kvm_locore.S
index e86fa2a..a434bbe 100644
--- a/arch/mips/kvm/kvm_locore.S
+++ b/arch/mips/kvm/kvm_locore.S
@@ -151,7 +151,7 @@ FEXPORT(__kvm_mips_vcpu_run)
/* Set Guest EPC */
- LONG_L t0, VCPU_PC(k1)
+ LONG_L t0, KVM_VCPU_ARCH_EPC(k1)
mtc0t0, CP0_EPC
FEXPORT(__kvm_mips_load_asid)
@@ -330,7 +330,7 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
/* Save Host level EPC, BadVaddr and Cause to VCPU, useful to process the
exception */
mfc0k0,CP0_EPC
-LONG_S k0, VCPU_PC(k1)
+LONG_S k0, KVM_VCPU_ARCH_EPC(k1)
mfc0k0, CP0_BADVADDR
LONG_S k0, VCPU_HOST_CP0_BADVADDR(k1)
@@ -438,7 +438,7 @@ __kvm_mips_return_to_guest:
/* Set Guest EPC */
- LONG_L t0, VCPU_PC(k1)
+ LONG_L t0, KVM_VCPU_ARCH_EPC(k1)
mtc0t0, CP0_EPC
/* Set the ASID for the Guest Kernel */
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index 6018e2a..4ac5ab4 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -583,7 +583,7 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
v = (long)vcpu->arch.lo;
break;
case KVM_REG_MIPS_PC:
- v = (long)vcpu->arch.pc;
+ v = (long)vcpu->arch.epc;
break;
case KVM_REG_MIPS_CP0_INDEX:
@@ -658,7 +658,7 @@ static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
vcpu->arch.lo = v;
break;
case KVM_REG_MIPS_PC:
- vcpu->arch.pc = v;
+ vcpu->arch.epc = v;
break;
case KVM_REG_MIPS_CP0_INDEX:
@@ -890,7 +890,7 @@ int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
return -1;
printk("VCPU Register Dump:\n");
- printk("\tpc = 0x%08lx\n", vcpu->arch.pc);;
+ printk("\tepc = 0x%08lx\n", vcpu->arch.epc);;
printk("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
for (i = 0; i < 32; i += 4) {
@@ -920,7 +920,7 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu,
struct kvm_regs *regs)
vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
vcpu->arch.hi = regs->hi;
vcpu->arch.lo = regs->lo;
- vcpu->arch.pc = regs->pc;
+ vcpu->arch.epc = regs->pc;
return 0;
}
@@ -934,7 +934,7 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu,
struct kvm_regs *regs)
regs->hi = vcpu->arch.hi;
regs->lo = vcpu->arch.lo;
- regs->pc = vcpu->arch.pc;
+ regs->pc = vcpu->arch.epc;
return 0;
}
@@ -1014,7 +1014,7 @@ int kvm_mips_handle_exit(struct kvm_run *run, struct
kvm_vcpu *vcpu)
{
uint32_t cause = vcpu->arch.host_cp0_cause;
uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
- uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
+ uint32_t __user *opc = (uint32_t __user *) vcpu->arch.epc;
unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
enum emulation_res
[PATCH 03/31] mips/kvm: Fix 32-bitisms in kvm_locore.S
From: David Daney For a warning free compile, we need to use the width aware PTR_LI and PTR_LA macros. Use LI variant for immediate data and LA variant for addresses. Signed-off-by: David Daney --- arch/mips/kvm/kvm_locore.S | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/mips/kvm/kvm_locore.S b/arch/mips/kvm/kvm_locore.S index dca2aa6..e86fa2a 100644 --- a/arch/mips/kvm/kvm_locore.S +++ b/arch/mips/kvm/kvm_locore.S @@ -310,7 +310,7 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra) LONG_S t0, VCPU_R26(k1) /* Get GUEST k1 and save it in VCPU */ -la t1, ~0x2ff + PTR_LI t1, ~0x2ff mfc0t0, CP0_EBASE and t0, t0, t1 LONG_L t0, 0x3000(t0) @@ -384,14 +384,14 @@ NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra) mtc0k0, CP0_DDATA_LO /* Restore RDHWR access */ -la k0, 0x200F + PTR_LI k0, 0x200F mtc0k0, CP0_HWRENA /* Jump to handler */ FEXPORT(__kvm_mips_jump_to_handler) /* XXXKYMA: not sure if this is safe, how large is the stack?? */ /* Now jump to the kvm_mips_handle_exit() to see if we can deal with this in the kernel */ -la t9,kvm_mips_handle_exit + PTR_LA t9, kvm_mips_handle_exit jalr.hb t9 addiu sp,sp, -CALLFRAME_SIZ /* BD Slot */ @@ -566,7 +566,7 @@ __kvm_mips_return_to_host: mtlok0 /* Restore RDHWR access */ -la k0, 0x200F + PTR_LI k0, 0x200F mtc0k0, CP0_HWRENA -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 00/31] KVM/MIPS: Implement hardware virtualization via the MIPS-VZ extensions.
I should also add that I will shortly send patches for the kvm tool required to drive this VM as well as a small set of patches that create a para-virtualized MIPS/Linux guest kernel. The idea is that because there is no standard SMP linux system, we create a standard para-virtualized system that uses a handful of hypercalls, but mostly just uses virtio devices. It has no emulated real hardware (no 8250 UART, no emulated legacy anything...) David Daney On 06/07/2013 04:03 PM, David Daney wrote: From: David Daney These patches take a somewhat different approach to MIPS virtualization via the MIPS-VZ extensions than the patches previously sent by Sanjay Lal. Several facts about the code: o Existing exception handlers are modified to hook in to KVM instead of intercepting all exceptions via the EBase register, and then chaining to real exception handlers. o Able to boot 64-bit SMP guests that use the FPU (I have booted 4-way SMP 64-bit MIPS/Linux). o Additional overhead on every exception even when *no* vCPU is running. o Lower interrupt overhead, than the EBase interception method, when vCPU *is* running. o This code is somewhat smaller than the existing trap/emulate implementation (about 2100 lines vs. about 5300 lines) o Currently probably only usable on the OCTEON III CPU model, as some MIPS-VZ implementation-defined behaviors were assumed to have the OCTEON III behavior. Note: I think Ralf already has the 17/31 (MIPS: Quit exposing Kconfig symbols in uapi headers.) queued, but I also include it here. David Daney (31): MIPS: Move allocate_kscratch to cpu-probe.c and make it public. MIPS: Save and restore K0/K1 when CONFIG_KVM_MIPSVZ mips/kvm: Fix 32-bitisms in kvm_locore.S mips/kvm: Add casts to avoid pointer width mismatch build failures. mips/kvm: Use generic cache flushing functions. mips/kvm: Rename kvm_vcpu_arch.pc to kvm_vcpu_arch.epc mips/kvm: Rename VCPU_registername to KVM_VCPU_ARCH_registername mips/kvm: Fix code formatting in arch/mips/kvm/kvm_locore.S mips/kvm: Factor trap-and-emulate support into a pluggable implementation. mips/kvm: Implement ioctls to get and set FPU registers. MIPS: Rearrange branch.c so it can be used by kvm code. MIPS: Add instruction format information for WAIT, MTC0, MFC0, et al. mips/kvm: Add accessors for MIPS VZ registers. mips/kvm: Add thread_info flag to indicate operation in MIPS VZ Guest Mode. mips/kvm: Exception handling to leave and reenter guest mode. mips/kvm: Add exception handler for MIPSVZ Guest exceptions. MIPS: Quit exposing Kconfig symbols in uapi headers. mips/kvm: Add pt_regs slots for BadInstr and BadInstrP mips/kvm: Add host definitions for MIPS VZ based host. mips/kvm: Hook into TLB fault handlers. mips/kvm: Allow set_except_vector() to be used from MIPSVZ code. mips/kvm: Split get_new_mmu_context into two parts. mips/kvm: Hook into CP unusable exception handler. mips/kvm: Add thread_struct fields used by MIPSVZ hosts. mips/kvm: Add some asm-offsets constants used by MIPSVZ. mips/kvm: Split up Kconfig and Makefile definitions in preperation for MIPSVZ. mips/kvm: Gate the use of kvm_local_flush_tlb_all() by KVM_MIPSTE mips/kvm: Only use KVM_COALESCED_MMIO_PAGE_OFFSET with KVM_MIPSTE mips/kvm: Add MIPSVZ support. mips/kvm: Enable MIPSVZ in Kconfig/Makefile mips/kvm: Allow for upto 8 KVM vcpus per vm. arch/mips/Kconfig |1 + arch/mips/include/asm/branch.h |7 + arch/mips/include/asm/kvm_host.h| 622 +--- arch/mips/include/asm/kvm_mips_te.h | 589 +++ arch/mips/include/asm/kvm_mips_vz.h | 29 + arch/mips/include/asm/mipsregs.h| 264 + arch/mips/include/asm/mmu_context.h | 12 +- arch/mips/include/asm/processor.h |6 + arch/mips/include/asm/ptrace.h | 36 + arch/mips/include/asm/stackframe.h | 150 ++- arch/mips/include/asm/thread_info.h |2 + arch/mips/include/asm/uasm.h|2 +- arch/mips/include/uapi/asm/inst.h | 23 +- arch/mips/include/uapi/asm/ptrace.h | 17 +- arch/mips/kernel/asm-offsets.c | 124 ++- arch/mips/kernel/branch.c | 63 +- arch/mips/kernel/cpu-probe.c| 34 + arch/mips/kernel/genex.S|8 + arch/mips/kernel/scall64-64.S | 12 + arch/mips/kernel/scall64-n32.S | 12 + arch/mips/kernel/traps.c| 15 +- arch/mips/kvm/Kconfig | 23 +- arch/mips/kvm/Makefile | 15 +- arch/mips/kvm/kvm_locore.S | 980 +- arch/mips/kvm/kvm_mips.c| 768 ++ arch/mips/kvm/kvm_mips_comm.h |1 + arch/mips/kvm/kvm_mips_commpage.c |9 +- arch/mips/kvm/kvm_mips_dyntrans.c |4 +- arch/mips/kvm/kvm_mips_emul.c | 312 +++--- arch/mips/kvm/kvm_mips_int.c| 53 +- arch/mips/kvm/kvm_mips_int.h
[PATCH 02/31] MIPS: Save and restore K0/K1 when CONFIG_KVM_MIPSVZ
From: David Daney
We cannot clobber any registers on exceptions as any guest will need
them all.
Signed-off-by: David Daney
---
arch/mips/include/asm/mipsregs.h | 2 ++
arch/mips/include/asm/stackframe.h | 15 +++
arch/mips/kernel/cpu-probe.c | 7 ++-
arch/mips/kernel/genex.S | 5 +
arch/mips/kernel/scall64-64.S | 12
arch/mips/kernel/scall64-n32.S | 12
arch/mips/kernel/traps.c | 5 +
arch/mips/mm/tlbex.c | 25 +
8 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 6e0da5aa..6f03c72 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -73,6 +73,8 @@
#define CP0_TAGHI $29
#define CP0_ERROREPC $30
#define CP0_DESAVE $31
+#define CP0_KSCRATCH1 $31, 2
+#define CP0_KSCRATCH2 $31, 3
/*
* R4640/R4650 cp0 register names. These registers are listed
diff --git a/arch/mips/include/asm/stackframe.h
b/arch/mips/include/asm/stackframe.h
index a89d1b1..20627b2 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -181,6 +181,16 @@
#endif
LONG_S k0, PT_R29(sp)
LONG_S $3, PT_R3(sp)
+#ifdef CONFIG_KVM_MIPSVZ
+ /*
+* With KVM_MIPSVZ, we must not clobber k0/k1
+* they were saved before they were used
+*/
+ MFC0k0, CP0_KSCRATCH1
+ MFC0$3, CP0_KSCRATCH2
+ LONG_S k0, PT_R26(sp)
+ LONG_S $3, PT_R27(sp)
+#endif
/*
* You might think that you don't need to save $0,
* but the FPU emulator and gdb remote debug stub
@@ -447,6 +457,11 @@
.endm
.macro RESTORE_SP_AND_RET
+
+#ifdef CONFIG_KVM_MIPSVZ
+ LONG_L k0, PT_R26(sp)
+ LONG_L k1, PT_R27(sp)
+#endif
LONG_L sp, PT_R29(sp)
.setmips3
eret
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ee1014e..7a07edb 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1067,7 +1067,12 @@ __cpuinit void cpu_report(void)
static DEFINE_SPINLOCK(kscratch_used_lock);
-static unsigned int kscratch_used_mask;
+static unsigned int kscratch_used_mask
+#ifdef CONFIG_KVM_MIPSVZ
+/* KVM_MIPSVZ implemtation uses these two statically. */
+= 0xc
+#endif
+;
int allocate_kscratch(void)
{
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 31fa856..163e299 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -46,6 +46,11 @@
NESTED(except_vec3_generic, 0, sp)
.setpush
.setnoat
+#ifdef CONFIG_KVM_MIPSVZ
+ /* With KVM_MIPSVZ, we must not clobber k0/k1 */
+ MTC0k0, CP0_KSCRATCH1
+ MTC0k1, CP0_KSCRATCH2
+#endif
#if R5432_CP0_INTERRUPT_WAR
mfc0k0, CP0_INDEX
#endif
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 97a5909..5ff4882 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -62,6 +62,9 @@ NESTED(handle_sys64, PT_SIZE, sp)
jalrt2 # Do The Real Thing (TM)
li t0, -EMAXERRNO - 1 # error?
+#if defined(CONFIG_KVM_MIPSVZ) && defined(CONFIG_FAST_ACCESS_TO_THREAD_POINTER)
+ ld t2, TI_TP_VALUE($28)
+#endif
sltut0, t0, v0
sd t0, PT_R7(sp) # set error flag
beqzt0, 1f
@@ -70,6 +73,9 @@ NESTED(handle_sys64, PT_SIZE, sp)
dnegu v0 # error
sd t1, PT_R0(sp) # save it for syscall restarting
1: sd v0, PT_R2(sp) # result
+#if defined(CONFIG_KVM_MIPSVZ) && defined(CONFIG_FAST_ACCESS_TO_THREAD_POINTER)
+ sd t2, PT_R26(sp)
+#endif
n64_syscall_exit:
j syscall_exit_partial
@@ -93,6 +99,9 @@ syscall_trace_entry:
jalrt0
li t0, -EMAXERRNO - 1 # error?
+#if defined(CONFIG_KVM_MIPSVZ) && defined(CONFIG_FAST_ACCESS_TO_THREAD_POINTER)
+ ld t2, TI_TP_VALUE($28)
+#endif
sltut0, t0, v0
sd t0, PT_R7(sp) # set error flag
beqzt0, 1f
@@ -101,6 +110,9 @@ syscall_trace_entry:
dnegu v0 # error
sd t1, PT_R0(sp) # save it for syscall restarting
1: sd v0, PT_R2(sp) # result
+#if defined(CONFIG_KVM_MIPSVZ) && defined(CONFIG_FAST_ACCESS_TO_THREAD_POINTER)
+ sd t2, PT_R26(sp)
+#endif
j syscall_exit
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index edcb659..cba35b4 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/s
[PATCH 04/31] mips/kvm: Add casts to avoid pointer width mismatch build failures.
From: David Daney
When building for 64-bits we need these cases to make it build.
Signed-off-by: David Daney
---
arch/mips/kvm/kvm_mips.c | 4 ++--
arch/mips/kvm/kvm_mips_dyntrans.c | 4 ++--
arch/mips/kvm/kvm_mips_emul.c | 2 +-
arch/mips/kvm/kvm_tlb.c | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index d934b01..6018e2a 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -303,7 +303,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
unsigned int id)
}
/* Save Linux EBASE */
- vcpu->arch.host_ebase = (void *)read_c0_ebase();
+ vcpu->arch.host_ebase = (void *)(long)(read_c0_ebase() & 0x3ff);
gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
@@ -339,7 +339,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
unsigned int id)
offset = 0x2000;
kvm_info("Installing KVM Exception handlers @ %p, %#x bytes\n",
gebase + offset,
-mips32_GuestExceptionEnd - mips32_GuestException);
+(unsigned)(mips32_GuestExceptionEnd - mips32_GuestException));
memcpy(gebase + offset, mips32_GuestException,
mips32_GuestExceptionEnd - mips32_GuestException);
diff --git a/arch/mips/kvm/kvm_mips_dyntrans.c
b/arch/mips/kvm/kvm_mips_dyntrans.c
index 96528e2..dd0b8f9 100644
--- a/arch/mips/kvm/kvm_mips_dyntrans.c
+++ b/arch/mips/kvm/kvm_mips_dyntrans.c
@@ -94,7 +94,7 @@ kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc, struct
kvm_vcpu *vcpu)
cop0);
}
- if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
+ if (KVM_GUEST_KSEGX((unsigned long)opc) == KVM_GUEST_KSEG0) {
kseg0_opc =
CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
(vcpu, (unsigned long) opc));
@@ -129,7 +129,7 @@ kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc, struct
kvm_vcpu *vcpu)
offsetof(struct mips_coproc,
reg[rd][sel]) + offsetof(struct kvm_mips_commpage, cop0);
- if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
+ if (KVM_GUEST_KSEGX((unsigned long)opc) == KVM_GUEST_KSEG0) {
kseg0_opc =
CKSEG0ADDR(kvm_mips_translate_guest_kseg0_to_hpa
(vcpu, (unsigned long) opc));
diff --git a/arch/mips/kvm/kvm_mips_emul.c b/arch/mips/kvm/kvm_mips_emul.c
index 4b6274b..af9a661 100644
--- a/arch/mips/kvm/kvm_mips_emul.c
+++ b/arch/mips/kvm/kvm_mips_emul.c
@@ -892,7 +892,7 @@ int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu
*vcpu)
pfn = kvm->arch.guest_pmap[gfn];
pa = (pfn << PAGE_SHIFT) | offset;
- printk("%s: va: %#lx, unmapped: %#x\n", __func__, va, CKSEG0ADDR(pa));
+ printk("%s: va: %#lx, unmapped: %#lx\n", __func__, va, CKSEG0ADDR(pa));
mips32_SyncICache(CKSEG0ADDR(pa), 32);
return 0;
diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c
index c777dd3..5e189be 100644
--- a/arch/mips/kvm/kvm_tlb.c
+++ b/arch/mips/kvm/kvm_tlb.c
@@ -353,7 +353,7 @@ int kvm_mips_handle_commpage_tlb_fault(unsigned long
badvaddr,
unsigned long entrylo0 = 0, entrylo1 = 0;
- pfn0 = CPHYSADDR(vcpu->arch.kseg0_commpage) >> PAGE_SHIFT;
+ pfn0 = CPHYSADDR((unsigned long)vcpu->arch.kseg0_commpage) >>
PAGE_SHIFT;
pfn1 = 0;
entrylo0 = mips3_paddr_to_tlbpfn(pfn0 << PAGE_SHIFT) | (0x3 << 3) | (1
<< 2) |
(0x1 << 1);
@@ -916,7 +916,7 @@ uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu)
inst = *(opc);
}
local_irq_restore(flags);
- } else if (KVM_GUEST_KSEGX(opc) == KVM_GUEST_KSEG0) {
+ } else if (KVM_GUEST_KSEGX((unsigned long)opc) == KVM_GUEST_KSEG0) {
paddr =
kvm_mips_translate_guest_kseg0_to_hpa(vcpu,
(unsigned long) opc);
--
1.7.11.7
--
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[PATCH 05/31] mips/kvm: Use generic cache flushing functions.
From: David Daney
We don't know if we have the r4k specific functions available, so use
universally available __flush_cache_all() instead. This takes longer
as it flushes both i-cache and d-cache, but is available for all CPUs.
Signed-off-by: David Daney
---
arch/mips/kvm/kvm_mips_emul.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/mips/kvm/kvm_mips_emul.c b/arch/mips/kvm/kvm_mips_emul.c
index af9a661..a2c6687 100644
--- a/arch/mips/kvm/kvm_mips_emul.c
+++ b/arch/mips/kvm/kvm_mips_emul.c
@@ -916,8 +916,6 @@ kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
uint32_t cause,
struct kvm_run *run, struct kvm_vcpu *vcpu)
{
struct mips_coproc *cop0 = vcpu->arch.cop0;
- extern void (*r4k_blast_dcache) (void);
- extern void (*r4k_blast_icache) (void);
enum emulation_result er = EMULATE_DONE;
int32_t offset, cache, op_inst, op, base;
struct kvm_vcpu_arch *arch = &vcpu->arch;
@@ -954,9 +952,9 @@ kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
uint32_t cause,
arch->gprs[base], offset);
if (cache == MIPS_CACHE_DCACHE)
- r4k_blast_dcache();
+ __flush_cache_all();
else if (cache == MIPS_CACHE_ICACHE)
- r4k_blast_icache();
+ __flush_cache_all();
else {
printk("%s: unsupported CACHE INDEX operation\n",
__func__);
--
1.7.11.7
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 20/31] mips/kvm: Hook into TLB fault handlers.
On 06/07/2013 04:34 PM, Sergei Shtylyov wrote:
Hello.
On 06/08/2013 03:03 AM, David Daney wrote:
From: David Daney
If the CPU is operating in guest mode when a TLB related excpetion
occurs, give KVM a chance to do emulation.
Signed-off-by: David Daney
---
arch/mips/mm/fault.c | 8
arch/mips/mm/tlbex-fault.S | 6 ++
2 files changed, 14 insertions(+)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 0fead53..9391da49 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
[...]
@@ -50,6 +51,13 @@ asmlinkage void __kprobes do_page_fault(struct
pt_regs *regs, unsigned long writ
field, regs->cp0_epc);
#endif
+#ifdef CONFIG_KVM_MIPSVZ
+if (test_tsk_thread_flag(current, TIF_GUESTMODE)) {
+if (mipsvz_page_fault(regs, write, address))
Any reason not to collapse these into single *if*?
It makes the conditional call to mipsvz_page_fault() less obvious.
Certainly the same semantics can be achieved several different ways.
David Daney
+return;
+}
+#endif
+
--
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