Re: [v11,3/3] Bluetooth: hci_uart: Support firmware download for Marvell
On 2016年05月06日 23:31, Amitkumar Karwar wrote: From: Ganapathi Bhat This patch implement firmware download feature for Marvell Bluetooth devices. If firmware is already downloaded, it will skip downloading. Signed-off-by: Ganapathi Bhat Signed-off-by: Amitkumar Karwar Tested-by: Caesar Wang Tested on chromeos4.4. so you can free add my test tag: I don't find the cover-letter, so add it in here. Cc: linux-rockc...@lists.infradead.org, that's interesting in this series patches. --- v2: Fixed compilation warning reported by kbuild test robot v3: Addressed review comments from Marcel Holtmann a) Removed vendor specific code from hci_ldisc.c b) Get rid of static forward declaration c) Removed unnecessary heavy nesting d) Git rid of module parameter and global variables e) Add logic to pick right firmware image v4: Addresses review comments from Alan a) Use existing kernel helper APIs instead of writing own. b) Replace mdelay() with msleep() v5: Addresses review comments from Loic Poulain a) Use bt_dev_err/warn/dbg helpers insted of BT_ERR/WARN/DBG b) Used static functions where required and removed forward delcarations c) Edited comments for the function hci_uart_recv_data d) Made HCI_UART_DNLD_FW flag a part of driver private data v6: Addresses review comments from Loic Poulain a) Used skb instead of array to store firmware data during download b) Used hci_uart_tx_wakeup and enqueued packets instead of tty write c) Used GFP_KERNEL instead of GFP_ATOMIC v7: Edited Kconfig to add dependency for BT_HCIUART_H4. The change resolves errors reported by kbuild test robot. v8: Addressed review comments from Marcel Holtmann a) Removed unnecessary memory allocation failure messages b) Get rid of btmrvl.h header file and add definitions in hci_mrvl.c file v9: Addressed review comments from Marcel Holtmann a) Moved firmware download code from setup to prepare handler. b) Change messages from bt_dev_*->BT_*, as hdev isn't available during firmware download. v10: Addressed review comments from Marcel Holtmann a) Added new callback recv_for_prepare to receive data from device during prepare phase b) Avoided using private flags (HCI_UART_DNLD_FW) as new receive callback is added for the same purpose c) Used kernel API to handle unaligned data d) Moved mrvl_set_baud functionality inside setup callback v11: Write data through ldisc in mrvl_send_ack() instead of directly calling write method(One Thousand Gnomes). --- drivers/bluetooth/Kconfig | 11 + drivers/bluetooth/Makefile| 1 + drivers/bluetooth/hci_ldisc.c | 6 + drivers/bluetooth/hci_mrvl.c | 543 ++ drivers/bluetooth/hci_uart.h | 8 +- 5 files changed, 568 insertions(+), 1 deletion(-) create mode 100644 drivers/bluetooth/hci_mrvl.c diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig index cf50fd2..daafd0c 100644 --- a/drivers/bluetooth/Kconfig +++ b/drivers/bluetooth/Kconfig @@ -180,6 +180,17 @@ config BT_HCIUART_AG6XX Say Y here to compile support for Intel AG6XX protocol. +config BT_HCIUART_MRVL + bool "Marvell protocol support" + depends on BT_HCIUART + select BT_HCIUART_H4 + help + Marvell is serial protocol for communication between Bluetooth + device and host. This protocol is required for most Marvell Bluetooth + devices with UART interface. + + Say Y here to compile support for HCI MRVL protocol. + config BT_HCIBCM203X tristate "HCI BCM203x USB driver" depends on USB diff --git a/drivers/bluetooth/Makefile b/drivers/bluetooth/Makefile index 9c18939..364dbb6 100644 --- a/drivers/bluetooth/Makefile +++ b/drivers/bluetooth/Makefile @@ -37,6 +37,7 @@ hci_uart-$(CONFIG_BT_HCIUART_INTEL) += hci_intel.o hci_uart-$(CONFIG_BT_HCIUART_BCM) += hci_bcm.o hci_uart-$(CONFIG_BT_HCIUART_QCA) += hci_qca.o hci_uart-$(CONFIG_BT_HCIUART_AG6XX) += hci_ag6xx.o +hci_uart-$(CONFIG_BT_HCIUART_MRVL) += hci_mrvl.o hci_uart-objs := $(hci_uart-y) ccflags-y += -D__CHECK_ENDIAN__ diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c index 047e786..4896b6f 100644 --- a/drivers/bluetooth/hci_ldisc.c +++ b/drivers/bluetooth/hci_ldisc.c @@ -821,6 +821,9 @@ static int __init hci_uart_init(void) #ifdef CONFIG_BT_HCIUART_AG6XX ag6xx_init(); #endif +#ifdef CONFIG_BT_HCIUART_MRVL + mrvl_init(); +#endif return 0; } @@ -856,6 +859,9 @@ static void __exit hci_uart_exit(void) #ifdef CONFIG_BT_HCIUART_AG6XX ag6xx_deinit(); #endif +#ifdef CONFIG_BT_HCIUART_MRVL + mrvl_deinit(); +#endif /* Release tty registration of line discipline */ err = tty_unregister_ldisc(N_HCI); diff --git a/drivers/bluetooth/hci_mrvl.c b/driv
[PATCH 2/2] thermal: rockchip: optimize sensor auto accessing period
From: Rocky Hao
In less than 10 ms, the temperature of soc will arise 10 degree. 250 ms
is too big for soc tempeture control. Setting 2.5 ms will speed up
temperature accessing speed but introduce no more cpu's computing overhead.
We set AUTO_PERIOD_TIME and TSADCV3_AUTO_PERIOD_HT_TIME the same value,
because normal temperature update speed is also our consern in IPA.
Signed-off-by: Rocky Hao
Signed-off-by: Caesar Wang
Cc: Zhang Rui
Cc: Eduardo Valentin
Cc: Heiko Stuebner
Cc: linux...@vger.kernel.org
---
drivers/thermal/rockchip_thermal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index a90423d..1f165c9 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -213,8 +213,8 @@ struct rockchip_thermal_data {
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
#define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
#define TSADCV2_AUTO_PERIOD_HT_TIME50 /* 50ms */
-#define TSADCV3_AUTO_PERIOD_TIME 187500 /* 250ms */
-#define TSADCV3_AUTO_PERIOD_HT_TIME37500 /* 50ms */
+#define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
+#define TSADCV3_AUTO_PERIOD_HT_TIME1875 /* 2.5ms */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
--
1.9.1
[PATCH 1/2] thermal: rockchip: enhance the tsadc's bandgap feature for rk3399
From: Rocky Hao
Due to the voltage ripple, the sensing data of the tsadc is not accurate.
And in this patch, the bandgap feature is enhanced to remove the voltage
ripple, and then the tsadc can sense the temperature more precisely.
Obsolete codes are removed as well.
Signed-off-by: Rocky Hao
Signed-off-by: Caesar Wang
Cc: Eduardo Valentin
Cc: Zhang Rui
Cc: Heiko Stuebner
Cc: linux...@vger.kernel.org
---
drivers/thermal/rockchip_thermal.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index db5ecc5..a90423d 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -222,10 +222,10 @@ struct rockchip_thermal_data {
#define GRF_TSADC_TESTBIT_L0x0e648
#define GRF_TSADC_TESTBIT_H0x0e64c
-#define GRF_TSADC_TSEN_PD_ON (0x30003 << 0)
-#define GRF_TSADC_TSEN_PD_OFF (0x3 << 0)
#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
+#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
+#define GRF_TSADC_VCM_EN_H (0x10001 << 7)
/**
* struct tsadc_table - code to temperature conversion table
@@ -567,9 +567,10 @@ static void rk_tsadcv3_initialize(struct regmap *grf, void
__iomem *regs,
regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
} else {
- regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_ON);
- mdelay(10);
- regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_TSEN_PD_OFF);
+ /* Enable the voltage common mode feature */
+ regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
+ regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
+
usleep_range(15, 100); /* The spec note says at least 15 us */
regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
--
1.9.1
[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc: linux-...@vger.kernel.org
Cc: linux-rockc...@lists.infradead.org
Tested-by: Guenter Roeck
---
Changes in v3:
- %s/devm_reset_control_get_optional()/devm_reset_control_get()
- add Guente's test tag.
Changes in v2:
- Make the reset as an optional property, since it should work
with old devicetrees as well.
.../bindings/iio/adc/rockchip-saradc.txt | 7 +
drivers/iio/adc/Kconfig| 1 +
drivers/iio/adc/rockchip_saradc.c | 30 ++
3 files changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
index bf99e2f..205593f 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -16,6 +16,11 @@ Required properties:
- vref-supply: The regulator supply ADC reference voltage.
- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+ this option. See ../reset/reset.txt for details.
+- reset-names: Must include the name "saradc-apb".
+
Example:
saradc: saradc@2006c000 {
compatible = "rockchip,saradc";
@@ -23,6 +28,8 @@ Example:
interrupts = ;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
#io-channel-cells = <1>;
vref-supply = <&vcc18>;
};
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..7675772 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
config ROCKCHIP_SARADC
tristate "Rockchip SARADC driver"
depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
+ depends on RESET_CONTROLLER
help
Say yes here to build support for the SARADC found in SoCs from
Rockchip.
diff --git a/drivers/iio/adc/rockchip_saradc.c
b/drivers/iio/adc/rockchip_saradc.c
index f9ad6c2..85d7012 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -53,6 +55,7 @@ struct rockchip_saradc {
struct clk *clk;
struct completion completion;
struct regulator*vref;
+ struct reset_control*reset;
const struct rockchip_saradc_data *data;
u16 last_val;
};
@@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] =
{
};
MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
+/**
+ * Reset SARADC Controller.
+ */
+static void rockchip_saradc_reset_controller(struct reset_control *reset)
+{
+ reset_control_assert(reset);
+ usleep_range(10, 20);
+ reset_control_deassert(reset);
+}
+
static int rockchip_saradc_probe(struct platform_device *pdev)
{
struct rockchip_saradc *info = NULL;
@@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device
*pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
+ /*
+* The reset should be an optional property, as it should work
+* with old devicetrees as well
+*/
+ info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ if (ret != -ENOENT)
+ return ret;
+
+ dev_dbg(&pdev->dev, "no reset control found\n");
+ info->reset = NULL;
+ }
+
init_completion(&info->completion);
irq = platform_get_irq(pdev, 0);
@@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device
*pdev)
return PTR_ERR(info->vref);
}
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
/*
* Use a default value for the converter clock.
* This may become user-configurable in the future.
--
1.9.1
[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang --- Changes in v3: None Changes in v2: None arch/arm/boot/dts/rk3066a.dtsi | 2 ++ arch/arm/boot/dts/rk3288.dtsi | 2 ++ arch/arm/boot/dts/rk3xxx.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index c0ba86c..0d0dae3 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -197,6 +197,8 @@ clock-names = "saradc", "apb_pclk"; interrupts = ; #io-channel-cells = <1>; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd33f01..91c4b3c 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -279,6 +279,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 99bbcc2..e2cd683 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -399,6 +399,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; -- 1.9.1
[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang --- Changes in v3: - add Doug's reviewed tag. Changes in v2: None arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index d02a9003..4f44d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -270,6 +270,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; -- 1.9.1
[PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399
This patch adds saradc needed information on rk3399 SoCs.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4c84229..b81f84b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -299,6 +299,18 @@
};
};
+ saradc: saradc@ff10 {
+ compatible = "rockchip,rk3399-saradc";
+ reg = <0x0 0xff10 0x0 0x100>;
+ interrupts = ;
+ #io-channel-cells = <1>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
i2c1: i2c@ff11 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff11 0x0 0x1000>;
--
1.9.1
Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it
On 2016年07月30日 05:28, Rob Herring wrote: On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote: SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang Cc: Jonathan Cameron Cc: Heiko Stuebner Cc: Rob Herring Cc: linux-...@vger.kernel.org Cc: linux-rockc...@lists.infradead.org Tested-by: Guenter Roeck --- Changes in v3: - %s/devm_reset_control_get_optional()/devm_reset_control_get() - add Guente's test tag. Changes in v2: - Make the reset as an optional property, since it should work with old devicetrees as well. .../bindings/iio/adc/rockchip-saradc.txt | 7 + drivers/iio/adc/Kconfig| 1 + drivers/iio/adc/rockchip_saradc.c | 30 ++ 3 files changed, 38 insertions(+) Please add acks when posting new versions. I didn't get your ACK when posting the V3. :-P --- Your ack on 2016-07-27 23:12 .../bindings/iio/adc/rockchip-saradc.txt | 7 + Acked-by: Rob Herring Rob ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- caesar wang | software engineer | w...@rock-chip.com
Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it
On 2016年07月30日 05:28, Rob Herring wrote: On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote: SARADC controller needs to be reset before programming it, otherwise it will not function properly. Signed-off-by: Caesar Wang Cc: Jonathan Cameron Cc: Heiko Stuebner Cc: Rob Herring Cc: linux-...@vger.kernel.org Cc: linux-rockc...@lists.infradead.org Tested-by: Guenter Roeck --- Changes in v3: - %s/devm_reset_control_get_optional()/devm_reset_control_get() - add Guente's test tag. Changes in v2: - Make the reset as an optional property, since it should work with old devicetrees as well. .../bindings/iio/adc/rockchip-saradc.txt | 7 + drivers/iio/adc/Kconfig| 1 + drivers/iio/adc/rockchip_saradc.c | 30 ++ 3 files changed, 38 insertions(+) Please add acks when posting new versions. I didn't get your ACK when posting the V3. :-P --- Your ack on 2016-07-27 23:12 .../bindings/iio/adc/rockchip-saradc.txt | 7 + Acked-by: Rob Herring Rob ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it
On 2016年07月27日 22:47, Peter Meerwald-Stadler wrote:
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
nitpicking on wording below
Signed-off-by: Caesar Wang
Cc: Jonathan Cameron
Cc: Heiko Stuebner
Cc: Rob Herring
Cc: linux-...@vger.kernel.org
Cc: linux-rockc...@lists.infradead.org
Tested-by: Guenter Roeck
---
Changes in v3:
- %s/devm_reset_control_get_optional()/devm_reset_control_get()
- add Guente's test tag.
Changes in v2:
- Make the reset as an optional property, since it should work
with old devicetrees as well.
.../bindings/iio/adc/rockchip-saradc.txt | 7 +
drivers/iio/adc/Kconfig| 1 +
drivers/iio/adc/rockchip_saradc.c | 30 ++
3 files changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
index bf99e2f..205593f 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -16,6 +16,11 @@ Required properties:
- vref-supply: The regulator supply ADC reference voltage.
- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+ this option. See ../reset/reset.txt for details.
'... if need support this option.' doesn't sound right, maybe
simply: '... if needed.' or drop this clause.
I don't plan to resend this series patches.
I'm assuming that Jonathan will help me fix it when ready to apply it.:-)
Glad to resend this series patches if Jonathan boss ask me to do.
Thanks,
Caesar
+- reset-names: Must include the name "saradc-apb".
+
Example:
saradc: saradc@2006c000 {
compatible = "rockchip,saradc";
@@ -23,6 +28,8 @@ Example:
interrupts = ;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC>;
+ reset-names = "saradc-apb";
#io-channel-cells = <1>;
vref-supply = <&vcc18>;
};
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..7675772 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
config ROCKCHIP_SARADC
tristate "Rockchip SARADC driver"
depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
+ depends on RESET_CONTROLLER
help
Say yes here to build support for the SARADC found in SoCs from
Rockchip.
diff --git a/drivers/iio/adc/rockchip_saradc.c
b/drivers/iio/adc/rockchip_saradc.c
index f9ad6c2..85d7012 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -21,6 +21,8 @@
#include
#include
#include
+#include
+#include
#include
#include
@@ -53,6 +55,7 @@ struct rockchip_saradc {
struct clk *clk;
struct completion completion;
struct regulator*vref;
+ struct reset_control*reset;
const struct rockchip_saradc_data *data;
u16 last_val;
};
@@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] =
{
};
MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
+/**
+ * Reset SARADC Controller.
+ */
+static void rockchip_saradc_reset_controller(struct reset_control *reset)
+{
+ reset_control_assert(reset);
+ usleep_range(10, 20);
+ reset_control_deassert(reset);
+}
+
static int rockchip_saradc_probe(struct platform_device *pdev)
{
struct rockchip_saradc *info = NULL;
@@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device
*pdev)
if (IS_ERR(info->regs))
return PTR_ERR(info->regs);
+ /*
+* The reset should be an optional property, as it should work
+* with old devicetrees as well
+*/
+ info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ if (ret != -ENOENT)
+ return ret;
+
+ dev_dbg(&pdev->dev, "no reset control found\n");
+ info->reset = NULL;
+ }
+
init_completion(&info->completion);
irq = platform_get_irq(pdev, 0);
@@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device
*pdev)
return PTR_ERR(info->vref);
}
+ if (info->reset)
+ rockchip_saradc_reset_controller(info->reset);
+
/*
* Use a default value for the converter clock.
* This may become user-configurable in the future.
--
caesar wang | software engineer | w...@rock-chip.com
[RESEND PATCH 0/4] Support the rk3399 gmac pd function
This patch add to handle the gmac pd issue, and support the rk3399 gmac for devicetree. Caesar Wang (2): arm64: dts: rockchip: support gmac for rk3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board David Wu (1): net: stmmac: dwmac-rk: add pd_gmac support for rk3399 Roger Chen (1): net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off arch/arm64/boot/dts/rockchip/rk3399-evb.dts| 31 + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 90 ++ drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 28 +--- 3 files changed, 140 insertions(+), 9 deletions(-) -- 1.9.1
[RESEND PATCH 2/4] net: stmmac: dwmac-rk: add pd_gmac support for rk3399
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 289e7a6..406573d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "stmmac_platform.h"
@@ -659,11 +660,19 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
if (ret)
return ret;
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
return 0;
}
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
{
+ struct device *dev = &gmac->pdev->dev;
+
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
phy_power_on(gmac, false);
gmac_clk_enable(gmac, false);
}
--
1.9.1
[RESEND PATCH 1/4] net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9210591..289e7a6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -629,6 +629,16 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
"rockchip,grf");
bsp_priv->pdev = pdev;
+ gmac_clk_init(bsp_priv);
+
+ return bsp_priv;
+}
+
+static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
+{
+ int ret;
+ struct device *dev = &bsp_priv->pdev->dev;
+
/*rmii or rgmii*/
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
dev_info(dev, "init for RGMII\n");
@@ -641,15 +651,6 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
dev_err(dev, "NO interface defined!\n");
}
- gmac_clk_init(bsp_priv);
-
- return bsp_priv;
-}
-
-static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
-{
- int ret;
-
ret = phy_power_on(bsp_priv, true);
if (ret)
return ret;
--
1.9.1
[RESEND PATCH 4/4] arm64: dts: rockchip: enable the gmac for rk3399 evb board
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index d47b4e9..ed6f2e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -94,12 +94,43 @@
regulator-always-on;
regulator-boot-on;
};
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
};
&emmc_phy {
status = "okay";
};
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&pwm0 {
status = "okay";
};
--
1.9.1
[RESEND PATCH 3/4] arm64: dts: rockchip: support gmac for rk3399
This patch adds needed gamc information for rk3399,
also support the gmac pd.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 90
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 32aebc8..abf27a4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -200,6 +200,26 @@
};
};
+ gmac: eth@fe30 {
+ compatible = "rockchip,rk3399-gmac";
+ reg = <0x0 0xfe30 0x0 0x1>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+<&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ power-domains = <&power RK3399_PD_GMAC>;
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
sdio0: dwmmc@fe31 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
@@ -611,6 +631,11 @@
status = "disabled";
};
+ qos_gmac: qos@ffa5c000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa5c000 0x0 0x20>;
+ };
+
qos_hdcp: qos@ffa9 {
compatible = "syscon";
reg = <0x0 0xffa9 0x0 0x20>;
@@ -704,6 +729,11 @@
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
+ pd_gmac@RK3399_PD_GMAC {
+ reg = ;
+ clocks = <&cru ACLK_GMAC>;
+ pm_qos = <&qos_gmac>;
+ };
pd_iep@RK3399_PD_IEP {
reg = ;
clocks = <&cru ACLK_IEP>,
@@ -1183,6 +1213,66 @@
drive-strength = <13>;
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxclk */
+ <3 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <3 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxd3 */
+ <3 3 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd2 */
+
[PATCH v3 3/5] arm64: dts: rockchip: add the gmac power domain on rk3399
This patch supports the gmac pd to save power consumption.
Even though some boards not need Ethernet support, the driver
core can also take care of powering up the pd before probe.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3:
- leave into two patches based on patchv2, and fix nits and commit, as
comment on https://patchwork.kernel.org/patch/9306339/
Changes in v2:
- Fixes the order, ss Heiko commnets on
https://patchwork.kernel.org/patch/9305991/
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 32aebc8..2ab233f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -611,6 +611,11 @@
status = "disabled";
};
+ qos_gmac: qos@ffa5c000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa5c000 0x0 0x20>;
+ };
+
qos_hdcp: qos@ffa9 {
compatible = "syscon";
reg = <0x0 0xffa9 0x0 0x20>;
@@ -739,6 +744,11 @@
};
/* These power domains are grouped by VD_LOGIC */
+ pd_gmac@RK3399_PD_GMAC {
+ reg = ;
+ clocks = <&cru ACLK_GMAC>;
+ pm_qos = <&qos_gmac>;
+ };
pd_vio@RK3399_PD_VIO {
reg = ;
#address-cells = <1>;
--
1.9.1
[PATCH v3 0/5] Support the rk3399 gmac pd function
This patch add to handle the gmac pd, and support the rk3399 gmac for devicetree. The History version: v1: https://lkml.org/lkml/2016/8/30/668 v2: https://lkml.org/lkml/2016/8/31/27 Changes in v3: - leave into two patches based on patchv2, and fix nits and commit, as comment on https://patchwork.kernel.org/patch/9306339/ - generate a patch from https://patchwork.kernel.org/patch/9306339/. Changes in v2: - rk_gmac_powerup instead of the rk_gmac_init. - fixes the build error on next kernel. - Fixes the order, ss Heiko commnets on https://patchwork.kernel.org/patch/9305991/ Caesar Wang (3): arm64: dts: rockchip: add the gmac power domain on rk3399 arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board David Wu (1): net: stmmac: dwmac-rk: add pd_gmac support for rk3399 Roger Chen (1): net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off arch/arm64/boot/dts/rockchip/rk3399-evb.dts| 31 + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 90 ++ drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 28 +--- 3 files changed, 140 insertions(+), 9 deletions(-) -- 1.9.1
[PATCH v3 1/5] net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2:
- rk_gmac_powerup instead of the rk_gmac_init.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9210591..289e7a6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -629,6 +629,16 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
"rockchip,grf");
bsp_priv->pdev = pdev;
+ gmac_clk_init(bsp_priv);
+
+ return bsp_priv;
+}
+
+static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
+{
+ int ret;
+ struct device *dev = &bsp_priv->pdev->dev;
+
/*rmii or rgmii*/
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
dev_info(dev, "init for RGMII\n");
@@ -641,15 +651,6 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
dev_err(dev, "NO interface defined!\n");
}
- gmac_clk_init(bsp_priv);
-
- return bsp_priv;
-}
-
-static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
-{
- int ret;
-
ret = phy_power_on(bsp_priv, true);
if (ret)
return ret;
--
1.9.1
[PATCH v3 2/5] net: stmmac: dwmac-rk: add pd_gmac support for rk3399
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2:
- fixes the build error on next kernel.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 289e7a6..406573d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "stmmac_platform.h"
@@ -659,11 +660,19 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
if (ret)
return ret;
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
return 0;
}
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
{
+ struct device *dev = &gmac->pdev->dev;
+
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
phy_power_on(gmac, false);
gmac_clk_enable(gmac, false);
}
--
1.9.1
[PATCH v3 5/5] arm64: dts: rockchip: enable the gmac for rk3399 evb board
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index d47b4e9..ed6f2e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -94,12 +94,43 @@
regulator-always-on;
regulator-boot-on;
};
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
};
&emmc_phy {
status = "okay";
};
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&pwm0 {
status = "okay";
};
--
1.9.1
[PATCH v3 4/5] arm64: dts: rockchip: add the gmac needed node for rk3399
The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface
from processor to a Reduced Media Independent Interface (RMII) and Reduced
Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY.
This patch adds the related needed device information.
e.g.: interrupts, grf, clocks, pinctrl and so on.
The full details are in [0].
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Caesar Wang
---
Changes in v3:
- generate a patch from https://patchwork.kernel.org/patch/9306339/.
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2ab233f..092bb45 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -200,6 +200,26 @@
};
};
+ gmac: ethernet@fe30 {
+ compatible = "rockchip,rk3399-gmac";
+ reg = <0x0 0xfe30 0x0 0x1>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+<&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ power-domains = <&power RK3399_PD_GMAC>;
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
sdio0: dwmmc@fe31 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
@@ -1193,6 +1213,66 @@
drive-strength = <13>;
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxclk */
+ <3 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <3 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxd3 */
+ <3 3 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd2 */
+ <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+
[PATCH v4 5/6] arm64: dts: rockchip: add the gmac needed node for rk3399
From: Roger Chen
The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface
from processor to a Reduced Media Independent Interface (RMII) and Reduced
Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY.
This patch adds the related needed device information.
e.g.: interrupts, grf, clocks, pinctrl and so on.
The full details are in [0].
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4:
- The Roger had posted patch on https://patchwork.kernel.org/patch/9274561/.
- re-fixup to original author.
Changes in v3:
- generate a patch from https://patchwork.kernel.org/patch/9306339/.
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2ab233f..092bb45 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -200,6 +200,26 @@
};
};
+ gmac: ethernet@fe30 {
+ compatible = "rockchip,rk3399-gmac";
+ reg = <0x0 0xfe30 0x0 0x1>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+<&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ power-domains = <&power RK3399_PD_GMAC>;
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
sdio0: dwmmc@fe31 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
@@ -1193,6 +1213,66 @@
drive-strength = <13>;
};
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins =
+ /* mac_txclk */
+ <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxclk */
+ <3 14 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txen */
+ <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_clk */
+ <3 11 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <3 9 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_mdc */
+ <3 8 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <3 7 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd0 */
+ <3 6 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd1 */
+ <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd0 */
+ <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_rxd3 */
+ <3 3 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_rxd2 */
+ <3 2 RK_FUNC_1 &pcfg_pull_none>,
+ /* mac_txd3 */
+ <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
+ /* mac_txd2 */
+ <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* mac_mdio */
+ <3 13 RK_FUNC_1 &pcfg_p
[PATCH v4 0/6] Support the rk3399 gmac and pd function
This patch have the following changes: 7edf13e net: stmmac: dwmac-rk: add rk3366 & rk3399 specific data 26e004e net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off b216c2f net: stmmac: dwmac-rk: add pd_gmac support for rk3399 848bb71 arm64: dts: rockchip: add the gmac power domain on rk3399 508e41f arm64: dts: rockchip: add the gmac needed node for rk3399 fb26795 arm64: dts: rockchip: enable the gmac for rk3399 evb board Hi David, The patch 1,2,3 is related to the rockchip net/stammc driver, Hi Heiko, The patch 4,5,6 is related to the dts changes. The History version: v1: https://lkml.org/lkml/2016/8/30/668 v2: https://lkml.org/lkml/2016/8/31/27 v3: https://lkml.org/lkml/2016/8/31/981 Thanks your reviewing! - Caesar Changes in v4: - Fixes from the original patch on https://patchwork.kernel.org/patch/9274557/ - remove the Roger signed-off for domain patch. - The Roger had posted patch on https://patchwork.kernel.org/patch/9274561/. - re-fixup to original author. Changes in v3: - leave into two patches based on patchv2, and fix nits and commit, as comment on https://patchwork.kernel.org/patch/9306339/ - generate a patch from https://patchwork.kernel.org/patch/9306339/. Changes in v2: - rk_gmac_powerup instead of the rk_gmac_init. - fixes the build error on next kernel. - Fixes the order, ss Heiko commnets on https://patchwork.kernel.org/patch/9305991/ Caesar Wang (1): arm64: dts: rockchip: add the gmac power domain on rk3399 David Wu (1): net: stmmac: dwmac-rk: add pd_gmac support for rk3399 Roger Chen (4): net: stmmac: dwmac-rk: add rk3366 & rk3399 specific data net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board .../devicetree/bindings/net/rockchip-dwmac.txt | 8 +- arch/arm64/boot/dts/rockchip/rk3399-evb.dts| 31 +++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 90 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 254 - 4 files changed, 372 insertions(+), 11 deletions(-) -- 1.9.1
[PATCH v4 1/6] net: stmmac: dwmac-rk: add rk3366 & rk3399 specific data
From: Roger Chen
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
Reviewed-by: Heiko Stuebner
---
Changes in v4:
- Fixes from the original patch on https://patchwork.kernel.org/patch/9274557/
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/net/rockchip-dwmac.txt | 8 +-
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 226 +
2 files changed, 232 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index cccd945..95383c5 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -3,8 +3,12 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
The device node has following properties.
Required properties:
- - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
- "rockchip,rk3368-gmac"
+ - compatible: should be "rockchip,-gamc"
+ "rockchip,rk3228-gmac": found on RK322x SoCs
+ "rockchip,rk3288-gmac": found on RK3288 SoCs
+ "rockchip,rk3366-gmac": found on RK3366 SoCs
+ "rockchip,rk3368-gmac": found on RK3368 SoCs
+ "rockchip,rk3399-gmac": found on RK3399 SoCs
- reg: addresses and length of the register sets for the device.
- interrupts: Should contain the GMAC interrupts.
- interrupt-names: Should contain the interrupt names "macirq".
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9210591..4e6a270 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -301,6 +301,118 @@ static const struct rk_gmac_ops rk3288_ops = {
.set_rmii_speed = rk3288_set_rmii_speed,
};
+#define RK3366_GRF_SOC_CON60x0418
+#define RK3366_GRF_SOC_CON70x041c
+
+/* RK3366_GRF_SOC_CON6 */
+#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_CLR_BIT(11))
+#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
+GRF_BIT(11))
+#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
+#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
+#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
+#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
+#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
+#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
+#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
+#define RK3366_GMAC_CLK_25M(GRF_BIT(4) | GRF_BIT(5))
+#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
+#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
+
+/* RK3366_GRF_SOC_CON7 */
+#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+RK3366_GMAC_PHY_INTF_SEL_RGMII |
+RK3366_GMAC_RMII_MODE_CLR);
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
+RK3366_GMAC_RXCLK_DLY_ENABLE |
+RK3366_GMAC_TXCLK_DLY_ENABLE |
+RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
+RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
+}
+
+static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+ return;
+ }
+
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
+}
+
+static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
+{
+ struct device *dev = &bsp_priv->pdev->dev;
+
+ if (IS_ERR(bsp_priv->grf)) {
+ dev_err(dev, "
[PATCH v4 2/6] net: stmmac: dwmac-rk: fixes the gmac resume after PD on/off
From: Roger Chen
GMAC Power Domain(PD) will be disabled during suspend.
That will causes GRF registers reset.
So corresponding GRF registers for GMAC must be setup again.
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- rk_gmac_powerup instead of the rk_gmac_init.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 4e6a270..e2ba6c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -853,6 +853,16 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
"rockchip,grf");
bsp_priv->pdev = pdev;
+ gmac_clk_init(bsp_priv);
+
+ return bsp_priv;
+}
+
+static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
+{
+ int ret;
+ struct device *dev = &bsp_priv->pdev->dev;
+
/*rmii or rgmii*/
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
dev_info(dev, "init for RGMII\n");
@@ -865,15 +875,6 @@ static struct rk_priv_data *rk_gmac_setup(struct
platform_device *pdev,
dev_err(dev, "NO interface defined!\n");
}
- gmac_clk_init(bsp_priv);
-
- return bsp_priv;
-}
-
-static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
-{
- int ret;
-
ret = phy_power_on(bsp_priv, true);
if (ret)
return ret;
--
1.9.1
[PATCH v4 6/6] arm64: dts: rockchip: enable the gmac for rk3399 evb board
From: Roger Chen
We add the required and optional properties for evb board.
See the [0] to get the detail information.
[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
Signed-off-by: Roger Chen
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index d47b4e9..ed6f2e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -94,12 +94,43 @@
regulator-always-on;
regulator-boot-on;
};
+
+ clkin_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <12500>;
+ clock-output-names = "clkin_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
};
&emmc_phy {
status = "okay";
};
+&gmac {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 5>;
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
+ assigned-clock-parents = <&clkin_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
&pwm0 {
status = "okay";
};
--
1.9.1
[PATCH v4 3/6] net: stmmac: dwmac-rk: add pd_gmac support for rk3399
From: David Wu
Add the gmac power domain support for rk3399, in order to save more
power consumption.
Signed-off-by: David Wu
Signed-off-by: Caesar Wang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- fixes the build error on next kernel.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index e2ba6c4..3740a44 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "stmmac_platform.h"
@@ -883,11 +884,19 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
if (ret)
return ret;
+ pm_runtime_enable(dev);
+ pm_runtime_get_sync(dev);
+
return 0;
}
static void rk_gmac_powerdown(struct rk_priv_data *gmac)
{
+ struct device *dev = &gmac->pdev->dev;
+
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
+
phy_power_on(gmac, false);
gmac_clk_enable(gmac, false);
}
--
1.9.1
[PATCH v4 4/6] arm64: dts: rockchip: add the gmac power domain on rk3399
This patch supports the gmac pd to save power consumption.
Even though some boards not need Ethernet support, the driver
core can also take care of powering up the pd before probe.
Signed-off-by: Caesar Wang
---
Changes in v4:
- remove the Roger signed-off for domain patch.
Changes in v3:
- leave into two patches based on patchv2, and fix nits and commit, as
comment on https://patchwork.kernel.org/patch/9306339/
Changes in v2:
- Fixes the order, ss Heiko commnets on
https://patchwork.kernel.org/patch/9305991/
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 32aebc8..2ab233f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -611,6 +611,11 @@
status = "disabled";
};
+ qos_gmac: qos@ffa5c000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa5c000 0x0 0x20>;
+ };
+
qos_hdcp: qos@ffa9 {
compatible = "syscon";
reg = <0x0 0xffa9 0x0 0x20>;
@@ -739,6 +744,11 @@
};
/* These power domains are grouped by VD_LOGIC */
+ pd_gmac@RK3399_PD_GMAC {
+ reg = ;
+ clocks = <&cru ACLK_GMAC>;
+ pm_qos = <&qos_gmac>;
+ };
pd_vio@RK3399_PD_VIO {
reg = ;
#address-cells = <1>;
--
1.9.1
Re: [PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver
Kevin,
Thanks for having a look into it.
在 2015年09月03日 02:28, Kevin Hilman 写道:
Caesar Wang writes:
This driver is found on RK3288 SoCs.
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power of the whole chip.
PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON
register. After setting the register, PMU would enter the Low Power mode.
In the low power mode, pmu will auto power on/off the specified power
domain, send idle req to specified power domain, shut down/up pll and
so on. All of above are configurable by setting corresponding registers.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
[...]
+static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
+{
+ int i;
+
+ for (i = 0; i < pd->num_clks; i++) {
+ clk_unprepare(pd->clks[i]);
+ clk_put(pd->clks[i]);
+ }
You don't set pd->num_clks = 0 here, which means other places that
iterate over the clocks might race with this and try to use clocks that
have been unprepared/put.
Agree, we should set the "pd->num_cloks=0' in here.
This might be over-paranoid, but in particular, this could race with
rockchip_pd_power().
Also not setting the pd->num_clks to zero would be a problem for a
power-controller that is configured as a module which could be unloaded
and reloaded (I know that doesn't really work now, but it will
eventually, I hope.)
Yep.
Maybe use the mutex here? It should at least protect the zeroing of
pm->num_clks.
Sound resonable.
Done.
---
Thanks,
Caesar
Kevin
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v17 1/4] dt-bindings: add document of Rockchip power domains
Kevin,
在 2015年09月03日 02:12, Kevin Hilman 写道:
Caesar Wang writes:
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16:
- remove the pmu node.
Changes in v15: None
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9:
- add document decription.
Changes in v8:
- document go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- DT structure has changed.
Changes in v2:
- move clocks to "optional".
.../bindings/soc/rockchip/power_domain.txt | 114 +
1 file changed, 114 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git
a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
new file mode 100644
index 000..4cf6b27
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -0,0 +1,114 @@
+* Rockchip Power Domains
+
+Rockchip processors include support for multiple power domains which can be
+powered up/down by software based on different application scenes to save
power.
+
+Required properties for power domain controller:
+- compatible: Should be one of the following.
+ "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+- #power-domain-cells: Number of cells in a power-domain specifier.
+ Should be 1 for multiple PM domains.
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power
domain.
+- clocks (optional): phandles to clocks which need to be enabled while power
domain
+ switches state.
+
+Example:
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+
+Node of a device using power domains must have a power-domains property,
+containing a phandle to the power device node and an index specifying which
+power domain to use.
+The index should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power
domain.
+
+Example of the node using power domain:
+
+ node {
+ /* ... */
+ power-domains = <&power RK3288_PD_GPU>;
+ /* ... */
+ };
+
+Others, all the device clocks being listed in the power-domains itself.
+All the device clocks are included in someone domians that need to enable
+before you operate them.
+
+As the chip designs for PM hardware. We need turn on the noc clocks,
+if we are operating the "pd_vio" domain to enter the idle status.
+
+As the following described in detail for every device be included in domains
+on RK3288 SoCs.
IMO, the below isn't really detailed enough, and also, the details
should be in the .dts file itself, not in the binding doc.
In particular, it's not obvious from the current series which of the
clocks are device clocks, and which are other/parent/infrastructure
clocks needed for the synchronous reset.
Okay, if we add some comments in dts. Says the following example.
What do you think of it?
I'm no sure if we should add these comments in dts.
It looks like it's always awkward. We can explain in the binding doc,
maybe for better reading.
/*
* Note: 'ACLK_GPU' is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
pd_gpu {
reg = ;
clocks = <&cru ACLK_GPU>;
};
/*
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
pd_hevc {
reg = ;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
};
/*
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
pd_video {
reg = ;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
};
/*
* Note: Although SCLK_* are the workin
[PATCH v18 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs
According to a description from TRM, add all the power domains. At the moment, we can support some domains on RK3288. We can add more types on RK3288 in the future, that's need to do. Signed-off-by: Caesar Wang --- Changes in v18: None Changes in v17: - delete the ugly chart in the commit. Changes in v16: - Add more domain decription. Changes in v15: - change the comment. Changes in v14: None Changes in v13: None Changes in v12: None Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None include/dt-bindings/power-domain/rk3288.h | 31 +++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/power-domain/rk3288.h diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h new file mode 100644 index 000..db5e810 --- /dev/null +++ b/include/dt-bindings/power-domain/rk3288.h @@ -0,0 +1,31 @@ +#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ +#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ + +/** + * RK3288 Power Domain and Voltage Domain Summary. + */ + +/* VD_CORE */ +#define RK3288_PD_A17_00 +#define RK3288_PD_A17_11 +#define RK3288_PD_A17_22 +#define RK3288_PD_A17_33 +#define RK3288_PD_SCU 4 +#define RK3288_PD_DEBUG5 +#define RK3288_PD_MEM 6 + +/* VD_LOGIC */ +#define RK3288_PD_BUS 7 +#define RK3288_PD_PERI 8 +#define RK3288_PD_VIO 9 +#define RK3288_PD_ALIVE10 +#define RK3288_PD_HEVC 11 +#define RK3288_PD_VIDEO12 + +/* VD_GPU */ +#define RK3288_PD_GPU 13 + +/* VD_PMU */ +#define RK3288_PD_PMU 14 + +#endif -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v18 3/4] soc: rockchip: power-domain: Add power domain driver
This driver is found on RK3288 SoCs. In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power of the whole chip. PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON register. After setting the register, PMU would enter the Low Power mode. In the low power mode, pmu will auto power on/off the specified power domain, send idle req to specified power domain, shut down/up pll and so on. All of above are configurable by setting corresponding registers. Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v18: - As Kevin suggestion, set pd->num_clks = 0 in rockchip_pm_remove_one_domain() ans add the mutex for protect - assign the order in rk3288_pm_domains[] in pm-domain driver. Changes in v17: - (re)defining config for ROCKCHIP. Changes in v16: - the driver type from tristate to bool. - Letter misspelled. - As Ulf suggestion, remove #include , use "%pC" as the formatting string for the dev_dbg(). - As the Ulf suggestion, set the genpd->flags to assign the ->stop|start() callbacks. Changes in v15: - As the kevin suggestion, put the power-domain driver into driver/soc/vendor. - As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver, 4: dts-changes. - return -ENXIO --> return -ENODEV. Changes in v14: - does not need to set an owner,remove the "THIS_MODULE". Changes in v13: - Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain. - Device drivers expect their devices to be powered on before their probing code is invoked. To achieve that we should start with power domains powered on (we may turn them off later once all devices enable runtime powermanagment and go idle). - This change switches Rockchip power domain driver to use updated device_attach and device_detach API. - set the gpu/core power domain power delay time. - fix enumerating PM clocks for devices. - fix use after free We can't use clk after we did clk_put(clk). Changes in v12: - fix the title doamin->domain. - updated device_attach and device_detach API,otherwise it will compile fail on next kernel. Changes in v11: - fix pm_genpd_init(&pd->genpd, NULL, false). Changes in v10: - this switches over domain infos to use masks instead of recomputing them each time and also gets rid of custom domain translator and uses standard onecell on. Changes in v9: - fix v8 changes as follows: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they trigger on and off during power transitions and independently from power domains clocks. We attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - add rockchip_pm_add_one_domain() to control domains. - add pd_start/pd_stop interface to control clocks. Changes in v8: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they toggle on and off during power transitions and independently from power domains clocks we attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. Changes in v7: - Delete unused variables Changes in v6: - delete pmu_lock. - modify dev_lock using mutex. - pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev). - pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev). - add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev. Changes in v5: - delete idle_lock. - add timeout in rockchip_pmu_set_idle_request(). Changes in v4: - use list storage dev. Changes in v3: - change use pm_clk_resume() and pm_clk_suspend(). Changes in v2: - remove the "pd->pd.of_node = np". drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/rockchip/Kconfig | 14 ++ drivers/soc/rockchip/Makefile | 4 + drivers/soc/rockchip/pm_domains.c | 490 ++ 5 files changed, 510 insertions(+) create mode 100644 drivers/soc/rockchip/Kconfig create mode 100644 drivers/soc/rockchip/Makefile create mode 100644 drivers/soc/rockchip/pm_domains.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 96ddecb..ecb1a6c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/rockchip/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" dif
[PATCH v18 1/4] dt-bindings: add document of Rockchip power domains
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v18:
- remove the notes of domains from dt-binding.
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16:
- remove the pmu node.
Changes in v15: None
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9:
- add document decription.
Changes in v8:
- document go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- DT structure has changed.
Changes in v2:
- move clocks to "optional".
.../bindings/soc/rockchip/power_domain.txt | 46 ++
1 file changed, 46 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
new file mode 100644
index 000..4be3418
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -0,0 +1,46 @@
+* Rockchip Power Domains
+
+Rockchip processors include support for multiple power domains which can be
+powered up/down by software based on different application scenes to save
power.
+
+Required properties for power domain controller:
+- compatible: Should be one of the following.
+ "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+- #power-domain-cells: Number of cells in a power-domain specifier.
+ Should be 1 for multiple PM domains.
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power
domain.
+- clocks (optional): phandles to clocks which need to be enabled while power
domain
+ switches state.
+
+Example:
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+
+Node of a device using power domains must have a power-domains property,
+containing a phandle to the power device node and an index specifying which
+power domain to use.
+The index should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power
domain.
+
+Example of the node using power domain:
+
+ node {
+ /* ... */
+ power-domains = <&power RK3288_PD_GPU>;
+ /* ... */
+ };
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v18 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs
We can add more domains node in the future.
This patch add the needed clocks into power-controller.
As the discuess about all the device clocks being listed in
the power-domains itself.
There are several reasons as follows:
Firstly, the clocks need be turned off to save power when
the system enter the suspend state. So we need to enumerate
the clocks in the dts. In order to power domain can turn on and off.
Secondly, the reset-circuit should reset be synchronous on RK3288,
then sync revoked. So we need to enable clocks of all devices.
In other words, we have to enable the clocks before you operate them
if all the device clocks are included in someone domians.
Thirdly, as the chip designs for PM hardhare. we need turn on the noc
clocks, if we are operating the "pd_vio" domain to enter the idle status.
The device's clock be included in domains that needed turn on if do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add these clocks in the future if we have some hidden clocks.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
Reviewed-by: Michael Turquette
---
Changes in v18:
- Change the index order in the dts on PATCH [4/4] .
- Add some notes for domains in the dts on PATCH [4/4].
Changes in v17:
- remove clocks of the HDMI ctrl.
- update the description.
- add Reviewed-by: Michale.
Changes in v16:
- Manually copy the problem in patch v15.
- rebase the description.
Changes in v15:
- As Tomasz remarked previously the dts should represent the hardware
and the power-domains are part of the pmu.
Changes in v14:
- Remove essential clocks from rk3288 PD_VIO domain, Some clocks are
essential for the system health and should not be turned down.
However there is no owner for them so if they listed as belonging to power
domain we'll try toggling them up and down during power domain transition.
As a result we either fail to suspend or resume the system.
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- fix missing the #include .
- remove the notes.
Changes in v9:
- add decription for power-doamin node.
Changes in v8:
- DTS go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
arch/arm/boot/dts/rk3288.dtsi | 93 ++-
1 file changed, 92 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..d7fa534 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include "skeleton.dtsi"
/ {
@@ -613,8 +614,98 @@
};
pmu: power-management@ff73 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff73 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+* Note: Although SCLK_* are the working clocks
+* of device without including on the NOC, needed for
+* synchronous reset.
+*
+* The clocks on the which NOC:
+* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
+* ACLK_RGA is on ACLK_RGA_NIU.
+* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+*
+* Which clock are device clocks:
+* clocks devices
+* *_IEP IEP:Image Enhancement Processor
+* *_ISP ISP:Image Signal Processing
+* *_VIP VIP:Video Input Processor
+* *_VOP* VOP:Visual Output Processor
+* *_RGA RGA
+* *_EDP* EDP
+* *_LVDS_*LVDS
+* *_HDMI HDMI
+* *_MIPI_*MIPI
+*/
+ pd_vio {
+
[PATCH v18 0/4] ARM: rk3288: Add PM Domain support
e the ugly chart in the commit. - (re)defining config for ROCKCHIP. - remove clocks of the HDMI ctrl. - update the description. - add Reviewed-by: Michale. Changes in v16: - remove the pmu node. - Add more domain decription. - the driver type from tristate to bool. - Letter misspelled. - As Ulf suggestion, remove #include , use "%pC" as the formatting string for the dev_dbg(). - As the Ulf suggestion, set the genpd->flags to assign the ->stop|start() callbacks. - Manually copy the problem in patch v15. - rebase the description. Changes in v15: - change the comment. - As the kevin suggestion, put the power-domain driver into driver/soc/vendor. - As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver, 4: dts-changes. - return -ENXIO --> return -ENODEV. - As Tomasz remarked previously the dts should represent the hardware and the power-domains are part of the pmu. Changes in v14: - does not need to set an owner,remove the "THIS_MODULE". - Remove essential clocks from rk3288 PD_VIO domain, Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain transition. As a result we either fail to suspend or resume the system. Changes in v13: - Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain. - Device drivers expect their devices to be powered on before their probing code is invoked. To achieve that we should start with power domains powered on (we may turn them off later once all devices enable runtime powermanagment and go idle). - This change switches Rockchip power domain driver to use updated device_attach and device_detach API. - set the gpu/core power domain power delay time. - fix enumerating PM clocks for devices. - fix use after free We can't use clk after we did clk_put(clk). Changes in v12: - fix the title doamin->domain. - updated device_attach and device_detach API,otherwise it will compile fail on next kernel. Changes in v11: - fix pm_genpd_init(&pd->genpd, NULL, false). Changes in v10: - this switches over domain infos to use masks instead of recomputing them each time and also gets rid of custom domain translator and uses standard onecell on. - fix missing the #include . - remove the notes. Changes in v9: - add document decription. - fix v8 changes as follows: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they trigger on and off during power transitions and independently from power domains clocks. We attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - add rockchip_pm_add_one_domain() to control domains. - add pd_start/pd_stop interface to control clocks. - add decription for power-doamin node. Changes in v8: - document go back to v2. - This reconciles the v2 and v7 code so that we power domain have lists of clocks they toggle on and off during power transitions and independently from power domains clocks we attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - DTS go back to v2. Changes in v7: - Delete unused variables Changes in v6: - delete pmu_lock. - modify dev_lock using mutex. - pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev). - pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev). - add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev. Changes in v5: - delete idle_lock. - add timeout in rockchip_pmu_set_idle_request(). Changes in v4: - use list storage dev. Changes in v3: - DT structure has changed. - change use pm_clk_resume() and pm_clk_suspend(). - Decomposition power-controller, changed to multiple controller (gpu-power-controller, hevc-power-controller). Changes in v2: - move clocks to "optional". - remove the "pd->pd.of_node = np". - make pd_vio clocks all one entry per line and alphabetize. - power: power-controller move back to pinctrl: pinctrl. Caesar Wang (4): dt-bindings: add document of Rockchip power domains ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs soc: rockchip: power-domain: Add power domain driver ARM: dts: add the support power-domain node on RK3288 SoCs .../bindings/soc/rockchip/power_domain.txt | 46 ++ arch/arm/boot/dts/rk3288.dtsi | 93 +++- drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/rockchip/Kconfig | 14 + drivers/soc/rockchip/Makefile | 4 + drivers/soc/ro
Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller
Doug, 在 2015年10月20日 23:52, Doug Anderson 写道: Caesar, On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang wrote: We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is high. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang --- drivers/thermal/rockchip_thermal.c | 32 1 file changed, 32 insertions(+) I think you could do this with no code changes to the thermal driver if we simply convince Linus W. to apply a change that I posted up just about a year ago. See: https://patchwork.kernel.org/patch/5055741/ In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/> Linus said he liked it "A lot" and was willing to merge it with Greg KH's Ack and with a small comment fix. I obtained the Ack and fixed the comment, but then the patch didn't end up being needed for me and so I never bumped it and it got lost... Maybe you could re-test that patch? It looks like it has a merge conflict with current linuxnext but it looks trivial to resolve. You could re-post my patch or I could repost it and you could add your Tested-by. You'd still want to have a bindings change to describe "init", but at least you shouldn't need any code changes. Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me. Fell free add my test tag if you resend the patch. (Tested-by: Caesar Wang ) 1634ed8 FROMLIST: drivers/pinctrl: Add the concept of an "init" state 15158f8 FROMLIST: ARM: dts: rockchip: Add the OTP gpio pinctrl e7d3b88 FROMLIST: thermal: rockchip: change the TSHUT default state 184b154 FROMLIST: thermal: rockchip: ensure the otp state before resetting the controller 9edbe15 FROMLIST: dt-bindings: Sync the dts to this document Meanwhile, I change the dts as follows. - pinctrl-names = "default", "otp_out"; + pinctrl-names = "init", "default"; pinctrl-0 = <&otp_gpio>; pinctrl-1 = <&otp_out>; -Doug ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state
Doug, 在 2015年10月21日 10:14, Doug Anderson 写道: Caesar, On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang wrote: Doug, 在 2015年10月21日 00:01, Doug Anderson 写道: Caesar, On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang wrote: As the TRM says, the TSHUT default state is high active. In general, the TSHUT state can get from the dts. Otherwise it gets the state from this. Can you point at where the TRM says that the default state is high active? With the manual I have, I look at TSADC_AUTO_CON and I look at the description of "Bit 8". It says that "tshut polarity" is 0 for low active and 1 for high active. It then said that the Reset Value is 0. ...the "Reset Value" in tables like this is notoriously unreliable, so I can totally believe that it's wrong. If you can point me at the part of the TRM that says that TSHUT is high active by default then I can confirm that for you. ;) Okay, I know that's my wrong, the polarity is high or low can be selected. :-( I remember the veyron why is the default HiGH active, since the opt is connected to the PMIC.(we need think about the devices) Why is the evb board LOW active, since the opt didn't connected to the devices. TSHUT is depend on the CRU to work. I think we can drop this patch then, right? Any boards that need a change from the default can just set "rockchip,hw-tshut-polarity", right? Yep, we should drop this patch. I'm ready resend the patchs. -Doug -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/2] fix the TSHUT issue on rockchip thermal
We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. This series patchs are depend on Doug's patch.(https://patchwork.kernel.org/patch/7454081/) This series patchs are based on the Linus master branch. c51a571 ARM: dts: rockchip: Add the OTP gpio pinctrl e1ecae4 dt-bindings: Sync the dts to this document 150426c drivers/pinctrl: Add the concept of an "init" state ce1fad2 Merge branch 'keys-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 1099f86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 911b79c KEYS: Don't permit request_key() to construct a new keyring 37850e3 net: bcmgenet: Fix early link interrupt enabling afc050d Merge tag 'wireless-drivers-for-davem-2015-10-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers e277de5 tunnels: Don't require remote endpoint or ID during creation. 740dbc2 openvswitch: Scrub skb between namespaces Tested on box board. Changes in v1: - As the Doug comments, add the 'init' property to sync document. - As the Doug comments, drop the thermal driver patchs since we can with pinctrl changing to work. - As the Doug's patch to add the 'init' property. Caesar Wang (2): dt-bindings: Sync the dts to this document ARM: dts: rockchip: Add the OTP gpio pinctrl Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++-- arch/arm/boot/dts/rk3288.dtsi | 9 +++-- 2 files changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..6ea89aa 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1274,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/2] dt-bindings: Sync the dts to this document
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/2] dt-bindings: Sync the dts to this document
Hi Rob,
在 2015年10月21日 23:18, Rob Herring 写道:
On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang wrote:
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
Are these optional or required? They only appear in the example.
Yep,
These are required for TSADC.
I‘m assumed that's right,
I think we don't need to introduce the pinctrl in this document.
Rob
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/2] dt-bindings: Add the "init" pinctrl in this document
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, since we need switch
the pin to gpio state before the TSADC controller is reset.
As I know, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- As the Rob comments, add the 'init' pinctrl more decription in document.
- fix the subject to make more obvious in PATCH[1/2]
Series-changes: 1
- As the Doug comments, add the 'init' property to sync document.
Changes in v1: None
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/2] fix the TSHUT issue on rockchip thermal
We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. This series patchs are depend on Doug's patch.(https://patchwork.kernel.org/patch/7454311/) This series patchs are based on the Linus master branch. 518cd44 ARM: dts: rockchip: Add the OTP gpio pinctrl 83e0bab dt-bindings: Add the "init" pinctrl in this document 150426c drivers/pinctrl: Add the concept of an "init" state ce1fad2 Merge branch 'keys-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 1099f86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 911b79c KEYS: Don't permit request_key() to construct a new keyring 37850e3 net: bcmgenet: Fix early link interrupt enabling afc050d Merge tag 'wireless-drivers-for-davem-2015-10-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers e277de5 tunnels: Don't require remote endpoint or ID during creation. 740dbc2 openvswitch: Scrub skb between namespaces Tested on box board. Changes in v2: - As the Rob comments, add the 'init' pinctrl more decription in document. - fix the subject to make more obvious in PATCH[1/2] Series-changes: 1 - As the Doug comments, add the 'init' property to sync document. - Add some commits for more obvious in PATCH[2/2] Changes in v1: - As the Doug comments, drop the thermal driver patchs since we can with pinctrl changing to work. - As the Doug's patch to add the 'init' property. Caesar Wang (2): dt-bindings: Add the "init" pinctrl in this document ARM: dts: rockchip: Add the OTP gpio pinctrl Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++-- arch/arm/boot/dts/rk3288.dtsi | 9 +++-- 2 files changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl
Add the "init" pinctrl as the OTP gpio state.
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
"init" pinctrl property is defined by Doug's Patch[0].
Patch[0]:
https://patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..6ea89aa 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1274,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 1/2] dt-bindings: Sync the dts to this document
在 2015年10月22日 09:18, Rob Herring 写道: On Wed, Oct 21, 2015 at 11:48 AM, Rob Herring wrote: On Wed, Oct 21, 2015 at 10:45 AM, Caesar Wang wrote: Hi Rob, 在 2015年10月21日 23:18, Rob Herring 写道: On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang wrote: Add the OTP gpio state, we need switch the pin to gpio state before the TSADC controller is reset. Also, please fix the subject to be specific what binding you are changing. dt-bindings: rockchip-thermal: Sorry, Mr. Rob I just sent the patch.:-( Rob -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 1/2] dt-bindings: Add the "init" pinctrl in this document
在 2015年10月22日 09:34, Rob Herring 写道:
On Wed, Oct 21, 2015 at 8:25 PM, Caesar Wang wrote:
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, since we need switch
the pin to gpio state before the TSADC controller is reset.
As I know, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- As the Rob comments, add the 'init' pinctrl more decription in document.
Where?
Okay, Mr, Rob
That strictly speaking only in commit.:-(
- fix the subject to make more obvious in PATCH[1/2]
Series-changes: 1
- As the Doug comments, add the 'init' property to sync document.
Changes in v1: None
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
Thanks,
Caesar
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox
I'm missing this patch for long time.
在 2015年10月06日 22:50, Rob Herring 写道:
On Mon, Sep 14, 2015 at 6:06 AM, Caesar Wang wrote:
This add the necessary binding documentation for mailbox
found on RK3368 SoC.
Signed-off-by: Caesar Wang
---
.../bindings/mailbox/rockchip-mailbox.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
new file mode 100644
index 000..b9b4768
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
@@ -0,0 +1,33 @@
+Rockchip mailbox
+
+The Rockchip mailbox is used by the Rockchip CPU cores to communicate
+requests to MCU processor.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Required properties:
+
+ - compatible: should be one of the following.
+ - "rockchip,rk3368-mbox" for rk3368
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ physical base address of the share buffer and length of memory mapped
s/share/shared/
Done.
+ region.
+ - interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
Need to specify the value of #mbox-cells.
Done.
+
+Example:
+
+
+/* RK3368 */
+mbox: mbox@ff6b {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b 0x0 0x1000>,
+ <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
If this is just onchip SRAM usable for anything, then use the SRAM
binding (misc/sram.txt). It has provisions for defining the use.
Okay, we don't need define the shared-sram in this document.
+ interrupts = ,
+,
+,
+;
+ #mbox-cells = <1>;
+};
--
1.9.1
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
--
Thanks,
Caesar
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/3] dt-bindings: Add document of Rockchip mailbox
Hello Jassi, Sorry for delay reply. 在 2015年10月06日 18:34, Jassi Brar 写道: On Mon, Sep 14, 2015 at 4:36 PM, Caesar Wang wrote: This add the necessary binding documentation for mailbox found on RK3368 SoC. Signed-off-by: Caesar Wang --- .../bindings/mailbox/rockchip-mailbox.txt | 33 ++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt new file mode 100644 index 000..b9b4768 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt @@ -0,0 +1,33 @@ +Rockchip mailbox + +The Rockchip mailbox is used by the Rockchip CPU cores to communicate +requests to MCU processor. + +Refer to ./mailbox.txt for generic information about mailbox device-tree +bindings. + +Required properties: + + - compatible: should be one of the following. + - "rockchip,rk3368-mbox" for rk3368 + - reg: physical base address of the controller and length of memory mapped + region. + physical base address of the share buffer and length of memory mapped + region. Please make shared-sram a property of user drivers. As Rob points out, maybe, don't we need also define it in user drivers. As the SRAM binding (misc/sram.txt) had defined. I just make the SCPI protocol client driver to work for mailbox. Location and size of shared-memory is a platform property, mailbox controller doesn't need sram to function. For example, protocol on some platform, with this controller, may be trivial enough to not need a shared sram... say only 32-bits wide requests and responses which can be passed via mailbox registers directly. mbox_client.tx_prepare() is where the user driver sets up the shared-memory. ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RESEND PATCH v2 1/2] dt-bindings: rockchip-thermal: Add the "init" pinctrl in this document
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, since we need switch
the pin to gpio state before the TSADC controller is reset.
As I know, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Add the 'init' pinctrl more decription in commit.
- Fix the subject to make more obvious in PATCH[1/2]
- Resend this patch v2 since fix the subject to be specific.
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[RESEND PATCH v2 0/2] fix the TSHUT issue on rockchip thermal
We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. This series patchs are depend on Doug's patch.(https://patchwork.kernel.org/patch/7454311/) This series patchs are based on the Linus master branch. 518cd44 ARM: dts: rockchip: Add the OTP gpio pinctrl 83e0bab dt-bindings: Add the "init" pinctrl in this document 150426c drivers/pinctrl: Add the concept of an "init" state ce1fad2 Merge branch 'keys-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 1099f86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 911b79c KEYS: Don't permit request_key() to construct a new keyring 37850e3 net: bcmgenet: Fix early link interrupt enabling afc050d Merge tag 'wireless-drivers-for-davem-2015-10-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers e277de5 tunnels: Don't require remote endpoint or ID during creation. 740dbc2 openvswitch: Scrub skb between namespaces Tested on box board. Changes in v2: - Add the 'init' pinctrl more decription in commit. - Fix the subject to make more obvious in PATCH[1/2] - Resend this patch v2 since fix the subject to be specific. - Add some commits for more obvious in PATCH[2/2] Changes in v1: - As the Doug comments, add the 'init' property to sync document. - As the Doug comments, drop the thermal driver patchs since we can with pinctrl changing to work. - As the Doug's patch to add the 'init' property. Caesar Wang (2): dt-bindings: rockchip-thermal: Add the "init" pinctrl in this document ARM: dts: rockchip: Add the OTP gpio pinctrl Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++-- arch/arm/boot/dts/rk3288.dtsi | 9 +++-- 2 files changed, 10 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[RESEND PATCH v2 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl
Add the "init" pinctrl as the OTP gpio state.
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
"init" pinctrl property is defined by Doug's Patch[0].
Patch[0]:
https://patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..6ea89aa 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1274,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [RESEND PATCH v2 1/2] dt-bindings: rockchip-thermal: Add the "init" pinctrl in this document
在 2015年10月22日 11:45, Doug Anderson 写道: Caesar, On Wed, Oct 21, 2015 at 7:30 PM, Caesar Wang wrote: The "init" pinctrl is defined we'll set pinctrl to this state before probe and then "default" after probe. Add the "init" pinctrl as the OTP gpio state, since we need switch the pin to gpio state before the TSADC controller is reset. As I know, the TSADC controller is reset, the tshut polarity will be a *low* signal in a short period of time for some devices. Says: The TSADC get the temperature on rockchip thermal. If T(current temperature) < (setting temperature), the OTP output the *high* signal. If T(current temperature) > (setting temperature), the OTP output the *low* Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang Reviewed-by: Douglas Anderson --- Changes in v2: - Add the 'init' pinctrl more decription in commit. - Fix the subject to make more obvious in PATCH[1/2] - Resend this patch v2 since fix the subject to be specific. Changes in v1: - As the Doug comments, add the 'init' property to sync document. Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt index ef802de..28e84f7 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt I think Rob wanted something more in the "rockchip-thermal.txt" document itself. Like: Pinctrl states: - During device probe a driver may glitch the output line. If this is not acceptable for your board, you can use the standard "init" and "default" pinctrl states. The "init" state will be set before device probe and "default" after. Sound resonable. Thanks Doug to explain! ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v17 2/4] ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs
According to a description from TRM, add all the power domains. At the moment, we can support some domains on RK3288. We can add more types on RK3288 in the future, that's need to do. Signed-off-by: Caesar Wang --- Changes in v17: - delete the ugly chart in the commit. Changes in v16: - Add more domain decription. Changes in v15: - change the comment. Changes in v14: None Changes in v13: None Changes in v12: None Changes in v11: None Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None include/dt-bindings/power-domain/rk3288.h | 31 +++ 1 file changed, 31 insertions(+) create mode 100644 include/dt-bindings/power-domain/rk3288.h diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h new file mode 100644 index 000..db5e810 --- /dev/null +++ b/include/dt-bindings/power-domain/rk3288.h @@ -0,0 +1,31 @@ +#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ +#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ + +/** + * RK3288 Power Domain and Voltage Domain Summary. + */ + +/* VD_CORE */ +#define RK3288_PD_A17_00 +#define RK3288_PD_A17_11 +#define RK3288_PD_A17_22 +#define RK3288_PD_A17_33 +#define RK3288_PD_SCU 4 +#define RK3288_PD_DEBUG5 +#define RK3288_PD_MEM 6 + +/* VD_LOGIC */ +#define RK3288_PD_BUS 7 +#define RK3288_PD_PERI 8 +#define RK3288_PD_VIO 9 +#define RK3288_PD_ALIVE10 +#define RK3288_PD_HEVC 11 +#define RK3288_PD_VIDEO12 + +/* VD_GPU */ +#define RK3288_PD_GPU 13 + +/* VD_PMU */ +#define RK3288_PD_PMU 14 + +#endif -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v17 1/4] dt-bindings: add document of Rockchip power domains
This add the necessary binding documentation for the power domains
found on Rockchip SoCs.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v17:
- add the decription in detail for RK3288 SoCs.
Changes in v16:
- remove the pmu node.
Changes in v15: None
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9:
- add document decription.
Changes in v8:
- document go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- DT structure has changed.
Changes in v2:
- move clocks to "optional".
.../bindings/soc/rockchip/power_domain.txt | 114 +
1 file changed, 114 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
diff --git a/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
new file mode 100644
index 000..4cf6b27
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/rockchip/power_domain.txt
@@ -0,0 +1,114 @@
+* Rockchip Power Domains
+
+Rockchip processors include support for multiple power domains which can be
+powered up/down by software based on different application scenes to save
power.
+
+Required properties for power domain controller:
+- compatible: Should be one of the following.
+ "rockchip,rk3288-power-controller" - for RK3288 SoCs.
+- #power-domain-cells: Number of cells in a power-domain specifier.
+ Should be 1 for multiple PM domains.
+- #address-cells: Should be 1.
+- #size-cells: Should be 0.
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for RK3288 type power
domain.
+- clocks (optional): phandles to clocks which need to be enabled while power
domain
+ switches state.
+
+Example:
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+ };
+
+Node of a device using power domains must have a power-domains property,
+containing a phandle to the power device node and an index specifying which
+power domain to use.
+The index should use macros in:
+ "include/dt-bindings/power-domain/rk3288.h" - for rk3288 type power
domain.
+
+Example of the node using power domain:
+
+ node {
+ /* ... */
+ power-domains = <&power RK3288_PD_GPU>;
+ /* ... */
+ };
+
+Others, all the device clocks being listed in the power-domains itself.
+All the device clocks are included in someone domians that need to enable
+before you operate them.
+
+As the chip designs for PM hardware. We need turn on the noc clocks,
+if we are operating the "pd_vio" domain to enter the idle status.
+
+As the following described in detail for every device be included in domains
+on RK3288 SoCs.
+
+ /* GPU's ACLK_GPU on the ACLK_GPU_NIU */
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ /* HEVC AXI clocks */
+ pd_hevc {
+ reg = ;
+ clocks = <&cru ACLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru HCLK_HEVC>;
+ };
+
+ /*
+* RGA, VOP, MIPI, LVDS, EDP..., says the ACLK* on the ACLK_VIO_NIU,
+* others are on the HCLK_VIO_NIU.
+*/
+ pd_vio {
+ reg = ;
+ clocks = <&cru ACLK_IEP>,
+ <&cru ACLK_ISP>,
+ <&cru ACLK_RGA>,
+ <&cru ACLK_VIP>,
+ <&cru ACLK_VOP0>,
+ <&cru ACLK_VOP1>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru HCLK_IEP>,
+ <&cru HCLK_ISP>,
+ <&cru HCLK_RGA>,
+ <&cru HCLK_VIP>,
+ <&cru HCLK_VOP0>,
+ <&cru HCLK_VOP1>,
+ <&cru PCLK_EDP_CTRL>,
+ <&cru PCLK_HDMI_CTRL>,
+ <&cru PCLK_LVDS_PHY>,
+ <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_MIPI_DSI0>,
+ <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_EDP_24M>,
+ <&cru SCLK_EDP>,
+ <&cru SCLK_ISP_JPE>,
+ &l
[PATCH v17 0/4] ARM: rk3288: Add PM Domain support
t() callbacks. - Manually copy the problem in patch v15. - rebase the description. Changes in v15: - change the comment. - As the kevin suggestion, put the power-domain driver into driver/soc/vendor. - As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver, 4: dts-changes. - return -ENXIO --> return -ENODEV. - As Tomasz remarked previously the dts should represent the hardware and the power-domains are part of the pmu. Changes in v14: - does not need to set an owner,remove the "THIS_MODULE". - Remove essential clocks from rk3288 PD_VIO domain, Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain transition. As a result we either fail to suspend or resume the system. Changes in v13: - Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain. - Device drivers expect their devices to be powered on before their probing code is invoked. To achieve that we should start with power domains powered on (we may turn them off later once all devices enable runtime powermanagment and go idle). - This change switches Rockchip power domain driver to use updated device_attach and device_detach API. - set the gpu/core power domain power delay time. - fix enumerating PM clocks for devices. - fix use after free We can't use clk after we did clk_put(clk). Changes in v12: - fix the title doamin->domain. - updated device_attach and device_detach API,otherwise it will compile fail on next kernel. Changes in v11: - fix pm_genpd_init(&pd->genpd, NULL, false). Changes in v10: - this switches over domain infos to use masks instead of recomputing them each time and also gets rid of custom domain translator and uses standard onecell on. - fix missing the #include . - remove the notes. Changes in v9: - add document decription. - fix v8 changes as follows: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they trigger on and off during power transitions and independently from power domains clocks. We attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - add rockchip_pm_add_one_domain() to control domains. - add pd_start/pd_stop interface to control clocks. - add decription for power-doamin node. Changes in v8: - document go back to v2. - This reconciles the v2 and v7 code so that we power domain have lists of clocks they toggle on and off during power transitions and independently from power domains clocks we attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - DTS go back to v2. Changes in v7: - Delete unused variables Changes in v6: - delete pmu_lock. - modify dev_lock using mutex. - pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev). - pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev). - add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev. Changes in v5: - delete idle_lock. - add timeout in rockchip_pmu_set_idle_request(). Changes in v4: - use list storage dev. Changes in v3: - DT structure has changed. - change use pm_clk_resume() and pm_clk_suspend(). - Decomposition power-controller, changed to multiple controller (gpu-power-controller, hevc-power-controller). Changes in v2: - move clocks to "optional". - remove the "pd->pd.of_node = np". - make pd_vio clocks all one entry per line and alphabetize. - power: power-controller move back to pinctrl: pinctrl. Caesar Wang (4): dt-bindings: add document of Rockchip power domains ARM: power-domain: rockchip: add all the domain type on RK3288 SoCs soc: rockchip: power-domain: Add power domain driver ARM: dts: add the support power-domain node on RK3288 SoCs .../bindings/soc/rockchip/power_domain.txt | 114 + arch/arm/boot/dts/rk3288.dtsi | 58 ++- drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/rockchip/Kconfig | 14 + drivers/soc/rockchip/Makefile | 4 + drivers/soc/rockchip/pm_domains.c | 485 + include/dt-bindings/power-domain/rk3288.h | 31 ++ 8 files changed, 707 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/soc/rockchip/power_domain.txt create mode 100644 drivers/soc/rockchip/Kconfig create mode 100644 drivers/soc/rockchip/Makefile create mode 100644 drivers/soc/rockchip/pm_domains.c create mode 100644 include/dt-bindings/power-domain/rk3288.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v17 3/4] soc: rockchip: power-domain: Add power domain driver
This driver is found on RK3288 SoCs. In order to meet high performance and low power requirements, a power management unit is designed or saving power when RK3288 in low power mode. The RK3288 PMU is dedicated for managing the power of the whole chip. PMU can work in the Low Power Mode by setting bit[0] of PMU_PWRMODE_CON register. After setting the register, PMU would enter the Low Power mode. In the low power mode, pmu will auto power on/off the specified power domain, send idle req to specified power domain, shut down/up pll and so on. All of above are configurable by setting corresponding registers. Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v17: - (re)defining config for ROCKCHIP. Changes in v16: - the driver type from tristate to bool. - Letter misspelled. - As Ulf suggestion, remove #include , use "%pC" as the formatting string for the dev_dbg(). - As the Ulf suggestion, set the genpd->flags to assign the ->stop|start() callbacks. Changes in v15: - As the kevin suggestion, put the power-domain driver into driver/soc/vendor. - As Heiko suggestion, Patch 1: binding doc, 2: binding-header, 3: driver, 4: dts-changes. - return -ENXIO --> return -ENODEV. Changes in v14: - does not need to set an owner,remove the "THIS_MODULE". Changes in v13: - Remove essential clocks from rk3288 PD_VIO domain Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain. - Device drivers expect their devices to be powered on before their probing code is invoked. To achieve that we should start with power domains powered on (we may turn them off later once all devices enable runtime powermanagment and go idle). - This change switches Rockchip power domain driver to use updated device_attach and device_detach API. - set the gpu/core power domain power delay time. - fix enumerating PM clocks for devices. - fix use after free We can't use clk after we did clk_put(clk). Changes in v12: - fix the title doamin->domain. - updated device_attach and device_detach API,otherwise it will compile fail on next kernel. Changes in v11: - fix pm_genpd_init(&pd->genpd, NULL, false). Changes in v10: - this switches over domain infos to use masks instead of recomputing them each time and also gets rid of custom domain translator and uses standard onecell on. Changes in v9: - fix v8 changes as follows: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they trigger on and off during power transitions and independently from power domains clocks. We attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. - add rockchip_pm_add_one_domain() to control domains. - add pd_start/pd_stop interface to control clocks. Changes in v8: - This reconciles the v2 and v7 code so that we power domain have lists of clocks they toggle on and off during power transitions and independently from power domains clocks we attach clocks to devices comprising power domain and prepare them so they are turn on and off by runtime PM. Changes in v7: - Delete unused variables Changes in v6: - delete pmu_lock. - modify dev_lock using mutex. - pm_clk_resume(pd->dev) change to pm_clk_resume(ed->dev). - pm_clk_suspend(pd->dev) change to pm_clk_suspend(ed->dev). - add devm_kfree(pd->dev, de) in rockchip_pm_domain_detach_dev. Changes in v5: - delete idle_lock. - add timeout in rockchip_pmu_set_idle_request(). Changes in v4: - use list storage dev. Changes in v3: - change use pm_clk_resume() and pm_clk_suspend(). Changes in v2: - remove the "pd->pd.of_node = np". drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/rockchip/Kconfig | 14 ++ drivers/soc/rockchip/Makefile | 4 + drivers/soc/rockchip/pm_domains.c | 485 ++ 5 files changed, 505 insertions(+) create mode 100644 drivers/soc/rockchip/Kconfig create mode 100644 drivers/soc/rockchip/Makefile create mode 100644 drivers/soc/rockchip/pm_domains.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 96ddecb..ecb1a6c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/rockchip/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 0b12d77..c2b485f 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_MACH_DOVE)+= dove
[PATCH v17 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs
We can add more domains node in the future.
This patch add the needed clocks into power-controller.
As the discuess about all the device clocks being listed in
the power-domains itself.
There are several reasons as follows:
Firstly, the clocks need be turned off to save power when
the system enter the suspend state. So we need to enumerate
the clocks in the dts. In order to power domain can turn on and off.
Secondly, the reset-circuit should reset be synchronous on RK3288,
then sync revoked. So we need to enable clocks of all devices.
In other words, we have to enable the clocks before you operate them
if all the device clocks are included in someone domians.
Thirdly, as the chip designs for PM hardhare. we need turn on the noc
clocks, if we are operating the "pd_vio" domain to enter the idle status.
The device's clock be included in domains that needed turn on if do that.
The clocks in the dts are needed to enable before you want to happy work.
At the moment, This patch is very good work for PM hardware.
Also, we can add it in the future if we have some hidden clocks.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
Reviewed-by: Michael Turquette
---
Changes in v17:
- remove clocks of the HDMI ctrl.
- update the description.
- add Reviewed-by: Michale.
Changes in v16:
- Manually copy the problem in patch v15.
- rebase the description.
Changes in v15:
- As Tomasz remarked previously the dts should represent the hardware
and the power-domains are part of the pmu.
Changes in v14:
- Remove essential clocks from rk3288 PD_VIO domain, Some clocks are
essential for the system health and should not be turned down.
However there is no owner for them so if they listed as belonging to power
domain we'll try toggling them up and down during power domain transition.
As a result we either fail to suspend or resume the system.
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- fix missing the #include .
- remove the notes.
Changes in v9:
- add decription for power-doamin node.
Changes in v8:
- DTS go back to v2.
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller).
Changes in v2:
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
arch/arm/boot/dts/rk3288.dtsi | 58 ++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..4ce3099 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include "skeleton.dtsi"
/ {
@@ -613,8 +614,63 @@
};
pmu: power-management@ff73 {
- compatible = "rockchip,rk3288-pmu", "syscon";
+ compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
reg = <0xff73 0x100>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ pd_hevc {
+ reg = ;
+ clocks = <&cru ACLK_HEVC>,
+<&cru SCLK_HEVC_CABAC>,
+<&cru SCLK_HEVC_CORE>,
+<&cru HCLK_HEVC>;
+ };
+
+ pd_vio {
+ reg = ;
+ clocks = <&cru ACLK_IEP>,
+<&cru ACLK_ISP>,
+<&cru ACLK_RGA>,
+<&cru ACLK_VIP>,
+<&cru ACLK_VOP0>,
+<&cru ACLK_VOP1>,
+<&cru DCLK_VOP0>,
+<&cru DCLK_VOP1>,
+<&cru HCLK_IEP>,
+<&cru HCLK_ISP>,
+<&cru HCLK_RGA>,
+<&cru HCLK_VIP>,
+<&cru HCLK_VOP0>,
+
[PATCH 1/4] dt-bindings: Sync the dts to this document
Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.
Signed-off-by: Caesar Wang
---
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..2587f34b 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "default", "otp_out";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/4]
We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Tested on box board. Caesar Wang (4): dt-bindings: Sync the dts to this document thermal: rockchip: ensure the otp state before resetting the controller thermal: rockchip: change the TSHUT default state ARM: dts: rockchip: Add the OTP gpio pinctrl .../bindings/thermal/rockchip-thermal.txt | 5 ++-- arch/arm/boot/dts/rk3288.dtsi | 9 -- drivers/thermal/rockchip_thermal.c | 34 +- 3 files changed, 43 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/4] ARM: dts: rockchip: Add the OTP gpio pinctrl
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Signed-off-by: Caesar Wang
---
arch/arm/boot/dts/rk3288.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..b59c451 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "default", "otp_out";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1274,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/4] thermal: rockchip: change the TSHUT default state
As the TRM says, the TSHUT default state is high active.
In general, the TSHUT state can get from the dts. Otherwise
it gets the state from this.
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index c53e318..776d668 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -326,7 +326,7 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem
*regs,
static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
- .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_polarity = TSHUT_HIGH_ACTIVE, /* default TSHUT HIGH ACTIVE */
.tshut_temp = 95000,
.initialize = rk_tsadcv2_initialize,
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Says:
The TSHUT temperature is setting more than 80 degree, the default tshut
polarity is high.
If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.
On the moment, the TSADC controller is reset, the tshut polarity will be
low in a short period of time.
So:
If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index c89ffb2..c53e318 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
/**
* If the temperature over a period of time High,
@@ -79,6 +80,9 @@ struct rockchip_thermal_sensor {
struct rockchip_thermal_data {
const struct rockchip_tsadc_chip *chip;
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pins_default;
+ struct pinctrl_state *pins_otp;
struct platform_device *pdev;
struct reset_control *reset;
@@ -548,6 +552,28 @@ static int rockchip_thermal_probe(struct platform_device
*pdev)
goto err_disable_clk;
}
+ /*
+* We need the OTP pin is gpio state before reset the TSADC controller
+* since the tshut polarity will generate a high signal.
+*/
+
+ thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(thermal->pinctrl)) {
+ error = PTR_ERR(thermal->pinctrl);
+ dev_err(&pdev->dev, "failed to get thermal pinctrl: %d\n",
+ error);
+ goto err_disable_pclk;
+ }
+
+ thermal->pins_default = pinctrl_lookup_state(thermal->pinctrl,
+"default");
+ if (IS_ERR(thermal->pins_default))
+ dev_warn(&pdev->dev, "could not get the pinctrl default
state\n");
+
+ thermal->pins_otp = pinctrl_lookup_state(thermal->pinctrl, "otp_out");
+ if (IS_ERR(thermal->pins_otp))
+ dev_warn(&pdev->dev, "could not get otp state\n");
+
rockchip_thermal_reset_controller(thermal->reset);
error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
@@ -592,6 +618,8 @@ static int rockchip_thermal_probe(struct platform_device
*pdev)
for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
+ pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
platform_set_drvdata(pdev, thermal);
return 0;
@@ -660,6 +688,8 @@ static int __maybe_unused rockchip_thermal_resume(struct
device *dev)
if (error)
return error;
+ pinctrl_select_state(thermal->pinctrl, thermal->pins_default);
+
rockchip_thermal_reset_controller(thermal->reset);
thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
@@ -678,6 +708,8 @@ static int __maybe_unused rockchip_thermal_resume(struct
device *dev)
for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
+ pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
return 0;
}
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/4] Add the OTP gpio pinctrl to fix the TSHUT issue
The subject is deleted by my finger. 在 2015年10月20日 17:11, Caesar Wang 写道: We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Tested on box board. Caesar Wang (4): dt-bindings: Sync the dts to this document thermal: rockchip: ensure the otp state before resetting the controller thermal: rockchip: change the TSHUT default state ARM: dts: rockchip: Add the OTP gpio pinctrl .../bindings/thermal/rockchip-thermal.txt | 5 ++-- arch/arm/boot/dts/rk3288.dtsi | 9 -- drivers/thermal/rockchip_thermal.c | 34 +- 3 files changed, 43 insertions(+), 5 deletions(-) -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/3] thermal: rockchip: ensure the otp states before resetting the controller
We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is high. If T > 80C, the OTP output the high signal. If T < 80C, the OTP output the low signal. On the moment, the tshut polarity will be low in a short period of time if the TSADC controller is reset. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang --- Changes in v3: - Add the pinctrl state for in the suspend/resume. Changes in v2: None Changes in v1: None drivers/thermal/rockchip_thermal.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index c89ffb2..3b8fbda 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -642,6 +642,8 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) clk_disable(thermal->pclk); clk_disable(thermal->clk); + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -678,6 +680,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); + pinctrl_pm_select_default_state(dev); + return 0; } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/3] ARM: dts: rockchip: Add the OTP gpio pinctrl
Add the "init" anf "sleep" pinctrl as the OTP gpio state.
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
"init" pinctrl property is defined by Doug's Patch[0].
Patch[0]:
https://patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v3:
- Add the "sleep" pinctrl as the gpio state in PATCH[3/3]
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..13ff09a 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,10 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1275,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/3] dt-bindings: rockchip-thermal: Add the pinctrl states in this document
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" and "sleep" pinctrl as the OTP gpio state, since we need
switch the pin to gpio state before the TSADC controller is reset.
AFAIK, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v3:
- Add the pictrl states decription in document.
Changes in v2:
- Add the 'init' pinctrl more decription in commit.
- Fix the subject to make more obvious in PATCH[1/2]
- Resend this patch v2 since fix the subject to be specific.
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
.../devicetree/bindings/thermal/rockchip-thermal.txt | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..b38200d 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -12,6 +12,11 @@ Required properties:
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the name "tsadc-apb".
+- pinctrl-names : The pin control state names;
+- pinctrl-0 : The "init" pinctrl state, it will be set before device probe.
+- pinctrl-1 : The "default" pinctrl state, it will be set after reset the
+ TSADC controller.
+- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend.
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
@@ -27,8 +32,10 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/3] fix the TSHUT issue on rockchip thermal
Thank you all for providing inputs and comments on previous versions of this patchset. Especially thanks to the (Doug, Rob). We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. This series patchs are depend on Doug's patch.(https://patchwork.kernel.org/patch/7454311/) This series patchs are based on the Linus master branch. 518cd44 ARM: dts: rockchip: Add the OTP gpio pinctrl 83e0bab dt-bindings: Add the "init" pinctrl in this document 150426c drivers/pinctrl: Add the concept of an "init" state ce1fad2 Merge branch 'keys-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 1099f86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 911b79c KEYS: Don't permit request_key() to construct a new keyring 37850e3 net: bcmgenet: Fix early link interrupt enabling afc050d Merge tag 'wireless-drivers-for-davem-2015-10-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers e277de5 tunnels: Don't require remote endpoint or ID during creation. 740dbc2 openvswitch: Scrub skb between namespaces Tested on box board. Changes in v3: - Add the pictrl states decription in document. - Add the pinctrl state for in the suspend/resume. - Add the "sleep" pinctrl as the gpio state in PATCH[3/3] Changes in v2: - Add the 'init' pinctrl more decription in commit. - Fix the subject to make more obvious in PATCH[1/2] - Resend this patch v2 since fix the subject to be specific. - Add some commits for more obvious in PATCH[2/2] Changes in v1: - As the Doug comments, add the 'init' property to sync document. - As the Doug comments, drop the thermal driver patchs since we can with pinctrl changing to work. - As the Doug's patch to add the 'init' property. Caesar Wang (3): dt-bindings: rockchip-thermal: Add the pinctrl states in this document thermal: rockchip: ensure the otp states before resetting the controller ARM: dts: rockchip: Add the OTP gpio pinctrl .../devicetree/bindings/thermal/rockchip-thermal.txt | 11 +-- arch/arm/boot/dts/rk3288.dtsi | 10 -- drivers/thermal/rockchip_thermal.c| 4 3 files changed, 21 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 2/3] thermal: rockchip: ensure the otp states before resetting the controller
在 2015年10月23日 12:04, Doug Anderson 写道: Caesar, On Thu, Oct 22, 2015 at 9:54 PM, Caesar Wang wrote: We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is high. If T > 80C, the OTP output the high signal. If T < 80C, the OTP output the low signal. On the moment, the tshut polarity will be low in a short period of time if the TSADC controller is reset. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang --- Changes in v3: - Add the pinctrl state for in the suspend/resume. Changes in v2: None Changes in v1: None drivers/thermal/rockchip_thermal.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index c89ffb2..3b8fbda 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -642,6 +642,8 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) clk_disable(thermal->pclk); clk_disable(thermal->clk); + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -678,6 +680,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); + pinctrl_pm_select_default_state(dev); + return 0; } The patch looks totally fine, but the description is a little confusing. Reading this patch it's all about adding support for the "sleep" state in the tsadc driver, but nothing in the description talks about that. I'd expect something like: thermal: rockchip: support the sleep pinctrl state to avoid glitches in s2r When we come out of system suspend state (S3) the tsadc will have been reset and back at its default state. While reprogramming the tsadc it's possible that we'll glitch the output and unintentionally cause the "over temperature" GPIO to be asserted. Since the over temperature GPIO is often hooked up to something that will cause a reboot or shutdown in hardware, this glitch can be catastrophic on some boards. We'll add support for selecting the "sleep" pinctrl state at suspend time. Boards can use this to effectively disable the tsadc at suspend time and avoid glitches when the system is resumed. Thanks Doug to take your time reviewing this series patchs. The commit is very good for this patch. --- Note that although this pinctrl approach is fine IMHO, I am left wondering whether we could just change the tsadc init sequence to avoid the glitch. I can't easily test myself, but if we can program the temperatures before re-enabling the tsadc would it avoid the problem too? It's the chip behaviour, the glitches is aways occured by reset controller. The best way need change to the gpio state before reset the controller. Like could we just swap things like: thermal->chip->set_tshut_temp(id, thermal->regs, thermal->hw_shut_temp); thermal->chip->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); Does that help? It didn't work on box board. -Doug ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- Thanks, Caesar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 2/3] thermal: rockchip: ensure the otp states before resetting the controller
在 2015年10月23日 12:04, Doug Anderson 写道: Caesar, On Thu, Oct 22, 2015 at 9:54 PM, Caesar Wang wrote: We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is high. If T > 80C, the OTP output the high signal. If T < 80C, the OTP output the low signal. On the moment, the tshut polarity will be low in a short period of time if the TSADC controller is reset. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. Signed-off-by: Caesar Wang --- Changes in v3: - Add the pinctrl state for in the suspend/resume. Changes in v2: None Changes in v1: None drivers/thermal/rockchip_thermal.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index c89ffb2..3b8fbda 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -642,6 +642,8 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) clk_disable(thermal->pclk); clk_disable(thermal->clk); + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -678,6 +680,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); + pinctrl_pm_select_default_state(dev); + return 0; } The patch looks totally fine, but the description is a little confusing. Reading this patch it's all about adding support for the "sleep" state in the tsadc driver, but nothing in the description talks about that. I'd expect something like: thermal: rockchip: support the sleep pinctrl state to avoid glitches in s2r When we come out of system suspend state (S3) the tsadc will have been reset and back at its default state. While reprogramming the tsadc it's possible that we'll glitch the output and unintentionally cause the "over temperature" GPIO to be asserted. Since the over temperature GPIO is often hooked up to something that will cause a reboot or shutdown in hardware, this glitch can be catastrophic on some boards. We'll add support for selecting the "sleep" pinctrl state at suspend time. Boards can use this to effectively disable the tsadc at suspend time and avoid glitches when the system is resumed. Thanks Doug to take your time reviewing this series patchs. The commit is very good for this patch. --- Note that although this pinctrl approach is fine IMHO, I am left wondering whether we could just change the tsadc init sequence to avoid the glitch. I can't easily test myself, but if we can program the temperatures before re-enabling the tsadc would it avoid the problem too? It's the chip behaviour, the glitches is aways occured by reset controller. The best way need change to the gpio state before reset the controller. Like could we just swap things like: thermal->chip->set_tshut_temp(id, thermal->regs, thermal->hw_shut_temp); thermal->chip->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); Does that help? It didn't work on box board. -Doug ___ Linux-rockchip mailing list linux-rockc...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/3] fix the TSHUT issue on rockchip thermal
Thank you all for providing inputs and comments on previous versions of this patchset. Especially thanks to the (Doug, Rob). We need the OTP pin is gpio state before resetting the TSADC controller, since the tshut polarity will generate a high signal. Says: The TSHUT temperature is setting more than 80 degree, the default tshut polarity is HIGH. If T > 80C, the OTP output the High Signal. If T < 80C, the OTP output the Low Signal. On the moment, the TSADC controller is reset, the tshut polarity will be Low in a short period of time. So: If T < 80C, the OTP output the High Signal. If T > 80C, the OTP output the Low Signal. In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can accept the reset response time to avoid this issue. In other words, the system will be always reboot if we make the OTP pin is connected the others IC to control the power. This series patchs are depend on Doug's patch.(https://patchwork.kernel.org/patch/7454311/) This series patchs are based on the Linus master branch. 518cd44 ARM: dts: rockchip: Add the OTP gpio pinctrl 83e0bab dt-bindings: Add the "init" pinctrl in this document 150426c drivers/pinctrl: Add the concept of an "init" state ce1fad2 Merge branch 'keys-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs 1099f86 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net 911b79c KEYS: Don't permit request_key() to construct a new keyring 37850e3 net: bcmgenet: Fix early link interrupt enabling afc050d Merge tag 'wireless-drivers-for-davem-2015-10-17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers e277de5 tunnels: Don't require remote endpoint or ID during creation. 740dbc2 openvswitch: Scrub skb between namespaces Tested on box board. Changes in v4: - take the Doug's commit as correct decription. Changes in v3: - Add the pictrl states decription in document. - Add the pinctrl state for in the suspend/resume. - Add the "sleep" pinctrl as the gpio state in PATCH[3/3] Changes in v2: - Add the 'init' pinctrl more decription in commit. - Fix the subject to make more obvious in PATCH[1/2] - Resend this patch v2 since fix the subject to be specific. - Add some commits for more obvious in PATCH[2/2] Changes in v1: - As the Doug comments, add the 'init' property to sync document. - As the Doug comments, drop the thermal driver patchs since we can with pinctrl changing to work. - As the Doug's patch to add the 'init' property. Caesar Wang (3): dt-bindings: rockchip-thermal: Add the pinctrl states in this document thermal: rockchip: support the sleep pinctrl state to avoid glitches in s2r ARM: dts: rockchip: Add the OTP gpio pinctrl .../devicetree/bindings/thermal/rockchip-thermal.txt | 11 +-- arch/arm/boot/dts/rk3288.dtsi | 10 -- drivers/thermal/rockchip_thermal.c| 4 3 files changed, 21 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/3] dt-bindings: rockchip-thermal: Add the pinctrl states in this document
The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" and "sleep" pinctrl as the OTP gpio state, since we need
switch the pin to gpio state before the TSADC controller is reset.
AFAIK, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v4: None
Changes in v3:
- Add the pictrl states decription in document.
Changes in v2:
- Add the 'init' pinctrl more decription in commit.
- Fix the subject to make more obvious in PATCH[1/2]
- Resend this patch v2 since fix the subject to be specific.
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
.../devicetree/bindings/thermal/rockchip-thermal.txt | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..b38200d 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -12,6 +12,11 @@ Required properties:
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the name "tsadc-apb".
+- pinctrl-names : The pin control state names;
+- pinctrl-0 : The "init" pinctrl state, it will be set before device probe.
+- pinctrl-1 : The "default" pinctrl state, it will be set after reset the
+ TSADC controller.
+- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend.
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
@@ -27,8 +32,10 @@ tsadc: tsadc@ff28 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 3/3] ARM: dts: rockchip: Add the OTP gpio pinctrl
Add the "init" anf "sleep" pinctrl as the OTP gpio state.
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
"init" pinctrl property is defined by Doug's Patch[0].
Patch[0]:
https://patchwork.kernel.org/patch/7454311/
Signed-off-by: Caesar Wang
Reviewed-by: Douglas Anderson
---
Changes in v4: None
Changes in v3:
- Add the "sleep" pinctrl as the gpio state in PATCH[3/3]
Changes in v2:
- Add some commits for more obvious in PATCH[2/2]
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..13ff09a 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,10 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1275,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO
&pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1
&pcfg_pull_none>;
};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 2/3] thermal: rockchip: support the sleep pinctrl state to avoid glitches in s2r
When we come out of system suspend state (S3) the tsadc will have been reset and back at its default state. While reprogramming the tsadc it's possible that we'll glitch the output and unintentionally cause the "over temperature" GPIO to be asserted. Since the over temperature GPIO is often hooked up to something that will cause a reboot or shutdown in hardware, this glitch can be catastrophic on some boards. We'll add support for selecting the "sleep" pinctrl state at suspend time. Boards can use this to effectively disable the tsadc at suspend time and avoid glitches when the system is resumed. Signed-off-by: Caesar Wang --- Changes in v4: - take the Doug's commit as correct decription. Changes in v3: - Add the pinctrl state for in the suspend/resume. Changes in v2: None Changes in v1: None drivers/thermal/rockchip_thermal.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index c89ffb2..3b8fbda 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -642,6 +642,8 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) clk_disable(thermal->pclk); clk_disable(thermal->clk); + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -678,6 +680,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++) rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); + pinctrl_pm_select_default_state(dev); + return 0; } -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 1/3] dt-bindings: rockchip-mailbox: Add mailbox controller document on Rockchip SoCs
This add the necessary binding documentation for mailbox
found on RK3368 SoC.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[1/3] doc:
- As the Rob Herring comments, s/share/shared/ and specify the value of
#mbox-cells.
- Move the shared memory in mailbox, let's move the property the client
driver in the future.
.../bindings/mailbox/rockchip-mailbox.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
new file mode 100644
index 000..b6bb84a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
@@ -0,0 +1,32 @@
+Rockchip mailbox
+
+The Rockchip mailbox is used by the Rockchip CPU cores to communicate
+requests to MCU processor.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Required properties:
+
+ - compatible: should be one of the following.
+ - "rockchip,rk3368-mbox" for rk3368
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+ - #mbox-cells: Common mailbox binding property to identify the number
+ of cells required for the mailbox specifier. Should be 1
+
+Example:
+
+
+/* RK3368 */
+mbox: mbox@ff6b {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b 0x0 0x1000>,
+ interrupts = ,
+,
+,
+;
+ #mbox-cells = <1>;
+};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/3] mailbox: rockchip: Add mailbox driver for Rockchip platform
Mailbox is used by the Rockchip CPU cores to communicate requests to MCU processor. This driver is found on RK3368 SoCs. The Mailbox module is a simple APB peripheral that allows both the Cortex-A53 MCU system to communicate by writing operation to generate interrupt. The registers are accessible by both CPU via APB interface. Tested on RK3368 SDK board. Changes in v1: - PATCH[1/3] doc: - As the Rob Herring comments, s/share/shared/ and specify the value of #mbox-cells. - Move the shared memory in mailbox, let's move the property the client driver in the future. - PATCH[2/3] driver: - The commit: %s/@/(num order). - Add the module authors to instead of the notes. - Add the COMPILE_TEST to auto compile test in Kconfig. - Let the chan_to_idx() trys to instead of rockchip_mbox_chan.idx. - Let's enable/disable the interrupt in startup/shutdown. - Move the share memory and tx buf into the client drivers. - PATCH[3/3] dts: - fix "processormZ"--> "processor",the miss-fingerboard. - Remove the shared memory in mailbox controller dtsi. Caesar Wang (3): dt-bindings: rockchip-mailbox: Add mailbox controller document on Rockchip SoCs mailbox: rockchip: Add Rockchip mailbox driver ARM64: dts: rk3368: Add mailbox device nodes .../bindings/mailbox/rockchip-mailbox.txt | 32 +++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 + drivers/mailbox/Kconfig| 9 + drivers/mailbox/Makefile | 2 + drivers/mailbox/rockchip-mailbox.c | 286 + 5 files changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt create mode 100644 drivers/mailbox/rockchip-mailbox.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/3] mailbox: rockchip: Add Rockchip mailbox driver
This driver is found on RK3368 SoCs.
The Mailbox module is a simple APB peripheral that allows both
the Cortex-A53 MCU system to communicate by writing operation to
generate interrupt.
The registers are accessible by both CPU via APB interface.
The Mailbox has the following main features:
1) Support dual-core system: Cortex-A53 and MCU.
2) Support APB interface.
3) Support four mailbox elements, each element includes one data word,
one command word register and one flag bit that can represent
one interrupt.
4) Four interrupts to Cortex-A53.
5) Four interrupts to MCU.
6) Provide 32 lock registers for software to use to indicate whether
mailbox is occupied.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[2/3] driver:
- The commit: %s/@/(num order).
- Add the module authors to instead of the notes.
- Add the COMPILE_TEST to auto compile test in Kconfig.
- Let the chan_to_idx() trys to instead of rockchip_mbox_chan.idx.
- Let's enable/disable the interrupt in startup/shutdown.
- Move the share memory and tx buf into the client drivers.
drivers/mailbox/Kconfig| 9 ++
drivers/mailbox/Makefile | 2 +
drivers/mailbox/rockchip-mailbox.c | 286 +
3 files changed, 297 insertions(+)
create mode 100644 drivers/mailbox/rockchip-mailbox.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index bbec500..8b8d46e 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -43,6 +43,15 @@ config OMAP_MBOX_KFIFO_SIZE
This can also be changed at runtime (via the mbox_kfifo_size
module parameter).
+config ROCKCHIP_MBOX
+ bool "Rockchip Soc Intergrated Mailbox Support"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ help
+ This driver provides support for inter-processor communication
+ between CPU cores and MCU processor on Some Rockchip SOCs.
+ Please check it that the Soc you use have Mailbox hardware.
+ Say Y here if you want to use the Rockchip Mailbox support.
+
config PCC
bool "Platform Communication Channel Driver"
depends on ACPI
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 8e6d822..730cb5d 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -8,6 +8,8 @@ obj-$(CONFIG_PL320_MBOX)+= pl320-ipc.o
obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
+obj-$(CONFIG_ROCKCHIP_MBOX)+= rockchip-mailbox.o
+
obj-$(CONFIG_PCC) += pcc.o
obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o
diff --git a/drivers/mailbox/rockchip-mailbox.c
b/drivers/mailbox/rockchip-mailbox.c
new file mode 100644
index 000..5ccdc6b
--- /dev/null
+++ b/drivers/mailbox/rockchip-mailbox.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MAILBOX_A2B_INTEN 0x00
+#define MAILBOX_A2B_STATUS 0x04
+#define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
+#define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
+
+#define MAILBOX_B2A_INTEN 0x28
+#define MAILBOX_B2A_STATUS 0x2C
+#define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
+#define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
+
+struct rockchip_mbox_msg {
+ u32 cmd;
+ int rx_size;
+};
+
+struct rockchip_mbox_data {
+ int num_chans;
+};
+
+struct rockchip_mbox_chan {
+ int idx;
+ int irq;
+ struct rockchip_mbox_msg *msg;
+ struct rockchip_mbox *mb;
+};
+
+struct rockchip_mbox {
+ struct mbox_controller mbox;
+ struct clk *pclk;
+ void __iomem *mbox_base;
+
+ /* The base address of share memory to transfer data */
+ void __iomem *buf_base;
+
+ /* The maximum size of buf for each channel */
+ u32 buf_size;
+
+ struct rockchip_mbox_chan *chans;
+};
+
+static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
+ struct rockchip_mbox_msg *msg = data;
+ struct rockchip_mbox_chan *chans = mb->chans;
+
+ if (!msg)
+ return -EINVAL;
+
+ if (msg->rx_size > mb->buf_size) {
+ dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
+ mb->buf_size);
+ return -EINVAL;
+ }
+
+
[PATCH v1 3/3] ARM64: dts: rk3368: Add mailbox device nodes
This adds mailbox device nodes in dts.
Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.
Signed-off-by: Caesar Wang
---
Changes in v1:
- PATCH[3/3] dts:
- fix "processormZ"--> "processor",the miss-fingerboard.
- Remove the shared memory in mailbox controller dtsi.
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index cc093a4..cefdad3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -484,6 +484,18 @@
status = "disabled";
};
+ mbox: mbox@ff6b {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b 0x0 0x1000>,
+ interrupts = ,
+,
+,
+;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ };
+
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/2] phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy
As we communicate through QQ, Shawn had been on vacation util next week.
在 2018年01月11日 01:46, Brian Norris 写道:
+ Caesar
IIUC, you didn't CC him? Also, he already sent a v2 of this patchset,
withi some minor difference.
On Wed, Jan 10, 2018 at 06:49:22PM +0800, Shawn Lin wrote:
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Tested-by: Caesar Wang
Tested-by: Ziyuan Xu
---
Changes in v2:
- propagate the error and print it
- avoid using busy wait
drivers/phy/rockchip/phy-rockchip-emmc.c | 32 +---
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index 547b746..e54e78f 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -79,6 +79,9 @@
#define PHYCTRL_IS_CALDONE(x) \
x) >> PHYCTRL_CALDONE_SHIFT) & \
PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+#define PHYCTRL_IS_DLLRDY(x) \
+ x) >> PHYCTRL_DLLRDY_SHIFT) & \
+ PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
struct rockchip_emmc_phy {
unsigned intreg_offset;
@@ -93,7 +96,6 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
unsigned int dllrdy;
unsigned int freqsel = PHYCTRL_FREQSEL_200M;
unsigned long rate;
- unsigned long timeout;
int ret;
/*
@@ -217,28 +219,20 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
I'd probably like Doug's comment on the comment rewording (and
functional change) since he wrote them in the first place, but this is
also where you and Caesar differed. Caesar just deleted most of the last
paragraph, because it really applied just to the busy wait loop, not
really to the sleep-based loop that you're putting in here.
* NOTE: There appear to be corner cases where the DLL seems to take
* extra long to lock for reasons that aren't understood. In some
* extreme cases we've seen it take up to over 10ms (!). We'll be
-* generous and give it 50ms. We still busy wait here because:
+* generous and give it 50ms. We still wait here because:
* - In most cases it should be super fast.
* - This is not called lots during normal operation so it shouldn't
-* be a power or performance problem to busy wait. We expect it
+* be a power or performance problem to wait. We expect it
Why would it be a power problem to just "wait"? (Hint: it was only a
potential power problem to *busy* wait, where we're spinning in a tight
loop.)
* only at boot / resume. In both cases, eMMC is probably on the
-* critical path so busy waiting a little extra time should be OK.
+* critical path so waiting a little extra time should be OK.
If we all agree that the above *performance* reasoning is not important,
then it should be fine to do the conversion to the sleep/polling macro,
and I think the best comment is just to delete all the above about power
and performance of this wait loop. It was only necessary to justify the
udelay() loop.
Just confirmed with Shawn, we can delete the above isn't important reason.
So IOW, I think Caesar's version was better :)
Otherwise, my 'Reviewed-by' for both series stands.
Doug, do you have any thoughts? Or at least Caesar and Shawn: please
choose one of your patch series, not both!
Brian
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &dllrdy);
- dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
- if (dllrdy == PHYCTRL_DLLRDY_DONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (dllrdy != PHYCTRL_DLLRDY_DONE) {
- pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
+ 1, 50 * USEC_PER_MSEC);
+ if (ret) {
+ pr_err("%s: dllrdy failed %d.\n", __func__, ret);
+ return ret;
}
return 0;
--
1.9.1
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
Re: [PATCH v2 2/2] phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy
在 2018年01月11日 03:36, Doug Anderson 写道:
Hi,
On Wed, Jan 10, 2018 at 9:46 AM, Brian Norris wrote:
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &dllrdy);
- dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
- if (dllrdy == PHYCTRL_DLLRDY_DONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (dllrdy != PHYCTRL_DLLRDY_DONE) {
- pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
+1, 50 * USEC_PER_MSEC);
It seems a bit schizophrenic that one of our delay loops sleeps 1 us
between loops and the other sleeps 5 us between loops.
...and, in fact, both of these numbers seem a little on the silly side
of things. Assuming that the timer docs are up to date, usleep_range
is intended for sleeping "10us - 20ms". Both 1 us and 5 us below that
range and "1 us" is an order of magnitude below that range. ...your 1
and 5 actually translate to usleep_range(1, 1) and usleep_range(3, 5).
It seems like trying to do a sleep (the whole idea that some other
process will get to run for some fraction of the 1 us) is just wasting
cycles.
So I'd say either:
1. Accept that we really expect this to be a long delay and change
your delay to 10 us
2. Change the delay to 0 us and accept that you're busy waiting.
I'd vote for #2 unless you have some evidence that we often need long
delays and we've started calling this code all the time.
Agreed with #2
-Caesar
+ if (ret) {
+ pr_err("%s: dllrdy failed %d.\n", __func__, ret);
+ return ret;
}
return 0;
--
1.9.1
___
Linux-rockchip mailing list
linux-rockc...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
[PATCH v3 2/2] phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on https://patchwork.kernel.org/patch/10154797,
Change "1, 50" to "0, 50".
Changes in v2:
- As Brian commented on https://patchwork.kernel.org/patch/10139891/,
changed the note and added to print error value with
regmap_read_poll_timeout API.
drivers/phy/rockchip/phy-rockchip-emmc.c | 33 +++-
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index b0d1093..b237360 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -79,6 +79,9 @@
#define PHYCTRL_IS_CALDONE(x) \
x) >> PHYCTRL_CALDONE_SHIFT) & \
PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+#define PHYCTRL_IS_DLLRDY(x) \
+ x) >> PHYCTRL_DLLRDY_SHIFT) & \
+ PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
struct rockchip_emmc_phy {
unsigned intreg_offset;
@@ -93,7 +96,6 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
unsigned int dllrdy;
unsigned int freqsel = PHYCTRL_FREQSEL_200M;
unsigned long rate;
- unsigned long timeout;
int ret;
/*
@@ -217,28 +219,15 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
* NOTE: There appear to be corner cases where the DLL seems to take
* extra long to lock for reasons that aren't understood. In some
* extreme cases we've seen it take up to over 10ms (!). We'll be
-* generous and give it 50ms. We still busy wait here because:
-* - In most cases it should be super fast.
-* - This is not called lots during normal operation so it shouldn't
-* be a power or performance problem to busy wait. We expect it
-* only at boot / resume. In both cases, eMMC is probably on the
-* critical path so busy waiting a little extra time should be OK.
+* generous and give it 50ms.
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &dllrdy);
- dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
- if (dllrdy == PHYCTRL_DLLRDY_DONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (dllrdy != PHYCTRL_DLLRDY_DONE) {
- pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
+ 0, 50 * USEC_PER_MSEC);
+ if (ret) {
+ pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
+ return ret;
}
return 0;
--
2.7.4
[PATCH v3 1/2] phy: rockchip-emmc: retry calpad busy trimming
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v3:
- As Doug commented on both upstream and gerrit.
Change "5, 50" to "0, 50", and the message of print.
Changes in v2:
- print the return valut with regmap_read_poll_timeout failing.
drivers/phy/rockchip/phy-rockchip-emmc.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index f1b24f1..b0d1093 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -76,6 +76,10 @@
#define PHYCTRL_OTAPDLYSEL_MASK0xf
#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
+#define PHYCTRL_IS_CALDONE(x) \
+ x) >> PHYCTRL_CALDONE_SHIFT) & \
+ PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+
struct rockchip_emmc_phy {
unsigned intreg_offset;
struct regmap *reg_base;
@@ -90,6 +94,7 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
unsigned int freqsel = PHYCTRL_FREQSEL_200M;
unsigned long rate;
unsigned long timeout;
+ int ret;
/*
* Keep phyctrl_pdb and phyctrl_endll low to allow
@@ -160,17 +165,19 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
PHYCTRL_PDB_SHIFT));
/*
-* According to the user manual, it asks driver to
-* wait 5us for calpad busy trimming
+* According to the user manual, it asks driver to wait 5us for
+* calpad busy trimming. However it is documented that this value is
+* PVT(A.K.A process,voltage and temperature) relevant, so some
+* failure cases are found which indicates we should be more tolerant
+* to calpad busy trimming.
*/
- udelay(5);
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &caldone);
- caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
- if (caldone != PHYCTRL_CALDONE_DONE) {
- pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ caldone, PHYCTRL_IS_CALDONE(caldone),
+ 0, 50);
+ if (ret) {
+ pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
+ return ret;
}
/* Set the frequency of the DLL operation */
--
2.7.4
[PATCH v3 0/2] phy: rockchip-emmc: fixes emmc-phy power on failed with rk3399 SoCs
Hi Kishon, Since the Shawn isn't available, I take over this series patches for now. As the original bug had tracked on https://issuetracker.google.com/71561742. In some cases, the mmc phy power on failed during booting up. The log as below: ... [ 2.375333] rockchip_emmc_phy_power: caldone timeout. [2.377815] phy phy-ff77.syscon:phy@f780.4: phy poweron failed --> -110 ... [2.489295] mmc0: mmc_select_hs400es failed, error -110 [2.489302] mmc0: error -110 whilst initialising MMC card .. The actual emulate, the wait 5us for calpad busy trimming, that's no enough. We need give the enough margin for it. Verified on url = https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.4 This series patches can apply and bring up with kernel-next on rk3399 chromebook. -Caesar Changes in v3: - As Doug commented on both upstream and gerrit. Change "5, 50" to "0, 50", and the message of print. - As Doug commented on https://patchwork.kernel.org/patch/10154797, Change "1, 50" to "0, 50". Changes in v2: - print the return valut with regmap_read_poll_timeout failing. - As Brian commented on https://patchwork.kernel.org/patch/10139891/, changed the note and added to print error value with regmap_read_poll_timeout API. Shawn Lin (2): phy: rockchip-emmc: retry calpad busy trimming phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy drivers/phy/rockchip/phy-rockchip-emmc.c | 60 +++- 1 file changed, 28 insertions(+), 32 deletions(-) -- 2.7.4
Re: [PATCH 1/2] phy: rockchip-emmc: retry calpad busy trimming
Hi Kishon & Shawn,
As the bug had tracked on https://issuetracker.google.com/71561742.
In some cases, the mmc phy power on failed during booting up.
The log as below:
...
[ 2.375333] rockchip_emmc_phy_power: caldone timeout.
[ 2.377815] phy phy-ff77.syscon:phy@f780.4: phy poweron failed
--> -110
...
[ 2.489295] mmc0: mmc_select_hs400es failed, error -110
[ 2.489302] mmc0: error -110 whilst initialising MMC card
..
在 2018年01月02日 10:21, Shawn Lin 写道:
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Caesar Wang
I had tested on rk3399 chromebook, so feel free to add my tag.
-Caesar
---
drivers/phy/rockchip/phy-rockchip-emmc.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index f1b24f1..512a6ef 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -76,6 +76,10 @@
#define PHYCTRL_OTAPDLYSEL_MASK 0xf
#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
+#define PHYCTRL_IS_CALDONE(x) \
+ x) >> PHYCTRL_CALDONE_SHIFT) & \
+ PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+
struct rockchip_emmc_phy {
unsigned intreg_offset;
struct regmap *reg_base;
@@ -160,15 +164,16 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
PHYCTRL_PDB_SHIFT));
/*
-* According to the user manual, it asks driver to
-* wait 5us for calpad busy trimming
+* According to the user manual, it asks driver to wait 5us for
+* calpad busy trimming. However it is documented that this value is
+* PVT(A.K.A process,voltage and temperature) relevant, so some
+* failure cases are found which indicates we should be more tolerant
+* to calpad busy trimming.
*/
- udelay(5);
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &caldone);
- caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
- if (caldone != PHYCTRL_CALDONE_DONE) {
+ if (regmap_read_poll_timeout(rk_phy->reg_base,
+rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+caldone, PHYCTRL_IS_CALDONE(caldone),
+5, 50)) {
pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
return -ETIMEDOUT;
}
[PATCH v2 1/2] phy: rockchip-emmc: retry calpad busy trimming
From: Shawn Lin
It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.
Signed-off-by: Shawn Lin
Tested-by: Ziyuan Xu
Signed-off-by: Caesar Wang
---
Changes in v2:
- print the return valut with regmap_read_poll_timeout failing.
drivers/phy/rockchip/phy-rockchip-emmc.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index f1b24f1..574838f 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -76,6 +76,10 @@
#define PHYCTRL_OTAPDLYSEL_MASK0xf
#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
+#define PHYCTRL_IS_CALDONE(x) \
+ x) >> PHYCTRL_CALDONE_SHIFT) & \
+ PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+
struct rockchip_emmc_phy {
unsigned intreg_offset;
struct regmap *reg_base;
@@ -90,6 +94,7 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
unsigned int freqsel = PHYCTRL_FREQSEL_200M;
unsigned long rate;
unsigned long timeout;
+ int ret;
/*
* Keep phyctrl_pdb and phyctrl_endll low to allow
@@ -160,17 +165,19 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
PHYCTRL_PDB_SHIFT));
/*
-* According to the user manual, it asks driver to
-* wait 5us for calpad busy trimming
+* According to the user manual, it asks driver to wait 5us for
+* calpad busy trimming. However it is documented that this value is
+* PVT(A.K.A process,voltage and temperature) relevant, so some
+* failure cases are found which indicates we should be more tolerant
+* to calpad busy trimming.
*/
- udelay(5);
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &caldone);
- caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
- if (caldone != PHYCTRL_CALDONE_DONE) {
- pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ caldone, PHYCTRL_IS_CALDONE(caldone),
+ 5, 50);
+ if (ret) {
+ pr_err("%s: caldone timeout, ret=%d\n", __func__, ret);
+ return ret;
}
/* Set the frequency of the DLL operation */
--
2.7.4
[PATCH v2 0/2] phy: rockchip-emmc: fixes emmc-phy power on failed with rk3399 SoCs
Hi Kishon, Since the Shawn isn't available, I take over this series patches for now. As the original bug had tracked on https://issuetracker.google.com/71561742. In some cases, the mmc phy power on failed during booting up. The log as below: ... [ 2.375333] rockchip_emmc_phy_power: caldone timeout. [2.377815] phy phy-ff77.syscon:phy@f780.4: phy poweron failed --> -110 ... [2.489295] mmc0: mmc_select_hs400es failed, error -110 [2.489302] mmc0: error -110 whilst initialising MMC card .. The actual emulate, the wait 5us for calpad busy trimming, that's no enough. We need give the enough margin for it. Verified on url = https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.4 This series patches can apply and bring up with kernel-next on rk3399 chromebook. -Caesar Changes in v2: - print the return valut with regmap_read_poll_timeout failing. - As Brian commented on https://patchwork.kernel.org/patch/10139891/, changed the note and added to print error value with regmap_read_poll_timeout API. Shawn Lin (2): phy: rockchip-emmc: retry calpad busy trimming phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy drivers/phy/rockchip/phy-rockchip-emmc.c | 60 +++- 1 file changed, 28 insertions(+), 32 deletions(-) -- 2.7.4
[PATCH v2 2/2] phy: rockchip-emmc: use regmap_read_poll_timeout to poll dllrdy
From: Shawn Lin
Just use the API instead of open-coding it, no functional change
intended.
Signed-off-by: Shawn Lin
Reviewed-by: Brian Norris
Signed-off-by: Caesar Wang
---
Changes in v2:
- As Brian commented on https://patchwork.kernel.org/patch/10139891/,
changed the note and added to print error value with
regmap_read_poll_timeout API.
drivers/phy/rockchip/phy-rockchip-emmc.c | 33 +++-
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c
b/drivers/phy/rockchip/phy-rockchip-emmc.c
index 574838f..343c623 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -79,6 +79,9 @@
#define PHYCTRL_IS_CALDONE(x) \
x) >> PHYCTRL_CALDONE_SHIFT) & \
PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
+#define PHYCTRL_IS_DLLRDY(x) \
+ x) >> PHYCTRL_DLLRDY_SHIFT) & \
+ PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
struct rockchip_emmc_phy {
unsigned intreg_offset;
@@ -93,7 +96,6 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
unsigned int dllrdy;
unsigned int freqsel = PHYCTRL_FREQSEL_200M;
unsigned long rate;
- unsigned long timeout;
int ret;
/*
@@ -217,28 +219,15 @@ static int rockchip_emmc_phy_power(struct phy *phy, bool
on_off)
* NOTE: There appear to be corner cases where the DLL seems to take
* extra long to lock for reasons that aren't understood. In some
* extreme cases we've seen it take up to over 10ms (!). We'll be
-* generous and give it 50ms. We still busy wait here because:
-* - In most cases it should be super fast.
-* - This is not called lots during normal operation so it shouldn't
-* be a power or performance problem to busy wait. We expect it
-* only at boot / resume. In both cases, eMMC is probably on the
-* critical path so busy waiting a little extra time should be OK.
+* generous and give it 50ms.
*/
- timeout = jiffies + msecs_to_jiffies(50);
- do {
- udelay(1);
-
- regmap_read(rk_phy->reg_base,
- rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
- &dllrdy);
- dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
- if (dllrdy == PHYCTRL_DLLRDY_DONE)
- break;
- } while (!time_after(jiffies, timeout));
-
- if (dllrdy != PHYCTRL_DLLRDY_DONE) {
- pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
- return -ETIMEDOUT;
+ ret = regmap_read_poll_timeout(rk_phy->reg_base,
+ rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+ dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
+ 1, 50 * USEC_PER_MSEC);
+ if (ret) {
+ pr_err("%s: dllrdy timeout. ret=%d\n", __func__, ret);
+ return ret;
}
return 0;
--
2.7.4
Re: [PATCH v2 17/19] mailbox: rockchip: Use device-managed registration API
On 2018/12/17 下午11:02, Thierry Reding wrote:
From: Thierry Reding
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.
Reviewed-by: Caesar Wang
Thanks,
Caesar
Cc: Caesar Wang
Signed-off-by: Thierry Reding
---
drivers/mailbox/rockchip-mailbox.c | 15 +--
1 file changed, 1 insertion(+), 14 deletions(-)
diff --git a/drivers/mailbox/rockchip-mailbox.c
b/drivers/mailbox/rockchip-mailbox.c
index d702a204f5c1..f24a77b1a0ff 100644
--- a/drivers/mailbox/rockchip-mailbox.c
+++ b/drivers/mailbox/rockchip-mailbox.c
@@ -247,28 +247,15 @@ static int rockchip_mbox_probe(struct platform_device
*pdev)
mb->chans[i].msg = NULL;
}
- ret = mbox_controller_register(&mb->mbox);
+ ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
if (ret < 0)
dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
return ret;
}
-static int rockchip_mbox_remove(struct platform_device *pdev)
-{
- struct rockchip_mbox *mb = platform_get_drvdata(pdev);
-
- if (!mb)
- return -EINVAL;
-
- mbox_controller_unregister(&mb->mbox);
-
- return 0;
-}
-
static struct platform_driver rockchip_mbox_driver = {
.probe = rockchip_mbox_probe,
- .remove = rockchip_mbox_remove,
.driver = {
.name = "rockchip-mailbox",
.of_match_table = of_match_ptr(rockchip_mbox_of_match),
--
王晓腾 | 系统产品三部 | 软件工程师
Caesar Wang | Product R&D Dept.III | Software engineer
**
福州瑞芯微电子股份有限公司
Fuzhou Rockchip Electronics Co.Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区20号楼 (福州总部)
Addr: No.20 Building, A District, Fuzhou Software Park.Gulou
District,Fuzhou,Fujian,China(Fuzhou Headquarters)
Tel：+86-0591-83991906-8221
Mobile: +86 15059456742
E-mail: w...@rock-chips.com
*
保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、
使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。
福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。
IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The
contents of this
email and any attachments may contain information that is privileged,
confidential and/or exempt from disclosure under applicable law and relevant
NDA.
If you are not the intended recipient, you are hereby notified that any
disclosure, copying, distribution, or use of the information is STRICTLY
PROHIBITED.
Please immediately contact the sender as soon as possible and destroy the
material in its entirety in any format. Thank you.
[PATCH v4] thermal: rockchip: make temperature reporting much more accurate
In general, the kernel should report temperature readings exactly as
reported by the hardware. The cpu / gpu thermal driver works in 5 degree
increments,but we ought to do more accurate. The temperature will do
linear interpolation between the entries in the table.
Test= $md5sum /dev/zero &
$while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;
sleep .5; done
e.g. We can get the result as follows:
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39086
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v4:
"return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)"
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
drivers/thermal/rockchip_thermal.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index 1bcddfc..6267349 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -193,19 +193,22 @@ static u32 rk_tsadcv2_temp_to_code(long temp)
static long rk_tsadcv2_code_to_temp(u32 code)
{
- int high, low, mid;
-
- low = 0;
- high = ARRAY_SIZE(v2_code_table) - 1;
- mid = (high + low) / 2;
+ unsigned int low = 0;
+ unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
+ unsigned int mid = (low + high) / 2;
+ unsigned int num;
+ unsigned long denom;
+ /* No code available, return -EAGAIN */
if (code > v2_code_table[low].code || code < v2_code_table[high].code)
- return 125000; /* No code available, return max temperature */
+ return -EAGAIN;
while (low <= high) {
- if (code >= v2_code_table[mid].code && code <
- v2_code_table[mid - 1].code)
- return v2_code_table[mid].temp;
+ if (code >= v2_code_table[mid].code &&
+ code < v2_code_table[mid - 1].code)
+ break;
+ else if (code == TSADCV2_DATA_MASK)
+ break;
else if (code < v2_code_table[mid].code)
low = mid + 1;
else
@@ -213,7 +216,16 @@ static long rk_tsadcv2_code_to_temp(u32 code)
mid = (low + high) / 2;
}
- return 125000;
+ /*
+* The 5C granularity provided by the table is too much. Let's
+* assume that the relationship between sensor readings and
+* temperature between 2 table entries is linear and interpolate
+* to produce less granular result.
+*/
+ num = v2_code_table[mid].temp - v2_code_table[mid - 1].temp;
+ num *= v2_code_table[mid - 1].code - code;
+ denom = v2_code_table[mid - 1].code - v2_code_table[mid].code;
+ return v2_code_table[mid - 1].temp + (num / denom);
}
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/1] thermal: rockchip: make temperature reporting much more accurate
This patch is merged on chromiumos/third_party/kernel. https://chromium-review.googlesource.com/#/c/239190/ Tested on veyron boards. Changes in v4: "return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)" Changes in v3: Suggested-by Daniel Kurtz, the check doesn't reject "code == 0xfff" Fixed in rk_tsadcv2_code_to_temp(u32 code) Changes in v2: Reviewed-by: Dmitry Torokhov Caesar Wang (1): thermal: rockchip: make temperature reporting much more accurate drivers/thermal/rockchip_thermal.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5 0/1] thermal: rockchip: make temperature reporting much more accurate
This patch is merged on chromiumos/third_party/kernel. https://chromium-review.googlesource.com/#/c/239190/ Tested on veyron boards. Changes in v5: Fixed some style. Changes in v4: "return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)" Changes in v3: Suggested-by Daniel Kurtz, the check doesn't reject "code == 0xfff" Fixed in rk_tsadcv2_code_to_temp(u32 code) Changes in v2: Reviewed-by: Dmitry Torokhov Caesar Wang (1): thermal: rockchip: make temperature reporting much more accurate drivers/thermal/rockchip_thermal.c | 38 +- 1 file changed, 25 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v5] thermal: rockchip: make temperature reporting much more accurate
In general, the kernel should report temperature readings exactly as
reported by the hardware. The cpu / gpu thermal driver works in 5 degree
increments,but we ought to do more accurate. The temperature will do
linear interpolation between the entries in the table.
Test= $md5sum /dev/zero &
$while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;
sleep .5; done
e.g. We can get the result as follows:
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39086
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v5:
Fixed some style.
Changes in v4:
"return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)"
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
drivers/thermal/rockchip_thermal.c | 38 +-
1 file changed, 25 insertions(+), 13 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index 1bcddfc..83bdf82 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -193,19 +193,22 @@ static u32 rk_tsadcv2_temp_to_code(long temp)
static long rk_tsadcv2_code_to_temp(u32 code)
{
- int high, low, mid;
-
- low = 0;
- high = ARRAY_SIZE(v2_code_table) - 1;
- mid = (high + low) / 2;
-
- if (code > v2_code_table[low].code || code < v2_code_table[high].code)
- return 125000; /* No code available, return max temperature */
+ unsigned int low = 0;
+ unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
+ unsigned int mid = (low + high) / 2;
+ unsigned int num;
+ unsigned long denom;
+
+ /* Invalid code, return -EAGAIN */
+ if (code > TSADCV2_DATA_MASK)
+ return -EAGAIN;
- while (low <= high) {
- if (code >= v2_code_table[mid].code && code <
- v2_code_table[mid - 1].code)
- return v2_code_table[mid].temp;
+ while (low <= high && mid) {
+ if (code >= v2_code_table[mid].code &&
+ code < v2_code_table[mid - 1].code)
+ break;
+ else if (code == TSADCV2_DATA_MASK)
+ break;
else if (code < v2_code_table[mid].code)
low = mid + 1;
else
@@ -213,7 +216,16 @@ static long rk_tsadcv2_code_to_temp(u32 code)
mid = (low + high) / 2;
}
- return 125000;
+ /*
+* The 5C granularity provided by the table is too much. Let's
+* assume that the relationship between sensor readings and
+* temperature between 2 table entries is linear and interpolate
+* to produce less granular result.
+*/
+ num = v2_code_table[mid].temp - v2_code_table[mid - 1].temp;
+ num *= v2_code_table[mid - 1].code - code;
+ denom = v2_code_table[mid - 1].code - v2_code_table[mid].code;
+ return v2_code_table[mid - 1].temp + (num / denom);
}
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6] thermal: rockchip: make temperature reporting much more accurate
In general, the kernel should report temperature readings exactly as
reported by the hardware. The cpu / gpu thermal driver works in 5 degree
increments,but we ought to do more accurate. The temperature will do
linear interpolation between the entries in the table.
Test= $md5sum /dev/zero &
$while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;
sleep .5; done
e.g. We can get the result as follows:
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39086
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
Reviewed-by: Daniel Kurtz
---
Changes in v6:
It's not really need,so delete the follows:
else if (code == TSADCV2_DATA_MASK)
Changes in v5:
Fixed some style.
Changes in v4:
"return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)"
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject "code == 0xfff"
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov
drivers/thermal/rockchip_thermal.c | 36 +++-
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index 1bcddfc..19553e9 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -193,19 +193,20 @@ static u32 rk_tsadcv2_temp_to_code(long temp)
static long rk_tsadcv2_code_to_temp(u32 code)
{
- int high, low, mid;
-
- low = 0;
- high = ARRAY_SIZE(v2_code_table) - 1;
- mid = (high + low) / 2;
-
- if (code > v2_code_table[low].code || code < v2_code_table[high].code)
- return 125000; /* No code available, return max temperature */
+ unsigned int low = 0;
+ unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
+ unsigned int mid = (low + high) / 2;
+ unsigned int num;
+ unsigned long denom;
+
+ /* Invalid code, return -EAGAIN */
+ if (code > TSADCV2_DATA_MASK)
+ return -EAGAIN;
- while (low <= high) {
- if (code >= v2_code_table[mid].code && code <
- v2_code_table[mid - 1].code)
- return v2_code_table[mid].temp;
+ while (low <= high && mid) {
+ if (code >= v2_code_table[mid].code &&
+ code < v2_code_table[mid - 1].code)
+ break;
else if (code < v2_code_table[mid].code)
low = mid + 1;
else
@@ -213,7 +214,16 @@ static long rk_tsadcv2_code_to_temp(u32 code)
mid = (low + high) / 2;
}
- return 125000;
+ /*
+* The 5C granularity provided by the table is too much. Let's
+* assume that the relationship between sensor readings and
+* temperature between 2 table entries is linear and interpolate
+* to produce less granular result.
+*/
+ num = v2_code_table[mid].temp - v2_code_table[mid - 1].temp;
+ num *= v2_code_table[mid - 1].code - code;
+ denom = v2_code_table[mid - 1].code - v2_code_table[mid].code;
+ return v2_code_table[mid - 1].temp + (num / denom);
}
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6 0/1] thermal: rockchip: make temperature reporting much more accurate
This patch is merged on chromiumos/third_party/kernel. https://chromium-review.googlesource.com/#/c/239190/ Tested on veyron boards. Changes in v6: It's not really need,so delete the follows: else if (code == TSADCV2_DATA_MASK) Changes in v5: Fixed some style. Changes in v4: "return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)" Changes in v3: Suggested-by Daniel Kurtz, the check doesn't reject "code == 0xfff" Fixed in rk_tsadcv2_code_to_temp(u32 code) Changes in v2: Reviewed-by: Dmitry Torokhov Caesar Wang (1): thermal: rockchip: make temperature reporting much more accurate drivers/thermal/rockchip_thermal.c | 36 +++- 1 file changed, 23 insertions(+), 13 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 0/1] thermal: rockchip: make temperature reporting much more accurate
This patch is merged on chromiumos/third_party/kernel. https://chromium-review.googlesource.com/#/c/239190/ Tested on veyron boards. Caesar Wang (1): thermal: rockchip: make temperature reporting much more accurate drivers/thermal/rockchip_thermal.c | 26 +- 1 file changed, 17 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1] thermal: rockchip: make temperature reporting much more accurate
In general, the kernel should report temperature readings exactly as
reported by the hardware. The cpu / gpu thermal driver works in 5 degree
increments,but we ought to do more accurate. The temperature will do
linear interpolation between the entries in the table.
Test= $md5sum /dev/zero &
$while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;
sleep .5; done
e.g. We can get the result as follows:
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39086
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
---
drivers/thermal/rockchip_thermal.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index 1bcddfc..a7ae23a 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -193,19 +193,18 @@ static u32 rk_tsadcv2_temp_to_code(long temp)
static long rk_tsadcv2_code_to_temp(u32 code)
{
- int high, low, mid;
-
- low = 0;
- high = ARRAY_SIZE(v2_code_table) - 1;
- mid = (high + low) / 2;
+ unsigned int low = 0;
+ unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
+ unsigned int mid = (low + high) / 2;
+ unsigned int scale;
if (code > v2_code_table[low].code || code < v2_code_table[high].code)
return 125000; /* No code available, return max temperature */
while (low <= high) {
- if (code >= v2_code_table[mid].code && code <
- v2_code_table[mid - 1].code)
- return v2_code_table[mid].temp;
+ if (code >= v2_code_table[mid].code &&
+ code < v2_code_table[mid - 1].code)
+ break;
else if (code < v2_code_table[mid].code)
low = mid + 1;
else
@@ -213,7 +212,16 @@ static long rk_tsadcv2_code_to_temp(u32 code)
mid = (low + high) / 2;
}
- return 125000;
+ /*
+* The 5C granularity provided by the table is too much. Let's
+* assume that the relationship between sensor readings and
+* temperature between 2 table entries is linear and extrapolate
+* to produce less granular result.
+*/
+ scale = (v2_code_table[mid].temp - v2_code_table[mid - 1].temp) /
+ (v2_code_table[mid - 1].code - v2_code_table[mid].code);
+ return v2_code_table[mid - 1].temp +
+ (v2_code_table[mid - 1].code - code) * scale;
}
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2] thermal: rockchip: make temperature reporting much more accurate
In general, the kernel should report temperature readings exactly as
reported by the hardware. The cpu / gpu thermal driver works in 5 degree
increments,but we ought to do more accurate. The temperature will do
linear interpolation between the entries in the table.
Test= $md5sum /dev/zero &
$while true; do grep "" /sys/class/thermal/thermal_zone[1-2]/temp;
sleep .5; done
e.g. We can get the result as follows:
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39086
/sys/class/thermal/thermal_zone1/temp:39994
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39540
/sys/class/thermal/thermal_zone1/temp:39540
/sys/class/thermal/thermal_zone2/temp:39994
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
Changes in v2:
Reviewed-by: Dmitry Torokhov
drivers/thermal/rockchip_thermal.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/thermal/rockchip_thermal.c
b/drivers/thermal/rockchip_thermal.c
index 1bcddfc..a7ae23a 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -193,19 +193,18 @@ static u32 rk_tsadcv2_temp_to_code(long temp)
static long rk_tsadcv2_code_to_temp(u32 code)
{
- int high, low, mid;
-
- low = 0;
- high = ARRAY_SIZE(v2_code_table) - 1;
- mid = (high + low) / 2;
+ unsigned int low = 0;
+ unsigned int high = ARRAY_SIZE(v2_code_table) - 1;
+ unsigned int mid = (low + high) / 2;
+ unsigned int scale;
if (code > v2_code_table[low].code || code < v2_code_table[high].code)
return 125000; /* No code available, return max temperature */
while (low <= high) {
- if (code >= v2_code_table[mid].code && code <
- v2_code_table[mid - 1].code)
- return v2_code_table[mid].temp;
+ if (code >= v2_code_table[mid].code &&
+ code < v2_code_table[mid - 1].code)
+ break;
else if (code < v2_code_table[mid].code)
low = mid + 1;
else
@@ -213,7 +212,16 @@ static long rk_tsadcv2_code_to_temp(u32 code)
mid = (low + high) / 2;
}
- return 125000;
+ /*
+* The 5C granularity provided by the table is too much. Let's
+* assume that the relationship between sensor readings and
+* temperature between 2 table entries is linear and extrapolate
+* to produce less granular result.
+*/
+ scale = (v2_code_table[mid].temp - v2_code_table[mid - 1].temp) /
+ (v2_code_table[mid - 1].code - v2_code_table[mid].code);
+ return v2_code_table[mid - 1].temp +
+ (v2_code_table[mid - 1].code - code) * scale;
}
/**
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/1] thermal: rockchip: make temperature reporting much more accurate
This patch is merged on chromiumos/third_party/kernel. https://chromium-review.googlesource.com/#/c/239190/ Tested on veyron boards. Changes in v2: Reviewed-by: Dmitry Torokhov Caesar Wang (1): thermal: rockchip: make temperature reporting much more accurate drivers/thermal/rockchip_thermal.c | 26 +- 1 file changed, 17 insertions(+), 9 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v14 0/3] ARM: rk3288: Add PM Domain support
Add power domain drivers based on generic power domain for Rockchip platform, and support RK3288. Verified on url = https://chromium.googlesource.com/chromiumos/third_party/kernel. At the moment,there are mass of products are using the driver. I believe the driver can happy work for next kernel. Caesar Wang (3): dt-bindings: add document of Rockchip power domain power-domain: rockchip: add power domain driver ARM: dts: add RK3288 power-domain node .../bindings/arm/rockchip/power_domain.txt | 48 ++ arch/arm/boot/dts/rk3288.dtsi | 59 +++ arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/Makefile| 1 + arch/arm/mach-rockchip/pm_domains.c| 506 + include/dt-bindings/power-domain/rk3288.h | 11 + 6 files changed, 626 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/rockchip/power_domain.txt create mode 100644 arch/arm/mach-rockchip/pm_domains.c create mode 100644 include/dt-bindings/power-domain/rk3288.h -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v14 2/3] power-domain: rockchip: add power domain driver
In order to meet high performance and low power requirements, a power
management unit is designed or saving power when RK3288 in low power
mode.
The RK3288 PMU is dedicated for managing the power ot the whole chip.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/Kconfig | 1 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/pm_domains.c | 506
3 files changed, 508 insertions(+)
create mode 100644 arch/arm/mach-rockchip/pm_domains.c
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ae4eb7c..578206b 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -15,6 +15,7 @@ config ARCH_ROCKCHIP
select ROCKCHIP_TIMER
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+ select PM_GENERIC_DOMAINS if PM
help
Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
containing the RK2928, RK30xx and RK31xx series.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5c3a9b2..9c902d3 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1,5 +1,6 @@
CFLAGS_platsmp.o := -march=armv7-a
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/pm_domains.c
b/arch/arm/mach-rockchip/pm_domains.c
new file mode 100644
index 000..92d2569
--- /dev/null
+++ b/arch/arm/mach-rockchip/pm_domains.c
@@ -0,0 +1,506 @@
+/*
+ * Rockchip Generic power domain support.
+ *
+ * Copyright (c) 2014 ROCKCHIP, Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct rockchip_domain_info {
+ int pwr_mask;
+ int status_mask;
+ int req_mask;
+ int idle_mask;
+ int ack_mask;
+};
+
+struct rockchip_pmu_info {
+ u32 pwr_offset;
+ u32 status_offset;
+ u32 req_offset;
+ u32 idle_offset;
+ u32 ack_offset;
+
+ u32 core_pwrcnt_offset;
+ u32 gpu_pwrcnt_offset;
+
+ unsigned int core_power_transition_time;
+ unsigned int gpu_power_transition_time;
+
+ int num_domains;
+ const struct rockchip_domain_info *domain_info;
+};
+
+struct rockchip_pm_domain {
+ struct generic_pm_domain genpd;
+ const struct rockchip_domain_info *info;
+ struct rockchip_pmu *pmu;
+ int num_clks;
+ struct clk *clks[];
+};
+
+struct rockchip_pmu {
+ struct device *dev;
+ struct regmap *regmap;
+ const struct rockchip_pmu_info *info;
+ struct mutex mutex; /* mutex lock for pmu */
+ struct genpd_onecell_data genpd_data;
+ struct generic_pm_domain *domains[];
+};
+
+#define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
+
+#define DOMAIN(pwr, status, req, idle, ack)\
+{ \
+ .pwr_mask = BIT(pwr), \
+ .status_mask = BIT(status), \
+ .req_mask = BIT(req), \
+ .idle_mask = BIT(idle), \
+ .ack_mask = BIT(ack), \
+}
+
+#define DOMAIN_RK3288(pwr, status, req)\
+ DOMAIN(pwr, status, req, req, (req) + 16)
+
+static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ const struct rockchip_domain_info *pd_info = pd->info;
+ unsigned int val;
+
+ regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
+ return (val & pd_info->idle_mask) == pd_info->idle_mask;
+}
+
+static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
+bool idle)
+{
+ const struct rockchip_domain_info *pd_info = pd->info;
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_update_bits(pmu->regmap, pmu->info->req_offset,
+ pd_info->req_mask, idle ? -1U : 0);
+
+ dsb();
+
+ do {
+ regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
+ } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
+
+ while (rockchip_pmu_domain_is_idle(pd) != idle)
+ cpu_relax();
+
+ return 0;
+}
+
+static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ unsigned int val;
+
+ regmap_read(pmu->regmap, pmu->info->status_offset,
[PATCH v14 3/3] ARM: dts: add RK3288 power-domain node
This patch add the needed clocks into power-controller.
why need we do so that?
Firstly, we always be needed turn off clocks to save power when
the system enter suspend.So we need to enumerate the clocks are needed
to switch power doamin no and off.
Secondly, RK3288 reset circuit should be syncchronous reset and
then sync revoked.so we need to enable clocks of all devices.
Signed-off-by: jinkun.hong
Signed-off-by: Caesar Wang
---
Changes in v14:
- does not need to set an owner,remove the "THIS_MODULE".
Changes in v13:
- Remove essential clocks from rk3288 PD_VIO domain
Some clocks are essential for the system health and should not
be turned down. However there is no owner for them so if they listed
as belonging to power domain we'll try toggling them up and down
during power domain.
- Device drivers expect their devices to be powered on before their
probing code is invoked. To achieve that we should start with
power domains powered on (we may turn them off later once all
devices enable runtime power managment and go idle).
- This change switches Rockchip power domain driver to use updated
device_attach and device_detach API.
- set the gpu/core power domain power delay time.
- fix enumerating PM clocks for devices.
- fix use after free
We can't use clk after we did clk_put(clk).
Changes in v12:
- Remove essential clocks from rk3288 PD_VIO domain,
Some clocks are essential for the system health and should
not be turned down. However there is no owner for them so
if they listed as belonging to power domain we'll try toggling
them up and down during power domain transition. As a result we
either fail to suspend or resume the system.
Changes in v11: None
Changes in v10:
- fix missing the #include
- remove the notes
Changes in v9:
- add decription for power-doamin node
Changes in v8:
- DTS go back to v2
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Decomposition power-controller, changed to multiple controller
(gpu-power-controller, hevc-power-controller)
Changes in v2:
- make pd_vio clocks all one entry per line and alphabetize.
- power: power-controller move back to pinctrl: pinctrl.
---
arch/arm/boot/dts/rk3288.dtsi | 59 +++
include/dt-bindings/power-domain/rk3288.h | 11 ++
2 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/power-domain/rk3288.h
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5999029..f3992db 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include "skeleton.dtsi"
@@ -1277,4 +1278,62 @@
};
};
};
+
+ power: power-controller {
+ compatible = "rockchip,rk3288-power-controller";
+ #power-domain-cells = <1>;
+ rockchip,pmu = <&pmu>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_gpu {
+ reg = ;
+ clocks = <&cru ACLK_GPU>;
+ };
+
+ pd_hevc {
+ reg = ;
+ clocks = <&cru ACLK_HEVC>,
+<&cru SCLK_HEVC_CABAC>,
+<&cru SCLK_HEVC_CORE>,
+<&cru HCLK_HEVC>;
+ };
+
+ pd_vio {
+ reg = ;
+ clocks = <&cru ACLK_IEP>,
+<&cru ACLK_ISP>,
+<&cru ACLK_RGA>,
+<&cru ACLK_VIP>,
+<&cru ACLK_VOP0>,
+<&cru ACLK_VOP1>,
+<&cru DCLK_VOP0>,
+<&cru DCLK_VOP1>,
+<&cru HCLK_IEP>,
+<&cru HCLK_ISP>,
+<&cru HCLK_RGA>,
+<&cru HCLK_VIP>,
+<&cru HCLK_VOP0>,
+<&cru HCLK_VOP1>,
+<&cru PCLK_EDP_CTRL>,
+<&cru PCLK_HDMI_CTRL>,
+<&cru PCLK_LVDS_PHY>,
+<&cru PCLK_MIPI_CSI>,
+<&cru PCLK_MIPI_DSI0>,
+<&cru PCLK_MIPI_DSI
