[rcu:rcu/test] BUILD REGRESSION 88054dca0f5708bee190e093dce64dc3cb025793
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git rcu/test branch HEAD: 88054dca0f5708bee190e093dce64dc3cb025793 ACPI: processor: Fix missing need_resched() check after rcu_idle_enter() Error/Warning ids grouped by kconfigs: gcc_recent_errors `-- nds32-randconfig-r014-20201221 `-- kernel-rcu-tree_plugin.h:error:struct-task_struct-has-no-member-named-on_cpu elapsed time: 721m configs tested: 133 configs skipped: 2 gcc tested configs: arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig nds32 allnoconfig m68km5407c3_defconfig openriscdefconfig sh se7343_defconfig mips maltasmvp_defconfig armvt8500_v6_v7_defconfig mips cu1830-neo_defconfig powerpc sbc8548_defconfig c6xevmc6474_defconfig powerpcge_imp3a_defconfig arm corgi_defconfig powerpc xes_mpc85xx_defconfig powerpc ppc40x_defconfig parisc defconfig c6x defconfig sh shx3_defconfig mips loongson3_defconfig powerpc mpc8315_rdb_defconfig arcvdk_hs38_defconfig arm pcm027_defconfig arm mv78xx0_defconfig armtrizeps4_defconfig sh landisk_defconfig m68kq40_defconfig sh sh03_defconfig m68k amcore_defconfig arcnsim_700_defconfig m68kmac_defconfig mipsmalta_kvm_guest_defconfig s390 debug_defconfig mips mtx1_defconfig sparc64 alldefconfig armclps711x_defconfig sh ap325rxa_defconfig xtensa common_defconfig arm multi_v4t_defconfig xtensa alldefconfig mipsnlm_xlp_defconfig mips db1xxx_defconfig sh ul2_defconfig powerpc skiroot_defconfig powerpcicon_defconfig powerpc mpc837x_rdb_defconfig arm zx_defconfig powerpc taishan_defconfig powerpc mpc83xx_defconfig h8300alldefconfig powerpc mpc834x_mds_defconfig arm omap2plus_defconfig powerpc mpc8560_ads_defconfig ia64generic_defconfig sparc sparc32_defconfig arm spear13xx_defconfig sh se7780_defconfig arm pxa_defconfig mips loongson1b_defconfig sparc64 defconfig alpha defconfig arm tegra_defconfig mips decstation_64_defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386 tinyconfig i386defconfig mips allyesconfig mips allmodconfig powerpc allyesconfig powerpc allmodconfig powerpc allnoconfig x86_64 randconfig-a001-20201223 x86_64 randconfig-a006-20201223 x86_64 randconfig-a002-20201223 x86_64
[rcu:dev.2020.12.21a] BUILD SUCCESS ceb57fe529baff777d89a46bff3580926b3186ef
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git dev.2020.12.21a branch HEAD: ceb57fe529baff777d89a46bff3580926b3186ef torture: Break affinity of kthreads last running on outgoing CPU elapsed time: 724m configs tested: 138 configs skipped: 2 The following configs have been built successfully. More configs may be tested in the coming days. gcc tested configs: arm defconfig arm64allyesconfig arm64 defconfig arm allyesconfig arm allmodconfig m68km5407c3_defconfig openriscdefconfig sh se7343_defconfig mips maltasmvp_defconfig nds32 allnoconfig parisc defconfig c6x defconfig sh shx3_defconfig mips loongson3_defconfig powerpc mpc8315_rdb_defconfig mipsworkpad_defconfig arm bcm2835_defconfig sh alldefconfig powerpc mpc8560_ads_defconfig armneponset_defconfig arcvdk_hs38_defconfig arm pcm027_defconfig arm mv78xx0_defconfig riscv defconfig armtrizeps4_defconfig arm prima2_defconfig sparcalldefconfig mips bmips_be_defconfig powerpcmpc7448_hpc2_defconfig microblaze mmu_defconfig sh sh7785lcr_32bit_defconfig sh landisk_defconfig m68kq40_defconfig sh sh03_defconfig m68k amcore_defconfig arcnsim_700_defconfig m68kmac_defconfig sh defconfig m68k bvme6000_defconfig openriscor1ksim_defconfig mipsmalta_kvm_guest_defconfig s390 debug_defconfig mips mtx1_defconfig sparc64 alldefconfig armclps711x_defconfig sh ap325rxa_defconfig xtensa common_defconfig arm multi_v4t_defconfig xtensa alldefconfig mipsnlm_xlp_defconfig mips db1xxx_defconfig sh ul2_defconfig powerpc skiroot_defconfig powerpcicon_defconfig powerpc mpc837x_rdb_defconfig mips allmodconfig arm zx_defconfig powerpc taishan_defconfig powerpc mpc83xx_defconfig h8300alldefconfig powerpc mpc834x_mds_defconfig arm omap2plus_defconfig ia64generic_defconfig sparc sparc32_defconfig arm spear13xx_defconfig sh se7780_defconfig arm pxa_defconfig mips loongson1b_defconfig sparc64 defconfig alpha defconfig arm tegra_defconfig mips decstation_64_defconfig ia64 allmodconfig ia64defconfig ia64 allyesconfig m68k allmodconfig m68kdefconfig m68k allyesconfig nios2 defconfig arc allyesconfig c6x allyesconfig nds32 defconfig nios2allyesconfig cskydefconfig alphaallyesconfig xtensa allyesconfig h8300allyesconfig arc defconfig sh allmodconfig s390 allyesconfig parisc allyesconfig s390defconfig i386 allyesconfig sparcallyesconfig sparc defconfig i386 tinyconfig i386defconfig mips allyesconfig powerpc allyesconfig powerpc allmodco
[PATCH] bpf: fix: symbol 'btf_vmlinux' was not declared.
Symbol 'btf_vmlinux' was not declared in the header file and does not
add extern, so no other file uses it. It's better to add static to it.
Signed-off-by: YANG LI
Reported-by: Abaci
---
kernel/bpf/verifier.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 17270b8..535d364 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -244,7 +244,7 @@ struct bpf_call_arg_meta {
u32 ret_btf_id;
};
-struct btf *btf_vmlinux;
+static struct btf *btf_vmlinux;
static DEFINE_MUTEX(bpf_verifier_lock);
--
1.8.3.1
Re: [PATCHv6 0/4] n_gsm serdev support and protocol driver for droid4 modem
Hi, * Pavel Machek [201220 22:48]: > Hi! > > > Sorry about the late reply on this. > > I'm afraid I'll need some more answers in near future, but for now: > > Tony, do you remember / can you figure out what gsmtty GPS is on? I > never used it on that interface, and I can't seem to figure it out. > > My notes say: > > /dev/motmdm1 -- basic support, calls, on/off > > /dev/motmdm3 -- send sms interface > > /dev/motmdm9 -- receive sms interface > > > (and gsmtty numbering is same) Yes I have not had a chance to look at these for several months now, but have the latest set in droid4-pending-v5.10 branch in my github tree. The gnss device is at /dev/gsmtty6, see the current droid4-agps tool to upload the almanac also on github. That's has turned out to be a pretty good gsm serdev test too :) > For now I converted gnss driver to use serdev interface, and n_gsm to > provide it... Not yet finished but I believe I'm walking in the right > direction. Great, sounds good to me if you got things working with just serdev calls :) I'll try to take a look at this stuff again after I have the other pending droid4 issues out of the way like v5.12 charger and keyboard stuff. Regards, Tony
Re: [PATCH v1 0/2] perf arm64: Support SDT
Hi Leo, On Wed, 23 Dec 2020 14:39:03 +0800 Leo Yan wrote: > This patch is to enable SDT on Arm64. > > Since Arm64 SDT marker in ELF file is different from other archs, > especially for using stack pointer (sp) to retrieve data for local > variables, patch 01 is used to fixup the arguments for this special > case. Patch 02 is to add argument support for Arm64 SDT. Both patches look good to me. Acked-by: Masami Hiramatsu for the seires. Thank you! > > This patch set has been verified on Arm64/x86_64 platforms with a > testing program usdt_test [1]. The program run the SDT interfaces > one by one for DTRACE_PROBE, DTRACE_PROBE1, ..., DTRACE_PROBE12, so > it tries to verify probe with different count of arguments (the > arguments count is 0 to 12). > > The testing flow and result are shown as below: > > # perf buildid-cache --add /root/test/usdt_test > # perf probe sdt_usdt:test_probe > # perf probe sdt_usdt:test_probe_param1 > # perf probe sdt_usdt:test_probe_param1x > # perf probe sdt_usdt:test_probe_param2 > # perf probe sdt_usdt:test_probe_param2x > # perf probe sdt_usdt:test_probe_param3 > # perf probe sdt_usdt:test_probe_param3x > # perf probe sdt_usdt:test_probe_param4 > # perf probe sdt_usdt:test_probe_param4x > # perf probe sdt_usdt:test_probe_param5 > # perf probe sdt_usdt:test_probe_param5x > # perf probe sdt_usdt:test_probe_param6 > # perf probe sdt_usdt:test_probe_param6x > # perf probe sdt_usdt:test_probe_param7 > # perf probe sdt_usdt:test_probe_param7x > # perf probe sdt_usdt:test_probe_param8 > # perf probe sdt_usdt:test_probe_param8x > # perf probe sdt_usdt:test_probe_param9 > # perf probe sdt_usdt:test_probe_param9x > # perf probe sdt_usdt:test_probe_param10 > # perf probe sdt_usdt:test_probe_param10x > # perf probe sdt_usdt:test_probe_param11 > # perf probe sdt_usdt:test_probe_param11x > # perf probe sdt_usdt:test_probe_param12 > # perf probe sdt_usdt:test_probe_param12x > > # perf record \ > -e sdt_usdt:test_probe_param1 -e sdt_usdt:test_probe_param1x \ > -e sdt_usdt:test_probe_param2 -e sdt_usdt:test_probe_param2x \ > -e sdt_usdt:test_probe_param3 -e sdt_usdt:test_probe_param3x \ > -e sdt_usdt:test_probe_param4 -e sdt_usdt:test_probe_param4x \ > -e sdt_usdt:test_probe_param5 -e sdt_usdt:test_probe_param5x \ > -e sdt_usdt:test_probe_param6 -e sdt_usdt:test_probe_param6x \ > -e sdt_usdt:test_probe_param7 -e sdt_usdt:test_probe_param7x \ > -e sdt_usdt:test_probe_param8 -e sdt_usdt:test_probe_param8x \ > -e sdt_usdt:test_probe_param9 -e sdt_usdt:test_probe_param9x \ > -e sdt_usdt:test_probe_param10 -e sdt_usdt:test_probe_param10x \ > -e sdt_usdt:test_probe_param11 -e sdt_usdt:test_probe_param11x \ > -e sdt_usdt:test_probe_param12 -e sdt_usdt:test_probe_param12x \ > -e sdt_usdt:test_probe -aR sleep 5 > ># ./usdt_test => Execute in another terminal > ># perf script > >usdt_test 7999 [003] 80493.418276: sdt_usdt:test_probe: > (b0d80714) >usdt_test 7999 [003] 80493.418352: sdt_usdt:test_probe_param1: > (b0d80728) arg1=1 >usdt_test 7999 [003] 80493.418379: sdt_usdt:test_probe_param2: > (b0d80744) arg1=1 arg2=2 >usdt_test 7999 [003] 80493.418405: sdt_usdt:test_probe_param3: > (b0d80764) arg1=1 arg2=2 arg3=3 >usdt_test 7999 [003] 80493.418432: sdt_usdt:test_probe_param4: > (b0d80788) arg1=1 arg2=2 arg3=3 arg4=4 >usdt_test 7999 [003] 80493.418459: sdt_usdt:test_probe_param5: > (b0d807b0) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 >usdt_test 7999 [003] 80493.418487: sdt_usdt:test_probe_param6: > (b0d807dc) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 >usdt_test 7999 [003] 80493.418516: sdt_usdt:test_probe_param7: > (b0d8080c) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 >usdt_test 7999 [003] 80493.418545: sdt_usdt:test_probe_param8: > (b0d80840) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 arg8=8 >usdt_test 7999 [003] 80493.418574: sdt_usdt:test_probe_param9: > (b0d80874) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 arg8=8 arg9=9 >usdt_test 7999 [003] 80493.418603: sdt_usdt:test_probe_param10: > (b0d808a8) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 arg8=8 arg9=9 > arg10=10 >usdt_test 7999 [003] 80493.418632: sdt_usdt:test_probe_param11: > (b0d808dc) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 arg8=8 arg9=9 > arg10=10 arg11=11 >usdt_test 7999 [003] 80493.418662: sdt_usdt:test_probe_param12: > (b0d80910) arg1=1 arg2=2 arg3=3 arg4=4 arg5=5 arg6=6 arg7=7 arg8=8 arg9=9 > arg10=10 arg11=11 arg12=12 >usdt_test 7999 [003] 80493.418687: sdt_usdt:test_probe_param1x: > (b0d8092c) arg1=1 >usdt_test 7999 [003] 80493.418713: sdt_usdt:test_probe_param2x: > (b0d80950) arg1=1 arg2=2
drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes address space '__iomem' of expression
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-184-g1b896707-dirty
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ac6795fcc085e8d03649f1bbd0d70aaff612cad
git remote add linus
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 2ac6795fcc085e8d03649f1bbd0d70aaff612cad
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
"sparse warnings: (new ones prefixed by >>)"
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes
>> address space '__iomem' of expression
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:72:24: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:72:24: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: cast removes
address space '__iomem' of expression
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: incorrect type in
argument 1 (different address spaces) @@ expected void const volatile
[noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:70:22: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:70:22: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:219:36: sparse: sparse: incorrect type in
argument 2 (different address spaces) @@ expected void * @@ got struct
clock_event_device [noderef] __percpu * @@
drivers/clocksource/timer-clint.c:219:36: sparse: expected void *
drivers/clocksource/timer-clint.c:219:36: sparse: got struct
clock_event_device [noderef] __percpu *
vim +/__iomem +72 drivers/clocksource/timer-clint.c
58
59 #ifdef CONFIG_64BIT
60 static u64 notrace clint_get_cycles64(void)
61 {
62 return clint_get_cycles();
63 }
64 #else /* CONFIG_64BIT */
65 static u64 notrace clint_get_cycles64(void)
66 {
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
> 72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75 }
76 #endif /* CONFIG_64BIT */
77
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
Re: [PATCH v5 2/5] tracing: Rework synthetic event command parsing
On Wed, 23 Dec 2020 17:17:27 -0600
Tom Zanussi wrote:
> Hi Masami,
>
> On Tue, 2020-12-22 at 21:42 +0900, Masami Hiramatsu wrote:
> > Hi Tom,
> >
> > On Mon, 21 Dec 2020 15:44:28 -0600
> > Tom Zanussi wrote:
> >
> >
> > > @@ -656,7 +651,6 @@ static struct synth_field
> > > *parse_synth_field(int argc, const char **argv,
> > >
> > > size = synth_field_size(field->type);
> > > if (size < 0) {
> > > - synth_err(SYNTH_ERR_INVALID_TYPE, errpos(field_type));
> >
> > Why did you remove this error message?
>
> It wasn't actually removed - it was just moved into the next patch, so
> is still there. I'll move it back here to avoid confusion.
>
> >
> > [..]
> > > @@ -1228,26 +1189,47 @@ static int __create_synth_event(int argc,
> > > const char *name, const char **argv)
> > > goto out;
> > > }
> > >
> > > - for (i = 0; i < argc - 1; i++) {
> > > - if (strcmp(argv[i], ";") == 0)
> > > - continue;
> > > + tmp_fields = saved_fields = kstrdup(raw_fields, GFP_KERNEL);
> > > + if (!tmp_fields) {
> > > + ret = -ENOMEM;
> > > + goto out;
> > > + }
> > > +
> > > + while ((field_str = strsep(&tmp_fields, ";")) != NULL) {
> > > if (n_fields == SYNTH_FIELDS_MAX) {
> > > synth_err(SYNTH_ERR_TOO_MANY_FIELDS, 0);
> > > ret = -EINVAL;
> > > goto err;
> > > }
> > >
> > > - field = parse_synth_field(argc - i, &argv[i],
> > > &consumed);
> > > + argv = argv_split(GFP_KERNEL, field_str, &argc);
> > > + if (!argv) {
> > > + ret = -ENOMEM;
> > > + goto err;
> > > + }
> > > +
> > > + if (!argc)
> > > + continue;
> > > +
> > > + field = parse_synth_field(argc, argv, &consumed);
> > > if (IS_ERR(field)) {
> > > + argv_free(argv);
> > > ret = PTR_ERR(field);
> > > goto err;
> > > }
> > > +
> > > + argv_free(argv);
> > > +
> > > + if (consumed < argc) {
> > > + ret = -EINVAL;
> > > + goto err;
> > > + }
> >
> > You can check the consumed < argc in parse_synth_field(), unless
> > you keep the backward compatibility - I think you can add an
> > inner loop for it, something like
> >
> > while ((field_str = strsep(&tmp_fields, ";")) != NULL) {
> > argv = argv_split(...);
> > consumed = 0;
> > while (argc > consumed) {
> > // increment consumed in parse_synth_field()
> > field = parse_synth_field(argc - consumed, argv + consumed,
> > &consumed);
> > if (IS_ERR(field)) {...}
> >
> > fields[n_fields++] = field;
> > if (n_fields == SYNTH_FIELDS_MAX) {...}
> > }
> >
> > argv_free(argv);
> > }
> >
> > what would you think?
>
> Hmm, not sure this helps - there's only supposed to be one field per
> field_str and consumed returns either 2 or 3 depending on the field.
I meant that this can be reused to support older syntax like
"myevent int foo unsigned long bar" without inserting semicolons.
> consumed is only used to detect whether there were unused words and if
> so flag an error, rather than loop around to try to get another field.
If you drop the backward compatibility from *this* patch, we can just
check the "consumed < argc" in parse_synth_field() and remove "consumed"
from this function.
Thank you,
--
Masami Hiramatsu
RE: [PATCH v6 11/12] mfd: bd9571mwv: Make the driver more generic
Hi Lee,
> From: Lee Jones, Sent: Thursday, December 24, 2020 4:34 PM
> > Hi Lee,
> >
> > > From: Lee Jones, Sent: Thursday, December 24, 2020 12:39 AM
> > > On Wed, 23 Dec 2020, Yoshihiro Shimoda wrote:
> > > > From: Khiem Nguyen
> > > > + switch (ret) {
> > > > + case BD9571MWV_PRODUCT_CODE_BD9571MWV:
> > > > + ddata = &bd9571mwv_ddata;
> > >
> > > Simply declare 'const struct mfd_cell *cells' locally in probe and
> > > assign it here instead.
> >
> > I got it. I'll also add "const struct regmap_config *regmap_config;"
> > and "const struct regmap_irq_chip *irq_chip;" locally in probe.
>
> If you only use them there, then yes, that's correct.
Thank you for the reply. Yes, I only use them there.
So, I have submitted v7 patches which have such implementation.
Best regards,
Yoshihiro Shimoda
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:122:6: warning: stack frame size of 4240 bytes in function 'dml_log_pipe_params'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 20f2ffe504728612d7b0c34e4f8280e34251e704 drm/amdgpu: fold
CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
date: 7 weeks ago
config: powerpc-randconfig-r016-20201223 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
cee1e7d14f4628d6174b33640d502bff3b54ae45)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc cross compiling tool for clang build
# apt-get install binutils-powerpc-linux-gnu
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=20f2ffe504728612d7b0c34e4f8280e34251e704
git remote add linus
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 20f2ffe504728612d7b0c34e4f8280e34251e704
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:122:6:
>> warning: stack frame size of 4240 bytes in function 'dml_log_pipe_params'
>> [-Wframe-larger-than=]
void dml_log_pipe_params(
^
1 warning generated.
vim +/dml_log_pipe_params +122
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c
20f2ffe50472861 Alex Deucher 2020-11-02 121
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 @122 void dml_log_pipe_params(
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 123 struct
display_mode_lib *mode_lib,
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 124
display_e2e_pipe_params_st *pipes,
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 125 int pipe_cnt)
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 126 {
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 127
display_pipe_source_params_st *pipe_src;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 128
display_pipe_dest_params_st *pipe_dest;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 129 scaler_ratio_depth_st
*scale_ratio_depth;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 130 scaler_taps_st
*scale_taps;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 131
display_output_params_st *dout;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 132
display_clocks_and_cfg_st *clks_cfg;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 133 int i;
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 134
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 135 for (i = 0; i <
pipe_cnt; i++) {
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 136 pipe_src =
&(pipes[i].pipe.src);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 137 pipe_dest =
&(pipes[i].pipe.dest);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 138
scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 139 scale_taps =
&(pipes[i].pipe.scale_taps);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 140 dout =
&(pipes[i].dout);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 141 clks_cfg =
&(pipes[i].clks_cfg);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 142
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 143 dml_print("DML
PARAMS: =\n");
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 144 dml_print("DML
PARAMS: PIPE [%d] SOURCE PARAMS:\n", i);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 145 dml_print("DML
PARAMS: source_format = %d\n", pipe_src->source_format);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 146 dml_print("DML
PARAMS: dcc= %d\n", pipe_src->dcc);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 147 dml_print("DML
PARAMS: dcc_rate = %d\n", pipe_src->dcc_rate);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 148 dml_print("DML
PARAMS: dcc_use_global = %d\n", pipe_src->dcc_use_global);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 149 dml_print("DML
PARAMS: vm = %d\n", pipe_src->vm);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 150 dml_print("DML
PARAMS: gpuvm = %d\n", pipe_src->gpuvm);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 151 dml_print("DML
PARAMS: hostvm = %d\n", pipe_src->hostvm);
6725a88f88a7e92 Bhawanpreet Lakha 2020-05-21 152 dml_print("DML
PARAMS: gpuv
Re: [kbuild-all] drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes address space '__iomem' of expression
On Thu, Dec 24, 2020 at 04:11:17PM +0800, kernel test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
> commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add
> CLINT timer driver
> date: 4 months ago
> config: riscv-randconfig-s031-20201221 (attached as .config)
> compiler: riscv32-linux-gcc (GCC) 9.3.0
> reproduce:
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # apt-get install sparse
> # sparse version: v0.6.3-184-g1b896707-dirty
> #
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ac6795fcc085e8d03649f1bbd0d70aaff612cad
> git remote add linus
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> git fetch --no-tags linus master
> git checkout 2ac6795fcc085e8d03649f1bbd0d70aaff612cad
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1
> CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot
Hi Anup and all, kindly ignore extra reports against this commit, we will
check why it sends out ~10 duplicated reports. Sorry for the inconvenience.
Thanks
>
>
> "sparse warnings: (new ones prefixed by >>)"
> >> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes
> >> address space '__iomem' of expression
> >> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: incorrect type in
> >> argument 1 (different address spaces) @@ expected void const volatile
> >> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>drivers/clocksource/timer-clint.c:72:24: sparse: expected void const
> volatile [noderef] __iomem *addr
>drivers/clocksource/timer-clint.c:72:24: sparse: got unsigned int
> [usertype] *
>drivers/clocksource/timer-clint.c:70:22: sparse: sparse: cast removes
> address space '__iomem' of expression
>drivers/clocksource/timer-clint.c:70:22: sparse: sparse: incorrect type in
> argument 1 (different address spaces) @@ expected void const volatile
> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
>drivers/clocksource/timer-clint.c:70:22: sparse: expected void const
> volatile [noderef] __iomem *addr
>drivers/clocksource/timer-clint.c:70:22: sparse: got unsigned int
> [usertype] *
>drivers/clocksource/timer-clint.c:219:36: sparse: sparse: incorrect type
> in argument 2 (different address spaces) @@ expected void * @@ got
> struct clock_event_device [noderef] __percpu * @@
>drivers/clocksource/timer-clint.c:219:36: sparse: expected void *
>drivers/clocksource/timer-clint.c:219:36: sparse: got struct
> clock_event_device [noderef] __percpu *
>
> vim +/__iomem +72 drivers/clocksource/timer-clint.c
>
> 58
> 59#ifdef CONFIG_64BIT
> 60static u64 notrace clint_get_cycles64(void)
> 61{
> 62return clint_get_cycles();
> 63}
> 64#else /* CONFIG_64BIT */
> 65static u64 notrace clint_get_cycles64(void)
> 66{
> 67u32 hi, lo;
> 68
> 69do {
> 70hi = clint_get_cycles_hi();
> 71lo = clint_get_cycles();
> > 72} while (hi != clint_get_cycles_hi());
> 73
> 74return ((u64)hi << 32) | lo;
> 75}
> 76#endif /* CONFIG_64BIT */
> 77
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
> ___
> kbuild-all mailing list -- kbuild-...@lists.01.org
> To unsubscribe send an email to kbuild-all-le...@lists.01.org
drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes address space '__iomem' of expression
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-184-g1b896707-dirty
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ac6795fcc085e8d03649f1bbd0d70aaff612cad
git remote add linus
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 2ac6795fcc085e8d03649f1bbd0d70aaff612cad
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
"sparse warnings: (new ones prefixed by >>)"
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes
>> address space '__iomem' of expression
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:72:24: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:72:24: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: cast removes
address space '__iomem' of expression
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: incorrect type in
argument 1 (different address spaces) @@ expected void const volatile
[noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:70:22: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:70:22: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:219:36: sparse: sparse: incorrect type in
argument 2 (different address spaces) @@ expected void * @@ got struct
clock_event_device [noderef] __percpu * @@
drivers/clocksource/timer-clint.c:219:36: sparse: expected void *
drivers/clocksource/timer-clint.c:219:36: sparse: got struct
clock_event_device [noderef] __percpu *
vim +/__iomem +72 drivers/clocksource/timer-clint.c
58
59 #ifdef CONFIG_64BIT
60 static u64 notrace clint_get_cycles64(void)
61 {
62 return clint_get_cycles();
63 }
64 #else /* CONFIG_64BIT */
65 static u64 notrace clint_get_cycles64(void)
66 {
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
> 72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75 }
76 #endif /* CONFIG_64BIT */
77
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
Re: [PATCH v4 09/11] dt-bindings: usb: convert mediatek,mtk-xhci.txt to YAML schema
On Mon, 2020-12-21 at 12:23 -0700, Rob Herring wrote: > On Wed, Dec 16, 2020 at 05:30:10PM +0800, Chunfeng Yun wrote: > > Convert mediatek,mtk-xhci.txt to YAML schema mediatek,mtk-xhci.yaml > > > > Signed-off-by: Chunfeng Yun > > --- > > v4: update it according to Rob's suggestion > > 1. modify dictionary of phys > > 2. fix endentation in "mediatek,syscon-wakeup" items > > 3. remove reference to usb-hcd.yaml > > > > v3: > > 1. fix yamllint warning > > 2. remove pinctrl* properties supported by default suggested by Rob > > 3. drop unused labels > > 4. modify description of mediatek,syscon-wakeup > > 5. remove type of imod-interval-ns > > > > v2: new patch > > --- > > .../bindings/usb/mediatek,mtk-xhci.txt| 121 - > > .../bindings/usb/mediatek,mtk-xhci.yaml | 171 ++ > > 2 files changed, 171 insertions(+), 121 deletions(-) > > delete mode 100644 > > Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt > > create mode 100644 > > Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml > > > > diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt > > b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt > > deleted file mode 100644 > > index 42d8814f903a.. > > --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt > > +++ /dev/null [...] > > +$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek USB3 xHCI Device Tree Bindings > > + > > +maintainers: > > + - Chunfeng Yun > > + > > +allOf: > > + - $ref: "usb-hcd.yaml" > > This will need to reference Serge's xhci.yaml instead. Yes, I forgot it > > > + > > +description: | > > + There are two scenarios: > > + case 1: only supports xHCI driver; > > + case 2: supports dual-role mode, and the host is based on xHCI driver. > > + > > +properties: > > + # common properties for both case 1 and case 2 > > + compatible: > > +items: > > + - enum: > > + - mediatek,mt2712-xhci > > + - mediatek,mt7622-xhci > > + - mediatek,mt7629-xhci > > + - mediatek,mt8173-xhci > > + - mediatek,mt8183-xhci > > + - const: mediatek,mtk-xhci > > + > > + reg: > > +minItems: 1 > > +maxItems: 2 > > You can drop maxItems, as that is implied by length of 'items'. Ok, will drop it for the following ones > > > +items: > > + - description: the registers of xHCI MAC > > + - description: the registers of IP Port Control > > + > > + reg-names: > > +minItems: 1 > > +maxItems: 2 > > +items: > > + - const: mac > > + - const: ippc # optional, only needed for case 1. > > + > > + interrupts: > > +maxItems: 1 > > + > > + power-domains: > > +description: A phandle to USB power domain node to control USB's MTCMOS > > +maxItems: 1 > > + > > + clocks: > > +minItems: 1 > > +maxItems: 5 > > +items: > > + - description: Controller clock used by normal mode > > + - description: Reference clock used by low power mode etc > > + - description: Mcu bus clock for register access > > + - description: DMA bus clock for data transfer > > + - description: controller clock > > + > > + clock-names: > > +minItems: 1 > > +maxItems: 5 > > +items: > > + - const: sys_ck # required, the following ones are optional > > + - const: ref_ck > > + - const: mcu_ck > > + - const: dma_ck > > + - const: xhci_ck > > + > > + phys: > > +description: List of at most 5 USB2 PHYs and 4 USB3 PHYs on this HCD > > If it's less, how does one know what each phy is? The SoC's spec will tell how many phys used, but each project may use some phys of them, due to not all ports are used for some scenarios. > > > +minItems: 0 > > minItems: 0 is never correct. That's phys not being present. Ok, will modify it. But it's useful for the case that the phy is an external sub-board, and can works without initialization. (FPGA env.) > > > +maxItems: 9 > > + > > + vusb33-supply: > > +description: Regulator of USB AVDD3.3v > > + > > + vbus-supply: > > +description: Regulator of USB VBUS5v > > + > > + usb3-lpm-capable: > > +description: supports USB3.0 LPM > > +type: boolean > > + > > + imod-interval-ns: > > +description: > > + Interrupt moderation interval value, it is 8 times as much as that > > + defined in the xHCI spec on MTK's controller. > > +default: 5000 > > + > > + # the following properties are only used for case 1 > > + wakeup-source: > > +description: enable USB remote wakeup, see power/wakeup-source.txt > > +type: boolean > > + > > + mediatek,syscon-wakeup: > > +$ref: /schemas/types.yaml#/definitions/phandle-array > > +maxItems: 1 > > +description: > > + A phandle to syscon used to access the register of the USB wakeup > > glue > > + layer betw
Teo En Ming's Guide to Configuring Asterisk/FreePBX with Cisco 7960 IP Phones
Subject: Teo En Ming's Guide to Configuring Asterisk/FreePBX with Cisco 7960 IP Phones Author: Mr. Turritopsis Dohrnii Teo En Ming (TARGETED INDIVIDUAL) Country: Singapore Date: 24 December 2020 Thursday Singapore Time Type of Publication: Plain Text Document version: 20201224.01 == System Information == My Asterisk version: 16.13.0 My FreePBX version: 15.0.16.81 On 7 December 2020, I was able to get Bria softphone to work with my Asterisk PBX server successfully (PJSIP extension). On 19 December 2020, I bought a refurbished Cisco CP-7960G IP hardphone for SGD$30 in Singapore. TFTP works. My DHCP server in my pfSense firewall applaince is able to assign my Cisco 7960 IP phone with an IP address with DHCP option 66 (TFTP server). My Cisco 7960 IP phone is able to connect to my TFTP server on my Asterisk PBX appliance and download firmware and configuration files successfully. On 24 December 2020 Thursday Christmas Eve, I have finally managed to get my Cisco 7960 IP phone to register on my Asterisk PBX server ***successfully***. This is an ***OLD AND OUTDATED*** video of my Cisco 7960 IP phone: https://www.youtube.com/watch?v=ip_F08jmmio I will publish new and updated Youtube video of my Cisco 7960 IP phone ***in the future***. BEGINNING OF THIS GUIDE === Reference Guide: Configure Asterisk with Cisco IP Phones Link: http://docshare02.docshare.tips/files/6706/67061980.pdf SECTION 1: INSTALLING TFTP SERVER ON ASTERISK PBX APPLIANCE === Putty/ssh into Teo En Ming's Asterisk VoIP IP PBX SIP Server at 192.168.1.9. # yum install tftp-server Package tftp-server-5.2-23.8.sng7.x86_64 already installed and latest version # chkconfig xinetd on # chkconfig tftp on # systemctl start tftp.service # ps -ef | grep tftp root 3424 1 0 11:17 ?00:00:00 /usr/sbin/in.tftpd -s /tftpboot SECTION 2: DOWNLOADING CISCO 7960 IP PHONE SIP FIRMWARE === # cd /tftpboot # wget http://www.firewall.cx/downloads/cisco-tools-a-applications/cisco-ip-phone-a-ata-firmware-downloads/107-7940-a-7960-ip-phone-sccp-a-sip/file.html # mv file.html file.zip # unzip file.zip # cd 7940_7960/ # cd SIP/ # tar -xf P0S3-8-12-00.tar # rm P0S3-8-12-00.tar # mv * /tftpboot/ # cd /tftpboot/ [root@freepbx tftpboot]# ls 7940_7960 file.zip OS79XX.TXT P003-8-12-00.bin P003-8-12-00.sbn P0S3-8-12-00.loads P0S3-8-12-00.sb2 SECTION 3: CREATING CISCO 7960 IP PHONE CONFIGURATION FILES === # nano OS79XX.TXT (Create configuration file) = P003-8-12-00 # nano XMLDefault.cnf.xml (Create configuration file) = 2000 2427 2428 P0S3-8-12-00 P0S3-8-12-00 SIP45.8-4-2S SIP45.8-4-2S SIP70.8-0-3S # nano SIPDefault.cnf (Create configuration file) = image_version: "P0S3-8-12-00" proxy1_address: "192.168.1.9" # proxy2_address: "xxx.xxx.xxx.xxx" # proxy3_address: "xxx.xxx.xxx.xxx" # proxy4_address: "xxx.xxx.xxx.xxx" # Proxy Server Port proxy1_port:"5060" # proxy2_port:"5060" # proxy3_port:"5060" # proxy4_port:"5060" proxy_emergency: "" proxy_emergency_port: "5060" proxy_backup: "" proxy_backup_port: "5060" outbound_proxy: "" outbound_proxy_port: "5060" nat_enable: "0" nat_address: "" voip_control_port: "5060" start_media_port: "16348" end_media_port: "20134" nat_received_processing: "1" dyn_dns_addr_1: "" dyn_dns_addr_2: "" dyn_tftp_addr: "192.168.1.9" tftp_cfg_dir: "./" proxy_register: "1" timer_register_expires: "120" preferred_codec: "none" tos_media: "5" enable_vad: "0" dial_template: "dialplan" network_media_type: "auto" autocomplete: "1" telnet_level: "2" cnf_join_enable: "1" semi_attended_transfer: "0" call_waiting: "1" anonymous_call_block: "0" callerid_blocking: "0" dnd_control: "0" dtmf_inband: "1" dtmf_outofband: "avt" dtmf_db_level: "3" dtmf_avt_payload: "101" timer_t1: "500" timer_t2: "4000" sip_retx: "10" sip_invite_retx: "6" timer_invite_expires: "180" sntp_mode: "directedbroadcast" sntp_server: "time-a-g.nist.gov" time_zone: "8" time_format_24hr: "0" dst_offset: "0" dst_start_month: "April" dst_start_day: "" dst_start_day_of_week: "Sun" dst_start_week_of_month: "1" dst_start_time: "2" dst_stop_month: "Nov" dst_stop_day: "1" dst_stop_day_of_week: "Sunday" dst_stop_week_of_month: "" dst_stop_time: "2" dst_auto_adjust: "1" messages_uri: "*99" services_url: "http://example.domain.ext/services/menu.xml"; directory_url: "http://example.domain.ext/services/directory.php"; logo_url: "http://example.domain.ext/imagename.bmp"; http_proxy_addr: "" http_pr
[PATCH v2] drm/hisilicon: Add load and unload callback functions
Add the callback functions of drm_driver structure member functions
load and unload, no need to call load in the hibmc_pci_probe function
and unload in the hibmc_pci_remove function.
v2:
remove the hibmc_unload called from hibmc_pic_remove.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
index 0d4e902..10042cf 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
@@ -27,6 +27,9 @@
DEFINE_DRM_GEM_FOPS(hibmc_fops);
+static int hibmc_load(struct drm_device *dev, unsigned long flags);
+static void hibmc_unload(struct drm_device *dev);
+
static irqreturn_t hibmc_drm_interrupt(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *)arg;
@@ -63,6 +66,8 @@ static const struct drm_driver hibmc_driver = {
.dumb_map_offset= drm_gem_vram_driver_dumb_mmap_offset,
.gem_prime_mmap = drm_gem_prime_mmap,
.irq_handler= hibmc_drm_interrupt,
+ .load = hibmc_load,
+ .unload = hibmc_unload,
};
static int __maybe_unused hibmc_pm_suspend(struct device *dev)
@@ -248,7 +253,7 @@ static int hibmc_hw_init(struct hibmc_drm_private *priv)
return 0;
}
-static int hibmc_unload(struct drm_device *dev)
+static void hibmc_unload(struct drm_device *dev)
{
drm_atomic_helper_shutdown(dev);
@@ -256,11 +261,9 @@ static int hibmc_unload(struct drm_device *dev)
drm_irq_uninstall(dev);
pci_disable_msi(dev->pdev);
-
- return 0;
}
-static int hibmc_load(struct drm_device *dev)
+static int hibmc_load(struct drm_device *dev, unsigned long flags)
{
struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
int ret;
@@ -335,12 +338,6 @@ static int hibmc_pci_probe(struct pci_dev *pdev,
goto err_return;
}
- ret = hibmc_load(dev);
- if (ret) {
- drm_err(dev, "failed to load hibmc: %d\n", ret);
- goto err_return;
- }
-
ret = drm_dev_register(dev, 0);
if (ret) {
drm_err(dev, "failed to register drv for userspace access:
%d\n",
@@ -363,7 +360,6 @@ static void hibmc_pci_remove(struct pci_dev *pdev)
struct drm_device *dev = pci_get_drvdata(pdev);
drm_dev_unregister(dev);
- hibmc_unload(dev);
}
static const struct pci_device_id hibmc_pci_table[] = {
--
2.7.4
Re: [PATCH v7 02/12] dt-bindings: mfd: bd9571mwv: Document BD9574MWF
On Thu, 24 Dec 2020, Yoshihiro Shimoda wrote: > Document other similar specification chip BD9574MWF. > > Signed-off-by: Yoshihiro Shimoda > --- > Documentation/devicetree/bindings/mfd/bd9571mwv.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) For my own reference (apply this as-is to your sign-off block): Acked-for-MFD-by: Lee Jones -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH v7 10/12] mfd: bd9571mwv: Use devm_regmap_add_irq_chip()
Hello!
On 24.12.2020 10:04, Yoshihiro Shimoda wrote:
Use dev_regmap_add_irq_chip() to simplify the code.
devm_?
Signed-off-by: Yoshihiro Shimoda
Acked-for-MFD-by: Lee Jones
Reviewed-by: Matti Vaittinen
Reviewed-by: Geert Uytterhoeven
---
drivers/mfd/bd9571mwv.c | 27 ++-
1 file changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/mfd/bd9571mwv.c b/drivers/mfd/bd9571mwv.c
index e68c3fa..49e968e 100644
--- a/drivers/mfd/bd9571mwv.c
+++ b/drivers/mfd/bd9571mwv.c
@@ -170,31 +170,17 @@ static int bd9571mwv_probe(struct i2c_client *client,
if (ret)
return ret;
- ret = regmap_add_irq_chip(bd->regmap, bd->irq, IRQF_ONESHOT, 0,
- &bd9571mwv_irq_chip, &bd->irq_data);
+ ret = devm_regmap_add_irq_chip(bd->dev, bd->regmap, bd->irq,
+ IRQF_ONESHOT, 0, &bd9571mwv_irq_chip,
+ &bd->irq_data);
if (ret) {
dev_err(bd->dev, "Failed to register IRQ chip\n");
return ret;
}
[...]
MBR, Sergei
Re: [PATCH v7 11/12] mfd: bd9571mwv: Make the driver more generic
On Thu, 24 Dec 2020, Yoshihiro Shimoda wrote: > From: Khiem Nguyen > > Since the driver supports BD9571MWV PMIC only, this patch makes > the functions and data structure become more generic so that > it can support other PMIC variants as well. Also remove printing > part name which Lee Jones suggested. > > Signed-off-by: Khiem Nguyen > Co-developed-by: Yoshihiro Shimoda > Signed-off-by: Yoshihiro Shimoda > Reviewed-by: Matti Vaittinen > --- > drivers/mfd/bd9571mwv.c | 77 > +++ > include/linux/mfd/bd9571mwv.h | 18 ++ > 2 files changed, 43 insertions(+), 52 deletions(-) For my own reference (apply this as-is to your sign-off block): Acked-for-MFD-by: Lee Jones -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog
How do I account for the Linux kernel development team
How do I account for the Linux kernel development team？
Re: [tip:efi/core 3/7] /tmp/slab-258052.s:9870: Error: unrecognized opcode `zext.b a2,a2'
Hi Ard, On Wed, Dec 23, 2020 at 11:43:45PM +0100, Ard Biesheuvel wrote: > I hope this report is not holding up the PR for efi/core? I was just looking at that yesterday... But nah, lemme send it. Thx. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette
[GIT PULL] efi/core for v5.11
Hi Linus, please pull the EFI updates for v5.11. They got delayed due to a last minute ia64 build issue which got fixed in the meantime: https://lkml.kernel.org/r/87o8iwdtbj@nanos.tec.linutronix.de and now the lot is all clear. Thx. --- The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec: Linux 5.10-rc1 (2020-10-25 15:14:11 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tags/efi_updates_for_v5.11 for you to fetch changes up to 3dcb8b53cbd2cc5618863b19ef00f8ea82f27e83: Merge tag 'efi-next-for-v5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into efi/core (2020-12-15 12:14:38 +0100) EFI updates collected by Ard Biesheuvel: - Don't move BSS section around pointlessly in the x86 decompressor - Refactor helper for discovering the EFI secure boot mode - Wire up EFI secure boot to IMA for arm64 - Some fixes for the capsule loader - Expose the RT_PROP table via the EFI test module - Relax DT and kernel placement restrictions on ARM + followup fixes: - fix the build breakage on IA64 caused by recent capsule loader changes - suppress a type mismatch build warning in the expansion of EFI_PHYS_ALIGN on ARM Ard Biesheuvel (7): efi: x86/xen: switch to efi_get_secureboot_mode helper efi: capsule: use atomic kmap for transient sglist mappings efi: capsule: clean scatter-gather entries from the D-cache efi: arm: reduce minimum alignment of uncompressed kernel efi: stub: get rid of efi_get_max_fdt_addr() efi: ia64: disable the capsule loader efi: arm: force use of unsigned type for EFI_PHYS_ALIGN Arvind Sankar (1): efi/x86: Only copy the compressed kernel image in efi_relocate_kernel() Chester Lin (3): efi: generalize efi_get_secureboot ima: generalize x86/EFI arch glue for other EFI architectures arm64/ima: add ima_arch support Geert Uytterhoeven (1): efi/libstub: EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER should not default to yes Heinrich Schuchardt (2): efi/libstub/x86: simplify efi_is_native() efi/efi_test: read RuntimeServicesSupported Thomas Gleixner (1): Merge tag 'efi-next-for-v5.11-3' of git://git.kernel.org/.../efi/efi into efi/core arch/arm/include/asm/efi.h | 24 ++-- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/efi.h | 11 +++--- arch/riscv/include/asm/efi.h | 6 --- arch/x86/boot/compressed/Makefile | 2 +- arch/x86/include/asm/efi.h | 5 ++- arch/x86/kernel/Makefile | 2 - arch/x86/xen/efi.c | 37 +- drivers/firmware/efi/Kconfig | 4 +- drivers/firmware/efi/Makefile | 5 ++- drivers/firmware/efi/capsule.c | 16 +++- drivers/firmware/efi/libstub/efi-stub.c| 1 - drivers/firmware/efi/libstub/efistub.h | 3 +- drivers/firmware/efi/libstub/fdt.c | 3 +- drivers/firmware/efi/libstub/secureboot.c | 44 - drivers/firmware/efi/libstub/x86-stub.c| 5 ++- drivers/firmware/efi/test/efi_test.c | 16 drivers/firmware/efi/test/efi_test.h | 3 ++ include/linux/efi.h| 33 security/integrity/ima/Makefile| 4 ++ .../ima_arch.c => security/integrity/ima/ima_efi.c | 45 ++ 21 files changed, 133 insertions(+), 137 deletions(-) rename arch/x86/kernel/ima_arch.c => security/integrity/ima/ima_efi.c (60%) -- Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg
Re: [tip:efi/core 3/7] /tmp/slab-258052.s:9870: Error: unrecognized opcode `zext.b a2,a2'
On Thu, 24 Dec 2020 at 09:55, Borislav Petkov wrote: > > Hi Ard, > > On Wed, Dec 23, 2020 at 11:43:45PM +0100, Ard Biesheuvel wrote: > > I hope this report is not holding up the PR for efi/core? > > I was just looking at that yesterday... > > But nah, lemme send it. > Cheers,
Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote: > > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski wrote: > > > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote: > > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier > > > board. > > > > > > Genaral features: > > > - Ethernet 10/100 > > > - Wifi/BT > > > - USB Type A/OTG > > > - Audio Out > > > - CAN > > > - LVDS panel connector > > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. > > > > > > i.Core MX8M Mini needs to mount on top of this Carrier board for > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board. > > > > > > Add support for it. > > > > > > Signed-off-by: Matteo Lisi > > > Signed-off-by: Jagan Teki > > > --- > > > Changes for v3: > > > - don't maintain common nodes and include it, if no feature diff > > > Changes for v2: > > > - enabled fec1 node > > > - updated commit message > > > - dropped engicam from filename since it aligned with imx6 engicam > > > dts files naming conventions. > > > - add i2c nodes > > > - fixed v1 comments > > > > > > arch/arm64/boot/dts/freescale/Makefile| 1 + > > > .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++ > > > .../freescale/imx8mm-icore-mx8mm-ctouch2.dts | 21 + > > > 3 files changed, 104 insertions(+) > > > create mode 100644 > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi > > > > You split some common part to ctouch2.dtsi so it can be reused in > > multiple places. I saw so far only one usage, where are the others? > > To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier > board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display), > since DSI is not yet mainlined, I didn't add this yet. If I understand correctly: it is a DTSI which is included only by one DTS... and DTS does not have any other nodes. This as well is not the design which makes any sense. We do not create empty DTS files which only include one more DTSI. The contents of imx8mm-engicam-ctouch2.dtsi should be directly in imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 - you overcomplicate simple stuff. It really looks like you ignored the comments from v1 in multiple places. The same applies to imx8mm-engicam-edimm2.2.dtsi. Best regards, Krzysztof
Re: [PATCH] ARM: dts: sun8i-v3s: Add CSI0 MCLK pin definition
Hi,
Le Tue 22 Dec 20, 09:17, Jernej Škrabec a écrit :
> Dne petek, 18. december 2020 ob 20:50:33 CET je Paul Kocialkowski napisal(a):
> > This adds a device-tree definition for the CSI0 MCLK pin,
> > which can be used for feeding MIPI CSI-2 sensors.
> >
> > Signed-off-by: Paul Kocialkowski
>
> Is this used anywhere? Current policy is to add pin definitions only if any
> user exists.
Ah right, sorry. I'll resend this when adding a board that uses it!
Cheers,
Paul
> Best regards,
> Jernej
>
> > ---
> > arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi
> > b/arch/arm/boot/dts/sun8i-v3s.dtsi index a9f5795d4e57..bff822b9fa01 100644
> > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> > @@ -337,6 +337,12 @@ pio: pinctrl@1c20800 {
> > interrupt-controller;
> > #interrupt-cells = <3>;
> >
> > + /omit-if-no-ref/
> > + csi0_mclk_pin: csi0-mclk-pin {
> > + pins = "PE20";
> > + function = "csi_mipi";
> > + };
> > +
> > /omit-if-no-ref/
> > csi1_8bit_pins: csi1-8bit-pins {
> > pins = "PE0", "PE2", "PE3",
> "PE8", "PE9",
>
>
>
>
--
Developer of free digital technology and hardware support.
Website: https://www.paulk.fr/
Coding blog: https://code.paulk.fr/
Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/
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Re: [PATCH v2 1/2] dt-bindings: pwm: allwinner: Add V3s compatible description
Hi, Le Tue 22 Dec 20, 09:21, Jernej Škrabec a écrit : > Dne petek, 18. december 2020 ob 21:54:35 CET je Paul Kocialkowski napisal(a): > > Introduce bindings description for the V3s PWM, which is > > register-compatible with the A20 PWM. > > > > Signed-off-by: Paul Kocialkowski > > This is meant to be used together with V3s PWM patch you recently send? Can > you please resend them together, with fixed compatible in DT node? Currently > it's not clear why this patch is needed and PWM patch will need fix anyway. I've sent them together (this one is v2 1/2 and 2/2 is the PWM dt patch). You can grab it at: https://lore.kernel.org/patchwork/patch/1355289/ if it didn't reach your emails. Cheers, Paul > > --- > > .../devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml > > b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index > > 7dcab2bf8128..04ff708fdc86 100644 > > --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml > > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml > > @@ -24,6 +24,9 @@ properties: > >- items: > >- const: allwinner,sun8i-a83t-pwm > >- const: allwinner,sun8i-h3-pwm > > + - items: > > + - const: allwinner,sun8i-v3s-pwm > > + - const: allwinner,sun7i-a20-pwm > >- items: > >- const: allwinner,sun50i-a64-pwm > >- const: allwinner,sun5i-a13-pwm > > > > -- Developer of free digital technology and hardware support. Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/ signature.asc Description: PGP signature
Re: [PATCH 3/3] overlayfs: Report writeback errors on upper
On Wed, Dec 23, 2020 at 10:44 PM Matthew Wilcox wrote:
>
> On Wed, Dec 23, 2020 at 08:21:41PM +, Sargun Dhillon wrote:
> > On Wed, Dec 23, 2020 at 08:07:46PM +, Matthew Wilcox wrote:
> > > On Wed, Dec 23, 2020 at 07:29:41PM +, Sargun Dhillon wrote:
> > > > On Wed, Dec 23, 2020 at 06:50:44PM +, Matthew Wilcox wrote:
> > > > > On Wed, Dec 23, 2020 at 06:20:27PM +, Sargun Dhillon wrote:
> > > > > > I fail to see why this is neccessary if you incorporate error
> > > > > > reporting into the
> > > > > > sync_fs callback. Why is this separate from that callback? If you
> > > > > > pickup Jeff's
> > > > > > patch that adds the 2nd flag to errseq for "observed", you should
> > > > > > be able to
> > > > > > stash the first errseq seen in the ovl_fs struct, and do the
> > > > > > check-and-return
> > > > > > in there instead instead of adding this new infrastructure.
> > > > >
> > > > > You still haven't explained why you want to add the "observed" flag.
> > > >
> > > >
> > > > In the overlayfs model, many users may be using the same filesystem
> > > > (super block)
> > > > for their upperdir. Let's say you have something like this:
> > > >
> > > > /workdir [Mounted FS]
> > > > /workdir/upperdir1 [overlayfs upperdir]
> > > > /workdir/upperdir2 [overlayfs upperdir]
> > > > /workdir/userscratchspace
> > > >
> > > > The user needs to be able to do something like:
> > > > sync -f ${overlayfs1}/file
> > > >
> > > > which in turn will call sync on the the underlying filesystem (the one
> > > > mounted
> > > > on /workdir), and can check if the errseq has changed since the
> > > > overlayfs was
> > > > mounted, and use that to return an error to the user.
> > >
> > > OK, but I don't see why the current scheme doesn't work for this. If
> > > (each instance of) overlayfs samples the errseq at mount time and then
> > > check_and_advances it at sync time, it will see any error that has
> > > occurred
> > > since the mount happened (and possibly also an error which occurred before
> > > the mount happened, but hadn't been reported to anybody before).
> > >
> >
> > If there is an outstanding error at mount time, and the SEEN flag is unset,
> > subsequent errors will not increment the counter, until the user calls sync
> > on
> > the upperdir's filesystem. If overlayfs calls check_and_advance on the
> > upperdir's
> > super block at any point, it will then set the seen block, and if the user
> > calls
> > syncfs on the upperdir, it will not return that there is an outstanding
> > error,
> > since overlayfs just cleared it.
>
> Your concern is this case:
>
> fs is mounted on /workdir
> /workdir/A is written to and then closed.
> writeback happens and -EIO happens, but there's nobody around to care.
> /workdir/upperdir1 becomes part of an overlayfs mount
> overlayfs samples the error
> a user writes to /workdir/B, another -EIO occurs, but nothing happens
> someone calls syncfs on /workdir/upperdir/A, gets the EIO.
> a user opens /workdir/B and calls syncfs, but sees no error
>
> do i have that right? or is it something else?
IMO it is something else. Others may disagree.
IMO the level of interference between users accessing overlay and users
accessing upper fs directly is not well defined and it can stay this way.
Concurrent access to /workdir/upperdir/A via overlay and underlying fs
is explicitly warranted against in Documentation/filesystems/overlayfs.rst#
Changes to underlying filesystems:
"Changes to the underlying filesystems while part of a mounted overlay
filesystem are not allowed. If the underlying filesystem is changed,
the behavior of the overlay is undefined, though it will not result in
a crash or deadlock."
The question is whether syncfs(open(/workdir/B)) is considered
"Changes to the underlying filesystems". Regardless of the answer,
this is not an interesting case IMO.
The real issue is with interference between overlays that share the
same upper fs, because this is by far and large the common use case
that is creating real problems for a lot of container users.
Workloads running inside containers (with overlayfs storage driver)
will never be as isolated as workloads running inside VMs, but it
doesn't mean we cannot try to improve.
In current master, syncfs() on any file by any container user will
result in full syncfs() of the upperfs, which is very bad for container
isolation. This has been partly fixed by Chengguang Xu [1] and I expect
his work will be merged soon. Overlayfs still does not do the writeback
and syncfs() in overlay still waits for all upper fs writeback to complete,
but at least syncfs() in overlay only kicks writeback for upper fs files
dirtied by this overlay.
[1]
https://lore.kernel.org/linux-unionfs/cajfpegsbb4itxw8zyurfvnc63zg7ku7vzpsnuzhasyzh-d5...@mail.gmail.com/
Sharing the same SEEN flag among thousands of containers is also
far from ideal, because effectively this means that any given workload
in any single container has very little chance of
drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes address space '__iomem' of expression
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-184-g1b896707-dirty
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ac6795fcc085e8d03649f1bbd0d70aaff612cad
git remote add linus
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 2ac6795fcc085e8d03649f1bbd0d70aaff612cad
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
"sparse warnings: (new ones prefixed by >>)"
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes
>> address space '__iomem' of expression
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:72:24: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:72:24: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: cast removes
address space '__iomem' of expression
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: incorrect type in
argument 1 (different address spaces) @@ expected void const volatile
[noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:70:22: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:70:22: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:219:36: sparse: sparse: incorrect type in
argument 2 (different address spaces) @@ expected void * @@ got struct
clock_event_device [noderef] __percpu * @@
drivers/clocksource/timer-clint.c:219:36: sparse: expected void *
drivers/clocksource/timer-clint.c:219:36: sparse: got struct
clock_event_device [noderef] __percpu *
vim +/__iomem +72 drivers/clocksource/timer-clint.c
58
59 #ifdef CONFIG_64BIT
60 static u64 notrace clint_get_cycles64(void)
61 {
62 return clint_get_cycles();
63 }
64 #else /* CONFIG_64BIT */
65 static u64 notrace clint_get_cycles64(void)
66 {
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
> 72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75 }
76 #endif /* CONFIG_64BIT */
77
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes address space '__iomem' of expression
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 2ac6795fcc085e8d03649f1bbd0d70aaff612cad clocksource/drivers: Add CLINT
timer driver
date: 4 months ago
config: riscv-randconfig-s031-20201221 (attached as .config)
compiler: riscv32-linux-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-184-g1b896707-dirty
#
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ac6795fcc085e8d03649f1bbd0d70aaff612cad
git remote add linus
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 2ac6795fcc085e8d03649f1bbd0d70aaff612cad
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
"sparse warnings: (new ones prefixed by >>)"
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: cast removes
>> address space '__iomem' of expression
>> drivers/clocksource/timer-clint.c:72:24: sparse: sparse: incorrect type in
>> argument 1 (different address spaces) @@ expected void const volatile
>> [noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:72:24: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:72:24: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: cast removes
address space '__iomem' of expression
drivers/clocksource/timer-clint.c:70:22: sparse: sparse: incorrect type in
argument 1 (different address spaces) @@ expected void const volatile
[noderef] __iomem *addr @@ got unsigned int [usertype] * @@
drivers/clocksource/timer-clint.c:70:22: sparse: expected void const
volatile [noderef] __iomem *addr
drivers/clocksource/timer-clint.c:70:22: sparse: got unsigned int
[usertype] *
drivers/clocksource/timer-clint.c:219:36: sparse: sparse: incorrect type in
argument 2 (different address spaces) @@ expected void * @@ got struct
clock_event_device [noderef] __percpu * @@
drivers/clocksource/timer-clint.c:219:36: sparse: expected void *
drivers/clocksource/timer-clint.c:219:36: sparse: got struct
clock_event_device [noderef] __percpu *
vim +/__iomem +72 drivers/clocksource/timer-clint.c
58
59 #ifdef CONFIG_64BIT
60 static u64 notrace clint_get_cycles64(void)
61 {
62 return clint_get_cycles();
63 }
64 #else /* CONFIG_64BIT */
65 static u64 notrace clint_get_cycles64(void)
66 {
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
> 72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75 }
76 #endif /* CONFIG_64BIT */
77
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
RE: [PATCH v1 1/2] scsi: ufs: Replace sprintf and snprintf with sysfs_emit
> > From: Bean Huo > > sprintf and snprintf may cause output defect in sysfs content, it is > better to use new added sysfs_emit function which knows the size of the > temporary buffer. > > Suggested-by: Greg Kroah-Hartman > Signed-off-by: Bean Huo Reviewed-by: Avri Altman
Re: [PATCH 5.10 24/40] f2fs: fix to seek incorrect data offset in inline data file
On 2020/12/24 15:52, Greg Kroah-Hartman wrote: On Thu, Dec 24, 2020 at 09:11:53AM +0800, Chao Yu wrote: Hi Greg, Thanks a lot for helping to resend and merge the patch. :) Not a problem, glad to help out. In the future, all you need to do is give us the git commit id that needs to be backported if it applies cleanly, no need to send the whole patch! I will keep this in mind, thanks for your reminder. Thanks, thanks, greg k-h .
Re: [PATCH 5.10 00/40] 5.10.3-rc1 review
On Wed, 2020-12-23 at 16:33 +0100, Greg Kroah-Hartman wrote: > This is the start of the stable review cycle for the 5.10.3 release. > There are 40 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, > please > let me know. > > Responses should be made by Fri, 25 Dec 2020 15:05:02 +. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.10.3-rc1.gz > or in the git tree and branch at: > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux- > stable-rc.git linux-5.10.y > and the diffstat can be found below. > > thanks, > > greg k-h hello , Compiled and booted 5.10.3-rc1+. dmesg -l err gives... --x-x---> 43.190922] Bluetooth: hci0: don't support firmware rome 0x31010100 --x---x-> My Bluetooth is Off. Tested-by: Jeffrin Jose T -- software engineer rajagiri school of engineering and technology - autonomous
Re: [PATCH v4 2/7] regulator: dt-bindings: Document max8997-pmic nodes
On Wed, Dec 23, 2020 at 01:42:43PM +, Timon Baetz wrote: > Add maxim,max8997-battery and maxim,max8997-muic optional nodes. > > Signed-off-by: Timon Baetz I already acked this, why did you skip my tag? Best regards, Krzysztof > --- > .../bindings/regulator/max8997-regulator.txt | 12 > 1 file changed, 12 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt > b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt > index 6fe825b8ac1b..faaf2bbf0272 100644 > --- a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt > +++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt > @@ -53,6 +53,18 @@ Additional properties required if either of the optional > properties are used: > - max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used >for dvs. The format of the gpio specifier depends in the gpio controller. > > +Optional nodes: > +- charger: Node for configuring the charger driver. > + Required properties: > + - compatible: "maxim,max8997-battery" > + Optional properties: > + - extcon: extcon specifier for charging events > + - charger-supply: regulator node for charging current > + > +- muic: Node used only by extcon consumers. > + Required properties: > + - compatible: "maxim,max8997-muic" > + > Regulators: The regulators of max8997 that have to be instantiated should be > included in a sub-node named 'regulators'. Regulator nodes included in this > sub-node should be of the format as listed below. > -- > 2.25.1 > >
Re: [PATCH AUTOSEL 5.4 075/130] net/lapb: fix t1 timer handling for LAPB_STATE_0
On Wed, Dec 23, 2020 at 9:01 AM Xie He wrote: > > I don't think this patch is suitable for stable branches. This patch is > part of a patch series that changes the lapb module from "establishing the > L2 connection only when needed by L3", to "establishing the L2 connection > automatically whenever we are able to". This is a behavioral change. It > should be seen as a new feature. It is not a bug fix. Applying this patch without other patches in the same series will also introduce problems, because this patch relies on part of the changes in the subsequent patch in the same series to be correct. Hi Martin, It's better that we avoid using words like "fix" in non-bug-fix patches, and make every patch work on its own without subsequent patches. Otherwise we'll make people confused.
Re: [PATCH v4 4/7] power: supply: max8997_charger: Set CHARGER current limit
On Wed, Dec 23, 2020 at 01:43:05PM +, Timon Baetz wrote:
> Register for extcon notification and set charging current depending on
> the detected cable type. Current values are taken from vendor kernel,
> where most charger types end up setting 650mA [0].
>
> Also enable and disable the CHARGER regulator based on extcon events.
>
> [0]
> https://github.com/krzk/linux-vendor-backup/blob/samsung/galaxy-s2-epic-4g-touch-sph-d710-exynos4210-dump/drivers/misc/max8997-muic.c#L1675-L1678
>
> Signed-off-by: Timon Baetz
> ---
> drivers/power/supply/max8997_charger.c | 89 ++
> 1 file changed, 89 insertions(+)
>
> diff --git a/drivers/power/supply/max8997_charger.c
> b/drivers/power/supply/max8997_charger.c
> index 1947af25879a..e8532e2af451 100644
> --- a/drivers/power/supply/max8997_charger.c
> +++ b/drivers/power/supply/max8997_charger.c
> @@ -6,12 +6,14 @@
> // MyungJoo Ham
>
> #include
> +#include
> #include
> #include
> #include
> #include
> #include
> #include
> +#include
>
> /* MAX8997_REG_STATUS4 */
> #define DCINOK_SHIFT 1
> @@ -31,6 +33,10 @@ struct charger_data {
> struct device *dev;
> struct max8997_dev *iodev;
> struct power_supply *battery;
> + struct regulator *reg;
> + struct extcon_dev *edev;
> + struct notifier_block extcon_nb;
> + struct work_struct extcon_work;
> };
>
> static enum power_supply_property max8997_battery_props[] = {
> @@ -88,6 +94,67 @@ static int max8997_battery_get_property(struct
> power_supply *psy,
> return 0;
> }
>
> +static void max8997_battery_extcon_evt_stop_work(void *data)
> +{
> + struct charger_data *charger = data;
> +
> + cancel_work_sync(&charger->extcon_work);
> +}
> +
> +static void max8997_battery_extcon_evt_worker(struct work_struct *work)
> +{
> + struct charger_data *charger =
> + container_of(work, struct charger_data, extcon_work);
> + struct extcon_dev *edev = charger->edev;
> + int current_limit;
> +
> + if (extcon_get_state(edev, EXTCON_CHG_USB_SDP) > 0) {
> + dev_dbg(charger->dev, "USB SDP charger is connected\n");
> + current_limit = 45;
> + } else if (extcon_get_state(edev, EXTCON_CHG_USB_DCP) > 0) {
> + dev_dbg(charger->dev, "USB DCP charger is connected\n");
> + current_limit = 65;
> + } else if (extcon_get_state(edev, EXTCON_CHG_USB_FAST) > 0) {
> + dev_dbg(charger->dev, "USB FAST charger is connected\n");
> + current_limit = 65;
> + } else if (extcon_get_state(edev, EXTCON_CHG_USB_SLOW) > 0) {
> + dev_dbg(charger->dev, "USB SLOW charger is connected\n");
> + current_limit = 65;
> + } else if (extcon_get_state(edev, EXTCON_CHG_USB_CDP) > 0) {
> + dev_dbg(charger->dev, "USB CDP charger is connected\n");
> + current_limit = 65;
> + } else {
> + dev_dbg(charger->dev, "USB charger is diconnected\n");
> + current_limit = -1;
> + }
> +
> + if (current_limit > 0) {
> + int ret = regulator_set_current_limit(charger->reg,
> current_limit, current_limit);
> +
> + if (ret) {
> + dev_err(charger->dev, "failed to set current limit:
> %d\n", ret);
> + return;
> + }
> + ret = regulator_enable(charger->reg);
> + if (ret)
> + dev_err(charger->dev, "failed to enable regulator:
> %d\n", ret);
> + } else {
> + int ret = regulator_disable(charger->reg);
> +
> + if (ret)
> + dev_err(charger->dev, "failed to disable regulator:
> %d\n", ret);
> + }
> +}
> +
> +static int max8997_battery_extcon_evt(struct notifier_block *nb,
> + unsigned long event, void *param)
> +{
> + struct charger_data *charger =
> + container_of(nb, struct charger_data, extcon_nb);
> + schedule_work(&charger->extcon_work);
> + return NOTIFY_OK;
> +}
> +
> static const struct power_supply_desc max8997_battery_desc = {
> .name = "max8997_pmic",
> .type = POWER_SUPPLY_TYPE_BATTERY,
> @@ -170,6 +237,28 @@ static int max8997_battery_probe(struct platform_device
> *pdev)
> return PTR_ERR(charger->battery);
> }
>
> + charger->reg = devm_regulator_get(&pdev->dev, "charger");
Since you do not use get_optional, you will always get a dummy
regulator. In case of error, you should either print it or entirely fail
the probe. Silently continuing makes it difficult to spot errors.
Since the driver could operate in case of extcon/regulator error, just
dev_err() so failure will be spotted with dmesg.
It will complain on older DTBs because you are introducing incompatible
change, but that's expected. Just correct all other in-tree DTS.
Best regards,
Krzysztof
> + charger->edev = extcon_get_e
memory leak in ext4_multi_mount_protect
Hello, syzbot found the following issue on: HEAD commit:467f8165 Merge tag 'close-range-cloexec-unshare-v5.11' of .. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=12b7fccb50 kernel config: https://syzkaller.appspot.com/x/.config?x=37c889fb8b2761af dashboard link: https://syzkaller.appspot.com/bug?extid=d9e482e303930fa4f6ff compiler: gcc (GCC) 10.1.0-syz 20200507 syz repro: https://syzkaller.appspot.com/x/repro.syz?x=1230f8a750 IMPORTANT: if you fix the issue, please add the following tag to the commit: Reported-by: syzbot+d9e482e303930fa4f...@syzkaller.appspotmail.com BUG: memory leak unreferenced object 0x88812560f120 (size 32): comm "syz-executor.3", pid 11391, jiffies 4294966956 (age 10.520s) hex dump (first 32 bytes): 28 2a e4 20 81 88 ff ff 00 f8 32 24 81 88 ff ff (*. ..2$ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 backtrace: [<1fd6256c>] kmalloc include/linux/slab.h:552 [inline] [<1fd6256c>] ext4_multi_mount_protect+0x4a6/0x5d0 fs/ext4/mmp.c:367 [] ext4_fill_super+0x551e/0x5ac0 fs/ext4/super.c:4779 [ ] mount_bdev+0x223/0x260 fs/super.c:1366 [ ] legacy_get_tree+0x2b/0x90 fs/fs_context.c:592 [<5310f7d7>] vfs_get_tree+0x28/0x100 fs/super.c:1496 [<6fc429ab>] do_new_mount fs/namespace.c:2875 [inline] [<6fc429ab>] path_mount+0xc5e/0x1170 fs/namespace.c:3205 [<4f8c23d3>] do_mount fs/namespace.c:3218 [inline] [<4f8c23d3>] __do_sys_mount fs/namespace.c:3426 [inline] [<4f8c23d3>] __se_sys_mount fs/namespace.c:3403 [inline] [<4f8c23d3>] __x64_sys_mount+0x18e/0x1d0 fs/namespace.c:3403 [<2cff8f95>] do_syscall_64+0x2d/0x70 arch/x86/entry/common.c:46 [<779cd3d5>] entry_SYSCALL_64_after_hwframe+0x44/0xa9 --- This report is generated by a bot. It may contain errors. See https://goo.gl/tpsmEJ for more information about syzbot. syzbot engineers can be reached at syzkal...@googlegroups.com. syzbot will keep track of this issue. See: https://goo.gl/tpsmEJ#status for how to communicate with syzbot. syzbot can test patches for this issue, for details see: https://goo.gl/tpsmEJ#testing-patches
Re: [PATCH 00/15] usb: serial: avoid using usb_control_msg() directly
On Fri, Dec 4, 2020 at 2:38 PM Johan Hovold wrote: > > Hi Himadri, > > and sorry about the late feedback on this one. I'm still trying to dig > myself out of some backlog. > > On Wed, Nov 04, 2020 at 12:16:48PM +0530, Himadri Pandya wrote: > > There are many usages of usb_control_msg() that can use the new wrapper > > functions usb_contro_msg_send() & usb_control_msg_recv() for better > > error checks on short reads and writes. Hence use them whenever possible > > and avoid using usb_control_msg() directly. > > Replacing working code with shiny new helpers unfortunately often ends > up introducing new bugs and I'm afraid there are a few examples of that > in this series as well. > > I'll comment on the patches individually, but my impression is that we > should primarily use these helpers to replace code which allocates a > temporary buffer for each transfer as otherwise there's no clear gain > from using them. > > Some of your patches contains unrelated changes which needs to go in > separate patches if they're to be included at all. > > Please also try to write dedicated commit messages rater than reusing > more or less the same stock message since not everything in these > messages apply to each patch. You never mention that these helpers > nicely hides the allocation of temporary transfer buffers in some cases > for examples. In other places they instead introduce additional > allocations which at least should have been highlighted. > > > Himadri Pandya (15): > > usb: serial: ark3116: use usb_control_msg_recv() and > > usb_control_msg_send() > > Nit: please also use an uppercase "USB" prefix. Hi Johan, Thanks for reviewing this series and sorry for the late reply. I'll soon send a v2 according to your comments. Best regards, Himadri > > > usb: serial: belkin_sa: use usb_control_msg_send() > > usb: serial: ch314: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: cp210x: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: cypress_m8: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: f81232: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: f81534: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: ftdi_sio: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: io_edgeport: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: io_ti: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: ipaq: use usb_control_msg_send() > > usb: serial: ipw: use usb_control_msg_send() > > usb: serial: iuu_phoenix: use usb_control_msg_send() > > usb: serial: keyspan_pda: use usb_control_msg_recv() and > > usb_control_msg_send() > > usb: serial: kl5kusb105: use usb_control_msg_recv() and > > usb_control_msg_send() > > > > drivers/usb/serial/ark3116.c | 29 + > > drivers/usb/serial/belkin_sa.c | 35 +++--- > > drivers/usb/serial/ch341.c | 45 +++- > > drivers/usb/serial/cp210x.c | 148 +++-- > > drivers/usb/serial/cypress_m8.c | 38 --- > > drivers/usb/serial/f81232.c | 88 +++ > > drivers/usb/serial/f81534.c | 63 +++ > > drivers/usb/serial/ftdi_sio.c| 182 +-- > > drivers/usb/serial/io_edgeport.c | 73 + > > drivers/usb/serial/io_ti.c | 28 ++--- > > drivers/usb/serial/ipaq.c| 9 +- > > drivers/usb/serial/ipw.c | 107 ++ > > drivers/usb/serial/iuu_phoenix.c | 5 +- > > drivers/usb/serial/keyspan_pda.c | 172 - > > drivers/usb/serial/kl5kusb105.c | 94 > > 15 files changed, 406 insertions(+), 710 deletions(-) > > Johan
[PATCH] xfs: fix system crash caused by null bp->b_pages
We have encountered the following problems several times:
1、A raid slot or hardware problem causes block device loss.
2、Continue to issue IO requests to the problematic block device.
3、The system possibly crash after a few hours.
dmesg log as below:
[15205901.268313] blk_partition_remap: fail for partition 1
[15205901.319309] blk_partition_remap: fail for partition 1
[15205901.319341] blk_partition_remap: fail for partition 1
[15205901.319873] sysctl (3998546): drop_caches: 3
[15205901.371379] BUG: unable to handle kernel NULL pointer dereference at
[15205901.372602] IP: xfs_buf_offset+0x32/0x60 [xfs]
[15205901.373605] PGD 0 P4D 0
[15205901.374690] Oops: [#1] SMP
[15205901.375629] Modules linked in:
[15205901.382445] CPU: 6 PID: 18545 Comm: xfsaild/sdh1 Kdump: loaded Tainted: G
[15205901.384728] Hardware name:
[15205901.385830] task: 885216939e80 task.stack: b28ba9b38000
[15205901.386974] RIP: 0010:xfs_buf_offset+0x32/0x60 [xfs]
[15205901.388044] RSP: 0018:b28ba9b3bc68 EFLAGS: 00010246
[15205901.389021] RAX: RBX: RCX:
000b
[15205901.390016] RDX: RSI: RDI:
88627bebf000
[15205901.391075] RBP: b28ba9b3bc98 R08: 88627bebf000 R09:
0001802a000d
[15205901.392031] R10: 88521f3a0240 R11: 88627bebf000 R12:
88521041e000
[15205901.392950] R13: 0020 R14: 88627bebf000 R15:
[15205901.393858] FS: () GS:88521f38()
knlGS:
[15205901.394774] CS: 0010 DS: ES: CR0: 80050033
[15205901.395756] CR2: CR3: 00099bc09001 CR4:
007606e0
[15205901.396904] DR0: DR1: DR2:
[15205901.397869] DR3: DR6: fffe0ff0 DR7:
0400
[15205901.398836] PKRU: 5554
[15205901.400111] Call Trace:
[15205901.401058] ? xfs_inode_buf_verify+0x8e/0xf0 [xfs]
[15205901.402069] ? xfs_buf_delwri_submit_buffers+0x16d/0x2b0 [xfs]
[15205901.403060] xfs_inode_buf_write_verify+0x10/0x20 [xfs]
[15205901.404017] _xfs_buf_ioapply+0x88/0x410 [xfs]
[15205901.404990] ? xfs_buf_delwri_submit_buffers+0x16d/0x2b0 [xfs]
[15205901.405929] xfs_buf_submit+0x63/0x200 [xfs]
[15205901.406801] xfs_buf_delwri_submit_buffers+0x16d/0x2b0 [xfs]
[15205901.407675] ? xfs_buf_delwri_submit_nowait+0x10/0x20 [xfs]
[15205901.408540] ? xfs_inode_item_push+0xb7/0x190 [xfs]
[15205901.409395] xfs_buf_delwri_submit_nowait+0x10/0x20 [xfs]
[15205901.410249] xfsaild+0x29a/0x780 [xfs]
[15205901.411121] kthread+0x109/0x140
[15205901.411981] ? xfs_trans_ail_cursor_first+0x90/0x90 [xfs]
[15205901.412785] ? kthread_park+0x60/0x60
[15205901.413578] ret_from_fork+0x2a/0x40
The "obvious" cause is that the bp->b_pages was NULL in function
xfs_buf_offset. Analyzing vmcore, we found that b_pages=NULL but
b_page_count=16, so b_pages is set to NULL for some reason.
crash> struct xfs_buf 88627bebf000 | less
...
b_pages = 0x0,
b_page_array = {0x0, 0x0},
b_maps = 0x88627bebf118,
__b_map = {
bm_bn = 512,
bm_len = 128
},
b_map_count = 1,
b_io_length = 128,
b_pin_count = {
counter = 0
},
b_io_remaining = {
counter = 1
},
b_page_count = 16,
b_offset = 0,
b_error = 0,
...
To avoid system crash, we can add the check of 'bp->b_pages' to
xfs_inode_buf_verify(). If b_pages == NULL, we mark the buffer
as -EFSCORRUPTED and the IO will not dispatched.
Signed-off-by: Fengfei Xi
Reviewed-by: Xianting Tian
---
fs/xfs/libxfs/xfs_inode_buf.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/fs/xfs/libxfs/xfs_inode_buf.c b/fs/xfs/libxfs/xfs_inode_buf.c
index c667c63f2..5a485c51f 100644
--- a/fs/xfs/libxfs/xfs_inode_buf.c
+++ b/fs/xfs/libxfs/xfs_inode_buf.c
@@ -45,6 +45,17 @@ xfs_inode_buf_verify(
int i;
int ni;
+ /*
+* Don't crash and mark buffer EFSCORRUPTED when b_pages is NULL
+*/
+ if (!bp->b_pages) {
+ xfs_buf_ioerror(bp, -EFSCORRUPTED);
+ xfs_alert(mp,
+ "xfs_buf(%p) b_pages corruption detected at %pS\n",
+ bp, __return_address);
+ return;
+ }
+
/*
* Validate the magic number and version of every inode in the buffer
*/
--
2.17.1
Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski wrote: > > On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote: > > > > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski wrote: > > > > > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote: > > > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier > > > > board. > > > > > > > > Genaral features: > > > > - Ethernet 10/100 > > > > - Wifi/BT > > > > - USB Type A/OTG > > > > - Audio Out > > > > - CAN > > > > - LVDS panel connector > > > > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. > > > > > > > > i.Core MX8M Mini needs to mount on top of this Carrier board for > > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board. > > > > > > > > Add support for it. > > > > > > > > Signed-off-by: Matteo Lisi > > > > Signed-off-by: Jagan Teki > > > > --- > > > > Changes for v3: > > > > - don't maintain common nodes and include it, if no feature diff > > > > Changes for v2: > > > > - enabled fec1 node > > > > - updated commit message > > > > - dropped engicam from filename since it aligned with imx6 engicam > > > > dts files naming conventions. > > > > - add i2c nodes > > > > - fixed v1 comments > > > > > > > > arch/arm64/boot/dts/freescale/Makefile| 1 + > > > > .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 +++ > > > > .../freescale/imx8mm-icore-mx8mm-ctouch2.dts | 21 + > > > > 3 files changed, 104 insertions(+) > > > > create mode 100644 > > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi > > > > > > You split some common part to ctouch2.dtsi so it can be reused in > > > multiple places. I saw so far only one usage, where are the others? > > > > To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier > > board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display), > > since DSI is not yet mainlined, I didn't add this yet. > > If I understand correctly: it is a DTSI which is included only by one > DTS... and DTS does not have any other nodes. This as well is not the This is not mandatory as per my understanding, including exiting DTS topologies in Mainline. There are several places where more than one dtsi has been included, Simple example of imx8mm tree is arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts /dts-v1/; #include "imx8mm.dtsi" #include "imx8mm-beacon-som.dtsi" #include "imx8mm-beacon-baseboard.dtsi" (SoC dtsi, SoM dtsi, Carrier board dtsi) > design which makes any sense. We do not create empty DTS files which > only include one more DTSI. The contents of > imx8mm-engicam-ctouch2.dtsi should be directly in > imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 - > you overcomplicate simple stuff. It really looks like you ignored the > comments from v1 in multiple places. As explained above, the design is pretty much the same as the existing SoM's. imx8mm-engicam-ctouch2.dtsi is not just a dtsi file where nodes are enabled. It has nodes enabled for Carrier board, so keeping nodes separately will 1. More verbose for which IP's are available in the carrier board 2. Easy to extend if someone can create another SoM with a similar Carrier. Ie is the whole idea to keep carrier board dtsi and includes them in dts. As I suggest, if you can look into px30 you can understand more easily. Jagan.
Re: [PATCH 3/3] overlayfs: Report writeback errors on upper
On Thu, Dec 24, 2020 at 11:32:55AM +0200, Amir Goldstein wrote:
> On Wed, Dec 23, 2020 at 10:44 PM Matthew Wilcox wrote:
> >
> > On Wed, Dec 23, 2020 at 08:21:41PM +, Sargun Dhillon wrote:
> > > On Wed, Dec 23, 2020 at 08:07:46PM +, Matthew Wilcox wrote:
> > > > On Wed, Dec 23, 2020 at 07:29:41PM +, Sargun Dhillon wrote:
> > > > > On Wed, Dec 23, 2020 at 06:50:44PM +, Matthew Wilcox wrote:
> > > > > > On Wed, Dec 23, 2020 at 06:20:27PM +, Sargun Dhillon wrote:
> > > > > > > I fail to see why this is neccessary if you incorporate error
> > > > > > > reporting into the
> > > > > > > sync_fs callback. Why is this separate from that callback? If you
> > > > > > > pickup Jeff's
> > > > > > > patch that adds the 2nd flag to errseq for "observed", you should
> > > > > > > be able to
> > > > > > > stash the first errseq seen in the ovl_fs struct, and do the
> > > > > > > check-and-return
> > > > > > > in there instead instead of adding this new infrastructure.
> > > > > >
> > > > > > You still haven't explained why you want to add the "observed" flag.
> > > > >
> > > > >
> > > > > In the overlayfs model, many users may be using the same filesystem
> > > > > (super block)
> > > > > for their upperdir. Let's say you have something like this:
> > > > >
> > > > > /workdir [Mounted FS]
> > > > > /workdir/upperdir1 [overlayfs upperdir]
> > > > > /workdir/upperdir2 [overlayfs upperdir]
> > > > > /workdir/userscratchspace
> > > > >
> > > > > The user needs to be able to do something like:
> > > > > sync -f ${overlayfs1}/file
> > > > >
> > > > > which in turn will call sync on the the underlying filesystem (the
> > > > > one mounted
> > > > > on /workdir), and can check if the errseq has changed since the
> > > > > overlayfs was
> > > > > mounted, and use that to return an error to the user.
> > > >
> > > > OK, but I don't see why the current scheme doesn't work for this. If
> > > > (each instance of) overlayfs samples the errseq at mount time and then
> > > > check_and_advances it at sync time, it will see any error that has
> > > > occurred
> > > > since the mount happened (and possibly also an error which occurred
> > > > before
> > > > the mount happened, but hadn't been reported to anybody before).
> > > >
> > >
> > > If there is an outstanding error at mount time, and the SEEN flag is
> > > unset,
> > > subsequent errors will not increment the counter, until the user calls
> > > sync on
> > > the upperdir's filesystem. If overlayfs calls check_and_advance on the
> > > upperdir's
> > > super block at any point, it will then set the seen block, and if the
> > > user calls
> > > syncfs on the upperdir, it will not return that there is an outstanding
> > > error,
> > > since overlayfs just cleared it.
> >
> > Your concern is this case:
> >
> > fs is mounted on /workdir
> > /workdir/A is written to and then closed.
> > writeback happens and -EIO happens, but there's nobody around to care.
> > /workdir/upperdir1 becomes part of an overlayfs mount
> > overlayfs samples the error
> > a user writes to /workdir/B, another -EIO occurs, but nothing happens
> > someone calls syncfs on /workdir/upperdir/A, gets the EIO.
> > a user opens /workdir/B and calls syncfs, but sees no error
> >
> > do i have that right? or is it something else?
>
> IMO it is something else. Others may disagree.
> IMO the level of interference between users accessing overlay and users
> accessing upper fs directly is not well defined and it can stay this way.
>
> Concurrent access to /workdir/upperdir/A via overlay and underlying fs
> is explicitly warranted against in Documentation/filesystems/overlayfs.rst#
> Changes to underlying filesystems:
> "Changes to the underlying filesystems while part of a mounted overlay
> filesystem are not allowed. If the underlying filesystem is changed,
> the behavior of the overlay is undefined, though it will not result in
> a crash or deadlock."
>
> The question is whether syncfs(open(/workdir/B)) is considered
> "Changes to the underlying filesystems". Regardless of the answer,
> this is not an interesting case IMO.
>
> The real issue is with interference between overlays that share the
> same upper fs, because this is by far and large the common use case
> that is creating real problems for a lot of container users.
>
> Workloads running inside containers (with overlayfs storage driver)
> will never be as isolated as workloads running inside VMs, but it
> doesn't mean we cannot try to improve.
>
> In current master, syncfs() on any file by any container user will
> result in full syncfs() of the upperfs, which is very bad for container
> isolation. This has been partly fixed by Chengguang Xu [1] and I expect
> his work will be merged soon. Overlayfs still does not do the writeback
> and syncfs() in overlay still waits for all upper fs writeback to complete,
> but at least syncfs() in overlay only kicks writeback for upper fs files
> dirtied by this overlay.
>
> [1]
> http
Re: [PATCH 0/3] add support for metadata encryption to F2FS
On Tue, Dec 22, 2020 at 07:47:45PM +0800, Chao Yu wrote: > On 2020/12/18 19:53, Satya Tangirala wrote: > > On Fri, Dec 18, 2020 at 05:02:23PM +0800, Chao Yu wrote: > > > But, what's the plan about supporting software encryption for metadata? > > > Current > > > f2fs write flow will handle all operations which may encounter failure > > > before > > > allocating block address for node, if we do allocation first, and then > > > use pba > > > as IV to encrypt node block, it will be a little complicated to revert > > > allocation > > > if we fail to encrypt node block. > > > > > Software encryption for metadata is supported through the blk-crypto > > blk-crypto will encrypt all data in filesystem, if FBE is enabled, data may > be encrypted twice? blk-crypto will only encrypt bios as directed to do so by the encryption context set on the bio. That encryption context is constructed by the submitter of the bio - in our case, the submitter is the filesystem. So the filesystem decides which bio gets encrypted with which key/algorithm/etc (and in the current implementation, each bio only supports a single bi_crypt_context, so *only one* layer of encryption is possible with blk-crypto anyway). So no, data won't be encrypted twice, because F2FS/fscrypt ensure that it does not (and the filesystem knows exactly which blocks need metadata encryption, and which blocks need FBE). > > And why not supporting hardware encryption for metadata in blk-crypto? then > both f2fs and ext4 can use inline-encryption based blk-crypto? > I may be misunderstanding what you're asking, but I think you're asking why not make blk-crypto do metadata encryption (without explicit involvement from filesystems)? Or more generally, why not do metadata encryption below the filesystem layer? As mentioned above, the filesystem is what knows which blocks need to be metadata encrypted and which blocks need to be FBE encrypted (or even just read without any encryption at all) - the block layer doesn't have this information, and so can't effectively decide which blocks to use the metadata encryption key on. Fwiw, Android does take a somewhat similar approach to what you're suggesting here (I explain more in detail in the cover letter for v2 of this patch series at https://lore.kernel.org/linux-fscrypt/20201217150435.1505269-1-sat...@google.com/ ). In Android, we have a new DM target (called dm-default-key) that adds an encryption context to any bio that doesn't already have an encryption context - so the assumption in general is that if the filesystem wants to use an FBE key, it would have already set the encryption context on the bio, so if a bio reaches dm-default-key without an encryption context, it must mean that it needs metadata encryption. However, that assumption doesn't always hold because F2FS sometimes needs to read the ciphertext of FBE files without having the file's FBE key available - in those situations, F2FS will send a bio without any encryption context, but will also tell dm-default-key to *not* add the metadata encryption context. That's a layering violation, which is why I'm not using that approach here. Does that answer your question? Or am I misunderstanding what you're asking? > Thanks, > > > framework - so encryption will happen in the block layer, not the > > filesystem layer. So there's nothing extra/special we need to do if > > there's an encryption failure - an encryption failure is no different > > from a read/write failure in a lower layer from f2fs' perspective. > > . > >
Re: Re: [PATCH] enic: Remove redundant free in enic_set_ringparam
> On Wed, 23 Dec 2020 20:38:33 +0800 Dinghao Liu wrote: > > The error handling paths in enic_alloc_vnic_resources() > > have called enic_free_vnic_resources() before returning. > > So we may not need to call it again on failure at caller > > side. > > > > Signed-off-by: Dinghao Liu > > But it's harmless, right? So the patch is just a cleanup not a fix? > I think it's harmless. Since there is a check every time before freeing, calling enic_free_vnic_resources() twice has no security issue. > In that case, could you please repost in two weeks? We're currently > in the merge window period, we're only accepting fixes to the > networking trees. > > Thanks!
Re: PROBLEM: Recent raid10 block discard patchset causes filesystem corruption on fstrim
On 12/09/2020 12:17 PM, Song Liu wrote:
Hi Matthew,
On Dec 8, 2020, at 7:46 PM, Matthew Ruffell
wrote:
Hello,
I recently backported the following patches into the Ubuntu stable kernels:
md: add md_submit_discard_bio() for submitting discard bio
md/raid10: extend r10bio devs to raid disks
md/raid10: pull codes that wait for blocked dev into one function
md/raid10: improve raid10 discard request
md/raid10: improve discard request for far layout
dm raid: fix discard limits for raid1 and raid10
dm raid: remove unnecessary discard limits for raid10
Thanks for the report!
Hi Xiao,
Could you please take a look at this and let me know soon? We need to fix
this before 5.10 official release.
Thanks,
Song
Hi all
The root cause is found. Now we use a similar way with raid0 to handle
discard request
for raid10. Because the discard region is very big, we can calculate the
start/end address
for each disk. Then we can submit the discard request to each disk. But
for raid10, it has
copies. For near layout, if the discard request doesn't align with chunk
size, we calculate
a start_disk_offset. Now we only use start_disk_offset for the first
disk, but it should be
used for the near copies disks too.
[ 789.709501] discard bio start : 70968, size : 191176
[ 789.709507] first stripe index 69, start disk index 0, start disk
offset 70968
[ 789.709509] last stripe index 256, end disk index 0, end disk offset
262144
[ 789.709511] disk 0, dev start : 70968, dev end : 262144
[ 789.709515] disk 1, dev start : 70656, dev end : 262144
For example, in this test case, it has 2 near copies. The
start_disk_offset for the first disk is 70968.
It should use the same offset address for second disk. But it uses the
start address of this chunk.
It discard more region. The patch in the attachment can fix this
problem. It split the region that
doesn't align with chunk size.
There is another problem. The stripe size should be calculated
differently for near layout and far layout.
@Song, do you want me to use a separate patch for this fix, or fix this
in the original patch?
Merry Christmas
Xiao
commit 0d74ac66ed0ec5af70296545e26044723a14657c
Author: Xiao Ni
Date: Thu Dec 24 17:58:43 2020 +0800
fix
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 3153183b7772..92182cf40d22 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -1604,6 +1604,7 @@ static int raid10_handle_discard(struct mddev *mddev,
struct bio *bio)
sector_t chunk;
unsigned int stripe_size;
sector_t split_size;
+ sector_t chunk_size = 1 << geo->chunk_shift;
sector_t bio_start, bio_end;
sector_t first_stripe_index, last_stripe_index;
@@ -1624,7 +1625,8 @@ static int raid10_handle_discard(struct mddev *mddev,
struct bio *bio)
if (test_bit(MD_RECOVERY_RESHAPE, &mddev->recovery))
goto out;
- stripe_size = geo->raid_disks << geo->chunk_shift;
+ stripe_size = geo->near_copies ? geo->near_copies << geo->chunk_shift:
+ geo->raid_disks << geo->chunk_shift;
bio_start = bio->bi_iter.bi_sector;
bio_end = bio_end_sector(bio);
@@ -1637,6 +1639,18 @@ static int raid10_handle_discard(struct mddev *mddev,
struct bio *bio)
if (bio_sectors(bio) < stripe_size*2)
goto out;
+ /* Keep the discard start/end address aligned with chunk size */
+ if (bio_start & geo->chunk_mask) {
+ split_size = (chunk_size - (bio_start & geo->chunk_mask));
+ bio = raid10_split_bio(conf, bio, split_size, false);
+ }
+ if (bio_end & geo->chunk_mask) {
+ split_size = bio_end & geo->chunk_mask;
+ bio = raid10_split_bio(conf, bio, split_size, true);
+ }
+ bio_start = bio->bi_iter.bi_sector;
+ bio_end = bio_end_sector(bio);
+
/* For far and far offset layout, if bio is not aligned with stripe
size,
* it splits the part that is not aligned with strip size.
*/
@@ -1664,8 +1678,8 @@ static int raid10_handle_discard(struct mddev *mddev,
struct bio *bio)
start_disk_index = sector_div(first_stripe_index, geo->raid_disks);
if (geo->far_offset)
first_stripe_index *= geo->far_copies;
- start_disk_offset = (bio_start & geo->chunk_mask) +
- (first_stripe_index << geo->chunk_shift);
+ /* Now the bio is aligned with chunk size */
+ start_disk_offset = first_stripe_index << geo->chunk_shift;
chunk = bio_end >> geo->chunk_shift;
chunk *= geo->near_copies;
@@ -1673,8 +1687,7 @@ static int raid10_handle_discard(struct mddev *mddev,
struct bio *bio)
end_disk_index = sector_div(last_stripe_index, geo->raid_disks);
if (geo->far_offset)
last_stripe_index *= geo->far_copies;
- end_disk_offset = (bio_end & geo->chunk_mask) +
- (last_st
Re: [PATCH v3 4/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
On Thu, 24 Dec 2020 at 11:08, Jagan Teki wrote: > > On Thu, Dec 24, 2020 at 2:48 PM Krzysztof Kozlowski wrote: > > > > On Wed, 23 Dec 2020 at 13:07, Jagan Teki wrote: > > > > > > On Wed, Dec 23, 2020 at 5:29 PM Krzysztof Kozlowski > > > wrote: > > > > > > > > On Wed, Dec 23, 2020 at 04:33:41PM +0530, Jagan Teki wrote: > > > > > Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier > > > > > board. > > > > > > > > > > Genaral features: > > > > > - Ethernet 10/100 > > > > > - Wifi/BT > > > > > - USB Type A/OTG > > > > > - Audio Out > > > > > - CAN > > > > > - LVDS panel connector > > > > > > > > > > i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from > > > > > Engicam. > > > > > > > > > > i.Core MX8M Mini needs to mount on top of this Carrier board for > > > > > creating complete i.Core MX8M Mini C.TOUCH 2.0 board. > > > > > > > > > > Add support for it. > > > > > > > > > > Signed-off-by: Matteo Lisi > > > > > Signed-off-by: Jagan Teki > > > > > --- > > > > > Changes for v3: > > > > > - don't maintain common nodes and include it, if no feature diff > > > > > Changes for v2: > > > > > - enabled fec1 node > > > > > - updated commit message > > > > > - dropped engicam from filename since it aligned with imx6 engicam > > > > > dts files naming conventions. > > > > > - add i2c nodes > > > > > - fixed v1 comments > > > > > > > > > > arch/arm64/boot/dts/freescale/Makefile| 1 + > > > > > .../dts/freescale/imx8mm-engicam-ctouch2.dtsi | 82 > > > > > +++ > > > > > .../freescale/imx8mm-icore-mx8mm-ctouch2.dts | 21 + > > > > > 3 files changed, 104 insertions(+) > > > > > create mode 100644 > > > > > arch/arm64/boot/dts/freescale/imx8mm-engicam-ctouch2.dtsi > > > > > > > > You split some common part to ctouch2.dtsi so it can be reused in > > > > multiple places. I saw so far only one usage, where are the others? > > > > > > To be clear, ctouch2.dtsi not mean for common it is C.TOUCH2 carrier > > > board dtsi. The other carrier is C.TOUCH2 10.1" Open Frame(display), > > > since DSI is not yet mainlined, I didn't add this yet. > > > > If I understand correctly: it is a DTSI which is included only by one > > DTS... and DTS does not have any other nodes. This as well is not the > > This is not mandatory as per my understanding, including exiting DTS > topologies in Mainline. > > There are several places where more than one dtsi has been included, > Simple example of imx8mm tree is It's not the problem of including more than one DTSI. It's the problem of creating fake DTS or DTSI files whose purpose is only to include others. Keep it simple. Don't create unnecessary files. "Entities should not be multiplied without necessity." > > arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts Which was wrong as well. Don't create unnecessary files. > > /dts-v1/; > > #include "imx8mm.dtsi" > #include "imx8mm-beacon-som.dtsi" > #include "imx8mm-beacon-baseboard.dtsi" > > (SoC dtsi, SoM dtsi, Carrier board dtsi) > > > design which makes any sense. We do not create empty DTS files which > > only include one more DTSI. The contents of > > imx8mm-engicam-ctouch2.dtsi should be directly in > > imx8mm-icore-mx8mm-ctouch2.dts. That's the same problem as with v1 - > > you overcomplicate simple stuff. It really looks like you ignored the > > comments from v1 in multiple places. > > As explained above, the design is pretty much the same as the existing SoM's. > > imx8mm-engicam-ctouch2.dtsi is not just a dtsi file where nodes are > enabled. It has nodes enabled for Carrier board, so keeping nodes > separately will The files represent real devices or their components. So you have a SOM - a DTSI file. You have a carrier board - a DTS file. That's simple design which is mostly followed, unless something over complicated passes the review. > 1. More verbose for which IP's are available in the carrier board No difference when carrier DTSI is the DTS. Exactly the same. > 2. Easy to extend if someone can create another SoM with a similar Carrier. Not really, if they include carrier DTSI they need to override a lot. So usually (including practice - I did it) they *copy* the carrier to create their own design. > > Ie is the whole idea to keep carrier board dtsi and includes them in dts. > > As I suggest, if you can look into px30 you can understand more easily. NAK from my side. I explained my reasoning. You created a fake, empty DTSI which included only other DTSI. After review, you agreed to fix it. However you still create a fake DTS which includes only a DTSI. "Entities should not be multiplied without necessity." Best regards, Krzysztof
[PATCH] opp: fix memory leak in _allocate_opp_table
From: Quanyang Wang In function _allocate_opp_table, opp_dev is allocated and referenced by opp_table via _add_opp_dev. But in the case that the subsequent calls return -EPROBE_DEFER, it will jump to err label and opp_table will be freed. Then opp_dev becomes an unreferenced object to cause memory leak. So let's call _remove_opp_dev to do the cleanup. This fixes the following kmemleak report: unreferenced object 0x000801524a00 (size 128): comm "swapper/0", pid 1, jiffies 4294892465 (age 84.616s) hex dump (first 32 bytes): 40 00 56 01 08 00 ff ff 40 00 56 01 08 00 ff ff @.V.@.V. b8 52 77 7f 08 00 ff ff 00 3c 4c 00 08 00 ff ff .Rw..] kmemleak_alloc+0x30/0x40 [<56da48f0>] kmem_cache_alloc+0x3d4/0x588 [] _add_opp_dev+0x2c/0x88 [<62a380cd>] _add_opp_table_indexed+0x124/0x268 [<8b4c8f1f>] dev_pm_opp_of_add_table+0x20/0x1d8 [ ] dev_pm_opp_of_cpumask_add_table+0x48/0xf0 [ ] dt_cpufreq_probe+0x20c/0x448 [<30a3a26c>] platform_probe+0x68/0xd8 [ ] really_probe+0xd0/0x3a0 [<642e856f>] driver_probe_device+0x58/0xb8 [ ] device_driver_attach+0x74/0x80 [<04f254b8>] __driver_attach+0x58/0xe0 [<09d5d19e>] bus_for_each_dev+0x70/0xc8 [<00d22e1c>] driver_attach+0x24/0x30 [<01d4e952>] bus_add_driver+0x14c/0x1f0 [<89928aaa>] driver_register+0x64/0x120 Fixes: dd461cd9183f ("opp: Allow dev_pm_opp_get_opp_table() to return -EPROBE_DEFER") Signed-off-by: Quanyang Wang --- drivers/opp/core.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 4268eb359915..c9e50836b4c2 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -1092,7 +1092,7 @@ static struct opp_table *_allocate_opp_table(struct device *dev, int index) if (IS_ERR(opp_table->clk)) { ret = PTR_ERR(opp_table->clk); if (ret == -EPROBE_DEFER) - goto err; + goto remove_opp_dev; dev_dbg(dev, "%s: Couldn't find clock: %d\n", __func__, ret); } @@ -1101,7 +1101,7 @@ static struct opp_table *_allocate_opp_table(struct device *dev, int index) ret = dev_pm_opp_of_find_icc_paths(dev, opp_table); if (ret) { if (ret == -EPROBE_DEFER) - goto err; + goto remove_opp_dev; dev_warn(dev, "%s: Error finding interconnect paths: %d\n", __func__, ret); @@ -1113,6 +1113,8 @@ static struct opp_table *_allocate_opp_table(struct device *dev, int index) return opp_table; +remove_opp_dev: + _remove_opp_dev(opp_dev, opp_table); err: kfree(opp_table); return ERR_PTR(ret); -- 2.25.1
RE: [PATCH v1] scsi: ufs-mediatek: Enable UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL
Hi, Just to clarify things: > > Do you see any substantial benefit of having fWriteBoosterBufferFlushEn > > disabled? > > 1. The definition of fWriteBoosterBufferFlushEn is that host allows > device to do flush in anytime after fWriteBoosterBufferFlushEn is set as > on. This is not what we want. > > Just Like BKOP, We do not want flush happening beyond host's expected > timing that device performance may be "randomly" dropped. Explicit flush takes place only when the device is idle: if fWriteBoosterBufferFlushEn is set, the device is idle, and before h8 received. If a request arrives, the flush operation should be halted. So no performance degradation is expected. > > 2. Another related concern is that currently fWriteBoosterBufferFlushEn > may keep on while device is not in Active Power Mode during suspend > period. I am not sure if such configuration would confuse the device. The spec says: " While the flushing operation is in progress, the device is in Active power mode" > > Thanks, > Stanley Chu > > > > > Thanks, > > Can Guo. > > > > > > > > Thanks, > > > > > > Can Guo. > > > > > >> Thanks, > > >> Stanley Chu > > >>> > > >>> Change LGTM. > > >>> > > >>> Regards, > > >>> > > >>> Can Guo.
[PATCH] nvmet-fc: associations list replaced with hlist rcu,
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c b/drivers/nvme/target/fc.c
index cd4e73aa9807..3928a17d073c 100644
--- a/drivers/nvme/target/fc.c
+++ b/drivers/nvme/target/fc.c
@@ -105,7 +105,7 @@ struct nvmet_fc_tgtport {
struct list_headls_rcv_list;
struct list_headls_req_list;
struct list_headls_busylist;
- struct list_headassoc_list;
+ struct hlist_head assoc_list;
struct list_headhost_list;
struct ida assoc_cnt;
struct nvmet_fc_port_entry *pe;
@@ -163,10 +163,11 @@ struct nvmet_fc_tgt_assoc {
struct nvmet_fc_tgtport *tgtport;
struct nvmet_fc_hostport*hostport;
struct nvmet_fc_ls_iod *rcv_disconn;
- struct list_heada_list;
+ struct hlist_node a_list;
struct nvmet_fc_tgt_queue *queues[NVMET_NR_QUEUES + 1];
struct kref ref;
struct work_struct del_work;
+ struct rcu_head rcu_head;
};
@@ -965,24 +966,23 @@ nvmet_fc_find_target_queue(struct nvmet_fc_tgtport
*tgtport,
struct nvmet_fc_tgt_queue *queue;
u64 association_id = nvmet_fc_getassociationid(connection_id);
u16 qid = nvmet_fc_getqueueid(connection_id);
- unsigned long flags;
if (qid > NVMET_NR_QUEUES)
return NULL;
- spin_lock_irqsave(&tgtport->lock, flags);
- list_for_each_entry(assoc, &tgtport->assoc_list, a_list) {
+ rcu_read_lock();
+ hlist_for_each_entry_rcu(assoc, &tgtport->assoc_list, a_list) {
if (association_id == assoc->association_id) {
queue = assoc->queues[qid];
if (queue &&
(!atomic_read(&queue->connected) ||
!nvmet_fc_tgt_q_get(queue)))
queue = NULL;
- spin_unlock_irqrestore(&tgtport->lock, flags);
+ rcu_read_unlock();
return queue;
}
}
- spin_unlock_irqrestore(&tgtport->lock, flags);
+ rcu_read_unlock();
return NULL;
}
@@ -1118,7 +1118,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
assoc->tgtport = tgtport;
assoc->a_id = idx;
- INIT_LIST_HEAD(&assoc->a_list);
+ INIT_HLIST_NODE(&assoc->a_list);
kref_init(&assoc->ref);
INIT_WORK(&assoc->del_work, nvmet_fc_delete_assoc);
atomic_set(&assoc->terminating, 0);
@@ -1129,7 +1129,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
spin_lock_irqsave(&tgtport->lock, flags);
needrandom = false;
- list_for_each_entry(tmpassoc, &tgtport->assoc_list, a_list) {
+ hlist_for_each_entry(tmpassoc, &tgtport->assoc_list, a_list) {
if (ran == tmpassoc->association_id) {
needrandom = true;
break;
@@ -1137,7 +1137,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
}
if (!needrandom) {
assoc->association_id = ran;
- list_add_tail(&assoc->a_list, &tgtport->assoc_list);
+ hlist_add_tail_rcu(&assoc->a_list,
&tgtport->assoc_list);
}
spin_unlock_irqrestore(&tgtport->lock, flags);
}
@@ -1153,6 +1153,17 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
return NULL;
}
+void nvmet_assoc_free_queue_rcu(struct rcu_head *rcu_head) {
+ struct nvmet_fc_tgt_assoc *assoc =
+ container_of(rcu_head, struct nvmet_fc_tgt_assoc, rcu_head);
+ struct nvmet_fc_tgtport *tgtport = assoc->tgtport;
+
+ kfree(assoc);
+ dev_info(tgtport->dev,
+ "{%d:%d} Association freed\n",
+ tgtport->fc_target_port.port_num, assoc->a_id);
+}
+
static void
nvmet_fc_target_assoc_free(struct kref *ref)
{
@@ -1167,17 +1178,14 @@ nvmet_fc_target_assoc_free(struct kref *ref)
nvmet_fc_free_hostport(assoc->hostport);
spin_lock_irqsave(&tgtport->lock, flags);
- list_del(&assoc->a_list);
+ hlist_del_rcu(&assoc->a_list);
oldls = assoc->rcv_disconn;
spin_unlock_irqrestore(&tgtport->lock, flags);
/* if pending Rcv Disconnect Association LS, send rsp now */
if (oldls)
nvmet_fc_xmt_ls_rsp(tgtport, oldls);
[PATCH] nvmet-fc: associations list replaced with hlist rcu,
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c b/drivers/nvme/target/fc.c
index cd4e73aa9807..3928a17d073c 100644
--- a/drivers/nvme/target/fc.c
+++ b/drivers/nvme/target/fc.c
@@ -105,7 +105,7 @@ struct nvmet_fc_tgtport {
struct list_headls_rcv_list;
struct list_headls_req_list;
struct list_headls_busylist;
- struct list_headassoc_list;
+ struct hlist_head assoc_list;
struct list_headhost_list;
struct ida assoc_cnt;
struct nvmet_fc_port_entry *pe;
@@ -163,10 +163,11 @@ struct nvmet_fc_tgt_assoc {
struct nvmet_fc_tgtport *tgtport;
struct nvmet_fc_hostport*hostport;
struct nvmet_fc_ls_iod *rcv_disconn;
- struct list_heada_list;
+ struct hlist_node a_list;
struct nvmet_fc_tgt_queue *queues[NVMET_NR_QUEUES + 1];
struct kref ref;
struct work_struct del_work;
+ struct rcu_head rcu_head;
};
@@ -965,24 +966,23 @@ nvmet_fc_find_target_queue(struct nvmet_fc_tgtport
*tgtport,
struct nvmet_fc_tgt_queue *queue;
u64 association_id = nvmet_fc_getassociationid(connection_id);
u16 qid = nvmet_fc_getqueueid(connection_id);
- unsigned long flags;
if (qid > NVMET_NR_QUEUES)
return NULL;
- spin_lock_irqsave(&tgtport->lock, flags);
- list_for_each_entry(assoc, &tgtport->assoc_list, a_list) {
+ rcu_read_lock();
+ hlist_for_each_entry_rcu(assoc, &tgtport->assoc_list, a_list) {
if (association_id == assoc->association_id) {
queue = assoc->queues[qid];
if (queue &&
(!atomic_read(&queue->connected) ||
!nvmet_fc_tgt_q_get(queue)))
queue = NULL;
- spin_unlock_irqrestore(&tgtport->lock, flags);
+ rcu_read_unlock();
return queue;
}
}
- spin_unlock_irqrestore(&tgtport->lock, flags);
+ rcu_read_unlock();
return NULL;
}
@@ -1118,7 +1118,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
assoc->tgtport = tgtport;
assoc->a_id = idx;
- INIT_LIST_HEAD(&assoc->a_list);
+ INIT_HLIST_NODE(&assoc->a_list);
kref_init(&assoc->ref);
INIT_WORK(&assoc->del_work, nvmet_fc_delete_assoc);
atomic_set(&assoc->terminating, 0);
@@ -1129,7 +1129,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
spin_lock_irqsave(&tgtport->lock, flags);
needrandom = false;
- list_for_each_entry(tmpassoc, &tgtport->assoc_list, a_list) {
+ hlist_for_each_entry(tmpassoc, &tgtport->assoc_list, a_list) {
if (ran == tmpassoc->association_id) {
needrandom = true;
break;
@@ -1137,7 +1137,7 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
}
if (!needrandom) {
assoc->association_id = ran;
- list_add_tail(&assoc->a_list, &tgtport->assoc_list);
+ hlist_add_tail_rcu(&assoc->a_list,
&tgtport->assoc_list);
}
spin_unlock_irqrestore(&tgtport->lock, flags);
}
@@ -1153,6 +1153,17 @@ nvmet_fc_alloc_target_assoc(struct nvmet_fc_tgtport
*tgtport, void *hosthandle)
return NULL;
}
+void nvmet_assoc_free_queue_rcu(struct rcu_head *rcu_head) {
+ struct nvmet_fc_tgt_assoc *assoc =
+ container_of(rcu_head, struct nvmet_fc_tgt_assoc, rcu_head);
+ struct nvmet_fc_tgtport *tgtport = assoc->tgtport;
+
+ kfree(assoc);
+ dev_info(tgtport->dev,
+ "{%d:%d} Association freed\n",
+ tgtport->fc_target_port.port_num, assoc->a_id);
+}
+
static void
nvmet_fc_target_assoc_free(struct kref *ref)
{
@@ -1167,17 +1178,14 @@ nvmet_fc_target_assoc_free(struct kref *ref)
nvmet_fc_free_hostport(assoc->hostport);
spin_lock_irqsave(&tgtport->lock, flags);
- list_del(&assoc->a_list);
+ hlist_del_rcu(&assoc->a_list);
oldls = assoc->rcv_disconn;
spin_unlock_irqrestore(&tgtport->lock, flags);
/* if pending Rcv Disconnect Association LS, send rsp now */
if (oldls)
nvmet_fc_xmt_ls_rsp(tgtport, oldls);
[PATCH 0/3] Add support for assigned-performance-states for geni i2c driver
Roja Rani Yarubandi (3): dt-bindings: power: Introduce 'assigned-performance-states' property arm64: dts: sc7180: Add assigned-performance-states for i2c i2c: i2c-qcom-geni: Add support for 'assigned-performance-states' .../bindings/power/power-domain.yaml | 49 +++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 24 + drivers/i2c/busses/i2c-qcom-geni.c| 49 +++ 3 files changed, 122 insertions(+) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 3/3] i2c: i2c-qcom-geni: Add support for 'assigned-performance-states'
For devices which have 'assigned-performance-states' specified in DT,
set the specified performance state during probe and drop it on remove.
Also drop/set as part of runtime suspend/resume callbacks.
Signed-off-by: Roja Rani Yarubandi
---
drivers/i2c/busses/i2c-qcom-geni.c | 49 ++
1 file changed, 49 insertions(+)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
index 046d241183c5..250773784631 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -86,6 +87,7 @@ struct geni_i2c_dev {
u32 clk_freq_out;
const struct geni_i2c_clk_fld *clk_fld;
int suspended;
+ unsigned int assigned_pstate;
};
struct geni_i2c_err_log {
@@ -497,6 +499,7 @@ static int geni_i2c_probe(struct platform_device *pdev)
u32 proto, tx_depth;
int ret;
struct device *dev = &pdev->dev;
+ unsigned int assigned_pstate;
gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
if (!gi2c)
@@ -520,6 +523,20 @@ static int geni_i2c_probe(struct platform_device *pdev)
gi2c->clk_freq_out = KHZ(100);
}
+ /* Set the assigned performance state */
+ if (!of_property_read_u32(pdev->dev.of_node,
"assigned-performance-states",
+ &assigned_pstate)) {
+ if (assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev,
+
assigned_pstate);
+ if (ret) {
+ dev_err(dev, "Failed to set performance
state\n");
+ return ret;
+ }
+ gi2c->assigned_pstate = assigned_pstate;
+ }
+ }
+
if (has_acpi_companion(dev))
ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
@@ -616,10 +633,22 @@ static int geni_i2c_probe(struct platform_device *pdev)
static int geni_i2c_remove(struct platform_device *pdev)
{
+ int ret;
+ struct device *dev = &pdev->dev;
struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
i2c_del_adapter(&gi2c->adap);
pm_runtime_disable(gi2c->se.dev);
+
+ /* Drop the assigned performance state */
+ if (gi2c->assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev, 0);
+ if (ret) {
+ dev_err(dev, "Failed to set performance state\n");
+ return ret;
+ }
+ }
+
return 0;
}
@@ -629,6 +658,16 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct
device *dev)
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
+
+ /* Drop the assigned performance state */
+ if (gi2c->assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev, 0);
+ if (ret) {
+ dev_err(dev, "Failed to set performance state\n");
+ return ret;
+ }
+ }
+
ret = geni_se_resources_off(&gi2c->se);
if (ret) {
enable_irq(gi2c->irq);
@@ -654,6 +693,16 @@ static int __maybe_unused geni_i2c_runtime_resume(struct
device *dev)
if (ret)
return ret;
+ /* Set the assigned performance state */
+ if (gi2c->assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev,
+gi2c->assigned_pstate);
+ if (ret) {
+ dev_err(dev, "Failed to set performance state\n");
+ return ret;
+ }
+ }
+
enable_irq(gi2c->irq);
gi2c->suspended = 0;
return 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/3] dt-bindings: power: Introduce 'assigned-performance-states' property
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the device is active.
These devices typically would also run off a fixed clock and not support
dynamically scaling the device's performance, also known as DVFS
techniques.
Add a property 'assigned-performance-states' which client devices can
use to set this default performance state on their power-domains.
Signed-off-by: Roja Rani Yarubandi
---
.../bindings/power/power-domain.yaml | 49 +++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml
b/Documentation/devicetree/bindings/power/power-domain.yaml
index aed51e9dcb11..a42977a82d06 100644
--- a/Documentation/devicetree/bindings/power/power-domain.yaml
+++ b/Documentation/devicetree/bindings/power/power-domain.yaml
@@ -66,6 +66,18 @@ properties:
by the given provider should be subdomains of the domain specified
by this binding.
+ assigned-performance-states:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description:
+ Some devices might need to configure their power domains in a default
+ performance state while the device is active. These devices typcially
+ would also run off a fixed clock and not support dynamically scaling
+ the device's performance, also known as DVFS techniques. Each cell in
+ performance state value corresponds to one power domain specified as
+ part of the power-domains property. Performance state value can be an
+ opp-level inside an OPP table of the power-domain and need not match
+ with any OPP table performance state.
+
required:
- "#power-domain-cells"
@@ -131,3 +143,40 @@ examples:
min-residency-us = <7000>;
};
};
+
+ - |
+parent4: power-controller@1234 {
+compatible = "foo,power-controller";
+reg = <0x1234 0x1000>;
+#power-domain-cells = <0>;
+};
+
+parent5: power-controller@4321 {
+compatible = "foo,power-controller";
+reg = <0x4321 0x1000>;
+#power-domain-cells = <0>;
+operating-points-v2 = <&power_opp_table>;
+
+power_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+power_opp_low: opp1 {
+opp-level = <16>;
+};
+
+rpmpd_opp_ret: opp2 {
+opp-level = <64>;
+};
+
+rpmpd_opp_svs: opp3 {
+opp-level = <256>;
+};
+};
+};
+
+child4: consumer@12341000 {
+compatible = "foo,consumer";
+reg = <0x12341000 0x1000>;
+power-domains = <&parent4>, <&parent5>;
+assigned-performance-states = <0>, <256>;
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
min_filelist_kbytes vs file_is_tiny
Hello, Mandeep, Guenter et al. I came across the out-of-tree patch [1] that apparently is still alive after 10 years of residing in the Chromium OS tree, and I have a couple of questions if you don't mind spending your time answering them. 1. is this knob really necessary given there's an explicit bailout mechanism relying on `file_is_tiny` which depends on the sum of high watermarks across the zones? Wouldn't increasing `vm.min_free_kbytes` achieve basically the same? 2. if `vm.min_free_kbytes` is not an option, would setting `file_is_tiny` based on your `min_filelist_kbytes` knob achieve the same? 3. if not, is `memory.min` cgroup2 knob supposed to work in a similar manner? it looks to be unavailable for the root cgroup, though. What I'm looking for, basically, is to achieve the effect of the mentioned patch using mechanisms that are already available in the upstream kernel. Thank you. [1] https://chromium.googlesource.com/chromiumos/third_party/kernel-next/+/545e2917dbd863760a51379de8c26631e667c563^!/ -- Oleksandr Natalenko (post-factum)
[PATCH 2/3] arm64: dts: sc7180: Add assigned-performance-states for i2c
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz).
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'CX' to satisfy the 19.2 MHz clock frequency
requirement.
Use 'assigned-performance-states' to pass this information from
device tree, and also add the power-domains property to specify
the CX power-domain.
Signed-off-by: Roja Rani Yarubandi
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 22b832fc62e3..70d74215ba8b 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -782,6 +782,8 @@ i2c0: i2c@88 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -834,6 +836,8 @@ i2c1: i2c@884000 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -886,6 +890,8 @@ i2c2: i2c@888000 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -920,6 +926,8 @@ i2c3: i2c@88c000 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -972,6 +980,8 @@ i2c4: i2c@89 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -1006,6 +1016,8 @@ i2c5: i2c@894000 {
<&aggre1_noc MASTER_QUP_0 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -1073,6 +1085,8 @@ i2c6: i2c@a8 {
<&aggre2_noc MASTER_QUP_1 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -1125,6 +1139,8 @@ i2c7: i2c@a84000 {
<&aggre2_noc MASTER_QUP_1 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
+ power-domains = <&rpmhpd SC7180_CX>;
+ assigned-performance-states =
;
status = "disabled";
};
@@ -1159,6 +1175,8 @@ i2c8: i2c@a88000 {
<&aggre2_noc MASTER_QUP_1 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
[PATCH] binfmt_misc: Fix possible deadlock in bm_register_write
There is a deadlock in bm_register_write:
First, in the beggining of the function, a lock is taken on the
binfmt_misc root inode with inode_lock(d_inode(root))
Then, if the user used the MISC_FMT_OPEN_FILE flag, the function will
call open_exec on the user-provided interpreter.
open_exec will call a path lookup, and if the path lookup process
includes the root of binfmt_misc, it will try to take a shared lock
on its inode again, but it is already locked, and the code will
get stuck in a deadlock
To reproduce the bug:
$ echo ":i:E::ii::/proc/sys/fs/binfmt_misc/bla:F" >
/proc/sys/fs/binfmt_misc/register
backtrace of where the lock occurs (#5):
0 schedule () at ./arch/x86/include/asm/current.h:15
1 0x81b51237 in rwsem_down_read_slowpath (sem=0x888003b202e0,
count=, state=state@entry=2) at kernel/locking/rwsem.c:992
2 0x81b5150a in __down_read_common (state=2, sem=) at
kernel/locking/rwsem.c:1213
3 __down_read (sem=) at kernel/locking/rwsem.c:1222
4 down_read (sem=) at kernel/locking/rwsem.c:1355
5 0x811ee22a in inode_lock_shared (inode=) at
./include/linux/fs.h:783
6 open_last_lookups (op=0xc922fe34, file=0x888004098600,
nd=0xc922fd10) at fs/namei.c:3177
7 path_openat (nd=nd@entry=0xc922fd10, op=op@entry=0xc922fe34,
flags=flags@entry=65) at fs/namei.c:3366
8 0x811efe1c in do_filp_open (dfd=,
pathname=pathname@entry=0x8880031b9000, op=op@entry=0xc922fe34) at
fs/namei.c:3396
9 0x811e493f in do_open_execat (fd=fd@entry=-100,
name=name@entry=0x8880031b9000, flags=, flags@entry=0) at
fs/exec.c:913
10 0x811e4a92 in open_exec (name=) at fs/exec.c:948
11 0x8124aa84 in bm_register_write (file=,
buffer=, count=19, ppos=) at fs/binfmt_misc.c:682
12 0x811decd2 in vfs_write (file=file@entry=0x888004098500,
buf=buf@entry=0xa758d0 ":i:E::ii::i:CF\n", count=count@entry=19,
pos=pos@entry=0xc922ff10) at fs/read_write.c:603
13 0x811defda in ksys_write (fd=, buf=0xa758d0
":i:E::ii::i:CF\n", count=19) at fs/read_write.c:658
14 0x81b49813 in do_syscall_64 (nr=,
regs=0xc922ff58) at arch/x86/entry/common.c:46
15 0x81c0007c in entry_SYSCALL_64 () at arch/x86/entry/entry_64.S:120
To solve the issue, the open_exec call is moved to before the write
lock is taken by bm_register_write
Signed-off-by: Lior Ribak
---
fs/binfmt_misc.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/fs/binfmt_misc.c b/fs/binfmt_misc.c
index 3880a82da1dc..5f8f34c8a053 100644
--- a/fs/binfmt_misc.c
+++ b/fs/binfmt_misc.c
@@ -647,12 +647,23 @@ static ssize_t bm_register_write(struct file *file, const
char __user *buffer,
struct super_block *sb = file_inode(file)->i_sb;
struct dentry *root = sb->s_root, *dentry;
int err = 0;
+ struct file *f = NULL;
e = create_entry(buffer, count);
if (IS_ERR(e))
return PTR_ERR(e);
+ if (e->flags & MISC_FMT_OPEN_FILE) {
+ f = open_exec(e->interpreter);
+ if (IS_ERR(f)) {
+ pr_notice("register: failed to install interpreter file
%s\n",
+e->interpreter);
+ return PTR_ERR(f);
+ }
+ e->interp_file = f;
+ }
+
inode_lock(d_inode(root));
dentry = lookup_one_len(e->name, root, strlen(e->name));
err = PTR_ERR(dentry);
@@ -676,21 +687,6 @@ static ssize_t bm_register_write(struct file *file, const
char __user *buffer,
goto out2;
}
- if (e->flags & MISC_FMT_OPEN_FILE) {
- struct file *f;
-
- f = open_exec(e->interpreter);
- if (IS_ERR(f)) {
- err = PTR_ERR(f);
- pr_notice("register: failed to install interpreter file
%s\n", e->interpreter);
- simple_release_fs(&bm_mnt, &entry_count);
- iput(inode);
- inode = NULL;
- goto out2;
- }
- e->interp_file = f;
- }
-
e->dentry = dget(dentry);
inode->i_private = e;
inode->i_fop = &bm_entry_operations;
@@ -707,6 +703,8 @@ static ssize_t bm_register_write(struct file *file, const
char __user *buffer,
inode_unlock(d_inode(root));
if (err) {
+ if (f)
+ filp_close(f, NULL);
kfree(e);
return err;
}
--
2.17.1
[PATCH v3 02/15] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()
Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index c9cfafe89cbf..a75433b459dd 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -947,27 +947,24 @@ static int wiz_probe(struct platform_device *pdev)
goto err_get_sync;
}
+ ret = wiz_init(wiz);
+ if (ret) {
+ dev_err(dev, "WIZ initialization failed\n");
+ goto err_wiz_init;
+ }
+
serdes_pdev = of_platform_device_create(child_node, NULL, dev);
if (!serdes_pdev) {
dev_WARN(dev, "Unable to create SERDES platform device\n");
ret = -ENOMEM;
- goto err_pdev_create;
- }
- wiz->serdes_pdev = serdes_pdev;
-
- ret = wiz_init(wiz);
- if (ret) {
- dev_err(dev, "WIZ initialization failed\n");
goto err_wiz_init;
}
+ wiz->serdes_pdev = serdes_pdev;
of_node_put(child_node);
return 0;
err_wiz_init:
- of_platform_device_destroy(&serdes_pdev->dev, NULL);
-
-err_pdev_create:
wiz_clock_cleanup(wiz, node);
err_get_sync:
--
2.17.1
[PATCH v3 03/15] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index d210843863df..f574b8ed358c 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -49,12 +49,14 @@ properties:
const: serdes
clocks:
-maxItems: 2
+maxItems: 4
clock-names:
items:
- const: cmn_refclk_dig_div
- const: cmn_refclk1_dig_div
+ - const: pll_cmnlc
+ - const: pll_cmnlc1
cdns,autoconf:
type: boolean
@@ -107,6 +109,58 @@ patternProperties:
additionalProperties: false
+ "^refrcv1?$":
+type: object
+description: |
+ Reference receivers that enables routing external clocks to the alternate
+ PLLCMNLC.
+properties:
+ clocks:
+maxItems: 1
+description: Phandle to clock nodes representing the input to the
+ reference receiver.
+
+ clock-names:
+items:
+ - const: pll_refclk
+
+ "#clock-cells":
+const: 0
+
+required:
+ - clocks
+ - "#clock-cells"
+
+ "^pll_cmnlc1?$":
+type: object
+description: |
+ SERDES node should have subnodes for each of the PLLs present in
+ the SERDES.
+properties:
+ clocks:
+maxItems: 2
+description: Phandle to clock nodes representing the two inputs to PLL.
+
+ clock-names:
+items:
+ - const: pll_refclk
+ - const: refrcv
+
+ "#clock-cells":
+const: 0
+
+ assigned-clocks:
+maxItems: 1
+
+ assigned-clock-parents:
+maxItems: 1
+
+required:
+ - clocks
+ - "#clock-cells"
+ - assigned-clocks
+ - assigned-clock-parents
+
required:
- compatible
- "#address-cells"
@@ -130,10 +184,39 @@ examples:
reg = <0x0 0xfd24 0x0 0x4>;
resets = <&phyrst 0>, <&phyrst 1>;
reset-names = "sierra_reset", "sierra_apb";
-clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
-clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>,
<&serdes_pll_cmnlc>, <&serdes_pll_cmnlc1>;
+clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
"pll_cmnlc", "pll_cmnlc1";
#address-cells = <1>;
#size-cells = <0>;
+
+serdes_refrcv: refrcv {
+clocks = <&pll0_refclk>;
+clock-names = "pll_refclk";
+#clock-cells = <0>;
+};
+
+serdes_refrcv1: refrcv1 {
+clocks = <&pll1_refclk>;
+clock-names = "pll_refclk";
+#clock-cells = <0>;
+};
+
+serdes_pll_cmnlc: pll_cmnlc {
+clocks = <&pll0_refclk>, <&serdes_refrcv1>;
+clock-names = "pll_refclk", "refrcv";
+#clock-cells = <0>;
+assigned-clocks = <&serdes_pll_cmnlc>;
+assigned-clock-parents = <&pll0_refclk>;
+};
+
+serdes_pll_cmnlc1: pll_cmnlc1 {
+clocks = <&pll1_refclk>, <&serdes_refrcv>;
+clock-names = "pll_refclk", "refrcv";
+#clock-cells = <0>;
+assigned-clocks = <&serdes_pll_cmnlc1>;
+assigned-clock-parents = <&pll1_refclk>;
+};
+
pcie0_phy0: phy@0 {
reg = <0>;
resets = <&phyrst 2>;
--
2.17.1
[PATCH v3 05/15] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9..f7ba0ed416bc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -577,6 +577,10 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
for_each_available_child_of_node(dn, child) {
struct phy *gphy;
+ if (!(of_node_name_eq(child, "phy") ||
+ of_node_name_eq(child, "link")))
+ continue;
+
sp->phys[node].lnk_rst =
of_reset_control_array_get_exclusive(child);
--
2.17.1
[PATCH v3 04/15] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode
"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnode.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index a75433b459dd..2a03191eac64 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -787,6 +787,10 @@ static int wiz_get_lane_phy_types(struct device *dev,
struct wiz *wiz)
u32 reg, num_lanes = 1, phy_type = PHY_NONE;
int ret, i;
+ if (!(of_node_name_eq(subnode, "phy") ||
+ of_node_name_eq(subnode, "link")))
+ continue;
+
ret = of_property_read_u32(subnode, "reg", ®);
if (ret) {
dev_err(dev,
--
2.17.1
[PATCH v3 07/15] phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 7bf1b4c7774a..935f165404e4 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -509,6 +509,28 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
+ struct device *dev)
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get(dev, "sierra_reset");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->phy_rst = rst;
+
+ rst = devm_reset_control_get_optional(dev, "sierra_apb");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get apb reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->apb_rst = rst;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct platform_device *pdev)
{
struct cdns_sierra_phy *sp;
@@ -559,17 +581,9 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
if (ret)
return ret;
- sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
- if (IS_ERR(sp->phy_rst)) {
- dev_err(dev, "failed to get reset\n");
- return PTR_ERR(sp->phy_rst);
- }
-
- sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb");
- if (IS_ERR(sp->apb_rst)) {
- dev_err(dev, "failed to get apb reset\n");
- return PTR_ERR(sp->apb_rst);
- }
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
ret = clk_prepare_enable(sp->clk);
if (ret)
--
2.17.1
[PATCH v3 12/15] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 --
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 2d526ea44a85..9d1edce31829 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -400,8 +400,36 @@
#size-cells = <0>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>,
<&wiz0_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div",
"cmn_refclk1_dig_div";
+ clocks = <&wiz0_cmn_refclk_dig_div>,
<&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div",
"cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes0_refrcv: refrcv {
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes0_refrcv1: refrcv1 {
+ clocks = <&wiz0_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes0_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz0_pll0_refclk>,
<&serdes0_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes0_pll_cmnlc>;
+ assigned-clock-parents = <&wiz0_pll0_refclk>;
+ };
+
+ serdes0_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes0_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+ };
};
};
@@ -457,8 +485,36 @@
#size-cells = <0>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>,
<&wiz1_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div",
"cmn_refclk1_dig_div";
+ clocks = <&wiz1_cmn_refclk_dig_div>,
<&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div",
"cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes1_refrcv: refrcv {
+ clocks = <&wiz1_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes1_refrcv1: refrcv1 {
+ clocks = <&wiz1_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes1_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz1_pll0_refclk>,
<&serdes1_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes1_pll_cmnlc>;
+ assigned-clock-parents = <&wiz1_pll0_refclk>;
+ };
+
+ serdes1_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes1_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+ };
};
};
@@ -514,8 +570,36 @@
#size-cells = <0>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>,
<&wiz2_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div",
"cmn_refclk1_dig_div";
+ clocks = <&wiz2_cmn_refclk_dig_div>,
<&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig
[PATCH v3 10/15] phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as
clocks so that it's possible to select one of these two inputs from
device tree.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 188 ++-
1 file changed, 185 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 8b7b2a838f5f..2a509be80c80 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -25,6 +25,7 @@
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG0x0
+#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
@@ -34,6 +35,7 @@
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
#define SIERRA_CMN_REFRCV_PREG 0x98
#define SIERRA_CMN_REFRCV1_PREG0xB8
+#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
((0x4000 << (block_offset)) + \
@@ -183,6 +185,36 @@ struct cdns_sierra_refrcv {
#define to_cdns_sierra_refrcv(_hw) \
container_of(_hw, struct cdns_sierra_refrcv, hw)
+enum cdns_sierra_cmn_plllc {
+ CMN_PLLLC,
+ CMN_PLLLC1,
+};
+
+#define SIERRA_NUM_CMN_PLLC0x2
+
+static const struct reg_field cmn_plllc_pfdclk1_sel_preg[] = {
+ [CMN_PLLLC] = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
+ [CMN_PLLLC1]= REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
+};
+
+static char *cmn_plllc_node_name[] = { "pll_cmnlc", "pll_cmnlc1" };
+
+struct cdns_sierra_pll_mux {
+ struct clk_hw hw;
+ struct regmap_field *pfdclk_sel_preg;
+ u32 *table;
+ struct clk_init_dataclk_data;
+};
+
+#define to_cdns_sierra_pll_mux(_hw)\
+ container_of(_hw, struct cdns_sierra_pll_mux, hw)
+
+/*
+ * Mux value to be configured for each of the input clocks
+ * in the order populated in device tree
+ */
+static u32 cdns_sierra_pll_mux_table[] = { 0, 1 };
+
struct cdns_sierra_inst {
struct phy *phy;
u32 phy_type;
@@ -231,6 +263,7 @@ struct cdns_sierra_phy {
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV];
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV];
+ struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
@@ -398,6 +431,138 @@ static const struct phy_ops ops = {
.owner = THIS_MODULE,
};
+static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
+{
+ struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
+ struct regmap_field *field = mux->pfdclk_sel_preg;
+ unsigned int val;
+
+ regmap_field_read(field, &val);
+ return clk_mux_val_to_index(hw, mux->table, 0, val);
+}
+
+static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
+ struct regmap_field *field = mux->pfdclk_sel_preg;
+ int val;
+
+ val = mux->table[index];
+ return regmap_field_write(field, val);
+}
+
+static const struct clk_ops cdns_sierra_pll_mux_ops = {
+ .set_parent = cdns_sierra_pll_mux_set_parent,
+ .get_parent = cdns_sierra_pll_mux_get_parent,
+};
+
+static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,
+ struct device_node *node,
+ struct regmap_field *field)
+{
+ struct cdns_sierra_pll_mux *mux;
+ struct device *dev = sp->dev;
+ struct clk_init_data *init;
+ const char **parent_names;
+ unsigned int num_parents;
+ char clk_name[100];
+ struct clk *clk;
+ int ret;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 2) {
+ dev_err(dev, "SERDES clock must have parents\n");
+ return -EINVAL;
+ }
+
+ parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
+ GFP_KERNEL);
+ if (!parent_names)
+ return -ENOMEM;
+
+ of_clk_parent_fill(node, parent_names, num_parents);
+
+ snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
[PATCH v3 00/15] PHY: Add support in Sierra to use external clock
Patch series adds support in Sierra driver to use external clock. v1 of the patch series can be found @ [1] v2 of the patch series can be found @ [2] Changes from v2: 1) Add depends on COMMON_CLK in Sierra 2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate patch 3) Disable clocks in Sierra driver remove Changes from v1: 1) Remove the part that prevents configuration if the SERDES is already configured and focus only on using external clock and the associated cleanups 2) Change patch ordering 3) Use exclusive reset control APIs 4) Fix error handling code 5) Include DT patches in this series (I can send this separately to DT MAINTAINER once the driver patches are merged) [1] -> http://lore.kernel.org/r/20201103035556.21260-1-kis...@ti.com [2] -> http://lore.kernel.org/r/20201222070520.28132-1-kis...@ti.com Kishon Vijay Abraham I (15): phy: cadence: Sierra: Fix PHY power_on sequence phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function phy: cadence: cadence-sierra: Move all reset_control_get*() to a separate function phy: cadence: cadence-sierra: Explicitly request exclusive reset control phy: cadence: sierra: Model reference receiver as clocks (gate clocks) phy: cadence: sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" .../bindings/phy/phy-cadence-sierra.yaml | 89 ++- .../dts/ti/k3-j721e-common-proc-board.dts | 57 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 186 -- drivers/phy/cadence/Kconfig | 1 + drivers/phy/cadence/phy-cadence-sierra.c | 544 -- drivers/phy/ti/phy-j721e-wiz.c| 21 +- 6 files changed, 810 insertions(+), 88 deletions(-) -- 2.17.1
[PATCH v3 01/15] phy: cadence: Sierra: Fix PHY power_on sequence
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 26a0badabe38..19f32ae877b9 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -319,6 +319,12 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
+
/* Take the PHY lane group out of reset */
ret = reset_control_deassert(ins->lnk_rst);
if (ret) {
@@ -616,7 +622,6 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
pm_runtime_enable(dev);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
- reset_control_deassert(sp->phy_rst);
return PTR_ERR_OR_ZERO(phy_provider);
put_child:
--
2.17.1
[PATCH v3 09/15] phy: cadence: sierra: Model reference receiver as clocks (gate clocks)
Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to
drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to
drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these
reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to
be able to seamlessly use any of the external reference clocks.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 209 ++-
2 files changed, 207 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 432832bdbd16..23d5382c34ed 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -24,6 +24,7 @@ config PHY_CADENCE_DPHY
config PHY_CADENCE_SIERRA
tristate "Cadence Sierra PHY Driver"
depends on OF && HAS_IOMEM && RESET_CONTROLLER
+ depends on COMMON_CLK
select GENERIC_PHY
help
Enable this to support the Cadence Sierra PHY driver
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 44c52a0842dc..8b7b2a838f5f 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -7,6 +7,7 @@
*
*/
#include
+#include
#include
#include
#include
@@ -31,6 +32,8 @@
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
+#define SIERRA_CMN_REFRCV_PREG 0x98
+#define SIERRA_CMN_REFRCV1_PREG0xB8
#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
((0x4000 << (block_offset)) + \
@@ -151,6 +154,35 @@ static const struct reg_field phy_pll_cfg_1 =
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+enum cdns_sierra_cmn_refrcv {
+ CMN_REFRCV,
+ CMN_REFRCV1,
+};
+
+#define SIERRA_NUM_REFRCV 0x2
+
+static const struct reg_field cmn_refrcv_refclk_plllc1en_preg[] = {
+ [CMN_REFRCV]= REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
+ [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
+};
+
+static const struct reg_field cmn_refrcv_refclk_termen_preg[] = {
+ [CMN_REFRCV]= REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
+ [CMN_REFRCV1] = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
+};
+
+static char *refrcv_node_name[] = { "refrcv", "refrcv1" };
+
+struct cdns_sierra_refrcv {
+ struct clk_hw hw;
+ struct regmap_field *plllc1en_field;
+ struct regmap_field *termen_field;
+ struct clk_init_dataclk_data;
+};
+
+#define to_cdns_sierra_refrcv(_hw) \
+ container_of(_hw, struct cdns_sierra_refrcv, hw)
+
struct cdns_sierra_inst {
struct phy *phy;
u32 phy_type;
@@ -197,6 +229,8 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
+ struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_REFRCV];
+ struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_REFRCV];
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
@@ -364,6 +398,146 @@ static const struct phy_ops ops = {
.owner = THIS_MODULE,
};
+static int cdns_sierra_refrcv_enable(struct clk_hw *hw)
+{
+ struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw);
+ struct regmap_field *plllc1en_field = refrcv->plllc1en_field;
+ struct regmap_field *termen_field = refrcv->termen_field;
+
+ regmap_field_write(plllc1en_field, 1);
+ regmap_field_write(termen_field, 1);
+
+ return 0;
+}
+
+static void cdns_sierra_refrcv_disable(struct clk_hw *hw)
+{
+ struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw);
+ struct regmap_field *plllc1en_field = refrcv->plllc1en_field;
+ struct regmap_field *termen_field = refrcv->termen_field;
+
+ regmap_field_write(plllc1en_field, 0);
+ regmap_field_write(termen_field, 0);
+}
+
+static int cdns_sierra_refrcv_is_enabled(struct clk_hw *hw)
+{
+ struct cdns_sierra_refrcv *refrcv = to_cdns_sierra_refrcv(hw);
+ struct regmap_field *plllc1en_field = refrcv->plllc1en_field;
+ int val;
+
+ regmap_field_read(plllc1en_field, &val);
+
+ return !!val;
+}
+
+static const struct clk_ops cdns_sierra_refrcv_ops = {
+ .enable = cdns_sierra_refrcv_enable,
+ .disable = cdns_sierra_refrcv_disable,
+ .is_enabled = cdns_sierra_refrcv_is_enabled,
+};
+
+static int cdns_sierra_refrcv_register(struct cdns_sierra_phy *sp,
+ struct device_node *node,
+
[PATCH v3 11/15] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 2a509be80c80..ad0ea74515d6 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -267,6 +267,8 @@ struct cdns_sierra_phy {
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
+ struct clk *pll_cmnlc;
+ struct clk *pll_cmnlc1;
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
}
sp->cmn_refclk1_dig_div = clk;
+ clk = devm_clk_get_optional(dev, "pll_cmnlc");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc = clk;
+
+ clk = devm_clk_get_optional(dev, "pll_cmnlc1");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc1 clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc1 = clk;
+
return 0;
}
+static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(sp->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc);
+ if (ret)
+ goto err_pll_cmnlc;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc1);
+ if (ret)
+ goto err_pll_cmnlc1;
+
+ return 0;
+
+err_pll_cmnlc:
+ clk_disable_unprepare(sp->clk);
+
+err_pll_cmnlc1:
+ clk_disable_unprepare(sp->pll_cmnlc);
+
+ return 0;
+}
+
+static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
+{
+ clk_disable_unprepare(sp->pll_cmnlc1);
+ clk_disable_unprepare(sp->pll_cmnlc);
+ clk_disable_unprepare(sp->clk);
+}
+
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct device *dev)
{
@@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
if (ret)
goto unregister_pll_mux;
- ret = clk_prepare_enable(sp->clk);
+ ret = cdns_sierra_phy_enable_clocks(sp);
if (ret)
goto unregister_pll_mux;
@@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
reset_control_put(sp->phys[i].lnk_rst);
of_node_put(child);
clk_disable:
- clk_disable_unprepare(sp->clk);
+ cdns_sierra_phy_disable_clocks(sp);
reset_control_assert(sp->apb_rst);
unregister_pll_mux:
cdns_sierra_pll_mux_unregister(sp, dn);
@@ -1059,6 +,7 @@ static int cdns_sierra_phy_remove(struct platform_device
*pdev)
reset_control_assert(phy->apb_rst);
pm_runtime_disable(&pdev->dev);
+ cdns_sierra_phy_disable_clocks(phy);
/*
* The device level resets will be put automatically.
* Need to put the subnode resets here though.
--
2.17.1
[PATCH v3 08/15] phy: cadence: cadence-sierra: Explicitly request exclusive reset control
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 935f165404e4..44c52a0842dc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -514,14 +514,14 @@ static int cdns_sierra_phy_get_resets(struct
cdns_sierra_phy *sp,
{
struct reset_control *rst;
- rst = devm_reset_control_get(dev, "sierra_reset");
+ rst = devm_reset_control_get_exclusive(dev, "sierra_reset");
if (IS_ERR(rst)) {
dev_err(dev, "failed to get reset\n");
return PTR_ERR(rst);
}
sp->phy_rst = rst;
- rst = devm_reset_control_get_optional(dev, "sierra_apb");
+ rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");
if (IS_ERR(rst)) {
dev_err(dev, "failed to get apb reset\n");
return PTR_ERR(rst);
--
2.17.1
[PATCH v3 13/15] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES
Rename the external refclk inputs to the SERDES from
dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1
respectively. Also move the external refclk DT nodes outside the
cbass_main DT node. Since in j721e common processor board, only the
cmn_refclk1 is connected to 100MHz clock, fix the clock frequency.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++-
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 60764366e22b..86f7ab511ee8 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -635,6 +635,10 @@
status = "disabled";
};
+&cmn_refclk1 {
+ clock-frequency = <1>;
+};
+
&serdes0 {
serdes0_pcie_link: link@0 {
reg = <0>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 9d1edce31829..20cb390d33b0 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -8,6 +8,20 @@
#include
#include
+/ {
+ cmn_refclk: cmn-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cmn_refclk1: cmn-refclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@7000 {
compatible = "mmio-sram";
@@ -336,24 +350,12 @@
pinctrl-single,function-mask = <0x>;
};
- dummy_cmn_refclk: dummy-cmn-refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1>;
- };
-
- dummy_cmn_refclk1: dummy-cmn-refclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1>;
- };
-
serdes_wiz0: wiz@500 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>,
<&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
@@ -362,21 +364,21 @@
ranges = <0x500 0x0 0x500 0x1>;
wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
<&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
<&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
@@ -438,7 +440,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>,
<&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
@@ -447,21 +449,21 @@
ranges = <0x501 0x0 0x501 0x1>;
wiz1_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
[PATCH v3 06/15] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index f7ba0ed416bc..7bf1b4c7774a 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -477,6 +477,38 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
return 0;
}
+static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
+ struct device *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->clk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk_dig_div = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk1_dig_div = clk;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct platform_device *pdev)
{
struct cdns_sierra_phy *sp;
@@ -487,7 +519,6 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
unsigned int id_value;
int i, ret, node = 0;
void __iomem *base;
- struct clk *clk;
struct device_node *dn = dev->of_node, *child;
if (of_get_child_count(dn) == 0)
@@ -524,11 +555,9 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
platform_set_drvdata(pdev, sp);
- sp->clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(sp->clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(sp->clk);
- }
+ ret = cdns_sierra_phy_get_clocks(sp, dev);
+ if (ret)
+ return ret;
sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
if (IS_ERR(sp->phy_rst)) {
@@ -542,22 +571,6 @@ static int cdns_sierra_phy_probe(struct platform_device
*pdev)
return PTR_ERR(sp->apb_rst);
}
- clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk_dig_div clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk_dig_div = clk;
-
- clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk1_dig_div = clk;
-
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
[PATCH v3 14/15] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 86f7ab511ee8..788126daf91c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -639,6 +639,51 @@
clock-frequency = <1>;
};
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes0_pll_cmnlc {
+ assigned-clocks = <&serdes0_pll_cmnlc>;
+ assigned-clock-parents = <&serdes0_refrcv1>;
+};
+
+&wiz1_pll1_refclk {
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes1_pll_cmnlc {
+ assigned-clocks = <&serdes1_pll_cmnlc>;
+ assigned-clock-parents = <&serdes1_refrcv1>;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&serdes2_pll_cmnlc {
+ assigned-clocks = <&serdes2_pll_cmnlc>;
+ assigned-clock-parents = <&serdes2_refrcv1>;
+};
+
&serdes0 {
serdes0_pcie_link: link@0 {
reg = <0>;
--
2.17.1
[PATCH v3 15/15] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed in [1].
Re-name subnodes of serdes in J721E to 'phy'.
[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus
Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure
the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for
USB0")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 788126daf91c..13ae0d89caf2 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -358,7 +358,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -685,7 +685,7 @@
};
&serdes0 {
- serdes0_pcie_link: link@0 {
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -695,7 +695,7 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -705,7 +705,7 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
--
2.17.1
[RFC PATCH 1/3] gpio: ep93xx: convert to multi irqchips
Since gpiolib requires having separate irqchips for each gpiochip, we
need to add some we definetly need a separate one for F port, and we
could combine gpiochip A and B into one - but this will break namespace
and logick.
So despite 3 irqchips is a bit beefy we need a separate irqchip for each
interrupt capable port.
- added separate irqchip for each iterrupt capable gpiochip
- dropped ep93xx_gpio_port (it wasn't working correct for port F anyway)
- moved irq registers into separate struct ep93xx_irq_chip, togather
with regs current state
- reworked irq handle for ab gpiochips (through bit not tottaly sure this
is a correct thing to do)
- dropped has_irq and has_hierarchical_irq and added a simple index
which we rely on when adding irq's to gpiochip's
Signed-off-by: Nikita Shubin
---
drivers/gpio/gpio-ep93xx.c | 407 +
1 file changed, 227 insertions(+), 180 deletions(-)
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index 226da8df6f10..d6db0ff16581 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -34,103 +35,83 @@
*/
#define EP93XX_GPIO_F_IRQ_BASE 80
+struct ep93xx_irq_chip {
+ void __iomem*int_type1;
+ void __iomem*int_type2;
+ void __iomem*eoi;
+ void __iomem*en;
+ void __iomem*debounce;
+ void __iomem*status;
+ u8 gpio_int_unmasked;
+ u8 gpio_int_enabled;
+ u8 gpio_int_type1;
+ u8 gpio_int_type2;
+ u8 gpio_int_debounce;
+ struct irq_chip chip;
+};
+
+#define to_ep93xx_irq_chip(x) container_of(x, struct ep93xx_irq_chip, chip)
+
struct ep93xx_gpio {
- void __iomem*base;
- struct gpio_chipgc[8];
+ void __iomem*base;
+ struct ep93xx_irq_chip ic[3];
+ struct gpio_chipgc[8];
};
/*
* Interrupt handling for EP93xx on-chip GPIOs
*/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-
/* Port ordering is: A B F */
+static const char *irq_chip_names[3] = {"gpio-irq-a",
+ "gpio-irq-b",
+ "gpio-irq-f"};
static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]= { 0xa8, 0xc4, 0x64 };
+static const u8 int_status_register_offset[3] = { 0xa0, 0xbc, 0x5c };
-static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned
port)
-{
- BUG_ON(port > 2);
-
- writeb_relaxed(0, epg->base + int_en_register_offset[port]);
-
- writeb_relaxed(gpio_int_type2[port],
- epg->base + int_type2_register_offset[port]);
-
- writeb_relaxed(gpio_int_type1[port],
- epg->base + int_type1_register_offset[port]);
-
- writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
- epg->base + int_en_register_offset[port]);
-}
-
-static int ep93xx_gpio_port(struct gpio_chip *gc)
+static void ep93xx_gpio_update_int_params(struct ep93xx_irq_chip *eic)
{
- struct ep93xx_gpio *epg = gpiochip_get_data(gc);
- int port = 0;
-
- while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port])
- port++;
-
- /* This should not happen but is there as a last safeguard */
- if (port == ARRAY_SIZE(epg->gc)) {
- pr_crit("can't find the GPIO port\n");
- return 0;
- }
-
- return port;
+ writeb_relaxed(0, eic->en); // disable port irqs
+ writeb_relaxed(eic->gpio_int_type2, eic->int_type2);
+ writeb_relaxed(eic->gpio_int_type1, eic->int_type1);
+ writeb(eic->gpio_int_unmasked, eic->en); // enable port irqs
}
-static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
+static void ep93xx_gpio_int_debounce(struct ep93xx_irq_chip *eic,
unsigned int offset, bool enable)
{
- struct ep93xx_gpio *epg = gpiochip_get_data(gc);
- int port = ep93xx_gpio_port(gc);
int port_mask = BIT(offset);
if (enable)
- gpio_int_debounce[port] |= port_mask;
+ eic->gpio_int_debounce |= port_mask;
else
- gpio_int_debounce[port] &= ~port_mask
Re: [PATCH 1/2] dt-bindings: arm: fsl: Add binding for Gateworks boards with IMX8MM
On Wed, Dec 23, 2020 at 02:23:15PM -0800, Tim Harvey wrote: > Add bindings for the Gateworks Venice Development kit boards with > IMX8MM System on Module. > > Signed-off-by: Tim Harvey > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml > b/Documentation/devicetree/bindings/arm/fsl.yaml > index 1ca9dfa..705c6e8 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -405,6 +405,9 @@ properties: >- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit >- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board >- fsl,imx8mm-evk# i.MX8MM EVK Board > + - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit > + - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit > + - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit I think you should skip the wildcards in compatible and choose one specific compatible. What if at some point you would like to add gw,imx8mm-gw7113-0x? Best regards, Krzysztof >- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM > module >- const: fsl,imx8mm > > -- > 2.7.4 >
[RFC PATCH 2/3] gpio: ep93xx: drop to_irq binding
As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in
driver is useless, so let's drop it.
Also i think it is worth to give a gentle warning in
gpiochip_add_irqchip, to prevent people relying on to_irq.
For example
WARN_ON_ONCE(gc->to_irq,
"to_irq is redefined in gpiochip_add_irqchip" \
"and you shouldn't rely on it\n");
Signed-off-by: Nikita Shubin
---
drivers/gpio/gpio-ep93xx.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
index d6db0ff16581..90afe07213ce 100644
--- a/drivers/gpio/gpio-ep93xx.c
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -325,11 +325,6 @@ static int ep93xx_gpio_set_config(struct gpio_chip *gc,
unsigned offset,
return 0;
}
-static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
-{
- return EP93XX_GPIO_F_IRQ_BASE + offset;
-}
-
static int ep93xx_gpio_add_ab_irq_chip(struct gpio_chip *gc,
struct platform_device *pdev,
struct ep93xx_irq_chip *eic,
@@ -407,7 +402,6 @@ static int ep93xx_gpio_add_f_irq_chip(struct gpio_chip *gc,
}
girq->default_type = IRQ_TYPE_NONE;
girq->handler = handle_level_irq;
- gc->to_irq = ep93xx_gpio_f_to_irq;
return 0;
}
--
2.26.2
[RFC PATCH 0/3] gpio: ep93xx: convert to multi irqchips
I was lucky enough to became an owner of some splendid piece's of antiques called ts7250 based on the top of Cirrus Logic EP9302. I don't know what fate expects this hardware (it's not EOL it's just Not recommended for new designs) but i wanted to share fixes in ep93xx gpio area. It seems ep93xx is deadly broken at current state usage of AB gpiochips interrupts leads to deadlocks coused by irq_unmask/irq_mask recursions. Port F is not working at all: -bash-5.0# gpio-event-mon -n gpiochip5 -o 0 -r -f [ cut here ] kernel BUG at drivers/gpio/gpio-ep93xx.c:64! Internal error: Oops - BUG: 0 [#1] ARM Modules linked in: CPU: 0 PID: 403 Comm: gpio-event-mon Not tainted 5.9.10-00011-ge93e9618628b-dirty #19 Hardware name: Technologic Systems TS-72xx SBC PC is at ep93xx_gpio_update_int_params+0x1c/0x80 LR is at ep93xx_gpio_update_int_params+0x14/0x80 pc : []lr : []psr: 2093 sp : c158de00 ip : fp : 0001 r10: c44154d4 r9 : r8 : c4415020 r7 : c04ef884 r6 : c051c842 r5 : c4415020 r4 : 0005 r3 : r2 : r1 : c04eb768 r0 : 0008 Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none Control: 717f Table: 01684000 DAC: 0051 Process gpio-event-mon (pid: 403, stack limit = 0x(ptrval)) Stack: (0xc158de00 to 0xc158e000) de00: 0005 0002 c051c842 c0238dc0 c0238c98 c0238c98 c04ef874 de20: 0003 c04fcfcc 6013 c04ef910 c04ef8d4 c00456f0 c04ef874 c15f1e00 de40: 0001 c0045d40 c15f1e00 c4400160 c0044ca8 c04ef8a8 de60: 6013 c15f1e00 c04ef874 c04ef884 0001 c0235d70 c158b800 de80: be825f0f c0045ec8 0003 c158b800 c440aa00 be825bc8 0003 0001 dea0: c0236f00 c44ed3a0 c158b800 c45c2015 0001 0003 dec0: 6f697067 6576652d 6d2d746e 6e6f dee0: be825df4 c00abb0c c440c500 c00aabd4 c440c500 c528b840 c45c2010 c04e1228 df00: 0ff0 c4478d28 c030b404 be825bc8 c1550e20 0003 c1550e20 c00c3388 df20: c4478d28 c00c3d48 be825f0f c00abd00 c45c2000 c45c2000 c1550e20 c00bfea8 df40: 0003 c00b0714 c445 0004 0100 0001 c04e1228 df60: c158dfb0 ff9c 000231f8 0003 0142 c00b085c c04e1228 df80: be825f0f 0003 0003 0036 c00083c4 c158c000 dfa0: be825f0f c00081e0 be825f0f 0003 0003 c030b404 be825bc8 dfc0: be825f0f 0003 0003 0036 0001 00022070 be825f0f dfe0: b6f2e4e0 be825bac 00010acc b6f2e4ec 6010 0003 [] (ep93xx_gpio_update_int_params) from [] (ep93xx_gpio_irq_type+0x128/0x1c0) [] (ep93xx_gpio_irq_type) from [] (__irq_set_trigger+0x6c/0x128) [] (__irq_set_trigger) from [] (__setup_irq+0x594/0x678) [] (__setup_irq) from [] (request_threaded_irq+0xa4/0x128) [] (request_threaded_irq) from [] (gpio_ioctl+0x300/0x4d8) [] (gpio_ioctl) from [] (vfs_ioctl+0x24/0x3c) [] (vfs_ioctl) from [] (sys_ioctl+0xbc/0x768) [] (sys_ioctl) from [] (ret_fast_syscall+0x0/0x50) Exception stack(0xc158dfa8 to 0xc158dff0) dfa0: be825f0f 0003 0003 c030b404 be825bc8 dfc0: be825f0f 0003 0003 0036 0001 00022070 be825f0f dfe0: b6f2e4e0 be825bac 00010acc b6f2e4ec Code: e59f0060 ebfff3e1 e3540002 9a00 (e7f001f2) ---[ end trace 3f6544e133e9f5ae ]--- These change requires your judgment.
Re: [PATCH v4 3/7] mfd: max8997: Add of_compatible to extcon and charger mfd_cell
On Wed, 23 Dec 2020 15:32:07 +, Lee Jones wrote:
> On Wed, 23 Dec 2020, Timon Baetz wrote:
>
> > Add of_compatible ("maxim,max8997-muic") to the mfd_cell to have a
> > of_node set in the extcon driver.
> >
> > Add of_compatible ("maxim,max8997-battery") to the mfd_cell to configure
> > the charger driver.
> >
> > Signed-off-by: Timon Baetz
> > ---
> > drivers/mfd/max8997.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Why have you resent this? It's already applied.
>
I made a change to an other patch in this series and wasn't sure if I
had to resubmit everything.
Thanks and sorry for the spam.
Timon
[PATCH v4 2/3] media: v4l2-ctrl: Add layer wise bitrate controls for h264
Adds bitrate control for all coding layers for h264
same as hevc.
Signed-off-by: Dikshita Agarwal
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst | 20
drivers/media/v4l2-core/v4l2-ctrls.c | 7 +++
include/uapi/linux/v4l2-controls.h | 7 +++
3 files changed, 34 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
index 90c60ad..400774c 100644
--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst
@@ -1513,6 +1513,26 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type -
* - Bit 16:32
- Layer number
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 0 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 1 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 2 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 3 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 4 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 5 for H264 encoder.
+
+``V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR (integer)``
+Indicates bit rate (bps) for hierarchical coding layer 6 for H264 encoder.
.. _v4l2-mpeg-mpeg2:
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c
b/drivers/media/v4l2-core/v4l2-ctrls.c
index 410e541..16ab54f 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -922,6 +922,13 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264
P-Frame Maximum QP Value";
case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: return "H264
B-Frame Minimum QP Value";
case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: return "H264
B-Frame Maximum QP Value";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR:return "H264
Hierarchical Lay 0 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR:return "H264
Hierarchical Lay 1 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR:return "H264
Hierarchical Lay 2 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR:return "H264
Hierarchical Lay 3 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR:return "H264
Hierarchical Lay 4 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR:return "H264
Hierarchical Lay 5 Bitrate";
+ case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR:return "H264
Hierarchical Lay 6 Bitrate";
case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2
Level";
case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2
Profile";
case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4
I-Frame QP Value";
diff --git a/include/uapi/linux/v4l2-controls.h
b/include/uapi/linux/v4l2-controls.h
index d0a69a8..af8dda2 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -587,6 +587,13 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type {
#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP
(V4L2_CID_CODEC_BASE+388)
#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP
(V4L2_CID_CODEC_BASE+389)
#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP
(V4L2_CID_CODEC_BASE+390)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR
(V4L2_CID_CODEC_BASE+391)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR
(V4L2_CID_CODEC_BASE+392)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR
(V4L2_CID_CODEC_BASE+393)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR
(V4L2_CID_CODEC_BASE+394)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR
(V4L2_CID_CODEC_BASE+395)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR
(V4L2_CID_CODEC_BASE+396)
+#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR
(V4L2_CID_CODEC_BASE+397)
#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_CODEC_BASE+400)
#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_CODEC_BASE+401)
#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_CODEC_BASE+402)
--
2.7.4
[PATCH v4 1/3] media: v4l2-ctrl: Add frame-specific min/max qp controls for hevc
- Adds min/max qp controls for B frame for h264. - Adds min/max qp controls for I/P/B frames for hevc similar to h264. - Update valid range of min/max qp for hevc to accommodate 10 bit. Signed-off-by: Dikshita Agarwal --- .../userspace-api/media/v4l/ext-ctrls-codec.rst| 52 +- drivers/media/v4l2-core/v4l2-ctrls.c | 8 include/uapi/linux/v4l2-controls.h | 9 3 files changed, 67 insertions(+), 2 deletions(-) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst index 454ecd9..90c60ad 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst @@ -1182,6 +1182,18 @@ enum v4l2_mpeg_video_h264_entropy_mode - V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter should be chosen to meet both requirements. +``V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP (integer)`` +Minimum quantization parameter for the H264 B frame to limit B frame +quality to a range. Valid range: from 0 to 51. If +V4L2_CID_MPEG_VIDEO_H264_MIN_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP (integer)`` +Maximum quantization parameter for the H264 B frame to limit B frame +quality to a range. Valid range: from 0 to 51. If +V4L2_CID_MPEG_VIDEO_H264_MAX_QP is also set, the quantization parameter +should be chosen to meet both requirements. + ``V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (integer)`` Quantization parameter for an I frame for MPEG4. Valid range: from 1 to 31. @@ -2628,11 +2640,11 @@ HEVC/H.265 Control IDs ``V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (integer)`` Minimum quantization parameter for HEVC. -Valid range: from 0 to 51. +Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. ``V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (integer)`` Maximum quantization parameter for HEVC. -Valid range: from 0 to 51. +Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. ``V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (integer)`` Quantization parameter for an I frame for HEVC. @@ -2649,6 +2661,42 @@ HEVC/H.265 Control IDs Valid range: [V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP]. +``V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP (integer)`` +Minimum quantization parameter for the HEVC I frame to limit I frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP (integer)`` +Maximum quantization parameter for the HEVC I frame to limit I frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP (integer)`` +Minimum quantization parameter for the HEVC P frame to limit P frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP (integer)`` +Maximum quantization parameter for the HEVC P frame to limit P frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP (integer)`` +Minimum quantization parameter for the HEVC B frame to limit B frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP is also set, the quantization parameter +should be chosen to meet both requirements. + +``V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP (integer)`` +Maximum quantization parameter for the HEVC B frame to limit B frame +quality to a range. Valid range: from 0 to 51 for 8 bit and from 0 to 63 for 10 bit. +If V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP is also set, the quantization parameter +should be chosen to meet both requirements. + ``V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP (boolean)`` HIERARCHICAL_QP allows the host to specify the quantization parameter values for each temporal layer through HIERARCHICAL_QP_LAYER. This is diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 5cbe0ff..410e541 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -920,6 +920,8 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CI
[PATCH v4 3/3] venus: venc: Add support for frame-specific min/max qp controls
Add support for frame type specific min and max qp controls
for encoder.
This is a preparation patch to support v6.
Signed-off-by: Dikshita Agarwal
---
drivers/media/platform/qcom/venus/core.h | 18
drivers/media/platform/qcom/venus/venc.c | 21 +++--
drivers/media/platform/qcom/venus/venc_ctrls.c | 114 +++--
3 files changed, 142 insertions(+), 11 deletions(-)
diff --git a/drivers/media/platform/qcom/venus/core.h
b/drivers/media/platform/qcom/venus/core.h
index f03ed42..54c42a3 100644
--- a/drivers/media/platform/qcom/venus/core.h
+++ b/drivers/media/platform/qcom/venus/core.h
@@ -230,10 +230,28 @@ struct venc_controls {
u32 h264_b_qp;
u32 h264_min_qp;
u32 h264_max_qp;
+ u32 h264_i_min_qp;
+ u32 h264_i_max_qp;
+ u32 h264_p_min_qp;
+ u32 h264_p_max_qp;
+ u32 h264_b_min_qp;
+ u32 h264_b_max_qp;
u32 h264_loop_filter_mode;
s32 h264_loop_filter_alpha;
s32 h264_loop_filter_beta;
+ u32 hevc_i_qp;
+ u32 hevc_p_qp;
+ u32 hevc_b_qp;
+ u32 hevc_min_qp;
+ u32 hevc_max_qp;
+ u32 hevc_i_min_qp;
+ u32 hevc_i_max_qp;
+ u32 hevc_p_min_qp;
+ u32 hevc_p_max_qp;
+ u32 hevc_b_min_qp;
+ u32 hevc_b_max_qp;
+
u32 vp8_min_qp;
u32 vp8_max_qp;
diff --git a/drivers/media/platform/qcom/venus/venc.c
b/drivers/media/platform/qcom/venus/venc.c
index 1c61602..3961e03 100644
--- a/drivers/media/platform/qcom/venus/venc.c
+++ b/drivers/media/platform/qcom/venus/venc.c
@@ -669,17 +669,28 @@ static int venc_set_properties(struct venus_inst *inst)
return ret;
ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP;
- quant.qp_i = ctr->h264_i_qp;
- quant.qp_p = ctr->h264_p_qp;
- quant.qp_b = ctr->h264_b_qp;
+ if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
+ quant.qp_i = ctr->hevc_i_qp;
+ quant.qp_p = ctr->hevc_p_qp;
+ quant.qp_b = ctr->hevc_b_qp;
+ } else {
+ quant.qp_i = ctr->h264_i_qp;
+ quant.qp_p = ctr->h264_p_qp;
+ quant.qp_b = ctr->h264_b_qp;
+ }
quant.layer_id = 0;
ret = hfi_session_set_property(inst, ptype, &quant);
if (ret)
return ret;
ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE;
- quant_range.min_qp = ctr->h264_min_qp;
- quant_range.max_qp = ctr->h264_max_qp;
+ if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) {
+ quant_range.min_qp = ctr->hevc_min_qp;
+ quant_range.max_qp = ctr->hevc_max_qp;
+ } else {
+ quant_range.min_qp = ctr->h264_min_qp;
+ quant_range.max_qp = ctr->h264_max_qp;
+ }
quant_range.layer_id = 0;
ret = hfi_session_set_property(inst, ptype, &quant_range);
if (ret)
diff --git a/drivers/media/platform/qcom/venus/venc_ctrls.c
b/drivers/media/platform/qcom/venus/venc_ctrls.c
index cf860e6..496ad4d 100644
--- a/drivers/media/platform/qcom/venus/venc_ctrls.c
+++ b/drivers/media/platform/qcom/venus/venc_ctrls.c
@@ -135,9 +135,60 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
ctr->h264_min_qp = ctrl->val;
break;
+ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP:
+ ctr->h264_i_min_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP:
+ ctr->h264_p_min_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP:
+ ctr->h264_b_min_qp = ctrl->val;
+ break;
case V4L2_CID_MPEG_VIDEO_H264_MAX_QP:
ctr->h264_max_qp = ctrl->val;
break;
+ case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP:
+ ctr->h264_i_max_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP:
+ ctr->h264_p_max_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP:
+ ctr->h264_b_max_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
+ ctr->hevc_i_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
+ ctr->hevc_p_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
+ ctr->hevc_b_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
+ ctr->hevc_min_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP:
+ ctr->hevc_i_min_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP:
+ ctr->hevc_p_min_qp = ctrl->val;
+ break;
+ case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP:
+ ctr->he
Re: [PATCH v5 04/27] dt-bindings: memory: mediatek: Add domain definition
On Wed, 2020-12-23 at 17:15 +0900, Tomasz Figa wrote: > Hi Yong, > > On Wed, Dec 09, 2020 at 04:00:39PM +0800, Yong Wu wrote: > > In the latest SoC, there are several HW IP require a sepecial iova > > range, mainly CCU and VPU has this requirement. Take CCU as a example, > > CCU require its iova locate in the range(0x4000_ ~ 0x43ff_). > > Is this really a domain? Does the address range come from the design of > the IOMMU? It is not a really a domain. The address range comes from CCU HW requirement. That HW can only access this iova range. thus I create a special iommu domain for it. > > Best regards, > Tomasz > > > > > In this patch we add a domain definition for the special port. In the > > example of CCU, If we preassign CCU port in domain1, then iommu driver > > will prepare a independent iommu domain of the special iova range for it, > > then the iova got from dma_alloc_attrs(ccu-dev) will locate in its special > > range. > > > > This is a preparing patch for multi-domain support. > > > > Signed-off-by: Yong Wu > > Acked-by: Krzysztof Kozlowski > > Acked-by: Rob Herring > > --- > > include/dt-bindings/memory/mtk-smi-larb-port.h | 9 - > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h > > b/include/dt-bindings/memory/mtk-smi-larb-port.h > > index 7d64103209af..2d4c973c174f 100644 > > --- a/include/dt-bindings/memory/mtk-smi-larb-port.h > > +++ b/include/dt-bindings/memory/mtk-smi-larb-port.h > > @@ -7,9 +7,16 @@ > > #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ > > > > #define MTK_LARB_NR_MAX32 > > +#define MTK_M4U_DOM_NR_MAX 8 > > + > > +#define MTK_M4U_DOM_ID(domid, larb, port) \ > > + (((domid) & 0x7) << 16 | (((larb) & 0x1f) << 5) | ((port) & 0x1f)) > > + > > +/* The default dom id is 0. */ > > +#define MTK_M4U_ID(larb, port) MTK_M4U_DOM_ID(0, larb, port) > > > > -#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > > #define MTK_M4U_TO_LARB(id)(((id) >> 5) & 0x1f) > > #define MTK_M4U_TO_PORT(id)((id) & 0x1f) > > +#define MTK_M4U_TO_DOM(id) (((id) >> 16) & 0x7) > > > > #endif > > -- > > 2.18.0 > > > > ___ > > iommu mailing list > > io...@lists.linux-foundation.org > > https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v4 0/3] Add new controls for QP and layer bitrate
This series adds frame specific min/max qp controls for hevc and layer wise bitrate control for h264. Chnages since v2: - Rebased the changes on latest media tree - Added driver side implementation for new controls. Dikshita Agarwal (3): media: v4l2-ctrl: Add frame-specific min/max qp controls for hevc media: v4l2-ctrl: Add layer wise bitrate controls for h264 venus: venc: Add support for frame-specific min/max qp controls .../userspace-api/media/v4l/ext-ctrls-codec.rst| 72 - drivers/media/platform/qcom/venus/core.h | 18 drivers/media/platform/qcom/venus/venc.c | 21 +++- drivers/media/platform/qcom/venus/venc_ctrls.c | 114 +++-- drivers/media/v4l2-core/v4l2-ctrls.c | 15 +++ include/uapi/linux/v4l2-controls.h | 16 +++ 6 files changed, 243 insertions(+), 13 deletions(-) -- 2.7.4
Re: [PATCH v3 1/7] iommu: Move iotlb_sync_map out from __iommu_map
On Wed, 2020-12-23 at 08:51 +, Christoph Hellwig wrote:
> On Wed, Dec 16, 2020 at 06:36:01PM +0800, Yong Wu wrote:
> > In the end of __iommu_map, It alway call iotlb_sync_map.
> > This patch moves iotlb_sync_map out from __iommu_map since it is
> > unnecessary to call this for each sg segment especially iotlb_sync_map
> > is flush tlb all currently.
> >
> > Signed-off-by: Yong Wu
> > Reviewed-by: Robin Murphy
>
> What about adding a little helper that does the NULL check and method
> call instead of duplicating it all over?
Thanks for the review. Of course OK.
Then the code like below.
(If the helper name "_iommu_map" is not good, please tell me.)
+static int _iommu_map(struct iommu_domain *domain, unsigned long iova,
+ phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
+{
+ const struct iommu_ops *ops = domain->ops;
+ int ret;
+
+ ret = __iommu_map(domain, iova, paddr, size, prot, gfp);
+ if (ret == 0 && ops->iotlb_sync_map)
+ ops->iotlb_sync_map(domain);
+ return ret;
+}
+
int iommu_map(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
might_sleep();
- return __iommu_map(domain, iova, paddr, size, prot, GFP_KERNEL);
+ return _iommu_map(domain, iova, paddr, size, prot, GFP_KERNEL);
}
EXPORT_SYMBOL_GPL(iommu_map);
int iommu_map_atomic(struct iommu_domain *domain, unsigned long iova,
phys_addr_t paddr, size_t size, int prot)
{
- return __iommu_map(domain, iova, paddr, size, prot, GFP_ATOMIC);
+ return _iommu_map(domain, iova, paddr, size, prot, GFP_ATOMIC);
}
EXPORT_SYMBOL_GPL(iommu_map_atomic);
[RFC PATCH 3/3] gpio: ep93xx: specify gpio_irq_chip->first
Port F irq's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE. So we need to specify girq->first otherwise: "If device tree is used, then first_irq will be 0 and irqs get mapped dynamically on the fly" And that's not the thing we want. Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 90afe07213ce..a321a7441294 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -402,6 +402,7 @@ static int ep93xx_gpio_add_f_irq_chip(struct gpio_chip *gc, } girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; + girq->first = EP93XX_GPIO_F_IRQ_BASE; return 0; } -- 2.26.2
[PATCH] rtc: pm8xxx: Read ALARM_EN and update to alarm enabled status
ALARM_EN status is retained in PMIC register after device shutdown
if poweron_alarm is enabled. Read it to make sure the driver has
consistent value with the register status.
Signed-off-by: Guixiong Wei
---
drivers/rtc/rtc-pm8xxx.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index 0d9dd6f..70d1ff5 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -20,6 +20,7 @@
/* RTC_CTRL register bit fields */
#define PM8xxx_RTC_ENABLE BIT(7)
#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
+#define PM8xxx_RTC_ALARM_ENABLEBIT(7)
#define NUM_8_BIT_RTC_REGS 0x4
@@ -265,6 +266,7 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct
rtc_wkalrm *alarm)
static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
{
int rc;
+ unsigned int ctrl_reg;
u8 value[NUM_8_BIT_RTC_REGS];
unsigned long secs;
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
@@ -282,6 +284,13 @@ static int pm8xxx_rtc_read_alarm(struct device *dev,
struct rtc_wkalrm *alarm)
rtc_time64_to_tm(secs, &alarm->time);
+ rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
+ if (rc) {
+ dev_err(dev, "Read from RTC alarm control register failed\n");
+ return rc;
+ }
+ alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
+
dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
&alarm->time, &alarm->time);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Re: [PATCH v2 2/3] fscrypt: Add metadata encryption support
I realized I didn't update fscrypt_mergeable_bio() to take metadata encryption into account, so bios will be more fragmented than required. I'll fix it in v3.
Re: [PATCH v5 06/27] dt-bindings: mediatek: Add binding for mt8192 IOMMU
On Wed, 2020-12-23 at 17:18 +0900, Tomasz Figa wrote: > On Wed, Dec 09, 2020 at 04:00:41PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > >| > > M4U > >| > > > >SMI Common > > > >| > > +---+--+--+--+---+ > > | | | | .. | | > > | | | | | | > > larb0 larb1 larb2 larb4 .. larb19 larb20 > > disp0 disp1 mdpvdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > >0 disp0 ~ 4G larb0/1 > >1 vcodec 4G ~ 8G larb4/5/7 > >2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > > Why do we preassign these addresses in DT? Shouldn't it be a user's or > integrator's decision to split the 16 GB address range into sub-ranges > and define which larbs those sub-ranges are shared with? The problem is that we can't split the 16GB range with the larb as unit. The example is the below ccu0(larb13 port9/10) is a independent range(domain), the others ports in larb13 is in another domain. disp/vcodec/cam/mdp don't have special iova requirement, they could access any range. vcodec also can locate 8G~12G. it don't care about where its iova locate. here I preassign like this following with our internal project setting. Why set this in DT?, this is only for simplifying the code. Assume we put it in the platform data. We have up to 32 larbs, each larb has up to 32 ports, each port may be in different iommu domains. we should have a big array for this..however we only use a macro to get the domain in the DT method. When replying this mail, I happen to see there is a "dev->dev_range_map" which has "dma-range" information, I think I could use this value to get which domain the device belong to. then no need put domid in DT. I will test this. Thanks. > > Best regards, > Tomasz > > >3 CCU00x4000_ ~ 0x43ff_ larb13: port 9/10 > >4 CCU10x4400_ ~ 0x47ff_ larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../bindings/iommu/mediatek,iommu.yaml| 18 +- > > include/dt-bindings/memory/mt8192-larb-port.h | 240 ++ > > 2 files changed, 257 insertions(+), 1 deletion(-) > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > [snip]
Re: [PATCH 2/2] arm64: dts: imx8mm: Add Gateworks IMX8MM Development Kits
On Wed, Dec 23, 2020 at 02:23:16PM -0800, Tim Harvey wrote:
> The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development
> kits comprised of a GW700x SoM and a Baseboard.
>
> The GW700x SoM contains:
> - IMX8MM SoC
It's i.MX 8M Mini.
https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI
> - LPDDR4 DRAM
> - eMMC FLASH
> - Gateworks System Controller (eeprom/pushbutton/reset/voltage-monitor)
> - GbE PHY connected to the IMX8MM FEC
> - Power Management IC
>
> The GW71xx Baseboard contains:
> - 1x MiniPCIe Socket with USB2.0, PCIe, and SIM
> - 1x RJ45 GbE (IMX8MM FEC)
> - PCIe Clock generator
> - GPS and accelerometer
> - 1x USB 2.0 Front Panel connector
> - wide range power supply
>
> The GW72xx Baseboard contains:
> - 2x MiniPCIe Socket with USB2.0, PCIe, and SIM
> - 2x RJ45 GbE (IMX8MM FEC and LAN743x)
> - 1x MicroSD connector
> - 1x USB 2.0 Front Panel connector
> - 1x SPI connector
> - PCIe Clock generator
> - GPS and accelerometer
> - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S)
> - wide range power supply
>
> The GW73xx Baseboard contains:
> - 3x MiniPCIe Socket with USB2.0, PCIe, and SIM
> - 2x RJ45 GbE (IMX8MM FEC and LAN743x)
> - 1x MicroSD connector
> - 1x USB 2.0 Front Panel connector
> - 1x SPI connector
> - WiFi/BT
> - PCIe Clock generator
> - GPS and accelerometer
> - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S)
> - wide range power supply
>
> Signed-off-by: Tim Harvey
> ---
> arch/arm64/boot/dts/freescale/Makefile | 3 +
> .../boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 482
> +
> .../boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts | 19 +
> .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 186
> .../boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts | 20 +
> .../boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 311 +
> .../boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts | 19 +
> .../boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 363
> 8 files changed, 1403 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> index f8d5943..ecdd233 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
> new file mode 100644
> index ..7e1b96b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
> @@ -0,0 +1,482 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2020 Gateworks Corporation
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
> + memory@4000 {
> + device_type = "memory";
> + reg = <0x0 0x4000 0 0x8000>;
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + user_pb {
> + label = "user_pb";
> + gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>;
> + linux,code = ;
> + };
> +
> + user_pb1x {
> + label = "user_pb1x";
> + linux,code = ;
> + interrupt-parent = <&gsc>;
> + interrupts = <0>;
> + };
> +
> + key_erased {
> + label = "key-erased";
Above you use underscore, here hyphen. Make it consistent.
> + linux,code = ;
> + interrupt-parent = <&gsc>;
> + interrupts = <1>;
> + };
> +
> + eeprom_wp {
> +
[PATCH 1/7] dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper
Add bindings for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index c33e9bc79521..4a1f9c27b5f0 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -12,9 +12,13 @@ maintainers: properties: compatible: -enum: - - ti,j721e-wiz-16g - - ti,j721e-wiz-10g +oneOf: + - const: ti,j721e-wiz-16g + - const: ti,j721e-wiz-10g + - const: ti,am64-wiz-10g + - items: + - const: ti,am64-wiz-10g + - const: ti,j721e-wiz-10g power-domains: maxItems: 1 -- 2.17.1
[PATCH 6/7] phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. In order to drive the refclk out from the SERDES
(Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ.
Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can
enable it.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 115 +
1 file changed, 115 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 08acfab1ebe6..d60a9a01a8b2 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -54,6 +54,7 @@ enum wiz_refclk_div_sel {
static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
+static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30,
30);
static const struct reg_field pll1_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 29, 29);
static const struct reg_field pll0_refclk_mux_sel =
@@ -141,6 +142,15 @@ struct wiz_clk_div_sel {
const char *node_name;
};
+struct wiz_phy_en_refclk {
+ struct clk_hw hw;
+ struct regmap_field *phy_en_refclk;
+ struct clk_init_dataclk_data;
+};
+
+#define to_wiz_phy_en_refclk(_hw) \
+ container_of(_hw, struct wiz_phy_en_refclk, hw)
+
static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
{
/*
@@ -214,6 +224,7 @@ struct wiz {
unsigned intclk_div_sel_num;
struct regmap_field *por_en;
struct regmap_field *phy_reset_n;
+ struct regmap_field *phy_en_refclk;
struct regmap_field *p_enable[WIZ_MAX_LANES];
struct regmap_field *p_align[WIZ_MAX_LANES];
struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
@@ -450,9 +461,96 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->typec_ln10_swap);
}
+ wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap,
+phy_en_refclk);
+ if (IS_ERR(wiz->phy_en_refclk)) {
+ dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
+ return PTR_ERR(wiz->phy_en_refclk);
+ }
+
return 0;
}
+static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+
+ regmap_field_write(phy_en_refclk, 1);
+
+ return 0;
+}
+
+static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+
+ regmap_field_write(phy_en_refclk, 0);
+}
+
+static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
+ struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
+ int val;
+
+ regmap_field_read(phy_en_refclk, &val);
+
+ return !!val;
+}
+
+static const struct clk_ops wiz_phy_en_refclk_ops = {
+ .enable = wiz_phy_en_refclk_enable,
+ .disable = wiz_phy_en_refclk_disable,
+ .is_enabled = wiz_phy_en_refclk_is_enabled,
+};
+
+static int wiz_phy_en_refclk_register(struct wiz *wiz, struct device_node
*node,
+ struct regmap_field *phy_en_refclk)
+{
+ struct wiz_phy_en_refclk *wiz_phy_en_refclk;
+ struct device *dev = wiz->dev;
+ struct clk_init_data *init;
+ unsigned int num_parents;
+ const char *parent_name;
+ char clk_name[100];
+ struct clk *clk;
+ int ret;
+
+ wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk),
+GFP_KERNEL);
+ if (!wiz_phy_en_refclk)
+ return -ENOMEM;
+
+ num_parents = of_clk_get_parent_count(node);
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
+node->name);
+
+ init = &wiz_phy_en_refclk->clk_data;
+
+ init->ops = &wiz_phy_en_refclk_ops;
+ init->flags = 0;
+ init->parent_names = parent_name ? &parent_name : NULL;
+ init->num_parents = num_parents ? 1 : 0;
+ init->name = clk_name;
+
+ wiz_phy_en_refclk->phy_en_refclk = phy_en_refclk;
+ wiz_phy_en_refclk->hw.init = init;
+
+ clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ if (ret)
+ dev_err(dev
[PATCH 3/7] dt-bindings: phy: cadence-torrent: Add binding for refclk driver
Add binding for refclk driver used to route the refclk out of the SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/phy/phy-cadence-torrent.yaml | 17 + 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index e266ade53d87..d3b96afd514c 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -125,6 +125,23 @@ patternProperties: additionalProperties: false + "^refclk-driver": +type: object +description: | + Driver to route the reference clock out of the SERDES. +properties: + clocks: +maxItems: 1 +description: Phandle to clock nodes representing the input to the + refclk driver. + + "#clock-cells": +const: 0 + +required: + - clocks + - "#clock-cells" + required: - compatible - "#address-cells" -- 2.17.1
[PATCH 5/7] phy: ti: j721e-wiz: Configure full rate divider for AM64
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 43 +++---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2a03191eac64..08acfab1ebe6 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -101,6 +101,13 @@ static const struct reg_field
p_standard_mode[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 24, 25),
};
+static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 22, 23),
+ REG_FIELD(WIZ_LANECTL(1), 22, 23),
+ REG_FIELD(WIZ_LANECTL(2), 22, 23),
+ REG_FIELD(WIZ_LANECTL(3), 22, 23),
+};
+
static const struct reg_field typec_ln10_swap =
REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
@@ -193,6 +200,7 @@ static struct wiz_clk_div_sel clk_div_sel[] = {
enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
+ AM64_WIZ_10G,
};
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
@@ -210,6 +218,7 @@ struct wiz {
struct regmap_field *p_align[WIZ_MAX_LANES];
struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
+ struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
@@ -380,7 +389,7 @@ static int wiz_regfield_init(struct wiz *wiz)
}
clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
clk_mux_sel->field =
devm_regmap_field_alloc(dev, regmap,
refclk_dig_sel_10g);
@@ -424,6 +433,14 @@ static int wiz_regfield_init(struct wiz *wiz)
i);
return PTR_ERR(wiz->p_standard_mode[i]);
}
+
+ wiz->p0_fullrt_div[i] =
+ devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
+ if (IS_ERR(wiz->p0_fullrt_div[i])) {
+ dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n",
+ i);
+ return PTR_ERR(wiz->p0_fullrt_div[i]);
+ }
}
wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
@@ -719,6 +736,19 @@ static int wiz_phy_reset_assert(struct
reset_controller_dev *rcdev,
return ret;
}
+static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
+{
+ int ret = 0;
+
+ if (wiz->type != AM64_WIZ_10G)
+ return 0;
+
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ ret = regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+
+ return ret;
+}
+
static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
@@ -742,6 +772,10 @@ static int wiz_phy_reset_deassert(struct
reset_controller_dev *rcdev,
return ret;
}
+ ret = wiz_phy_fullrt_div(wiz, id - 1);
+ if (ret)
+ return ret;
+
if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
else
@@ -769,6 +803,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
},
+ {
+ .compatible = "ti,am64-wiz-10g", .data = (void *)AM64_WIZ_10G
+ },
{}
};
MODULE_DEVICE_TABLE(of, wiz_id_table);
@@ -904,14 +941,14 @@ static int wiz_probe(struct platform_device *pdev)
wiz->dev = dev;
wiz->regmap = regmap;
wiz->num_lanes = num_lanes;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_mux_sel = clk_mux_sel_10g;
else
wiz->clk_mux_sel = clk_mux_sel_16g;
wiz->clk_div_sel = clk_div_sel;
- if (wiz->type == J721E_WIZ_10G)
+ if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G)
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
else
wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
--
2.17.1
[PATCH 2/7] dt-bindings: phy: ti,phy-j721e-wiz: Add binding for phy_en_refclk
Add DT binding for phy_en_refclk used to route the refclk out of the SERDES. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 + 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 4a1f9c27b5f0..14823588bc94 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -149,6 +149,19 @@ patternProperties: - assigned-clocks - assigned-clock-parents + "^phy-en-refclk$": +type: object +description: | + In order to drive the refclk out from the SERDES (Cadence Torrent), + PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model phy-en-refclk + as a clock so that it can be enabled directly or as a parent clock. +properties: + "#clock-cells": +const: 0 + +required: + - "#clock-cells" + "^serdes@[0-9a-f]+$": type: object description: | -- 2.17.1
[PATCH 7/7] phy: cadence-torrent: Add support to drive refclk out
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 158 ++
1 file changed, 158 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index f310e15d94cb..ad01fb61cfa4 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
#include
@@ -76,6 +77,8 @@
* register offsets from SD0801 PHY register block base (i.e MHDP
* register base + 0x50)
*/
+#define CMN_CDIAG_REFCLK_OVRD 0x004CU
+#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
#define CMN_SSM_BANDGAP_TMR0x0021U
#define CMN_SSM_BIAS_TMR 0x0022U
#define CMN_PLLSM0_PLLPRE_TMR 0x002AU
@@ -206,6 +209,8 @@
#define RX_DIAG_ACYA 0x01FFU
/* PHY PCS common registers */
+#define PHY_PIPE_CMN_CTRL1 0xU
+#define PHY_ISO_CMN_CTRL 0x0008U
#define PHY_PLL_CFG0x000EU
#define PHY_PIPE_USB3_GEN2_PRE_CFG00x0020U
#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
@@ -231,6 +236,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
static const struct reg_field phy_reset_ctrl =
REG_FIELD(PHY_RESET, 8, 8);
+#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG 2
+
+enum cdns_torrent_refclk_out_pcs {
+ PHY_ISO_CMN_CTRL_8,
+ PHY_PIPE_CMN_CTRL1_0,
+};
+
+#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG 5
+
+enum cdns_torrent_refclk_out_cmn {
+ CMN_CDIAG_REFCLK_OVRD_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_1,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_4,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_5,
+ CMN_CDIAG_REFCLK_DRV0_CTRL_6,
+};
+
+static const struct reg_field refclk_out_pcs_cfg[] = {
+ [PHY_ISO_CMN_CTRL_8]= REG_FIELD(PHY_ISO_CMN_CTRL, 8, 8),
+ [PHY_PIPE_CMN_CTRL1_0] = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0),
+};
+
+static const struct reg_field refclk_out_cmn_cfg[] = {
+ [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4,
4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL,
1, 1),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL,
4, 4),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL,
5, 5),
+ [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL,
6, 6),
+};
+
enum cdns_torrent_phy_type {
TYPE_NONE,
TYPE_DP,
@@ -288,6 +323,16 @@ enum phy_powerstate {
POWERSTATE_A3 = 3,
};
+struct cdns_torrent_derived_refclk {
+ struct clk_hw hw;
+ struct regmap_field
*pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
+ struct regmap_field
*cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
+ struct clk_init_dataclk_data;
+};
+
+#define to_cdns_torrent_derived_refclk(_hw)\
+ container_of(_hw, struct cdns_torrent_derived_refclk,
hw)
+
static int cdns_torrent_phy_init(struct phy *phy);
static int cdns_torrent_dp_init(struct phy *phy);
static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
@@ -1604,6 +1649,110 @@ static int cdns_torrent_dp_run(struct cdns_torrent_phy
*cdns_phy, u32 num_lanes)
return ret;
}
+static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk =
to_cdns_torrent_derived_refclk(hw);
+
+
regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
+
regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
+
regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
+
regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
+ regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4],
1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
+
+ return 0;
+}
+
+static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk =
to_cdns_torrent_derived_refclk(hw);
+
+ regmap_field_write(derived_refclk->pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
+}
+
+static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
+{
+ struct cdns_torrent_derived_refclk *derived_refclk =
to_cdns_torrent_derived_refclk(hw);
+ int val;
+
+
[PATCH 4/7] dt-bindings: ti-serdes-mux: Add defines for AM64 SoC
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I --- include/dt-bindings/mux/ti-serdes.h | 4 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 9047ec6bd3cf..68e0f76deed1 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -90,4 +90,8 @@ #define J7200_SERDES0_LANE3_USB0x2 #define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 +/* AM64 */ +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- 2.17.1
[PATCH 0/7] AM64: Add SERDES bindings and driver support
AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series adds support to drive reference clock output from SERDES and also adds SERDES (torrent) and SERDES wrapper (WIZ) bindings. Kishon Vijay Abraham I (7): dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES Wrapper dt-bindings: phy: ti,phy-j721e-wiz: Add binding for phy_en_refclk dt-bindings: phy: cadence-torrent: Add binding for refclk driver dt-bindings: ti-serdes-mux: Add defines for AM64 SoC phy: ti: j721e-wiz: Configure full rate divider for AM64 phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_ phy: cadence-torrent: Add support to drive refclk out .../bindings/phy/phy-cadence-torrent.yaml | 17 ++ .../bindings/phy/ti,phy-j721e-wiz.yaml| 23 ++- drivers/phy/cadence/phy-cadence-torrent.c | 158 ++ drivers/phy/ti/phy-j721e-wiz.c| 158 +- include/dt-bindings/mux/ti-serdes.h | 4 + 5 files changed, 354 insertions(+), 6 deletions(-) -- 2.17.1
Re: [Cocci] [PATCH v3] scripts: coccicheck: Correct usage of make coccicheck
On Wed, 25 Nov 2020, Sumera Priyadarsini wrote:
> The command "make coccicheck C=1 CHECK=scripts/coccicheck" results in the
> error:
> ./scripts/coccicheck: line 65: -1: shift count out of range
>
> This happens because every time the C variable is specified,
> the shell arguments need to be "shifted" in order to take only
> the last argument, which is the C file to test. These shell arguments
> mostly comprise flags that have been set in the Makefile. However,
> when coccicheck is specified in the make command as a rule, the
> number of shell arguments is zero, thus passing the invalid value -1
> to the shift command, resulting in an error.
>
> Modify coccicheck to print correct usage of make coccicheck so as to
> avoid the error.
Applied, thanks.
julia
>
> Signed-off-by: Sumera Priyadarsini
> ---
> Changes in v2:
> - Move test to only display error message
>
> Changes in v3:
> - Update example with latest file
> ---
> scripts/coccicheck | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/scripts/coccicheck b/scripts/coccicheck
> index 209bb0427b43..d1aaa1dc0a69 100755
> --- a/scripts/coccicheck
> +++ b/scripts/coccicheck
> @@ -61,6 +61,18 @@ COCCIINCLUDE=${COCCIINCLUDE// -include/ --include}
> if [ "$C" = "1" -o "$C" = "2" ]; then
> ONLINE=1
>
> +if [[ $# -le 0 ]]; then
> + echo ''
> + echo 'Specifying both the variable "C" and rule "coccicheck" in the
> make
> +command results in a shift count error.'
> + echo ''
> + echo 'Try specifying "scripts/coccicheck" as a value for the CHECK
> variable instead.'
> + echo ''
> + echo 'Example: make C=2 CHECK=scripts/coccicheck
> drivers/net/ethernet/ethoc.o'
> + echo ''
> + exit 1
> +fi
> +
> # Take only the last argument, which is the C file to test
> shift $(( $# - 1 ))
> OPTIONS="$COCCIINCLUDE $1"
> --
> 2.25.1
>
> ___
> Cocci mailing list
> co...@systeme.lip6.fr
> https://systeme.lip6.fr/mailman/listinfo/cocci
>
[PATCH 0/4] AM64: Add PCIe bindings and driver support
AM64 uses the same PCIe controller as in J7200, however AM642 EVM doesn't have a clock generator (unlike J7200 base board). Here the clock from the SERDES has to be routed to the PCIE connector. This series provides an option for the pci-j721e.c driver to drive reference clock output to the connector. Kishon Vijay Abraham I (4): dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector dt-bindings: pci: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC dt-bindings: pci: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC PCI: j721e: Add support to provide refclk to PCIe connector .../bindings/pci/ti,j721e-pci-ep.yaml | 10 --- .../bindings/pci/ti,j721e-pci-host.yaml | 27 ++- drivers/pci/controller/cadence/pci-j721e.c| 17 3 files changed, 44 insertions(+), 10 deletions(-) -- 2.17.1
[PATCH 1/4] dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector
Add binding to represent refclk to the PCIe connector. Signed-off-by: Kishon Vijay Abraham I --- .../bindings/pci/ti,j721e-pci-host.yaml | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 0880a613ece6..7607018a115b 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -46,12 +46,21 @@ properties: maxItems: 1 clocks: -maxItems: 1 -description: clock-specifier to represent input to the PCIe +minItems: 1 +maxItems: 2 +description: clock-specifier to represent input to the PCIe for 1 item. + 2nd item if present represents reference clock to the connector. clock-names: -items: - - const: fck +oneOf: + - description: Represent input clock to the PCIe +items: + - const: fck + - description: Represent input clock to the PCIe and reference clock to + the connector. +items: + - const: fck + - const: pcie_refclk vendor-id: const: 0x104c -- 2.17.1
[PATCH 3/4] dt-bindings: pci: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index d06f0c4464c6..447c8fe0f09e 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -16,12 +16,17 @@ allOf: properties: compatible: oneOf: - - description: PCIe EP controller in J7200 + - const: ti,am64-pcie-ep + - const: ti,j7200-pcie-ep + - const: ti,j721e-pcie-ep + - description: PCIe EP controller in AM64 items: + - const: ti,am64-pcie-ep - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep - - description: PCIe EP controller in J721E + - description: PCIe EP controller in J7200 items: + - const: ti,j7200-pcie-ep - const: ti,j721e-pcie-ep reg: @@ -66,7 +71,6 @@ required: - power-domains - clocks - clock-names - - dma-coherent - max-functions - phys - phy-names -- 2.17.1
[PATCH 2/4] dt-bindings: pci: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in J7200, however AM64 is a non-coherent architecture. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 7607018a115b..77118dba415e 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -16,12 +16,17 @@ allOf: properties: compatible: oneOf: - - description: PCIe controller in J7200 + - const: ti,am64-pcie-host + - const: ti,j7200-pcie-host + - const: ti,j721e-pcie-host + - description: PCIe controller in AM64 items: + - const: ti,am64-pcie-host - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host - - description: PCIe controller in J721E + - description: PCIe controller in J7200 items: + - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host reg: @@ -87,7 +92,6 @@ required: - vendor-id - device-id - msi-map - - dma-coherent - dma-ranges - ranges - reset-gpios -- 2.17.1
[PATCH 4/4] PCI: j721e: Add support to provide refclk to PCIe connector
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
index dac1ac8a7615..8ec6d9c3e164 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -6,6 +6,7 @@
* Author: Kishon Vijay Abraham I
*/
+#include
#include
#include
#include
@@ -50,6 +51,7 @@ enum link_status {
struct j721e_pcie {
struct device *dev;
+ struct clk *refclk;
u32 mode;
u32 num_lanes;
struct cdns_pcie*cdns_pcie;
@@ -310,6 +312,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
struct cdns_pcie_ep *ep;
struct gpio_desc *gpiod;
void __iomem *base;
+ struct clk *clk;
u32 num_lanes;
u32 mode;
int ret;
@@ -408,6 +411,19 @@ static int j721e_pcie_probe(struct platform_device *pdev)
goto err_get_sync;
}
+ clk = devm_clk_get_optional(dev, "pcie_refclk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get pcie_refclk\n");
+ goto err_pcie_setup;
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(dev, "failed to enable pcie_refclk\n");
+ goto err_get_sync;
+ }
+ pcie->refclk = clk;
+
/*
* "Power Sequencing and Reset Signal Timings" table in
* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
@@ -476,6 +492,7 @@ static int j721e_pcie_remove(struct platform_device *pdev)
struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
struct device *dev = &pdev->dev;
+ clk_disable_unprepare(pcie->refclk);
cdns_pcie_disable_phy(cdns_pcie);
pm_runtime_put(dev);
pm_runtime_disable(dev);
--
2.17.1
Re: [PATCH v1] scsi: ufs-mediatek: Enable UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL
On Thu, 2020-12-24 at 11:03 +, Avri Altman wrote: > > > Do you see any substantial benefit of having > > > fWriteBoosterBufferFlushEn > > > disabled? > > > > 1. The definition of fWriteBoosterBufferFlushEn is that host allows > > device to do flush in anytime after fWriteBoosterBufferFlushEn is > > set as > > on. This is not what we want. > > > > Just Like BKOP, We do not want flush happening beyond host's > > expected > > timing that device performance may be "randomly" dropped. > > Explicit flush takes place only when the device is idle: > if fWriteBoosterBufferFlushEn is set, the device is idle, and before > h8 received. > If a request arrives, the flush operation should be halted. > So no performance degradation is expected. Hi Stanley Avri's comment is correct, fWriteBoosterBufferFlushEn==1, device will flush only when it is in idle, once there is new incoming request, the flush will be suspended. You should be very careful when you want to skip this stetting of this flag. Bean
[PATCH] arm64: dts: qcom: msm8996: Add missing device_type under pcie[01]
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index fd6ae5464dea..e7eb2c9f37af 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -750,6 +750,8 @@ pcie0: pcie@60 {
ranges = <0x0100 0x0 0x0c20 0x0c20
0x0 0x10>,
<0x0200 0x0 0x0c30 0x0c30
0x0 0xd0>;
+ device_type = "pci";
+
interrupts = ;
interrupt-names = "msi";
#interrupt-cells = <1>;
@@ -802,6 +804,8 @@ pcie1: pcie@608000 {
ranges = <0x0100 0x0 0x0d20 0x0d20
0x0 0x10>,
<0x0200 0x0 0x0d30 0x0d30
0x0 0xd0>;
+ device_type = "pci";
+
interrupts = ;
interrupt-names = "msi";
#interrupt-cells = <1>;
--
2.29.2
