[PATCH] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
From: wthai
The GB200NVL BMC is an Aspeed Ast2600 based BMC
for Nvidia Blackwell GB200NVL platform.
Signed-off-by: wthai
---
.../bindings/arm/aspeed/aspeed.yaml |1 +
arch/arm/boot/dts/aspeed/Makefile |1 +
.../aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 1352 +
3 files changed, 1354 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
index 2f92b8ab08fa..0a6f3654dcb5 100644
--- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
+++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
@@ -96,6 +96,7 @@ properties:
- inventec,starscream-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
+ - nvidia,gb200nvl-bmc
- qcom,dc-scm-v1-bmc
- quanta,s6q-bmc
- ufispace,ncplite-bmc
diff --git a/arch/arm/boot/dts/aspeed/Makefile
b/arch/arm/boot/dts/aspeed/Makefile
index c4f064e4b073..0dc5240866f3 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-lenovo-hr630.dtb \
aspeed-bmc-lenovo-hr855xg2.dtb \
aspeed-bmc-microsoft-olympus.dtb \
+ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-mowgli.dtb \
aspeed-bmc-opp-nicole.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
new file mode 100644
index ..91d025229aba
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
@@ -0,0 +1,1352 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include
+#include
+
+&gpio0 {
+ gpio-line-names =
+
+ /* gpio-line-names are the combination of - , "" is the
placeholder for the unused pins
+ */
+
+ /* 208 (26*8) 3.3V GPIOs */
+
+ /*A0-A7*/
+ "", "", "", "", "", "", "", "",
+
+ /*B0-B7*/
+ "", "", "", "", "", "", "", "",
+
+ /*C0-C7*/
+ "SGPIO_I2C_MUX_SEL-O",
+ "", "", "", "", "", "", "",
+
+ /*D0-D7*/
+ "", "", "",
+ "UART1_MUX_SEL-O",
+ "",
+ "FPGA_PEX_RST_L-O",
+ "", "",
+
+ /*E0-E7*/
+ "RTL8221_PHY_RST_L-O",
+ "RTL8211_PHY_INT_L-I",
+ "",
+ "UART3_MUX_SEL-O",
+ "", "", "",
+ "SGPIO_BMC_EN-O",
+
+ /*F0-F7*/
+ "", "", "", "", "", "", "", "",
+
+ /*G0-G7*/
+ "", "", "", "", "", "", "", "",
+
+ /*H0-H7*/
+ "", "", "", "", "", "", "", "",
+
+ /*I0-I7*/
+ "", "", "", "", "",
+ "QSPI2_RST_L-O",
+ "GLOBAL_WP_BMC-O",
+ "BMC_DDR4_TEN-O",
+
+ /*J0-J7*/
+ "", "", "", "", "", "", "", "",
+
+ /*K0-K7*/
+ "", "", "", "", "", "", "", "",
+
+ /*L0-L7*/
+ "", "", "", "", "", "", "", "",
+
+ /*M0-M7*/
+ "PCIE_EP_RST_EN-O",
+ "BMC_FRU_WP-O",
+ "HMC_RESET_L-O",
+ "STBY_POWER_EN-O",
+ "STBY_POWER_PG-I",
+ "PCIE_EP_RST_L-O",
+ "", "",
+
+ /*N0-N7*/
+ "", "", "", "", "", "", "", "",
+
+ /*O0-O7*/
+ "", "", "", "", "", "", "", "",
+
+ /*P0-P7*/
+ "", "", "", "", "", "", "", "",
+
+ /*Q0-Q7*/
+ "", "", "", "", "", "", "", "",
+
+ /*R0-R7*/
+ "", "", "", "", "", "", "", "",
+
+ /*S0-S7*/
+ "", "", "", "", "", "", "", "",
+
+ /*T0-T7*/
+ "", "", "", "", "", "", "", "",
+
+ /*U0-U7*/
+ "", "", "", "", "", "", "", "",
+
+ /*V0-V7*/
+ "AP_EROT_REQ-O",
+ "EROT_AP_GNT-I",
+ "",
+ "",
+ "PCB_TEMP_ALERT-I",
+ "", "", "",
+
+ /*W0-W7*/
+ "", "", "", "", "", "", "", "",
+
+ /*X0-X7*/
+ "", "",
+ "TPM_MUX_SEL-O",
+ "", "", "", "", "",
+
+ /*Y0-Y7*/
+ "", "", "",
+ "EMMC_RST-O",
+ "","", "", "",
+
+ /*Z0-Z7*/
+ "BMC_READY-O",
+ "", "", "", "", "", "", "";
+};
+
+&sgpiom0 {
+ status="okay";
+ ngpios = <128>;
+
+ gpio-line-names =
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "RUN_POWER_FAULT_L-I",
+ "SYS_RST_IN_L-O",
+ "RUN_POWER_PG-I",
+ "PWR_BRAKE_L-O",
+ "SYS_RST_OUT_L-I",
+ "RUN_POWER_EN-O",
+ "L0L1_RST_REQ_OUT_L-I",
+ "SHDN_FORCE_L-O",
+ "L2_RST_REQ_OUT_L-I",
+ "SHDN_REQ_L-O",
+ "SHDN_OK_L-I",
+ "UID_LED_N-O",
+ "BMC_I2C1_FPGA_ALERT_L-I",
+ "SYS_FAULT_LED_N-O",
+ "BMC_I2C0_FPGA_ALERT_L-I",
+ "PWR_LED_N-O",
+ "FPGA_RSVD_FFU3-I",
+ "",
+
[PATCH v2] ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
The GB200NVL BMC is an Aspeed Ast2600 based BMC
for Nvidia Blackwell GB200NVL platform.
Reference to Ast2600 SOC [1].
Reference to Blackwell GB200NVL Platform [2].
Co-developed-by: Mars Yang
Signed-off-by: Mars Yang
Cc: Krzysztof Kozlowski
Cc: Andrew Lunn
Cc: Paul Menzel
Link: Reference to Ast2600 SOC: https://www.aspeedtech.com/server_ast2600/ [1]
Link: Reference to Blackwell GB200NVL Platform:
https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2]
Signed-off-by: Willie Thai
---
Changes in v2:
- Fix the SOB name [Krzysztof]
- Fix warnings from scripts/checkpatch.pl run [Krzysztof]
- Fix DTS coding style [Krzysztof]
- Move pinctrl override to the bottom [Krzysztof]
- Drop bootargs [Krzysztof]
- Follow DTS coding style and change naming for leds node [Krzysztof]
- Change flash 0 status property [Krzysztof]
- Change the phy-mode to rgmii [Andrew]
- Remove the max-speed in mac0 [Andrew]
---
---
arch/arm/boot/dts/aspeed/Makefile |1 +
.../aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 1229 +
2 files changed, 1230 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
diff --git a/arch/arm/boot/dts/aspeed/Makefile
b/arch/arm/boot/dts/aspeed/Makefile
index 2e5f4833a073..20fd357a1ee9 100644
--- a/arch/arm/boot/dts/aspeed/Makefile
+++ b/arch/arm/boot/dts/aspeed/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-lenovo-hr630.dtb \
aspeed-bmc-lenovo-hr855xg2.dtb \
aspeed-bmc-microsoft-olympus.dtb \
+ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \
aspeed-bmc-opp-lanyang.dtb \
aspeed-bmc-opp-mowgli.dtb \
aspeed-bmc-opp-nicole.dtb \
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
new file mode 100644
index ..eeec3704a43b
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
@@ -0,0 +1,1229 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include
+#include
+
+/ {
+ model = "AST2600 GB200NVL BMC";
+ compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600";
+
+ aliases {
+ serial2 = &uart3;
+ serial4 = &uart5;
+ i2c16 = &imux16;
+ i2c17 = &imux17;
+ i2c18 = &imux18;
+ i2c19 = &imux19;
+ i2c20 = &imux20;
+ i2c21 = &imux21;
+ i2c22 = &imux22;
+ i2c23 = &imux23;
+ i2c24 = &imux24;
+ i2c25 = &imux25;
+ i2c26 = &imux26;
+ i2c27 = &imux27;
+ i2c28 = &imux28;
+ i2c29 = &imux29;
+ i2c30 = &imux30;
+ i2c31 = &imux31;
+ i2c32 = &imux32;
+ i2c33 = &imux33;
+ i2c34 = &imux34;
+ i2c35 = &imux35;
+ i2c36 = &imux36;
+ i2c37 = &imux37;
+ i2c38 = &imux38;
+ i2c39 = &imux39;
+ i2c40 = &e1si2c0;
+ i2c41 = &e1si2c1;
+ i2c42 = &e1si2c2;
+ i2c43 = &e1si2c3;
+ i2c44 = &e1si2c4;
+ i2c45 = &e1si2c5;
+ i2c46 = &e1si2c6;
+ i2c47 = &e1si2c7;
+ i2c48 = &i2c17mux0;
+ i2c49 = &i2c17mux1;
+ i2c50 = &i2c17mux2;
+ i2c51 = &i2c17mux3;
+ i2c52 = &i2c25mux0;
+ i2c53 = &i2c25mux1;
+ i2c54 = &i2c25mux2;
+ i2c55 = &i2c25mux3;
+ i2c56 = &i2c29mux0;
+ i2c57 = &i2c29mux1;
+ i2c58 = &i2c29mux2;
+ i2c59 = &i2c29mux3;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ };
+
+ memory@8000 {
+ device_type = "memory";
+ reg = <0x8000 0x8000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vga_memory: framebuffer@9f00 {
+ no-map;
+ reg = <0x9f00 0x0100>; /* 16M */
+ };
+
+ ramoops@a000 {
+ compatible = "ramoops";
+ reg = <0xa000 0x10>; /* 1MB */
+ record-size = <0x1>; /* 64KB */
+ max-reason = <2>; /* KMSG_DUMP_OOPS */
+ };
+
+
