Hi Chander,
On 01/25/12 07:19, Chander Kashyap wrote:
> SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
>
> Signed-off-by: Chander Kashyap
> ---
[...]
> diff --git a/board/samsung/smdk5250/dmc_init.c
> b/board/samsung/smdk5250/dmc_init.c
> new file mode 100644
> index 000..6f92d8a
> --- /dev/null
> +++ b/board/samsung/smdk5250/dmc_init.c
> @@ -0,0 +1,508 @@
> +/*
> + * Memory setup for SMDK5250 board based on EXYNOS5
> + *
> + * Copyright (C) 2011 Samsung Electronics
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "setup.h"
> +
> +/* APLL : 1GHz */
> +/* MCLK_CDREX: MCLK_CDREX_533*/
> +/* LPDDR support: LPDDR2 */
> +
> +void mem_ctrl_asm_init()
> +{
> + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
> + struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
> + struct exynos5_dmc *dmc;
> + unsigned int val;
> +
> + phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
> + phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
> + dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
> +
> + /* Reset PHY Controllor: PHY_RESET[0] */
> + writel(0x0, &clk->lpddr3phy_ctrl);
> +
> + sdelay(0x1);
> +
> + /*set Read Latance and Burst Length for PHY0 and PHY1 */
> + val = 0x408;
> + writel(val, &phy0_ctrl->phy_con42);
> + writel(val, &phy1_ctrl->phy_con42);
> +
> + /*
> + * ZQ Calibration:
> + * Select Driver Strength,
> + * long calibration for manual calibration
> + */
> + val = 0x0DA40304;
> + writel(val, &phy0_ctrl->phy_con16);
> + writel(val, &phy1_ctrl->phy_con16);
> +
> + /* Enable termination */
> + val = 0x0DAC0304;
> + writel(val, &phy0_ctrl->phy_con16);
> + writel(val, &phy1_ctrl->phy_con16);
> +
> + /* Start Manual Calibration */
> + val = 0x0DAC0306;
> + writel(val, &phy0_ctrl->phy_con16);
> + writel(val, &phy1_ctrl->phy_con16);
> +
> + sdelay(0x1);
> +
> + /* Enable termination */
> + val = 0x0DAC0304;
> + writel(val, &phy0_ctrl->phy_con16);
> + writel(val, &phy1_ctrl->phy_con16);
> +
> + /* DDR Mode: LPDDR2 */
> + val = 0x17021240;
> + writel(val, &phy0_ctrl->phy_con0);
> + writel(val, &phy1_ctrl->phy_con0);
> +
> + /* DQS, DQ: Signal, for LPDDR2: Always Set */
> + val = 0x0F0F;
> + writel(val, &phy0_ctrl->phy_con14);
> + writel(val, &phy1_ctrl->phy_con14);
> +
> + /* RD_FETCH: 1 */
> + val = 0x1FFF1000;
> + writel(val, &dmc->concontrol);
> + sdelay(0x1);
> +
> + val = 0x0FFF1000;
> + writel(val, &dmc->concontrol);
> + sdelay(0x1);
> +
> + /*
> + * Update DLL Information:
> + * Force DLL Resyncronization
> + */
> + val = 0x0008;
> + writel(val, &dmc->phycontrol0);
> +
> + /* Reset Force DLL Resyncronization */
> + val = 0x;
> + writel(val, &dmc->phycontrol0);
> +
> + /*
> + * Dynamic Clock: Always Running
> + * Memory Burst length: 4
> + * Number of chips: 2
> + * Memory Bus width: 32 bit
> + * Memory Type: LPDDR2-S4
> + * Additional Latancy for PLL: 1 Cycle
> + */
> + val = 0x00212500;
> + writel(val, &dmc->memcontrol);
> +
> + /*
> + * Memory Configuration Chip 0
> + * Address Mapping: Interleaved
> + * Number of Column address Bits: 10 bits
> + * Number of Rows Address Bits: 14
> + * Number of Banks: 8
> + */
> + val = 0x1323;
> + writel(val, &dmc->memconfig0);
> +
> + /*
> + * Memory Configuration Chip 1
> + * Address Mapping: Interleaved
> + * Number of Column address Bits: 10 bits
> + * Number of Rows Address Bits: 14
> + * Number of Banks: 8
> + */
> + val = 0x1323;
> + writel(val, &dmc->memconfig1);
> +
> + /*
> + * Chip0: AXI
> + * AXI Base Address: 0x4000
> + * AXI Base Address Mask: 0x780
> + */
> + val = 0x00400780;
> + writel(val, &dmc->membaseconfig0);
> +
> + /*
> + * Chip1: AXI
> + * AXI Base Address: 0x80
