[Intel-gfx] [PATCH i-g-t 1/2] lib/kbl: move KBL check from IS_SKYLAKE() to IS_GEN9()
Remove the KBL check from IS_SKYLAKE() following the kernel definition. Then, add the KBL check to IS_GEN9(). The idea is to avoid confusion. On the kernel side, the mix of SKY and KBL was nacked so the platforms are split. Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer --- lib/intel_chipset.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 6fcc244..f9fcdd6 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -434,8 +434,7 @@ void intel_check_pch(void); IS_KBL_GT2(devid) || \ IS_KBL_GT3(devid)) -#define IS_SKYLAKE(devid) (IS_KABYLAKE(devid) || \ -IS_SKL_GT1(devid) || \ +#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ IS_SKL_GT3(devid)) @@ -443,7 +442,9 @@ void intel_check_pch(void); (devid) == PCI_CHIP_BROXTON_1 || \ (devid) == PCI_CHIP_BROXTON_2) -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid)) +#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \ +IS_SKYLAKE(devid) || \ +IS_BROXTON(devid)) #define IS_965(devid) (IS_GEN4(devid) || \ IS_GEN5(devid) || \ -- 2.6.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] lib/kbl: Add Kabylake GT4 PCI IDs
Add the Kabylake GT4 PCI IDs as defined in this kernel patch. commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d Author: Deepak S Date: Wed Oct 28 12:21:12 2015 -0700 drm/i915/kbl: Add Kabylake GT4 PCI ID Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer --- lib/intel_chipset.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index f9fcdd6..19fa02f 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -217,13 +217,17 @@ void intel_check_pch(void); #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B #define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A #define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A +#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 @@ -430,9 +434,15 @@ void intel_check_pch(void); (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) +#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_WKS_GT4) + #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ IS_KBL_GT2(devid) || \ -IS_KBL_GT3(devid)) +IS_KBL_GT3(devid) || \ +IS_KBL_GT4(devid)) #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ -- 2.6.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Clean up device info structure definitions
Beginning with gen7, newer devices repetitively redefine values
for the device info structure members. This patch simplifies the
structure definitions by grouping member value definitions into the
existing GEN7_FEATURES #define and into the new GEN7_LP_FEATURES
and HSW_FEATURES #defines.
Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are
added to GEN7_FEATURES and subsequent IVB definitions are simplified.
GEN7_LP_FEATURES is created to differentiate and simplify the
gen7 low power (LP) devices.
HSW_FEATURES is created and used to simplify all HSW+ devices
except for LP.
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_drv.c | 137 ++--
1 file changed, 35 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90faa8e..5f8b0ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -226,125 +226,87 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
#define GEN7_FEATURES \
.gen = 7, .num_pipes = 3, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
- .has_llc = 1
+ .has_llc = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS
static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.is_mobile = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.num_pipes = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
+#define GEN7_LP_FEATURES \
+ .gen = 7, .num_pipes = 2, \
+ .need_gfx_hws = 1, .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .display_mmio_offset = VLV_DISPLAY_BASE, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ CURSOR_OFFSETS
+
static const struct intel_device_info intel_valleyview_m_info = {
- GEN7_FEATURES,
- .is_mobile = 1,
- .num_pipes = 2,
+ GEN7_LP_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
+ .is_mobile = 1,
};
static const struct intel_device_info intel_valleyview_d_info = {
- GEN7_FEATURES,
- .num_pipes = 2,
+ GEN7_LP_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
};
+#define HSW_FEATURES \
+ GEN7_FEATURES, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1
+
static const struct intel_device_info intel_haswell_d_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_haswell_m_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
.is_mobile = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_broadwell_d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- .gen = 8, .is_mobile = 1, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
+ HSW_FEATURES,
+ .gen = 8,
.ring_mask = RENDER_RING | BSD_RING
[Intel-gfx] [PATCH] drm/i915: Separate cherryview from valleyview
The cherryview device shares many characteristics with the valleyview
device. When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.
This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and defines the HAS_GEN7_LP_FEATURES macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
HAS_GEN7_LP_FEATURES to test for either a valleyview or a cherryview
device.
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 -
drivers/gpu/drm/i915/i915_dma.c | 8 ++---
drivers/gpu/drm/i915/i915_drv.c | 10 +++---
drivers/gpu/drm/i915/i915_drv.h | 19
drivers/gpu/drm/i915/i915_gem.c | 4 +--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 6 ++--
drivers/gpu/drm/i915/i915_irq.c | 8 ++---
drivers/gpu/drm/i915/i915_suspend.c | 4 +--
drivers/gpu/drm/i915/i915_sysfs.c | 10 +++---
drivers/gpu/drm/i915/intel_audio.c | 6 ++--
drivers/gpu/drm/i915/intel_crt.c| 4 +--
drivers/gpu/drm/i915/intel_display.c| 54 -
drivers/gpu/drm/i915/intel_dp.c | 38 +++
drivers/gpu/drm/i915/intel_dsi.c| 13
drivers/gpu/drm/i915/intel_dsi_pll.c| 6 ++--
drivers/gpu/drm/i915/intel_hdmi.c | 4 +--
drivers/gpu/drm/i915/intel_hotplug.c| 2 +-
drivers/gpu/drm/i915/intel_i2c.c| 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8 ++---
drivers/gpu/drm/i915/intel_psr.c| 4 +--
drivers/gpu/drm/i915/intel_sprite.c | 4 +--
drivers/gpu/drm/i915/intel_uncore.c | 6 ++--
25 files changed, 123 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bfd57fb..a2d50da 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -862,7 +862,7 @@ static int i915_interrupt_info(struct seq_file *m, void
*data)
I915_READ(GEN8_PCU_IIR));
seq_printf(m, "PCU interrupt enable:\t%08x\n",
I915_READ(GEN8_PCU_IER));
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (HAS_GEN7_LP_FEATURES(dev)) {
seq_printf(m, "Display IER:\t%08x\n",
I915_READ(VLV_IER));
seq_printf(m, "Display IIR:\t%08x\n",
@@ -1284,7 +1284,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (HAS_GEN7_LP_FEATURES(dev)) {
u32 freq_sts;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -1602,7 +1602,7 @@ static int i915_drpc_info(struct seq_file *m, void
*unused)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
- if (IS_VALLEYVIEW(dev))
+ if (HAS_GEN7_LP_FEATURES(dev))
return vlv_drpc_info(m);
else if (INTEL_INFO(dev)->gen >= 6)
return gen6_drpc_info(m);
@@ -1743,7 +1743,7 @@ static int i915_sr_status(struct seq_file *m, void
*unused)
sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
else if (IS_PINEVIEW(dev))
sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
- else if (IS_VALLEYVIEW(dev))
+ else if (HAS_GEN7_LP_FEATURES(dev))
sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
intel_runtime_pm_put(dev_priv);
@@ -3983,7 +3983,7 @@ static int pipe_crc_set_source(struct drm_device *dev,
enum pipe pipe,
ret = i8xx_pipe_crc_ctl_reg(&source, &val);
else if (INTEL_INFO(dev)->gen < 5)
ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
- else if (IS_VALLEYVIEW(dev))
+ else if (HAS_GEN7_LP_FEATURES(dev))
ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ret = ilk_pipe_crc_ctl_reg(&source, &val);
@@ -4052,7 +4052,7 @@ static int pipe_crc_set_source(struct drm_device *dev,
enum pipe pipe,
if (IS_G4X(dev))
g4x_undo_pipe_scramble_reset(dev, pipe);
- else if (IS_VALLEYVIEW(dev))
+ else if (HAS_GEN7_LP_FEATURES(dev))
vlv_undo_pipe_scramble_reset(dev, pipe);
else if (IS_HASWELL(dev) &a
[Intel-gfx] [PATCH] drm/i915: Clean up device info structure definitions
Beginning with gen7, newer devices repetitively redefine values
for the device info structure members. This patch simplifies the
structure definitions by grouping member value definitions into the
existing GEN7_FEATURES #define and into the new GEN7_LP_FEATURES
and HSW_FEATURES #defines.
Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are
added to GEN7_FEATURES and subsequent IVB definitions are simplified.
VLV_FEATURES is defined to differentiate and simplify the
gen7 low power (LP) devices.
HSW_FEATURES is defined and used to simplify all HSW+ devices
except for LP.
v2: Use VLV_FEATURES for the gen7 low power devices. (Jani)
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_drv.c | 137 ++--
1 file changed, 35 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90faa8e..d2d7e24 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -226,125 +226,87 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
#define GEN7_FEATURES \
.gen = 7, .num_pipes = 3, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
- .has_llc = 1
+ .has_llc = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS
static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.is_mobile = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.num_pipes = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
+#define VLV_FEATURES \
+ .gen = 7, .num_pipes = 2, \
+ .need_gfx_hws = 1, .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .display_mmio_offset = VLV_DISPLAY_BASE, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ CURSOR_OFFSETS
+
static const struct intel_device_info intel_valleyview_m_info = {
- GEN7_FEATURES,
- .is_mobile = 1,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
+ .is_mobile = 1,
};
static const struct intel_device_info intel_valleyview_d_info = {
- GEN7_FEATURES,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
};
+#define HSW_FEATURES \
+ GEN7_FEATURES, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1
+
static const struct intel_device_info intel_haswell_d_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_haswell_m_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
.is_mobile = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_broadwell_d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- .gen = 8, .is_mobile = 1, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
+ HSW_FEATURES,
+ .gen = 8
[Intel-gfx] [PATCH] drm/i915: Clean up device info structure definitions
Beginning with gen7, newer devices repetitively redefine values
for the device info structure members. This patch simplifies the
structure definitions by grouping member value definitions into the
existing GEN7_FEATURES #define and into the new GEN7_LP_FEATURES
and HSW_FEATURES #defines.
Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are
added to GEN7_FEATURES and subsequent IVB definitions are simplified.
VLV_FEATURES is defined to differentiate and simplify the
gen7 low power (LP) devices.
HSW_FEATURES is defined and used to simplify all HSW+ devices
except for LP.
v2: Use VLV_FEATURES for the gen7 low power devices. (Jani)
v3: Include HSW_FEATURES definition in intel_skylake_gt3_info. (Chris)
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_drv.c | 138 +++-
1 file changed, 36 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90faa8e..46ac664 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -226,125 +226,87 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
#define GEN7_FEATURES \
.gen = 7, .num_pipes = 3, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
- .has_llc = 1
+ .has_llc = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS
static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.is_mobile = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.num_pipes = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
+#define VLV_FEATURES \
+ .gen = 7, .num_pipes = 2, \
+ .need_gfx_hws = 1, .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .display_mmio_offset = VLV_DISPLAY_BASE, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ CURSOR_OFFSETS
+
static const struct intel_device_info intel_valleyview_m_info = {
- GEN7_FEATURES,
- .is_mobile = 1,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
+ .is_mobile = 1,
};
static const struct intel_device_info intel_valleyview_d_info = {
- GEN7_FEATURES,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
};
+#define HSW_FEATURES \
+ GEN7_FEATURES, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1
+
static const struct intel_device_info intel_haswell_d_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_haswell_m_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
.is_mobile = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_broadwell_d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- .gen = 8, .is_mobile = 1, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- .gen = 8, .num_pipes = 3
[Intel-gfx] [PATCH] drm/i915: Clean up device info structure definitions
Beginning with gen7, newer devices repetitively redefine values
for the device info structure members. This patch simplifies the
structure definitions by grouping member value definitions into the
existing GEN7_FEATURES #define and into the new VLV_FEATURES and
HSW_FEATURES #defines.
Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are
added to GEN7_FEATURES and subsequent IVB definitions are simplified.
VLV_FEATURES is defined to differentiate and simplify the
gen7 low power (LP) devices.
HSW_FEATURES is defined and used to simplify all HSW+ devices
except for LP.
v2: Use VLV_FEATURES for the gen7 low power devices. (Jani)
v3: Include HSW_FEATURES definition in intel_skylake_gt3_info. (Chris)
v4: Fix commit message.
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_drv.c | 138 +++-
1 file changed, 36 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 90faa8e..46ac664 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -226,125 +226,87 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
#define GEN7_FEATURES \
.gen = 7, .num_pipes = 3, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
- .has_llc = 1
+ .has_llc = 1, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ IVB_CURSOR_OFFSETS
static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.is_mobile = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
.is_ivybridge = 1,
.num_pipes = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
+#define VLV_FEATURES \
+ .gen = 7, .num_pipes = 2, \
+ .need_gfx_hws = 1, .has_hotplug = 1, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
+ .display_mmio_offset = VLV_DISPLAY_BASE, \
+ GEN_DEFAULT_PIPEOFFSETS, \
+ CURSOR_OFFSETS
+
static const struct intel_device_info intel_valleyview_m_info = {
- GEN7_FEATURES,
- .is_mobile = 1,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
+ .is_mobile = 1,
};
static const struct intel_device_info intel_valleyview_d_info = {
- GEN7_FEATURES,
- .num_pipes = 2,
+ VLV_FEATURES,
.is_valleyview = 1,
- .display_mmio_offset = VLV_DISPLAY_BASE,
- .has_fbc = 0, /* legal, last one wins */
- .has_llc = 0, /* legal, last one wins */
- GEN_DEFAULT_PIPEOFFSETS,
- CURSOR_OFFSETS,
};
+#define HSW_FEATURES \
+ GEN7_FEATURES, \
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
+ .has_ddi = 1, \
+ .has_fpga_dbg = 1
+
static const struct intel_device_info intel_haswell_d_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_haswell_m_info = {
- GEN7_FEATURES,
+ HSW_FEATURES,
.is_haswell = 1,
.is_mobile = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
};
static const struct intel_device_info intel_broadwell_d_info = {
- .gen = 8, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8,
};
static const struct intel_device_info intel_broadwell_m_info = {
- .gen = 8, .is_mobile = 1, .num_pipes = 3,
- .need_gfx_hws = 1, .has_hotplug = 1,
- .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .has_llc = 1,
- .has_ddi = 1,
- .has_fpga_dbg = 1,
- .has_fbc = 1,
- GEN_DEFAULT_PIPEOFFSETS,
- IVB_CURSOR_OFFSETS,
+ HSW_FEATURES,
+ .gen = 8, .is_mobile = 1,
};
static const struct intel_device_info intel_broadwell_gt3d_info = {
- .gen = 8, .num_pipes = 3
[Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices
Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.
In this case, in i915_gem_alloc_context_obj() only call
i915_gem_object_set_cache_level() for Ivy Bridge devices
since later platforms don't have L3 control bits in the PTE.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 4b1161d..e4de433 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t
size)
/*
* Try to make the context utilize L3 as well as LLC.
*
-* On VLV we don't have L3 controls in the PTEs so we
-* shouldn't touch the cache level, especially as that
-* would make the object snooped which might have a
-* negative performance impact.
+* This is only applicable for Ivy Bridge devices since
+* later platforms don't have L3 control bits in the PTE.
*/
- if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
!IS_CHERRYVIEW(dev)) {
+ if (IS_IVYBRIDGE(dev)) {
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
/* Failure shouldn't ever happen this early */
if (WARN_ON(ret)) {
--
2.6.3
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[Intel-gfx] [PATCH 3/5] drm/i915: Remove VLV A0 hack
Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.
In this case remove a hack for VLV A0.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_gem.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b722a61..4556500 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4838,14 +4838,6 @@ int i915_gem_init(struct drm_device *dev)
mutex_lock(&dev->struct_mutex);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
- /* VLVA0 (potential hack), BIOS isn't actually waking us */
- I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
- if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
- VLV_GTLC_ALLOWWAKEACK), 10))
- DRM_DEBUG_DRIVER("allow wake ack timed out\n");
- }
-
if (!i915.enable_execlists) {
dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
dev_priv->gt.init_rings = i915_gem_init_rings;
--
2.6.3
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[Intel-gfx] [PATCH 1/5] drm/i915: Separate cherryview from valleyview
The cherryview device shares many characteristics with the valleyview
device. When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.
This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
Also add followup patches to fix issues discovered during the first
review. (Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_debugfs.c | 68 -
drivers/gpu/drm/i915/i915_dma.c | 8 ++--
drivers/gpu/drm/i915/i915_drv.c | 10 ++---
drivers/gpu/drm/i915/i915_drv.h | 16 +---
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
drivers/gpu/drm/i915/i915_suspend.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 10 ++---
drivers/gpu/drm/i915/intel_audio.c | 7 ++--
drivers/gpu/drm/i915/intel_bios.c | 4 +-
drivers/gpu/drm/i915/intel_crt.c| 2 +-
drivers/gpu/drm/i915/intel_display.c| 54 ++
drivers/gpu/drm/i915/intel_dp.c | 40 +--
drivers/gpu/drm/i915/intel_dsi.c| 14 +++
drivers/gpu/drm/i915/intel_dsi_pll.c| 6 +--
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_hotplug.c| 2 +-
drivers/gpu/drm/i915/intel_i2c.c| 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
drivers/gpu/drm/i915/intel_psr.c| 6 +--
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
24 files changed, 149 insertions(+), 140 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..a9ae642 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
- } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
- IS_BROADWELL(dev) || IS_GEN9(dev)) {
+ } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ u32 freq_sts;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+ seq_printf(m, "actual GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+ seq_printf(m, "current GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+ seq_printf(m, "max GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+ seq_printf(m, "min GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+ seq_printf(m, "idle GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+ seq_printf(m,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ } else if (IS_GEN6(dev) || IS_BROADWELL(dev) || IS_GEN9(dev)) {
u32 rp_state_limits;
u32 gt_perf_status;
u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
- } else if (IS_VALLEYVIEW(dev)) {
- u32 freq_sts;
-
- mutex_lock(&dev_priv->rps.hw_lock);
- freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
-
[Intel-gfx] [PATCH 0/5] CHV and VLV separation and clean up
The cherryview device shares many characteristics with the valleyview device. When support was added to the driver for cherryview, the corresponding device info structure included .is_valleyview = 1. This is not correct and leads to some confusion. In addition to separating cherryview from valleyview, this series helps to organize and prepare the code for future platforms. It helps avoid confusion like there was with IS_SKYLAKE and IS_KABYLAKE, and it makes things easier if we decide to add .is_atom_lp to these platform definitions. Finally, it provides fixes to issues that were identified in the first iteration of the separation changes. Wayne Boyer (5): drm/i915: Separate cherryview from valleyview drm/i915: Use HAS_PCH_SPLIT to determine correct devices drm/i915: Remove VLV A0 hack drm/i915: Only set gem object L3 cache level for IVB devices drm/i915: Remove BUG_ON call in vlv_enable_pll drivers/gpu/drm/i915/i915_debugfs.c | 68 - drivers/gpu/drm/i915/i915_dma.c | 8 ++-- drivers/gpu/drm/i915/i915_drv.c | 10 ++--- drivers/gpu/drm/i915/i915_drv.h | 16 +--- drivers/gpu/drm/i915/i915_gem.c | 10 + drivers/gpu/drm/i915/i915_gem_context.c | 8 ++-- drivers/gpu/drm/i915/i915_irq.c | 8 ++-- drivers/gpu/drm/i915/i915_suspend.c | 4 +- drivers/gpu/drm/i915/i915_sysfs.c | 10 ++--- drivers/gpu/drm/i915/intel_audio.c | 7 ++-- drivers/gpu/drm/i915/intel_bios.c | 4 +- drivers/gpu/drm/i915/intel_crt.c| 2 +- drivers/gpu/drm/i915/intel_display.c| 57 +-- drivers/gpu/drm/i915/intel_dp.c | 40 +-- drivers/gpu/drm/i915/intel_dsi.c| 14 +++ drivers/gpu/drm/i915/intel_dsi_pll.c| 6 +-- drivers/gpu/drm/i915/intel_hdmi.c | 4 +- drivers/gpu/drm/i915/intel_hotplug.c| 2 +- drivers/gpu/drm/i915/intel_i2c.c| 2 +- drivers/gpu/drm/i915/intel_panel.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 8 ++-- drivers/gpu/drm/i915/intel_psr.c| 6 +-- drivers/gpu/drm/i915/intel_sprite.c | 4 +- drivers/gpu/drm/i915/intel_uncore.c | 4 +- 24 files changed, 150 insertions(+), 154 deletions(-) -- 2.6.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Use HAS_PCH_SPLIT to determine correct devices
Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.
In this case check for '(GEN7 || GEN8) && HAS_PCH_SPLIT' since we're
reading FUSE_STRAP and SFUSE_STRAP which live in the PCH.
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index b156b08e..d816aa2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -791,7 +791,7 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
info->num_pipes = 0;
} else if (info->num_pipes > 0 &&
(INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
- !(IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) {
+ HAS_PCH_SPLIT(dev)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
u32 sfuse_strap = I915_READ(SFUSE_STRAP);
--
2.6.3
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[Intel-gfx] [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case remove the BUG_ON call in vlv_enable_pll(). Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer --- drivers/gpu/drm/i915/intel_display.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 05458a6..2b7d27d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc, assert_pipe_disabled(dev_priv, crtc->pipe); - /* No really, not for ILK+ */ - BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); - /* PLL is protected by panel, make sure we can write it */ if (IS_MOBILE(dev_priv->dev)) assert_panel_unlocked(dev_priv, crtc->pipe); -- 2.6.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Remove BUG_ON call in vlv_enable_pll
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case remove the BUG_ON call in vlv_enable_pll(). v2: Also remove the BUG_ON call in chv_enable_pll(). (Ville) Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer --- drivers/gpu/drm/i915/intel_display.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 05458a6..3c86649 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1607,9 +1607,6 @@ static void vlv_enable_pll(struct intel_crtc *crtc, assert_pipe_disabled(dev_priv, crtc->pipe); - /* No really, not for ILK+ */ - BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); - /* PLL is protected by panel, make sure we can write it */ if (IS_MOBILE(dev_priv->dev)) assert_panel_unlocked(dev_priv, crtc->pipe); @@ -1647,8 +1644,6 @@ static void chv_enable_pll(struct intel_crtc *crtc, assert_pipe_disabled(dev_priv, crtc->pipe); - BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); - mutex_lock(&dev_priv->sb_lock); /* Enable back the 10bit clock to display controller */ -- 2.6.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices
Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.
In this case, in i915_gem_alloc_context_obj() only call
i915_gem_object_set_cache_level() for Ivy Bridge devices
since later platforms don't have L3 control bits in the PTE.
v2: Expand comment to mention snooping requirement. (Ville, Imre)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_gem_context.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 4b1161d..900ffd0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -189,8 +189,15 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t
size)
* shouldn't touch the cache level, especially as that
* would make the object snooped which might have a
* negative performance impact.
+*
+* Snooping is required on non-llc platforms in execlist
+* mode, but since all GGTT accesses use PAT entry 0 we
+* get snooping anyway regardless of cache_level.
+*
+* This is only applicable for Ivy Bridge devices since
+* later platforms don't have L3 control bits in the PTE.
*/
- if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
!IS_CHERRYVIEW(dev)) {
+ if (IS_IVYBRIDGE(dev)) {
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
/* Failure shouldn't ever happen this early */
if (WARN_ON(ret)) {
--
2.6.3
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[Intel-gfx] [PATCH 1/5] drm/i915: Separate cherryview from valleyview
The cherryview device shares many characteristics with the valleyview
device. When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.
This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
Also add followup patches to fix issues discovered during the first
review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
as CRT is not supported on CHV. (Imre, Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_debugfs.c | 68 -
drivers/gpu/drm/i915/i915_dma.c | 8 ++--
drivers/gpu/drm/i915/i915_drv.c | 10 ++---
drivers/gpu/drm/i915/i915_drv.h | 16 +---
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
drivers/gpu/drm/i915/i915_suspend.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 10 ++---
drivers/gpu/drm/i915/intel_audio.c | 7 ++--
drivers/gpu/drm/i915/intel_display.c| 54 ++
drivers/gpu/drm/i915/intel_dp.c | 40 +--
drivers/gpu/drm/i915/intel_dsi.c| 14 +++
drivers/gpu/drm/i915/intel_dsi_pll.c| 6 +--
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_hotplug.c| 2 +-
drivers/gpu/drm/i915/intel_i2c.c| 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
drivers/gpu/drm/i915/intel_psr.c| 6 +--
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
22 files changed, 146 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..fff31253 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
- } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
- IS_BROADWELL(dev) || IS_GEN9(dev)) {
+ } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ u32 freq_sts;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+ seq_printf(m, "actual GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+ seq_printf(m, "current GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+ seq_printf(m, "max GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+ seq_printf(m, "min GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+ seq_printf(m, "idle GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+ seq_printf(m,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ } else if (INTEL_INFO(dev)->gen >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
- } else if (IS_VALLEYVIEW(dev)) {
- u32 freq_sts;
-
- mutex_lock(&dev_priv->rps.hw_lock);
- freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
[Intel-gfx] [PATCH 1/5] drm/i915: Separate cherryview from valleyview
The cherryview device shares many characteristics with the valleyview
device. When support was added to the driver for cherryview, the
corresponding device info structure included .is_valleyview = 1.
This is not correct and leads to some confusion.
This patch changes .is_valleyview to .is_cherryview in the cherryview
device info structure and simplifies the IS_CHERRYVIEW macro.
Then where appropriate, instances of IS_VALLEYVIEW are replaced with
IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent.
v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro.
Also add followup patches to fix issues discovered during the first
review. (Ville)
v3: Fix some style issues and one gen check. Remove CRT related changes
as CRT is not supported on CHV. (Imre, Ville)
v4: Make a few more optimizations. (Ville)
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_debugfs.c | 68 -
drivers/gpu/drm/i915/i915_dma.c | 11 ++
drivers/gpu/drm/i915/i915_drv.c | 10 ++---
drivers/gpu/drm/i915/i915_drv.h | 16 +---
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 8 ++--
drivers/gpu/drm/i915/i915_suspend.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 10 ++---
drivers/gpu/drm/i915/intel_audio.c | 7 ++--
drivers/gpu/drm/i915/intel_display.c| 54 ++
drivers/gpu/drm/i915/intel_dp.c | 40 +--
drivers/gpu/drm/i915/intel_dsi.c| 14 +++
drivers/gpu/drm/i915/intel_dsi_pll.c| 6 +--
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_hotplug.c| 2 +-
drivers/gpu/drm/i915/intel_i2c.c| 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
drivers/gpu/drm/i915/intel_psr.c| 6 +--
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
23 files changed, 147 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a8721fc..fff31253 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1142,8 +1142,34 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
MEMSTAT_VID_SHIFT);
seq_printf(m, "Current P-state: %d\n",
(rgvstat & MEMSTAT_PSTATE_MASK) >>
MEMSTAT_PSTATE_SHIFT);
- } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
- IS_BROADWELL(dev) || IS_GEN9(dev)) {
+ } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ u32 freq_sts;
+
+ mutex_lock(&dev_priv->rps.hw_lock);
+ freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
+
+ seq_printf(m, "actual GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
+
+ seq_printf(m, "current GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+
+ seq_printf(m, "max GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+
+ seq_printf(m, "min GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+
+ seq_printf(m, "idle GPU freq: %d MHz\n",
+ intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+
+ seq_printf(m,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
+ mutex_unlock(&dev_priv->rps.hw_lock);
+ } else if (INTEL_INFO(dev)->gen >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
u32 rp_state_cap;
@@ -1284,33 +1310,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv,
dev_priv->rps.efficient_freq));
- } else if (IS_VALLEYVIEW(dev)) {
- u32 freq_sts;
-
- mutex_lock(&dev_priv->rps.hw_lock);
- freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
-
[Intel-gfx] [PATCH] drm/i915: Pin the ifbdev for the info->system_base GGTT mmapping
From: Chris Wilson
A long time ago (before 3.14) we relied on a permanent pinning of the
ifbdev to lock the fb in place inside the GGTT. However, the
introduction of stealing the BIOS framebuffer and reusing its address in
the GGTT for the fbdev has muddied waters and we use an inherited fb.
However, the inherited fb is only pinned whilst it is active and we no
longer have an explicit pin for the info->system_base mmapping used by
the fbdev. The result is that after some aperture pressure the fbdev may
be evicted, but we continue to write the fbcon into the same GGTT
address - overwriting anything else that may be put into that offset.
The effect is most pronounced across suspend/resume as
intel_fbdev_set_suspend() does a full clear over the whole scanout.
v2: rebased on latest nightly (Wayne)
Signed-off-by: Chris Wilson
Cc: "Goel, Akash"
Cc: Daniel Vetter
Cc: Jesse Barnes
Cc: sta...@vger.kernel.org
Reviewed-by: Deepak S
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/intel_fbdev.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 6532912..c6aa4f9 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -215,6 +215,16 @@ static int intelfb_create(struct drm_fb_helper *helper,
obj = intel_fb->obj;
size = obj->base.size;
+ /* The fb constructor will have already pinned us (or inherited a
+* GGTT region from the BIOS) suitable for a scanout, so
+* this should just be a no-op and increment the pin count for the
+* fbdev mmapping. It does have a useful side-effect of validating
+* the pin for fbdev's use via a GGTT mmapping.
+*/
+ ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PIN_MAPPABLE);
+ if (ret)
+ goto out_unlock;
+
info = drm_fb_helper_alloc_fbi(helper);
if (IS_ERR(info)) {
ret = PTR_ERR(info);
@@ -274,6 +284,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
out_destroy_fbi:
drm_fb_helper_release_fbi(helper);
out_unpin:
+ /* Once for info->screen_base mmaping... */
+ i915_gem_object_ggtt_unpin(obj);
+ /* ...and once for the intel_fb */
i915_gem_object_ggtt_unpin(obj);
drm_gem_object_unreference(&obj->base);
out_unlock:
@@ -514,6 +527,8 @@ static const struct drm_fb_helper_funcs
intel_fb_helper_funcs = {
static void intel_fbdev_destroy(struct drm_device *dev,
struct intel_fbdev *ifbdev)
{
+ /* Release the pinning for the info->screen_base mmaping. */
+ i915_gem_object_ggtt_unpin(ifbdev->fb->obj);
drm_fb_helper_unregister_fbi(&ifbdev->helper);
drm_fb_helper_release_fbi(&ifbdev->helper);
--
1.9.1
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[Intel-gfx] [PATCH] drm/i915: Pin the ifbdev for the info->system_base GGTT mmapping
From: Chris Wilson
A long time ago (before 3.14) we relied on a permanent pinning of the
ifbdev to lock the fb in place inside the GGTT. However, the
introduction of stealing the BIOS framebuffer and reusing its address in
the GGTT for the fbdev has muddied waters and we use an inherited fb.
However, the inherited fb is only pinned whilst it is active and we no
longer have an explicit pin for the info->system_base mmapping used by
the fbdev. The result is that after some aperture pressure the fbdev may
be evicted, but we continue to write the fbcon into the same GGTT
address - overwriting anything else that may be put into that offset.
The effect is most pronounced across suspend/resume as
intel_fbdev_set_suspend() does a full clear over the whole scanout.
v2: rebased on latest nightly (Wayne)
v3: changed i915_gem_object_ggtt_pin() to i915_gem_obj_ggtt_pin() based
on Chris' review. (Wayne)
Signed-off-by: Chris Wilson
Cc: "Goel, Akash"
Cc: Daniel Vetter
Cc: Jesse Barnes
Cc: sta...@vger.kernel.org
Reviewed-by: Deepak S
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/intel_fbdev.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
b/drivers/gpu/drm/i915/intel_fbdev.c
index 6532912..0ad46521 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -215,6 +215,16 @@ static int intelfb_create(struct drm_fb_helper *helper,
obj = intel_fb->obj;
size = obj->base.size;
+ /* The fb constructor will have already pinned us (or inherited a
+* GGTT region from the BIOS) suitable for a scanout, so
+* this should just be a no-op and increment the pin count for the
+* fbdev mmapping. It does have a useful side-effect of validating
+* the pin for fbdev's use via a GGTT mmapping.
+*/
+ ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
+ if (ret)
+ goto out_unlock;
+
info = drm_fb_helper_alloc_fbi(helper);
if (IS_ERR(info)) {
ret = PTR_ERR(info);
@@ -274,6 +284,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
out_destroy_fbi:
drm_fb_helper_release_fbi(helper);
out_unpin:
+ /* Once for info->screen_base mmaping... */
+ i915_gem_object_ggtt_unpin(obj);
+ /* ...and once for the intel_fb */
i915_gem_object_ggtt_unpin(obj);
drm_gem_object_unreference(&obj->base);
out_unlock:
@@ -514,6 +527,8 @@ static const struct drm_fb_helper_funcs
intel_fb_helper_funcs = {
static void intel_fbdev_destroy(struct drm_device *dev,
struct intel_fbdev *ifbdev)
{
+ /* Release the pinning for the info->screen_base mmaping. */
+ i915_gem_object_ggtt_unpin(ifbdev->fb->obj);
drm_fb_helper_unregister_fbi(&ifbdev->helper);
drm_fb_helper_release_fbi(&ifbdev->helper);
--
1.9.1
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[Intel-gfx] [PATCH] drm/i915/skl: implement DP Aux Mutex framework
Beginning with SKL the DP Aux channel communication can be protected
using a built in H/W mutex.
This patch provides an initial implementation for using that mutex.
The use is currently limited to protecting the sink crc request based
on feedback from the H/W designers indicating that using the mutex
for all aux channel communication is not recommended.
Cc: Rodrigo Vivi
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5
drivers/gpu/drm/i915/intel_dp.c | 52 -
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b12594b..98e991d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2604,6 +2604,7 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
+#define HAS_AUX_MUTEX(dev) (INTEL_INFO(dev)->gen >= 9)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8942532..a033e70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4288,6 +4288,11 @@ enum skl_disp_power_wells {
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define DP_AUX_MUTEX_A 0x6402C
+#define DP_AUX_MUTEX_B 0x6412C
+#define DP_AUX_MUTEX_ENABLE (1 << 31)
+#define DP_AUX_MUTEX_STATUS (1 << 30)
+
/*
* Computing GMCH M and N values for the Display Port link
*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2fad873..e9e1239 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -781,6 +781,47 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
+static bool skl_aux_mutex(struct intel_dp *intel_dp, bool get)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t aux_ch_mutex, status;
+ int count = 0;
+
+ if (!HAS_AUX_MUTEX(dev))
+ return false;
+
+ /*
+* FIXME: determine actual aux channel
+* Hard coded to channel A for now to protect sink crc requests on eDP.
+*/
+ aux_ch_mutex = DP_AUX_MUTEX_A;
+
+ if (!get) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE |
DP_AUX_MUTEX_STATUS);
+ return false;
+ }
+
+ /*
+* The Bspec specifies waiting 500us between attempts to acquire the
+* mutex. Ten retries should be adequate to balance successfully
+* acquirng the mutex and spending too much time trying.
+*/
+ while (count++ < 10) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE);
+ status = I915_READ(aux_ch_mutex);
+ if (!(status & DP_AUX_MUTEX_STATUS))
+ return true;
+ udelay(500);
+ }
+
+ return false;
+}
+
+#define skl_aux_mutex_get(dev) skl_aux_mutex(dev, true)
+#define skl_aux_mutex_put(dev) skl_aux_mutex(dev, false)
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
@@ -4188,10 +4229,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8
*crc)
u8 buf;
int count, ret;
int attempts = 6;
+ bool aux_mutex_acquired = false;
+
+ aux_mutex_acquired = skl_aux_mutex_get(intel_dp);
ret = intel_dp_sink_crc_start(intel_dp);
+
if (ret)
- return ret;
+ goto release;
do {
intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -4218,6 +4263,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
stop:
intel_dp_sink_crc_stop(intel_dp);
+
+release:
+ if (aux_mutex_acquired)
+ aux_mutex_acquired = skl_aux_mutex_put(intel_dp);
+
return ret;
}
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/skl: implement DP Aux Mutex framework
Beginning with SKL the DP Aux channel communication can be protected
using a built in HW mutex.
When PSR is enablabled the HW takes control on AUX and uses it to
control panel exit/entry states.
When validating PSR with automated tests, grabbing CRC from sink
revealed strange aux communication issues. Aux reads were returning
a message read size equal to 0 and 0 is a forbidden message.
By using the HW mutex the HW is blocked from using aux when running
the automated PSR tests.
This patch provides an initial implementation for using that mutex.
The use is currently limited to protecting the sink crc request based
on feedback from the H/W designers indicating that using the mutex
for all aux channel communication is not recommended.
v2: Improved commit message to explain the case where the HW mutex is
helpful. Also added bug reference.
Signed-off-by: Wayne Boyer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91437
Reviewed-by: Rodrigo Vivi
Tested-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5
drivers/gpu/drm/i915/intel_dp.c | 52 -
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b12594b..98e991d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2604,6 +2604,7 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
+#define HAS_AUX_MUTEX(dev) (INTEL_INFO(dev)->gen >= 9)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8942532..a033e70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4288,6 +4288,11 @@ enum skl_disp_power_wells {
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define DP_AUX_MUTEX_A 0x6402C
+#define DP_AUX_MUTEX_B 0x6412C
+#define DP_AUX_MUTEX_ENABLE (1 << 31)
+#define DP_AUX_MUTEX_STATUS (1 << 30)
+
/*
* Computing GMCH M and N values for the Display Port link
*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2fad873..e9e1239 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -781,6 +781,47 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
+static bool skl_aux_mutex(struct intel_dp *intel_dp, bool get)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t aux_ch_mutex, status;
+ int count = 0;
+
+ if (!HAS_AUX_MUTEX(dev))
+ return false;
+
+ /*
+* FIXME: determine actual aux channel
+* Hard coded to channel A for now to protect sink crc requests on eDP.
+*/
+ aux_ch_mutex = DP_AUX_MUTEX_A;
+
+ if (!get) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE |
DP_AUX_MUTEX_STATUS);
+ return false;
+ }
+
+ /*
+* The Bspec specifies waiting 500us between attempts to acquire the
+* mutex. Ten retries should be adequate to balance successfully
+* acquirng the mutex and spending too much time trying.
+*/
+ while (count++ < 10) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE);
+ status = I915_READ(aux_ch_mutex);
+ if (!(status & DP_AUX_MUTEX_STATUS))
+ return true;
+ udelay(500);
+ }
+
+ return false;
+}
+
+#define skl_aux_mutex_get(dev) skl_aux_mutex(dev, true)
+#define skl_aux_mutex_put(dev) skl_aux_mutex(dev, false)
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
@@ -4188,10 +4229,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8
*crc)
u8 buf;
int count, ret;
int attempts = 6;
+ bool aux_mutex_acquired = false;
+
+ aux_mutex_acquired = skl_aux_mutex_get(intel_dp);
ret = intel_dp_sink_crc_start(intel_dp);
+
if (ret)
- return ret;
+ goto release;
do {
intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -4218,6 +4263,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
stop:
intel_dp_sink_crc_stop(intel_dp);
+
+release:
+ if (aux_mute
[Intel-gfx] [PATCH] drm/i915/skl: Implement DP Aux Mutex framework
From: "Boyer, Wayne"
Beginning with SKL the DP Aux channel communication can be protected
using a built in HW mutex.
When PSR is enabled the HW takes control on AUX and uses it to
control panel exit/entry states.
When validating PSR with automated tests, grabbing CRC from sink
revealed strange aux communication issues. Aux reads were returning
a message read size equal to 0 and 0 is a forbidden message.
By using the HW mutex the HW is blocked from using aux when running
the automated PSR tests.
This patch provides an initial implementation for using that mutex.
The use is currently limited to protecting the sink crc request based
on feedback from the H/W designers indicating that using the mutex
for all aux channel communication is not recommended.
v2: Improved commit message to explain the case where the HW mutex is
helpful. Also added bug reference.
v3: Fix typos in commit message.
Signed-off-by: Wayne Boyer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91437
Reviewed-by: Rodrigo Vivi
Tested-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 5
drivers/gpu/drm/i915/intel_dp.c | 52 -
3 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5cf30b..ac7ed0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2585,6 +2585,7 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev)(INTEL_INFO(dev)->has_fpga_dbg)
+#define HAS_AUX_MUTEX(dev) (INTEL_INFO(dev)->gen >= 9)
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd2699..f9ee874 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4288,6 +4288,11 @@ enum skl_disp_power_wells {
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
+#define DP_AUX_MUTEX_A 0x6402C
+#define DP_AUX_MUTEX_B 0x6412C
+#define DP_AUX_MUTEX_ENABLE (1 << 31)
+#define DP_AUX_MUTEX_STATUS (1 << 30)
+
/*
* Computing GMCH M and N values for the Display Port link
*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da02ed7..b3c7d82 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -781,6 +781,47 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp
*intel_dp,
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}
+static bool skl_aux_mutex(struct intel_dp *intel_dp, bool get)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t aux_ch_mutex, status;
+ int count = 0;
+
+ if (!HAS_AUX_MUTEX(dev))
+ return false;
+
+ /*
+* FIXME: determine actual aux channel
+* Hard coded to channel A for now to protect sink crc requests on eDP.
+*/
+ aux_ch_mutex = DP_AUX_MUTEX_A;
+
+ if (!get) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE |
DP_AUX_MUTEX_STATUS);
+ return false;
+ }
+
+ /*
+* The Bspec specifies waiting 500us between attempts to acquire the
+* mutex. Ten retries should be adequate to balance successfully
+* acquirng the mutex and spending too much time trying.
+*/
+ while (count++ < 10) {
+ I915_WRITE(aux_ch_mutex, DP_AUX_MUTEX_ENABLE);
+ status = I915_READ(aux_ch_mutex);
+ if (!(status & DP_AUX_MUTEX_STATUS))
+ return true;
+ udelay(500);
+ }
+
+ return false;
+}
+
+#define skl_aux_mutex_get(dev) skl_aux_mutex(dev, true)
+#define skl_aux_mutex_put(dev) skl_aux_mutex(dev, false)
+
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
const uint8_t *send, int send_bytes,
@@ -3927,10 +3968,14 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8
*crc)
u8 buf;
int count, ret;
int attempts = 6;
+ bool aux_mutex_acquired = false;
+
+ aux_mutex_acquired = skl_aux_mutex_get(intel_dp);
ret = intel_dp_sink_crc_start(intel_dp);
+
if (ret)
- return ret;
+ goto release;
do {
intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -3957,6 +4002,11 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
stop:
[Intel-gfx] [PATCH 2/2] lib/kbl: Add Kabylake GT4 PCI IDs
Add the Kabylake GT4 PCI IDs as defined in this kernel patch. commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d Author: Deepak S Date: Wed Oct 28 12:21:12 2015 -0700 drm/i915/kbl: Add Kabylake GT4 PCI ID Signed-off-by: Wayne Boyer --- lib/intel_chipset.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index f9fcdd6..19fa02f 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -217,13 +217,17 @@ void intel_check_pch(void); #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 +#define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B #define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B #define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B +#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A #define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A +#define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 @@ -430,9 +434,15 @@ void intel_check_pch(void); (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) +#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \ +(devid) == PCI_CHIP_KABYLAKE_WKS_GT4) + #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ IS_KBL_GT2(devid) || \ -IS_KBL_GT3(devid)) +IS_KBL_GT3(devid) || \ +IS_KBL_GT4(devid)) #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] lib/kbl: move KBL check from IS_SKYLAKE() to IS_GEN9()
Remove the KBL check from IS_SKYLAKE() following the kernel definition. Then, add the KBL check to IS_GEN9(). The idea is to avoid confusion. On the kernel side, the mix of SKY and KBL was nacked so the platforms are split. Signed-off-by: Wayne Boyer --- lib/intel_chipset.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index 6fcc244..f9fcdd6 100644 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -434,8 +434,7 @@ void intel_check_pch(void); IS_KBL_GT2(devid) || \ IS_KBL_GT3(devid)) -#define IS_SKYLAKE(devid) (IS_KABYLAKE(devid) || \ -IS_SKL_GT1(devid) || \ +#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ IS_SKL_GT2(devid) || \ IS_SKL_GT3(devid)) @@ -443,7 +442,9 @@ void intel_check_pch(void); (devid) == PCI_CHIP_BROXTON_1 || \ (devid) == PCI_CHIP_BROXTON_2) -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid)) +#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \ +IS_SKYLAKE(devid) || \ +IS_BROXTON(devid)) #define IS_965(devid) (IS_GEN4(devid) || \ IS_GEN5(devid) || \ -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't warn if the workaround list is empty part 2.
Extend the same reasoning as in the patch listed below. It's not an error for the workaround list to be empty if no workarounds are needed. commit 02235808b61cd9382d224b0df263193006dd9913 Author: Francisco Jerez Date: Wed Oct 7 14:44:01 2015 +0300 drm/i915: Don't warn if the workaround list is empty. Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer --- drivers/gpu/drm/i915/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 06180dc..b46e6af 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1082,7 +1082,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) struct drm_i915_private *dev_priv = dev->dev_private; struct i915_workarounds *w = &dev_priv->workarounds; - if (WARN_ON_ONCE(w->count == 0)) + if (w->count == 0) return 0; ring->gpu_caches_dirty = true; -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Add Kabylake PCI IDs
Add the Kabylake PCI IDs based on the following patches.
commit d97044b661d0d56b2a2ae9b2b95ab0b359b417dc
Author: Deepak S
Date: Wed Oct 28 12:19:51 2015 -0700
drm/i915/kbl: Add Kabylake PCI ID
commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d
Author: Deepak S
Date: Wed Oct 28 12:21:12 2015 -0700
drm/i915/kbl: Add Kabylake GT4 PCI ID
Cc: Rodrigo Vivi
Cc: Chris Wilson
Signed-off-by: Wayne Boyer
---
src/i915_pciids.h | 36
src/intel_module.c | 6 ++
2 files changed, 42 insertions(+)
diff --git a/src/i915_pciids.h b/src/i915_pciids.h
index 17c4456..6374f58 100644
--- a/src/i915_pciids.h
+++ b/src/i915_pciids.h
@@ -291,4 +291,40 @@
INTEL_VGA_DEVICE(0x1A84, info), \
INTEL_VGA_DEVICE(0x5A84, info)
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* HALO GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* HALO GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x592B, info), /* HALO GT3 */ \
+ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x593B, info), /* HALO GT4 */ \
+ INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
+ INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
+
+#define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info)
+
#endif /* _I915_PCIIDS_H */
diff --git a/src/intel_module.c b/src/intel_module.c
index d3dca83..60835b9 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -130,6 +130,10 @@ static const struct intel_device_info intel_broxton_info =
{
.gen = 0111,
};
+static const struct intel_device_info intel_kabylake_info = {
+ .gen = 0112,
+};
+
static const SymTabRec intel_chipsets[] = {
{PCI_CHIP_I810, "i810"},
{PCI_CHIP_I810_DC100, "i810-dc100"},
@@ -329,6 +333,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_BXT_IDS(&intel_broxton_info),
+ INTEL_KBL_IDS(&intel_kabylake_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
#endif
--
2.6.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Document and future-proof preemption control policy
On 9/7/22 2:24 PM, Matt Roper wrote:
Intel hardware allows some preemption settings to be controlled either
by the kernel-mode driver exclusively, or placed under control of the
user-mode drivers; on Linux we always select the userspace control
option. The various registers involved in this are not documented very
clearly; let's add some clarifying comments to help explain how this all
works and provide some history on why our Linux drivers take the
approach they do (which I believe differs from the path taken by certain
other operating systems' drivers).
While we're at it, let's also remove the graphics version 12 upper bound
on this programming. As described, we don't have any plans to move away
from UMD control of preemption settings on future platforms, and there's
currently no reason to believe that the hardware will fundamentally
change how these registers and settings work after version 12.
Bspec: 45921, 45858, 45863
Cc: Joonas Lahtinen
Cc: Jordan Justen
Cc: Lionel Landwerlin
Suggested-by: Joonas Lahtinen
Signed-off-by: Matt Roper
Reviewed-by: Wayne Boyer
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++--
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..3e5a41378e81 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2389,12 +2389,64 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_GRAPHICS_VER(i915, 9, 12)) {
- /*
FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
+ /*
+* Intel platforms that support fine-grained preemption (i.e., gen9 and
+* beyond) allow the kernel-mode driver to choose between two different
+* options for controlling preemption granularity and behavior.
+*
+* Option 1 (hardware default):
+* Preemption settings are controlled in a global manner via
+* kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity
+* and settings chosen by the kernel-mode driver will apply to all
+* userspace clients.
+*
+* Option 2:
+* Preemption settings are controlled on a per-context basis via
+* register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on
+* context switch and is writable by userspace (e.g., via
+* MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
+* which allows different userspace drivers/clients to select
+* different settings, or to change those settings on the fly in
+* response to runtime needs. This option was known by name
+* "FtrPerCtxtPreemptionGranularityControl" at one time, although
+* that name is somewhat misleading as other non-granularity
+* preemption settings are also impacted by this decision.
+*
+* On Linux, our policy has always been to let userspace drivers
+* control preemption granularity/settings (Option 2). This was
+* originally mandatory on gen9 to prevent ABI breakage (old gen9
+* userspace developed before object-level preemption was enabled would
+* not behave well if i915 were to go with Option 1 and enable that
+* preemption in a global manner). On gen9 each context would have
+* object-level preemption disabled by default (see
+* WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
+* userspace drivers could opt-in to object-level preemption as they
+* saw fit. For post-gen9 platforms, we continue to utilize Option 2;
+* even though it is no longer necessary for ABI compatibility when
+* enabling a new platform, it does ensure that userspace will be able
+* to implement any workarounds that show up requiring temporary
+* adjustments to preemption behavior at runtime.
+*
+* Notes/Workarounds:
+* - Wa_14015141709: On DG2 and early steppings of MTL,
+* CS_CHICKEN1[0] does not disable object-level preemption as
+* it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
+* using Option 1). Effectively this means userspace is unable
+* to disable object-level preemption on these platforms/steppings
+* despite the setting here.
+*
+* - Wa_16013994831: May require that userspace program
+* CS_CHICKEN1[10] when certain runtime conditions are true.
+* Userspace requires Option 2 to be in effect for their update of
+* CS_CHICKEN1[10] to be effective.
+*
+* Other workarounds may appear in the future that will also require
+
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Add missing mask when reading GEN12_DSMBASE
On 9/16/22 10:36 AM, Lucas De Marchi wrote:
DSMBASE register is defined so BDSM bitfield contains the bits 63 to 20
of the base address of stolen. For the supported platforms bits 0-19 are
zero but that may not be true in future. Add the missing mask.
v2: Use REG_GENMASK64()
Acked-by: Aravind Iddamsetty
Reviewed-by: Caz Yokoyama
Signed-off-by: Lucas De Marchi
Reviewed-by: Wayne Boyer
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index acc561c0f0aa..3665f9b035bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -814,7 +814,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
return ERR_PTR(-ENXIO);
/* Use DSM base address instead for stolen memory */
- dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
+ dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
if (IS_DG1(uncore->i915)) {
lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
if (WARN_ON(lmem_size < dsm_base))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a9bd829fc7e..9584a50ed612 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7953,6 +7953,7 @@ enum skl_power_gate {
#define GEN12_GSMBASE _MMIO(0x108100)
#define GEN12_DSMBASE _MMIO(0x1080C0)
+#define GEN12_BDSM_MASK REG_GENMASK64(63, 20)
#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
#define SGSI_SIDECLK_DISREG_BIT(17)
--
--
Wayne Boyer
Graphics Software Engineer
VTT-OSGC Platform Enablement
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Split i915_gem_init_stolen()
On 9/16/22 10:36 AM, Lucas De Marchi wrote:
Add some helpers: adjust_stolen(), request_smem_stolen_() and
init_reserved_stolen() that are now called by i915_gem_init_stolen() to
initialize each part of the Data Stolen Memory region.
Main goal is to split the reserved part within the stolen, also known as
WOPCM, as its calculation changes often per platform and is a big source
of confusion when handling stolen memory.
Signed-off-by: Lucas De Marchi
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 3665f9b035bb..6edf4e374f54 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -77,22 +77,26 @@ void i915_gem_stolen_remove_node(struct drm_i915_private
*i915,
mutex_unlock(&i915->mm.stolen_lock);
}
-static int i915_adjust_stolen(struct drm_i915_private *i915,
- struct resource *dsm)
+static bool valid_stolen_size(struct resource *dsm)
+{
+ return dsm->start != 0 && dsm->end > dsm->start;
+}
+
+static int adjust_stolen(struct drm_i915_private *i915,
+struct resource *dsm)
{
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
struct intel_uncore *uncore = ggtt->vm.gt->uncore;
- struct resource *r;
- if (dsm->start == 0 || dsm->end <= dsm->start)
+ if (!valid_stolen_size(dsm))
return -EINVAL;
/*
+* Make sure we don't clobber the GTT if it's within stolen memory
+*
* TODO: We have yet too encounter the case where the GTT wasn't at the
nit: as long as you're updating this comment block, s/too/to/
Otherwise,
Reviewed-by: Wayne Boyer
* end of stolen. With that assumption we could simplify this.
*/
-
- /* Make sure we don't clobber the GTT if it's within stolen memory */
if (GRAPHICS_VER(i915) <= 4 &&
!IS_G33(i915) && !IS_PINEVIEW(i915) && !IS_G4X(i915)) {
struct resource stolen[2] = {*dsm, *dsm};
@@ -131,10 +135,20 @@ static int i915_adjust_stolen(struct drm_i915_private
*i915,
}
}
+ if (!valid_stolen_size(dsm))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int request_smem_stolen(struct drm_i915_private *i915,
+ struct resource *dsm)
+{
+ struct resource *r;
+
/*
-* With stolen lmem, we don't need to check if the address range
-* overlaps with the non-stolen system memory range, since lmem is local
-* to the gpu.
+* With stolen lmem, we don't need to request system memory for the
+* address range since it's local to the gpu.
*/
if (HAS_LMEM(i915))
return 0;
@@ -392,39 +406,22 @@ static void icl_get_stolen_reserved(struct
drm_i915_private *i915,
}
}
-static int i915_gem_init_stolen(struct intel_memory_region *mem)
+/*
+ * Initialize i915->dsm_reserved to contain the reserved space within the Data
+ * Stolen Memory. This is a range on the top of DSM that is reserved, not to
+ * be used by driver, so must be excluded from the region passed to the
+ * allocator later. In the spec this is also called as WOPCM.
+ *
+ * Our expectation is that the reserved space is at the top of the stolen
+ * region, as it has been the case for every platform, and *never* at the
+ * bottom, so the calculation here can be simplified.
+ */
+static int init_reserved_stolen(struct drm_i915_private *i915)
{
- struct drm_i915_private *i915 = mem->i915;
struct intel_uncore *uncore = &i915->uncore;
resource_size_t reserved_base, stolen_top;
- resource_size_t reserved_total, reserved_size;
-
- mutex_init(&i915->mm.stolen_lock);
-
- if (intel_vgpu_active(i915)) {
- drm_notice(&i915->drm,
- "%s, disabling use of stolen memory\n",
- "iGVT-g active");
- return 0;
- }
-
- if (i915_vtd_active(i915) && GRAPHICS_VER(i915) < 8) {
- drm_notice(&i915->drm,
- "%s, disabling use of stolen memory\n",
- "DMAR active");
- return 0;
- }
-
- if (resource_size(&mem->region) == 0)
- return 0;
-
- i915->dsm = mem->region;
-
- if (i915_adjust_stolen(i915, &i915->dsm))
- return 0;
-
- GEM_BUG_ON(i915->dsm.start == 0);
- GEM_BUG_ON(i915->dsm.end <= i915->dsm.start);
+ resource_size_t reserved_size;
+ int ret = 0;
stolen_top = i915->dsm.end + 1;
reserved_base = stolen_top;
@@ -455,17 +452,16 @@ static int i915_gem_init_stolen(struct
int
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/dgfx: Make failure to setup stolen non-fatal
On 9/16/22 10:36 AM, Lucas De Marchi wrote:
There is no reason to consider the setup of Data Stolen Memory fatal on
dgfx and non-fatal on integrated. Move the debug and error propagation
around so both have the same behavior: non-fatal. Before this change,
loading i915 on a system with TGL + DG2 would result in just TGL
succeeding the initialization (without stolen).
Now loading i915 on the same system with an injected failure in
i915_gem_init_stolen():
$ dmesg | grep stolen
i915 :00:02.0: [drm] Injected failure, disabling use of stolen
memory
i915 :00:02.0: [drm:init_stolen_smem [i915]] Skip stolen region:
failed to setup
i915 :03:00.0: [drm] Injected failure, disabling use of stolen
memory
i915 :03:00.0: [drm:init_stolen_lmem [i915]] Skip stolen region:
failed to setup
Both GPUs are still available:
$ sudo build/tools/lsgpu
card1Intel Dg2 (Gen12)
drm:/dev/dri/card1
└─renderD129
drm:/dev/dri/renderD129
card0Intel Tigerlake (Gen12)
drm:/dev/dri/card0
└─renderD128
drm:/dev/dri/renderD128
Signed-off-by: Lucas De Marchi
Reviewed-by: Wayne Boyer
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 6edf4e374f54..c5a4035c99cd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -494,26 +494,26 @@ static int i915_gem_init_stolen(struct
intel_memory_region *mem)
drm_notice(&i915->drm,
"%s, disabling use of stolen memory\n",
"iGVT-g active");
- return 0;
+ return -ENOSPC;
}
if (i915_vtd_active(i915) && GRAPHICS_VER(i915) < 8) {
drm_notice(&i915->drm,
"%s, disabling use of stolen memory\n",
"DMAR active");
- return 0;
+ return -ENOSPC;
}
if (adjust_stolen(i915, &mem->region))
- return 0;
+ return -ENOSPC;
if (request_smem_stolen(i915, &mem->region))
- return 0;
+ return -ENOSPC;
i915->dsm = mem->region;
if (init_reserved_stolen(i915))
- return 0;
+ return -ENOSPC;
/* Exclude the reserved region from driver use */
mem->region.end = i915->dsm_reserved.start - 1;
@@ -527,7 +527,7 @@ static int i915_gem_init_stolen(struct intel_memory_region
*mem)
(u64)i915->stolen_usable_size >> 10);
if (i915->stolen_usable_size == 0)
- return 0;
+ return -ENOSPC;
/* Basic memrange allocator for stolen space. */
drm_mm_init(&i915->mm.stolen, 0, i915->stolen_usable_size);
@@ -765,11 +765,17 @@ i915_gem_object_create_stolen(struct drm_i915_private
*i915,
static int init_stolen_smem(struct intel_memory_region *mem)
{
+ int err;
+
/*
* Initialise stolen early so that we may reserve preallocated
* objects for the BIOS to KMS transition.
*/
- return i915_gem_init_stolen(mem);
+ err = i915_gem_init_stolen(mem);
+ if (err)
+ drm_dbg(&mem->i915->drm, "Skip stolen region: failed to
setup\n");
+
+ return 0;
}
static int release_stolen_smem(struct intel_memory_region *mem)
@@ -786,21 +792,25 @@ static const struct intel_memory_region_ops
i915_region_stolen_smem_ops = {
static int init_stolen_lmem(struct intel_memory_region *mem)
{
+ struct drm_i915_private *i915 = mem->i915;
int err;
if (GEM_WARN_ON(resource_size(&mem->region) == 0))
- return -ENODEV;
+ return 0;
err = i915_gem_init_stolen(mem);
- if (err)
- return err;
+ if (err) {
+ drm_dbg(&mem->i915->drm, "Skip stolen region: failed to
setup\n");
+ return 0;
+ }
- if (mem->io_size && !io_mapping_init_wc(&mem->iomap,
- mem->io_start,
- mem->io_size)) {
- err = -EIO;
+ if (mem->io_size &&
+ !io_mapping_init_wc(&mem->iomap, mem->io_start, mem->io_size))
goto err_cleanup;
- }
+
+ drm_dbg(&i915->drm, "Stolen Local memory IO start: %pa\n",
+ &mem->io_start);
+ drm_dbg(&i915->drm, "Stolen Local DSM base: %pa\n", &mem->region.start);
return 0;
@@ -874,16 +884,6
[Intel-gfx] [linux-gfx] [PATCH] drm/i915/pvc: Implement recommended caching policy
As per the performance tuning guide, set the HOSTCACHEEN bit to
implement the recommended caching policy on PVC.
Signed-off-by: Wayne Boyer
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 784152548472..f96570995cfc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -973,6 +973,7 @@
#define GEN7_L3AGDIS (1 << 19)
#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c)
+#define XEHPC_HOSTCACHEENREG_BIT(1)
#define XEHPC_OVRLSCCC REG_BIT(0)
#define GEN7_L3CNTLREG2_MMIO(0xb020)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b0e40e68a9d..35e3f43e8b06 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2903,6 +2903,7 @@ add_render_compute_tuning_settings(struct
drm_i915_private *i915,
if (IS_PONTEVECCHIO(i915)) {
wa_write(wal, XEHPC_L3SCRUB,
SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
+ wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
}
if (IS_DG2(i915)) {
--
2.37.3
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Implement recommended caching policy
gt; (i915#5461 <https://gitlab.freedesktop.org/drm/intel/issues/5461>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-rkl-6/igt@kms_psr_stress_t...@invalidate-primary-flip-overlay.html>
> *
>
> igt@perf@blocking:
>
> o shard-skl: FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-skl6/igt@p...@blocking.html>
> (i915#1542 <https://gitlab.freedesktop.org/drm/intel/issues/1542>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-skl6/igt@p...@blocking.html>
> *
>
> igt@perf@mi-rpc:
>
> o {shard-rkl}: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-rkl-6/igt@p...@mi-rpc.html>
> (i915#2434 <https://gitlab.freedesktop.org/drm/intel/issues/2434>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-rkl-5/igt@p...@mi-rpc.html>
> *
>
> igt@perf_pmu@enable-race@rcs0:
>
> o shard-tglb: INCOMPLETE
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-tglb7/igt@perf_pmu@enable-r...@rcs0.html>
> (i915#6453 <https://gitlab.freedesktop.org/drm/intel/issues/6453>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-tglb6/igt@perf_pmu@enable-r...@rcs0.html>
> *
>
> igt@prime_vgem@coherency-gtt:
>
> o {shard-rkl}: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-rkl-4/igt@prime_v...@coherency-gtt.html>
> (fdo#109295 <https://bugs.freedesktop.org/show_bug.cgi?id=109295> /
> fdo#111656 <https://bugs.freedesktop.org/show_bug.cgi?id=111656> / i915#3708
> <https://gitlab.freedesktop.org/drm/intel/issues/3708>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-rkl-5/igt@prime_v...@coherency-gtt.html>
> *
>
> igt@sysfs_heartbeat_interval@precise@rcs0:
>
> o {shard-dg1}: FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-dg1-15/igt@sysfs_heartbeat_interval@prec...@rcs0.html>
> (i915#1755 <https://gitlab.freedesktop.org/drm/intel/issues/1755>) -> PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-dg1-19/igt@sysfs_heartbeat_interval@prec...@rcs0.html>
> +1 similar issue
>
>
> Warnings
>
> *
>
> igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-iclb2/igt@kms_psr2...@overlay-plane-move-continuous-exceed-fully-sf.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-iclb1/igt@kms_psr2...@overlay-plane-move-continuous-exceed-fully-sf.html>
> (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>)
> *
>
> igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-iclb2/igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-iclb7/igt@kms_psr2...@overlay-primary-update-sf-dmg-area.html>
> (fdo#111068 <https://bugs.freedesktop.org/show_bug.cgi?id=111068> / i915#658
> <https://gitlab.freedesktop.org/drm/intel/issues/658>)
> *
>
> igt@kms_psr2_sf@plane-move-sf-dmg-area:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-iclb1/igt@kms_psr2...@plane-move-sf-dmg-area.html>
> (fdo#111068 <https://bugs.freedesktop.org/show_bug.cgi?id=111068> / i915#658
> <https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-iclb2/igt@kms_psr2...@plane-move-sf-dmg-area.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>)
> *
>
> igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-iclb1/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html>
> (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>)
> *
>
> igt@runner@aborted:
>
> o shard-apl: (FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-apl2/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-apl3/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-apl1/igt@run...@aborted.html>)
> (fdo#109271 <https://bugs.freedesktop.org/show_bug.cgi?id=109271> /
> i915#3002 <https://gitlab.freedesktop.org/drm/intel/issues/3002> / i915#4312
> <https://gitlab.freedesktop.org/drm/intel/issues/4312>) -> (FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-apl8/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-apl6/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-apl6/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-apl1/igt@run...@aborted.html>)
> (fdo#109271 <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#180
> <https://gitlab.freedesktop.org/drm/intel/issues/180> / i915#3002
> <https://gitlab.freedesktop.org/drm/intel/issues/3002> / i915#4312
> <https://gitlab.freedesktop.org/drm/intel/issues/4312>)
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
>
> Build changes
>
> * Linux: CI_DRM_12456 -> Patchwork_111491v1
>
> CI-20190529: 20190529
> CI_DRM_12456: 7a3c5315507ed0f4a9b0aa07ce6df1b3d28ebc35 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7076: 888725538e0d6bbb941ac278d4afcbbbdad0 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_111491v1: 7a3c5315507ed0f4a9b0aa07ce6df1b3d28ebc35 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
--
Wayne Boyer
Graphics Software Engineer
AXG SCSS Platform Enablement
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/pvc: Implement recommended caching policy
+ Sai Nandan as Lakshmi is out of the office. On 12/1/22 7:13 AM, Wayne Boyer wrote: > The failures below appear to be unrelated to my change which is > restricted to PVC. > > On 12/1/22 12:59 AM, Patchwork wrote: >> *Patch Details* >> *Series:*drm/i915/pvc: Implement recommended caching policy >> *URL:* https://patchwork.freedesktop.org/series/111491/ >> <https://patchwork.freedesktop.org/series/111491/> >> *State:* failure >> *Details:* >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/index.html >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/index.html> >> >> >> CI Bug Log - changes from CI_DRM_12456_full -> Patchwork_111491v1_full >> >> >> Summary >> >> *FAILURE* >> >> Serious unknown changes coming with Patchwork_111491v1_full absolutely >> need to be >> verified manually. >> >> If you think the reported changes have nothing to do with the changes >> introduced in Patchwork_111491v1_full, please notify your bug team to >> allow them >> to document this new failure mode, which will reduce false positives in CI. >> >> >> Participating hosts (11 -> 11) >> >> No changes in participating hosts >> >> >> Possible new issues >> >> Here are the unknown changes that may have been introduced in >> Patchwork_111491v1_full: >> >> >> IGT changes >> >> >> Possible regressions >> >> * >> >> igt@gem_exec_fence@syncobj-invalid-wait: >> >> o shard-skl: PASS >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-skl4/igt@gem_exec_fe...@syncobj-invalid-wait.html> >> -> WARN >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-skl4/igt@gem_exec_fe...@syncobj-invalid-wait.html> >> * >> >> igt@kms_atomic_interruptible@legacy-setmode@edp-1-pipe-a: >> >> o shard-tglb: PASS >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-tglb7/igt@kms_atomic_interruptible@legacy-setm...@edp-1-pipe-a.html> >> -> INCOMPLETE >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-tglb3/igt@kms_atomic_interruptible@legacy-setm...@edp-1-pipe-a.html> >> >> >> Known issues >> >> Here are the changes found in Patchwork_111491v1_full that come from >> known issues: >> >> >> IGT changes >> >> >> Issues hit >> >> * >> >> igt@gem_ctx_param@set-priority-not-supported: >> >> o shard-tglb: NOTRUN -> SKIP >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-tglb6/igt@gem_ctx_pa...@set-priority-not-supported.html> >> (fdo#109314 <https://bugs.freedesktop.org/show_bug.cgi?id=109314>) >> * >> >> igt@gem_exec_fair@basic-none-solo@rcs0: >> >> o shard-apl: PASS >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html> >> -> FAIL >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-apl6/igt@gem_exec_fair@basic-none-s...@rcs0.html> >> (i915#2842 <https://gitlab.freedesktop.org/drm/intel/issues/2842>) >> * >> >> igt@gem_exec_fair@basic-pace@vcs0: >> >> o shard-iclb: PASS >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12456/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html> >> -> FAIL >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-iclb7/igt@gem_exec_fair@basic-p...@vcs0.html> >> (i915#2842 <https://gitlab.freedesktop.org/drm/intel/issues/2842>) >> * >> >> igt@gem_lmem_swapping@heavy-verify-random-ccs: >> >> o shard-tglb: NOTRUN -> SKIP >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-tglb6/igt@gem_lmem_swapp...@heavy-verify-random-ccs.html> >> (i915#4613 <https://gitlab.freedesktop.org/drm/intel/issues/4613>) +1 >> similar issue >> * >> >> igt@gen3_render_mixed_blits: >> >> o shard-tglb: NOTRUN -> SKIP >> >> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111491v1/shard-tglb6/igt@gen3_render_mixed_blits.html> >> (fdo#109289 <https://bugs.freedesktop.org/show_bug.cgi?id=109289>) >> * >> >> igt@gen9_exec_parse@bb-oversize: >> >
[Intel-gfx] [PATCH] drm/i915/dg2: Introduce Wa_18017747507
WA 18017747507 applies to all DG2 skus. BSpec: 56035, 46121, 68173 Signed-off-by: Wayne Boyer --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index f4624262dc81..27b2641e1a53 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -501,6 +501,9 @@ #define VF_PREEMPTION _MMIO(0x83a4) #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) +#define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) +#define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) + #define GEN8_RC6_CTX_INFO _MMIO(0x8504) #define XEHP_SQCM MCR_REG(0x8724) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2a35e7e66625..3cdf5c24dbc5 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2975,6 +2975,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } } -- 2.37.3
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Introduce Wa_18017747507
p.org/drm/intel/issues/2658>) ->
> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-tglb6/igt@gem_pr...@exhaustion.html>
> (i915#7248 <https://gitlab.freedesktop.org/drm/intel/issues/7248>)
>
> o
>
> shard-glk: INCOMPLETE
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-glk3/igt@gem_pr...@exhaustion.html>
> (i915#7248 <https://gitlab.freedesktop.org/drm/intel/issues/7248>) -> WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-glk9/igt@gem_pr...@exhaustion.html>
> (i915#2658 <https://gitlab.freedesktop.org/drm/intel/issues/2658>)
>
> *
>
> igt@gem_pwrite@basic-exhaustion:
>
> o shard-tglb: INCOMPLETE
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-tglb7/igt@gem_pwr...@basic-exhaustion.html>
> (i915#7248 <https://gitlab.freedesktop.org/drm/intel/issues/7248>) -> WARN
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-tglb2/igt@gem_pwr...@basic-exhaustion.html>
> (i915#2658 <https://gitlab.freedesktop.org/drm/intel/issues/2658>)
> *
>
> igt@i915_pm_dc@dc3co-vpb-simulation:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb5/igt@i915_pm...@dc3co-vpb-simulation.html>
> (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-iclb2/igt@i915_pm...@dc3co-vpb-simulation.html>
> (i915#588 <https://gitlab.freedesktop.org/drm/intel/issues/588>)
> *
>
> igt@kms_flip@flip-vs-expired-vblank@c-edp1:
>
> o shard-skl: FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html>
> (i915#79 <https://gitlab.freedesktop.org/drm/intel/issues/79>) -> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-skl10/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html>
> (i915#2122 <https://gitlab.freedesktop.org/drm/intel/issues/2122>)
> *
>
> igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb2/igt@kms_psr2...@cursor-plane-move-continuous-sf.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-iclb3/igt@kms_psr2...@cursor-plane-move-continuous-sf.html>
> (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>)
> *
>
> igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
>
> o shard-iclb: SKIP
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-iclb1/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html>
> (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-iclb2/igt@kms_psr2...@primary-plane-update-sf-dmg-area-big-fb.html>
> (i915#2920 <https://gitlab.freedesktop.org/drm/intel/issues/2920>)
> *
>
> igt@runner@aborted:
>
> o
>
> shard-apl: (FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl6/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl6/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl2/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-apl7/igt@run...@aborted.html>)
> (fdo#109271 <https://bugs.freedesktop.org/show_bug.cgi?id=109271> /
> i915#3002 <https://gitlab.freedesktop.org/drm/intel/issues/3002> / i915#4312
> <https://gitlab.freedesktop.org/drm/intel/issues/4312>) -> (FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-apl8/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-apl2/igt@run...@aborted.html>)
> (i915#3002 <https://gitlab.freedesktop.org/drm/intel/issues/3002> /
> i915#4312 <https://gitlab.freedesktop.org/drm/intel/issues/4312>)
>
> o
>
> shard-skl: (FAIL
>
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl10/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12325/shard-skl4/igt@run...@aborted.html>)
> (i915#3002 <https://gitlab.freedesktop.org/drm/intel/issues/3002> /
> i915#4312 <https://gitlab.freedesktop.org/drm/intel/issues/4312>) -> (FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-skl3/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-skl10/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-skl9/igt@run...@aborted.html>,
> FAIL
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110323v1/shard-skl5/igt@run...@aborted.html>)
> (i915#3002 <https://gitlab.freedesktop.org/drm/intel/issues/3002> /
> i915#4312 <https://gitlab.freedesktop.org/drm/intel/issues/4312> / i915#6949
> <https://gitlab.freedesktop.org/drm/intel/issues/6949>)
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
>
> Build changes
>
> * Linux: CI_DRM_12325 -> Patchwork_110323v1
>
> CI-20190529: 20190529
> CI_DRM_12325: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7032: 372c56225e12578a7a4a6bcc5b79eb40b643fcde @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_110323v1: 1a90222aa5e5bb86ffcbde5ba9611659a23f0df6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
--
Wayne Boyer
Graphics Software Engineer
AXG SCSS Platform Enablement
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg2: Introduce Wa_18018764978
On 10/25/22 11:03 AM, Matt Atwood wrote: > Wa_18018764978 applies to specific steppings of DG2 (G11 C0+, > G11 and G12 A0+). > > Bspec: 66622 > > Signed-off-by: Matt Atwood With fixups to commit messages as mentioned by Gustavo, Reviewed-by: Wayne Boyer > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 36d95b79022c..e8372d4cd548 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -448,6 +448,9 @@ > #define GEN8_L3CNTLREG _MMIO(0x7034) > #define GEN8_ERRDETBCTRL (1 << 9) > > +#define PSS_MODE2_MMIO(0x703c) > +#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) > + > #define GEN7_SC_INSTDONE _MMIO(0x7100) > #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) > #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 63e1e6becf34..ced3a26cf7e7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -743,6 +743,11 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > wa_masked_field_set(wal, VF_PREEMPTION, > PREEMPTION_VERTEX_COUNT, 0x4000); > > + /* Wa_18018764978:dg2 */ > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); > + > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > } -- Wayne Boyer Graphics Software Engineer AXG SCSS Platform Enablement
