[Intel-gfx] [PATCH] drm/i915: Fix mode_get() for Broxton
Making changes in intel_crtc_mode_get() to get correct values for crtc clock,
vdisplay, hdisplay, vtotal.
1. intel_crtc_mode_get() gets clock using i9xx_crtc_clock_get() which wil not
work for hsw, skl, bxt.
2. For BXT DSI, hdisplay, vdisplay, vtotal registers are different. In the
current implementation, these value will be incorrect, thus impacting DPST.
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_display.c | 66 +---
1 file changed, 62 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0743337..974977b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -34,6 +34,7 @@
#include
#include
#include "intel_drv.h"
+#include "intel_dsi.h"
#include
#include "i915_drv.h"
#include "i915_trace.h"
@@ -116,6 +117,15 @@ static void skylake_pfit_enable(struct intel_crtc *crtc);
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
static void ironlake_pfit_enable(struct intel_crtc *crtc);
static void intel_modeset_setup_hw_state(struct drm_device *dev);
+static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
+static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
+static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
typedef struct {
int min, max;
@@ -10698,6 +10708,33 @@ static void ironlake_pch_clock_get(struct intel_crtc
*crtc,
&pipe_config->fdi_m_n);
}
+static void haswell_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder = NULL;
+ enum port port;
+ bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ port = intel_ddi_get_encoder_port(encoder);
+ if (IS_BROXTON(dev) && is_dsi) {
+ pipe_config->port_clock = bxt_get_dsi_pclk(encoder,
+ pipe_config->pipe_bpp);
+ break;
+ }
+ if (IS_SKYLAKE(dev))
+ skylake_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (IS_BROXTON(dev))
+ bxt_get_ddi_pll(dev_priv, port, pipe_config);
+ else
+ haswell_get_ddi_pll(dev_priv, port, pipe_config);
+
+ intel_ddi_clock_get(encoder, pipe_config);
+ }
+}
+
/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
struct drm_crtc *crtc)
@@ -10712,6 +10749,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct
drm_device *dev,
int vtot = I915_READ(VTOTAL(cpu_transcoder));
int vsync = I915_READ(VSYNC(cpu_transcoder));
enum pipe pipe = intel_crtc->pipe;
+ bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -10729,17 +10767,37 @@ struct drm_display_mode *intel_crtc_mode_get(struct
drm_device *dev,
pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
- i9xx_crtc_clock_get(intel_crtc, &pipe_config);
+ if (HAS_DDI(dev) || INTEL_INFO(dev)->gen >= 9) {
+ haswell_crtc_clock_get(intel_crtc, &pipe_config);
+ } else {
+ i9xx_crtc_clock_get(intel_crtc, &pipe_config);
+ }
mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
- mode->hdisplay = (htot & 0x) + 1;
mode->htotal = ((htot & 0x) >> 16) + 1;
mode->hsync_start = (hsync & 0x) + 1;
mode->hsync_end = ((hsync & 0x) >> 16) + 1;
- mode->vdisplay = (vtot & 0x) + 1;
- mode->vtotal = ((vtot & 0x) >> 16) + 1;
mode->vsync_start = (vsync & 0x) + 1;
mode->vsync_end = ((vsync & 0x) >> 16) + 1;
+ if (IS_BROXTON(dev) && is_dsi) {
+ struct intel_encoder *encoder;
+
+ for_each_encoder_on_crtc(dev, &intel_crtc->base, encoder) {
+ struct in
[Intel-gfx] [RFC 1/2] drm: Add aux plane verification in addFB2
From: Daniel Vetter
For render compression, userspace passes aux stride and offset values as an
additional entry in the fb structure. This should not be treated as garbage
and discarded as data belonging to no plane.
This patch introduces a check related to AUX plane to support the
scenario of render compression.
v2: Based on a discussion with Siva
Move num_planes check below the increment.
Signed-off-by: Daniel Vetter
Signed-off-by: Vandana Kannan
Cc: Sivakumar Thulasimani
---
drivers/gpu/drm/drm_crtc.c | 19 ++-
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/drm/drm_crtc.h | 3 +++
include/uapi/drm/drm.h | 1 +
include/uapi/drm/drm_mode.h | 1 +
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 32dd134..8b79ff8 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3204,6 +3204,16 @@ static int framebuffer_check(const struct
drm_mode_fb_cmd2 *r)
}
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE) {
+ num_planes++;
+
+ if (num_planes == 4) {
+ DRM_DEBUG_KMS("Number of planes cannot exceed 3"
+ "(including aux plane)\n");
+ return -EINVAL;
+ }
+ }
+
for (i = num_planes; i < 4; i++) {
if (r->modifier[i]) {
DRM_DEBUG_KMS("non-zero modifier for unused plane
%d\n", i);
@@ -3242,7 +3252,8 @@ internal_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
int ret;
- if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
+ if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
+ DRM_MODE_FB_AUX_PLANE)) {
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
@@ -3264,6 +3275,12 @@ internal_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL);
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE &&
+ !dev->mode_config.allow_aux_plane) {
+ DRM_DEBUG_KMS("driver does not support render compression\n");
+ return ERR_PTR(-EINVAL);
+ }
+
ret = framebuffer_check(r);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..ee00782 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -312,6 +312,9 @@ static int drm_getcap(struct drm_device *dev, void *data,
struct drm_file *file_
case DRM_CAP_ADDFB2_MODIFIERS:
req->value = dev->mode_config.allow_fb_modifiers;
break;
+ case DRM_CAP_RENDER_COMPRESSION:
+ req->value = dev->mode_config.allow_aux_plane;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 4765df3..533d0cd 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1156,6 +1156,9 @@ struct drm_mode_config {
/* whether the driver supports fb modifiers */
bool allow_fb_modifiers;
+ /* whether the driver supports render compression */
+ bool allow_aux_plane;
+
/* cursor size */
uint32_t cursor_width, cursor_height;
};
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..0834bf7 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -631,6 +631,7 @@ struct drm_gem_open {
#define DRM_CAP_CURSOR_WIDTH 0x8
#define DRM_CAP_CURSOR_HEIGHT 0x9
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
+#define DRM_CAP_RENDER_COMPRESSION 0x11
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca4..de59ace 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -354,6 +354,7 @@ struct drm_mode_fb_cmd {
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_AUX_PLANE (1<<2) /* for compressed buffer */
struct drm_mode_fb_cmd2 {
__u32 fb_id;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/2] drm/i915: Render decompression support for Gen9
This patch includes enabling render decompression after checking all the
requirements (format, tiling, rotation etc.). Along with this, the WAs
mentioned in BSpec Workaround page have been implemented.
In case, any of the conditions fail, the flip will fail.
TODO:
1. Disable stereo 3D when render decomp is enabled (bit 7:6)
2. Render decompression must not be used in VTd pass-through mode
3. Program hashing select CHICKEN_MISC1 bit 15
Note: This patch is based on top of Chandra's and Ville's NV12/fb->offset
related patches series.
Signed-off-by: Vandana Kannan
Cc: Konduru, Chandra
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_atomic_plane.c | 18 ++-
drivers/gpu/drm/i915/intel_display.c | 233 --
drivers/gpu/drm/i915/intel_drv.h | 9 ++
drivers/gpu/drm/i915/intel_sprite.c | 53 +--
5 files changed, 281 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1a8a53..340bb0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1866,6 +1866,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *render_comp_property;
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index c6bb0fc..7324204 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -222,8 +222,13 @@ intel_plane_atomic_get_property(struct drm_plane *plane,
struct drm_property *property,
uint64_t *val)
{
- DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
- return -EINVAL;
+ if (property == dev_priv->render_comp_property) {
+ *val = intel_state->render_comp_enable;
+ } else {
+ DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
+ return -EINVAL;
+ }
+ return 0;
}
/**
@@ -244,6 +249,11 @@ intel_plane_atomic_set_property(struct drm_plane *plane,
struct drm_property *property,
uint64_t val)
{
- DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
- return -EINVAL;
+ if (property == dev_priv->render_comp_property) {
+ intel_state->render_comp_enable = val;
+ } else {
+ DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
+ return -EINVAL;
+ }
+ return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b421d3c..255c5f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -118,6 +118,9 @@ static void skylake_pfit_enable(struct intel_crtc *crtc);
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
static void ironlake_pfit_enable(struct intel_crtc *crtc);
static void intel_modeset_setup_hw_state(struct drm_device *dev);
+static int skl_check_compression(struct drm_device *dev,
+ struct intel_plane_state *plane_state,
+ enum pipe pipe, int x, int y);
typedef struct {
int min, max;
@@ -3075,7 +3078,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
bool visible = to_intel_plane_state(plane->state)->visible;
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride;
- unsigned int rotation;
+ unsigned int rotation, render_comp;
u32 surf_addr;
struct intel_crtc_state *crtc_state = intel_crtc->config;
struct intel_plane_state *plane_state;
@@ -3084,7 +3087,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
int dst_x, dst_y, dst_w, dst_h;
unsigned long aux_dist = 0;
u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
- u32 tile_row_adjustment = 0;
+ u32 tile_row_adjustment = 0, height_in_mem = 0;
u32 hphase = 0, vphase = 0;
int pixel_size;
@@ -3155,15 +3158,15 @@ static void skylake_update_primary_plane(struct
drm_crtc *crtc,
fb->pixel_format);
tile_height = PAGE_SIZE / intel_fb_stride_alignment(dev_priv,
fb->modifier[0],
fb->pixel_format);
+ height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+ /*
+* If UV starts from middle of a page, then UV start should
+* be programmed to beginning of that page. And
[Intel-gfx] [PATCH v2 2/2] drm/i915: Render decompression support for Gen9 and above
This patch includes enabling render decompression (RC) after checking
all the requirements (format, tiling, rotation etc.).
TODO:
1. Disable stereo 3D when render decomp is enabled (bit 7:6)
2. Render decompression must not be used in VTd pass-through mode
3. Program hashing select CHICKEN_MISC1 bit 15
4. For Gen10, add support for RGB 1010102
5. RC-FBC workaround
6. RC watermark calculation
The reason for using a plane property instead of fb modifier:-
In Android, OGL passes a render compressed buffer to hardware composer
(HWC), which would then request a flip on that buffer after checking if
the target can support render compressed buffer. For example, only planes
1 and 2 on pipes 1 and 2 can support RC. In case the target cannot
support it, HWC will revert back to OGL requesting for uncompressed
buffer.
Here,
if plane property is used, OGL would send back the buffer (same ID) after
decompression, marked uncompressed. If fb modifier was used, a different
version of the buffer would have to be maintained for different
combinations - in the simple case of render compressed vs uncompressed
buffer, there would be 2 fbs with 2 IDs. So, in this case, OGL would give
a reference to a fb with a different ID.
To avoid the difficulty of keeping track of multiple fbs and the subsequent
complexity in debug, the architecture forum decided to go ahead with a
plane property for RC.
[Mayuresh] Added the plane check in skl_check_compression()
v2: Ville's review comments addressed
- Removed WAs specific to SKL-C and BXT-A
- Assign capabilities according to pipe and plane during property creation
- in skl_check_compression(), check for conditions that must be satisifed
Maintaining the check for pixel format, even though compressed fb of format
other RGB should not have been created, to be on the safer side.
Added checks for BGR too.
Bitmask is being used for the property to accommodate 2 more options
expected to be added in future.
This patch depends on Ville's patch series on fb->offsets.
(Ref: git://github.com/vsyrjala/linux.git fb_offsets_14)
Testing is in progress for v2 of the patch.
Signed-off-by: Vandana Kannan
Cc: Ville Syrjälä
Cc: Smith, Gary K
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 22 +
drivers/gpu/drm/i915/intel_atomic_plane.c | 24 +-
drivers/gpu/drm/i915/intel_display.c | 135 +-
drivers/gpu/drm/i915/intel_drv.h | 10 +++
drivers/gpu/drm/i915/intel_sprite.c | 27 +-
6 files changed, 213 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 32f0597..ba32e7c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1901,6 +1901,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *render_comp_property;
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25e229b..da45cc9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5816,6 +5816,28 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7de7721..2617b75 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -228,8 +228,16 @@ intel_plane_atomic_get_property(struct drm_plane *plane,
[Intel-gfx] [PATCH v3 2/2] drm/i915: Render decompression support for Gen9 and above
This patch includes enabling render decompression (RC) after checking
all the requirements (format, tiling, rotation etc.).
TODO:
1. Disable stereo 3D when render decomp is enabled (bit 7:6)
2. Render decompression must not be used in VTd pass-through mode
3. Program hashing select CHICKEN_MISC1 bit 15
4. For Gen10, add support for RGB 1010102
5. RC-FBC workaround
6. RC watermark calculation
The reason for using a plane property instead of fb modifier:-
In Android, OGL passes a render compressed buffer to hardware composer
(HWC), which would then request a flip on that buffer after checking if
the target can support render compressed buffer. For example, only planes
1 and 2 on pipes 1 and 2 can support RC. In case the target cannot
support it, HWC will revert back to OGL requesting for uncompressed
buffer.
Here,
if plane property is used, OGL would send back the buffer (same ID) after
decompression, marked uncompressed. If fb modifier was used, a different
version of the buffer would have to be maintained for different
combinations - in the simple case of render compressed vs uncompressed
buffer, there would be 2 fbs with 2 IDs. So, in this case, OGL would give
a reference to a fb with a different ID.
To avoid the difficulty of keeping track of multiple fbs and the subsequent
complexity in debug, the architecture forum decided to go ahead with a
plane property for RC.
[Mayuresh] Added the plane check in skl_check_compression()
v2: Ville's review comments addressed
- Removed WAs specific to SKL-C and BXT-A
- Assign capabilities according to pipe and plane during property creation
- in skl_check_compression(), check for conditions that must be satisifed
Maintaining the check for pixel format, even though compressed fb of format
other RGB should not have been created, to be on the safer side.
Added checks for BGR too.
Bitmask is being used for the property to accommodate 2 more options
expected to be added in future.
v3: This patch has been implemented on top of Ville's patch series on
fb->offsets.
(Ref: git://github.com/vsyrjala/linux.git fb_offsets_15)
- Userspace is expected to pass aux offset through fb->offsets[1].
Testing is in progress for v3 of the patch.
Signed-off-by: Vandana Kannan
Cc: Ville Syrjälä
Cc: Smith, Gary K
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 22 ++
drivers/gpu/drm/i915/intel_atomic_plane.c | 24 +--
drivers/gpu/drm/i915/intel_display.c | 111 ++
drivers/gpu/drm/i915/intel_drv.h | 10 +++
drivers/gpu/drm/i915/intel_sprite.c | 13
6 files changed, 177 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a0b513..0465e0f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1915,6 +1915,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *render_comp_property;
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 54ce0b1..9d008e1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5818,6 +5818,28 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7de7721..2617b75 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@
[Intel-gfx] [PATCH 1/2] drm: Add aux plane verification in addFB2
From: Daniel Vetter
For render compression, userspace passes aux stride and offset values as an
additional entry in the fb structure. This should not be treated as garbage
and discarded as data belonging to no plane.
This patch introduces a check related to AUX plane to support the
scenario of render compression.
v2: Based on a discussion with Siva
Move num_planes check below the increment.
Signed-off-by: Daniel Vetter
Signed-off-by: Vandana Kannan
Cc: Sivakumar Thulasimani
---
drivers/gpu/drm/drm_crtc.c | 19 ++-
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/drm/drm_crtc.h | 3 +++
include/uapi/drm/drm.h | 1 +
include/uapi/drm/drm_mode.h | 1 +
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index a4e90c7..8659748 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3287,6 +3287,16 @@ static int framebuffer_check(const struct
drm_mode_fb_cmd2 *r)
}
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE) {
+ num_planes++;
+
+ if (num_planes == 4) {
+ DRM_DEBUG_KMS("Number of planes cannot exceed 3"
+ "(including aux plane)\n");
+ return -EINVAL;
+ }
+ }
+
for (i = num_planes; i < 4; i++) {
if (r->modifier[i]) {
DRM_DEBUG_KMS("non-zero modifier for unused plane
%d\n", i);
@@ -3325,7 +3335,8 @@ internal_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
int ret;
- if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
+ if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
+ DRM_MODE_FB_AUX_PLANE)) {
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
@@ -3347,6 +3358,12 @@ internal_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL);
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE &&
+ !dev->mode_config.allow_aux_plane) {
+ DRM_DEBUG_KMS("driver does not support render compression\n");
+ return ERR_PTR(-EINVAL);
+ }
+
ret = framebuffer_check(r);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..ee00782 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -312,6 +312,9 @@ static int drm_getcap(struct drm_device *dev, void *data,
struct drm_file *file_
case DRM_CAP_ADDFB2_MODIFIERS:
req->value = dev->mode_config.allow_fb_modifiers;
break;
+ case DRM_CAP_RENDER_COMPRESSION:
+ req->value = dev->mode_config.allow_aux_plane;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 7fad193..00b1f59 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2141,6 +2141,9 @@ struct drm_mode_config {
/* whether the driver supports fb modifiers */
bool allow_fb_modifiers;
+ /* whether the driver supports render compression */
+ bool allow_aux_plane;
+
/* cursor size */
uint32_t cursor_width, cursor_height;
};
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index a0ebfe7..01561834 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -632,6 +632,7 @@ struct drm_gem_open {
#define DRM_CAP_CURSOR_WIDTH 0x8
#define DRM_CAP_CURSOR_HEIGHT 0x9
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
+#define DRM_CAP_RENDER_COMPRESSION 0x11
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 50adb46..f900dc95 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -354,6 +354,7 @@ struct drm_mode_fb_cmd {
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_AUX_PLANE (1<<2) /* for compressed buffer */
struct drm_mode_fb_cmd2 {
__u32 fb_id;
--
1.9.1
___
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[Intel-gfx] [PATCH 2/2] drm/i915: Render decompression support for Gen9 and above
This patch includes enabling render decompression (RC) after checking all the
requirements (format, tiling, rotation etc.). Along with this, the WAs
mentioned in BSpec Workaround page have been implemented.
TODO:
1. Disable stereo 3D when render decomp is enabled (bit 7:6)
2. Render decompression must not be used in VTd pass-through mode
3. Program hashing select CHICKEN_MISC1 bit 15
4. For Gen10, add support for RGB 1010102
5. RC-FBC workaround
6. RC watermark calculation
The reason for using a plane property instead of fb modifier:-
In Android, OGL passes a render compressed buffer to hardware composer (HWC),
which would then request a flip on that buffer after checking if the target
can support render compressed buffer. For example, only planes 1 and 2 on
pipes 1 and 2 can support RC. In case the target cannot support it, HWC will
revert back to OGL requesting for uncompressed buffer.
Here,
if plane property is used, OGL would send back the buffer (same ID) after
decompression, marked uncompressed. If fb modifier was used, a different
version of the buffer would have to be maintained for different combinations -
in the simple case of render compressed vs uncompressed buffer, there would be
2 fbs with 2 IDs. So, in this case, OGL would give a reference to a fb with a
different ID.
To avoid the difficulty of keeping track of multiple fbs and the subsequent
complexity in debug, the architecture forum decided to go ahead with a plane
property for RC.
[Mayuresh] Added the plane check in skl_check_compression()
Signed-off-by: Vandana Kannan
Cc: Smith, Gary K
Cc: Daniel Stone
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 22
drivers/gpu/drm/i915/intel_atomic_plane.c | 24 +++-
drivers/gpu/drm/i915/intel_display.c | 206 +-
drivers/gpu/drm/i915/intel_drv.h | 24 +++-
drivers/gpu/drm/i915/intel_sprite.c | 42 +-
6 files changed, 305 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f37ac12..bb47ee1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1929,6 +1929,7 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *render_comp_property;
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..773c37f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5756,6 +5756,28 @@ enum skl_disp_power_wells {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
_PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A 0x701c4
+#define PLANE_AUX_OFFSET_2_A 0x702c4
+#define PLANE_AUX_OFFSET_1_B 0x711c4
+#define PLANE_AUX_OFFSET_2_B 0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe) \
+ _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
_PLANE_AUX_OFFSET_2(pipe))
+
/* legacy palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index e0b851a..c431333 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -230,8 +230,16 @@ intel_plane_atomic_get_property(struct drm_plane *plane,
struct drm_property *property,
uint64_t *val)
{
- DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
- return -EINVAL;
+ struct drm_i915_private *dev_priv = state->plane->dev->dev_private;
+ struct intel_plane_state *intel_state = to_intel_plane_state(state);
+
+ if (property == dev_priv->render_comp_property) {
+ *val = intel_state->render_comp_enable;
+ } else {
+ DRM_DEBUG_KMS("Unk
[Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
Signed-off-by: Vandana Kannan
Reported-by: Philippe Lecluse
Cc: Deak, Imre
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 11 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..9a02bfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
#define _PORT_CL1CM_DW0_A 0x162000
#define _PORT_CL1CM_DW0_BC 0x6C000
#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy),
_PORT_CL1CM_DW0_BC, \
_PORT_CL1CM_DW0_A)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..354f949 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private
*dev_priv,
val |= GT_DISPLAY_POWER_ON(phy);
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- /* Considering 10ms timeout until BSpec is updated */
- if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ /*
+* HW team confirmed that the time to reach phypowergood status is
+* anywhere between 50 us and 100us.
+*/
+ if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_RESERVED)) &&
+ ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
+ }
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
1.9.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: BXT DDI PHY sequence BUN
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
v2: use wait_for_us instead of the atomic call.
Signed-off-by: Vandana Kannan
Reported-by: Philippe Lecluse
Cc: Deak, Imre
Cc: Nikula, Jani
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 15 +--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..9a02bfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
#define _PORT_CL1CM_DW0_A 0x162000
#define _PORT_CL1CM_DW0_BC 0x6C000
#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy),
_PORT_CL1CM_DW0_BC, \
_PORT_CL1CM_DW0_A)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..05a5b3a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2669,9 +2669,20 @@ static void broxton_phy_init(struct drm_i915_private
*dev_priv,
val |= GT_DISPLAY_POWER_ON(phy);
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- /* Considering 10ms timeout until BSpec is updated */
- if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ /*
+* The PHY registers start out inaccessible and respond to reads with
+* all 1s. Eventually they become accessible as they power up, then
+* the reserved bit will give the default 0. Poll on the reserved bit
+* becoming 0 to find when the PHY is accessible.
+* HW team confirmed that the time to reach phypowergood status is
+* anywhere between 50 us and 100us.
+*/
+ if (wait_for_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_RESERVED)) &&
+ ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
+ }
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
1.9.1
___
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[Intel-gfx] [PATCH v3] drm/i915: BXT DDI PHY sequence BUN
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
v2: [Ville] use wait_for_us instead of the atomic call.
v3: [Jani/Imre] read register only once
Signed-off-by: Vandana Kannan
Reported-by: Philippe Lecluse
Cc: Deak, Imre
Cc: Nikula, Jani
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 13 +++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..9a02bfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
#define _PORT_CL1CM_DW0_A 0x162000
#define _PORT_CL1CM_DW0_BC 0x6C000
#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy)_BXT_PHY((phy),
_PORT_CL1CM_DW0_BC, \
_PORT_CL1CM_DW0_A)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..4a8f504 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2669,9 +2669,18 @@ static void broxton_phy_init(struct drm_i915_private
*dev_priv,
val |= GT_DISPLAY_POWER_ON(phy);
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- /* Considering 10ms timeout until BSpec is updated */
- if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ /*
+* The PHY registers start out inaccessible and respond to reads with
+* all 1s. Eventually they become accessible as they power up, then
+* the reserved bit will give the default 0. Poll on the reserved bit
+* becoming 0 to find when the PHY is accessible.
+* HW team confirmed that the time to reach phypowergood status is
+* anywhere between 50 us and 100us.
+*/
+ if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
+ }
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
1.9.1
___
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[Intel-gfx] [PATCH 0/2] Introducing crtc_clock_get()
The implementation of crtc_clock_get() will not work for BXT. The 2 patches in this series, cleans up the code related to crtc_clock_get() and includes implementation for BXT (DSI and otherwise). A patch to correct crtc_mode_get() for BXT DSI will follow shortly. Vandana Kannan (2): drm/i915: Create crtc_clock_get function pointers drm/i915: Add crtc_clock_get for hsw, skl, bxt drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 57 +++- 2 files changed, 51 insertions(+), 8 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: Create crtc_clock_get function pointers
There are separate functions i9xx_crtc_clock_get(), vlv_crtc_clock_get(),
chv_crtc_clock_get(). instead of calling these using if-else, making
func pointers. This will also be useful going forward when the implementation
for BXT is done.
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 20
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8afda45..773f507 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -607,6 +607,8 @@ struct intel_limit;
struct dpll;
struct drm_i915_display_funcs {
+ void (*crtc_clock_get)(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config);
int (*get_display_clock_speed)(struct drm_device *dev);
int (*get_fifo_size)(struct drm_device *dev, int plane);
/**
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c28fb6a..d98385e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8130,12 +8130,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
DPLL_PORTB_READY_MASK);
}
- if (IS_CHERRYVIEW(dev))
- chv_crtc_clock_get(crtc, pipe_config);
- else if (IS_VALLEYVIEW(dev))
- vlv_crtc_clock_get(crtc, pipe_config);
- else
- i9xx_crtc_clock_get(crtc, pipe_config);
+ dev_priv->display.crtc_clock_get(crtc, pipe_config);
/*
* Normally the dotclock is filled in by the encoder .get_config()
@@ -10579,9 +10574,10 @@ static void ironlake_pch_clock_get(struct intel_crtc
*crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
/* read out port_clock from the DPLL */
- i9xx_crtc_clock_get(crtc, pipe_config);
+ dev_priv->display.crtc_clock_get(crtc, &pipe_config);
/*
* This value does not include pixel_multiplier.
@@ -10625,7 +10621,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct
drm_device *dev,
pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
- i9xx_crtc_clock_get(intel_crtc, &pipe_config);
+ dev_priv->display.crtc_clock_get(intel_crtc, &pipe_config);
mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
mode->hdisplay = (htot & 0x) + 1;
@@ -14413,6 +14409,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.update_primary_plane =
skylake_update_primary_plane;
+ dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get;
} else if (HAS_DDI(dev)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
@@ -14423,6 +14420,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.update_primary_plane =
ironlake_update_primary_plane;
+ dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
@@ -14433,6 +14431,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = ironlake_crtc_disable;
dev_priv->display.update_primary_plane =
ironlake_update_primary_plane;
+ dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
dev_priv->display.get_initial_plane_config =
@@ -14442,6 +14441,10 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = i9xx_crtc_disable;
dev_priv->display.update_primary_plane =
i9xx_update_primary_plane;
+ if (IS_CHERRYVIEW(dev))
+ dev_priv->display.crtc_clock_get = chv_crtc_clock_get;
+ else
+ dev_priv->display.crtc_clock_get = vlv_crtc_clock_get;
} else {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
dev_priv-
[Intel-gfx] [PATCH 2/2] drm/i915: Add crtc_clock_get for hsw, skl, bxt
Reusing the ddi_clock_get functions for hsw, skl, bxt and creating a
common crtc_clock_get function.
for BXT, there is a difference in clock between DSI and DDI. Taking care of
this as well.
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_display.c | 43 +---
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d98385e..c9fcadd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -34,6 +34,7 @@
#include
#include
#include "intel_drv.h"
+#include "intel_dsi.h"
#include
#include "i915_drv.h"
#include "i915_trace.h"
@@ -112,6 +113,15 @@ static void skl_init_scalers(struct drm_device *dev,
struct intel_crtc *intel_cr
struct intel_crtc_state *crtc_state);
static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
int num_connectors);
+static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
+static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
+static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
+ enum port port,
+ struct intel_crtc_state *pipe_config);
static void skylake_pfit_enable(struct intel_crtc *crtc);
static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
static void ironlake_pfit_enable(struct intel_crtc *crtc);
@@ -8050,6 +8060,33 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
}
+static void haswell_crtc_clock_get(struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder = NULL;
+ enum port port;
+ bool is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
+ port = intel_ddi_get_encoder_port(encoder);
+ if (IS_BROXTON(dev) && is_dsi) {
+ pipe_config->port_clock = bxt_get_dsi_pclk(encoder,
+ pipe_config->pipe_bpp);
+ break;
+ }
+ if (IS_SKYLAKE(dev))
+ skylake_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (IS_BROXTON(dev))
+ bxt_get_ddi_pll(dev_priv, port, pipe_config);
+ else
+ haswell_get_ddi_pll(dev_priv, port, pipe_config);
+
+ intel_ddi_clock_get(encoder, pipe_config);
+ }
+}
+
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -10577,7 +10614,7 @@ static void ironlake_pch_clock_get(struct intel_crtc
*crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
/* read out port_clock from the DPLL */
- dev_priv->display.crtc_clock_get(crtc, &pipe_config);
+ dev_priv->display.crtc_clock_get(crtc, pipe_config);
/*
* This value does not include pixel_multiplier.
@@ -14409,7 +14446,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.update_primary_plane =
skylake_update_primary_plane;
- dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get;
+ dev_priv->display.crtc_clock_get = haswell_crtc_clock_get;
} else if (HAS_DDI(dev)) {
dev_priv->display.get_pipe_config = haswell_get_pipe_config;
dev_priv->display.get_initial_plane_config =
@@ -14420,7 +14457,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.crtc_disable = haswell_crtc_disable;
dev_priv->display.update_primary_plane =
ironlake_update_primary_plane;
- dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get;
+ dev_priv->display.crtc_clock_get = haswell_crtc_clock_get;
} else if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
dev_priv->display.get_initial_plane_config =
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Add aux plane verification in addFB2
For render compression, userspace passes aux stride and offset values as an
additional entry in the fb structure. This should not be treated as garbage
and discarded as data belonging to no plane.
This patch introduces a check related to AUX plane to support the
scenario of render compression.
Suggested-by: Daniel Vetter
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/drm_crtc.c | 16 +++-
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/drm/drm_crtc.h | 3 +++
include/uapi/drm/drm.h | 1 +
include/uapi/drm/drm_mode.h | 1 +
5 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 24c5434..7dbc0f0 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3204,6 +3204,13 @@ static int framebuffer_check(const struct
drm_mode_fb_cmd2 *r)
}
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE) {
+ if (num_planes == 4)
+ return -EINVAL;
+
+ num_planes++;
+ }
+
for (i = num_planes; i < 4; i++) {
if (r->modifier[i]) {
DRM_DEBUG_KMS("non-zero modifier for unused plane
%d\n", i);
@@ -3242,7 +3249,8 @@ internal_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
int ret;
- if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
+ if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
+ DRM_MODE_FB_AUX_PLANE)) {
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
@@ -3264,6 +3272,12 @@ internal_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL);
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE &&
+ !dev->mode_config.allow_aux_plane) {
+ DRM_DEBUG_KMS("driver does not support render compression\n");
+ return ERR_PTR(-EINVAL);
+ }
+
ret = framebuffer_check(r);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..ee00782 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -312,6 +312,9 @@ static int drm_getcap(struct drm_device *dev, void *data,
struct drm_file *file_
case DRM_CAP_ADDFB2_MODIFIERS:
req->value = dev->mode_config.allow_fb_modifiers;
break;
+ case DRM_CAP_RENDER_COMPRESSION:
+ req->value = dev->mode_config.allow_aux_plane;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 3f0c690..a5a9da2 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1152,6 +1152,9 @@ struct drm_mode_config {
/* whether the driver supports fb modifiers */
bool allow_fb_modifiers;
+ /* whether the driver supports render compression */
+ bool allow_aux_plane;
+
/* cursor size */
uint32_t cursor_width, cursor_height;
};
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..0834bf7 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -631,6 +631,7 @@ struct drm_gem_open {
#define DRM_CAP_CURSOR_WIDTH 0x8
#define DRM_CAP_CURSOR_HEIGHT 0x9
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
+#define DRM_CAP_RENDER_COMPRESSION 0x11
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca4..de59ace 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -354,6 +354,7 @@ struct drm_mode_fb_cmd {
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_AUX_PLANE (1<<2) /* for compressed buffer */
struct drm_mode_fb_cmd2 {
__u32 fb_id;
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm: Add aux plane verification in addFB2
From: Daniel Vetter
For render compression, userspace passes aux stride and offset values as an
additional entry in the fb structure. This should not be treated as garbage
and discarded as data belonging to no plane.
This patch introduces a check related to AUX plane to support the
scenario of render compression.
v2: Based on a discussion with Siva
Moving num_planes check below the increment.
Changing the author to Daniel instead of suggested-by, since the core logic is
his.
Signed-off-by: Daniel Vetter
Signed-off-by: Vandana Kannan
Cc: Sivakumar Thulasimani
---
drivers/gpu/drm/drm_crtc.c | 19 ++-
drivers/gpu/drm/drm_ioctl.c | 3 +++
include/drm/drm_crtc.h | 3 +++
include/uapi/drm/drm.h | 1 +
include/uapi/drm/drm_mode.h | 1 +
5 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 24c5434..0d1030b 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -3204,6 +3204,16 @@ static int framebuffer_check(const struct
drm_mode_fb_cmd2 *r)
}
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE) {
+ num_planes++;
+
+ if (num_planes == 4) {
+ DRM_DEBUG_KMS("Number of planes cannot exceed 3"
+ "(including aux plane)\n");
+ return -EINVAL;
+ }
+ }
+
for (i = num_planes; i < 4; i++) {
if (r->modifier[i]) {
DRM_DEBUG_KMS("non-zero modifier for unused plane
%d\n", i);
@@ -3242,7 +3252,8 @@ internal_framebuffer_create(struct drm_device *dev,
struct drm_framebuffer *fb;
int ret;
- if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
+ if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS |
+ DRM_MODE_FB_AUX_PLANE)) {
DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
return ERR_PTR(-EINVAL);
}
@@ -3264,6 +3275,12 @@ internal_framebuffer_create(struct drm_device *dev,
return ERR_PTR(-EINVAL);
}
+ if (r->flags & DRM_MODE_FB_AUX_PLANE &&
+ !dev->mode_config.allow_aux_plane) {
+ DRM_DEBUG_KMS("driver does not support render compression\n");
+ return ERR_PTR(-EINVAL);
+ }
+
ret = framebuffer_check(r);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..ee00782 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -312,6 +312,9 @@ static int drm_getcap(struct drm_device *dev, void *data,
struct drm_file *file_
case DRM_CAP_ADDFB2_MODIFIERS:
req->value = dev->mode_config.allow_fb_modifiers;
break;
+ case DRM_CAP_RENDER_COMPRESSION:
+ req->value = dev->mode_config.allow_aux_plane;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 3f0c690..a5a9da2 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -1152,6 +1152,9 @@ struct drm_mode_config {
/* whether the driver supports fb modifiers */
bool allow_fb_modifiers;
+ /* whether the driver supports render compression */
+ bool allow_aux_plane;
+
/* cursor size */
uint32_t cursor_width, cursor_height;
};
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 3801584..0834bf7 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -631,6 +631,7 @@ struct drm_gem_open {
#define DRM_CAP_CURSOR_WIDTH 0x8
#define DRM_CAP_CURSOR_HEIGHT 0x9
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
+#define DRM_CAP_RENDER_COMPRESSION 0x11
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 6c11ca4..de59ace 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -354,6 +354,7 @@ struct drm_mode_fb_cmd {
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
+#define DRM_MODE_FB_AUX_PLANE (1<<2) /* for compressed buffer */
struct drm_mode_fb_cmd2 {
__u32 fb_id;
--
1.9.1
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio
On Apr-07-2014 3:24 PM, Vandana Kannan wrote:
> On Apr-07-2014 3:33 PM, Kannan, Vandana wrote:
>> Added a property to enable user space to set aspect ratio.
>> This patch contains declaration of the property and code to create the
>> property.
>>
>> Signed-off-by: Vandana Kannan
>> Cc: dri-de...@lists.freedesktop.org
>> ---
> This patch series is being submitted as discussed in
> http://lists.freedesktop.org/archives/dri-devel/2014-April/056593.html
>
> -Vandana
Please help review this patch series to enable user space to set aspect
ratio for AVI infoframe.
http://lists.freedesktop.org/archives/intel-gfx/2014-April/043226.html
http://lists.freedesktop.org/archives/intel-gfx/2014-April/043228.html
http://lists.freedesktop.org/archives/intel-gfx/2014-April/043227.html
-Vandana
>> drivers/gpu/drm/drm_crtc.c | 31 +++
>> include/drm/drm_crtc.h | 2 ++
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
>> index d8b7099..6cd34ad 100644
>> --- a/drivers/gpu/drm/drm_crtc.c
>> +++ b/drivers/gpu/drm/drm_crtc.c
>> @@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
>> drm_scaling_mode_enum_list[] =
>> { DRM_MODE_SCALE_ASPECT, "Full aspect" },
>> };
>>
>> +static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
>> +{ HDMI_PICTURE_ASPECT_NONE, "Automatic" },
>> +{ HDMI_PICTURE_ASPECT_4_3, "4:3" },
>> +{ HDMI_PICTURE_ASPECT_16_9, "16:9" },
>> +};
>> +
>> /*
>> * Non-global properties, but "required" for certain connectors.
>> */
>> @@ -1334,6 +1340,31 @@ int drm_mode_create_scaling_mode_property(struct
>> drm_device *dev)
>> EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
>>
>> /**
>> + * drm_mode_create_aspect_ratio_property - create aspect ratio property
>> + * @dev: DRM device
>> + *
>> + * Called by a driver the first time it's needed, must be attached to
>> desired
>> + * connectors.
>> + */
>> +int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
>> +{
>> +struct drm_property *aspect_ratio;
>> +
>> +if (dev->mode_config.aspect_ratio_property)
>> +return 0;
>> +
>> +aspect_ratio =
>> +drm_property_create_enum(dev, 0, "aspect ratio",
>> +drm_aspect_ratio_enum_list,
>> +ARRAY_SIZE(drm_aspect_ratio_enum_list));
>> +
>> +dev->mode_config.aspect_ratio_property = aspect_ratio;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
>> +
>> +/**
>> * drm_mode_create_dirty_property - create dirty property
>> * @dev: DRM device
>> *
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index c061bb3..99bb6ed 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -797,6 +797,7 @@ struct drm_mode_config {
>>
>> /* Optional properties */
>> struct drm_property *scaling_mode_property;
>> +struct drm_property *aspect_ratio_property;
>> struct drm_property *dirty_info_property;
>>
>> /* dumb ioctl parameters */
>> @@ -966,6 +967,7 @@ extern int drm_mode_create_dvi_i_properties(struct
>> drm_device *dev);
>> extern int drm_mode_create_tv_properties(struct drm_device *dev, int
>> num_formats,
>> char *formats[]);
>> extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
>> +extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
>> extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
>> extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
>>
>>
>
> ___
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> dri-de...@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
___
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v9 3/6] drm/i915: Add support for DRRS to switch RR
On Apr-11-2014 4:51 PM, Vandana Kannan wrote: > On Apr-11-2014 2:56 PM, Daniel Vetter wrote: >> On Fri, Apr 11, 2014 at 02:48:53PM +0530, Vandana Kannan wrote: >>> On Apr-10-2014 2:28 PM, Daniel Vetter wrote: >>>> On Thu, Apr 10, 2014 at 11:43:15AM +0300, Jani Nikula wrote: >>>>> >>>>> Reviewed-by: Jani Nikula >>>>> >>>>> >>>>> On Sat, 05 Apr 2014, Vandana Kannan wrote: >>>>>> From: Pradeep Bhat >>>>>> >>>>>> This patch computes and stored 2nd M/N/TU for switching to different >>>>>> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle >>>>>> between alternate refresh rates programmed in 2nd M/N/TU registers. >>>>>> >>>>>> v2: Daniel's review comments >>>>>> Computing M2/N2 in compute_config and storing it in crtc_config >>>>>> >>>>>> v3: Modified reference to edp_downclock and edp_downclock_avail based on >>>>>> the >>>>>> changes made to move them from dev_private to intel_panel. >>>>>> >>>>>> v4: Modified references to is_drrs_supported based on the changes made to >>>>>> rename it to drrs_support. >>>>>> >>>>>> v5: Jani's review comments >>>>>> Removed superfluous return statements. Changed support for Gen 7 and >>>>>> above. >>>>>> Corrected indentation. Re-structured the code which finds crtc and >>>>>> connector >>>>>> from encoder. Changed some logs to be less verbose. >>>>>> >>>>>> v6: Modifying i915_drrs to include only intel connector as intel_dp can >>>>>> be >>>>>> derived from intel connector when required. >>>>>> >>>>>> v7: As per internal review comments, acquiring mutex just before >>>>>> accessing >>>>>> drrs RR. As per Chris's review comments, added documentation about the >>>>>> use >>>>>> of locking in the function. >>>>>> >>>>>> v8: Incorporated Jani's review comments. >>>>>> Removed reference to edp_downclock. >>>>>> >>>>>> v9: Jani's review comments. Modified comment in set_drrs. Changed index >>>>>> to >>>>>> type edp_drrs_refresh_rate_type. Check if PSR is enabled before setting >>>>>> registers fo DRRS. >>>>>> >>>>>> Signed-off-by: Pradeep Bhat >>>>>> Signed-off-by: Vandana Kannan >>>>>> Cc: Jani Nikula >>>> >>>> Queued for -next, thanks for the patch. One thing that's missing though is >>>> the state readout and cross-check support for this new bit of crtc->config >>>> data. We need to add that before putting this to real use. >>>> -Daniel >>>> >>> Hi Daniel, >>> >>> Could you please elaborate on your input above - on the missing code and >>> cross-checking for support part? >> >> If you add new state to crtc->config then you need to add the relevan >> readout code for that state (see the code in check_crtc_state) and ofc >> also add it to intel_pipe_config_compare. >> >> This is a debug feature of our driver to make sure we never lose track of >> things and thus far has been extremely helpful in catching issues early. >> -Daniel >> > I have submitted a patch adding this piece of code. Please have a look.. > http://lists.freedesktop.org/archives/intel-gfx/2014-April/043569.html > > - Vandana > Hi Daniel, Please help review the patch http://lists.freedesktop.org/archives/intel-gfx/2014-April/043569.html which is based on your review comments above. -Vandana ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's review comments incorporated.
Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
only when high RR is not in use (This is because alternate m_n register
programming will be done only when low RR is being used).
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 72 +---
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
4 files changed, 72 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e96..6784f0b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->has_dp_encoder = true;
intel_dp_get_m_n(intel_crtc, pipe_config);
+ intel_dp_get_m2_n2(intel_crtc, pipe_config);
break;
default:
break;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 797f01c..2e625eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
&pipe_config->dp_m_n);
}
+void intel_dp_get_m2_n2(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = pipe_config->cpu_transcoder;
+
+ if (INTEL_INFO(dev)->gen >= 8) {
+ intel_cpu_transcoder_get_m_n(crtc, transcoder,
+ &pipe_config->dp_m_n);
+ } else if (INTEL_INFO(dev)->gen > 6) {
+ pipe_config->dp_m2_n2.link_m =
+ I915_READ(PIPE_LINK_M2(transcoder));
+ pipe_config->dp_m2_n2.link_n =
+ I915_READ(PIPE_LINK_N2(transcoder));
+ pipe_config->dp_m2_n2.gmch_m =
+ I915_READ(PIPE_DATA_M2(transcoder))
+ & ~TU_SIZE_MASK;
+ pipe_config->dp_m2_n2.gmch_n =
+ I915_READ(PIPE_DATA_N2(transcoder));
+ pipe_config->dp_m2_n2.tu =
+ ((I915_READ(PIPE_DATA_M2(transcoder))
+ & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ }
+
+}
+
+
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -9169,6 +9197,15 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
pipe_config->dp_m_n.tu);
+
+ DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2:
%u, tu2: %u\n",
+ pipe_config->has_dp_encoder,
+ pipe_config->dp_m2_n2.gmch_m,
+ pipe_config->dp_m2_n2.gmch_n,
+ pipe_config->dp_m2_n2.link_m,
+ pipe_config->dp_m2_n2.link_n,
+ pipe_config->dp_m2_n2.tu);
+
DRM_DEBUG_KMS("requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->requested_mode);
DRM_DEBUG_KMS("adjusted mode:\n");
@@ -9533,6 +9570,14 @@ intel_pipe_config_compare(struct drm_device *dev,
struct intel_crtc_config *current_config,
struct intel_crtc_config *pipe_config)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_connector *intel_connector = dev_priv->drrs.connector;
+ struct intel_encoder *encoder = (intel_connector != NULL) ?
+ intel_attached_encoder(&intel_connector->base) :
+ NULL;
+ struct intel_dp *intel_dp = (encoder != NULL) ?
+ enc_to_intel_dp(&encoder->base) : NULL;
+
#define PIPE_CONF_CHECK_X(name)\
if (current_config->name != pipe_config->name) { \
DRM_ERROR("mismatch in " #name " " \
@@ -9583,
Re: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-12-2014 3:57 PM, Ville Syrjälä wrote:
> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
>> Adding relevant read out comparison code, in check_crtc_state, for the new
>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>> values for a DP downclock mode (if available). Suggested by Daniel.
>>
>> v2: Changed patch title.
>> Daniel's review comments incorporated.
>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
>> only when high RR is not in use (This is because alternate m_n register
>> programming will be done only when low RR is being used).
>>
>> Signed-off-by: Vandana Kannan
>> Cc: Daniel Vetter
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 72
>> +---
>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 4 files changed, 72 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>> b/drivers/gpu/drm/i915/intel_ddi.c
>> index 0ad4e96..6784f0b 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder
>> *encoder,
>> case TRANS_DDI_MODE_SELECT_DP_MST:
>> pipe_config->has_dp_encoder = true;
>> intel_dp_get_m_n(intel_crtc, pipe_config);
>> +intel_dp_get_m2_n2(intel_crtc, pipe_config);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 797f01c..2e625eb 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>> &pipe_config->dp_m_n);
>> }
>>
>> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
>> + struct intel_crtc_config *pipe_config)
>> +{
>> +struct drm_device *dev = crtc->base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +enum transcoder transcoder = pipe_config->cpu_transcoder;
>> +
>> +if (INTEL_INFO(dev)->gen >= 8) {
>> +intel_cpu_transcoder_get_m_n(crtc, transcoder,
>> +&pipe_config->dp_m_n);
>
> dm_m2_n2 surely? And why do we even want to do this?
>
My miss, will change this.
For Gen8, there is only one set of MN registers to be programmed for
high and low RR. Hence this check.
>> +} else if (INTEL_INFO(dev)->gen > 6) {
>> +pipe_config->dp_m2_n2.link_m =
>> +I915_READ(PIPE_LINK_M2(transcoder));
>> +pipe_config->dp_m2_n2.link_n =
>> +I915_READ(PIPE_LINK_N2(transcoder));
>> +pipe_config->dp_m2_n2.gmch_m =
>> +I915_READ(PIPE_DATA_M2(transcoder))
>> +& ~TU_SIZE_MASK;
>> +pipe_config->dp_m2_n2.gmch_n =
>> +I915_READ(PIPE_DATA_N2(transcoder));
>> +pipe_config->dp_m2_n2.tu =
>> +((I915_READ(PIPE_DATA_M2(transcoder))
>> +& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
>> +}
>> +
>> +}
>>
>> +
>> static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
>> struct intel_crtc_config *pipe_config)
>> {
>> @@ -9169,6 +9197,15 @@ static void intel_dump_pipe_config(struct intel_crtc
>> *crtc,
>>pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
>>pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
>>pipe_config->dp_m_n.tu);
>> +
>> +DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2:
>> %u, tu2: %u\n",
>> + pipe_config->has_dp_encoder,
>> + pipe_config->dp_m2_n2.gmch_m,
>> + pipe_config->dp_m2_n2.gmch_n,
>> + pipe_config->dp_m2_n2.link_m,
>> + pipe_config->dp_m2_n2.link_n,
>> + pipe_config->dp_m2_n2.tu);
>> +
>> DRM_DEBUG_KMS("requested mode:\n
Re: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-13-2014 2:28 PM, Daniel Vetter wrote:
> On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
>> On May-12-2014 3:57 PM, Ville Syrjälä wrote:
>>> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
>>>> Adding relevant read out comparison code, in check_crtc_state, for the new
>>>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>>>> values for a DP downclock mode (if available). Suggested by Daniel.
>>>>
>>>> v2: Changed patch title.
>>>> Daniel's review comments incorporated.
>>>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
>>>> only when high RR is not in use (This is because alternate m_n register
>>>> programming will be done only when low RR is being used).
>>>>
>>>> Signed-off-by: Vandana Kannan
>>>> Cc: Daniel Vetter
>>>> ---
>>>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>>>> drivers/gpu/drm/i915/intel_display.c | 72
>>>> +---
>>>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>>>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>>>> 4 files changed, 72 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>> index 0ad4e96..6784f0b 100644
>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder
>>>> *encoder,
>>>>case TRANS_DDI_MODE_SELECT_DP_MST:
>>>>pipe_config->has_dp_encoder = true;
>>>>intel_dp_get_m_n(intel_crtc, pipe_config);
>>>> + intel_dp_get_m2_n2(intel_crtc, pipe_config);
>>>>break;
>>>>default:
>>>>break;
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>> index 797f01c..2e625eb 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>>>> &pipe_config->dp_m_n);
>>>> }
>>>>
>>>> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
>>>> +struct intel_crtc_config *pipe_config)
>>>> +{
>>>> + struct drm_device *dev = crtc->base.dev;
>>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>>> + enum transcoder transcoder = pipe_config->cpu_transcoder;
>>>> +
>>>> + if (INTEL_INFO(dev)->gen >= 8) {
>>>> + intel_cpu_transcoder_get_m_n(crtc, transcoder,
>>>> + &pipe_config->dp_m_n);
>>>
>>> dm_m2_n2 surely? And why do we even want to do this?
>>>
>> My miss, will change this.
>> For Gen8, there is only one set of MN registers to be programmed for
>> high and low RR. Hence this check.
>>>> + } else if (INTEL_INFO(dev)->gen > 6) {
>>>> + pipe_config->dp_m2_n2.link_m =
>>>> + I915_READ(PIPE_LINK_M2(transcoder));
>>>> + pipe_config->dp_m2_n2.link_n =
>>>> + I915_READ(PIPE_LINK_N2(transcoder));
>>>> + pipe_config->dp_m2_n2.gmch_m =
>>>> + I915_READ(PIPE_DATA_M2(transcoder))
>>>> + & ~TU_SIZE_MASK;
>>>> + pipe_config->dp_m2_n2.gmch_n =
>>>> + I915_READ(PIPE_DATA_N2(transcoder));
>>>> + pipe_config->dp_m2_n2.tu =
>>>> + ((I915_READ(PIPE_DATA_M2(transcoder))
>>>> + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
>>>> + }
>>>> +
>>>> +}
>>>>
>>>> +
>>>> static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
>>>>struct intel_crtc_config *pipe_config)
>>>> {
>>>> @@ -9169,6 +9197,15 @@ static void intel_dump_pipe_config(struct
>>>> intel_crtc *crtc,
>>>> pipe_config->dp_m_n.gmch_
Re: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-13-2014 3:10 PM, Vandana Kannan wrote:
> On May-13-2014 2:28 PM, Daniel Vetter wrote:
>> On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
>>> On May-12-2014 3:57 PM, Ville Syrjälä wrote:
>>>> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
>>>>> Adding relevant read out comparison code, in check_crtc_state, for the new
>>>>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>>>>> values for a DP downclock mode (if available). Suggested by Daniel.
>>>>>
>>>>> v2: Changed patch title.
>>>>> Daniel's review comments incorporated.
>>>>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be
>>>>> done
>>>>> only when high RR is not in use (This is because alternate m_n register
>>>>> programming will be done only when low RR is being used).
>>>>>
>>>>> Signed-off-by: Vandana Kannan
>>>>> Cc: Daniel Vetter
>>>>> ---
>>>>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>>>>> drivers/gpu/drm/i915/intel_display.c | 72
>>>>> +---
>>>>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>>>>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>>>>> 4 files changed, 72 insertions(+), 5 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>>> index 0ad4e96..6784f0b 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>>> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder
>>>>> *encoder,
>>>>> case TRANS_DDI_MODE_SELECT_DP_MST:
>>>>> pipe_config->has_dp_encoder = true;
>>>>> intel_dp_get_m_n(intel_crtc, pipe_config);
>>>>> + intel_dp_get_m2_n2(intel_crtc, pipe_config);
>>>>> break;
>>>>> default:
>>>>> break;
>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>>> index 797f01c..2e625eb 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>> @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>>>>>&pipe_config->dp_m_n);
>>>>> }
>>>>>
>>>>> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
>>>>> + struct intel_crtc_config *pipe_config)
>>>>> +{
>>>>> + struct drm_device *dev = crtc->base.dev;
>>>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>>>> + enum transcoder transcoder = pipe_config->cpu_transcoder;
>>>>> +
>>>>> + if (INTEL_INFO(dev)->gen >= 8) {
>>>>> + intel_cpu_transcoder_get_m_n(crtc, transcoder,
>>>>> + &pipe_config->dp_m_n);
>>>>
>>>> dm_m2_n2 surely? And why do we even want to do this?
>>>>
>>> My miss, will change this.
>>> For Gen8, there is only one set of MN registers to be programmed for
>>> high and low RR. Hence this check.
>>>>> + } else if (INTEL_INFO(dev)->gen > 6) {
>>>>> + pipe_config->dp_m2_n2.link_m =
>>>>> + I915_READ(PIPE_LINK_M2(transcoder));
>>>>> + pipe_config->dp_m2_n2.link_n =
>>>>> + I915_READ(PIPE_LINK_N2(transcoder));
>>>>> + pipe_config->dp_m2_n2.gmch_m =
>>>>> + I915_READ(PIPE_DATA_M2(transcoder))
>>>>> + & ~TU_SIZE_MASK;
>>>>> + pipe_config->dp_m2_n2.gmch_n =
>>>>> + I915_READ(PIPE_DATA_N2(transcoder));
>>>>> + pipe_config->dp_m2_n2.tu =
>>>>> + ((I915_READ(PIPE_DATA_M2(transcoder))
>>>>> + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
>>>>> + }
>>>>> +
>>>>> +}
>>>>>
>>>>> +
>&
Re: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-15-2014 3:01 PM, Ville Syrjälä wrote:
> On Thu, May 15, 2014 at 02:48:02PM +0530, Vandana Kannan wrote:
>> On May-13-2014 3:10 PM, Vandana Kannan wrote:
>>> On May-13-2014 2:28 PM, Daniel Vetter wrote:
>>>> On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
>>>>> On May-12-2014 3:57 PM, Ville Syrjälä wrote:
>>>>>> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
>>>>>>> Adding relevant read out comparison code, in check_crtc_state, for the
>>>>>>> new
>>>>>>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>>>>>>> values for a DP downclock mode (if available). Suggested by Daniel.
>>>>>>>
>>>>>>> v2: Changed patch title.
>>>>>>> Daniel's review comments incorporated.
>>>>>>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be
>>>>>>> done
>>>>>>> only when high RR is not in use (This is because alternate m_n register
>>>>>>> programming will be done only when low RR is being used).
>>>>>>>
>>>>>>> Signed-off-by: Vandana Kannan
>>>>>>> Cc: Daniel Vetter
>>>>>>> ---
>>>>>>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>>>>>>> drivers/gpu/drm/i915/intel_display.c | 72
>>>>>>> +---
>>>>>>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>>>>>>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>>>>>>> 4 files changed, 72 insertions(+), 5 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>>>>> index 0ad4e96..6784f0b 100644
>>>>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>>>>> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder
>>>>>>> *encoder,
>>>>>>> case TRANS_DDI_MODE_SELECT_DP_MST:
>>>>>>> pipe_config->has_dp_encoder = true;
>>>>>>> intel_dp_get_m_n(intel_crtc, pipe_config);
>>>>>>> + intel_dp_get_m2_n2(intel_crtc, pipe_config);
>>>>>>> break;
>>>>>>> default:
>>>>>>> break;
>>>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>>>>> index 797f01c..2e625eb 100644
>>>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>>>> @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>>>>>>> &pipe_config->dp_m_n);
>>>>>>> }
>>>>>>>
>>>>>>> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
>>>>>>> + struct intel_crtc_config *pipe_config)
>>>>>>> +{
>>>>>>> + struct drm_device *dev = crtc->base.dev;
>>>>>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>>>>>> + enum transcoder transcoder = pipe_config->cpu_transcoder;
>>>>>>> +
>>>>>>> + if (INTEL_INFO(dev)->gen >= 8) {
>>>>>>> + intel_cpu_transcoder_get_m_n(crtc, transcoder,
>>>>>>> + &pipe_config->dp_m_n);
>>>>>>
>>>>>> dm_m2_n2 surely? And why do we even want to do this?
>>>>>>
>>>>> My miss, will change this.
>>>>> For Gen8, there is only one set of MN registers to be programmed for
>>>>> high and low RR. Hence this check.
>>>>>>> + } else if (INTEL_INFO(dev)->gen > 6) {
>>>>>>> + pipe_config->dp_m2_n2.link_m =
>>>>>>> +
>>>>>>> I915_READ(PIPE_LINK_M2(transcoder));
>>>>>>> + pipe_config->dp_m2_n2.link_n =
>>>>>>> +
Re: [Intel-gfx] [PATCH v2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-15-2014 2:48 PM, Vandana Kannan wrote:
> On May-13-2014 3:10 PM, Vandana Kannan wrote:
>> On May-13-2014 2:28 PM, Daniel Vetter wrote:
>>> On Tue, May 13, 2014 at 01:56:04PM +0530, Vandana Kannan wrote:
>>>> On May-12-2014 3:57 PM, Ville Syrjälä wrote:
>>>>> On Mon, May 05, 2014 at 01:49:31PM +0530, Vandana Kannan wrote:
>>>>>> Adding relevant read out comparison code, in check_crtc_state, for the
>>>>>> new
>>>>>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>>>>>> values for a DP downclock mode (if available). Suggested by Daniel.
>>>>>>
>>>>>> v2: Changed patch title.
>>>>>> Daniel's review comments incorporated.
>>>>>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be
>>>>>> done
>>>>>> only when high RR is not in use (This is because alternate m_n register
>>>>>> programming will be done only when low RR is being used).
>>>>>>
>>>>>> Signed-off-by: Vandana Kannan
>>>>>> Cc: Daniel Vetter
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>>>>>> drivers/gpu/drm/i915/intel_display.c | 72
>>>>>> +---
>>>>>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>>>>>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>>>>>> 4 files changed, 72 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
>>>>>> b/drivers/gpu/drm/i915/intel_ddi.c
>>>>>> index 0ad4e96..6784f0b 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>>>> @@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder
>>>>>> *encoder,
>>>>>> case TRANS_DDI_MODE_SELECT_DP_MST:
>>>>>> pipe_config->has_dp_encoder = true;
>>>>>> intel_dp_get_m_n(intel_crtc, pipe_config);
>>>>>> +intel_dp_get_m2_n2(intel_crtc, pipe_config);
>>>>>> break;
>>>>>> default:
>>>>>> break;
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>>>> index 797f01c..2e625eb 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>>> @@ -6670,6 +6670,34 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
>>>>>> &pipe_config->dp_m_n);
>>>>>> }
>>>>>>
>>>>>> +void intel_dp_get_m2_n2(struct intel_crtc *crtc,
>>>>>> + struct intel_crtc_config *pipe_config)
>>>>>> +{
>>>>>> +struct drm_device *dev = crtc->base.dev;
>>>>>> +struct drm_i915_private *dev_priv = dev->dev_private;
>>>>>> +enum transcoder transcoder = pipe_config->cpu_transcoder;
>>>>>> +
>>>>>> +if (INTEL_INFO(dev)->gen >= 8) {
>>>>>> +intel_cpu_transcoder_get_m_n(crtc, transcoder,
>>>>>> +&pipe_config->dp_m_n);
>>>>>
>>>>> dm_m2_n2 surely? And why do we even want to do this?
>>>>>
>>>> My miss, will change this.
>>>> For Gen8, there is only one set of MN registers to be programmed for
>>>> high and low RR. Hence this check.
>>>>>> +} else if (INTEL_INFO(dev)->gen > 6) {
>>>>>> +pipe_config->dp_m2_n2.link_m =
>>>>>> +
>>>>>> I915_READ(PIPE_LINK_M2(transcoder));
>>>>>> +pipe_config->dp_m2_n2.link_n =
>>>>>> +
>>>>>> I915_READ(PIPE_LINK_N2(transcoder));
>>>>>> +pipe_config->dp_m2_n2.gmch_m =
>>>>>> +
>>>>>> I915_READ(PIPE_DATA_M2(transcoder))
>>>>>> +
[Intel-gfx] [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's review comments incorporated.
Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
only when high RR is not in use (This is because alternate m_n register
programming will be done only when low RR is being used).
v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake.
Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures
based on DRRS state for gen 8 and above.
Save and restore M2 N2 registers for gen 7 and below
v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
only one set of M_N registers
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm/i915/i915_ums.c | 26 +++
drivers/gpu/drm/i915/intel_ddi.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 83 +---
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
6 files changed, 117 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b82f157..a06551a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -815,6 +815,14 @@ struct i915_suspend_saved_registers {
u32 savePIPEB_DATA_N1;
u32 savePIPEB_LINK_M1;
u32 savePIPEB_LINK_N1;
+ u32 savePIPEA_DATA_M2;
+ u32 savePIPEA_DATA_N2;
+ u32 savePIPEA_LINK_M2;
+ u32 savePIPEA_LINK_N2;
+ u32 savePIPEB_DATA_M2;
+ u32 savePIPEB_DATA_N2;
+ u32 savePIPEB_LINK_M2;
+ u32 savePIPEB_LINK_N2;
u32 saveMCHBAR_RENDER_STANDBY;
u32 savePCH_PORT_HOTPLUG;
};
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 480da59..82fc08f 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
+ /* Saving M2_N2 registers only for Gen7 because DRRS will be
+* used only from Gen7 and for Gen8 & above there is no
+* M2_N2 register.
+*/
+ if (INTEL_INFO(dev)->gen == 7) {
+ dev_priv->regfile.savePIPEA_DATA_M2 =
+ I915_READ(_PIPEA_DATA_M2);
+ dev_priv->regfile.savePIPEA_DATA_N2 =
+ I915_READ(_PIPEA_DATA_N2);
+ dev_priv->regfile.savePIPEA_LINK_M2 =
+ I915_READ(_PIPEA_LINK_M2);
+ dev_priv->regfile.savePIPEA_LINK_N2 =
+ I915_READ(_PIPEA_LINK_N2);
+ }
+
dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
@@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
+ if (INTEL_INFO(dev)->gen == 7) {
+ I915_WRITE(_PIPEA_DATA_M2,
+ dev_priv->regfile.savePIPEA_DATA_M2);
+ I915_WRITE(_PIPEA_DATA_N2,
+ dev_priv->regfile.savePIPEA_DATA_N2);
+ I915_WRITE(_PIPEA_LINK_M2,
+ dev_priv->regfile.savePIPEA_LINK_M2);
+ I915_WRITE(_PIPEA_LINK_N2,
+ dev_priv->regfile.savePIPEA_LINK_N2);
+ }
+
I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0ad4e96..6784f0b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1587,6 +1587,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->has_dp_encoder = true;
intel_dp_get_m_n(intel_crtc, pipe_config);
+ intel_dp_get_m2_n2(intel_crtc, pipe_config);
break;
default:
break;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/int
[Intel-gfx] [PATCH 1/2] drm/i915: Set M2_N2 registers during mode set
For Gen < 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is supported.
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 30 +++---
drivers/gpu/drm/i915/intel_dp.c | 14 --
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 31 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b0e174..b82f157 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1956,6 +1956,9 @@ struct drm_i915_cmd_table {
#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
#define HAS_RUNTIME_PM(dev)(IS_GEN6(dev) || IS_HASWELL(dev) || \
IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
+#define HAS_DRRS(dev) (to_i915(dev)->drrs.connector && \
+to_i915(dev)->drrs.connector-> \
+panel.downclock_mode)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 767ca96..cf3ad87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5278,6 +5278,18 @@ static void intel_dp_set_m_n(struct intel_crtc *crtc)
intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
}
+void intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
static void vlv_update_pll(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -5872,8 +5884,12 @@ skip_dpll:
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_set_pipe_timings(intel_crtc);
@@ -6881,8 +6897,12 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
} else
intel_put_shared_dpll(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
if (is_lvds && has_reduced_clock && i915.powersave)
intel_crtc->lowfreq_avail = true;
@@ -7377,8 +7397,12 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
return -EINVAL;
intel_ddi_pll_enable(intel_crtc);
- if (intel_crtc->config.has_dp_encoder)
+ if (intel_crtc->config.has_dp_encoder) {
intel_dp_set_m_n(intel_crtc);
+ if (INTEL_INFO(dev)->gen < 8 && HAS_DRRS(dev))
+ intel_dp_set_m2_n2(intel_crtc,
+ &intel_crtc->config.dp_m2_n2);
+ }
intel_crtc->lowfreq_avail = false;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9f67b72..bcab4ea 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -780,20 +780,6 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
-static void
-intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum transcoder transcoder = crtc->config.cpu_transcoder;
-
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
-}
-
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct
Re: [Intel-gfx] [PATCH 2/2] drm/i915: State readout and cross-checking for dp_m2_n2
On May-21-2014 6:03 PM, Daniel Vetter wrote:
> On Wed, May 21, 2014 at 04:40:04PM +0530, Vandana Kannan wrote:
>> Adding relevant read out comparison code, in check_crtc_state, for the new
>> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
>> values for a DP downclock mode (if available). Suggested by Daniel.
>>
>> v2: Changed patch title.
>> Daniel's review comments incorporated.
>> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
>> only when high RR is not in use (This is because alternate m_n register
>> programming will be done only when low RR is being used).
>>
>> v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake.
>> Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures
>> based on DRRS state for gen 8 and above.
>> Save and restore M2 N2 registers for gen 7 and below
>>
>> v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
>> only one set of M_N registers
>>
>> Signed-off-by: Vandana Kannan
>> Cc: Daniel Vetter
>
> Some comments below.
> -Daniel
Thanks for your inputs.
I will resend the patch with all review comments incorporated..
-Vandana
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 8
>> drivers/gpu/drm/i915/i915_ums.c | 26 +++
>> drivers/gpu/drm/i915/intel_ddi.c | 1 +
>> drivers/gpu/drm/i915/intel_display.c | 83
>> +---
>> drivers/gpu/drm/i915/intel_dp.c | 2 +
>> drivers/gpu/drm/i915/intel_drv.h | 2 +
>> 6 files changed, 117 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index b82f157..a06551a 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -815,6 +815,14 @@ struct i915_suspend_saved_registers {
>> u32 savePIPEB_DATA_N1;
>> u32 savePIPEB_LINK_M1;
>> u32 savePIPEB_LINK_N1;
>> +u32 savePIPEA_DATA_M2;
>> +u32 savePIPEA_DATA_N2;
>> +u32 savePIPEA_LINK_M2;
>> +u32 savePIPEA_LINK_N2;
>> +u32 savePIPEB_DATA_M2;
>> +u32 savePIPEB_DATA_N2;
>> +u32 savePIPEB_LINK_M2;
>> +u32 savePIPEB_LINK_N2;
>> u32 saveMCHBAR_RENDER_STANDBY;
>> u32 savePCH_PORT_HOTPLUG;
>> };
>> diff --git a/drivers/gpu/drm/i915/i915_ums.c
>> b/drivers/gpu/drm/i915/i915_ums.c
>> index 480da59..82fc08f 100644
>> --- a/drivers/gpu/drm/i915/i915_ums.c
>> +++ b/drivers/gpu/drm/i915/i915_ums.c
>> @@ -141,6 +141,21 @@ void i915_save_display_reg(struct drm_device *dev)
>> dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
>> dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
>>
>> +/* Saving M2_N2 registers only for Gen7 because DRRS will be
>> + * used only from Gen7 and for Gen8 & above there is no
>> + * M2_N2 register.
>> + */
>> +if (INTEL_INFO(dev)->gen == 7) {
>> +dev_priv->regfile.savePIPEA_DATA_M2 =
>> +I915_READ(_PIPEA_DATA_M2);
>> +dev_priv->regfile.savePIPEA_DATA_N2 =
>> +I915_READ(_PIPEA_DATA_N2);
>> +dev_priv->regfile.savePIPEA_LINK_M2 =
>> +I915_READ(_PIPEA_LINK_M2);
>> +dev_priv->regfile.savePIPEA_LINK_N2 =
>> +I915_READ(_PIPEA_LINK_N2);
>> +}
>> +
>> dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
>> dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
>>
>> @@ -407,6 +422,17 @@ void i915_restore_display_reg(struct drm_device *dev)
>> I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
>> I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
>>
>> +if (INTEL_INFO(dev)->gen == 7) {
>> +I915_WRITE(_PIPEA_DATA_M2,
>> +dev_priv->regfile.savePIPEA_DATA_M2);
>> +I915_WRITE(_PIPEA_DATA_N2,
>> +dev_priv->regfile.savePIPEA_DATA_N2);
>> +I915_WRITE(_PIPEA_LINK_M2,
>> +dev_priv->regfile.savePIPEA_LINK_M2);
>> +
[Intel-gfx] [PATCH v5 2/2] drm/i915: State readout and cross-checking for dp_m2_n2
Adding relevant read out comparison code, in check_crtc_state, for the new
member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
values for a DP downclock mode (if available). Suggested by Daniel.
v2: Changed patch title.
Daniel's review comments incorporated.
Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
only when high RR is not in use (This is because alternate m_n register
programming will be done only when low RR is being used).
v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake.
Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures
based on DRRS state for gen 8 and above.
Save and restore M2 N2 registers for gen 7 and below
v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
only one set of M_N registers
v5: Removed the chunk which saves and restores M2_N2 registers. Modified
get_m_n() to get M2_N2 registers as well. Modified the macro which compares
hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen > 8.
Signed-off-by: Vandana Kannan
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/intel_display.c | 68 +++-
1 file changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index cf3ad87..d593897 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6945,7 +6945,8 @@ static void intel_pch_transcoder_get_m_n(struct
intel_crtc *crtc,
static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
enum transcoder transcoder,
-struct intel_link_m_n *m_n)
+struct intel_link_m_n *m_n,
+struct intel_link_m_n *m2_n2)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6959,6 +6960,15 @@ static void intel_cpu_transcoder_get_m_n(struct
intel_crtc *crtc,
m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ if (m2_n2 && INTEL_INFO(dev)->gen < 8) {
+ m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
+ m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
+ m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
+ & ~TU_SIZE_MASK;
+ m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
+ m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
+ & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
+ }
} else {
m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
@@ -6977,14 +6987,15 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
else
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
-&pipe_config->dp_m_n);
+&pipe_config->dp_m_n,
+&pipe_config->dp_m2_n2);
}
static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
-&pipe_config->fdi_m_n);
+&pipe_config->fdi_m_n, NULL);
}
static void ironlake_get_pfit_config(struct intel_crtc *crtc,
@@ -9485,6 +9496,15 @@ static void intel_dump_pipe_config(struct intel_crtc
*crtc,
pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
pipe_config->dp_m_n.tu);
+
+ DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2:
%u, tu2: %u\n",
+ pipe_config->has_dp_encoder,
+ pipe_config->dp_m2_n2.gmch_m,
+ pipe_config->dp_m2_n2.gmch_n,
+ pipe_config->dp_m2_n2.link_m,
+ pipe_config->dp_m2_n2.link_n,
+ pipe_config->dp_m2_n2.tu);
+
DRM_DEBUG_KMS("requested mode:\n");
drm_mode_debug_printmodeline(&pipe_config->requested_mode);
DRM_DEBUG_KMS("adjusted mode:\n");
@@ -9867,6 +9887,22 @@ intel_pipe_config_compare(struct drm_device *dev,
[Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
Signed-off-by: Vandana Kannan
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_crtc.c | 31 +++
include/drm/drm_crtc.h | 2 ++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 37a3e07..84d359e 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
drm_scaling_mode_enum_list[] =
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
+static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
+ { HDMI_PICTURE_ASPECT_NONE, "Automatic" },
+ { HDMI_PICTURE_ASPECT_4_3, "4:3" },
+ { HDMI_PICTURE_ASPECT_16_9, "16:9" },
+};
+
/*
* Non-global properties, but "required" for certain connectors.
*/
@@ -1344,6 +1350,31 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
/**
+ * drm_mode_create_aspect_ratio_property - create aspect ratio property
+ * @dev: DRM device
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * connectors.
+ */
+int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
+{
+ struct drm_property *aspect_ratio;
+
+ if (dev->mode_config.aspect_ratio_property)
+ return 0;
+
+ aspect_ratio =
+ drm_property_create_enum(dev, 0, "aspect ratio",
+ drm_aspect_ratio_enum_list,
+ ARRAY_SIZE(drm_aspect_ratio_enum_list));
+
+ dev->mode_config.aspect_ratio_property = aspect_ratio;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
+
+/**
* drm_mode_create_dirty_property - create dirty property
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5c1c31c..1149617 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,6 +801,7 @@ struct drm_mode_config {
/* Optional properties */
struct drm_property *scaling_mode_property;
+ struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* dumb ioctl parameters */
@@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int
num_formats,
char *formats[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
+extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
--
1.9.3
___
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[Intel-gfx] [PATCH 2/3] drm/edid: Check for user aspect ratio input
In case user has specified an input for aspect ratio through the property, then the user space value for PAR would take preference over the value from CEA mode list. Signed-off-by: Vandana Kannan Cc: dri-de...@lists.freedesktop.org --- drivers/gpu/drm/drm_edid.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 7a4fd2e..05db619 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3657,8 +3657,13 @@ drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; - /* Populate picture aspect ratio from CEA mode list */ - if (frame->video_code > 0) + /* Populate picture aspect ratio from either CEA mode list or +* user input + */ + if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || + mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) + frame->picture_aspect = mode->picture_aspect_ratio; + else if (frame->video_code > 0) frame->picture_aspect = drm_get_cea_aspect_ratio( frame->video_code); -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Add aspect ratio property for HDMI
Create and attach the drm property to set aspect ratio. If there is no user
specified value, then PAR_NONE/Automatic option is set by default. User can
select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would
come into effect with a mode set.
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
3 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 13495a4..8dc5f59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2691,6 +2691,11 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
int val);
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
+/* Aspect ratio property */
+#define INTEL_ASPECT_RATIO_AUTO 0
+#define INTEL_ASPECT_RATIO_4_3 1
+#define INTEL_ASPECT_RATIO_16_9 2
+
static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
{
if (HAS_PCH_SPLIT(dev))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 287b89e..f9f19b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -488,6 +488,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 171d0dd..2c6aa76 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
adjusted_mode);
if (ret < 0) {
@@ -1124,6 +1127,23 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == connector->dev->mode_config.aspect_ratio_property) {
+ switch (val) {
+ case INTEL_ASPECT_RATIO_AUTO:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+ break;
+ case INTEL_ASPECT_RATIO_4_3:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
+ break;
+ case INTEL_ASPECT_RATIO_16_9:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
+ break;
+ default:
+ return -EINVAL;
+ }
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1416,11 +1436,22 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
};
static void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ drm_mode_create_aspect_ratio_property(connector->dev);
+ drm_object_attach_property(&connector->base,
+ connector->dev->mode_config.aspect_ratio_property,
+ HDMI_PICTURE_ASPECT_NONE);
+}
+
+static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_hdmi->color_range_auto = true;
+ intel_attach_aspect_ratio_property(connector);
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
}
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
--
1.9.3
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add aspect ratio property for HDMI
Adding dri-devel..
On May-22-2014 4:50 PM, Kannan, Vandana wrote:
> Create and attach the drm property to set aspect ratio. If there is no user
> specified value, then PAR_NONE/Automatic option is set by default. User can
> select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would
> come into effect with a mode set.
>
> Signed-off-by: Vandana Kannan
> ---
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
> 3 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 13495a4..8dc5f59 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2691,6 +2691,11 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
> int val);
> #define INTEL_BROADCAST_RGB_FULL 1
> #define INTEL_BROADCAST_RGB_LIMITED 2
>
> +/* Aspect ratio property */
> +#define INTEL_ASPECT_RATIO_AUTO 0
> +#define INTEL_ASPECT_RATIO_4_3 1
> +#define INTEL_ASPECT_RATIO_16_9 2
> +
> static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
> {
> if (HAS_PCH_SPLIT(dev))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 287b89e..f9f19b6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -488,6 +488,7 @@ struct intel_hdmi {
> bool has_audio;
> enum hdmi_force_audio force_audio;
> bool rgb_quant_range_selectable;
> + enum hdmi_picture_aspect aspect_ratio;
> void (*write_infoframe)(struct drm_encoder *encoder,
> enum hdmi_infoframe_type type,
> const void *frame, ssize_t len);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 171d0dd..2c6aa76 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct
> drm_encoder *encoder,
> union hdmi_infoframe frame;
> int ret;
>
> + /* Set user selected PAR to incoming mode's member */
> + adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
> +
> ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
> adjusted_mode);
> if (ret < 0) {
> @@ -1124,6 +1127,23 @@ intel_hdmi_set_property(struct drm_connector
> *connector,
> goto done;
> }
>
> + if (property == connector->dev->mode_config.aspect_ratio_property) {
> + switch (val) {
> + case INTEL_ASPECT_RATIO_AUTO:
> + intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> + break;
> + case INTEL_ASPECT_RATIO_4_3:
> + intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
> + break;
> + case INTEL_ASPECT_RATIO_16_9:
> + intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
> + break;
> + default:
> + return -EINVAL;
> + }
> + goto done;
> + }
> +
> return -EINVAL;
>
> done:
> @@ -1416,11 +1436,22 @@ static const struct drm_encoder_funcs
> intel_hdmi_enc_funcs = {
> };
>
> static void
> +intel_attach_aspect_ratio_property(struct drm_connector *connector)
> +{
> + drm_mode_create_aspect_ratio_property(connector->dev);
> + drm_object_attach_property(&connector->base,
> + connector->dev->mode_config.aspect_ratio_property,
> + HDMI_PICTURE_ASPECT_NONE);
> +}
> +
> +static void
> intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct
> drm_connector *connector)
> {
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
> intel_hdmi->color_range_auto = true;
> + intel_attach_aspect_ratio_property(connector);
> + intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> }
>
> void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>
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Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio
On May-22-2014 5:08 PM, Thierry Reding wrote:
> On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
>> Added a property to enable user space to set aspect ratio.
>> This patch contains declaration of the property and code to create the
>> property.
>>
>> Signed-off-by: Vandana Kannan
>> Cc: dri-de...@lists.freedesktop.org
>> ---
>> drivers/gpu/drm/drm_crtc.c | 31 +++
>> include/drm/drm_crtc.h | 2 ++
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
>> index 37a3e07..84d359e 100644
>> --- a/drivers/gpu/drm/drm_crtc.c
>> +++ b/drivers/gpu/drm/drm_crtc.c
>> @@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
>> drm_scaling_mode_enum_list[] =
>> { DRM_MODE_SCALE_ASPECT, "Full aspect" },
>> };
>>
>> +static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
>> +{ HDMI_PICTURE_ASPECT_NONE, "Automatic" },
>> +{ HDMI_PICTURE_ASPECT_4_3, "4:3" },
>> +{ HDMI_PICTURE_ASPECT_16_9, "16:9" },
>> +};
>
> This seems like it should be either an HDMI specific property, since it
> uses values defined by HDMI/CEA. Alternatively we could introduce some
> new generic enumeration and translate that to the HDMI/CEA equivalent in
> the AVI infoframe helpers.
>
> Doing so would allow us to add aspect ratios different from what HDMI or
> CEA define.
>
>> /*
>> * Non-global properties, but "required" for certain connectors.
>> */
>> @@ -1344,6 +1350,31 @@ int drm_mode_create_scaling_mode_property(struct
>> drm_device *dev)
>> EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
>>
>> /**
>> + * drm_mode_create_aspect_ratio_property - create aspect ratio property
>> + * @dev: DRM device
>> + *
>> + * Called by a driver the first time it's needed, must be attached to
>> desired
>> + * connectors.
>> + */
>> +int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
>> +{
>> +struct drm_property *aspect_ratio;
>> +
>> +if (dev->mode_config.aspect_ratio_property)
>> +return 0;
>> +
>> +aspect_ratio =
>> +drm_property_create_enum(dev, 0, "aspect ratio",
>> +drm_aspect_ratio_enum_list,
>> +ARRAY_SIZE(drm_aspect_ratio_enum_list));
>> +
>> +dev->mode_config.aspect_ratio_property = aspect_ratio;
>
> I don't think you need the temporary aspect_ratio variable here. Can't
> you directly assign the new property to .aspect_ratio_property?
>
> Thierry
>
Thanks for your inputs.
I will make the following changes and resend the patch..
- Make the enum generic and translate that to the HDMI/CEA equivalent
for AVI IF.
- Remove the temporary aspect_ratio variable.
Thanks,
Vandana
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Re: [Intel-gfx] [PATCH 2/3] drm/edid: Check for user aspect ratio input
On May-22-2014 5:12 PM, Thierry Reding wrote: > On Thu, May 22, 2014 at 04:50:49PM +0530, Vandana Kannan wrote: >> In case user has specified an input for aspect ratio through the property, >> then the user space value for PAR would take preference over the value from >> CEA mode list. >> >> Signed-off-by: Vandana Kannan >> Cc: dri-de...@lists.freedesktop.org >> --- >> drivers/gpu/drm/drm_edid.c | 9 +++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c >> index 7a4fd2e..05db619 100644 >> --- a/drivers/gpu/drm/drm_edid.c >> +++ b/drivers/gpu/drm/drm_edid.c >> @@ -3657,8 +3657,13 @@ drm_hdmi_avi_infoframe_from_display_mode(struct >> hdmi_avi_infoframe *frame, >> >> frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; >> >> -/* Populate picture aspect ratio from CEA mode list */ >> -if (frame->video_code > 0) >> +/* Populate picture aspect ratio from either CEA mode list or >> + * user input >> +*/ > > This comment is mangled, it should look like this: > > /* >* Populate... >*/ > > And perhaps to clarify that user input takes precedence over CEA you > could list it first in the comment, like so for example: > > /* >* Populate picture aspect ratio from either user input (if specified) >* or from the CEA mode. >*/ > Sure, I will modify this comment > Also can you please resend patch 3/3 to dri-de...@lists.freedesktop.org > as well so we can see how this is used in a driver? > > Thierry > I have resent this patch including dri-de...@lists.freedesktop.org Thanks, Vandana ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio
On May-22-2014 5:46 PM, Daniel Vetter wrote:
> On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
>> Added a property to enable user space to set aspect ratio.
>> This patch contains declaration of the property and code to create the
>> property.
>>
>> Signed-off-by: Vandana Kannan
>> Cc: dri-de...@lists.freedesktop.org
>
> Documentation update is missing. Also for such patch series I recommend to
> post the entire patch series to dri-devel and intel-gfx. Otherwise people
> on dri-devel don't see how the new code is used and so can't really review
> it properly.
> -Daniel
>
Thanks for your inputs.
I will send the Documentation change along with the rest of the patches
(when I resend them).
Resent patch 3 adding dri-devel..
Thanks,
Vandana
>> ---
>> drivers/gpu/drm/drm_crtc.c | 31 +++
>> include/drm/drm_crtc.h | 2 ++
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
>> index 37a3e07..84d359e 100644
>> --- a/drivers/gpu/drm/drm_crtc.c
>> +++ b/drivers/gpu/drm/drm_crtc.c
>> @@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
>> drm_scaling_mode_enum_list[] =
>> { DRM_MODE_SCALE_ASPECT, "Full aspect" },
>> };
>>
>> +static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
>> +{ HDMI_PICTURE_ASPECT_NONE, "Automatic" },
>> +{ HDMI_PICTURE_ASPECT_4_3, "4:3" },
>> +{ HDMI_PICTURE_ASPECT_16_9, "16:9" },
>> +};
>> +
>> /*
>> * Non-global properties, but "required" for certain connectors.
>> */
>> @@ -1344,6 +1350,31 @@ int drm_mode_create_scaling_mode_property(struct
>> drm_device *dev)
>> EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
>>
>> /**
>> + * drm_mode_create_aspect_ratio_property - create aspect ratio property
>> + * @dev: DRM device
>> + *
>> + * Called by a driver the first time it's needed, must be attached to
>> desired
>> + * connectors.
>> + */
>> +int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
>> +{
>> +struct drm_property *aspect_ratio;
>> +
>> +if (dev->mode_config.aspect_ratio_property)
>> +return 0;
>> +
>> +aspect_ratio =
>> +drm_property_create_enum(dev, 0, "aspect ratio",
>> +drm_aspect_ratio_enum_list,
>> +ARRAY_SIZE(drm_aspect_ratio_enum_list));
>> +
>> +dev->mode_config.aspect_ratio_property = aspect_ratio;
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
>> +
>> +/**
>> * drm_mode_create_dirty_property - create dirty property
>> * @dev: DRM device
>> *
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index 5c1c31c..1149617 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -801,6 +801,7 @@ struct drm_mode_config {
>>
>> /* Optional properties */
>> struct drm_property *scaling_mode_property;
>> +struct drm_property *aspect_ratio_property;
>> struct drm_property *dirty_info_property;
>>
>> /* dumb ioctl parameters */
>> @@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
>> drm_device *dev);
>> extern int drm_mode_create_tv_properties(struct drm_device *dev, int
>> num_formats,
>> char *formats[]);
>> extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
>> +extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
>> extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
>> extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
>>
>> --
>> 1.9.3
>>
>> ___
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>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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Re: [Intel-gfx] [PATCH 1/3] drm/crtc: Add property for aspect ratio
On May-23-2014 4:18 PM, Vandana Kannan wrote:
> On May-22-2014 5:46 PM, Daniel Vetter wrote:
>> On Thu, May 22, 2014 at 04:50:48PM +0530, Vandana Kannan wrote:
>>> Added a property to enable user space to set aspect ratio.
>>> This patch contains declaration of the property and code to create the
>>> property.
>>>
>>> Signed-off-by: Vandana Kannan
>>> Cc: dri-de...@lists.freedesktop.org
>>
>> Documentation update is missing. Also for such patch series I recommend to
>> post the entire patch series to dri-devel and intel-gfx. Otherwise people
>> on dri-devel don't see how the new code is used and so can't really review
>> it properly.
>> -Daniel
>>
> Thanks for your inputs.
> I will send the Documentation change along with the rest of the patches
> (when I resend them).
> Resent patch 3 adding dri-devel..
>
> Thanks,
> Vandana
Hi Daniel,
For the Documentation update, should HTML table format be used in
drm.tmpl or is there some other method?
-Vandana
>>> ---
>>> drivers/gpu/drm/drm_crtc.c | 31 +++
>>> include/drm/drm_crtc.h | 2 ++
>>> 2 files changed, 33 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
>>> index 37a3e07..84d359e 100644
>>> --- a/drivers/gpu/drm/drm_crtc.c
>>> +++ b/drivers/gpu/drm/drm_crtc.c
>>> @@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
>>> drm_scaling_mode_enum_list[] =
>>> { DRM_MODE_SCALE_ASPECT, "Full aspect" },
>>> };
>>>
>>> +static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
>>> + { HDMI_PICTURE_ASPECT_NONE, "Automatic" },
>>> + { HDMI_PICTURE_ASPECT_4_3, "4:3" },
>>> + { HDMI_PICTURE_ASPECT_16_9, "16:9" },
>>> +};
>>> +
>>> /*
>>> * Non-global properties, but "required" for certain connectors.
>>> */
>>> @@ -1344,6 +1350,31 @@ int drm_mode_create_scaling_mode_property(struct
>>> drm_device *dev)
>>> EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
>>>
>>> /**
>>> + * drm_mode_create_aspect_ratio_property - create aspect ratio property
>>> + * @dev: DRM device
>>> + *
>>> + * Called by a driver the first time it's needed, must be attached to
>>> desired
>>> + * connectors.
>>> + */
>>> +int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
>>> +{
>>> + struct drm_property *aspect_ratio;
>>> +
>>> + if (dev->mode_config.aspect_ratio_property)
>>> + return 0;
>>> +
>>> + aspect_ratio =
>>> + drm_property_create_enum(dev, 0, "aspect ratio",
>>> + drm_aspect_ratio_enum_list,
>>> + ARRAY_SIZE(drm_aspect_ratio_enum_list));
>>> +
>>> + dev->mode_config.aspect_ratio_property = aspect_ratio;
>>> +
>>> + return 0;
>>> +}
>>> +EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
>>> +
>>> +/**
>>> * drm_mode_create_dirty_property - create dirty property
>>> * @dev: DRM device
>>> *
>>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>>> index 5c1c31c..1149617 100644
>>> --- a/include/drm/drm_crtc.h
>>> +++ b/include/drm/drm_crtc.h
>>> @@ -801,6 +801,7 @@ struct drm_mode_config {
>>>
>>> /* Optional properties */
>>> struct drm_property *scaling_mode_property;
>>> + struct drm_property *aspect_ratio_property;
>>> struct drm_property *dirty_info_property;
>>>
>>> /* dumb ioctl parameters */
>>> @@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
>>> drm_device *dev);
>>> extern int drm_mode_create_tv_properties(struct drm_device *dev, int
>>> num_formats,
>>> char *formats[]);
>>> extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
>>> +extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
>>> extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
>>> extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
>>>
>>> --
>>> 1.9.3
>>>
>>> ___
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>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>
> ___
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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[Intel-gfx] [PATCH v2 1/4] drm/crtc: Add property for aspect ratio
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
v2: Thierry's review comments.
- Made aspect ratio enum generic instead of HDMI/CEA specfic
- Removed usage of temporary aspect_ratio variable
Signed-off-by: Vandana Kannan
Cc: Thierry Reding
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_crtc.c | 27 +++
include/drm/drm_crtc.h | 2 ++
include/uapi/drm/drm_mode.h | 5 +
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 37a3e07..3085c34 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
drm_scaling_mode_enum_list[] =
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
+static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
+ { DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
+ { DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
+ { DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
+};
+
/*
* Non-global properties, but "required" for certain connectors.
*/
@@ -1344,6 +1350,27 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
/**
+ * drm_mode_create_aspect_ratio_property - create aspect ratio property
+ * @dev: DRM device
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * connectors.
+ */
+int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
+{
+ if (dev->mode_config.aspect_ratio_property)
+ return 0;
+
+ dev->mode_config.aspect_ratio_property =
+ drm_property_create_enum(dev, 0, "aspect ratio",
+ drm_aspect_ratio_enum_list,
+ ARRAY_SIZE(drm_aspect_ratio_enum_list));
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
+
+/**
* drm_mode_create_dirty_property - create dirty property
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5c1c31c..1149617 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,6 +801,7 @@ struct drm_mode_config {
/* Optional properties */
struct drm_property *scaling_mode_property;
+ struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* dumb ioctl parameters */
@@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int
num_formats,
char *formats[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
+extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index f104c26..943b377 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -88,6 +88,11 @@
#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
+/* Picture aspect ratio options */
+#define DRM_MODE_PICTURE_ASPECT_NONE 0
+#define DRM_MODE_PICTURE_ASPECT_4_31
+#define DRM_MODE_PICTURE_ASPECT_16_9 2
+
/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF 0
#define DRM_MODE_DITHERING_ON 1
--
1.9.3
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[Intel-gfx] [PATCH v2 2/4] drm/edid: Check for user aspect ratio input
In case user has specified an input for aspect ratio through the property, then the user space value for PAR would take preference over the value from CEA mode list. v2: Thierry's review comments. - Modified the comment "Populate..." as per review comments Signed-off-by: Vandana Kannan Cc: Thierry Reding Cc: Daniel Vetter --- drivers/gpu/drm/drm_edid.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 7a4fd2e..2628dd1 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3657,8 +3657,13 @@ drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; - /* Populate picture aspect ratio from CEA mode list */ - if (frame->video_code > 0) + /* Populate picture aspect ratio from either user input (if specified) +* or from the CEA mode list +*/ + if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || + mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) + frame->picture_aspect = mode->picture_aspect_ratio; + else if (frame->video_code > 0) frame->picture_aspect = drm_get_cea_aspect_ratio( frame->video_code); -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/4] drm/i915: Add aspect ratio property for HDMI
Create and attach the drm property to set aspect ratio. If there is no user
specified value, then PAR_NONE/Automatic option is set by default. User can
select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would
come into effect with a mode set.
v2: Modifications made based on changes to aspect ratio enum list.
Signed-off-by: Vandana Kannan
Cc: Thierry Reding
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 287b89e..f9f19b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -488,6 +488,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 171d0dd..34ab689 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
adjusted_mode);
if (ret < 0) {
@@ -1124,6 +1127,23 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == connector->dev->mode_config.aspect_ratio_property) {
+ switch (val) {
+ case DRM_MODE_PICTURE_ASPECT_NONE:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+ break;
+ case DRM_MODE_PICTURE_ASPECT_4_3:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
+ break;
+ case DRM_MODE_PICTURE_ASPECT_16_9:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
+ break;
+ default:
+ return -EINVAL;
+ }
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1416,11 +1436,22 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
};
static void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ drm_mode_create_aspect_ratio_property(connector->dev);
+ drm_object_attach_property(&connector->base,
+ connector->dev->mode_config.aspect_ratio_property,
+ DRM_MODE_PICTURE_ASPECT_NONE);
+}
+
+static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_hdmi->color_range_auto = true;
+ intel_attach_aspect_ratio_property(connector);
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
}
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
--
1.9.3
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[Intel-gfx] [PATCH 4/4] Documentation/drm: Describing aspect ratio property
Updated drm documentation to include description of aspect ratio property.
HTML table structure created by Sagar Kamble.
Signed-off-by: Vandana Kannan
Cc: Sagar Kamble
Cc: Daniel Vetter
Cc: Thierry Reding
---
Documentation/DocBook/drm.tmpl | 31 +++
1 file changed, 31 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 9574bf2..6e2c36f 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2442,6 +2442,37 @@ void intel_crt_init(struct drm_device *dev)
pointer to the target object, a pointer to the previously created
property
and an initial instance value.
+
+ Existing KMS Properties
+
+ The following table gives description of drm properties exposed by
various
+ modules/drivers.
+
+
+
+
+ Owner Module/Drivers
+ Group
+ Property Name
+ Type
+ Property Values
+ Object attached
+ Description/Restrictions
+
+
+ DRM
+ Generic
+ Aspect Ratio
+ ENUM
+ { "None", "4:3", "16:9" }
+ Connector
+ DRM property to set aspect ratio from user space.
+ This enum is made generic to allow addition of custom aspect
+ ratios.
+
+
+
+
--
1.9.3
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Re: [Intel-gfx] [PATCH v5 2/2] drm/i915: State readout and cross-checking for dp_m2_n2
Hi Daniel,
Please let me know if this patch
(http://lists.freedesktop.org/archives/intel-gfx/2014-May/045877.html)
and the patch
http://lists.freedesktop.org/archives/intel-gfx/2014-May/045804.html
require any other changes..
I have included all your review comments till date..
Thanks,
Vandana
On May-22-2014 12:18 PM, Kannan, Vandana wrote:
> Adding relevant read out comparison code, in check_crtc_state, for the new
> member of crtc_config, dp_m2_n2, which was introduced to store link_m_n
> values for a DP downclock mode (if available). Suggested by Daniel.
>
> v2: Changed patch title.
> Daniel's review comments incorporated.
> Added relevant state readout code for M2_N2. dp_m2_n2 comparison to be done
> only when high RR is not in use (This is because alternate m_n register
> programming will be done only when low RR is being used).
>
> v3: Modified call to get_m2_n2 which had dp_m_n as param by mistake.
> Compare dp_m_n and dp_m2_n2 for gen 7 and below. compare the structures
> based on DRRS state for gen 8 and above.
> Save and restore M2 N2 registers for gen 7 and below
>
> v4: For Gen>=8, check M_N registers against dp_m_n and dp_m2_n2 as there is
> only one set of M_N registers
>
> v5: Removed the chunk which saves and restores M2_N2 registers. Modified
> get_m_n() to get M2_N2 registers as well. Modified the macro which compares
> hw.dp_m_n against sw.dp_m2_n2/sw.dp_m_n for gen > 8.
>
> Signed-off-by: Vandana Kannan
> Cc: Daniel Vetter
> ---
> drivers/gpu/drm/i915/intel_display.c | 68
> +++-
> 1 file changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cf3ad87..d593897 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6945,7 +6945,8 @@ static void intel_pch_transcoder_get_m_n(struct
> intel_crtc *crtc,
>
> static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
>enum transcoder transcoder,
> - struct intel_link_m_n *m_n)
> + struct intel_link_m_n *m_n,
> + struct intel_link_m_n *m2_n2)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6959,6 +6960,15 @@ static void intel_cpu_transcoder_get_m_n(struct
> intel_crtc *crtc,
> m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
> m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
> & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> + if (m2_n2 && INTEL_INFO(dev)->gen < 8) {
> + m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
> + m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
> + m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
> + & ~TU_SIZE_MASK;
> + m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
> + m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
> + & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
> + }
> } else {
> m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
> m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
> @@ -6977,14 +6987,15 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
> else
> intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> - &pipe_config->dp_m_n);
> + &pipe_config->dp_m_n,
> + &pipe_config->dp_m2_n2);
> }
>
> static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
> struct intel_crtc_config *pipe_config)
> {
> intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
> - &pipe_config->fdi_m_n);
> + &pipe_config->fdi_m_n, NULL);
> }
>
> static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> @@ -9485,6 +9496,15 @@ static void intel_dump_pipe_config(struct intel_crtc
> *crtc,
> pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
> pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
> pipe_config->dp_m_n
[Intel-gfx] [PATCH v3 1/4] drm/crtc: Add property for aspect ratio
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
v2: Thierry's review comments.
- Made aspect ratio enum generic instead of HDMI/CEA specfic
- Removed usage of temporary aspect_ratio variable
v3: Thierry's review comments.
- Fixed indentation drm_mode_create_aspect_ratio_property()
Signed-off-by: Vandana Kannan
Cc: Thierry Reding
---
drivers/gpu/drm/drm_crtc.c | 27 +++
include/drm/drm_crtc.h | 2 ++
include/uapi/drm/drm_mode.h | 5 +
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 37a3e07..dcbc033 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
drm_scaling_mode_enum_list[] =
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
+static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
+ { DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
+ { DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
+ { DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
+};
+
/*
* Non-global properties, but "required" for certain connectors.
*/
@@ -1344,6 +1350,27 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
/**
+ * drm_mode_create_aspect_ratio_property - create aspect ratio property
+ * @dev: DRM device
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * connectors.
+ */
+int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
+{
+ if (dev->mode_config.aspect_ratio_property)
+ return 0;
+
+ dev->mode_config.aspect_ratio_property =
+ drm_property_create_enum(dev, 0, "aspect ratio",
+ drm_aspect_ratio_enum_list,
+ ARRAY_SIZE(drm_aspect_ratio_enum_list));
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
+
+/**
* drm_mode_create_dirty_property - create dirty property
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5c1c31c..1149617 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,6 +801,7 @@ struct drm_mode_config {
/* Optional properties */
struct drm_property *scaling_mode_property;
+ struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* dumb ioctl parameters */
@@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int
num_formats,
char *formats[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
+extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index f104c26..943b377 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -88,6 +88,11 @@
#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
+/* Picture aspect ratio options */
+#define DRM_MODE_PICTURE_ASPECT_NONE 0
+#define DRM_MODE_PICTURE_ASPECT_4_31
+#define DRM_MODE_PICTURE_ASPECT_16_9 2
+
/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF 0
#define DRM_MODE_DITHERING_ON 1
--
1.9.3
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[Intel-gfx] [PATCH v3 2/4] drm/edid: Check for user aspect ratio input
In case user has specified an input for aspect ratio through the property, then the user space value for PAR would take preference over the value from CEA mode list. v2: Thierry's review comments. - Modified the comment "Populate..." as per review comments v3: Thierry's review comments. - Modified the comment to block comment format. Signed-off-by: Vandana Kannan Cc: Thierry Reding --- drivers/gpu/drm/drm_edid.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 7a4fd2e..e76c58c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3657,8 +3657,14 @@ drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; - /* Populate picture aspect ratio from CEA mode list */ - if (frame->video_code > 0) + /* +* Populate picture aspect ratio from either +* user input (if specified) or from the CEA mode list. +*/ + if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || + mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) + frame->picture_aspect = mode->picture_aspect_ratio; + else if (frame->video_code > 0) frame->picture_aspect = drm_get_cea_aspect_ratio( frame->video_code); -- 1.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 1/4] drm/crtc: Add property for aspect ratio
On Jun-05-2014 2:58 PM, Thierry Reding wrote:
> On Thu, Jun 05, 2014 at 02:40:08PM +0530, Vandana Kannan wrote:
> [...]
>> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> [...]
>> /**
>> + * drm_mode_create_aspect_ratio_property - create aspect ratio property
>> + * @dev: DRM device
>> + *
>> + * Called by a driver the first time it's needed, must be attached to
>> desired
>> + * connectors.
>> + */
>> +int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
>> +{
>> +if (dev->mode_config.aspect_ratio_property)
>> +return 0;
>> +
>> +dev->mode_config.aspect_ratio_property =
>> +drm_property_create_enum(dev, 0, "aspect ratio",
>> +drm_aspect_ratio_enum_list,
>> +ARRAY_SIZE(drm_aspect_ratio_enum_list));
>> +
>> +return 0;
>
> Sorry for not noticing this before: what if drm_propert_create_enum()
> fails? Should that return an error? This function will currently
> silently ignore failure to create the property.
>
> Thierry
>
Yes..
I can
1. modify this to return the property (which would be NULL if create
fails) and have a NULL check at the calling end or
2. have a NULL check for the property at the calling end keeping the
existing implementation or
3. return a non-zero value in case of failure.
Please let me know your inputs on this..
- Vandana
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[Intel-gfx] [PATCH v4 1/4] drm/crtc: Add property for aspect ratio
Added a property to enable user space to set aspect ratio.
This patch contains declaration of the property and code to create the
property.
v2: Thierry's review comments.
- Made aspect ratio enum generic instead of HDMI/CEA specfic
- Removed usage of temporary aspect_ratio variable
v3: Thierry's review comments.
- Fixed indentation
v4: Thierry's review comments.
- Return ENOMEM when property creation fails
Signed-off-by: Vandana Kannan
Cc: Thierry Reding
---
drivers/gpu/drm/drm_crtc.c | 33 +
include/drm/drm_crtc.h | 2 ++
include/uapi/drm/drm_mode.h | 5 +
3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 37a3e07..a745df3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -139,6 +139,12 @@ static const struct drm_prop_enum_list
drm_scaling_mode_enum_list[] =
{ DRM_MODE_SCALE_ASPECT, "Full aspect" },
};
+static const struct drm_prop_enum_list drm_aspect_ratio_enum_list[] = {
+ { DRM_MODE_PICTURE_ASPECT_NONE, "Automatic" },
+ { DRM_MODE_PICTURE_ASPECT_4_3, "4:3" },
+ { DRM_MODE_PICTURE_ASPECT_16_9, "16:9" },
+};
+
/*
* Non-global properties, but "required" for certain connectors.
*/
@@ -1344,6 +1350,33 @@ int drm_mode_create_scaling_mode_property(struct
drm_device *dev)
EXPORT_SYMBOL(drm_mode_create_scaling_mode_property);
/**
+ * drm_mode_create_aspect_ratio_property - create aspect ratio property
+ * @dev: DRM device
+ *
+ * Called by a driver the first time it's needed, must be attached to desired
+ * connectors.
+ *
+ * Returns:
+ * Zero on success, errno on failure.
+ */
+int drm_mode_create_aspect_ratio_property(struct drm_device *dev)
+{
+ if (dev->mode_config.aspect_ratio_property)
+ return 0;
+
+ dev->mode_config.aspect_ratio_property =
+ drm_property_create_enum(dev, 0, "aspect ratio",
+ drm_aspect_ratio_enum_list,
+ ARRAY_SIZE(drm_aspect_ratio_enum_list));
+
+ if (dev->mode_config.aspect_ratio_property == NULL)
+ return -ENOMEM;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_mode_create_aspect_ratio_property);
+
+/**
* drm_mode_create_dirty_property - create dirty property
* @dev: DRM device
*
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5c1c31c..1149617 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,6 +801,7 @@ struct drm_mode_config {
/* Optional properties */
struct drm_property *scaling_mode_property;
+ struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* dumb ioctl parameters */
@@ -971,6 +972,7 @@ extern int drm_mode_create_dvi_i_properties(struct
drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int
num_formats,
char *formats[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
+extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern const char *drm_get_encoder_name(const struct drm_encoder *encoder);
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index f104c26..943b377 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -88,6 +88,11 @@
#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
+/* Picture aspect ratio options */
+#define DRM_MODE_PICTURE_ASPECT_NONE 0
+#define DRM_MODE_PICTURE_ASPECT_4_31
+#define DRM_MODE_PICTURE_ASPECT_16_9 2
+
/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF 0
#define DRM_MODE_DITHERING_ON 1
--
1.9.3
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[Intel-gfx] [PATCH v3 3/4] drm/i915: Add aspect ratio property for HDMI
Create and attach the drm property to set aspect ratio. If there is no user
specified value, then PAR_NONE/Automatic option is set by default. User can
select aspect ratio 4:3 or 16:9. The aspect ratio selected by user would
come into effect with a mode set.
v2: Modified switch case to include aspect ratio enum changes
v3: Modified the patch according the change in the earlier patch to return
errno in case property creation fails. With this change, property will be
attached only if creation is successful
Signed-off-by: Vandana Kannan
Cc: Thierry Reding
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 31 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 287b89e..f9f19b6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -488,6 +488,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 171d0dd..056409c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
adjusted_mode);
if (ret < 0) {
@@ -1124,6 +1127,23 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == connector->dev->mode_config.aspect_ratio_property) {
+ switch (val) {
+ case DRM_MODE_PICTURE_ASPECT_NONE:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+ break;
+ case DRM_MODE_PICTURE_ASPECT_4_3:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
+ break;
+ case DRM_MODE_PICTURE_ASPECT_16_9:
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
+ break;
+ default:
+ return -EINVAL;
+ }
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1416,11 +1436,22 @@ static const struct drm_encoder_funcs
intel_hdmi_enc_funcs = {
};
static void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ if (!drm_mode_create_aspect_ratio_property(connector->dev))
+ drm_object_attach_property(&connector->base,
+ connector->dev->mode_config.aspect_ratio_property,
+ DRM_MODE_PICTURE_ASPECT_NONE);
+}
+
+static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector
*connector)
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
intel_hdmi->color_range_auto = true;
+ intel_attach_aspect_ratio_property(connector);
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
}
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
--
1.9.3
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[Intel-gfx] [PATCH v2 4/4] Documentation/drm: Describing aspect ratio property
Updated drm documentation to include desscription of aspect ratio property.
v2: Updated aspect ratio specific documentation on top of the HTML table
created.
Signed-off-by: Vandana Kannan
Cc: Sagar Kamble
Cc: Daniel Vetter
---
Documentation/DocBook/drm.tmpl | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7df3134..3e98151 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2502,7 +2502,7 @@ void intel_crt_init(struct drm_device *dev)
Description/Restrictions
- DRM
+ DRM
Generic
“EDID”
BLOB | IMMUTABLE
@@ -2633,7 +2633,7 @@ void intel_crt_init(struct drm_device *dev)
TBD
- Optional
+ Optional
“scaling mode”
ENUM
{ "None", "Full", "Center", "Full aspect" }
@@ -2641,6 +2641,15 @@ void intel_crt_init(struct drm_device *dev)
TBD
+ "aspect ratio"
+ ENUM
+ { "None", "4:3", "16:9" }
+ Connector
+ DRM property to set aspect ratio from user space app.
+ This enum is made generic to allow addition of custom aspect
+ ratios.
+
+
“dirty”
ENUM | IMMUTABLE
{ "Off", "On", "Annotate" }
--
1.9.3
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[Intel-gfx] [PATCH] drm/i915: Initialize downclock mode in panel init
Instead of modifying intel_panel in lvds_init_connector/dsi_init_connector/
edp_init_connector, making changes to move intel_panel->downclock_mode
initialization to intel_panel_init()
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_dp.c|3 ++-
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |3 ++-
drivers/gpu/drm/i915/intel_lvds.c | 10 +-
drivers/gpu/drm/i915/intel_panel.c |4 +++-
5 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f1ef3d4..404d0f0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3675,6 +3675,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
@@ -3732,7 +3733,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
}
- intel_panel_init(&intel_connector->panel, fixed_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
intel_panel_setup_backlight(connector);
return true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44067bc..6aa549a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -824,7 +824,8 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
/* intel_panel.c */
int intel_panel_init(struct intel_panel *panel,
-struct drm_display_mode *fixed_mode);
+struct drm_display_mode *fixed_mode,
+struct drm_display_mode *downclock_mode);
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fabbf0d..73e6a44 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -550,6 +550,7 @@ bool intel_dsi_init(struct drm_device *dev)
struct intel_connector *intel_connector;
struct drm_connector *connector;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
const struct intel_dsi_device *dsi;
unsigned int i;
@@ -624,7 +625,7 @@ bool intel_dsi_init(struct drm_device *dev)
}
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
- intel_panel_init(&intel_connector->panel, fixed_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
return true;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 3f3043b..6341a88 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -899,6 +899,7 @@ void intel_lvds_init(struct drm_device *dev)
struct drm_encoder *encoder;
struct drm_display_mode *scan; /* *modes, *bios_mode; */
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
struct edid *edid;
struct drm_crtc *crtc;
u32 lvds;
@@ -1032,15 +1033,14 @@ void intel_lvds_init(struct drm_device *dev)
fixed_mode = drm_mode_duplicate(dev, scan);
if (fixed_mode) {
- intel_connector->panel.downclock_mode =
+ downclock_mode =
intel_find_panel_downclock(dev,
fixed_mode, connector);
- if (intel_connector->panel.downclock_mode !=
- NULL && i915.lvds_downclock) {
+ if (downclock_mode != NULL &&
+ i915.lvds_downclock) {
/* We found the downclock for LVDS. */
dev_priv->lvds_downclock_avail = true;
dev_priv->lvds_downclock =
- intel_connector->panel.
downclock_mode->clock;
DRM_DEBUG_KMS("LVDS downclock is found"
" in EDID. Normal clock %dKhz, "
@@ -1116,7 +1116,7 @@ out:
}
drm_sysfs_connector_add(conn
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Parse EDID probed modes for DRRS support
On Jan-30-2014 9:03 AM, Vandana Kannan wrote:
> On Jan-22-2014 7:03 PM, Jani Nikula wrote:
>> On Mon, 23 Dec 2013, Vandana Kannan wrote:
>>> From: Pradeep Bhat
>>>
>>> This patch and finds out the lowest refresh rate supported for the
>>> resolution
>>> same as the fixed_mode, based on the implementaion find_panel_downclock.
>>> It also checks the VBT fields to see if panel supports seamless DRRS or not.
>>> Based on above data it marks whether eDP panel supports seamless DRRS or
>>> not.
>>> This information is needed for supporting seamless DRRS switch for certain
>>> power saving usecases. This patch is tested by enabling the DRM logs and
>>> user should see whether Seamless DRRS is supported or not.
>>
>> This patch (and therefore the later patches) no longer apply to
>> drm-intel-nightly. It might affect my review a bit, but here goes
>> anyway.
>>
> I will rebase and resend the patch.
>>>
>>> v2: Daniel's review comments
>>> Modified downclock deduction based on intel_find_panel_downclock
>>>
>>> v3: Chris's review comments
>>> Moved edp_downclock_avail and edp_downclock to intel_panel
>>>
>>> v4: Jani's review comments.
>>> Changed name of the enum edp_panel_type to drrs_support type.
>>> Change is_drrs_supported to drrs_support of type enum drrs_support_type.
>>>
>>> Signed-off-by: Pradeep Bhat
>>> Signed-off-by: Vandana Kannan
>>> ---
>>> drivers/gpu/drm/i915/intel_dp.c | 45
>>> ++
>>> drivers/gpu/drm/i915/intel_drv.h | 30 +
>>> 2 files changed, 75 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c
>>> index 8f17f8f..079b53f 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -3522,6 +3522,46 @@ intel_dp_init_panel_power_sequencer_registers(struct
>>> drm_device *dev,
>>> I915_READ(pp_div_reg));
>>> }
>>>
>>> +static void
>>> +intel_dp_drrs_initialize(struct intel_digital_port *intel_dig_port,
>>> + struct intel_connector *intel_connector,
>>> + struct drm_display_mode *fixed_mode) {
>>
>> I'll explain later why I think you should change the signature of the
>> function.
>>
>>> + struct drm_connector *connector = &intel_connector->base;
>>> + struct intel_dp *intel_dp = &intel_dig_port->dp;
>>> + struct drm_device *dev = intel_dig_port->base.base.dev;
>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>> +
>>> + /**
>>> +* Check if PSR is supported by panel and enabled
>>> +* if so then DRRS is reported as not supported for Haswell.
>>> +*/
>>> + if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
>>> + DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
>>> + return;
>>> + }
>>> +
>>> + /* First check if DRRS is enabled from VBT struct */
>>> + if (!dev_priv->vbt.drrs_enabled) {
>>> + DRM_INFO("VBT doesn't support DRRS\n");
>>> + return;
>>> + }
>>> +
>>> + intel_connector->panel.downclock_mode = intel_find_panel_downclock(dev,
>>> + fixed_mode, connector);
>>> +
>>> + if (intel_connector->panel.downclock_mode != NULL &&
>>> + dev_priv->vbt.drrs_mode == SEAMLESS_DRRS_SUPPORT) {
>>> + intel_connector->panel.edp_downclock_avail = true;
>>
>> If you rearranged the code a bit, you could make the
>> panel.downclock_mode != NULL mean the same as
>> edp_downclock_avail. I.e. if you have the downclock_mode there, it's
>> available.
>>
> This was done to be in sync with lvds_downclock implementation based on
> previous review comments.
>>> + intel_connector->panel.edp_downclock =
>>> + intel_connector->panel.downclock_mode->clock;
>>
>> I don't understand why you need two copies of the clock.
>>
>> In general, we should try and avoid adding extra state and copies of
>> information for stuff that we can readily derive from other information.
>>
>>> +
>>>
[Intel-gfx] [PATCH] drm/i915: Initialize downclock mode in panel init
Instead of modifying intel_panel in lvds_init_connector/dsi_init/
edp_init_connector, making changes to move intel_panel->downclock_mode
initialization to intel_panel_init()
v2: Jani's review comments incorporated
Removed downclock_mode local variable in dsi_init and
edp_init_connector
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_dp.c|2 +-
drivers/gpu/drm/i915/intel_drv.h |3 ++-
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_lvds.c | 10 +-
drivers/gpu/drm/i915/intel_panel.c |4 +++-
5 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f1ef3d4..88cc9d3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3732,7 +3732,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
}
- intel_panel_init(&intel_connector->panel, fixed_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector);
return true;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44067bc..6aa549a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -824,7 +824,8 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
/* intel_panel.c */
int intel_panel_init(struct intel_panel *panel,
-struct drm_display_mode *fixed_mode);
+struct drm_display_mode *fixed_mode,
+struct drm_display_mode *downclock_mode);
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fabbf0d..6bffbdf 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -624,7 +624,7 @@ bool intel_dsi_init(struct drm_device *dev)
}
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
- intel_panel_init(&intel_connector->panel, fixed_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
return true;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 3f3043b..6341a88 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -899,6 +899,7 @@ void intel_lvds_init(struct drm_device *dev)
struct drm_encoder *encoder;
struct drm_display_mode *scan; /* *modes, *bios_mode; */
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
struct edid *edid;
struct drm_crtc *crtc;
u32 lvds;
@@ -1032,15 +1033,14 @@ void intel_lvds_init(struct drm_device *dev)
fixed_mode = drm_mode_duplicate(dev, scan);
if (fixed_mode) {
- intel_connector->panel.downclock_mode =
+ downclock_mode =
intel_find_panel_downclock(dev,
fixed_mode, connector);
- if (intel_connector->panel.downclock_mode !=
- NULL && i915.lvds_downclock) {
+ if (downclock_mode != NULL &&
+ i915.lvds_downclock) {
/* We found the downclock for LVDS. */
dev_priv->lvds_downclock_avail = true;
dev_priv->lvds_downclock =
- intel_connector->panel.
downclock_mode->clock;
DRM_DEBUG_KMS("LVDS downclock is found"
" in EDID. Normal clock %dKhz, "
@@ -1116,7 +1116,7 @@ out:
}
drm_sysfs_connector_add(connector);
- intel_panel_init(&intel_connector->panel, fixed_mode);
+ intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
intel_panel_setup_backlight(connector);
return;
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f1ee2c4..5bc3f6e 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1190,9 +1190,11 @@ void intel_panel_init_backlight_funcs(struct drm_device
*dev)
}
int intel_panel_init(struct intel_panel *panel,
-struct drm_display_mode *fixed_mode)
+struc
[Intel-gfx] [PATCH 0/5] v5: Enabling DRRS in the kernel
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which enables swtiching between low and high refresh rates based on the usage scenario. This feature is applciable for internal eDP panel. Indication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution. The patch series supports idleness detection in display i915 driver and switch to low refresh rate. Based on review comments, the functions for idleness detection have been restructured. DRRS idleness time has been modified to be a kernel module param. Pradeep Bhat (3): [Intel-gfx] drm/i915: Adding VBT fields to support eDP DRRS feature [Intel-gfx] drm/i915: Parse EDID probed modes for DRRS support [Intel-gfx] drm/i915: Add support for DRRS to switch RR Vandana Kannan (2): [Intel-gfx] drm/i915: Idleness detection for DRRS [Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR drivers/gpu/drm/i915/i915_drv.h | 25 + drivers/gpu/drm/i915/i915_params.c |8 ++ drivers/gpu/drm/i915/i915_reg.h |1 + drivers/gpu/drm/i915/intel_bios.c| 29 ++ drivers/gpu/drm/i915/intel_bios.h| 29 ++ drivers/gpu/drm/i915/intel_display.c | 18 +++- drivers/gpu/drm/i915/intel_dp.c | 176 +- drivers/gpu/drm/i915/intel_drv.h | 33 ++- drivers/gpu/drm/i915/intel_pm.c | 134 ++ drivers/gpu/drm/i915/intel_sprite.c |2 + 10 files changed, 451 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h |6 +++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 101 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
4 files changed, 113 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b4d0b20..3dd1d7e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,11 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ struct intel_connector *connector;
+ struct intel_dp *dp;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1466,6 +1471,7 @@ typedef struct drm_i915_private {
int num_plane;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f73a49d..bfd7703 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3225,6 +3225,7 @@
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f7dba83..1933675 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -832,6 +832,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -936,6 +950,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.edp_downclock_avail &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.edp_downclock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3666,6 +3689,79 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = dev_priv->drrs.dp;
+ struct intel_crtc_config *config = NULL;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel_connector *intel_connector = dev_priv->drrs.connector;
+ u32 reg, val;
+ int index = 0;
+
+ if (refresh_rate <= 0) {
+ DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
+ return;
+ }
+
+ if (intel_dp == NULL) {
+ DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
+ return;
+ }
+
+ encoder = inte
[Intel-gfx] [PATCH 2/5] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode, based on the implementaion find_panel_downclock.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_dp.c | 53 +-
drivers/gpu/drm/i915/intel_drv.h | 20 ++
2 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 88cc9d3..f7dba83 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3666,6 +3666,49 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_initialize(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ /**
+* Check if PSR is supported by panel and enabled
+* if so then DRRS is reported as not supported for Haswell.
+*/
+ if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
+ DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
+ return downclock_mode;
+ }
+
+ /* First check if DRRS is enabled from VBT struct */
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return downclock_mode;
+ }
+
+ downclock_mode = intel_find_panel_downclock(dev,fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_connector->panel.edp_downclock_avail = true;
+ intel_connector->panel.edp_downclock =
+ downclock_mode->clock;
+
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ }
+
+ return downclock_mode;
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3675,10 +3718,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3720,6 +3766,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ if (INTEL_INFO(dev)->gen > 6)
+ downclock_mode =
+ intel_dp_drrs_initialize(
+ intel_dig_port,
+ intel_connector, fixed_mode);
break;
}
}
@@ -3732,7 +3783,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
[Intel-gfx] [PATCH 4/5] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/i915_drv.h |6 ++
drivers/gpu/drm/i915/i915_params.c |8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c |9 +++
drivers/gpu/drm/i915/intel_drv.h |5 +-
drivers/gpu/drm/i915/intel_pm.c | 134 ++
drivers/gpu/drm/i915/intel_sprite.c |2 +
7 files changed, 179 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3dd1d7e..8cb91d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,11 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
struct intel_dp *dp;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -1976,6 +1981,7 @@ struct i915_params {
bool prefault_disable;
bool reset;
int invert_brightness;
+ int drrs_interval;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index c743057..69f8b83 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.reset = true,
.invert_brightness = 0,
+ .drrs_interval = 2000,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -153,3 +154,10 @@ MODULE_PARM_DESC(invert_brightness,
"report PCI device ID, subsystem vendor and subsystem device ID "
"to dri-de...@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 2000 ms)."
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled."
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..86cd603 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2410,6 +2410,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3598,6 +3599,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3639,6 +3641,7 @@ static void haswell_crtc_enable_planes(struct drm_crtc
*crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -3845,6 +3848,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -3892,6 +3896,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -4176,6 +4181,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
intel_crtc_update_cursor(crtc, true);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
for_each_encoder_on_crtc(dev, crtc, encoder)
encoder->enable(encoder);
@@ -4221,6 +4227,7 @@ static void i9xx_cr
[Intel-gfx] [PATCH 1/5] drm/i915: Adding VBT fields to support eDP DRRS feature
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps us decide if seamless DRRS can be done
at runtime to support certain power saving features. This patch
was tested by setting necessary bit in VBT struct and merging
the new VBT with system BIOS so that we can read the value.
v2: Incorporated review comments from Chris Wilson
Removed "intel_" as a prefix for DRRS specific declarations.
v3: Incorporated Jani's review comments
Removed function which deducts drrs mode from panel_type. Modified some
print statements. Made changes to use DRRS_NOT_SUPPORTED as 0 instead of -1.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/intel_bios.c | 29 +
drivers/gpu/drm/i915/intel_bios.h | 29 +
3 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 728b9c3..6b4d0b20 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1218,6 +1218,12 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
};
+enum drrs_support_type {
+ DRRS_NOT_SUPPORTED = 0,
+ STATIC_DRRS_SUPPORT = 1,
+ SEAMLESS_DRRS_SUPPORT = 2
+};
+
struct intel_vbt_data {
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1233,6 +1239,13 @@ struct intel_vbt_data {
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+ /*
+* DRRS support type (Seamless OR Static DRRS OR not supported)
+* drrs_support type Val 0x2 is Seamless DRRS and 0 is Static DRRS.
+* These values correspond to the VBT values for drrs mode.
+*/
+ enum drrs_support_type drrs_type;
+
/* eDP */
int edp_rate;
int edp_lanes;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 86b95ca..2414eca 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -218,6 +218,25 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
panel_type = lvds_options->panel_type;
+ dev_priv->vbt.drrs_type = (lvds_options->dps_panel_type_bits
+ >> (panel_type * 2)) & MODE_MASK;
+ /*
+* VBT has static DRRS = 0 and seamless DRRS = 2.
+* The below piece of code is required to adjust vbt.drrs_type
+* to match the enum drrs_support_type.
+*/
+ switch (dev_priv->vbt.drrs_type) {
+ case 0:
+ dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ DRM_DEBUG_KMS("DRRS supported mode is static\n");
+ break;
+ case 2:
+ DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
+ break;
+ default:
+ break;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -516,6 +535,16 @@ parse_driver_features(struct drm_i915_private *dev_priv,
if (driver->dual_frequency)
dev_priv->render_reclock_avail = true;
+
+ DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+ /*
+* If DRRS is not supported, drrs_type has to be set to 0.
+* This is because, VBT is configured in such a way that
+* static DRRS is 0 and DRRS not supported is represented by
+* driver->drrs_enabled=false
+*/
+ if (!driver->drrs_enabled)
+ dev_priv->vbt.drrs_type = driver->drrs_enabled;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index 282de5e..5505d6c 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -281,6 +281,9 @@ struct bdb_general_definitions {
union child_device_config devices[0];
} __packed;
+/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
+#define MODE_MASK 0x3
+
struct bdb_lvds_options {
u8 panel_type;
u8 rsvd1;
@@ -293,6 +296,18 @@ struct bdb_lvds_options {
u8 lvds_edid:1;
u8 rsvd2:1;
u8 rsvd4;
+ /* LVDS Panel channel bits stored here */
+ u32 lvds_panel_channel_bits;
+ /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
+ u16 ssc_bits;
+ u16 ssc_freq;
+ u16 ssc_ddt;
+ /* Panel color depth defined here */
+ u16 panel_color_depth;
+ /* LVDS panel type bits stored here
[Intel-gfx] [PATCH 5/5] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen >=8 or gen > 5 before setting M/N registers
v3: Incorporated Jani's review comments
Re-use cpu_transcoder_set_m_n for BDW.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 86cd603..64ed4e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4901,7 +4901,7 @@ static void intel_pch_transcoder_set_m_n(struct
intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3407af6..0cfba6b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -839,11 +839,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder transcoder = crtc->config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ if (INTEL_INFO(dev)->gen >= 8) {
+ intel_cpu_transcoder_set_m_n(crtc, m_n);
+ } else if (INTEL_INFO(dev)->gen > 6) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ }
}
bool
@@ -3749,7 +3753,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
mutex_lock(&intel_dp->drrs_state.mutex);
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c8d6aa2..4da5abc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -751,6 +751,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.7.9.5
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[Intel-gfx] [PATCH 0/6] v6: Enabling DRRS in the kernel
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which enables swtiching between low and high refresh rates based on the usage scenario. This feature is applciable for internal eDP panel. Indication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution. The patch series supports idleness detection in display i915 driver and switch to low refresh rate. Based on review comments, the functions for idleness detection have been restructured. DRRS idleness time has been modified to be a kernel module param. Added support for VLV. Pradeep Bhat (3): [Intel-gfx] drm/i915: Adding VBT fields to support eDP DRRS feature [Intel-gfx] drm/i915: Parse EDID probed modes for DRRS support [Intel-gfx] drm/i915: Add support for DRRS to switch RR Vandana Kannan (3): [Intel-gfx] drm/i915: Idleness detection for DRRS [Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR [Intel-gfx] drm/i915: Support for RR switching on VLV drivers/gpu/drm/i915/i915_drv.h | 25 + drivers/gpu/drm/i915/i915_params.c |8 ++ drivers/gpu/drm/i915/i915_reg.h |2 + drivers/gpu/drm/i915/intel_bios.c| 29 + drivers/gpu/drm/i915/intel_bios.h| 29 + drivers/gpu/drm/i915/intel_display.c | 18 +++- drivers/gpu/drm/i915/intel_dp.c | 196 +- drivers/gpu/drm/i915/intel_drv.h | 33 +- drivers/gpu/drm/i915/intel_pm.c | 138 drivers/gpu/drm/i915/intel_sprite.c |2 + 10 files changed, 476 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Adding VBT fields to support eDP DRRS feature
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps us decide if seamless DRRS can be done
at runtime to support certain power saving features. This patch
was tested by setting necessary bit in VBT struct and merging
the new VBT with system BIOS so that we can read the value.
v2: Incorporated review comments from Chris Wilson
Removed "intel_" as a prefix for DRRS specific declarations.
v3: Incorporated Jani's review comments
Removed function which deducts drrs mode from panel_type. Modified some
print statements. Made changes to use DRRS_NOT_SUPPORTED as 0 instead of -1.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Acked-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/intel_bios.c | 29 +
drivers/gpu/drm/i915/intel_bios.h | 29 +
3 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 728b9c3..6b4d0b20 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1218,6 +1218,12 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
};
+enum drrs_support_type {
+ DRRS_NOT_SUPPORTED = 0,
+ STATIC_DRRS_SUPPORT = 1,
+ SEAMLESS_DRRS_SUPPORT = 2
+};
+
struct intel_vbt_data {
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1233,6 +1239,13 @@ struct intel_vbt_data {
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+ /*
+* DRRS support type (Seamless OR Static DRRS OR not supported)
+* drrs_support type Val 0x2 is Seamless DRRS and 0 is Static DRRS.
+* These values correspond to the VBT values for drrs mode.
+*/
+ enum drrs_support_type drrs_type;
+
/* eDP */
int edp_rate;
int edp_lanes;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 86b95ca..2414eca 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -218,6 +218,25 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
panel_type = lvds_options->panel_type;
+ dev_priv->vbt.drrs_type = (lvds_options->dps_panel_type_bits
+ >> (panel_type * 2)) & MODE_MASK;
+ /*
+* VBT has static DRRS = 0 and seamless DRRS = 2.
+* The below piece of code is required to adjust vbt.drrs_type
+* to match the enum drrs_support_type.
+*/
+ switch (dev_priv->vbt.drrs_type) {
+ case 0:
+ dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ DRM_DEBUG_KMS("DRRS supported mode is static\n");
+ break;
+ case 2:
+ DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
+ break;
+ default:
+ break;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -516,6 +535,16 @@ parse_driver_features(struct drm_i915_private *dev_priv,
if (driver->dual_frequency)
dev_priv->render_reclock_avail = true;
+
+ DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+ /*
+* If DRRS is not supported, drrs_type has to be set to 0.
+* This is because, VBT is configured in such a way that
+* static DRRS is 0 and DRRS not supported is represented by
+* driver->drrs_enabled=false
+*/
+ if (!driver->drrs_enabled)
+ dev_priv->vbt.drrs_type = driver->drrs_enabled;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index 282de5e..5505d6c 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -281,6 +281,9 @@ struct bdb_general_definitions {
union child_device_config devices[0];
} __packed;
+/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
+#define MODE_MASK 0x3
+
struct bdb_lvds_options {
u8 panel_type;
u8 rsvd1;
@@ -293,6 +296,18 @@ struct bdb_lvds_options {
u8 lvds_edid:1;
u8 rsvd2:1;
u8 rsvd4;
+ /* LVDS Panel channel bits stored here */
+ u32 lvds_panel_channel_bits;
+ /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
+ u16 ssc_bits;
+ u16 ssc_freq;
+ u16 ssc_ddt;
+ /* Panel color depth defined here */
+ u16 panel_color_depth;
+ /* LVDS panel type bits
[Intel-gfx] [PATCH 5/6] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen >=8 or gen > 5 before setting M/N registers
v3: Incorporated Jani's review comments
Re-use cpu_transcoder_set_m_n for BDW.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 86cd603..64ed4e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4901,7 +4901,7 @@ static void intel_pch_transcoder_set_m_n(struct
intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5fd60a9..9eadb1d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -839,11 +839,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder transcoder = crtc->config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ if (INTEL_INFO(dev)->gen >= 8) {
+ intel_cpu_transcoder_set_m_n(crtc, m_n);
+ } else if (INTEL_INFO(dev)->gen > 6) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ }
}
bool
@@ -3765,7 +3769,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
mutex_lock(&intel_dp->drrs_state.mutex);
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b6dcc0..3d280b0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -751,6 +751,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.7.9.5
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[Intel-gfx] [PATCH 6/6] drm/i915: Support for RR switching on VLV
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bfd7703..577654b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3227,6 +3227,7 @@
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
#define PIPECONF_8BPC(0<<5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9eadb1d..bf9e13e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3782,10 +3782,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev,
int refresh_rate)
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val |= PIPECONF_EDP_RR_MODE_SWITCH;
intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
} else {
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
I915_WRITE(reg, val);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_dp.c | 54 +-
drivers/gpu/drm/i915/intel_drv.h | 20 ++
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 88cc9d3..39365bf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3666,6 +3666,50 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ /**
+* Check if PSR is supported by panel and enabled
+* if so then DRRS is reported as not supported for Haswell.
+*/
+ if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
+ DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
+ return downclock_mode;
+ }
+
+ /* First check if DRRS is enabled from VBT struct */
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return downclock_mode;
+ }
+
+ downclock_mode = intel_find_panel_downclock
+ (dev, fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_connector->panel.edp_downclock_avail = true;
+ intel_connector->panel.edp_downclock =
+ downclock_mode->clock;
+
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ }
+
+ return downclock_mode;
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3675,10 +3719,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3720,6 +3767,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ if (INTEL_INFO(dev)->gen > 6)
+ downclock_mode =
+ intel_dp_drrs_init(
+ intel_dig_port,
+ intel_connector, fixed_mode);
break;
}
}
[Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
v6: Modifying i915_drrs to include only intel connector as intel_dp can be
derived from intel connector when required.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h |5 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 101 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
4 files changed, 112 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b4d0b20..43d3dfe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,10 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ struct intel_connector *connector;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1466,6 +1470,7 @@ typedef struct drm_i915_private {
int num_plane;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f73a49d..bfd7703 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3225,6 +3225,7 @@
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 39365bf..fd22914 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -832,6 +832,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -936,6 +950,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.edp_downclock_avail &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.edp_downclock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3666,6 +3689,80 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+ struct intel_crtc_config *config = NULL;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel_connector *intel_connector = dev_priv->drrs.connector;
+ u32 reg, val;
+ int index = 0;
+
+ if (refresh_rate <= 0) {
+ DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
+ return;
+ }
+
+ if (intel_connector == NULL) {
+ DRM_DEBUG_KMS("DRRS support
[Intel-gfx] [PATCH 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/i915_drv.h |7 ++
drivers/gpu/drm/i915/i915_params.c |8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 26 ++-
drivers/gpu/drm/i915/intel_drv.h |5 +-
drivers/gpu/drm/i915/intel_pm.c | 138 ++
drivers/gpu/drm/i915/intel_sprite.c |2 +
7 files changed, 199 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43d3dfe..87865e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -776,6 +776,12 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -1975,6 +1981,7 @@ struct i915_params {
bool prefault_disable;
bool reset;
int invert_brightness;
+ int drrs_interval;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index c743057..69f8b83 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.reset = true,
.invert_brightness = 0,
+ .drrs_interval = 2000,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -153,3 +154,10 @@ MODULE_PARM_DESC(invert_brightness,
"report PCI device ID, subsystem vendor and subsystem device ID "
"to dri-de...@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 2000 ms)."
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled."
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..86cd603 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2410,6 +2410,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3598,6 +3599,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3639,6 +3641,7 @@ static void haswell_crtc_enable_planes(struct drm_crtc
*crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -3845,6 +3848,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -3892,6 +3896,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
[Intel-gfx] [PATCH 5/6] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen >=8 or gen > 5 before setting M/N registers
v3: Incorporated Jani's review comments
Re-use cpu_transcoder_set_m_n for BDW.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 86cd603..64ed4e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4901,7 +4901,7 @@ static void intel_pch_transcoder_set_m_n(struct
intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6a91856..a76a58c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -839,11 +839,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder transcoder = crtc->config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ if (INTEL_INFO(dev)->gen >= 8) {
+ intel_cpu_transcoder_set_m_n(crtc, m_n);
+ } else if (INTEL_INFO(dev)->gen > 6) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ }
}
bool
@@ -3763,7 +3767,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b6dcc0..3d280b0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -751,6 +751,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_dp.c | 54 +-
drivers/gpu/drm/i915/intel_drv.h | 20 ++
2 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 88cc9d3..39365bf 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3666,6 +3666,50 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ /**
+* Check if PSR is supported by panel and enabled
+* if so then DRRS is reported as not supported for Haswell.
+*/
+ if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
+ DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
+ return downclock_mode;
+ }
+
+ /* First check if DRRS is enabled from VBT struct */
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return downclock_mode;
+ }
+
+ downclock_mode = intel_find_panel_downclock
+ (dev, fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_connector->panel.edp_downclock_avail = true;
+ intel_connector->panel.edp_downclock =
+ downclock_mode->clock;
+
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ }
+
+ return downclock_mode;
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3675,10 +3719,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3720,6 +3767,11 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ if (INTEL_INFO(dev)->gen > 6)
+ downclock_mode =
+ intel_dp_drrs_init(
+ intel_dig_port,
+ intel_connector, fixed_mode);
break;
}
}
[Intel-gfx] [PATCH 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
v6: Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
v7: As per internal review comments, removing calls to update/disable drrs
from sprite update path. For sprite, all drrs related updates would be
taken care of with calls to crtc page flip itself. This will have to be
revisited later if flip infrastructure changes for sprite.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/i915_drv.h |7 ++
drivers/gpu/drm/i915/i915_params.c |8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 26 ++-
drivers/gpu/drm/i915/intel_drv.h |5 +-
drivers/gpu/drm/i915/intel_pm.c | 138 ++
6 files changed, 197 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43d3dfe..87865e9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -776,6 +776,12 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -1975,6 +1981,7 @@ struct i915_params {
bool prefault_disable;
bool reset;
int invert_brightness;
+ int drrs_interval;
};
extern struct i915_params i915 __read_mostly;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index c743057..69f8b83 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.reset = true,
.invert_brightness = 0,
+ .drrs_interval = 2000,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -153,3 +154,10 @@ MODULE_PARM_DESC(invert_brightness,
"report PCI device ID, subsystem vendor and subsystem device ID "
"to dri-de...@lists.freedesktop.org, if your machine needs it. "
"It will then be included in an upcoming module version.");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 2000 ms)."
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled."
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4d4a0d9..86cd603 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2410,6 +2410,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
}
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3598,6 +3599,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3639,6 +3641,7 @@ static void haswell_crtc_enable_planes(struct drm_crtc
*crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
}
@@ -3845,6 +3848,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
mutex_lock(&
[Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
v6: Modifying i915_drrs to include only intel connector as intel_dp can be
derived from intel connector when required.
v7: As per internal review comments, acquiring mutex just before accessing
drrs RR. As per Chris's review comments, added documentation about the use
of locking in the function.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/i915_drv.h |5 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 108 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b4d0b20..43d3dfe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -774,6 +774,10 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ struct intel_connector *connector;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1466,6 +1470,7 @@ typedef struct drm_i915_private {
int num_plane;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f73a49d..bfd7703 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3225,6 +3225,7 @@
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 39365bf..54cde57 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -832,6 +832,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -936,6 +950,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.edp_downclock_avail &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.edp_downclock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3666,6 +3689,87 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+ struct intel_crtc_config *config = NULL;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel_connector *intel_connector = dev_priv->drrs.connector;
+ u32 reg, val;
+ int index = 0;
+
+ if (refresh_rate <= 0) {
+ DRM
[Intel-gfx] [PATCH 6/6] drm/i915: Support for RR switching on VLV
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bfd7703..577654b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3227,6 +3227,7 @@
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
#define PIPECONF_8BPC(0<<5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a76a58c..3616d0e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3780,10 +3780,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev,
int refresh_rate)
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val |= PIPECONF_EDP_RR_MODE_SWITCH;
intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
} else {
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
I915_WRITE(reg, val);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 0/6] v6: Enabling DRRS in the kernel
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which enables swtiching between low and high refresh rates based on the usage scenario. This feature is applciable for internal eDP panel. Indication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution. The patch series supports idleness detection in display i915 driver and switch to low refresh rate. Based on review comments, the functions for idleness detection have been restructured. DRRS idleness time has been modified to be a kernel module param. Added support for VLV. Pradeep Bhat (3): [Intel-gfx] drm/i915: Adding VBT fields to support eDP DRRS feature [Intel-gfx] drm/i915: Parse EDID probed modes for DRRS support [Intel-gfx] drm/i915: Add support for DRRS to switch RR Vandana Kannan (3): [Intel-gfx] drm/i915: Idleness detection for DRRS [Intel-gfx] drm/i915/bdw: Add support for DRRS to switch RR [Intel-gfx] drm/i915: Support for RR switching on VLV drivers/gpu/drm/i915/i915_drv.h | 25 + drivers/gpu/drm/i915/i915_params.c |8 ++ drivers/gpu/drm/i915/i915_reg.h |2 + drivers/gpu/drm/i915/intel_bios.c| 29 + drivers/gpu/drm/i915/intel_bios.h| 29 + drivers/gpu/drm/i915/intel_display.c | 18 ++- drivers/gpu/drm/i915/intel_dp.c | 203 +- drivers/gpu/drm/i915/intel_drv.h | 33 +- drivers/gpu/drm/i915/intel_pm.c | 138 +++ 9 files changed, 481 insertions(+), 4 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Adding VBT fields to support eDP DRRS feature
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps us decide if seamless DRRS can be done
at runtime to support certain power saving features. This patch
was tested by setting necessary bit in VBT struct and merging
the new VBT with system BIOS so that we can read the value.
v2: Incorporated review comments from Chris Wilson
Removed "intel_" as a prefix for DRRS specific declarations.
v3: Incorporated Jani's review comments
Removed function which deducts drrs mode from panel_type. Modified some
print statements. Made changes to use DRRS_NOT_SUPPORTED as 0 instead of -1.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Acked-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/intel_bios.c | 29 +
drivers/gpu/drm/i915/intel_bios.h | 29 +
3 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 728b9c3..6b4d0b20 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1218,6 +1218,12 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
};
+enum drrs_support_type {
+ DRRS_NOT_SUPPORTED = 0,
+ STATIC_DRRS_SUPPORT = 1,
+ SEAMLESS_DRRS_SUPPORT = 2
+};
+
struct intel_vbt_data {
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1233,6 +1239,13 @@ struct intel_vbt_data {
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+ /*
+* DRRS support type (Seamless OR Static DRRS OR not supported)
+* drrs_support type Val 0x2 is Seamless DRRS and 0 is Static DRRS.
+* These values correspond to the VBT values for drrs mode.
+*/
+ enum drrs_support_type drrs_type;
+
/* eDP */
int edp_rate;
int edp_lanes;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 86b95ca..2414eca 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -218,6 +218,25 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
panel_type = lvds_options->panel_type;
+ dev_priv->vbt.drrs_type = (lvds_options->dps_panel_type_bits
+ >> (panel_type * 2)) & MODE_MASK;
+ /*
+* VBT has static DRRS = 0 and seamless DRRS = 2.
+* The below piece of code is required to adjust vbt.drrs_type
+* to match the enum drrs_support_type.
+*/
+ switch (dev_priv->vbt.drrs_type) {
+ case 0:
+ dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ DRM_DEBUG_KMS("DRRS supported mode is static\n");
+ break;
+ case 2:
+ DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
+ break;
+ default:
+ break;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -516,6 +535,16 @@ parse_driver_features(struct drm_i915_private *dev_priv,
if (driver->dual_frequency)
dev_priv->render_reclock_avail = true;
+
+ DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+ /*
+* If DRRS is not supported, drrs_type has to be set to 0.
+* This is because, VBT is configured in such a way that
+* static DRRS is 0 and DRRS not supported is represented by
+* driver->drrs_enabled=false
+*/
+ if (!driver->drrs_enabled)
+ dev_priv->vbt.drrs_type = driver->drrs_enabled;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index 282de5e..5505d6c 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -281,6 +281,9 @@ struct bdb_general_definitions {
union child_device_config devices[0];
} __packed;
+/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
+#define MODE_MASK 0x3
+
struct bdb_lvds_options {
u8 panel_type;
u8 rsvd1;
@@ -293,6 +296,18 @@ struct bdb_lvds_options {
u8 lvds_edid:1;
u8 rsvd2:1;
u8 rsvd4;
+ /* LVDS Panel channel bits stored here */
+ u32 lvds_panel_channel_bits;
+ /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
+ u16 ssc_bits;
+ u16 ssc_freq;
+ u16 ssc_ddt;
+ /* Panel color depth defined here */
+ u16 panel_color_depth;
+ /* LVDS panel type bits
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
On Mar-05-2014 3:28 PM, Chris Wilson wrote:
> On Wed, Mar 05, 2014 at 03:13:06PM +0530, Vandana Kannan wrote:
>> +void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>> +{
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +struct intel_encoder *encoder;
>> +struct intel_dp *intel_dp = NULL;
>> +struct intel_crtc_config *config = NULL;
>> +struct intel_crtc *intel_crtc = NULL;
>> +struct intel_connector *intel_connector = dev_priv->drrs.connector;
>> +u32 reg, val;
>> +int index = 0;
>
> This routine touches a register and reads state guarded by modeset locks,
> I don't see any documentation to make sure the caller complies with
> holding the right locks.
>
> And since this function isn't used yet, I can't check that the callers
> are correct at this point in time either. Please, please do document
> locking requirements on new functions.
> -Chris
>
Thanks for your inputs. I have added a short description explaining that
the locking may be required for future implementations/enhancements of DRRS.
I have pushed the revised set of patches.
-Vandana
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[Intel-gfx] [PATCH] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
Populate PAR in infoframe structure. If there is a user setting for PAR, then
that value is set. Else, value is taken from CEA mode list if VIC is found.
Else, PAR is calculated from resolution. If none of these conditions are
satisfied, PAR is NONE as per initialization.
As a next step, create a property that would enable a user space app to set
aspect ratio. (will be pushed as a separate patch)
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 34 ++
include/drm/drm_crtc.h |1 +
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d4e3f9d..3db693f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
*to_match)
}
EXPORT_SYMBOL(drm_match_cea_mode);
+/**
+ * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
+ * the input VIC from the CEA mode list
+ *
+ * Returns picture aspect ratio
+ */
+enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
+{
+ /* return picture aspect ratio for video_code - 1 to access the
+* right array element
+ */
+ return edid_cea_modes[video_code-1].picture_aspect_ratio;
+}
+EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
+
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
* specific block).
@@ -3613,6 +3628,25 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
frame->video_code = drm_match_cea_mode(mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+
+ /* Populate picture aspect ratio from either CEA mode list or
+* user input
+ */
+ if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
+ mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
+ frame->picture_aspect = mode->picture_aspect_ratio;
+ else if (frame->video_code > 0)
+ frame->picture_aspect = drm_get_cea_aspect_ratio(
+ frame->video_code);
+ else {
+ if (!(mode->vdisplay % 3) &&
+ (((mode->vdisplay * 4) / 3) == mode->hdisplay))
+ frame->picture_aspect = HDMI_PICTURE_ASPECT_4_3;
+ else if (!(mode->vdisplay % 9) &&
+ (((mode->vdisplay * 16) / 9) == mode->hdisplay))
+ frame->picture_aspect = HDMI_PICTURE_ASPECT_16_9;
+ }
+
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 27f828c..50dc55a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
+extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
extern bool drm_detect_hdmi_monitor(struct edid *edid);
extern bool drm_detect_monitor_audio(struct edid *edid);
extern bool drm_rgb_quant_range_selectable(struct edid *edid);
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Add property to set HDMI aspect ratio
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode set.
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 10 ++
drivers/gpu/drm/i915/intel_modes.c | 28
4 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b8c1e0..628ba2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1588,6 +1588,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *aspect_ratio_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa99104..262142f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -474,6 +474,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
@@ -834,6 +835,7 @@ int intel_connector_update_modes(struct drm_connector
*connector,
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+void intel_attach_aspect_ratio_property(struct drm_connector *connector);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index b0413e1..ae7628e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
adjusted_mode);
if (ret < 0) {
@@ -1094,6 +1097,9 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == dev_priv->aspect_ratio_property)
+ intel_hdmi->aspect_ratio = val;
+
return -EINVAL;
done:
@@ -1227,6 +1233,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_aspect_ratio_property(connector);
intel_hdmi->color_range_auto = true;
}
@@ -1291,6 +1298,9 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
+ /* Initialize aspect ratio member of intel_hdmi */
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
intel_hdmi_add_properties(intel_hdmi, connector);
intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index 0e860f3..6f814da 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,31 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
drm_object_attach_property(&connector->base, prop, 0);
}
+
+static const struct drm_prop_enum_list aspect_ratio_names[] = {
+ { HDMI_PICTURE_ASPECT_NONE, "Automatic" },
+ { HDMI_PICTURE_ASPECT_4_3, "4:3" },
+ { HDMI_PICTURE_ASPECT_16_9, "16:9" },
+};
+
+void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_property *prop;
+
+ prop = dev_priv->aspect_ratio_property;
+ if (prop == NULL) {
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
+ "HDMI aspect ratio",
+ aspect_ratio_names,
+
[Intel-gfx] [PATCH] drm/i915: Add property to set HDMI aspect ratio
Added a property to enable user space to set aspect ratio for HDMI displays.
If there is no user specified value, then PAR_NONE/Automatic option is set
by default. User can select aspect ratio 4:3 or 16:9. The aspect ratio
selected by user would come into effect with a mode set.
v2: Daniel's review comments incorporated.
Call for a mode set to update property.
Suggested-by: Ville Syrjälä
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 12
drivers/gpu/drm/i915/intel_modes.c | 28
4 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b8c1e0..628ba2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1588,6 +1588,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *aspect_ratio_property;
uint32_t hw_context_size;
struct list_head context_list;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fa99104..262142f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -474,6 +474,7 @@ struct intel_hdmi {
bool has_audio;
enum hdmi_force_audio force_audio;
bool rgb_quant_range_selectable;
+ enum hdmi_picture_aspect aspect_ratio;
void (*write_infoframe)(struct drm_encoder *encoder,
enum hdmi_infoframe_type type,
const void *frame, ssize_t len);
@@ -834,6 +835,7 @@ int intel_connector_update_modes(struct drm_connector
*connector,
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+void intel_attach_aspect_ratio_property(struct drm_connector *connector);
/* intel_overlay.c */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index b0413e1..0b99485 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -367,6 +367,9 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder
*encoder,
union hdmi_infoframe frame;
int ret;
+ /* Set user selected PAR to incoming mode's member */
+ adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
+
ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
adjusted_mode);
if (ret < 0) {
@@ -1094,6 +1097,11 @@ intel_hdmi_set_property(struct drm_connector *connector,
goto done;
}
+ if (property == dev_priv->aspect_ratio_property) {
+ intel_hdmi->aspect_ratio = val;
+ goto done;
+ }
+
return -EINVAL;
done:
@@ -1227,6 +1235,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi,
struct drm_connector *c
{
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
+ intel_attach_aspect_ratio_property(connector);
intel_hdmi->color_range_auto = true;
}
@@ -1291,6 +1300,9 @@ void intel_hdmi_init_connector(struct intel_digital_port
*intel_dig_port,
intel_connector->get_hw_state = intel_connector_get_hw_state;
intel_connector->unregister = intel_connector_unregister;
+ /* Initialize aspect ratio member of intel_hdmi */
+ intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
+
intel_hdmi_add_properties(intel_hdmi, connector);
intel_connector_attach_encoder(intel_connector, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_modes.c
b/drivers/gpu/drm/i915/intel_modes.c
index 0e860f3..6f814da 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,31 @@ intel_attach_broadcast_rgb_property(struct drm_connector
*connector)
drm_object_attach_property(&connector->base, prop, 0);
}
+
+static const struct drm_prop_enum_list aspect_ratio_names[] = {
+ { HDMI_PICTURE_ASPECT_NONE, "Automatic" },
+ { HDMI_PICTURE_ASPECT_4_3, "4:3" },
+ { HDMI_PICTURE_ASPECT_16_9, "16:9" },
+};
+
+void
+intel_attach_aspect_ratio_property(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_property *prop;
+
+ prop = dev_priv->aspect_ratio_property;
+ if (prop == NULL) {
+ prop = drm_property_create_enum
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Parse EDID probed modes for DRRS support
On Mar-26-2014 6:19 PM, Jani Nikula wrote:
> On Wed, 26 Mar 2014, Jani Nikula wrote:
>> This and the following patches need to be rebased on top of current
>> -nightly.
>>
>> On Fri, 07 Mar 2014, Vandana Kannan wrote:
>>> From: Pradeep Bhat
>>>
>>> This patch and finds out the lowest refresh rate supported for the
>>> resolution
>>> same as the fixed_mode.
>>> It also checks the VBT fields to see if panel supports seamless DRRS or not.
>>> Based on above data it marks whether eDP panel supports seamless DRRS or
>>> not.
>>> This information is needed for supporting seamless DRRS switch for certain
>>> power saving usecases. This patch is tested by enabling the DRM logs and
>>> user should see whether Seamless DRRS is supported or not.
>>>
>>> v2: Daniel's review comments
>>> Modified downclock deduction based on intel_find_panel_downclock
>>>
>>> v3: Chris's review comments
>>> Moved edp_downclock_avail and edp_downclock to intel_panel
>>>
>>> v4: Jani's review comments.
>>> Changed name of the enum edp_panel_type to drrs_support type.
>>> Change is_drrs_supported to drrs_support of type enum drrs_support_type.
>>>
>>> v5: Incorporated Jani's review comments
>>> Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
>>> and above.
>>>
>>> v6: Incorporated Chris's review comments.
>>> Changed initialize to init in intel_drrs_initialize
>>>
>>> Signed-off-by: Pradeep Bhat
>>> Signed-off-by: Vandana Kannan
>>> ---
>>> drivers/gpu/drm/i915/intel_dp.c | 54
>>> +-
>>> drivers/gpu/drm/i915/intel_drv.h | 20 ++
>>> 2 files changed, 73 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c
>>> index 88cc9d3..39365bf 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -3666,6 +3666,50 @@ intel_dp_init_panel_power_sequencer_registers(struct
>>> drm_device *dev,
>>> I915_READ(pp_div_reg));
>>> }
>>>
>>> +static struct drm_display_mode *
>>> +intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
>>> + struct intel_connector *intel_connector,
>>> + struct drm_display_mode *fixed_mode)
>>> +{
>>> + struct drm_connector *connector = &intel_connector->base;
>>> + struct intel_dp *intel_dp = &intel_dig_port->dp;
>>> + struct drm_device *dev = intel_dig_port->base.base.dev;
>>> + struct drm_i915_private *dev_priv = dev->dev_private;
>>> + struct drm_display_mode *downclock_mode = NULL;
>>> +
>>> + /**
>>> +* Check if PSR is supported by panel and enabled
>>> +* if so then DRRS is reported as not supported for Haswell.
>>> +*/
>>> + if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
>>> + DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
>>> + return downclock_mode;
>>
>> Just return NULL explicitly if that's the intention.
>>
Ok
>>> + }
>>> +
>>> + /* First check if DRRS is enabled from VBT struct */
>>> + if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
>>> + DRM_INFO("VBT doesn't support DRRS\n");
>>> + return downclock_mode;
>>
>> Same here.
>>
Ok
>>> + }
>>> +
>>> + downclock_mode = intel_find_panel_downclock
>>> + (dev, fixed_mode, connector);
>>> +
>>> + if (downclock_mode != NULL &&
>>> + dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
>>> + intel_connector->panel.edp_downclock_avail = true;
>>> + intel_connector->panel.edp_downclock =
>>> + downclock_mode->clock;
>>
>> Why do you need a copy of downclock_mode->clock in
>> intel_connector->panel.edp_downclock? You can always get that through
>> intel_connector->panel.downclock_mode->clock. Single point of truth.
>
> Also, what does intel_connector->panel.edp_downclock_avail indicate that
> can't be derived from downclock_mode != NULL && dev_priv->vbt.drrs_type
> =
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
On Mar-26-2014 6:25 PM, Jani Nikula wrote:
> On Fri, 07 Mar 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch computes and stored 2nd M/N/TU for switching to different
>> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
>> between alternate refresh rates programmed in 2nd M/N/TU registers.
>>
>> v2: Daniel's review comments
>> Computing M2/N2 in compute_config and storing it in crtc_config
>>
>> v3: Modified reference to edp_downclock and edp_downclock_avail based on the
>> changes made to move them from dev_private to intel_panel.
>>
>> v4: Modified references to is_drrs_supported based on the changes made to
>> rename it to drrs_support.
>>
>> v5: Jani's review comments
>> Removed superfluous return statements. Changed support for Gen 7 and above.
>> Corrected indentation. Re-structured the code which finds crtc and connector
>> from encoder. Changed some logs to be less verbose.
>>
>> v6: Modifying i915_drrs to include only intel connector as intel_dp can be
>> derived from intel connector when required.
>>
>> v7: As per internal review comments, acquiring mutex just before accessing
>> drrs RR. As per Chris's review comments, added documentation about the use
>> of locking in the function.
>>
>> Signed-off-by: Pradeep Bhat
>> Signed-off-by: Vandana Kannan
>> ---
>> drivers/gpu/drm/i915/i915_drv.h |5 ++
>> drivers/gpu/drm/i915/i915_reg.h |1 +
>> drivers/gpu/drm/i915/intel_dp.c | 108
>> ++
>> drivers/gpu/drm/i915/intel_drv.h |6 ++-
>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 6b4d0b20..43d3dfe 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -774,6 +774,10 @@ struct i915_fbc {
>> } no_fbc_reason;
>> };
>>
>> +struct i915_drrs {
>> +struct intel_connector *connector;
>> +};
>> +
>> struct i915_psr {
>> bool sink_support;
>> bool source_ok;
>> @@ -1466,6 +1470,7 @@ typedef struct drm_i915_private {
>> int num_plane;
>>
>> struct i915_fbc fbc;
>> +struct i915_drrs drrs;
>> struct intel_opregion opregion;
>> struct intel_vbt_data vbt;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index f73a49d..bfd7703 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3225,6 +3225,7 @@
>> #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb
>> only */
>> #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb
>> only */
>> #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
>> +#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
>> #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
>> #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
>> #define PIPECONF_BPC_MASK (0x7 << 5)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index 39365bf..54cde57 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -832,6 +832,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>> }
>> }
>>
>> +static void
>> +intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>> +{
>> +struct drm_device *dev = crtc->base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +enum transcoder transcoder = crtc->config.cpu_transcoder;
>> +
>> +I915_WRITE(PIPE_DATA_M2(transcoder),
>> +TU_SIZE(m_n->tu) | m_n->gmch_m);
>> +I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> +I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> +I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> +}
>> +
>> bool
>> intel_dp_compute_config(struct intel_encoder *encoder,
>> struct intel_crtc_config *pipe_config)
>> @@ -936,6 +950,15 @@ found:
>> pipe_config->port_clock,
>> &pipe_config->dp_m_n);
>>
>> +if (intel_connector->panel.edp_downclock_avail &&
>> +intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
>
>
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Adding VBT fields to support eDP DRRS feature
On Mar-26-2014 6:06 PM, Jani Nikula wrote:
> On Fri, 07 Mar 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch reads the DRRS support and Mode type from VBT fields.
>> The read information will be stored in VBT struct during BIOS
>> parsing. The above functionality is needed for decision making
>> whether DRRS feature is supported in i915 driver for eDP panels.
>> This information helps us decide if seamless DRRS can be done
>> at runtime to support certain power saving features. This patch
>> was tested by setting necessary bit in VBT struct and merging
>> the new VBT with system BIOS so that we can read the value.
>>
>> v2: Incorporated review comments from Chris Wilson
>> Removed "intel_" as a prefix for DRRS specific declarations.
>>
>> v3: Incorporated Jani's review comments
>> Removed function which deducts drrs mode from panel_type. Modified some
>> print statements. Made changes to use DRRS_NOT_SUPPORTED as 0 instead of -1.
>>
>> Signed-off-by: Pradeep Bhat
>> Signed-off-by: Vandana Kannan
>> Acked-by: Jesse Barnes
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 13 +
>> drivers/gpu/drm/i915/intel_bios.c | 29 +
>> drivers/gpu/drm/i915/intel_bios.h | 29 +
>> 3 files changed, 71 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 728b9c3..6b4d0b20 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1218,6 +1218,12 @@ struct ddi_vbt_port_info {
>> uint8_t supports_dp:1;
>> };
>>
>> +enum drrs_support_type {
>> +DRRS_NOT_SUPPORTED = 0,
>> +STATIC_DRRS_SUPPORT = 1,
>> +SEAMLESS_DRRS_SUPPORT = 2
>> +};
>> +
>> struct intel_vbt_data {
>> struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
>> struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
>> @@ -1233,6 +1239,13 @@ struct intel_vbt_data {
>> int lvds_ssc_freq;
>> unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
>>
>> +/*
>> + * DRRS support type (Seamless OR Static DRRS OR not supported)
>> + * drrs_support type Val 0x2 is Seamless DRRS and 0 is Static DRRS.
>> + * These values correspond to the VBT values for drrs mode.
>> + */
>
> The comment is wrong.
>
Could you elaborate on this?
>> +enum drrs_support_type drrs_type;
>> +
>> /* eDP */
>> int edp_rate;
>> int edp_lanes;
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c
>> b/drivers/gpu/drm/i915/intel_bios.c
>> index 86b95ca..2414eca 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -218,6 +218,25 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
>>
>> panel_type = lvds_options->panel_type;
>>
>> +dev_priv->vbt.drrs_type = (lvds_options->dps_panel_type_bits
>> +>> (panel_type * 2)) & MODE_MASK;
>> +/*
>> + * VBT has static DRRS = 0 and seamless DRRS = 2.
>> + * The below piece of code is required to adjust vbt.drrs_type
>> + * to match the enum drrs_support_type.
>> + */
>> +switch (dev_priv->vbt.drrs_type) {
>
> Please don't mix the vbt and the enum at all like this, it's error
> prone. Just make the switch on the value in vbt, and for each case
> assign the appropriate enum to dev_priv->vbt.drrs_type.
>
Ok
>> +case 0:
>> +dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
>> +DRM_DEBUG_KMS("DRRS supported mode is static\n");
>> +break;
>> +case 2:
>> +DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
>> +break;
>> +default:
>> +break;
>
> And fail on the default.
>
Ok
>> +}
>> +
>> lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
>> if (!lvds_lfp_data)
>> return;
>> @@ -516,6 +535,16 @@ parse_driver_features(struct drm_i915_private *dev_priv,
>>
>> if (driver->dual_frequency)
>> dev_priv->render_reclock_avail = true;
>> +
>> +DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
>> +/*
>> + * If DRRS is not supported, drrs_type has to be set to 0.
>> + * This is because, VBT is con
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Idleness detection for DRRS
On Mar-26-2014 6:35 PM, Jani Nikula wrote:
> On Fri, 07 Mar 2014, Vandana Kannan wrote:
>> Adding support to detect display idleness by tracking page flip from
>> user space. Switch to low refresh rate is triggered after 2 seconds of
>> idleness. The delay is configurable. If there is a page flip or call to
>> update the plane, then high refresh rate is applied.
>> The feature is not used in dual-display mode.
>>
>> v2: Chris Wilson's review comments incorporated.
>> Modify idleness detection implementation to make it similar to the
>> implementation of intel_update_fbc/intel_disable_fbc
>>
>> v3: Internal review comments incorporated
>> Add NULL pointer check in intel_disable_drrs.
>> Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
>>
>> v4: Jani's review comments incorporated.
>> Change in sequence in intel_update_drrs. Comment modified to remove details
>> of update param. Modified DRRS idleness interval to a module parameter.
>>
>> v5: Chris's review comments incorporated.
>> Initialize connector in idleness detection init. Modifications made to
>> use only intel_connector in i915_drrs and derive intel_dp when required.
>> Added a function drrs_fini to cleanup DRRS work.
>>
>> v6: Internal review comments. Removed check for primary enabled, which is
>> a redundant check, in the case of clone mode. Added a flag to track
>> dual-display configuration. Remove print statement for "cancel DRR work"
>> and print "DRRS not supported" only once.
>>
>> v7: As per internal review comments, removing calls to update/disable drrs
>> from sprite update path. For sprite, all drrs related updates would be
>> taken care of with calls to crtc page flip itself. This will have to be
>> revisited later if flip infrastructure changes for sprite.
>>
>> Signed-off-by: Vandana Kannan
>> Signed-off-by: Pradeep Bhat
>> ---
>> drivers/gpu/drm/i915/i915_drv.h |7 ++
>> drivers/gpu/drm/i915/i915_params.c |8 ++
>> drivers/gpu/drm/i915/intel_display.c | 16
>> drivers/gpu/drm/i915/intel_dp.c | 26 ++-
>> drivers/gpu/drm/i915/intel_drv.h |5 +-
>> drivers/gpu/drm/i915/intel_pm.c | 138
>> ++
>> 6 files changed, 197 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 43d3dfe..87865e9 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -776,6 +776,12 @@ struct i915_fbc {
>>
>> struct i915_drrs {
>> struct intel_connector *connector;
>> +bool is_clone;
>> +struct intel_drrs_work {
>> +struct delayed_work work;
>> +struct drm_crtc *crtc;
>> +int interval;
>> +} *drrs_work;
>> };
>>
>> struct i915_psr {
>> @@ -1975,6 +1981,7 @@ struct i915_params {
>> bool prefault_disable;
>> bool reset;
>> int invert_brightness;
>> +int drrs_interval;
>> };
>> extern struct i915_params i915 __read_mostly;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>> b/drivers/gpu/drm/i915/i915_params.c
>> index c743057..69f8b83 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
>> .prefault_disable = 0,
>> .reset = true,
>> .invert_brightness = 0,
>> +.drrs_interval = 2000,
>> };
>>
>> module_param_named(modeset, i915.modeset, int, 0400);
>> @@ -153,3 +154,10 @@ MODULE_PARM_DESC(invert_brightness,
>> "report PCI device ID, subsystem vendor and subsystem device ID "
>> "to dri-de...@lists.freedesktop.org, if your machine needs it. "
>> "It will then be included in an upcoming module version.");
>> +
>> +module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
>> +MODULE_PARM_DESC(drrs_interval,
>> +"DRRS idleness detection interval (default: 2000 ms)."
>> +"If this field is set to 0, then seamless DRRS feature "
>> +"based on idleness detection is disabled."
>> +"The interval is to be set in milliseconds.");
>
> When the strings are concatenated there won't be a space after the
> periods.
>
Ok.. Will make appropriate changes..
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/dri
[Intel-gfx] [PATCH 6/6] drm/i915: Support for RR switching on VLV
Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.
Signed-off-by: Vandana Kannan
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04fc64a..435ed64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3257,6 +3257,7 @@ enum punit_power_well {
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
#define PIPECONF_8BPC(0<<5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6cdbb38..79d880b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3721,10 +3721,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev,
int refresh_rate)
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
- val |= PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val |= PIPECONF_EDP_RR_MODE_SWITCH;
intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
} else {
- val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+ if (IS_VALLEYVIEW(dev))
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+ else
+ val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
}
I915_WRITE(reg, val);
}
--
1.7.9.5
___
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[Intel-gfx] [PATCH 1/6] drm/i915: Adding VBT fields to support eDP DRRS feature
From: Pradeep Bhat
This patch reads the DRRS support and Mode type from VBT fields.
The read information will be stored in VBT struct during BIOS
parsing. The above functionality is needed for decision making
whether DRRS feature is supported in i915 driver for eDP panels.
This information helps us decide if seamless DRRS can be done
at runtime to support certain power saving features. This patch
was tested by setting necessary bit in VBT struct and merging
the new VBT with system BIOS so that we can read the value.
v2: Incorporated review comments from Chris Wilson
Removed "intel_" as a prefix for DRRS specific declarations.
v3: Incorporated Jani's review comments
Removed function which deducts drrs mode from panel_type. Modified some
print statements. Made changes to use DRRS_NOT_SUPPORTED as 0 instead of -1.
v4: Incorporated Jani's review comments.
Modifications around setting vbt drrs_type.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Acked-by: Jesse Barnes
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/intel_bios.c | 34 +-
drivers/gpu/drm/i915/intel_bios.h | 29 +
3 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b8c1e0..cd73a33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1284,6 +1284,12 @@ struct ddi_vbt_port_info {
uint8_t supports_dp:1;
};
+enum drrs_support_type {
+ DRRS_NOT_SUPPORTED = 0,
+ STATIC_DRRS_SUPPORT = 1,
+ SEAMLESS_DRRS_SUPPORT = 2
+};
+
struct intel_vbt_data {
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
@@ -1299,6 +1305,12 @@ struct intel_vbt_data {
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
+ /*
+* DRRS support type (Seamless OR Static DRRS OR not supported)
+* These values correspond to the VBT values for drrs mode.
+*/
+ enum drrs_support_type drrs_type;
+
/* eDP */
int edp_rate;
int edp_lanes;
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 4867f4c..9b98677 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -206,7 +206,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
const struct lvds_dvo_timing *panel_dvo_timing;
const struct lvds_fp_timing *fp_timing;
struct drm_display_mode *panel_fixed_mode;
- int i, downclock;
+ int i, downclock, drrs_mode;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
@@ -218,6 +218,28 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
panel_type = lvds_options->panel_type;
+ drrs_mode = (lvds_options->dps_panel_type_bits
+ >> (panel_type * 2)) & MODE_MASK;
+ /*
+* VBT has static DRRS = 0 and seamless DRRS = 2.
+* The below piece of code is required to adjust vbt.drrs_type
+* to match the enum drrs_support_type.
+*/
+ switch (drrs_mode) {
+ case 0:
+ dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
+ DRM_DEBUG_KMS("DRRS supported mode is static\n");
+ break;
+ case 2:
+ dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
+ DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
+ break;
+ default:
+ dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
+ DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
+ break;
+ }
+
lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
if (!lvds_lfp_data)
return;
@@ -516,6 +538,16 @@ parse_driver_features(struct drm_i915_private *dev_priv,
if (driver->dual_frequency)
dev_priv->render_reclock_avail = true;
+
+ DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
+ /*
+* If DRRS is not supported, drrs_type has to be set to 0.
+* This is because, VBT is configured in such a way that
+* static DRRS is 0 and DRRS not supported is represented by
+* driver->drrs_enabled=false
+*/
+ if (!driver->drrs_enabled)
+ dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h
b/drivers/gpu/drm/i915/intel_bios.h
index 83b7629..d02e5f9 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -282,6 +282,9 @@ struct bdb_general_definitions {
union child_device_config devices[0];
} __packed;
+/* Mask for DR
[Intel-gfx] [PATCH 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
v7: Incorporated Jani's review comments.
Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 53 +-
drivers/gpu/drm/i915/intel_drv.h | 16
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 59ee4dc..f2735de 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3611,6 +3611,51 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ if (INTEL_INFO(dev)->gen <= 6) {
+ DRM_INFO("DRRS supported for Gen7 and above\n");
+ return NULL;
+ }
+
+ /**
+* Check if PSR is supported by panel and enabled
+* if so then DRRS is reported as not supported for Haswell.
+*/
+ if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
+ DRM_INFO("eDP panel has PSR enabled. Cannot support DRRS\n");
+ return NULL;
+ }
+
+ /* First check if DRRS is enabled from VBT struct */
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return NULL;
+ }
+
+ downclock_mode = intel_find_panel_downclock
+ (dev, fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ }
+
+ return downclock_mode;
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3620,10 +3665,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3665,6 +3713,9 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ downclock_mode = intel_dp_drrs_init(
+ intel_dig_port,
+ intel_connector, fixed_mode);
b
[Intel-gfx] [PATCH 5/6] drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder.
For dynamic switching between multiple refreshr rates, M/N values may be
reprogrammed on the fly. Link N programming triggers update of all data and
link M & N registers and the new M/N values will be used in the next frame
that is output.
v2: Incorporated Chris's review comments
Changed to check for gen >=8 or gen > 5 before setting M/N registers
v3: Incorporated Jani's review comments
Re-use cpu_transcoder_set_m_n for BDW.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
---
drivers/gpu/drm/i915/intel_display.c |2 +-
drivers/gpu/drm/i915/intel_dp.c | 25 +++--
drivers/gpu/drm/i915/intel_drv.h |2 ++
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c309561..f492b51 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5120,7 +5120,7 @@ static void intel_pch_transcoder_set_m_n(struct
intel_crtc *crtc,
I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
}
-static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4f0281a..6cdbb38 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -743,11 +743,15 @@ intel_dp_set_m2_n2(struct intel_crtc *crtc, struct
intel_link_m_n *m_n)
struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder transcoder = crtc->config.cpu_transcoder;
- I915_WRITE(PIPE_DATA_M2(transcoder),
- TU_SIZE(m_n->tu) | m_n->gmch_m);
- I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
- I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
- I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ if (INTEL_INFO(dev)->gen >= 8) {
+ intel_cpu_transcoder_set_m_n(crtc, m_n);
+ } else if (INTEL_INFO(dev)->gen > 6) {
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+ }
}
bool
@@ -3704,7 +3708,16 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int
refresh_rate)
return;
}
- if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(dev)->gen >= 8) {
+ switch (index) {
+ case DRRS_HIGH_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m_n);
+ break;
+ case DRRS_LOW_RR:
+ intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
+ break;
+ };
+ } else if (INTEL_INFO(dev)->gen > 6) {
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
val = I915_READ(reg);
if (index > DRRS_HIGH_RR) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 570cc47..e4b479e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -770,6 +770,8 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv);
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_config *pipe_config);
int intel_format_to_fourcc(int format);
+void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
+ struct intel_link_m_n *m_n);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
--
1.7.9.5
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[Intel-gfx] [PATCH 0/6] v7: Enabling DRRS in the kernel
Dynamic Refresh Rate Switching (DRRS) is a power conservation feature which enables swtiching between low and high refresh rates based on the usage scenario. This feature is applciable for internal eDP panel. Indication that the panel supports DRRS is given by the panel EDID, which would list multiple refresh rates for one resolution. The patch series supports idleness detection in display i915 driver and switch to low refresh rate. Based on review comments, the functions for idleness detection have been restructured. DRRS idleness time has been modified to be a kernel module param. v6: Added support for VLV. v7: Patches rebased, review comments incorporated Pradeep Bhat (3): drm/i915: Adding VBT fields to support eDP DRRS feature drm/i915: Parse EDID probed modes for DRRS support drm/i915: Add support for DRRS to switch RR Vandana Kannan (3): drm/i915: Idleness detection for DRRS drm/i915/bdw: Add support for DRRS to switch RR drm/i915: Support for RR switching on VLV drivers/gpu/drm/i915/i915_drv.h | 24 + drivers/gpu/drm/i915/i915_params.c |8 ++ drivers/gpu/drm/i915/i915_reg.h |2 + drivers/gpu/drm/i915/intel_bios.c| 34 +- drivers/gpu/drm/i915/intel_bios.h| 29 + drivers/gpu/drm/i915/intel_display.c | 18 +++- drivers/gpu/drm/i915/intel_dp.c | 198 +- drivers/gpu/drm/i915/intel_drv.h | 29 - drivers/gpu/drm/i915/intel_pm.c | 138 9 files changed, 475 insertions(+), 5 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
v6: Modifying i915_drrs to include only intel connector as intel_dp can be
derived from intel connector when required.
v7: As per internal review comments, acquiring mutex just before accessing
drrs RR. As per Chris's review comments, added documentation about the use
of locking in the function.
v8: Incorporated Jani's review comments.
Removed reference to edp_downclock.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |5 ++
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_dp.c | 108 ++
drivers/gpu/drm/i915/intel_drv.h |6 ++-
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd73a33..1c9d5cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,10 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ struct intel_connector *connector;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1497,6 +1501,7 @@ typedef struct drm_i915_private {
struct timer_list hotplug_reenable_timer;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74f7d85..04fc64a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3255,6 +3255,7 @@ enum punit_power_well {
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f2735de..9640df1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -736,6 +736,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -840,6 +854,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.downclock_mode != NULL &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.downclock_mode->clock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3611,6 +3634,87 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+ struct intel_crtc_config *config = NULL;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel
[Intel-gfx] [PATCH 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
v6: Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
v7: As per internal review comments, removing calls to update/disable drrs
from sprite update path. For sprite, all drrs related updates would be
taken care of with calls to crtc page flip itself. This will have to be
revisited later if flip infrastructure changes for sprite.
v8: Incorporated Jani's review comments. Added space after the periods in the
module param description. Changes around drrs-fini to remove seamless DRRS
check.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h |7 ++
drivers/gpu/drm/i915/i915_params.c |8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 22 +-
drivers/gpu/drm/i915/intel_drv.h |5 +-
drivers/gpu/drm/i915/intel_pm.c | 138 ++
6 files changed, 193 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c9d5cf..c4e9b37 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -796,6 +796,12 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -2092,6 +2098,7 @@ struct i915_params {
int enable_ips;
int invert_brightness;
int enable_cmd_parser;
+ int drrs_interval;
/* leave bools at the end to not create holes */
bool enable_hangcheck;
bool fastboot;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d1d7980..05ca0a0 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 0,
+ .drrs_interval = 2000,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -152,3 +153,10 @@ MODULE_PARM_DESC(disable_display, "Disable display
(default: false)");
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
"Enable command parsing (1=enabled, 0=disabled [default])");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 2000 ms). "
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled. "
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7e4ea8d..c309561 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2542,6 +2542,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3708,6 +3709,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
mutex_unlock(&dev->struct_mutex);
for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -3751,6 +3753,7 @@ static void haswell_crtc_enable_plane
Re: [Intel-gfx] [PATCH] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
On Apr-01-2014 12:35 AM, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 08:31:29AM +0530, Vandana Kannan wrote:
>> Populate PAR in infoframe structure. If there is a user setting for PAR, then
>> that value is set. Else, value is taken from CEA mode list if VIC is found.
>> Else, PAR is calculated from resolution. If none of these conditions are
>> satisfied, PAR is NONE as per initialization.
>>
>> As a next step, create a property that would enable a user space app to set
>> aspect ratio. (will be pushed as a separate patch)
>>
>> Signed-off-by: Vandana Kannan
>> Cc: Jesse Barnes
>> Cc: Vijay Purushothaman
>> Cc: Ville Syrjälä
>> Cc: intel-gfx@lists.freedesktop.org
>> ---
>> drivers/gpu/drm/drm_edid.c | 34 ++
>> include/drm/drm_crtc.h |1 +
>> 2 files changed, 35 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index d4e3f9d..3db693f 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
>> *to_match)
>> }
>> EXPORT_SYMBOL(drm_match_cea_mode);
>>
>> +/**
>> + * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
>> + * the input VIC from the CEA mode list
>> + *
>> + * Returns picture aspect ratio
>> + */
>> +enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
>> +{
>> +/* return picture aspect ratio for video_code - 1 to access the
>> + * right array element
>> +*/
>> +return edid_cea_modes[video_code-1].picture_aspect_ratio;
>> +}
>> +EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
>> +
>> /*
>> * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
>> * specific block).
>> @@ -3613,6 +3628,25 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
>> hdmi_avi_infoframe *frame,
>> frame->video_code = drm_match_cea_mode(mode);
>>
>> frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
>> +
>> +/* Populate picture aspect ratio from either CEA mode list or
>> + * user input
>> +*/
>> +if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
>> +mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
>> +frame->picture_aspect = mode->picture_aspect_ratio;
>
> Please pardon my ignorance, but how can userspace actually set this part
> of the mode? I couldn't find any code which sets this anywhere ...
> -Daniel
>
I have submitted a patch to enable user space to set picture aspect
ratio through a property..
drm/i915: Add property to set HDMI aspect ratio
http://lists.freedesktop.org/archives/intel-gfx/2014-March/042403.html
-Vandana
>> +else if (frame->video_code > 0)
>> +frame->picture_aspect = drm_get_cea_aspect_ratio(
>> +frame->video_code);
>> +else {
>> +if (!(mode->vdisplay % 3) &&
>> +(((mode->vdisplay * 4) / 3) == mode->hdisplay))
>> +frame->picture_aspect = HDMI_PICTURE_ASPECT_4_3;
>> +else if (!(mode->vdisplay % 9) &&
>> +(((mode->vdisplay * 16) / 9) == mode->hdisplay))
>> +frame->picture_aspect = HDMI_PICTURE_ASPECT_16_9;
>> +}
>> +
>> frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
>> frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
>>
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index 27f828c..50dc55a 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device
>> *dev,
>> extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
>> void *data, struct drm_file *file_priv);
>> extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
>> +extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8
>> video_code);
>> extern bool drm_detect_hdmi_monitor(struct edid *edid);
>> extern bool drm_detect_monitor_audio(struct edid *edid);
>> extern bool drm_rgb_quant_range_selectable(struct edid *edid);
>> --
>> 1.7.9.5
>>
>> ___
>> dri-devel mailing list
>> dri-de...@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
___
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
On Apr-01-2014 12:57 PM, Daniel Vetter wrote:
> On Tue, Apr 01, 2014 at 08:06:04AM +0530, Vandana Kannan wrote:
>> On Apr-01-2014 12:35 AM, Daniel Vetter wrote:
>>> On Fri, Mar 21, 2014 at 08:31:29AM +0530, Vandana Kannan wrote:
>>>> Populate PAR in infoframe structure. If there is a user setting for PAR,
>>>> then
>>>> that value is set. Else, value is taken from CEA mode list if VIC is found.
>>>> Else, PAR is calculated from resolution. If none of these conditions are
>>>> satisfied, PAR is NONE as per initialization.
>>>>
>>>> As a next step, create a property that would enable a user space app to set
>>>> aspect ratio. (will be pushed as a separate patch)
>>>>
>>>> Signed-off-by: Vandana Kannan
>>>> Cc: Jesse Barnes
>>>> Cc: Vijay Purushothaman
>>>> Cc: Ville Syrjälä
>>>> Cc: intel-gfx@lists.freedesktop.org
>>>> ---
>>>> drivers/gpu/drm/drm_edid.c | 34 ++
>>>> include/drm/drm_crtc.h |1 +
>>>> 2 files changed, 35 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>>> index d4e3f9d..3db693f 100644
>>>> --- a/drivers/gpu/drm/drm_edid.c
>>>> +++ b/drivers/gpu/drm/drm_edid.c
>>>> @@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
>>>> *to_match)
>>>> }
>>>> EXPORT_SYMBOL(drm_match_cea_mode);
>>>>
>>>> +/**
>>>> + * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding
>>>> to
>>>> + * the input VIC from the CEA mode list
>>>> + *
>>>> + * Returns picture aspect ratio
>>>> + */
>>>> +enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
>>>> +{
>>>> + /* return picture aspect ratio for video_code - 1 to access the
>>>> + * right array element
>>>> + */
>>>> + return edid_cea_modes[video_code-1].picture_aspect_ratio;
>>>> +}
>>>> +EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
>>>> +
>>>> /*
>>>> * Calculate the alternate clock for HDMI modes (those from the HDMI
>>>> vendor
>>>> * specific block).
>>>> @@ -3613,6 +3628,25 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
>>>> hdmi_avi_infoframe *frame,
>>>>frame->video_code = drm_match_cea_mode(mode);
>>>>
>>>>frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
>>>> +
>>>> + /* Populate picture aspect ratio from either CEA mode list or
>>>> + * user input
>>>> + */
>>>> + if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
>>>> + mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
>>>> + frame->picture_aspect = mode->picture_aspect_ratio;
>>>
>>> Please pardon my ignorance, but how can userspace actually set this part
>>> of the mode? I couldn't find any code which sets this anywhere ...
>>> -Daniel
>>>
>> I have submitted a patch to enable user space to set picture aspect
>> ratio through a property..
>> drm/i915: Add property to set HDMI aspect ratio
>> http://lists.freedesktop.org/archives/intel-gfx/2014-March/042403.html
>
> Ah, that makes more sense. I think we should move the property also into
> the drm core so that all drivers that want to expose this can use the same
> property. Also if you have patches which depend upon each another in a
> funtional way it's better to post them together in one series.
> -Daniel
>
Ok, I will modify the patch (which adds aspect ratio property) to move
the property to drm and resend separately.
This patch as it is unblocks AVI infoframe compliance test, so can this
patch be considered for acceptance now?
>> -Vandana
>>>> + else if (frame->video_code > 0)
>>>> + frame->picture_aspect = drm_get_cea_aspect_ratio(
>>>> + frame->video_code);
>>>> + else {
>>>> + if (!(mode->vdisplay % 3) &&
>>>> + (((mode->vdisplay * 4) / 3) == mode->hdisplay))
>>>> + frame->picture_aspect = HDMI_PICTURE_ASPECT_4_3;
>>>> + else if (!(mode->vdisplay % 9) &&
>>>> + (((mode->vdisplay * 16) / 9)
[Intel-gfx] [PATCH v2] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
Populate PAR in infoframe structure. If there is a user setting for PAR, then
that value is set. Else, value is taken from CEA mode list if VIC is found.
Else, PAR is calculated from resolution. If none of these conditions are
satisfied, PAR is NONE as per initialization.
v2: Removed the part which sets PAR according to user input, based on
Daniel's review comments.
A separate patch will be submitted to create a property that would enable a
user space app to set aspect ratio for AVI infoframe.
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Jesse Barnes
---
drivers/gpu/drm/drm_edid.c | 29 +
include/drm/drm_crtc.h | 1 +
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d4e3f9d..fee24d3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
*to_match)
}
EXPORT_SYMBOL(drm_match_cea_mode);
+/**
+ * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
+ * the input VIC from the CEA mode list
+ *
+ * Returns picture aspect ratio
+ */
+enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
+{
+ /* return picture aspect ratio for video_code - 1 to access the
+* right array element
+ */
+ return edid_cea_modes[video_code-1].picture_aspect_ratio;
+}
+EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
+
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
* specific block).
@@ -3613,6 +3628,20 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
frame->video_code = drm_match_cea_mode(mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+
+ /* Populate picture aspect ratio from CEA mode list */
+ if (frame->video_code > 0)
+ frame->picture_aspect = drm_get_cea_aspect_ratio(
+ frame->video_code);
+ else {
+ if (!(mode->vdisplay % 3) &&
+ (((mode->vdisplay * 4) / 3) == mode->hdisplay))
+ frame->picture_aspect = HDMI_PICTURE_ASPECT_4_3;
+ else if (!(mode->vdisplay % 9) &&
+ (((mode->vdisplay * 16) / 9) == mode->hdisplay))
+ frame->picture_aspect = HDMI_PICTURE_ASPECT_16_9;
+ }
+
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 27f828c..50dc55a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
+extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
extern bool drm_detect_hdmi_monitor(struct edid *edid);
extern bool drm_detect_monitor_audio(struct edid *edid);
extern bool drm_rgb_quant_range_selectable(struct edid *edid);
--
1.9.1
___
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Re: [Intel-gfx] [PATCH v2] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
On Apr-01-2014 5:04 PM, Ville Syrjälä wrote:
> On Tue, Apr 01, 2014 at 04:26:59PM +0530, Vandana Kannan wrote:
>> Populate PAR in infoframe structure. If there is a user setting for PAR, then
>> that value is set. Else, value is taken from CEA mode list if VIC is found.
>> Else, PAR is calculated from resolution. If none of these conditions are
>> satisfied, PAR is NONE as per initialization.
>>
>> v2: Removed the part which sets PAR according to user input, based on
>> Daniel's review comments.
>>
>> A separate patch will be submitted to create a property that would enable a
>> user space app to set aspect ratio for AVI infoframe.
>>
>> Signed-off-by: Vandana Kannan
>> Cc: Jesse Barnes
>> Cc: Vijay Purushothaman
>> Cc: Ville Syrjälä
>> Cc: intel-gfx@lists.freedesktop.org
>> Reviewed-by: Jesse Barnes
>> ---
>> drivers/gpu/drm/drm_edid.c | 29 +
>> include/drm/drm_crtc.h | 1 +
>> 2 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index d4e3f9d..fee24d3 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
>> *to_match)
>> }
>> EXPORT_SYMBOL(drm_match_cea_mode);
>>
>> +/**
>> + * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
>> + * the input VIC from the CEA mode list
>> + *
>> + * Returns picture aspect ratio
>> + */
>> +enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
>> +{
>> +/* return picture aspect ratio for video_code - 1 to access the
>> + * right array element
>> +*/
>> +return edid_cea_modes[video_code-1].picture_aspect_ratio;
>> +}
>> +EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
>> +
>> /*
>> * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
>> * specific block).
>> @@ -3613,6 +3628,20 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
>> hdmi_avi_infoframe *frame,
>> frame->video_code = drm_match_cea_mode(mode);
>>
>> frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
>> +
>> +/* Populate picture aspect ratio from CEA mode list */
>> +if (frame->video_code > 0)
>> +frame->picture_aspect = drm_get_cea_aspect_ratio(
>> +frame->video_code);
>> +else {
>> +if (!(mode->vdisplay % 3) &&
>> +(((mode->vdisplay * 4) / 3) == mode->hdisplay))
>> +frame->picture_aspect = HDMI_PICTURE_ASPECT_4_3;
>> +else if (!(mode->vdisplay % 9) &&
>> +(((mode->vdisplay * 16) / 9) == mode->hdisplay))
>> +frame->picture_aspect = HDMI_PICTURE_ASPECT_16_9;
>> +}
>
> I'm not sure if providing the PAR for non-CEA modes like this makes
> any real difference. But I guess it can't hurt since you only provide
> it for exact matches.
>
> But the matches are maybe even a bit too exact. For instance 1366x768
> will not match the 16:9 case. So maybe it should be calculated in a bit
> more relaxed way.
>
> Or just dropped totally. I'm not sure.
>
Maybe we can drop it for now (for this patch) and come up with another
patch containing calculations which are more relaxed than the above.
What do you think?
>> +
>> frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
>> frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
>>
>> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
>> index 27f828c..50dc55a 100644
>> --- a/include/drm/drm_crtc.h
>> +++ b/include/drm/drm_crtc.h
>> @@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device
>> *dev,
>> extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
>> void *data, struct drm_file *file_priv);
>> extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
>> +extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8
>> video_code);
>> extern bool drm_detect_hdmi_monitor(struct edid *edid);
>> extern bool drm_detect_monitor_audio(struct edid *edid);
>> extern bool drm_rgb_quant_range_selectable(struct edid *edid);
>> --
>> 1.9.1
>
___
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[Intel-gfx] [PATCH v3] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
Populate PAR in infoframe structure. If there is a user setting for PAR, then
that value is set. Else, value is taken from CEA mode list if VIC is found.
Else, PAR is calculated from resolution. If none of these conditions are
satisfied, PAR is NONE as per initialization.
v2: Removed the part which sets PAR according to user input, based on
Daniel's review comments.
v3: Removed calculation of PAR for non-CEA modes as per discussion with
Ville.
A separate patch will be submitted to create a property that would enable a
user space app to set aspect ratio for AVI infoframe.
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
Reviewed-by: Jesse Barnes
---
drivers/gpu/drm/drm_edid.c | 21 +
include/drm/drm_crtc.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d4e3f9d..09ece10 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2452,6 +2452,21 @@ u8 drm_match_cea_mode(const struct drm_display_mode
*to_match)
}
EXPORT_SYMBOL(drm_match_cea_mode);
+/**
+ * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
+ * the input VIC from the CEA mode list
+ *
+ * Returns picture aspect ratio
+ */
+enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
+{
+ /* return picture aspect ratio for video_code - 1 to access the
+* right array element
+ */
+ return edid_cea_modes[video_code-1].picture_aspect_ratio;
+}
+EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
+
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
* specific block).
@@ -3613,6 +3628,12 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
frame->video_code = drm_match_cea_mode(mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+
+ /* Populate picture aspect ratio from CEA mode list */
+ if (frame->video_code > 0)
+ frame->picture_aspect = drm_get_cea_aspect_ratio(
+ frame->video_code);
+
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 27f828c..50dc55a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
+extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
extern bool drm_detect_hdmi_monitor(struct edid *edid);
extern bool drm_detect_monitor_audio(struct edid *edid);
extern bool drm_rgb_quant_range_selectable(struct edid *edid);
--
1.9.1
___
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[Intel-gfx] [PATCH v4] drm/edid: Fill PAR in AVI infoframe based on CEA mode list
Populate PAR in infoframe structure. PAR is taken from CEA mode list if
VIC is found. Else, PAR is NONE as per initialization.
v2: Removed the part which sets PAR according to user input, based on
Daniel's review comments.
v3: Removed calculation of PAR for non-CEA modes as per discussion with
Ville.
v4: Added description for the param video_code. Absence of the description
led to a warning while executing "make htmldocs", as reported by
Wu, Fengguang.
Modified commit message.
A separate patch will be submitted to create a property that would enable a
user space app to set aspect ratio for AVI infoframe.
Signed-off-by: Vandana Kannan
Cc: Jesse Barnes
Cc: Vijay Purushothaman
Cc: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org
Cc: Wu, Fengguang
Reviewed-by: Jesse Barnes
---
drivers/gpu/drm/drm_edid.c | 22 ++
include/drm/drm_crtc.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d4e3f9d..b8d6c51 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2452,6 +2452,22 @@ u8 drm_match_cea_mode(const struct drm_display_mode
*to_match)
}
EXPORT_SYMBOL(drm_match_cea_mode);
+/**
+ * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
+ * the input VIC from the CEA mode list
+ * @video_code: ID given to each of the CEA modes
+ *
+ * Returns picture aspect ratio
+ */
+enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
+{
+ /* return picture aspect ratio for video_code - 1 to access the
+* right array element
+ */
+ return edid_cea_modes[video_code-1].picture_aspect_ratio;
+}
+EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
+
/*
* Calculate the alternate clock for HDMI modes (those from the HDMI vendor
* specific block).
@@ -3613,6 +3629,12 @@ drm_hdmi_avi_infoframe_from_display_mode(struct
hdmi_avi_infoframe *frame,
frame->video_code = drm_match_cea_mode(mode);
frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
+
+ /* Populate picture aspect ratio from CEA mode list */
+ if (frame->video_code > 0)
+ frame->picture_aspect = drm_get_cea_aspect_ratio(
+ frame->video_code);
+
frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 27f828c..50dc55a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -983,6 +983,7 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv);
extern u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
+extern enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);
extern bool drm_detect_hdmi_monitor(struct edid *edid);
extern bool drm_detect_monitor_audio(struct edid *edid);
extern bool drm_rgb_quant_range_selectable(struct edid *edid);
--
1.9.1
___
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Add support for DRRS to switch RR
On Apr-01-2014 6:55 PM, Jani Nikula wrote:
> On Fri, 28 Mar 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch computes and stored 2nd M/N/TU for switching to different
>> refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
>> between alternate refresh rates programmed in 2nd M/N/TU registers.
>>
>> v2: Daniel's review comments
>> Computing M2/N2 in compute_config and storing it in crtc_config
>>
>> v3: Modified reference to edp_downclock and edp_downclock_avail based on the
>> changes made to move them from dev_private to intel_panel.
>>
>> v4: Modified references to is_drrs_supported based on the changes made to
>> rename it to drrs_support.
>>
>> v5: Jani's review comments
>> Removed superfluous return statements. Changed support for Gen 7 and above.
>> Corrected indentation. Re-structured the code which finds crtc and connector
>> from encoder. Changed some logs to be less verbose.
>>
>> v6: Modifying i915_drrs to include only intel connector as intel_dp can be
>> derived from intel connector when required.
>>
>> v7: As per internal review comments, acquiring mutex just before accessing
>> drrs RR. As per Chris's review comments, added documentation about the use
>> of locking in the function.
>>
>> v8: Incorporated Jani's review comments.
>> Removed reference to edp_downclock.
>>
>> Signed-off-by: Pradeep Bhat
>> Signed-off-by: Vandana Kannan
>> Cc: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/i915_drv.h |5 ++
>> drivers/gpu/drm/i915/i915_reg.h |1 +
>> drivers/gpu/drm/i915/intel_dp.c | 108
>> ++
>> drivers/gpu/drm/i915/intel_drv.h |6 ++-
>> 4 files changed, 119 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index cd73a33..1c9d5cf 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -794,6 +794,10 @@ struct i915_fbc {
>> } no_fbc_reason;
>> };
>>
>> +struct i915_drrs {
>> +struct intel_connector *connector;
>> +};
>> +
>> struct i915_psr {
>> bool sink_support;
>> bool source_ok;
>> @@ -1497,6 +1501,7 @@ typedef struct drm_i915_private {
>> struct timer_list hotplug_reenable_timer;
>>
>> struct i915_fbc fbc;
>> +struct i915_drrs drrs;
>> struct intel_opregion opregion;
>> struct intel_vbt_data vbt;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 74f7d85..04fc64a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3255,6 +3255,7 @@ enum punit_power_well {
>> #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb
>> only */
>> #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb
>> only */
>> #define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
>> +#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
>> #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
>> #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
>> #define PIPECONF_BPC_MASK (0x7 << 5)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index f2735de..9640df1 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -736,6 +736,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>> }
>> }
>>
>> +static void
>> +intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
>> +{
>> +struct drm_device *dev = crtc->base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +enum transcoder transcoder = crtc->config.cpu_transcoder;
>> +
>> +I915_WRITE(PIPE_DATA_M2(transcoder),
>> +TU_SIZE(m_n->tu) | m_n->gmch_m);
>> +I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
>> +I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
>> +I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
>> +}
>> +
>> bool
>> intel_dp_compute_config(struct intel_encoder *encoder,
>> struct intel_crtc_config *pipe_config)
>> @@ -840,6 +854,15 @@ found:
>> pipe_config->port_clock,
>> &pipe_conf
[Intel-gfx] [PATCH v8 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
v7: Incorporated Jani's review comments.
Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
v8: Made changes to track PSR enable/disable throughout system use (instead
of just in the init sequence) for disabling/enabling DRRS. Jani's review
comments.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 5
drivers/gpu/drm/i915/intel_dp.c | 55 +++-
drivers/gpu/drm/i915/intel_drv.h | 16
3 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd73a33..b6ea225 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,10 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ bool is_psr_enabled;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1497,6 +1501,7 @@ typedef struct drm_i915_private {
struct timer_list hotplug_reenable_timer;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 59ee4dc..ce588d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1697,6 +1697,7 @@ static bool intel_edp_psr_match_conditions(struct
intel_dp *intel_dp)
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev->dev_private;
if (!intel_edp_psr_match_conditions(intel_dp) ||
intel_edp_is_psr_enabled(dev))
@@ -1710,6 +1711,11 @@ static void intel_edp_psr_do_enable(struct intel_dp
*intel_dp)
/* Enable PSR on the host */
intel_edp_psr_enable_source(intel_dp);
+
+ if (INTEL_INFO(dev)->gen < 8) {
+ dev_priv->drrs.is_psr_enabled = true;
+ DRM_DEBUG_KMS("eDP panel PSR enabled. Can't support DRRS\n");
+ }
}
void intel_edp_psr_enable(struct intel_dp *intel_dp)
@@ -1736,6 +1742,9 @@ void intel_edp_psr_disable(struct intel_dp *intel_dp)
if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
DRM_ERROR("Timed out waiting for PSR Idle State\n");
+
+ if (INTEL_INFO(dev)->gen < 8)
+ dev_priv->drrs.is_psr_enabled = false;
}
void intel_edp_psr_update(struct drm_device *dev)
@@ -3611,6 +3620,44 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ if (INTEL_INFO(dev)->gen <= 6) {
+ DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
+ return NULL;
+ }
+
+ if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev))
+ dev_priv->drrs.is_psr_enabled = true;
+
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ ret
[Intel-gfx] [PATCH v9 3/6] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
v6: Modifying i915_drrs to include only intel connector as intel_dp can be
derived from intel connector when required.
v7: As per internal review comments, acquiring mutex just before accessing
drrs RR. As per Chris's review comments, added documentation about the use
of locking in the function.
v8: Incorporated Jani's review comments.
Removed reference to edp_downclock.
v9: Jani's review comments. Modified comment in set_drrs. Changed index to
type edp_drrs_refresh_rate_type. Check if PSR is enabled before setting
registers fo DRRS.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 111 +++
drivers/gpu/drm/i915/intel_drv.h | 6 ++-
4 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b6ea225..652da3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -796,6 +796,7 @@ struct i915_fbc {
struct i915_drrs {
bool is_psr_enabled;
+ struct intel_connector *connector;
};
struct i915_psr {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74f7d85..04fc64a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3255,6 +3255,7 @@ enum punit_power_well {
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ce588d1..becc65b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -736,6 +736,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -840,6 +854,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.downclock_mode != NULL &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.downclock_mode->clock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3620,6 +3643,90 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp = NULL;
+ struct intel_crtc_config *config = NULL;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel_connector *intel_connector = dev_priv->drrs.connector;
+ u32 reg, val;
+ enum edp_drrs_refresh_rate_type index = DRRS_HIGH
[Intel-gfx] [PATCH v9 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
v6: Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
v7: As per internal review comments, removing calls to update/disable drrs
from sprite update path. For sprite, all drrs related updates would be
taken care of with calls to crtc page flip itself. This will have to be
revisited later if flip infrastructure changes for sprite.
v8: Incorporated Jani's review comments. Added space after the periods in the
module param description. Changes around drrs-fini to remove seamless DRRS
check.
v9: Added checks for PSR before updating DRRS. Added check for module
param drrs_interval before updating DRRS (this is required if the interval
is modified by the user during system use). DRRS disabled by default. Changes
based on Jani's review comments
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_params.c | 8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 142 +++
6 files changed, 201 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 652da3a..4a3eba6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -797,6 +797,12 @@ struct i915_fbc {
struct i915_drrs {
bool is_psr_enabled;
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -2093,6 +2099,7 @@ struct i915_params {
int enable_ips;
int invert_brightness;
int enable_cmd_parser;
+ int drrs_interval;
/* leave bools at the end to not create holes */
bool enable_hangcheck;
bool fastboot;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d1d7980..2410607 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 0,
+ .drrs_interval = 0,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -152,3 +153,10 @@ MODULE_PARM_DESC(disable_display, "Disable display
(default: false)");
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
"Enable command parsing (1=enabled, 0=disabled [default])");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 0 ms). "
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled. "
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7e4ea8d..c309561 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2542,6 +2542,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3708,6 +3709,7 @@ static void ironlake_crtc_enable(struct
[Intel-gfx] [PATCH v9 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
v7: Incorporated Jani's review comments.
Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
v8: Made changes to track PSR enable/disable throughout system use (instead
of just in the init sequence) for disabling/enabling DRRS. Jani's review
comments.
v9: PSR tracking will be done as part of idleness detection patch. Removed
PSR state tracker in i915_drrs. Jani's review comments.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 43 +++-
drivers/gpu/drm/i915/intel_drv.h | 16 +++
2 files changed, 58 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 59ee4dc..c85ae14 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3611,6 +3611,41 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ if (INTEL_INFO(dev)->gen <= 6) {
+ DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
+ return NULL;
+ }
+
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return NULL;
+ }
+
+ downclock_mode = intel_find_panel_downclock
+ (dev, fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ }
+
+ return downclock_mode;
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3620,10 +3655,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3665,6 +3703,9 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ downclock_mode = intel_dp_drrs_init(
+ intel_dig_port,
+ intel_connector, fixed_mode);
break;
}
}
@@ -3677,7 +3718,7 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
[Intel-gfx] [PATCH v9 3/6] drm/i915: Add support for DRRS to switch RR
From: Pradeep Bhat
This patch computes and stored 2nd M/N/TU for switching to different
refresh rate dynamically. PIPECONF_EDP_RR_MODE_SWITCH bit helps toggle
between alternate refresh rates programmed in 2nd M/N/TU registers.
v2: Daniel's review comments
Computing M2/N2 in compute_config and storing it in crtc_config
v3: Modified reference to edp_downclock and edp_downclock_avail based on the
changes made to move them from dev_private to intel_panel.
v4: Modified references to is_drrs_supported based on the changes made to
rename it to drrs_support.
v5: Jani's review comments
Removed superfluous return statements. Changed support for Gen 7 and above.
Corrected indentation. Re-structured the code which finds crtc and connector
from encoder. Changed some logs to be less verbose.
v6: Modifying i915_drrs to include only intel connector as intel_dp can be
derived from intel connector when required.
v7: As per internal review comments, acquiring mutex just before accessing
drrs RR. As per Chris's review comments, added documentation about the use
of locking in the function.
v8: Incorporated Jani's review comments.
Removed reference to edp_downclock.
v9: Jani's review comments. Modified comment in set_drrs. Changed index to
type edp_drrs_refresh_rate_type. Check if PSR is enabled before setting
registers fo DRRS.
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dp.c | 111 +++
drivers/gpu/drm/i915/intel_drv.h | 6 ++-
4 files changed, 122 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cd73a33..1c9d5cf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,10 @@ struct i915_fbc {
} no_fbc_reason;
};
+struct i915_drrs {
+ struct intel_connector *connector;
+};
+
struct i915_psr {
bool sink_support;
bool source_ok;
@@ -1497,6 +1501,7 @@ typedef struct drm_i915_private {
struct timer_list hotplug_reenable_timer;
struct i915_fbc fbc;
+ struct i915_drrs drrs;
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 74f7d85..04fc64a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3255,6 +3255,7 @@ enum punit_power_well {
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
+#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK(0x7 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c85ae14..374dcb6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -736,6 +736,20 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static void
+intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ enum transcoder transcoder = crtc->config.cpu_transcoder;
+
+ I915_WRITE(PIPE_DATA_M2(transcoder),
+ TU_SIZE(m_n->tu) | m_n->gmch_m);
+ I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
+ I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
+ I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_config *pipe_config)
@@ -840,6 +854,15 @@ found:
pipe_config->port_clock,
&pipe_config->dp_m_n);
+ if (intel_connector->panel.downclock_mode != NULL &&
+ intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
+ intel_link_compute_m_n(bpp, lane_count,
+ intel_connector->panel.downclock_mode->clock,
+ pipe_config->port_clock,
+ &pipe_config->dp_m2_n2);
+ }
+
+
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
return true;
@@ -3611,6 +3634,90 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_encoder *encoder
[Intel-gfx] [PATCH v10 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
v6: Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
v7: As per internal review comments, removing calls to update/disable drrs
from sprite update path. For sprite, all drrs related updates would be
taken care of with calls to crtc page flip itself. This will have to be
revisited later if flip infrastructure changes for sprite.
v8: Incorporated Jani's review comments. Added space after the periods in the
module param description. Changes around drrs-fini to remove seamless DRRS
check.
v9: Added checks for PSR before updating DRRS. Added check for module
param drrs_interval before updating DRRS (this is required if the interval
is modified by the user during system use). DRRS disabled by default. Changes
based on Jani's review comments
v10: Disable/enable DRRS when PSR is enable/disabled.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_params.c | 8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 30 +++-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 142 +++
6 files changed, 205 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c9d5cf..c4e9b37 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -796,6 +796,12 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -2092,6 +2098,7 @@ struct i915_params {
int enable_ips;
int invert_brightness;
int enable_cmd_parser;
+ int drrs_interval;
/* leave bools at the end to not create holes */
bool enable_hangcheck;
bool fastboot;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d1d7980..2410607 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 0,
+ .drrs_interval = 0,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -152,3 +153,10 @@ MODULE_PARM_DESC(disable_display, "Disable display
(default: false)");
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
"Enable command parsing (1=enabled, 0=disabled [default])");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 0 ms). "
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled. "
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7e4ea8d..c309561 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2542,6 +2542,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->struct_mutex);
@@ -3708,6 +3709,7 @@ static
[Intel-gfx] [PATCH v10 2/6] drm/i915: Parse EDID probed modes for DRRS support
From: Pradeep Bhat
This patch and finds out the lowest refresh rate supported for the resolution
same as the fixed_mode.
It also checks the VBT fields to see if panel supports seamless DRRS or not.
Based on above data it marks whether eDP panel supports seamless DRRS or not.
This information is needed for supporting seamless DRRS switch for certain
power saving usecases. This patch is tested by enabling the DRM logs and
user should see whether Seamless DRRS is supported or not.
v2: Daniel's review comments
Modified downclock deduction based on intel_find_panel_downclock
v3: Chris's review comments
Moved edp_downclock_avail and edp_downclock to intel_panel
v4: Jani's review comments.
Changed name of the enum edp_panel_type to drrs_support type.
Change is_drrs_supported to drrs_support of type enum drrs_support_type.
v5: Incorporated Jani's review comments
Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
and above.
v6: Incorporated Chris's review comments.
Changed initialize to init in intel_drrs_initialize
v7: Incorporated Jani's review comments.
Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
v8: Made changes to track PSR enable/disable throughout system use (instead
of just in the init sequence) for disabling/enabling DRRS. Jani's review
comments.
v9: PSR tracking will be done as part of idleness detection patch. Removed
PSR state tracker in i915_drrs. Jani's review comments.
v10: Added log for DRRS not supported in drrs_init
Signed-off-by: Pradeep Bhat
Signed-off-by: Vandana Kannan
Cc: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 45 +++-
drivers/gpu/drm/i915/intel_drv.h | 16 ++
2 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e48d47c..9f110bd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3632,6 +3632,43 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
I915_READ(pp_div_reg));
}
+static struct drm_display_mode *
+intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
+ struct intel_connector *intel_connector,
+ struct drm_display_mode *fixed_mode)
+{
+ struct drm_connector *connector = &intel_connector->base;
+ struct intel_dp *intel_dp = &intel_dig_port->dp;
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_display_mode *downclock_mode = NULL;
+
+ if (INTEL_INFO(dev)->gen <= 6) {
+ DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
+ return NULL;
+ }
+
+ if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
+ DRM_INFO("VBT doesn't support DRRS\n");
+ return NULL;
+ }
+
+ downclock_mode = intel_find_panel_downclock
+ (dev, fixed_mode, connector);
+
+ if (downclock_mode != NULL &&
+ dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
+ intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
+
+ intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
+ DRM_INFO("seamless DRRS supported for eDP panel.\n");
+ return downclock_mode;
+ } else {
+ DRM_INFO("DRRS not supported\n");
+ return NULL;
+ }
+}
+
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
struct intel_connector *intel_connector,
struct edp_power_seq *power_seq)
@@ -3641,10 +3678,13 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_display_mode *fixed_mode = NULL;
+ struct drm_display_mode *downclock_mode = NULL;
bool has_dpcd;
struct drm_display_mode *scan;
struct edid *edid;
+ intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
+
if (!is_edp(intel_dp))
return true;
@@ -3687,6 +3727,9 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
list_for_each_entry(scan, &connector->probed_modes, head) {
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
fixed_mode = drm_mode_duplicate(dev, scan);
+ downclock_mode = intel_dp_drrs_init(
+ intel_dig_port,
+ intel_connector,
[Intel-gfx] [PATCH v11 4/6] drm/i915: Idleness detection for DRRS
Adding support to detect display idleness by tracking page flip from
user space. Switch to low refresh rate is triggered after 2 seconds of
idleness. The delay is configurable. If there is a page flip or call to
update the plane, then high refresh rate is applied.
The feature is not used in dual-display mode.
v2: Chris Wilson's review comments incorporated.
Modify idleness detection implementation to make it similar to the
implementation of intel_update_fbc/intel_disable_fbc
v3: Internal review comments incorporated
Add NULL pointer check in intel_disable_drrs.
Add drrs calls in i9xx_crtc_enable/disable and valleyview_crtc_enable.
v4: Jani's review comments incorporated.
Change in sequence in intel_update_drrs. Comment modified to remove details
of update param. Modified DRRS idleness interval to a module parameter.
v5: Chris's review comments incorporated.
Initialize connector in idleness detection init. Modifications made to
use only intel_connector in i915_drrs and derive intel_dp when required.
Added a function drrs_fini to cleanup DRRS work.
v6: Internal review comments. Removed check for primary enabled, which is
a redundant check, in the case of clone mode. Added a flag to track
dual-display configuration. Remove print statement for "cancel DRR work"
and print "DRRS not supported" only once.
v7: As per internal review comments, removing calls to update/disable drrs
from sprite update path. For sprite, all drrs related updates would be
taken care of with calls to crtc page flip itself. This will have to be
revisited later if flip infrastructure changes for sprite.
v8: Incorporated Jani's review comments. Added space after the periods in the
module param description. Changes around drrs-fini to remove seamless DRRS
check.
v9: Added checks for PSR before updating DRRS. Added check for module
param drrs_interval before updating DRRS (this is required if the interval
is modified by the user during system use). DRRS disabled by default. Changes
based on Jani's review comments
v10: Disable/enable DRRS when PSR is enable/disabled.
v11: Moved DRRS not supported log to patch2.
Signed-off-by: Vandana Kannan
Signed-off-by: Pradeep Bhat
Cc: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_params.c | 8 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_pm.c | 142 +++
6 files changed, 203 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9da8d83..fb9f9f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -635,6 +635,12 @@ struct i915_fbc {
struct i915_drrs {
struct intel_connector *connector;
+ bool is_clone;
+ struct intel_drrs_work {
+ struct delayed_work work;
+ struct drm_crtc *crtc;
+ int interval;
+ } *drrs_work;
};
struct i915_psr {
@@ -1922,6 +1928,7 @@ struct i915_params {
int enable_ips;
int invert_brightness;
int enable_cmd_parser;
+ int drrs_interval;
/* leave bools at the end to not create holes */
bool enable_hangcheck;
bool fastboot;
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index d05a2af..144ab0b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -48,6 +48,7 @@ struct i915_params i915 __read_mostly = {
.disable_display = 0,
.enable_cmd_parser = 1,
.disable_vtd_wa = 0,
+ .drrs_interval = 0,
};
module_param_named(modeset, i915.modeset, int, 0400);
@@ -156,3 +157,10 @@ MODULE_PARM_DESC(disable_vtd_wa, "Disable all VT-d
workarounds (default: false)"
module_param_named(enable_cmd_parser, i915.enable_cmd_parser, int, 0600);
MODULE_PARM_DESC(enable_cmd_parser,
"Enable command parsing (1=enabled [default], 0=disabled)");
+
+module_param_named(drrs_interval, i915.drrs_interval, int, 0600);
+MODULE_PARM_DESC(drrs_interval,
+ "DRRS idleness detection interval (default: 0 ms). "
+ "If this field is set to 0, then seamless DRRS feature "
+ "based on idleness detection is disabled. "
+ "The interval is to be set in milliseconds.");
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3697433..363ca22 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2523,6 +2523,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ intel_update_drrs(dev);
intel_edp_psr_update(dev);
mutex_unlock(&dev->s
Re: [Intel-gfx] [PATCH v10 2/6] drm/i915: Parse EDID probed modes for DRRS support
On Apr-04-2014 4:25 PM, Jani Nikula wrote:
> On Fri, 04 Apr 2014, Vandana Kannan wrote:
>> From: Pradeep Bhat
>>
>> This patch and finds out the lowest refresh rate supported for the resolution
>> same as the fixed_mode.
>> It also checks the VBT fields to see if panel supports seamless DRRS or not.
>> Based on above data it marks whether eDP panel supports seamless DRRS or not.
>> This information is needed for supporting seamless DRRS switch for certain
>> power saving usecases. This patch is tested by enabling the DRM logs and
>> user should see whether Seamless DRRS is supported or not.
>>
>> v2: Daniel's review comments
>> Modified downclock deduction based on intel_find_panel_downclock
>>
>> v3: Chris's review comments
>> Moved edp_downclock_avail and edp_downclock to intel_panel
>>
>> v4: Jani's review comments.
>> Changed name of the enum edp_panel_type to drrs_support type.
>> Change is_drrs_supported to drrs_support of type enum drrs_support_type.
>>
>> v5: Incorporated Jani's review comments
>> Modify intel_dp_drrs_initialize to return downclock mode. Support for Gen7
>> and above.
>>
>> v6: Incorporated Chris's review comments.
>> Changed initialize to init in intel_drrs_initialize
>>
>> v7: Incorporated Jani's review comments.
>> Removed edp_downclock and edp_downclock_avail. Return NULL explicitly.
>> Make drrs_state and unnamed struct. Move Gen based check inside drrs_init.
>>
>> v8: Made changes to track PSR enable/disable throughout system use (instead
>> of just in the init sequence) for disabling/enabling DRRS. Jani's review
>> comments.
>>
>> v9: PSR tracking will be done as part of idleness detection patch. Removed
>> PSR state tracker in i915_drrs. Jani's review comments.
>>
>> v10: Added log for DRRS not supported in drrs_init
>>
>> Signed-off-by: Pradeep Bhat
>> Signed-off-by: Vandana Kannan
>> Cc: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 45
>> +++-
>> drivers/gpu/drm/i915/intel_drv.h | 16 ++
>> 2 files changed, 60 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index e48d47c..9f110bd 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3632,6 +3632,43 @@ intel_dp_init_panel_power_sequencer_registers(struct
>> drm_device *dev,
>>I915_READ(pp_div_reg));
>> }
>>
>> +static struct drm_display_mode *
>> +intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
>> +struct intel_connector *intel_connector,
>> +struct drm_display_mode *fixed_mode)
>> +{
>> +struct drm_connector *connector = &intel_connector->base;
>> +struct intel_dp *intel_dp = &intel_dig_port->dp;
>> +struct drm_device *dev = intel_dig_port->base.base.dev;
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +struct drm_display_mode *downclock_mode = NULL;
>> +
>> +if (INTEL_INFO(dev)->gen <= 6) {
>> +DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
>> +return NULL;
>> +}
>> +
>> +if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) {
>> +DRM_INFO("VBT doesn't support DRRS\n");
>> +return NULL;
>> +}
>> +
>> +downclock_mode = intel_find_panel_downclock
>> +(dev, fixed_mode, connector);
>> +
>> +if (downclock_mode != NULL &&
>> +dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) {
>> +intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
>> +
>> +intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
>> +DRM_INFO("seamless DRRS supported for eDP panel.\n");
>> +return downclock_mode;
>> +} else {
>> +DRM_INFO("DRRS not supported\n");
>> +return NULL;
>> +}
>
> The above now leaks downclock_mode on the return NULL path. Please try
> to be more careful.
>
> Please let's try to bring this patchset and review into
> conclusion. We'll both end up frustrated otherwise.
>
> How about this instead?
>
> if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
> DRM_INFO("VBT doesn't supp
