[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel,
The commit 7c5c15dffe1e ("drm/i915/gt: Declare gen9 has 64 mocs entries!")
should actually be sent last week along with the commit
777a7717d60c ("drm/i915/gt: Program mocs:63 for cache eviction on gen9"),
but I had missed that and dim didn't cope with fixes for fixes.
Here goes drm-intel-fixes-2020-12-09:
Fixes for VDSC/DP, selftests, shmem_utils, preemption, submission, and gt reset:
- Check the correct variable in selftest (Dan)
- Propagate error from canceled submit due to context closure (Chris)
- Ignore repeated attempts to suspend request flow across reset (Chris)
- Cancel the preemption timeout on responding to it (Chris)
- Fix unsigned compared against 0 (Colin)
- Compute the correct slice count for VDSC on DP (Manasi)
- Declar gen9 has 64 mocs entries (Chris)
Thanks,
Rodrigo.
The following changes since commit 0477e92881850d44910a7e94fc2c46f96faa131f:
Linux 5.10-rc7 (2020-12-06 14:25:12 -0800)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-12-09
for you to fetch changes up to 7c5c15dffe1e3c42f44735ce9552afb7207f1584:
drm/i915/gt: Declare gen9 has 64 mocs entries! (2020-12-08 07:09:58 -0800)
Fixes for VDSC/DP, selftests, shmem_utils, preemption, submission, and gt reset:
- Check the correct variable in selftest (Dan)
- Propagate error from canceled submit due to context closure (Chris)
- Ignore repeated attempts to suspend request flow across reset (Chris)
- Cancel the preemption timeout on responding to it (Chris)
- Fix unsigned compared against 0 (Colin)
- Compute the correct slice count for VDSC on DP (Manasi)
- Declar gen9 has 64 mocs entries (Chris)
Chris Wilson (4):
drm/i915/gem: Propagate error from cancelled submit due to context closure
drm/i915/gt: Ignore repeated attempts to suspend request flow across reset
drm/i915/gt: Cancel the preemption timeout on responding to it
drm/i915/gt: Declare gen9 has 64 mocs entries!
Colin Ian King (1):
drm/i915: fix size_t greater or equal to zero comparison
Dan Carpenter (1):
drm/i915/gem: Check the correct variable in selftest
Manasi Navare (1):
drm/i915/display/dp: Compute the correct slice count for VDSC on DP
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 7 +--
drivers/gpu/drm/i915/gt/intel_lrc.c| 7 ++-
drivers/gpu/drm/i915/gt/intel_mocs.c | 7 +++
drivers/gpu/drm/i915/gt/shmem_utils.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 4 ++--
6 files changed, 18 insertions(+), 11 deletions(-)
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Re: [Intel-gfx] [PATCH] drm/i915/display/tc: Only WARN once for bogus tc port flag
On Wed, Dec 09, 2020 at 04:16:36PM -0500, Sean Paul wrote: > From: Sean Paul > > No need to spam syslog/console when we can ignore/fix the flag. besides that we are calling from multiple places anyway.. > > Signed-off-by: Sean Paul Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display/intel_tc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c > b/drivers/gpu/drm/i915/display/intel_tc.c > index 4346bc1a747a..27dc2dad6809 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -262,7 +262,7 @@ static u32 tc_port_live_status_mask(struct > intel_digital_port *dig_port) > mask |= BIT(TC_PORT_LEGACY); > > /* The sink can be connected only in a single mode. */ > - if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) > + if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1)) > tc_port_fixup_legacy_flag(dig_port, mask); > > return mask; > -- > Sean Paul, Software Engineer, Google / Chromium OS > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/display: Go softly softly on initial modeset failure
On Thu, Dec 10, 2020 at 11:07:41PM +, Chris Wilson wrote:
> Reduce the module/device probe error into a mere debug to hide issues
> where the initial modeset is failing (after lies told by hw probe) and
> the system hangs with a livelock in cleaning up the failed commit.
>
> Reported-by: H.J. Lu
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=210619
> Fixes: b3bf99daaee9 ("drm/i915/display: Defer initial modeset until after
> GGTT is initialised")
> Fixes: ccc9e67ab26f ("drm/i915/display: Defer initial modeset until after
> GGTT is initialised")
> Signed-off-by: Chris Wilson
> Cc: "Ville Syrjälä"
> Cc: Rodrigo Vivi
> Cc: H.J. Lu
> Cc: Dave Airlie
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c567c0cada7e..761be8deaa9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18755,7 +18755,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
>*/
> ret = intel_initial_commit(&i915->drm);
> if (ret)
> - return ret;
> + drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
>
> intel_overlay_setup(i915);
>
> --
> 2.20.1
>
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[Intel-gfx] [PATCH] drm/i915/dg1: Fix power gate sequence.
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.
Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.")
Cc: Dale B Stimson
Cc: Chris Wilson
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index d7b8e4457fc2..79f63cdd8bfb 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -110,7 +110,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
- if (INTEL_GEN(gt->i915) >= 12) {
+ if (INTEL_GEN(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
for (i = 0; i < I915_MAX_VCS; i++)
if (HAS_ENGINE(gt, _VCS(i)))
pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
--
2.29.2
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[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel, Happy New Year. Here goes the first pull request targeting 5.12. drm-intel-next-2021-01-04: - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani)\ . - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Thanks, Rodrigo. The following changes since commit b3bf99daaee96a141536ce5c60a0d6dba6ec1d23: drm/i915/display: Defer initial modeset until after GGTT is initialised (2020-11-26 11:01:52 +) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-04 for you to fetch changes up to b3304591f14b437b6bccd8dbff06006c11837031: drm/i915/dp: Track pm_qos per connector (2020-12-30 21:22:55 +) - Display hotplug fix for gen2/gen3 (Chris) - Remove trailing semicolon (Tom) - Suppress display warnings for old ifwi presend on our CI (Chris) - OA/Perf related workaround (Lionel) - Replace I915_READ/WRITE per new uncore and display read/write functions (Jani)\ . - PSR improvements (Jose) - HDR and other color changes on LSPCON (Uma, Ville) - FBC fixes for TGL (Uma) - Record plane update times for debugging (Chris) - Refactor panel backlight control functions (Dave) - Display power improvements (Imre) - Add VRR register definition (Manasi) - Atomic modeset improvements for bigjoiner pipes (Ville) - Switch off the scanout during driver unregister (Chris) - Clean-up DP's FEW enable (Manasi) - Fix VDSCP slice count (Manasi) - Fix and clean up around rc_model_size for DSC (Jani) - Remove Type-C noisy debug warn message (Sean) - Display HPD code clean-up (Ville) - Refactor Intel Display (Dave) - Start adding support for Intel's eDP backlight controls (Lyude) Chris Wilson (6): Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" drm/i915/display: Suppress "Combo PHY A HW state changed unexpectedly" drm/i915/display: Record the plane update times for debugging drm/i915/gem: Spring clean debugfs drm/i915: Disable outputs during unregister drm/i915/dp: Track pm_qos per connector Dave Airlie (6): drm/i915: refactor panel backlight control functions. (v2) drm/i915/display: move needs_modeset to an inline in header drm/i915/display: move to_intel_frontbuffer to header drm/i915/display: fix misused comma drm/i915: refactor cursor code out of i915_display.c drm/i915: refactor i915 plane code into separate file. Imre Deak (10): drm/i915: Use CRTC index consistently during getting/putting CRTC power domains drm/i915: Factor out helpers to get/put a set of tracked power domains drm/i915: Track power references taken for enabled CRTCs drm/i915/ddi: Track power reference taken for encoder DDI IO use drm/i915/ddi: Track power reference taken for encoder main lane AUX use drm/i915: Track power reference taken for eDP VDD drm/i915: Rename power_domains.wakeref to init_wakeref drm/i915: Track power reference taken to disable power well functionality drm/i915: Make intel_display_power_put_unchecked() an internal-only function drm/i915/icl: Fix initing the DSI DSC power refcount during HW readout Jani Nikula (15): drm/i915/debugfs: remove RPS autotuning details from i915_rps_boost_info drm/i915: remove last traces of I915_READ_FW() and I915_WRITE_FW() drm/i915/cdclk: prefer intel_de_write() over I915_WRITE() drm/i915/debugfs: remove the i915_cache_sharing debugfs file drm/i915/debugfs: replace I915_READ() with intel_uncore_read() drm/i915/suspend: replace I915_READ()/WRITE() with intel_de_read()/write() drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write() drm/i915/irq: replace I915_READ()/WRITE() with intel_uncore_read()/write() drm/i915/gvt: replace I915_WRITE with intel_uncore_write drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ() drm/dsc: use rc_model_size from DSC config for PPS drm/i915/dsc: configure hardware
Re: [Intel-gfx] [PULL] gvt-next-fixes
On Tue, Jan 05, 2021 at 10:36:54AM +0200, Jani Nikula wrote: > On Tue, 05 Jan 2021, Zhenyu Wang wrote: > > Ping... > > I suppose this should be merged to drm-intel-next (or drm-intel-gt-next, > or both). It was too late for next-fixes, and it's really not the kind > of fixes we need to queue to v5.11-rc's. > > Rodrigo? I believe drm-intel-next should be enough for this... Pulled. Thanks, Rodrigo. > > BR, > Jani. > > > > > On 2020.12.25 10:20:09 +0800, Zhenyu Wang wrote: > >> > >> Hi, > >> > >> Here's queued fixes from Jani for one useless inline and fix > >> CONFIG_DRM_I915_WERROR for gvt headers. > >> > >> Thanks and Merry Christmas! > >> -- > >> The following changes since commit > >> 9a3a238b3de97b4210c6de66aa88b2d7021ac086: > >> > >> drm/i915/gvt: treat intel_gvt_mpt as const in gvt code (2020-11-23 > >> 17:14:20 +0800) > >> > >> are available in the Git repository at: > >> > >> https://github.com/intel/gvt-linux tags/gvt-next-fixes-2020-12-25 > >> > >> for you to fetch changes up to e056f669dbf76b8752b6cb0b8edd2f75cbdcabb1: > >> > >> drm/i915/gvt: make mpt.h self-contained (2020-12-22 11:41:35 +0800) > >> > >> > >> gvt-next-fixes-2020-12-25 > >> > >> - Avoid one useless inline (Jani) > >> - make gvt header self-contained, fix CONFIG_DRM_I915_WERROR (Jani) > >> > >> > >> Jani Nikula (9): > >> drm/i915/gvt: avoid useless use of inline > >> drm/i915/gvt: make execlist.h self-contained > >> drm/i915/gvt: make fb_decoder.h self-contained > >> drm/i915/gvt: make gtt.h self-contained > >> drm/i915/gvt: make interrupt.h self-contained > >> drm/i915/gvt: make mmio_context.h self-contained > >> drm/i915/gvt: make gvt.h self-contained > >> drm/i915/gvt: make scheduler.h self-contained > >> drm/i915/gvt: make mpt.h self-contained > >> > >> drivers/gpu/drm/i915/Makefile | 10 +- > >> drivers/gpu/drm/i915/gvt/execlist.h | 3 --- > >> drivers/gpu/drm/i915/gvt/fb_decoder.h | 6 -- > >> drivers/gpu/drm/i915/gvt/gtt.h | 11 ++- > >> drivers/gpu/drm/i915/gvt/gvt.h | 4 > >> drivers/gpu/drm/i915/gvt/handlers.c | 3 +-- > >> drivers/gpu/drm/i915/gvt/interrupt.h| 5 - > >> drivers/gpu/drm/i915/gvt/mmio_context.h | 11 +++ > >> drivers/gpu/drm/i915/gvt/mpt.h | 2 ++ > >> drivers/gpu/drm/i915/gvt/scheduler.h| 5 + > >> 10 files changed, 42 insertions(+), 18 deletions(-) > >> > >> -- > >> > >> $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 > > > > > > > >> ___ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Limit VFE threads based on GT
On Fri, Oct 16, 2020 at 06:54:11PM +0100, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
we need to get this closed...
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Prathap Kumar Valsan
> Cc: Akeem G Abodunrin
> Cc: Balestrieri Francesco
> Cc: Bloomfield Jon
> Cc: # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 35 +++---
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..f3b8fea6226e 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,8 +32,7 @@ struct batch_chunk {
> };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> + u32 max_primitives; /* == number of VFE threads */
> u32 cmd_size;
> u32 state_size;
> u32 state_start;
> @@ -50,18 +47,35 @@ static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_primitives = 70;
> + break;
> + case 2:
> + bv->max_primitives = 140;
> + break;
> + case 3:
> + bv->max_primitives = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_primitives = 36;
> + break;
> + case 2:
> + bv->max_primitives = 128;
> + break;
> + }
> bv->surface_height = 16 * 8;
> bv->surface_width = 32 * 16;
> }
> bv->cmd_size = bv->max_primitives * 4096;
> - bv->state_size = STATE_SIZE;
> + bv->state_size = SZ_4K;
> bv->state_start = bv->cmd_size;
> bv->batch_size = bv->cmd_size + bv->state_size;
> bv->scratch_size = bv->surface_height * bv->surface_width;
> @@ -244,7 +258,6 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> u32 urb_size, u32 curbe_size,
> u32 mode)
> {
> - u32 urb_entries = bv->max_urb_entries;
> u32 threads = bv->max_primitives - 1;
> u32 *cs = batch_alloc_items(batch, 32, 8);
>
> @@ -254,7 +267,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch,
> *cs++ = 0;
>
> /* number of threads & urb entries for GPGPU vs Media Mode */
> - *cs++ = threads << 16 | urb_entries << 8 | mode << 2;
> + *cs++ = threads << 16 | 1 << 8 | mode << 2;
why urb_entries = 1 ?
the range is 0,64 and 0,128 depending on the sku.
in general there's a min of 32 URBs
>
> *cs++ = 0;
>
> --
> 2.20.1
>
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Re: [Intel-gfx] [PATCH 01/11] drm/i915/gt: Limit VFE threads based on GT
On Sun, Jan 10, 2021 at 03:03:54PM +, Chris Wilson wrote:
> MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> based on plaform and the number of EU based on the number of slices and
> subslices. This is a fixed number per platform/gt, so appropriately
> limit the number of threads we spawn to match the device.
>
> v2: Oversaturate the system with tasks to force execution on every HW
> thread; if the thread idles it is returned to the pool and may be reused
> again before an unused thread.
>
> v3: Fix more state commands, which was causing Baytrail to barf.
CI is still not happy with byt right? or is that false positive?
> v4: STATE_CACHE_INVALIDATE requires a stall on Ivybridge
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Prathap Kumar Valsan
> Cc: Akeem G Abodunrin
> Cc: Jon Bloomfield
> Cc: Rodrigo Vivi
> Cc: Randy Wright
> Cc: sta...@vger.kernel.org # v5.7+
> ---
> drivers/gpu/drm/i915/gt/gen7_renderclear.c | 157 -
> 1 file changed, 94 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> index d93d85cd3027..f32a8e8040b2 100644
> --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> @@ -7,8 +7,6 @@
> #include "i915_drv.h"
> #include "intel_gpu_commands.h"
>
> -#define MAX_URB_ENTRIES 64
> -#define STATE_SIZE (4 * 1024)
> #define GT3_INLINE_DATA_DELAYS 0x1E00
> #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
>
> @@ -34,38 +32,59 @@ struct batch_chunk {
> };
>
> struct batch_vals {
> - u32 max_primitives;
> - u32 max_urb_entries;
> - u32 cmd_size;
> - u32 state_size;
> + u32 max_threads;
> u32 state_start;
> - u32 batch_size;
> + u32 surface_start;
> u32 surface_height;
> u32 surface_width;
> - u32 scratch_size;
> - u32 max_size;
> + u32 size;
> };
>
> +static inline int num_primitives(const struct batch_vals *bv)
> +{
> + /*
> + * We need to saturate the GPU with work in order to dispatch
> + * a shader on every HW thread, and clear the thread-local registers.
> + * In short, we have to dispatch work faster than the shaders can
> + * run in order to fill occupy each HW thread.
> + */
> + return bv->max_threads;
> +}
> +
> static void
> batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> if (IS_HASWELL(i915)) {
> - bv->max_primitives = 280;
> - bv->max_urb_entries = MAX_URB_ENTRIES;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1:
> + bv->max_threads = 70;
> + break;
> + case 2:
> + bv->max_threads = 140;
> + break;
> + case 3:
> + bv->max_threads = 280;
> + break;
> + }
> bv->surface_height = 16 * 16;
> bv->surface_width = 32 * 2 * 16;
> } else {
> - bv->max_primitives = 128;
> - bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> + switch (INTEL_INFO(i915)->gt) {
> + default:
> + case 1: /* including vlv */
> + bv->max_threads = 36;
> + break;
> + case 2:
> + bv->max_threads = 128;
> + break;
> + }
> bv->surface_height = 16 * 8;
> bv->surface_width = 32 * 16;
all the values above matches the spec.
> }
> - bv->cmd_size = bv->max_primitives * 4096;
> - bv->state_size = STATE_SIZE;
> - bv->state_start = bv->cmd_size;
> - bv->batch_size = bv->cmd_size + bv->state_size;
> - bv->scratch_size = bv->surface_height * bv->surface_width;
> - bv->max_size = bv->batch_size + bv->scratch_size;
> + bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
> + bv->surface_start = bv->state_start + SZ_4K;
> + bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
I liked this batch values simplification...
> }
>
> static void batch_init(struct
Re: [Intel-gfx] [PATCH 02/11] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail
On Sun, Jan 10, 2021 at 03:03:55PM +, Chris Wilson wrote:
> The mitigation is required for all gen7 platforms, now that it does not
> cause GPU hangs, restore it for Ivybridge and Baytrail.
>
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Prathap Kumar Valsan
> Cc: Akeem G Abodunrin
> Cc: Bloomfield Jon
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 1c6d421f6fe5..724d56c9583d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1324,7 +1324,7 @@ int intel_ring_submission_setup(struct intel_engine_cs
> *engine)
>
> GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
>
> - if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
> + if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
when CI is really happy
Reviewed-by: Rodrigo Vivi
> err = gen7_ctx_switch_bb_init(engine);
> if (err)
> goto err_ring_unpin;
> --
> 2.20.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] drm/i915: Allow the sysadmin to override security mitigations
On Sun, Jan 10, 2021 at 03:03:56PM +, Chris Wilson wrote:
> The clear-residuals mitigation is a relatively heavy hammer and under some
> circumstances the user may wish to forgo the context isolation in order
> to meet some performance requirement. Introduce a generic module
> parameter to allow selectively enabling/disabling different mitigations.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1858
I'm afraid this will have the same faith as the rc6 and the validation impact :/
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Jon Bloomfield
> Cc: Rodrigo Vivi
> Cc: sta...@vger.kernel.org # v5.7
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../gpu/drm/i915/gt/intel_ring_submission.c | 4 +-
> drivers/gpu/drm/i915/i915_mitigations.c | 148 ++
> drivers/gpu/drm/i915/i915_mitigations.h | 13 ++
> 4 files changed, 165 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/i915_mitigations.c
> create mode 100644 drivers/gpu/drm/i915/i915_mitigations.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 4074d8cb0d6e..48f82c354611 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -38,6 +38,7 @@ i915-y += i915_drv.o \
> i915_config.o \
> i915_irq.o \
> i915_getparam.o \
> + i915_mitigations.o \
> i915_params.o \
> i915_pci.o \
> i915_scatterlist.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 724d56c9583d..657afd8ebc14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -32,6 +32,7 @@
> #include "gen6_ppgtt.h"
> #include "gen7_renderclear.h"
> #include "i915_drv.h"
> +#include "i915_mitigations.h"
> #include "intel_breadcrumbs.h"
> #include "intel_context.h"
> #include "intel_gt.h"
> @@ -918,7 +919,8 @@ static int switch_context(struct i915_request *rq)
> GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
>
> if (engine->wa_ctx.vma && ce != engine->kernel_context) {
> - if (engine->wa_ctx.vma->private != ce) {
> + if (engine->wa_ctx.vma->private != ce &&
> + i915_mitigate_clear_residuals()) {
> ret = clear_residuals(rq);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/i915_mitigations.c
> b/drivers/gpu/drm/i915/i915_mitigations.c
> new file mode 100644
> index ..8d5637cfa734
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_mitigations.c
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "i915_drv.h"
> +#include "i915_mitigations.h"
> +
> +static unsigned long mitigations = ~0UL;
> +
> +enum {
> + CLEAR_RESIDUALS = 0,
specially worse if this list grows...
> +};
> +
> +static const char * const names[] = {
> + [CLEAR_RESIDUALS] = "residuals",
> +};
> +
> +bool i915_mitigate_clear_residuals(void)
> +{
> + return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
> +}
> +
> +static int mitigations_set(const char *val, const struct kernel_param *kp)
> +{
> + unsigned long new = ~0UL;
> + char *str, *sep, *tok;
> + bool first = true;
> + int err = 0;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(names) >= BITS_PER_TYPE(mitigations));
> +
> + str = kstrdup(val, GFP_KERNEL);
> + if (!str)
> + return -ENOMEM;
> +
> + for (sep = str; (tok = strsep(&sep, ","));) {
> + bool enable = true;
> + int i;
> +
> + /* Be tolerant of leading/trailing whitespace */
> + tok = strim(tok);
> +
> + if (first) {
> + first = false;
> +
> + if (!strcmp(tok, "auto")) {
> + new = ~0UL;
> + continue;
> + }
> +
> + new = 0;
> + if (!strcmp(tok, "off"))
> + continue;
> + }
> +
> + if (*tok == '!') {
> + enable
Re: [Intel-gfx] [PATCH 01/11] drm/i915/gt: Limit VFE threads based on GT
On Mon, Jan 11, 2021 at 08:51:23PM +, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2021-01-11 17:35:12)
> > On Sun, Jan 10, 2021 at 03:03:54PM +, Chris Wilson wrote:
> > > MEDIA_STATE_VFE only accepts the 'maximum number of threads' in the
> > > range [0, n-1] where n is #EU * (#threads/EU) with the number of threads
> > > based on plaform and the number of EU based on the number of slices and
> > > subslices. This is a fixed number per platform/gt, so appropriately
> > > limit the number of threads we spawn to match the device.
> > >
> > > v2: Oversaturate the system with tasks to force execution on every HW
> > > thread; if the thread idles it is returned to the pool and may be reused
> > > again before an unused thread.
> > >
> > > v3: Fix more state commands, which was causing Baytrail to barf.
> >
> > CI is still not happy with byt right? or is that false positive?
>
> After v3, ivb still failed.
>
> > > v4: STATE_CACHE_INVALIDATE requires a stall on Ivybridge
>
> Right now with the multiple pipecontrls around the PIPELINE_SELECT *and*
> STATE_BASE, CI has been happy for multiple runs. I was able to reproduce
> the same selftests failures and confirm that we do not see any of those
> failures in a thousand iterations. High level of confidence, but since
> we are dealing with empirical results with cross-referencing to mesa who
> also have seen similar undocumented failures, there's still an element
> of doubt as to whether it is truly watertight.
>
> The CI results for this series passed on the all important ivb,byt,hsw.
great!
>
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2024
> > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> > > Signed-off-by: Chris Wilson
> > > Cc: Mika Kuoppala
> > > Cc: Prathap Kumar Valsan
> > > Cc: Akeem G Abodunrin
> > > Cc: Jon Bloomfield
> > > Cc: Rodrigo Vivi
> > > Cc: Randy Wright
> > > Cc: sta...@vger.kernel.org # v5.7+
> > > ---
> > > drivers/gpu/drm/i915/gt/gen7_renderclear.c | 157 -
> > > 1 file changed, 94 insertions(+), 63 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> > > b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> > > index d93d85cd3027..f32a8e8040b2 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
> > > @@ -7,8 +7,6 @@
> > > #include "i915_drv.h"
> > > #include "intel_gpu_commands.h"
> > >
> > > -#define MAX_URB_ENTRIES 64
> > > -#define STATE_SIZE (4 * 1024)
> > > #define GT3_INLINE_DATA_DELAYS 0x1E00
> > > #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
> > >
> > > @@ -34,38 +32,59 @@ struct batch_chunk {
> > > };
> > >
> > > struct batch_vals {
> > > - u32 max_primitives;
> > > - u32 max_urb_entries;
> > > - u32 cmd_size;
> > > - u32 state_size;
> > > + u32 max_threads;
> > > u32 state_start;
> > > - u32 batch_size;
> > > + u32 surface_start;
> > > u32 surface_height;
> > > u32 surface_width;
> > > - u32 scratch_size;
> > > - u32 max_size;
> > > + u32 size;
> > > };
> > >
> > > +static inline int num_primitives(const struct batch_vals *bv)
> > > +{
> > > + /*
> > > + * We need to saturate the GPU with work in order to dispatch
> > > + * a shader on every HW thread, and clear the thread-local
> > > registers.
> > > + * In short, we have to dispatch work faster than the shaders can
> > > + * run in order to fill occupy each HW thread.
> > > + */
> > > + return bv->max_threads;
> > > +}
> > > +
> > > static void
> > > batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> > > {
> > > if (IS_HASWELL(i915)) {
> > > - bv->max_primitives = 280;
> > > - bv->max_urb_entries = MAX_URB_ENTRIES;
> > > + switch (INTEL_INFO(i915)->gt) {
> > > + default:
> > > + case 1:
> > > + bv->max_threads = 70;
> > > + break;
> > > + case 2:
> > > +
Re: [Intel-gfx] [PATCH V4] drm/i915/gen9_bc : Add TGP PCH support
On Fri, Jan 08, 2021 at 05:39:22PM +0530, Tejas Upadhyay wrote:
> We have TGP PCH support for Tigerlake and Rocketlake. Similarly
> now TGP PCH can be used with Cometlake CPU.
>
> Changes since V3 :
> - Rebased to top drm-tip commit
> - dev_priv replaced with i915 for new API
> - Enable default Port B,C,D detection for TGP && GEN9_BC
> Changes since V2 :
> - IS_COMETLAKE replaced with IS_GEN9_BC
> - VBT ddc pin remapping added
> - Added dedicated HPD pin and DDC pin handling API
> Changes since V1 :
> - Matched HPD Pin mapping for PORT C and PORT D of CML CPU.
>
> Cc: Matt Roper
> Cc: Jani Nikula
> Signed-off-by: Tejas Upadhyay
> ---
> drivers/gpu/drm/i915/display/intel_bios.c| 9 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> drivers/gpu/drm/i915/display/intel_display.c | 9 -
> drivers/gpu/drm/i915/display/intel_hdmi.c| 20
> drivers/gpu/drm/i915/intel_pch.c | 3 ++-
> 5 files changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 987cf509337f..730b7f45e5d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1630,6 +1630,12 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = {
> [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
> };
>
> +static const u8 gen9bc_tgp_ddc_pin_map[] = {
> + [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> + [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
> + [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
> +};
Could you please point out the spec you are using here?
VBT's spec at BSpec - at Block 2
I can see the TGP table is same as ICP.
So I'm kind of confused now.
> +
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> const u8 *ddc_pin_map;
> @@ -1640,6 +1646,9 @@ static u8 map_ddc_pin(struct drm_i915_private
> *dev_priv, u8 vbt_pin)
> } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) ==
> PCH_TGP) {
> ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
> n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
> + } else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) {
> + ddc_pin_map = gen9bc_tgp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
> } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
> ddc_pin_map = icp_ddc_pin_map;
> n_entries = ARRAY_SIZE(icp_ddc_pin_map);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3df6913369bc..13f1268e2cff 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5337,7 +5337,9 @@ static enum hpd_pin dg1_hpd_pin(struct drm_i915_private
> *dev_priv,
> static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (port >= PORT_TC1)
> + if (IS_GEN9_BC(dev_priv) && port >= PORT_C)
gen9 in tgl function?!
please, no!
> + return HPD_PORT_TC1 + port - PORT_C;
> + else if (port >= PORT_TC1)
> return HPD_PORT_TC1 + port - PORT_TC1;
> else
> return HPD_PORT_A + port - PORT_A;
> @@ -5493,7 +5495,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
> else if (IS_ROCKETLAKE(dev_priv))
> encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
> - else if (INTEL_GEN(dev_priv) >= 12)
> + else if (INTEL_GEN(dev_priv) >= 12 || (IS_GEN9_BC(dev_priv) &&
> +HAS_PCH_TGP(dev_priv)))
Here's another aspect that I don't like in this code.
It mixes the gfx gen with the PCH in many places.
Something is not right...
> encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
> else if (IS_JSL_EHL(dev_priv))
> encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0189d379a55e..81c93c49ddef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16212,7 +16212,14 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>
> /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP
>* register */
> - found = intel_de_read(dev_priv, SFUSE_STRAP);
> + if (HAS_PCH_TGP(dev_priv)) {
> + /* W/A due to lack of STRAP config on TGP PCH*/
> + found = (SFUSE_STRAP_DDIB_DETECTED |
> + SFUSE_STRAP_DDIC_DETECTED |
> + SFUSE_STRAP_DDID_DETECTED);
> + } else {
> + found = int
[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel,
A very short collection of patches, mostly with display fixes. Plus GVT.
The goal is to get both drm-intel-next and drm-intel-gt-next in sync again
through drm-next backports so we can continue with ADL enabling in a topic
branch.
Please be aware that there's a drm only patch here:
commit 7d8ac172d7f1 ("drm: Add function to convert rect in 16.16 fixed format
to regular format")
Here goes drm-intel-next-2021-01-12:
- PSR fixes and improvements for selective fetch (Jose)
- GVT build fixed and cleanup (Jani)
- RKL display fixes (Lee, Matt)
- DSI fix (Hans)
- Panel Power and Backlight fixes (Anshuman, Jani)
- RPM fix (Chris)
- Fix HTI port checking (Jose)
- Clean-up in cursor code (Ville)
- Once again, trying to use fast+narrow link on eDP (Ville)
- DG1 display fix (Matt)
Thanks,
Rodrigo.
The following changes since commit cb3cfbf79aff7decb4e5ee69a7c74864497f61dc:
Merge tag 'drm-misc-next-2021-01-06' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next (2021-01-07 13:40:20
+0100)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-12
for you to fetch changes up to cce73665eae238791f4342b29ca54188227717c8:
drm/i915/dg1: Update voltage swing tables for DP (2021-01-11 19:20:18 -0800)
- PSR fixes and improvements for selective fetch (Jose)
- GVT build fixed and cleanup (Jani)
- RKL display fixes (Lee, Matt)
- DSI fix (Hans)
- Panel Power and Backlight fixes (Anshuman, Jani)
- RPM fix (Chris)
- Fix HTI port checking (Jose)
- Clean-up in cursor code (Ville)
- Once again, trying to use fast+narrow link on eDP (Ville)
- DG1 display fix (Matt)
Anshuman Gupta (1):
drm/i915/pps: Reuse POWER_DOMAIN_DISPLAY_CORE in pps_{lock, unlock}
Chris Wilson (1):
drm/i915: Disable RPM wakeref assertions during driver shutdown
Hans de Goede (1):
drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there
is no reset-deassert MIPI-sequence
Jani Nikula (10):
drm/i915/gvt: avoid useless use of inline
drm/i915/gvt: make execlist.h self-contained
drm/i915/gvt: make fb_decoder.h self-contained
drm/i915/gvt: make gtt.h self-contained
drm/i915/gvt: make interrupt.h self-contained
drm/i915/gvt: make mmio_context.h self-contained
drm/i915/gvt: make gvt.h self-contained
drm/i915/gvt: make scheduler.h self-contained
drm/i915/gvt: make mpt.h self-contained
drm/i915/backlight: fix CPU mode backlight takeover on LPT
José Roberto de Souza (5):
drm: Add function to convert rect in 16.16 fixed format to regular format
drm/i915/display/psr: Use plane damage clips to calculate damaged area
drm/i915/display: Split and export main surface calculation from
skl_check_main_surface()
drm/i915/display/psr: Program plane's calculated offset to plane SF
register
drm/i915: Fix HTI port checking
Lee Shawn C (1):
drm/i915/rkl: new rkl ddc map for different PCH
Matt Roper (2):
drm/i915/rkl: Add DP vswing programming tables
drm/i915/dg1: Update voltage swing tables for DP
Rodrigo Vivi (2):
Merge tag 'gvt-next-fixes-2020-12-25' of
https://github.com/intel/gvt-linux into drm-intel-next
Merge drm/drm-next into drm-intel-next
Ville Syrjälä (2):
drm/i915: Fix checkpatch warns in cursor code
drm/i915: Try to use fast+narrow link on eDP again and fall back to the
old max strategy on failure
drivers/gpu/drm/i915/Makefile | 10 +-
drivers/gpu/drm/i915/display/intel_bios.c | 10 ++
drivers/gpu/drm/i915/display/intel_cursor.c| 6 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 79 -
drivers/gpu/drm/i915/display/intel_display.c | 78 -
drivers/gpu/drm/i915/display/intel_display.h | 2 +
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 83 +++---
drivers/gpu/drm/i915/display/intel_panel.c | 9 +-
drivers/gpu/drm/i915/display/intel_psr.c | 127 ++---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 16 ++-
drivers/gpu/drm/i915/gvt/execlist.h| 3 -
drivers/gpu/drm/i915/gvt/fb_decoder.h | 6 +-
drivers/gpu/drm/i915/gvt/gtt.h | 11 +-
drivers/gpu/drm/i915/gvt/gvt.h | 4 +
drivers/gpu/drm/i915/gvt/handlers.c| 3 +-
drivers/gpu/drm/i915/gvt/interrupt.h | 5 +-
drivers/gpu/drm/i915/gvt/mmio_context.h| 11 ++
drivers/gpu/drm/i915/gvt/mpt.h | 2 +
drivers/gpu/drm/i915/gvt/scheduler.h | 5 +
drivers/gpu/drm/i915/i915_drv.c
Re: [Intel-gfx] regression on fedora 5.12 on Lenovo T400
On Tue, May 25, 2021 at 04:28:20PM +1000, Dave Airlie wrote:
> https://bugzilla.redhat.com/show_bug.cgi?id=1964252
>
> dmesg below.
> Feel free to point me at any fixes already in flight.
Hi Dave,
sorry for the delay here, but I'd like to just confirm if we are on the
same page that this got fixed with this patch:
036867e93ebf ("drm/i915/gem: Pin the L-shape quirked object as unshrinkable")
is this your current understanding?
>
> Dave.
>
> [ 140.302041] list_add double add: new=9ed109790fe0,
> prev=9ed109790fe0, next=9ed109465b38.
> [ 140.302076] [ cut here ]
> [ 140.302078] kernel BUG at lib/list_debug.c:29!
> [ 140.302091] invalid opcode: [#1] SMP PTI
> [ 140.302097] CPU: 1 PID: 1712 Comm: Xorg Kdump: loaded Tainted: G
> I 5.12.5-300.fc34.x86_64 #1
> [ 140.302103] Hardware name: LENOVO 6475H82/6475H82, BIOS 7UET91WW
> (3.21 ) 12/06/2010
> [ 140.302106] RIP: 0010:__list_add_valid.cold+0x26/0x3f
> [ 140.302117] Code: ee c1 a6 ff 4c 89 c1 48 c7 c7 f8 4d 41 9b e8 12
> 2c fe ff 0f 0b 48 89 f2 4c 89 c1 48 89 fe 48 c7 c7 a8 4e 41 9b e8 fb
> 2b fe ff <0f> 0b 48 89 d1 4c 89 c6 4c 89 ca 48 c7 c7 50 4e 41 9b e8 e4
> 2b fe
> [ 140.302122] RSP: 0018:ad63c0cbfcf8 EFLAGS: 00010082
> [ 140.302127] RAX: 0058 RBX: 9ed109790d00 RCX:
>
> [ 140.302131] RDX: 9ed137ca6720 RSI: 9ed137c985c0 RDI:
> 9ed137c985c0
> [ 140.302135] RBP: 9ed109465b38 R08: R09:
> ad63c0cbfb30
> [ 140.302139] R10: ad63c0cbfb28 R11: 9bb45f28 R12:
> 9ed10946
> [ 140.302142] R13: 0246 R14: 9ed109465b20 R15:
> 9ed109790fe0
> [ 140.302146] FS: 7f0edf882a80() GS:9ed137c8()
> knlGS:
> [ 140.302151] CS: 0010 DS: ES: CR0: 80050033
> [ 140.302155] CR2: 7f0ed7ba2001 CR3: 00011ff34000 CR4:
> 000406e0
> [ 140.302159] Call Trace:
> [ 140.302166] __i915_gem_object_make_shrinkable+0xa5/0xe0 [i915]
> [ 140.302330] i915_gem_object_set_tiling+0x4fe/0x530 [i915]
> [ 140.302473] i915_gem_set_tiling_ioctl+0x112/0x250 [i915]
> [ 140.302613] ? i915_gem_object_set_tiling+0x530/0x530 [i915]
> [ 140.302755] drm_ioctl_kernel+0x86/0xd0 [drm]
> [ 140.302819] drm_ioctl+0x20f/0x3c0 [drm]
> [ 140.302870] ? i915_gem_object_set_tiling+0x530/0x530 [i915]
> [ 140.303013] __x64_sys_ioctl+0x82/0xb0
> [ 140.303020] do_syscall_64+0x33/0x40
> [ 140.303026] entry_SYSCALL_64_after_hwframe+0x44/0xae
> [ 140.303033] RIP: 0033:0x7f0ee01070ab
> [ 140.303038] Code: ff ff ff 85 c0 79 9b 49 c7 c4 ff ff ff ff 5b 5d
> 4c 89 e0 41 5c c3 66 0f 1f 84 00 00 00 00 00 f3 0f 1e fa b8 10 00 00
> 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 95 bd 0c 00 f7 d8 64 89
> 01 48
> [ 140.303043] RSP: 002b:7ffc7bf48ff8 EFLAGS: 0246 ORIG_RAX:
> 0010
> [ 140.303048] RAX: ffda RBX: 55c6591c78d0 RCX:
> 7f0ee01070ab
> [ 140.303052] RDX: 7ffc7bf49010 RSI: c0106461 RDI:
> 0011
> [ 140.303056] RBP: 7ffc7bf49060 R08: 55c6583b39e0 R09:
>
> [ 140.303059] R10: 7f0ee01d3a00 R11: 0246 R12:
>
> [ 140.303063] R13: 55c6583b38c0 R14: c0106461 R15:
> 7ffc7bf49010
> [ 140.303069] Modules linked in: xt_CHECKSUM xt_MASQUERADE
> xt_conntrack ipt_REJECT nf_nat_tftp nf_conntrack_tftp bridge stp llc
> nft_objref nf_conntrack_netbios_ns nf_conntrack_broadcast nft_fib_inet
> nft_fib_ipv4 nft_fib_ipv6 nft_fib nft_reject_inet nf_reject_ipv4
> nf_reject_ipv6 nft_reject nft_ct nft_chain_nat ip6table_nat
> ip6table_mangle ip6table_raw ip6table_security iptable_nat nf_nat
> nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 iptable_mangle iptable_raw
> iptable_security ip_set nf_tables nfnetlink ip6table_filter ip6_tables
> iptable_filter sunrpc coretemp kvm_intel iTCO_wdt kvm intel_pmc_bxt
> mei_wdt iTCO_vendor_support snd_hda_codec_conexant
> snd_hda_codec_generic snd_hda_intel snd_intel_dspcfg
> snd_intel_sdw_acpi irqbypass snd_hda_codec joydev snd_hda_core
> snd_hwdep pcspkr wmi_bmof snd_seq i2c_i801 i2c_smbus thinkpad_acpi
> snd_seq_device snd_pcm platform_profile snd_timer ledtrig_audio snd
> rfkill soundcore mei_me mei lpc_ich zram ip_tables i915 i2c_algo_bit
> drm_kms_helper cec e1000e
> [ 140.303171] firewire_ohci serio_raw firewire_core drm yenta_socket
> crc_itu_t wmi video fuse
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
> From: Chris Wilson
>
> Allow internal clients to create a pinned context.
>
> v2 (Daniele): export destructor as well, allow optional usage of custom
> vm for maximum flexibility.
>
> Signed-off-by: Chris Wilson
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h| 10
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++
> 2 files changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 47ee8578e511..a64d28aba257 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -18,7 +18,9 @@
> #include "intel_workarounds.h"
>
> struct drm_printer;
> +struct intel_context;
> struct intel_gt;
> +struct lock_class_key;
>
> /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is
> overkill,
> * but keeps the logic simple. Indeed, the whole purpose of this macro is
> just
> @@ -255,6 +257,14 @@ struct i915_request *
> intel_engine_find_active_request(struct intel_engine_cs *engine);
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> +struct i915_address_space *vm,
> +unsigned int ring_size,
> +unsigned int hwsp,
> +struct lock_class_key *key,
> +const char *name);
> +void intel_engine_destroy_pinned_context(struct intel_context *ce);
>
> void intel_engine_init_active(struct intel_engine_cs *engine,
> unsigned int subclass);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index eba2da9679a5..8cbf11497e8e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs
> *engine, unsigned int subclass)
> #endif
> }
>
> -static struct intel_context *
> -create_pinned_context(struct intel_engine_cs *engine,
> - unsigned int hwsp,
> - struct lock_class_key *key,
> - const char *name)
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> +struct i915_address_space *vm,
> +unsigned int ring_size,
> +unsigned int hwsp,
> +struct lock_class_key *key,
> +const char *name)
> {
> struct intel_context *ce;
> int err;
> @@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
>
> __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> ce->timeline = page_pack_bits(NULL, hwsp);
> + ce->ring = __intel_context_ring_size(ring_size);
why do we need this now and we didn't need before?
> +
> + if (vm) {
> + i915_vm_put(ce->vm);
> + ce->vm = i915_vm_get(vm);
> + }
same question here...
>
> err = intel_context_pin(ce); /* perma-pin so it is always available */
> if (err) {
> @@ -834,7 +842,7 @@ create_pinned_context(struct intel_engine_cs *engine,
> return ce;
> }
>
> -static void destroy_pinned_context(struct intel_context *ce)
> +void intel_engine_destroy_pinned_context(struct intel_context *ce)
> {
> struct intel_engine_cs *engine = ce->engine;
> struct i915_vma *hwsp = engine->status_page.vma;
> @@ -854,8 +862,9 @@ create_kernel_context(struct intel_engine_cs *engine)
> {
> static struct lock_class_key kernel;
>
> - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
> - &kernel, "kernel_context");
> + return intel_engine_create_pinned_context(engine, NULL, SZ_4K,
> + I915_GEM_HWS_SEQNO_ADDR,
> + &kernel, "kernel_context");
> }
>
> /**
> @@ -898,7 +907,7 @@ static int engine_init_common(struct intel_engine_cs
> *engine)
> return 0;
>
> err_context:
> - destroy_pinned_context(ce);
> + intel_engine_destroy_pinned_context(ce);
> return ret;
> }
>
> @@ -956,7 +965,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
> *engine)
> fput(engine->default_state);
>
> if (engine->kernel_context)
> - destroy_pinned_context(engine->kernel_context);
> + intel_engine_destroy_pinned_context(engine->kernel_context);
>
> GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
> cleanup_status_page(engine);
> --
> 2.29.2
>
_
Re: [Intel-gfx] [PATCH v4 05/17] drm/i915/pxp: allocate a vcs context for pxp usage
t;intel_pxp.h"
> +#include "gt/intel_context.h"
> +#include "i915_drv.h"
> +
> +static int create_vcs_context(struct intel_pxp *pxp)
> +{
> + static struct lock_class_key pxp_lock;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_engine_cs *engine;
> + struct intel_context *ce;
> +
> + /*
> + * Find the first VCS engine present. We're guaranteed there is one
> + * if we're in this function due to the check in has_pxp
> + */
> + for (engine = gt->engine_class[VIDEO_DECODE_CLASS][0]; !engine;
> engine++);
> + GEM_BUG_ON(!engine || engine->class != VIDEO_DECODE_CLASS);
> +
> + ce = intel_engine_create_pinned_context(engine, NULL, SZ_4K,
> + I915_GEM_HWS_PXP_ADDR,
> + &pxp_lock, "pxp_context");
> + if (IS_ERR(ce)) {
> + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
> + return PTR_ERR(ce);
> + }
> +
> + pxp->ce = ce;
> +
> + return 0;
> +}
> +
> +static void destroy_vcs_context(struct intel_pxp *pxp)
> +{
> + intel_engine_destroy_pinned_context(fetch_and_zero(&pxp->ce));
> +}
> +
> +void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + if (!HAS_PXP(gt->i915))
> + return;
> +
... and we will need to add the PXP version check here, not in IGT...
But both changes can be done in follow-up patches, once we get the extra
docs we requested. For now this patch lgtm
Reviewed-by: Rodrigo Vivi
> + ret = create_vcs_context(pxp);
> + if (ret)
> + return;
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + destroy_vcs_context(pxp);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index ..e87550fb9821
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "gt/intel_gt_types.h"
> +#include "intel_pxp_types.h"
> +
> +static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> +{
> + return container_of(pxp, struct intel_gt, pxp);
> +}
> +
> +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> +{
> + return pxp->ce;
> +}
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_fini(struct intel_pxp *pxp);
> +#else
> +static inline void intel_pxp_init(struct intel_pxp *pxp)
> +{
> +}
> +
> +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> new file mode 100644
> index ..bd12c520e60a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
7> +
> +#ifndef __INTEL_PXP_TYPES_H__
> +#define __INTEL_PXP_TYPES_H__
> +
> +struct intel_context;
> +
> +struct intel_pxp {
> + struct intel_context *ce;
> +};
> +
> +#endif /* __INTEL_PXP_TYPES_H__ */
> --
> 2.29.2
>
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Re: [Intel-gfx] [PATCH v4 06/17] drm/i915/pxp: Implement funcs to create the TEE channel
On Mon, May 24, 2021 at 10:47:52PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (default) session.
>
> v2: fix locking, don't pollute dev_priv (Chris)
>
> v3: wait for mei PXP component to be bound.
good idea. it would be useful for the case where the mei side was
checking for the version instead i915 for instance...
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Reviewed-by: Rodrigo Vivi #v2
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 13
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 87 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 3 +
> 5 files changed, 119 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index efd950122e40..0dfff52fea24 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -275,7 +275,8 @@ i915-y += i915_perf.o
>
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> - pxp/intel_pxp.o
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 3255c6da34e8..5df2a09c9e4b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -50,7 +51,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (ret)
> return;
>
> + ret = intel_pxp_tee_component_init(pxp);
> + if (ret)
> + goto out_context;
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
> +
> + return;
> +
> +out_context:
> + destroy_vcs_context(pxp);
> }
>
> void intel_pxp_fini(struct intel_pxp *pxp)
> @@ -58,5 +68,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> destroy_vcs_context(pxp);
> +
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index ..4ed234d8584f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> +{
> + return &kdev_to_i915(i915_kdev)->gt.pxp;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind function to pass the function pointers
> to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume from system
> sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> +struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = data;
> + pxp->pxp_component->tee_dev = tee_kdev;
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +
> + pxp->pxp_component = NULL;
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
>
Re: [Intel-gfx] [PATCH v4 08/17] drm/i915/pxp: Create the arbitrary session after boot
On Mon, May 24, 2021 at 10:47:54PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot,
We will have to change this and only create on-demand.
Then delete when no one is using... but this will be a follow-up.
Also let's add this patch for preserving history and credits as well.
> for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session will need to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> The session ID is exposed as part of the uapi so it can be used as part
> of userspace commands.
>
> v2: use gt->uncore->rpm (Chris)
> v3: s/arb_is_in_play/arb_is_valid (Chris), move set-up to the new
> init_hw function
> v4: move interface defs to separate header, set arb_is valid to false
> on fini (Rodrigo)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 5 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 74 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 15
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 68 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> .../drm/i915/pxp/intel_pxp_tee_interface.h| 37 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 9 +++
> include/uapi/drm/i915_drm.h | 3 +
> 10 files changed, 220 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0dfff52fea24..739510549545 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -276,6 +276,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ab19d2a23ec2..4e30e5e98522 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
> @@ -86,6 +87,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + pxp->arb_is_valid = false;
> +
> intel_pxp_tee_component_fini(pxp);
>
> destroy_vcs_context(pxp);
> @@ -94,6 +97,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> kcr_pxp_enable(pxp_to_gt(pxp));
> +
> + intel_pxp_create_arb_session(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 5427c3b28aa9..8eeb65af78b1 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -19,6 +19,11 @@ static inline bool intel_pxp_is_enabled(const struct
> intel_pxp *pxp)
> return pxp->ce;
> }
>
> +static inline bool intel_pxp_is_active(const struct intel_pxp *pxp)
> +{
> + return pxp->arb_is_valid;
> +}
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> new file mode 100644
> index ..3331868f354c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "drm/i915_drm.h"
> +#include "i915_drv.h"
> +
> +#include "i
Re: [Intel-gfx] [PATCH v4 10/17] drm/i915/pxp: Implement PXP irq handler
On Mon, May 24, 2021 at 10:47:56PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
> which point it is safe to re-create the session.
>
> Since the termination and re-creation flow is something we want to
> trigger from the driver as well, use a common work function that can be
> called both from the irq handler and from the driver set-up flows, which
> has the addded benefit of allowing us to skip any extra locks because
> the work itself serializes the operations.
>
> v2: use struct completion instead of bool (Chris)
> v3: drop locks, clean up functions and improve comments (Chris),
> move to common work function.
> v4: improve comments, simplify wait logic (Rodrigo)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 66 +++--
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 97
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 ++-
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 18
> 11 files changed, 281 insertions(+), 16 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0fba97014512..29331bbb3e98 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -277,6 +277,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> + pxp/intel_pxp_irq.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 9fc6c912a4e5..7c4ec8880b1a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp_irq.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
> instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(>->pxp, iir);
> +
> WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> instance, iir);
> }
> @@ -232,6 +236,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
> +
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
> }
>
> void gen11_gt_irq_postinstall(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4dbe79009c0e..297671d78076 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8023,6 +8023,7 @@ enum {
> /* irq instances for OTHER_CLASS */
> #define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> +#define OTHER_KCR_INSTANCE 4
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index e48debb5ca22..6b0e7170c29b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -2,7 +2,9 @@
> /*
> * Copyright(c) 2020 Intel Corporation.
> */
> +#include
> #include "intel_pxp.h"
> +#include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
Re: [Intel-gfx] [PATCH v4 10/17] drm/i915/pxp: Implement PXP irq handler
On Mon, May 24, 2021 at 10:47:56PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
> which point it is safe to re-create the session.
>
> Since the termination and re-creation flow is something we want to
> trigger from the driver as well, use a common work function that can be
> called both from the irq handler and from the driver set-up flows, which
> has the addded benefit of allowing us to skip any extra locks because
> the work itself serializes the operations.
>
> v2: use struct completion instead of bool (Chris)
> v3: drop locks, clean up functions and improve comments (Chris),
> move to common work function.
> v4: improve comments, simplify wait logic (Rodrigo)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 66 +++--
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 97
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 ++-
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 18
> 11 files changed, 281 insertions(+), 16 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0fba97014512..29331bbb3e98 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -277,6 +277,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> + pxp/intel_pxp_irq.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 9fc6c912a4e5..7c4ec8880b1a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp_irq.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
> instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(>->pxp, iir);
> +
> WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> instance, iir);
> }
> @@ -232,6 +236,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
> +
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
> }
>
> void gen11_gt_irq_postinstall(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4dbe79009c0e..297671d78076 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8023,6 +8023,7 @@ enum {
> /* irq instances for OTHER_CLASS */
> #define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> +#define OTHER_KCR_INSTANCE 4
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index e48debb5ca22..6b0e7170c29b 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -2,7 +2,9 @@
> /*
> * Copyright(c) 2020 Intel Corporation.
> */
> +#include
> #include "intel_pxp.h"
> +#include "intel_pxp_irq.h"
> #include "intel_pxp_session.h"
> #include "intel_pxp_tee.h"
Re: [Intel-gfx] [PATCH v4 13/17] drm/i915/pxp: Enable PXP power management
On Mon, May 24, 2021 at 10:47:59PM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> During the power event S3+ sleep/resume, hardware will lose all the
> encryption keys for every hardware session, even though the
> session state might still be marked as alive after resume. Therefore,
> we should consider the session as dead on suspend and invalidate all the
> objects. The session will be automatically restarted on the first
> protected submission on resume.
>
> v2: runtime suspend also invalidates the keys
> v3: fix return codes, simplify rpm ops (Chris), use the new worker func
> v4: invalidate the objects on suspend, don't re-create the arb sesson on
> resume (delayed to first submission).
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 +++-
> drivers/gpu/drm/i915/i915_drv.c | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 11 --
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 40
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 ++-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9 +
> 8 files changed, 124 insertions(+), 15 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 29331bbb3e98..9cce0bf9a50f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -278,6 +278,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_irq.o \
> + pxp/intel_pxp_pm.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index aef3084e8b16..91151a02f7a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -19,6 +19,7 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_pm.h"
>
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> @@ -265,6 +266,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> intel_uc_resume(>->uc);
>
> + intel_pxp_resume(>->pxp);
> +
> user_forcewake(gt, false);
>
> out_fw:
> @@ -299,6 +302,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> user_forcewake(gt, true);
> wait_for_suspend(gt);
>
> + intel_pxp_suspend(>->pxp);
> intel_uc_suspend(>->uc);
> }
>
> @@ -349,6 +353,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
>
> void intel_gt_runtime_suspend(struct intel_gt *gt)
> {
> + intel_pxp_suspend(>->pxp);
> intel_uc_runtime_suspend(>->uc);
>
> GT_TRACE(gt, "\n");
> @@ -356,11 +361,19 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
>
> int intel_gt_runtime_resume(struct intel_gt *gt)
> {
> + int ret;
> +
> GT_TRACE(gt, "\n");
> intel_gt_init_swizzling(gt);
> intel_ggtt_restore_fences(gt->ggtt);
>
> - return intel_uc_runtime_resume(>->uc);
> + ret = intel_uc_runtime_resume(>->uc);
> + if (ret)
> + return ret;
> +
> + intel_pxp_resume(>->pxp);
> +
> + return 0;
> }
>
> static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f06bb7b3ed2..6543e5577709 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -68,6 +68,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
>
> +#include "pxp/intel_pxp_pm.h"
> +
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> #include "i915_ioc32.h"
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> index a230d0034e50..9e5847c653f2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> @@ -9,6 +9,7 @@
> #include "gt/intel_gt_irq.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_runtime_pm.h"
>
&g
Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/pxp: start the arb session on demand
On Mon, May 24, 2021 at 10:47:58PM -0700, Daniele Ceraolo Spurio wrote:
> Now that we can handle destruction and re-creation of the arb session,
> we can postpone the start of the session to the first submission that
> requires it, to avoid keeping it running with no user.
>
> Signed-off-by: Daniele Ceraolo Spurio
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 ++--
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 37 ---
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 +--
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 3 ++
> 7 files changed, 39 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index a11e9d5767bf..c08e28847064 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2948,9 +2948,11 @@ eb_select_engine(struct i915_execbuffer *eb)
> intel_gt_pm_get(ce->engine->gt);
>
> if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> - err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> - if (err)
> - goto err;
> + if (!intel_pxp_is_active(&ce->engine->gt->pxp)) {
> + err = intel_pxp_start(&ce->engine->gt->pxp);
> + if (err)
> + goto err;
> + }
>
> if (i915_gem_context_invalidated(eb->gem_context)) {
> err = -EACCES;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index f713d3423cea..2291c68fd3a0 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -77,6 +77,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
> init_completion(&pxp->termination);
> complete_all(&pxp->termination);
>
> + mutex_init(&pxp->arb_mutex);
> INIT_WORK(&pxp->session_work, intel_pxp_session_work);
>
> ret = create_vcs_context(pxp);
> @@ -113,7 +114,7 @@ void intel_pxp_mark_termination_in_progress(struct
> intel_pxp *pxp)
> reinit_completion(&pxp->termination);
> }
>
> -static void intel_pxp_queue_termination(struct intel_pxp *pxp)
> +static void pxp_queue_termination(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = pxp_to_gt(pxp);
>
> @@ -132,31 +133,41 @@ static void intel_pxp_queue_termination(struct
> intel_pxp *pxp)
> * the arb session is restarted from the irq work when we receive the
> * termination completion interrupt
> */
> -int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> +int intel_pxp_start(struct intel_pxp *pxp)
> {
> + int ret = 0;
> +
> if (!intel_pxp_is_enabled(pxp))
> - return 0;
> + return -ENODEV;
> +
> + mutex_lock(&pxp->arb_mutex);
> +
> + if (pxp->arb_is_valid)
> + goto unlock;
> +
> + pxp_queue_termination(pxp);
>
> if (!wait_for_completion_timeout(&pxp->termination,
> - msecs_to_jiffies(100)))
> - return -ETIMEDOUT;
> + msecs_to_jiffies(100))) {
> + ret = -ETIMEDOUT;
> + goto unlock;
> + }
> +
> + /* make sure the compiler doesn't optimize the double access */
> + barrier();
>
> if (!pxp->arb_is_valid)
> - return -EIO;
> + ret = -EIO;
>
> - return 0;
> +unlock:
> + mutex_unlock(&pxp->arb_mutex);
> + return ret;
> }
>
> void intel_pxp_init_hw(struct intel_pxp *pxp)
> {
> kcr_pxp_enable(pxp_to_gt(pxp));
> intel_pxp_irq_enable(pxp);
> -
> - /*
> - * the session could've been attacked while we weren't loaded, so
> - * handle it as if it was and re-create it.
> - */
> - intel_pxp_queue_termination(pxp);
> }
>
> void intel_pxp_fini_hw(struct intel_pxp *pxp)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 91c1a2056309..1f9871e64096 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -32,7 +32,7 @@ void intel_pxp_init_hw(struct intel_pxp *pxp);
> void intel_pxp_fini_hw(struct intel_pxp *pxp);
>
> void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> -int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> +int intel_pxp_start(struct intel_pxp *pxp);
> void intel_pxp_invalidate(struct intel_pxp *pxp);
> #else
> static inline void intel_pxp_init(struct intel_pxp *pxp)
> @@ -43,7 +43,7 @@ static inline void intel_pxp_fini(struct intel_pxp *pxp)
> {
> }
>
> -static inline int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> +static inline int intel_pxp_start(struct intel
Re: [Intel-gfx] [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
On Tue, Jun 01, 2021 at 02:23:00PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 6/1/2021 1:20 PM, Rodrigo Vivi wrote:
> > On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
> > > From: Chris Wilson
> > >
> > > Allow internal clients to create a pinned context.
> > >
> > > v2 (Daniele): export destructor as well, allow optional usage of custom
> > > vm for maximum flexibility.
> > >
> > > Signed-off-by: Chris Wilson
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_engine.h| 10
> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++
> > > 2 files changed, 29 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> > > b/drivers/gpu/drm/i915/gt/intel_engine.h
> > > index 47ee8578e511..a64d28aba257 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > > @@ -18,7 +18,9 @@
> > > #include "intel_workarounds.h"
> > > struct drm_printer;
> > > +struct intel_context;
> > > struct intel_gt;
> > > +struct lock_class_key;
> > > /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is
> > > overkill,
> > >* but keeps the logic simple. Indeed, the whole purpose of this macro
> > > is just
> > > @@ -255,6 +257,14 @@ struct i915_request *
> > > intel_engine_find_active_request(struct intel_engine_cs *engine);
> > > u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
> > > +struct intel_context *
> > > +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> > > +struct i915_address_space *vm,
> > > +unsigned int ring_size,
> > > +unsigned int hwsp,
> > > +struct lock_class_key *key,
> > > +const char *name);
> > > +void intel_engine_destroy_pinned_context(struct intel_context *ce);
> > > void intel_engine_init_active(struct intel_engine_cs *engine,
> > > unsigned int subclass);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index eba2da9679a5..8cbf11497e8e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs
> > > *engine, unsigned int subclass)
> > > #endif
> > > }
> > > -static struct intel_context *
> > > -create_pinned_context(struct intel_engine_cs *engine,
> > > - unsigned int hwsp,
> > > - struct lock_class_key *key,
> > > - const char *name)
> > > +struct intel_context *
> > > +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> > > +struct i915_address_space *vm,
> > > +unsigned int ring_size,
> > > +unsigned int hwsp,
> > > +struct lock_class_key *key,
> > > +const char *name)
> > > {
> > > struct intel_context *ce;
> > > int err;
> > > @@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
> > > __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> > > ce->timeline = page_pack_bits(NULL, hwsp);
> > > + ce->ring = __intel_context_ring_size(ring_size);
> > why do we need this now and we didn't need before?
>
> Since we're now exporting the function as a more "official" interface, the
> idea was to provide as much flexibility as possible. The ring size could be
> used if e.g. we decide to use more pxp sessions and therefore need more
> space in the ring to insert instructions. Same for the vm below.
it makes sense. thanks for the explanation.
Reviewed-by: Rodrigo Vivi
>
> Daniele
>
> >
> > > +
> > > + if (vm) {
> > > + i915_vm_put(ce->vm);
> > > + ce->vm = i915_vm_get(vm);
> > > + }
> > same question here...
> >
> > > err = intel_context_pin(ce); /* perma-pin so it is
Re: [Intel-gfx] [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support
On Mon, May 24, 2021 at 10:48:01PM -0700, Daniele Ceraolo Spurio wrote:
> From: Anshuman Gupta
>
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PXP session is enabled.
> 2. Buffer object is protected.
>
> v2:
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> v3:
> - intel_pxp_gem_object_status() API changes.
>
> v4: use intel_pxp_is_active (Daniele)
>
> v5: rebase and use the new protected object status checker (Daniele)
>
> v6: used plane state for plane_decryption to handle async flip
> as suggested by Ville.
>
> v7: check pxp session while plane decrypt state computation. [Ville]
> removed pointless code. [Ville]
>
> v8 (Daniele): update PXP check
>
> Cc: Bommu Krishnaiah
> Cc: Huang Sean Z
> Cc: Gaurav Kumar
> Cc: Ville Syrjälä
> Signed-off-by: Anshuman Gupta
> Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Rodrigo Vivi
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c| 16
> drivers/gpu/drm/i915/display/intel_display.c | 4
> .../gpu/drm/i915/display/intel_display_types.h | 3 +++
> .../gpu/drm/i915/display/skl_universal_plane.c | 15 ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 5 files changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 36f52a1d7552..88b3272c0b00 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -41,6 +41,7 @@
> #include "intel_display_types.h"
> #include "intel_pm.h"
> #include "intel_sprite.h"
> +#include "pxp/intel_pxp.h"
>
> static void intel_plane_state_reset(struct intel_plane_state *plane_state,
> struct intel_plane *plane)
> @@ -383,6 +384,14 @@ intel_crtc_get_plane(struct intel_crtc *crtc, enum
> plane_id plane_id)
> return NULL;
> }
>
> +static int bo_has_valid_encryption(const struct drm_i915_gem_object *obj)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> +
> + return i915_gem_object_has_valid_protection(obj) &&
> +intel_pxp_is_active(&i915->gt.pxp);
> +}
> +
> int intel_plane_atomic_check(struct intel_atomic_state *state,
>struct intel_plane *plane)
> {
> @@ -397,6 +406,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_framebuffer *fb;
>
> if (new_crtc_state && new_crtc_state->bigjoiner_slave) {
> struct intel_plane *master_plane =
> @@ -413,6 +423,12 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> new_master_plane_state,
> crtc);
>
> + fb = new_plane_state->hw.fb;
> + if (fb)
> + new_plane_state->decrypt =
> bo_has_valid_encryption(intel_fb_obj(fb));
> + else
> + new_plane_state->decrypt = old_plane_state->decrypt;
> +
> new_plane_state->uapi.visible = false;
> if (!new_crtc_state)
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0bb2e582c87f..f7f5374114ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9767,6 +9767,10 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
> drm_dbg_kms(&i915->drm, "Color range cannot be changed
> in async flip\n");
> return -EINVAL;
> }
> +
> + /* plane decryption is allow to change only in synchronous
> flips */
> + if (old_plane_state->decrypt != new_plane_state->decrypt)
> + return -EINVAL;
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ce05475ad560..6b5dab9e1c40 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -621,6 +621,9 @@ struct intel_plane_state {
>
Re: [Intel-gfx] [PATCH v4 16/17] drm/i915/pxp: black pixels on pxp disabled
static void
> skl_program_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -1088,14 +1115,21 @@ skl_program_plane(struct intel_plane *plane,
>*/
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> + plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> plane_id));
>
> /*
>* FIXME: pxp session invalidation can hit any time even at time of
> commit
>* or after the commit, display content will be garbage.
>*/
> - if (plane_state->decrypt)
> + if (plane_state->decrypt) {
> plane_surf |= PLANE_SURF_DECRYPT;
> + } else if (plane_state->force_black) {
> + intel_load_plane_csc_black(plane);
> + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> + }
>
> + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> + plane_color_ctl);
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b3eaf45ae3ab..3ad6577b7fa4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7161,6 +7161,7 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /*
> ICL+ */
> #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> #define PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23) /* Pre-ICL */
> #define PLANE_COLOR_CSC_MODE_BYPASS(0 << 17)
> @@ -11276,6 +11277,51 @@ enum skl_power_gate {
> _PAL_PREC_MULTI_SEG_DATA_A, \
> _PAL_PREC_MULTI_SEG_DATA_B)
>
> +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
> +
> +/* Plane CSC Registers */
> +#define _PLANE_CSC_RY_GY_1_A 0x70210
registers could have followed spec and be simply PLANCE_CSC_1_A ...
and also "HI" removed from the ones below.
But anyway, they are right and the patch looks right.
I wish we had some kind of solution for the async flips as well,
but, this is already very good:
Reviewed-by: Rodrigo Vivi
> +#define _PLANE_CSC_RY_GY_2_A 0x70310
> +
> +#define _PLANE_CSC_RY_GY_1_B 0x71210
> +#define _PLANE_CSC_RY_GY_2_B 0x71310
> +
> +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
> + _PLANE_CSC_RY_GY_1_B)
> +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A,
> \
> + _PLANE_INPUT_CSC_RY_GY_2_B)
> +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
> +
> _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
> +
> _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
> +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
> +
> +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
> +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
> +
> +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
> + _PLANE_CSC_PREOFF_HI_1_B)
> +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
> + _PLANE_CSC_PREOFF_HI_2_B)
> +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
> _PLANE_CSC_PREOFF_HI_1(pipe) + \
> + (index) * 4,
> _PLANE_CSC_PREOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_A0x70234
> +#define _PLANE_CSC_POSTOFF_HI_2_A0x70334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1_B0x71234
> +#define _PLANE_CSC_POSTOFF_HI_2_B0x71334
> +
> +#define _PLANE_CSC_POSTOFF_HI_1(pipe)_PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_1_A, \
> + _PLANE_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_CSC_POSTOFF_HI_2(pipe)_PIPE(pipe,
> _PLANE_CSC_POSTOFF_HI_2_A, \
> + _PLANE_CSC_POSTOFF_HI_2_B)
> +#define PLANE_CSC_POSTOFF(pipe, plane, index)_MMIO_PLANE(plane,
> _PLANE_CSC_POSTOFF_HI_1(pipe) + \
> + (index) * 4,
> _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> + (index) * 4)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> --
> 2.29.2
>
___
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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH v4 02/17] mei: pxp: export pavp client to me client bus
uct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !buffer)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + byte = mei_cldev_recv(cldev, buffer, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return byte;
> +}
> +
> +static const struct i915_pxp_component_ops mei_pxp_ops = {
> + .owner = THIS_MODULE,
> + .send = mei_pxp_send_message,
> + .recv = mei_pxp_receive_message,
> +};
> +
> +static int mei_component_master_bind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> + int ret;
> +
> + dev_dbg(dev, "%s\n", __func__);
> + comp_master->ops = &mei_pxp_ops;
> + comp_master->tee_dev = dev;
> + ret = component_bind_all(dev, comp_master);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void mei_component_master_unbind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> +
> + dev_dbg(dev, "%s\n", __func__);
> + component_unbind_all(dev, comp_master);
> +}
> +
> +static const struct component_master_ops mei_component_master_ops = {
> + .bind = mei_component_master_bind,
> + .unbind = mei_component_master_unbind,
> +};
> +
> +/**
> + * mei_pxp_component_match - compare function for matching mei pxp.
> + *
> + *The function checks if the driver is i915, the subcomponent is PXP
> + *and the grand parent of pxp and the parent of i915 are the same
> + *PCH device.
> + *
> + * @dev: master device
> + * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
> + * @data: compare data (mei pxp device)
> + *
> + * Return:
> + * * 1 - if components match
> + * * 0 - otherwise
> + */
> +static int mei_pxp_component_match(struct device *dev, int subcomponent,
> +void *data)
> +{
> + struct device *base = data;
> +
> + if (subcomponent != I915_COMPONENT_PXP)
> + return 0;
> +
> + if (strcmp(dev->driver->name, "i915") == 0) {
> + base = base->parent;
> + if (!base)
> + return 0;
> +
> + base = base->parent;
> + dev = dev->parent;
> + return (base && dev && dev == base);
> + }
> +
> + return 0;
> +}
> +
> +static int mei_pxp_probe(struct mei_cl_device *cldev,
> + const struct mei_cl_device_id *id)
> +{
> + struct i915_pxp_component *comp_master;
> + struct component_match *master_match;
> + int ret;
> +
> + ret = mei_cldev_enable(cldev);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
> + goto enable_err_exit;
> + }
> +
> + comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
> + if (!comp_master) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> +
> + master_match = NULL;
> + component_match_add_typed(&cldev->dev, &master_match,
> + mei_pxp_component_match, &cldev->dev);
> + if (IS_ERR_OR_NULL(master_match)) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> +
> + mei_cldev_set_drvdata(cldev, comp_master);
> + ret = component_master_add_with_match(&cldev->dev,
> + &mei_component_master_ops,
> + master_match);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
> + goto err_exit;
> + }
> +
> + return 0;
> +
> +err_exit:
> + mei_cldev_set_drvdata(cldev, NULL);
> + kfree(comp_master);
> + mei_cldev_disable(cldev);
> +enable_err_exit:
> + return ret;
> +}
> +
> +static void mei_pxp_remove(struct mei_cl_device *cldev)
> +{
> + struct i915_pxp_component *comp_master = mei_cldev_get_drvdata(cldev);
> + int ret;
> +
> + component_master_del(&cldev->dev, &mei_component_master_ops);
> + kfree(comp_master);
> + mei_cldev_set_drvdata(cldev, NULL);
> +
> + ret = mei_cldev_disable(cldev);
> + if (ret)
> + dev_warn(&cldev
Re: [Intel-gfx] [PATCH v2] drm/i915: Initialize the mbus_offset to fix static analysis issue
On Thu, Jun 03, 2021 at 03:07:54PM -0700, Manasi Navare wrote:
> Static analysis identified an issue in skl_crtc_allocate_ddb where
> mbus_offset may be used uninitialized.
> This patch fixes it.
I'm sorry, but I really cannot see what this tool is seeing...
I even tried to look to our internal branch to see if it was an issue
there.
But I'm failing to see how it is possible...
>
> Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets")
> Cc: Ville Syrjälä
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 00f3dead20ad..a385b8b7414f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4163,7 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> struct intel_crtc_state *crtc_state;
> struct skl_ddb_entry ddb_slices;
> enum pipe pipe = crtc->pipe;
> - unsigned int mbus_offset;
> + unsigned int mbus_offset = 0;
> u32 ddb_range_size;
> u32 dbuf_slice_mask;
> u32 start, end;
> --
> 2.19.1
>
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Re: [Intel-gfx] [PATCH v2] drm/i915: Initialize the mbus_offset to fix static analysis issue
On Fri, Jun 04, 2021 at 06:22:49PM +0300, Mika Kuoppala wrote:
> Rodrigo Vivi writes:
>
> > On Thu, Jun 03, 2021 at 03:07:54PM -0700, Manasi Navare wrote:
> >> Static analysis identified an issue in skl_crtc_allocate_ddb where
> >> mbus_offset may be used uninitialized.
> >> This patch fixes it.
> >
> > I'm sorry, but I really cannot see what this tool is seeing...
> > I even tried to look to our internal branch to see if it was an issue
> > there.
> > But I'm failing to see how it is possible...
>
> It is in the goto out; path.
indeed... thanks
what a huge "out" block.
For me it looks like another function and not just an "out".
Could we get a refactor here?
I'm afraid that setting mbus_offset = 0 silence the static analysis tool,
but this might not be right for this "out" section. Because offset gets
totally ignored.
The condition to call the goto out is not that clear on why we want
one or another path, so a refactor there to make things more clear is
probably the best.
> -Mika
>
> >
> >>
> >> Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets")
> >> Cc: Ville Syrjälä
> >> Signed-off-by: Manasi Navare
> >> ---
> >> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> >> b/drivers/gpu/drm/i915/intel_pm.c
> >> index 00f3dead20ad..a385b8b7414f 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -4163,7 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state
> >> *state, struct intel_crtc *crtc)
> >>struct intel_crtc_state *crtc_state;
> >>struct skl_ddb_entry ddb_slices;
> >>enum pipe pipe = crtc->pipe;
> >> - unsigned int mbus_offset;
> >> + unsigned int mbus_offset = 0;
> >>u32 ddb_range_size;
> >>u32 dbuf_slice_mask;
> >>u32 start, end;
> >> --
> >> 2.19.1
> >>
> >> ___
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> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > ___
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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Stop hand rolling drm_crtc_mask()
On Wed, Jun 09, 2021 at 11:56:27AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use drm_crtc_mask() instead of hand rolling it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 362bff9beb5c..62ad4cfae073 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6485,7 +6485,7 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> struct drm_atomic_state *state = NULL, *restore_state = NULL;
> struct drm_connector_state *connector_state;
> struct intel_crtc_state *crtc_state;
> - int ret, i = -1;
> + int ret;
>
> drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
> connector->base.id, connector->name,
> @@ -6519,8 +6519,7 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
>
> /* Find an unused one (if possible) */
> for_each_crtc(dev, possible_crtc) {
> - i++;
> - if (!(encoder->possible_crtcs & (1 << i)))
> + if (!(encoder->possible_crtcs & drm_crtc_mask(possible_crtc)))
> continue;
>
> ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Clean up intel_get_load_detect_pipe() a bit
On Wed, Jun 09, 2021 at 11:56:28AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Sort out the mess with the local variables in
> intel_get_load_detect_pipe(). Get rid of all aliasing pointers
> and use standard naming/types.
>
> Signed-off-by: Ville Syrjälä
nice clean up
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 41 +---
> 1 file changed, 19 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 62ad4cfae073..78815a1ac0ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6473,13 +6473,11 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> struct intel_load_detect_pipe *old,
> struct drm_modeset_acquire_ctx *ctx)
> {
> - struct intel_crtc *intel_crtc;
> - struct intel_encoder *intel_encoder =
> + struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> - struct drm_crtc *possible_crtc;
> - struct drm_encoder *encoder = &intel_encoder->base;
> - struct drm_crtc *crtc = NULL;
> - struct drm_device *dev = encoder->dev;
> + struct intel_crtc *possible_crtc;
> + struct intel_crtc *crtc = NULL;
> + struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_mode_config *config = &dev->mode_config;
> struct drm_atomic_state *state = NULL, *restore_state = NULL;
> @@ -6489,7 +6487,7 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
>
> drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
> connector->base.id, connector->name,
> - encoder->base.id, encoder->name);
> + encoder->base.base.id, encoder->base.name);
>
> old->restore_state = NULL;
>
> @@ -6507,9 +6505,9 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
>
> /* See if we already have a CRTC for this connector */
> if (connector->state->crtc) {
> - crtc = connector->state->crtc;
> + crtc = to_intel_crtc(connector->state->crtc);
>
> - ret = drm_modeset_lock(&crtc->mutex, ctx);
> + ret = drm_modeset_lock(&crtc->base.mutex, ctx);
> if (ret)
> goto fail;
>
> @@ -6518,16 +6516,17 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> }
>
> /* Find an unused one (if possible) */
> - for_each_crtc(dev, possible_crtc) {
> - if (!(encoder->possible_crtcs & drm_crtc_mask(possible_crtc)))
> + for_each_intel_crtc(dev, possible_crtc) {
> + if (!(encoder->base.possible_crtcs &
> + drm_crtc_mask(&possible_crtc->base)))
> continue;
>
> - ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
> + ret = drm_modeset_lock(&possible_crtc->base.mutex, ctx);
> if (ret)
> goto fail;
>
> - if (possible_crtc->state->enable) {
> - drm_modeset_unlock(&possible_crtc->mutex);
> + if (possible_crtc->base.state->enable) {
> + drm_modeset_unlock(&possible_crtc->base.mutex);
> continue;
> }
>
> @@ -6546,8 +6545,6 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> }
>
> found:
> - intel_crtc = to_intel_crtc(crtc);
> -
> state = drm_atomic_state_alloc(dev);
> restore_state = drm_atomic_state_alloc(dev);
> if (!state || !restore_state) {
> @@ -6564,11 +6561,11 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> goto fail;
> }
>
> - ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
> + ret = drm_atomic_set_crtc_for_connector(connector_state, &crtc->base);
> if (ret)
> goto fail;
>
> - crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
> + crtc_state = intel_atomic_get_crtc_state(state, crtc);
> if (IS_ERR(crtc_state)) {
> ret = PTR_ERR(crtc_state);
> goto fail;
> @@ -6581,15 +6578,15 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> if (ret)
>
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Clean up intel_find_initial_plane_obj() a bit
On Wed, Jun 09, 2021 at 11:56:29AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Sort out the mess with the local variables in
> intel_find_initial_plane_obj(). Get rid of all aliasing pointers
> and use standard naming/types.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 113 ++-
> 1 file changed, 62 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 78815a1ac0ca..1615501685c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1914,20 +1914,50 @@ static void intel_dpt_unpin(struct i915_address_space
> *vm)
> i915_vma_put(dpt->vma);
> }
>
> +static bool
> +intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
> + const struct intel_initial_plane_config
> *plane_config,
> + struct drm_framebuffer **fb,
> + struct i915_vma **vma)
> +{
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&i915->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane =
> + to_intel_plane(crtc->base.primary);
> + struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> +
> + if (!crtc_state->uapi.active)
> + continue;
> +
> + if (!plane_state->ggtt_vma)
> + continue;
> +
> + if (intel_plane_ggtt_offset(plane_state) == plane_config->base)
> {
> + *fb = plane_state->hw.fb;
> + *vma = plane_state->ggtt_vma;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> static void
> -intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> +intel_find_initial_plane_obj(struct intel_crtc *crtc,
>struct intel_initial_plane_config *plane_config)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> + struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_crtc *c;
> - struct drm_plane *primary = intel_crtc->base.primary;
> - struct drm_plane_state *plane_state = primary->state;
> - struct intel_plane *intel_plane = to_intel_plane(primary);
> - struct intel_plane_state *intel_state =
> - to_intel_plane_state(plane_state);
> struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(intel_crtc->base.state);
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane =
> + to_intel_plane(crtc->base.primary);
> + struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> struct drm_framebuffer *fb;
> struct i915_vma *vma;
>
> @@ -1939,7 +1969,7 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
> if (!plane_config->fb)
> return;
>
> - if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
> + if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
> fb = &plane_config->fb->base;
> vma = plane_config->vma;
> goto valid_fb;
> @@ -1949,25 +1979,8 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
>* Failed to alloc the obj, check to see if we should share
>* an fb with another CRTC instead
>*/
> - for_each_crtc(dev, c) {
> - struct intel_plane_state *state;
> -
> - if (c == &intel_crtc->base)
> - continue;
> -
> - if (!to_intel_crtc_state(c->state)->uapi.active)
> - continue;
> -
> - state = to_intel_plane_state(c->primary->state);
> - if (!state->ggtt_vma)
> - continue;
> -
> - if (intel_plane_ggtt_offset(state) == plane_config->base) {
> - fb = state->hw.fb;
> - vma = state->ggtt_vma;
> - goto valid_fb;
> - }
> - }
> + if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
> + goto valid_fb;
>
> /*
>* We've failed to reconstruct the BIOS FB. Current display state
> @@ -1976,7 +1989,7 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
>* simplest solution is to just disable the primary plane now and
>* pretend the BIOS never had it enabled.
>*/
> - intel_plane_disable_noatomic(intel_crtc, intel_plane);
> + intel_plane_disable_noatomic(crtc, plane);
> if (crtc_state->bigjoiner) {
> struct intel_crtc *slave =
> crtc_state->bigj
Re: [Intel-gfx] [PATCH 4/6] drm/i915: Clean up pre-skl wm calling convention
e *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct g4x_wm_state *intermediate =
> &new_crtc_state->wm.g4x.intermediate;
> const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
> - struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->uapi.state);
> - const struct intel_crtc_state *old_crtc_state =
> - intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
> enum plane_id plane_id;
>
> - if (!new_crtc_state->hw.active ||
> drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> + if (!new_crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -1890,12 +1891,12 @@ static bool vlv_raw_crtc_wm_is_valid(const struct
> intel_crtc_state *crtc_state,
> vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
> }
>
> -static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> +static int vlv_compute_pipe_wm(struct intel_atomic_state *state,
> +struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state =
> - to_intel_atomic_state(crtc_state->uapi.state);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
> const struct vlv_fifo_state *fifo_state =
> &crtc_state->wm.vlv.fifo_state;
> @@ -2095,19 +2096,20 @@ static void vlv_atomic_update_fifo(struct
> intel_atomic_state *state,
>
> #undef VLV_FIFO
>
> -static int vlv_compute_intermediate_wm(struct intel_crtc_state
> *new_crtc_state)
> +static int vlv_compute_intermediate_wm(struct intel_atomic_state *state,
> +struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> struct vlv_wm_state *intermediate =
> &new_crtc_state->wm.vlv.intermediate;
> const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
> - struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(new_crtc_state->uapi.state);
> - const struct intel_crtc_state *old_crtc_state =
> - intel_atomic_get_old_crtc_state(intel_state, crtc);
> const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
> int level;
>
> - if (!new_crtc_state->hw.active ||
> drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> + if (!new_crtc_state->hw.active ||
> + drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
> *intermediate = *optimal;
>
> intermediate->cxsr = false;
> @@ -3144,10 +3146,12 @@ static bool ilk_validate_pipe_wm(const struct
> drm_i915_private *dev_priv,
> }
>
> /* Compute new watermarks for the pipe */
> -static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> +static int ilk_compute_pipe_wm(struct intel_atomic_state *state,
> +struct intel_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
I didn't see much advantage on changing 1 to 2 arguments when you need the
previous one anyway.
But maybe I'm missing some other patch like the possible clean-up
mentioned at the commit message above...
anyway the code looks correct and no blocker here, so up to you:
Reviewed-by: Rodrigo Vivi
> struct intel_pipe_wm *pipe_wm;
> struct intel_plane *plane;
> const struct intel_plane_state *plane_state;
> @@
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Clean up intel_fbdev_init_bios() a bit
On Wed, Jun 09, 2021 at 11:56:31AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Sort out the mess with the local variables in
> intel_fbdev_init_bios(). Get rid of all aliasing pointers,
> use standard naming/types, and introduc a few more locals
^ typo
> in the loops to avoid the hard to read long struct walks.
>
> While at we also polish the debugs a bit to use the
> canonical [CRTC:%d:%s] style.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_fbdev.c | 94 +-
> 1 file changed, 56 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
> b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 4af40229f5ec..df05d285f0bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -335,32 +335,43 @@ static void intel_fbdev_destroy(struct intel_fbdev
> *ifbdev)
> * fbcon), so we just find the biggest and use that.
> */
> static bool intel_fbdev_init_bios(struct drm_device *dev,
> - struct intel_fbdev *ifbdev)
> + struct intel_fbdev *ifbdev)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> struct intel_framebuffer *fb = NULL;
> - struct drm_crtc *crtc;
> - struct intel_crtc *intel_crtc;
> + struct intel_crtc *crtc;
> unsigned int max_size = 0;
>
> /* Find the largest fb */
> - for_each_crtc(dev, crtc) {
> + for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane =
> + to_intel_plane(crtc->base.primary);
> + struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> struct drm_i915_gem_object *obj =
> - intel_fb_obj(crtc->primary->state->fb);
> - intel_crtc = to_intel_crtc(crtc);
> + intel_fb_obj(plane_state->uapi.fb);
oh, here we have again that plane_state uapi change that I don't understand
and I'm not seeing any mention in any commit msg..
>
> - if (!crtc->state->active || !obj) {
> + if (!crtc_state->uapi.active) {
> drm_dbg_kms(&i915->drm,
> - "pipe %c not active or no fb, skipping\n",
> - pipe_name(intel_crtc->pipe));
> + "[CRTC:%d:%s] not active, skipping\n",
> + crtc->base.base.id, crtc->base.name);
> + continue;
> + }
> +
> + if (!obj) {
> + drm_dbg_kms(&i915->drm,
> + "[PLANE:%d:%s] no fb, skipping\n",
> + plane->base.base.id, plane->base.name);
> continue;
> }
>
> if (obj->base.size > max_size) {
> drm_dbg_kms(&i915->drm,
> - "found possible fb from plane %c\n",
> - pipe_name(intel_crtc->pipe));
> - fb = to_intel_framebuffer(crtc->primary->state->fb);
> + "found possible fb from [PLANE:%d:%s]\n",
> + plane->base.base.id, plane->base.name);
> + fb = to_intel_framebuffer(plane_state->uapi.fb);
> max_size = obj->base.size;
> }
> }
> @@ -372,60 +383,62 @@ static bool intel_fbdev_init_bios(struct drm_device
> *dev,
> }
>
> /* Now make sure all the pipes will fit into it */
> - for_each_crtc(dev, crtc) {
> + for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane =
> + to_intel_plane(crtc->base.primary);
> unsigned int cur_size;
>
> - intel_crtc = to_intel_crtc(crtc);
> -
> - if (!crtc->state->active) {
> + if (!crtc_state->uapi.active) {
> drm_dbg_kms(&i915->drm,
> - "pipe %c not active, skipping\n",
> - pipe_name(intel_crtc->pipe));
> + "[CRTC:%d:%s] not active, skipping\n",
> + crtc->base.base.id, crtc->base.name);
> continue;
> }
>
> - drm_dbg_kms(&i915->drm, "checking plane %c for BIOS fb\n",
> - pipe_name(intel_crtc->pipe));
> + drm_dbg_kms(&i915->drm, "checking [PLANE:%d:%s] for BIOS fb\n",
> + plane->base.base.id, plane->base.name);
>
> /*
Re: [Intel-gfx] [PATCH 6/6] drm/i915: s/intel_crtc/crtc/
On Wed, Jun 09, 2021 at 11:56:32AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Clear out the straggler 'intel_crtc' variables.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
> drivers/gpu/drm/i915/display/intel_crtc.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +--
> drivers/gpu/drm/i915/display/intel_display.c | 6 +--
> .../drm/i915/display/intel_display_debugfs.c | 28 ++---
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 20 -
> drivers/gpu/drm/i915/display/intel_hdmi.c | 42 +--
> drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 4 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 13 +++---
> drivers/gpu/drm/i915/display/skl_scaler.c | 27 ++--
> drivers/gpu/drm/i915/display/vlv_dsi.c| 13 +++---
> drivers/gpu/drm/i915/i915_irq.c | 22 +-
> 15 files changed, 100 insertions(+), 105 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 16812488c5dd..55ceae6a8de5 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -729,8 +729,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> - enum pipe pipe = intel_crtc->pipe;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + enum pipe pipe = crtc->pipe;
> u32 tmp;
> enum port port;
> enum transcoder dsi_trans;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 95ff1707b4bd..448c4d99ac35 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -163,12 +163,12 @@ static void intel_crtc_free(struct intel_crtc *crtc)
> kfree(crtc);
> }
>
> -static void intel_crtc_destroy(struct drm_crtc *crtc)
> +static void intel_crtc_destroy(struct drm_crtc *_crtc)
> {
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_crtc *crtc = to_intel_crtc(_crtc);
>
> - drm_crtc_cleanup(crtc);
> - kfree(intel_crtc);
> + drm_crtc_cleanup(&crtc->base);
> + kfree(crtc);
> }
>
> static int intel_crtc_late_register(struct drm_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 390869bd6b63..313fd86c827b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3577,7 +3577,7 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> u32 temp, flags = 0;
> @@ -3640,7 +3640,7 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
> pipe_config->lane_count =
> ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT)
> + 1;
> - intel_dp_get_m_n(intel_crtc, pipe_config);
> + intel_dp_get_m_n(crtc, pipe_config);
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder,
> pipe_config);
> @@ -3670,7 +3670,7 @@ static void intel_ddi_read_func_ctl(struct
> intel_encoder *encoder,
> pipe_config->mst_master_transcoder =
>
> REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
>
> - intel_dp_get_m_n(intel_crtc, pipe_config);
> + intel_dp_get_m_n(crtc, pipe_config);
>
> pipe_config->infoframes.enable |=
> intel_hdmi_infoframes_enabled(encoder, pipe_config);
> diff --git a/dr
Re: [Intel-gfx] [PATCH 3/6] drm/i915: Clean up intel_find_initial_plane_obj() a bit
On Wed, Jun 09, 2021 at 03:15:54PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 09, 2021 at 07:36:01AM -0400, Rodrigo Vivi wrote:
> > On Wed, Jun 09, 2021 at 11:56:29AM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Sort out the mess with the local variables in
> > > intel_find_initial_plane_obj(). Get rid of all aliasing pointers
> > > and use standard naming/types.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 113 ++-
> > > 1 file changed, 62 insertions(+), 51 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 78815a1ac0ca..1615501685c9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1914,20 +1914,50 @@ static void intel_dpt_unpin(struct
> > > i915_address_space *vm)
> > > i915_vma_put(dpt->vma);
> > > }
> > >
> > > +static bool
> > > +intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
> > > + const struct intel_initial_plane_config
> > > *plane_config,
> > > + struct drm_framebuffer **fb,
> > > + struct i915_vma **vma)
> > > +{
> > > + struct intel_crtc *crtc;
> > > +
> > > + for_each_intel_crtc(&i915->drm, crtc) {
> > > + struct intel_crtc_state *crtc_state =
> > > + to_intel_crtc_state(crtc->base.state);
> > > + struct intel_plane *plane =
> > > + to_intel_plane(crtc->base.primary);
> > > + struct intel_plane_state *plane_state =
> > > + to_intel_plane_state(plane->base.state);
> > > +
> > > + if (!crtc_state->uapi.active)
> > > + continue;
> > > +
> > > + if (!plane_state->ggtt_vma)
> > > + continue;
> > > +
> > > + if (intel_plane_ggtt_offset(plane_state) == plane_config->base)
> > > {
> > > + *fb = plane_state->hw.fb;
> > > + *vma = plane_state->ggtt_vma;
> > > + return true;
> > > + }
> > > + }
> > > +
> > > + return false;
> > > +}
> > > +
> > > static void
> > > -intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > +intel_find_initial_plane_obj(struct intel_crtc *crtc,
> > >struct intel_initial_plane_config *plane_config)
> > > {
> > > - struct drm_device *dev = intel_crtc->base.dev;
> > > + struct drm_device *dev = crtc->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > - struct drm_crtc *c;
> > > - struct drm_plane *primary = intel_crtc->base.primary;
> > > - struct drm_plane_state *plane_state = primary->state;
> > > - struct intel_plane *intel_plane = to_intel_plane(primary);
> > > - struct intel_plane_state *intel_state =
> > > - to_intel_plane_state(plane_state);
> > > struct intel_crtc_state *crtc_state =
> > > - to_intel_crtc_state(intel_crtc->base.state);
> > > + to_intel_crtc_state(crtc->base.state);
> > > + struct intel_plane *plane =
> > > + to_intel_plane(crtc->base.primary);
> > > + struct intel_plane_state *plane_state =
> > > + to_intel_plane_state(plane->base.state);
> > > struct drm_framebuffer *fb;
> > > struct i915_vma *vma;
> > >
> > > @@ -1939,7 +1969,7 @@ intel_find_initial_plane_obj(struct intel_crtc
> > > *intel_crtc,
> > > if (!plane_config->fb)
> > > return;
> > >
> > > - if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
> > > + if (intel_alloc_initial_plane_obj(crtc, plane_config)) {
> > > fb = &plane_config->fb->base;
> > > vma = plane_config->vma;
> > > goto valid_fb;
> > > @@ -1949,25 +1979,8 @@ intel_find_initial_plane_obj(struct intel_crtc
> > > *intel_crtc,
> > >* Failed to alloc the obj, check to see if we should share
> > >* an fb with another CRTC instead
> > >*/
> > > - for_each_crtc(dev, c) {
> > > - st
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Clean up intel_fbdev_init_bios() a bit
On Wed, Jun 09, 2021 at 07:46:28AM -0400, Rodrigo Vivi wrote:
> On Wed, Jun 09, 2021 at 11:56:31AM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Sort out the mess with the local variables in
> > intel_fbdev_init_bios(). Get rid of all aliasing pointers,
> > use standard naming/types, and introduc a few more locals
>
> ^ typo
>
> > in the loops to avoid the hard to read long struct walks.
> >
> > While at we also polish the debugs a bit to use the
> > canonical [CRTC:%d:%s] style.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_fbdev.c | 94 +-
> > 1 file changed, 56 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
> > b/drivers/gpu/drm/i915/display/intel_fbdev.c
> > index 4af40229f5ec..df05d285f0bd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> > @@ -335,32 +335,43 @@ static void intel_fbdev_destroy(struct intel_fbdev
> > *ifbdev)
> > * fbcon), so we just find the biggest and use that.
> > */
> > static bool intel_fbdev_init_bios(struct drm_device *dev,
> > -struct intel_fbdev *ifbdev)
> > + struct intel_fbdev *ifbdev)
> > {
> > struct drm_i915_private *i915 = to_i915(dev);
> > struct intel_framebuffer *fb = NULL;
> > - struct drm_crtc *crtc;
> > - struct intel_crtc *intel_crtc;
> > + struct intel_crtc *crtc;
> > unsigned int max_size = 0;
> >
> > /* Find the largest fb */
> > - for_each_crtc(dev, crtc) {
> > + for_each_intel_crtc(dev, crtc) {
> > + struct intel_crtc_state *crtc_state =
> > + to_intel_crtc_state(crtc->base.state);
> > + struct intel_plane *plane =
> > + to_intel_plane(crtc->base.primary);
> > + struct intel_plane_state *plane_state =
> > + to_intel_plane_state(plane->base.state);
> > struct drm_i915_gem_object *obj =
> > - intel_fb_obj(crtc->primary->state->fb);
> > - intel_crtc = to_intel_crtc(crtc);
> > + intel_fb_obj(plane_state->uapi.fb);
>
> oh, here we have again that plane_state uapi change that I don't understand
> and I'm not seeing any mention in any commit msg..
sorry...
Reviewed-by: Rodrigo Vivi
>
> >
> > - if (!crtc->state->active || !obj) {
> > + if (!crtc_state->uapi.active) {
> > drm_dbg_kms(&i915->drm,
> > - "pipe %c not active or no fb, skipping\n",
> > - pipe_name(intel_crtc->pipe));
> > + "[CRTC:%d:%s] not active, skipping\n",
> > + crtc->base.base.id, crtc->base.name);
> > + continue;
> > + }
> > +
> > + if (!obj) {
> > + drm_dbg_kms(&i915->drm,
> > + "[PLANE:%d:%s] no fb, skipping\n",
> > + plane->base.base.id, plane->base.name);
> > continue;
> > }
> >
> > if (obj->base.size > max_size) {
> > drm_dbg_kms(&i915->drm,
> > - "found possible fb from plane %c\n",
> > - pipe_name(intel_crtc->pipe));
> > - fb = to_intel_framebuffer(crtc->primary->state->fb);
> > + "found possible fb from [PLANE:%d:%s]\n",
> > + plane->base.base.id, plane->base.name);
> > + fb = to_intel_framebuffer(plane_state->uapi.fb);
> > max_size = obj->base.size;
> > }
> > }
> > @@ -372,60 +383,62 @@ static bool intel_fbdev_init_bios(struct drm_device
> > *dev,
> > }
> >
> > /* Now make sure all the pipes will fit into it */
> > - for_each_crtc(dev, crtc) {
> > + for_each_intel_crtc(dev, crtc) {
> > + struct intel_crtc_state *crtc_state =
> > + to_intel_crtc_state(crtc->base.state);
> > + struct intel_plane *plane =
> > + to_intel_plane(crtc-&
[Intel-gfx] [PULL] drm-intel-next
ace IS_GEN and friends with GRAPHICS_VER
drm/i915: Add remaining conversions to GRAPHICS_VER
Manasi Navare (2):
drm/i915/xelpd: Add VRR guardband for VRR CTL
drm/i915: Initialize the mbus_offset to fix Klockwork issue
Matt Roper (2):
drm/i915/adl_p: Add dedicated SAGV watermarks
drm/i915/xelpd: Enhanced pipe underrun reporting
Mika Kahola (2):
drm/i915/adl_p: Tx escape clock with DSI
drm/i915/adl_p: Define and use ADL-P specific DP translation tables
Rodrigo Vivi (1):
Merge drm/drm-next into drm-intel-next
Shaokun Zhang (1):
drm/i915: Remove the repeated declaration
Stanislav Lisovskiy (2):
drm/i915/adl_p: CDCLK crawl support for ADL
drm/i915/adl_p: Same slices mask is not same Dbuf state
Tejas Upadhyay (1):
x86/gpu: add JasperLake to gen11 early quirks
Vandita Kulkarni (5):
drm/i915/xelpd: Calculate VDSC RC parameters
drm/i915/xelpd: Add rc_qp_table for rcparams calculation
drm/i915/adl_p: Add ddb allocation support
drm/i915/adl_p: MBUS programming
drm/i915/dsc: Fix bigjoiner check in dsc_disable
Ville Syrjälä (10):
drm/i915: Introduce MBUS relative dbuf offsets
drm/i915: Extract intel_hdmi_bpc_possible()
drm/i915: Move has_hdmi_sink check into intel_hdmi_bpc_possible()
drm/i915: Move platform checks into intel_hdmi_bpc_possible()
drm/i915: Check sink deep color capabilitis during HDMI .mode_valid()
drm/i915: Move the TMDS clock division into intel_hdmi_mode_clock_valid()
drm/i915: Drop redundant has_hdmi_sink check
drm/i915/adl_p: Disable FIFO underrun recovery
drm/i915/adl_p: Implement Wa_22012358565
drm/i915: Disable PSR around cdclk changes
Wan Jiabing (1):
drm/i915/display: remove duplicated argument
Documentation/gpu/i915.rst | 12 +-
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 21 +-
drivers/gpu/drm/i915/display/intel_atomic.c| 20 ++
drivers/gpu/drm/i915/display/intel_atomic.h| 1 +
drivers/gpu/drm/i915/display/intel_bw.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 85 -
drivers/gpu/drm/i915/display/intel_csr.h | 21 --
drivers/gpu/drm/i915/display/intel_cursor.c| 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 53 ++-
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 53 +++
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 4 +
drivers/gpu/drm/i915/display/intel_display.c | 143 +++-
.../gpu/drm/i915/display/intel_display_debugfs.c | 30 +-
drivers/gpu/drm/i915/display/intel_display_power.c | 139
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/{intel_csr.c => intel_dmc.c} | 386 +++--
drivers/gpu/drm/i915/display/intel_dmc.h | 43 +++
.../gpu/drm/i915/display/intel_dp_link_training.c | 71 ++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++-
drivers/gpu/drm/i915/display/intel_fb.c| 13 +-
drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 57 ++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 104 +++---
drivers/gpu/drm/i915/display/intel_psr.c | 187 +++---
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
drivers/gpu/drm/i915/display/intel_qp_tables.c | 309 +
drivers/gpu/drm/i915/display/intel_qp_tables.h | 14 +
drivers/gpu/drm/i915/display/intel_tc.c| 152 +++-
drivers/gpu/drm/i915/display/intel_tc.h| 2 +
drivers/gpu/drm/i915/display/intel_tv.c| 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 117 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 58 +++-
drivers/gpu/drm/i915/display/skl_universal_plane.c | 27 ++
drivers/gpu/drm/i915/gt/intel_gtt.h| 3 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 8 +-
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 10 +-
drivers/gpu/drm/i915/gvt/gtt.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c| 14 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c| 10 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/gvt/vgpu.c| 4 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 10 +-
drivers/gpu/drm/i915/i915_debugfs.c| 47 ++-
drivers/gpu/drm/i915/i915_drv.c| 28 +-
drivers/gpu/drm/i915/i915_drv.h| 64 ++--
drivers/gpu/drm/i915/i915_gem.c| 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 92 ++---
drivers/gpu/drm/i915/i915_irq.c
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Thu, Jun 10, 2021 at 12:39:55PM +0200, Zbigniew Kempczyński wrote:
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Rocketlake and Alderlake under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
hmm... to be really honest I'm not so happy that we are introducing
a new criteria to the force_probe.
The criteria was to have a functional driver and not to track uapi.
But on the other hand I do recognize that the current definition
of the flag allows that, because we have established that with
this behavior, the "driver for new Intel graphics devices that
are recognized but not properly supported by this kernel version"
(as stated in the Kconfig for the DRM_I915_FORCE_PROBE).
However...
>
> v2: - remove inline from function definition (Jani)
> - fix indentation
>
> v3: change to GRAPHICS_VER() (Zbigniew)
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Acked-by: Dave Airlie
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24 +++
> 1 file changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index a8abc9af5ff4..30c4f0549ea0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,30 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> + * Relocations are disallowed starting from gen12 with Tigerlake
> + * as an exception. We allow temporarily use relocations for Rocketlake
> + * and Alderlake when require_force_probe flag is set.
> + */
> + if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> + return true;
> +
> + if (INTEL_INFO(eb->i915)->require_force_probe &&
> + (IS_ROCKETLAKE(eb->i915)
This ship has sailed... RKL is not protected by this flag any longer.
Should this be on the TGL side now?
> || IS_ALDERLAKE_S(eb->i915) ||
> + IS_ALDERLAKE_P(eb->i915)))
How to ensure that we will easily catch this when removing the
flag?
I mean, should we have a GEM_BUG or drm_err message when these
platforms in this list has not the required_force_probe?
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> - * also covers all platforms with local memory.
> - */
> - if (entry->relocation_count &&
> - GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
> --
> 2.26.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH v4 12/17] drm/i915/pxp: start the arb session on demand
On Thu, Jun 10, 2021 at 03:44:37PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 6/2/2021 11:14 AM, Rodrigo Vivi wrote:
> > On Mon, May 24, 2021 at 10:47:58PM -0700, Daniele Ceraolo Spurio wrote:
> > > Now that we can handle destruction and re-creation of the arb session,
> > > we can postpone the start of the session to the first submission that
> > > requires it, to avoid keeping it running with no user.
> > >
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > ---
> > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 ++--
> > > drivers/gpu/drm/i915/pxp/intel_pxp.c | 37 ---
> > > drivers/gpu/drm/i915/pxp/intel_pxp.h | 4 +-
> > > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 2 +-
> > > drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 +--
> > > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 10 +
> > > drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 3 ++
> > > 7 files changed, 39 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > index a11e9d5767bf..c08e28847064 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > @@ -2948,9 +2948,11 @@ eb_select_engine(struct i915_execbuffer *eb)
> > > intel_gt_pm_get(ce->engine->gt);
> > > if (i915_gem_context_uses_protected_content(eb->gem_context)) {
> > > - err = intel_pxp_wait_for_arb_start(&ce->engine->gt->pxp);
> > > - if (err)
> > > - goto err;
> > > + if (!intel_pxp_is_active(&ce->engine->gt->pxp)) {
> > > + err = intel_pxp_start(&ce->engine->gt->pxp);
> > > + if (err)
> > > + goto err;
> > > + }
> > > if (i915_gem_context_invalidated(eb->gem_context)) {
> > > err = -EACCES;
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > index f713d3423cea..2291c68fd3a0 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > > @@ -77,6 +77,7 @@ void intel_pxp_init(struct intel_pxp *pxp)
> > > init_completion(&pxp->termination);
> > > complete_all(&pxp->termination);
> > > + mutex_init(&pxp->arb_mutex);
> > > INIT_WORK(&pxp->session_work, intel_pxp_session_work);
> > > ret = create_vcs_context(pxp);
> > > @@ -113,7 +114,7 @@ void intel_pxp_mark_termination_in_progress(struct
> > > intel_pxp *pxp)
> > > reinit_completion(&pxp->termination);
> > > }
> > > -static void intel_pxp_queue_termination(struct intel_pxp *pxp)
> > > +static void pxp_queue_termination(struct intel_pxp *pxp)
> > > {
> > > struct intel_gt *gt = pxp_to_gt(pxp);
> > > @@ -132,31 +133,41 @@ static void intel_pxp_queue_termination(struct
> > > intel_pxp *pxp)
> > >* the arb session is restarted from the irq work when we receive the
> > >* termination completion interrupt
> > >*/
> > > -int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp)
> > > +int intel_pxp_start(struct intel_pxp *pxp)
> > > {
> > > + int ret = 0;
> > > +
> > > if (!intel_pxp_is_enabled(pxp))
> > > - return 0;
> > > + return -ENODEV;
> > > +
> > > + mutex_lock(&pxp->arb_mutex);
> > > +
> > > + if (pxp->arb_is_valid)
> > > + goto unlock;
> > > +
> > > + pxp_queue_termination(pxp);
> > > if (!wait_for_completion_timeout(&pxp->termination,
> > > - msecs_to_jiffies(100)))
> > > - return -ETIMEDOUT;
> > > + msecs_to_jiffies(100))) {
> > > + ret = -ETIMEDOUT;
> > > + goto unlock;
> > > + }
> > > +
> > > + /* make sure the compiler doesn't optimize the double access */
> > > + barrier();
> > > if (!pxp->arb_is_valid)
> > > - return -EIO;
> > > + ret = -EIO;
> > > - return 0;
> > > +unlock:
&
Re: [Intel-gfx] [PATCH v4 13/17] drm/i915/pxp: Enable PXP power management
On Thu, Jun 10, 2021 at 03:58:13PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 6/2/2021 9:20 AM, Rodrigo Vivi wrote:
> > On Mon, May 24, 2021 at 10:47:59PM -0700, Daniele Ceraolo Spurio wrote:
> > > From: "Huang, Sean Z"
> > >
> > > During the power event S3+ sleep/resume, hardware will lose all the
> > > encryption keys for every hardware session, even though the
> > > session state might still be marked as alive after resume. Therefore,
> > > we should consider the session as dead on suspend and invalidate all the
> > > objects. The session will be automatically restarted on the first
> > > protected submission on resume.
> > >
> > > v2: runtime suspend also invalidates the keys
> > > v3: fix return codes, simplify rpm ops (Chris), use the new worker func
> > > v4: invalidate the objects on suspend, don't re-create the arb sesson on
> > > resume (delayed to first submission).
> > >
> > > Signed-off-by: Huang, Sean Z
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > Cc: Chris Wilson
> > > Cc: Rodrigo Vivi
> > > ---
> > > drivers/gpu/drm/i915/Makefile| 1 +
> > > drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 +++-
> > > drivers/gpu/drm/i915/i915_drv.c | 2 +
> > > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 11 --
> > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 40
> > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 +++
> > > drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 ++-
> > > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9 +
> > > 8 files changed, 124 insertions(+), 15 deletions(-)
> > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> > >
> > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > > index 29331bbb3e98..9cce0bf9a50f 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -278,6 +278,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> > > pxp/intel_pxp.o \
> > > pxp/intel_pxp_cmd.o \
> > > pxp/intel_pxp_irq.o \
> > > + pxp/intel_pxp_pm.o \
> > > pxp/intel_pxp_session.o \
> > > pxp/intel_pxp_tee.o
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > index aef3084e8b16..91151a02f7a2 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > @@ -19,6 +19,7 @@
> > > #include "intel_rc6.h"
> > > #include "intel_rps.h"
> > > #include "intel_wakeref.h"
> > > +#include "pxp/intel_pxp_pm.h"
> > > static void user_forcewake(struct intel_gt *gt, bool suspend)
> > > {
> > > @@ -265,6 +266,8 @@ int intel_gt_resume(struct intel_gt *gt)
> > > intel_uc_resume(>->uc);
> > > + intel_pxp_resume(>->pxp);
> > > +
> > > user_forcewake(gt, false);
> > > out_fw:
> > > @@ -299,6 +302,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> > > user_forcewake(gt, true);
> > > wait_for_suspend(gt);
> > > + intel_pxp_suspend(>->pxp);
> > > intel_uc_suspend(>->uc);
> > > }
> > > @@ -349,6 +353,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
> > > void intel_gt_runtime_suspend(struct intel_gt *gt)
> > > {
> > > + intel_pxp_suspend(>->pxp);
> > > intel_uc_runtime_suspend(>->uc);
> > > GT_TRACE(gt, "\n");
> > > @@ -356,11 +361,19 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
> > > int intel_gt_runtime_resume(struct intel_gt *gt)
> > > {
> > > + int ret;
> > > +
> > > GT_TRACE(gt, "\n");
> > > intel_gt_init_swizzling(gt);
> > > intel_ggtt_restore_fences(gt->ggtt);
> > > - return intel_uc_runtime_resume(>->uc);
> > > + ret = intel_uc_runtime_resume(>->uc);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + intel_pxp_resume(>->pxp);
> > > +
> > > + return 0;
> > > }
> > > static ktime_t __intel_gt_get_awak
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Fri, Jun 11, 2021 at 08:09:00AM +0200, Zbigniew Kempczyński wrote:
> On Thu, Jun 10, 2021 at 10:36:12AM -0400, Rodrigo Vivi wrote:
> > On Thu, Jun 10, 2021 at 12:39:55PM +0200, Zbigniew Kempczyński wrote:
> > > We have established previously we stop using relocations starting
> > > from gen12 platforms with Tigerlake as an exception. We keep this
> > > statement but we want to enable relocations conditionally for
> > > Rocketlake and Alderlake under require_force_probe flag set.
> > >
> > > Keeping relocations under require_force_probe flag is interim solution
> > > until IGTs will be rewritten to use softpin.
> >
> > hmm... to be really honest I'm not so happy that we are introducing
> > a new criteria to the force_probe.
> >
> > The criteria was to have a functional driver and not to track uapi.
> >
> > But on the other hand I do recognize that the current definition
> > of the flag allows that, because we have established that with
> > this behavior, the "driver for new Intel graphics devices that
> > are recognized but not properly supported by this kernel version"
> > (as stated in the Kconfig for the DRM_I915_FORCE_PROBE).
> >
> > However...
> >
> > >
> > > v2: - remove inline from function definition (Jani)
> > > - fix indentation
> > >
> > > v3: change to GRAPHICS_VER() (Zbigniew)
> > >
> > > Signed-off-by: Zbigniew Kempczyński
> > > Cc: Dave Airlie
> > > Cc: Daniel Vetter
> > > Cc: Jason Ekstrand
> > > Acked-by: Dave Airlie
> > > ---
> > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24 +++
> > > 1 file changed, 19 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > index a8abc9af5ff4..30c4f0549ea0 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > @@ -491,16 +491,30 @@ eb_unreserve_vma(struct eb_vma *ev)
> > > ev->flags &= ~__EXEC_OBJECT_RESERVED;
> > > }
> > >
> > > +static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> > > +{
> > > + /*
> > > + * Relocations are disallowed starting from gen12 with Tigerlake
> > > + * as an exception. We allow temporarily use relocations for Rocketlake
> > > + * and Alderlake when require_force_probe flag is set.
> > > + */
> > > + if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> > > + return true;
> > > +
> > > + if (INTEL_INFO(eb->i915)->require_force_probe &&
> > > + (IS_ROCKETLAKE(eb->i915)
> >
> > This ship has sailed... RKL is not protected by this flag any longer.
> > Should this be on the TGL side now?
>
> +Lucas
>
> I think no, RKL has relocations disabled so we cannot put it to TGL side.
> So if RKL is already released then putting it under require_force_probe
> flag is wrong and only I can do is to remove it from that condition.
> There's no option to unblock RKL on IGT CI until we rewrite all the tests.
> We have to rely then on ADL* with require_force_probe flag to check how
> ADL will work with relocations.
So... I'm confused now. I'm missing the point of this patch then.
I thought the reason was to protect from any user space to attempt to
use the relocation, unless using the force_probe temporarily only for
these platforms.
But if I'm understanding correctly now it is only to silence CI?!
Is that the case?
Is the CI noise so bad?
>
> >
> > > || IS_ALDERLAKE_S(eb->i915) ||
> > > + IS_ALDERLAKE_P(eb->i915)))
> >
> > How to ensure that we will easily catch this when removing the
> > flag?
> >
> > I mean, should we have a GEM_BUG or drm_err message when these
> > platforms in this list has not the required_force_probe?
>
> I don't think we need GEM_BUG()/drm_err() - when IGT tests will support
> both - reloc + no-reloc - then condition will be limited to:
>
> if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> return true;
>
> return false;
>
> so require_force_probe condition will be deleted and we won't need it
> anymore (IGTs will be ready).
yes...
but then, when we remove the flag we will forget to come here and remove
this check.
Oh, and I just thought that we might need drm_error wh
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Mon, Jun 14, 2021 at 10:35:30AM +0200, Zbigniew Kempczyński wrote:
> On Fri, Jun 11, 2021 at 04:54:32AM -0400, Rodrigo Vivi wrote:
> > On Fri, Jun 11, 2021 at 08:09:00AM +0200, Zbigniew Kempczyński wrote:
> > > On Thu, Jun 10, 2021 at 10:36:12AM -0400, Rodrigo Vivi wrote:
> > > > On Thu, Jun 10, 2021 at 12:39:55PM +0200, Zbigniew Kempczyński wrote:
> > > > > We have established previously we stop using relocations starting
> > > > > from gen12 platforms with Tigerlake as an exception. We keep this
> > > > > statement but we want to enable relocations conditionally for
> > > > > Rocketlake and Alderlake under require_force_probe flag set.
> > > > >
> > > > > Keeping relocations under require_force_probe flag is interim solution
> > > > > until IGTs will be rewritten to use softpin.
> > > >
> > > > hmm... to be really honest I'm not so happy that we are introducing
> > > > a new criteria to the force_probe.
> > > >
> > > > The criteria was to have a functional driver and not to track uapi.
> > > >
> > > > But on the other hand I do recognize that the current definition
> > > > of the flag allows that, because we have established that with
> > > > this behavior, the "driver for new Intel graphics devices that
> > > > are recognized but not properly supported by this kernel version"
> > > > (as stated in the Kconfig for the DRM_I915_FORCE_PROBE).
> > > >
> > > > However...
> > > >
> > > > >
> > > > > v2: - remove inline from function definition (Jani)
> > > > > - fix indentation
> > > > >
> > > > > v3: change to GRAPHICS_VER() (Zbigniew)
> > > > >
> > > > > Signed-off-by: Zbigniew Kempczyński
> > > > > Cc: Dave Airlie
> > > > > Cc: Daniel Vetter
> > > > > Cc: Jason Ekstrand
> > > > > Acked-by: Dave Airlie
> > > > > ---
> > > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 24
> > > > > +++
> > > > > 1 file changed, 19 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > index a8abc9af5ff4..30c4f0549ea0 100644
> > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> > > > > @@ -491,16 +491,30 @@ eb_unreserve_vma(struct eb_vma *ev)
> > > > > ev->flags &= ~__EXEC_OBJECT_RESERVED;
> > > > > }
> > > > >
> > > > > +static bool platform_has_relocs_enabled(const struct i915_execbuffer
> > > > > *eb)
> > > > > +{
> > > > > + /*
> > > > > + * Relocations are disallowed starting from gen12 with Tigerlake
> > > > > + * as an exception. We allow temporarily use relocations for
> > > > > Rocketlake
> > > > > + * and Alderlake when require_force_probe flag is set.
> > > > > + */
> > > > > + if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915))
> > > > > + return true;
> > > > > +
> > > > > + if (INTEL_INFO(eb->i915)->require_force_probe &&
> > > > > + (IS_ROCKETLAKE(eb->i915)
> > > >
> > > > This ship has sailed... RKL is not protected by this flag any longer.
> > > > Should this be on the TGL side now?
> > >
> > > +Lucas
> > >
> > > I think no, RKL has relocations disabled so we cannot put it to TGL side.
> > > So if RKL is already released then putting it under require_force_probe
> > > flag is wrong and only I can do is to remove it from that condition.
> > > There's no option to unblock RKL on IGT CI until we rewrite all the tests.
> > > We have to rely then on ADL* with require_force_probe flag to check how
> > > ADL will work with relocations.
> >
> > So... I'm confused now. I'm missing the point of this patch then.
> > I thought the reason was to protect from any user space to attempt to
> > use the relocation, unless using the force_probe temporarily only for
> > these platforms.
> > Bu
Re: [Intel-gfx] [PATCH 1/3] drm/i915: extract steered reg access to common function
On Mon, Jun 14, 2021 at 08:34:31PM -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> New steering cases will be added in the follow-up patches, so prepare a
> common helper to avoid code duplication.
>
> Cc: Tvrtko Ursulin
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 41 +
> drivers/gpu/drm/i915/intel_uncore.c | 55 +++
> drivers/gpu/drm/i915/intel_uncore.h | 6 +++
> 3 files changed, 63 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 9ceddfbb1687..8b913c6961c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1105,45 +1105,8 @@ static u32
> read_subslice_reg(const struct intel_engine_cs *engine,
> int slice, int subslice, i915_reg_t reg)
> {
> - struct drm_i915_private *i915 = engine->i915;
> - struct intel_uncore *uncore = engine->uncore;
> - u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> - enum forcewake_domains fw_domains;
> -
> - if (GRAPHICS_VER(i915) >= 11) {
> - mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> - mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> - } else {
> - mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
> - mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> - }
> -
> - fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
> - FW_REG_READ);
> - fw_domains |= intel_uncore_forcewake_for_reg(uncore,
> - GEN8_MCR_SELECTOR,
> - FW_REG_READ |
> FW_REG_WRITE);
> -
> - spin_lock_irq(&uncore->lock);
> - intel_uncore_forcewake_get__locked(uncore, fw_domains);
> -
> - old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
> -
> - mcr &= ~mcr_mask;
> - mcr |= mcr_ss;
> - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> -
> - val = intel_uncore_read_fw(uncore, reg);
> -
> - mcr &= ~mcr_mask;
> - mcr |= old_mcr & mcr_mask;
> -
> - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> -
> - intel_uncore_forcewake_put__locked(uncore, fw_domains);
> - spin_unlock_irq(&uncore->lock);
> -
> - return val;
> + return intel_uncore_read_with_mcr_steering(engine->uncore, reg,
> +slice, subslice);
> }
>
> /* NB: please notice the memset */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 1bed8f666048..d067524f9162 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2277,6 +2277,61 @@ intel_uncore_forcewake_for_reg(struct intel_uncore
> *uncore,
> return fw_domains;
> }
>
> +u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore,
> +i915_reg_t reg,
> +int slice, int subslice)
> +{
> + u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> +
> + lockdep_assert_held(&uncore->lock);
> +
> + if (GRAPHICS_VER(uncore->i915) >= 11) {
> + mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> + mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> + } else {
> + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
> + mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> + }
> +
> + old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
> +
> + mcr &= ~mcr_mask;
> + mcr |= mcr_ss;
> + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> +
> + val = intel_uncore_read_fw(uncore, reg);
> +
> + mcr &= ~mcr_mask;
> + mcr |= old_mcr & mcr_mask;
> +
> + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> +
> + return val;
> +}
> +
> +u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore,
> + i915_reg_t reg, int slice, int subslice)
> +{
> + enum forcewake_domains fw_domains;
> + u32 val;
> +
> + fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
> + FW_REG_READ);
> + fw_domains |= intel_uncore_forcew
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote:
> Although most of our multicast registers are replicated per-subslice, we
> also have a small number of multicast registers that are replicated
> per-l3 bank instead. For both types of multicast registers we need to
> make sure we steer reads of these registers to a valid instance.
> Ideally we'd like to find a specific instance ID that would steer reads
> of either type of multicast register to a valid instance (i.e., not
> fused off and not powered down), but sometimes the combination of
> part-specific fusing and the additional restrictions imposed by Render
> Power Gating make it impossible to find any overlap between the set of
> valid subslices and valid l3 banks. This problem will become even more
> noticeable on our upcoming platforms since they will be adding
> additional types of multicast registers with new types of replication
> and rules for finding valid instances for reads.
>
> To handle this we'll continue to pick a suitable subslice instance at
> driver startup and program this as the default (sliceid,subsliceid)
> setting in the steering control register (0xFDC). In cases where we
> need to read another type of multicast GT register, but the default
> subslice steering would not correspond to a valid instance, we'll
> explicitly re-steer the single read to a valid value, perform the read,
> and then reset the steering to it's "subslice" default.
>
> This patch adds the general functionality to prepare for this explicit
> steering of other multicast register types. We'll plug L3 bank steering
> into this in the next patch, and then add additional types of multicast
> registers when the support for our next upcoming platform arrives.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ---
> .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> 5 files changed, 131 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..f2bea1c20d56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
> intel_engines_free(gt);
> }
>
> +/**
> + * intel_gt_reg_needs_read_steering - determine whether a register read
> + * requires explicit steering
> + * @gt: GT structure
> + * @reg: the register to check steering requirements for
> + * @type: type of multicast steering to check
> + *
> + * Determines whether @reg needs explicit steering of a specific type for
> + * reads.
> + *
> + * Returns false if @reg does not belong to a register range of the given
> + * steering type, or if the default (subslice-based) steering IDs are
> suitable
> + * for @type steering too.
> + */
> +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> + i915_reg_t reg,
> + enum intel_steering_type type)
> +{
> + const u32 offset = i915_mmio_reg_offset(reg);
> + const struct intel_mmio_range *entry;
> +
> + if (likely(!intel_gt_needs_read_steering(gt, type)))
> + return false;
> +
> + for (entry = gt->steering_table[type]; entry->start < 0xFF;
> entry++) {
I'm not comfortable with this stop condition...
we should know the right amount of entries that we have.
Even if that means having another intermediate struct.
> + if (offset >= entry->start && offset <= entry->end)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +/**
> + * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
> steering
> + * @gt: GT structure
> + * @type: multicast register type
> + * @sliceid: Slice ID returned
> + * @subsliceid: Subslice ID returned
> + *
> + * Determines sliceid and subsliceid values that will steer reads
> + * of a specific multicast register class to a valid value.
> + */
> +static void intel_gt_get_valid_steering(struct intel_gt *gt,
> + enum intel_steering_type type,
> + u8 *sliceid, u8 *subsliceid)
> +{
> + switch (type) {
> + default:
> + MISSING_CASE(type);
I understand that we are preparing the infra for the upcoming cases,
but adding a missing_case warn by default doesn't look the right way...
did CI not complain?!
> + *sliceid = 0;
> + *subsliceid = 0;
> + }
> +}
> +
> +/**
> + * intel_gt_read_register_fw - reads a GT register with support for multicast
> + * @gt: GT structure
> + * @reg: register to read
> + *
> + * This function will read a GT register. If the register is a multicast
> + * register, th
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote:
> On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote:
> > Although most of our multicast registers are replicated per-subslice, we
> > also have a small number of multicast registers that are replicated
> > per-l3 bank instead. For both types of multicast registers we need to
> > make sure we steer reads of these registers to a valid instance.
> > Ideally we'd like to find a specific instance ID that would steer reads
> > of either type of multicast register to a valid instance (i.e., not
> > fused off and not powered down), but sometimes the combination of
> > part-specific fusing and the additional restrictions imposed by Render
> > Power Gating make it impossible to find any overlap between the set of
> > valid subslices and valid l3 banks. This problem will become even more
> > noticeable on our upcoming platforms since they will be adding
> > additional types of multicast registers with new types of replication
> > and rules for finding valid instances for reads.
> >
> > To handle this we'll continue to pick a suitable subslice instance at
> > driver startup and program this as the default (sliceid,subsliceid)
> > setting in the steering control register (0xFDC). In cases where we
> > need to read another type of multicast GT register, but the default
> > subslice steering would not correspond to a valid instance, we'll
> > explicitly re-steer the single read to a valid value, perform the read,
> > and then reset the steering to it's "subslice" default.
> >
> > This patch adds the general functionality to prepare for this explicit
> > steering of other multicast register types. We'll plug L3 bank steering
> > into this in the next patch, and then add additional types of multicast
> > registers when the support for our next upcoming platform arrives.
> >
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> > drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ---
> > .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> > 5 files changed, 131 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 2161bf01ef8b..f2bea1c20d56 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
> > intel_engines_free(gt);
> > }
> >
> > +/**
> > + * intel_gt_reg_needs_read_steering - determine whether a register read
> > + * requires explicit steering
> > + * @gt: GT structure
> > + * @reg: the register to check steering requirements for
> > + * @type: type of multicast steering to check
> > + *
> > + * Determines whether @reg needs explicit steering of a specific type for
> > + * reads.
> > + *
> > + * Returns false if @reg does not belong to a register range of the given
> > + * steering type, or if the default (subslice-based) steering IDs are
> > suitable
> > + * for @type steering too.
> > + */
> > +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> > +i915_reg_t reg,
> > +enum intel_steering_type type)
> > +{
> > + const u32 offset = i915_mmio_reg_offset(reg);
> > + const struct intel_mmio_range *entry;
> > +
> > + if (likely(!intel_gt_needs_read_steering(gt, type)))
> > + return false;
> > +
> > + for (entry = gt->steering_table[type]; entry->start < 0xFF;
> > entry++) {
>
> I'm not comfortable with this stop condition...
> we should know the right amount of entries that we have.
> Even if that means having another intermediate struct.
>
> > + if (offset >= entry->start && offset <= entry->end)
> > + return true;
> > + }
> > +
> > + return false;
> > +}
> > +
> > +/**
> > + * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
> > steering
> > + * @gt: GT structure
> > + * @type: multicast register type
> > + * @sliceid: Slice ID returned
> > + * @subsliceid: Subslice ID returned
> > + *
> > + * Determines sliceid and subsliceid values that will steer reads
&g
Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Tue, Jun 15, 2021 at 08:30:23AM -0700, Matt Roper wrote:
> On Tue, Jun 15, 2021 at 05:11:04AM -0400, Rodrigo Vivi wrote:
> > On Tue, Jun 15, 2021 at 05:08:20AM -0400, Rodrigo Vivi wrote:
> > > On Mon, Jun 14, 2021 at 08:34:32PM -0700, Matt Roper wrote:
> > > > Although most of our multicast registers are replicated per-subslice, we
> > > > also have a small number of multicast registers that are replicated
> > > > per-l3 bank instead. For both types of multicast registers we need to
> > > > make sure we steer reads of these registers to a valid instance.
> > > > Ideally we'd like to find a specific instance ID that would steer reads
> > > > of either type of multicast register to a valid instance (i.e., not
> > > > fused off and not powered down), but sometimes the combination of
> > > > part-specific fusing and the additional restrictions imposed by Render
> > > > Power Gating make it impossible to find any overlap between the set of
> > > > valid subslices and valid l3 banks. This problem will become even more
> > > > noticeable on our upcoming platforms since they will be adding
> > > > additional types of multicast registers with new types of replication
> > > > and rules for finding valid instances for reads.
> > > >
> > > > To handle this we'll continue to pick a suitable subslice instance at
> > > > driver startup and program this as the default (sliceid,subsliceid)
> > > > setting in the steering control register (0xFDC). In cases where we
> > > > need to read another type of multicast GT register, but the default
> > > > subslice steering would not correspond to a valid instance, we'll
> > > > explicitly re-steer the single read to a valid value, perform the read,
> > > > and then reset the steering to it's "subslice" default.
> > > >
> > > > This patch adds the general functionality to prepare for this explicit
> > > > steering of other multicast register types. We'll plug L3 bank steering
> > > > into this in the next patch, and then add additional types of multicast
> > > > registers when the support for our next upcoming platform arrives.
> > > >
> > > > Signed-off-by: Matt Roper
> > > > ---
> > > > drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> > > > drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> > > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 ---
> > > > .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> > > > 5 files changed, 131 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > index 2161bf01ef8b..f2bea1c20d56 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt
> > > > *gt)
> > > > intel_engines_free(gt);
> > > > }
> > > >
> > > > +/**
> > > > + * intel_gt_reg_needs_read_steering - determine whether a register read
> > > > + * requires explicit steering
> > > > + * @gt: GT structure
> > > > + * @reg: the register to check steering requirements for
> > > > + * @type: type of multicast steering to check
> > > > + *
> > > > + * Determines whether @reg needs explicit steering of a specific type
> > > > for
> > > > + * reads.
> > > > + *
> > > > + * Returns false if @reg does not belong to a register range of the
> > > > given
> > > > + * steering type, or if the default (subslice-based) steering IDs are
> > > > suitable
> > > > + * for @type steering too.
> > > > + */
> > > > +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> > > > +i915_reg_t reg,
> > > > +enum intel_steering_type
> > > > type)
> > > > +{
> > > > + const u32 offset = i915_mmio_reg_offset(reg);
> > > > + const struct intel_mmio_range *entry;
> > > > +
> > > > + if (likely(!intel_gt_needs_read_steering(gt, type)))
&g
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Wed, Jun 16, 2021 at 11:48:02AM +0200, Zbigniew Kempczyński wrote:
> For topic/intel-for-CI branch only.
>
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Alderlake S+P under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
>
> v2: - remove inline from function definition (Jani)
> - fix indentation
>
> v3: change to GRAPHICS_VER() (Zbigniew)
>
> v4: remove RKL from flag as it is already shipped (Rodrigo)
>
> v5: prepare patch to be used within topic/intel-for-CI branch only
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Cc: Rodrigo Vivi
> Acked-by: Dave Airlie
> Acked-by: Rodrigo Vivi
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 ++-
> 1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 760c8aefea3a..906ee0116443 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,27 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> + * Relocations are disallowed starting from gen12 with Tigerlake
> + * as an exception. We allow temporarily use relocations for Alderlake
> + * when require_force_probe flag is set.
To whoever end up applying this patch, please fix the comment here while
pushing to topic/core-for-CI.
+ /*
+* Relocations are disallowed starting from gen12 with Tigerlake
+* as an exception. To unblock CI, we are temporarily allowing it
+* for Rocketlake and Alderlake
+*/
> + */
> + if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915) ||
> + IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
> + IS_ALDERLAKE_P(eb->i915))
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> - * also covers all platforms with local memory.
> - */
> - if (entry->relocation_count &&
> - GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
> --
> 2.26.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2.1 2/3] drm/i915: Add GT support for multiple types of multicast steering
On Tue, Jun 15, 2021 at 05:42:12PM -0700, Matt Roper wrote:
> Although most of our multicast registers are replicated per-subslice, we
> also have a small number of multicast registers that are replicated
> per-l3 bank instead. For both types of multicast registers we need to
> make sure we steer reads of these registers to a valid instance.
> Ideally we'd like to find a specific instance ID that would steer reads
> of either type of multicast register to a valid instance (i.e., not
> fused off and not powered down), but sometimes the combination of
> part-specific fusing and the additional restrictions imposed by Render
> Power Gating make it impossible to find any overlap between the set of
> valid subslices and valid l3 banks. This problem will become even more
> noticeable on our upcoming platforms since they will be adding
> additional types of multicast registers with new types of replication
> and rules for finding valid instances for reads.
>
> To handle this we'll continue to pick a suitable subslice instance at
> driver startup and program this as the default (sliceid,subsliceid)
> setting in the steering control register (0xFDC). In cases where we
> need to read another type of multicast GT register, but the default
> subslice steering would not correspond to a valid instance, we'll
> explicitly re-steer the single read to a valid value, perform the read,
> and then reset the steering to it's "subslice" default.
>
> This patch adds the general functionality to prepare for this explicit
> steering of other multicast register types. We'll plug L3 bank steering
> into this in the next patch, and then add additional types of multicast
> registers when the support for our next upcoming platform arrives.
>
> v2:
> - Use entry->end==0 as table terminator. (Rodrigo)
> - Grab forcewake in wa_list_verify() now that we're using accessors
>that assume forcewake is already held.
>
> Cc: Rodrigo Vivi
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 84 +++
> drivers/gpu/drm/i915/gt/intel_gt.h| 8 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ++---
> .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> 5 files changed, 142 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..66299105da66 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -697,6 +697,90 @@ void intel_gt_driver_late_release(struct intel_gt *gt)
> intel_engines_free(gt);
> }
>
> +/**
> + * intel_gt_reg_needs_read_steering - determine whether a register read
> + * requires explicit steering
> + * @gt: GT structure
> + * @reg: the register to check steering requirements for
> + * @type: type of multicast steering to check
> + *
> + * Determines whether @reg needs explicit steering of a specific type for
> + * reads.
> + *
> + * Returns false if @reg does not belong to a register range of the given
> + * steering type, or if the default (subslice-based) steering IDs are
> suitable
> + * for @type steering too.
> + */
> +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt,
> + i915_reg_t reg,
> + enum intel_steering_type type)
> +{
> + const u32 offset = i915_mmio_reg_offset(reg);
> + const struct intel_mmio_range *entry;
> +
> + if (likely(!intel_gt_needs_read_steering(gt, type)))
> + return false;
> +
> + for (entry = gt->steering_table[type]; !entry->end; entry++) {
shouldn't it be:
for (entry = gt->steering_table[type]; entry->end; entry++) {
?!
or maybe this is just the proof that the 0x terminator
is less confusing?! :)
with this fixed:
Reviewed-by: Rodrigo Vivi
> + if (offset >= entry->start && offset <= entry->end)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +/**
> + * intel_gt_get_valid_steering - determines valid IDs for a class of MCR
> steering
> + * @gt: GT structure
> + * @type: multicast register type
> + * @sliceid: Slice ID returned
> + * @subsliceid: Subslice ID returned
> + *
> + * Determines sliceid and subsliceid values that will steer reads
> + * of a specific multicast register class to a valid value.
> + */
> +static void intel_gt_get_valid_steering(struct intel_gt *gt,
> + enum intel_steering_type type,
> +
Re: [Intel-gfx] [PATCH v2.1 3/3] drm/i915: Add support for explicit L3BANK steering
On Tue, Jun 15, 2021 at 05:42:13PM -0700, Matt Roper wrote:
> Because Render Power Gating restricts us to just a single subslice as a
> valid steering target for reads of multicast registers in a SUBSLICE
> range, the default steering we setup at init may not lead to a suitable
> target for L3BANK multicast register. In cases where it does not, use
> explicit runtime steering whenever an L3BANK multicast register is read.
>
> While we're at it, let's simplify the function a little bit and drop its
> support for gen10/CNL since no such platforms ever materialized for real
> use. Multicast register steering is already an area that causes enough
> confusion; no need to complicate it with what's effectively dead code.
>
> v2:
> - Use gt->uncore instead of gt->i915->uncore. (Tvrtko)
> - Use {} as table terminator. (Rodrigo)
>
> Cc: Tvrtko Ursulin
> Cc: Rodrigo Vivi
> Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 18 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h| 4 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 84 ++---
> 3 files changed, 46 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 66299105da66..25a3ecf9892a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -83,6 +83,11 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct
> i915_ggtt *ggtt)
> gt->ggtt = ggtt;
> }
>
> +static const struct intel_mmio_range icl_l3bank_steering_table[] = {
> + { 0x00B100, 0x00B3FF },
> + {},
> +};
> +
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> intel_gt_init_clock_frequency(gt);
> @@ -90,6 +95,13 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> intel_uc_init_mmio(>->uc);
> intel_sseu_info_init(gt);
>
> + if (GRAPHICS_VER(gt->i915) >= 11) {
> + gt->steering_table[L3BANK] = icl_l3bank_steering_table;
> + gt->info.l3bank_mask =
> + intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> + GEN10_L3BANK_MASK;
> + }
> +
> return intel_engines_init_mmio(gt);
> }
>
> @@ -744,6 +756,12 @@ static void intel_gt_get_valid_steering(struct intel_gt
> *gt,
> u8 *sliceid, u8 *subsliceid)
> {
> switch (type) {
> + case L3BANK:
> + GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
> impossible! */
> +
> + *sliceid = __ffs(gt->info.l3bank_mask);
> + *subsliceid = 0;/* unused */
> + break;
> default:
> MISSING_CASE(type);
> *sliceid = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index f2c274eee1e6..80dc131e862f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -48,6 +48,8 @@ struct intel_mmio_range {
> * need to explicitly re-steer reads of registers of the other type.
> */
> enum intel_steering_type {
> + L3BANK,
> +
> NUM_STEERING_TYPES
> };
>
> @@ -174,6 +176,8 @@ struct intel_gt {
> /* Media engine access to SFC per instance */
> u8 vdbox_sfc_access;
>
> + u32 l3bank_mask;
> +
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 93c74d4cae02..d9a5a445ceec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -945,71 +945,37 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> }
>
> static void
> -wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
> unsigned int slice, subslice;
> - u32 l3_en, mcr, mcr_mask;
> + u32 mcr, mcr_mask;
>
> - GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
> + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
> + GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> + slice = 0;
>
> /*
> - * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> - * L3Banks could be fused off in single slice scenario. If that is
> - * the case, we might need to program M
Re: [Intel-gfx] [PATCH] drm/i915: Add relocation exceptions for two other platforms
On Thu, Jun 17, 2021 at 07:44:18AM +0200, Zbigniew Kempczyński wrote:
> For topic/intel-for-CI branch only.
pushed to topic/core-for-CI.
Thanks for the patch.
>
> We have established previously we stop using relocations starting
> from gen12 platforms with Tigerlake as an exception. We keep this
> statement but we want to enable relocations conditionally for
> Alderlake S+P under require_force_probe flag set.
>
> Keeping relocations under require_force_probe flag is interim solution
> until IGTs will be rewritten to use softpin.
>
> v2: - remove inline from function definition (Jani)
> - fix indentation
>
> v3: change to GRAPHICS_VER() (Zbigniew)
>
> v4: remove RKL from flag as it is already shipped (Rodrigo)
>
> v5: prepare patch to be used within topic/intel-for-CI branch only
>
> v6: change comment (Rodrigo)
>
> Signed-off-by: Zbigniew Kempczyński
> Cc: Dave Airlie
> Cc: Daniel Vetter
> Cc: Jason Ekstrand
> Cc: Rodrigo Vivi
> Acked-by: Dave Airlie
> Acked-by: Rodrigo Vivi
> ---
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 ++-
> 1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 760c8aefea3a..8f15fa88cac6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -491,16 +491,27 @@ eb_unreserve_vma(struct eb_vma *ev)
> ev->flags &= ~__EXEC_OBJECT_RESERVED;
> }
>
> +static bool platform_has_relocs_enabled(const struct i915_execbuffer *eb)
> +{
> + /*
> + * Relocations are disallowed starting from gen12 with Tigerlake
> + * as an exception. To unblock CI, we are temporarily allowing it
> + * for Rocketlake and Alderlake.
> + */
> + if (GRAPHICS_VER(eb->i915) < 12 || IS_TIGERLAKE(eb->i915) ||
> + IS_ROCKETLAKE(eb->i915) || IS_ALDERLAKE_S(eb->i915) ||
> + IS_ALDERLAKE_P(eb->i915))
> + return true;
> +
> + return false;
> +}
> +
> static int
> eb_validate_vma(struct i915_execbuffer *eb,
> struct drm_i915_gem_exec_object2 *entry,
> struct i915_vma *vma)
> {
> - /* Relocations are disallowed for all platforms after TGL-LP. This
> - * also covers all platforms with local memory.
> - */
> - if (entry->relocation_count &&
> - GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> + if (entry->relocation_count && !platform_has_relocs_enabled(eb))
> return -EINVAL;
>
> if (unlikely(entry->flags & eb->invalid_flags))
> --
> 2.26.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix up skl_program_plane() pxp stuff
On Thu, Oct 07, 2021 at 02:57:02AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> There's lots of expensive stuff inserted between the PLANE_CTL
> and PLANE_SURF writes even though the comment before the PLANE_CTL
> write says not to put stuff there. Move it all to a more apporiate
> place.
Yeap, the comment was ignored by all, including me during reviews. Sorry.
I'm wondering now if this entire block deserves a separated function
with more emphasis on the "do not put anything between plane_ctl and
plane_srf...
>
> There's also a weird PLANE_COLOR_CTL RMW in there. I guess because
> force_black was computed way too late originally, but that is now
> sorted.
I would be hesitant in removing that, but since Juston confirmed that
everything works well for him with these patches, it is fine by me.
Great clean-up.
Reviewed-by: Rodrigo Vivi
Thanks for this and all the other patches.
>
> Cc: Anshuman Gupta
> Cc: Daniele Ceraolo Spurio
> Cc: Juston Li
> Cc: Rodrigo Vivi
> Cc: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/skl_universal_plane.c| 30 +--
> 1 file changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 1fcb41942c7e..55dae8c8fcad 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -985,6 +985,9 @@ static u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
> plane_color_ctl |=
> PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> }
>
> + if (plane_state->force_black)
> + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> +
> return plane_color_ctl;
> }
>
> @@ -1090,8 +1093,19 @@ skl_program_plane(struct intel_plane *plane,
> aux_dist |= skl_plane_stride(plane_state, aux_plane);
> }
>
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> + if (plane_state->decrypt)
> + plane_surf |= PLANE_SURF_DECRYPT;
> +
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>
> + /*
> + * FIXME: pxp session invalidation can hit any time even at time of
> commit
> + * or after the commit, display content will be garbage.
> + */
> + if (plane_state->force_black)
> + intel_load_plane_csc_black(plane);
> +
> intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> (crtc_y << 16) | crtc_x);
> @@ -1146,22 +1160,6 @@ skl_program_plane(struct intel_plane *plane,
>* the control register just before the surface register.
>*/
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> - plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe,
> plane_id));
> -
> - /*
> - * FIXME: pxp session invalidation can hit any time even at time of
> commit
> - * or after the commit, display content will be garbage.
> - */
> - if (plane_state->decrypt) {
> - plane_surf |= PLANE_SURF_DECRYPT;
> - } else if (plane_state->force_black) {
> - intel_load_plane_csc_black(plane);
> - plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
> - }
> -
> - intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> - plane_color_ctl);
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> --
> 2.32.0
>
[Intel-gfx] [PATCH 2/5] drm/i915: Clean up PXP Kconfig info.
During the review I focused on stop the using of the "+" to reference the newer platforms, but I forgot that we are in a process of making things more clear and differentiate graphics and display versions. So, let me to clean up this a bit. Also, we don't need any version mentioned in the config menu entry, only in the help. Cc: Alan Previn Cc: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/Kconfig | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 8859444943a0..bf041b26ffec 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -132,15 +132,15 @@ config DRM_I915_GVT_KVMGT Intel GVT-g. config DRM_I915_PXP - bool "Enable Intel PXP support for Intel Gen12 and newer platform" + bool "Enable Intel PXP support" depends on DRM_I915 depends on INTEL_MEI && INTEL_MEI_PXP default n help - PXP (Protected Xe Path) is an i915 component, available on GEN12 and - newer GPUs, that helps to establish the hardware protected session and - manage the status of the alive software session, as well as its life - cycle. + PXP (Protected Xe Path) is an i915 component, available on graphics + version 12 and newer GPUs, that helps to establish the hardware + protected session and manage the status of the alive software session, + as well as its life cycle. menu "drm/i915 Debugging" depends on DRM_I915 -- 2.31.1
[Intel-gfx] [PATCH 3/5] drm/i915/display: Random clean up of comments around display version.
We should prefer Display version over the old global "gen" thing.
Of course we are not changing functions and variables and the legacy
there, but at least let's start to document things properly and
set some good examples.
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index e04767695530..08ffea6e1ae3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2244,7 +2244,7 @@ static int i915_lpsp_capability_show(struct seq_file *m,
void *data)
/*
* Actually TGL can drive LPSP on port till DDI_C
* but there is no physical connected DDI_C on TGL sku's,
-* even driver is not initilizing DDI_C port for gen12.
+* even driver is not initilizing DDI_C port for display 12.
*/
lpsp_capable = encoder->port <= PORT_B;
else if (DISPLAY_VER(i915) == 11)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1672604f9ef7..7f94ef997ea7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5287,7 +5287,7 @@ static void icl_mbus_init(struct drm_i915_private
*dev_priv)
MBUS_ABOX_BW_CREDIT(1);
/*
-* gen12 platforms that use abox1 and abox2 for pixel data reads still
+* Display 12 platforms using abox1 and abox2 for pixel data reads still
* expect us to program the abox_ctl0 register as well, even though
* we don't have to program other instance-0 registers like BW_BUDDY.
*/
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3..73c8500c79d1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -506,9 +506,9 @@ struct intel_hdcp {
int cp_irq_count_cached;
/*
-* HDCP register access for gen12+ need the transcoder associated.
-* Transcoder attached to the connector could be changed at modeset.
-* Hence caching the transcoder here.
+* HDCP register access for display 12 and newer platforms need the
+* transcoder associated. Transcoder attached to the connector could be
+* changed at modeset. Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
/* Only used for DP MST stream encryption */
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 62a8a69f9f5d..e759d98bb766 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -18,7 +18,7 @@
* engine that can be programmed to download the DSB from memory.
* It allows driver to batch submit display HW programming. This helps to
* reduce loading time and CPU activity, thereby making the context switch
- * faster. DSB Support added from Gen12 Intel graphics based platform.
+ * faster. DSB Support is introduced on Display Version 12.
*
* DSB's can access only the pipe, plane, and transcoder Data Island Packet
* registers.
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 4509fe7438e8..e377a192b744 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2188,7 +2188,7 @@ static int initialize_hdcp_port_data(struct
intel_connector *connector,
/*
* As associated transcoder is set and modified at modeset, here fw_tc
* is initialized to zero (invalid transcoder index). This will be
-* retained for fw_tc = MEI_INVALID_TRANSCODER;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a205fd5023b..920b86f165a1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -68,7 +68,7 @@
*
* DC3CO (DC3 clock off)
*
- * On top of PSR2, GEN12 adds a intermediate power savings state that turns
+ * On top of PSR2, Display 12 adds a intermediate power savings state that
turns
* clock off automatically during PSR2 idle state.
* The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
* ent
[Intel-gfx] [PATCH 1/5] drm/i915: Clean-up bonding debug message.
We should stop using the gen name and the "+" to reference
the newer platforms.
And on this case specifically we can simplify the debug
message even further.
Cc: Jani Nikula
Cc: Matthew Brost
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..30759b651180 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -479,7 +479,7 @@ set_proto_ctx_engines_bond(struct i915_user_extension
__user *base, void *data)
if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
!IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
drm_dbg(&i915->drm,
- "Bonding on gen12+ aside from TGL, RKL, and ADL_S not
supported\n");
+ "Bonding not supported on this platform\n");
return -ENODEV;
}
--
2.31.1
[Intel-gfx] [PATCH 5/5] drm/i915: Other random display and graphics version comment clean-ups
We should prefer Graphics and Display version over the
old global "gen" thing. Of course we are not changing functions
and variables and the legacy there, but at least let's start to
document things properly and set some good examples.
Cc: Jani Nikula
Cc: Joonas Lahtinen
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 8
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77680bca46ee..c50ae0843757 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2362,7 +2362,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private
*dev_priv, u32 iir)
intel_psr_irq_handler(intel_dp, psr_iir);
- /* prior GEN12 only have one EDP PSR */
+ /* prior Display 12 only have one EDP PSR */
if (DISPLAY_VER(dev_priv) < 12)
break;
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2f01b8c0284c..44e149a4cae8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3444,10 +3444,10 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
*
-* For Gen12+ we gain a new OAR unit that only monitors the RCS on a
-* per context basis. So we can relax requirements there if the user
-* doesn't request global stream access (i.e. query based sampling
-* using MI_RECORD_PERF_COUNT.
+* For Graphics 12 and newer platforms, we gain a new OAR unit that only
+* monitors the RCS on a per context basis. So we can relax requirements
+* there if the user doesn't request global stream access (i.e. query
+* based sampling using MI_RECORD_PERF_COUNT.
*/
if (IS_HASWELL(perf->i915) && specific_ctx)
privileged_op = false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..b01fe09729ef 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8264,8 +8264,8 @@ enum {
#define DISP_IPC_ENABLE (1 << 3)
/*
- * The below are numbered starting from "S1" on gen11/gen12, but starting
- * with gen13 display, the bspec switches to a 0-based numbering scheme
+ * The below are numbered starting from "S1" on display versions 11 and 12, but
+ * starting with display 13, the bspec switches to a 0-based numbering scheme
* (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
* We'll just use the 0-based numbering here for all platforms since it's the
* way things will be named by the hardware team going forward, plus it's more
--
2.31.1
[Intel-gfx] [PATCH 4/5] drm/i915/gt: Random clean up of comments around display version.
Although gen12 is a valid thing for the gt side on TGL,
we should prefer graphics version over the old global "gen" thing.
Of course we are not changing functions and variables and the legacy
there, but at least let's start to document things properly and
set some good examples.
Cc: Joonas Lahtinen
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 73a79c2acd3a..b6b9d324f519 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1650,7 +1650,7 @@ static void invalidate_csb_entries(const u64 *first,
const u64 *last)
}
/*
- * Starting with Gen12, the status has a new format:
+ * Starting with Graphics version 12, the status has a new format:
*
* bit 0: switched to new queue
* bit 1: reserved
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 3ef9eaf8c50e..ed0f0e81bb56 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -611,10 +611,10 @@ static const u8 dg2_rcs_offsets[] = {
static const u8 *reg_offsets(const struct intel_engine_cs *engine)
{
/*
-* The gen12+ lists only have the registers we program in the basic
-* default state. We rely on the context image using relative
-* addressing to automatic fixup the register state between the
-* physical engines for virtual engine.
+* The graphics 12 and newer platforms, lists only have the registers we
+* program in the basic default state. We rely on the context image
+* using relative addressing to automatic fixup the register state
+* between the physical engines for virtual engine.
*/
GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
!intel_engine_has_relative_mmio(engine));
--
2.31.1
[Intel-gfx] [PATCH] drm/i915: Clean up PXP Kconfig info.
During the review I focused on stop the using of the "+" to reference the newer platforms, but I forgot that we are in a process of making things more clear and differentiate graphics and display versions. So, let me to clean up this a bit. Also, we don't need any version mentioned in the config menu entry, only in the help. Cc: Alan Previn Cc: Daniele Ceraolo Spurio Signed-off-by: Rodrigo Vivi Reviewed-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 8859444943a0..bf041b26ffec 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -132,15 +132,15 @@ config DRM_I915_GVT_KVMGT Intel GVT-g. config DRM_I915_PXP - bool "Enable Intel PXP support for Intel Gen12 and newer platform" + bool "Enable Intel PXP support" depends on DRM_I915 depends on INTEL_MEI && INTEL_MEI_PXP default n help - PXP (Protected Xe Path) is an i915 component, available on GEN12 and - newer GPUs, that helps to establish the hardware protected session and - manage the status of the alive software session, as well as its life - cycle. + PXP (Protected Xe Path) is an i915 component, available on graphics + version 12 and newer GPUs, that helps to establish the hardware + protected session and manage the status of the alive software session, + as well as its life cycle. menu "drm/i915 Debugging" depends on DRM_I915 -- 2.31.1
[Intel-gfx] [PATCH] drm/i915: Clean-up bonding debug message.
We should stop using the gen name and the "+" to reference
the newer platforms.
And on this case specifically we can simplify the debug
message even further.
Cc: Jani Nikula
Cc: Matthew Brost
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d225d3dd0b40..30759b651180 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -479,7 +479,7 @@ set_proto_ctx_engines_bond(struct i915_user_extension
__user *base, void *data)
if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
!IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
drm_dbg(&i915->drm,
- "Bonding on gen12+ aside from TGL, RKL, and ADL_S not
supported\n");
+ "Bonding not supported on this platform\n");
return -ENODEV;
}
--
2.31.1
[Intel-gfx] [PATCH] drm/i915: Don't propagate the gen split confusion further
There's no such thing as gen13. It is either display 13
or graphics 13. Don't propagate the gen12 confusion
further.
Cc: Joonas Lahtinen
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index da9055c3ebf0..1e221fbe37fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8263,7 +8263,7 @@ enum {
/*
* The below are numbered starting from "S1" on gen11/gen12, but starting
- * with gen13 display, the bspec switches to a 0-based numbering scheme
+ * with display 13, the bspec switches to a 0-based numbering scheme
* (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
* We'll just use the 0-based numbering here for all platforms since it's the
* way things will be named by the hardware team going forward, plus it's more
--
2.31.1
[Intel-gfx] [PULL] drm-intel-next
Hi Dave and Daniel,
Here goes drm-intel-next-2021-10-15:
Likely the last one towards 5.15.
UAPI Changes:
- No Functional change, but a clarification around I915_TILING values (Matt).
Driver Changes:
- Changes around async flip VT-d w/a (Ville)
- Delete bogus NULL check in intel_ddi_encoder_destroy (Dan)
- DP link training improvements and DP per-lane driver settings (Ville)
- Free the returned object of acpi_evaluate_dsm (Zenghui)
- Fixes and improvements around DP's UHBR and MST (Jani)
- refactor plane config + pin out (Dave)
- remove unused include in intel_dsi_vbt.c (Lucas)
- some code clean up (Lucas, Jani)
- gracefully disable dual eDP (Jani)
- Remove memory frequency calculation (Jose)
- Fix oops on platforms w/o hpd support (Ville)
- Clean up PXP Kconfig info (Rodrigo)
Thanks,
Rodrigo.
The following changes since commit 1176d15f0f6e556d54ced510ac4a91694960332b:
Merge tag 'drm-intel-gt-next-2021-10-08' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-10-11 18:09:39
+1000)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-10-15
for you to fetch changes up to c974cf01b248c6f4220bfadd57cce74058453aea:
drm/i915: Clean up PXP Kconfig info. (2021-10-15 14:22:11 -0400)
UAPI Changes:
- No Functional change, but a clarification around I915_TILING values (Matt).
Driver Changes:
- Changes around async flip VT-d w/a (Ville)
- Delete bogus NULL check in intel_ddi_encoder_destroy (Dan)
- DP link training improvements and DP per-lane driver settings (Ville)
- Free the returned object of acpi_evaluate_dsm (Zenghui)
- Fixes and improvements around DP's UHBR and MST (Jani)
- refactor plane config + pin out (Dave)
- remove unused include in intel_dsi_vbt.c (Lucas)
- some code clean up (Lucas, Jani)
- gracefully disable dual eDP (Jani)
- Remove memory frequency calculation (Jose)
- Fix oops on platforms w/o hpd support (Ville)
- Clean up PXP Kconfig info (Rodrigo)
Dan Carpenter (1):
drm/i915/tc: Delete bogus NULL check in intel_ddi_encoder_destroy()
Dave Airlie (5):
drm/i915/display: move plane prepare/cleanup to intel_atomic_plane.c
drm/i915/display: let intel_plane_uses_fence be used from other places.
drm/i915/display: refactor out initial plane config for crtcs
drm/i915/display: refactor initial plane config to a separate file
drm/i915/display: move pin/unpin fb/plane code to a new file.
Jani Nikula (9):
drm/i915/dg2: fix snps buf trans for uhbr
drm/i915/dp: take LTTPR into account in 128b/132b rates
drm/i915/mst: abstract intel_dp_mst_source_support()
drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
drm/i915/dg2: update link training for 128b/132b
drm/i915: split out vlv sideband to a separate file
drm/i915/bios: gracefully disable dual eDP for now
drm/i915: split out intel_pcode.[ch] to separate file
drm/i915: rename intel_sideband.[ch] to intel_sbi.[ch]
José Roberto de Souza (1):
drm/i915: Remove memory frequency calculation
Lucas De Marchi (1):
drm/i915/display: remove unused intel-mid.h include
Matt Roper (1):
drm/i915/uapi: Add comment clarifying purpose of I915_TILING_* values
Rodrigo Vivi (2):
Merge drm/drm-next into drm-intel-next
drm/i915: Clean up PXP Kconfig info.
Ville Syrjälä (14):
drm/i915: Extend the async flip VT-d w/a to skl/bxt
drm/i195: Make the async flip VT-d workaround dynamic
drm/i915: Tweak the DP "max vswing reached?" condition
drm/i915: Show LTTPR in the TPS debug print
drm/i915: Print the DP vswing adjustment request
drm/i915: Pimp link training debug prints
drm/i915: Call intel_dp_dump_link_status() for CR failures
drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs
drm/i915: Shrink {icl_mg,tgl_dkl}_phy_ddi_buf_trans
drm/i915: Use standard form terminating condition for lane for loops
drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
drm/i915: Extract icl_combo_phy_loadgen_select()
drm/i915: Add all per-lane register definitions for icl combo phy
drm/i915: Fix oops on platforms w/o hpd support
Zenghui Yu (1):
drm/i915: Free the returned object of acpi_evaluate_dsm()
drivers/gpu/drm/i915/Kconfig | 10 +-
drivers/gpu/drm/i915/Makefile | 6 +-
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c| 2 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +-
drivers/gpu/drm/i915/display/intel_acpi.c | 7 +-
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 209 ++
drivers/gpu/drm/i915/display/intel_bios.c | 47 ++
drivers/g
Re: [Intel-gfx] [PATCH] drm/i915: Don't propagate the gen split confusion further
On Mon, Oct 18, 2021 at 11:25:00AM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Rodrigo Vivi wrote:
> > There's no such thing as gen13. It is either display 13
> > or graphics 13. Don't propagate the gen12 confusion
> > further.
>
> Reviewed-by: Jani Nikula
thanks, pushed
>
> >
> > Cc: Joonas Lahtinen
> > Cc: Jani Nikula
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index da9055c3ebf0..1e221fbe37fd 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8263,7 +8263,7 @@ enum {
> >
> > /*
> > * The below are numbered starting from "S1" on gen11/gen12, but starting
> > - * with gen13 display, the bspec switches to a 0-based numbering scheme
> > + * with display 13, the bspec switches to a 0-based numbering scheme
> > * (although the addresses stay the same so new S0 = old S1, new S1 = old
> > S2).
> > * We'll just use the 0-based numbering here for all platforms since it's
> > the
> > * way things will be named by the hardware team going forward, plus it's
> > more
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915: Clean-up bonding debug message.
On Mon, Oct 18, 2021 at 11:24:21AM +0300, Jani Nikula wrote:
> On Fri, 15 Oct 2021, Rodrigo Vivi wrote:
> > We should stop using the gen name and the "+" to reference
> > the newer platforms.
> > And on this case specifically we can simplify the debug
> > message even further.
>
> Reviewed-by: Jani Nikula
thanks, pushed
>
> >
> > Cc: Jani Nikula
> > Cc: Matthew Brost
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index d225d3dd0b40..30759b651180 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -479,7 +479,7 @@ set_proto_ctx_engines_bond(struct i915_user_extension
> > __user *base, void *data)
> > if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
> > !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
> > drm_dbg(&i915->drm,
> > - "Bonding on gen12+ aside from TGL, RKL, and ADL_S not
> > supported\n");
> > + "Bonding not supported on this platform\n");
> > return -ENODEV;
> > }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/display: Exit PSR when doing async flips
On Fri, Oct 29, 2021 at 05:18:01PM -0700, José Roberto de Souza wrote:
> Changing the buffer in the middle of the scanout then entering an
> period of flip idleness will cause part of the previous buffer being
> diplayed to user when PSR is enabled.
>
> So here disabling and scheduling activation after a few milliseconds
> when async flip is enabled in the state.
>
> The async flip check that we had in PSR compute is not executed at
> every flip so it was not doing anything useful and is also being
> dropped here.
>
> Cc: Karthik B S
> Cc: Vandita Kulkarni
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +--
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9d589d471e335..d1301e2729553 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -731,12 +731,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (crtc_state->uapi.async_flip) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR2 sel fetch not enabled, async flip enabled\n");
> - return false;
> - }
> -
> /* Wa_14010254185 Wa_14010103792 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> drm_dbg_kms(&dev_priv->drm,
> @@ -1780,6 +1774,11 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
>
> + if (psr->enabled && crtc_state->uapi.async_flip) {
> + intel_psr_exit(intel_dp);
> + schedule_work(&intel_dp->psr.work);
wouldn't it be better(safer?) to reschedule it back in a later stage?
> + }
> +
> mutex_unlock(&psr->lock);
> }
> }
> --
> 2.33.1
>
Re: [Intel-gfx] [PATCH v9 12/17] drm/i915/pxp: Enable PXP power management
On Fri, Sep 10, 2021 at 08:36:22AM -0700, Daniele Ceraolo Spurio wrote:
> From: "Huang, Sean Z"
>
> During the power event S3+ sleep/resume, hardware will lose all the
> encryption keys for every hardware session, even though the
> session state might still be marked as alive after resume. Therefore,
> we should consider the session as dead on suspend and invalidate all the
> objects. The session will be automatically restarted on the first
> protected submission on resume.
>
> v2: runtime suspend also invalidates the keys
> v3: fix return codes, simplify rpm ops (Chris), use the new worker func
> v4: invalidate the objects on suspend, don't re-create the arb sesson on
> resume (delayed to first submission).
> v5: move irq changes back to irq patch (Rodrigo)
> v6: drop invalidation in runtime suspend (Rodrigo)
>
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
ops, I had missed this patch. Sorry
and thanks Alan for the ping.
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 ++-
> drivers/gpu/drm/i915/i915_drv.c | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 46
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 +++-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9
> 8 files changed, 124 insertions(+), 11 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index b22b8c195bb8..366e82cec44d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -286,6 +286,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_irq.o \
> + pxp/intel_pxp_pm.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index dea8e2479897..b47a8d8f1bb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -18,6 +18,7 @@
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_pm.h"
>
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> @@ -262,6 +263,8 @@ int intel_gt_resume(struct intel_gt *gt)
>
> intel_uc_resume(>->uc);
>
> + intel_pxp_resume(>->pxp);
> +
> user_forcewake(gt, false);
>
> out_fw:
> @@ -296,6 +299,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> user_forcewake(gt, true);
> wait_for_suspend(gt);
>
> + intel_pxp_suspend(>->pxp, false);
> intel_uc_suspend(>->uc);
> }
>
> @@ -346,6 +350,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
>
> void intel_gt_runtime_suspend(struct intel_gt *gt)
> {
> + intel_pxp_suspend(>->pxp, true);
We should actually remove this from here
> intel_uc_runtime_suspend(>->uc);
>
> GT_TRACE(gt, "\n");
> @@ -353,11 +358,19 @@ void intel_gt_runtime_suspend(struct intel_gt *gt)
>
> int intel_gt_runtime_resume(struct intel_gt *gt)
> {
> + int ret;
> +
> GT_TRACE(gt, "\n");
> intel_gt_init_swizzling(gt);
> intel_ggtt_restore_fences(gt->ggtt);
>
> - return intel_uc_runtime_resume(>->uc);
> + ret = intel_uc_runtime_resume(>->uc);
> + if (ret)
> + return ret;
> +
> + intel_pxp_resume(>->pxp);
And from here...
> +
> + return 0;
> }
>
> static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 59fb4c710c8c..d5bcc70a22d4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -67,6 +67,8 @@
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_rc6.h"
>
> +#include "pxp/intel_pxp_pm.h"
> +
> #include "i915_debugfs.h"
> #include "i915_drv.h"
> #include "i915_ioc32.h"
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> index 340f20d130a8..9e5847c653f2 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
>
Re: [Intel-gfx] [PATCH v9 12/17] drm/i915/pxp: Enable PXP power management
On Wed, Sep 15, 2021 at 08:11:54AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 9/14/2021 12:13 PM, Rodrigo Vivi wrote:
> > On Fri, Sep 10, 2021 at 08:36:22AM -0700, Daniele Ceraolo Spurio wrote:
> > > From: "Huang, Sean Z"
> > >
> > > During the power event S3+ sleep/resume, hardware will lose all the
> > > encryption keys for every hardware session, even though the
> > > session state might still be marked as alive after resume. Therefore,
> > > we should consider the session as dead on suspend and invalidate all the
> > > objects. The session will be automatically restarted on the first
> > > protected submission on resume.
> > >
> > > v2: runtime suspend also invalidates the keys
> > > v3: fix return codes, simplify rpm ops (Chris), use the new worker func
> > > v4: invalidate the objects on suspend, don't re-create the arb sesson on
> > > resume (delayed to first submission).
> > > v5: move irq changes back to irq patch (Rodrigo)
> > > v6: drop invalidation in runtime suspend (Rodrigo)
> > >
> > > Signed-off-by: Huang, Sean Z
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > Cc: Chris Wilson
> > > Cc: Rodrigo Vivi
> > ops, I had missed this patch. Sorry
> > and thanks Alan for the ping.
> >
> > > ---
> > > drivers/gpu/drm/i915/Makefile| 1 +
> > > drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 ++-
> > > drivers/gpu/drm/i915/i915_drv.c | 2 +
> > > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 +
> > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 46
> > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++
> > > drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 +++-
> > > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9
> > > 8 files changed, 124 insertions(+), 11 deletions(-)
> > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> > >
> > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > > index b22b8c195bb8..366e82cec44d 100644
> > > --- a/drivers/gpu/drm/i915/Makefile
> > > +++ b/drivers/gpu/drm/i915/Makefile
> > > @@ -286,6 +286,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> > > pxp/intel_pxp.o \
> > > pxp/intel_pxp_cmd.o \
> > > pxp/intel_pxp_irq.o \
> > > + pxp/intel_pxp_pm.o \
> > > pxp/intel_pxp_session.o \
> > > pxp/intel_pxp_tee.o
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > index dea8e2479897..b47a8d8f1bb5 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > @@ -18,6 +18,7 @@
> > > #include "intel_rc6.h"
> > > #include "intel_rps.h"
> > > #include "intel_wakeref.h"
> > > +#include "pxp/intel_pxp_pm.h"
> > > static void user_forcewake(struct intel_gt *gt, bool suspend)
> > > {
> > > @@ -262,6 +263,8 @@ int intel_gt_resume(struct intel_gt *gt)
> > > intel_uc_resume(>->uc);
> > > + intel_pxp_resume(>->pxp);
> > > +
> > > user_forcewake(gt, false);
> > > out_fw:
> > > @@ -296,6 +299,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> > > user_forcewake(gt, true);
> > > wait_for_suspend(gt);
> > > + intel_pxp_suspend(>->pxp, false);
> > > intel_uc_suspend(>->uc);
> > > }
> > > @@ -346,6 +350,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
> > > void intel_gt_runtime_suspend(struct intel_gt *gt)
> > > {
> > > + intel_pxp_suspend(>->pxp, true);
> > We should actually remove this from here
>
> No we shouldn't. The PXP suspend does other things in addition to the
> invalidation (e.g. marking the ARB session as invalid) and those must be
> performed, otherwise the SW state won't match the HW. That's why I added a
> variable instead of dropping the call. Similar for the resume.
Why? We are blocking the runtime PM. This functions will never be called
anyway...
>
> Daniele
>
> >
> > > intel_uc_runtime_suspend(>->uc);
> > > GT_TRACE(gt, "\n");
> > > @@
Re: [Intel-gfx] [PATCH v9 03/17] drm/i915/pxp: define PXP device flag and kconfig
On Wed, Sep 15, 2021 at 04:29:50PM +0300, Jani Nikula wrote:
> On Fri, 10 Sep 2021, Daniele Ceraolo Spurio
> wrote:
> > Ahead of the PXP implementation, define the relevant define flag and
> > kconfig option.
> >
> > v2: flip kconfig default to N. Some machines have IFWIs that do not
> > support PXP, so we need it to be an opt-in until we add support to query
> > the caps from the mei device.
> >
> > Signed-off-by: Daniele Ceraolo Spurio
> > Reviewed-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/Kconfig | 11 +++
> > drivers/gpu/drm/i915/i915_drv.h | 3 +++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > 3 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> > index f960f5d7664e..5987c3d5d9fb 100644
> > --- a/drivers/gpu/drm/i915/Kconfig
> > +++ b/drivers/gpu/drm/i915/Kconfig
> > @@ -131,6 +131,17 @@ config DRM_I915_GVT_KVMGT
> > Choose this option if you want to enable KVMGT support for
> > Intel GVT-g.
> >
> > +config DRM_I915_PXP
> > + bool "Enable Intel PXP support for Intel Gen12+ platform"
> > + depends on DRM_I915
> > + depends on INTEL_MEI && INTEL_MEI_PXP
> > + default n
> > + help
> > + PXP (Protected Xe Path) is an i915 component, available on GEN12+
>
> Is GEN12+ something we still want to use in help texts?
Good catch. The + might create some confusion.
We need to change this to something like gen12 and newer,
or something like that...
>
> BR,
> Jani.
>
> > + GPUs, that helps to establish the hardware protected session and
> > + manage the status of the alive software session, as well as its life
> > + cycle.
> > +
> > menu "drm/i915 Debugging"
> > depends on DRM_I915
> > depends on EXPERT
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 37c1ca266bcd..447a248f14aa 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1678,6 +1678,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
> > (INTEL_INFO(dev_priv)->has_global_mocs)
> >
> > +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
> > + INTEL_INFO(dev_priv)->has_pxp) && \
> > + VDBOX_MASK(&dev_priv->gt)
> >
> > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index d328bb95c49b..8e6f48d1eb7b 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -133,6 +133,7 @@ enum intel_ppgtt_type {
> > func(has_logical_ring_elsq); \
> > func(has_mslices); \
> > func(has_pooled_eu); \
> > + func(has_pxp); \
> > func(has_rc6); \
> > func(has_rc6p); \
> > func(has_rps); \
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v9 04/17] drm/i915/pxp: allocate a vcs context for pxp usage
On Wed, Sep 15, 2021 at 04:53:35PM +0300, Jani Nikula wrote:
> On Fri, 10 Sep 2021, Daniele Ceraolo Spurio
> wrote:
> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > new file mode 100644
> > index ..e87550fb9821
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > @@ -0,0 +1,35 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> > + */
> > +
> > +#ifndef __INTEL_PXP_H__
> > +#define __INTEL_PXP_H__
> > +
> > +#include "gt/intel_gt_types.h"
>
> I've been trying to promote the idea that we don't include headers from
> headers, unless really necessary. It helps with build times by reducing
> rebuilds due to changes, but more importantly, it helps with coming up
> with abstractions that don't need to look at the guts of other
> components.
>
> The above include line pulls in 67 other includes. And it has to look at
> the same files a *lot* more times to know not to include them again.
>
> Maybe we need to start being more aggressive about hiding the
> abstractions behind the interfaces and headers. Static inlines are
> nothing but micro-optimizations that leak abstractions. Do we need
> these?
Yeap, we have a few cases where this is already happening...
Should we start using the container_of more directly and avoid the a_to_b()
helpers?
Should we create the a_to_b() helpers only inside .c files like we have
in a few other cases?
In this pxp case here it looks like using the container of directly is
everywhere is better... is this your recommendation?
>
> > +#include "intel_pxp_types.h"
> > +
> > +static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> > +{
> > + return container_of(pxp, struct intel_gt, pxp);
> > +}
>
> I think it's questionable to claim the parameter is const, when you can
> do:
>
> const struct intel_pxp *const_pxp = something;
> struct intel_pxp *pxp = &pxp_to_gt(const_pxp)->pxp;
>
> BR,
> Jani.
>
> > +
> > +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> > +{
> > + return pxp->ce;
> > +}
> > +
> > +#ifdef CONFIG_DRM_I915_PXP
> > +void intel_pxp_init(struct intel_pxp *pxp);
> > +void intel_pxp_fini(struct intel_pxp *pxp);
> > +#else
> > +static inline void intel_pxp_init(struct intel_pxp *pxp)
> > +{
> > +}
> > +
> > +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> > +{
> > +}
> > +#endif
> > +
> > +#endif /* __INTEL_PXP_H__ */
> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > new file mode 100644
> > index ..bd12c520e60a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> > @@ -0,0 +1,15 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> > + */
> > +
> > +#ifndef __INTEL_PXP_TYPES_H__
> > +#define __INTEL_PXP_TYPES_H__
> > +
> > +struct intel_context;
> > +
> > +struct intel_pxp {
> > + struct intel_context *ce;
> > +};
> > +
> > +#endif /* __INTEL_PXP_TYPES_H__ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v9 12/17] drm/i915/pxp: Enable PXP power management
On Wed, Sep 15, 2021 at 11:23:45AM -0400, Rodrigo Vivi wrote:
> On Wed, Sep 15, 2021 at 08:11:54AM -0700, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 9/14/2021 12:13 PM, Rodrigo Vivi wrote:
> > > On Fri, Sep 10, 2021 at 08:36:22AM -0700, Daniele Ceraolo Spurio wrote:
> > > > From: "Huang, Sean Z"
> > > >
> > > > During the power event S3+ sleep/resume, hardware will lose all the
> > > > encryption keys for every hardware session, even though the
> > > > session state might still be marked as alive after resume. Therefore,
> > > > we should consider the session as dead on suspend and invalidate all the
> > > > objects. The session will be automatically restarted on the first
> > > > protected submission on resume.
> > > >
> > > > v2: runtime suspend also invalidates the keys
> > > > v3: fix return codes, simplify rpm ops (Chris), use the new worker func
> > > > v4: invalidate the objects on suspend, don't re-create the arb sesson on
> > > > resume (delayed to first submission).
> > > > v5: move irq changes back to irq patch (Rodrigo)
> > > > v6: drop invalidation in runtime suspend (Rodrigo)
> > > >
> > > > Signed-off-by: Huang, Sean Z
> > > > Signed-off-by: Daniele Ceraolo Spurio
> > > > Cc: Chris Wilson
> > > > Cc: Rodrigo Vivi
> > > ops, I had missed this patch. Sorry
> > > and thanks Alan for the ping.
> > >
> > > > ---
> > > > drivers/gpu/drm/i915/Makefile| 1 +
> > > > drivers/gpu/drm/i915/gt/intel_gt_pm.c| 15 ++-
> > > > drivers/gpu/drm/i915/i915_drv.c | 2 +
> > > > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 1 +
> > > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 46
> > > > drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 23 ++
> > > > drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 38 +++-
> > > > drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9
> > > > 8 files changed, 124 insertions(+), 11 deletions(-)
> > > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> > > > create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > > b/drivers/gpu/drm/i915/Makefile
> > > > index b22b8c195bb8..366e82cec44d 100644
> > > > --- a/drivers/gpu/drm/i915/Makefile
> > > > +++ b/drivers/gpu/drm/i915/Makefile
> > > > @@ -286,6 +286,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
> > > > pxp/intel_pxp.o \
> > > > pxp/intel_pxp_cmd.o \
> > > > pxp/intel_pxp_irq.o \
> > > > + pxp/intel_pxp_pm.o \
> > > > pxp/intel_pxp_session.o \
> > > > pxp/intel_pxp_tee.o
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > > b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > > index dea8e2479897..b47a8d8f1bb5 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> > > > @@ -18,6 +18,7 @@
> > > > #include "intel_rc6.h"
> > > > #include "intel_rps.h"
> > > > #include "intel_wakeref.h"
> > > > +#include "pxp/intel_pxp_pm.h"
> > > > static void user_forcewake(struct intel_gt *gt, bool suspend)
> > > > {
> > > > @@ -262,6 +263,8 @@ int intel_gt_resume(struct intel_gt *gt)
> > > > intel_uc_resume(>->uc);
> > > > + intel_pxp_resume(>->pxp);
> > > > +
> > > > user_forcewake(gt, false);
> > > > out_fw:
> > > > @@ -296,6 +299,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
> > > > user_forcewake(gt, true);
> > > > wait_for_suspend(gt);
> > > > + intel_pxp_suspend(>->pxp, false);
> > > > intel_uc_suspend(>->uc);
> > > > }
> > > > @@ -346,6 +350,7 @@ void intel_gt_suspend_late(struct intel_gt *gt)
> > > > void intel_gt_runtime_suspend(struct intel_gt *gt)
> > > > {
> > > > + intel_pxp_suspend(>->pxp, true);
> > > We should actually remove this from here
> >
> > No we shouldn't. The PXP suspend does other things in add
Re: [Intel-gfx] [PATCH v9 04/17] drm/i915/pxp: allocate a vcs context for pxp usage
On Thu, Sep 16, 2021 at 02:06:56PM +0300, Jani Nikula wrote:
> On Wed, 15 Sep 2021, Rodrigo Vivi wrote:
> > On Wed, Sep 15, 2021 at 04:53:35PM +0300, Jani Nikula wrote:
> >> On Fri, 10 Sep 2021, Daniele Ceraolo Spurio
> >> wrote:
> >> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> >> > b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> >> > new file mode 100644
> >> > index ..e87550fb9821
> >> > --- /dev/null
> >> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> >> > @@ -0,0 +1,35 @@
> >> > +/* SPDX-License-Identifier: MIT */
> >> > +/*
> >> > + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> >> > + */
> >> > +
> >> > +#ifndef __INTEL_PXP_H__
> >> > +#define __INTEL_PXP_H__
> >> > +
> >> > +#include "gt/intel_gt_types.h"
> >>
> >> I've been trying to promote the idea that we don't include headers from
> >> headers, unless really necessary. It helps with build times by reducing
> >> rebuilds due to changes, but more importantly, it helps with coming up
> >> with abstractions that don't need to look at the guts of other
> >> components.
> >>
> >> The above include line pulls in 67 other includes. And it has to look at
> >> the same files a *lot* more times to know not to include them again.
> >>
> >> Maybe we need to start being more aggressive about hiding the
> >> abstractions behind the interfaces and headers. Static inlines are
> >> nothing but micro-optimizations that leak abstractions. Do we need
> >> these?
> >
> > Yeap, we have a few cases where this is already happening...
> >
> > Should we start using the container_of more directly and avoid the a_to_b()
> > helpers?
> >
> > Should we create the a_to_b() helpers only inside .c files like we have
> > in a few other cases?
> >
> > In this pxp case here it looks like using the container of directly is
> > everywhere is better... is this your recommendation?
>
> Either that, or make it a non-inline function that's actually
> abstracted. Yes, it leads to a function call, but I'm really starting to
> wonder about the costs of a function call vs. maintainability across the
> board.
Alan, could you please address this? With that addressed and CI happy
we will merge to the already created topic/pxp and do the proper
pull requests.
if your change only touches this patch don't need to resend the whole
series but just in-reply-to. But if changes everything to container-of
please resend it entirely.
Thanks,
Rodrigo.
>
> Static inlines considered harmful.
>
>
> BR,
> Jani.
>
>
> >
> >>
> >> > +#include "intel_pxp_types.h"
> >> > +
> >> > +static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> >> > +{
> >> > +return container_of(pxp, struct intel_gt, pxp);
> >> > +}
> >>
> >> I think it's questionable to claim the parameter is const, when you can
> >> do:
> >>
> >>const struct intel_pxp *const_pxp = something;
> >>struct intel_pxp *pxp = &pxp_to_gt(const_pxp)->pxp;
> >>
> >> BR,
> >> Jani.
> >>
> >> > +
> >> > +static inline bool intel_pxp_is_enabled(const struct intel_pxp *pxp)
> >> > +{
> >> > +return pxp->ce;
> >> > +}
> >> > +
> >> > +#ifdef CONFIG_DRM_I915_PXP
> >> > +void intel_pxp_init(struct intel_pxp *pxp);
> >> > +void intel_pxp_fini(struct intel_pxp *pxp);
> >> > +#else
> >> > +static inline void intel_pxp_init(struct intel_pxp *pxp)
> >> > +{
> >> > +}
> >> > +
> >> > +static inline void intel_pxp_fini(struct intel_pxp *pxp)
> >> > +{
> >> > +}
> >> > +#endif
> >> > +
> >> > +#endif /* __INTEL_PXP_H__ */
> >> > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> >> > b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> >> > new file mode 100644
> >> > index ..bd12c520e60a
> >> > --- /dev/null
> >> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> >> > @@ -0,0 +1,15 @@
> >> > +/* SPDX-License-Identifier: MIT */
> >> > +/*
> >> > + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> >> > + */
> >> > +
> >> > +#ifndef __INTEL_PXP_TYPES_H__
> >> > +#define __INTEL_PXP_TYPES_H__
> >> > +
> >> > +struct intel_context;
> >> > +
> >> > +struct intel_pxp {
> >> > +struct intel_context *ce;
> >> > +};
> >> > +
> >> > +#endif /* __INTEL_PXP_TYPES_H__ */
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915: Make wa list per-gt
On Fri, Sep 17, 2021 at 10:08:45AM -0700, Matt Roper wrote:
> From: Venkata Sandeep Dhanalakota
>
> Support for multiple GT's within a single i915 device will be arriving
> soon. Since each GT may have its own fusing and require different
> workarounds, we need to make the GT workaround functions and multicast
> steering setup per-gt.
>
> Cc: Tvrtko Ursulin
> Cc: Daniele Ceraolo Spurio
> Signed-off-by: Venkata Sandeep Dhanalakota
> Signed-off-by: Matt Roper
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c| 3 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 143 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.h | 2 +-
> .../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 2 -
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/i915_gem.c | 2 -
> 8 files changed, 81 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 55e87aff51d2..449ff6e83543 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> return err;
>
> + intel_gt_init_workarounds(gt);
> +
> /*
>* This is just a security blanket to placate dragons.
>* On some systems, we very sporadically observe that the first TLBs
> @@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
> if (vm) /* FIXME being called twice on error paths :( */
> i915_vm_put(vm);
>
> + intel_wa_list_free(>->wa_list);
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6fdcde64c180..ce127cae9e49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -72,6 +72,8 @@ struct intel_gt {
>
> struct intel_uc uc;
>
> + struct i915_wa_list wa_list;
> +
> struct intel_gt_timelines {
> spinlock_t lock; /* protects active_list */
> struct list_head active_list;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c314d4917b6b..1f0a54b383d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> }
>
> static void
> -gen4_gt_workarounds_init(struct drm_i915_private *i915,
> +gen4_gt_workarounds_init(struct intel_gt *gt,
>struct i915_wa_list *wal)
> {
> /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
> @@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915,
> }
>
> static void
> -g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - gen4_gt_workarounds_init(i915, wal);
> + gen4_gt_workarounds_init(gt, wal);
>
> /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
> wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
> }
>
> static void
> -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - g4x_gt_workarounds_init(i915, wal);
> + g4x_gt_workarounds_init(gt, wal);
>
> wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
> }
>
> static void
> -snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> }
>
> static void
> -ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
> wa_masked_dis(wal,
> @@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915,
> struct i915_wa_list *wal)
> }
>
> static void
> -vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list
> *wal)
> +vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> /* WaForceL3Serializa
Re: [Intel-gfx] [PATCH v10 09/17] drm/i915/pxp: Implement PXP irq handler
On Fri, Sep 17, 2021 at 09:20:00PM -0700, Alan Previn wrote:
> From: "Huang, Sean Z"
>
> The HW will generate a teardown interrupt when session termination is
> required, which requires i915 to submit a terminating batch. Once the HW
> is done with the termination it will generate another interrupt, at
> which point it is safe to re-create the session.
>
> Since the termination and re-creation flow is something we want to
> trigger from the driver as well, use a common work function that can be
> called both from the irq handler and from the driver set-up flows, which
> has the addded benefit of allowing us to skip any extra locks because
> the work itself serializes the operations.
>
> v2: use struct completion instead of bool (Chris)
> v3: drop locks, clean up functions and improve comments (Chris),
> move to common work function.
> v4: improve comments, simplify wait logic (Rodrigo)
> v5: unconditionally set interrupts, rename state_attacked var (Rodrigo)
>
> Signed-off-by: Alan Previn
> Signed-off-by: Huang, Sean Z
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Rodrigo Vivi
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 66 ++--
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 100 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 32 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 54 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 5 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 8 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 18
> 11 files changed, 284 insertions(+), 16 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 86ea9c98e815..892e17549314 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -284,6 +284,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_cmd.o \
> + pxp/intel_pxp_irq.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index b2de83be4d97..699a74582d32 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_lrc_reg.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp_irq.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8
> instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(>->pxp, iir);
> +
> WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> instance, iir);
> }
> @@ -196,6 +200,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
> intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
> +
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
> + intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
> }
>
> void gen11_gt_irq_postinstall(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..84bc884bd474 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8117,6 +8117,7 @@ enum {
> /* irq instances for OTHER_CLASS */
> #define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> +#define OTHER_KCR_INSTANCE 4
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 8a4755b235ad..584c998f79be 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -2,7 +2,9 @@
> /*
> * Copyright(c) 2020 Intel Corporation.
> */
> +#include
> #include "intel_pxp.h"
> +#includ
Re: [Intel-gfx] [PATCH v10 10/17] drm/i915/pxp: interfaces for using protected objects
On Fri, Sep 17, 2021 at 09:20:01PM -0700, Alan Previn wrote:
> From: Daniele Ceraolo Spurio
>
> This api allow user mode to create protected buffers and to mark
> contexts as making use of such objects. Only when using contexts
> marked in such a way is the execution guaranteed to work as expected.
>
> Contexts can only be marked as using protected content at creation time
> (i.e. the parameter is immutable) and they must be both bannable and not
> recoverable. Given that the protected session gets invalidated on
> suspend, contexts created this way hold a runtime pm wakeref until
> they're either destroyed or invalidated.
>
> All protected objects and contexts will be considered invalid when the
> PXP session is destroyed and all new submissions using them will be
> rejected. All intel contexts within the invalidated gem contexts will be
> marked banned. Userspace can detect that an invalidation has occurred via
> the RESET_STATS ioctl, where we report it the same way as a ban due to a
> hang.
>
> v5: squash patches, rebase on proto_ctx, update kerneldoc
>
> v6: rebase on obj create_ext changes
>
> v7: Use session counter to check if an object it valid, hold wakeref in
> context, don't add a new flag to RESET_STATS (Daniel)
>
> v8: don't increase guilty count for contexts banned during pxp
> invalidation (Rodrigo)
>
> v9: better comments, avoid wakeref put race between pxp_inval and
> context_close, add usage examples (Rodrigo)
can you please add the v10 change explanation here instead of only
in the cover letter? (apply this comment to all the modified patches)
>
> Signed-off-by: Alan Previn
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Bommu Krishnaiah
> Cc: Rodrigo Vivi
> Cc: Chris Wilson
> Cc: Lionel Landwerlin
> Cc: Jason Ekstrand
> Cc: Daniel Vetter
> Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 95 +++---
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 28 ++
> drivers/gpu/drm/i915/gem/i915_gem_create.c| 72 ++
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 18
> drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 +
> drivers/gpu/drm/i915/gem/i915_gem_object.h| 6 ++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 8 ++
> .../gpu/drm/i915/gem/selftests/mock_context.c | 4 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 78 +++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 12 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 6 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h| 9 ++
> include/uapi/drm/i915_drm.h | 96 ++-
> 14 files changed, 404 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c2ab0e22db0a..4ef643e20849 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -77,6 +77,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_gem_context.h"
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
> @@ -186,10 +188,13 @@ static int validate_priority(struct drm_i915_private
> *i915,
> return 0;
> }
>
> -static void proto_context_close(struct i915_gem_proto_context *pc)
> +static void proto_context_close(struct drm_i915_private *i915,
> + struct i915_gem_proto_context *pc)
> {
> int i;
>
> + if (pc->pxp_wakeref)
> + intel_runtime_pm_put(&i915->runtime_pm, pc->pxp_wakeref);
> if (pc->vm)
> i915_vm_put(pc->vm);
> if (pc->user_engines) {
> @@ -241,6 +246,33 @@ static int proto_context_set_persistence(struct
> drm_i915_private *i915,
> return 0;
> }
>
> +static int proto_context_set_protected(struct drm_i915_private *i915,
> +struct i915_gem_proto_context *pc,
> +bool protected)
> +{
> + int ret = 0;
> +
> + if (!protected) {
> + pc->uses_protected_content = false;
v10:
Reviewed-by: Rodrigo Vivi
> + } else if (!intel_pxp_is_enabled(&i915->gt.pxp)) {
> + ret = -ENODEV;
> + } else if ((pc->user_flags & BIT(UCONTEXT_RECOVERABLE)) ||
> +!(pc->user_flags & BIT(UCONTEXT_BANNABLE))) {
> + ret = -EPERM;
> + } else {
> + pc
Re: [Intel-gfx] [PATCH v10 09/17] drm/i915/pxp: Implement PXP irq handler
On Mon, Sep 20, 2021 at 04:18:10PM +, Teres Alexis, Alan Previn wrote:
>
> On Mon, 2021-09-20 at 12:04 -0400, Rodrigo Vivi wrote:
> > On Fri, Sep 17, 2021 at 09:20:00PM -0700, Alan Previn wrote:
> > > From: "Huang, Sean Z"
> > >
> > > The HW will generate a teardown interrupt when session termination is
> > > required, which requires i915 to submit a terminating batch. Once the HW
> > > is done with the termination it will generate another interrupt, at
> > > which point it is safe to re-create the session.
> > >
> > > Since the termination and re-creation flow is something we want to
> > > trigger from the driver as well, use a common work function that can be
> > > called both from the irq handler and from the driver set-up flows, which
> > > has the addded benefit of allowing us to skip any extra locks because
> > > the work itself serializes the operations.
> > >
> > > v2: use struct completion instead of bool (Chris)
> > > v3: drop locks, clean up functions and improve comments (Chris),
> > > move to common work function.
> > > v4: improve comments, simplify wait logic (Rodrigo)
> > > v5: unconditionally set interrupts, rename state_attacked var (Rodrigo)
> > >
> > > Signed-off-by: Alan Previn
> > > Signed-off-by: Huang, Sean Z
> > > Signed-off-by: Daniele Ceraolo Spurio
> > > Cc: Chris Wilson
> > > Cc: Rodrigo Vivi
> > > Reviewed-by: Rodrigo Vivi
> > > ---
> > > +#include
> > > +#include "intel_pxp.h"
> > > +#include "intel_pxp_irq.h"
> > > +#include "intel_pxp_session.h"
> > > +#include "gt/intel_gt_irq.h"
> > > +#include "gt/intel_gt_types.h"
> > > +#include "i915_irq.h"
> > > +#include "i915_reg.h"
> > > +
> > > +/**
> > > + * intel_pxp_irq_handler - Handles PXP interrupts.
> > > + * @pxp: pointer to pxp struct
> > > + * @iir: interrupt vector
> > > + */
> > > +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> > > +{
> > > + struct intel_gt *gt = pxp_to_gt(pxp);
> >
> > this compiles, but I don't see how this can work.
> >
> > shouldn't we use the container_of here directly instead of trying
> > to use something that is not properly defined?
> >
> Its now a function that's abstracted in .c file and prototype defined in the
> intel_pxp.h. Unless i
> misunderstood something, i thought this was one of the options discussed in
> last rev - i can change it
> again to use the container_of directly in all the instances if you like. side
> note: inline was still
> defined but only for the CONFIG_PXP==off case that doesn't require the
> additional header inclusions.
Oh, indeed Sorry
If this was not working we would get an "Undefined referrence" in the face.
Reviewed-by: Rodrigo Vivi
for this v as well.
>
> > > +
Re: [Intel-gfx] [PATCH 3/3] drm/i915: remove some debug-only registers from MCHBAR
On Tue, Jul 06, 2021 at 04:44:30PM -0700, Lucas De Marchi wrote:
> On Thu, Nov 05, 2020 at 10:02:27AM +0200, Joonas Lahtinen wrote:
> > Quoting Lucas De Marchi (2020-11-05 03:04:22)
> > > On Wed, Nov 04, 2020 at 11:55:15AM +0200, Joonas Lahtinen wrote:
> > > >Quoting Lucas De Marchi (2020-10-27 06:46:18)
> > > >> GT_PERF_STATUS and RP_STATE_LIMITS were added a long time ago in
> > > >> commit 3b8d8d91d51c ("drm/i915: dynamic render p-state support for
> > > >> Sandy
> > > >> Bridge"). Other than printing their values in debugfs we don't do
> > > >> anything with them. There's not much useful information in them. These
> > > >> registers may change location in future platforms, but instead of
> > > >> adding
> > > >> new locations, it's simpler to just remove them.
> > > >
> > > >This code seems to have been updated for Gen9LP, so that would indicate
> > > >the debugging information is useful, right? The value is even decoded,
> > > >not
> > > >simply dumped as most registers. So I would be hesitant to drop it for
> > > >not being useful.
> > >
> > > but just updating the register in itself for a new gen doesn't mean it's
> > > actually useful... the commit message where this happened is pretty
> > > vague: 350405623ff3 ("drm/i915: Update rps frequencies for BXT")
> > >
> > > My first reaction would be to do the same if the register had moved or
> > > if it ceased to exist in a new platform. Talking with Matt Roper some
> > > time ago we arrived to the conclusion that just printing these values is
> > > not giving us much benefit and it could very well be accomplished by
> > > intel_reg.
> > >
> > > So answering the question: is it really useful as is? IMO, no.
> >
> > A quick discussion on #intel-gfx seems to indicate it was used for
> > bug triaging in the past year. So that would indicate it is still
> > useful to include.
>
> getting back to this as we are trying to upstream XeHP-SDV that doesn't
> have access to the MCHBAR. So do you think we should just make it
> conditional instead of removing?
Yes, please let's make this conditional.
>
> I'm still on the side that this additional code doesn't bring much value
> and could be replaced by intel-reg.
In general I'd agree. However:
1. Sometimes it is very hard to find out what registers and bits have
some useful information.
2. If it is hard to remove sometimes it is harder to add some information
like this.
3. I was not part of the IRC chat that Joonas mentioned, but apparently
this data was useful in the past for some cases.
Thanks,
Rodrigo.
>
> >
> > So let's not remove it.
> >
> > > >The second question is why we have a huge block of 1-to-1 duplicated
> > > >code in there. Has there been an incorrect merge or some transition has
> > > >been left mid-way?
> > >
> > > not a bad merge, no. It seems to be to preserve the previous file
> > > location since now it moved to be inside a gt dir. Long term I think
> > > this is bad both because of the code duplication and because it's easy
> > > to update one and forget the other.
> >
> > I started a discussion in the thread of the original patch which called
> > to move code but left the old code in place too, effectively copying it.
> >
> > When this path was written and such code duplication noticed, would have
> > been good to highlight or address the code duplication.
>
> yes, but it doesn't mean there will be an action regarding that, as can
> be noticed since that duplication is still there today and this patch
> applies cleanly :-/... and they had slightly different changes according
> to
>
> git log -L:frequency_show:drivers/gpu/drm/i915/gt/debugfs_gt_pm.c \
> -L:i915_frequency_info:drivers/gpu/drm/i915/i915_debugfs.c
>
>
> Lucas De Marchi
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-intel-next
g()
drm/i915/hdcp: read RxInfo once when reading
RepeaterAuth_Send_ReceiverID_List
drm/i915/hdcp: reuse rx_info for mst stream type1 capability check
Kai-Heng Feng (2):
drm/i915/dp: Use max params for panels < eDP 1.4
drm/i915/audio: Use BIOS provided value for RKL HDA link
Lee Shawn C (6):
drm/i915/dp: return proper DPRX link training result
drm/i915/dsi: wait for header and payload credit available
drm/i915/dsi: refine send MIPI DCS command sequence
drm/i915: Get proper min cdclk if vDSC enabled
drm/i915/dsi: Retrieve max brightness level from VBT
drm/i915/dsi: Read/write proper brightness value via MIPI DCS command
Lukasz Majczak (1):
drm/i915/bdb: Fix version check
Maarten Lankhorst (1):
drm/i915: Add ww context to intel_dpt_pin, v2.
Matt Atwood (1):
drm/i915/dp: Fix eDP max rate for display 11+
Matt Roper (3):
drm/i915: Only access SFC_DONE when media domain is not fused off
drm/i915/adl_p: Also disable underrun recovery with MSO
drm/i915/dg2: Memory latency values from pcode must be doubled
Radhakrishna Sripada (1):
drm/i915: Update memory bandwidth parameters
Rodrigo Vivi (2):
Merge tag 'drm-misc-intel-oob-hotplug-v1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hansg/linux into drm-intel-next
Merge drm/drm-next into drm-intel-next
Swati Sharma (1):
drm/i915/dp: Drop redundant debug print
Tejas Upadhyay (3):
drm/i915/adl_s: Update ADL-S PCI IDs
drm/i915/display: Add HDR mode helper function
drm/i915/gen11: Disable cursor clock gating in HDR mode
Vandita Kulkarni (4):
drm/i915/display: Update small joiner ram size
drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband
drm/i915/dsi/xelpd: Enable mipi dsi support.
drm/i915/display: Fix the dsc check while selecting min_cdclk
Ville Syrjälä (63):
drm/i915/fbc: Rewrite the FBC tiling check a bit
drm/i915/fbc: Extract intel_fbc_update()
drm/i915/fbc: Move the "recompress on activate" to a central place
drm/i915/fbc: Polish the skl+ FBC stride override handling
drm/i915: Silence __iomem sparse warn
drm/i915: Set output_types to EDP for vlv/chv DPLL forcing
drm/i915: Clean up gen2 DPLL readout
drm/i915: Extract ilk_update_pll_dividers()
drm/i915: Constify struct dpll all over
drm/i915: Clean dpll calling convention
drm/i915: Clean up variable names in old dpll functions
drm/i915: Remove the 'reg' local variable
drm/i915: Program DPLL P1 dividers consistently
drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()
drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well
drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()
drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()
drm/i915: Nuke intel_prepare_shared_dpll()
drm/i915: Extract intel_dp_need_bigjoiner()
drm/i915: Flatten hsw_crtc_compute_clock()
drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONF
drm/i915: Introduce with_intel_display_power_if_enabled()
drm/i915: Adjust intel_dsc_power_domain() calling convention
drm/i915: Extract hsw_panel_transcoders()
drm/i915: s/crtc_state/new_crtc_state/ etc.
drm/i915: Use u8 consistently for active_planes bitmask
drm/i915: Fix g4x cxsr enable condition
drm/i915: Apply WaUse32BppForSRWM to elk as well as ctg
drm/i915: Fix HPLL watermark readout for g4x
drm/i915/fbc: Rework cfb stride/size calculations
drm/i915/fbc: Align FBC segments to 512B on glk+
drm/i915/fbc: Implement Wa_16011863758 for icl+
drm/i915/fbc: Allow higher compression limits on FBC1
drm/i915: Extract intel_panel_mode_valid()
drm/i915: Use intel_panel_mode_valid() for DSI/LVDS/(s)DVO
drm/i915: Reject modes that don't match fixed_mode vrefresh
drm/i915: Introduce intel_panel_compute_config()
drm/i915: Reject user modes that don't match fixed mode's refresh rate
drm/i915: Drop pointless fixed_mode checks from dsi code
drm/i915: Enable TPS3/4 on all platforms that support them
drm/i915/fbc: Allow FBC with Yf tiling
drm/i915: Pimp HSW+ transcoder state readout
drm/i915: Configure TRANSCONF just the once with bigjoiner
drm/i915: Clear leftover DP vswing/preemphasis values before modeset
drm/i915: Call intel_ddi_init_dp_buf_reg() earlier
drm/i915: Remove DP_PORT_EN stuff from link training code
drm/i915: Nuke local copies/pointers of intel_dp->DP
drm/i915: s/ddi_translations/trans/
drm/i915: Use standard form -EDEADLK check
drm/i915: Adjust intel_crtc_compute_config() debug message
drm/i915: Move WaPruneModeWithIncorrectHsyncOffset into intel_mode_valid()
drm/i915: Stop force enabling pipe bottom color ga
Re: [Intel-gfx] [PATCH] drm/i915: Correct the docs for intel_engine_cmd_parser
On Tue, Jul 20, 2021 at 01:21:08PM -0500, Jason Ekstrand wrote:
> In c9d9fdbc108a ("drm/i915: Revert "drm/i915/gem: Asynchronous
> cmdparser""), the parameters to intel_engine_cmd_parser() were altered
> without updating the docs, causing Fi.CI.DOCS to start failing.
>
> Signed-off-by: Jason Ekstrand
> ---
> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 322f4d5955a4f..e0403ce9ce692 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1416,9 +1416,7 @@ static unsigned long *alloc_whitelist(u32 batch_length)
> * @batch_offset: byte offset in the batch at which execution starts
> * @batch_length: length of the commands in batch_obj
> * @shadow: validated copy of the batch buffer in question
> - * @jump_whitelist: buffer preallocated with
> intel_engine_cmd_parser_alloc_jump_whitelist()
> - * @shadow_map: mapping to @shadow vma
> - * @batch_map: mapping to @batch vma
> + * @trampoline: true if we need to trampoline into privileged execution
I was wondering if we should also return the original text, but this one
here looks better.
Reviewed-by: Rodrigo Vivi
> *
> * Parses the specified batch buffer looking for privilege violations as
> * described in the overview.
> --
> 2.31.1
>
> ___
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Re: [Intel-gfx] [PATCH] drm/i915: Correct the docs for intel_engine_cmd_parser
On Tue, Jul 20, 2021 at 04:25:21PM -0400, Rodrigo Vivi wrote:
> On Tue, Jul 20, 2021 at 01:21:08PM -0500, Jason Ekstrand wrote:
> > In c9d9fdbc108a ("drm/i915: Revert "drm/i915/gem: Asynchronous
> > cmdparser""), the parameters to intel_engine_cmd_parser() were altered
> > without updating the docs, causing Fi.CI.DOCS to start failing.
> >
> > Signed-off-by: Jason Ekstrand
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index 322f4d5955a4f..e0403ce9ce692 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -1416,9 +1416,7 @@ static unsigned long *alloc_whitelist(u32
> > batch_length)
> > * @batch_offset: byte offset in the batch at which execution starts
> > * @batch_length: length of the commands in batch_obj
> > * @shadow: validated copy of the batch buffer in question
> > - * @jump_whitelist: buffer preallocated with
> > intel_engine_cmd_parser_alloc_jump_whitelist()
> > - * @shadow_map: mapping to @shadow vma
> > - * @batch_map: mapping to @batch vma
> > + * @trampoline: true if we need to trampoline into privileged execution
>
> I was wondering if we should also return the original text, but this one
> here looks better.
>
>
> Reviewed-by: Rodrigo Vivi
btw, while on it, I wouldn't mind if you squash some english fixes to
the trampoline documentation block inside this function ;)
>
>
> > *
> > * Parses the specified batch buffer looking for privilege violations as
> > * described in the overview.
> > --
> > 2.31.1
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH] drm/i915: Correct the docs for intel_engine_cmd_parser
On Tue, Jul 20, 2021 at 04:04:59PM -0500, Jason Ekstrand wrote:
> On Tue, Jul 20, 2021 at 3:26 PM Rodrigo Vivi wrote:
> >
> > On Tue, Jul 20, 2021 at 04:25:21PM -0400, Rodrigo Vivi wrote:
> > > On Tue, Jul 20, 2021 at 01:21:08PM -0500, Jason Ekstrand wrote:
> > > > In c9d9fdbc108a ("drm/i915: Revert "drm/i915/gem: Asynchronous
> > > > cmdparser""), the parameters to intel_engine_cmd_parser() were altered
> > > > without updating the docs, causing Fi.CI.DOCS to start failing.
> > > >
> > > > Signed-off-by: Jason Ekstrand
> > > > ---
> > > > drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +---
> > > > 1 file changed, 1 insertion(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > index 322f4d5955a4f..e0403ce9ce692 100644
> > > > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > @@ -1416,9 +1416,7 @@ static unsigned long *alloc_whitelist(u32
> > > > batch_length)
> > > > * @batch_offset: byte offset in the batch at which execution starts
> > > > * @batch_length: length of the commands in batch_obj
> > > > * @shadow: validated copy of the batch buffer in question
> > > > - * @jump_whitelist: buffer preallocated with
> > > > intel_engine_cmd_parser_alloc_jump_whitelist()
> > > > - * @shadow_map: mapping to @shadow vma
> > > > - * @batch_map: mapping to @batch vma
> > > > + * @trampoline: true if we need to trampoline into privileged execution
> > >
> > > I was wondering if we should also return the original text, but this one
> > > here looks better.
> > >
> > >
> > > Reviewed-by: Rodrigo Vivi
> >
> > btw, while on it, I wouldn't mind if you squash some english fixes to
> > the trampoline documentation block inside this function ;)
>
> I don't mind at all but I'm not sure what changes you're suggesting.
nevermind...
It was just my broke english that didn't know the inversion on the "only if"
>
> > >
> > >
> > > > *
> > > > * Parses the specified batch buffer looking for privilege violations
> > > > as
> > > > * described in the overview.
> > > > --
> > > > 2.31.1
> > > >
> > > > ___
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Wed, Jul 21, 2021 at 01:10:49PM +0200, Christoph Hellwig wrote: > Hi all, > > I'm trying to test some changes for the gvt code, but even with a baseline > 5.14-rc2 host and guest the 915 driver does not seem overly happy: Is this a regression over -rc1 or over 5.13? Bisect possible? Could you please file a bug to our gitlab issues tracker: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs Thanks, Rodrigo. > > [5.693099] i915 :00:04.0: [drm] Virtual GPU for Intel GVT-g detected. > [5.694841] i915 :00:04.0: [drm] VT-d active for gfx access > [5.696411] i915 :00:04.0: [drm] iGVT-g active, disabling use of > stolen memory > [5.711317] i915 :00:04.0: BAR 6: can't assign [??? 0x flags > 0x2000] (bogus alignm) > [5.712847] i915 :00:04.0: [drm] Failed to find VBIOS tables (VBT) > [5.714343] i915 :00:04.0: vgaarb: changed VGA decodes: > olddecodes=io+mem,decodes=none:owns=iom > [5.716466] i915 :00:04.0: Direct firmware load for > i915/kbl_dmc_ver1_04.bin failed with error2 > [5.718021] i915 :00:04.0: [drm] Failed to load DMC firmware > i915/kbl_dmc_ver1_04.bin. Disabli. > [5.719914] i915 :00:04.0: [drm] DMC firmware homepage: > https://git.kernel.org/pub/scm/linux/k5 > [5.733269] i915 :00:04.0: [drm] failed to retrieve link info, > disabling eDP > [5.735841] i915 :00:04.0: [drm] *ERROR* crtc 51: Can't calculate > constants, dotclock = 0! > [5.737354] [ cut here ] > [5.738141] i915 :00:04.0: > drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) > [5.738165] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_vblank.c:728 > drm_crtc_vblank_helper_get_0 > [5.738745] Modules linked in: > [5.738745] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc2+ #22 > [5.738745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS > 1.14.0-2 04/01/2014 > [5.738745] RIP: > 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x335/0x350 > [5.738745] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 34 10 26 00 48 c7 > c1 20 54 0d 83 4c 89 ea0 > [5.738745] RSP: :c9013a90 EFLAGS: 00010086 > [5.738745] RAX: RBX: 81c3c5b0 RCX: > > [5.738745] RDX: 0003 RSI: fffe RDI: > > [5.738745] RBP: c9013b00 R08: 83bb3e28 R09: > 0003 > [5.738745] R10: 834b3e40 R11: 3fff R12: > > [5.738745] R13: 888100e982f0 R14: 8881053f0340 R15: > 888105592178 > [5.738745] FS: () GS:88813bc0() > knlGS: > [5.738745] CS: 0010 DS: ES: CR0: 80050033 > [5.738745] CR2: CR3: 03462000 CR4: > 06f0 > [5.738745] Call Trace: > [5.738745] drm_get_last_vbltimestamp+0xa5/0xb0 > [5.738745] drm_reset_vblank_timestamp+0x56/0xc0 > [5.738745] drm_crtc_vblank_on+0x81/0x140 > [5.738745] intel_crtc_vblank_on+0x2b/0xe0 > [5.738745] intel_modeset_setup_hw_state+0xa9c/0x1ab0 > [5.738745] ? ww_mutex_lock+0x2b/0x90 > [5.738745] intel_modeset_init_nogem+0x3c5/0x1310 > [5.738745] ? intel_irq_postinstall+0x1aa/0x520 > [5.738745] i915_driver_probe+0x695/0xd30 > [5.738745] ? _raw_spin_unlock_irqrestore+0x33/0x50 > [5.738745] pci_device_probe+0xcd/0x140 > [5.738745] really_probe.part.0+0x99/0x270 > [5.738745] __driver_probe_device+0x8b/0x120 > [5.738745] driver_probe_device+0x19/0x90 > [5.738745] __driver_attach+0x79/0x120 > [5.738745] ? __device_attach_driver+0x90/0x90 > [5.738745] bus_for_each_dev+0x78/0xc0 > [5.738745] bus_add_driver+0x109/0x1b0 > [5.738745] driver_register+0x86/0xd0 > [5.738745] ? ttm_init+0x18/0x18 > [5.738745] i915_init+0x58/0x72 > [5.738745] do_one_initcall+0x56/0x2e0 > [5.738745] ? rcu_read_lock_sched_held+0x3a/0x70 > [5.738745] kernel_init_freeable+0x186/0x1ce > [5.738745] ? rest_init+0x250/0x250 > [5.738745] kernel_init+0x11/0x110 > [5.738745] ret_from_fork+0x22/0x30 > [5.738745] irq event stamp: 8200428 > [5.738745] hardirqs last enabled at (8200427): [] > _raw_spin_unlock_irqrestore+0 > [5.738745] hardirqs last disabled at (8200428): [] > _raw_spin_lock_irq+0x41/0x50 > [5.738745] softirqs last enabled at (8199086): [] > irq_exit_rcu+0x108/0x140 > [5.738745] softirqs last disabled at (8199079): [] > irq_exit_rcu+0x108/0x140 > [5.738745] ---[ end trace e99e0812b8ee9c5d ]--- > [5.786472] i915 :00:04.0: [drm] VGT ballooning configuration: > [5.787531] i915 :00:04.0: [drm] Mappable graphic memory: base > 0x31c7000 size 65536KiB > [5.788865] i915 :00:04.0: [drm] Unmappable graphic memory: base > 0xe7ef8000 size 393216KiB > [5.790270] i915 :00:04.0: [drm] balloon
Re: [Intel-gfx] [PATCH] drm/i915: Correct the docs for intel_engine_cmd_parser
On Wed, Jul 21, 2021 at 10:25:27AM -0500, Jason Ekstrand wrote:
> Would you mind pushing? I still don't have those magic powers. :-)
>
> --Jason
>
> On Wed, Jul 21, 2021 at 5:05 AM Rodrigo Vivi wrote:
> >
> > On Tue, Jul 20, 2021 at 04:04:59PM -0500, Jason Ekstrand wrote:
> > > On Tue, Jul 20, 2021 at 3:26 PM Rodrigo Vivi
> > > wrote:
> > > >
> > > > On Tue, Jul 20, 2021 at 04:25:21PM -0400, Rodrigo Vivi wrote:
> > > > > On Tue, Jul 20, 2021 at 01:21:08PM -0500, Jason Ekstrand wrote:
> > > > > > In c9d9fdbc108a ("drm/i915: Revert "drm/i915/gem: Asynchronous
while pushing I noticed this hash was for the patch in the drm-intel-fixes
branch. I updated to the right one in drm-intel-gt-next.
Then I also added the Fixes tag and cherry-picked to drm-intel-fixes branch.
Everything pushed now.
Thanks for the patch,
Rodrigo.
> > > > > > cmdparser""), the parameters to intel_engine_cmd_parser() were
> > > > > > altered
> > > > > > without updating the docs, causing Fi.CI.DOCS to start failing.
> > > > > >
> > > > > > Signed-off-by: Jason Ekstrand
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +---
> > > > > > 1 file changed, 1 insertion(+), 3 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > > > b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > > > index 322f4d5955a4f..e0403ce9ce692 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > > > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > > > > > @@ -1416,9 +1416,7 @@ static unsigned long *alloc_whitelist(u32
> > > > > > batch_length)
> > > > > > * @batch_offset: byte offset in the batch at which execution
> > > > > > starts
> > > > > > * @batch_length: length of the commands in batch_obj
> > > > > > * @shadow: validated copy of the batch buffer in question
> > > > > > - * @jump_whitelist: buffer preallocated with
> > > > > > intel_engine_cmd_parser_alloc_jump_whitelist()
> > > > > > - * @shadow_map: mapping to @shadow vma
> > > > > > - * @batch_map: mapping to @batch vma
> > > > > > + * @trampoline: true if we need to trampoline into privileged
> > > > > > execution
> > > > >
> > > > > I was wondering if we should also return the original text, but this
> > > > > one
> > > > > here looks better.
> > > > >
> > > > >
> > > > > Reviewed-by: Rodrigo Vivi
> > > >
> > > > btw, while on it, I wouldn't mind if you squash some english fixes to
> > > > the trampoline documentation block inside this function ;)
> > >
> > > I don't mind at all but I'm not sure what changes you're suggesting.
> >
> > nevermind...
> > It was just my broke english that didn't know the inversion on the "only if"
> >
> >
> > >
> > > > >
> > > > >
> > > > > > *
> > > > > > * Parses the specified batch buffer looking for privilege
> > > > > > violations as
> > > > > > * described in the overview.
> > > > > > --
> > > > > > 2.31.1
> > > > > >
> > > > > > ___
> > > > > > Intel-gfx mailing list
> > > > > > Intel-gfx@lists.freedesktop.org
> > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] 5.14-rc2 warnings with kvmgvt
On Wed, Jul 21, 2021 at 09:40:03PM +0100, Christoph Hellwig wrote:
> On Wed, Jul 21, 2021 at 04:43:44PM +0100, Christoph Hellwig wrote:
> > > > I'm trying to test some changes for the gvt code, but even with a
> > > > baseline
> > > > 5.14-rc2 host and guest the 915 driver does not seem overly happy:
> > >
> > > Is this a regression over -rc1 or over 5.13?
> > > Bisect possible?
> >
> > This was introduced somewhere between 5.12 and 5.13, still bisecting.
> > Note that it only happens for "headless" setups. Once a display is
> > added on the qemu command line it goes away.
>
> The culprit is:
>
> commit f4eb6d4906669b4285c4f49c87814d4ce63c35bb
> Author: Jani Nikula
> Date: Wed Mar 17 18:36:45 2021 +0200
>
> drm/i915/bios: limit default outputs to ports A through F
>
could you please try this small patch?
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..8bbeb5978bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
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[Intel-gfx] [PATCH] drm/i915/bios: Fix ports mask
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found on headless
GVT configuration which bisect blamed commit 3ae04c0c7e63 ("drm/i915/bios:
limit default outputs to ports A through F")
Cc: Christoph Hellwig
Fixes: 3ae04c0c7e63 ("drm/i915/bios: limit default outputs to ports A through
F")
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..8bbeb5978bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | \
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
return;
--
2.31.1
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[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes drm-intel-fixes-2021-07-22: Couple reverts from Jason getting rid of asynchronous command parsing and fence error propagation and a GVT fix of shadow ppgtt invalidation with proper D3 state tracking from Colin. Thanks, Rodrigo. The following changes since commit 2734d6c1b1a089fb593ef6a23d4b70903526fe0c: Linux 5.14-rc2 (2021-07-18 14:13:49 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-07-22 for you to fetch changes up to 6e0b6528d783b2b87bd9e1bea97cf4dac87540d7: drm/i915: Correct the docs for intel_engine_cmd_parser (2021-07-21 11:49:36 -0400) Couple reverts from Jason getting rid of asynchronous command parsing and fence error propagation and a GVT fix of shadow ppgtt invalidation with proper D3 state tracking from Colin. Colin Xu (1): drm/i915/gvt: Clear d3_entered on elsp cmd submission. Jason Ekstrand (3): drm/i915: Revert "drm/i915/gem: Asynchronous cmdparser" Revert "drm/i915: Propagate errors on awaiting already signaled fences" drm/i915: Correct the docs for intel_engine_cmd_parser Rodrigo Vivi (1): Merge tag 'gvt-fixes-2021-07-15' of https://github.com/intel/gvt-linux into drm-intel-fixes drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 227 ++--- .../drm/i915/gem/selftests/i915_gem_execbuffer.c | 4 + drivers/gpu/drm/i915/gvt/handlers.c| 15 ++ drivers/gpu/drm/i915/i915_cmd_parser.c | 136 ++-- drivers/gpu/drm/i915/i915_drv.h| 7 +- drivers/gpu/drm/i915/i915_request.c| 8 +- 6 files changed, 109 insertions(+), 288 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI] drm/i915/bios: Fix ports mask
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found on headless
GVT configuration which bisect blamed commit 3ae04c0c7e63 ("drm/i915/bios:
limit default outputs to ports A through F")
v2: Avoid unnecessary line continuations as pointed by CI and Christoph
Cc: Christoph Hellwig
Fixes: 3ae04c0c7e63 ("drm/i915/bios: limit default outputs to ports A through
F")
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Tested-by: Christoph Hellwig
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..aa667fa71158 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) |
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
return;
--
2.31.1
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Re: [Intel-gfx] [PATCH] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
On Thu, Jul 22, 2021 at 10:15:35AM -0700, Lucas De Marchi wrote:
> Commit 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt
> in intel_bios.c") moved the workaround for broken or missing VBT to
> intel_bios.c. However is_port_valid() only protects the handling of
> different skus of the same display version. Since in
> intel_setup_outputs() we share the code path with version 9, this would
> also create port F for SKL/KBL, which does not exist.
>
> Missing VBT can be reproduced when starting a headless QEMU with no
> opregion available.
>
> Avoid the issue by splitting versions 9 and 10 in intel_setup_outputs(),
> which also makes it more clear what code path it's taking for each
> version.
>
> Fixes: 5a9d38b20a5a ("drm/i915/display: hide workaround for broken vbt in
> intel_bios.c")
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Reported-by: Christoph Hellwig
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c274bfb8e549..44cad63e20fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11371,6 +11371,13 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_E);
> intel_ddi_init(dev_priv, PORT_F);
> icl_dsi_init(dev_priv);
> + } else if (DISPLAY_VER(dev_priv) == 10) {
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + intel_ddi_init(dev_priv, PORT_C);
> + intel_ddi_init(dev_priv, PORT_D);
> + intel_ddi_init(dev_priv, PORT_E);
> + intel_ddi_init(dev_priv, PORT_F);
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> @@ -11382,7 +11389,6 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_C);
> intel_ddi_init(dev_priv, PORT_D);
> intel_ddi_init(dev_priv, PORT_E);
> - intel_ddi_init(dev_priv, PORT_F);
> } else if (HAS_DDI(dev_priv)) {
> u32 found;
>
> --
> 2.31.1
>
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/bios: Fix ports mask (rev2)
On Thu, Jul 22, 2021 at 03:09:13PM -, Patchwork wrote:
>Patch Details
>
>Series: drm/i915/bios: Fix ports mask (rev2)
>URL: [1]https://patchwork.freedesktop.org/series/92850/
>State: failure
>Details:
>[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/index.html
>
>CI Bug Log - changes from CI_DRM_10371 -> Patchwork_20680
>
> Summary
>
>FAILURE
>
>Serious unknown changes coming with Patchwork_20680 absolutely need to
>be
>verified manually.
>
>If you think the reported changes have nothing to do with the changes
>introduced in Patchwork_20680, please notify your bug team to allow
>them
>to document this new failure mode, which will reduce false positives in
>CI.
>
>External URL:
>https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/index.html
>
> Possible new issues
>
>Here are the unknown changes that may have been introduced in
>Patchwork_20680:
>
> IGT changes
>
> Possible regressions
>
> * igt@i915_pm_rpm@basic-rte:
> + fi-bdw-5557u: NOTRUN -> [3]FAIL
Apparently after we moved to -rc2 this test is failing in all platforms.
Unfortunately I couldn't bisect because on the machines I got access it
was failing regardless the kernel that I was using :/
>
> Known issues
>
>Here are the changes found in Patchwork_20680 that come from known
>issues:
>
> IGT changes
>
> Issues hit
>
> * igt@amdgpu/amd_basic@query-info:
> + fi-bsw-kefka: NOTRUN -> [4]SKIP ([5]fdo#109271) +17 similar
> issues
> * igt@amdgpu/amd_basic@semaphore:
> + fi-bdw-5557u: NOTRUN -> [6]SKIP ([7]fdo#109271) +25 similar
> issues
> * igt@core_hotunplug@unbind-rebind:
> + fi-bdw-5557u: NOTRUN -> [8]WARN ([9]i915#3718)
>
> Possible fixes
>
> * igt@gem_exec_suspend@basic-s3:
> + {fi-tgl-1115g4}: [10]FAIL ([11]i915#1888) -> [12]PASS
> * igt@i915_selftest@live@execlists:
> + fi-bsw-kefka: [13]INCOMPLETE ([14]i915#2782 / [15]i915#2940)
> -> [16]PASS
> * igt@kms_chamelium@dp-crc-fast:
> + fi-kbl-7500u: [17]FAIL ([18]i915#1372) -> [19]PASS
>
>{name}: This element is suppressed. This means it is ignored when
>computing
>the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Participating hosts (38 -> 35)
>
>Missing (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
>
> Build changes
>
> * Linux: CI_DRM_10371 -> Patchwork_20680
>
>CI-20190529: 20190529
>CI_DRM_10371: 8e68c13425e29c96ef94c9dd3583159000c61380 @
>git://anongit.freedesktop.org/gfx-ci/linux
>IGT_6147: f3994c2cd99a1acfe991a8cc838a387dcb36598a @
>https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
>Patchwork_20680: e1fd6ca0eb59bf30864ec455071ae7082201381b @
>git://anongit.freedesktop.org/gfx-ci/linux
>
>== Linux commits ==
>
>e1fd6ca0eb59 drm/i915/bios: Fix ports mask
>
> References
>
>1. https://patchwork.freedesktop.org/series/92850/
>2. https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/index.html
>3.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html
>4.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
>5. https://bugs.freedesktop.org/show_bug.cgi?id=109271
>6.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html
>7. https://bugs.freedesktop.org/show_bug.cgi?id=109271
>8.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html
>9. https://gitlab.freedesktop.org/drm/intel/issues/3718
> 10.
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10371/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
> 11. https://gitlab.freedesktop.org/drm/intel/issues/1888
> 12.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
> 13.
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10371/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
> 14. https://gitlab.freedesktop.org/drm/intel/issues/2782
> 15. https://gitlab.freedesktop.org/drm/intel/issues/2940
> 16.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
> 17.
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10371/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
> 18. https://gitlab.freedesktop.org/drm/intel/issues/1372
> 19.
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20680/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
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[Intel-gfx] [CI] drm/i915/bios: Fix ports mask
PORT_A to PORT_F are regular integers defined in the enum port,
while for_each_port_masked requires a bit mask for the ports.
Current given mask: 0b111
Desired mask: 0b11
I noticed this while Christoph was reporting a bug found on headless
GVT configuration which bisect blamed commit 3ae04c0c7e63 ("drm/i915/bios:
limit default outputs to ports A through F")
v2: Avoid unnecessary line continuations as pointed by CI and Christoph
Cc: Christoph Hellwig
Fixes: 3ae04c0c7e63 ("drm/i915/bios: limit default outputs to ports A through
F")
Cc: Lucas De Marchi
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
Reviewed-by: José Roberto de Souza
Reviewed-by: Lucas De Marchi
Tested-by: Christoph Hellwig
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 5b6922e28ef2..aa667fa71158 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2166,7 +2166,8 @@ static void
init_vbt_missing_defaults(struct drm_i915_private *i915)
{
enum port port;
- int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;
+ int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) |
+ BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);
if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))
return;
--
2.31.1
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Re: [Intel-gfx] [PATCH 28/30] drm/i915: rename/remove CNL registers
On Fri, Jul 23, 2021 at 05:11:12PM -0700, Lucas De Marchi wrote: > Remove registers that are not used anymore due to CNL removal and rename > those that are. > > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 192 ++- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > 2 files changed, 48 insertions(+), 146 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8782d1723254..925cbdb53712 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) > > /* > - * CNL/ICL Port/COMBO-PHY Registers > + * ICL Port/COMBO-PHY Registers > */ > #define _ICL_COMBOPHY_A 0x162000 > #define _ICL_COMBOPHY_B 0x6C000 > @@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > _RKL_COMBOPHY_D, \ > _ADL_COMBOPHY_E) > > -/* CNL/ICL Port CL_DW registers */ > +/* ICL Port CL_DW registers */ > #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ >4 * (dw)) > > -#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) > #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) > #define CL_POWER_DOWN_ENABLE (1 << 4) > #define SUS_CLOCK_CONFIG (3 << 0) > @@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define ICL_PORT_CL_DW12(phy)_MMIO(_ICL_PORT_CL_DW(12, phy)) > #define ICL_LANE_ENABLE_AUX(1 << 0) > > -/* CNL/ICL Port COMP_DW registers */ > +/* ICL Port COMP_DW registers */ > #define _ICL_PORT_COMP 0x100 > #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ >_ICL_PORT_COMP + 4 * (dw)) > > -#define CNL_PORT_COMP_DW0_MMIO(0x162100) > #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) > #define COMP_INIT (1 << 31) > > -#define CNL_PORT_COMP_DW1_MMIO(0x162104) > #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) > > -#define CNL_PORT_COMP_DW3_MMIO(0x16210c) > #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) > #define PROCESS_INFO_DOT_0 (0 << 26) > #define PROCESS_INFO_DOT_1 (1 << 26) > @@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) > #define IREFGEN(1 << 24) > > -#define CNL_PORT_COMP_DW9_MMIO(0x162124) > #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) > > -#define CNL_PORT_COMP_DW10 _MMIO(0x162128) > #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, > phy)) > > -/* CNL/ICL Port PCS registers */ > -#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 > -#define _CNL_PORT_PCS_DW1_GRP_B 0x162384 > -#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 > -#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 > -#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 > -#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 > -#define _CNL_PORT_PCS_DW1_LN0_B 0x162604 > -#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 > -#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 > -#define _CNL_PORT_PCS_DW1_LN0_F 0x162804 > -#define CNL_PORT_PCS_DW1_GRP(phy)_MMIO(_PICK(phy, \ > - _CNL_PORT_PCS_DW1_GRP_AE, \ > - _CNL_PORT_PCS_DW1_GRP_B, \ > - _CNL_PORT_PCS_DW1_GRP_C, \ > - _CNL_PORT_PCS_DW1_GRP_D, \ > - _CNL_PORT_PCS_DW1_GRP_AE, \ > - _CNL_PORT_PCS_DW1_GRP_F)) > -#define CNL_PORT_PCS_DW1_LN0(phy)_MMIO(_PICK(phy, \ > - _CNL_PORT_PCS_DW1_LN0_AE, \ > - _CNL_PORT_PCS_DW1_LN0_B, \ > - _CNL_PORT_PCS_DW1_LN0_C, \ > - _CNL_PORT_PCS_DW1_LN0_D, \ >
Re: [Intel-gfx] [PATCH 27/30] drm/i915: remove GRAPHICS_VER == 10
On Fri, Jul 23, 2021 at 05:11:11PM -0700, Lucas De Marchi wrote:
> Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
> {==,>=} 11. With the removal of CNL, there is no platform with graphics
> version equals 10.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 1 -
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 ++---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 10 ++---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +--
> drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--
> drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +--
> drivers/gpu/drm/i915/gvt/gtt.c| 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 21 --
> drivers/gpu/drm/i915/intel_device_info.c | 4 +-
> 15 files changed, 37 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 90708de27684..ddd37ccb1362 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct
> intel_memory_region *mem)
> break;
> case 8:
> case 9:
> - case 10:
> if (IS_LP(i915))
> chv_get_stolen_reserved(i915, uncore,
> &reserved_base, &reserved_size);
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 4270b5a34a83..d6f5836396f8 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void
> *unused)
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
> seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
> intel_gpu_freq(rps,
> (gpu_freq *
> (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ?
> + GRAPHICS_VER(i915) >= 11 ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> diff --git a/drivers/gpu/drm/i915/gt/intel_
Re: [Intel-gfx] [PATCH 29/30] drm/i915: replace random CNL comments
On Fri, Jul 23, 2021 at 05:11:13PM -0700, Lucas De Marchi wrote:
> Cleanup remaining cases that we find CNL in the codebase.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 -
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 -
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 6 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4172c8ee6aa6..e86e6ed2d3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private
> *i915,
> "Port %c VBT HDMI boost level: %d\n",
> port_name(port), hdmi_boost_level);
>
> - /* DP max link rate for CNL+ */
> + /* DP max link rate for GLK+ */
> if (i915->vbt.version >= 216) {
> if (i915->vbt.version >= 230)
> info->dp_max_link_rate =
> parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ee6d5f8de24b..b49bf380baab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9778,7 +9778,7 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
>
> /*
>* FIXME: This check is kept generic for all platforms.
> - * Need to verify this for all gen9 and gen10 platforms to
> enable
> + * Need to verify this for all gen9 platforms to enable
>* this selectively if required.
>*/
> switch (new_plane_state->hw.fb->modifier) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 7c048d2ecf43..f483f479dd0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> /*
>* Max timeout values:
>* SKL-GLK: 1.6ms
> - * CNL: 3.2ms
>* ICL+: 4ms
>*/
> ret = DP_AUX_CH_CTL_SEND_BUSY |
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 7fd031a70cfd..6b19f74efd61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -206,7 +206,6 @@ struct intel_dpll_hw_state {
>
> /* cnl */
> u32 cfgcr0;
> - /* CNL also uses cfgcr1 */
>
> /* bxt */
> u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
> pcsdw12;
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index dbe24d7e7375..330077c2e588 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -456,7 +456,7 @@ struct child_device_config {
> u16 dp_gpio_pin_num;/* 195 */
> u8 dp_iboost_level:4; /* 196 */
> u8 hdmi_iboost_level:4; /* 196 */
> - u8 dp_max_link_rate:3; /* 216/230 CNL+
> */
> + u8 dp_max_link_rate:3; /* 216/230 GLK+
> */
> u8 dp_max_link_rate_reserved:5; /* 216/230 */
> } __packed;
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 057c9aa6f9c6..ef1eecd259e0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -103,7 +103,7 @@ enum intel_platform {
> #define INTEL_SUBPLATFORM_ULT(0)
> #define INTEL_SUBPLATFORM_ULX(1)
>
> -/* CNL/ICL */
> +/* ICL */
> #define INTEL_SUBPLATFORM_PORTF (0)
>
> /* DG2 */
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 17/30] drm/i915/display: rename CNL references in skl_scaler.c
On Fri, Jul 23, 2021 at 05:11:01PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider GLK as the first platform using
> those constants since GLK has DISPLAY_VER == 10.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 10 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 911a113ee006..ebdd3115de16 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -341,12 +341,12 @@ static u16 cnl_nearest_filter_coef(int t)
> *
> */
>
> -static void cnl_program_nearest_filter_coefs(struct drm_i915_private
> *dev_priv,
> +static void glk_program_nearest_filter_coefs(struct drm_i915_private
> *dev_priv,
>enum pipe pipe, int id, int set)
> {
> int i;
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
> PS_COEE_INDEX_AUTO_INC);
>
> for (i = 0; i < 17 * 7; i += 2) {
> @@ -359,11 +359,11 @@ static void cnl_program_nearest_filter_coefs(struct
> drm_i915_private *dev_priv,
> t = cnl_coef_tap(i + 1);
> tmp |= cnl_nearest_filter_coef(t) << 16;
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
> tmp);
> }
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
> }
>
> static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int
> set)
> @@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct
> drm_i915_private *dev_priv, enum pipe
> case DRM_SCALING_FILTER_DEFAULT:
> break;
> case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
> - cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
> + glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
> break;
> default:
> MISSING_CASE(filter);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91e93f3e9649..d198b1a2d4b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7726,11 +7726,11 @@ enum {
> #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> -#define CNL_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\
> +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\
> _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A)
> + (set) * 8, \
> _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B)
> + (set) * 8)
>
> -#define CNL_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) +
> (set) * 8, \
> _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) +
> (set) * 8)
> /* legacy palette */
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 30/30] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
> The numbers of scalers and sprites depend on the display version, so use
> it instead of GRAPHICS_VER. We were mixing both, which let me confused
> while removing CNL and GRAPHICS_VER == 10.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index ffe3b5d89a63..7023d36a9a28 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
> for_each_pipe(dev_priv, pipe)
> runtime->num_scalers[pipe] = 0;
> - else if (GRAPHICS_VER(dev_priv) >= 11) {
> + else if (DISPLAY_VER(dev_priv) >= 11) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_scalers[pipe] = 2;
> - } else if (GRAPHICS_VER(dev_priv) == 9) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> runtime->num_scalers[PIPE_A] = 2;
> runtime->num_scalers[PIPE_B] = 2;
> runtime->num_scalers[PIPE_C] = 1;
> @@ -279,7 +279,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 4;
> - else if (GRAPHICS_VER(dev_priv) >= 11)
> + else if (DISPLAY_VER(dev_priv) >= 11)
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 6;
> else if (IS_GEMINILAKE(dev_priv))
while at it we could probably change this to DISPLAY_VER == 10?!
but anyway:
Reviewed-by: Rodrigo Vivi
> @@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 2;
> - } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 1;
> }
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 21/30] drm/i915: remove explicit CNL handling from intel_pch.c
On Fri, Jul 23, 2021 at 05:11:05PM -0700, Lucas De Marchi wrote: > Remove references for CNL from pch detection. for a moment I almost thought you were removing the CNP support... > > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pch.c | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pch.c > b/drivers/gpu/drm/i915/intel_pch.c > index cc44164e242b..d1d4b97b86f5 100644 > --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, > unsigned short id) > case INTEL_PCH_CNP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_CANNONLAKE(dev_priv) && > !IS_COFFEELAKE(dev_priv) && > !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > @@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, > unsigned short id) > drm_dbg_kms(&dev_priv->drm, > "Found Cannon Lake LP PCH (CNP-LP)\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_CANNONLAKE(dev_priv) && > !IS_COFFEELAKE(dev_priv) && > !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > @@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private > *dev_priv, > id = INTEL_PCH_MCC_DEVICE_ID_TYPE; > else if (IS_ICELAKE(dev_priv)) > id = INTEL_PCH_ICP_DEVICE_ID_TYPE; > - else if (IS_CANNONLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv) || > + else if (IS_COFFEELAKE(dev_priv) || >IS_COMETLAKE(dev_priv)) > id = INTEL_PCH_CNP_DEVICE_ID_TYPE; > else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) > -- > 2.31.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
On Sat, Jul 24, 2021 at 10:02:15PM -0700, Lucas De Marchi wrote: > On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote: > > Still tests fine: > > > > Tested-by: Christoph Hellwig > > I just pushed this to drm-intel-next as part of another series and > added your Tested-by. > > Rodrigo, can you pick this up for -fixes? This should go with your other > patch to fix the port mask, too. done. But while doing this and reviewing this series at the same time I got myself wondering if we shouldn't remove the PORT_F support entirely... > > Thanks for the bug report and test. > > Lucas De Marchi > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 26/30] drm/i915: finish removal of CNL
On Fri, Jul 23, 2021 at 05:11:10PM -0700, Lucas De Marchi wrote:
> With all the users removed, finish removing the CNL platform definitions.
> We will leave the PCI IDs around as those are exposed to userspace.
> Even if mesa doesn't support CNL anymore, let's avoid build breakages
> due to changing the headers.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +--
> drivers/gpu/drm/i915/i915_pci.c | 23 +--
> drivers/gpu/drm/i915/i915_perf.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.c | 2 --
> drivers/gpu/drm/i915/intel_device_info.h | 2 --
> 5 files changed, 6 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd2d196050d4..e3c8283d770c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1437,7 +1437,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> -#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
> IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> @@ -1503,8 +1502,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
>INTEL_INFO(dev_priv)->gt == 2)
>
> -#define IS_CNL_WITH_PORT_F(dev_priv) \
> - IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
> #define IS_ICL_WITH_PORT_F(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>
> @@ -1649,9 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> /* WaRsDisableCoarsePowerGating:skl,cnl */
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> - (IS_CANNONLAKE(dev_priv) || \
> - IS_SKL_GT3(dev_priv) ||\
> - IS_SKL_GT4(dev_priv))
> + (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 48ea23dd3b5b..aea2c2d82fbf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = {
> .gt = 2,
> };
>
> -#define GEN10_FEATURES \
> - GEN9_FEATURES, \
> - GEN(10), \
> - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
> - .display.has_dsc = 1, \
> - .has_coherent_ggtt = false, \
> - GLK_COLORS
> -
> -static const struct intel_device_info cnl_info = {
> - GEN10_FEATURES,
> - PLATFORM(INTEL_CANNONLAKE),
> - .gt = 2,
> -};
> -
> #define GEN11_DEFAULT_PAGE_SIZES \
> .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_64K | \
> I915_GTT_PAGE_SIZE_2M
>
> #define GEN11_FEATURES \
> - GEN10_FEATURES, \
> + GEN9_FEATURES, \
> GEN11_DEFAULT_PAGE_SIZES, \
> .abox_mask = BIT(0), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> @@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = {
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> }, \
> GEN(11), \
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
> .dbuf.size = 2048, \
> .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> - .has_logical_ring_elsq = 1, \
> - .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
> + .display.has_dsc = 1, \
> + .has_coherent_ggtt = false, \
> + .has_logical_ring_elsq = 1
>
> static const struct intel_device_info icl_info = {
> GEN11_FEATURES,
> @@ -1123,7 +,6 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CML_GT2_IDS(&cml_gt2_info),
> INTEL_CML_U_GT1_IDS(&cml_gt1_info),
> INTEL_CML_U_GT2_IDS(&cml_gt2_info),
> - INTEL_CNL_IDS(&cnl_info),
> INTEL_ICL_11_IDS(&icl_info),
> INTEL_EHL_IDS(&ehl_info),
> INTEL_JSL_IDS(&jsl_info)
Re: [Intel-gfx] [PATCH 20/30] drm/i915: remove explicit CNL handling from intel_mocs.c
On Fri, Jul 23, 2021 at 05:11:04PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> GEN9_BC, so leave the code around and just remove the special
> case for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 17848807f111..582c4423b95d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> table->size = ARRAY_SIZE(icl_mocs_table);
> table->table = icl_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> + } else if (IS_GEN9_BC(i915)) {
> table->size = ARRAY_SIZE(skl_mocs_table);
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> table->table = skl_mocs_table;
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 14/30] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c
On Fri, Jul 23, 2021 at 05:10:58PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in skl_universal_plane.c.
>
> Remove code and rename functions/macros accordingly to use ICL prefix.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 3ad04bf2a0fd..0f40f8b07724 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
> return 0;
> }
>
> -static u32 cnl_plane_ctl_flip(unsigned int reflect)
> +static u32 icl_plane_ctl_flip(unsigned int reflect)
> {
> switch (reflect) {
> case 0:
> @@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state
> *crtc_state,
> plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
> plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> - plane_ctl |= cnl_plane_ctl_flip(rotation &
> + if (DISPLAY_VER(dev_priv) >= 11)
> + plane_ctl |= icl_plane_ctl_flip(rotation &
> DRM_MODE_REFLECT_MASK);
>
> if (key->flags & I915_SET_COLORKEY_DESTINATION)
> @@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private
> *dev_priv,
> if (plane_id == PLANE_CURSOR)
> return false;
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> return true;
>
> if (IS_GEMINILAKE(dev_priv))
> @@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> supported_rotations |= DRM_MODE_REFLECT_X;
>
> drm_plane_create_rotation_property(&plane->base,
> @@ -2174,7 +2174,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> if (DISPLAY_VER(dev_priv) >= 12)
> drm_plane_enable_fb_damage_clips(&plane->base);
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> drm_plane_create_scaling_filter_property(&plane->base,
> BIT(DRM_SCALING_FILTER_DEFAULT)
> |
>
> BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
> @@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> break;
> }
>
> - if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val &
> PLANE_CTL_FLIP_HORIZONTAL)
> + if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
> plane_config->rotation |= DRM_MODE_REFLECT_X;
>
> /* 90/270 degree rotation would require extra work */
> --
> 2.31.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 24/30] drm/i915: rename CNL references in intel_dram.c
On Fri, Jul 23, 2021 at 05:11:08PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider ICL as the first platform using
> those constants.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 24 +++
> drivers/gpu/drm/i915/intel_dram.c | 32 +++
> 2 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f032a4c8b26d..8782d1723254 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11082,18 +11082,18 @@ enum skl_power_gate {
> #define SKL_DRAM_RANK_1 (0x0 << 10)
> #define SKL_DRAM_RANK_2 (0x1 << 10)
> #define SKL_DRAM_RANK_MASK (0x1 << 10)
> -#define CNL_DRAM_SIZE_MASK 0x7F
> -#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
> -#define CNL_DRAM_WIDTH_SHIFT7
> -#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
> -#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
> -#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
> -#define CNL_DRAM_RANK_MASK (0x3 << 9)
> -#define CNL_DRAM_RANK_SHIFT 9
> -#define CNL_DRAM_RANK_1 (0x0 << 9)
> -#define CNL_DRAM_RANK_2 (0x1 << 9)
> -#define CNL_DRAM_RANK_3 (0x2 << 9)
> -#define CNL_DRAM_RANK_4 (0x3 << 9)
> +#define ICL_DRAM_SIZE_MASK 0x7F
> +#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
> +#define ICL_DRAM_WIDTH_SHIFT7
> +#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
> +#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
> +#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
> +#define ICL_DRAM_RANK_MASK (0x3 << 9)
> +#define ICL_DRAM_RANK_SHIFT 9
> +#define ICL_DRAM_RANK_1 (0x0 << 9)
> +#define ICL_DRAM_RANK_2 (0x1 << 9)
> +#define ICL_DRAM_RANK_3 (0x2 << 9)
> +#define ICL_DRAM_RANK_4 (0x3 << 9)
>
> #define SA_PERF_STATUS_0_0_0_MCHBAR_PC
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 9675bb94b70b..34d6cf440352 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
> }
>
> /* Returns total Gb for the whole DIMM */
> -static int cnl_get_dimm_size(u16 val)
> +static int icl_get_dimm_size(u16 val)
> {
> - return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
> + return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
> }
>
> -static int cnl_get_dimm_width(u16 val)
> +static int icl_get_dimm_width(u16 val)
> {
> - if (cnl_get_dimm_size(val) == 0)
> + if (icl_get_dimm_size(val) == 0)
> return 0;
>
> - switch (val & CNL_DRAM_WIDTH_MASK) {
> - case CNL_DRAM_WIDTH_X8:
> - case CNL_DRAM_WIDTH_X16:
> - case CNL_DRAM_WIDTH_X32:
> - val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
> + switch (val & ICL_DRAM_WIDTH_MASK) {
> + case ICL_DRAM_WIDTH_X8:
> + case ICL_DRAM_WIDTH_X16:
> + case ICL_DRAM_WIDTH_X32:
> + val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
> return 8 << val;
> default:
> MISSING_CASE(val);
> @@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
> }
> }
>
> -static int cnl_get_dimm_ranks(u16 val)
> +static int icl_get_dimm_ranks(u16 val)
> {
> - if (cnl_get_dimm_size(val) == 0)
> + if (icl_get_dimm_size(val) == 0)
> return 0;
>
> - val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
> + val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
>
> return val + 1;
> }
> @@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
> struct dram_dimm_info *dimm,
> int channel, char dimm_name, u16 val)
> {
> - if (GRAPHICS_VER(i915) >= 10) {
> - dimm->size = cnl_get_dimm_size(val);
> - dimm->width = cnl_get_dimm_width(val);
> - dimm->
Re: [Intel-gfx] [PATCH 15/30] drm/i915/display: remove explicit CNL handling from intel_display_power.c
On Fri, Jul 23, 2021 at 05:10:59PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_display_power.c.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> .../drm/i915/display/intel_display_power.c| 289 --
> .../drm/i915/display/intel_display_power.h| 2 -
> drivers/gpu/drm/i915/i915_reg.h | 13 -
> 3 files changed, 304 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 81efc77bada0..44aef0c44ab7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -447,17 +447,6 @@ static void hsw_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> hsw_wait_for_power_well_enable(dev_priv, power_well, false);
>
> - /* Display WA #1178: cnl */
> - if (IS_CANNONLAKE(dev_priv) &&
> - pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
> - pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
> - u32 val;
> -
> - val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
> - val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> - intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
> - }
> -
> if (power_well->desc->hsw.has_fuses) {
> enum skl_power_gate pg;
>
> @@ -2743,63 +2732,6 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_GMBUS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
Re: [Intel-gfx] [PATCH 12/30] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
On Fri, Jul 23, 2021 at 05:10:56PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_ddi.c.
>
> A lot of special code for CNL can be removed. There were some
> __cnl.*() functions that were created to share the implementation
> between ICL and CNL. Those are now embedded in the only caller, in ICL.
>
> Remove code and rename functions/macros accordingly to use ICL prefix
> for those that are still needed.
>
> Verified with:
>
> make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o
good idea...
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++---
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> 2 files changed, 96 insertions(+), 494 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8e2bd8fa090a..0d72917e5670 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
> else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
> return MG_PLL_ENABLE(0);
>
> - return CNL_DPLL_ENABLE(pll->info->id);
> + return ICL_DPLL_ENABLE(pll->info->id);
> }
>
> static i915_reg_t
> @@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
> .dump_hw_state = bxt_dump_hw_state,
> };
>
> -static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
> -struct intel_shared_dpll *pll)
> -{
> - const enum intel_dpll_id id = pll->info->id;
> - u32 val;
> -
> - /* 1. Enable DPLL power in DPLL_ENABLE. */
> - val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> - val |= PLL_POWER_ENABLE;
> - intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> - /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
> - if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
> - PLL_POWER_STATE, 5))
> - drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
> -
> - /*
> - * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
> - * select DP mode, and set DP link rate.
> - */
> - val = pll->state.hw_state.cfgcr0;
> - intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
> -
> - /* 4. Reab back to ensure writes completed */
> - intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
> -
> - /* 3. Configure DPLL_CFGCR0 */
> - /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> - if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> - val = pll->state.hw_state.cfgcr1;
> - intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
> - /* 4. Reab back to ensure writes completed */
> - intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
> - }
> -
> - /*
> - * 5. If the frequency will result in a change to the voltage
> - * requirement, follow the Display Voltage Frequency Switching
> - * Sequence Before Frequency Change
> - *
> - * Note: DVFS is actually handled via the cdclk code paths,
> - * hence we do nothing here.
> - */
> -
> - /* 6. Enable DPLL in DPLL_ENABLE. */
> - val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> - val |= PLL_ENABLE;
> - intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> - /* 7. Wait for PLL lock status in DPLL_ENABLE. */
> - if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
> - drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
> -
> - /*
> - * 8. If the frequency will result in a change to the voltage
> - * requirement, follow the Display Voltage Frequency Switching
> - * Sequence After Frequency Change
> - *
> - * Note: DVFS is actually handled via the cdclk code paths,
> - * hence we do nothing here.
> - */
> -
> - /*
> - * 9. turn on the clock for the DDI and map the DPLL to the DDI
> - * Done at intel_ddi_clk_select
> - */
> -}
> -
> -static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll)
> -{
> - const enum intel_dpll_id id = pll->info->id;
> - u32 val;
> -
> - /*
> - * 1. Configure DPCLKA_CFGCR0 to turn off the clock f
