[Intel-gfx] [PATCH] drm/i915: Fix possible null dereference in framebuffer_info debugfs function
Found by static code analysis tool.
v2: Inserted block instead of goto & renamed variables (Chris)
Signed-off-by: Namrta Salonie
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bd..7c068ea 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1865,31 +1865,29 @@ static int i915_gem_framebuffer_info(struct seq_file
*m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
- struct intel_fbdev *ifbdev = NULL;
- struct intel_framebuffer *fb;
+ struct intel_framebuffer *fbdev_fb = NULL;
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- struct drm_i915_private *dev_priv = dev->dev_private;
- ifbdev = dev_priv->fbdev;
- fb = to_intel_framebuffer(ifbdev->helper.fb);
-
- seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx,
refcount %d, obj ",
- fb->base.width,
- fb->base.height,
- fb->base.depth,
- fb->base.bits_per_pixel,
- fb->base.modifier[0],
- atomic_read(&fb->base.refcount.refcount));
- describe_obj(m, fb->obj);
- seq_putc(m, '\n');
+ if (to_i915(dev)->fbdev) {
+ fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
+ seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
+ fbdev_fb->base.width,
+ fbdev_fb->base.height,
+ fbdev_fb->base.depth,
+ fbdev_fb->base.bits_per_pixel,
+ fbdev_fb->base.modifier[0],
+ atomic_read(&fbdev_fb->base.refcount.refcount));
+ describe_obj(m, fbdev_fb->obj);
+ seq_putc(m, '\n');
+ }
#endif
mutex_lock(&dev->mode_config.fb_lock);
drm_for_each_fb(drm_fb, dev) {
- fb = to_intel_framebuffer(drm_fb);
- if (ifbdev && &fb->base == ifbdev->helper.fb)
+ struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
+ if (fb == fbdev_fb)
continue;
seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Fix possible null dereference in framebuffer_info debugfs function
Found by static code analysis tool.
v2: Inserted block instead of goto & renamed variables (Chris)
v3: Aligned code as per the opening brace (Chris)
Rebased on top of nightly (Daniel)
Signed-off-by: Namrta Salonie
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_debugfs.c | 36 ---
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a728ff1..bfd57fb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1869,33 +1869,29 @@ static int i915_gem_framebuffer_info(struct seq_file
*m, void *data)
{
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
- struct intel_fbdev *ifbdev = NULL;
- struct intel_framebuffer *fb;
+ struct intel_framebuffer *fbdev_fb = NULL;
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- ifbdev = dev_priv->fbdev;
- if (ifbdev) {
- fb = to_intel_framebuffer(ifbdev->helper.fb);
-
- seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
- fb->base.width,
- fb->base.height,
- fb->base.depth,
- fb->base.bits_per_pixel,
- fb->base.modifier[0],
- atomic_read(&fb->base.refcount.refcount));
- describe_obj(m, fb->obj);
- seq_putc(m, '\n');
- }
+ if (to_i915(dev)->fbdev) {
+ fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
+
+ seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
+ fbdev_fb->base.width,
+ fbdev_fb->base.height,
+ fbdev_fb->base.depth,
+ fbdev_fb->base.bits_per_pixel,
+ fbdev_fb->base.modifier[0],
+ atomic_read(&fbdev_fb->base.refcount.refcount));
+ describe_obj(m, fbdev_fb->obj);
+ seq_putc(m, '\n');
+ }
#endif
mutex_lock(&dev->mode_config.fb_lock);
drm_for_each_fb(drm_fb, dev) {
- fb = to_intel_framebuffer(drm_fb);
- if (ifbdev && &fb->base == ifbdev->helper.fb)
+ struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
+ if (fb == fbdev_fb)
continue;
seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier
0x%llx, refcount %d, obj ",
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Enabling RC6 immediately during init/resume
Since RC6 enabling does not involve PCU communication overhead,
it can be enabled immediately during the resume time.
This will help save additional power & meet power requirements
for active Idle KPI where power is evaluated over
number of transitions of suspend/resume.
v2: RPM ref count is not needed with immediate enabling of RC6, that is removed.
And code extended to other GEN as well. (Chris & Daniel)
Signed-off-by: Namrta Salonie
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 126 +++
1 file changed, 87 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 96f45d7..1c1ea63 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4719,7 +4719,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
}
-static void gen8_enable_rps(struct drm_device *dev)
+static void gen8_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
@@ -4729,16 +4729,13 @@ static void gen8_enable_rps(struct drm_device *dev)
/* 1a: Software RC state - RC0 */
I915_WRITE(GEN6_RC_STATE, 0);
- /* 1c & 1d: Get forcewake during program sequence. Although the driver
+ /* 1b & 1c: Get forcewake during program sequence. Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* 2a: Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
- /* Initialize rps frequencies */
- gen6_init_rps_frequencies(dev);
-
/* 2b: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4764,7 +4761,20 @@ static void gen8_enable_rps(struct drm_device *dev)
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
- /* 4 Program defaults and thresholds for RPS*/
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void gen8_enable_rps(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* 1: Get forcewake during program sequence. */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* Initialize rps frequencies */
+ gen6_init_rps_frequencies(dev);
+
+ /* 2: Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RPNSWREQ,
HSW_FREQUENCY(dev_priv->rps.rp1_freq));
I915_WRITE(GEN6_RC_VIDEO_FREQ,
@@ -4784,7 +4794,7 @@ static void gen8_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
- /* 5: Enable RPS */
+ /* 3: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_TURBO |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
@@ -4793,7 +4803,7 @@ static void gen8_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
- /* 6: Ring frequency + overclocking (our driver does this later */
+ /* 4: Ring frequency + overclocking (our driver does this later */
dev_priv->rps.power = HIGH_POWER; /* force a reset */
gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
@@ -5320,14 +5330,13 @@ static void valleyview_cleanup_gt_powersave(struct
drm_device *dev)
valleyview_cleanup_pctx(dev);
}
-static void cherryview_enable_rps(struct drm_device *dev)
+static void cherryview_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
int i;
- WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
gtfifodbg = I915_READ(GTFIFODBG);
if (gtfifodbg) {
@@ -5338,7 +5347,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
cherryview_check_pctx(dev_priv);
- /* 1a & 1b: Get forcewake during program sequence. Although the driver
+ /* 1: Get forcewake during program sequence. . Although the driver
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
@@ -5372,8 +5381,20 @@ static void cherryview_enable_rps(struct drm_device *dev)
rc6_mode = GEN7_RC_CTL_TO_MODE;
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
- /* 4 Program defaults and thresholds for RPS*/
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+struct drm_i915_private *dev_priv = dev->dev_private;
+u32 val;
+
+ WARN_ON(!mutex_is_lo
[Intel-gfx] [PATCH] drm/i915/vlv: Modifying RC6 Promotion timer for Media workloads.
In normal cases, RC6 promotion timer is 1700us. This will result in more
time spent in C1 state. For more residency in C6 in case of media workloads,
this is changed to 250us. Not doing this for 3D workloads as too many C6-C0
transition delays can result in performance impact. Tracking the media
workloads based on command submission to MFX engine.
Signed-off-by: Namrta Salonie
Signed-off-by: Satyanantha, Rama Gopal M
---
drivers/gpu/drm/i915/i915_drv.h|3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 +
drivers/gpu/drm/i915/i915_reg.h|2 ++
drivers/gpu/drm/i915/intel_drv.h |2 ++
drivers/gpu/drm/i915/intel_pm.c| 30 +++-
5 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc865e23..74c9f86 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1147,6 +1147,9 @@ struct intel_gen6_power_mgmt {
* talking to hw - so only take it when talking to hw!
*/
struct mutex hw_lock;
+
+ /* Delayed work to adjust RC6 promotion timer */
+ struct delayed_work vlv_media_timeout_work;
};
/* defined intel_pm.c */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a4c243c..af7fbf8 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1254,6 +1254,20 @@ i915_gem_ringbuffer_submission(struct
i915_execbuffer_params *params,
return ret;
}
+ /* For VLV, modify RC6 promotion timer upon hitting Media workload only
+ This will help in better power savings with media scenarios.
+*/
+ if (((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) &&
+ !IS_CHERRYVIEW(dev) && IS_VALLEYVIEW(dev) &&
+ dev_priv->rps.enabled) {
+ vlv_modify_rc6_promotion_timer(dev_priv, true);
+
+ /*Start a timer for 1 sec to reset this value to original*/
+ mod_delayed_work(dev_priv->wq,
+ &dev_priv->rps.vlv_media_timeout_work,
+ msecs_to_jiffies(1000));
+ }
+
exec_len = args->batch_len;
exec_start = params->batch_obj_vm_offset +
params->args_batch_start_offset;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4872245..3f66f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6905,6 +6905,8 @@ enum skl_disp_power_wells {
#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
#define GEN6_RC1e_THRESHOLD_MMIO(0xA0B4)
#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
+#define GEN6_RC6_RENDER_PROMOTION_TIMER_TO 0x0557
+#define GEN6_RC6_MEDIA_PROMOTION_TIMER_TO 0x00C3
#define GEN6_RC6p_THRESHOLD_MMIO(0xA0BC)
#define VLV_RCEDATA_MMIO(0xA0BC)
#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fae824..e563d65 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1283,6 +1283,8 @@ void intel_dsi_init(struct drm_device *dev);
/* intel_dvo.c */
void intel_dvo_init(struct drm_device *dev);
+extern void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+ bool media_active);
/* legacy fbdev emulation in intel_fbdev.c */
#ifdef CONFIG_DRM_FBDEV_EMULATION
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1c1ea63..149b944 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4492,6 +4492,26 @@ static void valleyview_disable_rps(struct drm_device
*dev)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
+void vlv_modify_rc6_promotion_timer(struct drm_i915_private *dev_priv,
+ bool media_active)
+{
+ /* Update RC6 promotion timers */
+ if (media_active)
+ I915_WRITE(GEN6_RC6_THRESHOLD,
+ GEN6_RC6_MEDIA_PROMOTION_TIMER_TO);
+ else
+ I915_WRITE(GEN6_RC6_THRESHOLD,
+ GEN6_RC6_RENDER_PROMOTION_TIMER_TO);
+}
+
+static void vlv_media_timeout_work_func(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv = container_of(work, struct
drm_i915_private,
+ rps.vlv_media_timeout_work.work);
+
+ vlv_modify_rc6_promotion_timer(dev_priv, false);
+}
+
static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
{
if (IS_VALLEYVIEW(dev)) {
@@ -6050,7 +6070,9 @@ static void gen6_suspend_rps(st
[Intel-gfx] [PATCH 1/4] drm/i915: Fix for potential NULL pointer dereference at ctx access.
Added a null check for the context pointer, before de-referencing it. Found by static analysis tool. Signed-off-by: Namrta Salonie --- drivers/gpu/drm/i915/i915_gpu_error.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 2f04e4f..29ecd0c 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1036,7 +1036,7 @@ static void i915_gem_record_rings(struct drm_device *dev, * for it to be useful (e.g. dump the context being * executed). */ - if (request) + if (request && request->ctx) rbuf = request->ctx->engine[ring->id].ringbuf; else rbuf = ring->default_context->engine[ring->id].ringbuf; -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/4] Fix issues reported by static code analysis tool
The patchset is created to fix the issues static analysis tool has reported Namrta Salonie (4): drm/i915: Fix for potential NULL pointer dereference at ctx access. drm/i915: Fix possible null dereference in two debugfs functions drm/i915 : Fix to remove unnecsessary checks in postclose function. drm/i915: Fix potential NULL pointer de-reference in ggtt unbind. drivers/gpu/drm/i915/i915_debugfs.c | 19 +++ drivers/gpu/drm/i915/i915_dma.c |2 -- drivers/gpu/drm/i915/i915_drv.h |5 - drivers/gpu/drm/i915/i915_gpu_error.c |2 +- 4 files changed, 20 insertions(+), 8 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/4] drm/i915: Fix potential NULL pointer de-reference in ggtt unbind.
Found by static analysis tool.
Signed-off-by: Namrta Salonie
---
drivers/gpu/drm/i915/i915_drv.h |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8afda45..705b1e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3097,7 +3097,10 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
- return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
+ struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
+ if (!vma)
+ return -EINVAL;
+ return i915_vma_unbind(vma);
}
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
--
1.7.9.5
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[Intel-gfx] [PATCH 3/4] drm/i915 : Fix to remove unnecsessary checks in postclose function.
Found by static analysis tool.
Signed-off-by: Namrta Salonie
---
drivers/gpu/drm/i915/i915_dma.c |2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2336af9..ac1bca6 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1269,8 +1269,6 @@ void i915_driver_postclose(struct drm_device *dev, struct
drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
- if (file_priv && file_priv->bsd_ring)
- file_priv->bsd_ring = NULL;
kfree(file_priv);
}
--
1.7.9.5
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[Intel-gfx] [PATCH 2/4] drm/i915: Fix possible null dereference in two debugfs functions
Found by static code analysis tool.
Signed-off-by: Namrta Salonie
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_debugfs.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a3b22bd..d1719e9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1873,6 +1873,9 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
struct drm_i915_private *dev_priv = dev->dev_private;
ifbdev = dev_priv->fbdev;
+ if (!ifbdev)
+ goto fb_loop;
+
fb = to_intel_framebuffer(ifbdev->helper.fb);
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx,
refcount %d, obj ",
@@ -1884,8 +1887,9 @@ static int i915_gem_framebuffer_info(struct seq_file *m,
void *data)
atomic_read(&fb->base.refcount.refcount));
describe_obj(m, fb->obj);
seq_putc(m, '\n');
-#endif
+fb_loop:
+#endif
mutex_lock(&dev->mode_config.fb_lock);
drm_for_each_fb(drm_fb, dev) {
fb = to_intel_framebuffer(drm_fb);
@@ -3868,12 +3872,19 @@ static int pipe_crc_set_source(struct drm_device *dev,
enum pipe pipe,
enum intel_pipe_crc_source source)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
- struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
- pipe));
+ struct intel_pipe_crc *pipe_crc;
+ struct intel_crtc *crtc;
u32 val = 0; /* shut up gcc */
int ret;
+ if ((pipe < PIPE_A) || (pipe >= I915_MAX_PIPES))
+ return -EINVAL;
+
+ pipe_crc = &dev_priv->pipe_crc[pipe];
+
+ crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
+ pipe));
+
if (pipe_crc->source == source)
return 0;
--
1.7.9.5
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[Intel-gfx] [PATCH] drm/i915: Enabling RC6 immediately during init/resume
Since RC6 enabling does not involve PCU communication overhead,
it can be enabled immediately during the resume time.
This will help save additional power & meet power requirements
for active Idle KPI where power is evaluated over
number of transitions of suspend/resume.
Signed-off-by: Namrta Salonie
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 94 ++-
1 file changed, 63 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fff0c22..f1164c0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5468,14 +5468,13 @@ static void valleyview_cleanup_gt_powersave(struct
drm_device *dev)
valleyview_cleanup_pctx(dev);
}
-static void cherryview_enable_rps(struct drm_device *dev)
+static void cherryview_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+ u32 gtfifodbg, rc6_mode = 0, pcbr;
int i;
- WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
gtfifodbg = I915_READ(GTFIFODBG);
if (gtfifodbg) {
@@ -5486,9 +5485,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
cherryview_check_pctx(dev_priv);
- /* 1a & 1b: Get forcewake during program sequence. Although the driver
-* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ /* 1: Get forcewake during program sequence. Although the driver
+ * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
+intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -5520,8 +5519,21 @@ static void cherryview_enable_rps(struct drm_device *dev)
rc6_mode = GEN7_RC_CTL_TO_MODE;
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
- /* 4 Program defaults and thresholds for RPS*/
+static void cherryview_enable_rps(struct drm_device *dev)
+{
+struct drm_i915_private *dev_priv = dev->dev_private;
+u32 val;
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+/* 1: Get forcewake during program sequence. As Driver would have
enabled RC6
+* by now before Turbo enabling sequence */
+intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ /* 2: Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -5530,7 +5542,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
- /* 5: Enable RPS */
+ /* 3: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
@@ -5538,7 +5550,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
- /* Setting Fixed Bias */
+ /* 4: Setting Fixed Bias */
val = VLV_OVERRIDE_EN |
VLV_SOC_TDP_EN |
CHV_BIAS_CPU_50_SOC_50;
@@ -5546,7 +5558,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- /* RPS code assumes GPLL is used */
+ /* 5: RPS code assumes GPLL is used */
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
@@ -5566,14 +5578,13 @@ static void cherryview_enable_rps(struct drm_device
*dev)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
}
-static void valleyview_enable_rps(struct drm_device *dev)
+static void valleyview_enable_rc6(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
- u32 gtfifodbg, val, rc6_mode = 0;
+ u32 gtfifodbg, rc6_mode = 0;
int i;
- WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
valleyview_check_pctx(dev_priv);
@@ -5583,28 +5594,12 @@ static void valleyview_enable_rps(struct drm_device
*dev)
I915_WRITE(GTFIFODBG, gtfifodbg);
}
- /* If VLV, Forcewake all wells, else re-direct to regular path */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+/* If VLV, Forcewake all wells */
+intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
-
