Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: add rc6 residency times to debugfs
On Mon, Mar 26, 2012 at 06:34, Daniel Vetter wrote:
> On Sun, Mar 25, 2012 at 05:33:27PM -0700, Ben Widawsky wrote:
> > RC6 residency should be in intervals of 1.28us, and the counter wraps.
> > Here is an example using awk to get the various RC6 and RC6+ residency
> > times in seconds, since boot.
> >
> > cat /sys/kernel/debug/dri/0/i915_drpc_info | grep residency | awk -F':'
> -F' ' '{print $5 * 1.28 / 100}'
> >
> > This is primarily for debug, and QA/application developers using the
> > sysfs interface looking for more insight.
> >
> > Untested on IVB.
>
> Tested on my ivb, seems to yield sane numbers for the default
> configuration (i.e. enable rc+rc6p, disable rc6pp).
>
Yeah, it should work on IVB except for some strange behavior sometimes (I
noticed that on IVB we sometimes get into RC6 even if we pass the
i915_enable_rc6=0 parameter). I don't know if it is Bios playing some
tricks with us or something changed in the mailbox communication, but no
harm came from this so far. I'll see what is going on there.
But for the patch itself:
Reviewed-by: Eugeni Dodonov
Nothing like new and shiny powertop power-saving options :).
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/37] drm/i915: add support for power wells
On Mon, Mar 26, 2012 at 14:32, Rodrigo Vivi wrote: > Like in this patch, the defines indentation in some patches in this > series sounds strange, wrong, or at least different from the one > already in use. > > So, since I don't know if we should care about indentation now, for > those patches I'll just mark like this: > > * indentation > Reviewed-by: Rodrigo Vivi > The identation is different between registers themselves (e.g., 0xSOMETHING) and the bits we use in those registers (e.g., (1<<31)). So this is on purpose. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/37] drm/i915: add DDI registers
On Mon, Mar 26, 2012 at 14:35, Rodrigo Vivi wrote: > *indentation > and it is missing > #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) > > Otherwise: > Reviewed-by: Rodrigo Vivi > We are not using this bit, this is why I am not exposing it... -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: add rc6 residency times to debugfs
On Mon, Mar 26, 2012 at 19:34, Ben Widawsky wrote: > I'd like to resubmit this patch with either %u or %x instead of the %d. > Can I still keep your r-b? > I'd vote for %u - it makes more sense as we are counting real time here. But sure, you can keep my R-b for this. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 31/37] drm/i915: enable PCH earlier
On Wed, Mar 28, 2012 at 16:32, Jesse Barnes wrote: > On Thu, 22 Mar 2012 11:05:22 + > Chris Wilson wrote: > > > On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > > The modesetting sequence for PCH-related connections mentions that the > > > order of plane/pipe enablement could happen either before of after PCH > > > enablement. > > > > > > With LPT, however, we need to enable some things earlier to be able to > > > talk to PCH. So let's do it a bit in advance. > > > > Touching modesetting sequence is a nerve racking experience. Can we > > arrange to have this patch tested by itself, right now? > > Double plus agree. Core changes like this need to be run against as > many configs and previous gens as possible... > With the latest iteration of the patches, I managed to work-around this properly. So I'll drop this patch from the next patch-bomb. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] RFC: i915 arch changes to better support new chipsets
On Wed, Mar 28, 2012 at 16:46, Jesse Barnes wrote: > > I guess we could have the gen-number stuff be a union of > > IS_IVB()/IS_HSW()/IS_VLV(), and switch chipset probing to using each of > > those instead of just gen >= 4. > > > > Does this sound sane? > > Yeah that might be better anyway, at least for the kernel where the > IS_GEN stuff is getting more and more overloaded and I'd like to move > away from it in some places. > > So if you're ok with it, that sounds like a good approach. > I think that we could move away from the IS_GEN checks in most places actually, and not just in some of them, by using the feature checks instead. My latest branch reports gives `grep IS_GEN * | wc -l` = 112; and if we look for recent chipsets, we have `grep IS_GEN[67] *` = 47. And most of those checks have sub-checks as well for specific chip features or names. So if we drop the IS_GEN macros, and just use the specific feature or GPU name checks instead we should improve both the readability and decrease the code complexity I think. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] RFC: i915 arch changes to better support new chipsets
On Wed, Mar 28, 2012 at 17:37, Daniel Vetter wrote: > > > My latest branch reports gives `grep IS_GEN * | wc -l` = 112; and if we > > > look for recent chipsets, we have `grep IS_GEN[67] *` = 47. And most of > > > those checks have sub-checks as well for specific chip features or > names. > > > So if we drop the IS_GEN macros, and just use the specific feature or > GPU > > > name checks instead we should improve both the readability and > decrease the > > > code complexity I think. > > > > A grep for IS_GEN will be significantly under-counting the number of > > places that gen numbers are used, given that Mesa uses intel->gen, and > > the 2d driver tends to use INTEL_INFO(intel)->gen. > > Actually the kernel uses INTEL_INFO(dev)->gen, too, mostly where we want > to case switch on the gen number. And that happens at a fair amount of > places. > Indeed, you are right, my grep skills failed on me here. After looking on the way gen info is used in Mesa, yeah, I think it is not really a solution to abandon it just yet. I came to think on the possible feature checks to replace them, but I don't think it would be worth the effort just to replace all the Gen checks with a different switch just for the sake of doing it. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/41] [RFC] Haswell v2
This is an updated set of patches for Haswell enablement. I tried to address all the comments, and re-diffed the patches to simplify their inclusion into Daniel's tree. I have also split the PCI IDs definitions and their hook-up into the binding tables as well. But I think we should wait on picking up those 2 patches for now - the PCI ID allocation logic here will still receive some additional changes I think. Functionality-wise, those patches do detect digital outputs now, namely HDMI, but said outputs do not (yet) work. The digital output detection process is also different from what we had previously - we can detect the presence of a connection on a port via DDI port feedback, but we cannot say if it is HDMI or DP. So I am not quite certain on how to address this properly in the driver yet. For now, I just blindly assume that it is HDMI as I don't have any DP monitors or connectors to test :). But for all means, please consider that support for digital outputs in this series is still unfinished and will change considerable in the future. Nonetheless, any feedback on how to implement it properly is much welcome. Note that with the DDI buffers, the same port can drive DP and HDMI without any buffer configuration changes; and we can drive FDI and HDMI likewise. So I've split the DDI buffers settings into a separate patch to pre-configure the ports to their suggested connection settings at the init time, which should work for any combinations of outputs. As for other changes, there are some comments improvements, some register name changes, a new enum for DDI ports, some changes in SBI handchake handling, a couple of new clocks we need for digital outputs and a bit of changes in the DDI pipe settings handling code. So Daniel, as we talked on irc, could you check which of those patches could be early picked into your tree? This would reduce future patchbombs from my side - I'd expect to have at least a half-dozen new patches until we'll have working digital outputs in place.. Eugeni Dodonov (41): drm/i915: transform HAS_PCH_SPLIT in a feature check drm/i915: add Haswell devices and their PCI IDs drm/i915: hook Haswell devices in place drm/i915: add support for LynxPoint PCH drm/i915: add support for power wells drm/i915: add enumeration for DDI ports drm/i915: add DDI registers drm/i915: add DP_TP_CTL registers drm/i915: add DP_TP_STATUS registers drm/i915: add definitions for DDI_BUF_CTL registers drm/i915: add definition of DDI buffer translations regs drm/i915: add definition of LPT FDI port width registers drm/i915: add SBI registers drm/i915: add support for SBI ops drm/i915: add PIXCLK_GATE register drm/i915: add S PLL control drm/i915: add port clock selection support for HSW drm/i915: add SSC offsets for SBI access drm/i915: add LCPLL control registers drm/i915: add WRPLL clocks drm/i915: add WM_LINETIME registers drm/i915: add SFUSE_STRAP registers for digital port detection drm/i915: calculate same watermarks on Haswell as on Ivy Bridge drm/i915: share forcewaking code between IVB and HSW drm/i915: haswell has 3 pipes as well drm/i915: reuse Ivybridge interrupts code for Haswell drm/i915: share pipe count handling with Ivybridge drm/i915: share IVB cursor routine with Haswell drm/i915: show unknown sdvox registers on hdmi init drm/i915: enable power wells on haswell init drm/i915: disable rc6 on haswell for now drm/i915: program WM_LINETIME on Haswell drm/i915: initialize DDI buffer translations drm/i915: perform Haswell DDI link training in FDI mode drm/i915: disable pipe DDI function when disabling pipe drm/i915: do not use fdi_normal_train on haswell drm/i915: program iCLKIP on Lynx Point drm/i915: detect digital outputs on Haswell drm/i915: add support for DDI-controlled digital outputs drm/i915: prepare HDMI link for Haswell drm/i915: add debugging bits for haswell modesetting drivers/char/agp/intel-agp.c |4 + drivers/char/agp/intel-agp.h | 11 + drivers/char/agp/intel-gtt.c | 14 + drivers/gpu/drm/i915/i915_dma.c |2 +- drivers/gpu/drm/i915/i915_drv.c | 37 ++ drivers/gpu/drm/i915/i915_drv.h | 17 +- drivers/gpu/drm/i915/i915_irq.c |6 +- drivers/gpu/drm/i915/i915_reg.h | 194 + drivers/gpu/drm/i915/intel_display.c | 733 -- drivers/gpu/drm/i915/intel_drv.h |1 + drivers/gpu/drm/i915/intel_hdmi.c| 84 +++- 11 files changed, 1064 insertions(+), 39 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/41] drm/i915: transform HAS_PCH_SPLIT in a feature check
The macro is becoming too complex and with VLV upon us it can lead to
confusion. So transforming this into a feature check instead.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |6 ++
drivers/gpu/drm/i915/i915_drv.h |3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8e2c52e..9cf66e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -211,6 +211,7 @@ static const struct intel_device_info intel_ironlake_d_info
= {
.gen = 5,
.need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
+ .has_pch_split = 1,
};
static const struct intel_device_info intel_ironlake_m_info = {
@@ -218,6 +219,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.need_gfx_hws = 1, .has_hotplug = 1,
.has_fbc = 1,
.has_bsd_ring = 1,
+ .has_pch_split = 1,
};
static const struct intel_device_info intel_sandybridge_d_info = {
@@ -226,6 +228,7 @@ static const struct intel_device_info
intel_sandybridge_d_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.has_llc = 1,
+ .has_pch_split = 1,
};
static const struct intel_device_info intel_sandybridge_m_info = {
@@ -235,6 +238,7 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.has_llc = 1,
+ .has_pch_split = 1,
};
static const struct intel_device_info intel_ivybridge_d_info = {
@@ -243,6 +247,7 @@ static const struct intel_device_info
intel_ivybridge_d_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.has_llc = 1,
+ .has_pch_split = 1,
};
static const struct intel_device_info intel_ivybridge_m_info = {
@@ -252,6 +257,7 @@ static const struct intel_device_info
intel_ivybridge_m_info = {
.has_bsd_ring = 1,
.has_blt_ring = 1,
.has_llc = 1,
+ .has_pch_split = 1,
};
static const struct pci_device_id pciidlist[] = { /* aka */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2f9dd9..0443f2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,6 +255,7 @@ struct intel_device_info {
u8 is_broadwater:1;
u8 is_crestline:1;
u8 is_ivybridge:1;
+ u8 has_pch_split:1;
u8 has_fbc:1;
u8 has_pipe_cxsr:1;
u8 has_hotplug:1;
@@ -1048,7 +1049,7 @@ struct drm_i915_file_private {
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private
*)(dev)->dev_private)->pch_type)
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/41] drm/i915: add Haswell devices and their PCI IDs
This adds product definitions for desktop, mobile and server boards.
v2: split into a separate patch, add .has_pch_split feature.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.h| 11 +++
drivers/char/agp/intel-gtt.c| 14 ++
drivers/gpu/drm/i915/i915_drv.c | 18 ++
drivers/gpu/drm/i915/i915_drv.h |2 ++
4 files changed, 45 insertions(+)
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5da67f1..46394c11 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -234,6 +234,17 @@
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
+#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /*
Desktop */
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /*
Mobile */
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /*
Server */
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV0x0c16 /* SDV */
+#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
int intel_gmch_probe(struct pci_dev *pdev,
struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..f494556 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1459,6 +1459,20 @@ static const struct intel_gtt_driver_description {
"Ivybridge", &sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
"Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
+ "Haswell", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+ "Haswell", &sandybridge_gtt_driver },
{ 0, NULL, NULL }
};
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9cf66e1..6e4d90c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -260,6 +260,24 @@ static const struct intel_device_info
intel_ivybridge_m_info = {
.has_pch_split = 1,
};
+static const struct intel_device_info intel_haswell_d_info = {
+ .is_haswell = 1, .gen = 7,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+ .has_llc = 1,
+ .has_pch_split = 1,
+};
+
+static const struct intel_device_info intel_haswell_m_info = {
+ .is_haswell = 1, .gen = 7, .is_mobile = 1,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+ .has_llc = 1,
+ .has_pch_split = 1,
+};
+
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0443f2d..90681d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -256,6 +256,7 @@ struct intel_device_info {
u8 is_crestline:1;
u8 is_ivybridge:1;
u8 has_pch_split:1;
+ u8 is_haswell:1;
u8 has_fbc:1;
u8 has_pipe_cxsr:1;
u8 has_hotplug:1;
@@ -1006,6 +1007,7 @@ struct drm_i915_file_private {
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_HASWELL(dev)(INTEL_INFO(dev)->is_haswell)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
/*
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/41] drm/i915: hook Haswell devices in place
This patch enabled i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.c|4
drivers/gpu/drm/i915/i915_drv.c |7 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 962e75d..0ad4933 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -907,6 +907,10 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
{ }
};
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6e4d90c..8995165 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,13 @@ static const struct pci_device_id pciidlist[] = {
/* aka */
INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+ INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
+ INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+ INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
+ INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+ INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
+ INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
+ INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
{0, 0, 0}
};
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/41] drm/i915: add support for LynxPoint PCH
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |4
drivers/gpu/drm/i915/i915_drv.h |2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8995165..e4b5571 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -340,6 +340,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
+#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
void intel_detect_pch(struct drm_device *dev)
{
@@ -368,6 +369,9 @@ void intel_detect_pch(struct drm_device *dev)
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
+ } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_LPT;
+ DRM_DEBUG_KMS("Found LynxPoint PCH\n");
}
}
pci_dev_put(pch);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90681d6..146778e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -293,6 +293,7 @@ enum no_fbc_reason {
enum intel_pch {
PCH_IBX,/* Ibexpeak PCH */
PCH_CPT,/* Cougarpoint PCH */
+ PCH_LPT,/* Lynxpoint PCH */
};
#define QUIRK_PIPEA_FORCE (1<<0)
@@ -1055,6 +1056,7 @@ struct drm_i915_file_private {
#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private
*)(dev)->dev_private)->pch_type)
+#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/41] drm/i915: add support for power wells
This defines the registers used by different power wells. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52a06be..b13ed38 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3850,4 +3850,17 @@ #define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) #define AUD_CONFIG_DISABLE_NCTS (1 << 3) +/* HSW Power Wells */ +#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */ +#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ +#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ +#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ +#define HSW_PWR_WELL_ENABLE (1<<31) +#define HSW_PWR_WELL_STATE (1<<30) +#define HSW_PWR_WELL_CTL5 0x45410 +#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) +#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) +#define HSW_PWR_WELL_FORCE_ON(1<<19) +#define HSW_PWR_WELL_CTL6 0x45414 + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/41] drm/i915: add enumeration for DDI ports
There are 5 DDI ports on Haswell. Port A is always enabled, and is the one
connected to eDP, and Port E is the one that can be connected to the PCH
using FDI protocol. Ports B, C, D and E can be used for digital outputs.
Signed-off-by: Daniel Vetter
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers/gpu/drm/i915/i915_reg.h |2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 146778e..a30e88f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -63,6 +63,16 @@ enum plane {
};
#define plane_name(p) ((p) + 'A')
+enum port {
+ PORT_A = 0,
+ PORT_B,
+ PORT_C,
+ PORT_D,
+ PORT_E,
+ I915_MAX_PORTS
+};
+#define port_name(p) ((p) + 'A')
+
#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b13ed38..cf7b397 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -27,6 +27,8 @@
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
+
/*
* The Bridge device's PCI config space has information about the
* fb aperture size and the amount of pre-reserved memory.
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/41] drm/i915: add DDI registers
There is one set of such registers for each pipe (A/B/C/EDP). v2: update to use DDI PORTS enum v1 Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 26 ++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cf7b397..26c6929 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3865,4 +3865,30 @@ #define HSW_PWR_WELL_FORCE_ON(1<<19) #define HSW_PWR_WELL_CTL6 0x45414 +/* Per-pipe DDI Function Control */ +#define PIPE_DDI_FUNC_CTL_A0x60400 +#define PIPE_DDI_FUNC_CTL_B0x61400 +#define PIPE_DDI_FUNC_CTL_C0x62400 +#define PIPE_DDI_FUNC_CTL_EDP 0x6F400 +#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \ + PIPE_DDI_FUNC_CTL_A, \ + PIPE_DDI_FUNC_CTL_B) +#define PIPE_DDI_FUNC_ENABLE (1<<31) +/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ +#define PIPE_DDI_PORT_MASK(0xf<<28) +#define PIPE_DDI_SELECT_PORT(x) ((x)<<28) +#define PIPE_DDI_MODE_SELECT_HDMI (0<<24) +#define PIPE_DDI_MODE_SELECT_DVI (1<<24) +#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24) +#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24) +#define PIPE_DDI_MODE_SELECT_FDI (4<<24) +#define PIPE_DDI_BPC_8(0<<20) +#define PIPE_DDI_BPC_10 (1<<20) +#define PIPE_DDI_BPC_6(2<<20) +#define PIPE_DDI_BPC_12 (3<<20) +#define PIPE_DDI_BFI_ENABLE (1<<4) +#define PIPE_DDI_PORT_WIDTH_X1(0<<1) +#define PIPE_DDI_PORT_WIDTH_X2(1<<1) +#define PIPE_DDI_PORT_WIDTH_X4(3<<1) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/41] drm/i915: add DP_TP_CTL registers
This is one set of those registers for each pipe. v2: use port enum to access individual registers Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 26c6929..627e52d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3891,4 +3891,20 @@ #define PIPE_DDI_PORT_WIDTH_X2(1<<1) #define PIPE_DDI_PORT_WIDTH_X4(3<<1) +/* DisplayPort Transport Control */ +#define DP_TP_CTL_A0x64040 +#define DP_TP_CTL_B0x64140 +#define DP_TP_CTL(port) _PORT(port, \ + DP_TP_CTL_A, \ + DP_TP_CTL_B) +#define DP_TP_CTL_ENABLE (1<<31) +#define DP_TP_CTL_MODE_SST(0<<27) +#define DP_TP_CTL_MODE_MST(1<<27) +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) +#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) +#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) +#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) +#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) +#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/41] drm/i915: add DP_TP_STATUS registers
There is one set of those registers for each port. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 627e52d..666e319 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3907,4 +3907,12 @@ #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) +/* DisplayPort Transport Status */ +#define DP_TP_STATUS_A 0x64044 +#define DP_TP_STATUS_B 0x64144 +#define DP_TP_STATUS(port) _PORT(port, \ + DP_TP_STATUS_A, \ + DP_TP_STATUS_B) +#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 26/41] drm/i915: reuse Ivybridge interrupts code for Haswell
v2: prevent possible conflicts with VLV.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_irq.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 998116e..16e9972 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1795,7 +1795,7 @@ static void ironlake_irq_preinstall(struct drm_device
*dev)
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
- if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
I915_WRITE(HWSTAM, 0xeffe);
@@ -2121,7 +2121,7 @@ void intel_irq_init(struct drm_device *dev)
{
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0xff; /* only 24 bits of frame count */
- if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+ if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
IS_HASWELL(dev)) {
dev->max_vblank_count = 0x; /* full 32 bit counter */
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
}
@@ -2132,7 +2132,7 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->get_vblank_timestamp = NULL;
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share pre & uninstall handlers with ILK/SNB */
dev->driver->irq_handler = ivybridge_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_preinstall;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 24/41] drm/i915: share forcewaking code between IVB and HSW
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5e226ad..1484195 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8924,7 +8924,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
/* IVB configs may use multi-threaded forcewake */
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
u32 ecobus;
/* A small trick here - if the bios hasn't configured
MT forcewake,
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/41] drm/i915: add support for SBI ops
With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
v2: de-inline the function and address changes in bits names
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 44 ++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a0e3166..8e5f5be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1220,6 +1220,50 @@ static void intel_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(reg);
}
+/* SBI access */
+static void
+intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
+{
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_DATA,
+ value);
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_BUSY |
+ SBI_CTL_OP_CRWR);
+
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY |
SBI_RESPONSE_SUCCESS)) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to complete write
transaction\n");
+}
+
+static u32
+intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
+{
+ u32 value;
+ if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_BUSY |
+ SBI_CTL_OP_CRRD);
+
+ if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY |
SBI_RESPONSE_SUCCESS)) == 0,
+ 10))
+ DRM_ERROR("timeout waiting for SBI to complete read
transaction\n");
+
+ value = I915_READ(SBI_DATA);
+
+ return value;
+}
+
/**
* intel_enable_pch_pll - enable PCH PLL
* @dev_priv: i915 private structure
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 29/41] drm/i915: show unknown sdvox registers on hdmi init
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..de54c01 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -542,6 +542,8 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+ } else {
+ DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
}
intel_hdmi->sdvox_reg = sdvox_reg;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 40/41] drm/i915: prepare HDMI link for Haswell
On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI.
Note that we do enable the DDI Function for the corresponding pipe, in a
similar fashion as we do with FDI. This ensures that the pipe DDI
transport is left in a almost-ready state, and we only need to enable the
pipe afterwards to get a working modesetting.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 63 -
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 6921756..480f54b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -324,6 +324,67 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder
*encoder,
return true;
}
+static void intel_hdmi_prepare(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ int port = intel_hdmi->ddi_port;
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp;
+
+ /* On Haswell, we need to enable the clocks and prepare DDI function to
+* work in HDMI mode for this pipe.
+*/
+ if (IS_HASWELL(encoder->dev)) {
+ DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c,
pipe %c\n", port_name(port), pipe_name(pipe));
+
+ /* Enable LCPLL if disabled */
+ reg = I915_READ(LCPLL_CTL);
+ if (reg & LCPLL_PLL_DISABLE)
+ I915_WRITE(LCPLL_CTL,
+ reg & ~LCPLL_PLL_DISABLE);
+
+ /* Configure CPU PLL, wait for warmup */
+ I915_WRITE(WRPLL_CTL1,
+ WRPLL_PLL_ENABLE |
+ WRPLL_PLL_SELECT_LCPLL_2700);
+
+ udelay(20);
+
+ /* Use WRPLL1 clock to drive the output to the port, and tell
the pipe to use
+* this port for connection.
+*/
+ I915_WRITE(PORT_CLK_SEL(port),
+ PORT_CLK_SEL_WRPLL1);
+ I915_WRITE(PIPE_CLK_SEL(pipe),
+ PIPE_CLK_SEL_PORT(port));
+
+ udelay(20);
+
+ /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+ temp = I915_READ(DDI_FUNC_CTL(pipe));
+ temp &= ~PIPE_DDI_PORT_MASK;
+ temp |= PIPE_DDI_SELECT_PORT(port) |
+ PIPE_DDI_MODE_SELECT_HDMI |
+ PIPE_DDI_FUNC_ENABLE;
+ I915_WRITE(DDI_FUNC_CTL(pipe),
+ temp);
+
+ /* Enable DDI_BUF_CTL. In HDMI/DVI mode, the port width,
+* and swing/emphasis values are ignored so nothing special
needs
+* to be done besides enabling the port.
+*/
+ I915_WRITE(DDI_BUF_CTL(port),
+ I915_READ(DDI_BUF_CTL(port)) |
+ DDI_BUF_CTL_ENABLE);
+ }
+
+ return intel_encoder_prepare(encoder);
+}
+
static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
@@ -457,7 +518,7 @@ static void intel_hdmi_destroy(struct drm_connector
*connector)
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
.dpms = intel_hdmi_dpms,
.mode_fixup = intel_hdmi_mode_fixup,
- .prepare = intel_encoder_prepare,
+ .prepare = intel_hdmi_prepare,
.mode_set = intel_hdmi_mode_set,
.commit = intel_encoder_commit,
};
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 35/41] drm/i915: disable pipe DDI function when disabling pipe
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09c18f8..0324250 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1475,6 +1475,16 @@ static void intel_disable_pipe(struct drm_i915_private
*dev_priv,
I915_WRITE(reg, val & ~PIPECONF_ENABLE);
intel_wait_for_pipe_off(dev_priv->dev, pipe);
+
+ /* On HSW, disable pipe DDI function the pipe */
+ if (IS_HASWELL(dev_priv->dev)) {
+ val = I915_READ(DDI_FUNC_CTL(pipe));
+ val &= ~PIPE_DDI_PORT_MASK;
+ val &= ~PIPE_DDI_FUNC_ENABLE;
+ I915_WRITE(DDI_FUNC_CTL(pipe),
+ val);
+ }
+
}
/*
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 39/41] drm/i915: add support for DDI-controlled digital outputs
Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index de54c01..6921756 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -41,6 +41,7 @@ struct intel_hdmi {
struct intel_encoder base;
u32 sdvox_reg;
int ddc_bus;
+ int ddi_port;
uint32_t color_range;
bool has_hdmi_sink;
bool has_audio;
@@ -542,6 +543,24 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
+ intel_hdmi->ddi_port = PORT_B;
+ dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
+ intel_hdmi->ddi_port = PORT_C;
+ dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI A\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+ intel_hdmi->ddi_port = PORT_D;
+ dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
} else {
DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
}
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/41] drm/i915: add SFUSE_STRAP registers for digital port detection
DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC and DDID we need to consult SFUSE_STRAP values. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d9df228..f300f5f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4037,4 +4037,11 @@ #define PIPE_WM_LINETIME_TIME(x) ((x)) #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) + +/* SFUSE_STRAP */ +#define SFUSE_STRAP0xc2014 +#define SFUSE_STRAP_DDIB_DETECTED (1<<2) +#define SFUSE_STRAP_DDIC_DETECTED (1<<1) +#define SFUSE_STRAP_DDID_DETECTED (1<<0) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 23/41] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge
Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8e5f5be..5e226ad 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4679,7 +4679,7 @@ void sandybridge_update_wm(struct drm_device *dev) } /* IVB has 3 pipes */ - if (IS_IVYBRIDGE(dev) && + if ((IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) && g4x_compute_wm0(dev, 2, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 28/41] drm/i915: share IVB cursor routine with Haswell
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ea103ca..7daad41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6485,7 +6485,7 @@ static void intel_crtc_update_cursor(struct drm_crtc
*crtc,
if (!visible && !intel_crtc->cursor_visible)
return;
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
I915_WRITE(CURPOS_IVB(pipe), pos);
ivb_update_cursor(crtc, base);
} else {
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 31/41] drm/i915: disable rc6 on haswell for now
This needs proper enablement to avoid machine hangs, so let's just avoid it for now. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0e06a29..b2dc1eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8293,6 +8293,10 @@ static bool intel_enable_rc6(struct drm_device *dev) if (INTEL_INFO(dev)->gen == 5) return 0; + /* Sorry Haswell, no RC6 for you for now. */ + if (IS_HASWELL(dev)) + return 0; + /* * Disable rc6 on Sandybridge */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 36/41] drm/i915: do not use fdi_normal_train on haswell
This should be already configured when FDI auto-negotiation is done. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0324250..dc207e7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3259,7 +3259,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); - intel_fdi_normal_train(crtc); + if (!IS_HASWELL(dev)) + intel_fdi_normal_train(crtc); /* For PCH DP, enable TRANS_DP_CTL */ if (HAS_PCH_CPT(dev) && -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 30/41] drm/i915: enable power wells on haswell init
This attempts to enable all the available power wells during the
initialization.
Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed, but this is out of scope of this initial
enablement. Proper tracking of who uses which power well will require
a considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7daad41..0e06a29 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9173,6 +9173,34 @@ static void i915_disable_vga(struct drm_device *dev)
POSTING_READ(vga_reg);
}
+/* Starting with Haswell, we have different power wells for
+ * different parts of the GPU. This attempts to enable them all.
+ */
+static void intel_init_power_wells(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long power_wells[] = {
+ HSW_PWR_WELL_CTL1,
+ HSW_PWR_WELL_CTL2,
+ HSW_PWR_WELL_CTL4
+ };
+ int i;
+
+ mutex_lock(&dev->struct_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
+ int well = I915_READ(power_wells[i]);
+
+ if ((well & HSW_PWR_WELL_STATE) == 0) {
+ I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
+ if (wait_for(I915_READ(power_wells[i] &
HSW_PWR_WELL_STATE), 20))
+ DRM_ERROR("Error enabling power well %lx\n",
power_wells[i]);
+ }
+ }
+
+ mutex_unlock(&dev->struct_mutex);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9190,6 +9218,9 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
+ if (IS_HASWELL(dev))
+ intel_init_power_wells(dev);
+
intel_init_display(dev);
if (IS_GEN2(dev)) {
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/41] drm/i915: add port clock selection support for HSW
Multiple clocks can drive different outputs. v2: use the port enums to access individual ports v1 Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index db03446..81b076c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3974,4 +3974,27 @@ #define SPLL_PLL_FREQ_810MHz (0<<26) #define SPLL_PLL_FREQ_1350MHz (1<<26) +/* Port clock selection */ +#define PORT_CLK_SEL_A 0x46100 +#define PORT_CLK_SEL_B 0x46104 +#define PORT_CLK_SEL(port) _PORT(port, \ + PORT_CLK_SEL_A, \ + PORT_CLK_SEL_B) +#define PORT_CLK_SEL_LCPLL_2700 (0<<29) +#define PORT_CLK_SEL_LCPLL_1350 (1<<29) +#define PORT_CLK_SEL_LCPLL_810(2<<29) +#define PORT_CLK_SEL_SPLL (3<<29) +#define PORT_CLK_SEL_WRPLL1 (4<<29) +#define PORT_CLK_SEL_WRPLL2 (5<<29) + +/* Pipe clock selection */ +#define PIPE_CLK_SEL_A 0x46140 +#define PIPE_CLK_SEL_B 0x46144 +#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \ + PIPE_CLK_SEL_A, \ + PIPE_CLK_SEL_B) +/* For each pipe, we need to select the corresponding port clock */ +#define PIPE_CLK_SEL_DISABLED (0x0<<29) +#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/41] drm/i915: add definition of LPT FDI port width registers
Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 880c4f7..58fcfae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3475,6 +3475,9 @@ #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) +/* LPT */ +#define LPT_FDI_PORT_WIDTH_1X (0<<19) +#define LPT_FDI_PORT_WIDTH_2X (1<<19) #define _FDI_RXA_MISC0xf0010 #define _FDI_RXB_MISC0xf1010 -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 32/41] drm/i915: program WM_LINETIME on Haswell
The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.
v2: improve comment as per Chris Wilson suggestion
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b2dc1eb..72f2211 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6103,6 +6103,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
+ if (IS_HASWELL(dev)) {
+ temp = I915_READ(PIPE_WM_LINETIME(pipe));
+ temp &= ~PIPE_WM_LINETIME_MASK;
+
+ /* The WM are computed with base on how long it takes to fill a
single
+* row at the given clock rate
+* */
+ temp |= PIPE_WM_LINETIME_TIME(
+ adjusted_mode->crtc_hdisplay /
+ (adjusted_mode->clock / 1000));
+ I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
+ }
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 38/41] drm/i915: detect digital outputs on Haswell
Digital port detection on Haswell is indicated by the presence of a bit in
DDI_BUF_CTL for port A, and by a different register for ports B, C and D.
So we check for those bits during the initialization time and let the hdmi
function know about those.
Note that this bit does not indicates whether the output is DP or HDMI.
However, the DDI buffers can be programmed in a way that is shared between
DP/HDMI and FDI/HDMI except for PORT E.
So for now, we detect those digital outputs as being HDMI, but proper DP
support is still pending.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 50 +++---
1 file changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5aaf592..c457592 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8372,26 +8372,44 @@ static void intel_setup_outputs(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev)) {
int found;
- if (I915_READ(HDMIB) & PORT_DETECTED) {
- /* PCH SDVOB multiplex with HDMIB */
- found = intel_sdvo_init(dev, PCH_SDVOB);
- if (!found)
- intel_hdmi_init(dev, HDMIB);
- if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
- intel_dp_init(dev, PCH_DP_B);
- }
+ if (IS_HASWELL(dev)) {
+ /* Haswell uses DDI functions to detect digital outputs
*/
+ found = I915_READ(DDI_BUF_CTL_A) &
DDI_INIT_DISPLAY_DETECTED;
+ if (found)
+ intel_hdmi_init(dev, DDI_BUF_CTL_A);
+
+ /* DDI B, C and D detection is indicated by the
SFUSE_STRAP
+* register */
+ found = I915_READ(SFUSE_STRAP);
+
+ if (found & SFUSE_STRAP_DDIB_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_B));
+ if (found & SFUSE_STRAP_DDIC_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_C));
+ if (found & SFUSE_STRAP_DDID_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_D));
+ } else {
+ if (I915_READ(HDMIB) & PORT_DETECTED) {
+ /* PCH SDVOB multiplex with HDMIB */
+ found = intel_sdvo_init(dev, PCH_SDVOB);
+ if (!found)
+ intel_hdmi_init(dev, HDMIB);
+ if (!found && (I915_READ(PCH_DP_B) &
DP_DETECTED))
+ intel_dp_init(dev, PCH_DP_B);
+ }
- if (I915_READ(HDMIC) & PORT_DETECTED)
- intel_hdmi_init(dev, HDMIC);
+ if (I915_READ(HDMIC) & PORT_DETECTED)
+ intel_hdmi_init(dev, HDMIC);
- if (I915_READ(HDMID) & PORT_DETECTED)
- intel_hdmi_init(dev, HDMID);
+ if (I915_READ(HDMID) & PORT_DETECTED)
+ intel_hdmi_init(dev, HDMID);
- if (I915_READ(PCH_DP_C) & DP_DETECTED)
- intel_dp_init(dev, PCH_DP_C);
+ if (I915_READ(PCH_DP_C) & DP_DETECTED)
+ intel_dp_init(dev, PCH_DP_C);
- if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
- intel_dp_init(dev, PCH_DP_D);
+ if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
+ intel_dp_init(dev, PCH_DP_D);
+ }
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
--
1.7.9.5
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/41] drm/i915: add definition of DDI buffer translations regs
Those registers are used to train DDI buffer translations for each link type. v2: access each port registers through the DDI_BUF_TRANS macro Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ef99df3..880c4f7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3938,4 +3938,11 @@ #define DDI_PORT_WIDTH_X4 (3<<1) #define DDI_INIT_DISPLAY_DETECTED (1<<0) +/* DDI Buffer Translations */ +#define DDI_BUF_TRANS_A0x64E00 +#define DDI_BUF_TRANS_B0x64E60 +#define DDI_BUF_TRANS(port) _PORT(port, \ + DDI_BUF_TRANS_A, \ + DDI_BUF_TRANS_B) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/41] drm/i915: haswell has 3 pipes as well
They work differently, but the count is the same. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_dma.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index fdff009..1fb7beb 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -2089,7 +2089,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) spin_lock_init(&dev_priv->error_lock); spin_lock_init(&dev_priv->rps_lock); - if (IS_IVYBRIDGE(dev)) + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) dev_priv->num_pipe = 3; else if (IS_MOBILE(dev) || !IS_GEN2(dev)) dev_priv->num_pipe = 2; -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/41] drm/i915: add WM_LINETIME registers
Watermark line time registers for display low power watermark. v2: improve bit names as suggested by Chris Wilson Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7b6754d..d9df228 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4027,4 +4027,14 @@ #define LCPLL_CD_CLOCK_DISABLE(1<<25) #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) +/* Pipe WM_LINETIME - watermark line time */ +#define PIPE_WM_LINETIME_A 0x45270 +#define PIPE_WM_LINETIME_B 0x45274 +#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \ + PIPE_WM_LINETIME_A, \ + PIPE_WM_LINETIME_A) +#define PIPE_WM_LINETIME_MASK(0x1ff) +#define PIPE_WM_LINETIME_TIME(x) ((x)) +#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) +#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/41] drm/i915: add WRPLL clocks
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP and FDI. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fc24229..7b6754d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3989,6 +3989,14 @@ #define SPLL_PLL_FREQ_810MHz (0<<26) #define SPLL_PLL_FREQ_1350MHz (1<<26) +/* WRPLL */ +#define WRPLL_CTL1 0x46040 +#define WRPLL_CTL2 0x46060 +#define WRPLL_PLL_ENABLE (1<<31) +#define WRPLL_PLL_SELECT_SSC (0x01<<28) +#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) +#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) + /* Port clock selection */ #define PORT_CLK_SEL_A 0x46100 #define PORT_CLK_SEL_B 0x46104 -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 41/41] drm/i915: add debugging bits for haswell modesetting
-- THIS PATCH IS NOT INTENDED FOR MERGING. IT IS MERELY HERE TO SIMPLIFY
THE DEBUGGING --
This patch is here for make debugging and log tracing easier, it should
go away in the future, when we'll stop hitting those code paths.
v2: cope with changes in bit names
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |2 ++
drivers/gpu/drm/i915/intel_display.c | 61 +++---
2 files changed, 51 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e4b5571..8ef2512 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1036,6 +1036,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32
reg) { \
val = read##y(dev_priv->regs + reg); \
} \
trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+ DRM_DEBUG("I915_READ: 0x%x = 0x%x\n", reg, val); \
return val; \
}
@@ -1048,6 +1049,7 @@ __i915_read(64, q)
#define __i915_write(x, y) \
void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
u32 __fifo_ret = 0; \
+ DRM_DEBUG("I915_WRITE: 0x%x = 0x%x\n", reg, val); \
trace_i915_reg_rw(true, reg, val, sizeof(val)); \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c457592..82afc8a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -869,9 +869,16 @@ static void assert_fdi_tx(struct drm_i915_private
*dev_priv,
u32 val;
bool cur_state;
- reg = FDI_TX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_TX_ENABLE);
+ if (IS_HASWELL(dev_priv->dev)) {
+ DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI
instead\n");
+ reg = DDI_FUNC_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+ } else {
+ reg = FDI_TX_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & FDI_TX_ENABLE);
+ }
WARN(cur_state != state,
"FDI TX state assertion failure (expected %s, current %s)\n",
state_string(state), state_string(cur_state));
@@ -886,9 +893,14 @@ static void assert_fdi_rx(struct drm_i915_private
*dev_priv,
u32 val;
bool cur_state;
- reg = FDI_RX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_RX_ENABLE);
+ if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+ DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe
> 0\n");
+ return;
+ } else {
+ reg = FDI_RX_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & FDI_RX_ENABLE);
+ }
WARN(cur_state != state,
"FDI RX state assertion failure (expected %s, current %s)\n",
state_string(state), state_string(cur_state));
@@ -906,6 +918,11 @@ static void assert_fdi_tx_pll_enabled(struct
drm_i915_private *dev_priv,
if (dev_priv->info->gen == 5)
return;
+ if (IS_HASWELL(dev_priv->dev)) {
+ DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell,
aborting\n");
+ return;
+ }
+
reg = FDI_TX_CTL(pipe);
val = I915_READ(reg);
WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should
be active but is disabled\n");
@@ -917,6 +934,10 @@ static void assert_fdi_rx_pll_enabled(struct
drm_i915_private *dev_priv,
int reg;
u32 val;
+ if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+ DRM_ERROR("Attempting to enable FDI on Haswell with pipe >
0\n");
+ return;
+ }
reg = FDI_RX_CTL(pipe);
val = I915_READ(reg);
WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should
be active but is disabled\n");
@@ -1022,6 +1043,11 @@ static void assert_pch_refclk_enabled(struct
drm_i915_private *dev_priv)
u32 val;
bool enabled;
+ if (HAS_PCH_LPT(dev_priv->dev)) {
+ DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
+ return;
+ }
+
val = I915_READ(PCH_DREF_CONTROL);
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1236,6 +1262,7 @@ intel_sbi_write(struct drm_i915_private *dev_priv, u16
reg, u32 value)
SBI_BUSY |
SBI_CTL_OP_CRWR);
+ DRM_DEBUG(&quo
[Intel-gfx] [PATCH 10/41] drm/i915: add definitions for DDI_BUF_CTL registers
There is one instance of those registers for each DDI port. v2: access registers via the DDI_BUF_CTL() macro Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 666e319..ef99df3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3915,4 +3915,27 @@ DP_TP_STATUS_B) #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) +/* DDI Buffer Control */ +#define DDI_BUF_CTL_A 0x64000 +#define DDI_BUF_CTL_B 0x64100 +#define DDI_BUF_CTL(port) _PORT(port, \ + DDI_BUF_CTL_A, \ + DDI_BUF_CTL_B) +#define DDI_BUF_CTL_ENABLE(1<<31) +#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ +#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */ +#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */ +#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */ +#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */ +#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */ +#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */ +#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */ +#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */ +#define DDI_BUF_EMP_MASK (0xf<<24) +#define DDI_BUF_IS_IDLE (1<<7) +#define DDI_PORT_WIDTH_X1 (0<<1) +#define DDI_PORT_WIDTH_X2 (1<<1) +#define DDI_PORT_WIDTH_X4 (3<<1) +#define DDI_INIT_DISPLAY_DETECTED (1<<0) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/41] drm/i915: add S PLL control
This PLL control can drive DDI ports at desired frequencies for DisplayPort and FDI connections. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 48346ad..db03446 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3966,4 +3966,12 @@ #define PIXCLK_GATE_UNGATE1<<0 #define PIXCLK_GATE_GATE 0<<0 +/* SPLL */ +#define SPLL_CTL 0x46020 +#define SPLL_PLL_ENABLE (1<<31) +#define SPLL_PLL_SCC (1<<28) +#define SPLL_PLL_NON_SCC (2<<28) +#define SPLL_PLL_FREQ_810MHz (0<<26) +#define SPLL_PLL_FREQ_1350MHz (1<<26) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 37/41] drm/i915: program iCLKIP on Lynx Point
The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.
Those values can be programmed individually, by doing some math; or we
could use a pre-defined table of values for each modeset. For speed and
simplification, the idea was to just adopt the table of valid pixel clocks
and select the matching iCLKIP values from there.
As a possible idea for the future, it would be possible to add a fallback
and calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 309 ++
1 file changed, 309 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dc207e7..5aaf592 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2830,6 +2830,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
DDI_BUF_EMP_800MV_3_5DB_HSW
};
+/* Available pixel clock values */
+struct iclk_vga_clock {
+ u32 clock;
+ u16 auxdiv;
+ u16 divsel;
+ u16 phasedir;
+ u16 phaseinc;
+};
+
+static const struct iclk_vga_clock iclk_vga_clock_table[] = {
+ {2, 1, 0x41, 0, 0x20}, /* 2 ppm=0 */
+ {21000, 0, 0x7E, 0, 0x25}, /* 20999 ppm=-53 */
+ {21912, 0, 0x79, 0, 0x0E}, /* 21912 ppm=12 */
+ {22000, 0, 0x78, 0, 0x2F}, /* 21999 ppm=-58 */
+ {23000, 0, 0x73, 0, 0x19}, /* 23000 ppm=6 */
+ {24000, 0, 0x6E, 0, 0x20}, /* 24000 ppm=0 */
+ {25000, 0, 0x6A, 0, 0x00}, /* 25000 ppm=0 */
+ {25175, 0, 0x69, 0, 0x10}, /* 25175 ppm=-7 */
+ {25200, 0, 0x69, 0, 0x09}, /* 25201 ppm=21 */
+ {26000, 0, 0x66, 1, 0x0A}, /* 26001 ppm=24 */
+ {27000, 0, 0x62, 0, 0x00}, /* 27000 ppm=0 */
+ {27027, 0, 0x62, 1, 0x06}, /* 27025 ppm=-62 */
+ {27500, 0, 0x60, 0, 0x0C}, /* 27498 ppm=-58 */
+ {28000, 0, 0x5E, 0, 0x1B}, /* 28002 ppm=70 */
+ {28320, 0, 0x5D, 0, 0x16}, /* 28319 ppm=-50 */
+ {28322, 0, 0x5D, 0, 0x15}, /* 28323 ppm=44 */
+ {29000, 0, 0x5B, 0, 0x07}, /* 28998 ppm=-64 */
+ {3, 0, 0x58, 0, 0x00}, /* 3 ppm=0 */
+ {31000, 0, 0x55, 0, 0x06}, /* 31001 ppm=35 */
+ {31500, 0, 0x54, 1, 0x12}, /* 31498 ppm=-53 */
+ {32000, 0, 0x52, 0, 0x18}, /* 32000 ppm=0 */
+ {32500, 0, 0x51, 0, 0x05}, /* 32500 ppm=-15 */
+ {33000, 0, 0x50, 1, 0x0C}, /* 33002 ppm=70 */
+ {34000, 0, 0x4D, 0, 0x1A}, /* 34002 ppm=70 */
+ {35000, 0, 0x4B, 0, 0x09}, /* 35001 ppm=29 */
+ {35500, 0, 0x4A, 0, 0x04}, /* 35497 ppm=-82 */
+ {36000, 0, 0x49, 0, 0x00}, /* 36000 ppm=0 */
+ {37000, 0, 0x47, 1, 0x02}, /* 37002 ppm=58 */
+ {38000, 0, 0x45, 0, 0x03}, /* 38003 ppm=82 */
+ {39000, 0, 0x43, 0, 0x0F}, /* 38998 ppm=-53 */
+ {4, 0, 0x41, 0, 0x20}, /* 4 ppm=0 */
+ {40500, 0, 0x41, 1, 0x15}, /* 40497 ppm=-79 */
+ {40541, 0, 0x41, 1, 0x1A}, /* 40544 ppm=95 */
+ {41000, 0, 0x40, 1, 0x09}, /* 40996 ppm=-87 */
+ {41540, 0, 0x3F, 0, 0x00}, /* 41538 ppm=-38 */
+ {42000, 0, 0x3E, 0, 0x12}, /* 42003 ppm=70 */
+ {43000, 0, 0x3D, 1, 0x0D}, /* 42996 ppm=-99 */
+ {43163, 0, 0x3D, 1, 0x1D}, /* 43168 ppm=108 */
+ {44000, 0, 0x3B, 0, 0x17}, /* 44003 ppm=70 */
+ {44900, 0, 0x3A, 0, 0x09}, /* 44895 ppm=-117 */
+ {45000, 0, 0x3A, 0, 0x00}, /* 45000 ppm=0 */
+ {46000, 0, 0x39, 1, 0x13}, /* 45994 ppm=-128 */
+ {47000, 0, 0x37, 0, 0x1D}, /* 46995 ppm=-110 */
+ {48000, 0, 0x36, 0, 0x10}, /* 48000 ppm=0 */
+ {49000, 0, 0x35, 0, 0x07}, /* 48993 ppm=-134 */
+ {49500, 0, 0x35, 1, 0x1D}, /* 49499 ppm=-27 */
+ {5, 0, 0x34, 0, 0x00}, /* 5 ppm=0 */
+ {51000, 0, 0x33, 1, 0x04}, /* 51004 ppm=70 */
+ {52000, 0, 0x32, 1, 0x05}, /* 52001 ppm=24 */
+ {52406, 0, 0x32, 1, 0x1F}, /* 52411 ppm=101 */
+ {53000, 0, 0x31, 1, 0x04}, /* 53006 ppm=116 */
+ {54000, 0, 0x30, 0, 0x00}, /* 54000 ppm=0 */
+
[Intel-gfx] [PATCH 15/41] drm/i915: add PIXCLK_GATE register
Pixel clock gating control for Lynx point. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d6c0e36..48346ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3960,4 +3960,10 @@ #define SBI_RESPONSE_SUCCESS (0x0<<1) #define SBI_BUSY (0x1<<0) #define SBI_READY (0x0<<0) + +/* LPT PIXCLK_GATE */ +#define PIXCLK_GATE0xC6020 +#define PIXCLK_GATE_UNGATE1<<0 +#define PIXCLK_GATE_GATE 0<<0 + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/41] drm/i915: add SSC offsets for SBI access
Different registers are identified by their target id and offset. To simplify their programming, they are called as . For example, SSCCTL register accessed through SBI at target id 6 and offset 0c is called SBI_SSCCTL6. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81b076c..b7eca0c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3961,6 +3961,21 @@ #define SBI_BUSY (0x1<<0) #define SBI_READY (0x0<<0) +/* SBI offsets */ +#define SBI_SSCDIVINTPHASE6 0x0600 +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) +#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) +#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) +#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) +#define SBI_SSCDIVINTPHASE_DIR(x)((x)<<15) +#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) +#define SBI_SSCCTL0x020c +#define SBI_SSCCTL6 0x060C +#define SBI_SSCCTL_DISABLE (1<<0) +#define SBI_SSCAUXDIV60x0610 +#define SBI_SSCAUXDIV_FINALDIV2SEL(x)((x)<<4) +#define SBI_DBUFF00x2a00 + /* LPT PIXCLK_GATE */ #define PIXCLK_GATE0xC6020 #define PIXCLK_GATE_UNGATE1<<0 -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 27/41] drm/i915: share pipe count handling with Ivybridge
Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1484195..ea103ca 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2330,7 +2330,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, case 1: break; case 2: - if (IS_IVYBRIDGE(dev)) + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) break; /* fall through otherwise */ default: -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/41] drm/i915: add LCPLL control registers
Those are used to control the display core clock. v2: change the enable bit setting, spotted by Rodrigo Vivi. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b7eca0c..fc24229 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4012,4 +4012,11 @@ #define PIPE_CLK_SEL_DISABLED (0x0<<29) #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) +/* LCPLL Control */ +#define LCPLL_CTL 0x130040 +#define LCPLL_PLL_DISABLE (1<<31) +#define LCPLL_PLL_LOCK(1<<30) +#define LCPLL_CD_CLOCK_DISABLE(1<<25) +#define LCPLL_CD2X_CLOCK_DISABLE (1<<23) + #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 33/41] drm/i915: initialize DDI buffer translations
Buffer translations for DDI links must be initialized prior to enablement.
For FDI and DP, first 9 pairs of values are used to select the connection
parameters. HDMI uses the last pair of values and ignores the first 9
pairs. So we program HDMI values in both cases, which allows HDMI to work
over both FDI and DP-friendly buffers.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 84 +-
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 72f2211..1fdcd56 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2728,6 +2728,86 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
DRM_DEBUG_KMS("FDI train done.\n");
}
+/* HDMI/DVI modes ignore everything but the last 2 items. So we share
+ * them for both DP and FDI transports, allowing those ports to
+ * automatically adapt to HDMI connections as well
+ */
+static const long hsw_ddi_translations_dp[] = {
+ 0x00FF, 0x0006000E,
+ 0x00D75FFF, 0x0005000A,
+ 0x00C30FFF, 0x00040006,
+ 0x80AAAFFF, 0x000B,
+ 0x00FF, 0x0005000A,
+ 0x00D75FFF, 0x000C0004,
+ 0x80C30FFF, 0x000B,
+ 0x00FF, 0x00040006,
+ 0x80D75FFF, 0x000B,
+ 0x00FF, 0x00040006
+};
+
+static const long hsw_ddi_translations_fdi[] = {
+ 0x00FF, 0x0007000E,
+ 0x00D75FFF, 0x000F000A,
+ 0x00C30FFF, 0x00060006,
+ 0x00AAAFFF, 0x001E,
+ 0x00FF, 0x000F000A,
+ 0x00D75FFF, 0x00160004,
+ 0x00C30FFF, 0x001E,
+ 0x00FF, 0x00060006,
+ 0x00D75FFF, 0x001E,
+ 0x00FF, 0x00040006
+};
+
+/* On Haswell, DDI port buffers must be programmed with correct values
+ * in advance. The buffer values are different for FDI and DP modes,
+ * but the HDMI/DVI fields are shared among those. So we program the DDI
+ * in either FDI or DP modes only, as HDMI connections will work with both
+ * of those
+ */
+void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool
use_fdi_mode)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 reg;
+ int i, j;
+
+ DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
+ port_name(port),
+ use_fdi_mode ? "FDI" : "DP");
+
+ WARN((use_fdi_mode && (port != PORT_E)),
+ "Programming port %c in FDI mode, this probably will not
work.\n",
+ port_name(port));
+
+ /* Those registers seem to be double-buffered, so write them twice */
+ for (j=0; j < 2; j++) {
+ for (i=0, reg=DDI_BUF_TRANS(port); i <
ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+ I915_WRITE(reg,
+ (use_fdi_mode) ?
+ hsw_ddi_translations_fdi[i] :
+ hsw_ddi_translations_dp[i]);
+ reg += 4;
+ }
+ udelay(20);
+ }
+}
+
+/* Program DDI buffers translations for DP. By default, program ports A-D in DP
+ * mode and port E for FDI.
+ */
+static void intel_hsw_prepare_ddi_buffers(struct drm_device *dev)
+{
+ int port;
+
+ for (port = PORT_A; port < PORT_E; port++)
+ hsw_prepare_ddi_buffers(dev, port, false);
+
+ /* DDI E is the suggested one to work in FDI mode, so program is as
such by
+* default. It will have to be re-programmed in case a digital DP output
+* will be detected on it
+*/
+ hsw_prepare_ddi_buffers(dev, PORT_E, true);
+}
+
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
@@ -9235,8 +9315,10 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev)) {
intel_init_power_wells(dev);
+ intel_hsw_prepare_ddi_buffers(dev);
+ }
intel_init_display(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9cec6c3..ef1d4ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -407,6 +407,7 @@ extern void intel_init_clock_gating(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
+extern void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port,
bool use_fdi_mode);
/* For use by IVB LP watermark workaround in intel_sprite.c */
extern void sandybridge_update_wm(struct drm_device *dev);
[Intel-gfx] [PATCH 34/41] drm/i915: perform Haswell DDI link training in FDI mode
This patch attempts at following the modeset sequence closely, retrying
with different voltages if the DP_TP_STATUS reports a failed training.
For training, we add a table of recommended settings for FDI, HDMI and DP
connections. For FDI and DP modes, we also add the HDMI buffer
translation as the last item. Those are ignored in such modes, so there is
no harm in having them set.
Initially, we use DDI E for FDI connectivity. This is the suggested
configuration, and this seems to be what should work the best with FDI.
Note that we leave the DDI Function for corresponding pipe active when we
are done with the training. This ensures that we only need to enable pipe
afterwards to get a working modesetting, in a similar fashion as on
pre-HSW hardware. The modeset disabling sequence mentions a correct order
of disabling things, but this is out of scope of this patch and is being
done separately, for clearer distinction of what happens when.
v2: improve comments a bit, use PORT enums instead of hardcoded PORT_E
registers, split DDI buffers programming into a separate patch.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 118 ++
1 file changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1fdcd56..09c18f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2808,6 +2808,113 @@ static void intel_hsw_prepare_ddi_buffers(struct
drm_device *dev)
hsw_prepare_ddi_buffers(dev, PORT_E, true);
}
+static const long hsw_ddi_buf_ctl_values[] = {
+ DDI_BUF_EMP_400MV_0DB_HSW,
+ DDI_BUF_EMP_400MV_3_5DB_HSW,
+ DDI_BUF_EMP_400MV_6DB_HSW,
+ DDI_BUF_EMP_400MV_9_5DB_HSW,
+ DDI_BUF_EMP_600MV_0DB_HSW,
+ DDI_BUF_EMP_600MV_3_5DB_HSW,
+ DDI_BUF_EMP_600MV_6DB_HSW,
+ DDI_BUF_EMP_800MV_0DB_HSW,
+ DDI_BUF_EMP_800MV_3_5DB_HSW
+};
+
+
+/* Link training for HSW parts */
+static void hsw_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp, i;
+
+ /* Configure CPU PLL, wait for warmup */
+ I915_WRITE(SPLL_CTL,
+ SPLL_PLL_ENABLE |
+ SPLL_PLL_FREQ_1350MHz |
+ SPLL_PLL_SCC);
+
+ /* Use SPLL to drive the output when in FDI mode */
+ I915_WRITE(PORT_CLK_SEL(PORT_E),
+ PORT_CLK_SEL_SPLL);
+ I915_WRITE(PIPE_CLK_SEL(pipe),
+ PIPE_CLK_SEL_PORT(PORT_E));
+
+ udelay(20);
+
+ /* Start the training iterating through available voltages and emphasis
*/
+ for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
+ /* Configure DP_TP_CTL with auto-training */
+ I915_WRITE(DP_TP_CTL(PORT_E),
+ DP_TP_CTL_FDI_AUTOTRAIN |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_PAT1 |
+ DP_TP_CTL_ENABLE);
+
+ /* Configure and enable DDI_BUF_CTL for DDI E with next voltage
*/
+ temp = I915_READ(DDI_BUF_CTL(PORT_E));
+ temp = (temp & ~DDI_BUF_EMP_MASK);
+ I915_WRITE(DDI_BUF_CTL(PORT_E),
+ temp |
+ DDI_BUF_CTL_ENABLE |
+ DDI_PORT_WIDTH_X2 |
+ hsw_ddi_buf_ctl_values[i]);
+
+ udelay(600);
+
+ /* Enable CPU FDI Receiver with auto-training */
+ reg = FDI_RX_CTL(pipe);
+ I915_WRITE(reg,
+ I915_READ(reg) |
+ FDI_LINK_TRAIN_AUTO |
+ FDI_RX_ENABLE |
+ FDI_LINK_TRAIN_PATTERN_1_CPT |
+ FDI_RX_ENHANCE_FRAME_ENABLE |
+ LPT_FDI_PORT_WIDTH_2X |
+ FDI_RX_PLL_ENABLE);
+ POSTING_READ(reg);
+ udelay(100);
+
+ temp = I915_READ(DP_TP_STATUS(PORT_E));
+ if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
+ DRM_INFO("BUF_CTL training done on %d step\n", i);
+
+ /* Enable normal pixel sending for FDI */
+ I915_WRITE(DP_TP_CTL(PORT_E),
+ DP_TP_CTL_FDI_AUTOTRAIN |
+ DP_TP_CTL_LINK_TRAIN_NORMAL |
+ D
[Intel-gfx] [PATCH 13/41] drm/i915: add SBI registers
Those are responsible for the Sideband Interface programming. v2: rename SBI bits to better reflect their meaning Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58fcfae..d6c0e36 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3948,4 +3948,16 @@ DDI_BUF_TRANS_A, \ DDI_BUF_TRANS_B) +/* Sideband Interface (SBI) is programmed indirectly, via + * SBI_ADDR, which contains the register offset; and SBI_DATA, + * which contains the payload */ +#define SBI_ADDR 0xC6000 +#define SBI_DATA 0xC6004 +#define SBI_CTL_STAT 0xC6008 +#define SBI_CTL_OP_CRRD (0x6<<8) +#define SBI_CTL_OP_CRWR (0x7<<8) +#define SBI_RESPONSE_FAIL (0x1<<1) +#define SBI_RESPONSE_SUCCESS (0x0<<1) +#define SBI_BUSY (0x1<<0) +#define SBI_READY (0x0<<0) #endif /* _I915_REG_H_ */ -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: add Ivy Bridge GT2 Server entries
This adds PCI ID for IVB GT2 server variant which we were missing.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.h|1 +
drivers/char/agp/intel-gtt.c|2 ++
drivers/gpu/drm/i915/i915_drv.c |1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 0b07101..c009175 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -235,6 +235,7 @@
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /*
Desktop */
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 7e223a2..936ca69 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1486,6 +1486,8 @@ static const struct intel_gtt_driver_description {
"Ivybridge", &sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
"Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
"ValleyView", &valleyview_gtt_driver },
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0efc02e..85900dd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -340,6 +340,7 @@ static const struct pci_device_id pciidlist[] = {
/* aka */
INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+ INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
{0, 0, 0}
};
--
1.7.9.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] intel: add Ivy Bridge GT2 server variant
From: Eugeni Dodonov We were missing this one and it is being used by Bromolow. Signed-off-by: Eugeni Dodonov --- intel/intel_chipset.h |4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 435d01a..9c1abc8 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -44,6 +44,7 @@ #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ +#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ #define PCI_CHIP_HASWELL_GT10x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT20x0412 @@ -128,7 +129,8 @@ dev == PCI_CHIP_IVYBRIDGE_GT2 || \ dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \ dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \ -dev == PCI_CHIP_IVYBRIDGE_S) +dev == PCI_CHIP_IVYBRIDGE_S || \ +dev == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ devid == PCI_CHIP_HASWELL_M_GT1) -- 1.7.9.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] intel_driver: add support for Ivy Bridge GT2 Server chipset
This is the GT2 variant of Ivy Bridge server chip.
Signed-off-by: Eugeni Dodonov
---
src/intel_driver.h |1 +
src/intel_module.c |2 ++
2 files changed, 3 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h
index e9d6d9e..98973e5 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -190,6 +190,7 @@
#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
+#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
#endif
diff --git a/src/intel_module.c b/src/intel_module.c
index 2c0e5cc..c6f94f5 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -142,6 +142,7 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_IVYBRIDGE_D_GT1, "Ivybridge Desktop (GT1)" },
{PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
{PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
+ {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" },
{-1,NULL}
};
#define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0]))
@@ -210,6 +211,7 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
{ 0, 0, 0 },
};
--
1.7.9.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Video tearing on Sandybridge
On Mon, Apr 2, 2012 at 08:30, Oliver Seitz wrote: > > Video tearing in windows is a known issue on SandyBridge >> > > And also on IvyBridge, I presume. Then I'll try to be patient until > there's a new implementation of vsynced update logic in the driver :-) > There are some improvements on the next one after that though :). But the real fix for SNB/IVB depends on the DERRMR implementation which we could not get to work without nasty side effects on Sandy Bridge yet (such as hangs). Jesse has sent something in this sense for Ivy Bridge in his '[Intel-gfx] Scanline wait hack for IVB' patch, so hope is not lost yet. There is a huge thread about this on the https://bugs.freedesktop.org/show_bug.cgi?id=37686 bug as well. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] intel/decode: decode MI_WAIT_FOR_EVENT
On Mon, Apr 2, 2012 at 08:08, Daniel Vetter wrote:
> ... and add support to decode MI instructions with functions.
>
> Signed-Off-by: Daniel Vetter
>
---
> intel/intel_decode.c | 77
> -
> 1 files changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/intel/intel_decode.c b/intel/intel_decode.c
> index df9b704..4141f9e 100644
> --- a/intel/intel_decode.c
> +++ b/intel/intel_decode.c
> @@ -139,6 +139,74 @@ instr_out(struct drm_intel_decode *ctx, unsigned int
> index,
> }
>
> static int
> +decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx)
> +{
> + if (ctx->gen <= 5) {
> + instr_out(ctx, 0,
> "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
> + data & (1<<18)? ", pipe B start vblank wait": "",
> + data & (1<<17)? ", pipe A start vblank wait": "",
> + data & (1<<16)? ", overlay flip pending wait":
> "",
> + data & (1<<14)? ", pipe B hblank wait": "",
> + data & (1<<13)? ", pipe A hblank wait": "",
> + cc_wait,
> + data & (1<<8)? ", plane C pending flip wait": "",
> + data & (1<<7)? ", pipe B vblank wait": "",
> + data & (1<<6)? ", plane B pending flip wait": "",
> + data & (1<<5)? ", pipe B scan line wait": "",
> + data & (1<<4)? ", fbc idle wait": "",
> + data & (1<<3)? ", pipe A vblank wait": "",
> + data & (1<<2)? ", plane A pending flip wait": "",
> + data & (1<<1)? ", plane A scan linscan line":
> "");
>
Shouldn't it be "plane A scan line wait"?
> + } else {
> + instr_out(ctx, 0,
> "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
> + data & (1<<20)? ", prite C pending flip wait":
> "", /* ivb */
>
s/prite/sprite/.
The only major question I have about this is if we should add the other
IVB-specific fields as well, besides the (1<<20) one.
Other than that,
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Finish any pending operations on the framebuffer before disabling
On Tue, Apr 3, 2012 at 13:58, Chris Wilson wrote: > + /* Flush any pending WAITs before we disable the pipe. Note that > +* we need to drop the struct_mutex in order to acquire it again > +* during the lowlevel dpms routines around a couple of the > +* operations. It does not look trivial nor desirable to move > +* that lokcing higher. So instead we leave a window for the > *locking Reviewed-by: Eugeni Dodonov -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fixed VS thread distribution between slices
On Tue, Apr 10, 2012 at 01:10, Ben Widawsky wrote: > +#define GEN7_FF_THREAD_MODE0x20a0 +#define GEN7_FF_THREAD_SIMPLE_SCHED0x28a00010 > Would it be too much asking you to check with the 0x28a0 value as well please, and with a patch which only cleans the bit 12 and 4? I think we don't need to write the entire pre-defined message here, only those 2 bits seem to matter in this case.. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/29] Haswell round 3
Hi forks, Just in time for everyone's weekend, here comes the 3rd round of patches on Haswell. As major highlights, it also adds support for HDMI/DVI outputs and multi-head modes (I tried with VGA and HDMI). Other than that, it is the same patches with comments from the past round addressed (SBI locking support, proper WM calculation, better PCH items detection, and so on). Daniel, I think that the bits definitions, power wells, clocks programming, and modesetting for both FDI and HDMI modes should be good to go unless someone spots additional issues with them - so please, all of you who have something to say about them, say it now and bikeshed as you please :). Note that the DP and eDP modesetting support is not there yet - it will still require a considerable amount of patches. Also, there is one patch which fixes null pointer exceptions in gmbus code I was having with some of the drm-intel-next-queued iterations, but I don't think it is necessary at the moment now that gmbus stuff was disabled again (patch 5). I am not even sure if we'll hit those code paths with invalid values in real life, so I simple added some checks for cases when we don't have a valid adapter as it was looking too error-prone otherwise. Perhaps we could add a WARN into them as well. Eugeni Dodonov (29): drm/i915: add definition of LPT FDI port width registers drm/i915: add WRPLL divider programming bits drm/i915: add Haswell DIP controls registers drm/i915: support infoframes on Haswell drm/i915: prevent NULL pointer exception when using gmbus drm/i915: add support for SBI ops drm/i915: calculate same watermarks on Haswell as on Ivy Bridge drm/i915: share forcewaking code between IVB and HSW drm/i915: haswell has 3 pipes as well drm/i915: reuse Ivybridge interrupts code for Haswell drm/i915: share pipe count handling with Ivybridge drm/i915: share IVB cursor routine with Haswell drm/i915: show unknown sdvox registers on hdmi init drm/i915: do not use fdi_normal_train on haswell drm/i915: do not enable PCH PLL on pre-haswell drm/i915: detect PCH encoders on Haswell drm/i915: enable power wells on haswell init drm/i915: disable rc6 on haswell for now drm/i915: program WM_LINETIME on Haswell drm/i915: do not use old code paths on Haswell drm/i915: initialize DDI buffer translations drm/i915: perform Haswell DDI link training in FDI mode drm/i915: disable pipe DDI function when disabling pipe drm/i915: program iCLKIP on Lynx Point drm/i915: detect digital outputs on Haswell drm/i915: add support for DDI-controlled digital outputs drm/i915: add WR PLL programming table drm/i915: prepare HDMI link for Haswell drm/i915: hook Haswell devices in place drivers/char/agp/intel-agp.c |4 + drivers/gpu/drm/i915/i915_dma.c |2 +- drivers/gpu/drm/i915/i915_drv.c |7 + drivers/gpu/drm/i915/i915_irq.c |6 +- drivers/gpu/drm/i915/i915_reg.h | 23 + drivers/gpu/drm/i915/intel_display.c | 763 -- drivers/gpu/drm/i915/intel_drv.h |1 + drivers/gpu/drm/i915/intel_hdmi.c| 602 ++- 8 files changed, 1357 insertions(+), 51 deletions(-) -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/29] drm/i915: add definition of LPT FDI port width registers
v2: change bits names to align better with other bits style Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 972321f..98579f5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3648,6 +3648,9 @@ #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) +/* LPT */ +#define FDI_PORT_WIDTH_2X_LPT (1<<19) +#define FDI_PORT_WIDTH_1X_LPT (0<<19) #define _FDI_RXA_MISC0xf0010 #define _FDI_RXB_MISC0xf1010 -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/29] drm/i915: add WRPLL divider programming bits
Those are used to program the WRPLL dividers correctly for each gives frequency. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 98579f5..05d98f2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4178,6 +4178,10 @@ #define WRPLL_PLL_SELECT_SSC (0x01<<28) #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) +/* WRPLL divider programming */ +#define WRPLL_DIVIDER_REFERENCE(x)((x)<<0) +#define WRPLL_DIVIDER_POST(x) ((x)<<8) +#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) /* Port clock selection */ #define PORT_CLK_SEL_A 0x46100 -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/29] drm/i915: add Haswell DIP controls registers
Haswell has different DIP control registers and offsets. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 16 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 05d98f2..8cc53fb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3488,6 +3488,22 @@ #define VLV_TVIDEO_DIP_GCP(pipe) \ _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) +/* Haswell DIP controls */ +#define HSW_VIDEO_DIP_CTL_A0x60200 +#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 +#define HSW_VIDEO_DIP_GCP_A0x60210 + +#define HSW_VIDEO_DIP_CTL_B0x61200 +#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 +#define HSW_VIDEO_DIP_GCP_B0x61210 + +#define HSW_TVIDEO_DIP_CTL(pipe) \ +_PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ +_PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) +#define HSW_TVIDEO_DIP_GCP(pipe) \ + _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) + #define _TRANS_HTOTAL_B 0xe1000 #define _TRANS_HBLANK_B 0xe1004 #define _TRANS_HSYNC_B 0xe1008 -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/29] drm/i915: support infoframes on Haswell
Haswell has different DIP registers which we need to use for infoframes,
so add proper infrastructure to address that.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 7de2d3b..f6a9b83 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -208,6 +208,36 @@ static void vlv_write_infoframe(struct drm_encoder
*encoder,
I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
}
+static void hsw_write_infoframe(struct drm_encoder *encoder,
+struct dip_infoframe *frame)
+{
+ uint32_t *data = (uint32_t *)frame;
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
+ unsigned i, len = DIP_HEADER_SIZE + frame->len;
+ u32 flags, val = I915_READ(reg);
+
+ intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+ flags = intel_infoframe_index(frame);
+
+ val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+
+ I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+
+ for (i = 0; i < len; i += 4) {
+ I915_WRITE(HSW_TVIDEO_DIP_AVI_DATA(intel_crtc->pipe), *data);
+ data++;
+ }
+
+ flags |= intel_infoframe_flags(frame);
+
+ I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+}
+
static void intel_set_infoframe(struct drm_encoder *encoder,
struct dip_infoframe *frame)
{
@@ -587,6 +617,10 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_hdmi->write_infoframe = vlv_write_infoframe;
for_each_pipe(i)
I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
+ } else if (IS_HASWELL(dev)) {
+ intel_hdmi->write_infoframe = hsw_write_infoframe;
+ for_each_pipe(i)
+ I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
} else {
intel_hdmi->write_infoframe = ironlake_write_infoframe;
for_each_pipe(i)
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/29] drm/i915: prevent NULL pointer exception when using gmbus
Prevent a NULL pointer exception when we are trying to retrieve EDID data
from non-existent adapter.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index f6a9b83..700bd0b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -389,14 +389,16 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
{
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct edid *edid;
+ struct edid *edid = NULL;
enum drm_connector_status status = connector_status_disconnected;
+ struct i2c_adapter *adapter;
intel_hdmi->has_hdmi_sink = false;
intel_hdmi->has_audio = false;
- edid = drm_get_edid(connector,
- intel_gmbus_get_adapter(dev_priv,
- intel_hdmi->ddc_bus));
+
+ adapter = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
+ if (adapter)
+ edid = drm_get_edid(connector, adapter);
if (edid) {
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
@@ -423,14 +425,17 @@ static int intel_hdmi_get_modes(struct drm_connector
*connector)
{
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
struct drm_i915_private *dev_priv = connector->dev->dev_private;
+ struct i2c_adapter *adapter;
/* We should parse the EDID data and find out if it's an HDMI sink so
* we can send audio to it.
*/
- return intel_ddc_get_modes(connector,
- intel_gmbus_get_adapter(dev_priv,
-
intel_hdmi->ddc_bus));
+ adapter = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
+ if (!adapter)
+ return 0;
+
+ return intel_ddc_get_modes(connector, adapter);
}
static bool
@@ -438,12 +443,15 @@ intel_hdmi_detect_audio(struct drm_connector *connector)
{
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
struct drm_i915_private *dev_priv = connector->dev->dev_private;
- struct edid *edid;
+ struct edid *edid = NULL;
bool has_audio = false;
+ struct i2c_adapter *adapter;
+
+ adapter = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
+
+ if (adapter)
+ edid = drm_get_edid(connector, adapter);
- edid = drm_get_edid(connector,
- intel_gmbus_get_adapter(dev_priv,
- intel_hdmi->ddc_bus));
if (edid) {
if (edid->input & DRM_EDID_INPUT_DIGITAL)
has_audio = drm_detect_monitor_audio(edid);
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/29] drm/i915: add support for SBI ops
With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
v2: de-inline the function and address changes in bits names
v3: protect operations with dpio_lock, increase timeout to 100 for
paranoia sake.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..36f6b8e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1300,6 +1300,69 @@ static void intel_disable_pll(struct drm_i915_private
*dev_priv, enum pipe pipe)
POSTING_READ(reg);
}
+/* SBI access */
+static void
+intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+ if (wait_for_atomic_us((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 100)) {
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+ goto out_unlock;
+ }
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_DATA,
+ value);
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_BUSY |
+ SBI_CTL_OP_CRWR);
+
+ if (wait_for_atomic_us((I915_READ(SBI_CTL_STAT) & (SBI_READY |
SBI_RESPONSE_SUCCESS)) == 0,
+ 100)) {
+ DRM_ERROR("timeout waiting for SBI to complete write
transaction\n");
+ goto out_unlock;
+ }
+
+out_unlock:
+ spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+}
+
+static u32
+intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
+{
+ unsigned long flags;
+ u32 value;
+
+ spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+ if (wait_for_atomic_us((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+ 100)) {
+ DRM_ERROR("timeout waiting for SBI to become ready\n");
+ goto out_unlock;
+ }
+
+ I915_WRITE(SBI_ADDR,
+ (reg << 16));
+ I915_WRITE(SBI_CTL_STAT,
+ SBI_BUSY |
+ SBI_CTL_OP_CRRD);
+
+ if (wait_for_atomic_us((I915_READ(SBI_CTL_STAT) & (SBI_READY |
SBI_RESPONSE_SUCCESS)) == 0,
+ 100)) {
+ DRM_ERROR("timeout waiting for SBI to complete read
transaction\n");
+ goto out_unlock;
+ }
+
+ value = I915_READ(SBI_DATA);
+
+out_unlock:
+ spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+ return value;
+}
+
/**
* intel_enable_pch_pll - enable PCH PLL
* @dev_priv: i915 private structure
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/29] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge
Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 36f6b8e..60b1540 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4921,7 +4921,7 @@ void sandybridge_update_wm(struct drm_device *dev) } /* IVB has 3 pipes */ - if (IS_IVYBRIDGE(dev) && + if ((IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) && g4x_compute_wm0(dev, 2, &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/29] drm/i915: share forcewaking code between IVB and HSW
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 60b1540..3d78686 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9336,7 +9336,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
/* IVB configs may use multi-threaded forcewake */
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
u32 ecobus;
/* A small trick here - if the bios hasn't configured
MT forcewake,
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/29] drm/i915: haswell has 3 pipes as well
They work differently, but the count is the same. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_dma.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 333b746..a813f65 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -2115,7 +2115,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) spin_lock_init(&dev_priv->error_lock); spin_lock_init(&dev_priv->rps_lock); - if (IS_IVYBRIDGE(dev)) + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) dev_priv->num_pipe = 3; else if (IS_MOBILE(dev) || !IS_GEN2(dev)) dev_priv->num_pipe = 2; -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/29] drm/i915: do not enable PCH PLL on pre-haswell
Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0768f48..e4ebd39 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1437,8 +1437,9 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, /* PCH only available on ILK+ */ BUG_ON(dev_priv->info->gen < 5); - /* Make sure PCH DPLL is enabled */ - assert_pch_pll_enabled(dev_priv, pipe); + /* Make sure PCH DPLL is enabled on Pre-Haswell platforms */ + if (!IS_HASWELL(dev_priv->dev)) + assert_pch_pll_enabled(dev_priv, pipe); /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(dev_priv, pipe); -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/29] drm/i915: enable power wells on haswell init
This attempts to enable all the available power wells during the
initialization.
Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed, but this is out of scope of this initial
enablement. Proper tracking of who uses which power well will require
a considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b01afb0..cc2be0b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9635,6 +9635,34 @@ void intel_modeset_init_hw(struct drm_device *dev)
ivb_pch_pwm_override(dev);
}
+/* Starting with Haswell, we have different power wells for
+ * different parts of the GPU. This attempts to enable them all.
+ */
+static void intel_init_power_wells(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long power_wells[] = {
+ HSW_PWR_WELL_CTL1,
+ HSW_PWR_WELL_CTL2,
+ HSW_PWR_WELL_CTL4
+ };
+ int i;
+
+ mutex_lock(&dev->struct_mutex);
+
+ for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
+ int well = I915_READ(power_wells[i]);
+
+ if ((well & HSW_PWR_WELL_STATE) == 0) {
+ I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
+ if (wait_for(I915_READ(power_wells[i] &
HSW_PWR_WELL_STATE), 20))
+ DRM_ERROR("Error enabling power well %lx\n",
power_wells[i]);
+ }
+ }
+
+ mutex_unlock(&dev->struct_mutex);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9652,6 +9680,9 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
+ if (IS_HASWELL(dev))
+ intel_init_power_wells(dev);
+
intel_init_display(dev);
if (IS_GEN2(dev)) {
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/29] drm/i915: detect PCH encoders on Haswell
On Haswell, the only PCH-connected output is the one driven by DDI E in
FDI mode, used for VGA connection. All the others are handled by the CPU.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e4ebd39..b01afb0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3098,6 +3098,13 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
if (encoder->base.crtc != crtc)
continue;
+ /* On Haswell, only DDI E can connect to PCH through FDI to
drive VGA */
+ if (IS_HASWELL(dev) && (encoder->type != DRM_MODE_ENCODER_DAC))
{
+ DRM_DEBUG_KMS("Non-PCH encoder detected on Haswell.
Allowed: %d, detected: %d\n",
+ DRM_MODE_ENCODER_DAC, encoder->type);
+ return false;
+ }
+
switch (encoder->type) {
case INTEL_OUTPUT_EDP:
if (!intel_encoder_is_pch_edp(&encoder->base))
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/29] drm/i915: do not use old code paths on Haswell
Haswell has a different way of accessing pipes and PCH-specific registers,
so avoid using legacy registers on it.
This patch will probably be reworked into a series of smaller patches once
the required plumbing lands and we won't hit those assertions anymore.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 59 +++---
1 file changed, 47 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 712bbaa..a1598a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -949,9 +949,16 @@ static void assert_fdi_tx(struct drm_i915_private
*dev_priv,
u32 val;
bool cur_state;
- reg = FDI_TX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_TX_ENABLE);
+ if (IS_HASWELL(dev_priv->dev)) {
+ DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI
instead\n");
+ reg = DDI_FUNC_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+ } else {
+ reg = FDI_TX_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & FDI_TX_ENABLE);
+ }
WARN(cur_state != state,
"FDI TX state assertion failure (expected %s, current %s)\n",
state_string(state), state_string(cur_state));
@@ -966,9 +973,14 @@ static void assert_fdi_rx(struct drm_i915_private
*dev_priv,
u32 val;
bool cur_state;
- reg = FDI_RX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_RX_ENABLE);
+ if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+ DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe
> 0\n");
+ return;
+ } else {
+ reg = FDI_RX_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & FDI_RX_ENABLE);
+ }
WARN(cur_state != state,
"FDI RX state assertion failure (expected %s, current %s)\n",
state_string(state), state_string(cur_state));
@@ -986,6 +998,11 @@ static void assert_fdi_tx_pll_enabled(struct
drm_i915_private *dev_priv,
if (dev_priv->info->gen == 5)
return;
+ if (IS_HASWELL(dev_priv->dev)) {
+ DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell,
aborting\n");
+ return;
+ }
+
reg = FDI_TX_CTL(pipe);
val = I915_READ(reg);
WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should
be active but is disabled\n");
@@ -997,6 +1014,10 @@ static void assert_fdi_rx_pll_enabled(struct
drm_i915_private *dev_priv,
int reg;
u32 val;
+ if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+ DRM_ERROR("Attempting to enable FDI on Haswell with pipe >
0\n");
+ return;
+ }
reg = FDI_RX_CTL(pipe);
val = I915_READ(reg);
WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should
be active but is disabled\n");
@@ -1102,6 +1123,11 @@ static void assert_pch_refclk_enabled(struct
drm_i915_private *dev_priv)
u32 val;
bool enabled;
+ if (HAS_PCH_LPT(dev_priv->dev)) {
+ DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
+ return;
+ }
+
val = I915_READ(PCH_DREF_CONTROL);
enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1445,6 +1471,10 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, pipe);
assert_fdi_rx_enabled(dev_priv, pipe);
+ if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+ DRM_ERROR("Attempting to enable transcoder on Haswell with pipe
> 0\n");
+ return;
+ }
reg = TRANSCONF(pipe);
val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -2971,13 +3001,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc)
udelay(200);
/* Enable CPU FDI TX PLL, always on for Ironlake */
- reg = FDI_TX_CTL(pipe);
- temp = I915_READ(reg);
- if ((temp & FDI_TX_PLL_ENABLE) == 0) {
- I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
+ if (IS_HASWELL(dev)) {
+ DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
+ return;
+ } else {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ if ((temp & FDI_TX_PLL_ENABL
[Intel-gfx] [PATCH 24/29] drm/i915: program iCLKIP on Lynx Point
The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.
Those values can be programmed individually, by doing some math; or we
could use a pre-defined table of values for each modeset. For speed and
simplification, the idea was to just adopt the table of valid pixel clocks
and select the matching iCLKIP values from there.
As a possible idea for the future, it would be possible to add a fallback
and calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 309 ++
1 file changed, 309 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ac34457..bdc22f5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2958,6 +2958,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
DDI_BUF_EMP_800MV_3_5DB_HSW
};
+/* Available pixel clock values */
+struct iclk_vga_clock {
+ u32 clock;
+ u16 auxdiv;
+ u16 divsel;
+ u16 phasedir;
+ u16 phaseinc;
+};
+
+static const struct iclk_vga_clock iclk_vga_clock_table[] = {
+ {2, 1, 0x41, 0, 0x20}, /* 2 ppm=0 */
+ {21000, 0, 0x7E, 0, 0x25}, /* 20999 ppm=-53 */
+ {21912, 0, 0x79, 0, 0x0E}, /* 21912 ppm=12 */
+ {22000, 0, 0x78, 0, 0x2F}, /* 21999 ppm=-58 */
+ {23000, 0, 0x73, 0, 0x19}, /* 23000 ppm=6 */
+ {24000, 0, 0x6E, 0, 0x20}, /* 24000 ppm=0 */
+ {25000, 0, 0x6A, 0, 0x00}, /* 25000 ppm=0 */
+ {25175, 0, 0x69, 0, 0x10}, /* 25175 ppm=-7 */
+ {25200, 0, 0x69, 0, 0x09}, /* 25201 ppm=21 */
+ {26000, 0, 0x66, 1, 0x0A}, /* 26001 ppm=24 */
+ {27000, 0, 0x62, 0, 0x00}, /* 27000 ppm=0 */
+ {27027, 0, 0x62, 1, 0x06}, /* 27025 ppm=-62 */
+ {27500, 0, 0x60, 0, 0x0C}, /* 27498 ppm=-58 */
+ {28000, 0, 0x5E, 0, 0x1B}, /* 28002 ppm=70 */
+ {28320, 0, 0x5D, 0, 0x16}, /* 28319 ppm=-50 */
+ {28322, 0, 0x5D, 0, 0x15}, /* 28323 ppm=44 */
+ {29000, 0, 0x5B, 0, 0x07}, /* 28998 ppm=-64 */
+ {3, 0, 0x58, 0, 0x00}, /* 3 ppm=0 */
+ {31000, 0, 0x55, 0, 0x06}, /* 31001 ppm=35 */
+ {31500, 0, 0x54, 1, 0x12}, /* 31498 ppm=-53 */
+ {32000, 0, 0x52, 0, 0x18}, /* 32000 ppm=0 */
+ {32500, 0, 0x51, 0, 0x05}, /* 32500 ppm=-15 */
+ {33000, 0, 0x50, 1, 0x0C}, /* 33002 ppm=70 */
+ {34000, 0, 0x4D, 0, 0x1A}, /* 34002 ppm=70 */
+ {35000, 0, 0x4B, 0, 0x09}, /* 35001 ppm=29 */
+ {35500, 0, 0x4A, 0, 0x04}, /* 35497 ppm=-82 */
+ {36000, 0, 0x49, 0, 0x00}, /* 36000 ppm=0 */
+ {37000, 0, 0x47, 1, 0x02}, /* 37002 ppm=58 */
+ {38000, 0, 0x45, 0, 0x03}, /* 38003 ppm=82 */
+ {39000, 0, 0x43, 0, 0x0F}, /* 38998 ppm=-53 */
+ {4, 0, 0x41, 0, 0x20}, /* 4 ppm=0 */
+ {40500, 0, 0x41, 1, 0x15}, /* 40497 ppm=-79 */
+ {40541, 0, 0x41, 1, 0x1A}, /* 40544 ppm=95 */
+ {41000, 0, 0x40, 1, 0x09}, /* 40996 ppm=-87 */
+ {41540, 0, 0x3F, 0, 0x00}, /* 41538 ppm=-38 */
+ {42000, 0, 0x3E, 0, 0x12}, /* 42003 ppm=70 */
+ {43000, 0, 0x3D, 1, 0x0D}, /* 42996 ppm=-99 */
+ {43163, 0, 0x3D, 1, 0x1D}, /* 43168 ppm=108 */
+ {44000, 0, 0x3B, 0, 0x17}, /* 44003 ppm=70 */
+ {44900, 0, 0x3A, 0, 0x09}, /* 44895 ppm=-117 */
+ {45000, 0, 0x3A, 0, 0x00}, /* 45000 ppm=0 */
+ {46000, 0, 0x39, 1, 0x13}, /* 45994 ppm=-128 */
+ {47000, 0, 0x37, 0, 0x1D}, /* 46995 ppm=-110 */
+ {48000, 0, 0x36, 0, 0x10}, /* 48000 ppm=0 */
+ {49000, 0, 0x35, 0, 0x07}, /* 48993 ppm=-134 */
+ {49500, 0, 0x35, 1, 0x1D}, /* 49499 ppm=-27 */
+ {5, 0, 0x34, 0, 0x00}, /* 5 ppm=0 */
+ {51000, 0, 0x33, 1, 0x04}, /* 51004 ppm=70 */
+ {52000, 0, 0x32, 1, 0x05}, /* 52001 ppm=24 */
+ {52406, 0, 0x32, 1, 0x1F}, /* 52411 ppm=101 */
+ {53000, 0, 0x31, 1, 0x04}, /* 53006 ppm=116 */
+ {54000, 0, 0x30, 0, 0x00}, /* 54000 ppm=0 */
+
[Intel-gfx] [PATCH 23/29] drm/i915: disable pipe DDI function when disabling pipe
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dcfe143..ac34457 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1605,6 +1605,16 @@ static void intel_disable_pipe(struct drm_i915_private
*dev_priv,
I915_WRITE(reg, val & ~PIPECONF_ENABLE);
intel_wait_for_pipe_off(dev_priv->dev, pipe);
+
+ /* On HSW, disable pipe DDI function the pipe */
+ if (IS_HASWELL(dev_priv->dev)) {
+ val = I915_READ(DDI_FUNC_CTL(pipe));
+ val &= ~PIPE_DDI_PORT_MASK;
+ val &= ~PIPE_DDI_FUNC_ENABLE;
+ I915_WRITE(DDI_FUNC_CTL(pipe),
+ val);
+ }
+
}
/*
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/29] drm/i915: do not use fdi_normal_train on haswell
This should be already configured when FDI auto-negotiation is done. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 33ff60e..0768f48 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3159,7 +3159,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); - intel_fdi_normal_train(crtc); + if (!IS_HASWELL(dev)) + intel_fdi_normal_train(crtc); /* For PCH DP, enable TRANS_DP_CTL */ if (HAS_PCH_CPT(dev) && -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/29] drm/i915: share pipe count handling with Ivybridge
Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3d78686..5ee652d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2427,7 +2427,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, case 1: break; case 2: - if (IS_IVYBRIDGE(dev)) + if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) break; /* fall through otherwise */ default: -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 28/29] drm/i915: prepare HDMI link for Haswell
On Haswell, we need to properly train the DDI buffers prior to enabling
HDMI, and enable the required clocks with correct dividers for the desired
frequency.
Also, we cannot simple reuse HDMI routines from previous generations of
GPU, as most of HDMI-specific stuff is being done via the DDI port
programming instead of HDMI-specific registers.
This commit take advantage of the WR PLL clock table which is in a
separate (previous) commit to select the right divisors for each mode.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 129 -
1 file changed, 128 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index d2f278f..e2b8847 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -665,6 +665,98 @@ static const struct wrpll_tmds_clock
wrpll_tmds_clock_table[] = {
{298000,2, 21, 19},
};
+static void intel_hdmi_mode_set_hsw(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+ int port = intel_hdmi->ddi_port;
+ int pipe = intel_crtc->pipe;
+ int p, n2, r2, valid=0;
+ u32 temp, i;
+
+ /* On Haswell, we need to enable the clocks and prepare DDI function to
+* work in HDMI mode for this pipe.
+*/
+ DRM_DEBUG_KMS("Preparing HDMI DDI mode for Haswell on port %c, pipe
%c\n", port_name(port), pipe_name(pipe));
+
+ for (i=0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) {
+ if (crtc->mode.clock == wrpll_tmds_clock_table[i].clock) {
+ p = wrpll_tmds_clock_table[i].p;
+ n2 = wrpll_tmds_clock_table[i].n2;
+ r2 = wrpll_tmds_clock_table[i].r2;
+
+ DRM_INFO("Found clock settings for %dKHz refresh rate:
p=%d, n2=%d, r2=%d\n",
+ crtc->mode.clock,
+ p, n2, r2);
+
+ valid = 1;
+ break;
+ }
+ }
+
+ if (!valid) {
+ DRM_ERROR("Unable to find WRPLL clock settings for %dKHz
refresh rate\n",
+ crtc->mode.clock);
+ return;
+ }
+
+ /* Enable LCPLL if disabled */
+ temp = I915_READ(LCPLL_CTL);
+ if (temp & LCPLL_PLL_DISABLE)
+ I915_WRITE(LCPLL_CTL,
+ temp & ~LCPLL_PLL_DISABLE);
+
+ /* Configure WR PLL 1, program the correct divider values for
+* the desired frequency and wait for warmup */
+ I915_WRITE(WRPLL_CTL1,
+ WRPLL_PLL_ENABLE |
+ WRPLL_PLL_SELECT_LCPLL_2700 |
+ WRPLL_DIVIDER_REFERENCE(r2) |
+ WRPLL_DIVIDER_FEEDBACK(n2) |
+ WRPLL_DIVIDER_POST(p));
+
+ udelay(20);
+
+ /* Use WRPLL1 clock to drive the output to the port, and tell the pipe
to use
+* this port for connection.
+*/
+ I915_WRITE(PORT_CLK_SEL(port),
+ PORT_CLK_SEL_WRPLL1);
+ I915_WRITE(PIPE_CLK_SEL(pipe),
+ PIPE_CLK_SEL_PORT(port));
+
+ udelay(20);
+
+ if (intel_hdmi->has_audio) {
+ /* Proper support for digital audio needs a new logic and a new
set
+* of registers, so we leave it for future patch bombing.
+*/
+ DRM_DEBUG_DRIVER("HDMI audio on pipe %c not yet supported on
DDI\n",
+pipe_name(intel_crtc->pipe));
+ }
+
+ /* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
+ temp = I915_READ(DDI_FUNC_CTL(pipe));
+ temp &= ~PIPE_DDI_PORT_MASK;
+ temp &= ~PIPE_DDI_BPC_12;
+ temp |= PIPE_DDI_SELECT_PORT(port) |
+ PIPE_DDI_MODE_SELECT_HDMI |
+ ((intel_crtc->bpp > 24) ?
+ PIPE_DDI_BPC_12 :
+ PIPE_DDI_BPC_8) |
+ PIPE_DDI_FUNC_ENABLE;
+
+ I915_WRITE(DDI_FUNC_CTL(pipe), temp);
+
+ intel_hdmi_set_avi_infoframe(encoder);
+ intel_hdmi_set_spd_infoframe(encoder);
+}
+
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
@@ -713,6 +805,30 @@ sta
[Intel-gfx] [PATCH 12/29] drm/i915: share IVB cursor routine with Haswell
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5ee652d..33ff60e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6807,7 +6807,7 @@ static void intel_crtc_update_cursor(struct drm_crtc
*crtc,
if (!visible && !intel_crtc->cursor_visible)
return;
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
I915_WRITE(CURPOS_IVB(pipe), pos);
ivb_update_cursor(crtc, base);
} else {
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 21/29] drm/i915: initialize DDI buffer translations
Buffer translations for DDI links must be initialized prior to enablement.
For FDI and DP, first 9 pairs of values are used to select the connection
parameters. HDMI uses the last pair of values and ignores the first 9
pairs. So we program HDMI values in both cases, which allows HDMI to work
over both FDI and DP-friendly buffers.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 84 +-
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a1598a5..e7a2a81 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2856,6 +2856,86 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
DRM_DEBUG_KMS("FDI train done.\n");
}
+/* HDMI/DVI modes ignore everything but the last 2 items. So we share
+ * them for both DP and FDI transports, allowing those ports to
+ * automatically adapt to HDMI connections as well
+ */
+static const long hsw_ddi_translations_dp[] = {
+ 0x00FF, 0x0006000E,
+ 0x00D75FFF, 0x0005000A,
+ 0x00C30FFF, 0x00040006,
+ 0x80AAAFFF, 0x000B,
+ 0x00FF, 0x0005000A,
+ 0x00D75FFF, 0x000C0004,
+ 0x80C30FFF, 0x000B,
+ 0x00FF, 0x00040006,
+ 0x80D75FFF, 0x000B,
+ 0x00FF, 0x00040006
+};
+
+static const long hsw_ddi_translations_fdi[] = {
+ 0x00FF, 0x0007000E,
+ 0x00D75FFF, 0x000F000A,
+ 0x00C30FFF, 0x00060006,
+ 0x00AAAFFF, 0x001E,
+ 0x00FF, 0x000F000A,
+ 0x00D75FFF, 0x00160004,
+ 0x00C30FFF, 0x001E,
+ 0x00FF, 0x00060006,
+ 0x00D75FFF, 0x001E,
+ 0x00FF, 0x00040006
+};
+
+/* On Haswell, DDI port buffers must be programmed with correct values
+ * in advance. The buffer values are different for FDI and DP modes,
+ * but the HDMI/DVI fields are shared among those. So we program the DDI
+ * in either FDI or DP modes only, as HDMI connections will work with both
+ * of those
+ */
+void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool
use_fdi_mode)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 reg;
+ int i, j;
+
+ DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
+ port_name(port),
+ use_fdi_mode ? "FDI" : "DP");
+
+ WARN((use_fdi_mode && (port != PORT_E)),
+ "Programming port %c in FDI mode, this probably will not
work.\n",
+ port_name(port));
+
+ /* Those registers seem to be double-buffered, so write them twice */
+ for (j=0; j < 2; j++) {
+ for (i=0, reg=DDI_BUF_TRANS(port); i <
ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+ I915_WRITE(reg,
+ (use_fdi_mode) ?
+ hsw_ddi_translations_fdi[i] :
+ hsw_ddi_translations_dp[i]);
+ reg += 4;
+ }
+ udelay(20);
+ }
+}
+
+/* Program DDI buffers translations for DP. By default, program ports A-D in DP
+ * mode and port E for FDI.
+ */
+static void intel_hsw_prepare_ddi_buffers(struct drm_device *dev)
+{
+ int port;
+
+ for (port = PORT_A; port < PORT_E; port++)
+ hsw_prepare_ddi_buffers(dev, port, false);
+
+ /* DDI E is the suggested one to work in FDI mode, so program is as
such by
+* default. It will have to be re-programmed in case a digital DP output
+* will be detected on it
+*/
+ hsw_prepare_ddi_buffers(dev, PORT_E, true);
+}
+
/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
@@ -9732,8 +9812,10 @@ void intel_modeset_init(struct drm_device *dev)
intel_init_quirks(dev);
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev)) {
intel_init_power_wells(dev);
+ intel_hsw_prepare_ddi_buffers(dev);
+ }
intel_init_display(dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 79cabf5..6862ed3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -420,6 +420,7 @@ extern void intel_init_clock_gating(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
+extern void hsw_prepare_ddi_buffers(struct drm_device *dev, enum port port,
bool use_fdi_mode);
/* For use by IVB LP watermark workaround in intel_sprite.c */
extern void sandybridge_update_wm(struct drm_device *dev);
[Intel-gfx] [PATCH 26/29] drm/i915: add support for DDI-controlled digital outputs
Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 0978fb7..09dab76 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -41,6 +41,7 @@ struct intel_hdmi {
struct intel_encoder base;
u32 sdvox_reg;
int ddc_bus;
+ int ddi_port;
uint32_t color_range;
bool has_hdmi_sink;
bool has_audio;
@@ -614,6 +615,24 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
+ intel_hdmi->ddi_port = PORT_B;
+ dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
+ intel_hdmi->ddi_port = PORT_C;
+ dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
+ } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
+ DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
+ intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
+ intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
+ intel_hdmi->ddi_port = PORT_D;
+ dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
} else {
DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
}
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 27/29] drm/i915: add WR PLL programming table
This table is used for programming WR PLL clocks, used by HDMI and DVI outputs.
I split it into a separate patch to simplify the HDMI enabling patch which was
getting huge.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 388 +
1 file changed, 388 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 09dab76..d2f278f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -277,6 +277,394 @@ static void intel_hdmi_set_spd_infoframe(struct
drm_encoder *encoder)
intel_set_infoframe(encoder, &spd_if);
}
+/* WRPLL clock dividers */
+struct wrpll_tmds_clock {
+ u32 clock;
+ u16 p; /* Post divider */
+ u16 n2; /* Feedback divider */
+ u16 r2; /* Reference divider */
+};
+
+/* Table of matching values for WRPLL clocks programming for each frequency */
+static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
+ {19750, 38, 25, 18},
+ {2, 48, 32, 18},
+ {21000, 36, 21, 15},
+ {21912, 42, 29, 17},
+ {22000, 36, 22, 15},
+ {23000, 36, 23, 15},
+ {23500, 40, 40, 23},
+ {23750, 26, 16, 14},
+ {23750, 26, 16, 14},
+ {24000, 36, 24, 15},
+ {25000, 36, 25, 15},
+ {25175, 26, 40, 33},
+ {25200, 30, 21, 15},
+ {26000, 36, 26, 15},
+ {27000, 30, 21, 14},
+ {27027, 18, 100,111},
+ {27500, 30, 29, 19},
+ {28000, 34, 30, 17},
+ {28320, 26, 30, 22},
+ {28322, 32, 42, 25},
+ {28750, 24, 23, 18},
+ {29000, 30, 29, 18},
+ {29750, 32, 30, 17},
+ {3, 30, 25, 15},
+ {30750, 30, 41, 24},
+ {31000, 30, 31, 18},
+ {31500, 30, 28, 16},
+ {32000, 30, 32, 18},
+ {32500, 28, 32, 19},
+ {33000, 24, 22, 15},
+ {34000, 28, 30, 17},
+ {35000, 26, 32, 19},
+ {35500, 24, 30, 19},
+ {36000, 26, 26, 15},
+ {36750, 26, 46, 26},
+ {37000, 24, 23, 14},
+ {37762, 22, 40, 26},
+ {37800, 20, 21, 15},
+ {38000, 24, 27, 16},
+ {38250, 24, 34, 20},
+ {39000, 24, 26, 15},
+ {4, 24, 32, 18},
+ {40500, 20, 21, 14},
+ {40541, 22, 147,89},
+ {40750, 18, 19, 14},
+ {41000, 16, 17, 14},
+ {41500, 22, 44, 26},
+ {41540, 22, 44, 26},
+ {42000, 18, 21, 15},
+ {42500, 22, 45, 26},
+ {43000, 20, 43, 27},
+ {43163, 20, 24, 15},
+ {44000, 18, 22, 15},
+ {44900, 20, 108,65},
+ {45000, 20, 25, 15},
+ {45250, 20, 52, 31},
+ {46000, 18, 23, 15},
+ {46750, 20, 45, 26},
+ {47000, 20, 40, 23},
+ {48000, 18, 24, 15},
+ {49000, 18, 49, 30},
+ {49500, 16, 22, 15},
+ {5, 18, 25, 15},
+ {50500, 18, 32, 19},
+ {51000, 18, 34, 20},
+ {52000, 18, 26, 15},
+ {52406, 14, 34, 25},
+ {53000, 16, 22, 14},
+ {54000, 16, 24, 15},
+ {54054, 16, 173,108},
+ {54500, 14, 24, 17},
+ {55000, 12, 22, 18},
+ {56000, 14, 45, 31},
+ {56250, 16, 25, 15},
+ {56750, 14, 25, 17},
+ {57000, 16, 27, 16},
+ {58000, 16, 43, 25},
+ {58250, 16, 38, 22},
+ {58750, 16, 40, 23},
+ {59000, 14, 26, 17},
+ {59341, 14, 40, 26},
+ {59400, 16, 44, 25},
+ {6, 16, 32, 18},
+ {60500, 12, 39, 29},
+ {61000, 14, 49, 31},
+ {62000, 14, 37, 23},
+ {62250, 14, 42, 26},
+ {63000, 12, 21, 15},
+ {63500, 14, 28, 17},
+ {64000, 12, 27, 19},
+ {65000, 14, 32, 19},
+ {65250, 12, 29, 20},
+ {65500, 12, 32, 22},
+ {66000, 12, 22, 15},
+ {7, 14, 38, 22},
+ {66750, 10, 21, 17},
+ {67000, 14, 33, 19},
+ {67750, 14, 58, 33},
+ {68000, 14, 30, 17},
+ {68179, 14, 46, 26},
+ {68250, 14, 46, 26},
+ {69000, 12, 23, 15},
+ {7, 12, 28, 18},
+ {71000, 12, 30, 19},
+ {72000, 12, 24, 15},
+ {73000, 10, 23, 17},
+ {74000, 12, 23,
[Intel-gfx] [PATCH 19/29] drm/i915: program WM_LINETIME on Haswell
The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.
v2: improve comment as per Chris Wilson suggestion
v3: incorporate latest changes in specs.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 448f8d7..712bbaa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6436,6 +6436,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
+ if (IS_HASWELL(dev)) {
+ temp = I915_READ(PIPE_WM_LINETIME(pipe));
+ temp &= ~PIPE_WM_LINETIME_MASK;
+
+ /* The WM are computed with base on how long it takes to fill a
single
+* row at the given clock rate, multiplied by 8.
+* */
+ temp |= PIPE_WM_LINETIME_TIME(
+ ((adjusted_mode->crtc_hdisplay * 1000) /
adjusted_mode->clock) * 8);
+
+ I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
+ }
+
/* pipesrc controls the size that is scaled from, which should
* always be the user's requested size.
*/
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 22/29] drm/i915: perform Haswell DDI link training in FDI mode
This patch attempts at following the modeset sequence closely, retrying
with different voltages if the DP_TP_STATUS reports a failed training.
For training, we add a table of recommended settings for FDI, HDMI and DP
connections. For FDI and DP modes, we also add the HDMI buffer
translation as the last item. Those are ignored in such modes, so there is
no harm in having them set.
Initially, we use DDI E for FDI connectivity. This is the suggested
configuration, and this seems to be what should work the best with FDI.
Note that we leave the DDI Function for corresponding pipe active when we
are done with the training. This ensures that we only need to enable pipe
afterwards to get a working modesetting, in a similar fashion as on
pre-HSW hardware. The modeset disabling sequence mentions a correct order
of disabling things, but this is out of scope of this patch and is being
done separately, for clearer distinction of what happens when.
v2: improve comments a bit, use PORT enums instead of hardcoded PORT_E
registers, split DDI buffers programming into a separate patch.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 118 ++
1 file changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e7a2a81..dcfe143 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2936,6 +2936,113 @@ static void intel_hsw_prepare_ddi_buffers(struct
drm_device *dev)
hsw_prepare_ddi_buffers(dev, PORT_E, true);
}
+static const long hsw_ddi_buf_ctl_values[] = {
+ DDI_BUF_EMP_400MV_0DB_HSW,
+ DDI_BUF_EMP_400MV_3_5DB_HSW,
+ DDI_BUF_EMP_400MV_6DB_HSW,
+ DDI_BUF_EMP_400MV_9_5DB_HSW,
+ DDI_BUF_EMP_600MV_0DB_HSW,
+ DDI_BUF_EMP_600MV_3_5DB_HSW,
+ DDI_BUF_EMP_600MV_6DB_HSW,
+ DDI_BUF_EMP_800MV_0DB_HSW,
+ DDI_BUF_EMP_800MV_3_5DB_HSW
+};
+
+
+/* Link training for HSW parts */
+static void hsw_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp, i;
+
+ /* Configure CPU PLL, wait for warmup */
+ I915_WRITE(SPLL_CTL,
+ SPLL_PLL_ENABLE |
+ SPLL_PLL_FREQ_1350MHz |
+ SPLL_PLL_SCC);
+
+ /* Use SPLL to drive the output when in FDI mode */
+ I915_WRITE(PORT_CLK_SEL(PORT_E),
+ PORT_CLK_SEL_SPLL);
+ I915_WRITE(PIPE_CLK_SEL(pipe),
+ PIPE_CLK_SEL_PORT(PORT_E));
+
+ udelay(20);
+
+ /* Start the training iterating through available voltages and emphasis
*/
+ for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
+ /* Configure DP_TP_CTL with auto-training */
+ I915_WRITE(DP_TP_CTL(PORT_E),
+ DP_TP_CTL_FDI_AUTOTRAIN |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_PAT1 |
+ DP_TP_CTL_ENABLE);
+
+ /* Configure and enable DDI_BUF_CTL for DDI E with next voltage
*/
+ temp = I915_READ(DDI_BUF_CTL(PORT_E));
+ temp = (temp & ~DDI_BUF_EMP_MASK);
+ I915_WRITE(DDI_BUF_CTL(PORT_E),
+ temp |
+ DDI_BUF_CTL_ENABLE |
+ DDI_PORT_WIDTH_X2 |
+ hsw_ddi_buf_ctl_values[i]);
+
+ udelay(600);
+
+ /* Enable CPU FDI Receiver with auto-training */
+ reg = FDI_RX_CTL(pipe);
+ I915_WRITE(reg,
+ I915_READ(reg) |
+ FDI_LINK_TRAIN_AUTO |
+ FDI_RX_ENABLE |
+ FDI_LINK_TRAIN_PATTERN_1_CPT |
+ FDI_RX_ENHANCE_FRAME_ENABLE |
+ FDI_PORT_WIDTH_2X_LPT |
+ FDI_RX_PLL_ENABLE);
+ POSTING_READ(reg);
+ udelay(100);
+
+ temp = I915_READ(DP_TP_STATUS(PORT_E));
+ if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
+ DRM_INFO("BUF_CTL training done on %d step\n", i);
+
+ /* Enable normal pixel sending for FDI */
+ I915_WRITE(DP_TP_CTL(PORT_E),
+ DP_TP_CTL_FDI_AUTOTRAIN |
+ DP_TP_CTL_LINK_TRAIN_NORMAL |
+ D
[Intel-gfx] [PATCH 29/29] drm/i915: hook Haswell devices in place
This patch enables i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.c|4
drivers/gpu/drm/i915/i915_drv.c |7 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 74c2d92..764f70c 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -908,6 +908,10 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
{ }
};
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ccfdc81..9282bd0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -345,6 +345,13 @@ static const struct pci_device_id pciidlist[] = {
/* aka */
INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
+ INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
+ INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+ INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
+ INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+ INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
+ INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
+ INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
{0, 0, 0}
};
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/29] drm/i915: reuse Ivybridge interrupts code for Haswell
v2: prevent possible conflicts with VLV.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_irq.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index febddc2..1ed18db 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1969,7 +1969,7 @@ static void ironlake_irq_preinstall(struct drm_device
*dev)
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
- if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
I915_WRITE(HWSTAM, 0xeffe);
@@ -2445,7 +2445,7 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0xff; /* only 24 bits of frame count */
if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
- IS_VALLEYVIEW(dev)) {
+ IS_VALLEYVIEW(dev) || IS_HASWELL(dev)) {
dev->max_vblank_count = 0x; /* full 32 bit counter */
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
}
@@ -2463,7 +2463,7 @@ void intel_irq_init(struct drm_device *dev)
dev->driver->irq_uninstall = valleyview_irq_uninstall;
dev->driver->enable_vblank = valleyview_enable_vblank;
dev->driver->disable_vblank = valleyview_disable_vblank;
- } else if (IS_IVYBRIDGE(dev)) {
+ } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share pre & uninstall handlers with ILK/SNB */
dev->driver->irq_handler = ivybridge_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_preinstall;
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/29] drm/i915: show unknown sdvox registers on hdmi init
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 700bd0b..0978fb7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -614,6 +614,8 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
+ } else {
+ DRM_DEBUG_DRIVER("Unknown sdvox register %x\n", sdvox_reg);
}
intel_hdmi->sdvox_reg = sdvox_reg;
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/29] drm/i915: disable rc6 on haswell for now
This needs proper enablement to avoid machine hangs, so let's just avoid it for now. Reviewed-by: Rodrigo Vivi Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cc2be0b..448f8d7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8631,6 +8631,10 @@ int intel_enable_rc6(const struct drm_device *dev) if (INTEL_INFO(dev)->gen == 5) return 0; + /* Sorry Haswell, no RC6 for you for now. */ + if (IS_HASWELL(dev)) + return 0; + /* * Disable rc6 on Sandybridge */ -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 25/29] drm/i915: detect digital outputs on Haswell
Digital port detection on Haswell is indicated by the presence of a bit in
DDI_BUF_CTL for port A, and by a different register for ports B, C and D.
So we check for those bits during the initialization time and let the hdmi
function know about those.
Note that this bit does not indicates whether the output is DP or HDMI.
However, the DDI buffers can be programmed in a way that is shared between
DP/HDMI and FDI/HDMI except for PORT E.
So for now, we detect those digital outputs as being HDMI, but proper DP
support is still pending.
Note that DDI A can only drive eDP, so we do not handle it here for hdmi
initialization.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 51 +++---
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index bdc22f5..1524966 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8743,26 +8743,45 @@ static void intel_setup_outputs(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev)) {
int found;
- if (I915_READ(HDMIB) & PORT_DETECTED) {
- /* PCH SDVOB multiplex with HDMIB */
- found = intel_sdvo_init(dev, PCH_SDVOB, true);
- if (!found)
- intel_hdmi_init(dev, HDMIB);
- if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
- intel_dp_init(dev, PCH_DP_B);
- }
+ if (IS_HASWELL(dev)) {
+ /* Haswell uses DDI functions to detect digital outputs
*/
+ found = I915_READ(DDI_BUF_CTL_A) &
DDI_INIT_DISPLAY_DETECTED;
+ /* DDI A only supports eDP */
+ if (found)
+ DRM_INFO("Found digital output on DDI port
A\n");
+
+ /* DDI B, C and D detection is indicated by the
SFUSE_STRAP
+* register */
+ found = I915_READ(SFUSE_STRAP);
+
+ if (found & SFUSE_STRAP_DDIB_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_B));
+ if (found & SFUSE_STRAP_DDIC_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_C));
+ if (found & SFUSE_STRAP_DDID_DETECTED)
+ intel_hdmi_init(dev, DDI_BUF_CTL(PORT_D));
+ } else {
+ if (I915_READ(HDMIB) & PORT_DETECTED) {
+ /* PCH SDVOB multiplex with HDMIB */
+ found = intel_sdvo_init(dev, PCH_SDVOB, true);
+ if (!found)
+ intel_hdmi_init(dev, HDMIB);
+ if (!found && (I915_READ(PCH_DP_B) &
DP_DETECTED))
+ intel_dp_init(dev, PCH_DP_B);
+ }
- if (I915_READ(HDMIC) & PORT_DETECTED)
- intel_hdmi_init(dev, HDMIC);
+ if (I915_READ(HDMIC) & PORT_DETECTED)
+ intel_hdmi_init(dev, HDMIC);
- if (I915_READ(HDMID) & PORT_DETECTED)
- intel_hdmi_init(dev, HDMID);
+ if (I915_READ(HDMID) & PORT_DETECTED)
+ intel_hdmi_init(dev, HDMID);
- if (I915_READ(PCH_DP_C) & DP_DETECTED)
- intel_dp_init(dev, PCH_DP_C);
+ if (I915_READ(PCH_DP_C) & DP_DETECTED)
+ intel_dp_init(dev, PCH_DP_C);
- if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
- intel_dp_init(dev, PCH_DP_D);
+ if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
+ intel_dp_init(dev, PCH_DP_D);
+ }
} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
bool found = false;
--
1.7.10
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/29] drm/i915: prevent NULL pointer exception when using gmbus
On Fri, Apr 13, 2012 at 17:18, Chris Wilson wrote: > On Fri, 13 Apr 2012 17:08:41 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > Prevent a NULL pointer exception when we are trying to retrieve EDID data > > from non-existent adapter. > > This just means that a HDMI with a garbage ddc_bus is never detected. > Since we control ddc_bus entirely, it means that the initialisation is > completely bogus. Please fix the root cause and not paper over > programming bugs. > Sorry, I think I wasn't clear in my cover letter about this one.. I am not hitting any issue with this current branch I sent; but the nature of the code we have after the gmbus refactoring made me a bit paranoid about accessing properties of something that could potential be NULL. As far as I can see, we should not hit this with any combination of outputs on any hardware that is already covered by the wikipedia :). So I am fine with dropping this patch if you also think that it does not adds anything relevant to us. Or perhaps I should refactor it into adding some WARN's instead? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 06/29] drm/i915: add support for SBI ops
On Fri, Apr 13, 2012 at 17:26, Chris Wilson wrote: > On Fri, 13 Apr 2012 17:08:42 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > With Lynx Point, we need to use SBI to communicate with the display clock > > control. This commit adds helper functions to access the registers via > > SBI. > > > > v2: de-inline the function and address changes in bits names > > > > v3: protect operations with dpio_lock, increase timeout to 100 for > > paranoia sake. > > > > v1 Reviewed-by: Rodrigo Vivi > > Hmm, busy-waits upon a register change. Does it have to be atomic? Can > it really be called in IRQ context? Can I have a sleepy version that > won't cause audible stutters for the normal case? (Admittedly > single-core processors are history...) > The original version wasn't atomic and wasn't called in IRQ context, but Daniel suggested that I should be more paranoid about this so I followed his idea :). Anyway, both versions (this one and previous one) work; would both you and Daniel be happy if I do another version of this keeping the dpio_lock handling but dropping atomic bits? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 15/29] drm/i915: do not enable PCH PLL on pre-haswell
On Fri, Apr 13, 2012 at 17:55, Chris Wilson wrote: > The PLL split needs to be reconsidered in light of Jesse's decoupling > PLLs from the pipes. > > I think we want to start annotating those so that we can keep track of > CPU vs PCH DP/FDI links and plls. > Yes, I'll wait for the PLL patches to land and will refactor this accordingly. I just didn't wanted to have it blocking my entire series here. With HSW, on PCH, we only have 1 PLL (iCLKIP), the other ones are on the CPU. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 25/29] drm/i915: detect digital outputs on Haswell
On Fri, Apr 13, 2012 at 18:17, Chris Wilson wrote: > We're starting to get to ridiculous levels of indention. Break the PCH > detection of SDVO/HDMI outputs into its own routine, and perhaps further > down in architectures? > Yes, both intel_display and intel_hdmi get too overcomplex with those patches :(. I haven't done the split in those series because I thought that the plan was to land those VLV/HSW patches before doing the big display refactoring we discussed some weeks ago. But I could certainly start doing it. Daniel, what do you think would best from your dinq maintainership point of view - refactor those bits here and in other big patches of this series (fdi and hdmi ones) and then resend all the patches; or have them as is and do the big refactoring for everything after that? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 17/29] drm/i915: enable power wells on haswell init
On Fri, Apr 13, 2012 at 18:03, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:53 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > void intel_modeset_init(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -9652,6 +9680,9 @@ void intel_modeset_init(struct drm_device *dev)
> >
> > intel_init_quirks(dev);
> >
> > + if (IS_HASWELL(dev))
> > + intel_init_power_wells(dev);
> > +
>
> Perform the gen checks in intel_init_power_wells() so that we keep the
> initialisation sequence readable.
>
Yes, makes total sense, I'll do this.
Thanks!
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 21/29] drm/i915: initialize DDI buffer translations
On Fri, Apr 13, 2012 at 18:11, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:57 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > - if (IS_HASWELL(dev))
> > + if (IS_HASWELL(dev)) {
> > intel_init_power_wells(dev);
> > + intel_hsw_prepare_ddi_buffers(dev);
> Give this a much more generic, more grandiose name and move the
> generation specific routines down a level:
> intel_init_ddi() [but make it more verbose and self-documenting!]
>
Will do.
> When you do that you'll might consider it to actually a part of the
> display initialisation and so move it down below intel_init_display().
> Remember it is vital for our sanity that we be able to concisely describe
> the sequence of steps required to initialise the GPU.
>
My initial idea here was to re-use the IS_HASWELL check to do all the
platform-specific stuff in one place, but with the suggestion above it
makes it much easier to move the intel_ddi_init into more logical position.
The specs ask to make sure that the DDI buffers translations are configured
correctly before attempting to enable them, so I thought on doing them
early in the process, so the further step assume that everything is up and
ready to use already. But yes, I believe that it could be done from within
intel_init_display as well, and it will be more logical indeed.
In both cases, I agree that it will make the driver code much more
self-explainable and easier to maintain. Huge thanks! I'll send a new
version with those comments addressed later.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: [GEN7] Use HW scheduler for fixed function shaders
On Sat, Apr 14, 2012 at 22:41, Ben Widawsky wrote: > This originally started as a patch from Bernard as a way of simply > setting the VS scheduler. After submitting the RFC patch, we decided to > also modify the DS scheduler. To be most explicit, I've made the patch > explicitly set all scheduler modes, and included the defines for other > modes (in case someone feels frisky later). > > The rest of the story gets a bit weird. The first version of the patch > showed an almost unbelievable performance improvement. Since rebasing my > branch it appears the performance improvement has gone, unfortunately. > But setting these bits seem to be the right thing to do given that the > docs describe corruption that can occur with the default settings. > > In summary, I am seeing no more perf improvements (or regressions) in my > limited testing, but we believe this should be set to prevent rendering > corruption, therefore cc stable. > > v1: Clear bit 4 also (Ken + Eugeni) > Do a full clear + set of the bits we want (Me). > > Cc: Bernard Kilarski > Cc: stable > Reviewed-by (RFC): Kenneth Graunke > Signed-off-by: Ben Widawsky > Very nice! I also suspect that maybe the initial performance improvement you've seen with previous testing could be related to the occasional turbo disabling we've been seeing in other cases as well (e.g., https://bugs.freedesktop.org/show_bug.cgi?id=44006). But as for this patch, I have just one comment/suggestion below, but other than that: Reviewed-by: Eugeni Dodonov +static void gen7_setup_fixed_func_scheduler(struct drm_i915_private > *dev_priv) > Perhaps this functions should be named ivybridge_setup_fixed_func_scheduler instead? Even if those bits are not ivy bridge-exclusive, this specific explicit setup applies to ivb only.. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: don't clobber the special upscaling lvds timings
On Sat, Apr 14, 2012 at 14:05, Chris Wilson wrote: > And most of that concern is due to the fact that the modesetting code > seems to have evolved ad-hoc with very few sanity checks and no > overarching design. > Yep, I have to agree on that :(. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: don't clobber the special upscaling lvds timings
On Sat, Apr 14, 2012 at 13:17, Daniel Vetter wrote: > This regression has been introduced in > > commit ca9bfa7eed20ea34e862804e62aae10eb159edbb > Author: Daniel Vetter > Date: Sat Jan 28 14:49:20 2012 +0100 > >drm/i915: fixup interlaced vertical timings confusion, part 1 > > Unfortunately that commit failed to take into account that the lvds > code does some special adjustements to the crtc timings for upscaling > an centering. > > Fix this by explicitly computing crtc timings in the lvds mode fixup > function and setting a special flag in mode->private_flags if the crtc > timings have been adjusted. > > Reported-and-Tested-by: Hans de Bruin > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43071 > Signed-Off-by: Daniel Vetter > As for the patch itself, as far as I can tell, it does what it meant to, so: Reviewed-by: Eugeni Dodonov I have one small suggestion in one hunk below, but that's it. - /* All interlaced capable intel hw wants timings in frames. */ > - drm_mode_set_crtcinfo(adjusted_mode, 0); > + /* All interlaced capable intel hw wants timings in frames. Note > though > +* that intel_lvds_mode_fixup does some funny tricks with the crtc > +* timings, so we need to be careful not to clobber these.*/ > + if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) > + drm_mode_set_crtcinfo(adjusted_mode, 0); > To simplify the life of next volunteers to touch those paths, perhaps we should improve the comment either here, or at the INTEL_MODE_CRTC_TIMING_SET definition, to mention that this flag should be set by any encoder that does its timing config on its own and does not wants his custom settings to get overwritten by the generic intel_crtc_mode_fixup() call? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] HDMI TV doesn't work over HDMI cable
On Sat, Apr 14, 2012 at 15:08, Dmitry Nezhevenko wrote: > Hi, > > I've got some really strange issue. I've followed GPU within ASUS MB: > > 00:02.0 VGA compatible controller: Intel Corporation Core Processor > Integrated Graphics Controller (rev 12) > > I'm trying to attach HDMI TV to it. My motherboard has both HDMI and DVI > outputs. So when I'm using DVI output together with cheap DVI->HDMI cable, > everything works. But once I switch to HDMI->HDMI, display is detected, > but display nothing. TV shows "No signal" message. > Hi, could you open a bug on this and attach those Xorg log files together with the 'dmesg' output when booting with the 'drm.debug=0xe' kernel parameter? And also your kernel version? The http://intellinuxgraphics.org/how_to_report_bug.html has a nice summary on how to collect all the data we need. One thing that would certainly help is if you could attach the diff between running 'intel_reg_dumper' with DVI and HDMI connections (running it over ssh for example, if you don't have any valid output with HDMI). The 'no signal' message means that we are sending TV data that it does not understands, but there are many possible cases why it could happen.. Intel_reg_dumper should give us a summary of what bits and registers could be wrong. -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 24/29] drm/i915: program iCLKIP on Lynx Point
On Sun, Apr 15, 2012 at 20:49, Daniel Vetter wrote: > > I'm honestly not too happy with this table, because somewhere in there > we'll have an annoying type, and there's almost zero chance we'll ever > find that. So I prefer if we can replicate the pixel clock computation > from some stupid excel sheet ... > The latest specs say that the table is the recommended way for configuring known clocks settings, for both iCLKIP and WR PLL, and the algorithm/formula should be used as fallback only. But I'll add them as well. One never knows when a new and previously unthinkable mode pops up :). -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Suggestions on fixing fill_modes ioctl() delays under i915
On Mon, Apr 16, 2012 at 09:04, Dan Aloni wrote: > Hello, > > I'd like to assist in fixing an issue that is quite nagging concerning the > i915 driver. I wasn't sure whether to classify this as a bug, but it's > something worth considering. Let me explain. > > When I first used the i915 driver on my Lenovo X220 laptop, I noticed that > every time I run xrandr, or when any X client tries to query the display > modes, the X server hangs for a second or so. Using systemtap, I was able > to track the hang to the Intel DRM driver, around the area in which it > talks over i2C in order to query the modes from display controller. > Could you try using the 3.4-rc1 or newer kernel by a chance? The patch that I initially sent in past October which improves the i2c interaction for output detection over 'phantom' outputs went in there, and so far it seems to improve the display detection timing by 30%-3000% (depending on hardware of course and number of outputs and such). -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: split power-related items into intel_pm module
On Mon, Apr 16, 2012 at 20:23, Chris Wilson wrote: > On Mon, 16 Apr 2012 20:06:01 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > As previously discussed on irc with Daniel, Ben and Jesse, This patch > > moves the power-related functionality into intel_pm module, aiming at > > simplifying the intel_display code and make it less cluttered. > > > > The functionality affected by this move are: clock gating, rc6 and rps, > > display watermarks, display fifo-related items, cxsr and FBC. > > > > This simplifies intel_display by +/- 2800 lines of code and centralizes > > most of the power-related items in one place to simplify future hardware > > enablement and subsystems interaction. > > Diff is making this really difficult to verify that no functional change > is taking place. Suggestions? A series of small commits? > I am fine with making it into a small series of commits which move 1 subsystem at a time (fbc, cxsr, rc6, fifo, wm, ...). Would everyone be happy with that? I think Daniel wanted to move everything in 1 commit, hence this initial approach from my side, but yes, as functions are spread all around the place it makes very hard to review the patch. But in general, does this idea of intel_pm.c looks interesting, or anyone has anything against it? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] refactor power management into intel_pm
As Chris Wilson noticed, my previous patch that did the refactoring as one big patch which moved everything at once was extremely difficult to review and maintain. So I split the same refactoring into a series of smaller patches, which move one subsystem at a time. As previously, this reduces the intel_display.c module by around 2800 lines while also simplifying future power-related developments. Eugeni Dodonov (5): drm/i915: move fbc-related functionality into intel_pm module drm/i915: move watermarks settings into intel_pm module drm/i915: move drps, rps and rc6-related functions to intel_pm drm/i915: move emon functionality into intel_pm module drm/i915: move clock gating functionality into intel_pm module drivers/gpu/drm/i915/Makefile|1 + drivers/gpu/drm/i915/intel_display.c | 7803 +++--- drivers/gpu/drm/i915/intel_drv.h | 72 + drivers/gpu/drm/i915/intel_pm.c | 2898 + 4 files changed, 5432 insertions(+), 5342 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_pm.c -- 1.7.10 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
