Re: [Intel-gfx] [PATCH 0/7] dma-buf: Add an API for exporting sync files (v11)
On Tue, May 25, 2021 at 2:18 PM Jason Ekstrand wrote: > Modern userspace APIs like Vulkan are built on an explicit > synchronization model. This doesn't always play nicely with the > implicit synchronization used in the kernel and assumed by X11 and > Wayland. The client -> compositor half of the synchronization isn't too > bad, at least on intel, because we can control whether or not i915 > synchronizes on the buffer and whether or not it's considered written. We might have an important use case for this half, for virtio-gpu and Chrome OS. When the guest compositor acts as a proxy to connect guest apps to the host compositor, implicit fencing requires the guest compositor to do a wait before forwarding the buffer to the host compositor. With this patch, the guest compositor can extract the dma-fence from the buffer, and if the fence is a virtio-gpu fence, forward both the fence and the buffer to the host compositor. It will allow us to convert a guest-side wait into a host-side wait. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH libdrm] intel: silence valgrind warnings for unsynchronized maps
Mark the address ranges as accessible with VALGRIND_MAKE_MEM_DEFINED.
Signed-off-by: Chia-I Wu
---
intel/intel_bufmgr_gem.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index a51e3f3..f98f7a7 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1322,6 +1322,7 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
int ret;
/* If the CPU cache isn't coherent with the GTT, then use a
@@ -1335,7 +1336,13 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
return drm_intel_gem_bo_map_gtt(bo);
pthread_mutex_lock(&bufmgr_gem->lock);
+
ret = map_gtt(bo);
+ if (ret == 0) {
+ drm_intel_gem_bo_mark_mmaps_incoherent(bo);
+ VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size));
+ }
+
pthread_mutex_unlock(&bufmgr_gem->lock);
return ret;
--
1.8.3.1
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[Intel-gfx] [RFC-PATCH libdrm] intel/aub: allow to dump only states
Add drm_intel_bufmgr_gem_set_aub_state_only to disable dumping of unannotated
or untyped data. The result should still be a valid AUB dump, in that it can
be fed to the simulator. But it will not trigger execution.
This can be used to dump states in binary form.
Signed-off-by: Chia-I Wu
---
intel/intel_bufmgr.h | 3 +++
intel/intel_bufmgr_gem.c | 47 +++
2 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 9383c72..46c25ce 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -180,6 +180,9 @@ void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo,
int write_enable);
void
drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
const char *filename);
+void
+drm_intel_bufmgr_gem_set_aub_state_only(drm_intel_bufmgr *bufmgr,
+ int enable);
void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
int x1, int y1, int width, int height,
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 007a6d8..c91cc3f 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -129,6 +129,7 @@ typedef struct _drm_intel_bufmgr_gem {
bool fenced_relocs;
char *aub_filename;
+ int aub_state_only;
FILE *aub_file;
uint32_t aub_offset;
} drm_intel_bufmgr_gem;
@@ -2018,6 +2019,7 @@ aub_write_large_trace_block(drm_intel_bo *bo, uint32_t
type, uint32_t subtype,
static void
aub_write_bo(drm_intel_bo *bo)
{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
uint32_t offset = 0;
unsigned i;
@@ -2029,19 +2031,42 @@ aub_write_bo(drm_intel_bo *bo)
drm_intel_aub_annotation *annotation =
&bo_gem->aub_annotations[i];
uint32_t ending_offset = annotation->ending_offset;
+ bool write;
+
+ if (ending_offset <= offset)
+ continue;
+
if (ending_offset > bo->size)
ending_offset = bo->size;
- if (ending_offset > offset) {
+
+ if (bufmgr_gem->aub_state_only) {
+ switch (annotation->type) {
+ case AUB_TRACE_TYPE_BATCH:
+ case AUB_TRACE_TYPE_CONSTANT_BUFFER:
+ case AUB_TRACE_TYPE_GENERAL:
+ case AUB_TRACE_TYPE_SURFACE:
+ write = true;
+ break;
+ default:
+ write = false;
+ break;
+ }
+ } else {
+ write = true;
+ }
+
+ if (write) {
aub_write_large_trace_block(bo, annotation->type,
annotation->subtype,
offset,
ending_offset - offset);
- offset = ending_offset;
}
+
+ offset = ending_offset;
}
/* Write out any remaining unannotated data */
- if (offset < bo->size) {
+ if (offset < bo->size && !bufmgr_gem->aub_state_only) {
aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
offset, bo->size - offset);
}
@@ -2170,7 +2195,8 @@ aub_exec(drm_intel_bo *bo, int ring_flag, int used)
drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
/* Dump ring buffer */
- aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag);
+ if (!bufmgr_gem->aub_state_only)
+ aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset,
ring_flag);
fflush(bufmgr_gem->aub_file);
@@ -2974,6 +3000,19 @@ drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr
*bufmgr,
}
/**
+ * Sets the AUB dumping rule.
+ *
+ * When true, only states are dumped.
+ */
+void
+drm_intel_bufmgr_gem_set_aub_state_only(drm_intel_bufmgr *bufmgr,
+ int enable)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
+ bufmgr_gem->aub_state_only = enable;
+}
+
+/**
* Sets up AUB dumping.
*
* This is a trace file format that can be used with the simulator.
--
1.8.5.3
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Re: [Intel-gfx] [RFC-PATCH libdrm] intel/aub: allow to dump only states
On Tue, Apr 15, 2014 at 3:37 PM, Chia-I Wu wrote:
> Add drm_intel_bufmgr_gem_set_aub_state_only to disable dumping of unannotated
> or untyped data. The result should still be a valid AUB dump, in that it can
> be fed to the simulator. But it will not trigger execution.
>
> This can be used to dump states in binary form.
The intended use is to create a binary and offline alternative of
Mesa's INTEL_DEBUG=batch. Right now the binary output can only be
decoded with deaub from https://github.com/olvaffe/envytools. But I
can update test_decode to accept AUB files if this change is welcomed.
deaub is an XML-based (rules-ng-ng based) command/state decoder for
GEN6+. I am also curious if there is any interest in it outside deaub
(and ilo).
>
> Signed-off-by: Chia-I Wu
> ---
> intel/intel_bufmgr.h | 3 +++
> intel/intel_bufmgr_gem.c | 47 +++
> 2 files changed, 46 insertions(+), 4 deletions(-)
>
> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
> index 9383c72..46c25ce 100644
> --- a/intel/intel_bufmgr.h
> +++ b/intel/intel_bufmgr.h
> @@ -180,6 +180,9 @@ void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo,
> int write_enable);
> void
> drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
> const char *filename);
> +void
> +drm_intel_bufmgr_gem_set_aub_state_only(drm_intel_bufmgr *bufmgr,
> + int enable);
> void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
> void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
>int x1, int y1, int width, int height,
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 007a6d8..c91cc3f 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -129,6 +129,7 @@ typedef struct _drm_intel_bufmgr_gem {
> bool fenced_relocs;
>
> char *aub_filename;
> + int aub_state_only;
> FILE *aub_file;
> uint32_t aub_offset;
> } drm_intel_bufmgr_gem;
> @@ -2018,6 +2019,7 @@ aub_write_large_trace_block(drm_intel_bo *bo, uint32_t
> type, uint32_t subtype,
> static void
> aub_write_bo(drm_intel_bo *bo)
> {
> + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)
> bo->bufmgr;
> drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
> uint32_t offset = 0;
> unsigned i;
> @@ -2029,19 +2031,42 @@ aub_write_bo(drm_intel_bo *bo)
> drm_intel_aub_annotation *annotation =
> &bo_gem->aub_annotations[i];
> uint32_t ending_offset = annotation->ending_offset;
> + bool write;
> +
> + if (ending_offset <= offset)
> + continue;
> +
> if (ending_offset > bo->size)
> ending_offset = bo->size;
> - if (ending_offset > offset) {
> +
> + if (bufmgr_gem->aub_state_only) {
> + switch (annotation->type) {
> + case AUB_TRACE_TYPE_BATCH:
> + case AUB_TRACE_TYPE_CONSTANT_BUFFER:
> + case AUB_TRACE_TYPE_GENERAL:
> + case AUB_TRACE_TYPE_SURFACE:
> + write = true;
> + break;
> + default:
> + write = false;
> + break;
> + }
> + } else {
> + write = true;
> + }
> +
> + if (write) {
> aub_write_large_trace_block(bo, annotation->type,
> annotation->subtype,
> offset,
> ending_offset - offset);
> - offset = ending_offset;
> }
> +
> + offset = ending_offset;
> }
>
> /* Write out any remaining unannotated data */
> - if (offset < bo->size) {
> + if (offset < bo->size && !bufmgr_gem->aub_state_only) {
> aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0,
> offset, bo->size - offset);
> }
> @@ -2170,7 +2195,8 @@ aub_exec(drm_intel_bo *bo, int ring_flag, int used)
> drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0);
>
> /* Dump ring buffer */
> - aub_build_dump_ringbuffer(bufmgr
Re: [Intel-gfx] [PATCH] Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"
On Tue, Mar 4, 2014 at 5:41 PM, Chris Wilson wrote:
> This reverts commit 116f2b6da868dec7539103574d0421cd6221e931.
>
> This optimization causes widespread corruption in games, and even in
> glxgears, on my ivb:gt1. The corruption appears like z-fighting of
> overlapping polygons in the HiZ buffer.
>
> The observation ties in very closely with the description of the
> optimization disabled by default on IVB:
>
> "The Hierarchical Z RAW Stall Optimization allows non-overlapping
> polygons in the same 8x4 pixel/sample area to be processed without
> stalling waiting for the earlier ones to write to Hierarchical Z
> buffer."
>
> No reason is given for why it is disabled by default, usually for such
> optimizations it is that it is incomplete. However, there is no
> indication whether this a gt1 only issue either. Before considering
> reenabling this optimization, I would first suggest reproducing the
> corruption in piglit.
I wonder if Haswell GT1 is affected too (that's in another commit). I
do not own a GT1 for either GEN to verify the issue or to create a
sensible piglit test.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75623
> Signed-off-by: Chris Wilson
> Cc: Chia-I Wu
> Cc: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b016d9bcd7c1..6b4d1a89e9bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4908,9 +4908,11 @@ static void ivybridge_init_clock_gating(struct
> drm_device *dev)
>
> gen7_setup_fixed_func_scheduler(dev_priv);
>
> - /* enable HiZ Raw Stall Optimization */
> - I915_WRITE(CACHE_MODE_0_GEN7,
> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> + if (0) { /* causes HiZ corruption on ivb:gt1 */
> + /* enable HiZ Raw Stall Optimization */
> + I915_WRITE(CACHE_MODE_0_GEN7,
> + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
> + }
>
> /* WaDisable4x2SubspanOptimization:ivb */
> I915_WRITE(CACHE_MODE_1,
> --
> 1.9.0
>
--
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Re: [Intel-gfx] [PATCH] Revert "drm/i915: enable HiZ Raw Stall Optimization on IVB"
On Wed, Mar 5, 2014 at 2:38 AM, Daniel Vetter wrote:
> On Tue, Mar 04, 2014 at 05:06:22PM +0200, Ville Syrjälä wrote:
>> On Tue, Mar 04, 2014 at 10:38:58PM +0800, Chia-I Wu wrote:
>> > On Tue, Mar 4, 2014 at 5:41 PM, Chris Wilson
>> > wrote:
>> > > This reverts commit 116f2b6da868dec7539103574d0421cd6221e931.
>> > >
>> > > This optimization causes widespread corruption in games, and even in
>> > > glxgears, on my ivb:gt1. The corruption appears like z-fighting of
>> > > overlapping polygons in the HiZ buffer.
>> > >
>> > > The observation ties in very closely with the description of the
>> > > optimization disabled by default on IVB:
>> > >
>> > > "The Hierarchical Z RAW Stall Optimization allows non-overlapping
>> > > polygons in the same 8x4 pixel/sample area to be processed without
>> > > stalling waiting for the earlier ones to write to Hierarchical Z
>> > > buffer."
>> > >
>> > > No reason is given for why it is disabled by default, usually for such
>> > > optimizations it is that it is incomplete. However, there is no
>> > > indication whether this a gt1 only issue either. Before considering
>> > > reenabling this optimization, I would first suggest reproducing the
>> > > corruption in piglit.
>> > I wonder if Haswell GT1 is affected too (that's in another commit). I
>> > do not own a GT1 for either GEN to verify the issue or to create a
>> > sensible piglit test.
>>
>> I'm seeing corruption on IVB GT2 as well. I might be more blind than
>> Chris or it's less subtle on GT2 since it took me a while to spot it.
>> Seems to be easiest to spot in Epic citadel when you go inside the
>> temple. I can't spot the same corruption on HSW GT3.
>
> Queued for -next, thanks for the patch. We can tackle hsw when that on
> blows up ...
I've created a simple demo that demonstrates the problem on IVB GT2,
FWIW. The patch is against mesa-demos. Not sure if there is a need
to make it a piglit test.
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
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From 00f78fa9c2162e97ff89e9131c53c7f7cd557949 Mon Sep 17 00:00:00 2001
From: Chia-I Wu
Date: Wed, 12 Mar 2014 15:12:43 +0800
Subject: [PATCH] ivb-hiz: demonstrate hiz depth stall opt bug on IVB
---
src/demos/Makefile.am | 1 +
src/demos/ivb-hiz.c | 110 ++
2 files changed, 111 insertions(+)
create mode 100644 src/demos/ivb-hiz.c
diff --git a/src/demos/Makefile.am b/src/demos/Makefile.am
index 41603fa..2333476 100644
--- a/src/demos/Makefile.am
+++ b/src/demos/Makefile.am
@@ -32,6 +32,7 @@ AM_LDFLAGS = \
if HAVE_GLUT
bin_PROGRAMS = \
+ ivb-hiz \
arbfplight \
arbfslight \
arbocclude \
diff --git a/src/demos/ivb-hiz.c b/src/demos/ivb-hiz.c
new file mode 100644
index 000..0404d80
--- /dev/null
+++ b/src/demos/ivb-hiz.c
@@ -0,0 +1,110 @@
+#include
+#include
+#include
+#include
+#include "glut_wrap.h"
+
+static GLfloat radius = 0.7f;
+static GLboolean grid = GL_FALSE;
+static int win_width, win_height;
+
+static void
+draw(void)
+{
+ const int num_triangles = 100;
+ const GLfloat delta = M_PI / 2.0f / num_triangles;
+ int i;
+
+ glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
+
+ glBegin(GL_TRIANGLE_FAN);
+ glColor3f(1.0, 1.0, 1.0);
+ glVertex2f(0.0f, 1.0f);
+ glVertex2f(radius, 1.0f);
+ for (i = 1; i <= num_triangles; i++) {
+ GLfloat angle = i * delta;
+ glVertex2f(radius * cos(angle), 1.0f - radius * sin(angle));
+ }
+ glEnd();
+
+ if (grid) {
+ glDisable(GL_DEPTH_TEST);
+ glColor3f(1.0, 0.0, 0.0);
+
+ glPushMatrix();
+ glLoadIdentity();
+ glBegin(GL_LINES);
+
+ for (i = 0; 8 * i < win_width; i++) {
+ glVertex2f(8 * i + 0.5f, 0.0f);
+ glVertex2f(8 * i + 0.5f, win_height);
+ }
+
+ for (i = 0; 8 * i < win_height; i++) {
+ glVertex2f(0.0f, win_height - 8 * i - 0.5f);
+ glVertex2f(win_width, win_height - 8 * i - 0.5f);
+ }
+
+ glEnd();
+ glPopMatrix();
+ glEnable(GL_DEPTH_TEST);
+ }
+
+ glutSwapBuffers();
+ glutPostRedisplay();
+}
+
+static void
+key(unsigned char k, int x, int y)
+{
+ switch (k) {
+ case 'r':
+ radius -= 0.01f;
+ break;
+ case 'R':
+ radius += 0.01f;
+ break;
+ case 'g':
+ grid = !grid;
+ break;
+ case 27: /* Escape */
+exit(0);
+ }
+}
+
+static void
+reshape(int width, int height)
+{
+ glViewport(0, 0, width, height);
+
+ glMatrixMode(GL_PROJECTION);
+ glLoadIdentity();
+ glOrtho(0.0, widt
[Intel-gfx] [PATCH] drm/i915: enable HiZ Raw Stall Optimization
From: Chia-I Wu The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test. Signed-off-by: Chia-I Wu Cc: Ian Romanick Cc: Chad Versace --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/i915_suspend.c | 9 +++-- drivers/gpu/drm/i915/intel_pm.c | 8 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ee27421..bd90ef3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -930,6 +930,8 @@ #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE(1<<0) +#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 98790c7..13fefbd 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev) intel_disable_gt_powersave(dev); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_INFO(dev)->gen >= 7) + dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0_GEN7); + else dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ @@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev) } /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_INFO(dev)->gen >= 7) + I915_WRITE(CACHE_MODE_0_GEN7, dev_priv->regfile.saveCACHE_MODE_0 | + 0x); + else I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0x); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 26c29c1..d6ddc39 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:hsw */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:hsw */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); @@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:ivb */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:ivb */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- 1.8.5.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: enable HiZ Raw Stall Optimization
[Additional comments, and copy Ian and Chad for real] On Mon, Jan 27, 2014 at 4:18 PM, Chia-I Wu wrote: > From: Chia-I Wu > > The optimization is available on Ivy Bridge and later, and is disabled by > default. Enabling it helps certain workloads such as GLBenchmark TRex test. With the patch applied, GLB27_TRex_C24Z16_FixedTimeStep goes from 99fps to 109fps on my Haswell, and from 60fps to 65fps on my Ivy Bridge. No piglit regression on both GENs. I had a non-recoverable system hang once with the patch applied. I was not sure if it is because of the patch or drm-intel-nightly (which I checkout out some weeks ago). I did my tests today against latest drm-intel-next, and did not have any hang. Since the optimization is disabled by default, I am curious if there is any caveat before enabling it. > > Signed-off-by: Chia-I Wu > Cc: Ian Romanick > Cc: Chad Versace > > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/i915_suspend.c | 9 +++-- > drivers/gpu/drm/i915/intel_pm.c | 8 > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ee27421..bd90ef3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -930,6 +930,8 @@ > #define ECO_GATING_CX_ONLY (1<<3) > #define ECO_FLIP_DONE(1<<0) > > +#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ > +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) > #define CACHE_MODE_1 0x7004 /* IVB+ */ > #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c > b/drivers/gpu/drm/i915/i915_suspend.c > index 98790c7..13fefbd 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev) > intel_disable_gt_powersave(dev); > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_INFO(dev)->gen >= 7) > + dev_priv->regfile.saveCACHE_MODE_0 = > I915_READ(CACHE_MODE_0_GEN7); > + else > dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > /* Memory Arbitration state */ > @@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev) > } > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_INFO(dev)->gen >= 7) > + I915_WRITE(CACHE_MODE_0_GEN7, > dev_priv->regfile.saveCACHE_MODE_0 | > + 0x); > + else > I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | >0x); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 26c29c1..d6ddc39 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct > drm_device *dev) > /* WaVSRefCountFullforceMissDisable:hsw */ > gen7_setup_fixed_func_scheduler(dev_priv); > > + /* enable HiZ Raw Stall Optimization */ > + I915_WRITE(CACHE_MODE_0_GEN7, > + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); > + > /* WaDisable4x2SubspanOptimization:hsw */ > I915_WRITE(CACHE_MODE_1, >_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > @@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct > drm_device *dev) > /* WaVSRefCountFullforceMissDisable:ivb */ > gen7_setup_fixed_func_scheduler(dev_priv); > > + /* enable HiZ Raw Stall Optimization */ > + I915_WRITE(CACHE_MODE_0_GEN7, > + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); > + > /* WaDisable4x2SubspanOptimization:ivb */ > I915_WRITE(CACHE_MODE_1, >_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > -- > 1.8.5.3 > -- o...@lunarg.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: enable HiZ Raw Stall Optimization
On Mon, Jan 27, 2014 at 9:07 PM, Ville Syrjälä wrote: > On Mon, Jan 27, 2014 at 04:18:36PM +0800, Chia-I Wu wrote: >> From: Chia-I Wu >> >> The optimization is available on Ivy Bridge and later, and is disabled by >> default. Enabling it helps certain workloads such as GLBenchmark TRex test. > > Actually BSpec even goes as far as saying that this optimization must > be enabled on HSW+. The public documentation actually says if you want the optimization, you must enable it. Kind of stating the obvious. :) > So it seems you should enable it for BDW as well. I'm not sure about VLV. > The description of the bit says nothing about VLV, even though the > documented default value is specified to have it set for VLV as well. I > guess someone should just try it and see what happens. > > Might make sense to split the patch into per-platforms patches. That way > we could more easily revert eg. just the IVB part if it causes problems. Will do. Though I will leave BDW/VLV out as I do not have the hardware. >> >> Signed-off-by: Chia-I Wu >> Cc: Ian Romanick >> Cc: Chad Versace >> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 2 ++ >> drivers/gpu/drm/i915/i915_suspend.c | 9 +++-- >> drivers/gpu/drm/i915/intel_pm.c | 8 >> 3 files changed, 17 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h >> index ee27421..bd90ef3 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -930,6 +930,8 @@ >> #define ECO_GATING_CX_ONLY (1<<3) >> #define ECO_FLIP_DONE (1<<0) >> >> +#define CACHE_MODE_0_GEN70x7000 /* IVB+ */ >> +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) >> #define CACHE_MODE_1 0x7004 /* IVB+ */ >> #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) >> >> diff --git a/drivers/gpu/drm/i915/i915_suspend.c >> b/drivers/gpu/drm/i915/i915_suspend.c >> index 98790c7..13fefbd 100644 >> --- a/drivers/gpu/drm/i915/i915_suspend.c >> +++ b/drivers/gpu/drm/i915/i915_suspend.c >> @@ -398,7 +398,9 @@ int i915_save_state(struct drm_device *dev) >> intel_disable_gt_powersave(dev); >> >> /* Cache mode state */ >> - if (INTEL_INFO(dev)->gen < 7) >> + if (INTEL_INFO(dev)->gen >= 7) >> + dev_priv->regfile.saveCACHE_MODE_0 = >> I915_READ(CACHE_MODE_0_GEN7); >> + else >> dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); >> >> /* Memory Arbitration state */ >> @@ -448,7 +450,10 @@ int i915_restore_state(struct drm_device *dev) >> } >> >> /* Cache mode state */ >> - if (INTEL_INFO(dev)->gen < 7) >> + if (INTEL_INFO(dev)->gen >= 7) >> + I915_WRITE(CACHE_MODE_0_GEN7, >> dev_priv->regfile.saveCACHE_MODE_0 | >> +0x); >> + else >> I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | >> 0x); > > These hunks are material for a separate patch. > >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c >> b/drivers/gpu/drm/i915/intel_pm.c >> index 26c29c1..d6ddc39 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -5355,6 +5355,10 @@ static void haswell_init_clock_gating(struct >> drm_device *dev) >> /* WaVSRefCountFullforceMissDisable:hsw */ >> gen7_setup_fixed_func_scheduler(dev_priv); >> >> + /* enable HiZ Raw Stall Optimization */ >> + I915_WRITE(CACHE_MODE_0_GEN7, >> +_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); >> + >> /* WaDisable4x2SubspanOptimization:hsw */ >> I915_WRITE(CACHE_MODE_1, >> _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); >> @@ -5445,6 +5449,10 @@ static void ivybridge_init_clock_gating(struct >> drm_device *dev) >> /* WaVSRefCountFullforceMissDisable:ivb */ >> gen7_setup_fixed_func_scheduler(dev_priv); >> >> + /* enable HiZ Raw Stall Optimization */ >> + I915_WRITE(CACHE_MODE_0_GEN7, >> +_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); >> + >> /* WaDisable4x2SubspanOptimization:ivb */ >> I915_WRITE(CACHE_MODE_1, >> _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); >> -- >> 1.8.5.3 >> >> ___ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC -- o...@lunarg.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: enable HiZ Raw Stall Optimization on IVB
From: Chia-I Wu The optimization helps IVB too. No piglit regression. Signed-off-by: Chia-I Wu --- drivers/gpu/drm/i915/intel_pm.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c535e5c..58aba3e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4881,6 +4881,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:ivb */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:ivb */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: enable HiZ Raw Stall Optimization on HSW
From: Chia-I Wu The optimization is available on Ivy Bridge and later, and is disabled by default. Enabling it helps certain workloads such as GLBenchmark TRex test. No piglit regression. v2 - no need to save the register before suspend as init_clock_gating can correctly program it after resume - split IVB change to another commit Signed-off-by: Chia-I Wu --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 4 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 76126e0..c74bc28 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -934,6 +934,8 @@ #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE(1<<0) +#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ +#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d77cc81..c535e5c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4789,6 +4789,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaVSRefCountFullforceMissDisable:hsw */ gen7_setup_fixed_func_scheduler(dev_priv); + /* enable HiZ Raw Stall Optimization */ + I915_WRITE(CACHE_MODE_0_GEN7, + _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); + /* WaDisable4x2SubspanOptimization:hsw */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); -- 1.8.3.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix current fb blocking for page flip.
Hi list,
According to the doc for page_flip, intel_crtc_page_flip should
... block all rendering to the current fb until the flip has
completed.
I am not entirely sure, but it seems that it is
work->old_fb_obj->pending_flip that needs to be incremented instead of
work->pending_flip_obj->pending_flip. This patch does fix the
rendering artifacts with my Android on i915 project. Any thought?
--
o...@lunarg.com
From fd72d779b84d70bac104d5d46541e3ac1ced6f35 Mon Sep 17 00:00:00 2001
From: Chia-I Wu
Date: Thu, 21 Oct 2010 16:39:14 +0800
Subject: [PATCH] drm/i915: Fix current fb blocking for page flip.
Block execbuffer for the fb to be flipped away, not the one that is to
be flipped in.
Signed-off-by: Chia-I Wu
---
drivers/gpu/drm/i915/intel_display.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9792285..41bf75a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4928,7 +4928,7 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
spin_unlock_irqrestore(&dev->event_lock, flags);
- obj_priv = to_intel_bo(work->pending_flip_obj);
+ obj_priv = to_intel_bo(work->old_fb_obj);
/* Initial scanout buffer will have a 0 pending flip count */
if ((atomic_read(&obj_priv->pending_flip) == 0) ||
@@ -5031,8 +5031,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_objs;
- obj_priv = to_intel_bo(obj);
+ obj_priv = to_intel_bo(work->old_fb_obj);
atomic_inc(&obj_priv->pending_flip);
+
+ obj_priv = to_intel_bo(obj);
work->pending_flip_obj = obj;
if (IS_GEN3(dev) || IS_GEN2(dev)) {
--
1.7.1
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[Intel-gfx] [PATCH] drm/i915: fix current fb blocking for flipping.
Block execbuffer for the fb to be flipped away, not the one that is to be flipped in. Signed-off-by: Chia-I Wu --- drivers/gpu/drm/i915/intel_display.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5e21b31..2e8cf7d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4664,7 +4664,7 @@ static void do_intel_finish_page_flip(struct drm_device *dev, spin_unlock_irqrestore(&dev->event_lock, flags); - obj_priv = to_intel_bo(work->pending_flip_obj); + obj_priv = to_intel_bo(work->old_fb_obj); /* Initial scanout buffer will have a 0 pending flip count */ if ((atomic_read(&obj_priv->pending_flip) == 0) || @@ -4729,6 +4729,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->dev = crtc->dev; intel_fb = to_intel_framebuffer(crtc->fb); work->old_fb_obj = intel_fb->obj; + obj_priv = to_intel_bo(intel_fb->obj); + atomic_inc(&obj_priv->pending_flip); INIT_WORK(&work->work, intel_unpin_work_fn); /* We borrow the event spin lock for protecting unpin_work */ @@ -4770,7 +4772,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, i915_gem_object_flush_write_domain(obj); drm_vblank_get(dev, intel_crtc->pipe); obj_priv = to_intel_bo(obj); - atomic_inc(&obj_priv->pending_flip); work->pending_flip_obj = obj; if (intel_crtc->plane) -- 1.7.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fix current fb blocking for flipping.
On Fri, Oct 22, 2010 at 12:56 AM, Jesse Barnes wrote: > On Thu, 21 Oct 2010 17:32:30 +0800 > Chia-I Wu wrote: > >> Block execbuffer for the fb to be flipped away, not the one that is to >> be flipped in. > I think we want to block rendering on both? Otherwise we could display > partial drawing in the new buffer. I sent the wrong patch accidentally. Please ignore this one. -- o...@lunarg.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix current fb blocking for page flip.
On Fri, Oct 22, 2010 at 12:18 AM, Jesse Barnes wrote: > On Thu, 21 Oct 2010 17:55:13 +0800 > Chia-I Wu wrote: > >> Hi list, >> >> According to the doc for page_flip, intel_crtc_page_flip should >> >> ... block all rendering to the current fb until the flip has >> completed. >> >> I am not entirely sure, but it seems that it is >> work->old_fb_obj->pending_flip that needs to be incremented instead of >> work->pending_flip_obj->pending_flip. This patch does fix the >> rendering artifacts with my Android on i915 project. Any thought? > In intel_crtc_page_flip()? It *looks* like incrementing the flip count > for the fb passed into the routine is the right thing to do; we want to > make sure the fb passed in isn't used again until its flip is complete. If one flips a buffer and immediately renders to it, the caller should know that the buffer is the front buffer and there will be artifacts. Waiting for the flip here makes less sense. A common use of page flip looks like [X being the front buffer] 1) render to Y 2) flip Y 3) render to X 4) flip X 5) render to Y A caller expects 3) to be back buffer rendering. It is reasonable to insert a wait between 2) and 3). That is, have pending_flip of X, instead of Y, set at 2). > But maybe we're decrementing it incorrectly in the buffer exec path or > allowing rendering to continue too soon? > -- > Jesse Barnes, Intel Open Source Technology Center > -- o...@lunarg.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fix wait ioctl with negative timeout
When timeout_ns is negative, it really means to wait indefinitely instead of
returning immediately. But since userspace can no longer rely on that, I am
not sure if there is any point fixing it.
Signed-off-by: Chia-I Wu
---
drivers/gpu/drm/i915/i915_gem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ad55b06..3da2d62 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2787,9 +2787,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
goto out;
/* Do this after OLR check to make sure we make forward progress polling
-* on this IOCTL with a timeout <=0 (like busy ioctl)
+* on this IOCTL with a timeout == 0 (like busy ioctl)
*/
- if (args->timeout_ns <= 0) {
+ if (args->timeout_ns == 0) {
ret = -ETIME;
goto out;
}
@@ -2798,7 +2798,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
mutex_unlock(&dev->struct_mutex);
- return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
+ return __wait_seqno(ring, seqno, reset_counter, true,
+ (args->timeout_ns > 0) ? &args->timeout_ns : NULL,
file->driver_priv);
out:
--
2.1.1
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Re: [Intel-gfx] [PATCH] drm/i915: fix wait ioctl with negative timeout
On Sun, Oct 12, 2014 at 1:21 AM, Chia-I Wu wrote:
> When timeout_ns is negative, it really means to wait indefinitely instead
> of
> returning immediately. But since userspace can no longer rely on that, I
> am
> not sure if there is any point fixing it.
>
Note that userspace may use GL_TIMEOUT_IGNORED for timeout_ns to wait
indefinitely. The macro is defined to
#define GL_TIMEOUT_IGNORED0xull
Prior to 3.17, the kernel would behave as expected. But on 3.17, it would
return immediately with -ETIME if the bo is busy.
>
> Signed-off-by: Chia-I Wu
> ---
> drivers/gpu/drm/i915/i915_gem.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index ad55b06..3da2d62 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2787,9 +2787,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void
> *data, struct drm_file *file)
> goto out;
>
> /* Do this after OLR check to make sure we make forward progress
> polling
> -* on this IOCTL with a timeout <=0 (like busy ioctl)
> +* on this IOCTL with a timeout == 0 (like busy ioctl)
> */
> - if (args->timeout_ns <= 0) {
> + if (args->timeout_ns == 0) {
> ret = -ETIME;
> goto out;
> }
> @@ -2798,7 +2798,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void
> *data, struct drm_file *file)
> reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
> mutex_unlock(&dev->struct_mutex);
>
> - return __wait_seqno(ring, seqno, reset_counter, true,
> &args->timeout_ns,
> + return __wait_seqno(ring, seqno, reset_counter, true,
> + (args->timeout_ns > 0) ? &args->timeout_ns :
> NULL,
> file->driver_priv);
>
> out:
> --
> 2.1.1
>
>
--
o...@lunarg.com
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