✓ Fi.CI.BAT: success for drm: Support per-plane async flip configuration
== Series Details ==
Series: drm: Support per-plane async flip configuration
URL : https://patchwork.freedesktop.org/series/134900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134900v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134900v1/index.html
Participating hosts (43 -> 35)
--
Missing(8): bat-kbl-2 bat-adlp-9 fi-tgl-1115g4 bat-adlp-6 fi-snb-2520m
bat-dg2-14 bat-jsl-1 bat-arlh-2
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_134900v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-9:
- {bat-mtlp-9}: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134900v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-b-dp-9.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-8:
- {bat-mtlp-9}: [PASS][2] -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-8.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134900v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-n...@pipe-c-dp-8.html
Known issues
Here are the changes found in Patchwork_134900v1 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
Build changes
-
* Linux: CI_DRM_14943 -> Patchwork_134900v1
CI-20190529: 20190529
CI_DRM_14943: 00e9498b453447a5afe527bd0e174587b12f66d2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7888: 021538d059575eb9f93d36fea36015cd3f9fca7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_134900v1: 00e9498b453447a5afe527bd0e174587b12f66d2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134900v1/index.html
RE: [PATCH v8 05/20] drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 05/20] drm/i915/psr: Disable Panel Replay if PSR mode is
> set via module parameter
>
> If enable_psr module parameter is set as disabled, PSR1 or PSR2: Panel
> Replay is disabled.
This patch is modifying the way how to enable/disable panel-replay/psr/psr2
through kernel cmdline.
Good to have little more detailed commit description. Patch commit title and
description is different but agree are true.
>
> Signed-off-by: Jouni Högander
> ---
> .../gpu/drm/i915/display/intel_display_params.c | 3 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 16
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c
> b/drivers/gpu/drm/i915/display/intel_display_params.c
> index aebdb7b59dbf..79107607a6ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -106,8 +106,7 @@ intel_display_param_named_unsafe(enable_fbc, int,
> 0400,
>
> intel_display_param_named_unsafe(enable_psr, int, 0400,
> "Enable PSR "
> - "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame
> update, "
> - "2=enable up to PSR2 and Panel Replay Selective Update) "
> + "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) "
> "Default: -1 (use per-chip default)");
>
> intel_display_param_named(psr_safest_params, bool, 0400, diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f8e746e476e9..0df557676e08 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -235,6 +235,15 @@ static bool psr2_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> +static bool panel_replay_global_enabled(struct intel_dp *intel_dp) {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (i915->display.params.enable_psr != -1)
> + return false;
> + return true;
> +}
> +
> static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 1457,9 +1466,16 @@ static bool _psr_compute_config(struct intel_dp
> *intel_dp,
>
> static bool _panel_replay_compute_config(struct intel_dp *intel_dp) {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> if (!CAN_PANEL_REPLAY(intel_dp))
> return false;
>
> + if (!panel_replay_global_enabled(intel_dp)) {
> + drm_dbg_kms(&i915->drm, "Panel Replay disabled by flag\n");
> + return false;
> + }
Just a nitpick: Maybe can add an extra debug print like below,
if (!panel_replay_global_enabled(intel_dp)) {
if (i915->display.params.enable_psr)
drm_dbg_kms(&i915->drm, "Panel Replay disabled as PSR
is enabled\n");
else
drm_dbg_kms(&i915->drm, "Panel Replay disabled by
flag\n");
return false;
}
Regards,
Animesh
> +
> return true;
> }
>
> --
> 2.34.1
RE: [PATCH v8 06/20] drm/i915/psr: Disable PSR2 SU Region Early Transport if psr_enable is set
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 06/20] drm/i915/psr: Disable PSR2 SU Region Early
> Transport if psr_enable is set
>
> Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake
> if panel supports it despite psr_enable value. Prevent SU Region Early
> Transport if psr_enable is set to than -1 which is the default.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 0df557676e08..27cf330d13e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> +static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (i915->display.params.enable_psr != -1)
> + return false;
> +
> + return true;
> +}
> +
> static bool panel_replay_global_enabled(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -683,7
> +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp,
> bool panel_replay
>
> return panel_replay ?
> intel_dp->pr_dpcd &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> - intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
> + intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> + psr2_su_region_et_global_enabled(intel_dp);
How to enable early transport with psr/psr2? Is it not possible now/future?
Regards,
Animesh
> }
>
> static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> --
> 2.34.1
RE: [PATCH v8 07/20] drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 07/20] drm/i915/psr: Disable PSR/Panel Replay on sink
> side for PSR only
>
> Enabling/disabling Panel Replay on sink side has to be done before link
> training. We can't disable it in sink side on PSR disable.
>
> Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink")
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 12 ++--
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 27cf330d13e2..7300d04806cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1974,13 +1974,13 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
> }
>
> /* Disable PSR on Sink */
> - drm_dp_dpcd_writeb(&intel_dp->aux,
> -intel_dp->psr.panel_replay_enabled ?
> -PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG, 0);
> + if (!intel_dp->psr.panel_replay_enabled) {
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
>
> - if (!intel_dp->psr.panel_replay_enabled &&
> - intel_dp->psr.sel_update_enabled)
> - drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG, 0);
> + if (intel_dp->psr.sel_update_enabled)
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> +DP_RECEIVER_ALPM_CONFIG, 0);
> + }
>
> intel_dp->psr.enabled = false;
> intel_dp->psr.panel_replay_enabled = false;
> --
> 2.34.1
Re: Linux 6.10-rc1
On Fri, 14 Jun 2024 at 09:21, Linus Torvalds wrote: > > Let's bring in the actual gpu people.. Dave/Jani/others - does any of > this sound familiar? Pavel says things have gotten much slower in > 6.10: "something was very wrong with the performance, likely to do > with graphics" Actually, maybe it's not graphics at all. Rafael just sent me a pull request that fixes a "turbo is disabled at boot, but magically enabled at runtime by firmware" issue. The 6.10-rc1 kernel would notice that turbo was disabled, and stopped noticing that it magically got re-enabled. Pavel, that was with a very different laptop, but who knows... That would match the "laptop is much slower" thing. So current -git might be worth checking. Linus
RE: [PATCH v8 08/20] drm/i915/psr: Add new debug bit to disable Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, June 13, 2024 3:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v8 08/20] drm/i915/psr: Add new debug bit to disable Panel
> Replay
>
> Add new debug bit to be used with i915_edp_psr_debug debugfs interface.
> This can be used to disable Panel Replay.
>
> v2: ensure that fastset is performed when the bit changes
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ---
> 2 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 4ee760bd26f7..b8980e8b4c36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1697,6 +1697,7 @@ struct intel_psr {
> #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
> #define I915_PSR_DEBUG_IRQ 0x10
> #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
> +#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> bool sink_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7300d04806cd..cd77cfeba679 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -249,7 +249,8 @@ static bool panel_replay_global_enabled(struct
> intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - if (i915->display.params.enable_psr != -1)
> + if ((i915->display.params.enable_psr != -1) ||
> + (intel_dp->psr.debug &
> I915_PSR_DEBUG_PANEL_REPLAY_DISABLE))
> return false;
> return true;
> }
> @@ -2788,11 +2789,13 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
> - const u32 disable_bits = val &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
> + const u32 disable_bits = val &
> (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> +
> I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
> u32 old_mode, old_disable_bits;
> int ret;
>
> if (val & ~(I915_PSR_DEBUG_IRQ |
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE |
> I915_PSR_DEBUG_MODE_MASK) ||
> mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n",
> val); @@ -2805,7 +2808,9 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val)
>
> old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
> old_disable_bits = intel_dp->psr.debug &
> - I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
> + (I915_PSR_DEBUG_SU_REGION_ET_DISABLE |
> + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
> +
> intel_dp->psr.debug = val;
>
> /*
> --
> 2.34.1
RE: [PATCH v8 09/20] Revert "drm/i915/psr: Disable early transport by default"
> -Original Message- > From: Hogander, Jouni > Sent: Thursday, June 13, 2024 3:02 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Kahola, Mika > ; Hogander, Jouni > Subject: [PATCH v8 09/20] Revert "drm/i915/psr: Disable early transport by > default" > > This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. > > We want to notice possible issues faced with PSR2 Region Early Transport as > early as possible -> let's revert patch disabling Region Early Transport by > default. Also eDP 1.5 Panel Replay requires Early Transport. > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index cd77cfeba679..db5f98e3a0db 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -3110,9 +3110,6 @@ void intel_psr_init(struct intel_dp *intel_dp) > else > intel_dp->psr.source_support = true; > > - /* Disable early transport for now */ > - intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; > - > /* Set link_standby x link_off defaults */ > if (DISPLAY_VER(dev_priv) < 12) > /* For new platforms up to TGL let's respect VBT back again > */ > -- > 2.34.1
Re: [PATCH v6 2/8] drm: Support per-plane async flip configuration
On Fri, Jun 14, 2024 at 12:35:29PM GMT, André Almeida wrote:
> Drivers have different capabilities on what plane types they can or
> cannot perform async flips. Create a plane::async_flip field so each
> driver can choose which planes they allow doing async flips.
>
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
> include/drm/drm_plane.h | 5 +
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 2e1d9391febe..ed1af3455477 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -1079,9 +1079,9 @@ int drm_atomic_set_property(struct drm_atomic_state
> *state,
> break;
> }
>
> - if (async_flip && plane_state->plane->type !=
> DRM_PLANE_TYPE_PRIMARY) {
> + if (async_flip && !plane->async_flip) {
So, after this patch async flips becomes disabled until the driver
enables that manually. Whether that's desired or not is a separate
topic, but this definitely should be explicitly mentioned in the commit
message.
> drm_dbg_atomic(prop->dev,
> -"[OBJECT:%d] Only primary planes can be
> changed during async flip\n",
> +"[PLANE:%d] does not support async
> flips\n",
> obj->id);
> ret = -EINVAL;
> break;
> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
> index 9507542121fa..0bebc72af5c3 100644
> --- a/include/drm/drm_plane.h
> +++ b/include/drm/drm_plane.h
> @@ -786,6 +786,11 @@ struct drm_plane {
>* @kmsg_panic: Used to register a panic notifier for this plane
>*/
> struct kmsg_dumper kmsg_panic;
> +
> + /**
> + * @async_flip: indicates if a plane can do async flips
> + */
> + bool async_flip;
> };
>
> #define obj_to_plane(x) container_of(x, struct drm_plane, base)
> --
> 2.45.2
>
--
With best wishes
Dmitry
Re: [PATCH v6 0/8] drm: Support per-plane async flip configuration
On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote: > AMD hardware can do async flips with overlay planes, but currently there's no > easy way to enable that in DRM. To solve that, this patchset creates a new > drm_plane field, bool async_flip, that allows drivers to choose which plane > can > or cannot do async flips. This is latter used on drm_atomic_set_property when > users want to do async flips. > > Patch 1 allows async commits with IN_FENCE_ID in any driver. > > Patches 2 to 7 have no function change. As per current code, every driver that > allows async page flips using the atomic API, allows doing it only in the > primary plane. Those patches then enable it for every driver. > > Patch 8 finally enables async flip on overlay planes for amdgpu. > > Changes from v5: > - Instead of enabling plane->async_flip in the common code, move it to driver > code. > - Enable primary plane async flip on every driver > https://lore.kernel.org/dri-devel/20240612193713.167448-1-andrealm...@igalia.com/ > > André Almeida (8): > drm/atomic: Allow userspace to use explicit sync with atomic async > flips > drm: Support per-plane async flip configuration > drm/amdgpu: Enable async flips on the primary plane > drm: atmel-hlcdc: Enable async flips on the primary plane > drm/i915: Enable async flips on the primary plane > drm/nouveau: Enable async flips on the primary plane > drm/vc4: Enable async flips on the primary plane > drm/amdgpu: Make it possible to async flip overlay planes > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++ > drivers/gpu/drm/drm_atomic_uapi.c | 8 +--- > drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++ > drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 > drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 > drivers/gpu/drm/vc4/vc4_plane.c | 4 +++- The main question is why only these drivers were updated. > include/drm/drm_plane.h | 5 + > 8 files changed, 29 insertions(+), 4 deletions(-) > > -- > 2.45.2 > -- With best wishes Dmitry
[PATCH 0/9] drm/i915: Dump DSC state to dmesg/debugfs
Add a DRM core helper to dump the DSC state and take this into use in the i915 driver to dump the state to dmesg after state computation and HW readout as well as to the i915_display_info debugfs entry. The state contains an x16 fixed point value, so also move the corresponding bpp_x16 helpers from i915 to DRM core. Imre Deak (9): drm: Add helpers for x16 fixed point values drm/display/dsc: Add a helper to dump the DSC configuration drm/i915: Replace to_bpp_x16() with drm_x16_from_int() drm/i915: Replace to_bpp_int() with drm_x16_to_int() drm/i915: Replace to_bpp_int_roundup() with drm_x16_to_int_roundup() drm/i915: Replace to_bpp_frac() with drm_x16_to_frac() drm/i915: Replace BPP_X16_FMT()/ARGS() with DRM_X16_FMT()/ARGS() drm/i915: Dump DSC state to dmesg and debugfs/i915_display_info drm/i915: Remove DSC register dump drivers/gpu/drm/display/drm_dp_helper.c | 5 +- drivers/gpu/drm/display/drm_dsc_helper.c | 91 +++ drivers/gpu/drm/i915/display/icl_dsi.c| 9 +- drivers/gpu/drm/i915/display/intel_audio.c| 5 +- drivers/gpu/drm/i915/display/intel_bios.c | 5 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- .../drm/i915/display/intel_crtc_state_dump.c | 3 + drivers/gpu/drm/i915/display/intel_display.c | 7 +- .../drm/i915/display/intel_display_debugfs.c | 4 + .../drm/i915/display/intel_display_types.h| 23 - drivers/gpu/drm/i915/display/intel_dp.c | 51 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 26 +++--- drivers/gpu/drm/i915/display/intel_fdi.c | 6 +- drivers/gpu/drm/i915/display/intel_link_bw.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 51 ++- drivers/gpu/drm/i915/display/intel_vdsc.h | 4 + include/drm/display/drm_dsc_helper.h | 3 + include/drm/drm_fixed.h | 23 + 18 files changed, 221 insertions(+), 103 deletions(-) -- 2.43.3
[PATCH 1/9] drm: Add helpers for x16 fixed point values
Add helpers to convert between x16 fixed point and integer/fraction
values. Also add the format/argument macros required to printk x16
fixed point variables.
These are needed by later patches dumping the Display Stream Compression
configuration in DRM core and in the i915 driver to replace the
corresponding bpp_x16 helpers defined locally in the driver.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_helper.c | 5 +++--
include/drm/drm_fixed.h | 23 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index 79a615667aab1..806f9c9764995 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -4151,9 +4152,9 @@ int drm_dp_bw_overhead(int lane_count, int hactive,
int symbol_cycles;
if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
- DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d,
hactive %d, bpp_x16 %d.%04d\n",
+ DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d,
hactive %d, bpp_x16 " DRM_X16_FMT "\n",
lane_count, hactive,
- bpp_x16 >> 4, (bpp_x16 & 0xf) * 625);
+ DRM_X16_ARGS(bpp_x16));
return 0;
}
diff --git a/include/drm/drm_fixed.h b/include/drm/drm_fixed.h
index 81572d32db0c2..0fe2a7f50d54e 100644
--- a/include/drm/drm_fixed.h
+++ b/include/drm/drm_fixed.h
@@ -214,4 +214,27 @@ static inline s64 drm_fixp_exp(s64 x)
return sum;
}
+static inline int drm_x16_from_int(int val_int)
+{
+ return val_int << 4;
+}
+
+static inline int drm_x16_to_int(int val_x16)
+{
+ return val_x16 >> 4;
+}
+
+static inline int drm_x16_to_int_roundup(int val_x16)
+{
+ return (val_x16 + 0xf) >> 4;
+}
+
+static inline int drm_x16_to_frac(int val_x16)
+{
+ return val_x16 & 0xf;
+}
+
+#define DRM_X16_FMT"%d.%04d"
+#define DRM_X16_ARGS(val_x16) drm_x16_to_int(val_x16),
(drm_x16_to_frac(val_x16) * 625)
+
#endif
--
2.43.3
[PATCH 3/9] drm/i915: Replace to_bpp_x16() with drm_x16_from_int()
Replace to_bpp_x16() defined by the driver with the drm_x16_from_int()
defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_bios.c | 5 +++--
.../gpu/drm/i915/display/intel_display_types.h | 5 -
drivers/gpu/drm/i915/display/intel_dp.c | 17 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++---
drivers/gpu/drm/i915/display/intel_fdi.c| 4 +++-
drivers/gpu/drm/i915/display/intel_link_bw.c| 4 +++-
6 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index def2ade619548..a1872957532bc 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -30,6 +30,7 @@
#include
#include
#include
+#include
#include "i915_drv.h"
#include "i915_reg.h"
@@ -3525,8 +3526,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3;
- crtc_state->dsc.compressed_bpp_x16 =
to_bpp_x16(min(crtc_state->pipe_bpp,
-
VBT_DSC_MAX_BPP(dsc->max_bpp)));
+ crtc_state->dsc.compressed_bpp_x16 =
drm_x16_from_int(min(crtc_state->pipe_bpp,
+
VBT_DSC_MAX_BPP(dsc->max_bpp)));
/*
* FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 02ebe6f3e765d..5c93dcb8f01dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2186,11 +2186,6 @@ static inline int to_bpp_int_roundup(int bpp_x16)
return (bpp_x16 + 0xf) >> 4;
}
-static inline int to_bpp_x16(int bpp)
-{
- return bpp << 4;
-}
-
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9a9bb0f5b7fe0..348ab95bc0d53 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include
#include "g4x_dp.h"
@@ -1903,7 +1904,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 =
- to_bpp_x16(valid_dsc_bpp[i]);
+ drm_x16_from_int(valid_dsc_bpp[i]);
return 0;
}
}
@@ -2156,7 +2157,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
pipe_config->dsc.compressed_bpp_x16 =
- to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
+ drm_x16_from_int(max(dsc_min_bpp, dsc_max_bpp));
pipe_config->pipe_bpp = pipe_bpp;
@@ -2288,15 +2289,15 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
int max_link_bpp_x16;
max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
- to_bpp_x16(limits->pipe.max_bpp));
+ drm_x16_from_int(limits->pipe.max_bpp));
if (!dsc) {
- max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 *
3));
+ max_link_bpp_x16 = rounddown(max_link_bpp_x16,
drm_x16_from_int(2 * 3));
- if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
+ if (max_link_bpp_x16 < drm_x16_from_int(limits->pipe.min_bpp))
return false;
- limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
+ limits->link.min_bpp_x16 =
drm_x16_from_int(limits->pipe.min_bpp);
} else {
/*
* TODO: set the DSC link limits already here, atm these are
@@ -2945,8 +2946,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable)
link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
else
- link_bpp_x16 =
to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
-
pipe_config->pipe_bpp));
+ link_bpp_x16 =
drm_x16_from_int(intel_dp_output_bpp(pipe_config->output_format,
+
pipe_config->pipe_bpp));
if (intel_dp->mso_link_count) {
int n = intel_dp->mso_link_count;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a2884833075dc..b8e2ffc2301f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.
[PATCH 2/9] drm/display/dsc: Add a helper to dump the DSC configuration
Add a helper to dump the Display Stream Compression configuration, taken
into use in the i915 driver by a later patch.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dsc_helper.c | 91
include/drm/display/drm_dsc_helper.h | 3 +
2 files changed, 94 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c
b/drivers/gpu/drm/display/drm_dsc_helper.c
index 4424380c6cb63..ef2237f2b8630 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -14,6 +14,7 @@
#include
#include
+#include
#include
/**
@@ -1472,3 +1473,93 @@ u32 drm_dsc_flatness_det_thresh(const struct
drm_dsc_config *dsc)
return 2 << (dsc->bits_per_component - 8);
}
EXPORT_SYMBOL(drm_dsc_flatness_det_thresh);
+
+static void drm_dsc_dump_config_main_params(struct drm_printer *p, int indent,
+ const struct drm_dsc_config *cfg)
+{
+ drm_printf_indent(p, indent,
+ "dsc-cfg: version: %d.%d, picture: w=%d, h=%d, slice:
count=%d, w=%d, h=%d, size=%d\n",
+ cfg->dsc_version_major, cfg->dsc_version_minor,
+ cfg->pic_width, cfg->pic_height,
+ cfg->slice_count, cfg->slice_width,
cfg->slice_height, cfg->slice_chunk_size);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: mode: block-pred=%s, vbr=%s, rgb=%s,
simple-422=%s, native-422=%s, native-420=%s\n",
+ str_yes_no(cfg->block_pred_enable),
str_yes_no(cfg->vbr_enable),
+ str_yes_no(cfg->convert_rgb),
+ str_yes_no(cfg->simple_422),
str_yes_no(cfg->native_422), str_yes_no(cfg->native_420));
+ drm_printf_indent(p, indent,
+ "dsc-cfg: color-depth: uncompressed-bpc=%d,
compressed-bpp=" DRM_X16_FMT " line-buf-bpp=%d\n",
+ cfg->bits_per_component,
DRM_X16_ARGS(cfg->bits_per_pixel), cfg->line_buf_depth);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: rc-model: size=%d, bits=%d, mux-word-size:
%d, initial-delays: xmit=%d, dec=%d\n",
+ cfg->rc_model_size, cfg->rc_bits, cfg->mux_word_size,
+ cfg->initial_xmit_delay, cfg->initial_dec_delay);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: offsets: initial=%d, final=%d,
slice-bpg=%d\n",
+ cfg->initial_offset, cfg->final_offset,
cfg->slice_bpg_offset);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: line-bpg-offsets: first=%d, non-first=%d,
second=%d, non-second=%d, second-adj=%d\n",
+ cfg->first_line_bpg_offset, cfg->nfl_bpg_offset,
+ cfg->second_line_bpg_offset, cfg->nsl_bpg_offset,
cfg->second_line_offset_adj);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: rc-tgt-offsets: low=%d, high=%d,
rc-edge-factor: %d, rc-quant-incr-limits: [0]=%d, [1]=%d\n",
+ cfg->rc_tgt_offset_low, cfg->rc_tgt_offset_high,
+ cfg->rc_edge_factor, cfg->rc_quant_incr_limit0,
cfg->rc_quant_incr_limit1);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: initial-scale: %d, scale-intervals:
increment=%d, decrement=%d\n",
+ cfg->initial_scale_value,
cfg->scale_increment_interval, cfg->scale_decrement_interval);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: flatness: min-qp=%d, max-qp=%d\n",
+ cfg->flatness_min_qp, cfg->flatness_max_qp);
+}
+
+static void drm_dsc_dump_config_rc_params(struct drm_printer *p, int indent,
+ const struct drm_dsc_config *cfg)
+{
+ const u16 *bt = cfg->rc_buf_thresh;
+ const struct drm_dsc_rc_range_parameters *rp = cfg->rc_range_params;
+
+ BUILD_BUG_ON(ARRAY_SIZE(cfg->rc_buf_thresh) != 14);
+ BUILD_BUG_ON(ARRAY_SIZE(cfg->rc_range_params) != 15);
+
+ drm_printf_indent(p, indent,
+ "dsc-cfg: rc-level: 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, 10, 11, 12, 13, 14\n");
+ drm_printf_indent(p, indent,
+ "dsc-cfg: rc-buf-thresh:
%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
+ bt[0], bt[1], bt[2], bt[3], bt[4], bt[5], bt[6],
bt[7],
+ bt[8], bt[9], bt[10], bt[11], bt[12], bt[13]);
+ drm_printf_indent(p, indent,
+ "dsc-cfg: rc-min-qp:
%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d,%3d\n",
+ rp[0].range_min_qp, rp[1].range_min_qp,
rp[2].range_min_qp, rp[3].range_min_qp,
+ rp[4].range_min_qp, rp[5].range_min_qp,
rp[6].range_min_qp, rp[7].range_min_qp,
+ rp[8].range_min_qp, rp[9].rang
[PATCH 8/9] drm/i915: Dump DSC state to dmesg and debugfs/i915_display_info
Dump the DSC state to dmesg during HW readout and state computation as
well as the i915_display_info debugfs entry.
Signed-off-by: Imre Deak
---
.../drm/i915/display/intel_crtc_state_dump.c | 3 +++
.../drm/i915/display/intel_display_debugfs.c | 4
drivers/gpu/drm/i915/display/intel_vdsc.c | 20 +++
drivers/gpu/drm/i915/display/intel_vdsc.h | 4
4 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 6df526e189b5b..705ec5ad385c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -10,6 +10,7 @@
#include "intel_crtc_state_dump.h"
#include "intel_display_types.h"
#include "intel_hdmi.h"
+#include "intel_vdsc.h"
#include "intel_vrr.h"
static void intel_dump_crtc_timings(struct drm_printer *p,
@@ -369,6 +370,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
else if (IS_VALLEYVIEW(i915))
vlv_dump_csc(&p, "wgc csc", &pipe_config->csc);
+ intel_vdsc_state_dump(&p, 0, pipe_config);
+
dump_planes:
if (!state)
return;
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 91757fed9c6d2..c20a5097ea331 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -36,6 +36,7 @@
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_psr_regs.h"
+#include "intel_vdsc.h"
#include "intel_wm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
@@ -551,6 +552,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct drm_printer p = drm_seq_file_printer(m);
const struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_encoder *encoder;
@@ -581,6 +583,8 @@ static void intel_crtc_info(struct seq_file *m, struct
intel_crtc *crtc)
crtc_state->joiner_pipes,
intel_crtc_is_joiner_secondary(crtc_state) ? "slave"
: "master");
+ intel_vdsc_state_dump(&p, 1, crtc_state);
+
for_each_intel_encoder_mask(&dev_priv->drm, encoder,
crtc_state->uapi.encoder_mask)
intel_encoder_info(m, crtc, encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ffda11b417e24..ca1d8be659195 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -990,3 +990,23 @@ void intel_dsc_get_config(struct intel_crtc_state
*crtc_state)
out:
intel_display_power_put(dev_priv, power_domain, wakeref);
}
+
+static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
+ const struct intel_crtc_state *crtc_state)
+{
+ drm_printf_indent(p, indent,
+ "dsc-dss: compressed-bpp:" DRM_X16_FMT ",
slice-count: %d, split: %s\n",
+ DRM_X16_ARGS(crtc_state->dsc.compressed_bpp_x16),
+ crtc_state->dsc.slice_count,
+ str_yes_no(crtc_state->dsc.dsc_split));
+}
+
+void intel_vdsc_state_dump(struct drm_printer *p, int indent,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->dsc.compression_enable)
+ return;
+
+ intel_vdsc_dump_state(p, indent, crtc_state);
+ drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 2cc41ff089094..290b2e9b3482e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -8,6 +8,8 @@
#include
+struct drm_printer;
+
enum transcoder;
struct intel_crtc;
struct intel_crtc_state;
@@ -27,5 +29,7 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+void intel_vdsc_state_dump(struct drm_printer *p, int indent,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VDSC_H__ */
--
2.43.3
[PATCH 6/9] drm/i915: Replace to_bpp_frac() with drm_x16_to_frac()
Replace to_bpp_frac() defined by the driver with the equivalent
drm_x16_to_frac() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +--
drivers/gpu/drm/i915/display/intel_dp.c| 4 ++--
drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 68f37029dbd88..128edecb69a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2168,13 +2168,8 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline int to_bpp_frac(int bpp_x16)
-{
- return bpp_x16 & 0xf;
-}
-
#define BPP_X16_FMT"%d.%04d"
-#define BPP_X16_ARGS(bpp_x16) drm_x16_to_int(bpp_x16), (to_bpp_frac(bpp_x16)
* 625)
+#define BPP_X16_ARGS(bpp_x16) drm_x16_to_int(bpp_x16),
(drm_x16_to_frac(bpp_x16) * 625)
/*
* Conversion functions/macros from various pointer types to struct
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 67d0348152878..168852e20f756 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1947,7 +1947,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
compressed_bppx16 >= dsc_min_bpp;
compressed_bppx16 -= bppx16_step) {
if (intel_dp->force_dsc_fractional_bpp_en &&
- !to_bpp_frac(compressed_bppx16))
+ !drm_x16_to_frac(compressed_bppx16))
continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
@@ -1957,7 +1957,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
if (intel_dp->force_dsc_fractional_bpp_en &&
- to_bpp_frac(compressed_bppx16))
+ drm_x16_to_frac(compressed_bppx16))
drm_dbg_kms(&i915->drm, "Forcing DSC fractional
bpp\n");
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 5c0acbed7d6a1..ffda11b417e24 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -185,7 +185,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
}
} else {
/* fractional bpp part * 1 (for precision up to 4 decimal
places) */
- int fractional_bits = to_bpp_frac(vdsc_cfg->bits_per_pixel);
+ int fractional_bits = drm_x16_to_frac(vdsc_cfg->bits_per_pixel);
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12,
-12, -12
--
2.43.3
[PATCH 4/9] drm/i915: Replace to_bpp_int() with drm_x16_to_int()
Replace to_bpp_int() defined by the driver with the equivalent
drm_x16_from_int() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c | 9 +
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display_types.h | 7 +--
drivers/gpu/drm/i915/display/intel_dp.c| 8
drivers/gpu/drm/i915/display/intel_dp_mst.c| 6 +++---
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++--
7 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae8f6617aa70c..8e32e5958bd7b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -27,6 +27,7 @@
#include
#include
+#include
#include
#include "i915_reg.h"
@@ -330,7 +331,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
- bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
+ bpp = drm_x16_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -863,7 +864,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
- mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
+ mul = drm_x16_to_int(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@@ -887,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
- bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
+ bpp =
drm_x16_to_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp =
mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1470,7 +1471,7 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
&pipe_config->hw.adjusted_mode;
if (pipe_config->dsc.compressed_bpp_x16) {
- int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
+ int div = drm_x16_to_int(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7bc4f3de691e0..179e37cc7df0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -39,6 +39,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -4668,7 +4669,7 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
- if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
+ if (crtc_state->pipe_bpp >
drm_x16_to_int(crtc_state->max_link_bpp_x16)) {
drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
crtc->base.base.id, crtc->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5c93dcb8f01dc..0d0ab54ab9ebf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2168,18 +2168,13 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline int to_bpp_int(int bpp_x16)
-{
- return bpp_x16 >> 4;
-}
-
static inline int to_bpp_frac(int bpp_x16)
{
return bpp_x16 & 0xf;
}
#define BPP_X16_FMT"%d.%04d"
-#define BPP_X16_ARGS(bpp_x16) to_bpp_int(bpp_x16), (to_bpp_frac(bpp_x16) *
625)
+#define BPP_X16_ARGS(bpp_x16) drm_x16_to_int(bpp_x16), (to_bpp_frac(bpp_x16)
* 625)
static inline int to_bpp_int_roundup(int bpp_x16)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 348ab95bc0d53..25284d2318096 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1575,8 +1575,8 @@ intel_dp_compute_link_config_wide(struct intel_dp
*intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config,
conn_state);
int mode_rate, link_rate, link_avail;
- for (bpp = to_bpp_int(limits->link.max_bpp_x16);
-
[PATCH 5/9] drm/i915: Replace to_bpp_int_roundup() with drm_x16_to_int_roundup()
Replace to_bpp_int_roundup() defined by the driver with the equivalent
drm_x16_to_int_roundup() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +++-
drivers/gpu/drm/i915/display/intel_display_types.h | 5 -
drivers/gpu/drm/i915/display/intel_dp.c| 6 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c| 2 +-
4 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c5bc49e48c882..3aebf42b50cf6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,8 @@
#include
+#include
+
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
@@ -2749,7 +2751,7 @@ static int intel_vdsc_min_cdclk(const struct
intel_crtc_state *crtc_state)
*/
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 :
24;
int min_cdclk_bj =
- (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16)
*
+
(drm_x16_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
pixel_clock) / (2 * bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0d0ab54ab9ebf..68f37029dbd88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2176,11 +2176,6 @@ static inline int to_bpp_frac(int bpp_x16)
#define BPP_X16_FMT"%d.%04d"
#define BPP_X16_ARGS(bpp_x16) drm_x16_to_int(bpp_x16), (to_bpp_frac(bpp_x16)
* 625)
-static inline int to_bpp_int_roundup(int bpp_x16)
-{
- return (bpp_x16 + 0xf) >> 4;
-}
-
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 25284d2318096..67d0348152878 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1982,7 +1982,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp
*intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
- dsc_min_bpp = max(dsc_min_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
+ dsc_min_bpp = max(dsc_min_bpp,
drm_x16_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
@@ -2144,7 +2144,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp
*intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
- dsc_min_bpp = max(dsc_min_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
+ dsc_min_bpp = max(dsc_min_bpp,
drm_x16_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
@@ -2370,7 +2370,7 @@ int intel_dp_config_required_rate(const struct
intel_crtc_state *crtc_state)
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int bpp = crtc_state->dsc.compression_enable ?
- to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
+ drm_x16_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
crtc_state->pipe_bpp;
return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a67b2ee7af750..09c1ca63362e7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -378,7 +378,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct
intel_encoder *encoder,
min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
min_compressed_bpp = max(min_compressed_bpp,
-to_bpp_int_roundup(limits->link.min_bpp_x16));
+
drm_x16_to_int_roundup(limits->link.min_bpp_x16));
drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d
compressed max bpp %d\n",
min_compressed_bpp, max_compressed_bpp);
--
2.43.3
[PATCH 7/9] drm/i915: Replace BPP_X16_FMT()/ARGS() with DRM_X16_FMT()/ARGS()
Replace BPP_X16_FMT()/ARGS() defined by the driver with the equivalent
DRM_X16_FMT()/ARGS() defined by DRM core.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +++--
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_types.h | 3 ---
drivers/gpu/drm/i915/display/intel_dp.c | 16
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
5 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index b9bafec06fb8b..bba303af1dd0d 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -26,6 +26,7 @@
#include
#include
+#include
#include
#include "i915_drv.h"
@@ -452,8 +453,8 @@ static unsigned int calc_hblank_early_prog(struct
intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm,
- "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = "
BPP_X16_FMT " cdclk = %u\n",
- h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16),
cdclk);
+ "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = "
DRM_X16_FMT " cdclk = %u\n",
+ h_active, link_clk, lanes, DRM_X16_ARGS(vdsc_bppx16),
cdclk);
if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 ||
!cdclk))
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 179e37cc7df0a..9a9f05debf462 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4671,9 +4671,9 @@ intel_modeset_pipe_config(struct intel_atomic_state
*state,
if (crtc_state->pipe_bpp >
drm_x16_to_int(crtc_state->max_link_bpp_x16)) {
drm_dbg_kms(&i915->drm,
- "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT
"\n",
+ "[CRTC:%d:%s] Link bpp limited to " DRM_X16_FMT
"\n",
crtc->base.base.id, crtc->base.name,
- BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
+ DRM_X16_ARGS(crtc_state->max_link_bpp_x16));
crtc_state->bw_constrained = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 128edecb69a20..795bea8ebde11 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2168,9 +2168,6 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-#define BPP_X16_FMT"%d.%04d"
-#define BPP_X16_ARGS(bpp_x16) drm_x16_to_int(bpp_x16),
(drm_x16_to_frac(bpp_x16) * 625)
-
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 168852e20f756..f469913472fdb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2247,17 +2247,17 @@ int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp
= %d"
- "Compressed BPP = " BPP_X16_FMT "\n",
+ "Compressed BPP = " DRM_X16_FMT "\n",
pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
+ DRM_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
- "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
+ "Compressed Bpp = " DRM_X16_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp,
- BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
+ DRM_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
return 0;
@@ -2310,7 +2310,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp
*intel_dp,
limits->link.max_bpp_x16 = max_link_bpp_x16;
drm_dbg_kms(&i915->drm,
- "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d
kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT
"\n",
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d
kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " DRM_X16_FMT
"\n",
encoder->base.base.id, encoder->base.na
[PATCH 9/9] drm/i915: Remove DSC register dump
The Display Engine's DSC register values are deducted from the DSC
configuration stored in intel_crtc_state::dsc. The latter one is
dumped in a human-readable format, so dumping the register values is
redundant, remove it.
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 ++-
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ca1d8be659195..e55c87cbf4ee4 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -457,36 +457,30 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
pps_val |= DSC_PPS0_422_ENABLE;
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_PPS0_VBR_ENABLE;
- drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 0, pps_val);
/* PPS 1 */
pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
- drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 1, pps_val);
/* PPS 2 */
pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
- drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 2, pps_val);
/* PPS 3 */
pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
- drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 3, pps_val);
/* PPS 4 */
pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
- drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 4, pps_val);
/* PPS 5 */
pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
- drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 5, pps_val);
/* PPS 6 */
@@ -494,25 +488,21 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset)
|
DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
- drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 6, pps_val);
/* PPS 7 */
pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
- drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 7, pps_val);
/* PPS 8 */
pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
- drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 8, pps_val);
/* PPS 9 */
pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
- drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 9, pps_val);
/* PPS 10 */
@@ -520,7 +510,6 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
- drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 10, pps_val);
/* PPS 16 */
@@ -529,31 +518,25 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
vdsc_cfg->slice_width) |
DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
vdsc_cfg->slice_height);
- drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 16, pps_val);
if (DISPLAY_VER(dev_priv) >= 14) {
/* PPS 17 */
pps_val =
DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
- drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
intel_dsc_pps_write(crtc_state, 17, pps_val);
/* PPS 18 */
pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj)
✗ Fi.CI.IGT: failure for drm/i915/dsc: don't mess up splitter state in joiner or dsc config
== Series Details == Series: drm/i915/dsc: don't mess up splitter state in joiner or dsc config URL : https://patchwork.freedesktop.org/series/134825/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14935_full -> Patchwork_134825v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_134825v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_134825v1_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/index.html Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_134825v1_full: ### IGT changes ### Possible regressions * igt@perf@rc6-disable: - shard-dg2: [PASS][1] -> [SKIP][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14935/shard-dg2-11/igt@p...@rc6-disable.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg2-5/igt@p...@rc6-disable.html Known issues Here are the changes found in Patchwork_134825v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-keep-cache: - shard-rkl: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-rkl-2/igt@api_intel...@object-reloc-keep-cache.html * igt@api_intel_bb@object-reloc-purge-cache: - shard-dg1: NOTRUN -> [SKIP][4] ([i915#8411]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-15/igt@api_intel...@object-reloc-purge-cache.html * igt@device_reset@unbind-cold-reset-rebind: - shard-dg1: NOTRUN -> [SKIP][5] ([i915#11078]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-14/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@virtual-busy-idle-all: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-15/igt@drm_fdi...@virtual-busy-idle-all.html * igt@drm_fdinfo@virtual-idle: - shard-rkl: NOTRUN -> [FAIL][7] ([i915#7742]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-rkl-2/igt@drm_fdi...@virtual-idle.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][8] ([i915#9323]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-rkl-2/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@ctrl-surf-copy: - shard-tglu: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-tglu-8/igt@gem_...@ctrl-surf-copy.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#7697]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-15/igt@gem_close_r...@multigpu-basic-threads.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#8555]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-15/igt@gem_ctx_persiste...@heartbeat-many.html * igt@gem_ctx_sseu@invalid-args: - shard-rkl: NOTRUN -> [SKIP][12] ([i915#280]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-rkl-2/igt@gem_ctx_s...@invalid-args.html * igt@gem_ctx_sseu@invalid-sseu: - shard-dg2: NOTRUN -> [SKIP][13] ([i915#280]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg2-6/igt@gem_ctx_s...@invalid-sseu.html - shard-tglu: NOTRUN -> [SKIP][14] ([i915#280]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-tglu-8/igt@gem_ctx_s...@invalid-sseu.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#4525]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-rkl-2/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_balancer@sliced: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#4812]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg2-2/igt@gem_exec_balan...@sliced.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg1: NOTRUN -> [SKIP][17] ([i915#6334]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134825v1/shard-dg1-14/igt@gem_exec_capture@capture-invisi...@lmem0.html * igt@gem_exec_fai
[drm-intel:for-linux-next-gt 3/3] drivers/gpu/drm/i915/gem/i915_gem_stolen.c:943:32: sparse: sparse: Using plain integer as NULL pointer
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-gt
head: 05da7d9f717bcb03c457379fa8a61c1689dab86c
commit: 05da7d9f717bcb03c457379fa8a61c1689dab86c [3/3] drm/i915/gem: Downgrade
stolen lmem setup warning
config: x86_64-randconfig-122-20240614
(https://download.01.org/0day-ci/archive/20240615/202406150232.r9of4ebo-...@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project
617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240615/202406150232.r9of4ebo-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202406150232.r9of4ebo-...@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:943:32: sparse: sparse: Using
>> plain integer as NULL pointer
vim +943 drivers/gpu/drm/i915/gem/i915_gem_stolen.c
889
890 struct intel_memory_region *
891 i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
892 u16 instance)
893 {
894 struct intel_uncore *uncore = &i915->uncore;
895 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
896 resource_size_t dsm_size, dsm_base, lmem_size;
897 struct intel_memory_region *mem;
898 resource_size_t io_start, io_size;
899 resource_size_t min_page_size;
900 int ret;
901
902 if (WARN_ON_ONCE(instance))
903 return ERR_PTR(-ENODEV);
904
905 if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR))
906 return ERR_PTR(-ENXIO);
907
908 if (HAS_LMEMBAR_SMEM_STOLEN(i915) || IS_DG1(i915)) {
909 lmem_size = pci_resource_len(pdev, GEN12_LMEM_BAR);
910 } else {
911 resource_size_t lmem_range;
912
913 lmem_range = intel_gt_mcr_read_any(to_gt(i915),
XEHP_TILE0_ADDR_RANGE) & 0x;
914 lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;
915 lmem_size *= SZ_1G;
916 }
917
918 if (HAS_LMEMBAR_SMEM_STOLEN(i915)) {
919 /*
920 * MTL dsm size is in GGC register.
921 * Also MTL uses offset to GSMBASE in ptes, so i915
922 * uses dsm_base = 8MBs to setup stolen region, since
923 * DSMBASE = GSMBASE + 8MB.
924 */
925 ret = mtl_get_gms_size(uncore);
926 if (ret < 0) {
927 drm_err(&i915->drm, "invalid MTL GGC register
setting\n");
928 return ERR_PTR(ret);
929 }
930
931 dsm_base = SZ_8M;
932 dsm_size = (resource_size_t)(ret * SZ_1M);
933
934 GEM_BUG_ON(pci_resource_len(pdev, GEN12_LMEM_BAR) !=
SZ_256M);
935 GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
936 } else {
937 /* Use DSM base address instead for stolen memory */
938 dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) &
GEN11_BDSM_MASK;
939 if (lmem_size < dsm_base) {
940 drm_dbg(&i915->drm,
941 "Disabling stolen memory support due to
OOB placement: lmem_size = %lli vs dsm_base = %lli\n",
942 lmem_size, dsm_base);
> 943 return 0;
944 }
945 dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
946 }
947
948 if (i915_direct_stolen_access(i915)) {
949 drm_dbg(&i915->drm, "Using direct DSM access\n");
950 io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) &
GEN11_BDSM_MASK;
951 io_size = dsm_size;
952 } else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
953 io_start = 0;
954 io_size = 0;
955 } else {
956 io_start = pci_resource_start(pdev, GEN12_LMEM_BAR) +
dsm_base;
957 io_size = dsm_size;
958 }
959
960 min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
961 I915_GTT_PAGE_SIZE_4K;
962
963 mem = intel_memory_region_create(i915, dsm_base, dsm_size,
964 min_page_size,
965
Re: [PATCH v6 5/8] drm/i915: Enable async flips on the primary plane
On Fri, Jun 14, 2024 at 12:35:32PM -0300, André Almeida wrote: > This driver can perfom async flips on primary planes, so enable it. > Cc: Ville Syrjälä Cc: Naveen Kumar c: Vandita Kulkarni > Signed-off-by: André Almeida > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c > b/drivers/gpu/drm/i915/display/i9xx_plane.c > index 0279c8aabdd1..0142beef20dc 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -931,6 +931,9 @@ intel_primary_plane_create(struct drm_i915_private > *dev_priv, enum pipe pipe) > > intel_plane_helper_add(plane); > > + if (plane->async_flip) > + plane->base.async_flip = true; I believe this is not enough and besides this we would also need to have in the: skl_universal_plane_create[2447] plane->async_flip = skl_plane_async_flip; at: drivers/gpu/drm/i915/display/skl_universal_plane.c > + > return plane; > > fail: > -- > 2.45.2 >
✗ Fi.CI.BUILD: warning for drm/i915: Dump DSC state to dmesg/debugfs
== Series Details == Series: drm/i915: Dump DSC state to dmesg/debugfs URL : https://patchwork.freedesktop.org/series/134906/ State : warning == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/134906/revisions/1/mbox/ not found
✗ Fi.CI.CHECKPATCH: warning for drm/i915: Dump DSC state to dmesg/debugfs
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : warning
== Summary ==
Error: dim checkpatch failed
f07f771fbdda drm: Add helpers for x16 fixed point values
-:33: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#33: FILE: drivers/gpu/drm/display/drm_dp_helper.c:4155:
+ DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d,
hactive %d, bpp_x16 " DRM_X16_FMT "\n",
-:69: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#69: FILE: include/drm/drm_fixed.h:238:
+#define DRM_X16_ARGS(val_x16) drm_x16_to_int(val_x16),
(drm_x16_to_frac(val_x16) * 625)
-:69: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val_x16' - possible
side-effects?
#69: FILE: include/drm/drm_fixed.h:238:
+#define DRM_X16_ARGS(val_x16) drm_x16_to_int(val_x16),
(drm_x16_to_frac(val_x16) * 625)
total: 1 errors, 1 warnings, 1 checks, 45 lines checked
2d5a17f369ab drm/display/dsc: Add a helper to dump the DSC configuration
-:35: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#35: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1484:
+ cfg->slice_count, cfg->slice_width,
cfg->slice_height, cfg->slice_chunk_size);
-:40: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#40: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1489:
+ str_yes_no(cfg->simple_422),
str_yes_no(cfg->native_422), str_yes_no(cfg->native_420));
-:43: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#43: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1492:
+ cfg->bits_per_component,
DRM_X16_ARGS(cfg->bits_per_pixel), cfg->line_buf_depth);
-:54: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#54: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1503:
+ cfg->second_line_bpg_offset, cfg->nsl_bpg_offset,
cfg->second_line_offset_adj);
-:58: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#58: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1507:
+ cfg->rc_edge_factor, cfg->rc_quant_incr_limit0,
cfg->rc_quant_incr_limit1);
-:61: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#61: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1510:
+ cfg->initial_scale_value,
cfg->scale_increment_interval, cfg->scale_decrement_interval);
-:84: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#84: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1533:
+ rp[0].range_min_qp, rp[1].range_min_qp,
rp[2].range_min_qp, rp[3].range_min_qp,
-:85: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#85: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1534:
+ rp[4].range_min_qp, rp[5].range_min_qp,
rp[6].range_min_qp, rp[7].range_min_qp,
-:86: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#86: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1535:
+ rp[8].range_min_qp, rp[9].range_min_qp,
rp[10].range_min_qp, rp[11].range_min_qp,
-:90: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#90: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1539:
+ rp[0].range_max_qp, rp[1].range_max_qp,
rp[2].range_max_qp, rp[3].range_max_qp,
-:91: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#91: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1540:
+ rp[4].range_max_qp, rp[5].range_max_qp,
rp[6].range_max_qp, rp[7].range_max_qp,
-:92: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#92: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1541:
+ rp[8].range_max_qp, rp[9].range_max_qp,
rp[10].range_max_qp, rp[11].range_max_qp,
-:96: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#96: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1545:
+ rp[0].range_bpg_offset, rp[1].range_bpg_offset,
rp[2].range_bpg_offset, rp[3].range_bpg_offset,
-:97: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#97: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1546:
+ rp[4].range_bpg_offset, rp[5].range_bpg_offset,
rp[6].range_bpg_offset, rp[7].range_bpg_offset,
-:98: WARNING:LONG_LINE: line length of 125 exceeds 100 columns
#98: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1547:
+ rp[8].range_bpg_offset, rp[9].range_bpg_offset,
rp[10].range_bpg_offset, rp[11].range_bpg_offset,
-:99: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#99: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1548:
+ rp[12].range_bpg_offset, rp[13].range_bpg_offset,
rp[14].range_bpg_offset);
-:108: WARNING:TYPO_SPELLING: 'configration' may be misspelled - perhaps
'configuration'?
#108: FILE: drivers/gpu/drm/display/drm_dsc_helper.c:1557:
+ * Print the provided DSC co
✗ Fi.CI.SPARSE: warning for drm/i915: Dump DSC state to dmesg/debugfs
== Series Details == Series: drm/i915: Dump DSC state to dmesg/debugfs URL : https://patchwork.freedesktop.org/series/134906/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✓ Fi.CI.BAT: success for drm/i915: Dump DSC state to dmesg/debugfs
== Series Details ==
Series: drm/i915: Dump DSC state to dmesg/debugfs
URL : https://patchwork.freedesktop.org/series/134906/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14945 -> Patchwork_134906v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/index.html
Participating hosts (43 -> 39)
--
Missing(4): bat-dg1-7 bat-jsl-1 fi-snb-2520m fi-kbl-8809g
Known issues
Here are the changes found in Patchwork_134906v1 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_flip@basic-flip-vs-modeset@c-dp6:
- {bat-mtlp-9}: [DMESG-WARN][1] ([i915#11009]) -> [PASS][2] +2 other
tests pass
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14945/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@c-dp6.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-mode...@c-dp6.html
* igt@kms_flip@basic-plain-flip@c-dp7:
- {bat-mtlp-9}: [FAIL][3] ([i915#6121]) -> [PASS][4] +5 other tests
pass
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14945/bat-mtlp-9/igt@kms_flip@basic-plain-f...@c-dp7.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/bat-mtlp-9/igt@kms_flip@basic-plain-f...@c-dp7.html
* igt@kms_flip@basic-plain-flip@d-dp7:
- {bat-mtlp-9}: [DMESG-FAIL][5] ([i915#11009]) -> [PASS][6] +1 other
test pass
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14945/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp7.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/bat-mtlp-9/igt@kms_flip@basic-plain-f...@d-dp7.html
* igt@kms_force_connector_basic@force-connector-state:
- {bat-mtlp-9}: [FAIL][7] -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14945/bat-mtlp-9/igt@kms_force_connector_ba...@force-connector-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/bat-mtlp-9/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_frontbuffer_tracking@basic:
- bat-arls-2: [DMESG-WARN][9] ([i915#7507]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14945/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#7507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7507
[i915#9159]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9159
Build changes
-
* Linux: CI_DRM_14945 -> Patchwork_134906v1
CI-20190529: 20190529
CI_DRM_14945: 5c623c9712af3170cc9782a10ed7360ddf8f8bb4 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7889: 9dca15da37f2a385b04427eb39cd460224d09c25 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_134906v1: 5c623c9712af3170cc9782a10ed7360ddf8f8bb4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134906v1/index.html
Re: [PATCH v6 0/8] drm: Support per-plane async flip configuration
Hi Dmitry, Em 14/06/2024 14:32, Dmitry Baryshkov escreveu: On Fri, Jun 14, 2024 at 12:35:27PM GMT, André Almeida wrote: AMD hardware can do async flips with overlay planes, but currently there's no easy way to enable that in DRM. To solve that, this patchset creates a new drm_plane field, bool async_flip, that allows drivers to choose which plane can or cannot do async flips. This is latter used on drm_atomic_set_property when users want to do async flips. Patch 1 allows async commits with IN_FENCE_ID in any driver. Patches 2 to 7 have no function change. As per current code, every driver that allows async page flips using the atomic API, allows doing it only in the primary plane. Those patches then enable it for every driver. Patch 8 finally enables async flip on overlay planes for amdgpu. Changes from v5: - Instead of enabling plane->async_flip in the common code, move it to driver code. - Enable primary plane async flip on every driver https://lore.kernel.org/dri-devel/20240612193713.167448-1-andrealm...@igalia.com/ André Almeida (8): drm/atomic: Allow userspace to use explicit sync with atomic async flips drm: Support per-plane async flip configuration drm/amdgpu: Enable async flips on the primary plane drm: atmel-hlcdc: Enable async flips on the primary plane drm/i915: Enable async flips on the primary plane drm/nouveau: Enable async flips on the primary plane drm/vc4: Enable async flips on the primary plane drm/amdgpu: Make it possible to async flip overlay planes drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 8 +--- drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++ drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 drivers/gpu/drm/vc4/vc4_plane.c | 4 +++- The main question is why only these drivers were updated. According to `git grep async_page_flip`, only those drivers supports async page flip. The only corner case is radeon, that does supports async but doesn't support planes. Do you know any other driver that should be updated to? include/drm/drm_plane.h | 5 + 8 files changed, 29 insertions(+), 4 deletions(-) -- 2.45.2
Re: [PATCH v6 2/8] drm: Support per-plane async flip configuration
Em 14/06/2024 14:32, Dmitry Baryshkov escreveu:> On Fri, Jun 14, 2024 at
12:35:29PM GMT, André Almeida wrote:
>> Drivers have different capabilities on what plane types they can or
>> cannot perform async flips. Create a plane::async_flip field so each
>> driver can choose which planes they allow doing async flips.
>>
>> Signed-off-by: André Almeida
>> ---
>> drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
>> include/drm/drm_plane.h | 5 +
>> 2 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
>> index 2e1d9391febe..ed1af3455477 100644
>> --- a/drivers/gpu/drm/drm_atomic_uapi.c
>> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
>> @@ -1079,9 +1079,9 @@ int drm_atomic_set_property(struct
drm_atomic_state *state,
>>break;
>>}
>>
>> - if (async_flip && plane_state->plane->type !=
DRM_PLANE_TYPE_PRIMARY) {
>> + if (async_flip && !plane->async_flip) {
>
> So, after this patch async flips becomes disabled until the driver
> enables that manually. Whether that's desired or not is a separate
> topic, but this definitely should be explicitly mentioned in the commit
> message.
>
You are right, I think I should separate this in the last commit, so we
don't have any regression commits. Thanks for the feedback
Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
On Fri, Jun 14, 2024 at 03:23:54PM +, Cavitt, Jonathan wrote:
> -Original Message-
> From: Andi Shyti
> Sent: Friday, June 14, 2024 8:22 AM
> To: Andi Shyti
> Cc: intel-gfx ; dri-devel
> ; Harrison, John C
> ; Cavitt, Jonathan
> Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
> >
> > I guess sparse and potential CI errors won't minimally relate to
> > this patch.
>
> Yeah, I don't see how a change to a comment could ever be related
> to any CI errors:
>
> Reviewed-by: Jonathan Cavitt
Please ensure you use the full line.
1. People don't have to go to the header of your email to get your email.
2. People might not be entirely sure of your choice of email. Please notice that
even on Intel many folks have @intel.com and @linux.intel.com and sometimes
although
responding from one, they use the other to sign things.
3. Tooling! (b4, patchwork, etc) There are many tools that get these tags
directly
from the email response and by using partial one you can complicate things.
If you also allow one advice, try to use a terminal mail client like mutt and
open the replies in your favorite editor and add macros there to add your lines
based on shortcuts... For instance, on my case I use mutt+emacs and I just hit
Ctrl+c-rev and that adds my full rv-b tag in the response.
Thanks,
Rodrigo.
> -Jonathan Cavitt
>
> >
> > Adding also Jonathan in Cc :-)
> >
> > Thanks,
> > Andi
> >
> > On Fri, Jun 14, 2024 at 12:28:37AM +0200, Andi Shyti wrote:
> > > Replace "dynmically" with "dynamically".
> > >
> > > Signed-off-by: Andi Shyti
> > > Cc: John Harrison
> > > ---
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > index 14797e80bc92..263c9c3f6a03 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > @@ -295,7 +295,7 @@ struct guc_update_scheduling_policy_header {
> > > } __packed;
> > >
> > > /*
> > > - * Can't dynmically allocate memory for the scheduling policy KLV because
> > > + * Can't dynamically allocate memory for the scheduling policy KLV
> > > because
> > > * it will be sent from within the reset path. Need a fixed size lump on
> > > * the stack instead :(.
> > > *
> > > --
> > > 2.45.1
> >
Re: [PATCH v2 1/2] drm/dp: Describe target_rr_divider in struct drm_dp_as_sdp
On Fri, Jun 14, 2024 at 09:55:57AM +0530, Mitul Golani wrote:
> Describe newly added parameter target_rr_divider in struct
> drm_dp_as_sdp.
>
> -v2:
> Remove extra line from commit message.(Lucas)
>
> Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing
> AS SDP")
> Cc: Mitul Golani
> Cc: Arun R Murthy
> Cc: Suraj Kandpal
> Cc: Ankit Nautiyal
> Cc: Jani Nikula
> Cc: Stephen Rothwell
> Signed-off-by: Mitul Golani
> Reviewed-by: Ankit Nautiyal
> ---
> include/drm/display/drm_dp_helper.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index ea03e1dd26ba..7f2567fa230d 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -112,6 +112,7 @@ struct drm_dp_vsc_sdp {
> * @target_rr: Target Refresh
> * @duration_incr_ms: Successive frame duration increase
> * @duration_decr_ms: Successive frame duration decrease
> + * @target_rr_divider: Target refresh rate divider
Maarten, Maxime, or Thomas,
the patch introducing this target_rr_divider is in drm-intel-next.
Ack on adding this through drm-intel-next as well?
> * @mode: Adaptive Sync Operation Mode
> */
> struct drm_dp_as_sdp {
> --
> 2.45.2
>
RE: [PATCH] drm/i915/gt/uc: Fix typo in comment
>
> -Original Message-
From: Vivi, Rodrigo
Sent: Friday, June 14, 2024 12:46 PM
To: Cavitt, Jonathan
Cc: Andi Shyti ; intel-gfx
; dri-devel ;
Harrison, John C
Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
>
> On Fri, Jun 14, 2024 at 03:23:54PM +, Cavitt, Jonathan wrote:
> > -Original Message-
> > From: Andi Shyti
> > Sent: Friday, June 14, 2024 8:22 AM
> > To: Andi Shyti
> > Cc: intel-gfx ; dri-devel
> > ; Harrison, John C
> > ; Cavitt, Jonathan
> > Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
> > >
> > > I guess sparse and potential CI errors won't minimally relate to
> > > this patch.
> >
> > Yeah, I don't see how a change to a comment could ever be related
> > to any CI errors:
> >
> > Reviewed-by: Jonathan Cavitt
>
> Please ensure you use the full line.
> 1. People don't have to go to the header of your email to get your email.
> 2. People might not be entirely sure of your choice of email. Please notice
> that
> even on Intel many folks have @intel.com and @linux.intel.com and sometimes
> although
> responding from one, they use the other to sign things.
> 3. Tooling! (b4, patchwork, etc) There are many tools that get these tags
> directly
> from the email response and by using partial one you can complicate things.
>
> If you also allow one advice, try to use a terminal mail client like mutt and
> open the replies in your favorite editor and add macros there to add your
> lines
> based on shortcuts... For instance, on my case I use mutt+emacs and I just hit
> Ctrl+c-rev and that adds my full rv-b tag in the response.
>
Whoops!
Reviewed-by: Jonathan Cavitt
-Jonathan Cavitt
> Thanks,
> Rodrigo.
>
> > -Jonathan Cavitt
> >
> > >
> > > Adding also Jonathan in Cc :-)
> > >
> > > Thanks,
> > > Andi
> > >
> > > On Fri, Jun 14, 2024 at 12:28:37AM +0200, Andi Shyti wrote:
> > > > Replace "dynmically" with "dynamically".
> > > >
> > > > Signed-off-by: Andi Shyti
> > > > Cc: John Harrison
> > > > ---
> > > > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > > index 14797e80bc92..263c9c3f6a03 100644
> > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > > > @@ -295,7 +295,7 @@ struct guc_update_scheduling_policy_header {
> > > > } __packed;
> > > >
> > > > /*
> > > > - * Can't dynmically allocate memory for the scheduling policy KLV
> > > > because
> > > > + * Can't dynamically allocate memory for the scheduling policy KLV
> > > > because
> > > > * it will be sent from within the reset path. Need a fixed size lump
> > > > on
> > > > * the stack instead :(.
> > > > *
> > > > --
> > > > 2.45.1
> > >
>
Re: Linux 6.10-rc1
Hi! > > Let's bring in the actual gpu people.. Dave/Jani/others - does any of > > this sound familiar? Pavel says things have gotten much slower in > > 6.10: "something was very wrong with the performance, likely to do > > with graphics" > > Actually, maybe it's not graphics at all. Rafael just sent me a pull > request that fixes a "turbo is disabled at boot, but magically enabled > at runtime by firmware" issue. > > The 6.10-rc1 kernel would notice that turbo was disabled, and stopped > noticing that it magically got re-enabled. > > Pavel, that was with a very different laptop, but who knows... That > would match the "laptop is much slower" thing. > > So current -git might be worth checking. Ok, let me check. That sounds like something that could make machine hotter. My problem seems to be that machine seems to run way hotter with 6.10, and when it hovers around the 97C limit, it is unusable with all the throttling. It gets unusable with 6.9 at 97C, too, it is just that it is harder to make it so hot with 6.9. (And yes, I'm running Chromium, and yes, that means websites influence this. Media playback also does, 1080p video pushes thermals close to the limits even on good kernels.) Thanks and best regards, Pavel -- People of Russia, stop Putin before his war on Ukraine escalates. signature.asc Description: PGP signature
Re: Linux 6.10-rc1
Hi! > > Let's bring in the actual gpu people.. Dave/Jani/others - does any of > > this sound familiar? Pavel says things have gotten much slower in > > 6.10: "something was very wrong with the performance, likely to do > > with graphics" > > Actually, maybe it's not graphics at all. Rafael just sent me a pull > request that fixes a "turbo is disabled at boot, but magically enabled > at runtime by firmware" issue. > > The 6.10-rc1 kernel would notice that turbo was disabled, and stopped > noticing that it magically got re-enabled. > > Pavel, that was with a very different laptop, but who knows... That > would match the "laptop is much slower" thing. > > So current -git might be worth checking. Is that: commit 0cac73eb3875f6ecb6105e533218dba1868d04c9 Merge: 94df82fe5bfd 350cbb5d2f67 Author: Linus Torvalds Date: Fri Jun 14 09:52:51 2024 -0700 Merge tag 'pm-6.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management fix from Rafael Wysocki: "Restore the behavior of the no_turbo sysfs attribute in the intel_pstate driver which allowed users to make the driver start using turbo P-states if they have been enabled on the fly by the firmware after OS initialization (Rafael Wysocki)" * tag 'pm-6.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: cpufreq: intel_pstate: Check turbo_is_disabled() in store_no_turbo() ? I don't think I tweaking no_turbo in the sysfs. But the thermal stuff looks important: commit cee84c0b003f2e0f486f200a72eca2bcdb3a49a7 Merge: d20f6b3d747c b6846826982b Author: Linus Torvalds Date: Fri Jun 14 09:28:56 2024 -0700 Merge tag 'thermal-6.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm So I guess I'll have to try again. Thanks and best regards, Pavel -- People of Russia, stop Putin before his war on Ukraine escalates. signature.asc Description: PGP signature
[drm-intel:for-linux-next-gt 3/3] drivers/gpu/drm/i915/gem/i915_gem_stolen.c:941:5: error: format '%lli' expects argument of type 'long long int', but argument 5 has type 'resource_size_t' {aka 'unsig
tree: git://anongit.freedesktop.org/drm-intel for-linux-next-gt
head: 05da7d9f717bcb03c457379fa8a61c1689dab86c
commit: 05da7d9f717bcb03c457379fa8a61c1689dab86c [3/3] drm/i915/gem: Downgrade
stolen lmem setup warning
config: i386-buildonly-randconfig-002-20240615
(https://download.01.org/0day-ci/archive/20240615/202406150427.gdadsy5g-...@intel.com/config)
compiler: gcc-9 (Ubuntu 9.5.0-4ubuntu2) 9.5.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20240615/202406150427.gdadsy5g-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202406150427.gdadsy5g-...@intel.com/
All errors (new ones prefixed by >>):
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/i915/gem/i915_gem_stolen.c:10:
drivers/gpu/drm/i915/gem/i915_gem_stolen.c: In function
'i915_gem_stolen_lmem_setup':
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:941:5: error: format '%lli'
>> expects argument of type 'long long int', but argument 5 has type
>> 'resource_size_t' {aka 'unsigned int'} [-Werror=format=]
941 | "Disabling stolen memory support due to OOB placement: lmem_size
= %lli vs dsm_base = %lli\n",
|
^
942 | lmem_size, dsm_base);
| ~
| |
| resource_size_t {aka unsigned int}
include/drm/drm_print.h:422:32: note: in definition of macro 'drm_dev_dbg'
422 | __drm_dev_dbg(NULL, dev, cat, fmt, ##__VA_ARGS__)
|^~~
include/drm/drm_print.h:522:32: note: in expansion of macro 'drm_dbg_driver'
522 | #define drm_dbg(drm, fmt, ...) drm_dbg_driver(drm, fmt,
##__VA_ARGS__)
|^~
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:940:4: note: in expansion of
macro 'drm_dbg'
940 |drm_dbg(&i915->drm,
|^~~
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:941:75: note: format string is
defined here
941 | "Disabling stolen memory support due to OOB placement: lmem_size
= %lli vs dsm_base = %lli\n",
|
~~~^
|
|
|
long long int
|
%i
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/i915/gem/i915_gem_stolen.c:10:
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:941:5: error: format '%lli'
expects argument of type 'long long int', but argument 6 has type
'resource_size_t' {aka 'unsigned int'} [-Werror=format=]
941 | "Disabling stolen memory support due to OOB placement: lmem_size
= %lli vs dsm_base = %lli\n",
|
^
942 | lmem_size, dsm_base);
|
||
|resource_size_t {aka unsigned int}
include/drm/drm_print.h:422:32: note: in definition of macro 'drm_dev_dbg'
422 | __drm_dev_dbg(NULL, dev, cat, fmt, ##__VA_ARGS__)
|^~~
include/drm/drm_print.h:522:32: note: in expansion of macro 'drm_dbg_driver'
522 | #define drm_dbg(drm, fmt, ...) drm_dbg_driver(drm, fmt,
##__VA_ARGS__)
|^~
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:940:4: note: in expansion of
macro 'drm_dbg'
940 |drm_dbg(&i915->drm,
|^~~
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:941:94: note: format string is
defined here
941 | "Disabling stolen memory support due to OOB placement: lmem_size
= %lli vs dsm_base = %lli\n",
|
~~~^
|
|
|
long long int
|
%i
cc1: all warnings being treated as errors
vim +941 drivers/gpu/drm/i915/gem/i915_gem_stolen.c
889
890 struct intel_memory_region *
891 i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
892 u16 instance)
893 {
894 struct intel_uncore *uncore = &i915->uncore;
895 struct pci_dev *pdev = to_pc
Re: [PATCH v8 06/20] drm/i915/psr: Disable PSR2 SU Region Early Transport if psr_enable is set
On Fri, 2024-06-14 at 16:55 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Thursday, June 13, 2024 3:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v8 06/20] drm/i915/psr: Disable PSR2 SU Region
> > Early
> > Transport if psr_enable is set
> >
> > Currently PSR2 SU Region Early Transport is enabled by default on
> > Lunarlake
> > if panel supports it despite psr_enable value. Prevent SU Region
> > Early
> > Transport if psr_enable is set to than -1 which is the default.
> >
> > Signed-off-by: Jouni Högander
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 13 -
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 0df557676e08..27cf330d13e2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct
> > intel_dp
> > *intel_dp)
> > }
> > }
> >
> > +static bool psr2_su_region_et_global_enabled(struct intel_dp
> > *intel_dp)
> > +{
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (i915->display.params.enable_psr != -1)
> > + return false;
> > +
> > + return true;
> > +}
> > +
> > static bool panel_replay_global_enabled(struct intel_dp
> > *intel_dp) {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -
> > 683,7
> > +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp
> > *intel_dp,
> > bool panel_replay
> >
> > return panel_replay ?
> > intel_dp->pr_dpcd &
> > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> > - intel_dp->psr_dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
> > + intel_dp->psr_dpcd[0] ==
> > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> > + psr2_su_region_et_global_enabled(intel_dp);
>
> How to enable early transport with psr/psr2? Is it not possible
> now/future?
It gets enabled if panel supports it. Unless disable bit is set
(I915_PSR_DEBUG_SU_REGION_ET_DISABLE) or enable_psr module parameter is
set.
BR,
Jouni Högander
>
> Regards,
> Animesh
>
> > }
> >
> > static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
> > --
> > 2.34.1
>
Re: [PATCH v8 02/20] drm/i915/display: Wa 16021440873 is writing wrong register
On Fri, 2024-06-14 at 16:11 +, Manna, Animesh wrote:
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Thursday, June 13, 2024 3:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Kahola, Mika
> > ; Hogander, Jouni
> > Subject: [PATCH v8 02/20] drm/i915/display: Wa 16021440873 is
> > writing
> > wrong register
> >
> > Wa 16021440873 is writing wrong register. Instead of
> > PIPE_SRCSZ_ERLY_TPT
> > write CURPOS_ERLY_TPT.
> >
> > v2: use right offset as well
> >
> > Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873")
> > Signed-off-by: Jouni Högander
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_psr.c | 12 +++-
> > 2 files changed, 5 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
> > b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index cea0cfed569d..6ea76687dd14 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -524,8 +524,8 @@ static void wa_16021440873(struct intel_plane
> > *plane,
> >
> > intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
> >
> > - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
> > - PIPESRC_HEIGHT(et_y_position));
> > + intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe),
> > + CURSOR_POS_Y(et_y_position));
> > }
> >
> > static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane
> > *plane, diff
> > --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 66ab8abd0a04..44144dcfb1a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2164,19 +2164,14 @@ static void psr2_man_trk_ctl_calc(struct
> > intel_crtc_state *crtc_state,
> > crtc_state->psr2_man_track_ctl = val;
> > }
> >
> > -static u32
> > -psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state
> > *crtc_state,
> > - bool full_update, bool
> > cursor_in_su_area)
> > +static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state
> > *crtc_state,
> > + bool full_update)
> > {
> > int width, height;
> >
> > if (!crtc_state->enable_psr2_su_region_et || full_update)
> > return 0;
> >
> > - if (!cursor_in_su_area)
> > - return PIPESRC_WIDTH(0) |
> > - PIPESRC_HEIGHT(drm_rect_height(&crtc_state-
> > > pipe_src));
> > -
>
> Should the PIPESRC_WIDTH() related changes go with patch1?
> Not sure why it is added with this patch which correct the register
> offset value.
I was originally thinking I need to take wa_16021440873 into account
here as well because this is calculating value for PIPE_SRCSZ_ERLY_TPT.
As PIPE_SRCSZ_ERLY_TPT was wrong offset -> no need to care about the
wa.
BR,
Jouni Högander
>
> Regards,
> Animesh
>
> > width = drm_rect_width(&crtc_state->psr2_su_area);
> > height = drm_rect_height(&crtc_state->psr2_su_area);
> >
> > @@ -2485,8 +2480,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > skip_sel_fetch_set_loop:
> > psr2_man_trk_ctl_calc(crtc_state, full_update);
> > crtc_state->pipe_srcsz_early_tpt =
> > - psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update,
> > - cursor_in_su_area);
> > + psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > return 0;
> > }
> >
> > --
> > 2.34.1
>
✓ Fi.CI.IGT: success for drm/i915/gt/uc: Evaluate GuC priority within locks (rev4)
== Series Details == Series: drm/i915/gt/uc: Evaluate GuC priority within locks (rev4) URL : https://patchwork.freedesktop.org/series/134525/ State : success == Summary == CI Bug Log - changes from CI_DRM_14937_full -> Patchwork_134525v4_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_134525v4_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-6/igt@api_intel...@blit-reloc-keep-cache.html - shard-rkl: NOTRUN -> [SKIP][2] ([i915#8411]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-4/igt@api_intel...@blit-reloc-keep-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][3] ([i915#10380]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-6/igt@api_intel...@render-ccs.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#11078]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-6/igt@device_re...@cold-reset-bound.html - shard-rkl: NOTRUN -> [SKIP][5] ([i915#11078]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-4/igt@device_re...@cold-reset-bound.html * igt@drm_fdinfo@all-busy-check-all: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg1-14/igt@drm_fdi...@all-busy-check-all.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +6 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-10/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#7742]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14937/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-5/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@gem_bad_reloc@negative-reloc-lut: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#3281]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg1-14/igt@gem_bad_re...@negative-reloc-lut.html * igt@gem_basic@multigpu-create-close: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#7697]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-mtlp-3/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][12] ([i915#9323]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-4/igt@gem_...@block-multicopy-compressed.html * igt@gem_ctx_freq@sysfs@gt0: - shard-dg2: [PASS][13] -> [FAIL][14] ([i915#9561]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14937/shard-dg2-7/igt@gem_ctx_freq@sy...@gt0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-6/igt@gem_ctx_freq@sy...@gt0.html * igt@gem_ctx_sseu@mmap-args: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#280]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-10/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@kms: - shard-dg1: NOTRUN -> [FAIL][16] ([i915#5784]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg1-14/igt@gem_...@kms.html * igt@gem_exec_balancer@bonded-semaphore: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#4812]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-mtlp-3/igt@gem_exec_balan...@bonded-semaphore.html * igt@gem_exec_balancer@parallel-out-fence: - shard-rkl: NOTRUN -> [SKIP][18] ([i915#4525]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-5/igt@gem_exec_balan...@parallel-out-fence.html * igt@gem_exec_balancer@sliced: - shard-dg2: NOTRUN -> [SKIP][19] ([i915#4812]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-10/igt@gem_exec_balan...@sliced.html * igt@gem_exec_fair@basic-deadline: - shard-rkl: NOTRUN -> [FAIL][20] ([i915#2846]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-rkl-4/igt@gem_exec_f...@basic-deadline.html - shard-dg2: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134525v4/shard-dg2-6/igt@gem_exec_f...@basic-dead
✓ Fi.CI.IGT: success for drm/i915/gt/uc: Fix typo in comment
== Series Details == Series: drm/i915/gt/uc: Fix typo in comment URL : https://patchwork.freedesktop.org/series/134851/ State : success == Summary == CI Bug Log - changes from CI_DRM_14937_full -> Patchwork_134851v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_134851v1_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-keep-cache: - shard-rkl: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-rkl-5/igt@api_intel...@blit-reloc-keep-cache.html * igt@api_intel_bb@blit-reloc-purge-cache: - shard-dg2: NOTRUN -> [SKIP][2] ([i915#8411]) +1 other test skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-11/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@render-ccs: - shard-dg2: NOTRUN -> [FAIL][3] ([i915#10380]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-5/igt@api_intel...@render-ccs.html * igt@device_reset@cold-reset-bound: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#11078]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-5/igt@device_re...@cold-reset-bound.html - shard-rkl: NOTRUN -> [SKIP][5] ([i915#11078]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-rkl-5/igt@device_re...@cold-reset-bound.html * igt@drm_fdinfo@all-busy-check-all: - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg1-16/igt@drm_fdi...@all-busy-check-all.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414]) +6 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-6/igt@drm_fdinfo@busy-h...@bcs0.html * igt@drm_fdinfo@most-busy-check-all@rcs0: - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#7742]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14937/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-rkl-1/igt@drm_fdinfo@most-busy-check-...@rcs0.html * igt@gem_bad_reloc@negative-reloc-lut: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#3281]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg1-16/igt@gem_bad_re...@negative-reloc-lut.html * igt@gem_basic@multigpu-create-close: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#7697]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-mtlp-5/igt@gem_ba...@multigpu-create-close.html - shard-dg2: NOTRUN -> [SKIP][12] ([i915#7697]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-11/igt@gem_ba...@multigpu-create-close.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][13] ([i915#9323]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-rkl-5/igt@gem_...@block-multicopy-compressed.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][14] -> [FAIL][15] ([i915#6268]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14937/shard-tglu-6/igt@gem_ctx_e...@basic-nohangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-tglu-5/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#8555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-11/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_sseu@mmap-args: - shard-dg2: NOTRUN -> [SKIP][17] ([i915#280]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-6/igt@gem_ctx_s...@mmap-args.html * igt@gem_eio@kms: - shard-dg1: NOTRUN -> [FAIL][18] ([i915#5784]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg1-16/igt@gem_...@kms.html * igt@gem_exec_balancer@bonded-semaphore: - shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4812]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-mtlp-5/igt@gem_exec_balan...@bonded-semaphore.html * igt@gem_exec_balancer@invalid-bonds: - shard-dg2: NOTRUN -> [SKIP][20] ([i915#4036]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/shard-dg2-11/igt@gem_exec_balan...@invalid-bonds.html * igt@gem_exec_balancer@parallel-out-fence: - shard-rkl: NOTRUN -> [SKIP][21] ([i915#4525]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134851v1/
Re: [PATCH v3] drm/i915/display: update handling of FBC when VT-d active workaround
On Tue, 2024-05-28 at 14:48 +0300, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane(). As the hw is still there,
> intel_fbc_sanitize should be able to handle the state properly.
>
> v2: update the patch description (Jani Nikula)
>
> v3: fix the return value in wa handling (Jani Nikula)
>
> Bspec: 21664
> Suggested-by: Ville Syrjälä
> Signed-off-by: Vinod Govindapillai
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index e9189a864f69..b546ebc6823d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,6 +1235,12 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> + if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) ||
> IS_BROXTON(i915))) {
> + plane_state->no_fbc_reason = "VT-d enabled";
> + return 0;
> + }
> +
> crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>
> if (crtc_state->hw.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE) {
> @@ -1820,19 +1826,6 @@ static int intel_sanitize_fbc_option(struct
> drm_i915_private *i915)
> return 0;
> }
>
> -static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
> -{
> - /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> - if (i915_vtd_active(i915) &&
> - (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
> - drm_info(&i915->drm,
> - "Disabling framebuffer compression (FBC) to
> prevent screen flicker with VT-d enabled\n");
> - return true;
> - }
> -
> - return false;
> -}
> -
> void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane
> *plane)
> {
> plane->fbc = fbc;
> @@ -1878,9 +1871,6 @@ void intel_fbc_init(struct drm_i915_private
> *i915)
> {
> enum intel_fbc_id fbc_id;
>
> - if (need_fbc_vtd_wa(i915))
> - DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
> -
> i915->display.params.enable_fbc =
> intel_sanitize_fbc_option(i915);
> drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
> i915->display.params.enable_fbc);
Re: [PATCH v1] drm/xe: avoid the async_flip update in the initial plane config
On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote: > Async flip call is not needed. The updated fb mapping is updated > as part of the fixup_initial_plane_config() call. Otherwise we > end up updating the PLAN_SURF register twice with the same info. async_flip is writing PLANE_CTL as well. Is it ok to leave that out? BR, Jouni Högander > > v2: avoid async_flip instead of removing fixup call (Ville) > > Signed-off-by: Vinod Govindapillai > --- > drivers/gpu/drm/xe/display/xe_plane_initial.c | 10 -- > 1 file changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c > b/drivers/gpu/drm/xe/display/xe_plane_initial.c > index 9693c56d386b..b5f8381b593d 100644 > --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c > +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c > @@ -189,8 +189,6 @@ intel_find_initial_plane_obj(struct intel_crtc > *crtc, > to_intel_plane(crtc->base.primary); > struct intel_plane_state *plane_state = > to_intel_plane_state(plane->base.state); > - struct intel_crtc_state *crtc_state = > - to_intel_crtc_state(crtc->base.state); > struct drm_framebuffer *fb; > struct i915_vma *vma; > > @@ -236,14 +234,6 @@ intel_find_initial_plane_obj(struct intel_crtc > *crtc, > atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)- > >bits); > > plane_config->vma = vma; > - > - /* > - * Flip to the newly created mapping ASAP, so we can re-use > the > - * first part of GGTT for WOPCM, prevent flickering, and > prevent > - * the lookup of sysmem scratch pages. > - */ > - plane->check_plane(crtc_state, plane_state); > - plane->async_flip(plane, crtc_state, plane_state, true); > return; > > nofb:
Re: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Send vrr vsync params whne vrr is enabled
On Tue, 11 Jun 2024, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: Send vrr vsync params whne vrr is enabled
> URL : https://patchwork.freedesktop.org/series/134714/
> State : warning
>
> == Summary ==
>
> Error: dim checkpatch failed
> 711332181393 drm/i915/display: Send vrr vsync params whne vrr is enabled
> -:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
> #26: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:236:
> + if (intel_dp_as_sdp_supported(intel_dp) &&
> + crtc_state->vrr.enable) {
Please fix this.
>
> total: 0 errors, 0 warnings, 1 checks, 9 lines checked
>
>
--
Jani Nikula, Intel
RE: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Send vrr vsync params whne vrr is enabled
Hi @Jani Nikula
> -Original Message-
> From: Jani Nikula
> Sent: Friday, June 14, 2024 1:09 PM
> To: Patchwork ; Golani, Mitulkumar
> Ajitkumar
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Send vrr
> vsync params whne vrr is enabled
>
> On Tue, 11 Jun 2024, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/display: Send vrr vsync params whne vrr is enabled
> > URL : https://patchwork.freedesktop.org/series/134714/
> > State : warning
> >
> > == Summary ==
> >
> > Error: dim checkpatch failed
> > 711332181393 drm/i915/display: Send vrr vsync params whne vrr is
> enabled
> > -:26: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open
> parenthesis
> > #26: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:236:
> > + if (intel_dp_as_sdp_supported(intel_dp) &&
> > + crtc_state->vrr.enable) {
>
> Please fix this.
I fixed into next revision and got merged.
https://patchwork.freedesktop.org/patch/598089/?series=134714&rev=2
Thanks,
Mitul
>
>
> >
> > total: 0 errors, 0 warnings, 1 checks, 9 lines checked
> >
> >
>
> --
> Jani Nikula, Intel
[PULL] drm-misc-fixes
Hi Dave, Sima, Got a bit distracted with drm-misc-next-fixes yesterday, so here's a slightly late drm-misc-fixes. Cheers, ~Maarten drm-misc-fixes-2024-06-14: drm-misc-fixes for v6.10-rc4: - Kconfig fix for WERROR. - Add panel quirk for Aya Neo KUN - Small bugfixes in komeda, bridge/panel, amdgpu, nouveau. - Remove unused nouveau struct. - Call drm_atomic_helper_shutdown for shmobile and mediatek on shutdown. - Remove DEBUGFS ifdefs from komeda. The following changes since commit f1909e859753c9bda87c6d2b82a7f832ef80aa2d: Merge tag 'drm-xe-fixes-2024-06-13' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes (2024-06-14 11:08:06 +1000) are available in the Git repository at: https://gitlab.freedesktop.org/drm/misc/kernel.git tags/drm-misc-fixes-2024-06-14 for you to fetch changes up to 14731a640e5513bd514adcf35e96c84ad42f540d: Merge drm/drm-fixes into drm-misc-fixes (2024-06-14 09:55:46 +0200) drm-misc-fixes for v6.10-rc4: - Kconfig fix for WERROR. - Add panel quirk for Aya Neo KUN - Small bugfixes in komeda, bridge/panel, amdgpu, nouveau. - Remove unused nouveau struct. - Call drm_atomic_helper_shutdown for shmobile and mediatek on shutdown. - Remove DEBUGFS ifdefs from komeda. Adam Miotk (1): drm/bridge/panel: Fix runtime warning on panel bridge release Amjad Ouled-Ameur (1): drm/komeda: check for error-valued pointer Arunpravin Paneer Selvam (1): drm/amdgpu: Fix the BO release clear memory warning Douglas Anderson (2): drm: renesas: shmobile: Call drm_atomic_helper_shutdown() at shutdown time drm/mediatek: Call drm_atomic_helper_shutdown() at shutdown time Dr. David Alan Gilbert (1): drm/nouveau: remove unused struct 'init_exec' Jani Nikula (1): drm: have config DRM_WERROR depend on !WERROR Maxime Ripard (1): Merge drm/drm-fixes into drm-misc-fixes Tobias Jakobi (1): drm: panel-orientation-quirks: Add quirk for Aya Neo KUN Vasily Khoruzhick (1): drm/nouveau: don't attempt to schedule hpd_work on headless cards pengfuyuan (1): arm/komeda: Remove all CONFIG_DEBUG_FS conditional compilations drivers/gpu/drm/Kconfig| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 -- drivers/gpu/drm/arm/display/komeda/komeda_dev.c| 8 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 2 +- drivers/gpu/drm/bridge/panel.c | 7 +-- drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 drivers/gpu/drm/nouveau/dispnv04/disp.c| 2 +- drivers/gpu/drm/nouveau/dispnv50/disp.c| 2 +- drivers/gpu/drm/nouveau/nouveau_bios.c | 5 - drivers/gpu/drm/nouveau/nouveau_display.c | 6 +- drivers/gpu/drm/nouveau/nouveau_drv.h | 1 + drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.c | 8 14 files changed, 38 insertions(+), 21 deletions(-)
Re: [PATCH v2 0/6] drm/i915: gvt register macro cleanups, unused macro removals
On Fri, 07 Jun 2024, Jani Nikula wrote: > v2 of https://lore.kernel.org/r/cover.1717757337.git.jani.nik...@intel.com Thanks for the reviews, pushed to din. BR, Jani. > > Jani Nikula (6): > drm/i915/gvt: remove the unused end parameter from calc_index() > drm/i915/gvt: use proper i915_reg_t for calc_index() parameters > drm/i915/gvt: rename range variable to stride > drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE() > drm/i915: relocate some DSPCNTR reg bit definitions > drm/i915: remove unused pipe/plane B register macros > > .../gpu/drm/i915/display/i9xx_plane_regs.h| 2 ++ > drivers/gpu/drm/i915/gvt/handlers.c | 29 ++- > drivers/gpu/drm/i915/i915_reg.h | 23 --- > 3 files changed, 17 insertions(+), 37 deletions(-) -- Jani Nikula, Intel
Re: [PATCH v1] drm/xe: avoid the async_flip update in the initial plane config
On Fri, 2024-06-14 at 07:11 +, Hogander, Jouni wrote: > On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote: > > Async flip call is not needed. The updated fb mapping is updated > > as part of the fixup_initial_plane_config() call. Otherwise we > > end up updating the PLAN_SURF register twice with the same info. > > async_flip is writing PLANE_CTL as well. Is it ok to leave that out? Thanks for the review Jouni! Yes.. that is not needed for the initial plane config. The i915 counterpart don't have this either! I had confirmed this with Maarten and Ville. According to Maarten, most likely this part was copied from i915 which got dropped when refactoring. BR Vinod > > BR, > > Jouni Högander > > > > > v2: avoid async_flip instead of removing fixup call (Ville) > > > > Signed-off-by: Vinod Govindapillai > > --- > > drivers/gpu/drm/xe/display/xe_plane_initial.c | 10 -- > > 1 file changed, 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c > > b/drivers/gpu/drm/xe/display/xe_plane_initial.c > > index 9693c56d386b..b5f8381b593d 100644 > > --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c > > +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c > > @@ -189,8 +189,6 @@ intel_find_initial_plane_obj(struct intel_crtc > > *crtc, > > to_intel_plane(crtc->base.primary); > > struct intel_plane_state *plane_state = > > to_intel_plane_state(plane->base.state); > > - struct intel_crtc_state *crtc_state = > > - to_intel_crtc_state(crtc->base.state); > > struct drm_framebuffer *fb; > > struct i915_vma *vma; > > > > @@ -236,14 +234,6 @@ intel_find_initial_plane_obj(struct intel_crtc > > *crtc, > > atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)- > > > bits); > > > > plane_config->vma = vma; > > - > > - /* > > - * Flip to the newly created mapping ASAP, so we can re-use > > the > > - * first part of GGTT for WOPCM, prevent flickering, and > > prevent > > - * the lookup of sysmem scratch pages. > > - */ > > - plane->check_plane(crtc_state, plane_state); > > - plane->async_flip(plane, crtc_state, plane_state, true); > > return; > > > > nofb: >
Re: [PATCH v2 3/8] drm/i915: Don't check for atomic context on PREEMPT_RT
On 13/06/2024 11:20, Sebastian Andrzej Siewior wrote:
The !in_atomic() check in _wait_for_atomic() triggers on PREEMPT_RT
because the uncore::lock is a spinlock_t and does not disable
preemption or interrupts.
Changing the uncore:lock to a raw_spinlock_t doubles the worst case
latency on an otherwise idle testbox during testing. Therefore I'm
currently unsure about changing this.
Link: https://lore.kernel.org/all/20211006164628.s2mtsdd2jdbfy...@linutronix.de/
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/gpu/drm/i915/i915_utils.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 06ec6ceb61d57..2ca54bc235925 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -274,7 +274,7 @@ wait_remaining_ms_from_jiffies(unsigned long
timestamp_jiffies, int to_wait_ms)
#define wait_for(COND, MS)_wait_for((COND), (MS) * 1000, 10, 1000)
/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
-#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
+#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) &&
!defined(CONFIG_PREEMPT_RT)
# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
#else
# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
I think this could be okay-ish in principle, but the commit text is not
entirely accurate because there is no direct coupling between the wait
helpers and the uncore lock. They can be used from any atomic context.
Okay-ish in principle because there is sufficient testing in Intel's CI
on non-PREEMPT_RT kernels to catch any conceptual misuses.
But see also the caller in skl_pcode_request. It is a bit harder to hit
since it is the fallback path. Or gen5_rps_enable which nests under a
different lock.
Hmm would there be a different helper, or combination of helpers, which
could replace in_atomic() which would do the right thing on both
kernels? Something to tell us we are neither under a spin_lock, nor
preempt_disable, nor interrupts disabled, nor bottom-half. On either
stock or PREEMPT_RT.
WARN_ON_ONCE((ATOMIC) && !(!preemptible() || in_hardirq() ||
in_serving_softirq())
Would this work?
Regards,
Tvrtko
Re: [PATCH v1] drm/xe: avoid the async_flip update in the initial plane config
On Fri, 2024-06-14 at 08:23 +, Govindapillai, Vinod wrote: > On Fri, 2024-06-14 at 07:11 +, Hogander, Jouni wrote: > > On Fri, 2024-04-19 at 17:09 +0300, Vinod Govindapillai wrote: > > > Async flip call is not needed. The updated fb mapping is updated > > > as part of the fixup_initial_plane_config() call. Otherwise we > > > end up updating the PLAN_SURF register twice with the same info. > > > > async_flip is writing PLANE_CTL as well. Is it ok to leave that > > out? > > Thanks for the review Jouni! > > Yes.. that is not needed for the initial plane config. The i915 > counterpart don't have this either! > I had confirmed this with Maarten and Ville. According to Maarten, > most likely this part was copied > from i915 which got dropped when refactoring. Reviewed-by: Jouni Högander > > BR > Vinod > > > > > BR, > > > > Jouni Högander > > > > > > > > v2: avoid async_flip instead of removing fixup call (Ville) > > > > > > Signed-off-by: Vinod Govindapillai > > > > > > --- > > > drivers/gpu/drm/xe/display/xe_plane_initial.c | 10 -- > > > 1 file changed, 10 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c > > > b/drivers/gpu/drm/xe/display/xe_plane_initial.c > > > index 9693c56d386b..b5f8381b593d 100644 > > > --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c > > > +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c > > > @@ -189,8 +189,6 @@ intel_find_initial_plane_obj(struct > > > intel_crtc > > > *crtc, > > > to_intel_plane(crtc->base.primary); > > > struct intel_plane_state *plane_state = > > > to_intel_plane_state(plane->base.state); > > > - struct intel_crtc_state *crtc_state = > > > - to_intel_crtc_state(crtc->base.state); > > > struct drm_framebuffer *fb; > > > struct i915_vma *vma; > > > > > > @@ -236,14 +234,6 @@ intel_find_initial_plane_obj(struct > > > intel_crtc > > > *crtc, > > > atomic_or(plane->frontbuffer_bit, > > > &to_intel_frontbuffer(fb)- > > > > bits); > > > > > > plane_config->vma = vma; > > > - > > > - /* > > > - * Flip to the newly created mapping ASAP, so we can re- > > > use > > > the > > > - * first part of GGTT for WOPCM, prevent flickering, and > > > prevent > > > - * the lookup of sysmem scratch pages. > > > - */ > > > - plane->check_plane(crtc_state, plane_state); > > > - plane->async_flip(plane, crtc_state, plane_state, true); > > > return; > > > > > > nofb: > > >
[CI 00/11] drm/i915: mem/fsb/rawclk freq cleanups
The earlier series [1] had some init order issues in patch 11/14 as noted by Ville [2]. I'll look into it, but in the mean time, here are the reviewed patches 1-10 and 14 from that series for CI, with 11-13 dropped and to be revisited and posted later. BR, Jani. [1] https://lore.kernel.org/r/cover.1717672515.git.jani.nik...@intel.com [2] https://lore.kernel.org/r/zmlzcsomkt3cb...@intel.com Jani Nikula (11): drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency drm/i915/wm: clarify logging on not finding CxSR latency config drm/i915/dram: separate fsb freq detection from mem freq drm/i915/dram: split out pnv DDR3 detection drm/i915/dram: rearrange mem freq init drm/i915/gt: remove mem freq from gt debugfs drm/i915: convert fsb_freq and mem_freq to kHz drm/i915: extend the fsb_freq initialization to more platforms drm/i915: use i9xx_fsb_freq() for GT clock frequency drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization drm/i915: move comments about FSB straps to proper place drivers/gpu/drm/i915/display/i9xx_wm.c| 27 +-- drivers/gpu/drm/i915/display/intel_cdclk.c| 57 + .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 3 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 - drivers/gpu/drm/i915/gt/intel_rps.c | 11 +- drivers/gpu/drm/i915/soc/intel_dram.c | 212 +++--- drivers/gpu/drm/i915/soc/intel_dram.h | 1 + 7 files changed, 151 insertions(+), 161 deletions(-) -- 2.39.2
[CI 01/11] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency
Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index a12765d9e9e4..ba4a38be7545 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = {
{0, 1, 400, 800, 6042, 36042, 6584, 36584},/* DDR3-800 SC */
};
-static const struct cxsr_latency *intel_get_cxsr_latency(struct
drm_i915_private *i915)
+static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private
*i915)
{
int i;
@@ -637,7 +637,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
u32 reg;
unsigned int wm;
- latency = intel_get_cxsr_latency(dev_priv);
+ latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
drm_dbg_kms(&dev_priv->drm,
"Unknown FSB/MEM found, disable CxSR\n");
@@ -4029,7 +4029,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
g4x_setup_wm_latency(dev_priv);
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
- if (!intel_get_cxsr_latency(dev_priv)) {
+ if (!pnv_get_cxsr_latency(dev_priv)) {
drm_info(&dev_priv->drm,
"failed to find known CxSR latency "
"(found ddr%s fsb freq %d, mem freq %d), "
--
2.39.2
[CI 03/11] drm/i915/dram: separate fsb freq detection from mem freq
To simplify further changes, add separate functions for reading the fsb
frequency.
This ends up reading CLKCFG register twice, but it's not a big deal.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++---
1 file changed, 60 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 18a879e98f03..3dce9b9a2c5e 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
- switch (tmp & CLKCFG_FSB_MASK) {
- case CLKCFG_FSB_533:
- dev_priv->fsb_freq = 533; /* 133*4 */
- break;
- case CLKCFG_FSB_800:
- dev_priv->fsb_freq = 800; /* 200*4 */
- break;
- case CLKCFG_FSB_667:
- dev_priv->fsb_freq = 667; /* 167*4 */
- break;
- case CLKCFG_FSB_400:
- dev_priv->fsb_freq = 400; /* 100*4 */
- break;
- }
-
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
dev_priv->mem_freq = 533;
@@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
{
- u16 ddrpll, csipll;
+ u16 ddrpll;
ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
@@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private
*dev_priv)
dev_priv->mem_freq = 0;
break;
}
-
- csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
- switch (csipll & 0x3ff) {
- case 0x00c:
- dev_priv->fsb_freq = 3200;
- break;
- case 0x00e:
- dev_priv->fsb_freq = 3733;
- break;
- case 0x010:
- dev_priv->fsb_freq = 4266;
- break;
- case 0x012:
- dev_priv->fsb_freq = 4800;
- break;
- case 0x014:
- dev_priv->fsb_freq = 5333;
- break;
- case 0x016:
- dev_priv->fsb_freq = 5866;
- break;
- case 0x018:
- dev_priv->fsb_freq = 6400;
- break;
- default:
- drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
- csipll & 0x3ff);
- dev_priv->fsb_freq = 0;
- break;
- }
}
static void chv_detect_mem_freq(struct drm_i915_private *i915)
@@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
}
+static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+{
+ u32 fsb;
+
+ fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
+
+ switch (fsb) {
+ case CLKCFG_FSB_400:
+ return 400;
+ case CLKCFG_FSB_533:
+ return 533;
+ case CLKCFG_FSB_667:
+ return 667;
+ case CLKCFG_FSB_800:
+ return 800;
+ }
+
+ return 0;
+}
+
+static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
+{
+ u16 fsb;
+
+ fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff;
+
+ switch (fsb) {
+ case 0x00c:
+ return 3200;
+ case 0x00e:
+ return 3733;
+ case 0x010:
+ return 4266;
+ case 0x012:
+ return 4800;
+ case 0x014:
+ return 5333;
+ case 0x016:
+ return 5866;
+ case 0x018:
+ return 6400;
+ default:
+ drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
+ return 0;
+ }
+}
+
+static void detect_fsb_freq(struct drm_i915_private *i915)
+{
+ if (GRAPHICS_VER(i915) == 5)
+ i915->fsb_freq = ilk_fsb_freq(i915);
+ else if (IS_PINEVIEW(i915))
+ i915->fsb_freq = pnv_fsb_freq(i915);
+
+ if (i915->fsb_freq)
+ drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
+}
+
static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
{
return dimm->ranks * 64 / (dimm->width ?: 1);
@@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
struct dram_info *dram_info = &i915->dram_info;
int ret;
+ detect_fsb_freq(i915);
detect_mem_freq(i915);
if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
--
2.39.2
[CI 02/11] drm/i915/wm: clarify logging on not finding CxSR latency config
Clarify and unify the logging on not finding PNV CxSR latency
config.
Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through
the table instead of checking for it separately.
v2: Do not check for fsb == 0 || mem == 0 separately (Matt)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index ba4a38be7545..f70ac2f06968 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -74,9 +74,6 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct
drm_i915_private *
{
int i;
- if (i915->fsb_freq == 0 || i915->mem_freq == 0)
- return NULL;
-
for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
const struct cxsr_latency *latency = &cxsr_latency_table[i];
bool is_desktop = !IS_MOBILE(i915);
@@ -88,7 +85,9 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct
drm_i915_private *
return latency;
}
- drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n");
+ drm_dbg_kms(&i915->drm,
+ "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
MHz\n",
+ i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
return NULL;
}
@@ -639,8 +638,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
- drm_dbg_kms(&dev_priv->drm,
- "Unknown FSB/MEM found, disable CxSR\n");
+ drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling
CxSR\n");
intel_set_memory_cxsr(dev_priv, false);
return;
}
@@ -4030,12 +4028,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!pnv_get_cxsr_latency(dev_priv)) {
- drm_info(&dev_priv->drm,
-"failed to find known CxSR latency "
-"(found ddr%s fsb freq %d, mem freq %d), "
-"disabling CxSR\n",
-(dev_priv->is_ddr3 == 1) ? "3" : "2",
-dev_priv->fsb_freq, dev_priv->mem_freq);
+ drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling
CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
dev_priv->display.funcs.wm = &nop_funcs;
--
2.39.2
[CI 04/11] drm/i915/dram: split out pnv DDR3 detection
Split out the PNV DDR3 detection to a distinct step instead of
conflating it with mem freq detection.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 3dce9b9a2c5e..1a4db52ac258 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type
type)
#undef DRAM_TYPE_STR
+static bool pnv_is_ddr3(struct drm_i915_private *i915)
+{
+ return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
+}
+
static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
{
u32 tmp;
@@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
dev_priv->mem_freq = 800;
break;
}
-
- /* detect pineview DDR3 setting */
- tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
- dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
}
static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
@@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915)
else if (IS_VALLEYVIEW(i915))
vlv_detect_mem_freq(i915);
+ if (IS_PINEVIEW(i915))
+ i915->is_ddr3 = pnv_is_ddr3(i915);
+
if (i915->mem_freq)
drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
}
--
2.39.2
[CI 05/11] drm/i915/dram: rearrange mem freq init
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 59 ---
1 file changed, 25 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 1a4db52ac258..266ed6cfa485 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915)
return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
}
-static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
{
u32 tmp;
@@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
- dev_priv->mem_freq = 533;
- break;
+ return 533;
case CLKCFG_MEM_667:
- dev_priv->mem_freq = 667;
- break;
+ return 667;
case CLKCFG_MEM_800:
- dev_priv->mem_freq = 800;
- break;
+ return 800;
}
+
+ return 0;
}
-static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
{
u16 ddrpll;
ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
case 0xc:
- dev_priv->mem_freq = 800;
- break;
+ return 800;
case 0x10:
- dev_priv->mem_freq = 1066;
- break;
+ return 1066;
case 0x14:
- dev_priv->mem_freq = 1333;
- break;
+ return 1333;
case 0x18:
- dev_priv->mem_freq = 1600;
- break;
+ return 1600;
default:
drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
ddrpll & 0xff);
- dev_priv->mem_freq = 0;
- break;
+ return 0;
}
}
-static void chv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int chv_mem_freq(struct drm_i915_private *i915)
{
u32 val;
@@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 2) & 0x7) {
case 3:
- i915->mem_freq = 2000;
- break;
+ return 2000;
default:
- i915->mem_freq = 1600;
- break;
+ return 1600;
}
}
-static void vlv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
{
u32 val;
@@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 6) & 3) {
case 0:
case 1:
- i915->mem_freq = 800;
- break;
+ return 800;
case 2:
- i915->mem_freq = 1066;
- break;
+ return 1066;
case 3:
- i915->mem_freq = 1333;
- break;
+ return 1333;
}
+
+ return 0;
}
static void detect_mem_freq(struct drm_i915_private *i915)
{
if (IS_PINEVIEW(i915))
- pnv_detect_mem_freq(i915);
+ i915->mem_freq = pnv_mem_freq(i915);
else if (GRAPHICS_VER(i915) == 5)
- ilk_detect_mem_freq(i915);
+ i915->mem_freq = ilk_mem_freq(i915);
else if (IS_CHERRYVIEW(i915))
- chv_detect_mem_freq(i915);
+ i915->mem_freq = chv_mem_freq(i915);
else if (IS_VALLEYVIEW(i915))
- vlv_detect_mem_freq(i915);
+ i915->mem_freq = vlv_mem_freq(i915);
if (IS_PINEVIEW(i915))
i915->is_ddr3 = pnv_is_ddr3(i915);
--
2.39.2
[CI 06/11] drm/i915/gt: remove mem freq from gt debugfs
It's a bit out of place, and only printed for VLV/CHV. Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 0437fd8217e0..8d08b38874ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -371,7 +371,6 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) vlv_punit_put(i915); drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); - drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); drm_printf(p, "actual GPU freq: %d MHz\n", intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); -- 2.39.2
[CI 07/11] drm/i915: convert fsb_freq and mem_freq to kHz
We'll want to use fsb frequency for deriving GT clock and rawclk
frequencies in the future. Increase the accuracy by converting to
kHz. Do the same for mem freq to be aligned.
Round the frequencies ending in 666 to 667.
v2: Also handle mem_freq in gen5_rps_init() (Ville)
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
drivers/gpu/drm/i915/gt/intel_rps.c| 11 +++---
drivers/gpu/drm/i915/soc/intel_dram.c | 50 +-
3 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index f70ac2f06968..2b7c3d270b17 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -80,13 +80,13 @@ static const struct cxsr_latency
*pnv_get_cxsr_latency(struct drm_i915_private *
if (is_desktop == latency->is_desktop &&
i915->is_ddr3 == latency->is_ddr3 &&
- i915->fsb_freq == latency->fsb_freq &&
- i915->mem_freq == latency->mem_freq)
+ DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) ==
latency->fsb_freq &&
+ DIV_ROUND_CLOSEST(i915->mem_freq, 1000) ==
latency->mem_freq)
return latency;
}
drm_dbg_kms(&i915->drm,
- "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
MHz\n",
+ "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u
kHz\n",
i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 70176be269d3..fa304ea088e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -265,10 +265,10 @@ static const struct cparams {
u16 c;
} cparams[] = {
{ 1, 1333, 301, 28664 },
- { 1, 1066, 294, 24460 },
+ { 1, 1067, 294, 24460 },
{ 1, 800, 294, 25192 },
{ 0, 1333, 276, 27605 },
- { 0, 1066, 276, 27605 },
+ { 0, 1067, 276, 27605 },
{ 0, 800, 231, 23784 },
};
@@ -280,15 +280,16 @@ static void gen5_rps_init(struct intel_rps *rps)
u32 rgvmodectl;
int c_m, i;
- if (i915->fsb_freq <= 3200)
+ if (i915->fsb_freq <= 320)
c_m = 0;
- else if (i915->fsb_freq <= 4800)
+ else if (i915->fsb_freq <= 480)
c_m = 1;
else
c_m = 2;
for (i = 0; i < ARRAY_SIZE(cparams); i++) {
- if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) {
+ if (cparams[i].i == c_m &&
+ cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) {
rps->ips.m = cparams[i].m;
rps->ips.c = cparams[i].c;
break;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 266ed6cfa485..ace9372244a4 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private
*dev_priv)
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
- return 533;
+ return 53;
case CLKCFG_MEM_667:
- return 667;
+ return 67;
case CLKCFG_MEM_800:
- return 800;
+ return 80;
}
return 0;
@@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private
*dev_priv)
ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
case 0xc:
- return 800;
+ return 80;
case 0x10:
- return 1066;
+ return 107;
case 0x14:
- return 1333;
+ return 133;
case 0x18:
- return 1600;
+ return 160;
default:
drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
ddrpll & 0xff);
@@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 2) & 0x7) {
case 3:
- return 2000;
+ return 200;
default:
- return 1600;
+ return 160;
}
}
@@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 6) & 3) {
case 0:
case 1:
- return 800;
+ return 80;
case 2:
- return 1066;
+ return 107;
case 3:
- return 1333;
+ return 133;
}
return 0;
@@ -139,7 +139,7 @@ static void det
[CI 08/11] drm/i915: extend the fsb_freq initialization to more platforms
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.
Default to 1333 MHz for unknown values, similar to i9xx_hrawclk().
v2:
- Add MISSING_CASE() (Ville)
- Default to the same frequency for both branches (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 55 ---
1 file changed, 41 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index ace9372244a4..1b01e5130f79 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,24 +142,51 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
}
-static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
{
u32 fsb;
fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
- switch (fsb) {
- case CLKCFG_FSB_400:
- return 40;
- case CLKCFG_FSB_533:
- return 53;
- case CLKCFG_FSB_667:
- return 67;
- case CLKCFG_FSB_800:
- return 80;
+ if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
+ switch (fsb) {
+ case CLKCFG_FSB_400:
+ return 40;
+ case CLKCFG_FSB_533:
+ return 53;
+ case CLKCFG_FSB_667:
+ return 67;
+ case CLKCFG_FSB_800:
+ return 80;
+ case CLKCFG_FSB_1067:
+ return 107;
+ case CLKCFG_FSB_1333:
+ return 133;
+ default:
+ MISSING_CASE(fsb);
+ return 133;
+ }
+ } else {
+ switch (fsb) {
+ case CLKCFG_FSB_400_ALT:
+ return 40;
+ case CLKCFG_FSB_533:
+ return 53;
+ case CLKCFG_FSB_667:
+ return 67;
+ case CLKCFG_FSB_800:
+ return 80;
+ case CLKCFG_FSB_1067_ALT:
+ return 107;
+ case CLKCFG_FSB_1333_ALT:
+ return 133;
+ case CLKCFG_FSB_1600_ALT:
+ return 160;
+ default:
+ MISSING_CASE(fsb);
+ return 133;
+ }
}
-
- return 0;
}
static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
@@ -193,8 +220,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
{
if (GRAPHICS_VER(i915) == 5)
i915->fsb_freq = ilk_fsb_freq(i915);
- else if (IS_PINEVIEW(i915))
- i915->fsb_freq = pnv_fsb_freq(i915);
+ else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
+ i915->fsb_freq = i9xx_fsb_freq(i915);
if (i915->fsb_freq)
drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
--
2.39.2
[CI 09/11] drm/i915: use i9xx_fsb_freq() for GT clock frequency
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(), with a dependency on intel_pcode_init().
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 3 ++-
drivers/gpu/drm/i915/soc/intel_dram.c | 2 +-
drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 7c9be4fd1c8c..6e63505fe478 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -9,6 +9,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_print.h"
#include "intel_gt_regs.h"
+#include "soc/intel_dram.h"
static u32 read_reference_ts_freq(struct intel_uncore *uncore)
{
@@ -151,7 +152,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore
*uncore)
*
* Testing on actual hardware has shown there is no /16.
*/
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
+ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000;
}
static u32 read_clock_frequency(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 1b01e5130f79..dac39b41fa51 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,7 +142,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq);
}
-static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
{
u32 fsb;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h
b/drivers/gpu/drm/i915/soc/intel_dram.h
index 4ba13c13162c..a10136eda674 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -10,5 +10,6 @@ struct drm_i915_private;
void intel_dram_edram_detect(struct drm_i915_private *i915);
void intel_dram_detect(struct drm_i915_private *i915);
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915);
#endif /* __INTEL_DRAM_H__ */
--
2.39.2
[CI 10/11] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
figure out rawclk_freq where applicable.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
1 file changed, 3 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c5bc49e48c88..b6adcbd9025f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,7 @@
#include
+#include "soc/intel_dram.h"
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
@@ -3539,10 +3540,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
CCK_DISPLAY_REF_CLOCK_CONTROL);
}
-static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
+static int i9xx_hrawclk(struct drm_i915_private *i915)
{
- u32 clkcfg;
-
/*
* hrawclock is 1/4 the FSB frequency
*
@@ -3553,46 +3552,7 @@ static int i9xx_hrawclk(struct drm_i915_private
*dev_priv)
* don't know which registers have that information,
* and all the relevant docs have gone to bit heaven :(
*/
- clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
-
- if (IS_MOBILE(dev_priv)) {
- switch (clkcfg) {
- case CLKCFG_FSB_400:
- return 10;
- case CLKCFG_FSB_533:
- return 13;
- case CLKCFG_FSB_667:
- return 17;
- case CLKCFG_FSB_800:
- return 20;
- case CLKCFG_FSB_1067:
- return 27;
- case CLKCFG_FSB_1333:
- return 33;
- default:
- MISSING_CASE(clkcfg);
- return 13;
- }
- } else {
- switch (clkcfg) {
- case CLKCFG_FSB_400_ALT:
- return 10;
- case CLKCFG_FSB_533:
- return 13;
- case CLKCFG_FSB_667:
- return 17;
- case CLKCFG_FSB_800:
- return 20;
- case CLKCFG_FSB_1067_ALT:
- return 27;
- case CLKCFG_FSB_1333_ALT:
- return 33;
- case CLKCFG_FSB_1600_ALT:
- return 40;
- default:
- return 13;
- }
- }
+ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
}
/**
--
2.39.2
[CI 11/11] drm/i915: move comments about FSB straps to proper place
Move the comment about FSB straps to where the relevant register is
read.
Suggested-by: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +--
drivers/gpu/drm/i915/soc/intel_dram.c | 8
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b6adcbd9025f..16d5550f7e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3542,16 +3542,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
static int i9xx_hrawclk(struct drm_i915_private *i915)
{
- /*
-* hrawclock is 1/4 the FSB frequency
-*
-* Note that this only reads the state of the FSB
-* straps, not the actual FSB frequency. Some BIOSen
-* let you configure each independently. Ideally we'd
-* read out the actual FSB frequency but sadly we
-* don't know which registers have that information,
-* and all the relevant docs have gone to bit heaven :(
-*/
+ /* hrawclock is 1/4 the FSB frequency */
return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
}
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index dac39b41fa51..4aba47bccc63 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -146,6 +146,14 @@ unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
{
u32 fsb;
+ /*
+* Note that this only reads the state of the FSB
+* straps, not the actual FSB frequency. Some BIOSen
+* let you configure each independently. Ideally we'd
+* read out the actual FSB frequency but sadly we
+* don't know which registers have that information,
+* and all the relevant docs have gone to bit heaven :(
+*/
fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK;
if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
--
2.39.2
✓ Fi.CI.BAT: success for drm/i915: mem/fsb/rawclk freq cleanups (rev3)
== Series Details ==
Series: drm/i915: mem/fsb/rawclk freq cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/134145/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14942 -> Patchwork_134145v3
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/index.html
Participating hosts (38 -> 37)
--
Missing(1): fi-snb-2520m
Known issues
Here are the changes found in Patchwork_134145v3 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][1] -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-mtlp-9/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/bat-mtlp-9/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@gt_lrc:
- {bat-twl-1}:[INCOMPLETE][3] ([i915#10886]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-14: [DMESG-FAIL][5] ([i915#9500]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-dg2-14/igt@i915_selftest@l...@workarounds.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/bat-dg2-14/igt@i915_selftest@l...@workarounds.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {bat-mtlp-9}: [DMESG-WARN][7] ([i915#11009]) -> [PASS][8] +1 other
test pass
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- {bat-mtlp-9}: [SKIP][9] ([i915#10580]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/bat-mtlp-9/igt@kms_cursor_leg...@basic-flip-before-cursor-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10886
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
Build changes
-
* Linux: CI_DRM_14942 -> Patchwork_134145v3
CI-20190529: 20190529
CI_DRM_14942: 9e00ec95f823e394044b8d9b5cdadd2c71714d91 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7888: 021538d059575eb9f93d36fea36015cd3f9fca7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_134145v3: 9e00ec95f823e394044b8d9b5cdadd2c71714d91 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134145v3/index.html
✗ Fi.CI.SPARSE: warning for drm/i915: mem/fsb/rawclk freq cleanups (rev3)
== Series Details == Series: drm/i915: mem/fsb/rawclk freq cleanups (rev3) URL : https://patchwork.freedesktop.org/series/134145/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbi
[PATCH v2 0/2] drm/i915: fix MSO vs. joiner issue
This superseeds and includes [1]. BR, Jani. [1] https://lore.kernel.org/r/20240613150424.262567-1-jani.nik...@intel.com Jani Nikula (2): drm/i915/mso: using joiner is not possible with eDP MSO drm/i915/dsc: don't mess up splitter state in joiner or dsc config drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++--- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dp.c | 4 drivers/gpu/drm/i915/display/intel_vdsc.c| 12 +--- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 1 + 5 files changed, 22 insertions(+), 8 deletions(-) -- 2.39.2
[PATCH v2 1/2] drm/i915/mso: using joiner is not possible with eDP MSO
It's not possible to use the joiner at the same time with eDP MSO. When
a panel needs MSO, it's not optional, so MSO trumps joiner.
While just reporting false for intel_dp_has_joiner() should be
sufficient, also skip creation of the joiner force enable debugfs to
better handle this in testing.
Cc: sta...@vger.kernel.org
Cc: Ville Syrjala
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 4
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 91757fed9c6d..5eb31404436c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1546,8 +1546,12 @@ void intel_connector_debugfs_add(struct intel_connector
*connector)
if (DISPLAY_VER(i915) >= 11 &&
(connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector_type == DRM_MODE_CONNECTOR_eDP)) {
- debugfs_create_bool("i915_bigjoiner_force_enable", 0644, root,
- &connector->force_bigjoiner_enable);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+
+ /* eDP MSO is not compatible with joiner */
+ if (!intel_dp->mso_link_count)
+ debugfs_create_bool("i915_bigjoiner_force_enable",
0644, root,
+ &connector->force_bigjoiner_enable);
}
if (connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9a9bb0f5b7fe..ab33c9de393a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp)
struct intel_encoder *encoder = &intel_dig_port->base;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ /* eDP MSO is not compatible with joiner */
+ if (intel_dp->mso_link_count)
+ return false;
+
return DISPLAY_VER(dev_priv) >= 12 ||
(DISPLAY_VER(dev_priv) == 11 &&
encoder->port != PORT_A);
--
2.39.2
[PATCH v2 2/2] drm/i915/dsc: don't mess up splitter state in joiner or dsc config
The driver handles splitter (for MSO) and joiner/dsc configuration in
different places. Avoid messing up the splitter hardware state when
enabling/disabling joiner or dsc. It should not be possible to enable
both joiner and splitter at the same time, but add more clarity to the
register use overall.
Note: We should probably handle splitter for MSO as well as dual-link
DSI in intel_vdsc.c. Also, we have intel_uncompressed_joiner_enable()
but no corresponding disable.
Cc: Ville Syrjala
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++---
drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 1 +
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bb13a3ca8c7c..49509a6599fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2417,9 +2417,8 @@ static void intel_ddi_mso_configure(const struct
intel_crtc_state *crtc_state)
dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
}
- intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
-SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
-OVERLAP_PIXELS_MASK, dss1);
+ /* Only touch the splitter */
+ intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_STATE, dss1);
}
static u8 mtl_get_port_width(u8 lane_count)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b9687b7692b8..a8671d3f1d41 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -766,7 +766,9 @@ void intel_uncompressed_joiner_enable(const struct
intel_crtc_state *crtc_state)
else
dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
- intel_de_write(dev_priv, dss_ctl1_reg(crtc,
crtc_state->cpu_transcoder), dss_ctl1_val);
+ /* Avoid touching the splitter */
+ intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
crtc_state->cpu_transcoder),
+~SPLITTER_STATE, dss_ctl1_val);
}
}
@@ -793,7 +795,9 @@ void intel_dsc_enable(const struct intel_crtc_state
*crtc_state)
if (!intel_crtc_is_joiner_secondary(crtc_state))
dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
}
- intel_de_write(dev_priv, dss_ctl1_reg(crtc,
crtc_state->cpu_transcoder), dss_ctl1_val);
+ /* Avoid touching the splitter */
+ intel_de_rmw(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
+~SPLITTER_STATE, dss_ctl1_val);
intel_de_write(dev_priv, dss_ctl2_reg(crtc,
crtc_state->cpu_transcoder), dss_ctl2_val);
}
@@ -805,7 +809,9 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
/* Disable only if either of them is enabled */
if (old_crtc_state->dsc.compression_enable ||
old_crtc_state->joiner_pipes) {
- intel_de_write(dev_priv, dss_ctl1_reg(crtc,
old_crtc_state->cpu_transcoder), 0);
+ /* Avoid touching the splitter */
+ intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
old_crtc_state->cpu_transcoder),
+~SPLITTER_STATE, 0);
intel_de_write(dev_priv, dss_ctl2_reg(crtc,
old_crtc_state->cpu_transcoder), 0);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index f921ad67b587..3734cd96f55e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -37,6 +37,7 @@
#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
#define SPLITTER_CONFIGURATION_2_SEGMENT
REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
#define SPLITTER_CONFIGURATION_4_SEGMENT
REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define SPLITTER_STATE(SPLITTER_ENABLE |
SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK)
#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21)
#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20)
--
2.39.2
✗ Fi.CI.SPARSE: warning for drm/i915: fix MSO vs. joiner issue
== Series Details == Series: drm/i915: fix MSO vs. joiner issue URL : https://patchwork.freedesktop.org/series/134883/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:147:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:149:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:153:26: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:155:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:173:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:175:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:179:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:181:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:185:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:187:9: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:191:35: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:16: warning: unreplaced symbol 'oldbit' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:194:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:236:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:238:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:243:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:243:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:245:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:245:9: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old' +./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symb
✓ Fi.CI.BAT: success for drm/i915: fix MSO vs. joiner issue
== Series Details ==
Series: drm/i915: fix MSO vs. joiner issue
URL : https://patchwork.freedesktop.org/series/134883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14942 -> Patchwork_134883v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/index.html
Participating hosts (38 -> 42)
--
Additional (6): bat-dg1-7 bat-kbl-2 fi-glk-j4005 fi-cfl-8109u fi-elk-e7500
bat-dg2-11
Missing(2): fi-snb-2520m fi-bsw-n3050
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_134883v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-mtlp-9}: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14942/bat-mtlp-9/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-mtlp-9/igt@i915_module_l...@load.html
Known issues
Here are the changes found in Patchwork_134883v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][3] ([i915#1849])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-kbl-2/igt@fb...@info.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][4] ([i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-glk-j4005: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][7] +39 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-7: NOTRUN -> [SKIP][9] ([i915#4083])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg1-7/igt@gem_m...@basic.html
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#4083])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@gem_m...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-7: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-7: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg1-7/igt@gem_tiled_pread_basic.html
- bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-7: NOTRUN -> [SKIP][15] ([i915#6621])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg1-7/igt@i915_pm_...@basic-api.html
- bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#6621])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg1-7: NOTRUN -> [SKIP][17] ([i915#4212]) +7 other tests skip
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg1-7/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#4212]) +7 other tests skip
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][19] ([i915#5190])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134883v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-l
Re: [PATCH v2 3/8] drm/i915: Don't check for atomic context on PREEMPT_RT
On 2024-06-14 09:32:07 [+0100], Tvrtko Ursulin wrote: > I think this could be okay-ish in principle, but the commit text is not > entirely accurate because there is no direct coupling between the wait > helpers and the uncore lock. They can be used from any atomic context. > > Okay-ish in principle because there is sufficient testing in Intel's CI on > non-PREEMPT_RT kernels to catch any conceptual misuses. You just avoid disabling preemption if you expect to be in atomic context to save a few cycles. It wouldn't hurt to disable it anyway. The only reason you need it is to remain on the same CPU while reading the clock because it is not guaranteed otherwise. Delays > 50ms are detected at build time. > But see also the caller in skl_pcode_request. It is a bit harder to hit > since it is the fallback path. Or gen5_rps_enable which nests under a > different lock. > > Hmm would there be a different helper, or combination of helpers, which > could replace in_atomic() which would do the right thing on both kernels? > Something to tell us we are neither under a spin_lock, nor preempt_disable, > nor interrupts disabled, nor bottom-half. On either stock or PREEMPT_RT. There is nothing that you can use to deduct that you are under a spin-lock. preemptible() works only if you have a preemption counter which is not mandatory. It can affect RCU but not in all configurations. > WARN_ON_ONCE((ATOMIC) && !(!preemptible() || in_hardirq() || > in_serving_softirq()) > > Would this work? Nope. None of this triggers if you acquire a spinlock_t. And I can't think of something that would always be true. So the question is why do you need to know if the context is atomic? The only impact is avoiding disabling preemption. Is it that important to avoid it? If so would cant_migrate() work? It requires CONFIG_DEBUG_ATOMIC_SLEEP=y to do the trick. > Regards, > > Tvrtko Sebastian
Re: [PATCH v2 1/2] drm/i915/mso: using joiner is not possible with eDP MSO
On Fri, Jun 14, 2024 at 01:16:03PM +0300, Jani Nikula wrote:
> It's not possible to use the joiner at the same time with eDP MSO. When
> a panel needs MSO, it's not optional, so MSO trumps joiner.
>
> While just reporting false for intel_dp_has_joiner() should be
> sufficient, also skip creation of the joiner force enable debugfs to
> better handle this in testing.
>
> Cc: sta...@vger.kernel.org
> Cc: Ville Syrjala
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_dp.c | 4
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 91757fed9c6d..5eb31404436c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1546,8 +1546,12 @@ void intel_connector_debugfs_add(struct
> intel_connector *connector)
> if (DISPLAY_VER(i915) >= 11 &&
> (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>connector_type == DRM_MODE_CONNECTOR_eDP)) {
> - debugfs_create_bool("i915_bigjoiner_force_enable", 0644, root,
> - &connector->force_bigjoiner_enable);
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
That won't give you anything on MST. Dunno if there's any point in
trying to do anything here anyway. We don't account for the other
intel_dp_has_joiner() restrictions here either.
> +
> + /* eDP MSO is not compatible with joiner */
> + if (!intel_dp->mso_link_count)
> + debugfs_create_bool("i915_bigjoiner_force_enable",
> 0644, root,
> + &connector->force_bigjoiner_enable);
> }
>
> if (connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9a9bb0f5b7fe..ab33c9de393a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = &intel_dig_port->base;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + /* eDP MSO is not compatible with joiner */
> + if (intel_dp->mso_link_count)
> + return false;
> +
This part looks fine.
> return DISPLAY_VER(dev_priv) >= 12 ||
> (DISPLAY_VER(dev_priv) == 11 &&
>encoder->port != PORT_A);
> --
> 2.39.2
--
Ville Syrjälä
Intel
Re: [PATCH v2 2/2] drm/i915/dsc: don't mess up splitter state in joiner or dsc config
On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
> The driver handles splitter (for MSO) and joiner/dsc configuration in
> different places. Avoid messing up the splitter hardware state when
> enabling/disabling joiner or dsc. It should not be possible to enable
> both joiner and splitter at the same time, but add more clarity to the
> register use overall.
>
> Note: We should probably handle splitter for MSO as well as dual-link
> DSI in intel_vdsc.c. Also, we have intel_uncompressed_joiner_enable()
> but no corresponding disable.
>
> Cc: Ville Syrjala
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
> drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 1 +
> 3 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bb13a3ca8c7c..49509a6599fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2417,9 +2417,8 @@ static void intel_ddi_mso_configure(const struct
> intel_crtc_state *crtc_state)
> dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
> }
>
> - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
> - SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
> - OVERLAP_PIXELS_MASK, dss1);
> + /* Only touch the splitter */
> + intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_STATE, dss1);
> }
>
> static u8 mtl_get_port_width(u8 lane_count)
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b9687b7692b8..a8671d3f1d41 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -766,7 +766,9 @@ void intel_uncompressed_joiner_enable(const struct
> intel_crtc_state *crtc_state)
> else
> dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
>
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> crtc_state->cpu_transcoder), dss_ctl1_val);
> + /* Avoid touching the splitter */
> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
> crtc_state->cpu_transcoder),
> + ~SPLITTER_STATE, dss_ctl1_val);
> }
> }
>
> @@ -793,7 +795,9 @@ void intel_dsc_enable(const struct intel_crtc_state
> *crtc_state)
> if (!intel_crtc_is_joiner_secondary(crtc_state))
> dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
> }
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> crtc_state->cpu_transcoder), dss_ctl1_val);
> + /* Avoid touching the splitter */
> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
> + ~SPLITTER_STATE, dss_ctl1_val);
> intel_de_write(dev_priv, dss_ctl2_reg(crtc,
> crtc_state->cpu_transcoder), dss_ctl2_val);
> }
>
> @@ -805,7 +809,9 @@ void intel_dsc_disable(const struct intel_crtc_state
> *old_crtc_state)
> /* Disable only if either of them is enabled */
> if (old_crtc_state->dsc.compression_enable ||
> old_crtc_state->joiner_pipes) {
> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> old_crtc_state->cpu_transcoder), 0);
> + /* Avoid touching the splitter */
> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
> old_crtc_state->cpu_transcoder),
> + ~SPLITTER_STATE, 0);
> intel_de_write(dev_priv, dss_ctl2_reg(crtc,
> old_crtc_state->cpu_transcoder), 0);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index f921ad67b587..3734cd96f55e 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -37,6 +37,7 @@
> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> #define SPLITTER_CONFIGURATION_2_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> #define SPLITTER_CONFIGURATION_4_SEGMENT
> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> +#define SPLITTER_STATE (SPLITTER_ENABLE |
> SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK)
Not a big fan of this. I'd rather explicicitly list the bits
we actually want to modify in each call site.
Also not a big fan of the rmws. I think in the future we might be
able to adjust some DSC stuff via fastsets, and that means no rmws
because we then want to do it via DSB. But not sure if the DSS
registers specifically would be involved in that, and I guess we
already had some rmws in there so it'll require work anyway. So
no hard objection to using rmw for now.
> #define UNCOMPRESSED_JOINER_PRIMARY (1 << 21)
> #define UNCOMPRESSED_JOINER_SECONDARY (1 << 20)
>
> --
> 2.39.2
--
Ville Syrjälä
Intel
Re: [PATCH v2 3/8] drm/i915: Don't check for atomic context on PREEMPT_RT
On 14/06/2024 12:05, Sebastian Andrzej Siewior wrote: On 2024-06-14 09:32:07 [+0100], Tvrtko Ursulin wrote: I think this could be okay-ish in principle, but the commit text is not entirely accurate because there is no direct coupling between the wait helpers and the uncore lock. They can be used from any atomic context. Okay-ish in principle because there is sufficient testing in Intel's CI on non-PREEMPT_RT kernels to catch any conceptual misuses. You just avoid disabling preemption if you expect to be in atomic context to save a few cycles. It wouldn't hurt to disable it anyway. The only reason you need it is to remain on the same CPU while reading the clock because it is not guaranteed otherwise. Ah no, that is not why. Reason for conditional disabling of preemption is to have an implementation for very short delays which does not run with preemption permanently disabled. So it is disabled only around time tracking. Delays > 50ms are detected at build time. Right, point of that is to ask the contributor if they are sure this is what they want. Catching misuse of the short delay wait helper step one.. But see also the caller in skl_pcode_request. It is a bit harder to hit since it is the fallback path. Or gen5_rps_enable which nests under a different lock. Hmm would there be a different helper, or combination of helpers, which could replace in_atomic() which would do the right thing on both kernels? Something to tell us we are neither under a spin_lock, nor preempt_disable, nor interrupts disabled, nor bottom-half. On either stock or PREEMPT_RT. There is nothing that you can use to deduct that you are under a spin-lock. preemptible() works only if you have a preemption counter which is not mandatory. It can affect RCU but not in all configurations. WARN_ON_ONCE((ATOMIC) && !(!preemptible() || in_hardirq() || in_serving_softirq()) Would this work? Nope. None of this triggers if you acquire a spinlock_t. And I can't think of something that would always be true. Bummer. So the question is why do you need to know if the context is atomic? The only impact is avoiding disabling preemption. Is it that important to avoid it? If so would cant_migrate() work? It requires CONFIG_DEBUG_ATOMIC_SLEEP=y to do the trick. ... catching misuse of atomic wait helpers step 2 - are you calling it from a non-atomic context without the real need. So should use the non-atomic helper instead. When i915 development was very active and with a lot of contributors it was beneficial to catch these things which code review would easily miss. Now that the pace is much, much slower, it is probably not very important. So this patch is acceptable for what I am concerned and: Reviewed-by: Tvrtko Ursulin Actually please also add the PREEMPT_RT angle to the comment above _WAIT_FOR_ATOMIC_CHECK. Sometimes lines change and git blame makes it hard to find the commit text. Regards, Tvrtko Regards, Tvrtko Sebastian
[PATCH 3/6] drm/ttm: Support partial buffer mappings for ttm_bo_vmap()
Add offset and size parameters to ttm_bo_vmap() to allow for partial
mappings of a buffer object. This brings the functionality on par with
ttm_bo_kmap().
Callers pass the byte offset and size within the buffer object and
receive a page-aligned mapping of the buffer object's memory for the
specified area.
Also update all callers of ttm_bo_vmap() for the new parameters. As
before, existing callers map the buffer object's complete memory.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_ttm_helper.c | 2 +-
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
drivers/gpu/drm/loongson/lsdc_gem.c | 2 +-
drivers/gpu/drm/qxl/qxl_object.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 21 +++--
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_vm.c| 2 +-
include/drm/ttm/ttm_bo.h | 4 +++-
8 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c
b/drivers/gpu/drm/drm_gem_ttm_helper.c
index 3734aa2d1c5b5..f26b7c9077a68 100644
--- a/drivers/gpu/drm/drm_gem_ttm_helper.c
+++ b/drivers/gpu/drm/drm_gem_ttm_helper.c
@@ -67,7 +67,7 @@ int drm_gem_ttm_vmap(struct drm_gem_object *gem,
{
struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
- return ttm_bo_vmap(bo, map);
+ return ttm_bo_vmap(bo, 0, gem->size, map);
}
EXPORT_SYMBOL(drm_gem_ttm_vmap);
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
b/drivers/gpu/drm/drm_gem_vram_helper.c
index 6027584406af6..1670f9a459a9d 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -398,7 +398,7 @@ int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo,
struct iosys_map *map)
* no mapping present.
*/
if (iosys_map_is_null(&gbo->map)) {
- ret = ttm_bo_vmap(&gbo->bo, &gbo->map);
+ ret = ttm_bo_vmap(&gbo->bo, 0, gbo->bo.base.size, &gbo->map);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/loongson/lsdc_gem.c
b/drivers/gpu/drm/loongson/lsdc_gem.c
index a720d8f532093..f709960c781b9 100644
--- a/drivers/gpu/drm/loongson/lsdc_gem.c
+++ b/drivers/gpu/drm/loongson/lsdc_gem.c
@@ -77,7 +77,7 @@ static int lsdc_gem_object_vmap(struct drm_gem_object *obj,
struct iosys_map *ma
return ret;
}
- ret = ttm_bo_vmap(tbo, &lbo->map);
+ ret = ttm_bo_vmap(tbo, 0, tbo->base.size, &lbo->map);
if (ret) {
drm_err(obj->dev, "ttm bo vmap failed\n");
lsdc_bo_unpin(lbo);
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 5893e27a7ae50..9f06d5e26a32c 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -164,7 +164,7 @@ int qxl_bo_vmap_locked(struct qxl_bo *bo, struct iosys_map
*map)
goto out;
}
- r = ttm_bo_vmap(&bo->tbo, &bo->map);
+ r = ttm_bo_vmap(&bo->tbo, 0, bo->tbo.base.size, &bo->map);
if (r) {
qxl_bo_unpin_locked(bo);
return r;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index a9df0deff2deb..31f9772f05dac 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -457,17 +457,23 @@ EXPORT_SYMBOL(ttm_bo_kunmap);
* ttm_bo_vmap
*
* @bo: The buffer object.
+ * @offset: Byte offset into the buffer.
+ * @size: Number of bytes to map.
* @map: pointer to a struct iosys_map representing the map.
*
* Sets up a kernel virtual mapping, using ioremap or vmap to the
* data in the buffer object. The parameter @map returns the virtual
* address as struct iosys_map. Unmap the buffer with ttm_bo_vunmap().
+ * The address stored in @map will be aligned to the next lower page
+ * boundaries.
*
* Returns
* -ENOMEM: Out of memory.
* -EINVAL: Invalid range.
*/
-int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map)
+int ttm_bo_vmap(struct ttm_buffer_object *bo,
+ unsigned long offset, unsigned long size,
+ struct iosys_map *map)
{
struct ttm_resource *mem = bo->resource;
int ret;
@@ -483,18 +489,18 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
u16 alloc_flags;
if (mem->bus.addr) {
- vaddr_iomem = (void __iomem *)mem->bus.addr;
+ vaddr_iomem = (u8 __iomem *)mem->bus.addr + offset;
alloc_flags = ttm_bo_map_premapped;
} else if (mem->bus.caching == ttm_write_combined) {
- vaddr_iomem = ioremap_wc(mem->bus.offset,
bo->base.size);
+ vaddr_iomem = ioremap_wc(mem->bus.offset + offset,
size);
alloc_flags = ttm_bo_map_iomap;
#ifdef CONFIG_X86
} else if (mem->bus.caching == ttm_cached) {
- vaddr_iomem
[PATCH 6/6] drm/xe: Replace ttm_bo_kmap() with ttm_bo_vmap()
Use the newer ttm_bo_vmap() instead of ttm_bo_kmap(). The new interface
uses struct iomap_map, which helps with pointer setup and memcpy() ops.
Removes a TODO item and quite a bit of workarounds from the code.
Signed-off-by: Thomas Zimmermann
---
.../compat-i915-headers/gem/i915_gem_object.h | 17 +++---
drivers/gpu/drm/xe/xe_bo.c| 32 ---
drivers/gpu/drm/xe/xe_bo_types.h | 2 --
3 files changed, 10 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
index 777c20ceabab1..25ae56d700431 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h
@@ -34,28 +34,19 @@ static inline bool i915_gem_object_is_userptr(const struct
xe_bo *bo)
static inline int i915_gem_object_read_from_page(struct xe_bo *bo,
u32 ofs, u64 *ptr, u32 size)
{
- struct ttm_bo_kmap_obj map;
- void *src;
- bool is_iomem;
+ struct iosys_map src;
int ret;
ret = xe_bo_lock(bo, true);
if (ret)
return ret;
- ret = ttm_bo_kmap(&bo->ttm, ofs >> PAGE_SHIFT, 1, &map);
+ ret = ttm_bo_vmap(&bo->ttm, ofs, size, &src);
if (ret)
goto out_unlock;
+ iosys_map_memcpy_from(ptr, &src, ofs & ~PAGE_MASK, size);
+ ttm_bo_vunmap(&bo->ttm, &src);
- ofs &= ~PAGE_MASK;
- src = ttm_kmap_obj_virtual(&map, &is_iomem);
- src += ofs;
- if (is_iomem)
- memcpy_fromio(ptr, (void __iomem *)src, size);
- else
- memcpy(ptr, src, size);
-
- ttm_bo_kunmap(&map);
out_unlock:
xe_bo_unlock(bo);
return ret;
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index a98d857ff1e5a..6158e1a959cd4 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1888,10 +1888,6 @@ dma_addr_t xe_bo_addr(struct xe_bo *bo, u64 offset,
size_t page_size)
int xe_bo_vmap(struct xe_bo *bo)
{
- void *virtual;
- bool is_iomem;
- int ret;
-
xe_bo_assert_held(bo);
if (!(bo->flags & XE_BO_FLAG_NEEDS_CPU_ACCESS))
@@ -1900,32 +1896,16 @@ int xe_bo_vmap(struct xe_bo *bo)
if (!iosys_map_is_null(&bo->vmap))
return 0;
- /*
-* We use this more or less deprecated interface for now since
-* ttm_bo_vmap() doesn't offer the optimization of kmapping
-* single page bos, which is done here.
-* TODO: Fix up ttm_bo_vmap to do that, or fix up ttm_bo_kmap
-* to use struct iosys_map.
-*/
- ret = ttm_bo_kmap(&bo->ttm, 0, bo->size >> PAGE_SHIFT, &bo->kmap);
- if (ret)
- return ret;
-
- virtual = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
- if (is_iomem)
- iosys_map_set_vaddr_iomem(&bo->vmap, (void __iomem *)virtual);
- else
- iosys_map_set_vaddr(&bo->vmap, virtual);
-
- return 0;
+ return ttm_bo_vmap(&bo->ttm, 0, bo->size, &bo->vmap);
}
static void __xe_bo_vunmap(struct xe_bo *bo)
{
- if (!iosys_map_is_null(&bo->vmap)) {
- iosys_map_clear(&bo->vmap);
- ttm_bo_kunmap(&bo->kmap);
- }
+ if (iosys_map_is_null(&bo->vmap))
+ return;
+
+ ttm_bo_vunmap(&bo->ttm, &bo->vmap);
+ iosys_map_clear(&bo->vmap);
}
void xe_bo_vunmap(struct xe_bo *bo)
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 86422e113d396..5cba681ba73c2 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -42,8 +42,6 @@ struct xe_bo {
struct drm_mm_node ggtt_node;
/** @vmap: iosys map of this buffer */
struct iosys_map vmap;
- /** @ttm_kmap: TTM bo kmap object for internal use only. Keep off. */
- struct ttm_bo_kmap_obj kmap;
/** @pinned_link: link to present / evicted list of pinned BO */
struct list_head pinned_link;
#ifdef CONFIG_PROC_FS
--
2.45.2
RE: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
On Mon, 10 Jun 2024, "Kandpal, Suraj" wrote:
>> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>>
>> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
>> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
>> > things
>> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
>> > entered
>> > 2) Allow PSR2 deep sleep when DC5 can be entered
>> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
>> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
>> > not happening.
>> >
>> > WA: 16023497226
>> > Signed-off-by: Suraj Kandpal
>> > ---
>> > drivers/gpu/drm/i915/display/intel_psr.c | 75
>> > +++-
>> > 1 file changed, 73 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> > b/drivers/gpu/drm/i915/display/intel_psr.c
>> > index 6fc88f6c6b26..b22745c019df 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> > @@ -811,12 +811,81 @@ static u8 psr_compute_idle_frames(struct
>> intel_dp *intel_dp)
>> >return idle_frames;
>> > }
>> >
>> > +static bool intel_psr_check_delayed_vblank_limit(struct drm_i915_private
>> *i915,
>> > + enum transcoder
>> cpu_transcoder) {
>> > + return intel_de_read(i915,
>> > +TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)) >= 6;
>>
> Hi Jani,
> Thanks for the reviews
>
>> Please don't use the hardware to preserve the state for you. It will get
>> really
>> complicated to maintain.
>>
>
> Yes wanted to calculate the delayed vblank using the following way
> Adjusted_mode->vblank_start - adjusted_mode->vblank_end
> But I'll need crtc_state for that and I don't see a way of deriving it
> Specially when this function is called from intel_psr_work
> One way could be to have this wa check function be called from
> Intel_psr_enable_locked and save the corresponding Booleans in
> Intel_psr or make in drm_i915_private
> structure and access that when intel_psr_activate is called from
> Intel_psr_resume and intel_psr_work.
> Do you think that could be feasible ?
You'll be able to figure out a lot of cases up front at compute config
time, and disable PSR beforehand.
You'll know LNL_PKG_C_LATENCY (we seem to always configure it). You'll
know TRANS_SET_CONTEXT_LATENCY. You'll know whether all transcoders have
PSR enabled.
I think you'll need to split the conditions, and disable PSR as early as
possible when it should not be enabled. Then at actual enabling time,
you'll know the conditions that already have to hold, and you can check
fewer things.
This workaround is a bummer because it's permanent. It also means we
need to do this properly. Can't just poke at random stuff, because it'll
be painful forever.
BR,
Jani.
>
>> > +}
>> > +
>> > +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
>> > +*i915) {
>> > + return intel_de_read(i915, LNL_PKG_C_LATENCY) == U32_MAX;
>>
>> Ditto.
>>
>
> Similar question as above only place that I can manage a state to see if it
> is configured or not
> would be in drm_i915_private.
>
>> > +}
>> > +
>> > +static bool intel_psr_is_dc5_entry_possible(struct drm_i915_private
>> > +*i915) {
>> > + struct intel_crtc *intel_crtc;
>> > + bool ret = true;
>> > +
>> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
>> > + struct intel_encoder *encoder;
>> > + struct drm_crtc *crtc = &intel_crtc->base;
>> > + enum pipe pipe = intel_crtc->pipe;
>> > +
>> > + if (!crtc->active)
>> > + continue;
>> > +
>> > + if (!(i915->display.irq.de_irq_mask[pipe] &
>> GEN8_PIPE_VBLANK))
>>
>> You have no business looking directly at that. It's for display irq code
>> *only*.
>>
>
> Is there another way I can ensure if the vblank interrupt for the particular
> pipe is disabled?
>
>> > + ret = false;
>> > +
>> > + for_each_encoder_on_crtc(&i915->drm, crtc, encoder) {
>> > + struct intel_dp *intel_dp = enc_to_intel_dp(_encoder);
>> > + struct intel_psr *psr = &intel_dp->psr;
>> > +
>> > + if (!psr->enabled)
>> > + ret = false;
>> > + }
>> > + }
>> > +
>> > + return ret;
>> > +}
>> > +
>> > +static bool wa_16023497226_check(struct intel_dp *intel_dp, bool
>> > +psr1) {
>> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> > + enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>> > +
>> > + if (DISPLAY_VER(i915) != 20)
>> > + return true;
>> > +
>> > + if (is_dpkg_c_configured(i915)) {
>> > + if (psr1 &&
>> > + (intel_psr_check_delayed_vblank_limit(i915,
>> cpu_transcoder) ||
>> > + intel_psr_is_dc5_entry_possible(i915)))
>> > + return true;
>> > + else if (!psr1 && is_dc5_entry_possible(i915))
>> > + return true;
>> > +
[PATCH 4/6] drm/ttm: Support kmap for single-page mappings in ttm_bo_vmap()
In ttm_bo_vmap(), set up single-page mappings with kmap() in certain
cases. The feature is already present in ttm_bo_kmap().
This functionality is require by DRM's xe driver, which claims that
using kmap() is an optimization over vmap(). [1] Reading the commit
at [2] indicates otherwise. It is not possible to use kmap_local_page()
and kunmap_local_page(), as TTM cannot guarantee the requirements for
ordering these calls. [3]
Signed-off-by: Thomas Zimmermann
Link:
https://elixir.bootlin.com/linux/v6.9/source/drivers/gpu/drm/xe/xe_bo.c#L1870 #
1
Link:
https://lore.kernel.org/all/20220813220034.806698-1-ira.we...@intel.com/T/#u # 2
Link: https://elixir.bootlin.com/linux/v6.9/source/include/linux/highmem.h#L70
# 3
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 33 ++-
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 31f9772f05dac..c06cfccace39d 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -516,6 +516,8 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo,
.no_wait_gpu = false
};
struct ttm_tt *ttm = bo->ttm;
+ struct ttm_resource_manager *man =
+ ttm_manager_type(bo->bdev, bo->resource->mem_type);
unsigned long start_page = offset >> PAGE_SHIFT;
unsigned long aligned_size = size + (offset - (start_page <<
PAGE_SHIFT));
unsigned long num_pages = DIV_ROUND_UP(aligned_size, PAGE_SIZE);
@@ -527,15 +529,25 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo,
if (ret)
return ret;
- /*
-* We need to use vmap to get the desired page protection
-* or to make the buffer object look contiguous.
-*/
- prot = ttm_io_prot(bo, mem, PAGE_KERNEL);
- vaddr = vmap(ttm->pages + start_page, num_pages, 0, prot);
- if (!vaddr)
- return -ENOMEM;
- alloc_flags = ttm_bo_map_vmap;
+ if (num_pages == 1 && ttm->caching == ttm_cached &&
+ !(man->use_tt && (ttm->page_flags &
TTM_TT_FLAG_DECRYPTED))) {
+ /*
+* We're mapping a single page, and the desired
+* page protection is consistent with the bo.
+*/
+ vaddr = kmap(ttm->pages[start_page]);
+ alloc_flags = ttm_bo_map_kmap;
+ } else {
+ /*
+* We need to use vmap to get the desired page
protection
+* or to make the buffer object look contiguous.
+*/
+ prot = ttm_io_prot(bo, mem, PAGE_KERNEL);
+ vaddr = vmap(ttm->pages + start_page, num_pages, 0,
prot);
+ if (!vaddr)
+ return -ENOMEM;
+ alloc_flags = ttm_bo_map_vmap;
+ }
iosys_map_set_vaddr(map, vaddr);
map->alloc_flags = alloc_flags;
@@ -567,6 +579,9 @@ void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
case ttm_bo_map_vmap:
vunmap(map->vaddr);
break;
+ case ttm_bo_map_kmap:
+ kunmap(kmap_to_page(map->vaddr));
+ break;
case ttm_bo_map_premapped:
break;
default:
--
2.45.2
[PATCH 5/6] drm/xe: Remove vunmap calls object-freeing code
Move calls to unmap the buffer-object memory from the object-release
code in xe_gem_object_free() to the caller of the release.
Doing an unmap for a BO requires holding the reservation lock, which
is not allowed while releasing a GEM object. Without the reservation
lock, TTM can concurrently evict the buffer object that is to be
released; making the mapping invalid.
Pushing the unmap calls, namely xe_bo_vunmap(), releases the mapped
pages before the buffer object.
While at it, add a warning about buffer mappings to the GEM-object
release code. The warning message and unmap code can be removed after
the driver has been audited to not release mapped buffer objects.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/xe/display/intel_fb_bo.c | 12 +++-
drivers/gpu/drm/xe/xe_bo.c | 14 +-
drivers/gpu/drm/xe/xe_bo.h | 23 ---
drivers/gpu/drm/xe/xe_lrc.c | 1 +
4 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c
b/drivers/gpu/drm/xe/display/intel_fb_bo.c
index f835492f73fb4..cf2720dbdd51f 100644
--- a/drivers/gpu/drm/xe/display/intel_fb_bo.c
+++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c
@@ -12,12 +12,14 @@
void intel_fb_bo_framebuffer_fini(struct xe_bo *bo)
{
- if (bo->flags & XE_BO_FLAG_PINNED) {
- /* Unpin our kernel fb first */
- xe_bo_lock(bo, false);
+ xe_bo_lock(bo, false);
+ xe_bo_vunmap(bo);
+
+ /* Unpin our kernel fb first */
+ if (bo->flags & XE_BO_FLAG_PINNED)
xe_bo_unpin(bo);
- xe_bo_unlock(bo);
- }
+
+ xe_bo_unlock(bo);
xe_bo_put(bo);
}
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 2bae01ce4e5b9..a98d857ff1e5a 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1093,6 +1093,19 @@ static void xe_ttm_bo_destroy(struct ttm_buffer_object
*ttm_bo)
static void xe_gem_object_free(struct drm_gem_object *obj)
{
+ struct xe_bo *bo = gem_to_xe_bo(obj);
+
+ /*
+* Trying to free the object with a mapping in place. Resolve
+* this warning by calling xe_bo_vunmap() in the code that leads
+* ot this object release.
+*
+* TODO: Audit the driver to not release mapped buffer objects and
+* then remove this block.
+*/
+ if (drm_WARN_ON(obj->dev, !iosys_map_is_null(&bo->vmap)))
+ __xe_bo_vunmap(bo);
+
/* Our BO reference counting scheme works as follows:
*
* The gem object kref is typically used throughout the driver,
@@ -1106,7 +1119,6 @@ static void xe_gem_object_free(struct drm_gem_object *obj)
* driver ttm callbacks is allowed to use the ttm_buffer_object
* refcount directly if needed.
*/
- __xe_bo_vunmap(gem_to_xe_bo(obj));
ttm_bo_put(container_of(obj, struct ttm_buffer_object, base));
}
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 6de894c728f54..5d1f8f13fbf13 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -170,17 +170,6 @@ static inline bool xe_bo_is_pinned(struct xe_bo *bo)
return bo->ttm.pin_count;
}
-static inline void xe_bo_unpin_map_no_vm(struct xe_bo *bo)
-{
- if (likely(bo)) {
- xe_bo_lock(bo, false);
- xe_bo_unpin(bo);
- xe_bo_unlock(bo);
-
- xe_bo_put(bo);
- }
-}
-
bool xe_bo_is_xe_bo(struct ttm_buffer_object *bo);
dma_addr_t __xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size);
dma_addr_t xe_bo_addr(struct xe_bo *bo, u64 offset, size_t page_size);
@@ -202,6 +191,18 @@ xe_bo_ggtt_addr(struct xe_bo *bo)
int xe_bo_vmap(struct xe_bo *bo);
void xe_bo_vunmap(struct xe_bo *bo);
+static inline void xe_bo_unpin_map_no_vm(struct xe_bo *bo)
+{
+ if (likely(bo)) {
+ xe_bo_lock(bo, false);
+ xe_bo_vunmap(bo);
+ xe_bo_unpin(bo);
+ xe_bo_unlock(bo);
+
+ xe_bo_put(bo);
+ }
+}
+
bool mem_type_is_vram(u32 mem_type);
bool xe_bo_is_vram(struct xe_bo *bo);
bool xe_bo_is_stolen(struct xe_bo *bo);
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 3a68fe6d592ed..8a52797fe79bb 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -812,6 +812,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
{
xe_hw_fence_ctx_finish(&lrc->fence_ctx);
xe_bo_lock(lrc->bo, false);
+ xe_bo_vunmap(lrc->bo);
xe_bo_unpin(lrc->bo);
xe_bo_unlock(lrc->bo);
xe_bo_put(lrc->bo);
--
2.45.2
[PATCH 1/6] iosys-map: Add allocator flags
Add the public field alloc_flags to struct iosys_map. It allows for
the allocator of the mapping to store additional flags, such details
about the internal alloctor operations. This will be helpful with
DRM's TTM memory manager, which supports various types of memory in
it's vmap functions.
The new field fills existing padding bytes in struct iosys_map, so
instances of the type do not grow in size.
Signed-off-by: Thomas Zimmermann
---
include/linux/iosys-map.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/linux/iosys-map.h b/include/linux/iosys-map.h
index 4696abfd311cc..f3b351094bca0 100644
--- a/include/linux/iosys-map.h
+++ b/include/linux/iosys-map.h
@@ -97,6 +97,11 @@
*
* iosys_map_memcpy_to(&map, src, len);
* iosys_map_incr(&map, len); // go to first byte after the memcpy
+ *
+ * The only public field in :c:type:`struct iosys_map ` is
+ * alloc_flags. It allows allocators to store additional information about the
+ * stored memory. Helpers will initialize or clear it to zero, but the values
+ * are only used by the allocator.
*/
/**
@@ -105,6 +110,7 @@
* @vaddr: The buffer's address if in system memory
* @is_iomem: True if the buffer is located in I/O memory, or false
* otherwise.
+ * @alloc_flagsAllocator private flags
*/
struct iosys_map {
union {
@@ -112,6 +118,7 @@ struct iosys_map {
void *vaddr;
};
bool is_iomem;
+ u16 alloc_flags;
};
/**
@@ -122,6 +129,7 @@ struct iosys_map {
{ \
.vaddr = (vaddr_), \
.is_iomem = false, \
+ .alloc_flags = 0, \
}
/**
@@ -132,6 +140,7 @@ struct iosys_map {
{ \
.vaddr_iomem = (vaddr_iomem_), \
.is_iomem = true, \
+ .alloc_flags = 0, \
}
/**
@@ -260,7 +269,8 @@ static inline bool iosys_map_is_set(const struct iosys_map
*map)
*
* Clears all fields to zero, including struct iosys_map.is_iomem, so
* mapping structures that were set to point to I/O memory are reset for
- * system memory. Pointers are cleared to NULL. This is the default.
+ * system memory. Pointers are cleared to NULL. The allocator flags in
+ * struct iosys_map.alloc_flags are cleared to zero.
*/
static inline void iosys_map_clear(struct iosys_map *map)
{
@@ -270,6 +280,7 @@ static inline void iosys_map_clear(struct iosys_map *map)
} else {
map->vaddr = NULL;
}
+ map->alloc_flags = 0;
}
/**
--
2.45.2
[PATCH 2/6] drm/ttm: Store the bo_kmap_type in struct iosys_map
For each instances of struct iosys_map set up by ttm_bo_vmap(), store
the type of allocation in the instance. Use this information to unmap
the memory in ttm_bo_vunmap(). This change simplifies the unmap code
and puts the complicated logic entirely into the map code.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 46 +--
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 0b3f4267130c4..a9df0deff2deb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -36,6 +36,7 @@
#include
#include
+#include
struct ttm_transfer_obj {
struct ttm_buffer_object base;
@@ -479,24 +480,29 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
if (mem->bus.is_iomem) {
void __iomem *vaddr_iomem;
+ u16 alloc_flags;
- if (mem->bus.addr)
+ if (mem->bus.addr) {
vaddr_iomem = (void __iomem *)mem->bus.addr;
- else if (mem->bus.caching == ttm_write_combined)
- vaddr_iomem = ioremap_wc(mem->bus.offset,
-bo->base.size);
+ alloc_flags = ttm_bo_map_premapped;
+ } else if (mem->bus.caching == ttm_write_combined) {
+ vaddr_iomem = ioremap_wc(mem->bus.offset,
bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
#ifdef CONFIG_X86
- else if (mem->bus.caching == ttm_cached)
- vaddr_iomem = ioremap_cache(mem->bus.offset,
- bo->base.size);
+ } else if (mem->bus.caching == ttm_cached) {
+ vaddr_iomem = ioremap_cache(mem->bus.offset,
bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
#endif
- else
+ } else {
vaddr_iomem = ioremap(mem->bus.offset, bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
+ }
if (!vaddr_iomem)
return -ENOMEM;
iosys_map_set_vaddr_iomem(map, vaddr_iomem);
+ map->alloc_flags = alloc_flags;
} else {
struct ttm_operation_ctx ctx = {
@@ -506,6 +512,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
struct ttm_tt *ttm = bo->ttm;
pgprot_t prot;
void *vaddr;
+ u16 alloc_flags;
ret = ttm_tt_populate(bo->bdev, ttm, &ctx);
if (ret)
@@ -519,8 +526,10 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
vaddr = vmap(ttm->pages, ttm->num_pages, 0, prot);
if (!vaddr)
return -ENOMEM;
+ alloc_flags = ttm_bo_map_vmap;
iosys_map_set_vaddr(map, vaddr);
+ map->alloc_flags = alloc_flags;
}
return 0;
@@ -537,20 +546,27 @@ EXPORT_SYMBOL(ttm_bo_vmap);
*/
void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map)
{
- struct ttm_resource *mem = bo->resource;
-
dma_resv_assert_held(bo->base.resv);
if (iosys_map_is_null(map))
return;
- if (!map->is_iomem)
- vunmap(map->vaddr);
- else if (!mem->bus.addr)
+ switch (map->alloc_flags) {
+ case ttm_bo_map_iomap:
iounmap(map->vaddr_iomem);
- iosys_map_clear(map);
-
+ break;
+ case ttm_bo_map_vmap:
+ vunmap(map->vaddr);
+ break;
+ case ttm_bo_map_premapped:
+ break;
+ default:
+ drm_err(bo->base.dev, "Unsupported alloc_flags 0x%x\n",
map->alloc_flags);
+ return;
+ }
ttm_mem_io_free(bo->bdev, bo->resource);
+
+ iosys_map_clear(map);
}
EXPORT_SYMBOL(ttm_bo_vunmap);
--
2.45.2
[PATCH 0/6] drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
Add ttm_bo_kmap()'s features to ttm_bo_vmap() and convert xe to use the latter helper. ttm_bo_vmap() returns mappings in an instance of struct iosys_map, which simplifies driver code in several places. Patches 1 and 2 allow ttm_bo_vmap() to store the method of allocation in the iosys_map instance. This simplifies the unmap and driver code. Patch 3 adds support for partial mappings to ttm_bo_vmap(). That's another feature of ttm_bo_kmap(). It is now possible to map only a subrange of a buffer object's memory buffer. This requires a trivial change to existing callers, so that they still map the full buffer range. Patch 4 adds support for kmap()-based mappings in certain cases to ttm_bo_vmap(). Patches 5 and 6 convert xe to ttm_bo_vmap(). ttm_bo_vmap() tests if the caller holds the object's reservation lock; and therefore cannot be called while relasing the buffer object. Patch 5 resolves this problem in xe. Patch 6 then replaces ttm_bo_kmap() with ttm_bo_vmap() and also updates the callers to use struct iosys_map everywhere. Tested on Intel ARC hardware. Future direction: DRM's TTM-based drivers use a mixture of ttm_bo_kmap() and ttm_bo_vmap(). After merging these updates for ttm_bo_vmap(), the other drivers can be converted and ttm_bo_kmap() can be removed. Thomas Zimmermann (6): iosys-map: Add allocator flags drm/ttm: Store the bo_kmap_type in struct iosys_map drm/ttm: Support partial buffer mappings for ttm_bo_vmap() drm/ttm: Support kmap for single-page mappings in ttm_bo_vmap() drm/xe: Remove vunmap calls object-freeing code drm/xe: Replace ttm_bo_kmap() with ttm_bo_vmap() drivers/gpu/drm/drm_gem_ttm_helper.c | 2 +- drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- drivers/gpu/drm/loongson/lsdc_gem.c | 2 +- drivers/gpu/drm/qxl/qxl_object.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 94 +-- .../compat-i915-headers/gem/i915_gem_object.h | 17 +--- drivers/gpu/drm/xe/display/intel_fb_bo.c | 12 ++- drivers/gpu/drm/xe/xe_bo.c| 46 - drivers/gpu/drm/xe/xe_bo.h| 23 ++--- drivers/gpu/drm/xe/xe_bo_types.h | 2 - drivers/gpu/drm/xe/xe_lrc.c | 3 +- drivers/gpu/drm/xe/xe_vm.c| 2 +- include/drm/ttm/ttm_bo.h | 4 +- include/linux/iosys-map.h | 13 ++- 14 files changed, 131 insertions(+), 93 deletions(-) -- 2.45.2
Re: [PATCH v2 1/2] drm/i915/mso: using joiner is not possible with eDP MSO
On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> On Fri, Jun 14, 2024 at 01:16:03PM +0300, Jani Nikula wrote:
>> It's not possible to use the joiner at the same time with eDP MSO. When
>> a panel needs MSO, it's not optional, so MSO trumps joiner.
>>
>> While just reporting false for intel_dp_has_joiner() should be
>> sufficient, also skip creation of the joiner force enable debugfs to
>> better handle this in testing.
>>
>> Cc: sta...@vger.kernel.org
>> Cc: Ville Syrjala
>> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8 ++--
>> drivers/gpu/drm/i915/display/intel_dp.c | 4
>> 2 files changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 91757fed9c6d..5eb31404436c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -1546,8 +1546,12 @@ void intel_connector_debugfs_add(struct
>> intel_connector *connector)
>> if (DISPLAY_VER(i915) >= 11 &&
>> (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>> connector_type == DRM_MODE_CONNECTOR_eDP)) {
>> -debugfs_create_bool("i915_bigjoiner_force_enable", 0644, root,
>> -&connector->force_bigjoiner_enable);
>> +struct intel_dp *intel_dp = intel_attached_dp(connector);
>
> That won't give you anything on MST.
Gah!
> Dunno if there's any point in
> trying to do anything here anyway. We don't account for the other
> intel_dp_has_joiner() restrictions here either.
The only point would be skipping a bunch of IGT tests. With the debugfs
in place, kms_big_joiner thinks it enables joiner, and runs extra joiner
tests for nothing.
Thoughts? I guess the simplest fix for stable could be just the last
hunk here.
BR,
Jani.
>
>> +
>> +/* eDP MSO is not compatible with joiner */
>> +if (!intel_dp->mso_link_count)
>> +debugfs_create_bool("i915_bigjoiner_force_enable",
>> 0644, root,
>> +&connector->force_bigjoiner_enable);
>> }
>>
>> if (connector_type == DRM_MODE_CONNECTOR_DSI ||
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 9a9bb0f5b7fe..ab33c9de393a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp)
>> struct intel_encoder *encoder = &intel_dig_port->base;
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> +/* eDP MSO is not compatible with joiner */
>> +if (intel_dp->mso_link_count)
>> +return false;
>> +
>
> This part looks fine.
>
>> return DISPLAY_VER(dev_priv) >= 12 ||
>> (DISPLAY_VER(dev_priv) == 11 &&
>> encoder->port != PORT_A);
>> --
>> 2.39.2
--
Jani Nikula, Intel
Re: [PATCH v2 2/2] drm/i915/dsc: don't mess up splitter state in joiner or dsc config
On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
>> The driver handles splitter (for MSO) and joiner/dsc configuration in
>> different places. Avoid messing up the splitter hardware state when
>> enabling/disabling joiner or dsc. It should not be possible to enable
>> both joiner and splitter at the same time, but add more clarity to the
>> register use overall.
>>
>> Note: We should probably handle splitter for MSO as well as dual-link
>> DSI in intel_vdsc.c. Also, we have intel_uncompressed_joiner_enable()
>> but no corresponding disable.
>>
>> Cc: Ville Syrjala
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
>> drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 1 +
>> 3 files changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index bb13a3ca8c7c..49509a6599fe 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2417,9 +2417,8 @@ static void intel_ddi_mso_configure(const struct
>> intel_crtc_state *crtc_state)
>> dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
>> }
>>
>> -intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
>> - SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
>> - OVERLAP_PIXELS_MASK, dss1);
>> +/* Only touch the splitter */
>> +intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_STATE, dss1);
>> }
>>
>> static u8 mtl_get_port_width(u8 lane_count)
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index b9687b7692b8..a8671d3f1d41 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -766,7 +766,9 @@ void intel_uncompressed_joiner_enable(const struct
>> intel_crtc_state *crtc_state)
>> else
>> dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
>>
>> -intel_de_write(dev_priv, dss_ctl1_reg(crtc,
>> crtc_state->cpu_transcoder), dss_ctl1_val);
>> +/* Avoid touching the splitter */
>> +intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
>> crtc_state->cpu_transcoder),
>> + ~SPLITTER_STATE, dss_ctl1_val);
>> }
>> }
>>
>> @@ -793,7 +795,9 @@ void intel_dsc_enable(const struct intel_crtc_state
>> *crtc_state)
>> if (!intel_crtc_is_joiner_secondary(crtc_state))
>> dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
>> }
>> -intel_de_write(dev_priv, dss_ctl1_reg(crtc,
>> crtc_state->cpu_transcoder), dss_ctl1_val);
>> +/* Avoid touching the splitter */
>> +intel_de_rmw(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
>> + ~SPLITTER_STATE, dss_ctl1_val);
>> intel_de_write(dev_priv, dss_ctl2_reg(crtc,
>> crtc_state->cpu_transcoder), dss_ctl2_val);
>> }
>>
>> @@ -805,7 +809,9 @@ void intel_dsc_disable(const struct intel_crtc_state
>> *old_crtc_state)
>> /* Disable only if either of them is enabled */
>> if (old_crtc_state->dsc.compression_enable ||
>> old_crtc_state->joiner_pipes) {
>> -intel_de_write(dev_priv, dss_ctl1_reg(crtc,
>> old_crtc_state->cpu_transcoder), 0);
>> +/* Avoid touching the splitter */
>> +intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
>> old_crtc_state->cpu_transcoder),
>> + ~SPLITTER_STATE, 0);
>> intel_de_write(dev_priv, dss_ctl2_reg(crtc,
>> old_crtc_state->cpu_transcoder), 0);
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> index f921ad67b587..3734cd96f55e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> @@ -37,6 +37,7 @@
>> #define SPLITTER_CONFIGURATION_MASKREG_GENMASK(26, 25)
>> #define SPLITTER_CONFIGURATION_2_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> #define SPLITTER_CONFIGURATION_4_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> +#define SPLITTER_STATE (SPLITTER_ENABLE |
>> SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK)
>
> Not a big fan of this. I'd rather explicicitly list the bits
> we actually want to modify in each call site.
>
> Also not a big fan of the rmws. I think in the future we might be
> able to adjust some DSC stuff via fastsets, and that means no rmws
> because we then want to do it via DSB. But not sure if the DSS
> registers specifically would be involved in that, and I guess we
> already had some rmws in there so it'll require work anyway. So
> no hard objection to using rmw for now.
I'm definitely not a fan of the rmws myself. It'
✗ Fi.CI.SPARSE: warning for drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Re: [PATCH v2] drm/i915/display: Update calculation to avoid overflow
On Fri, Jun 14, 2024 at 10:12:13AM GMT, Mitul Golani wrote:
Update calculation to avoid overflow.
-v2:
Remove extra line between cc and signed-off.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Reviewed-by: Ankit Nautiyal
Acked-by: Lucas De Marchi
Lucas De Marchi
✗ Fi.CI.CHECKPATCH: warning for drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : warning
== Summary ==
Error: dim checkpatch failed
9e6b478225b7 iosys-map: Add allocator flags
77686d1beaaf drm/ttm: Store the bo_kmap_type in struct iosys_map
f6c08785dc7f drm/ttm: Support partial buffer mappings for ttm_bo_vmap()
a6e718455990 drm/ttm: Support kmap for single-page mappings in ttm_bo_vmap()
-:53: WARNING:DEPRECATED_API: Deprecated use of 'kmap', prefer
'kmap_local_page' instead
#53: FILE: drivers/gpu/drm/ttm/ttm_bo_util.c:538:
+ vaddr = kmap(ttm->pages[start_page]);
-:74: WARNING:DEPRECATED_API: Deprecated use of 'kunmap', prefer 'kunmap_local'
instead
#74: FILE: drivers/gpu/drm/ttm/ttm_bo_util.c:583:
+ kunmap(kmap_to_page(map->vaddr));
total: 0 errors, 2 warnings, 0 checks, 51 lines checked
0bc209bee997 drm/xe: Remove vunmap calls object-freeing code
647ef007ceb6 drm/xe: Replace ttm_bo_kmap() with ttm_bo_vmap()
Re: [PATCH 2/6] drm/ttm: Store the bo_kmap_type in struct iosys_map
Am 14.06.24 um 15:21 schrieb Thomas Zimmermann:
For each instances of struct iosys_map set up by ttm_bo_vmap(), store
the type of allocation in the instance. Use this information to unmap
the memory in ttm_bo_vunmap(). This change simplifies the unmap code
and puts the complicated logic entirely into the map code.
I'm not sure that's a good idea.
The mapping information should already be available in the resource and
storing it in the iosys_map structures duplicates that information.
So we might run into the issue that the resource has changed and so we
need a different approach now, but the iosys_map will say that we should
unmap things for example.
Regards,
Christian.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 46 +--
1 file changed, 31 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 0b3f4267130c4..a9df0deff2deb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -36,6 +36,7 @@
#include
#include
+#include
struct ttm_transfer_obj {
struct ttm_buffer_object base;
@@ -479,24 +480,29 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
if (mem->bus.is_iomem) {
void __iomem *vaddr_iomem;
+ u16 alloc_flags;
- if (mem->bus.addr)
+ if (mem->bus.addr) {
vaddr_iomem = (void __iomem *)mem->bus.addr;
- else if (mem->bus.caching == ttm_write_combined)
- vaddr_iomem = ioremap_wc(mem->bus.offset,
-bo->base.size);
+ alloc_flags = ttm_bo_map_premapped;
+ } else if (mem->bus.caching == ttm_write_combined) {
+ vaddr_iomem = ioremap_wc(mem->bus.offset,
bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
#ifdef CONFIG_X86
- else if (mem->bus.caching == ttm_cached)
- vaddr_iomem = ioremap_cache(mem->bus.offset,
- bo->base.size);
+ } else if (mem->bus.caching == ttm_cached) {
+ vaddr_iomem = ioremap_cache(mem->bus.offset,
bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
#endif
- else
+ } else {
vaddr_iomem = ioremap(mem->bus.offset, bo->base.size);
+ alloc_flags = ttm_bo_map_iomap;
+ }
if (!vaddr_iomem)
return -ENOMEM;
iosys_map_set_vaddr_iomem(map, vaddr_iomem);
+ map->alloc_flags = alloc_flags;
} else {
struct ttm_operation_ctx ctx = {
@@ -506,6 +512,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
struct ttm_tt *ttm = bo->ttm;
pgprot_t prot;
void *vaddr;
+ u16 alloc_flags;
ret = ttm_tt_populate(bo->bdev, ttm, &ctx);
if (ret)
@@ -519,8 +526,10 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
vaddr = vmap(ttm->pages, ttm->num_pages, 0, prot);
if (!vaddr)
return -ENOMEM;
+ alloc_flags = ttm_bo_map_vmap;
iosys_map_set_vaddr(map, vaddr);
+ map->alloc_flags = alloc_flags;
}
return 0;
@@ -537,20 +546,27 @@ EXPORT_SYMBOL(ttm_bo_vmap);
*/
void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map)
{
- struct ttm_resource *mem = bo->resource;
-
dma_resv_assert_held(bo->base.resv);
if (iosys_map_is_null(map))
return;
- if (!map->is_iomem)
- vunmap(map->vaddr);
- else if (!mem->bus.addr)
+ switch (map->alloc_flags) {
+ case ttm_bo_map_iomap:
iounmap(map->vaddr_iomem);
- iosys_map_clear(map);
-
+ break;
+ case ttm_bo_map_vmap:
+ vunmap(map->vaddr);
+ break;
+ case ttm_bo_map_premapped:
+ break;
+ default:
+ drm_err(bo->base.dev, "Unsupported alloc_flags 0x%x\n",
map->alloc_flags);
+ return;
+ }
ttm_mem_io_free(bo->bdev, bo->resource);
+
+ iosys_map_clear(map);
}
EXPORT_SYMBOL(ttm_bo_vunmap);
✓ Fi.CI.BAT: success for drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
== Series Details ==
Series: drm/{ttm,xe}: Improve ttm_bo_vmap() and update xe
URL : https://patchwork.freedesktop.org/series/134891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134891v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/index.html
Participating hosts (43 -> 41)
--
Additional (1): fi-kbl-8809g
Missing(3): fi-cfl-8109u fi-snb-2520m bat-mtlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_134891v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@guc:
- {bat-arlh-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-arlh-2/igt@i915_selftest@l...@guc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/bat-arlh-2/igt@i915_selftest@l...@guc.html
Known issues
Here are the changes found in Patchwork_134891v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live@gt_mocs:
- bat-adlm-1: [PASS][5] -> [INCOMPLETE][6] ([i915#9413])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html
* igt@kms_dsc@dsc-basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] +30 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html
Possible fixes
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-8:
- {bat-mtlp-9}: [DMESG-FAIL][8] ([i915#11009]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-8.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-c-dp-8.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-8:
- {bat-mtlp-9}: [FAIL][10] ([i915#10979]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-8.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-8.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#11060]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11060
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-
* Linux: CI_DRM_14943 -> Patchwork_134891v1
CI-20190529: 20190529
CI_DRM_14943: 00e9498b453447a5afe527bd0e174587b12f66d2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7888: 021538d059575eb9f93d36fea36015cd3f9fca7d @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_134891v1: 00e9498b453447a5afe527bd0e174587b12f66d2 @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134891v1/index.html
[PATCH] drm/i915/mso: using joiner is not possible with eDP MSO
It's not possible to use the joiner at the same time with eDP MSO. When a panel needs MSO, it's not optional, so MSO trumps joiner. v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville) Cc: sta...@vger.kernel.org Cc: Ville Syrjala Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668 Signed-off-by: Jani Nikula --- Just the minimal fix for starters to move things along. --- drivers/gpu/drm/i915/display/intel_dp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9a9bb0f5b7fe..ab33c9de393a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp) struct intel_encoder *encoder = &intel_dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + /* eDP MSO is not compatible with joiner */ + if (intel_dp->mso_link_count) + return false; + return DISPLAY_VER(dev_priv) >= 12 || (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A); -- 2.39.2
Re: [PATCH v2 2/2] drm/i915/dsc: don't mess up splitter state in joiner or dsc config
On Fri, Jun 14, 2024 at 05:17:51PM +0300, Jani Nikula wrote:
> On Fri, 14 Jun 2024, Ville Syrjälä wrote:
> > On Fri, Jun 14, 2024 at 01:16:04PM +0300, Jani Nikula wrote:
> >> The driver handles splitter (for MSO) and joiner/dsc configuration in
> >> different places. Avoid messing up the splitter hardware state when
> >> enabling/disabling joiner or dsc. It should not be possible to enable
> >> both joiner and splitter at the same time, but add more clarity to the
> >> register use overall.
> >>
> >> Note: We should probably handle splitter for MSO as well as dual-link
> >> DSI in intel_vdsc.c. Also, we have intel_uncompressed_joiner_enable()
> >> but no corresponding disable.
> >>
> >> Cc: Ville Syrjala
> >> Signed-off-by: Jani Nikula
> >> ---
> >> drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++---
> >> drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +---
> >> drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 1 +
> >> 3 files changed, 12 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index bb13a3ca8c7c..49509a6599fe 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -2417,9 +2417,8 @@ static void intel_ddi_mso_configure(const struct
> >> intel_crtc_state *crtc_state)
> >>dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
> >>}
> >>
> >> - intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
> >> - SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
> >> - OVERLAP_PIXELS_MASK, dss1);
> >> + /* Only touch the splitter */
> >> + intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), SPLITTER_STATE, dss1);
> >> }
> >>
> >> static u8 mtl_get_port_width(u8 lane_count)
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> index b9687b7692b8..a8671d3f1d41 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> @@ -766,7 +766,9 @@ void intel_uncompressed_joiner_enable(const struct
> >> intel_crtc_state *crtc_state)
> >>else
> >>dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
> >>
> >> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> >> crtc_state->cpu_transcoder), dss_ctl1_val);
> >> + /* Avoid touching the splitter */
> >> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
> >> crtc_state->cpu_transcoder),
> >> + ~SPLITTER_STATE, dss_ctl1_val);
> >>}
> >> }
> >>
> >> @@ -793,7 +795,9 @@ void intel_dsc_enable(const struct intel_crtc_state
> >> *crtc_state)
> >>if (!intel_crtc_is_joiner_secondary(crtc_state))
> >>dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
> >>}
> >> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> >> crtc_state->cpu_transcoder), dss_ctl1_val);
> >> + /* Avoid touching the splitter */
> >> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
> >> + ~SPLITTER_STATE, dss_ctl1_val);
> >>intel_de_write(dev_priv, dss_ctl2_reg(crtc,
> >> crtc_state->cpu_transcoder), dss_ctl2_val);
> >> }
> >>
> >> @@ -805,7 +809,9 @@ void intel_dsc_disable(const struct intel_crtc_state
> >> *old_crtc_state)
> >>/* Disable only if either of them is enabled */
> >>if (old_crtc_state->dsc.compression_enable ||
> >>old_crtc_state->joiner_pipes) {
> >> - intel_de_write(dev_priv, dss_ctl1_reg(crtc,
> >> old_crtc_state->cpu_transcoder), 0);
> >> + /* Avoid touching the splitter */
> >> + intel_de_rmw(dev_priv, dss_ctl1_reg(crtc,
> >> old_crtc_state->cpu_transcoder),
> >> + ~SPLITTER_STATE, 0);
> >>intel_de_write(dev_priv, dss_ctl2_reg(crtc,
> >> old_crtc_state->cpu_transcoder), 0);
> >>}
> >> }
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> index f921ad67b587..3734cd96f55e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> >> @@ -37,6 +37,7 @@
> >> #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> >> #define SPLITTER_CONFIGURATION_2_SEGMENT
> >> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> >> #define SPLITTER_CONFIGURATION_4_SEGMENT
> >> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> >> +#define SPLITTER_STATE (SPLITTER_ENABLE |
> >> SPLITTER_CONFIGURATION_MASK | OVERLAP_PIXELS_MASK)
> >
> > Not a big fan of this. I'd rather explicicitly list the bits
> > we actually want to modify in each call site.
> >
> > Also not a big fan of the rmws. I think in the future we might be
> > able to adjust some DSC stuff via fastsets, and that means no rmws
> > because we then want to do it via DSB. But not sure if the DSS
> > registers specifi
Re: [PATCH 3/6] drm/ttm: Support partial buffer mappings for ttm_bo_vmap()
Am 14.06.24 um 15:21 schrieb Thomas Zimmermann:
Add offset and size parameters to ttm_bo_vmap() to allow for partial
mappings of a buffer object. This brings the functionality on par with
ttm_bo_kmap().
Well the long term plan was to remove this functionality from
ttm_bo_kmap() and nuke that function sooner or later.
What exactly is the use case for partial mappings?
Regards,
Christian.
Callers pass the byte offset and size within the buffer object and
receive a page-aligned mapping of the buffer object's memory for the
specified area.
Also update all callers of ttm_bo_vmap() for the new parameters. As
before, existing callers map the buffer object's complete memory.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_ttm_helper.c | 2 +-
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
drivers/gpu/drm/loongson/lsdc_gem.c | 2 +-
drivers/gpu/drm/qxl/qxl_object.c | 2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c | 21 +++--
drivers/gpu/drm/xe/xe_lrc.c | 2 +-
drivers/gpu/drm/xe/xe_vm.c| 2 +-
include/drm/ttm/ttm_bo.h | 4 +++-
8 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_ttm_helper.c
b/drivers/gpu/drm/drm_gem_ttm_helper.c
index 3734aa2d1c5b5..f26b7c9077a68 100644
--- a/drivers/gpu/drm/drm_gem_ttm_helper.c
+++ b/drivers/gpu/drm/drm_gem_ttm_helper.c
@@ -67,7 +67,7 @@ int drm_gem_ttm_vmap(struct drm_gem_object *gem,
{
struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem);
- return ttm_bo_vmap(bo, map);
+ return ttm_bo_vmap(bo, 0, gem->size, map);
}
EXPORT_SYMBOL(drm_gem_ttm_vmap);
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index 6027584406af6..1670f9a459a9d 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -398,7 +398,7 @@ int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo,
struct iosys_map *map)
* no mapping present.
*/
if (iosys_map_is_null(&gbo->map)) {
- ret = ttm_bo_vmap(&gbo->bo, &gbo->map);
+ ret = ttm_bo_vmap(&gbo->bo, 0, gbo->bo.base.size, &gbo->map);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/loongson/lsdc_gem.c
b/drivers/gpu/drm/loongson/lsdc_gem.c
index a720d8f532093..f709960c781b9 100644
--- a/drivers/gpu/drm/loongson/lsdc_gem.c
+++ b/drivers/gpu/drm/loongson/lsdc_gem.c
@@ -77,7 +77,7 @@ static int lsdc_gem_object_vmap(struct drm_gem_object *obj,
struct iosys_map *ma
return ret;
}
- ret = ttm_bo_vmap(tbo, &lbo->map);
+ ret = ttm_bo_vmap(tbo, 0, tbo->base.size, &lbo->map);
if (ret) {
drm_err(obj->dev, "ttm bo vmap failed\n");
lsdc_bo_unpin(lbo);
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 5893e27a7ae50..9f06d5e26a32c 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -164,7 +164,7 @@ int qxl_bo_vmap_locked(struct qxl_bo *bo, struct iosys_map
*map)
goto out;
}
- r = ttm_bo_vmap(&bo->tbo, &bo->map);
+ r = ttm_bo_vmap(&bo->tbo, 0, bo->tbo.base.size, &bo->map);
if (r) {
qxl_bo_unpin_locked(bo);
return r;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index a9df0deff2deb..31f9772f05dac 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -457,17 +457,23 @@ EXPORT_SYMBOL(ttm_bo_kunmap);
* ttm_bo_vmap
*
* @bo: The buffer object.
+ * @offset: Byte offset into the buffer.
+ * @size: Number of bytes to map.
* @map: pointer to a struct iosys_map representing the map.
*
* Sets up a kernel virtual mapping, using ioremap or vmap to the
* data in the buffer object. The parameter @map returns the virtual
* address as struct iosys_map. Unmap the buffer with ttm_bo_vunmap().
+ * The address stored in @map will be aligned to the next lower page
+ * boundaries.
*
* Returns
* -ENOMEM: Out of memory.
* -EINVAL: Invalid range.
*/
-int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map)
+int ttm_bo_vmap(struct ttm_buffer_object *bo,
+ unsigned long offset, unsigned long size,
+ struct iosys_map *map)
{
struct ttm_resource *mem = bo->resource;
int ret;
@@ -483,18 +489,18 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct
iosys_map *map)
u16 alloc_flags;
if (mem->bus.addr) {
- vaddr_iomem = (void __iomem *)mem->bus.addr;
+ vaddr_iomem = (u8 __iomem *)mem->bus.addr + offset;
alloc_flags = ttm_bo_map_premapped;
} else if (mem->bus.caching == ttm_write_combined) {
- vaddr_iomem = ioremap_wc(mem->bus.offset,
bo->base.size);
+
Re: [PATCH] drm/i915/mso: using joiner is not possible with eDP MSO
On Fri, Jun 14, 2024 at 05:23:11PM +0300, Jani Nikula wrote: > It's not possible to use the joiner at the same time with eDP MSO. When > a panel needs MSO, it's not optional, so MSO trumps joiner. > > v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville) > > Cc: sta...@vger.kernel.org > Cc: Ville Syrjala > Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668 > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > > --- > > Just the minimal fix for starters to move things along. > --- > drivers/gpu/drm/i915/display/intel_dp.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 9a9bb0f5b7fe..ab33c9de393a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp) > struct intel_encoder *encoder = &intel_dig_port->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + /* eDP MSO is not compatible with joiner */ > + if (intel_dp->mso_link_count) > + return false; > + > return DISPLAY_VER(dev_priv) >= 12 || > (DISPLAY_VER(dev_priv) == 11 && >encoder->port != PORT_A); > -- > 2.39.2 -- Ville Syrjälä Intel
✓ Fi.CI.BAT: success for drm/i915/mso: using joiner is not possible with eDP MSO
== Series Details ==
Series: drm/i915/mso: using joiner is not possible with eDP MSO
URL : https://patchwork.freedesktop.org/series/134893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14943 -> Patchwork_134893v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/index.html
Participating hosts (43 -> 41)
--
Additional (2): fi-glk-j4005 bat-dg2-11
Missing(4): fi-cfl-8109u bat-jsl-1 fi-snb-2520m bat-mtlp-6
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_134893v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-b-dp-6:
- {bat-mtlp-9}: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-b-dp-6.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-mtlp-9/igt@kms_pipe_crc_basic@nonblocking-...@pipe-b-dp-6.html
Known issues
Here are the changes found in Patchwork_134893v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4083])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@gem_m...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@gem_render_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#6621])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#4212]) +7 other tests skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#5190])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4215] / [i915#5190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#4103] / [i915#4213]) +1
other test skip
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#3840])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-11: NOTRUN -> [SKIP][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#5274])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-arls-2: [PASS][16] -> [DMESG-WARN][17] ([i915#7507])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14943/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134893v1/bat-arls-2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pm_backlight@basic-brightness:
- bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#5354])
[18]:
https://
Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
I guess sparse and potential CI errors won't minimally relate to
this patch.
Adding also Jonathan in Cc :-)
Thanks,
Andi
On Fri, Jun 14, 2024 at 12:28:37AM +0200, Andi Shyti wrote:
> Replace "dynmically" with "dynamically".
>
> Signed-off-by: Andi Shyti
> Cc: John Harrison
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 14797e80bc92..263c9c3f6a03 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -295,7 +295,7 @@ struct guc_update_scheduling_policy_header {
> } __packed;
>
> /*
> - * Can't dynmically allocate memory for the scheduling policy KLV because
> + * Can't dynamically allocate memory for the scheduling policy KLV because
> * it will be sent from within the reset path. Need a fixed size lump on
> * the stack instead :(.
> *
> --
> 2.45.1
RE: [PATCH] drm/i915/gt/uc: Fix typo in comment
-Original Message-
From: Andi Shyti
Sent: Friday, June 14, 2024 8:22 AM
To: Andi Shyti
Cc: intel-gfx ; dri-devel
; Harrison, John C
; Cavitt, Jonathan
Subject: Re: [PATCH] drm/i915/gt/uc: Fix typo in comment
>
> I guess sparse and potential CI errors won't minimally relate to
> this patch.
Yeah, I don't see how a change to a comment could ever be related
to any CI errors:
Reviewed-by: Jonathan Cavitt
-Jonathan Cavitt
>
> Adding also Jonathan in Cc :-)
>
> Thanks,
> Andi
>
> On Fri, Jun 14, 2024 at 12:28:37AM +0200, Andi Shyti wrote:
> > Replace "dynmically" with "dynamically".
> >
> > Signed-off-by: Andi Shyti
> > Cc: John Harrison
> > ---
> > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > index 14797e80bc92..263c9c3f6a03 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> > @@ -295,7 +295,7 @@ struct guc_update_scheduling_policy_header {
> > } __packed;
> >
> > /*
> > - * Can't dynmically allocate memory for the scheduling policy KLV because
> > + * Can't dynamically allocate memory for the scheduling policy KLV because
> > * it will be sent from within the reset path. Need a fixed size lump on
> > * the stack instead :(.
> > *
> > --
> > 2.45.1
>
[PATCH v6 2/8] drm: Support per-plane async flip configuration
Drivers have different capabilities on what plane types they can or
cannot perform async flips. Create a plane::async_flip field so each
driver can choose which planes they allow doing async flips.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 ++--
include/drm/drm_plane.h | 5 +
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 2e1d9391febe..ed1af3455477 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1079,9 +1079,9 @@ int drm_atomic_set_property(struct drm_atomic_state
*state,
break;
}
- if (async_flip && plane_state->plane->type !=
DRM_PLANE_TYPE_PRIMARY) {
+ if (async_flip && !plane->async_flip) {
drm_dbg_atomic(prop->dev,
- "[OBJECT:%d] Only primary planes can be
changed during async flip\n",
+ "[PLANE:%d] does not support async
flips\n",
obj->id);
ret = -EINVAL;
break;
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 9507542121fa..0bebc72af5c3 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -786,6 +786,11 @@ struct drm_plane {
* @kmsg_panic: Used to register a panic notifier for this plane
*/
struct kmsg_dumper kmsg_panic;
+
+ /**
+* @async_flip: indicates if a plane can do async flips
+*/
+ bool async_flip;
};
#define obj_to_plane(x) container_of(x, struct drm_plane, base)
--
2.45.2
[PATCH v6 0/8] drm: Support per-plane async flip configuration
AMD hardware can do async flips with overlay planes, but currently there's no easy way to enable that in DRM. To solve that, this patchset creates a new drm_plane field, bool async_flip, that allows drivers to choose which plane can or cannot do async flips. This is latter used on drm_atomic_set_property when users want to do async flips. Patch 1 allows async commits with IN_FENCE_ID in any driver. Patches 2 to 7 have no function change. As per current code, every driver that allows async page flips using the atomic API, allows doing it only in the primary plane. Those patches then enable it for every driver. Patch 8 finally enables async flip on overlay planes for amdgpu. Changes from v5: - Instead of enabling plane->async_flip in the common code, move it to driver code. - Enable primary plane async flip on every driver https://lore.kernel.org/dri-devel/20240612193713.167448-1-andrealm...@igalia.com/ André Almeida (8): drm/atomic: Allow userspace to use explicit sync with atomic async flips drm: Support per-plane async flip configuration drm/amdgpu: Enable async flips on the primary plane drm: atmel-hlcdc: Enable async flips on the primary plane drm/i915: Enable async flips on the primary plane drm/nouveau: Enable async flips on the primary plane drm/vc4: Enable async flips on the primary plane drm/amdgpu: Make it possible to async flip overlay planes drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++ drivers/gpu/drm/drm_atomic_uapi.c | 8 +--- drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++ drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 drivers/gpu/drm/vc4/vc4_plane.c | 4 +++- include/drm/drm_plane.h | 5 + 8 files changed, 29 insertions(+), 4 deletions(-) -- 2.45.2
[PATCH v6 3/8] drm/amdgpu: Enable async flips on the primary plane
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 8a4c40b4c27e..0c126c5609d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -1705,6 +1705,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager
*dm,
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
drm_plane_create_zpos_immutable_property(plane, 0);
+ plane->async_flip = true;
} else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
unsigned int zpos = 1 + drm_plane_index(plane);
drm_plane_create_zpos_property(plane, zpos, 1, 254);
--
2.45.2
[PATCH v6 4/8] drm: atmel-hlcdc: Enable async flips on the primary plane
This driver can perfom async flips on primary planes, so enable it. Signed-off-by: André Almeida --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index 4a7ba0918eca..22b8a5c888ef 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -1227,6 +1227,9 @@ static int atmel_hlcdc_plane_create(struct drm_device *dev, if (ret) return ret; + if (type == DRM_PLANE_TYPE_PRIMARY) + plane->base.async_flip = true; + drm_plane_helper_add(&plane->base, &atmel_hlcdc_layer_plane_helper_funcs); -- 2.45.2
[PATCH v6 5/8] drm/i915: Enable async flips on the primary plane
This driver can perfom async flips on primary planes, so enable it. Signed-off-by: André Almeida --- drivers/gpu/drm/i915/display/i9xx_plane.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 0279c8aabdd1..0142beef20dc 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -931,6 +931,9 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) intel_plane_helper_add(plane); + if (plane->async_flip) + plane->base.async_flip = true; + return plane; fail: -- 2.45.2
[PATCH v6 6/8] drm/nouveau: Enable async flips on the primary plane
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 4310ad71870b..fd06d46d49ec 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -1285,6 +1285,7 @@ int
nv04_crtc_create(struct drm_device *dev, int crtc_num)
{
struct nouveau_display *disp = nouveau_display(dev);
+ struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_crtc *nv_crtc;
struct drm_plane *primary;
int ret;
@@ -1338,6 +1339,9 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num)
if (ret)
return ret;
+ if (drm->client.device.info.chipset >= 0x11)
+ primary->async_flip = true;
+
return nvif_head_vblank_event_ctor(&nv_crtc->head, "kmsVbl",
nv04_crtc_vblank_handler,
false, &nv_crtc->vblank);
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 7a2cceaee6e9..55db0fdf61e7 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -763,6 +763,10 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct
drm_device *dev,
return ret;
}
+ if (type == DRM_PLANE_TYPE_PRIMARY &&
+ drm->client.device.info.chipset >= 0x11)
+ wndw->plane.async_flip = true;
+
return 0;
}
--
2.45.2
[PATCH v6 7/8] drm/vc4: Enable async flips on the primary plane
This driver can perfom async flips on primary planes, so enable it.
Signed-off-by: André Almeida
---
drivers/gpu/drm/vc4/vc4_plane.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 07caf2a47c6c..e3d41da14e6f 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -1672,8 +1672,10 @@ struct drm_plane *vc4_plane_init(struct drm_device *dev,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
- if (type == DRM_PLANE_TYPE_PRIMARY)
+ if (type == DRM_PLANE_TYPE_PRIMARY) {
drm_plane_create_zpos_immutable_property(plane, 0);
+ plane->async_flip = true;
+ }
return plane;
}
--
2.45.2
[PATCH v6 1/8] drm/atomic: Allow userspace to use explicit sync with atomic async flips
Allow userspace to use explicit synchronization with atomic async flips.
That means that the flip will wait for some hardware fence, and then
will flip as soon as possible (async) in regard of the vblank.
Signed-off-by: André Almeida
---
drivers/gpu/drm/drm_atomic_uapi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 22bbb2d83e30..2e1d9391febe 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1070,7 +1070,9 @@ int drm_atomic_set_property(struct drm_atomic_state
*state,
break;
}
- if (async_flip && prop != config->prop_fb_id) {
+ if (async_flip &&
+ prop != config->prop_fb_id &&
+ prop != config->prop_in_fence_fd) {
ret = drm_atomic_plane_get_property(plane, plane_state,
prop, &old_val);
ret = drm_atomic_check_prop_changes(ret, old_val,
prop_value, prop);
--
2.45.2
