date:20221025

[Intel-gfx] [PATCH v5 10/19] drm/i915/vm_bind: Abstract out common execbuf functions

2022-10-25 Thread Niranjana Vishwanathapura

The new execbuf3 ioctl path and the legacy execbuf ioctl
paths have many common functionalities.
Abstract out the common execbuf functionalities into a
separate file where possible, thus allowing code sharing.

Reviewed-by: Andi Shyti 
Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../drm/i915/gem/i915_gem_execbuffer_common.c | 666 ++
 .../drm/i915/gem/i915_gem_execbuffer_common.h |  74 ++
 3 files changed, 741 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index bfb59b8f8a43..8d76bb888dc3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -148,6 +148,7 @@ gem-y += \
gem/i915_gem_create.o \
gem/i915_gem_dmabuf.o \
gem/i915_gem_domain.o \
+   gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
new file mode 100644
index ..4d1c9ce154b5
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c
@@ -0,0 +1,666 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
+#include "gt/intel_ring.h"
+
+#include "i915_gem_execbuffer_common.h"
+
+#define __EXEC_COMMON_FENCE_WAIT   BIT(0)
+#define __EXEC_COMMON_FENCE_SIGNAL BIT(1)
+
+static struct i915_request *eb_throttle(struct intel_context *ce)
+{
+   struct intel_ring *ring = ce->ring;
+   struct intel_timeline *tl = ce->timeline;
+   struct i915_request *rq;
+
+   /*
+* Completely unscientific finger-in-the-air estimates for suitable
+* maximum user request size (to avoid blocking) and then backoff.
+*/
+   if (intel_ring_update_space(ring) >= PAGE_SIZE)
+   return NULL;
+
+   /*
+* Find a request that after waiting upon, there will be at least half
+* the ring available. The hysteresis allows us to compete for the
+* shared ring and should mean that we sleep less often prior to
+* claiming our resources, but not so long that the ring completely
+* drains before we can submit our next request.
+*/
+   list_for_each_entry(rq, &tl->requests, link) {
+   if (rq->ring != ring)
+   continue;
+
+   if (__intel_ring_space(rq->postfix,
+  ring->emit, ring->size) > ring->size / 2)
+   break;
+   }
+   if (&rq->link == &tl->requests)
+   return NULL; /* weird, we will check again later for real */
+
+   return i915_request_get(rq);
+}
+
+static int eb_pin_timeline(struct intel_context *ce, bool throttle,
+  bool nonblock)
+{
+   struct intel_timeline *tl;
+   struct i915_request *rq = NULL;
+
+   /*
+* Take a local wakeref for preparing to dispatch the execbuf as
+* we expect to access the hardware fairly frequently in the
+* process, and require the engine to be kept awake between accesses.
+* Upon dispatch, we acquire another prolonged wakeref that we hold
+* until the timeline is idle, which in turn releases the wakeref
+* taken on the engine, and the parent device.
+*/
+   tl = intel_context_timeline_lock(ce);
+   if (IS_ERR(tl))
+   return PTR_ERR(tl);
+
+   intel_context_enter(ce);
+   if (throttle)
+   rq = eb_throttle(ce);
+   intel_context_timeline_unlock(tl);
+
+   if (rq) {
+   long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
+
+   if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
+ timeout) < 0) {
+   i915_request_put(rq);
+
+   /*
+* Error path, cannot use intel_context_timeline_lock as
+* that is user interruptable and this clean up step
+* must be done.
+*/
+   mutex_lock(&ce->timeline->mutex);
+   intel_context_exit(ce);
+   mutex_unlock(&ce->timeline->mutex);
+
+   if (nonblock)
+   return -EWOULDBLOCK;
+   else
+   return -EINTR;
+   }
+   i915_request_put(rq);
+   }
+
+   return 0;
+}
+
+/**
+ * i915_eb_pin_engine() - Pin the engine
+ * @ce: the context
+ * @ww: optional locking contex

[Intel-gfx] [PATCH v5 11/19] drm/i915/vm_bind: Use common execbuf functions in execbuf path

2022-10-25 Thread Niranjana Vishwanathapura

Update the execbuf path to use common execbuf functions to
reduce code duplication with the newer execbuf3 path.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 507 ++
 1 file changed, 38 insertions(+), 469 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 43f29acfbec9..749c3c80e02d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -28,6 +28,7 @@
 #include "i915_file_private.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
 #include "i915_gem_evict.h"
 #include "i915_gem_ioctls.h"
 #include "i915_trace.h"
@@ -235,13 +236,6 @@ enum {
  * the batchbuffer in trusted mode, otherwise the ioctl is rejected.
  */
 
-struct eb_fence {
-   struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
-   struct dma_fence *dma_fence;
-   u64 value;
-   struct dma_fence_chain *chain_fence;
-};
-
 struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -2446,164 +2440,29 @@ static const enum intel_engine_id user_ring_map[] = {
[I915_EXEC_VEBOX]   = VECS0
 };
 
-static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct 
intel_context *ce)
-{
-   struct intel_ring *ring = ce->ring;
-   struct intel_timeline *tl = ce->timeline;
-   struct i915_request *rq;
-
-   /*
-* Completely unscientific finger-in-the-air estimates for suitable
-* maximum user request size (to avoid blocking) and then backoff.
-*/
-   if (intel_ring_update_space(ring) >= PAGE_SIZE)
-   return NULL;
-
-   /*
-* Find a request that after waiting upon, there will be at least half
-* the ring available. The hysteresis allows us to compete for the
-* shared ring and should mean that we sleep less often prior to
-* claiming our resources, but not so long that the ring completely
-* drains before we can submit our next request.
-*/
-   list_for_each_entry(rq, &tl->requests, link) {
-   if (rq->ring != ring)
-   continue;
-
-   if (__intel_ring_space(rq->postfix,
-  ring->emit, ring->size) > ring->size / 2)
-   break;
-   }
-   if (&rq->link == &tl->requests)
-   return NULL; /* weird, we will check again later for real */
-
-   return i915_request_get(rq);
-}
-
-static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context 
*ce,
-  bool throttle)
-{
-   struct intel_timeline *tl;
-   struct i915_request *rq = NULL;
-
-   /*
-* Take a local wakeref for preparing to dispatch the execbuf as
-* we expect to access the hardware fairly frequently in the
-* process, and require the engine to be kept awake between accesses.
-* Upon dispatch, we acquire another prolonged wakeref that we hold
-* until the timeline is idle, which in turn releases the wakeref
-* taken on the engine, and the parent device.
-*/
-   tl = intel_context_timeline_lock(ce);
-   if (IS_ERR(tl))
-   return PTR_ERR(tl);
-
-   intel_context_enter(ce);
-   if (throttle)
-   rq = eb_throttle(eb, ce);
-   intel_context_timeline_unlock(tl);
-
-   if (rq) {
-   bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
-   long timeout = nonblock ? 0 : MAX_SCHEDULE_TIMEOUT;
-
-   if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
- timeout) < 0) {
-   i915_request_put(rq);
-
-   /*
-* Error path, cannot use intel_context_timeline_lock as
-* that is user interruptable and this clean up step
-* must be done.
-*/
-   mutex_lock(&ce->timeline->mutex);
-   intel_context_exit(ce);
-   mutex_unlock(&ce->timeline->mutex);
-
-   if (nonblock)
-   return -EWOULDBLOCK;
-   else
-   return -EINTR;
-   }
-   i915_request_put(rq);
-   }
-
-   return 0;
-}
-
 static int eb_pin_engine(struct i915_execbuffer *eb, bool throttle)
 {
-   struct intel_context *ce = eb->context, *child;
int err;
-   int i = 0, j = 0;
 
GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED);
 
-   if (unlikely(intel_context_is_banned(ce)))
-   return -EIO;
-
-   /*
-* Pinning the contexts may

[Intel-gfx] [PATCH v5 12/19] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl

2022-10-25 Thread Niranjana Vishwanathapura

Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.

The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.

Legacy features like relocations etc are not supported by execbuf3.

v2: Add more input validity checks.
v3: batch_address is a VA (not an array) if num_batches=1,
minor cleanup
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()
v5: Remove unwanted krealloc() and address other review comments.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 578 ++
 drivers/gpu/drm/i915/gem/i915_gem_ioctls.h|   2 +
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 include/uapi/drm/i915_drm.h   |  61 ++
 5 files changed, 643 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8d76bb888dc3..6a801684d569 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -150,6 +150,7 @@ gem-y += \
gem/i915_gem_domain.o \
gem/i915_gem_execbuffer_common.o \
gem/i915_gem_execbuffer.o \
+   gem/i915_gem_execbuffer3.o \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_lmem.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
new file mode 100644
index ..64251dc4cf91
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include 
+#include 
+
+#include 
+
+#include "gt/intel_context.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+
+#include "i915_drv.h"
+#include "i915_gem_context.h"
+#include "i915_gem_execbuffer_common.h"
+#include "i915_gem_ioctls.h"
+#include "i915_gem_vm_bind.h"
+#include "i915_trace.h"
+
+#define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
+#define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
+
+/* Catch emission of unexpected errors for CI! */
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
+#undef EINVAL
+#define EINVAL ({ \
+   DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \
+   22; \
+})
+#endif
+
+/**
+ * DOC: User command execution in vm_bind mode
+ *
+ * A VM in VM_BIND mode will not support older execbuf mode of binding.
+ * The execbuf ioctl handling in VM_BIND mode differs significantly from the
+ * older execbuf2 ioctl (See struct drm_i915_gem_execbuffer2).
+ * Hence, a new execbuf3 ioctl has been added to support VM_BIND mode. (See
+ * struct drm_i915_gem_execbuffer3). The execbuf3 ioctl will not accept any
+ * execlist. Hence, no support for implicit sync.
+ *
+ * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
+ * works with execbuf3 ioctl for submission.
+ *
+ * The execbuf3 ioctl directly specifies the batch addresses instead of as
+ * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
+ * support many of the older features like in/out/submit fences, fence array,
+ * default gem context etc. (See struct drm_i915_gem_execbuffer3).
+ *
+ * In VM_BIND mode, VA allocation is completely managed by the user instead of
+ * the i915 driver. Hence all VA assignment, eviction are not applicable in
+ * VM_BIND mode. Also, for determining object activeness, VM_BIND mode will not
+ * be using the i915_vma active reference tracking. It will instead check the
+ * dma-resv object's fence list for that.
+ *
+ * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
+ * vma lookup table, implicit sync, vma active reference tracking etc., are not
+ * applicable for execbuf3 ioctl.
+ */
+
+/**
+ * struct i915_execbuffer - execbuf struct for execbuf3
+ * @i915: reference to the i915 instance we run on
+ * @file: drm file reference
+ * @args: execbuf3 ioctl structure
+ * @gt: reference to the gt instance ioctl submitted for
+ * @context: logical state for the request
+ * @gem_context: callers context
+ * @requests: requests to be build
+ * @composite_fence: used for excl fence in dma_resv objects when > 1 BB 
submitted
+ * @ww: i915_gem_ww_ctx instance
+ * @num_batches: number of batches submitted
+ * @batch_addresses: addresses corresponds to the submitted batches
+ * @batches: references to the i915_vmas corresponding to the batches
+ * @fences: array of execbuf fences (See struct eb_fence)
+ * @num_fences: number of fences in @fences array
+ */
+struct i915_execbuffer {
+   struct drm_i915_private *i915;
+   struct drm_file *file;
+   struct drm_i915_gem_execbuffer3 *args;
+
+   str

[Intel-gfx] [PATCH v5 15/19] drm/i915/vm_bind: Handle persistent vmas in execbuf3

2022-10-25 Thread Niranjana Vishwanathapura

Handle persistent (VM_BIND) mappings during the request submission
in the execbuf3 path.

v2: Ensure requests wait for bindings to complete.
v3: Remove short term pinning with PIN_VALIDATE flag.
Individualize fences before adding to dma_resv obj.
v4: Fix bind completion check, use PIN_NOEVICT,
use proper lock while checking if vm_rebind_list is empty.

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 215 +-
 1 file changed, 214 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index 64251dc4cf91..d91c2e96cd0f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -3,6 +3,7 @@
  * Copyright © 2022 Intel Corporation
  */
 
+#include 
 #include 
 #include 
 
@@ -19,6 +20,7 @@
 #include "i915_gem_vm_bind.h"
 #include "i915_trace.h"
 
+#define __EXEC3_HAS_PINBIT_ULL(33)
 #define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
 #define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
 
@@ -42,7 +44,9 @@
  * execlist. Hence, no support for implicit sync.
  *
  * The new execbuf3 ioctl only works in VM_BIND mode and the VM_BIND mode only
- * works with execbuf3 ioctl for submission.
+ * works with execbuf3 ioctl for submission. All BOs mapped on that VM (through
+ * VM_BIND call) at the time of execbuf3 call are deemed required for that
+ * submission.
  *
  * The execbuf3 ioctl directly specifies the batch addresses instead of as
  * object handles as in execbuf2 ioctl. The execbuf3 ioctl will also not
@@ -58,6 +62,13 @@
  * So, a lot of code supporting execbuf2 ioctl, like relocations, VA evictions,
  * vma lookup table, implicit sync, vma active reference tracking etc., are not
  * applicable for execbuf3 ioctl.
+ *
+ * During each execbuf submission, request fence is added to all VM_BIND mapped
+ * objects with DMA_RESV_USAGE_BOOKKEEP. The DMA_RESV_USAGE_BOOKKEEP usage will
+ * prevent over sync (See enum dma_resv_usage). Note that DRM_I915_GEM_WAIT and
+ * DRM_I915_GEM_BUSY ioctls do not check for DMA_RESV_USAGE_BOOKKEEP usage and
+ * hence should not be used for end of batch check. Instead, the execbuf3
+ * timeline out fence should be used for end of batch check.
  */
 
 /**
@@ -129,6 +140,23 @@ eb_find_vma(struct i915_address_space *vm, u64 addr)
return i915_gem_vm_bind_lookup_vma(vm, va);
 }
 
+static void eb_scoop_unbound_vma_all(struct i915_address_space *vm)
+{
+   struct i915_vma *vma, *vn;
+
+   /**
+* Move all unbound vmas back into vm_bind_list so that they are
+* revalidated.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   list_for_each_entry_safe(vma, vn, &vm->vm_rebind_list, vm_rebind_link) {
+   list_del_init(&vma->vm_rebind_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->vm_rebind_lock);
+}
+
 static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 {
struct i915_vma *vma;
@@ -142,14 +170,108 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
eb->batches[i] = vma;
}
 
+   eb_scoop_unbound_vma_all(eb->context->vm);
+
+   return 0;
+}
+
+static int eb_lock_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma;
+   int err;
+
+   err = i915_gem_object_lock(eb->context->vm->root_obj, &eb->ww);
+   if (err)
+   return err;
+
+   list_for_each_entry(vma, &vm->non_priv_vm_bind_list,
+   non_priv_vm_bind_link) {
+   err = i915_gem_object_lock(vma->obj, &eb->ww);
+   if (err)
+   return err;
+   }
+
return 0;
 }
 
+static void eb_release_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *vma, *vn;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   if (!(eb->args->flags & __EXEC3_HAS_PIN))
+   return;
+
+   assert_object_held(vm->root_obj);
+
+   list_for_each_entry_safe(vma, vn, &vm->vm_bind_list, vm_bind_link)
+   if (!i915_vma_verify_bind_complete(vma))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bound_list);
+
+   eb->args->flags &= ~__EXEC3_HAS_PIN;
+}
+
 static void eb_release_vma_all(struct i915_execbuffer *eb)
 {
+   eb_release_persistent_vma_all(eb);
eb_unpin_engine(eb);
 }
 
+static int eb_reserve_fence_for_persistent_vma_all(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   u64 num_fences = 1;
+   struct i915_vma *vma;
+   int ret;
+
+   /* Reserve enough slots to accommodate composite

[Intel-gfx] [PATCH v5 18/19] drm/i915/vm_bind: Add uapi for user to enable vm_bind_mode

2022-10-25 Thread Niranjana Vishwanathapura

Add getparam support for VM_BIND capability version.
Add VM creation time flag to enable vm_bind_mode for the VM.

v2: update kernel-doc
v3: create vm->root_obj only upon I915_VM_CREATE_FLAGS_USE_VM_BIND
v4: replace vm->vm_bind_mode check with i915_gem_vm_is_vm_bind_mode()

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 ++--
 drivers/gpu/drm/i915/gem/i915_gem_context.h |  3 +--
 drivers/gpu/drm/i915/gt/intel_gtt.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/i915_getparam.c|  3 +++
 include/uapi/drm/i915_drm.h | 26 -
 6 files changed, 56 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 9a7eaa574966..072efb32892c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1809,9 +1809,13 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
if (!HAS_FULL_PPGTT(i915))
return -ENODEV;
 
-   if (args->flags)
+   if (args->flags & I915_VM_CREATE_FLAGS_UNKNOWN)
return -EINVAL;
 
+   if ((args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) &&
+   !HAS_VM_BIND(i915))
+   return -EOPNOTSUPP;
+
ppgtt = i915_ppgtt_create(to_gt(i915), 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1824,15 +1828,32 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, 
void *data,
goto err_put;
}
 
+   if (args->flags & I915_VM_CREATE_FLAGS_USE_VM_BIND) {
+   struct drm_i915_gem_object *obj;
+
+   obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+   if (IS_ERR(obj)) {
+   err = PTR_ERR(obj);
+   goto err_put;
+   }
+
+   ppgtt->vm.root_obj = obj;
+   }
+
err = xa_alloc(&file_priv->vm_xa, &id, &ppgtt->vm,
   xa_limit_32b, GFP_KERNEL);
if (err)
-   goto err_put;
+   goto err_root_obj_put;
 
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
args->vm_id = id;
return 0;
 
+err_root_obj_put:
+   if (ppgtt->vm.root_obj) {
+   i915_gem_object_put(ppgtt->vm.root_obj);
+   ppgtt->vm.root_obj = NULL;
+   }
 err_put:
i915_vm_put(&ppgtt->vm);
return err;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h 
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index e8b41aa8f8c4..b53aef2853cb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -150,8 +150,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev, void *data,
  */
 static inline bool i915_gem_vm_is_vm_bind_mode(struct i915_address_space *vm)
 {
-   /* No support to enable vm_bind mode yet */
-   return false;
+   return !!vm->root_obj;
 }
 
 struct i915_address_space *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 50648ab9214a..ae66fdd4bce9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -178,6 +178,8 @@ int i915_vm_lock_objects(struct i915_address_space *vm,
 void i915_address_space_fini(struct i915_address_space *vm)
 {
drm_mm_takedown(&vm->mm);
+   if (vm->root_obj)
+   i915_gem_object_put(vm->root_obj);
GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));
mutex_destroy(&vm->vm_bind_lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..481590dffbce 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -972,6 +972,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
   GRAPHICS_VER_FULL(i915) >= IP_VER(12, 
70))
 
+#define HAS_VM_BIND(i915) (GRAPHICS_VER(i915) >= 12)
+
 /* intel_device_info.c */
 static inline struct intel_device_info *
 mkwrite_device_info(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
b/drivers/gpu/drm/i915/i915_getparam.c
index 342c8ca6414e..f45b3c684bcf 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -175,6 +175,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+   case I915_PARAM_VM_BIND_VERSION:
+   value = HAS_VM_BIND(i915);
+   break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/include/uapi/drm/i915_d

[Intel-gfx] [PATCH v5 13/19] drm/i915/vm_bind: Update i915_vma_verify_bind_complete()

2022-10-25 Thread Niranjana Vishwanathapura

Ensure i915_vma_verify_bind_complete() handles case where bind
is not initiated. Also make it non static, add documentation
and move it out of CONFIG_DRM_I915_DEBUG_GEM.

v2: Fix fence leak

Reviewed-by: Matthew Auld 
Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 drivers/gpu/drm/i915/i915_vma.c | 22 --
 drivers/gpu/drm/i915/i915_vma.h |  1 +
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index eaa13e9ba966..aa4705246993 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -439,12 +439,25 @@ int i915_vma_sync(struct i915_vma *vma)
return i915_vm_sync(vma->vm);
 }
 
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
-static int i915_vma_verify_bind_complete(struct i915_vma *vma)
+/**
+ * i915_vma_verify_bind_complete() - Check for the bind completion of the vma
+ * @vma: vma to check for bind completion
+ *
+ * As the fence reference is obtained under RCU, no locking is required by
+ * the caller.
+ *
+ * Returns: 0 if the vma bind is completed. Error code otherwise.
+ */
+int i915_vma_verify_bind_complete(struct i915_vma *vma)
 {
-   struct dma_fence *fence = i915_active_fence_get(&vma->active.excl);
+   struct dma_fence *fence;
int err;
 
+   /* Ensure vma bind is initiated */
+   if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
+   return -EINVAL;
+
+   fence = i915_active_fence_get(&vma->active.excl);
if (!fence)
return 0;
 
@@ -457,9 +470,6 @@ static int i915_vma_verify_bind_complete(struct i915_vma 
*vma)
 
return err;
 }
-#else
-#define i915_vma_verify_bind_complete(_vma) 0
-#endif
 
 I915_SELFTEST_EXPORT void
 i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res,
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 1cadbf8fdedf..04770f8ba815 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -440,6 +440,7 @@ void i915_vma_make_purgeable(struct i915_vma *vma);
 
 int i915_vma_wait_for_bind(struct i915_vma *vma);
 int i915_vma_sync(struct i915_vma *vma);
+int i915_vma_verify_bind_complete(struct i915_vma *vma);
 
 /**
  * i915_vma_get_current_resource - Get the current resource of the vma
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v5 14/19] drm/i915/vm_bind: Expose i915_request_await_bind()

2022-10-25 Thread Niranjana Vishwanathapura

Rename __i915_request_await_bind() as i915_request_await_bind()
and make it non-static as it will be used in execbuf3 ioctl path.

v2: add documentation

Reviewed-by: Matthew Auld 
Reviewed-by: Andi Shyti 
Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/i915_vma.c |  8 +---
 drivers/gpu/drm/i915/i915_vma.h | 16 
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index aa4705246993..f73955aef16a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1888,18 +1888,12 @@ void i915_vma_revoke_mmap(struct i915_vma *vma)
list_del(&vma->obj->userfault_link);
 }
 
-static int
-__i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
-{
-   return __i915_request_await_exclusive(rq, &vma->active);
-}
-
 static int __i915_vma_move_to_active(struct i915_vma *vma, struct i915_request 
*rq)
 {
int err;
 
/* Wait for the vma to be bound before we start! */
-   err = __i915_request_await_bind(rq, vma);
+   err = i915_request_await_bind(rq, vma);
if (err)
return err;
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 04770f8ba815..737ef310d046 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -54,6 +54,22 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma, 
unsigned int flags);
 /* do not reserve memory to prevent deadlocks */
 #define __EXEC_OBJECT_NO_RESERVE BIT(31)
 
+/**
+ * i915_request_await_bind() - Setup request to wait for a vma bind completion
+ * @rq: the request which should wait
+ * @vma: vma whose binding @rq should wait to complete
+ *
+ * Setup the request @rq to asynchronously wait for @vma bind to complete
+ * before starting execution.
+ *
+ * Returns 0 on success, error code on failure.
+ */
+static inline int
+i915_request_await_bind(struct i915_request *rq, struct i915_vma *vma)
+{
+   return __i915_request_await_exclusive(rq, &vma->active);
+}
+
 int __must_check _i915_vma_move_to_active(struct i915_vma *vma,
  struct i915_request *rq,
  struct dma_fence *fence,
-- 
2.21.0.rc0.32.g243a4c7e27

[Intel-gfx] [PATCH v5 16/19] drm/i915/vm_bind: userptr dma-resv changes

2022-10-25 Thread Niranjana Vishwanathapura

For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions

v2: Do not double add vma to vm->userptr_invalidated_list

Signed-off-by: Niranjana Vishwanathapura 
Signed-off-by: Andi Shyti 
---
 .../gpu/drm/i915/gem/i915_gem_execbuffer3.c   | 84 ++-
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   | 19 +
 .../drm/i915/gem/i915_gem_vm_bind_object.c| 15 
 drivers/gpu/drm/i915/gt/intel_gtt.c   |  2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h   |  4 +
 drivers/gpu/drm/i915/i915_vma_types.h |  2 +
 6 files changed, 124 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
index d91c2e96cd0f..895d4f0a2647 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer3.c
@@ -20,6 +20,7 @@
 #include "i915_gem_vm_bind.h"
 #include "i915_trace.h"
 
+#define __EXEC3_USERPTR_USED   BIT_ULL(34)
 #define __EXEC3_HAS_PINBIT_ULL(33)
 #define __EXEC3_ENGINE_PINNED  BIT_ULL(32)
 #define __EXEC3_INTERNAL_FLAGS (~0ull << 32)
@@ -144,7 +145,22 @@ static void eb_scoop_unbound_vma_all(struct 
i915_address_space *vm)
 {
struct i915_vma *vma, *vn;
 
-   /**
+#ifdef CONFIG_MMU_NOTIFIER
+   /*
+* Move all invalidated userptr vmas back into vm_bind_list so that
+* they are looked up and revalidated.
+*/
+   spin_lock(&vm->userptr_invalidated_lock);
+   list_for_each_entry_safe(vma, vn, &vm->userptr_invalidated_list,
+userptr_invalidated_link) {
+   list_del_init(&vma->userptr_invalidated_link);
+   if (!list_empty(&vma->vm_bind_link))
+   list_move_tail(&vma->vm_bind_link, &vm->vm_bind_list);
+   }
+   spin_unlock(&vm->userptr_invalidated_lock);
+#endif
+
+   /*
 * Move all unbound vmas back into vm_bind_list so that they are
 * revalidated.
 */
@@ -157,10 +173,47 @@ static void eb_scoop_unbound_vma_all(struct 
i915_address_space *vm)
spin_unlock(&vm->vm_rebind_lock);
 }
 
+static int eb_lookup_persistent_userptr_vmas(struct i915_execbuffer *eb)
+{
+   struct i915_address_space *vm = eb->context->vm;
+   struct i915_vma *last_vma = NULL;
+   struct i915_vma *vma;
+   int err;
+
+   lockdep_assert_held(&vm->vm_bind_lock);
+
+   list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) {
+   if (!i915_gem_object_is_userptr(vma->obj))
+   continue;
+
+   err = i915_gem_object_userptr_submit_init(vma->obj);
+   if (err)
+   return err;
+
+   /*
+* The above submit_init() call does the object unbind and
+* hence adds vma into vm_rebind_list. Remove it from that
+* list as it is already scooped for revalidation.
+*/
+   spin_lock(&vm->vm_rebind_lock);
+   if (!list_empty(&vma->vm_rebind_link))
+   list_del_init(&vma->vm_rebind_link);
+   spin_unlock(&vm->vm_rebind_lock);
+
+   last_vma = vma;
+   }
+
+   if (last_vma)
+   eb->args->flags |= __EXEC3_USERPTR_USED;
+
+   return 0;
+}
+
 static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 {
struct i915_vma *vma;
unsigned int i;
+   int err = 0;
 
for (i = 0; i < eb->num_batches; i++) {
vma = eb_find_vma(eb->context->vm, eb->batch_addresses[i]);
@@ -172,6 +225,10 @@ static int eb_lookup_vma_all(struct i915_execbuffer *eb)
 
eb_scoop_unbound_vma_all(eb->context->vm);
 
+   err = eb_lookup_persistent_userptr_vmas(eb);
+   if (err)
+   return err;
+
return 0;
 }
 
@@ -344,6 +401,29 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
}
}
 
+#ifdef CONFIG_MMU_NOTIFIER
+   /* Check for further userptr invalidations */
+   spin_lock(&vm->userptr_invalidated_lock);
+   if (!list_empty(&vm->userptr_invalidated_list))
+   err = -EAGAIN;
+   spin_unlock(&vm->userptr_invalidated_lock);
+
+   if (!err && (eb->args->flags & __EXEC3_USERPTR_USED)) {
+   read_lock(&eb->i915->mm.notifier_lock);
+   list_for_each_entry(vma, &vm->vm_bind_list, vm_bind_link) {
+   if (!i915_gem_object_is_userptr(vma->obj))
+   continue;
+
+   err = i915_gem_object_userptr_submit_done(vma->obj);
+   if (err)
+   break;
+   }
+   read_unlock(&eb->i915->mm.notifier_lock);
+   }
+#endif
+   if (unlikely(err))
+   goto err_skip;
+
/* Unconditionally flush any chipset

[Intel-gfx] [PATCH v5 19/19] drm/i915/vm_bind: Render VM_BIND documentation

2022-10-25 Thread Niranjana Vishwanathapura

Update i915 documentation to include VM_BIND changes
and render all VM_BIND related documentation.

Signed-off-by: Niranjana Vishwanathapura 
---
 Documentation/gpu/i915.rst | 78 --
 1 file changed, 59 insertions(+), 19 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 4e59db1cfb00..5c55cbc980b1 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -283,15 +283,18 @@ An Intel GPU has multiple engines. There are several 
engine types.
 
 The Intel GPU family is a family of integrated GPU's using Unified
 Memory Access. For having the GPU "do work", user space will feed the
-GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
-or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
-instruct the GPU to perform work (for example rendering) and that work
-needs memory from which to read and memory to which to write. All memory
-is encapsulated within GEM buffer objects (usually created with the ioctl
-`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
-to create will also list all GEM buffer objects that the batchbuffer reads
-and/or writes. For implementation details of memory management see
-`GEM BO Management Implementation Details`_.
+GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`,
+`DRM_IOCTL_I915_GEM_EXECBUFFER2_WR` or `DRM_IOCTL_I915_GEM_EXECBUFFER3`.
+Most such batchbuffers will instruct the GPU to perform work (for example
+rendering) and that work needs memory from which to read and memory to
+which to write. All memory is encapsulated within GEM buffer objects
+(usually created with the ioctl `DRM_IOCTL_I915_GEM_CREATE`). In vm_bind mode
+(see `VM_BIND mode`_), the batch buffer and all the GEM buffer objects that
+it reads and/or writes should be bound with vm_bind ioctl before submitting
+the batch buffer to GPU. In legacy (non-VM_BIND) mode, an ioctl providing a
+batchbuffer for the GPU to create will also list all GEM buffer objects that
+the batchbuffer reads and/or writes. For implementation details of memory
+management see `GEM BO Management Implementation Details`_.
 
 The i915 driver allows user space to create a context via the ioctl
 `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
@@ -309,8 +312,9 @@ In addition to the ordering guarantees, the kernel will 
restore GPU
 state via HW context when commands are issued to a context, this saves
 user space the need to restore (most of atleast) the GPU state at the
 start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
-work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
-to identify what context to use with the command.
+work can pass that ID (drm_i915_gem_execbuffer3::ctx_id, or in the lower
+bits of drm_i915_gem_execbuffer2::rsvd1) to identify what context to use
+with the command.
 
 The GPU has its own memory management and address space. The kernel
 driver maintains the memory translation table for the GPU. For older
@@ -318,14 +322,14 @@ GPUs (i.e. those before Gen8), there is a single global 
such translation
 table, a global Graphics Translation Table (GTT). For newer generation
 GPUs each context has its own translation table, called Per-Process
 Graphics Translation Table (PPGTT). Of important note, is that although
-PPGTT is named per-process it is actually per context. When user space
-submits a batchbuffer, the kernel walks the list of GEM buffer objects
-used by the batchbuffer and guarantees that not only is the memory of
-each such GEM buffer object resident but it is also present in the
-(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
-then it is given an address. Two consequences of this are: the kernel
-needs to edit the batchbuffer submitted to write the correct value of
-the GPU address when a GEM BO is assigned a GPU address and the kernel
+PPGTT is named per-process it is actually per context. In legacy
+(non-vm_bind) mode, when user space submits a batchbuffer, the kernel walks
+the list of GEM buffer objects used by the batchbuffer and guarantees that
+not only is the memory of each such GEM buffer object resident but it is
+also present in the (PP)GTT. If the GEM buffer object is not yet placed in
+the (PP)GTT, then it is given an address. Two consequences of this are: the
+kernel needs to edit the batchbuffer submitted to write the correct value
+of the GPU address when a GEM BO is assigned a GPU address and the kernel
 might evict a different GEM BO from the (PP)GTT to make address room
 for another GEM BO. Consequently, the ioctls submitting a batchbuffer
 for execution also include a list of all locations within buffers that
@@ -407,6 +411,15 @@ objects, which has the goal to make space in gpu virtual 
address spaces.
 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
:internal:
 
+VM_BIND mode
+
+
+.. kernel-doc:: drivers/gpu/

[Intel-gfx] [PATCH v5 17/19] drm/i915/vm_bind: Limit vm_bind mode to non-recoverable contexts

2022-10-25 Thread Niranjana Vishwanathapura

Only support vm_bind mode with non-recoverable contexts.
With new vm_bind mode with eb3 submission path, we need not
support older recoverable contexts.

Signed-off-by: Niranjana Vishwanathapura 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 76c6419b7ae0..9a7eaa574966 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1617,6 +1617,12 @@ i915_gem_create_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(&ctx->stale.engines);
 
if (pc->vm) {
+   /* Only non-recoverable contexts are allowed in vm_bind mode */
+   if (i915_gem_vm_is_vm_bind_mode(pc->vm) &&
+   (pc->user_flags & BIT(UCONTEXT_RECOVERABLE))) {
+   err = -EINVAL;
+   goto err_ctx;
+   }
vm = i915_vm_get(pc->vm);
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
-- 
2.21.0.rc0.32.g243a4c7e27

Re: [Intel-gfx] [PATCH] Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Das, Nirmoy




On 10/24/2022 12:19 PM, Matthew Auld wrote:

The process for merging uAPI is to have UMD side ready and reviewed and
merged before merging. Revert for now until that is ready.

This reverts commit d54576a074a29d4901d0a693cd84e1a89057f694.

Reported-by: Joonas Lahtinen 
Signed-off-by: Matthew Auld 
Cc: Lionel Landwerlin 
Cc: Michal Mrozek 
Cc: Thomas Hellström 
Cc: Stuart Summers 
Cc: Jordan Justen 
Cc: Yang A Shi 
Cc: Nirmoy Das 
Cc: Niranjana Vishwanathapura 

Reviewed-by: Nirmoy Das 

---
  drivers/gpu/drm/i915/i915_query.c |  1 -
  include/uapi/drm/i915_drm.h   | 29 ++---
  2 files changed, 2 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_query.c 
b/drivers/gpu/drm/i915/i915_query.c
index 111377f210ed..6ec9c9fb7b0d 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -498,7 +498,6 @@ static int query_memregion_info(struct drm_i915_private 
*i915,
info.region.memory_class = mr->type;
info.region.memory_instance = mr->instance;
info.probed_size = mr->total;
-   info.gtt_alignment = mr->min_page_size;
  
  		if (mr->type == INTEL_MEMORY_LOCAL)

info.probed_cpu_visible_size = mr->io_size;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index c2dce8633005..9bf281ec1125 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3466,33 +3466,8 @@ struct drm_i915_memory_region_info {
/** @region: The class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
  
-	union {

-   /** @rsvd0: MBZ */
-   __u32 rsvd0;
-   /**
-* @gtt_alignment:
-*
-* The minimum required GTT alignment for this type of memory.
-* When allocating a GTT address it must be aligned to this
-* value or larger. On some platforms the kernel might opt to
-* using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
-* pages can then be used if we also use 64K GTT alignment.
-*
-* NOTE: If this is zero then this must be an older
-* kernel which lacks support for this field.
-*
-* Side note: For larger objects (especially for
-* I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
-* consider potentially bumping the GTT alignment to say 2M,
-* which could potentially increase the likelihood of the kernel
-* being able to utilise 2M GTT pages underneath, if the layout
-* of the physical pages allows it.  On some configurations we
-* can then also use a more efficient page-table layout, if we
-* can't use the more desirable 2M GTT page, so long as we know
-* that the entire page-table will be used by this object.
-*/
-   __u32 gtt_alignment;
-   };
+   /** @rsvd0: MBZ */
+   __u32 rsvd0;
  
  	/**

 * @probed_size: Memory probed by the driver

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

2022-10-25 Thread Tvrtko Ursulin




On 24/10/2022 15:23, Mel Gorman wrote:

On Mon, Oct 24, 2022 at 02:04:50PM +0100, Tvrtko Ursulin wrote:


Hi Mel, mm experts,

With 6.1-rc2 we started hitting the WARN_ON added in 71e2d666ef85 ("mm/huge_memory: 
do not clobber swp_entry_t during THP split") in i915 automated CI:



Thanks for the report. As shmem pages pages are allocated via vma_alloc_folio
and are compound pages, can you try the following patch please?  If it
still triggers, please post the new oops as it'll include the tail page
information.

--8<--
From: Hugh Dickins 
Subject: [PATCH] mm: prep_compound_tail() clear page->private

Although page allocation always clears page->private in the first page
or head page of an allocation, it has never made a point of clearing
page->private in the tails (though 0 is often what is already there).

But now commit 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t
during THP split") issues a warning when page_tail->private is found to
be non-0 (unless it's swapcache).

Change that warning to dump page_tail (which also dumps head), instead
of just the head: so far we have seen dead0122, dead0003,
dead0001 or 0002 in the raw output for tail private.

We could just delete the warning, but today's consensus appears to want
page->private to be 0, unless there's a good reason for it to be set:
so now clear it in prep_compound_tail() (more general than just for THP;
but not for high order allocation, which makes no pass down the tails).

Fixes: 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t during THP 
split")
Signed-off-by: Hugh Dickins 
Cc: Mel Gorman 
Cc: Matthew Wilcox (Oracle) 
Cc: 
---
  mm/huge_memory.c | 2 +-
  mm/page_alloc.c  | 1 +
  2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 03fc7e5edf07..561a42567477 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -2462,7 +2462,7 @@ static void __split_huge_page_tail(struct page *head, int 
tail,
 * Fix up and warn once if private is unexpectedly set.
 */
if (!folio_test_swapcache(page_folio(head))) {
-   VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, head);
+   VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, page_tail);
page_tail->private = 0;
}
  
diff --git a/mm/page_alloc.c b/mm/page_alloc.c

index b5a6c815ae28..218b28ee49ed 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -807,6 +807,7 @@ static void prep_compound_tail(struct page *head, int 
tail_idx)
  
  	p->mapping = TAIL_MAPPING;

set_compound_head(p, head);
+   set_page_private(p, 0);
  }
  
  void prep_compound_page(struct page *page, unsigned int order)


The patch seems to fix our CI runs. Is it considered final version? If 
so I can temporarily put it in until it arrives via the next rc - 
assuming that would be the flow from upstream pov?


Regards,

Tvrtko

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev8)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev8)
URL   : https://patchwork.freedesktop.org/series/105879/
State : warning

== Summary ==

Error: dim checkpatch failed
f90c61132e40 drm/i915/vm_bind: Expose vm lookup function
ce0a50fbd695 drm/i915/vm_bind: Add __i915_sw_fence_await_reservation()
96720f194e91 drm/i915/vm_bind: Expose i915_gem_object_max_page_size()
85b5fc29129a drm/i915/vm_bind: Add support to create persistent vma
-:61: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#61: FILE: drivers/gpu/drm/i915/i915_vma.c:309:
+   GEM_BUG_ON(!IS_ERR(vma) && i915_vma_compare(vma, vm, view));

-:82: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#82: FILE: drivers/gpu/drm/i915/i915_vma.c:330:
+   GEM_BUG_ON(!kref_read(&vm->ref));

-:127: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#127: FILE: drivers/gpu/drm/i915/i915_vma.h:181:
+   GEM_BUG_ON(view && !(i915_is_ggtt_or_dpt(vm) ||

total: 0 errors, 3 warnings, 0 checks, 107 lines checked
5e7adf229a35 drm/i915/vm_bind: Implement bind and unbind of object
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#83: 
new file mode 100644

-:459: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#459: FILE: drivers/gpu/drm/i915/gt/intel_gtt.c:181:
+   GEM_BUG_ON(!RB_EMPTY_ROOT(&vm->va.rb_root));

-:580: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#580: FILE: include/uapi/drm/i915_drm.h:539:
+#define DRM_IOCTL_I915_GEM_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind)

-:581: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#581: FILE: include/uapi/drm/i915_drm.h:540:
+#define DRM_IOCTL_I915_GEM_VM_UNBIND   DRM_IOWR(DRM_COMMAND_BASE + 
DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_unbind)

total: 0 errors, 4 warnings, 0 checks, 607 lines checked
3bba46628e09 drm/i915/vm_bind: Support for VM private BOs
11bebebd40f5 drm/i915/vm_bind: Add support to handle object evictions
2ff8bd9137b2 drm/i915/vm_bind: Support persistent vma activeness tracking
4a9ed0e6ac9c drm/i915/vm_bind: Add out fence support
fea013678f0d drm/i915/vm_bind: Abstract out common execbuf functions
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#28: 
new file mode 100644

-:171: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#171: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:139:
+   GEM_BUG_ON(err);/* perma-pinned should incr a counter */

-:246: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#246: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:214:
+   GEM_BUG_ON("Context not found");

-:600: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#600: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer_common.c:568:
+   GEM_BUG_ON(!intel_context_is_parent(context));

total: 0 errors, 4 warnings, 0 checks, 747 lines checked
3e4718e2bb90 drm/i915/vm_bind: Use common execbuf functions in execbuf path
8cbdd730afb4 drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#39: 
new file mode 100644

-:266: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#266: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuf

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/vm_bind: Add VM_BIND functionality (rev8)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev8)
URL   : https://patchwork.freedesktop.org/series/105879/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Matthew Auld


On 24/10/2022 12:55, Patchwork wrote:

*Patch Details*
*Series:*   Revert "drm/i915/uapi: expose GTT alignment"
*URL:*	https://patchwork.freedesktop.org/series/110041/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html 




  CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110041v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html



Participating hosts (41 -> 41)

Additional (3): fi-hsw-4770 fi-icl-u2 bat-atsm-1
Missing (3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:



  IGT changes


Possible regressions

  *

igt@i915_selftest@live@hugepages:

  o

fi-glk-j4005: PASS


 -> DMESG-FAIL 


  o

fi-rkl-guc: PASS


 -> DMESG-FAIL 


  o

fi-icl-u2: NOTRUN -> DMESG-FAIL





These failures are unrelated. 
https://gitlab.freedesktop.org/drm/intel/-/issues/7311




Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
  o {fi-ehl-2}: PASS


 -> INCOMPLETE 



Known issues

Here are the changes found in Patchwork_110041v1 that come from known 
issues:



  IGT changes


Issues hit

  *

igt@gem_exec_gttfill@basic:

  o fi-pnv-d510: PASS


 -> FAIL 

 (i915#7229 )
  *

igt@gem_huc_copy@huc-copy:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#2190 )
  *

igt@gem_lmem_swapping@random-engines:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#4613 ) +3 similar issues
  *

igt@gem_render_tiled_blits@basic:

  o fi-apl-guc: PASS


 -> INCOMPLETE 

 (i915#7056 )
  *

igt@gem_softpin@allocator-basic-reserve:

  o fi-hsw-4770: NOTRUN -> SKIP


 (fdo#109271 ) +9 similar issues
  *

igt@i915_pm_backlight@basic-brightness:

  o fi-hsw-4770: NOTRUN -> SKIP


 (fdo#109271  / i915#3012 
)
  *

igt@i915_selftest@live@hangcheck:

  o fi-hsw-4770: NOTRUN -> INCOMPLETE


 (i915#4785 )
  *

igt@kms_chamelium@dp-crc-fast:

  o fi-hsw-4770: NOTRUN -> SKIP

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Andi Shyti

On Tue, Oct 25, 2022 at 12:09:53AM +0300, Gwan-gyeong Mun wrote:
> If a non-constant variable is used as the first argument of the FIELD_PREP
> macro, a build error occurs when using the clang compiler.

good catch! FIELD_PREP wants indeed a constant as a first
paramenter, also for gcc.

Reviewed-by: Andi Shyti 

Thanks,
Andi

> Fix the following build error used with clang compiler:
> 
> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> constant 18446744073709551615 with expression of type 'typeof 
> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long 
> long: (unsigned long long)0, long long: (unsigned long long)0, default: 
> (field_msk)))' (aka 'unsigned int') is always false 
> [-Werror,-Wtautological-constant-out-of-range-compare]
> bits_to_set = FIELD_PREP(field_msk, nval);
>   ^~~
> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> ^~~
> ./include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK'
> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> ~~^~~
> ./include/linux/build_bug.h:39:58: note: expanded from macro 
> 'BUILD_BUG_ON_MSG'
> ~^~~
> ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, 
> __COUNTER__)
> 
> ^~~
> ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~^~~
> ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> '__compiletime_assert'
> if (!(condition))   \
> 
> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> Cc: Ashutosh Dixit 
> Cc: Anshuman Gupta 
> Cc: Andi Shyti 
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
>  1 file changed, 3 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> b/drivers/gpu/drm/i915/i915_hwmon.c
> index 9e9781493025..782a621b1928 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> i915_reg_t rgadr,
>  
>  static void
>  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> -   u32 field_msk, int nshift,
> -   unsigned int scale_factor, long lval)
> +   int nshift, unsigned int scale_factor, long lval)
>  {
>   u32 nval;
> - u32 bits_to_clear;
> - u32 bits_to_set;
>  
>   /* Computation in 64-bits to avoid overflow. Round to nearest. */
>   nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
>  
> - bits_to_clear = field_msk;
> - bits_to_set = FIELD_PREP(field_msk, nval);
> -
>   hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> - bits_to_clear, bits_to_set);
> + PKG_PWR_LIM_1,
> + FIELD_PREP(PKG_PWR_LIM_1, nval));
>  }
>  
>  /*
> @@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int 
> chan, long val)
>   case hwmon_power_max:
>   hwm_field_scale_and_write(ddat,
> hwmon->rg.pkg_rapl_limit,
> -   PKG_PWR_LIM_1,
> hwmon->scl_shift_power,
> SF_POWER, val);
>   return 0;
> -- 
> 2.37.1

[Intel-gfx] [PATCH] i915/i915_gem_context: Remove debug message in i915_gem_context_create_ioctl

2022-10-25 Thread Karolina Drobnik

We know that as long as GEM context create ioctl succeeds, a context was
created. There is no need to write about it, especially when such a message
heavily pollutes dmesg and makes debugging actual errors harder.

Suggested-by: Chris Wilson 
Signed-off-by: Karolina Drobnik 
Cc: Andi Shyti 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1e29b1e6d186..1456ca87c04e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2298,7 +2298,6 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, 
void *data,
}
 
args->ctx_id = id;
-   drm_dbg(&i915->drm, "HW context %d created\n", args->ctx_id);
 
return 0;
 
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/vm_bind: Add VM_BIND functionality (rev8)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/vm_bind: Add VM_BIND functionality (rev8)
URL   : https://patchwork.freedesktop.org/series/105879/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12290 -> Patchwork_105879v8


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_105879v8 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_105879v8, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/index.html

Participating hosts (41 -> 37)
--

  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_105879v8:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-ivb-3770:[PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-ivb-3770/igt@i915_selftest@l...@hugepages.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-ivb-3770/igt@i915_selftest@l...@hugepages.html

  
Known issues


  Here are the changes found in Patchwork_105879v8 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271]) +32 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][4] -> [DMESG-FAIL][5] ([i915#7311])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
- fi-rkl-guc: NOTRUN -> [DMESG-FAIL][6] ([i915#7311])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
- fi-adl-ddr5:[PASS][7] -> [DMESG-FAIL][8] ([i915#7311])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-adl-ddr5/igt@i915_selftest@l...@hugepages.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-adl-ddr5/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-x1275:   NOTRUN -> [SKIP][9] ([fdo#109271])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-kbl-x1275/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-x1275:   NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-kbl-x1275/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-cfl-8109u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-bsw-nick:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-bsw-nick/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
- fi-bdw-5557u:   [PASS][13] -> [INCOMPLETE][14] ([i915#146])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-hdmi-a-2.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-bdw-5557u/igt@kms_pipe_crc_basic@suspend-read-...@pipe-a-hdmi-a-2.html

  * igt@runner@aborted:
- fi-ivb-3770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-ivb-3770/igt@run...@aborted.html
- fi-glk-j4005:   NOTRUN -> [FAIL][16] ([i915#4312])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-glk-j4005/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][17] ([i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-rkl-guc/igt@run...@aborted.html
- fi-adl-ddr5:NOTRUN -> [FAIL][18] ([i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/fi-adl-ddr5/igt@run...@aborted.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][19] ([i915#2582]) -> [PASS][20] +4 similar 
issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/bat-rpls-2/igt@fb...@read.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105879v8/bat-rpls-

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Andi Shyti

Hi Ashutosh,

> > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> > constant 18446744073709551615 with expression of type 'typeof 
> > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> > short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> > int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> > long long: (unsigned long long)0, long long: (unsigned long long)0, 
> > default: (field_msk)))' (aka 'unsigned int') is always false 
> > [-Werror,-Wtautological-constant-out-of-range-compare]
> 
> What is 18446744073709551615? You may want to limit the length of this line
> or checkpatch doesn't complain?

yeah! I am not a clang user, and this must be some ugly error
output. I don't think it makes sense to break it, though.

> > bits_to_set = FIELD_PREP(field_msk, nval);
> >   ^~~
> > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> > ^~~
> > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > '__BF_FIELD_CHECK'
> > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> > ~~^~~
> > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > 'BUILD_BUG_ON_MSG'
> > ~^~~
> > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > 'compiletime_assert'
> > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > __COUNTER__)
> > 
> > ^~~
> > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > '_compiletime_assert'
> > __compiletime_assert(condition, msg, prefix, suffix)
> > ~^~~
> > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > '__compiletime_assert'
> > if (!(condition))   \
> >
> > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > Cc: Ashutosh Dixit 
> > Cc: Anshuman Gupta 
> > Cc: Andi Shyti 
> > Signed-off-by: Gwan-gyeong Mun 
> > ---
> >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> >  1 file changed, 3 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > b/drivers/gpu/drm/i915/i915_hwmon.c
> > index 9e9781493025..782a621b1928 100644
> > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> > i915_reg_t rgadr,
> >
> >  static void
> >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> > - u32 field_msk, int nshift,
> > - unsigned int scale_factor, long lval)
> > + int nshift, unsigned int scale_factor, long lval)
> >  {
> > u32 nval;
> > -   u32 bits_to_clear;
> > -   u32 bits_to_set;
> >
> > /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> >
> > -   bits_to_clear = field_msk;
> > -   bits_to_set = FIELD_PREP(field_msk, nval);
> > -
> > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> > -   bits_to_clear, bits_to_set);
> > +   PKG_PWR_LIM_1,
> > +   FIELD_PREP(PKG_PWR_LIM_1, nval));
> 
> I don't want to give up so easily. We might have future uses for the
> function where we want field_msk to be passed into the function (rather
> than set inside the function as in this patch).
> 
> Do we understand what clang is complaining about? And why this compiles
> with gcc?

Because we are not compiling the builtin functions with gcc but
gcc has support for them. The FIELD_PREP checks if the first
parameter is a constant:

BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),

where _mask was our field_mask, but we ignore it. Apparently
clang doesn't.

If we want to stick to gcc only, then I still think the patch is
correct for two reasons:

  1. it's cleaner
  2. we would get on with the job and if one day we will decide
 to suppport builtin functions in gcc as well, we will sleep
 peacefully :)

> Copying l...@lists.linux.dev too.

maybe llvm folks have a better opinion.

Thanks,
Andi

> Thanks.
> --
> Ashutosh
> 
> 
> >  }
> >
> >  /*
> > @@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int 
> > chan, long val)
> > case hwmon_power_max:
> > hwm_field_scale_and_write(ddat,
> >

Re: [Intel-gfx] [PATCH] i915/i915_gem_context: Remove debug message in i915_gem_context_create_ioctl

2022-10-25 Thread Andi Shyti

> We know that as long as GEM context create ioctl succeeds, a context was
> created. There is no need to write about it, especially when such a message
> heavily pollutes dmesg and makes debugging actual errors harder.
> 
> Suggested-by: Chris Wilson 
> Signed-off-by: Karolina Drobnik 
> Cc: Andi Shyti 

Reviewed-by: Andi Shyti 

Thanks, Karolina!
Andi

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 1e29b1e6d186..1456ca87c04e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -2298,7 +2298,6 @@ int i915_gem_context_create_ioctl(struct drm_device 
> *dev, void *data,
>   }
>  
>   args->ctx_id = id;
> - drm_dbg(&i915->drm, "HW context %d created\n", args->ctx_id);
>  
>   return 0;
>  
> -- 
> 2.25.1

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

2022-10-25 Thread Mel Gorman

Cc'ing Andrew for awareness. Andrew, this bug report is almost identical to
the one Hugh already reported and fixed in "[PATCH] mm: prep_compound_tail()
clear page->private". Nothing wrong with the patch AFAIK and only the last
paragraph is relevant to you.

On Tue, Oct 25, 2022 at 09:50:14AM +0100, Tvrtko Ursulin wrote:
> 
> On 24/10/2022 15:23, Mel Gorman wrote:
> > On Mon, Oct 24, 2022 at 02:04:50PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > Hi Mel, mm experts,
> > > 
> > > With 6.1-rc2 we started hitting the WARN_ON added in 71e2d666ef85 
> > > ("mm/huge_memory: do not clobber swp_entry_t during THP split") in i915 
> > > automated CI:
> > > 
> > 
> > Thanks for the report. As shmem pages pages are allocated via 
> > vma_alloc_folio
> > and are compound pages, can you try the following patch please?  If it
> > still triggers, please post the new oops as it'll include the tail page
> > information.
> > 
> > --8<--
> > From: Hugh Dickins 
> > Subject: [PATCH] mm: prep_compound_tail() clear page->private
> > 
> > Although page allocation always clears page->private in the first page
> > or head page of an allocation, it has never made a point of clearing
> > page->private in the tails (though 0 is often what is already there).
> > 
> > But now commit 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t
> > during THP split") issues a warning when page_tail->private is found to
> > be non-0 (unless it's swapcache).
> > 
> > Change that warning to dump page_tail (which also dumps head), instead
> > of just the head: so far we have seen dead0122, dead0003,
> > dead0001 or 0002 in the raw output for tail private.
> > 
> > We could just delete the warning, but today's consensus appears to want
> > page->private to be 0, unless there's a good reason for it to be set:
> > so now clear it in prep_compound_tail() (more general than just for THP;
> > but not for high order allocation, which makes no pass down the tails).
> > 
> > Fixes: 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t during THP 
> > split")
> > Signed-off-by: Hugh Dickins 
> > Cc: Mel Gorman 
> > Cc: Matthew Wilcox (Oracle) 
> > Cc: 
> > ---
> >   mm/huge_memory.c | 2 +-
> >   mm/page_alloc.c  | 1 +
> >   2 files changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/mm/huge_memory.c b/mm/huge_memory.c
> > index 03fc7e5edf07..561a42567477 100644
> > --- a/mm/huge_memory.c
> > +++ b/mm/huge_memory.c
> > @@ -2462,7 +2462,7 @@ static void __split_huge_page_tail(struct page *head, 
> > int tail,
> >  * Fix up and warn once if private is unexpectedly set.
> >  */
> > if (!folio_test_swapcache(page_folio(head))) {
> > -   VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, head);
> > +   VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, page_tail);
> > page_tail->private = 0;
> > }
> > diff --git a/mm/page_alloc.c b/mm/page_alloc.c
> > index b5a6c815ae28..218b28ee49ed 100644
> > --- a/mm/page_alloc.c
> > +++ b/mm/page_alloc.c
> > @@ -807,6 +807,7 @@ static void prep_compound_tail(struct page *head, int 
> > tail_idx)
> > p->mapping = TAIL_MAPPING;
> > set_compound_head(p, head);
> > +   set_page_private(p, 0);
> >   }
> >   void prep_compound_page(struct page *page, unsigned int order)
> 
> The patch seems to fix our CI runs.

Thanks for letting me know.

> Is it considered final version?

AFAIK, yes.

> If so I
> can temporarily put it in until it arrives via the next rc - assuming that
> would be the flow from upstream pov?
> 

I expect it to. It's currently in the akpm/mm.git branch
mm/mm-hotfixes-unstable where I expect it to flow to mm/mm-hotfixes-stable
in due course before sending to Linus. I can't make promises about the
timing as that's determined by Andrew.

-- 
Mel Gorman
SUSE Labs

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/i915_gem_context: Remove debug message in i915_gem_context_create_ioctl

2022-10-25 Thread Patchwork

== Series Details ==

Series: i915/i915_gem_context: Remove debug message in 
i915_gem_context_create_ioctl
URL   : https://patchwork.freedesktop.org/series/110116/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12290 -> Patchwork_110116v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/index.html

Participating hosts (41 -> 39)
--

  Additional (1): bat-rplp-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110116v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_module_load@reload:
- {bat-rpls-2}:   [PASS][1] -> [WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/bat-rpls-2/igt@i915_module_l...@reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/bat-rpls-2/igt@i915_module_l...@reload.html

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [DMESG-WARN][3] ([i915#5537]) -> [WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_110116v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_parallel@engines@fds:
- fi-bsw-nick:NOTRUN -> [DMESG-WARN][5] ([i915#7311])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-bsw-nick/igt@gem_exec_parallel@engi...@fds.html

  * igt@i915_selftest@live@hugepages:
- fi-rkl-guc: NOTRUN -> [DMESG-FAIL][6] ([i915#7311])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
- fi-skl-guc: [PASS][7] -> [DMESG-FAIL][8] ([i915#7311])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-skl-guc/igt@i915_selftest@l...@hugepages.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-skl-guc/igt@i915_selftest@l...@hugepages.html
- fi-apl-guc: [PASS][9] -> [DMESG-FAIL][10] ([i915#7311])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-apl-guc/igt@i915_selftest@l...@hugepages.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-apl-guc/igt@i915_selftest@l...@hugepages.html

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-x1275:   NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-kbl-x1275/igt@i915_susp...@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-kbl-x1275:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-kbl-x1275/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-cfl-8109u:   NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-cfl-8109u/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor@atomic-transitions:
- fi-icl-u2:  [PASS][15] -> [DMESG-WARN][16] ([i915#4890])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cur...@atomic-transitions.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cur...@atomic-transitions.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][17] ([i915#4312])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-icl-u2/igt@run...@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#4312])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-apl-guc/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][19] ([i915#4312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-rkl-guc/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][20] ([i915#4312])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/fi-skl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick:[INCOMPLETE][21] ([i915#7311]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/fi-bsw-nick/igt@ge

[Intel-gfx] [PATCH v3 0/4] drm/i915/tgl+: Fix race conditions during DKL PHY accesses

2022-10-25 Thread Imre Deak

This is v3 of [1] fixing checkpatch issues and adding the Acked-bys.

[1] 
https://lore.kernel.org/intel-gfx/20221020160022.1823365-1-imre.d...@intel.com/T/#md92b51e5698295844f5436b479fdd473bf430882

Cc: Jani Nikula 
Cc: Ville Syrjälä 

Imre Deak (4):
  drm/i915/tgl+: Add locking around DKL PHY register accesses
  drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h
  drm/i915/tgl+: Move DKL PHY register definitions to
intel_dkl_phy_regs.h
  drm/i915/tgl+: Sanitize DKL PHY register definitions

 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c  |  71 +++---
 .../gpu/drm/i915/display/intel_display_core.h |   8 +
 .../i915/display/intel_display_power_well.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  | 106 +
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |  24 +++
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 204 ++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  62 +++---
 ...ntel_tc_phy_regs.h => intel_mg_phy_regs.h} |   6 +-
 drivers/gpu/drm/i915/display/intel_tc.c   |   3 +-
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 176 ---
 12 files changed, 412 insertions(+), 258 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
 rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => 
intel_mg_phy_regs.h} (99%)

-- 
2.37.1

[Intel-gfx] [PATCH v3 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses

2022-10-25 Thread Imre Deak

Accessing the TypeC DKL PHY registers during modeset-commit,
-verification, DP link-retraining and AUX power well toggling is racy
due to these code paths being concurrent and the PHY register bank
selection register (HIP_INDEX_REG) being shared between PHY instances
(aka TC ports) and the bank selection being not atomic wrt. the actual
PHY register access.

Add the required locking around each PHY register bank selection->
register access sequence.

Kudos to Ville for noticing the race conditions.

v2:
- Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani)
- Make the DKL_REG_TC_PORT macro independent of PHY internals.
- Move initing the DKL PHY lock to a more logical place.

v3:
- Fix parameter reuse in the DKL_REG_TC_PORT definition.
- Document the usage of phy_lock.

Cc: Ville Syrjälä 
Cc: Jani Nikula 
Cc:  # v5.5+
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c  |  68 +--
 .../gpu/drm/i915/display/intel_display_core.h |   8 ++
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  | 109 ++
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |  24 
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  59 +-
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 drivers/gpu/drm/i915/i915_reg.h   |   3 +
 9 files changed, 204 insertions(+), 76 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2535593ab379e..51704b54317cf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -285,6 +285,7 @@ i915-y += \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
+   display/intel_dkl_phy.o \
display/intel_dp.o \
display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 971356237eca3..7708ccbbdeb75 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -43,6 +43,7 @@
 #include "intel_de.h"
 #include "intel_display_power.h"
 #include "intel_display_types.h"
+#include "intel_dkl_phy.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
@@ -1262,33 +1263,30 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
-  HIP_INDEX_VAL(tc_port, ln));
-
-   intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
+   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+ DKL_TX_PRESHOOT_COEFF_MASK |
+ DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+ DKL_TX_VSWING_CONTROL_MASK,
+ 
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
+ 
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+ 
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+ DKL_TX_PRESHOOT_COEFF_MASK |
+ DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+ DKL_TX_VSWING_CONTROL_MASK,
+

[Intel-gfx] [PATCH v3 2/4] drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h

2022-10-25 Thread Imre Deak

An upcoming patch moves the DKL PHY register definitions to
intel_dkl_phy_regs.h, so for consistency rename intel_tc_phy_regs.h
containing only MG PHY register definitions to intel_mg_phy_regs.h.

Suggested-by: Jani Nikula 
Cc: Jani Nikula 
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c| 2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c   | 2 +-
 .../display/{intel_tc_phy_regs.h => intel_mg_phy_regs.h}| 6 +++---
 drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)
 rename drivers/gpu/drm/i915/display/{intel_tc_phy_regs.h => 
intel_mg_phy_regs.h} (99%)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7708ccbbdeb75..37272c6e4269d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -56,13 +56,13 @@
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_lspcon.h"
+#include "intel_mg_phy_regs.h"
 #include "intel_pps.h"
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
 #include "intel_sprite.h"
 #include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
 #include "skl_scaler.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8bbc2b5e50ed9..eb4decd8c68bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -29,9 +29,9 @@
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
 #include "intel_dpll_mgr.h"
+#include "intel_mg_phy_regs.h"
 #include "intel_pch_refclk.h"
 #include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
 
 /**
  * DOC: Display PLLs
diff --git a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h 
b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
similarity index 99%
rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
rename to drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
index 5a545086f9599..07978f8d5fb74 100644
--- a/drivers/gpu/drm/i915/display/intel_tc_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef __INTEL_TC_PHY_REGS__
-#define __INTEL_TC_PHY_REGS__
+#ifndef __INTEL_MG_PHY_REGS__
+#define __INTEL_MG_PHY_REGS__
 
 #include "i915_reg_defs.h"
 
@@ -277,4 +277,4 @@
   
_MG_PLL_TDC_COLDST_BIAS_PORT1, \
   
_MG_PLL_TDC_COLDST_BIAS_PORT2)
 
-#endif /* __INTEL_TC_PHY_REGS__ */
+#endif /* __INTEL_MG_PHY_REGS__ */
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c 
b/drivers/gpu/drm/i915/display/intel_tc.c
index 8cecd41ed0033..351709725cd04 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -9,8 +9,8 @@
 #include "intel_display_power_map.h"
 #include "intel_display_types.h"
 #include "intel_dp_mst.h"
+#include "intel_mg_phy_regs.h"
 #include "intel_tc.h"
-#include "intel_tc_phy_regs.h"
 
 static const char *tc_port_mode_name(enum tc_port_mode mode)
 {
-- 
2.37.1

[Intel-gfx] [PATCH v3 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions

2022-10-25 Thread Imre Deak

Not all Dekel PHY registers have a lane instance, so having to specify
this when using them is awkward. It makes more sense to define each PHY
register with its full internal PHY offset where bits 15:12 is the lane
for lane-instanced PHY registers and just a register bank index for other
PHY registers. This way lane-instanced registers can be referred to with
the (tc_port, lane) parameters, while other registers just with a tc_port
parameter.

An additional benefit of this change is to prevent passing a Dekel
register to a generic MMIO access function or vice versa.

v2:
- Fix parameter reuse in the DKL_REG_MMIO definition.

Cc: Jani Nikula 
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  20 +-
 .../i915/display/intel_display_power_well.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |  32 ++-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |  10 +-
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 191 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  48 ++---
 6 files changed, 155 insertions(+), 148 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 54142ca3e6947..e95bde5cf060e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1264,11 +1264,11 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
+   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
  DKL_TX_PRESHOOT_COEFF_MASK |
  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
  DKL_TX_VSWING_CONTROL_MASK,
@@ -1278,7 +1278,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
  DKL_TX_PRESHOOT_COEFF_MASK |
  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
  DKL_TX_VSWING_CONTROL_MASK,
@@ -1286,7 +1286,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
  
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
  
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
  DKL_TX_DP20BITMODE, 0);
 
if (IS_ALDERLAKE_P(dev_priv)) {
@@ -1305,7 +1305,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
  
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
  
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
  val);
@@ -2018,8 +2018,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
return;
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0);
-   ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1);
+   ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
+   ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
} else {
ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
@@ -2080,8 +2080,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
}
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0);
-   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1);
+   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
} else {
intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
@@ -3086,7 +3086,7 @@ static void adlp_tbt

[Intel-gfx] [PATCH v3 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h

2022-10-25 Thread Imre Deak

Move the TypeC DKL PHY register definitions to intel_dkl_phy_regs.h.

No functional changes.

v2:
- Move the definitions to a new intel_dkl_phy_regs.h file. (Jani).

Cc: Jani Nikula 
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |   1 +
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 193 ++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   1 +
 drivers/gpu/drm/i915/display/intel_tc.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 179 
 7 files changed, 198 insertions(+), 179 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 37272c6e4269d..54142ca3e6947 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -44,6 +44,7 @@
 #include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 1d18eee562534..86974c515206e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -13,6 +13,7 @@
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 #include "intel_dmc.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c 
b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index 710b030c7ed54..01781293ffdcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 
 static void
 dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h 
b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
new file mode 100644
index 0..189201278f590
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DKL_PHY_REGS__
+#define __INTEL_DKL_PHY_REGS__
+
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+#define DKL_REG_TC_PORT(__reg) \
+   (((__reg).reg - _DKL_PHY1_BASE) / (TC_PORT_1 + _DKL_PHY2_BASE - 
_DKL_PHY1_BASE))
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PCS_DW5   0x14
+#define DKL_PCS_DW5(tc_port)   _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PCS_DW5)
+#define   DKL_PCS_DW5_CORE_SOFTRESET   REG_BIT(11)
+
+#define _DKL_PLL_DIV0  0x200
+#define DKL_PLL_DIV0(tc_port)  _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+#define   DKL_PLL_DIV0_AFC_STARTUP_MASKREG_GENMASK(27, 
25)
+#define   DKL_PLL_DIV0_AFC_STARTUP(val)
REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
+#define   DKL_PLL_DIV0_INTEG_COEFF(x)  ((x) << 16)
+#define   DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
+#define   DKL_PLL_DIV0_PROP_COEFF(x)   ((x) << 12)
+#define   DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define   DKL_PLL_DIV0_FBPREDIV_SHIFT  (8)
+#define   DKL_PLL_DIV0_FBPREDIV(x) ((x) << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBPREDIV_MASK   (0xF << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
+#define   DKL_PLL_DIV0_FBDIV_INT_MASK  (0xFF << 0)
+#define   DKL_PLL_DIV0_MASK

Re: [Intel-gfx] [PATCH v3 6/6] freezer, sched: Rewrite core freezer logic

2022-10-25 Thread Peter Zijlstra

On Tue, Oct 25, 2022 at 07:52:07AM +0300, Ville Syrjälä wrote:
> On Fri, Oct 21, 2022 at 08:22:41PM +0300, Ville Syrjälä wrote:
> > On Mon, Aug 22, 2022 at 01:18:22PM +0200, Peter Zijlstra wrote:
> > > +#ifdef CONFIG_LOCKDEP
> > > + /*
> > > +  * It's dangerous to freeze with locks held; there be dragons there.
> > > +  */
> > > + if (!(state & __TASK_FREEZABLE_UNSAFE))
> > > + WARN_ON_ONCE(debug_locks && p->lockdep_depth);
> > > +#endif
> > 
> > We now seem to be hitting this sporadically in the intel gfx CI.
> > 
> > I've spotted it on two machines so far:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12270/shard-tglb7/igt@gem_ctx_isolation@preservation...@vcs0.html
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109950v1/shard-snb5/igt@kms_flip@flip-vs-suspend-interrupti...@a-vga1.html
> 
> Sadly no luck in reproducing this locally so far. In the meantime
> I added the following patch into our topic/core-for-CI branch in
> the hopes of CI stumbling on it again and dumping a bit more data:
> 
> --- a/kernel/freezer.c
> +++ b/kernel/freezer.c
> @@ -125,8 +125,16 @@ static int __set_task_frozen(struct task_struct *p, void 
> *arg)
>   /*
>* It's dangerous to freeze with locks held; there be dragons there.
>*/
> - if (!(state & __TASK_FREEZABLE_UNSAFE))
> - WARN_ON_ONCE(debug_locks && p->lockdep_depth);
> + if (!(state & __TASK_FREEZABLE_UNSAFE)) {
> + static bool warned = false;
> +
> + if (!warned && debug_locks && p->lockdep_depth) {
> + debug_show_held_locks(p);
> + WARN(1, "%s/%d holding locks while freezing\n",
> +  p->comm, task_pid_nr(p));
> + warned = true;
> + }
> + }
>  #endif
>  
>   WRITE_ONCE(p->__state, TASK_FROZEN);

That seems reasonable. But note that this constraint isn't new; the
previous freezer had much the same constraint but perhaps it wasn't
triggered for mysterious raisins. see the previous
try_to_freeze_unsafe() function.

[Intel-gfx] [PATCH v4 1/4] drm/i915/tgl+: Add locking around DKL PHY register accesses

2022-10-25 Thread Imre Deak

Accessing the TypeC DKL PHY registers during modeset-commit,
-verification, DP link-retraining and AUX power well toggling is racy
due to these code paths being concurrent and the PHY register bank
selection register (HIP_INDEX_REG) being shared between PHY instances
(aka TC ports) and the bank selection being not atomic wrt. the actual
PHY register access.

Add the required locking around each PHY register bank selection->
register access sequence.

Kudos to Ville for noticing the race conditions.

v2:
- Add the DKL PHY register accessors to intel_dkl_phy.[ch]. (Jani)
- Make the DKL_REG_TC_PORT macro independent of PHY internals.
- Move initing the DKL PHY lock to a more logical place.

v3:
- Fix parameter reuse in the DKL_REG_TC_PORT definition.
- Document the usage of phy_lock.

v4:
- Fix adding TC_PORT_1 offset in the DKL_REG_TC_PORT definition.

Cc: Ville Syrjälä 
Cc: Jani Nikula 
Cc:  # v5.5+
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c  |  68 +--
 .../gpu/drm/i915/display/intel_display_core.h |   8 ++
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  | 109 ++
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |  24 
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  59 +-
 drivers/gpu/drm/i915/i915_driver.c|   1 +
 drivers/gpu/drm/i915/i915_reg.h   |   3 +
 9 files changed, 204 insertions(+), 76 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2535593ab379e..51704b54317cf 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -285,6 +285,7 @@ i915-y += \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
+   display/intel_dkl_phy.o \
display/intel_dp.o \
display/intel_dp_aux.o \
display/intel_dp_aux_backlight.o \
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 971356237eca3..7708ccbbdeb75 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -43,6 +43,7 @@
 #include "intel_de.h"
 #include "intel_display_power.h"
 #include "intel_display_types.h"
+#include "intel_dkl_phy.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
@@ -1262,33 +1263,30 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
-  HIP_INDEX_VAL(tc_port, ln));
-
-   intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
+   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+ DKL_TX_PRESHOOT_COEFF_MASK |
+ DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+ DKL_TX_VSWING_CONTROL_MASK,
+ 
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
+ 
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+ 
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
-DKL_TX_PRESHOOT_COEFF_MASK |
-DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-DKL_TX_VSWING_CONTROL_MASK,
-
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
-
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+ DKL_TX_PRESHOOT_COEFF_MASK |
+ DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+

[Intel-gfx] [PATCH v4 3/4] drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h

2022-10-25 Thread Imre Deak

Move the TypeC DKL PHY register definitions to intel_dkl_phy_regs.h.

No functional changes.

v2:
- Move the definitions to a new intel_dkl_phy_regs.h file. (Jani).
v3:
- Rebase on latest patchset version.

Cc: Jani Nikula 
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |   1 +
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 193 ++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   1 +
 drivers/gpu/drm/i915/display/intel_tc.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 179 
 7 files changed, 198 insertions(+), 179 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 37272c6e4269d..54142ca3e6947 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -44,6 +44,7 @@
 #include "intel_display_power.h"
 #include "intel_display_types.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c 
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 1d18eee562534..86974c515206e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -13,6 +13,7 @@
 #include "intel_display_power_well.h"
 #include "intel_display_types.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 #include "intel_dmc.h"
 #include "intel_dpio_phy.h"
 #include "intel_dpll.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c 
b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index 710b030c7ed54..01781293ffdcf 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_dkl_phy.h"
+#include "intel_dkl_phy_regs.h"
 
 static void
 dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx)
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h 
b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
new file mode 100644
index 0..7d0f3aab7f5c6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DKL_PHY_REGS__
+#define __INTEL_DKL_PHY_REGS__
+
+#define _DKL_PHY1_BASE 0x168000
+#define _DKL_PHY2_BASE 0x169000
+#define _DKL_PHY3_BASE 0x16A000
+#define _DKL_PHY4_BASE 0x16B000
+#define _DKL_PHY5_BASE 0x16C000
+#define _DKL_PHY6_BASE 0x16D000
+
+#define DKL_REG_TC_PORT(__reg) \
+   (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - 
_DKL_PHY1_BASE))
+
+/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */
+#define _DKL_PCS_DW5   0x14
+#define DKL_PCS_DW5(tc_port)   _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PCS_DW5)
+#define   DKL_PCS_DW5_CORE_SOFTRESET   REG_BIT(11)
+
+#define _DKL_PLL_DIV0  0x200
+#define DKL_PLL_DIV0(tc_port)  _MMIO(_PORT(tc_port, \
+   
_DKL_PHY1_BASE, \
+   
_DKL_PHY2_BASE) + \
+ _DKL_PLL_DIV0)
+#define   DKL_PLL_DIV0_AFC_STARTUP_MASKREG_GENMASK(27, 
25)
+#define   DKL_PLL_DIV0_AFC_STARTUP(val)
REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
+#define   DKL_PLL_DIV0_INTEG_COEFF(x)  ((x) << 16)
+#define   DKL_PLL_DIV0_INTEG_COEFF_MASK(0x1F << 16)
+#define   DKL_PLL_DIV0_PROP_COEFF(x)   ((x) << 12)
+#define   DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12)
+#define   DKL_PLL_DIV0_FBPREDIV_SHIFT  (8)
+#define   DKL_PLL_DIV0_FBPREDIV(x) ((x) << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBPREDIV_MASK   (0xF << 
DKL_PLL_DIV0_FBPREDIV_SHIFT)
+#define   DKL_PLL_DIV0_FBDIV_INT(x)((x) << 0)
+#define   DKL_PLL_DIV0_FBDIV_INT_MASK  (

[Intel-gfx] [PATCH v4 4/4] drm/i915/tgl+: Sanitize DKL PHY register definitions

2022-10-25 Thread Imre Deak

Not all Dekel PHY registers have a lane instance, so having to specify
this when using them is awkward. It makes more sense to define each PHY
register with its full internal PHY offset where bits 15:12 is the lane
for lane-instanced PHY registers and just a register bank index for other
PHY registers. This way lane-instanced registers can be referred to with
the (tc_port, lane) parameters, while other registers just with a tc_port
parameter.

An additional benefit of this change is to prevent passing a Dekel
register to a generic MMIO access function or vice versa.

v2:
- Fix parameter reuse in the DKL_REG_MMIO definition.
v3:
- Rebase on latest patchset version.

Cc: Jani Nikula 
Acked-by: Jani Nikula 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  20 +-
 .../i915/display/intel_display_power_well.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |  32 ++-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |  10 +-
 .../gpu/drm/i915/display/intel_dkl_phy_regs.h | 191 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  48 ++---
 6 files changed, 155 insertions(+), 148 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 54142ca3e6947..e95bde5cf060e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1264,11 +1264,11 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
for (ln = 0; ln < 2; ln++) {
int level;
 
-   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), ln, 
0);
+   intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 
0);
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
  DKL_TX_PRESHOOT_COEFF_MASK |
  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
  DKL_TX_VSWING_CONTROL_MASK,
@@ -1278,7 +1278,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
 
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
  DKL_TX_PRESHOOT_COEFF_MASK |
  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
  DKL_TX_VSWING_CONTROL_MASK,
@@ -1286,7 +1286,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
  
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
  
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
  DKL_TX_DP20BITMODE, 0);
 
if (IS_ALDERLAKE_P(dev_priv)) {
@@ -1305,7 +1305,7 @@ static void tgl_dkl_phy_set_signal_levels(struct 
intel_encoder *encoder,
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
}
 
-   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port), ln,
+   intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
  
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
  
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
  val);
@@ -2018,8 +2018,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
return;
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 0);
-   ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port), 1);
+   ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
+   ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
} else {
ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
@@ -2080,8 +2080,8 @@ icl_program_mg_dp_mode(struct intel_digital_port 
*dig_port,
}
 
if (DISPLAY_VER(dev_priv) >= 12) {
-   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 0, ln0);
-   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port), 1, ln1);
+   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
+   intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
} else {
intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
@

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: stop abusing swiotlb_max_segment (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915: stop abusing swiotlb_max_segment (rev5)
URL   : https://patchwork.freedesktop.org/series/109946/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH v5 05/19] drm/i915/vm_bind: Implement bind and unbind of object

2022-10-25 Thread kernel test robot

Hi Niranjana,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-tip/drm-tip]

url:
https://github.com/intel-lab-lkp/linux/commits/Niranjana-Vishwanathapura/drm-i915-vm_bind-Add-VM_BIND-functionality/20221025-150246
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:
https://lore.kernel.org/r/20221025065905.13325-6-niranjana.vishwanathapura%40intel.com
patch subject: [Intel-gfx] [PATCH v5 05/19] drm/i915/vm_bind: Implement bind 
and unbind of object
config: i386-randconfig-a003-20221024 (attached as .config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project 
f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/493d35709c7a1fafd30f53c539e36cec9a1f9fb8
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Niranjana-Vishwanathapura/drm-i915-vm_bind-Add-VM_BIND-functionality/20221025-150246
git checkout 493d35709c7a1fafd30f53c539e36cec9a1f9fb8
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=i386 SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c:18:1: error: unused 
>> function 'i915_vm_bind_it_iter_next' [-Werror,-Wunused-function]
   INTERVAL_TREE_DEFINE(struct i915_vma, rb, u64, __subtree_last,
   ^
   include/linux/interval_tree_generic.h:151:33: note: expanded from macro 
'INTERVAL_TREE_DEFINE'
   ITSTATIC ITSTRUCT *  
 \

 ^
   :88:1: note: expanded from here
   i915_vm_bind_it_iter_next
   ^
   1 error generated.


vim +/i915_vm_bind_it_iter_next +18 
drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c

17  
  > 18  INTERVAL_TREE_DEFINE(struct i915_vma, rb, u64, __subtree_last,
19   START, LAST, static inline, i915_vm_bind_it)
20  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp


.config.gz
Description: application/gzip

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/i915_gem_context: Remove debug message in i915_gem_context_create_ioctl

2022-10-25 Thread Patchwork

== Series Details ==

Series: i915/i915_gem_context: Remove debug message in 
i915_gem_context_create_ioctl
URL   : https://patchwork.freedesktop.org/series/110116/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12290_full -> Patchwork_110116v1_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110116v1_full absolutely need 
to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110116v1_full, please notify your bug team to allow 
them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110116v1_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_gttfill@basic:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-glk5/igt@gem_exec_gttf...@basic.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/shard-glk8/igt@gem_exec_gttf...@basic.html

  * igt@gem_softpin@allocator-evict@bcs0:
- shard-glk:  [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-glk6/igt@gem_softpin@allocator-ev...@bcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/shard-glk2/igt@gem_softpin@allocator-ev...@bcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/shard-rkl-6/igt@kms_rotation_...@primary-y-tiled-reflect-x-90.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][6] +9 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110116v1/shard-dg1-19/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_110116v1_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-apl:  ([PASS][7], [PASS][8], [PASS][9], [PASS][10], 
[PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], 
[PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], 
[PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], 
[PASS][47], [PASS][48], [PASS][49], [PASS][50], [FAIL][51], [PASS][52], 
[PASS][53], [PASS][54], [PASS][55], [PASS][56]) ([i915#4386])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl6/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl6/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl7/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl8/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl8/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl8/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl8/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl7/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl7/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl7/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl1/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl1/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl1/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl1/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl2/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl3/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12290/shard-apl3/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: stop abusing swiotlb_max_segment (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915: stop abusing swiotlb_max_segment (rev5)
URL   : https://patchwork.freedesktop.org/series/109946/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109946v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109946v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109946v5, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/index.html

Participating hosts (42 -> 38)
--

  Additional (1): fi-tgl-dsi 
  Missing(5): fi-rkl-11600 bat-dg1-5 fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109946v5:

### CI changes ###

 Possible regressions 

  * boot:
- fi-hsw-g3258:   [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-hsw-g3258/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-hsw-g3258/boot.html

  
Known issues


  Here are the changes found in Patchwork_109946v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- bat-adlp-4: NOTRUN -> [SKIP][4] ([fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3546])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][8] ([i915#7229]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][10] ([i915#2867]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][12] ([fdo#109271]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][14] ([i915#7056]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][16] ([i915#7308]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][18] ([i915#6257]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v5/bat-rpls-1/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [f

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/edid: EDID override refactoring and fixes (rev3)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/edid: EDID override refactoring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/109579/
State : warning

== Summary ==

Error: dim checkpatch failed
8153ed33254a drm/i915/hdmi: do dual mode detect only if connected
25b066dd561d drm/i915/hdmi: stop using connector->override_edid
4ccec7a746c6 drm/amd/display: stop using connector->override_edid
c62d4fee46a0 drm/edid: debug log EDID override set/reset
7a44c6cfbde1 drm/edid: abstract debugfs override EDID show better
2d9a36acb3ba drm/edid: rename drm_add_override_edid_modes() to 
drm_edid_override_connector_update()
5357079fedfb drm/edid: split drm_edid block count helper
7107ea57ae6a drm/edid: add function for checking drm_edid validity
92c237aa17a5 drm/edid: detach debugfs EDID override from EDID property update
-:196: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#196: FILE: include/drm/drm_connector.h:1565:
+   struct mutex edid_override_mutex;

total: 0 errors, 0 warnings, 1 checks, 150 lines checked
4ad1085956a6 drm/edid/firmware: drop redundant connector_name variable/parameter
d945031e0660 drm/edid/firmware: rename drm_load_edid_firmware() to 
drm_edid_load_firmware()
f221eb34bf80 drm/edid: use struct drm_edid for override/firmware EDID
3c7dc1859ff4 drm/edid: move edid load declarations to internal header
b0f80f2b7753 drm/edid/firmware: convert to drm device specific logging
ca738866c29a drm/edid: add [CONNECTOR:%d:%s] to debug logging
4a9c7e085c74 drm/edid: convert to device specific logging

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/edid: EDID override refactoring and fixes (rev3)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/edid: EDID override refactoring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/109579/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109579v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/index.html

Participating hosts (42 -> 39)
--

  Missing(3): fi-ctg-p8600 fi-bdw-samus bat-dg1-5 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109579v3:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [WARN][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/bat-rpls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_109579v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][7] -> [FAIL][8] ([i915#6298])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][9] ([i915#3546])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271]) +11 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][11] ([i915#7229]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][13] ([i915#2867]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][15] ([fdo#109271]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][17] ([i915#7056]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][19] ([i915#4785]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][21] ([i915#7308]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : warning

== Summary ==

Error: dim checkpatch failed
15062ed1404b drm/i915/tgl+: Add locking around DKL PHY register accesses
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:218: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#218: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 442 lines checked
d90f6b228a01 drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h
-:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#51: 
rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h

total: 0 errors, 1 warnings, 0 checks, 48 lines checked
4570d7dd4e54 drm/i915/tgl+: Move DKL PHY register definitions to 
intel_dkl_phy_regs.h
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in 
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#57: 
new file mode 100644

-:94: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:33:
+#define   DKL_PLL_DIV0_AFC_STARTUP(val)
REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))

-:199: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#199: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:138:
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) 
REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))

-:201: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#201: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:140:
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) 
REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))

total: 0 errors, 4 warnings, 0 checks, 413 lines checked
0b7eb0f5a4e6 drm/i915/tgl+: Sanitize DKL PHY register definitions
-:294: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy_offset' - possible 
side-effects?
#294: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:39:
+#define _DKL_REG(tc_port, phy_offset)  \
+   ((const struct intel_dkl_phy_reg) { \
+   .reg = _DKL_REG_PHY_BASE(tc_port) + \
+  _DKL_REG_BANK_OFFSET(phy_offset), \
+   .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \
+   })

-:301: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0_offs' - possible 
side-effects?
#301: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:46:
+#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \
+   _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs)))

total: 0 errors, 0 warnings, 2 checks, 584 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL   : https://patchwork.freedesktop.org/series/109963/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109963v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/index.html

Participating hosts (42 -> 39)
--

  Missing(3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109963v5:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hangcheck:
- {bat-dg2-9}:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg2-9/igt@i915_selftest@l...@hangcheck.html

  
Known issues


  Here are the changes found in Patchwork_109963v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][4] -> [SKIP][5] ([fdo#109271])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  [PASS][6] -> [INCOMPLETE][7] ([i915#4418])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][9] ([fdo#111827])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * 
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka:   [PASS][11] -> [FAIL][12] ([i915#6298])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3546])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- bat-dg1-5:  NOTRUN -> [FAIL][15] ([i915#4312])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-dg1-5/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][16] ([i915#2867]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][18] ([fdo#109271]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109963v5/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][20] ([i915#7056]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [21]: 
h

Re: [Intel-gfx] [PATCH 09/22] platform/x86: fujitsu-laptop: Use acpi_video_get_backlight_types()

2022-10-25 Thread Jonathan Woithe

On Mon, Oct 24, 2022 at 08:35:00PM +0900, Akihiko Odaki wrote:
> acpi_video_get_backlight_type() is now deprecated.

The practical impact of this patch series on fujitsu-laptop is obviously
very minor assuming the new acpi_video_get_backlight_types() function
functions as advertised.  Accordingly, as maintainer of fujitsu-laptop I
will defer to the opinions of others who maintain the lower level
infrastructure which is more substantially affected by the bulk of the
changes in this series.

I note that Hans has naked the series and I'm happy to go along with that.

Regards
  jonathan

> Signed-off-by: Akihiko Odaki 
> ---
>  drivers/platform/x86/fujitsu-laptop.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/platform/x86/fujitsu-laptop.c 
> b/drivers/platform/x86/fujitsu-laptop.c
> index b543d117b12c..e820de39cb68 100644
> --- a/drivers/platform/x86/fujitsu-laptop.c
> +++ b/drivers/platform/x86/fujitsu-laptop.c
> @@ -387,7 +387,7 @@ static int acpi_fujitsu_bl_add(struct acpi_device *device)
>   struct fujitsu_bl *priv;
>   int ret;
>  
> - if (acpi_video_get_backlight_type() != acpi_backlight_vendor)
> + if (!(acpi_video_get_backlight_types() & ACPI_BACKLIGHT_VENDOR))
>   return -ENODEV;
>  
>   priv = devm_kzalloc(&device->dev, sizeof(*priv), GFP_KERNEL);
> @@ -819,7 +819,7 @@ static int acpi_fujitsu_laptop_add(struct acpi_device 
> *device)
>  
>   /* Sync backlight power status */
>   if (fujitsu_bl && fujitsu_bl->bl_device &&
> - acpi_video_get_backlight_type() == acpi_backlight_vendor) {
> + (acpi_video_get_backlight_types() & ACPI_BACKLIGHT_VENDOR)) {
>   if (call_fext_func(fext, FUNC_BACKLIGHT, 0x2,
>  BACKLIGHT_PARAM_POWER, 0x0) == BACKLIGHT_OFF)
>   fujitsu_bl->bl_device->props.power = FB_BLANK_POWERDOWN;
> -- 
> 2.37.3

Re: [Intel-gfx] [linus:master] [i915] f683b9d613: igt.gem_userptr_blits.probe.fail

2022-10-25 Thread Liam Howlett

* kernel test robot  [221024 01:06]:
> 
> Greeting,
> 
> FYI, we noticed igt.gem_userptr_blits.probe.fail due to commit (built with 
> gcc-11):
> 
> commit: f683b9d613193362ceb954c216f663a43c027302 ("i915: use the VMA 
> iterator")
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git master
> 
> in testcase: igt
> version: igt-x86_64-cf55acde-1_20221012
> with following parameters:
> 
>   group: group-13
> 
> 
> 
> on test machine: 20 threads 1 sockets (Commet Lake) with 16G memory
> 
> caused below changes (please refer to attached dmesg/kmsg for entire 
> log/backtrace):
> 
> 
> 
> 
> If you fix the issue, kindly add following tag
> | Reported-by: kernel test robot 
> | Link: https://lore.kernel.org/r/202210241246.68be2f11-oliver.s...@intel.com
> 
> 
> 
> 2022-10-24 03:27:39 build/tests/gem_userptr_blits --run-subtest probe
> IGT-Version: 1.26-gcf55acde (x86_64) (Linux: 6.0.0-rc3-00280-gf683b9d61319 
> x86_64)
> Aperture size is 268435456 MiB
> Total RAM is 13505 MiB
> Not enough RAM to run test, reducing buffer count.
> Test requirement not met in function __igt_uniquereal_main2320, file 
> ../tests/i915/gem_userptr_blits.c:2401:
> Test requirement: has_userptr(fd)
> Starting subtest: probe
> (gem_userptr_blits:1984) CRITICAL: Test assertion failure function 
> test_probe, file ../tests/i915/gem_userptr_blits.c:2231:
> (gem_userptr_blits:1984) CRITICAL: Failed assertion: __gem_userptr(fd, ptr + 
> 4096, 3*4096, 0, 0x2, &handle) == expected
> (gem_userptr_blits:1984) CRITICAL: Last errno: 14, Bad address
> (gem_userptr_blits:1984) CRITICAL: error: 0 != -14
> Subtest probe failed.
>  DEBUG 
> (gem_userptr_blits:1984) DEBUG: Test requirement passed: has_userptr_probe(fd)
> (gem_userptr_blits:1984) CRITICAL: Test assertion failure function 
> test_probe, file ../tests/i915/gem_userptr_blits.c:2231:
> (gem_userptr_blits:1984) CRITICAL: Failed assertion: __gem_userptr(fd, ptr + 
> 4096, 3*4096, 0, 0x2, &handle) == expected
> (gem_userptr_blits:1984) CRITICAL: Last errno: 14, Bad address
> (gem_userptr_blits:1984) CRITICAL: error: 0 != -14
> (gem_userptr_blits:1984) igt_core-INFO: Stack trace:
> (gem_userptr_blits:1984) igt_core-INFO:   #0 [__igt_fail_assert+0x106]
> (gem_userptr_blits:1984) igt_core-INFO:   #1 
> ../tests/i915/gem_userptr_blits.c:801 __igt_uniquereal_main2320()
> (gem_userptr_blits:1984) igt_core-INFO:   #2 
> ../tests/i915/gem_userptr_blits.c:2320 main()
> (gem_userptr_blits:1984) igt_core-INFO:   #3 ../csu/libc-start.c:308 
> __libc_start_main()
> (gem_userptr_blits:1984) igt_core-INFO:   #4 [_start+0x2a]
>   END  
> Stack trace:
>   #0 [__igt_fail_assert+0x106]
>   #1 ../tests/i915/gem_userptr_blits.c:801 __igt_uniquereal_main2320()
>   #2 ../tests/i915/gem_userptr_blits.c:2320 main()
>   #3 ../csu/libc-start.c:308 __libc_start_main()
>   #4 [_start+0x2a]
> Subtest probe: FAIL (0.052s)
> 
> 
> 
> To reproduce:
> 
> git clone https://github.com/intel/lkp-tests.git
> cd lkp-tests
> sudo bin/lkp install job.yaml   # job file is attached in 
> this email
> bin/lkp split-job --compatible job.yaml # generate the yaml file for 
> lkp run
> sudo bin/lkp run generated-yaml-file
> 
> # if come across any failure that blocks the test,
> # please remove ~/.lkp and /lkp dir to run from a clean state.
> 

These steps seem insufficient.  Initially, it failed complaining about a
missing config so I created the directory manually and copied the
confing in only to have it fail again:

lkp-tests/filters/need_kconfig_hw.rb:11:in `load_kernel_context':
context.yaml doesn't exist:
/pkg/linux/x86_64-rhel-8.3-func/gcc-11/f683b9d613193362ceb954c216f663a43c027302/context.yaml

Is there a full set of instructions for recreation?

Thanks,
Liam

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Jani Nikula

On Tue, 25 Oct 2022, Gwan-gyeong Mun  wrote:
> If a non-constant variable is used as the first argument of the FIELD_PREP
> macro, a build error occurs when using the clang compiler.
>
> Fix the following build error used with clang compiler:
>
> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> constant 18446744073709551615 with expression of type 'typeof 
> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long 
> long: (unsigned long long)0, long long: (unsigned long long)0, default: 
> (field_msk)))' (aka 'unsigned int') is always false 
> [-Werror,-Wtautological-constant-out-of-range-compare]
> bits_to_set = FIELD_PREP(field_msk, nval);
>   ^~~
> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> ^~~
> ./include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK'
> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> ~~^~~
> ./include/linux/build_bug.h:39:58: note: expanded from macro 
> 'BUILD_BUG_ON_MSG'
> ~^~~
> ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> 'compiletime_assert'
> _compiletime_assert(condition, msg, __compiletime_assert_, 
> __COUNTER__)
> 
> ^~~
> ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> '_compiletime_assert'
> __compiletime_assert(condition, msg, prefix, suffix)
> ~^~~
> ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> '__compiletime_assert'
> if (!(condition))   \
>
> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> Cc: Ashutosh Dixit 
> Cc: Anshuman Gupta 
> Cc: Andi Shyti 
> Signed-off-by: Gwan-gyeong Mun 
> ---
>  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
>  1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> b/drivers/gpu/drm/i915/i915_hwmon.c
> index 9e9781493025..782a621b1928 100644
> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> i915_reg_t rgadr,
>  
>  static void
>  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> -   u32 field_msk, int nshift,
> -   unsigned int scale_factor, long lval)
> +   int nshift, unsigned int scale_factor, long lval)
>  {
>   u32 nval;
> - u32 bits_to_clear;
> - u32 bits_to_set;
>  
>   /* Computation in 64-bits to avoid overflow. Round to nearest. */
>   nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
>  
> - bits_to_clear = field_msk;
> - bits_to_set = FIELD_PREP(field_msk, nval);

Please just switch to REG_FIELD_PREP() and it should be fine.

BR,
Jani.


> -
>   hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> - bits_to_clear, bits_to_set);
> + PKG_PWR_LIM_1,
> + FIELD_PREP(PKG_PWR_LIM_1, nval));
>  }
>  
>  /*
> @@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int 
> chan, long val)
>   case hwmon_power_max:
>   hwm_field_scale_and_write(ddat,
> hwmon->rg.pkg_rapl_limit,
> -   PKG_PWR_LIM_1,
> hwmon->scl_shift_power,
> SF_POWER, val);
>   return 0;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Jani Nikula

On Tue, 25 Oct 2022, Jani Nikula  wrote:
> On Tue, 25 Oct 2022, Gwan-gyeong Mun  wrote:
>> If a non-constant variable is used as the first argument of the FIELD_PREP
>> macro, a build error occurs when using the clang compiler.
>>
>> Fix the following build error used with clang compiler:
>>
>> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
>> constant 18446744073709551615 with expression of type 'typeof 
>> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
>> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
>> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
>> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
>> long long: (unsigned long long)0, long long: (unsigned long long)0, default: 
>> (field_msk)))' (aka 'unsigned int') is always false 
>> [-Werror,-Wtautological-constant-out-of-range-compare]
>> bits_to_set = FIELD_PREP(field_msk, nval);
>>   ^~~
>> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
>> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
>> ^~~
>> ./include/linux/bitfield.h:71:53: note: expanded from macro 
>> '__BF_FIELD_CHECK'
>> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
>> ~~^~~
>> ./include/linux/build_bug.h:39:58: note: expanded from macro 
>> 'BUILD_BUG_ON_MSG'
>> ~^~~
>> ./include/linux/compiler_types.h:357:22: note: expanded from macro 
>> 'compiletime_assert'
>> _compiletime_assert(condition, msg, __compiletime_assert_, 
>> __COUNTER__)
>> 
>> ^~~
>> ./include/linux/compiler_types.h:345:23: note: expanded from macro 
>> '_compiletime_assert'
>> __compiletime_assert(condition, msg, prefix, suffix)
>> ~^~~
>> ./include/linux/compiler_types.h:337:9: note: expanded from macro 
>> '__compiletime_assert'
>> if (!(condition))   \
>>
>> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
>> Cc: Ashutosh Dixit 
>> Cc: Anshuman Gupta 
>> Cc: Andi Shyti 
>> Signed-off-by: Gwan-gyeong Mun 
>> ---
>>  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
>>  1 file changed, 3 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
>> b/drivers/gpu/drm/i915/i915_hwmon.c
>> index 9e9781493025..782a621b1928 100644
>> --- a/drivers/gpu/drm/i915/i915_hwmon.c
>> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
>> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
>> i915_reg_t rgadr,
>>  
>>  static void
>>  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
>> -  u32 field_msk, int nshift,
>> -  unsigned int scale_factor, long lval)
>> +  int nshift, unsigned int scale_factor, long lval)
>>  {
>>  u32 nval;
>> -u32 bits_to_clear;
>> -u32 bits_to_set;
>>  
>>  /* Computation in 64-bits to avoid overflow. Round to nearest. */
>>  nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
>>  
>> -bits_to_clear = field_msk;
>> -bits_to_set = FIELD_PREP(field_msk, nval);
>
> Please just switch to REG_FIELD_PREP() and it should be fine.

Actually, probably not, but please switch to it anyway. ;)


>
> BR,
> Jani.
>
>
>> -
>>  hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
>> -bits_to_clear, bits_to_set);
>> +PKG_PWR_LIM_1,
>> +FIELD_PREP(PKG_PWR_LIM_1, nval));
>>  }
>>  
>>  /*
>> @@ -406,7 +401,6 @@ hwm_power_write(struct hwm_drvdata *ddat, u32 attr, int 
>> chan, long val)
>>  case hwmon_power_max:
>>  hwm_field_scale_and_write(ddat,
>>hwmon->rg.pkg_rapl_limit,
>> -  PKG_PWR_LIM_1,
>>hwmon->scl_shift_power,
>>SF_POWER, val);
>>  return 0;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prep work for finishing (de)gamma readout (rev3)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915: Prep work for finishing (de)gamma readout (rev3)
URL   : https://patchwork.freedesktop.org/series/109229/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109229v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/index.html

Participating hosts (42 -> 39)
--

  Missing(3): fi-ctg-p8600 fi-bdw-samus bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_109229v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][2] -> [DMESG-FAIL][3] ([i915#62])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u:   [PASS][4] -> [DMESG-WARN][5] ([i915#5904] / 
[i915#7174]) +2 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][6] -> [DMESG-WARN][7] ([i915#5904]) +27 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][8] -> [DMESG-WARN][9] ([i915#5904] / [i915#62])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][11] ([fdo#111827])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [PASS][13] -> [FAIL][14] ([i915#6298])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][15] -> [DMESG-WARN][16] ([i915#62]) +14 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][17] ([i915#3546])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][18] ([fdo#109271]) +11 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@gem_exec_gttfill@basic:
- fi-pnv-d510:[FAIL][19] ([i915#7229]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109229v3/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][21] ([i915#2867]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [22]: 
https:

Re: [Intel-gfx] [PATCH v4] drm/i915/slpc: Use platform limits for min/max frequency

2022-10-25 Thread Dixit, Ashutosh

On Mon, 24 Oct 2022 15:54:53 -0700, Vinay Belgaumkar wrote:
>
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a server part so that we can iterate between
> platform min and max.
>
> v2: Check softlimits instead of platform limits (Riana)
> v3: More review comments (Ashutosh)
> v4: No need to use saved_min_freq and other comments (Ashutosh)

OK, much better now overall.

> Bug: https://gitlab.freedesktop.org/drm/intel/-/issues/7030
>
> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
> +{
> + /* For server parts, SLPC min will be at RPMax.
> +  * Use min softlimit to clamp it to RP0 instead.
> +  */
> + if (!slpc->min_freq_softlimit &&
> + is_slpc_min_freq_rpmax(slpc)) {
> + slpc->min_is_rpmax = true;

The only remaining issue is slpc->min_is_rpmax is now set but never used so
it can possibly be removed, or retained for debuggability (I think it's a
fair reason to retain it). Though I am not sure if we will hit a "variable
set but never used" error from these clever compilers.

> + slpc->min_freq_softlimit = slpc->rp0_freq;
> + (slpc_to_gt(slpc))->defaults.min_freq = 
> slpc->min_freq_softlimit;
> + }
> +}

In any case, this is now:

Reviewed-by: Ashutosh Dixit

Re: [Intel-gfx] mm/huge_memory: do not clobber swp_entry_t during THP split

2022-10-25 Thread Hugh Dickins

On Tue, 25 Oct 2022, Mel Gorman wrote:

> Cc'ing Andrew for awareness. Andrew, this bug report is almost identical to
> the one Hugh already reported and fixed in "[PATCH] mm: prep_compound_tail()
> clear page->private". Nothing wrong with the patch AFAIK and only the last
> paragraph is relevant to you.
> 
> On Tue, Oct 25, 2022 at 09:50:14AM +0100, Tvrtko Ursulin wrote:
> > 
> > On 24/10/2022 15:23, Mel Gorman wrote:
> > > On Mon, Oct 24, 2022 at 02:04:50PM +0100, Tvrtko Ursulin wrote:
> > > > 
> > > > Hi Mel, mm experts,
> > > > 
> > > > With 6.1-rc2 we started hitting the WARN_ON added in 71e2d666ef85 
> > > > ("mm/huge_memory: do not clobber swp_entry_t during THP split") in i915 
> > > > automated CI:
> > > > 
> > > 
> > > Thanks for the report. As shmem pages pages are allocated via 
> > > vma_alloc_folio
> > > and are compound pages, can you try the following patch please?  If it
> > > still triggers, please post the new oops as it'll include the tail page
> > > information.
> > > 
> > > --8<--
> > > From: Hugh Dickins 
> > > Subject: [PATCH] mm: prep_compound_tail() clear page->private
> > > 
> > > Although page allocation always clears page->private in the first page
> > > or head page of an allocation, it has never made a point of clearing
> > > page->private in the tails (though 0 is often what is already there).
> > > 
> > > But now commit 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t
> > > during THP split") issues a warning when page_tail->private is found to
> > > be non-0 (unless it's swapcache).
> > > 
> > > Change that warning to dump page_tail (which also dumps head), instead
> > > of just the head: so far we have seen dead0122, dead0003,
> > > dead0001 or 0002 in the raw output for tail private.
> > > 
> > > We could just delete the warning, but today's consensus appears to want
> > > page->private to be 0, unless there's a good reason for it to be set:
> > > so now clear it in prep_compound_tail() (more general than just for THP;
> > > but not for high order allocation, which makes no pass down the tails).
> > > 
> > > Fixes: 71e2d666ef85 ("mm/huge_memory: do not clobber swp_entry_t during 
> > > THP split")
> > > Signed-off-by: Hugh Dickins 
> > > Cc: Mel Gorman 
> > > Cc: Matthew Wilcox (Oracle) 
> > > Cc: 
> > > ---
> > >   mm/huge_memory.c | 2 +-
> > >   mm/page_alloc.c  | 1 +
> > >   2 files changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/mm/huge_memory.c b/mm/huge_memory.c
> > > index 03fc7e5edf07..561a42567477 100644
> > > --- a/mm/huge_memory.c
> > > +++ b/mm/huge_memory.c
> > > @@ -2462,7 +2462,7 @@ static void __split_huge_page_tail(struct page 
> > > *head, int tail,
> > >* Fix up and warn once if private is unexpectedly set.
> > >*/
> > >   if (!folio_test_swapcache(page_folio(head))) {
> > > - VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, head);
> > > + VM_WARN_ON_ONCE_PAGE(page_tail->private != 0, page_tail);
> > >   page_tail->private = 0;
> > >   }
> > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c
> > > index b5a6c815ae28..218b28ee49ed 100644
> > > --- a/mm/page_alloc.c
> > > +++ b/mm/page_alloc.c
> > > @@ -807,6 +807,7 @@ static void prep_compound_tail(struct page *head, int 
> > > tail_idx)
> > >   p->mapping = TAIL_MAPPING;
> > >   set_compound_head(p, head);
> > > + set_page_private(p, 0);
> > >   }
> > >   void prep_compound_page(struct page *page, unsigned int order)
> > 
> > The patch seems to fix our CI runs.
> 
> Thanks for letting me know.
> 
> > Is it considered final version?
> 
> AFAIK, yes.

AFAItooK, yes - modulo akpm's signoff and final SHA1.

> 
> > If so I
> > can temporarily put it in until it arrives via the next rc - assuming that
> > would be the flow from upstream pov?

The right thing for now is for GregKH to drop Mel's from 6.0.4:
I've just sent a mail asking for that (I would have asked yesterday,
but mistook that GregKH was not in Cc).

Of course Mel's fix is much more important than the harmless
(unless panic on warn) warning, but let's delay it a few more days,
it just flowed into stable too quickly.

Thanks Mel: I never knowingly hit the THP_SWAP issue which your patch
is fixing, but it now looks like it was also responsible for mysterious
occasional OOM kills that I had been chasing for weeks.

Hugh

> > 
> 
> I expect it to. It's currently in the akpm/mm.git branch
> mm/mm-hotfixes-unstable where I expect it to flow to mm/mm-hotfixes-stable
> in due course before sending to Linus. I can't make promises about the
> timing as that's determined by Andrew.
> 
> -- 
> Mel Gorman
> SUSE Labs

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Patchwork

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR

Re: [Intel-gfx] [PATCH] drm/i915/userptr: restore probe_range behaviour

2022-10-25 Thread Tvrtko Ursulin




On 24/10/2022 18:21, Matthew Auld wrote:

The conversion looks harmless, however the addr value is updated inside
the loop with the previous vm_end, which then incorrectly leads to
for_each_vma_range() iterating over stuff outside the range we care
about. Fix this by storing the end value separately.

Testcase: igt@gem_userptr_blits@probe
Fixes: f683b9d61319 ("i915: use the VMA iterator")
Reported-by: kernel test robot 
Signed-off-by: Matthew Auld 
Cc: Tvrtko Ursulin 
Cc: Matthew Wilcox (Oracle) 
Cc: Vlastimil Babka 
Cc: Yu Zhao 
---
  drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index b7e24476a0fd..dadb3e3fa9c8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
  {
VMA_ITERATOR(vmi, mm, addr);
struct vm_area_struct *vma;
+   unsigned long end = addr + len;
  
  	mmap_read_lock(mm);

-   for_each_vma_range(vmi, vma, addr + len) {
+   for_each_vma_range(vmi, vma, end) {
/* Check for holes, note that we also update the addr below */
if (vma->vm_start > addr)
break;


I am unsure of the for_each_vma_range() behaviour regarding holes. If it 
just skips overs them and continues to next VMA in the range then patch 
looks good to me. Could someone confirm?


Regards,

Tvrtko

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: stop abusing swiotlb_max_segment (rev6)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915: stop abusing swiotlb_max_segment (rev6)
URL   : https://patchwork.freedesktop.org/series/109946/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109946v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/index.html

Participating hosts (42 -> 38)
--

  Missing(4): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109946v6:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@migrate:
- {bat-adlp-6}:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-6/igt@i915_selftest@l...@migrate.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/bat-adlp-6/igt@i915_selftest@l...@migrate.html

  
Known issues


  Here are the changes found in Patchwork_109946v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [PASS][4] -> [DMESG-FAIL][5] ([i915#62])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-kefka:   [PASS][6] -> [INCOMPLETE][7] ([i915#7120])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@gt_engines:
- bat-dg1-5:  [PASS][8] -> [INCOMPLETE][9] ([i915#4418])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/bat-dg1-5/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u:   [PASS][10] -> [DMESG-WARN][11] ([i915#5904] / 
[i915#7174]) +2 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][12] -> [DMESG-WARN][13] ([i915#5904]) +27 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][14] -> [DMESG-WARN][15] ([i915#5904] / 
[i915#62])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
- fi-apl-guc: NOTRUN -> [DMESG-WARN][16] ([i915#180] / [i915#5904] 
/ [i915#62])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-apl-guc/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][18] ([fdo#111827])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][20] -> [DMESG-WARN][21] ([i915#62]) +13 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109946v6/fi-cfl-8109u/igt@kms_frontbuffer_track...

[Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Somalapuram Amaranath

Change ttm_resource structure from num_pages to size_t size in bytes.
v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
v1 -> v2: change bo->resource->size to bo->base.size at some places
v1 -> v2: remove the local variable
v1 -> v2: cleanup cmp_size_smaller_first()

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   |  8 
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
 drivers/gpu/drm/i915/i915_scatterlist.c|  4 ++--
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  | 12 ++--
 drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
 drivers/gpu/drm/nouveau/nouveau_bo.c   |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo0039.c   |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo5039.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_bo74c1.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_bo85b5.c   |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo9039.c   |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_bo90b5.c   |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_boa0b5.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_gem.c  |  5 ++---
 drivers/gpu/drm/nouveau/nouveau_mem.c  |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_ttm.c  |  2 +-
 drivers/gpu/drm/radeon/radeon_cs.c |  7 +--
 drivers/gpu/drm/radeon/radeon_object.c |  4 ++--
 drivers/gpu/drm/radeon/radeon_trace.h  |  2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c|  4 ++--
 drivers/gpu/drm/ttm/ttm_bo.c   |  3 ---
 drivers/gpu/drm/ttm/ttm_bo_util.c  |  6 +++---
 drivers/gpu/drm/ttm/ttm_bo_vm.c|  4 ++--
 drivers/gpu/drm/ttm/ttm_range_manager.c|  2 +-
 drivers/gpu/drm/ttm/ttm_resource.c | 14 ++
 drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 ++--
 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  6 +++---
 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c|  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c  |  6 +++---
 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c |  6 +++---
 include/drm/ttm/ttm_resource.h |  4 ++--
 38 files changed, 79 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 1f3302aebeff..44367f03316f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -144,7 +144,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
node->base.start = node->mm_nodes[0].start;
} else {
node->mm_nodes[0].start = 0;
-   node->mm_nodes[0].size = node->base.num_pages;
+   node->mm_nodes[0].size = PFN_UP(node->base.size);
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 2e8f6cd7a729..974e85d8b6cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -542,6 +542,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
/* GWS and OA don't need any alignment. */
page_align = bp->byte_align;
size <<= PAGE_SHIFT;
+
} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
/* Both size and alignment must be a multiple of 4. */
page_align = ALIGN(bp->byte_align, 4);
@@ -776,7 +777,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
return 0;
}
 
-   r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
+   r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
if (r)
return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 6546552e596c..5c4f93ee0c57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -62,7 +62,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
if (!res)
goto fallback;
 
-   BUG_ON(start + size > res->num_pages << PAGE_SHIFT);
+   BUG_ON(start + size > res->size);
 
cur->mem_type = res->mem_type;
 
@@ -110,7 +110,7 @@ static inline void amdgpu_res_first(struct ttm_resource 
*res,
cur->size = size;
cur->remaining = size;
cur->node = NULL;
-   WARN_ON(res && start + size > res->num_pages << PAGE_SHIFT);
+   WARN_ON(res && start + size > res->size);

Re: [Intel-gfx] [PATCH] drm/i915/userptr: restore probe_range behaviour

2022-10-25 Thread Matthew Wilcox

On Tue, Oct 25, 2022 at 04:40:23PM +0100, Tvrtko Ursulin wrote:
> 
> On 24/10/2022 18:21, Matthew Auld wrote:
> > The conversion looks harmless, however the addr value is updated inside
> > the loop with the previous vm_end, which then incorrectly leads to
> > for_each_vma_range() iterating over stuff outside the range we care
> > about. Fix this by storing the end value separately.
> > 
> > Testcase: igt@gem_userptr_blits@probe
> > Fixes: f683b9d61319 ("i915: use the VMA iterator")
> > Reported-by: kernel test robot 
> > Signed-off-by: Matthew Auld 
> > Cc: Tvrtko Ursulin 
> > Cc: Matthew Wilcox (Oracle) 
> > Cc: Vlastimil Babka 
> > Cc: Yu Zhao 
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
> >   1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
> > b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > index b7e24476a0fd..dadb3e3fa9c8 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > @@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
> > unsigned long len)
> >   {
> > VMA_ITERATOR(vmi, mm, addr);
> > struct vm_area_struct *vma;
> > +   unsigned long end = addr + len;
> > mmap_read_lock(mm);
> > -   for_each_vma_range(vmi, vma, addr + len) {
> > +   for_each_vma_range(vmi, vma, end) {
> > /* Check for holes, note that we also update the addr below */
> > if (vma->vm_start > addr)
> > break;
> 
> I am unsure of the for_each_vma_range() behaviour regarding holes. If it
> just skips overs them and continues to next VMA in the range then patch
> looks good to me. Could someone confirm?

It's "For each VMA in this range".  It doesn't iterate over non-VMAs
within that range ;-)  Nor does a gap between VMAs stop the iteration.

Re: [Intel-gfx] [PATCH] drm/i915/userptr: restore probe_range behaviour

2022-10-25 Thread Tvrtko Ursulin




On 25/10/2022 16:54, Matthew Wilcox wrote:

On Tue, Oct 25, 2022 at 04:40:23PM +0100, Tvrtko Ursulin wrote:


On 24/10/2022 18:21, Matthew Auld wrote:

The conversion looks harmless, however the addr value is updated inside
the loop with the previous vm_end, which then incorrectly leads to
for_each_vma_range() iterating over stuff outside the range we care
about. Fix this by storing the end value separately.

Testcase: igt@gem_userptr_blits@probe
Fixes: f683b9d61319 ("i915: use the VMA iterator")
Reported-by: kernel test robot 
Signed-off-by: Matthew Auld 
Cc: Tvrtko Ursulin 
Cc: Matthew Wilcox (Oracle) 
Cc: Vlastimil Babka 
Cc: Yu Zhao 
---
   drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index b7e24476a0fd..dadb3e3fa9c8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -427,9 +427,10 @@ probe_range(struct mm_struct *mm, unsigned long addr, 
unsigned long len)
   {
VMA_ITERATOR(vmi, mm, addr);
struct vm_area_struct *vma;
+   unsigned long end = addr + len;
mmap_read_lock(mm);
-   for_each_vma_range(vmi, vma, addr + len) {
+   for_each_vma_range(vmi, vma, end) {
/* Check for holes, note that we also update the addr below */
if (vma->vm_start > addr)
break;


I am unsure of the for_each_vma_range() behaviour regarding holes. If it
just skips overs them and continues to next VMA in the range then patch
looks good to me. Could someone confirm?


It's "For each VMA in this range".  It doesn't iterate over non-VMAs
within that range ;-)  Nor does a gap between VMAs stop the iteration.


Thank you Matthew - I ventured briefly into the maple leaf world but 
quickly decided it would be much easier to ask. :)


Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Patchwork

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : warning

== Summary ==

Error: dim checkpatch failed
5d3feb81e845 drm/ttm: rework on ttm_resource to use size_t type
-:57: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#57: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h:65:
+   BUG_ON(start + size > res->size);

-:192: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely 
unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of 
BUG() or variants
#192: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:65:
+   GEM_BUG_ON(!bman_res->base.size);

-:313: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#313: FILE: drivers/gpu/drm/nouveau/nouveau_bo74c1.c:48:
+   PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->size,
0x0308, upper_32_bits(mem->vma[0].addr),

total: 0 errors, 2 warnings, 1 checks, 582 lines checked

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/ttm: rework on ttm_resource to use size_t type
URL   : https://patchwork.freedesktop.org/series/110129/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_110129v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/index.html

Participating hosts (42 -> 38)
--

  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus bat-dg1-5 

Known issues


  Here are the changes found in Patchwork_110129v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor@atomic:
- fi-icl-u2:  [PASS][4] -> [DMESG-WARN][5] ([i915#4890])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][6] ([i915#3546])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271]) +11 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][8] ([i915#4312])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-icl-u2/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][9] ([i915#2867]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][11] ([fdo#109271]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][13] ([i915#7056]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][15] ([i915#7308]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][17] ([i915#6257]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110129v1/bat-rpls-1/igt@i915_selftest@l...@requests.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6687]: https://gitla

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Christian König


Am 25.10.22 um 17:50 schrieb Somalapuram Amaranath:

Change ttm_resource structure from num_pages to size_t size in bytes.
v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
v1 -> v2: change bo->resource->size to bo->base.size at some places
v1 -> v2: remove the local variable
v1 -> v2: cleanup cmp_size_smaller_first()


Of hand that looks good to me now.

It would be nice if we keep the separation of one patch for each driver. 
But that would mean we need something like adding the size field first, 
patch all drivers and then remove num_pages which isn't a good approach 
either.


But please make sure that the Intel CI systems are happy with that.


Signed-off-by: Somalapuram Amaranath 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 ++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h |  4 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   |  8 
  drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
  drivers/gpu/drm/i915/i915_scatterlist.c|  4 ++--
  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  | 12 ++--
  drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo0039.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo5039.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo74c1.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo85b5.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo9039.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_bo90b5.c   |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_boa0b5.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_gem.c  |  5 ++---
  drivers/gpu/drm/nouveau/nouveau_mem.c  |  4 ++--
  drivers/gpu/drm/nouveau/nouveau_ttm.c  |  2 +-
  drivers/gpu/drm/radeon/radeon_cs.c |  7 +--
  drivers/gpu/drm/radeon/radeon_object.c |  4 ++--
  drivers/gpu/drm/radeon/radeon_trace.h  |  2 +-
  drivers/gpu/drm/radeon/radeon_ttm.c|  4 ++--
  drivers/gpu/drm/ttm/ttm_bo.c   |  3 ---
  drivers/gpu/drm/ttm/ttm_bo_util.c  |  6 +++---
  drivers/gpu/drm/ttm/ttm_bo_vm.c|  4 ++--
  drivers/gpu/drm/ttm/ttm_range_manager.c|  2 +-
  drivers/gpu/drm/ttm/ttm_resource.c | 14 ++
  drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 ++--
  drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  6 +++---
  drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c  |  6 +++---
  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c |  6 +++---
  include/drm/ttm/ttm_resource.h |  4 ++--
  38 files changed, 79 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 1f3302aebeff..44367f03316f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -144,7 +144,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
node->base.start = node->mm_nodes[0].start;
} else {
node->mm_nodes[0].start = 0;
-   node->mm_nodes[0].size = node->base.num_pages;
+   node->mm_nodes[0].size = PFN_UP(node->base.size);
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index 2e8f6cd7a729..974e85d8b6cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -542,6 +542,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
/* GWS and OA don't need any alignment. */
page_align = bp->byte_align;
size <<= PAGE_SHIFT;
+
} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
/* Both size and alignment must be a multiple of 4. */
page_align = ALIGN(bp->byte_align, 4);
@@ -776,7 +777,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
return 0;
}
  
-	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);

+   r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
if (r)
return r;
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h

index 6546552e596c..5c4f93ee0c57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -62,7 +62,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
if (!res)

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Patchwork

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Nick Desaulniers

Start of lore thread for context:
https://lore.kernel.org/intel-gfx/20221024210953.1572998-1-gwan-gyeong@intel.com/

On Tue, Oct 25, 2022 at 2:25 AM Andi Shyti  wrote:
>
> Hi Ashutosh,
>
> > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> > > constant 18446744073709551615 with expression of type 'typeof 
> > > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > > char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> > > short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> > > int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> > > long long: (unsigned long long)0, long long: (unsigned long long)0, 
> > > default: (field_msk)))' (aka 'unsigned int') is always false 
> > > [-Werror,-Wtautological-constant-out-of-range-compare]
> >
> > What is 18446744073709551615? You may want to limit the length of this line
> > or checkpatch doesn't complain?
>
> yeah! I am not a clang user, and this must be some ugly error
> output. I don't think it makes sense to break it, though.
>
> > > bits_to_set = FIELD_PREP(field_msk, nval);
> > >   ^~~
> > > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> > > ^~~
> > > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > > '__BF_FIELD_CHECK'
> > > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> > > ~~^~~
> > > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > > 'BUILD_BUG_ON_MSG'
> > > ~^~~
> > > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > > 'compiletime_assert'
> > > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > > __COUNTER__)
> > > 
> > > ^~~
> > > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > > '_compiletime_assert'
> > > __compiletime_assert(condition, msg, prefix, suffix)
> > > ~^~~
> > > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > > '__compiletime_assert'
> > > if (!(condition))   \
> > >
> > > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > > Cc: Ashutosh Dixit 
> > > Cc: Anshuman Gupta 
> > > Cc: Andi Shyti 
> > > Signed-off-by: Gwan-gyeong Mun 
> > > ---
> > >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> > >  1 file changed, 3 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > index 9e9781493025..782a621b1928 100644
> > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> > > i915_reg_t rgadr,
> > >
> > >  static void
> > >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> > > - u32 field_msk, int nshift,
> > > - unsigned int scale_factor, long lval)
> > > + int nshift, unsigned int scale_factor, long lval)
> > >  {
> > > u32 nval;
> > > -   u32 bits_to_clear;
> > > -   u32 bits_to_set;
> > >
> > > /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> > >
> > > -   bits_to_clear = field_msk;
> > > -   bits_to_set = FIELD_PREP(field_msk, nval);
> > > -
> > > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr,
> > > -   bits_to_clear, bits_to_set);
> > > +   PKG_PWR_LIM_1,
> > > +   FIELD_PREP(PKG_PWR_LIM_1, nval));
> >
> > I don't want to give up so easily. We might have future uses for the
> > function where we want field_msk to be passed into the function (rather
> > than set inside the function as in this patch).
> >
> > Do we understand what clang is complaining about? And why this compiles
> > with gcc?
>
> Because we are not compiling the builtin functions with gcc but
> gcc has support for them. The FIELD_PREP checks if the first
> parameter is a constant:
>
> BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),
>
> where _mask was our field_mask, but we ignore it. Apparently
> clang doesn't.

So we've been in this code before. I'm having vague memories of
commit 444da3f52407 ("bitfield.h: don't compile-time validate _val in
FIELD_FIT")

But looking at the first __builtin_constant_p check in
__BF_FIELD_CHECK, I'm curious

Re: [Intel-gfx] [PATCH v2] drm/ttm: rework on ttm_resource to use size_t type

2022-10-25 Thread Matthew Auld

On Tue, 25 Oct 2022 at 16:51, Somalapuram Amaranath
 wrote:
>
> Change ttm_resource structure from num_pages to size_t size in bytes.
> v1 -> v2: change PFN_UP(dst_mem->size) to ttm->num_pages
> v1 -> v2: change bo->resource->size to bo->base.size at some places
> v1 -> v2: remove the local variable
> v1 -> v2: cleanup cmp_size_smaller_first()
>
> Signed-off-by: Somalapuram Amaranath 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c|  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h |  4 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h  |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  6 +++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c   |  8 
>  drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  2 +-
>  drivers/gpu/drm/i915/i915_scatterlist.c|  4 ++--
>  drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  | 12 ++--
>  drivers/gpu/drm/i915/intel_region_ttm.c|  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo0039.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo5039.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo74c1.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_bo85b5.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo9039.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_bo90b5.c   |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_boa0b5.c   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_gem.c  |  5 ++---
>  drivers/gpu/drm/nouveau/nouveau_mem.c  |  4 ++--
>  drivers/gpu/drm/nouveau/nouveau_ttm.c  |  2 +-
>  drivers/gpu/drm/radeon/radeon_cs.c |  7 +--
>  drivers/gpu/drm/radeon/radeon_object.c |  4 ++--
>  drivers/gpu/drm/radeon/radeon_trace.h  |  2 +-
>  drivers/gpu/drm/radeon/radeon_ttm.c|  4 ++--
>  drivers/gpu/drm/ttm/ttm_bo.c   |  3 ---
>  drivers/gpu/drm/ttm/ttm_bo_util.c  |  6 +++---
>  drivers/gpu/drm/ttm/ttm_bo_vm.c|  4 ++--
>  drivers/gpu/drm/ttm/ttm_range_manager.c|  2 +-
>  drivers/gpu/drm/ttm/ttm_resource.c | 14 ++
>  drivers/gpu/drm/vmwgfx/vmwgfx_blit.c   |  4 ++--
>  drivers/gpu/drm/vmwgfx/vmwgfx_bo.c |  6 +++---
>  drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_gmrid_manager.c  |  6 +++---
>  drivers/gpu/drm/vmwgfx/vmwgfx_kms.c|  2 +-
>  drivers/gpu/drm/vmwgfx/vmwgfx_page_dirty.c |  6 +++---
>  include/drm/ttm/ttm_resource.h |  4 ++--
>  38 files changed, 79 insertions(+), 81 deletions(-)
>



> diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
> index 38119311284d..f86dc92965bb 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
> @@ -217,7 +217,7 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf,
> page_last = vma_pages(vma) + vma->vm_pgoff -
> drm_vma_node_start(&bo->base.vma_node);
>
> -   if (unlikely(page_offset >= bo->resource->num_pages))
> +   if (unlikely(page_offset >= bo->base.size))

At a glance it looks like we are missing PFN_UP(bo->base.size) for this one?

[Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

2022-10-25 Thread Ville Syrjala

From: Ville Syrjälä 

If we can't dig out a fixed mode for LVDS from the VBT or EDID
let's fall back to using the current output timings. This should
work as long as the BIOS has (somehow) enabled the output.

In this case we are dealing with the some kind of BLB based POS
machine (Toshiba SurePOS 500) where neither the OpRegion mailbox
nor the vbios ROM contain a valid VBT. And no EDID anywhere we
could find either.

Cc:  # v5.19+
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_panel.c |  6 ++--
 drivers/gpu/drm/i915/display/intel_panel.h |  3 ++
 drivers/gpu/drm/i915/display/intel_sdvo.c  | 40 ++
 3 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
b/drivers/gpu/drm/i915/display/intel_panel.c
index 69ce77711b7c..69082fbc7647 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -275,9 +275,9 @@ void intel_panel_add_edid_fixed_modes(struct 
intel_connector *connector,
intel_panel_destroy_probed_modes(connector);
 }
 
-static void intel_panel_add_fixed_mode(struct intel_connector *connector,
-  struct drm_display_mode *fixed_mode,
-  const char *type)
+void intel_panel_add_fixed_mode(struct intel_connector *connector,
+   struct drm_display_mode *fixed_mode,
+   const char *type)
 {
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct drm_display_info *info = &connector->base.display_info;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h 
b/drivers/gpu/drm/i915/display/intel_panel.h
index 5c5b5b7f95b6..964efed8ef3c 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -43,6 +43,9 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
 int intel_panel_compute_config(struct intel_connector *connector,
   struct drm_display_mode *adjusted_mode);
+void intel_panel_add_fixed_mode(struct intel_connector *connector,
+   struct drm_display_mode *fixed_mode,
+   const char *type);
 void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
  bool use_alt_fixed_modes);
 void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index cf8e80936d8e..9ed54118b669 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -781,6 +781,13 @@ static bool intel_sdvo_get_input_timing(struct intel_sdvo 
*intel_sdvo,
 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
 }
 
+static bool intel_sdvo_get_output_timing(struct intel_sdvo *intel_sdvo,
+struct intel_sdvo_dtd *dtd)
+{
+   return intel_sdvo_get_timing(intel_sdvo,
+SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
+}
+
 static bool
 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
 struct intel_sdvo_connector 
*intel_sdvo_connector,
@@ -2864,6 +2871,36 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, 
int device)
return true;
 }
 
+static void
+intel_sdvo_add_current_fixed_mode(struct intel_sdvo *intel_sdvo,
+ struct intel_sdvo_connector *connector)
+{
+   struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
+   struct drm_display_mode *mode;
+   struct intel_sdvo_dtd dtd = {};
+
+   if (!intel_sdvo_set_target_output(intel_sdvo,
+ connector->output_flag)) {
+   drm_dbg_kms(&i915->drm, "failed to set SDVO target output\n");
+   return;
+   }
+
+   if (!intel_sdvo_get_output_timing(intel_sdvo, &dtd)) {
+   drm_dbg_kms(&i915->drm, "failed to get SDVO output timings\n");
+   return;
+   }
+
+   mode = drm_mode_create(&i915->drm);
+   if (!mode)
+   return;
+
+   intel_sdvo_get_mode_from_dtd(mode, &dtd);
+
+   drm_mode_set_name(mode);
+
+   intel_panel_add_fixed_mode(&connector->base, mode, "current (SDVO)");
+}
+
 static bool
 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
 {
@@ -2913,6 +2950,9 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int 
device)
intel_panel_add_edid_fixed_modes(intel_connector, false);
}
 
+   if (!intel_panel_preferred_fixed_mode(intel_connector))
+   intel_sdvo_add_current_fixed_mode(intel_sdvo, 
intel_sdvo_connecto

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL   : https://patchwork.freedesktop.org/series/109632/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Matthew Auld


On 25/10/2022 17:37, Patchwork wrote:

*Patch Details*
*Series:*   Revert "drm/i915/uapi: expose GTT alignment"
*URL:*	https://patchwork.freedesktop.org/series/110041/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html 




  CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_110041v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html



Participating hosts (41 -> 42)

Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1
Missing (3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:



  IGT changes


Possible regressions

  * igt@i915_selftest@live@hugepages:
  o fi-kbl-soraka: NOTRUN -> INCOMPLETE




Also unrelated. Looks like some incomplete with no logs in the 
selftests. Patch is for sure not related, since it's just some uapi thing.





Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
  o {fi-ehl-2}: PASS


 -> INCOMPLETE 



Known issues

Here are the changes found in Patchwork_110041v1 that come from known 
issues:



  IGT changes


Issues hit

  *

igt@gem_exec_gttfill@basic:

  o

fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271 ) +9 similar issues

  o

fi-pnv-d510: PASS


 -> FAIL 

 (i915#7229 )

  *

igt@gem_huc_copy@huc-copy:

  o

fi-icl-u2: NOTRUN -> SKIP


 (i915#2190 )

  o

fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271  / i915#2190 
)

  *

igt@gem_lmem_swapping@basic:

  o fi-kbl-soraka: NOTRUN -> SKIP


 (fdo#109271  / i915#4613 
) +3 similar issues
  *

igt@gem_lmem_swapping@random-engines:

  o fi-icl-u2: NOTRUN -> SKIP


 (i915#4613 ) +3 similar issues
  *

igt@gem_render_tiled_blits@basic:

  o fi-apl-guc: PASS


 -> INCOMPLETE 

 (i915#7056 )
  *

igt@gem_softpin@allocator-basic-reserve:

  o fi-hsw-4770: NOTRUN -> SKIP


 (fdo#109271 ) +9 similar issues
  *

igt@i915_module_load@load:

  o fi-kbl-soraka: NOTRUN -> DMESG-WARN


 (i915#1982 )
  *

igt@i915_pm_backlight@basic-brightness:

  o fi-hsw-4770: NO

[Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Patchwork

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_110041v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110041v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][2] -> [INCOMPLETE][3]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271]) +9 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][5] -> [FAIL][6] ([i915#7229])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#7056])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][13] ([fdo#109271]) +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][14] ([i915#1982])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3012])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][16] ([i915#1886])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][17] ([i915#4785])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][18] -> [DMESG-FAIL][19] ([i915#7311])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)

2022-10-25 Thread Dixit, Ashutosh

On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>

Hi Lakshmi,

The below failures are unrelated to this series.

Thanks.
--
Ashutosh

> Patch Details
>
> Series:  i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State:   failure
> Details: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_108156v11, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> Participating hosts (41 -> 40)
>
> Additional (1): bat-atsm-1
> Missing (2): fi-ctg-p8600 fi-icl-u2
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in 
> Patchwork_108156v11:
>
> IGT changes
>
> Possible regressions
>
>   • igt@gem_exec_parallel@engines@contexts:
>
>   □ fi-bsw-nick: PASS -> INCOMPLETE
>   • igt@i915_selftest@live@hugepages:
>
>   □ fi-cfl-8109u: PASS -> DMESG-FAIL
>
>   □ fi-skl-guc: PASS -> DMESG-FAIL
>
>   • igt@i915_suspend@basic-s3-without-i915:
>
>   □ fi-rkl-11600: NOTRUN -> INCOMPLETE
>
> Suppressed

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Use platform limits for min/max frequency (rev5)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/slpc: Use platform limits for min/max frequency (rev5)
URL   : https://patchwork.freedesktop.org/series/109632/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293 -> Patchwork_109632v5


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/index.html

Participating hosts (42 -> 39)
--

  Missing(3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_109632v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_tiled_blits@basic:
- fi-pnv-d510:[PASS][2] -> [SKIP][3] ([fdo#109271])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_tiled_bl...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-pnv-d510/igt@gem_tiled_bl...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- bat-adlp-4: NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-apl-guc: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-adlp-4: NOTRUN -> [SKIP][7] ([i915#3546])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@kms_pipe_crc_ba...@suspend-read-crc.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +11 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@kms_psr@sprite_plane_onoff.html

  * igt@runner@aborted:
- fi-skl-guc: NOTRUN -> [FAIL][9] ([i915#4312])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-skl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}:   [DMESG-WARN][10] ([i915#2867]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@gem_linear_blits@basic:
- fi-pnv-d510:[SKIP][12] ([fdo#109271]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-pnv-d510/igt@gem_linear_bl...@basic.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-pnv-d510/igt@gem_linear_bl...@basic.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [INCOMPLETE][14] ([i915#7056]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@i915_selftest@live@guc:
- {bat-rpls-2}:   [DMESG-WARN][16] ([i915#6471]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-2/igt@i915_selftest@l...@guc.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rpls-2/igt@i915_selftest@l...@guc.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [INCOMPLETE][20] ([i915#7308]) -> [PASS][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@requests:
- {bat-rpls-1}:   [INCOMPLETE][22] ([i915#6257]) -> [PASS][23]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/bat-rpls-1/igt@i915_selftest@l...@requests.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v5/bat-rpls-1/igt@i915_selftest@l...@requests.html

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

2022-10-25 Thread Balasubramani Vivekanandan

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional changes. Changing terminolgy in some
> print statements. s/has_cdclk_squasher/has_cdclk_squash,
> s/crawler/crawl and s/squasher/squash.
> 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad401357ab66..0f5add2fc51b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
> *dev_priv)
>   skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
>  
> -static bool has_cdclk_squasher(struct drm_i915_private *i915)
> +static bool has_cdclk_squash(struct drm_i915_private *i915)
>  {
>   return IS_DG2(i915);
>  }
> @@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>  
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>  
>   if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (has_cdclk_squasher(dev_priv)) {
> + if (has_cdclk_squash(dev_priv)) {
>   u32 squash_ctl = 0;
>  
>   if (waveform)
> @@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   expected = skl_cdclk_decimal(cdclk);
>  
>   /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   clock = dev_priv->display.cdclk.hw.vco / 2;
>   else
>   clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (!has_cdclk_squasher(dev_priv))
> + if (!has_cdclk_squash(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (has_cdclk_squasher(dev_priv))
> + if (has_cdclk_squash(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct 
> intel_atomic_state *state)
>  &old_cdclk_state->actual,
>  &new_cdclk_state->actual)) {
>   drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk via squasher\n");
> + "Can change cdclk via squashing\n");
>   } else if (intel_cdclk_can_crawl(dev_priv,
>&old_cdclk_state->actual,
>&new_cdclk_state->actual)) {
>   drm_dbg_kms(&dev_priv->drm,
> - "Can change cdclk via crawl\n");
> + "Can change cdclk via crawling\n");
>   } else if (pipe != INVALID_PIPE) {
>   new_cdclk_state->pipe = pipe;
>  
> -- 
> 2.25.1
>

Re: [Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

2022-10-25 Thread Balasubramani Vivekanandan

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> Driver had discrepancy in how cdclk squash and crawl support
> were checked. Like crawl, add squash as a 1 bit feature flag
> to the display section of DG2.
> 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
>  drivers/gpu/drm/i915/i915_drv.h|  1 +
>  drivers/gpu/drm/i915/i915_pci.c|  1 +
>  drivers/gpu/drm/i915/intel_device_info.h   |  1 +
>  4 files changed, 8 insertions(+), 10 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0f5add2fc51b..45babbc6290f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct 
> drm_i915_private *dev_priv)
>   skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
>  
> -static bool has_cdclk_squash(struct drm_i915_private *i915)
> -{
> - return IS_DG2(i915);
> -}
> -
>  struct intel_cdclk_vals {
>   u32 cdclk;
>   u16 refclk;
> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>  
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>  
>   if (squash_ctl & CDCLK_SQUASH_ENABLE) {
> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (has_cdclk_squash(dev_priv)) {
> + if (HAS_CDCLK_SQUASH(dev_priv)) {
>   u32 squash_ctl = 0;
>  
>   if (waveform)
> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>   expected = skl_cdclk_decimal(cdclk);
>  
>   /* Figure out what CD2X divider we should be using for this cdclk */
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   clock = dev_priv->display.cdclk.hw.vco / 2;
>   else
>   clock = dev_priv->display.cdclk.hw.cdclk;
> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (!has_cdclk_squash(dev_priv))
> + if (!HAS_CDCLK_SQUASH(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
> drm_i915_private *dev_priv,
>* the moment all platforms with squasher use a fixed cd2x
>* divider.
>*/
> - if (has_cdclk_squash(dev_priv))
> + if (HAS_CDCLK_SQUASH(dev_priv))
>   return false;
>  
>   return a->cdclk != b->cdclk &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d7b8eb9d4117..db51050e3ba2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)(DISPLAY_VER(dev_priv) >= 9 || 
> IS_BROADWELL(dev_priv))
>  
>  #define HAS_CDCLK_CRAWL(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(dev_priv)
> (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
>  #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 19bf5ef6a20d..a88e1439a426 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
>   .has_guc_deprivilege = 1, \
>   .has_heci_pxp = 1, \
>   .has_media_ratio_mode = 1, \
> + .display.has_cdclk_squash = 1, \
>   .__runtime.platform_engine_mask = \
>   BIT(RCS0) | BIT(BCS0) | \
>   BIT(VECS0) | BIT(VECS1) | \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
> b/drivers/gpu/drm/i915/intel_device_info.h
> index cdf78728dcad..67d8759c802c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
>   /* Keep in alphabetical order */ \
>   func(cursor_needs_physical); \
>   func(has_cdclk_crawl); \
> + func(has_cdclk_squash); \
>   func(has_ddi); \
>   func(has_dp_mst); \
>   func(has_dsb); \
> -- 
> 2.25.1
>

Re: [Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

2022-10-25 Thread Balasubramani Vivekanandan

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Moving segments out to simplify
> bxt_set_cdlck()
> 
> v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)
> 
> Cc: Jani Nikula 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
>  1 file changed, 25 insertions(+), 15 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 45babbc6290f..3893779e0c23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct 
> drm_i915_private *dev_priv,
>   return 0x;
>  }
>  
> +static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + icl_cdclk_pll_enable(i915, vco);
> +}
> +
> +static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
> +{
> + if (i915->display.cdclk.hw.vco != 0 &&
> + i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_disable(i915);
> +
> + if (i915->display.cdclk.hw.vco != vco)
> + bxt_de_pll_enable(i915, vco);
> +
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
> vco > 0) {
>   if (dev_priv->display.cdclk.hw.vco != vco)
>   adlp_cdclk_pll_crawl(dev_priv, vco);
> - } else if (DISPLAY_VER(dev_priv) >= 11) {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - icl_cdclk_pll_enable(dev_priv, vco);
> - } else {
> - if (dev_priv->display.cdclk.hw.vco != 0 &&
> - dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_disable(dev_priv);
> -
> - if (dev_priv->display.cdclk.hw.vco != vco)
> - bxt_de_pll_enable(dev_priv, vco);
> - }
> + } else if (DISPLAY_VER(dev_priv) >= 11)
> + icl_cdclk_pll_update(dev_priv, vco);
> + else
> + bxt_cdclk_pll_update(dev_priv, vco);
>  
>   waveform = cdclk_squash_waveform(dev_priv, cdclk);
>  
> -- 
> 2.25.1
>

Re: [Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

2022-10-25 Thread Balasubramani Vivekanandan

On 21.10.2022 14:39, Anusha Srivatsa wrote:
> No functional change. Introduce dg2_cdclk_squash_program and
> move squash_ctl register programming bits to this.
> 
> v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)
> 
> Cc: Jani Nikula 
> Cc: Balasubramani Vivekanandan 
> Cc: Ville Syrjälä 
> Signed-off-by: Anusha Srivatsa 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
>  1 file changed, 14 insertions(+), 9 deletions(-)

Reviewed-by: Balasubramani Vivekanandan 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3893779e0c23..e21cd0fbe29a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct 
> drm_i915_private *i915, int vco)
>  
>  }
>  
> +static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
> +  u16 waveform)
> +{
> + u32 squash_ctl = 0;
> +
> + if (waveform)
> + squash_ctl = CDCLK_SQUASH_ENABLE |
> +  CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> +
> + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
> +}
> +
>  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> @@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv,
>   else
>   clock = cdclk;
>  
> - if (HAS_CDCLK_SQUASH(dev_priv)) {
> - u32 squash_ctl = 0;
> -
> - if (waveform)
> - squash_ctl = CDCLK_SQUASH_ENABLE |
> - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
> -
> - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
> - }
> + if (HAS_CDCLK_SQUASH(dev_priv))
> + dg2_cdclk_squash_program(dev_priv, waveform);
>  
>   val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
>   bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> -- 
> 2.25.1
>

Re: [Intel-gfx] [PATCH] drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

2022-10-25 Thread Jani Nikula

On Tue, 25 Oct 2022, Ville Syrjala  wrote:
> From: Ville Syrjälä 
>
> If we can't dig out a fixed mode for LVDS from the VBT or EDID
> let's fall back to using the current output timings. This should
> work as long as the BIOS has (somehow) enabled the output.
>
> In this case we are dealing with the some kind of BLB based POS
> machine (Toshiba SurePOS 500) where neither the OpRegion mailbox
> nor the vbios ROM contain a valid VBT. And no EDID anywhere we
> could find either.
>
> Cc:  # v5.19+
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7301
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Jani Nikula 

But they're saying it's a regression between 4.19 and 5.10...


> ---
>  drivers/gpu/drm/i915/display/intel_panel.c |  6 ++--
>  drivers/gpu/drm/i915/display/intel_panel.h |  3 ++
>  drivers/gpu/drm/i915/display/intel_sdvo.c  | 40 ++
>  3 files changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c 
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index 69ce77711b7c..69082fbc7647 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -275,9 +275,9 @@ void intel_panel_add_edid_fixed_modes(struct 
> intel_connector *connector,
>   intel_panel_destroy_probed_modes(connector);
>  }
>  
> -static void intel_panel_add_fixed_mode(struct intel_connector *connector,
> -struct drm_display_mode *fixed_mode,
> -const char *type)
> +void intel_panel_add_fixed_mode(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode,
> + const char *type)
>  {
>   struct drm_i915_private *i915 = to_i915(connector->base.dev);
>   struct drm_display_info *info = &connector->base.display_info;
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.h 
> b/drivers/gpu/drm/i915/display/intel_panel.h
> index 5c5b5b7f95b6..964efed8ef3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.h
> +++ b/drivers/gpu/drm/i915/display/intel_panel.h
> @@ -43,6 +43,9 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state,
>   const struct drm_connector_state *conn_state);
>  int intel_panel_compute_config(struct intel_connector *connector,
>  struct drm_display_mode *adjusted_mode);
> +void intel_panel_add_fixed_mode(struct intel_connector *connector,
> + struct drm_display_mode *fixed_mode,
> + const char *type);
>  void intel_panel_add_edid_fixed_modes(struct intel_connector *connector,
> bool use_alt_fixed_modes);
>  void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector);
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c 
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index cf8e80936d8e..9ed54118b669 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -781,6 +781,13 @@ static bool intel_sdvo_get_input_timing(struct 
> intel_sdvo *intel_sdvo,
>SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
>  }
>  
> +static bool intel_sdvo_get_output_timing(struct intel_sdvo *intel_sdvo,
> +  struct intel_sdvo_dtd *dtd)
> +{
> + return intel_sdvo_get_timing(intel_sdvo,
> +  SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
> +}
> +
>  static bool
>  intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
>struct intel_sdvo_connector 
> *intel_sdvo_connector,
> @@ -2864,6 +2871,36 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, 
> int device)
>   return true;
>  }
>  
> +static void
> +intel_sdvo_add_current_fixed_mode(struct intel_sdvo *intel_sdvo,
> +   struct intel_sdvo_connector *connector)
> +{
> + struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
> + struct drm_display_mode *mode;
> + struct intel_sdvo_dtd dtd = {};
> +
> + if (!intel_sdvo_set_target_output(intel_sdvo,
> +   connector->output_flag)) {
> + drm_dbg_kms(&i915->drm, "failed to set SDVO target output\n");
> + return;
> + }
> +
> + if (!intel_sdvo_get_output_timing(intel_sdvo, &dtd)) {
> + drm_dbg_kms(&i915->drm, "failed to get SDVO output timings\n");
> + return;
> + }
> +
> + mode = drm_mode_create(&i915->drm);
> + if (!mode)
> + return;
> +
> + intel_sdvo_get_mode_from_dtd(mode, &dtd);
> +
> + drm_mode_set_name(mode);
> +
> + intel_panel_add_fixed_mode(&connector->base, mode, "current (SDVO)");
> +}
> +
>  static bool
>  intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
>  {
> @@ -2913,6 +2950,9 @@ intel_sdvo_l

[Intel-gfx] [PATCH 2/2] drm/i915/dg2: Introduce Wa_18019271663

2022-10-25 Thread Matt Atwood

Wa_18019271663 applies to all DG2 steppings and skus.

Bspec:45809

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e8372d4cd548..46035503068c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -421,9 +421,10 @@
 #define   RC_OP_FLUSH_ENABLE   (1 << 0)
 #define   HIZ_RAW_STALL_OPT_DISABLE(1 << 2)
 #define CACHE_MODE_1   _MMIO(0x7004) /* IVB+ */
-#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE(1 << 6)
-#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE(1 << 6)
-#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   (1 << 1)
+#define   MSAA_OPTIMIZATION_REDUC_DISABLE  REG_BIT(11)
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLEREG_BIT(6)
+#define   GEN8_4x4_STC_OPTIMIZATION_DISABLEREG_BIT(6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE   REG_BIT(1)
 
 #define GEN7_GT_MODE   _MMIO(0x7008)
 #define   GEN9_IZ_HASHING_MASK(slice)  (0x3 << ((slice) * 2))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ced3a26cf7e7..9f39b7758ff3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs 
*engine,
 
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
+
+   /* Wa_18019271663:dg2 */
+   wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
-- 
2.37.3

[Intel-gfx] [PATCH 1/2] drm/i915/dg2: Introduce Wa_18018764978

2022-10-25 Thread Matt Atwood

Wa_18018764978 applies to specific steppings of DG2 (G11 C0+,
G11 and G12 A0+).

Bspec: 66622

Signed-off-by: Matt Atwood 
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c..e8372d4cd548 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -448,6 +448,9 @@
 #define GEN8_L3CNTLREG _MMIO(0x7034)
 #define   GEN8_ERRDETBCTRL (1 << 9)
 
+#define PSS_MODE2  _MMIO(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL   REG_BIT(5)
+
 #define GEN7_SC_INSTDONE   _MMIO(0x7100)
 #define GEN12_SC_INSTDONE_EXTRA_MMIO(0x7104)
 #define GEN12_SC_INSTDONE_EXTRA2   _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 63e1e6becf34..ced3a26cf7e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -743,6 +743,11 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
 
+   /* Wa_18018764978:dg2 */
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+   wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
/* Wa_15010599737:dg2 */
wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
 }
-- 
2.37.3

[Intel-gfx] [PATCH 05/10] vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for vfio_file_enforced_coherent()

2022-10-25 Thread Jason Gunthorpe

iommufd doesn't establish the iommu_domains until after the device FD is
opened, even if the container has been set. This design is part of moving
away from the group centric iommu APIs.

This is fine, except that the normal sequence of establishing the kvm
wbindv won't work:

   group = open("/dev/vfio/XX")
   ioctl(group, VFIO_GROUP_SET_CONTAINER)
   ioctl(kvm, KVM_DEV_VFIO_GROUP_ADD)
   ioctl(group, VFIO_GROUP_GET_DEVICE_FD)

As the domains don't start existing until GET_DEVICE_FD. Further,
GET_DEVICE_FD requires that KVM_DEV_VFIO_GROUP_ADD already be done as that
is what sets the group->kvm and thus device->kvm for the driver to use
during open.

Now that we have device centric cap ops and the new
IOMMU_CAP_ENFORCE_CACHE_COHERENCY we know what the iommu_domain will be
capable of without having to create it. Use this to compute
vfio_file_enforced_coherent() and resolve the ordering problems.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c |  5 +++--
 drivers/vfio/vfio.h  |  2 --
 drivers/vfio/vfio_main.c | 27 ++-
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index 499777930b08fa..d97747dfb05d02 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -188,8 +188,9 @@ void vfio_device_container_unregister(struct vfio_device 
*device)
device->group->container->iommu_data, device);
 }
 
-long vfio_container_ioctl_check_extension(struct vfio_container *container,
- unsigned long arg)
+static long
+vfio_container_ioctl_check_extension(struct vfio_container *container,
+unsigned long arg)
 {
struct vfio_iommu_driver *driver;
long ret = 0;
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index 54e5a8e0834ccb..247590334e14b0 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -119,8 +119,6 @@ int vfio_container_attach_group(struct vfio_container 
*container,
 void vfio_group_detach_container(struct vfio_group *group);
 void vfio_device_container_register(struct vfio_device *device);
 void vfio_device_container_unregister(struct vfio_device *device);
-long vfio_container_ioctl_check_extension(struct vfio_container *container,
- unsigned long arg);
 int __init vfio_container_init(void);
 void vfio_container_cleanup(void);
 
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 1e414b2c48a511..a8d1fbfcc3ddad 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -1625,24 +1625,25 @@ EXPORT_SYMBOL_GPL(vfio_file_is_group);
 bool vfio_file_enforced_coherent(struct file *file)
 {
struct vfio_group *group = file->private_data;
-   bool ret;
+   struct vfio_device *device;
+   bool ret = true;
 
if (!vfio_file_is_group(file))
return true;
 
-   mutex_lock(&group->group_lock);
-   if (group->container) {
-   ret = vfio_container_ioctl_check_extension(group->container,
-  VFIO_DMA_CC_IOMMU);
-   } else {
-   /*
-* Since the coherency state is determined only once a container
-* is attached the user must do so before they can prove they
-* have permission.
-*/
-   ret = true;
+   /*
+* If the device does not have IOMMU_CAP_ENFORCE_CACHE_COHERENCY then
+* any domain later attached to it will also not support it.
+*/
+   mutex_lock(&group->device_lock);
+   list_for_each_entry(device, &group->device_list, group_next) {
+   if (!device_iommu_capable(device->dev,
+ IOMMU_CAP_ENFORCE_CACHE_COHERENCY)) {
+   ret = false;
+   break;
+   }
}
-   mutex_unlock(&group->group_lock);
+   mutex_unlock(&group->device_lock);
return ret;
 }
 EXPORT_SYMBOL_GPL(vfio_file_enforced_coherent);
-- 
2.38.0

[Intel-gfx] [PATCH 03/10] vfio: Rename vfio_device_assign/unassign_container()

2022-10-25 Thread Jason Gunthorpe

These functions don't really assign anything anymore, they just increment
some refcounts and do a sanity check. Call them
vfio_group_[un]use_container()

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c | 14 ++
 drivers/vfio/vfio.h  |  4 ++--
 drivers/vfio/vfio_main.c |  6 +++---
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index dd79a66ec62cad..499777930b08fa 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -511,10 +511,8 @@ void vfio_group_detach_container(struct vfio_group *group)
vfio_container_put(container);
 }
 
-int vfio_device_assign_container(struct vfio_device *device)
+int vfio_group_use_container(struct vfio_group *group)
 {
-   struct vfio_group *group = device->group;
-
lockdep_assert_held(&group->group_lock);
 
if (!group->container || !group->container->iommu_driver ||
@@ -529,13 +527,13 @@ int vfio_device_assign_container(struct vfio_device 
*device)
return 0;
 }
 
-void vfio_device_unassign_container(struct vfio_device *device)
+void vfio_group_unuse_container(struct vfio_group *group)
 {
-   lockdep_assert_held_write(&device->group->group_lock);
+   lockdep_assert_held(&group->group_lock);
 
-   WARN_ON(device->group->container_users <= 1);
-   device->group->container_users--;
-   fput(device->group->opened_file);
+   WARN_ON(group->container_users <= 1);
+   group->container_users--;
+   fput(group->opened_file);
 }
 
 /*
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index bcad54bbab08c4..f95f4925b83bbd 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -112,8 +112,8 @@ void vfio_unregister_iommu_driver(const struct 
vfio_iommu_driver_ops *ops);
 bool vfio_assert_device_open(struct vfio_device *device);
 
 struct vfio_container *vfio_container_from_file(struct file *filep);
-int vfio_device_assign_container(struct vfio_device *device);
-void vfio_device_unassign_container(struct vfio_device *device);
+int vfio_group_use_container(struct vfio_group *group);
+void vfio_group_unuse_container(struct vfio_group *group);
 int vfio_container_attach_group(struct vfio_container *container,
struct vfio_group *group);
 void vfio_group_detach_container(struct vfio_group *group);
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 204443ba3b3cd9..8d809ecd982b39 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -749,7 +749,7 @@ static int vfio_device_first_open(struct vfio_device 
*device)
 * it during close_device.
 */
mutex_lock(&device->group->group_lock);
-   ret = vfio_device_assign_container(device);
+   ret = vfio_group_use_container(device->group);
if (ret)
goto err_module_put;
 
@@ -764,7 +764,7 @@ static int vfio_device_first_open(struct vfio_device 
*device)
return 0;
 
 err_container:
-   vfio_device_unassign_container(device);
+   vfio_group_unuse_container(device->group);
 err_module_put:
device->kvm = NULL;
mutex_unlock(&device->group->group_lock);
@@ -781,7 +781,7 @@ static void vfio_device_last_close(struct vfio_device 
*device)
if (device->ops->close_device)
device->ops->close_device(device);
device->kvm = NULL;
-   vfio_device_unassign_container(device);
+   vfio_group_unuse_container(device->group);
mutex_unlock(&device->group->group_lock);
module_put(device->dev->driver->owner);
 }
-- 
2.38.0

[Intel-gfx] [PATCH 02/10] vfio: Move vfio_device_assign_container() into vfio_device_first_open()

2022-10-25 Thread Jason Gunthorpe

The only thing this function does is assert the group has an assigned
container and incrs refcounts.

The overall model we have is that once a conatiner_users refcount is
incremented it cannot be de-assigned from the group -
vfio_group_ioctl_unset_container() will fail and the group FD cannot be
closed.

Thus we do not need to check this on evey device FD open, just the
first. Reorganize the code so that only the first open and last close
manages the container.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/container.c |  4 ++--
 drivers/vfio/vfio_main.c | 18 --
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index d74164abbf401d..dd79a66ec62cad 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -531,11 +531,11 @@ int vfio_device_assign_container(struct vfio_device 
*device)
 
 void vfio_device_unassign_container(struct vfio_device *device)
 {
-   mutex_lock(&device->group->group_lock);
+   lockdep_assert_held_write(&device->group->group_lock);
+
WARN_ON(device->group->container_users <= 1);
device->group->container_users--;
fput(device->group->opened_file);
-   mutex_unlock(&device->group->group_lock);
 }
 
 /*
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index d043383fc3ba2b..204443ba3b3cd9 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -749,16 +749,22 @@ static int vfio_device_first_open(struct vfio_device 
*device)
 * it during close_device.
 */
mutex_lock(&device->group->group_lock);
+   ret = vfio_device_assign_container(device);
+   if (ret)
+   goto err_module_put;
+
device->kvm = device->group->kvm;
if (device->ops->open_device) {
ret = device->ops->open_device(device);
if (ret)
-   goto err_module_put;
+   goto err_container;
}
vfio_device_container_register(device);
mutex_unlock(&device->group->group_lock);
return 0;
 
+err_container:
+   vfio_device_unassign_container(device);
 err_module_put:
device->kvm = NULL;
mutex_unlock(&device->group->group_lock);
@@ -775,6 +781,7 @@ static void vfio_device_last_close(struct vfio_device 
*device)
if (device->ops->close_device)
device->ops->close_device(device);
device->kvm = NULL;
+   vfio_device_unassign_container(device);
mutex_unlock(&device->group->group_lock);
module_put(device->dev->driver->owner);
 }
@@ -784,12 +791,6 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
struct file *filep;
int ret;
 
-   mutex_lock(&device->group->group_lock);
-   ret = vfio_device_assign_container(device);
-   mutex_unlock(&device->group->group_lock);
-   if (ret)
-   return ERR_PTR(ret);
-
mutex_lock(&device->dev_set->lock);
device->open_count++;
if (device->open_count == 1) {
@@ -833,7 +834,6 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
 err_unassign_container:
device->open_count--;
mutex_unlock(&device->dev_set->lock);
-   vfio_device_unassign_container(device);
return ERR_PTR(ret);
 }
 
@@ -1040,8 +1040,6 @@ static int vfio_device_fops_release(struct inode *inode, 
struct file *filep)
device->open_count--;
mutex_unlock(&device->dev_set->lock);
 
-   vfio_device_unassign_container(device);
-
vfio_device_put_registration(device);
 
return 0;
-- 
2.38.0

[Intel-gfx] [PATCH 04/10] vfio: Move storage of allow_unsafe_interrupts to vfio_main.c

2022-10-25 Thread Jason Gunthorpe

This legacy module knob has become uAPI, when set on the vfio_iommu_type1
it disables some security protections in the iommu drivers. Move the
storage for this knob to vfio_main.c so that iommufd can access it too.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/vfio.h | 2 ++
 drivers/vfio/vfio_iommu_type1.c | 5 ++---
 drivers/vfio/vfio_main.c| 3 +++
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index f95f4925b83bbd..54e5a8e0834ccb 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -130,4 +130,6 @@ extern bool vfio_noiommu __read_mostly;
 enum { vfio_noiommu = false };
 #endif
 
+extern bool vfio_allow_unsafe_interrupts;
+
 #endif
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 23c24fe98c00d4..186e33a006d314 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -44,9 +44,8 @@
 #define DRIVER_AUTHOR   "Alex Williamson "
 #define DRIVER_DESC "Type1 IOMMU driver for VFIO"
 
-static bool allow_unsafe_interrupts;
 module_param_named(allow_unsafe_interrupts,
-  allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
+  vfio_allow_unsafe_interrupts, bool, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(allow_unsafe_interrupts,
 "Enable VFIO IOMMU support for on platforms without interrupt 
remapping support.");
 
@@ -2282,7 +2281,7 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
iommu_group_for_each_dev(iommu_group, (void 
*)IOMMU_CAP_INTR_REMAP,
 vfio_iommu_device_capable);
 
-   if (!allow_unsafe_interrupts && !msi_remap) {
+   if (!vfio_allow_unsafe_interrupts && !msi_remap) {
pr_warn("%s: No interrupt remapping support.  Use the module 
param \"allow_unsafe_interrupts\" to enable VFIO IOMMU support on this 
platform\n",
   __func__);
ret = -EPERM;
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 8d809ecd982b39..1e414b2c48a511 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -51,6 +51,9 @@ static struct vfio {
struct ida  device_ida;
 } vfio;
 
+bool vfio_allow_unsafe_interrupts;
+EXPORT_SYMBOL_GPL(vfio_allow_unsafe_interrupts);
+
 static DEFINE_XARRAY(vfio_device_set_xa);
 static const struct file_operations vfio_group_fops;
 
-- 
2.38.0

[Intel-gfx] [PATCH 00/10] Connect VFIO to IOMMUFD

2022-10-25 Thread Jason Gunthorpe

This series provides an alternative container layer for VFIO implemented
using iommufd. This is optional, if CONFIG_IOMMUFD is not set then it will
not be compiled in.

At this point iommufd can be injected by passing in a iommfd FD to
VFIO_GROUP_SET_CONTAINER which will use the VFIO compat layer in iommufd
to obtain the compat IOAS and then connect up all the VFIO drivers as
appropriate.

This is temporary stopping point, a following series will provide a way to
directly open a VFIO device FD and directly connect it to IOMMUFD using
native ioctls that can expose the IOMMUFD features like hwpt, future
vPASID and dynamic attachment.

This series, in compat mode, has passed all the qemu tests we have
available, including the test suites for the Intel GVT mdev. Aside from
the temporary limitation with P2P memory this is belived to be fully
compatible with VFIO.

This is on github: https://github.com/jgunthorpe/linux/commits/vfio_iommufd

It requires the iommufd series:

https://lore.kernel.org/r/0-v3-402a7d6459de+24b-iommufd_...@nvidia.com

Jason Gunthorpe (10):
  vfio: Move vfio_device driver open/close code to a function
  vfio: Move vfio_device_assign_container() into
vfio_device_first_open()
  vfio: Rename vfio_device_assign/unassign_container()
  vfio: Move storage of allow_unsafe_interrupts to vfio_main.c
  vfio: Use IOMMU_CAP_ENFORCE_CACHE_COHERENCY for
vfio_file_enforced_coherent()
  vfio-iommufd: Allow iommufd to be used in place of a container fd
  vfio-iommufd: Support iommufd for physical VFIO devices
  vfio-iommufd: Support iommufd for emulated VFIO devices
  vfio: Make vfio_container optionally compiled
  iommufd: Allow iommufd to supply /dev/vfio/vfio

 drivers/gpu/drm/i915/gvt/kvmgt.c  |   3 +
 drivers/iommu/iommufd/Kconfig |  12 +
 drivers/iommu/iommufd/main.c  |  35 +-
 drivers/s390/cio/vfio_ccw_ops.c   |   3 +
 drivers/s390/crypto/vfio_ap_ops.c |   3 +
 drivers/vfio/Kconfig  |  38 ++-
 drivers/vfio/Makefile |   5 +-
 drivers/vfio/container.c  | 136 ++--
 drivers/vfio/fsl-mc/vfio_fsl_mc.c |   3 +
 drivers/vfio/iommufd.c| 161 +
 .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c|   6 +
 drivers/vfio/pci/mlx5/main.c  |   3 +
 drivers/vfio/pci/vfio_pci.c   |   3 +
 drivers/vfio/platform/vfio_amba.c |   3 +
 drivers/vfio/platform/vfio_platform.c |   3 +
 drivers/vfio/vfio.h   | 100 +-
 drivers/vfio/vfio_iommu_type1.c   |   5 +-
 drivers/vfio/vfio_main.c  | 318 ++
 include/linux/vfio.h  |  39 +++
 19 files changed, 681 insertions(+), 198 deletions(-)
 create mode 100644 drivers/vfio/iommufd.c


base-commit: 3bec937e94942a6aee8854be1c1f5cc2b92d15e2
-- 
2.38.0

[Intel-gfx] [PATCH 01/10] vfio: Move vfio_device driver open/close code to a function

2022-10-25 Thread Jason Gunthorpe

This error unwind is getting complicated. Move all the code into two
pair'd function. The functions should be called when the open_count == 1
after incrementing/before decrementing.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/vfio_main.c | 95 ++--
 1 file changed, 53 insertions(+), 42 deletions(-)

diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index 2d168793d4e1ce..d043383fc3ba2b 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -734,6 +734,51 @@ bool vfio_assert_device_open(struct vfio_device *device)
return !WARN_ON_ONCE(!READ_ONCE(device->open_count));
 }
 
+static int vfio_device_first_open(struct vfio_device *device)
+{
+   int ret;
+
+   lockdep_assert_held(&device->dev_set->lock);
+
+   if (!try_module_get(device->dev->driver->owner))
+   return -ENODEV;
+
+   /*
+* Here we pass the KVM pointer with the group under the read lock.  If
+* the device driver will use it, it must obtain a reference and release
+* it during close_device.
+*/
+   mutex_lock(&device->group->group_lock);
+   device->kvm = device->group->kvm;
+   if (device->ops->open_device) {
+   ret = device->ops->open_device(device);
+   if (ret)
+   goto err_module_put;
+   }
+   vfio_device_container_register(device);
+   mutex_unlock(&device->group->group_lock);
+   return 0;
+
+err_module_put:
+   device->kvm = NULL;
+   mutex_unlock(&device->group->group_lock);
+   module_put(device->dev->driver->owner);
+   return ret;
+}
+
+static void vfio_device_last_close(struct vfio_device *device)
+{
+   lockdep_assert_held(&device->dev_set->lock);
+
+   mutex_lock(&device->group->group_lock);
+   vfio_device_container_unregister(device);
+   if (device->ops->close_device)
+   device->ops->close_device(device);
+   device->kvm = NULL;
+   mutex_unlock(&device->group->group_lock);
+   module_put(device->dev->driver->owner);
+}
+
 static struct file *vfio_device_open(struct vfio_device *device)
 {
struct file *filep;
@@ -745,29 +790,12 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
if (ret)
return ERR_PTR(ret);
 
-   if (!try_module_get(device->dev->driver->owner)) {
-   ret = -ENODEV;
-   goto err_unassign_container;
-   }
-
mutex_lock(&device->dev_set->lock);
device->open_count++;
if (device->open_count == 1) {
-   /*
-* Here we pass the KVM pointer with the group under the read
-* lock.  If the device driver will use it, it must obtain a
-* reference and release it during close_device.
-*/
-   mutex_lock(&device->group->group_lock);
-   device->kvm = device->group->kvm;
-
-   if (device->ops->open_device) {
-   ret = device->ops->open_device(device);
-   if (ret)
-   goto err_undo_count;
-   }
-   vfio_device_container_register(device);
-   mutex_unlock(&device->group->group_lock);
+   ret = vfio_device_first_open(device);
+   if (ret)
+   goto err_unassign_container;
}
mutex_unlock(&device->dev_set->lock);
 
@@ -800,20 +828,11 @@ static struct file *vfio_device_open(struct vfio_device 
*device)
 
 err_close_device:
mutex_lock(&device->dev_set->lock);
-   mutex_lock(&device->group->group_lock);
-   if (device->open_count == 1 && device->ops->close_device) {
-   device->ops->close_device(device);
-
-   vfio_device_container_unregister(device);
-   }
-err_undo_count:
-   mutex_unlock(&device->group->group_lock);
+   if (device->open_count == 1)
+   vfio_device_last_close(device);
+err_unassign_container:
device->open_count--;
-   if (device->open_count == 0 && device->kvm)
-   device->kvm = NULL;
mutex_unlock(&device->dev_set->lock);
-   module_put(device->dev->driver->owner);
-err_unassign_container:
vfio_device_unassign_container(device);
return ERR_PTR(ret);
 }
@@ -1016,19 +1035,11 @@ static int vfio_device_fops_release(struct inode 
*inode, struct file *filep)
 
mutex_lock(&device->dev_set->lock);
vfio_assert_device_open(device);
-   mutex_lock(&device->group->group_lock);
-   if (device->open_count == 1 && device->ops->close_device)
-   device->ops->close_device(device);
-
-   vfio_device_container_unregister(device);
-   mutex_unlock(&device->group->group_lock);
+   if (device->open_count == 1)
+   vfio_device_last_close(device);
device->open_count--;
-   if (device->open_count == 0)
-   d

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/edid: EDID override refactoring and fixes (rev3)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/edid: EDID override refactoring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/109579/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109579v3_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 11)
--

  Additional (2): shard-rkl shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109579v3_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ctx_shared@q-smoketest@vcs0:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-rkl-5/igt@gem_ctx_shared@q-smoket...@vcs0.html

  * igt@gem_exec_whisper@basic-contexts-priority:
- {shard-rkl}:NOTRUN -> [FAIL][2]
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-rkl-5/igt@gem_exec_whis...@basic-contexts-priority.html

  * igt@sysfs_timeslice_duration@idempotent@vcs0:
- {shard-dg1}:NOTRUN -> [FAIL][3] +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-dg1-17/igt@sysfs_timeslice_duration@idempot...@vcs0.html

  
Known issues


  Here are the changes found in Patchwork_109579v3_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#6268])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-tglb2/igt@gem_ctx_e...@basic-nohangcheck.html

  * igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-iclb1/igt@gem_exec_balan...@parallel-out-fence.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb3/igt@gem_exec_balan...@parallel-out-fence.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@gem_lmem_swapp...@parallel-random.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl:  NOTRUN -> [SKIP][10] ([fdo#109271]) +47 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_color_chamelium@ctm-limited-range:
- shard-skl:  NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_color_chamel...@ctm-limited-range.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl:  [PASS][12] -> [FAIL][13] ([i915#79])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_flip@flip-vs-expired-vbl...@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl:  [PASS][14] -> [DMESG-WARN][15] ([i915#180])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-apl3/igt@kms_flip@flip-vs-susp...@c-dp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-apl1/igt@kms_flip@flip-vs-susp...@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl:  [PASS][16] -> [FAIL][17] ([i915#2122])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12293/shard-skl9/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-skl7/igt@kms_flip@plain-flip-fb-recre...@c-edp1.html

  * 
igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#2587] / [i915#2672]) +3 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109579v3/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscal...@pipe-a-valid-mode.html

  * 
igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#2672]) +4 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tre

[Intel-gfx] [PATCH 3/4] drm/i915/display: Move chunks of code out of bxt_set_cdclk()

2022-10-25 Thread Anusha Srivatsa

No functional change. Moving segments out to simplify
bxt_set_cdlck()

v2: s/bxt_cdclk_pll/bxt_cdclk_pll_update (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 40 ++
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 45babbc6290f..3893779e0c23 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1684,6 +1684,27 @@ static u32 cdclk_squash_waveform(struct drm_i915_private 
*dev_priv,
return 0x;
 }
 
+static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   icl_cdclk_pll_enable(i915, vco);
+}
+
+static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
+{
+   if (i915->display.cdclk.hw.vco != 0 &&
+   i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_disable(i915);
+
+   if (i915->display.cdclk.hw.vco != vco)
+   bxt_de_pll_enable(i915, vco);
+
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1719,21 +1740,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && 
vco > 0) {
if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
-   } else if (DISPLAY_VER(dev_priv) >= 11) {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   icl_cdclk_pll_enable(dev_priv, vco);
-   } else {
-   if (dev_priv->display.cdclk.hw.vco != 0 &&
-   dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_disable(dev_priv);
-
-   if (dev_priv->display.cdclk.hw.vco != vco)
-   bxt_de_pll_enable(dev_priv, vco);
-   }
+   } else if (DISPLAY_VER(dev_priv) >= 11)
+   icl_cdclk_pll_update(dev_priv, vco);
+   else
+   bxt_cdclk_pll_update(dev_priv, vco);
 
waveform = cdclk_squash_waveform(dev_priv, cdclk);
 
-- 
2.25.1

[Intel-gfx] [PATCH 1/4] drm/i915/display: Change terminology for cdclk actions

2022-10-25 Thread Anusha Srivatsa

No functional changes. Changing terminology in some
print statements. s/has_cdclk_squasher/has_cdclk_squash,
s/crawler/crawl and s/squasher/squash.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad401357ab66..0f5add2fc51b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,7 +1220,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squasher(struct drm_i915_private *i915)
+static bool has_cdclk_squash(struct drm_i915_private *i915)
 {
return IS_DG2(i915);
 }
@@ -1520,7 +1520,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1747,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squasher(dev_priv)) {
+   if (has_cdclk_squash(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1845,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1976,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squasher(dev_priv))
+   if (!has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2028,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squasher(dev_priv))
+   if (has_cdclk_squash(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2754,12 +2754,12 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
   &old_cdclk_state->actual,
   &new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
-   "Can change cdclk via squasher\n");
+   "Can change cdclk via squashing\n");
} else if (intel_cdclk_can_crawl(dev_priv,
 &old_cdclk_state->actual,
 &new_cdclk_state->actual)) {
drm_dbg_kms(&dev_priv->drm,
-   "Can change cdclk via crawl\n");
+   "Can change cdclk via crawling\n");
} else if (pipe != INVALID_PIPE) {
new_cdclk_state->pipe = pipe;
 
-- 
2.25.1

[Intel-gfx] [PATCH 2/4] drm/i915/display: Introduce HAS_CDCLK_SQUASH macro

2022-10-25 Thread Anusha Srivatsa

Driver had discrepancy in how cdclk squash and crawl support
were checked. Like crawl, add squash as a 1 bit feature flag
to the display section of DG2.

Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +--
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_pci.c|  1 +
 drivers/gpu/drm/i915/intel_device_info.h   |  1 +
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0f5add2fc51b..45babbc6290f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private 
*dev_priv)
skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
 
-static bool has_cdclk_squash(struct drm_i915_private *i915)
-{
-   return IS_DG2(i915);
-}
-
 struct intel_cdclk_vals {
u32 cdclk;
u16 refclk;
@@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
 
if (squash_ctl & CDCLK_SQUASH_ENABLE) {
@@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (has_cdclk_squash(dev_priv)) {
+   if (HAS_CDCLK_SQUASH(dev_priv)) {
u32 squash_ctl = 0;
 
if (waveform)
@@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
*dev_priv)
expected = skl_cdclk_decimal(cdclk);
 
/* Figure out what CD2X divider we should be using for this cdclk */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
clock = dev_priv->display.cdclk.hw.vco / 2;
else
clock = dev_priv->display.cdclk.hw.cdclk;
@@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (!has_cdclk_squash(dev_priv))
+   if (!HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
@@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct 
drm_i915_private *dev_priv,
 * the moment all platforms with squasher use a fixed cd2x
 * divider.
 */
-   if (has_cdclk_squash(dev_priv))
+   if (HAS_CDCLK_SQUASH(dev_priv))
return false;
 
return a->cdclk != b->cdclk &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7b8eb9d4117..db51050e3ba2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv)  (DISPLAY_VER(dev_priv) >= 9 || 
IS_BROADWELL(dev_priv))
 
 #define HAS_CDCLK_CRAWL(dev_priv)   
(INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(dev_priv)  
(INTEL_INFO(dev_priv)->display.has_cdclk_squash)
 #define HAS_DDI(dev_priv)   (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) 
(INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)   (INTEL_INFO(dev_priv)->display.has_psr)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 19bf5ef6a20d..a88e1439a426 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.has_media_ratio_mode = 1, \
+   .display.has_cdclk_squash = 1, \
.__runtime.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index cdf78728dcad..67d8759c802c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ enum intel_ppgtt_type {
/* Keep in alphabetical order */ \
func(cursor_needs_physical); \
func(has_cdclk_crawl); \
+   func(has_cdclk_squash); \
func(has_ddi); \
func(has_dp_mst); \
func(has_dsb); \
-- 
2.25.1

[Intel-gfx] [PATCH 4/4] drm/i915/display: Move squash_ctl register programming to its own function

2022-10-25 Thread Anusha Srivatsa

No functional change. Introduce dg2_cdclk_squash_program and
move squash_ctl register programming bits to this.

v2: s/dg2_cdclk_squash_programming/dg2_cdclk_squash_program (Jani)

Cc: Jani Nikula 
Cc: Balasubramani Vivekanandan 
Cc: Ville Syrjälä 
Signed-off-by: Anusha Srivatsa 
Reviewed-by: Balasubramani Vivekanandan 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +-
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3893779e0c23..e21cd0fbe29a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1705,6 +1705,18 @@ static void bxt_cdclk_pll_update(struct drm_i915_private 
*i915, int vco)
 
 }
 
+static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
+u16 waveform)
+{
+   u32 squash_ctl = 0;
+
+   if (waveform)
+   squash_ctl = CDCLK_SQUASH_ENABLE |
+CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+
+   intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
+}
+
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
@@ -1752,15 +1764,8 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
else
clock = cdclk;
 
-   if (HAS_CDCLK_SQUASH(dev_priv)) {
-   u32 squash_ctl = 0;
-
-   if (waveform)
-   squash_ctl = CDCLK_SQUASH_ENABLE |
-   CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-   intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
-   }
+   if (HAS_CDCLK_SQUASH(dev_priv))
+   dg2_cdclk_squash_program(dev_priv, waveform);
 
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/sdvo: Fallback to current output timings for LVDS fixed mode
URL   : https://patchwork.freedesktop.org/series/110130/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110130v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/index.html

Participating hosts (40 -> 37)
--

  Additional (1): fi-skl-guc 
  Missing(4): fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus fi-pnv-d510 

Known issues


  Here are the changes found in Patchwork_110130v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_setmode@basic-clone-single-crtc:
- fi-skl-guc: NOTRUN -> [SKIP][4] ([fdo#109271]) +10 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-skl-guc/igt@kms_setm...@basic-clone-single-crtc.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][5] ([i915#6687]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][7] ([i915#3303] / [i915#4785]) -> 
[PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][9] ([i915#6367]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][11] ([i915#6298]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110130v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687


Build changes
-

  * Linux: CI_DRM_12294 -> Patchwork_110130v1

  CI-20190529: 20190529
  CI_DRM_12294: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110130v1: fca30d6149441ff1

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Patchwork

== Series Details ==

Series: Revert "drm/i915/uapi: expose GTT alignment"
URL   : https://patchwork.freedesktop.org/series/110041/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html

Participating hosts (41 -> 42)
--

  Additional (4): fi-kbl-soraka fi-hsw-4770 fi-icl-u2 bat-atsm-1 
  Missing(3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_110041v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@engines@contexts:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-ehl-2/igt@gem_exec_parallel@engi...@contexts.html

  
Known issues


  Here are the changes found in Patchwork_110041v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_gttfill@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271]) +9 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_exec_gttf...@basic.html
- fi-pnv-d510:[PASS][4] -> [FAIL][5] ([i915#7229])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-pnv-d510/igt@gem_exec_gttf...@basic.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-pnv-d510/igt@gem_exec_gttf...@basic.html

  * igt@gem_huc_copy@huc-copy:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_render_tiled_blits@basic:
- fi-apl-guc: [PASS][10] -> [INCOMPLETE][11] ([i915#7056])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-apl-guc/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271]) +9 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@gem_soft...@allocator-basic-reserve.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  NOTRUN -> [DMESG-WARN][13] ([i915#1982])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3012])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][15] ([i915#1886])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:NOTRUN -> [INCOMPLETE][16] ([i915#4785])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@hugepages:
- fi-glk-j4005:   [PASS][17] -> [DMESG-FAIL][18] ([i915#7311])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-glk-j4005/igt@i915_selftest@l...@hugepages.html
- fi-rkl-guc: [PASS][19] -> [DMESG-FAIL][20] ([i915#7311])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12284/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html
- fi-icl-u2:  NOTRUN -> [DMESG-FAIL][21] ([i915#7311])
   [21

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Dixit, Ashutosh

On Tue, 25 Oct 2022 02:25:06 -0700, Andi Shyti wrote:
>
> Hi Ashutosh,

Hi Andi :)

> > > If a non-constant variable is used as the first argument of the FIELD_PREP
> > > macro, a build error occurs when using the clang compiler.

A "non-constant variable" does not seem to be the cause of the compile
error with clang, see below.

>
> > > drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> > > constant 18446744073709551615 with expression of type 'typeof 
> > > (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> > > char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> > > short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> > > int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> > > long long: (unsigned long long)0, long long: (unsigned long long)0, 
> > > default: (field_msk)))' (aka 'unsigned int') is always false 
> > > [-Werror,-Wtautological-constant-out-of-range-compare]
> >
> > What is 18446744073709551615? You may want to limit the length of this line
> > or checkpatch doesn't complain?
>
> yeah! I am not a clang user, and this must be some ugly error
> output. I don't think it makes sense to break it, though.

18446744073709551615 == ~0ull (see use in __BF_FIELD_CHECK).

>
> > > bits_to_set = FIELD_PREP(field_msk, nval);
> > >   ^~~
> > > ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> > > __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> > > ^~~
> > > ./include/linux/bitfield.h:71:53: note: expanded from macro 
> > > '__BF_FIELD_CHECK'
> > > BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \

So clang seems to break here at this line in __BF_FIELD_CHECK (note ~0ull
also occurs here):

BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
 __bf_cast_unsigned(_reg, ~0ull),   \
 _pfx "type of reg too small for mask"); \

So it goes through previous checks including the "mask is not constant"
check. As Nick Desaulniers mentions "__builtin_constant_p is evaluated
after most optimizations have run" so by that time both compilers (gcc and
clang) have figured out that even though _mask is coming in as function
argument it is really the constant below:

#define   PKG_PWR_LIM_1 REG_GENMASK(14, 0)

But it is not clear why clang chokes on this "type of reg too small for
mask" check (and gcc doesn't) since everything is u32.

It is for this reason I want someone from llvm to chime in.

> > > ~~^~~
> > > ./include/linux/build_bug.h:39:58: note: expanded from macro 
> > > 'BUILD_BUG_ON_MSG'
> > > ~^~~
> > > ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> > > 'compiletime_assert'
> > > _compiletime_assert(condition, msg, __compiletime_assert_, 
> > > __COUNTER__)
> > > 
> > > ^~~
> > > ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> > > '_compiletime_assert'
> > > __compiletime_assert(condition, msg, prefix, suffix)
> > > ~^~~
> > > ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> > > '__compiletime_assert'
> > > if (!(condition))   \
> > >
> > > Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> > > Cc: Ashutosh Dixit 
> > > Cc: Anshuman Gupta 
> > > Cc: Andi Shyti 
> > > Signed-off-by: Gwan-gyeong Mun 
> > > ---
> > >  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> > >  1 file changed, 3 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> > > b/drivers/gpu/drm/i915/i915_hwmon.c
> > > index 9e9781493025..782a621b1928 100644
> > > --- a/drivers/gpu/drm/i915/i915_hwmon.c
> > > +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> > > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> > > i915_reg_t rgadr,
> > >
> > >  static void
> > >  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> > > -   u32 field_msk, int nshift,
> > > -   unsigned int scale_factor, long lval)
> > > +   int nshift, unsigned int scale_factor, long lval)
> > >  {
> > >   u32 nval;
> > > - u32 bits_to_clear;
> > > - u32 bits_to_set;
> > >
> > >   /* Computation in 64-bits to avoid overflow. Round to nearest. */
> > >   nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> > >
> > > - bits_to_clear = field_msk;
> > > - bits_to_set = FIELD_PREP(field_msk, nval);
> > > -
> > >   hwm_locked_with_pm_

Re: [Intel-gfx] [PATCH] drm/i915/hwmon: Fix a build error used with clang compiler

2022-10-25 Thread Dixit, Ashutosh

On Tue, 25 Oct 2022 07:30:49 -0700, Jani Nikula wrote:
>
> On Tue, 25 Oct 2022, Jani Nikula  wrote:
> > On Tue, 25 Oct 2022, Gwan-gyeong Mun  wrote:
> >> If a non-constant variable is used as the first argument of the FIELD_PREP
> >> macro, a build error occurs when using the clang compiler.
> >>
> >> Fix the following build error used with clang compiler:
> >>
> >> drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of 
> >> constant 18446744073709551615 with expression of type 'typeof 
> >> (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned 
> >> char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, 
> >> short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned 
> >> int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned 
> >> long long: (unsigned long long)0, long long: (unsigned long long)0, 
> >> default: (field_msk)))' (aka 'unsigned int') is always false 
> >> [-Werror,-Wtautological-constant-out-of-range-compare]
> >> bits_to_set = FIELD_PREP(field_msk, nval);
> >>   ^~~
> >> ./include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP'
> >> __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\
> >> ^~~
> >> ./include/linux/bitfield.h:71:53: note: expanded from macro 
> >> '__BF_FIELD_CHECK'
> >> BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \
> >> ~~^~~
> >> ./include/linux/build_bug.h:39:58: note: expanded from macro 
> >> 'BUILD_BUG_ON_MSG'
> >> ~^~~
> >> ./include/linux/compiler_types.h:357:22: note: expanded from macro 
> >> 'compiletime_assert'
> >> _compiletime_assert(condition, msg, __compiletime_assert_, 
> >> __COUNTER__)
> >> 
> >> ^~~
> >> ./include/linux/compiler_types.h:345:23: note: expanded from macro 
> >> '_compiletime_assert'
> >> __compiletime_assert(condition, msg, prefix, suffix)
> >> ~^~~
> >> ./include/linux/compiler_types.h:337:9: note: expanded from macro 
> >> '__compiletime_assert'
> >> if (!(condition))   \
> >>
> >> Fixes: 99f55efb7911 ("drm/i915/hwmon: Power PL1 limit and TDP setting")
> >> Cc: Ashutosh Dixit 
> >> Cc: Anshuman Gupta 
> >> Cc: Andi Shyti 
> >> Signed-off-by: Gwan-gyeong Mun 
> >> ---
> >>  drivers/gpu/drm/i915/i915_hwmon.c | 12 +++-
> >>  1 file changed, 3 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
> >> b/drivers/gpu/drm/i915/i915_hwmon.c
> >> index 9e9781493025..782a621b1928 100644
> >> --- a/drivers/gpu/drm/i915/i915_hwmon.c
> >> +++ b/drivers/gpu/drm/i915/i915_hwmon.c
> >> @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, 
> >> i915_reg_t rgadr,
> >>
> >>  static void
> >>  hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr,
> >> -u32 field_msk, int nshift,
> >> -unsigned int scale_factor, long lval)
> >> +int nshift, unsigned int scale_factor, long lval)
> >>  {
> >>u32 nval;
> >> -  u32 bits_to_clear;
> >> -  u32 bits_to_set;
> >>
> >>/* Computation in 64-bits to avoid overflow. Round to nearest. */
> >>nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor);
> >>
> >> -  bits_to_clear = field_msk;
> >> -  bits_to_set = FIELD_PREP(field_msk, nval);
> >
> > Please just switch to REG_FIELD_PREP() and it should be fine.
>
> Actually, probably not, but please switch to it anyway. ;)

This is what happens with REG_FIELD_PREP(), that is why we went ahead with
FIELD_PREP(). So REG_FIELD_PREP is not an option.

  CC [M]  drivers/gpu/drm/i915/i915_hwmon.o
In file included from ./include/linux/bits.h:22,
 from ./include/linux/bitops.h:6,
 from ./include/linux/hwmon.h:15,
 from drivers/gpu/drm/i915/i915_hwmon.c:6:
drivers/gpu/drm/i915/i915_hwmon.c: In function ‘hwm_field_scale_and_write’:
./include/linux/build_bug.h:16:51: error: negative width in bit-field 
‘’
   16 | #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); })))
  |   ^
./drivers/gpu/drm/i915/i915_reg_defs.h:72:16: note: in expansion of macro 
‘BUILD_BUG_ON_ZERO’
   72 |BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + 
\
  |^
drivers/gpu/drm/i915/i915_hwmon.c:115:23: note: in expansion of macro 
‘REG_FIELD_PREP’
  115 | bits_to_set = REG_FIELD_PREP(field_msk, nval);
  |   ^~
./include/linux/build_bug.h:16:51: error: bit-fiel

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

2022-10-25 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/110131/
State : warning

== Summary ==

Error: dim checkpatch failed
c5d85fb8644b drm/i915/dg2: Introduce Wa_18018764978
-:37: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#37: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:748:
+   if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+   IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
99f313e60fa1 drm/i915/dg2: Introduce Wa_18019271663

[Intel-gfx] [PATCH 10/10] iommufd: Allow iommufd to supply /dev/vfio/vfio

2022-10-25 Thread Jason Gunthorpe

If the VFIO container is compiled out, give a kconfig option for iommufd
to provide the miscdev node with the same name and permissions as vfio
uses.

The compatibility node supports the same ioctls as VFIO and automatically
enables the VFIO compatible pinned page accounting mode.

Signed-off-by: Jason Gunthorpe 
---
 drivers/iommu/iommufd/Kconfig | 12 
 drivers/iommu/iommufd/main.c  | 35 ---
 2 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/iommufd/Kconfig b/drivers/iommu/iommufd/Kconfig
index f0a2012234fa09..afc83b7575cce6 100644
--- a/drivers/iommu/iommufd/Kconfig
+++ b/drivers/iommu/iommufd/Kconfig
@@ -14,6 +14,18 @@ config IOMMUFD
  If you don't know what to do here, say N.
 
 if IOMMUFD
+config IOMMUFD_VFIO_CONTAINER
+   bool "IOMMUFD provides the VFIO container /dev/vfio/vfio"
+   depends on VFIO && !VFIO_CONTAINER
+   default VFIO && !VFIO_CONTAINER
+   help
+ IOMMUFD will provide /dev/vfio/vfio instead of VFIO. This relies on
+ IOMMUFD providing compatibility emulation to give the same ioctls.
+ It provides an option to build a kernel with legacy VFIO components
+ removed.
+
+ Unless testing IOMMUFD say N here.
+
 config IOMMUFD_TEST
bool "IOMMU Userspace API Test support"
depends on RUNTIME_TESTING_MENU
diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c
index 8a31c1a14cdd53..19db81fbf7f08f 100644
--- a/drivers/iommu/iommufd/main.c
+++ b/drivers/iommu/iommufd/main.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 
+#include "io_pagetable.h"
 #include "iommufd_private.h"
 #include "iommufd_test.h"
 
@@ -31,6 +32,7 @@ struct iommufd_object_ops {
void (*destroy)(struct iommufd_object *obj);
 };
 static struct iommufd_object_ops iommufd_object_ops[];
+static struct miscdevice vfio_misc_dev;
 
 struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx,
 size_t size,
@@ -167,6 +169,13 @@ static int iommufd_fops_open(struct inode *inode, struct 
file *filp)
if (!ictx)
return -ENOMEM;
 
+   /*
+* For compatibility with VFIO when /dev/vfio/vfio is opened we default
+* to the same rlimit accounting as vfio uses.
+*/
+   if (filp->private_data == &vfio_misc_dev)
+   ictx->account_mode = IOPT_PAGES_ACCOUNT_MM;
+
xa_init_flags(&ictx->objects, XA_FLAGS_ALLOC1 | XA_FLAGS_ACCOUNT);
ictx->file = filp;
filp->private_data = ictx;
@@ -392,26 +401,46 @@ static struct miscdevice iommu_misc_dev = {
.mode = 0660,
 };
 
+
+static struct miscdevice vfio_misc_dev = {
+   .minor = VFIO_MINOR,
+   .name = "vfio",
+   .fops = &iommufd_fops,
+   .nodename = "vfio/vfio",
+   .mode = 0666,
+};
+
 static int __init iommufd_init(void)
 {
int ret;
 
ret = misc_register(&iommu_misc_dev);
-   if (ret) {
-   pr_err("Failed to register misc device\n");
+   if (ret)
return ret;
-   }
 
+   if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)) {
+   ret = misc_register(&vfio_misc_dev);
+   if (ret)
+   goto err_misc;
+   }
return 0;
+err_misc:
+   misc_deregister(&iommu_misc_dev);
+   return ret;
 }
 
 static void __exit iommufd_exit(void)
 {
+   if (IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER))
+   misc_deregister(&vfio_misc_dev);
misc_deregister(&iommu_misc_dev);
 }
 
 module_init(iommufd_init);
 module_exit(iommufd_exit);
 
+#if IS_ENABLED(CONFIG_IOMMUFD_VFIO_CONTAINER)
+MODULE_ALIAS_MISCDEV(VFIO_MINOR);
+#endif
 MODULE_DESCRIPTION("I/O Address Space Management for passthrough devices");
 MODULE_LICENSE("GPL");
-- 
2.38.0

[Intel-gfx] [PATCH 08/10] vfio-iommufd: Support iommufd for emulated VFIO devices

2022-10-25 Thread Jason Gunthorpe

Emulated VFIO devices are calling vfio_register_emulated_iommu_dev() and
consist of all the mdev drivers.

Like the physical drivers, support for iommufd is provided by the driver
supplying the correct correct standard ops. Provide ops from the core that
duplicate what vfio_register_emulated_iommu_dev() does.

Emulated drivers are where it is more likely to see variation in the
iommfd support ops. For instance IDXD will probably need to setup both a
iommfd_device context linked to a PASID and an iommufd_access context to
support all their mdev operations.

Signed-off-by: Jason Gunthorpe 
---
 drivers/gpu/drm/i915/gvt/kvmgt.c  |   3 +
 drivers/s390/cio/vfio_ccw_ops.c   |   3 +
 drivers/s390/crypto/vfio_ap_ops.c |   3 +
 drivers/vfio/container.c  | 108 ++---
 drivers/vfio/iommufd.c|  57 
 drivers/vfio/vfio.h   |  10 ++-
 drivers/vfio/vfio_main.c  | 110 +-
 include/linux/vfio.h  |  14 
 8 files changed, 217 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 7a45e5360caf2d..579b230a0f58d9 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1474,6 +1474,9 @@ static const struct vfio_device_ops intel_vgpu_dev_ops = {
.mmap   = intel_vgpu_mmap,
.ioctl  = intel_vgpu_ioctl,
.dma_unmap  = intel_vgpu_dma_unmap,
+   .bind_iommufd   = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas= vfio_iommufd_emulated_attach_ioas,
 };
 
 static int intel_vgpu_probe(struct mdev_device *mdev)
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index 6ae4d012d80084..560453d99c24fc 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -588,6 +588,9 @@ static const struct vfio_device_ops vfio_ccw_dev_ops = {
.ioctl = vfio_ccw_mdev_ioctl,
.request = vfio_ccw_mdev_request,
.dma_unmap = vfio_ccw_dma_unmap,
+   .bind_iommufd = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas = vfio_iommufd_emulated_attach_ioas,
 };
 
 struct mdev_driver vfio_ccw_mdev_driver = {
diff --git a/drivers/s390/crypto/vfio_ap_ops.c 
b/drivers/s390/crypto/vfio_ap_ops.c
index 0b4cc8c597ae67..bb7776d207924f 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -1789,6 +1789,9 @@ static const struct vfio_device_ops 
vfio_ap_matrix_dev_ops = {
.close_device = vfio_ap_mdev_close_device,
.ioctl = vfio_ap_mdev_ioctl,
.dma_unmap = vfio_ap_mdev_dma_unmap,
+   .bind_iommufd = vfio_iommufd_emulated_bind,
+   .unbind_iommufd = vfio_iommufd_emulated_unbind,
+   .attach_ioas = vfio_iommufd_emulated_attach_ioas,
 };
 
 static struct mdev_driver vfio_ap_matrix_driver = {
diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index 8772dad6808539..0388f2e33447eb 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -540,113 +540,45 @@ void vfio_group_unuse_container(struct vfio_group *group)
fput(group->opened_file);
 }
 
-/*
- * Pin contiguous user pages and return their associated host pages for local
- * domain only.
- * @device [in]  : device
- * @iova [in]: starting IOVA of user pages to be pinned.
- * @npage [in]   : count of pages to be pinned.  This count should not
- *be greater than VFIO_PIN_PAGES_MAX_ENTRIES.
- * @prot [in]: protection flags
- * @pages[out]   : array of host pages
- * Return error or number of pages pinned.
- *
- * A driver may only call this function if the vfio_device was created
- * by vfio_register_emulated_iommu_dev().
- */
-int vfio_pin_pages(struct vfio_device *device, dma_addr_t iova,
-  int npage, int prot, struct page **pages)
+int vfio_container_pin_pages(struct vfio_container *container,
+struct iommu_group *iommu_group, dma_addr_t iova,
+int npage, int prot, struct page **pages)
 {
-   struct vfio_container *container;
-   struct vfio_group *group = device->group;
-   struct vfio_iommu_driver *driver;
-   int ret;
-
-   if (!pages || !npage || !vfio_assert_device_open(device))
-   return -EINVAL;
+   /* group->container cannot change while a vfio device is open */
+   struct vfio_iommu_driver *driver = container->iommu_driver;
 
if (npage > VFIO_PIN_PAGES_MAX_ENTRIES)
return -E2BIG;
 
/* group->container cannot change while a vfio device is open */
-   container = group->container;
driver = container->iommu_driver;
-   if (likely(driver && driver->ops->pin_pages))
-   ret = driver->ops->pin_pages(container->iommu_data,
-group->iom

[Intel-gfx] [PATCH 07/10] vfio-iommufd: Support iommufd for physical VFIO devices

2022-10-25 Thread Jason Gunthorpe

This creates the iommufd_device for the physical VFIO drivers. These are
all the drivers that are calling vfio_register_group_dev() and expect the
type1 code to setup a real iommu_domain against their parent struct
device.

The design gives the driver a choice in how it gets connected to iommufd
by providing bind_iommufd/unbind_iommufd/attach_ioas callbacks to
implement as required. The core code provides three default callbacks for
physical mode using a real iommu_domain. This is suitable for drivers
using vfio_register_group_dev()

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Makefile |   1 +
 drivers/vfio/fsl-mc/vfio_fsl_mc.c |   3 +
 drivers/vfio/iommufd.c| 104 ++
 .../vfio/pci/hisilicon/hisi_acc_vfio_pci.c|   6 +
 drivers/vfio/pci/mlx5/main.c  |   3 +
 drivers/vfio/pci/vfio_pci.c   |   3 +
 drivers/vfio/platform/vfio_amba.c |   3 +
 drivers/vfio/platform/vfio_platform.c |   3 +
 drivers/vfio/vfio.h   |  15 +++
 drivers/vfio/vfio_main.c  |  13 ++-
 include/linux/vfio.h  |  25 +
 11 files changed, 177 insertions(+), 2 deletions(-)
 create mode 100644 drivers/vfio/iommufd.c

diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
index b693a1169286f8..3863922529ef20 100644
--- a/drivers/vfio/Makefile
+++ b/drivers/vfio/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_VFIO) += vfio.o
 vfio-y += vfio_main.o \
  iova_bitmap.o \
  container.o
+vfio-$(CONFIG_IOMMUFD) += iommufd.o
 
 obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o
 obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o
diff --git a/drivers/vfio/fsl-mc/vfio_fsl_mc.c 
b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
index b16874e913e4f5..5cd4bb47644039 100644
--- a/drivers/vfio/fsl-mc/vfio_fsl_mc.c
+++ b/drivers/vfio/fsl-mc/vfio_fsl_mc.c
@@ -592,6 +592,9 @@ static const struct vfio_device_ops vfio_fsl_mc_ops = {
.read   = vfio_fsl_mc_read,
.write  = vfio_fsl_mc_write,
.mmap   = vfio_fsl_mc_mmap,
+   .bind_iommufd   = vfio_iommufd_physical_bind,
+   .unbind_iommufd = vfio_iommufd_physical_unbind,
+   .attach_ioas= vfio_iommufd_physical_attach_ioas,
 };
 
 static struct fsl_mc_driver vfio_fsl_mc_driver = {
diff --git a/drivers/vfio/iommufd.c b/drivers/vfio/iommufd.c
new file mode 100644
index 00..8280bb32ee677c
--- /dev/null
+++ b/drivers/vfio/iommufd.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES
+ */
+#include 
+#include 
+
+#include "vfio.h"
+
+MODULE_IMPORT_NS(IOMMUFD);
+MODULE_IMPORT_NS(IOMMUFD_VFIO);
+
+int vfio_iommufd_bind(struct vfio_device *vdev, struct iommufd_ctx *ictx)
+{
+   u32 ioas_id;
+   u32 device_id;
+   int ret;
+
+   lockdep_assert_held(&vdev->dev_set->lock);
+
+   /*
+* If the driver doesn't provide this op then it means the device does
+* not do DMA at all. So nothing to do.
+*/
+   if (!vdev->ops->bind_iommufd)
+   return 0;
+
+   ret = vdev->ops->bind_iommufd(vdev, ictx, &device_id);
+   if (ret)
+   return ret;
+
+   if (vdev->ops->attach_ioas) {
+   ret = iommufd_vfio_compat_ioas_id(ictx, &ioas_id);
+   if (ret)
+   goto err_unbind;
+   ret = vdev->ops->attach_ioas(vdev, &ioas_id);
+   if (ret)
+   goto err_unbind;
+   vdev->iommufd_attached = true;
+   }
+
+   /*
+* The legacy path has no way to return the device id or the selected
+* pt_id
+*/
+   return 0;
+
+err_unbind:
+   if (vdev->ops->unbind_iommufd)
+   vdev->ops->unbind_iommufd(vdev);
+   return ret;
+}
+
+void vfio_iommufd_unbind(struct vfio_device *vdev)
+{
+   lockdep_assert_held(&vdev->dev_set->lock);
+
+   if (!vdev->iommufd_device)
+   return;
+
+   if (vdev->ops->unbind_iommufd)
+   vdev->ops->unbind_iommufd(vdev);
+}
+
+/*
+ * The physical standard ops mean that the iommufd_device is bound to the
+ * physical device vdev->dev that was provided to vfio_init_group_dev(). 
Drivers
+ * using this ops set should call vfio_register_group_dev()
+ */
+int vfio_iommufd_physical_bind(struct vfio_device *vdev,
+  struct iommufd_ctx *ictx, u32 *out_device_id)
+{
+   struct iommufd_device *idev;
+
+   idev = iommufd_device_bind(ictx, vdev->dev, out_device_id);
+   if (IS_ERR(idev))
+   return PTR_ERR(idev);
+   vdev->iommufd_device = idev;
+   return 0;
+}
+EXPORT_SYMBOL_GPL(vfio_iommufd_physical_bind);
+
+void vfio_iommufd_physical_unbind(struct vfio_device *vdev)
+{
+   lockdep_assert_held(&vdev->dev_set->lock);
+
+   if (vdev->iommufd_attached) {
+   iommufd_device_d

[Intel-gfx] [PATCH 06/10] vfio-iommufd: Allow iommufd to be used in place of a container fd

2022-10-25 Thread Jason Gunthorpe

This makes VFIO_GROUP_SET_CONTAINER accept both a vfio container FD and an
iommufd.

In iommufd mode an IOAS will exist after the SET_CONTAINER, but it will
not be attached to any groups.

>From a VFIO perspective this means that the VFIO_GROUP_GET_STATUS and
VFIO_GROUP_FLAGS_VIABLE works subtly differently. With the container FD
the iommu_group_claim_dma_owner() is done during SET_CONTAINER but for
IOMMFD this is done during VFIO_GROUP_GET_DEVICE_FD. Meaning that
VFIO_GROUP_FLAGS_VIABLE could be set but GET_DEVICE_FD will fail due to
viability.

As GET_DEVICE_FD can fail for many reasons already this is not expected to
be a meaningful difference.

Reorganize the tests for if the group has an assigned container or iommu
into a vfio_group_has_iommu() function and consolidate all the duplicated
WARN_ON's etc related to this.

Call container functions only if a container is actually present on the
group.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Kconfig |  1 +
 drivers/vfio/container.c |  7 ++--
 drivers/vfio/vfio.h  |  2 ++
 drivers/vfio/vfio_main.c | 76 
 4 files changed, 69 insertions(+), 17 deletions(-)

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index 86c381ceb9a1e9..1118d322eec97d 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -2,6 +2,7 @@
 menuconfig VFIO
tristate "VFIO Non-Privileged userspace driver framework"
select IOMMU_API
+   depends on IOMMUFD || !IOMMUFD
select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
select INTERVAL_TREE
help
diff --git a/drivers/vfio/container.c b/drivers/vfio/container.c
index d97747dfb05d02..8772dad6808539 100644
--- a/drivers/vfio/container.c
+++ b/drivers/vfio/container.c
@@ -516,8 +516,11 @@ int vfio_group_use_container(struct vfio_group *group)
 {
lockdep_assert_held(&group->group_lock);
 
-   if (!group->container || !group->container->iommu_driver ||
-   WARN_ON(!group->container_users))
+   /*
+* The container fd has been assigned with VFIO_GROUP_SET_CONTAINER but
+* VFIO_SET_IOMMU hasn't been done yet.
+*/
+   if (!group->container->iommu_driver)
return -EINVAL;
 
if (group->type == VFIO_NO_IOMMU && !capable(CAP_SYS_RAWIO))
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index 247590334e14b0..985e13d52989ca 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -10,6 +10,7 @@
 #include 
 #include 
 
+struct iommufd_ctx;
 struct iommu_group;
 struct vfio_device;
 struct vfio_container;
@@ -60,6 +61,7 @@ struct vfio_group {
struct kvm  *kvm;
struct file *opened_file;
struct blocking_notifier_head   notifier;
+   struct iommufd_ctx  *iommufd;
 };
 
 /* events for the backend driver notify callback */
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index a8d1fbfcc3ddad..cf0ea744de931e 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "vfio.h"
 
 #define DRIVER_VERSION "0.3"
@@ -665,6 +666,16 @@ EXPORT_SYMBOL_GPL(vfio_unregister_group_dev);
 /*
  * VFIO Group fd, /dev/vfio/$GROUP
  */
+static bool vfio_group_has_iommu(struct vfio_group *group)
+{
+   lockdep_assert_held(&group->group_lock);
+   if (!group->container)
+   WARN_ON(group->container_users);
+   else
+   WARN_ON(!group->container_users);
+   return group->container || group->iommufd;
+}
+
 /*
  * VFIO_GROUP_UNSET_CONTAINER should fail if there are other users or
  * if there was no container to unset.  Since the ioctl is called on
@@ -676,15 +687,21 @@ static int vfio_group_ioctl_unset_container(struct 
vfio_group *group)
int ret = 0;
 
mutex_lock(&group->group_lock);
-   if (!group->container) {
+   if (!vfio_group_has_iommu(group)) {
ret = -EINVAL;
goto out_unlock;
}
-   if (group->container_users != 1) {
-   ret = -EBUSY;
-   goto out_unlock;
+   if (group->container) {
+   if (group->container_users != 1) {
+   ret = -EBUSY;
+   goto out_unlock;
+   }
+   vfio_group_detach_container(group);
+   }
+   if (group->iommufd) {
+   iommufd_ctx_put(group->iommufd);
+   group->iommufd = NULL;
}
-   vfio_group_detach_container(group);
 
 out_unlock:
mutex_unlock(&group->group_lock);
@@ -695,6 +712,7 @@ static int vfio_group_ioctl_set_container(struct vfio_group 
*group,
  int __user *arg)
 {
struct vfio_container *container;
+   struct iommufd_ctx *iommufd;
struct fd f;
int ret;
int fd;
@@ -707,7 +725,7 @@ static int vfio_group_ioctl_set_container(struct vfio_gr

[Intel-gfx] [PATCH 09/10] vfio: Make vfio_container optionally compiled

2022-10-25 Thread Jason Gunthorpe

Add a kconfig CONFIG_VFIO_CONTAINER that controls compiling the container
code. If 'n' then only iommufd will provide the container service. All the
support for vfio iommu drivers, including type1, will not be built.

This allows a compilation check that no inappropriate dependencies between
the device/group and container have been created.

Signed-off-by: Jason Gunthorpe 
---
 drivers/vfio/Kconfig  | 37 
 drivers/vfio/Makefile |  4 +--
 drivers/vfio/vfio.h   | 65 +++
 3 files changed, 92 insertions(+), 14 deletions(-)

diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig
index 1118d322eec97d..d384419d151dda 100644
--- a/drivers/vfio/Kconfig
+++ b/drivers/vfio/Kconfig
@@ -3,8 +3,8 @@ menuconfig VFIO
tristate "VFIO Non-Privileged userspace driver framework"
select IOMMU_API
depends on IOMMUFD || !IOMMUFD
-   select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
select INTERVAL_TREE
+   select VFIO_CONTAINER if IOMMUFD=n
help
  VFIO provides a framework for secure userspace device drivers.
  See Documentation/driver-api/vfio.rst for more details.
@@ -12,25 +12,27 @@ menuconfig VFIO
  If you don't know what to do here, say N.
 
 if VFIO
+config VFIO_CONTAINER
+   bool "Support for the VFIO container /dev/vfio/vfio"
+   select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64)
+   default y
+   help
+ The VFIO container is the classic interface to VFIO for establishing
+ mappings. If N is selected here then IOMMUFD must be used the manage
+ the mappings.
+
+ Unless testing IOMMUFD say Y here.
+
+if VFIO_CONTAINER
 config VFIO_IOMMU_TYPE1
tristate
-   default n
+   default MMU && (X86 || S390 || ARM || ARM64)
 
 config VFIO_IOMMU_SPAPR_TCE
tristate
depends on SPAPR_TCE_IOMMU
default VFIO
 
-config VFIO_SPAPR_EEH
-   tristate
-   depends on EEH && VFIO_IOMMU_SPAPR_TCE
-   default VFIO
-
-config VFIO_VIRQFD
-   tristate
-   select EVENTFD
-   default n
-
 config VFIO_NOIOMMU
bool "VFIO No-IOMMU support"
help
@@ -44,6 +46,17 @@ config VFIO_NOIOMMU
  this mode since there is no IOMMU to provide DMA translation.
 
  If you don't know what to do here, say N.
+endif
+
+config VFIO_SPAPR_EEH
+   tristate
+   depends on EEH && VFIO_IOMMU_SPAPR_TCE
+   default VFIO
+
+config VFIO_VIRQFD
+   tristate
+   select EVENTFD
+   default n
 
 source "drivers/vfio/pci/Kconfig"
 source "drivers/vfio/platform/Kconfig"
diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile
index 3863922529ef20..b953517dc70f99 100644
--- a/drivers/vfio/Makefile
+++ b/drivers/vfio/Makefile
@@ -4,9 +4,9 @@ vfio_virqfd-y := virqfd.o
 obj-$(CONFIG_VFIO) += vfio.o
 
 vfio-y += vfio_main.o \
- iova_bitmap.o \
- container.o
+ iova_bitmap.o
 vfio-$(CONFIG_IOMMUFD) += iommufd.o
+vfio-$(CONFIG_VFIO_CONTAINER) += container.o
 
 obj-$(CONFIG_VFIO_VIRQFD) += vfio_virqfd.o
 obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o
diff --git a/drivers/vfio/vfio.h b/drivers/vfio/vfio.h
index d57a08afb5cf5c..3378714a746274 100644
--- a/drivers/vfio/vfio.h
+++ b/drivers/vfio/vfio.h
@@ -55,7 +55,9 @@ struct vfio_group {
struct list_headdevice_list;
struct mutexdevice_lock;
struct list_headvfio_next;
+#if IS_ENABLED(CONFIG_VFIO_CONTAINER)
struct list_headcontainer_next;
+#endif
enum vfio_group_typetype;
struct mutexgroup_lock;
struct kvm  *kvm;
@@ -64,6 +66,7 @@ struct vfio_group {
struct iommufd_ctx  *iommufd;
 };
 
+#if IS_ENABLED(CONFIG_VFIO_CONTAINER)
 /* events for the backend driver notify callback */
 enum vfio_iommu_notify_type {
VFIO_IOMMU_CONTAINER_CLOSE = 0,
@@ -129,6 +132,68 @@ int vfio_container_dma_rw(struct vfio_container 
*container, dma_addr_t iova,
 
 int __init vfio_container_init(void);
 void vfio_container_cleanup(void);
+#else
+static inline struct vfio_container *
+vfio_container_from_file(struct file *filep)
+{
+   return NULL;
+}
+
+static inline int vfio_group_use_container(struct vfio_group *group)
+{
+   return -EOPNOTSUPP;
+}
+
+static inline void vfio_group_unuse_container(struct vfio_group *group)
+{
+}
+
+static inline int vfio_container_attach_group(struct vfio_container *container,
+ struct vfio_group *group)
+{
+   return -EOPNOTSUPP;
+}
+
+static inline void vfio_group_detach_container(struct vfio_group *group)
+{
+}
+
+static inline void vfio_device_container_register(struct vfio_device *device)
+{
+}
+
+static inline void vfio_device_container_unregister(struct vfio_device *device)
+{
+}
+
+static inline int vfio_container_pin_pages(str

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

2022-10-25 Thread Hans de Goede

Hi,

On 10/24/22 22:30, Matthew Garrett wrote:
> On Tue, Sep 27, 2022 at 01:04:52PM +0200, Hans de Goede wrote:
> 
>> So to fix this we need to make acpi_video_get_backlight_type()
>> return native on the Acer Chromebook Spin 713.
> 
> Isn't the issue broader than that? Unless the platform is Windows 8 or 
> later, we'll *always* (outside of some corner cases) return 
> acpi_backlight_vendor if there's no ACPI video interface. This is broken 
> for any platform that implements ACPI but relies on native video 
> control, which is going to include a range of Coreboot platforms, not 
> just Chromebooks.

That is a valid point, but keep in mind that this is only used on ACPI
platforms and then only on devices with a builtin LCD panel and then
only by GPU drivers which actually call acpi_video_get_backlight_type(),
so e.g. not by all the ARM specific display drivers.

So I believe that Chromebooks quite likely are the only devices with
this issue.

We could do something like the patch which I have pasted at the end
of this email, but as its commit message notes there is a real
good chance this will cause regressions on some laptops.

So if we ever decide to go with something like the patch below,
I think we should at a minimum wait for the next cycle with that,
because 6.1 already significantly reworks the ACPI backlight
detect handling and I don't want to throw this into the mix
on top of those changes.

> I think for this to work correctly you need to have 
> the infrastructure be aware of whether or not a vendor interface exists, 
> which means having to handle cleanup if a vendor-specific module gets 
> loaded later.

Getting rid of the whole ping-ponging of which backlight drivers
get loaded during boot was actually one of the goals of the rework
which landed in 6.1 this actually allowed us to remove some quirks
because some hw/firmware did not like us changing our mind and
switching backlight interfaces after first poking another one.
So we definitely don't want to go back to the ping-pong thing.

Regards,

Hans

>From 67ee5d7163e33e65dca06887befd0639b0345883 Mon Sep 17 00:00:00 2001
From: Hans de Goede 
Date: Tue, 25 Oct 2022 20:38:56 +0200
Subject: [PATCH] ACPI: video: Simplify __acpi_video_get_backlight_type()

Simplify __acpi_video_get_backlight_type() removing a nested if which
makes the flow harder to follow.

Note this will cause a behavior change on devices which do not have
ACPI video support but do have both a vendor and native backlight
driver available. This change will cause these devices to switch
from vendor to native.

This may not be desirable in all cases, this is likely to happen
on significantly older laptops, where there very well might be
cases where the native driver does not work because the backlight is
controlled by the EC.

This removes the need for the special handling of Chromebooks,
these will now hit the if (native_available) return acpi_backlight_native;
path.

Signed-off-by: Hans de Goede 
---
 drivers/acpi/video_detect.c | 36 +++-
 1 file changed, 11 insertions(+), 25 deletions(-)

diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c
index 9cd8797d12bb..9bd85b159e02 100644
--- a/drivers/acpi/video_detect.c
+++ b/drivers/acpi/video_detect.c
@@ -668,11 +668,6 @@ static const struct dmi_system_id video_detect_dmi_table[] 
= {
{ },
 };

-static bool google_cros_ec_present(void)
-{
-   return acpi_dev_found("GOOG0004");
-}
-
 /*
  * Determine which type of backlight interface to use on this system,
  * First check cmdline, then dmi quirks, then do autodetect.
@@ -718,30 +713,21 @@ static enum acpi_backlight_type 
__acpi_video_get_backlight_type(bool native)
if (apple_gmux_present())
return acpi_backlight_apple_gmux;

-   /* On systems with ACPI video use either native or ACPI video. */
-   if (video_caps & ACPI_VIDEO_BACKLIGHT) {
-   /*
-* Windows 8 and newer no longer use the ACPI video interface,
-* so it often does not work. If the ACPI tables are written
-* for win8 and native brightness ctl is available, use that.
-*
-* The native check deliberately is inside the if acpi-video
-* block on older devices without acpi-video support native
-* is usually not the best choice.
-*/
-   if (acpi_osi_is_win8() && native_available)
-   return acpi_backlight_native;
-   else
-   return acpi_backlight_video;
-   }
-
/*
-* Chromebooks that don't have backlight handle in ACPI table
-* are supposed to use native backlight if it's available.
+* Pre Windows 8, Windows uses ACPI video, so prefer that over native
+* on pre-win8 systems (Windows 8+ no longer uses ACPI video).
 */
-   if (google_cros_ec_present() && native_available)
+

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978

2022-10-25 Thread Patchwork

== Series Details ==

Series: series starting with [1/2] drm/i915/dg2: Introduce Wa_18018764978
URL   : https://patchwork.freedesktop.org/series/110131/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_110131v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/index.html

Participating hosts (40 -> 38)
--

  Additional (1): fi-skl-guc 
  Missing(3): fi-ctg-p8600 fi-icl-u2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_110131v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_psr@sprite_plane_onoff:
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271]) +10 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-skl-guc/igt@kms_psr@sprite_plane_onoff.html

  
 Possible fixes 

  * igt@fbdev@read:
- {bat-rpls-2}:   [SKIP][7] ([i915#2582]) -> [PASS][8] +4 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@fb...@read.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/bat-rpls-2/igt@fb...@read.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258:   [INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> 
[PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][11] ([i915#6367]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka:   [FAIL][13] ([i915#6298]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110131v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997


Build changes
-

  * Linux: CI_DRM_12294 -> Patchwork_110131v1

  CI-20190529: 20190529
  CI_DRM_12294: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110131v1: fca30d6149441ff19df784c0554b8c20a29c7f53 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

fd1f4c786109 drm/i915/dg2: Introduce Wa_18019271663
7eae151085da drm/i915/dg2: Introduce Wa_18018764978

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patc

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT alignment"

2022-10-25 Thread Vudum, Lakshminarayana

Regression failures are related to 
https://gitlab.freedesktop.org/drm/intel/-/issues/7311
Re-reported.

Lakshmi.
-Original Message-
From: Auld, Matthew  
Sent: Tuesday, October 25, 2022 2:09 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: Re: ✗ Fi.CI.BAT: failure for Revert "drm/i915/uapi: expose GTT 
alignment"

On 24/10/2022 12:55, Patchwork wrote:
> *Patch Details*
> *Series:* Revert "drm/i915/uapi: expose GTT alignment"
> *URL:*https://patchwork.freedesktop.org/series/110041/ 
> 
> *State:*  failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html
>  l>
> 
> 
>   CI Bug Log - changes from CI_DRM_12284 -> Patchwork_110041v1
> 
> 
> Summary
> 
> *FAILURE*
> 
> Serious unknown changes coming with Patchwork_110041v1 absolutely need 
> to be verified manually.
> 
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_110041v1, please notify your bug team to allow 
> them to document this new failure mode, which will reduce false positives in 
> CI.
> 
> External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/index.html
> 
> 
> Participating hosts (41 -> 41)
> 
> Additional (3): fi-hsw-4770 fi-icl-u2 bat-atsm-1 Missing (3): 
> fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi
> 
> 
> Possible new issues
> 
> Here are the unknown changes that may have been introduced in
> Patchwork_110041v1:
> 
> 
>   IGT changes
> 
> 
> Possible regressions
> 
>   *
> 
> igt@i915_selftest@live@hugepages:
> 
>   o
> 
> fi-glk-j4005: PASS
> 
>  t@i915_selftest@l...@hugepages.html> -> DMESG-FAIL 
>  005/igt@i915_selftest@l...@hugepages.html>
> 
>   o
> 
> fi-rkl-guc: PASS
> 
>  i915_selftest@l...@hugepages.html> -> DMESG-FAIL 
>  c/igt@i915_selftest@l...@hugepages.html>
> 
>   o
> 
> fi-icl-u2: NOTRUN -> DMESG-FAIL
> 
>  /igt@i915_selftest@l...@hugepages.html>
> 

These failures are unrelated. 
https://gitlab.freedesktop.org/drm/intel/-/issues/7311

> 
> Suppressed
> 
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
> 
>   * igt@gem_exec_parallel@engines@contexts:
>   o {fi-ehl-2}: PASS
> 
>  m_exec_parallel@engi...@contexts.html> -> INCOMPLETE 
>  igt@gem_exec_parallel@engi...@contexts.html>
> 
> 
> Known issues
> 
> Here are the changes found in Patchwork_110041v1 that come from known
> issues:
> 
> 
>   IGT changes
> 
> 
> Issues hit
> 
>   *
> 
> igt@gem_exec_gttfill@basic:
> 
>   o fi-pnv-d510: PASS
> 
> 
>  -> FAIL 
> 
>  (i915#7229 )
>   *
> 
> igt@gem_huc_copy@huc-copy:
> 
>   o fi-icl-u2: NOTRUN -> SKIP
> 
> 
>  (i915#2190 )
>   *
> 
> igt@gem_lmem_swapping@random-engines:
> 
>   o fi-icl-u2: NOTRUN -> SKIP
> 
> 
>  (i915#4613 ) +3 
> similar issues
>   *
> 
> igt@gem_render_tiled_blits@basic:
> 
>   o fi-apl-guc: PASS
> 
> 
>  -> INCOMPLETE 
> 
>  (i915#7056 )
>   *
> 
> igt@gem_softpin@allocator-basic-reserve:
> 
>   o fi-hsw-4770: NOTRUN -> SKIP
> 
> 
>  (fdo#109271 ) +9 
> similar issues
>   *
> 
> igt@i915_pm_backlight@basic-brightness:
> 
>   o fi-hsw-4770: NOTRUN -> SKIP
> 
>

Re: [Intel-gfx] [PATCH v5 02/31] drm/i915: Don't register backlight when another backlight should be used (v2)

2022-10-25 Thread Matthew Garrett

On Tue, Oct 25, 2022 at 08:50:54PM +0200, Hans de Goede wrote:

> That is a valid point, but keep in mind that this is only used on ACPI
> platforms and then only on devices with a builtin LCD panel and then
> only by GPU drivers which actually call acpi_video_get_backlight_type(),
> so e.g. not by all the ARM specific display drivers.
> 
> So I believe that Chromebooks quite likely are the only devices with
> this issue.

My laptop is, uh, weird, but it falls into this category.
 
> > I think for this to work correctly you need to have 
> > the infrastructure be aware of whether or not a vendor interface exists, 
> > which means having to handle cleanup if a vendor-specific module gets 
> > loaded later.
> 
> Getting rid of the whole ping-ponging of which backlight drivers
> get loaded during boot was actually one of the goals of the rework
> which landed in 6.1 this actually allowed us to remove some quirks
> because some hw/firmware did not like us changing our mind and
> switching backlight interfaces after first poking another one.
> So we definitely don't want to go back to the ping-pong thing.

Defaulting to native but then having a vendor driver be able to disable 
native drivers seems easiest? It shouldn't be a regression over the 
previous state of affairs since both drivers were being loaded already.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/slpc: Optmize waitboost for SLPC (rev6)

2022-10-25 Thread Patchwork

== Series Details ==

Series: drm/i915/slpc: Optmize waitboost for SLPC (rev6)
URL   : https://patchwork.freedesktop.org/series/109840/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12294 -> Patchwork_109840v6


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_109840v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_109840v6, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/index.html

Participating hosts (40 -> 39)
--

  Additional (1): fi-skl-guc 
  Missing(2): fi-ctg-p8600 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_109840v6:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-kbl-7567u/igt@i915_susp...@basic-s3-without-i915.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@reset:
- {bat-rpls-2}:   [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/bat-rpls-2/igt@i915_selftest@l...@reset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/bat-rpls-2/igt@i915_selftest@l...@reset.html

  
Known issues


  Here are the changes found in Patchwork_109840v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-skl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-icl-u2:  NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@guc_multi_lrc:
- fi-cfl-8109u:   [PASS][7] -> [DMESG-WARN][8] ([i915#5904] / 
[i915#7174]) +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u:   [PASS][9] -> [DMESG-WARN][10] ([i915#5904]) +32 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#5904] / 
[i915#62]) +3 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12294/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-g3258:   NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-hsw-g3258/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-icl-u2:  NOTRUN -> [SKIP][15] ([fdo#111827])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-skl-guc/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2:  NOTRUN -> [SKIP][17] ([fdo#109285])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109840v6/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u:   [PASS][18] -> [DMESG-WARN][19] ([i915#165] / 
[i915#62]) +14 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip

1 2 >

1 - 100 of 161 matches

Mail list logo