Re: [Intel-gfx] [PATCH v2 12/12] drm/i915/dp: Disable DFP RGB->YCbCr conversion for now
> -Original Message-
> From: Ville Syrjala
> Sent: Tuesday, March 22, 2022 5:30 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; Shankar, Uma
>
> Subject: [PATCH v2 12/12] drm/i915/dp: Disable DFP RGB->YCbCr conversion for
> now
>
> From: Ville Syrjälä
>
> We lack sufficient state tracking to figure out whether we want the DFP to
> perform
> the RGB->YCbCr conversion for us or not. So currently we are blindly just
> enabling
> that all the time when supported by the DFP. That is nonsense. So until we
> imporve
> our state tracking for this just disable the feature.
>
> Cc: Ankit Nautiyal
> Cc: Uma Shankar
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d3d458b3267d..a57581198a47 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1180,6 +1180,7 @@ static bool intel_dp_supports_dsc(struct intel_dp
> *intel_dp, static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>const struct intel_crtc_state *crtc_state) {
> + /* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
> return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420
> ||
> (crtc_state->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR444 &&
>intel_dp->dfp.ycbcr_444_to_420);
> @@ -2574,6 +2575,7 @@ void intel_dp_configure_protocol_converter(struct
> intel_dp *intel_dp,
> "Failed to %s protocol converter YCbCr 4:2:0
> conversion
> mode\n",
> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>
> + /* FIXME see intel_dp_update_420() regarding rgb_to_ycbcr */
> tmp = intel_dp->dfp.rgb_to_ycbcr ?
> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>
> @@ -4430,6 +4432,14 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp-
> >dpcd,
>intel_dp-
> >downstream_ports,
>
> DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
> + /*
> + * FIXME need to actually track whether we're really
> + * going to be doing the RGB->YCbCr connversion or not.
> + * We can't tell by simply looking at intel_dp->dfp.rgb_to_ycbcr.
> + * Readout is going to annoying due to having to read that
> + * state from external hardware that may vanish at any time :(
> + */
> + rgb_to_ycbcr = false;
I think this will break 8k yuv pcon case as of now.
@Nautiyal, Ankit K Can we get that fixed. We will need 8k YUV from source due to
bandwidth constraints.
Rest of the series all looks nice and good.
Regards,
Uma Shankar
> if (DISPLAY_VER(i915) >= 11) {
> /* Let PCON convert from RGB->YCbCr if possible */
> --
> 2.34.1
Re: [Intel-gfx] [PATCH 1/3] drm/i915/dmc: abstract GPU error state dump
On Wed, 30 Mar 2022, Jani Nikula wrote:
> Only intel_dmc.c should be accessing dmc details directly.
>
> Need to add an i915_error_printf() stub for
> CONFIG_DRM_I915_CAPTURE_ERROR=n.
>
> v2: Add the stub (kernel test robot )
>
> Signed-off-by: Jani Nikula
> Reviewed-by: Lucas De Marchi # v1
Just as I pushed to din, I realized I jumped the gun a bit, I meant to
wait for rb confirmation on v2. The diff isn't big, but generally I
prefer erring on the side of caution. Sorry.
And thanks for review on v1. :)
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++
> drivers/gpu/drm/i915/display/intel_dmc.h | 3 +++
> drivers/gpu/drm/i915/i915_gpu_error.c| 10 +-
> drivers/gpu/drm/i915/i915_gpu_error.h| 6 ++
> 4 files changed, 25 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 5de13f978e57..f0eb3de8de60 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -811,6 +811,21 @@ void intel_dmc_ucode_fini(struct drm_i915_private
> *dev_priv)
> kfree(dev_priv->dmc.dmc_info[id].payload);
> }
>
> +void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
> + struct drm_i915_private *i915)
> +{
> + struct intel_dmc *dmc = &i915->dmc;
> +
> + if (!HAS_DMC(i915))
> + return;
> +
> + i915_error_printf(m, "DMC loaded: %s\n",
> + str_yes_no(intel_dmc_has_payload(i915)));
> + i915_error_printf(m, "DMC fw version: %d.%d\n",
> + DMC_VERSION_MAJOR(dmc->version),
> + DMC_VERSION_MINOR(dmc->version));
> +}
> +
> static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> {
> struct drm_i915_private *i915 = m->private;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> b/drivers/gpu/drm/i915/display/intel_dmc.h
> index b9f608057700..dd8880d2cbed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -10,6 +10,7 @@
> #include "intel_wakeref.h"
> #include
>
> +struct drm_i915_error_state_buf;
> struct drm_i915_private;
>
> #define DMC_VERSION(major, minor)((major) << 16 | (minor))
> @@ -55,6 +56,8 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
> void intel_dmc_ucode_resume(struct drm_i915_private *i915);
> bool intel_dmc_has_payload(struct drm_i915_private *i915);
> void intel_dmc_debugfs_register(struct drm_i915_private *i915);
> +void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
> + struct drm_i915_private *i915);
>
> void assert_dmc_loaded(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 795f91a88d1d..25f4e178b410 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -848,15 +848,7 @@ static void __err_print_to_sgl(struct
> drm_i915_error_state_buf *m,
>
> err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
>
> - if (HAS_DMC(m->i915)) {
> - struct intel_dmc *dmc = &m->i915->dmc;
> -
> - err_printf(m, "DMC loaded: %s\n",
> -str_yes_no(intel_dmc_has_payload(m->i915) != 0));
> - err_printf(m, "DMC fw version: %d.%d\n",
> -DMC_VERSION_MAJOR(dmc->version),
> -DMC_VERSION_MINOR(dmc->version));
> - }
> + intel_dmc_print_error_state(m, m->i915);
>
> err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
> err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
> b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 09159ff01411..7977a01a708f 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -298,6 +298,12 @@ void i915_disable_error_state(struct drm_i915_private
> *i915, int err);
>
> #else
>
> +__printf(2, 3)
> +static inline void
> +i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
> +{
> +}
> +
> static inline void
> i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t
> engine_mask, u32 dump_flags)
> {
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 14/15] drm/i915: Define multicast registers as a new type
On 31/03/2022 00:28, Matt Roper wrote:
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
heterogeneous lists of registers (e.g., various MMIO whitelists used by
perf, GVT, etc.) rather than performing reads/writes. We only really
care about the offset in those cases, so for now we can "cast" the
registers as non-MCR, leaving us with a list of i915_reg_t's, but we may
want to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 49 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.h| 14 +++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 27 +++---
drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 +++-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 4 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 17 ---
drivers/gpu/drm/i915/gvt/mmio_context.c | 14 +++---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_reg_defs.h | 9
13 files changed, 113 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index c8e52d625f18..a9a9fa6881f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -103,6 +103,19 @@ void intel_gt_mcr_init(struct intel_gt *gt)
}
}
+/*
+ * Although the rest of the driver should use MCR-specific functions to
+ * read/write MCR registers, we still use the regular intel_uncore_* functions
+ * internally to implement those, so we need a way for the functions in this
+ * file to "cast" an i915_mcr_reg_t into an i915_reg_t.
+ */
+static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
+{
+ i915_reg_t r = { .reg = mcr.mmio };
+
+ return r;
+}
+
/*
* rw_with_mcr_steering_fw - Access a register with specific MCR steering
* @uncore: pointer to struct intel_uncore
@@ -117,7 +130,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* Caller needs to make sure the relevant forcewake wells are up.
*/
static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
@@ -154,9 +167,9 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
if (rw_flag == FW_REG_READ)
- val = intel_uncore_read_fw(uncore, reg);
+ val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
- intel_uncore_write_fw(uncore, reg, value);
+ intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
mcr &= ~mcr_mask;
mcr |= old_mcr & mcr_mask;
@@ -167,14 +180,14 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore
*uncore,
}
static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance,
u32 value)
{
enum forcewake_domains fw_domains;
u32 val;
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
rw_flag);
fw_domains |= intel_uncore_forcewake_for_reg(uncore,
GEN8_MCR_SELECTOR,
@@ -203,7 +216,7 @@ static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
* group/instance.
*/
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance)
{
return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ,
@@ -222,7 +235,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
* group/instance.
*/
void intel_gt_mcr_unicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value,
+ i915_mcr_reg_t reg, u32 value,
int group, int instance)
{
rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE,
@@ -238,9 +251,9 @@ void intel_gt_mcr_unicast_w
[Intel-gfx] [PATCH v2] drm/i915/debugfs: Dump i915 children runtime status
i915 doesn't use pm_suspend_ignore_children(), which warrants that
any runtime active child of i915 will block the runtime suspend
of i915.
i915_runtime_pm_status only exposes i915 runtime pm usage_count,
which is not sufficient to debug in the scenarios when i915 has
zero usage_count but there are runtime active children.
Dump i915 child's runtime pm status to debug such
i915 runtime suspend issues.
v2:
- Added const array of rpm_status strings to avoid switch. [Ashutosh]
Cc: Chris Wilson
Reviewed-by: Badal Nilawar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_debugfs.c | 32 +
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 445b4da23950..930815c8b978 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -483,6 +483,34 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
return 0;
}
+#ifdef CONFIG_PM
+static int i915_runtime_dump_child_status(struct device *dev, void *data)
+{
+ struct seq_file *m = data;
+ const char *rpm_status;
+
+ static const char * const status_lookup[] = {
+ [RPM_ACTIVE] = "active",
+ [RPM_RESUMING] = "resuming",
+ [RPM_SUSPENDED] = "suspended",
+ [RPM_SUSPENDING] = "suspending"
+ };
+
+ /* Early return if runtime_pm is disabled */
+ if (dev->power.disable_depth)
+ return 0;
+ else if (dev->power.runtime_status < ARRAY_SIZE(status_lookup))
+ rpm_status = status_lookup[dev->power.runtime_status];
+ else
+ rpm_status = "unknown";
+
+ seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
+ dev_name(dev), rpm_status);
+
+ return 0;
+}
+#endif
+
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -500,6 +528,10 @@ static int i915_runtime_pm_status(struct seq_file *m, void
*unused)
#ifdef CONFIG_PM
seq_printf(m, "Usage count: %d\n",
atomic_read(&dev_priv->drm.dev->power.usage_count));
+ seq_printf(m, "Runtime active children: %d\n",
+ atomic_read(&dev_priv->drm.dev->power.child_count));
+ device_for_each_child(&pdev->dev, m, i915_runtime_dump_child_status);
+
#else
seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
#endif
--
2.26.2
Re: [Intel-gfx] [PATCH 15/15] drm/i915/xehp: Eliminate shared/implicit steering
On 31/03/2022 00:28, Matt Roper wrote:
Historically we've selected and programmed a single MCR group/instance
ID at driver startup that will steer register accesses for GSLICE/DSS
ranges to a non-terminated instance. Any reads of these register ranges
that don't need a specific unicast access won't bother explicitly
resteering because the control register should already be set to a
suitable value to receive a non-terminated response. Any accesses to
other types of MCR ranges (MSLICE, LNCF, etc.) that are also satisfied
by the default steering target will also skip explicit re-steering at
runtime.
This approach has worked well for many years and many platforms, but our
hardware teams have recently advised us that they're not 100%
comfortable with our strategy going forward. They now suggest
explicitly steering reads of any multicast register at the time the
register access happens rather than relying on previously-programmed
steering values. In debug settings there could be external agents that
have adjusted the default steering without the driver's knowledge (e.g.,
we could do this manually with IGT's intel_reg today, although the
hardware teams also have other tools they use for debug and analysis).
In theory it would also be possible for bad firmware and/or incorrect
handling of power management events to clobber/wipe the steering
value we had previously initialized because they assume we'll be
re-programming it anyway.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 40 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 98 -
3 files changed, 56 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index a9a9fa6881f2..787752367337 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -35,6 +35,7 @@
*/
static const char * const intel_steering_types[] = {
+ "GSLICE/DSS",
"L3BANK",
"MSLICE",
"LNCF",
@@ -45,6 +46,35 @@ static const struct intel_mmio_range
icl_l3bank_steering_table[] = {
{},
};
+static const struct intel_mmio_range xehpsdv_dss_steering_table[] = {
+ { 0x005200, 0x0052FF },
+ { 0x005400, 0x007FFF },
+ { 0x008140, 0x00815F },
+ { 0x008D00, 0x008DFF },
+ { 0x0094D0, 0x00955F },
+ { 0x009680, 0x0096FF },
+ { 0x00DC00, 0x00DCFF },
+ { 0x00DE80, 0x00E8FF },
+ { 0x017000, 0x017FFF },
+ { 0x024A00, 0x024A7F },
+ {},
+};
+
+static const struct intel_mmio_range dg2_dss_steering_table[] = {
+ { 0x005200, 0x0052FF },
+ { 0x005400, 0x007FFF },
+ { 0x008140, 0x00815F },
+ { 0x008D00, 0x008DFF },
+ { 0x0094D0, 0x00955F },
+ { 0x009680, 0x0096FF },
+ { 0x00D800, 0x00D87F },
+ { 0x00DC00, 0x00DCFF },
+ { 0x00DE80, 0x00E8FF },
+ { 0x017000, 0x017FFF },
+ { 0x024A00, 0x024A7F },
+ {},
+};
+
static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = {
{ 0x004000, 0x004AFF },
{ 0x00C800, 0x00CFFF },
@@ -87,9 +117,11 @@ void intel_gt_mcr_init(struct intel_gt *gt)
GEN12_MEML3_EN_MASK);
if (IS_DG2(i915)) {
+ gt->steering_table[DSS] = dg2_dss_steering_table;
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
gt->steering_table[LNCF] = dg2_lncf_steering_table;
} else if (IS_XEHPSDV(i915)) {
+ gt->steering_table[DSS] = xehpsdv_dss_steering_table;
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
gt->steering_table[LNCF] = xehpsdv_lncf_steering_table;
} else if (GRAPHICS_VER(i915) >= 11 &&
@@ -317,7 +349,15 @@ static void get_valid_steering(struct intel_gt *gt,
enum intel_steering_type type,
u8 *group, u8 *instance)
{
+ u32 dssmask = intel_sseu_get_subslices(>->info.sseu, 0);
+
switch (type) {
+ case DSS:
+ drm_WARN_ON(>->i915->drm, dssmask == 0);
+
+ *group = __ffs(dssmask) / GEN_DSS_PER_GSLICE;
+ *instance = __ffs(dssmask) % GEN_DSS_PER_GSLICE;
+ break;
case L3BANK:
GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be
impossible! */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 937b2e1a305e..b77bbaac7622 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -54,6 +54,7 @@ struct intel_mmio_range {
* are listed here.
*/
enum intel_steering_type {
+ DSS,
L3BANK,
MSLICE,
LNCF,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 818ba71f4909..248
Re: [Intel-gfx] [PATCH] drm/atomic-helpers: remove legacy_cursor_update hacks
On Thu, Mar 31, 2022 at 05:20:21PM +0200, Daniel Vetter wrote: > The stuff never really worked, and leads to lots of fun because it > out-of-order frees atomic states. Which upsets KASAN, among other > things. > > For async updates we now have a more solid solution with the > ->atomic_async_check and ->atomic_async_commit hooks. Support for that > for msm and vc4 landed. nouveau and i915 have their own commit > routines, doing something similar. > > For everyone else it's probably better to remove the use-after-free > bug, and encourage folks to use the async support instead. The > affected drivers which register a legacy cursor plane and don't either > use the new async stuff or their own commit routine are: amdgpu, > atmel, mediatek, qxl, rockchip, sti, sun4i, tegra, virtio, and vmwgfx. > > Inspired by an amdgpu bug report. > > v2: Drop RFC, I think with amdgpu converted over to use > atomic_async_check/commit done in > > commit 674e78acae0dfb4beb56132e41cbae5b60f7d662 > Author: Nicholas Kazlauskas > Date: Wed Dec 5 14:59:07 2018 -0500 > > drm/amd/display: Add fast path for cursor plane updates > > we don't have any driver anymore where we have userspace expecting > solid legacy cursor support _and_ they are using the atomic helpers in > their fully glory. So we can retire this. > > v3: Paper over msm and i915 regression. The complete_all is the only > thing missing afaict. > > v4: Fixup i915 fixup ... > > References: https://bugzilla.kernel.org/show_bug.cgi?id=199425 > References: > https://lore.kernel.org/all/20220221134155.125447-9-max...@cerno.tech/ > References: https://bugzilla.kernel.org/show_bug.cgi?id=199425 > Cc: Maxime Ripard > Tested-by: Maxime Ripard > Cc: mikita.lip...@amd.com > Cc: Michel Dänzer > Cc: harry.wentl...@amd.com > Cc: Rob Clark > Cc: "Kazlauskas, Nicholas" > Cc: Dmitry Osipenko > Signed-off-by: Daniel Vetter Acked-by: Maxime Ripard Maxime
Re: [Intel-gfx] [PATCH v2 00/12] drm/edid: cleanup and refactoring around validity checks
On Thu, 31 Mar 2022, Jani Nikula wrote: > v2 of https://patchwork.freedesktop.org/series/101931/ > > Rebased, review comments addressed. Ville, care to double check patches 1 & 7 please? Thanks, Jani. > > BR, > Jani. > > > > Jani Nikula (12): > drm/edid: use struct edid * in drm_do_get_edid() > drm/edid: clean up EDID block checksum functions > drm/edid: add edid_block_tag() helper to get the EDID extension tag > drm/edid: make drm_edid_header_is_valid() accept void pointer > drm/edid: clean up edid_is_zero() > drm/edid: split out edid_header_fix() > drm/edid: split drm_edid_block_valid() to check and act parts > drm/edid: use a better variable name for EDID block read retries > drm/edid: simplify block check when filtering invalid blocks > drm/edid: split out invalid block filtering to a separate function > drm/edid: track invalid blocks in drm_do_get_edid() > drm/edid: reduce magic when updating the EDID block checksum > > drivers/gpu/drm/drm_edid.c | 295 + > include/drm/drm_edid.h | 2 +- > 2 files changed, 173 insertions(+), 124 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/debugfs: Dump i915 children runtime status (rev2)
== Series Details == Series: drm/i915/debugfs: Dump i915 children runtime status (rev2) URL : https://patchwork.freedesktop.org/series/101866/ State : success == Summary == CI Bug Log - changes from CI_DRM_11437 -> Patchwork_22757 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/index.html Participating hosts (42 -> 41) -- Additional (4): bat-dg2-8 bat-rpls-2 fi-icl-u2 fi-tgl-u2 Missing(5): shard-tglu fi-bsw-cyan fi-pnv-d510 shard-rkl fi-bdw-samus Known issues Here are the changes found in Patchwork_22757 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [PASS][3] -> [INCOMPLETE][4] ([i915#5127]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-tgl-u2: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@gem_lmem_swapp...@verify-random.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-u2: NOTRUN -> [SKIP][9] ([fdo#109284] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#109278]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@a-edp1: - fi-tgl-u2: NOTRUN -> [DMESG-WARN][13] ([i915#402]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_setmode@basic-clone-single-crtc: - fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-tgl-u2/igt@kms_setm...@basic-clone-single-crtc.html - fi-icl-u2: NOTRUN -> [SKIP][17] ([i915#3555]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#3301]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/fi-icl-u2/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[INCOMPLETE][19] ([i915#3921]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/fi-snb-26
[Intel-gfx] [PATCH i-g-t 2/2] tests/gem_ctx_engines: handle missing set_caching
Not supported on discrete. Here the object will already have the GTT caching bits enabled, and the mapping will be WB, which looks inline with what the test is expecting here. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4926 Signed-off-by: Matthew Auld Cc: Nirmoy Das --- tests/i915/gem_ctx_engines.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c index de4b822c..19cf9b05 100644 --- a/tests/i915/gem_ctx_engines.c +++ b/tests/i915/gem_ctx_engines.c @@ -492,7 +492,8 @@ static void independent(int i915, const intel_ctx_t *base_ctx, param.ctx_id = gem_context_create(i915); gem_context_set_param(i915, ¶m); - gem_set_caching(i915, results.handle, I915_CACHING_CACHED); + if (!gem_has_lmem(i915)) + gem_set_caching(i915, results.handle, I915_CACHING_CACHED); map = gem_mmap__cpu(i915, results.handle, 0, 4096, PROT_READ); gem_set_domain(i915, results.handle, I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); -- 2.34.1
[Intel-gfx] [PATCH i-g-t 1/2] tests/kms_pwrite_crc: handle missing get_caching
gem_get_caching is not supported on discrete. The object itself should
already be coherent with the display engine as-is on such platforms, by
virtue of the scanout happening via local-memory.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4903
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
tests/i915/kms_pwrite_crc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tests/i915/kms_pwrite_crc.c b/tests/i915/kms_pwrite_crc.c
index 44fcfadb..584e6a19 100644
--- a/tests/i915/kms_pwrite_crc.c
+++ b/tests/i915/kms_pwrite_crc.c
@@ -50,7 +50,6 @@ static void test(data_t *data)
igt_output_t *output = data->output;
struct igt_fb *fb = &data->fb[1];
drmModeModeInfo *mode;
- uint32_t caching;
void *buf;
igt_crc_t crc;
@@ -76,9 +75,14 @@ static void test(data_t *data)
0, 0, fb->width, fb->height,
0, 0, fb->width << 16, fb->height << 16);
- /* make sure caching mode has become UC/WT */
- caching = gem_get_caching(data->drm_fd, fb->gem_handle);
- igt_assert(caching == I915_CACHING_NONE || caching ==
I915_CACHING_DISPLAY);
+ if (!gem_has_lmem(data->drm_fd)) {
+ uint32_t caching;
+
+ /* make sure caching mode has become UC/WT */
+ caching = gem_get_caching(data->drm_fd, fb->gem_handle);
+ igt_assert(caching == I915_CACHING_NONE ||
+ caching == I915_CACHING_DISPLAY);
+ }
/* use pwrite to make the other fb all white too */
buf = malloc(fb->size);
--
2.34.1
Re: [Intel-gfx] [PATCH i-g-t 1/2] tests/kms_pwrite_crc: handle missing get_caching
I was just looking into this :) LGTM Reviewed-by: Nirmoy Das
On 4/1/2022 1:09 PM, Matthew Auld wrote:
gem_get_caching is not supported on discrete. The object itself should
already be coherent with the display engine as-is on such platforms, by
virtue of the scanout happening via local-memory.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4903
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
tests/i915/kms_pwrite_crc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tests/i915/kms_pwrite_crc.c b/tests/i915/kms_pwrite_crc.c
index 44fcfadb..584e6a19 100644
--- a/tests/i915/kms_pwrite_crc.c
+++ b/tests/i915/kms_pwrite_crc.c
@@ -50,7 +50,6 @@ static void test(data_t *data)
igt_output_t *output = data->output;
struct igt_fb *fb = &data->fb[1];
drmModeModeInfo *mode;
- uint32_t caching;
void *buf;
igt_crc_t crc;
@@ -76,9 +75,14 @@ static void test(data_t *data)
0, 0, fb->width, fb->height,
0, 0, fb->width << 16, fb->height << 16);
- /* make sure caching mode has become UC/WT */
- caching = gem_get_caching(data->drm_fd, fb->gem_handle);
- igt_assert(caching == I915_CACHING_NONE || caching ==
I915_CACHING_DISPLAY);
+ if (!gem_has_lmem(data->drm_fd)) {
+ uint32_t caching;
+
+ /* make sure caching mode has become UC/WT */
+ caching = gem_get_caching(data->drm_fd, fb->gem_handle);
+ igt_assert(caching == I915_CACHING_NONE ||
+ caching == I915_CACHING_DISPLAY);
+ }
/* use pwrite to make the other fb all white too */
buf = malloc(fb->size);
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
On Tue, 29 Mar 2022, "Dixit, Ashutosh" wrote:
> On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
>>
>> +#ifdef CONFIG_PM
>> +static int i915_runtime_dump_child_status(struct device *dev, void *data)
>> +{
>> +struct seq_file *m = data;
>> +const char *rpm_status;
>> +
>> +/* Early return if runtime_pm is disabled */
>> +if (dev->power.disable_depth)
>> +return 0;
>> +
>> +switch (dev->power.runtime_status) {
>> +case RPM_SUSPENDED:
>> +rpm_status = "suspended";
>> +break;
>> +case RPM_SUSPENDING:
>> +rpm_status = "suspending";
>> +break;
>> +case RPM_RESUMING:
>> +rpm_status = "resuming";
>> +break;
>> +case RPM_ACTIVE:
>> +rpm_status = "active";
>> +break;
>> +default:
>> +rpm_status = "unknown";
>> +}
>> +
>> +seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
>> + dev_name(dev), rpm_status);
>> +
>> +return 0;
>> +}
>> +#endif
>
> Maybe a nit, but perhaps defining a const array is better than having a
> switch statement? Similar to what is done in rtpm_status_str(). The
> function itself is very similar to rtpm_status_str() so can probably
> benefit from that similarity. Can perhaps even be nearly identical to
> rtpm_status_str() (since that is static in the genpd (generic power domain)
> code).
>
> See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
> generic_pm_domain-s"), though I am not sure if genpd's are applicable in
> our case and certainly look way out of scope for now. Thanks.
See also /sys/devices/i915/power/runtime_status and
/sys/devices/i915/power/runtime_active_kids.
Kinda feels like the info should be made available there?
BR,
Jani.
>
>> +
>> static int i915_runtime_pm_status(struct seq_file *m, void *unused)
>> {
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> @@ -500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file *m,
>> void *unused)
>> #ifdef CONFIG_PM
>> seq_printf(m, "Usage count: %d\n",
>> atomic_read(&dev_priv->drm.dev->power.usage_count));
>> +seq_printf(m, "Runtime active children: %d\n",
>> + atomic_read(&dev_priv->drm.dev->power.child_count));
>> +device_for_each_child(&pdev->dev, m, i915_runtime_dump_child_status);
>> +
>> #else
>> seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
>> #endif
>> --
>> 2.26.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/debugfs: Dump i915 children runtime status (rev2)
== Series Details == Series: drm/i915/debugfs: Dump i915 children runtime status (rev2) URL : https://patchwork.freedesktop.org/series/101866/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11437_full -> Patchwork_22757_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22757_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22757_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 11) -- Missing(1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22757_full: ### IGT changes ### Possible regressions * igt@gem_exec_balancer@persistence: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-skl6/igt@gem_exec_balan...@persistence.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-skl3/igt@gem_exec_balan...@persistence.html Known issues Here are the changes found in Patchwork_22757_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk1/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk2/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk7/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk7/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11437/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk9/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk1/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk1/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk1/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk2/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22757/shard-glk2/boot.html [37
[Intel-gfx] [PATCH v7 0/9] drm/i915/ttm: Evict and restore of compressed object
On Xe-HP and later devices, we use dedicated compression control state (CCS) stored in local memory for each surface, to support the 3D and media compression formats. The memory required for the CCS of the entire local memory is 1/256 of the local memory size. So before the kernel boot, the required memory is reserved for the CCS data and a secure register will be programmed with the CCS base address So when we allocate a object in local memory we dont need to explicitly allocate the space for ccs data. But when we evict the obj into the smem to hold the compression related data along with the obj we need smem space of obj_size + (obj_size/256). Hence when we create smem for an obj with lmem placement possibility we create with the extra space. When we are swapping out the local memory obj on flat-ccs capable platform, we need to capture the ccs data too along with main meory and we need to restore it when we are swapping in the content. When lmem object is swapped into a smem obj, smem obj will have the extra pages required to hold the ccs data corresponding to the lmem main memory. So main memory of lmem will be copied into the initial pages of the smem and then ccs data corresponding to the main memory will be copied to the subsequent pages of smem. Swapin happens exactly in reverse order. First main memory of lmem is restored from the smem's initial pages and the ccs data will be restored from the subsequent pages of smem. Extracting and restoring the CCS data is done through a special cmd called XY_CTRL_SURF_COPY_BLT v7: GEM_BUG_ON is added for catching if inflated pages are filled for get_pages Optimised emit_copy_clear Engine index is directly used for the upper 32 bits of offset Use FAT_COLOR_BLT only for FLAT_CCS capable platforms Resending with updated igt version for test with. Test-with: 20220401074527.15709-2-ramalinga...@intel.com Ramalingam C (9): drm/i915/gt: use engine instance directly for offset drm/i915/gt: Use XY_FAST_COLOR_BLT to clear obj on graphics ver 12+ drm/i915/gt: Optimize the migration and clear loop drm/i915/gt: Clear compress metadata for Flat-ccs objects drm/i915/selftest_migrate: Consider the possible roundup of size drm/i915/selftest_migrate: Check CCS meta data clear drm/ttm: Add a parameter to add extra pages into ttm_tt drm/i915/gem: Add extra pages in ttm_tt for ccs data drm/i915/migrate: Evict and restore the flatccs capable lmem obj drivers/gpu/drm/drm_gem_vram_helper.c| 2 +- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 30 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 21 + drivers/gpu/drm/i915/gt/intel_migrate.c | 387 +-- drivers/gpu/drm/i915/gt/selftest_migrate.c | 253 ++-- drivers/gpu/drm/qxl/qxl_ttm.c| 2 +- drivers/gpu/drm/ttm/ttm_agp_backend.c| 2 +- drivers/gpu/drm/ttm/ttm_tt.c | 12 +- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +- include/drm/ttm/ttm_tt.h | 4 +- 10 files changed, 642 insertions(+), 73 deletions(-) -- 2.20.1
[Intel-gfx] [PATCH v7 1/9] drm/i915/gt: use engine instance directly for offset
To make it uniform across copy and clear, use the engine offset directly
to calculate the offset in the cmd forming for emit_clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 950fd6da146c..9d852a570400 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -613,15 +613,13 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, u64 offset, int size, u32 value)
+static int emit_clear(struct i915_request *rq, u32 offset, int size, u32 value)
{
const int ver = GRAPHICS_VER(rq->engine->i915);
u32 *cs;
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- offset += (u64)rq->engine->instance << 32;
-
cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -631,17 +629,16 @@ static int emit_clear(struct i915_request *rq, u64
offset, int size, u32 value)
*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
*cs++ = 0;
*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(offset);
- *cs++ = upper_32_bits(offset);
+ *cs++ = offset;
+ *cs++ = rq->engine->instance;
*cs++ = value;
*cs++ = MI_NOOP;
} else {
- GEM_BUG_ON(upper_32_bits(offset));
*cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
*cs++ = 0;
*cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
- *cs++ = lower_32_bits(offset);
+ *cs++ = offset;
*cs++ = value;
}
--
2.20.1
[Intel-gfx] [PATCH v7 3/9] drm/i915/gt: Optimize the migration and clear loop
Move the static calculations out of the loops for copy and clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 40 -
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index e81f20266f62..580b4cf1efa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -526,6 +526,7 @@ intel_context_migrate_copy(struct intel_context *ce,
struct i915_request **out)
{
struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
+ u32 src_offset, dst_offset;
struct i915_request *rq;
int err;
@@ -535,8 +536,18 @@ intel_context_migrate_copy(struct intel_context *ce,
GEM_BUG_ON(ce->ring->size < SZ_64K);
+ src_offset = 0;
+ dst_offset = CHUNK_SZ;
+ if (HAS_64K_PAGES(ce->engine->i915)) {
+ src_offset = 0;
+ dst_offset = 0;
+ if (src_is_lmem)
+ src_offset = CHUNK_SZ;
+ if (dst_is_lmem)
+ dst_offset = 2 * CHUNK_SZ;
+ }
+
do {
- u32 src_offset, dst_offset;
int len;
rq = i915_request_create(ce);
@@ -564,17 +575,6 @@ intel_context_migrate_copy(struct intel_context *ce,
if (err)
goto out_rq;
- src_offset = 0;
- dst_offset = CHUNK_SZ;
- if (HAS_64K_PAGES(ce->engine->i915)) {
- src_offset = 0;
- dst_offset = 0;
- if (src_is_lmem)
- src_offset = CHUNK_SZ;
- if (dst_is_lmem)
- dst_offset = 2 * CHUNK_SZ;
- }
-
len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem,
src_offset, CHUNK_SZ);
if (len <= 0) {
@@ -584,12 +584,10 @@ intel_context_migrate_copy(struct intel_context *ce,
err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
dst_offset, len);
- if (err < 0)
- goto out_rq;
- if (err < len) {
+ if (err < len)
err = -EINVAL;
+ if (err < 0)
goto out_rq;
- }
err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
if (err)
@@ -690,6 +688,7 @@ intel_context_migrate_clear(struct intel_context *ce,
{
struct sgt_dma it = sg_sgt(sg);
struct i915_request *rq;
+ u32 offset;
int err;
GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
@@ -697,8 +696,11 @@ intel_context_migrate_clear(struct intel_context *ce,
GEM_BUG_ON(ce->ring->size < SZ_64K);
+ offset = 0;
+ if (HAS_64K_PAGES(ce->engine->i915) && is_lmem)
+ offset = CHUNK_SZ;
+
do {
- u32 offset;
int len;
rq = i915_request_create(ce);
@@ -726,10 +728,6 @@ intel_context_migrate_clear(struct intel_context *ce,
if (err)
goto out_rq;
- offset = 0;
- if (HAS_64K_PAGES(ce->engine->i915) && is_lmem)
- offset = CHUNK_SZ;
-
len = emit_pte(rq, &it, cache_level, is_lmem, offset, CHUNK_SZ);
if (len <= 0) {
err = len;
--
2.20.1
[Intel-gfx] [PATCH v7 2/9] drm/i915/gt: Use XY_FAST_COLOR_BLT to clear obj on graphics ver 12+
Use faster XY_FAST_COLOR_BLT cmd on graphics version of 12 and more,
for clearing (Zero out) the pages of the newly allocated object.
XY_FAST_COLOR_BLT is faster than the older XY_COLOR_BLT.
v2:
Typo fix at title [Thomas]
v3:
XY_FAST_COLOR_BLT is used only for FLAT_CCS capable gen12+
Signed-off-by: Ramalingam C
Signed-off-by: Chris Wilson
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 5 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 43 +---
2 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 4243be030bc1..d1b8c23f7a9e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -206,6 +206,11 @@
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
+#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
+#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)
+#define XY_FAST_COLOR_BLT_DW 16
+#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
+#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
#define XY_SRC_COPY_BLT_CMD(2 << 29 | 0x53 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 9d852a570400..e81f20266f62 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -613,18 +613,51 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, u32 offset, int size, u32 value)
+static int emit_clear(struct i915_request *rq, u32 offset, int size,
+ u32 value, bool is_lmem)
{
- const int ver = GRAPHICS_VER(rq->engine->i915);
+ struct drm_i915_private *i915 = rq->engine->i915;
+ int mocs = rq->engine->gt->mocs.uc_index << 1;
+ const int ver = GRAPHICS_VER(i915);
+ int ring_sz;
u32 *cs;
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- cs = intel_ring_begin(rq, ver >= 8 ? 8 : 6);
+ if (HAS_FLAT_CCS(i915) && ver >= 12)
+ ring_sz = XY_FAST_COLOR_BLT_DW;
+ else if (ver >= 8)
+ ring_sz = 8;
+ else
+ ring_sz = 6;
+
+ cs = intel_ring_begin(rq, ring_sz);
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (ver >= 8) {
+ if (HAS_FLAT_CCS(i915) && ver >= 12) {
+ *cs++ = XY_FAST_COLOR_BLT_CMD | XY_FAST_COLOR_BLT_DEPTH_32 |
+ (XY_FAST_COLOR_BLT_DW - 2);
+ *cs++ = FIELD_PREP(XY_FAST_COLOR_BLT_MOCS_MASK, mocs) |
+ (PAGE_SIZE - 1);
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = offset;
+ *cs++ = rq->engine->instance;
+ *cs++ = !is_lmem << XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT;
+ /* BG7 */
+ *cs++ = value;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ /* BG11 */
+ *cs++ = 0;
+ *cs++ = 0;
+ /* BG13 */
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ } else if (ver >= 8) {
*cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
*cs++ = 0;
@@ -707,7 +740,7 @@ intel_context_migrate_clear(struct intel_context *ce,
if (err)
goto out_rq;
- err = emit_clear(rq, offset, len, value);
+ err = emit_clear(rq, offset, len, value, is_lmem);
/* Arbitration is re-enabled between requests. */
out_rq:
--
2.20.1
[Intel-gfx] [PATCH v7 4/9] drm/i915/gt: Clear compress metadata for Flat-ccs objects
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
XY_CTRL_SURF_COPY_BLT is a BLT cmd used for reading and writing the
ccs surface of a lmem memory. So on Flat-CCS capable platform we use
XY_CTRL_SURF_COPY_BLT to clear the CCS meta data.
v2: Fixed issues with platform naming [Lucas]
v3: Rebased [Ram]
Used the round_up funcs [Bob]
v4: Fixed ccs blk calculation [Ram]
Added Kdoc on flat-ccs.
v5: GENMASK is used [Matt]
mocs fix [Matt]
Comments Fix [Matt]
Flush address programming [Ram]
v6: FLUSH_DW is fixed
Few coding style fix
v7: Adopting the XY_FAST_COLOR_BLT (Thomas]
v8: XY_CTRL_SURF_COPY_BLT for ccs clearing.
v9: emit_copy_ccs is used.
v10: ctrl_surf cmds are filled in caller itself. [Thomas]
only one ctrl surf cmd is used as size of lmem is <=8M [Thomas]
Signed-off-by: Ramalingam C
Signed-off-by: Ayaz A Siddiqui
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 16 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 137 ++-
2 files changed, 152 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index d1b8c23f7a9e..724ab069ddb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -154,8 +154,10 @@
#define MI_FLUSH_DW_PROTECTED_MEM_EN (1 << 22)
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB(1<<18)
+#define MI_FLUSH_DW_CCS (1<<16)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
#define MI_FLUSH_DW_OP_MASK (3<<14)
+#define MI_FLUSH_DW_LLC (1<<9)
#define MI_FLUSH_DW_NOTIFY (1<<8)
#define MI_INVALIDATE_BSD(1<<7)
#define MI_FLUSH_DW_USE_GTT (1<<2)
@@ -204,6 +206,20 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT21
+#define DST_ACCESS_TYPE_SHIFT20
+#define CCS_SIZE_MASK0x3FF
+#define CCS_SIZE_SHIFT 8
+#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 25)
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_BYTES_PER_CCS_BYTE 256
+#define NUM_CCS_BLKS_PER_XFER1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS1
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 580b4cf1efa2..a44f2d29da4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -17,6 +17,8 @@ struct insert_pte_data {
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+#define GET_CCS_BYTES(i915, size) (HAS_FLAT_CCS(i915) ? \
+DIV_ROUND_UP(size,
NUM_BYTES_PER_CCS_BYTE) : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
if (!engine)
@@ -467,6 +469,123 @@ static bool wa_1209644611_applies(int ver, u32 size)
return height % 4 == 3 && height <= 8;
}
+/**
+ * DOC: Flat-CCS - Memory compression for Local memory
+ *
+ * On Xe-HP and later devices, we use dedicated compression control state (CCS)
+ * stored in local memory for each surface, to support the 3D and media
+ * compression formats.
+ *
+ * The memory required for the CCS of the entire local memory is 1/256 of the
+ * local memory size. So before the kernel boot, the required memory is
reserved
+ * for the CCS data and a secure register will be programmed with the CCS base
+ * address.
+ *
+ * Flat CCS data needs to be cleared when a lmem object is allocated.
+ * And CCS data can be copied in and out of CCS region through
+ * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
+ *
+ * When we exhaust the lmem, if the object's placements support smem, then we
can
+ * directly decompress the compressed lmem object into smem and start using it
+ * from smem itself.
+ *
+ * But when we need to swapout the compressed lmem object into a smem region
+ * though objects' placement doesn't support smem, then we copy the lmem
content
+ * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT).
+ * When the object is referred, lmem content will be swaped in along with
+ * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresp
[Intel-gfx] [PATCH v7 5/9] drm/i915/selftest_migrate: Consider the possible roundup of size
Consider the possible round up happened at obj size alignment to
min_page_size during the obj allocation.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index c9c4f391c5cc..b5da8b8cd039 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -152,6 +152,9 @@ static int clear(struct intel_migrate *migrate,
if (IS_ERR(obj))
return 0;
+ /* Consider the rounded up memory too */
+ sz = obj->base.size;
+
for_i915_gem_ww(&ww, err, true) {
err = i915_gem_object_lock(obj, &ww);
if (err)
--
2.20.1
[Intel-gfx] [PATCH v7 6/9] drm/i915/selftest_migrate: Check CCS meta data clear
Extend the live migrate selftest, to verify the ccs surface clearing
during the Flat-CCS capable lmem obj clear.
v2:
Look at right places for ccs data [Thomas]
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 250 ++---
1 file changed, 222 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c
b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index b5da8b8cd039..8cd9a22054f3 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -132,6 +132,124 @@ static int copy(struct intel_migrate *migrate,
return err;
}
+static int intel_context_copy_ccs(struct intel_context *ce,
+ const struct i915_deps *deps,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool write_to_ccs,
+ struct i915_request **out)
+{
+ u8 src_access = write_to_ccs ? DIRECT_ACCESS : INDIRECT_ACCESS;
+ u8 dst_access = write_to_ccs ? INDIRECT_ACCESS : DIRECT_ACCESS;
+ struct sgt_dma it = sg_sgt(sg);
+ struct i915_request *rq;
+ u32 offset;
+ int err;
+
+ GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
+ *out = NULL;
+
+ GEM_BUG_ON(ce->ring->size < SZ_64K);
+
+ offset = 0;
+ if (HAS_64K_PAGES(ce->engine->i915))
+ offset = CHUNK_SZ;
+
+ do {
+ int len;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ if (deps) {
+ err = i915_request_await_deps(rq, deps);
+ if (err)
+ goto out_rq;
+
+ if (rq->engine->emit_init_breadcrumb) {
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ deps = NULL;
+ }
+
+ /* The PTE updates + clear must not be interrupted. */
+ err = emit_no_arbitration(rq);
+ if (err)
+ goto out_rq;
+
+ len = emit_pte(rq, &it, cache_level, true, offset, CHUNK_SZ);
+ if (len <= 0) {
+ err = len;
+ goto out_rq;
+ }
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ err = emit_copy_ccs(rq, offset, dst_access,
+ offset, src_access, len);
+ if (err)
+ goto out_rq;
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+
+ /* Arbitration is re-enabled between requests. */
+out_rq:
+ if (*out)
+ i915_request_put(*out);
+ *out = i915_request_get(rq);
+ i915_request_add(rq);
+ if (err || !it.sg || !sg_dma_len(it.sg))
+ break;
+
+ cond_resched();
+ } while (1);
+
+out_ce:
+ return err;
+}
+
+static int
+intel_migrate_ccs_copy(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ const struct i915_deps *deps,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool write_to_ccs,
+ struct i915_request **out)
+{
+ struct intel_context *ce;
+ int err;
+
+ *out = NULL;
+ if (!m->context)
+ return -ENODEV;
+
+ ce = intel_migrate_create_context(m);
+ if (IS_ERR(ce))
+ ce = intel_context_get(m->context);
+ GEM_BUG_ON(IS_ERR(ce));
+
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ err = intel_context_copy_ccs(ce, deps, sg, cache_level,
+write_to_ccs, out);
+
+ intel_context_unpin(ce);
+out:
+ intel_context_put(ce);
+ return err;
+}
+
static int clear(struct intel_migrate *migrate,
int (*fn)(struct intel_migrate *migrate,
struct i915_gem_ww_ctx *ww,
@@ -144,7 +262,8 @@ static int clear(struct intel_migrate *migrate,
struct drm_i915_gem_object *obj;
struct i915_request *rq;
struct i915_gem_ww_ctx ww;
- u32 *vaddr;
+ u32 *vaddr, val = 0;
+ bool ccs_cap = false;
int err = 0;
int i;
@@ -155,7 +274,12 @@ static int clear(struct intel_migrate *migrate,
/* Consider the rounded up memory too */
sz = obj->ba
[Intel-gfx] [PATCH v7 7/9] drm/ttm: Add a parameter to add extra pages into ttm_tt
Add a parameter called "extra_pages" for ttm_tt_init, to indicate that
driver needs extra pages in ttm_tt.
v2:
Used imperative wording [Thomas and Christian]
Signed-off-by: Ramalingam C
cc: Christian Koenig
cc: Hellstrom Thomas
Reviewed-by: Thomas Hellstrom
Reviewed-by: Christian Konig
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 2 +-
drivers/gpu/drm/qxl/qxl_ttm.c | 2 +-
drivers/gpu/drm/ttm/ttm_agp_backend.c | 2 +-
drivers/gpu/drm/ttm/ttm_tt.c | 12 +++-
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +-
include/drm/ttm/ttm_tt.h | 4 +++-
7 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
b/drivers/gpu/drm/drm_gem_vram_helper.c
index dc7f938bfff2..123045b58fec 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -867,7 +867,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct
ttm_buffer_object *bo,
if (!tt)
return NULL;
- ret = ttm_tt_init(tt, bo, page_flags, ttm_cached);
+ ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
if (ret < 0)
goto err_ttm_tt_init;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index c40aca99442f..a878910a563c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -293,7 +293,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
- ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching);
+ ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0);
if (ret)
goto err_free;
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 95df5750f47f..9ba871bd19b1 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -113,7 +113,7 @@ static struct ttm_tt *qxl_ttm_tt_create(struct
ttm_buffer_object *bo,
ttm = kzalloc(sizeof(struct ttm_tt), GFP_KERNEL);
if (ttm == NULL)
return NULL;
- if (ttm_tt_init(ttm, bo, page_flags, ttm_cached)) {
+ if (ttm_tt_init(ttm, bo, page_flags, ttm_cached, 0)) {
kfree(ttm);
return NULL;
}
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
b/drivers/gpu/drm/ttm/ttm_agp_backend.c
index 6ddc16f0fe2b..d27691f2e451 100644
--- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -134,7 +134,7 @@ struct ttm_tt *ttm_agp_tt_create(struct ttm_buffer_object
*bo,
agp_be->mem = NULL;
agp_be->bridge = bridge;
- if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined)) {
+ if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined, 0)) {
kfree(agp_be);
return NULL;
}
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index d234aab800a0..1a66d9fc589a 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -134,9 +134,10 @@ void ttm_tt_destroy(struct ttm_device *bdev, struct ttm_tt
*ttm)
static void ttm_tt_init_fields(struct ttm_tt *ttm,
struct ttm_buffer_object *bo,
uint32_t page_flags,
- enum ttm_caching caching)
+ enum ttm_caching caching,
+ unsigned long extra_pages)
{
- ttm->num_pages = PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT;
+ ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
extra_pages;
ttm->caching = ttm_cached;
ttm->page_flags = page_flags;
ttm->dma_address = NULL;
@@ -146,9 +147,10 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
}
int ttm_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo,
- uint32_t page_flags, enum ttm_caching caching)
+ uint32_t page_flags, enum ttm_caching caching,
+ unsigned long extra_pages)
{
- ttm_tt_init_fields(ttm, bo, page_flags, caching);
+ ttm_tt_init_fields(ttm, bo, page_flags, caching, extra_pages);
if (ttm_tt_alloc_page_directory(ttm)) {
pr_err("Failed allocating page table\n");
@@ -180,7 +182,7 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct
ttm_buffer_object *bo,
{
int ret;
- ttm_tt_init_fields(ttm, bo, page_flags, caching);
+ ttm_tt_init_fields(ttm, bo, page_flags, caching, 0);
if (page_flags & TTM_TT_FLAG_EXTERNAL)
ret = ttm_sg_tt_alloc_page_directory(ttm);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index b84ecc6d6611..4e3938e62c08 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/g
[Intel-gfx] [PATCH v7 8/9] drm/i915/gem: Add extra pages in ttm_tt for ccs data
On Xe-HP and later devices, dedicated compression control state (CCS)
stored in local memory is used for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory size. So before the kernel boot, the required memory
is reserved for the CCS data and a secure register will be programmed
with the CCS base address
So when an object is allocated in local memory, dont need to explicitly
allocate the space for ccs data. But when the obj is evicted into the
smem, to hold the compression related data along with the obj extra space
is needed in smem. i.e obj_size + (obj_size/256).
Hence when a smem pages are allocated for an obj with lmem placement
possibility we create with the extra pages required for the ccs data for
the obj size.
v2:
Used imperative wording [Thomas]
v3:
Inflate the pages only when obj's placement is lmem only
v4:
GEM_BUG_ON if the ttm->num_pages > obj page size [Thomas]
Signed-off-by: Ramalingam C
cc: Christian Koenig
cc: Hellstrom Thomas
Reviewed-by: Thomas Hellstrom
Reviewed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index a878910a563c..4c25d9b2f138 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -20,6 +20,7 @@
#include "gem/i915_gem_ttm.h"
#include "gem/i915_gem_ttm_move.h"
#include "gem/i915_gem_ttm_pm.h"
+#include "gt/intel_gpu_commands.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -265,12 +266,33 @@ static const struct i915_refct_sgt_ops tt_rsgt_ops = {
.release = i915_ttm_tt_release
};
+static inline bool
+i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
+{
+ bool lmem_placement = false;
+ int i;
+
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ /* Compression is not allowed for the objects with smem
placement */
+ if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
+ return false;
+ if (!lmem_placement &&
+ obj->mm.placements[i]->type == INTEL_MEMORY_LOCAL)
+ lmem_placement = true;
+ }
+
+ return lmem_placement;
+}
+
static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
uint32_t page_flags)
{
+ struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
+bdev);
struct ttm_resource_manager *man =
ttm_manager_type(bo->bdev, bo->resource->mem_type);
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ unsigned long ccs_pages = 0;
enum ttm_caching caching;
struct i915_ttm_tt *i915_tt;
int ret;
@@ -293,7 +315,12 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
- ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0);
+ if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))
+ ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,
+ NUM_BYTES_PER_CCS_BYTE),
+PAGE_SIZE);
+
+ ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, ccs_pages);
if (ret)
goto err_free;
@@ -773,6 +800,7 @@ static int __i915_ttm_get_pages(struct drm_i915_gem_object
*obj,
i915_sg_dma_sizes(rsgt->table.sgl));
}
+ GEM_BUG_ON(bo->ttm && ((obj->base.size >> PAGE_SHIFT) <
bo->ttm->num_pages));
i915_ttm_adjust_lru(obj);
return ret;
}
--
2.20.1
[Intel-gfx] [PATCH v7 9/9] drm/i915/migrate: Evict and restore the flatccs capable lmem obj
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
When lmem object is swapped into a smem obj, smem obj will
have the extra pages required to hold the ccs data corresponding to the
lmem main memory. So main memory of lmem will be copied into the initial
pages of the smem and then ccs data corresponding to the main memory
will be copied to the subsequent pages of smem. ccs data is 1/256 of
lmem size.
Swapin happens exactly in reverse order. First main memory of lmem is
restored from the smem's initial pages and the ccs data will be restored
from the subsequent pages of smem.
Extracting and restoring the CCS data is done through a special cmd called
XY_CTRL_SURF_COPY_BLT
v2: Fixing the ccs handling
v3: Handle the ccs data at same loop as main memory [Thomas]
v4: changes for emit_copy_ccs
v5: handle non-flat-ccs scenario
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellstrom
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index a44f2d29da4e..ec417c84600b 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -633,6 +633,65 @@ static int emit_copy(struct i915_request *rq,
return 0;
}
+static int scatter_list_length(struct scatterlist *sg)
+{
+ int len = 0;
+
+ while (sg && sg_dma_len(sg)) {
+ len += sg_dma_len(sg);
+ sg = sg_next(sg);
+ };
+
+ return len;
+}
+
+static void
+calculate_chunk_sz(struct drm_i915_private *i915, bool src_is_lmem,
+ int *src_sz, int *ccs_sz, u32 bytes_to_cpy,
+ u32 ccs_bytes_to_cpy)
+{
+ if (ccs_bytes_to_cpy) {
+ /*
+* We can only copy the ccs data corresponding to
+* the CHUNK_SZ of lmem which is
+* GET_CCS_BYTES(i915, CHUNK_SZ))
+*/
+ *ccs_sz = min_t(int, ccs_bytes_to_cpy, GET_CCS_BYTES(i915,
CHUNK_SZ));
+
+ if (!src_is_lmem)
+ /*
+* When CHUNK_SZ is passed all the pages upto CHUNK_SZ
+* will be taken for the blt. in Flat-ccs supported
+* platform Smem obj will have more pages than required
+* for main meory hence limit it to the required size
+* for main memory
+*/
+ *src_sz = min_t(int, bytes_to_cpy, CHUNK_SZ);
+ } else { /* ccs handling is not required */
+ *src_sz = CHUNK_SZ;
+ }
+}
+
+static void get_ccs_sg_sgt(struct sgt_dma *it, u32 bytes_to_cpy)
+{
+ u32 len;
+
+ do {
+ GEM_BUG_ON(!it->sg || !sg_dma_len(it->sg));
+ len = it->max - it->dma;
+ if (len > bytes_to_cpy) {
+ it->dma += bytes_to_cpy;
+ break;
+ }
+
+ bytes_to_cpy -= len;
+
+ it->sg = __sg_next(it->sg);
+ it->dma = sg_dma_address(it->sg);
+ it->max = it->dma + sg_dma_len(it->sg);
+ } while (bytes_to_cpy);
+}
+
int
intel_context_migrate_copy(struct intel_context *ce,
const struct i915_deps *deps,
@@ -644,9 +703,15 @@ intel_context_migrate_copy(struct intel_context *ce,
bool dst_is_lmem,
struct i915_request **out)
{
- struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
+ struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst), it_ccs;
+ struct drm_i915_private *i915 = ce->engine->i915;
+ u32 ccs_bytes_to_cpy = 0, bytes_to_cpy;
+ enum i915_cache_level ccs_cache_level;
+ int src_sz, dst_sz, ccs_sz;
u32 src_offset, dst_offset;
+ u8 src_access, dst_access;
struct i915_request *rq;
+ bool ccs_is_src;
int err;
GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
@@ -655,6 +720,38 @@ intel_context_migrate_copy(struct intel_context *ce,
GEM_BUG_ON(ce->ring->size < SZ_64K);
+ src_sz = scatter_list_length(src);
+ bytes_to_cpy = src_sz;
+
+ if (HAS_FLAT_CCS(i915) && src_is_lmem ^ dst_is_lmem) {
+ src_access = !src_is_lmem && dst_is_lmem;
+ dst_access = !src_access;
+
+ dst_sz = scatter_list_length(dst);
+ if (src_is_lmem) {
+ it_ccs = it_dst;
+ ccs_cache_level = dst_cache_level;
+ ccs_is_src = false;
+ } else if (dst_is_lmem) {
+ bytes_to_cpy = dst_sz;
+ it_ccs = it_src;
+
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
> -Original Message-
> From: Jani Nikula
> Sent: Friday, April 1, 2022 5:31 PM
> To: Dixit, Ashutosh ; Gupta, Anshuman
>
> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> ;
> Vivi, Rodrigo
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime
> status
>
> On Tue, 29 Mar 2022, "Dixit, Ashutosh" wrote:
> > On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
> >>
> >> +#ifdef CONFIG_PM
> >> +static int i915_runtime_dump_child_status(struct device *dev, void
> >> +*data) {
> >> + struct seq_file *m = data;
> >> + const char *rpm_status;
> >> +
> >> + /* Early return if runtime_pm is disabled */
> >> + if (dev->power.disable_depth)
> >> + return 0;
> >> +
> >> + switch (dev->power.runtime_status) {
> >> + case RPM_SUSPENDED:
> >> + rpm_status = "suspended";
> >> + break;
> >> + case RPM_SUSPENDING:
> >> + rpm_status = "suspending";
> >> + break;
> >> + case RPM_RESUMING:
> >> + rpm_status = "resuming";
> >> + break;
> >> + case RPM_ACTIVE:
> >> + rpm_status = "active";
> >> + break;
> >> + default:
> >> + rpm_status = "unknown";
> >> + }
> >> +
> >> + seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
> >> + dev_name(dev), rpm_status);
> >> +
> >> + return 0;
> >> +}
> >> +#endif
> >
> > Maybe a nit, but perhaps defining a const array is better than having
> > a switch statement? Similar to what is done in rtpm_status_str(). The
> > function itself is very similar to rtpm_status_str() so can probably
> > benefit from that similarity. Can perhaps even be nearly identical to
> > rtpm_status_str() (since that is static in the genpd (generic power
> > domain) code).
> >
> > See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
> > generic_pm_domain-s"), though I am not sure if genpd's are applicable
> > in our case and certainly look way out of scope for now. Thanks.
>
> See also /sys/devices/i915/power/runtime_status and
> /sys/devices/i915/power/runtime_active_kids.
>
> Kinda feels like the info should be made available there?
runtime_active_kids we are already printing by
dev_priv->drm.dev->power.child_count.
About runtime_status , we already prints usage count and pci device power
state, IMO that is sufficient for debug ?
If it is really needed , I will add dev->power.runtime_status in next revision.
Thanks,
Anshuman Gupta.
>
> BR,
> Jani.
>
> >
> >> +
> >> static int i915_runtime_pm_status(struct seq_file *m, void *unused)
> >> {
> >>struct drm_i915_private *dev_priv = node_to_i915(m->private); @@
> >>-500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file
> >>*m, void *unused)
> >> #ifdef CONFIG_PM
> >>seq_printf(m, "Usage count: %d\n",
> >> atomic_read(&dev_priv->drm.dev->power.usage_count));
> >> + seq_printf(m, "Runtime active children: %d\n",
> >> + atomic_read(&dev_priv->drm.dev->power.child_count));
> >> + device_for_each_child(&pdev->dev, m,
> >> +i915_runtime_dump_child_status);
> >> +
> >> #else
> >>seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
> >> #endif
> >> --
> >> 2.26.2
> >>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/display/debugfs: Add connector debugfs for "output_bpc"
On Tue, 29 Mar 2022, Bhanuprakash Modem wrote:
> This new debugfs will expose the connector's max supported bpc
> and the bpc currently using. It is very useful for verifying
> whether we enter the correct output color depth from IGT.
>
> Example:
> cat /sys/kernel/debug/dri/0/DP-1/output_bpc
> Current: 8
> Maximum: 10
>
> V2: Add connector's max bpc to i915_display_info
>
> Cc: Ville Syrjälä
> Cc: Uma Shankar
> Cc: Swati Sharma
> Signed-off-by: Bhanuprakash Modem
> ---
> .../drm/i915/display/intel_display_debugfs.c | 46 +++
> 1 file changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index c1e74a13a0828..694d27f3b109c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -663,6 +663,8 @@ static void intel_connector_info(struct seq_file *m,
> seq_puts(m, "\tHDCP version: ");
> intel_hdcp_info(m, intel_connector);
>
> + seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc);
> +
> intel_panel_info(m, intel_connector);
>
> seq_printf(m, "\tmodes:\n");
> @@ -2275,6 +2277,47 @@ static const struct file_operations i915_dsc_bpp_fops
> = {
> .write = i915_dsc_bpp_write
> };
>
> +/*
> + * Returns the maximum output bpc for the connector.
> + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
> + */
> +static int output_bpc_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct drm_device *dev = connector->dev;
> + struct drm_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> + int res;
> +
> + if (!encoder)
> + return -ENODEV;
> +
> + res =
> drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
> + if (res)
> + return res;
> +
> + crtc = connector->state->crtc;
> + if (connector->status != connector_status_connected || !crtc) {
> + res = -ENODEV;
> + goto unlock;
> + }
> +
> + crtc_state = to_intel_crtc_state(crtc->state);
> + if (!crtc_state->hw.active)
> + goto unlock;
> +
> + seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3);
> + seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
> + res = 0;
> +
> +unlock:
> + drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
> + return res;
> +}
> +DEFINE_SHOW_ATTRIBUTE(output_bpc);
Looks like an excessive amount of code for a single value.
BR,
Jani.
> +
> /**
> * intel_connector_debugfs_add - add i915 specific connector debugfs files
> * @connector: pointer to a registered drm_connector
> @@ -2330,6 +2373,9 @@ void intel_connector_debugfs_add(struct intel_connector
> *intel_connector)
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
> debugfs_create_file("i915_lpsp_capability", 0444, root,
> connector, &i915_lpsp_capability_fops);
> +
> + debugfs_create_file("output_bpc", 0444, root,
> + connector, &output_bpc_fops);
> }
>
> /**
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/dmc: Add DMC_EVT_HTP and DMC_EVT_CTL programming
On Mon, 28 Mar 2022, Anusha Srivatsa wrote:
> We need add some checks around DMC reloading to
> prevents the rare possibility of some adversary
> writing to a random mmio register
I've recently merged cleanup to localize all DMC register definitions to
a new file display/intel_dmc_regs.h, and all DMC register access to
intel_dmc.c.
Basically if it's about DMC, it should be in intel_dmc.c, not spread
around.
BR,
Jani.
>
> BSpec: 49193
>
> Cc: Imre Deak
> Signed-off-by: Anusha Srivatsa
> ---
> .../drm/i915/display/intel_display_power.c| 23 +++
> drivers/gpu/drm/i915/i915_reg.h | 10
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 3dc859032bac..81cc4c658e3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -29,6 +29,8 @@
> #include "intel_vga.h"
> #include "vlv_sideband.h"
>
> +#define DMC_EVT_HTP_CTL_MAX 8
> +
> const char *
> intel_display_power_domain_str(enum intel_display_power_domain domain)
> {
> @@ -1101,6 +1103,26 @@ static void gen9_assert_dbuf_enabled(struct
> drm_i915_private *dev_priv)
>enabled_dbuf_slices);
> }
>
> +static void tgl_dmc_mmio_prog(struct drm_i915_private *dev_priv)
> +{
> + struct intel_dmc *dmc = &dev_priv->dmc;
> + int i, id;
> +
> + for (i = 0; i <= DMC_EVT_HTP_CTL_MAX; i++) {
> + intel_de_write(dev_priv, TGL_MAIN_DMC_EVT_CTL(i),
> DMC_EVT_CTL_VAL);
> + intel_de_write(dev_priv, TGL_MAIN_DMC_EVT_HTP(i),
> DMC_EVT_HTP_VAL);
> + }
> + /* Pipe DMC MMIOs */
> + for (id = 1; i <= DMC_FW_MAX; id++) {
> + for (i = 0; i <= DMC_EVT_HTP_CTL_MAX; i++) {
> + intel_de_write(dev_priv,
> PIPEDMC_EVT_CTL_OFFSET(dmc->dmc_info[id].start_mmioaddr, i),
> + DMC_EVT_CTL_VAL);
> + intel_de_write(dev_priv,
> PIPEDMC_EVT_HTP_OFFSET(dmc->dmc_info[id].start_mmioaddr, i),
> + DMC_EVT_HTP_VAL);
> + }
> + }
> +}
> +
> static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_config cdclk_config = {};
> @@ -1139,6 +1161,7 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> gen9_disable_dc_states(dev_priv);
> + tgl_dmc_mmio_prog(dev_priv);
> }
>
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d652f19ff9..7e3ef777c26d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5525,6 +5525,16 @@
> #define TGL_DMC_DEBUG3 _MMIO(0x101090)
> #define DG1_DMC_DEBUG3 _MMIO(0x13415c)
>
> +/* Main DMC EVT_HTP and EVT_CTL registers */
> +#define DMC_EVT_CTL_VAL 0x00030100
> +#define DMC_EVT_HTP_VAL 0x
> +#define TGL_MAIN_DMC_EVT_HTP(n) _MMIO(0x8F004 + (n) * 4)
> +#define TGL_MAIN_DMC_EVT_CTL(n) _MMIO(0x8F034 + (n) * 4)
> +#define PIPEDMC_EVT_HTP_BASE 0x4
> +#define PIPEDMC_EVT_CTL_BASE 0x00034
> +#define PIPEDMC_EVT_HTP_OFFSET(addr, i) _MMIO(addr +
> PIPEDMC_EVT_HTP_BASE + (i * 4))
> +#define PIPEDMC_EVT_CTL_OFFSET(addr, i) _MMIO(addr +
> PIPEDMC_EVT_CTL_BASE + (i * 4))
> +
> /* Display Internal Timeout Register */
> #define RM_TIMEOUT _MMIO(0x42060)
> #define MMIO_TIMEOUT_US(us) ((us) << 0)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
On Fri, 01 Apr 2022, "Gupta, Anshuman" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Friday, April 1, 2022 5:31 PM
>> To: Dixit, Ashutosh ; Gupta, Anshuman
>>
>> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
>> ;
>> Vivi, Rodrigo
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime
>> status
>>
>> On Tue, 29 Mar 2022, "Dixit, Ashutosh" wrote:
>> > On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
>> >>
>> >> +#ifdef CONFIG_PM
>> >> +static int i915_runtime_dump_child_status(struct device *dev, void
>> >> +*data) {
>> >> + struct seq_file *m = data;
>> >> + const char *rpm_status;
>> >> +
>> >> + /* Early return if runtime_pm is disabled */
>> >> + if (dev->power.disable_depth)
>> >> + return 0;
>> >> +
>> >> + switch (dev->power.runtime_status) {
>> >> + case RPM_SUSPENDED:
>> >> + rpm_status = "suspended";
>> >> + break;
>> >> + case RPM_SUSPENDING:
>> >> + rpm_status = "suspending";
>> >> + break;
>> >> + case RPM_RESUMING:
>> >> + rpm_status = "resuming";
>> >> + break;
>> >> + case RPM_ACTIVE:
>> >> + rpm_status = "active";
>> >> + break;
>> >> + default:
>> >> + rpm_status = "unknown";
>> >> + }
>> >> +
>> >> + seq_printf(m, "\t%s %s: Runtime status: %s\n", dev_driver_string(dev),
>> >> +dev_name(dev), rpm_status);
>> >> +
>> >> + return 0;
>> >> +}
>> >> +#endif
>> >
>> > Maybe a nit, but perhaps defining a const array is better than having
>> > a switch statement? Similar to what is done in rtpm_status_str(). The
>> > function itself is very similar to rtpm_status_str() so can probably
>> > benefit from that similarity. Can perhaps even be nearly identical to
>> > rtpm_status_str() (since that is static in the genpd (generic power
>> > domain) code).
>> >
>> > See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
>> > generic_pm_domain-s"), though I am not sure if genpd's are applicable
>> > in our case and certainly look way out of scope for now. Thanks.
>>
>> See also /sys/devices/i915/power/runtime_status and
>> /sys/devices/i915/power/runtime_active_kids.
>>
>> Kinda feels like the info should be made available there?
> runtime_active_kids we are already printing by
> dev_priv->drm.dev->power.child_count.
> About runtime_status , we already prints usage count and pci device power
> state, IMO that is sufficient for debug ?
> If it is really needed , I will add dev->power.runtime_status in next
> revision.
My point is, the patch at hand adds runtime pm status printing that
isn't specific to drm or i915 into i915 debugfs. Why?
What is the reason we should take on the burden of maintaining this
while the right place for it might be in runtime pm code, benefiting
other drivers in addition to ours?
BR,
Jani.
> Thanks,
> Anshuman Gupta.
>
>
>
>
>>
>> BR,
>> Jani.
>>
>> >
>> >> +
>> >> static int i915_runtime_pm_status(struct seq_file *m, void *unused)
>> >> {
>> >> struct drm_i915_private *dev_priv = node_to_i915(m->private); @@
>> >>-500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file
>> >>*m, void *unused)
>> >> #ifdef CONFIG_PM
>> >> seq_printf(m, "Usage count: %d\n",
>> >> atomic_read(&dev_priv->drm.dev->power.usage_count));
>> >> + seq_printf(m, "Runtime active children: %d\n",
>> >> +atomic_read(&dev_priv->drm.dev->power.child_count));
>> >> + device_for_each_child(&pdev->dev, m,
>> >> +i915_runtime_dump_child_status);
>> >> +
>> >> #else
>> >> seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
>> >> #endif
>> >> --
>> >> 2.26.2
>> >>
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 0/3] drm/i915: Random cleanups
On Mon, 21 Mar 2022, Ville Syrjala wrote: > From: Ville Syrjälä > > Clean up a few random things that caught my eye. Dunno if this got reviewed and merged already, but anyway, on the series, Reviewed-by: Jani Nikula > > Ville Syrjälä (3): > drm/i915: Program i830 DPLL FP register later > drm/i915: Use drm_connector_attach_hdr_output_metadata_property() > drm/i915: Remove dead members from dev_priv > > drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_dp.c | 8 ++-- > drivers/gpu/drm/i915/i915_drv.h | 9 - > 3 files changed, 5 insertions(+), 18 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v8 0/3] Refactor GVT-g MMIO tracking table and handlers
To support the new mdev interfaces and the re-factor patches from Christoph, which moves the GVT-g code into a dedicated module, the GVT-g initialization path has to be separated into two phases: a) Early initialization. The early initialization of GVT requires to be done when loading i915. Mostly it's because the initial clean HW state needs to be saved before i915 touches the HW. b) Late initalization. This phases of initalization will setup the rest components of GVT-g, which can be done later when the dedicated module is being loaded. To initialize the GVT-g MMIO tracking table in the early initalization stage, which will be done in i915, the GVT-g MMIO tracking table needs to be sperated accordingly and moved into i915. --- v8: - Use SPDX header in the intel_gvt_mmio_table.c - Reference the gvt.h with path. (Jani) - Add a missing fix on mmio emulation path during my debug. - Fix a building problem on refreshed gvt-staging branch. (Christoph) v7: - Keep the marcos of device generation in GVT-g. (Christoph, Jani) v6: - Move the mmio_table.c into i915. (Christoph) - Keep init_device_info and related structures in GVT-g. (Christoph) - Refine the callbacks of the iterator. (Christoph) - Move the flags of MMIO register defination to GVT-g. (Chrsitoph) - Move the mmio block handling to GVT-g. v5: - Re-design the mmio table framework. (Christoph) v4: - Fix the errors of patch checking scripts. v3: - Fix the errors when CONFIG_DRM_I915_WERROR is turned on. (Jani) v2: - Implement a mmio table instead of generating it by marco in i915. (Jani) Zhi Wang (3): i915/gvt: Separate the MMIO tracking table from GVT-g i915/gvt: Save the initial HW state snapshot in i915 i915/gvt: Use the initial HW state snapshot saved in i915 drivers/gpu/drm/i915/Makefile |2 +- drivers/gpu/drm/i915/gvt/firmware.c | 25 +- drivers/gpu/drm/i915/gvt/gvt.h |3 +- drivers/gpu/drm/i915/gvt/handlers.c | 1031 ++- drivers/gpu/drm/i915/gvt/mmio.h |1 - drivers/gpu/drm/i915/gvt/reg.h |9 +- drivers/gpu/drm/i915/i915_drv.h |2 + drivers/gpu/drm/i915/intel_gvt.c| 92 +- drivers/gpu/drm/i915/intel_gvt.h| 21 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1290 +++ 10 files changed, 1559 insertions(+), 917 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_gvt_mmio_table.c -- 2.25.1
[Intel-gfx] [PATCH v8 2/3] i915/gvt: Save the initial HW state snapshot in i915
Save the initial HW state snapshot in i915 so that the rest code of GVT-g
can be moved into a dedicated module while it can still get a clean
initial HW state saved at the correct time during the initialization of
i915. The futhrer vGPU created by GVT-g will use this HW state as the
initial HW state.
---
v6:
- Remove the reference of intel_gvt_device_info.(Christoph)
- Refine the save_mmio() function. (Christoph)
Cc: Christoph Hellwig
Cc: Jason Gunthorpe
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Vivi Rodrigo
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_gvt.c | 92 +++-
2 files changed, 92 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 943267393ecb..abb39444b8be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -421,6 +421,8 @@ struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
u32 caps;
+ u32 *initial_mmio;
+ u8 *initial_cfg_space;
};
struct i915_selftest_stash {
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index cf6e98962d82..65daab2c4d9e 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -86,6 +86,85 @@ void intel_gvt_sanitize_options(struct drm_i915_private
*dev_priv)
dev_priv->params.enable_gvt = 0;
}
+static void free_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+}
+
+static void save_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
+ u32 size)
+{
+ struct drm_i915_private *dev_priv = iter->i915;
+ u32 *mmio, i;
+
+ for (i = offset; i < offset + size; i += 4) {
+ mmio = iter->data + i;
+ *mmio = intel_uncore_read_notrace(to_gt(dev_priv)->uncore,
+ _MMIO(i));
+ }
+}
+
+static int handle_mmio(struct intel_gvt_mmio_table_iter *iter,
+ u32 offset, u32 size)
+{
+ if (WARN_ON(!IS_ALIGNED(offset, 4)))
+ return -EINVAL;
+
+ save_mmio(iter, offset, size);
+ return 0;
+}
+
+static int save_initial_hw_state(struct drm_i915_private *dev_priv)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ struct i915_virtual_gpu *vgpu = &dev_priv->vgpu;
+ struct intel_gvt_mmio_table_iter iter;
+ void *mem;
+ int i, ret;
+
+ mem = kzalloc(PCI_CFG_SPACE_EXP_SIZE, GFP_KERNEL);
+ if (!mem)
+ return -ENOMEM;
+
+ vgpu->initial_cfg_space = mem;
+
+ for (i = 0; i < PCI_CFG_SPACE_EXP_SIZE; i += 4)
+ pci_read_config_dword(pdev, i, mem + i);
+
+ mem = vzalloc(2 * SZ_1M);
+ if (!mem) {
+ ret = -ENOMEM;
+ goto err_mmio;
+ }
+
+ vgpu->initial_mmio = mem;
+
+ iter.i915 = dev_priv;
+ iter.data = vgpu->initial_mmio;
+ iter.handle_mmio_cb = handle_mmio;
+
+ ret = intel_gvt_iterate_mmio_table(&iter);
+ if (ret)
+ goto err_iterate;
+
+ return 0;
+
+err_iterate:
+ vfree(vgpu->initial_mmio);
+ vgpu->initial_mmio = NULL;
+err_mmio:
+ kfree(vgpu->initial_cfg_space);
+ vgpu->initial_cfg_space = NULL;
+
+ return ret;
+}
+
/**
* intel_gvt_init - initialize GVT components
* @dev_priv: drm i915 private data
@@ -115,15 +194,23 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return -EIO;
}
+ ret = save_initial_hw_state(dev_priv);
+ if (ret) {
+ drm_dbg(&dev_priv->drm, "Fail to save initial HW state\n");
+ goto err_save_hw_state;
+ }
+
ret = intel_gvt_init_device(dev_priv);
if (ret) {
drm_dbg(&dev_priv->drm, "Fail to init GVT device\n");
- goto bail;
+ goto err_init_device;
}
return 0;
-bail:
+err_init_device:
+ free_initial_hw_state(dev_priv);
+err_save_hw_state:
dev_priv->params.enable_gvt = 0;
return 0;
}
@@ -147,6 +234,7 @@ void intel_gvt_driver_remove(struct drm_i915_private
*dev_priv)
return;
intel_gvt_clean_device(dev_priv);
+ free_initial_hw_state(dev_priv);
}
/**
--
2.25.1
[Intel-gfx] [PATCH v8 3/3] i915/gvt: Use the initial HW state snapshot saved in i915
The code of saving initial HW state snapshot has been moved into i915.
Let the GVT-g core logic use that snapshot.
Cc: Christoph Hellwig
Cc: Jason Gunthorpe
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Vivi Rodrigo
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/gvt/firmware.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/firmware.c
b/drivers/gpu/drm/i915/gvt/firmware.c
index 1a8274a3f4b1..54fe442238c6 100644
--- a/drivers/gpu/drm/i915/gvt/firmware.c
+++ b/drivers/gpu/drm/i915/gvt/firmware.c
@@ -66,22 +66,16 @@ static struct bin_attribute firmware_attr = {
.mmap = NULL,
};
-static int mmio_snapshot_handler(struct intel_gvt *gvt, u32 offset, void *data)
-{
- *(u32 *)(data + offset) = intel_uncore_read_notrace(gvt->gt->uncore,
- _MMIO(offset));
- return 0;
-}
-
static int expose_firmware_sysfs(struct intel_gvt *gvt)
{
struct intel_gvt_device_info *info = &gvt->device_info;
- struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
+ struct drm_i915_private *i915 = gvt->gt->i915;
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct gvt_firmware_header *h;
void *firmware;
void *p;
unsigned long size, crc32_start;
- int i, ret;
+ int ret;
size = sizeof(*h) + info->mmio_size + info->cfg_space_size;
firmware = vzalloc(size);
@@ -99,17 +93,16 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt)
p = firmware + h->cfg_space_offset;
- for (i = 0; i < h->cfg_space_size; i += 4)
- pci_read_config_dword(pdev, i, p + i);
-
- memcpy(gvt->firmware.cfg_space, p, info->cfg_space_size);
+ memcpy(gvt->firmware.cfg_space, i915->vgpu.initial_cfg_space,
+ info->cfg_space_size);
+ memcpy(p, gvt->firmware.cfg_space, info->cfg_space_size);
p = firmware + h->mmio_offset;
- /* Take a snapshot of hw mmio registers. */
- intel_gvt_for_each_tracked_mmio(gvt, mmio_snapshot_handler, p);
+ memcpy(gvt->firmware.mmio, i915->vgpu.initial_mmio,
+ info->mmio_size);
- memcpy(gvt->firmware.mmio, p, info->mmio_size);
+ memcpy(p, gvt->firmware.mmio, info->mmio_size);
crc32_start = offsetof(struct gvt_firmware_header, crc32) + 4;
h->crc32 = crc32_le(0, firmware + crc32_start, size - crc32_start);
--
2.25.1
[Intel-gfx] [PATCH v8 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
From: Zhi Wang
To support the new mdev interfaces and the re-factor patches from
Christoph, which moves the GVT-g code into a dedicated module, the GVT-g
MMIO tracking table needs to be separated from GVT-g.
---
v8:
- Use SPDX header in the intel_gvt_mmio_table.c
- Reference the gvt.h with path. (Jani)
- Add a missing fix on mmio emulation path during the debug.
- Fix a building problem on refreshed gvt-staging branch. (Christoph)
v7:
- Keep the marcos of device generation in GVT-g. (Christoph, Jani)
v6:
- Move the mmio_table.c into i915. (Christoph)
- Keep init_device_info and related structures in GVT-g. (Christoph)
- Refine the callbacks of the iterator. (Christoph)
- Move the flags of MMIO register defination to GVT-g. (Chrsitoph)
- Move the mmio block handling to GVT-g.
v5:
- Re-design the mmio table framework. (Christoph)
v4:
- Fix the errors of patch checking scripts.
v3:
- Fix the errors when CONFIG_DRM_I915_WERROR is turned on. (Jani)
v2:
- Implement a mmio table instead of generating it by marco in i915. (Jani)
Cc: Christoph Hellwig
Cc: Jason Gunthorpe
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Vivi Rodrigo
Cc: Zhenyu Wang
Cc: Zhi Wang
Signed-off-by: Zhi Wang
---
drivers/gpu/drm/i915/Makefile |2 +-
drivers/gpu/drm/i915/gvt/gvt.h |3 +-
drivers/gpu/drm/i915/gvt/handlers.c | 1031 ++-
drivers/gpu/drm/i915/gvt/mmio.h |1 -
drivers/gpu/drm/i915/gvt/reg.h |9 +-
drivers/gpu/drm/i915/intel_gvt.h| 21 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1290 +++
7 files changed, 1458 insertions(+), 899 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_gvt_mmio_table.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a771ee5b1d0..b4abe0650ba1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -321,7 +321,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
i915-y += i915_vgpu.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
-i915-y += intel_gvt.o
+i915-y += intel_gvt.o intel_gvt_mmio_table.o
include $(src)/gvt/Makefile
endif
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0ebffc327528..bfe07c69cfd2 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -36,6 +36,7 @@
#include
#include "i915_drv.h"
+#include "intel_gvt.h"
#include "debug.h"
#include "hypercall.h"
@@ -272,7 +273,7 @@ struct intel_gvt_mmio {
/* Value of command write of this reg needs to be patched */
#define F_CMD_WRITE_PATCH (1 << 8)
- const struct gvt_mmio_block *mmio_block;
+ struct gvt_mmio_block *mmio_block;
unsigned int num_mmio_block;
DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 520a7e1942f3..a84783eecd3b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -101,12 +101,11 @@ struct intel_gvt_mmio_info
*intel_gvt_find_mmio_info(struct intel_gvt *gvt,
return NULL;
}
-static int new_mmio_info(struct intel_gvt *gvt,
- u32 offset, u16 flags, u32 size,
- u32 addr_mask, u32 ro_mask, u32 device,
- gvt_mmio_func read, gvt_mmio_func write)
+static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
+ u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
+ gvt_mmio_func read, gvt_mmio_func write)
{
- struct intel_gvt_mmio_info *info, *p;
+ struct intel_gvt_mmio_info *p;
u32 start, end, i;
if (!intel_gvt_match_device(gvt, device))
@@ -119,32 +118,18 @@ static int new_mmio_info(struct intel_gvt *gvt,
end = offset + size;
for (i = start; i < end; i += 4) {
- info = kzalloc(sizeof(*info), GFP_KERNEL);
- if (!info)
- return -ENOMEM;
-
- info->offset = i;
- p = intel_gvt_find_mmio_info(gvt, info->offset);
- if (p) {
- WARN(1, "dup mmio definition offset %x\n",
- info->offset);
- kfree(info);
-
- /* We return -EEXIST here to make GVT-g load fail.
-* So duplicated MMIO can be found as soon as
-* possible.
-*/
- return -EEXIST;
+ p = intel_gvt_find_mmio_info(gvt, i);
+ if (!p) {
+ WARN(1, "assign a handler to a non-tracked mmio %x\n",
+ i);
+ return -ENODEV;
}
-
- info->ro_mask = ro_mask;
- info->device = device;
- info->read = read ? read : intel_vgpu_default_mmio_read;
- info->write = write
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
> -Original Message-
> From: Jani Nikula
> Sent: Friday, April 1, 2022 6:26 PM
> To: Gupta, Anshuman ; Dixit, Ashutosh
>
> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> ;
> Vivi, Rodrigo
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime
> status
>
> On Fri, 01 Apr 2022, "Gupta, Anshuman" wrote:
> >> -Original Message-
> >> From: Jani Nikula
> >> Sent: Friday, April 1, 2022 5:31 PM
> >> To: Dixit, Ashutosh ; Gupta, Anshuman
> >>
> >> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> >> ; Vivi, Rodrigo
> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children
> >> runtime status
> >>
> >> On Tue, 29 Mar 2022, "Dixit, Ashutosh" wrote:
> >> > On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
> >> >>
> >> >> +#ifdef CONFIG_PM
> >> >> +static int i915_runtime_dump_child_status(struct device *dev,
> >> >> +void
> >> >> +*data) {
> >> >> + struct seq_file *m = data;
> >> >> + const char *rpm_status;
> >> >> +
> >> >> + /* Early return if runtime_pm is disabled */
> >> >> + if (dev->power.disable_depth)
> >> >> + return 0;
> >> >> +
> >> >> + switch (dev->power.runtime_status) {
> >> >> + case RPM_SUSPENDED:
> >> >> + rpm_status = "suspended";
> >> >> + break;
> >> >> + case RPM_SUSPENDING:
> >> >> + rpm_status = "suspending";
> >> >> + break;
> >> >> + case RPM_RESUMING:
> >> >> + rpm_status = "resuming";
> >> >> + break;
> >> >> + case RPM_ACTIVE:
> >> >> + rpm_status = "active";
> >> >> + break;
> >> >> + default:
> >> >> + rpm_status = "unknown";
> >> >> + }
> >> >> +
> >> >> + seq_printf(m, "\t%s %s: Runtime status: %s\n",
> >> >> dev_driver_string(dev),
> >> >> + dev_name(dev), rpm_status);
> >> >> +
> >> >> + return 0;
> >> >> +}
> >> >> +#endif
> >> >
> >> > Maybe a nit, but perhaps defining a const array is better than
> >> > having a switch statement? Similar to what is done in
> >> > rtpm_status_str(). The function itself is very similar to
> >> > rtpm_status_str() so can probably benefit from that similarity. Can
> >> > perhaps even be nearly identical to
> >> > rtpm_status_str() (since that is static in the genpd (generic power
> >> > domain) code).
> >> >
> >> > See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
> >> > generic_pm_domain-s"), though I am not sure if genpd's are
> >> > applicable in our case and certainly look way out of scope for now.
> >> > Thanks.
> >>
> >> See also /sys/devices/i915/power/runtime_status and
> >> /sys/devices/i915/power/runtime_active_kids.
> >>
> >> Kinda feels like the info should be made available there?
> > runtime_active_kids we are already printing by dev_priv->drm.dev-
> >power.child_count.
> > About runtime_status , we already prints usage count and pci device power
> state, IMO that is sufficient for debug ?
> > If it is really needed , I will add dev->power.runtime_status in next
> > revision.
>
> My point is, the patch at hand adds runtime pm status printing that isn't
> specific
> to drm or i915 into i915 debugfs. Why?
>
> What is the reason we should take on the burden of maintaining this while the
> right place for it might be in runtime pm code, benefiting other drivers in
> addition to ours?
Benefit is there to debug CI runtime suspend failures , we need to know the
culprit child blocking i915 runtime PM.
runtime_active_kids just revels the count , it doesn't reveal the culprit
children.
Thanks,
Anshuman.
>
> BR,
> Jani.
>
>
> > Thanks,
> > Anshuman Gupta.
> >
> >
> >
> >
> >>
> >> BR,
> >> Jani.
> >>
> >> >
> >> >> +
> >> >> static int i915_runtime_pm_status(struct seq_file *m, void
> >> >>*unused)
> >> >> {
> >> >> struct drm_i915_private *dev_priv = node_to_i915(m->private); @@
> >> >>-500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file
> >> >>*m, void *unused)
> >> >> #ifdef CONFIG_PM
> >> >> seq_printf(m, "Usage count: %d\n",
> >> >>atomic_read(&dev_priv->drm.dev->power.usage_count));
> >> >> + seq_printf(m, "Runtime active children: %d\n",
> >> >> + atomic_read(&dev_priv->drm.dev->power.child_count));
> >> >> + device_for_each_child(&pdev->dev, m,
> >> >> +i915_runtime_dump_child_status);
> >> >> +
> >> >> #else
> >> >> seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
> >> >> #endif
> >> >> --
> >> >> 2.26.2
> >> >>
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v7 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
Hi Jani: Thanks so much for the guidance. :) I included it in the v8 patch. :) Thanks, Zhi. On 3/31/22 8:25 AM, Jani Nikula wrote: > On Thu, 31 Mar 2022, "Wang, Zhi A" wrote: >> Hi Jani and Joonas: >> >> Are you OK with these patches? I noticed I need to change the license >> of the new file. Will do that when check-in if you are OK with these. > > Use SPDX license header instead of the full text? > > I don't know much about the actual contents, I'll leave that part to > others. > > Seems that you are dropping const in a number of places where I thought > you could perhaps retain it. > > Also in drivers/gpu/drm/i915/intel_gvt_mmio_table.c: > > #include "gvt.h" > > looks bad. It should be "gvt/gvt.h". I realize you can do that because > gvt/Makefile has: > > ccflags-y += -I $(srctree)/$(src) -I $(srctree)/$(src)/$(GVT_DIR)/ > > which I think should be removed. > > I sent patches fixing this to give you an idea. No need to queue them > first, I can rebase them later. But please make sure this builds without > the ccflags. > > > BR, > Jani. > > >> >> Thanks, >> Zhi. >> >> On 3/28/22 6:50 AM, Christoph Hellwig wrote: >>> On Fri, Mar 25, 2022 at 01:52:49PM -0400, Zhi Wang wrote: v7: - Keep the marcos of device generation in GVT-g. (Christoph, Jani) >>> >>> The changelog go under the "---" line (also for the other patches). >>> >>> Otherwise looks good: >>> >>> Reviewed-by: Christoph Hellwig >>> >> >
Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/opregion: Abstract opregion function
On 2022-03-16 at 11:25:33 +0200, Jani Nikula wrote:
> On Sun, 20 Feb 2022, Anshuman Gupta wrote:
> > Abstract opregion operations like get opregion base, get rvda and
> > opregion cleanup in form of i915_opregion_ops.
> > This will be required to converge igfx and dgfx opregion.
> >
> > v2:
> > - Keep only function pointer abstraction stuff. [Jani]
> > - Add alloc_rvda error handling.
> >
> > v3:
> > - Added necessary credit to Manasi for static analysis fix around
> > drm_WARN_ON(&i915->drm, !opregion->asls || !opregion->header)
> >
> > Cc: Jani Nikula
> > Cc: Rodrigo Vivi
> > Cc: Badal Nilawar
> > Cc: Uma Shankar
> > Signed-off-by: Manasi Navare
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_opregion.c | 179 +-
> > drivers/gpu/drm/i915/display/intel_opregion.h | 3 +
> > 2 files changed, 134 insertions(+), 48 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index 9b56064ddb5d..94eb7c23fcb4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -138,6 +138,13 @@ struct opregion_asle_ext {
> > u8 rsvd[764];
> > } __packed;
> >
> > +struct i915_opregion_func {
> > + void *(*alloc_opregion)(struct drm_i915_private *i915);
> > + void *(*alloc_rvda)(struct drm_i915_private *i915);
> > + void (*free_rvda)(struct drm_i915_private *i915);
> > + void (*free_opregion)(struct drm_i915_private *i915);
> > +};
> > +
> > /* Driver readiness indicator */
> > #define ASLE_ARDY_READY(1 << 0)
> > #define ASLE_ARDY_NOT_READY(0 << 0)
> > @@ -876,10 +883,7 @@ static int intel_load_vbt_firmware(struct
> > drm_i915_private *dev_priv)
> > static int intel_opregion_setup(struct drm_i915_private *dev_priv)
> > {
> > struct intel_opregion *opregion = &dev_priv->opregion;
> > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > - u32 asls, mboxes;
> > - char buf[sizeof(OPREGION_SIGNATURE)];
> > - int err = 0;
> > + u32 mboxes;
> > void *base;
> > const void *vbt;
> > u32 vbt_size;
> > @@ -890,27 +894,12 @@ static int intel_opregion_setup(struct
> > drm_i915_private *dev_priv)
> > BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100);
> > BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400);
> >
> > - pci_read_config_dword(pdev, ASLS, &asls);
> > - drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n",
> > - asls);
> > - if (asls == 0) {
> > - drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n");
> > - return -ENOTSUPP;
> > - }
> > -
> > INIT_WORK(&opregion->asle_work, asle_work);
> >
> > - base = memremap(asls, OPREGION_SIZE, MEMREMAP_WB);
> > - if (!base)
> > - return -ENOMEM;
> > + base = opregion->opregion_func->alloc_opregion(dev_priv);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> >
> > - memcpy(buf, base, sizeof(buf));
> > -
> > - if (memcmp(buf, OPREGION_SIGNATURE, 16)) {
> > - drm_dbg(&dev_priv->drm, "opregion signature mismatch\n");
> > - err = -EINVAL;
> > - goto err_out;
> > - }
> > opregion->header = base;
> > opregion->lid_state = base + ACPI_CLID;
> >
> > @@ -970,23 +959,10 @@ static int intel_opregion_setup(struct
> > drm_i915_private *dev_priv)
> >
> > if (opregion->header->over.major >= 2 && opregion->asle &&
> > opregion->asle->rvda && opregion->asle->rvds) {
> > - resource_size_t rvda = opregion->asle->rvda;
> > -
> > - /*
> > -* opregion 2.0: rvda is the physical VBT address.
> > -*
> > -* opregion 2.1+: rvda is unsigned, relative offset from
> > -* opregion base, and should never point within opregion.
> > -*/
> > - if (opregion->header->over.major > 2 ||
> > - opregion->header->over.minor >= 1) {
> > - drm_WARN_ON(&dev_priv->drm, rvda < OPREGION_SIZE);
> > -
> > - rvda += asls;
> > - }
> >
> > - opregion->rvda = memremap(rvda, opregion->asle->rvds,
> > - MEMREMAP_WB);
> > + opregion->rvda = opregion->opregion_func->alloc_rvda(dev_priv);
>
> It's a basic principle of interfaces to do corresponding things at the
> same abstraction level.
>
> Now, you set opregion->rvda at the level that calls ->alloc_rvda,
> however ->free_rvda accesses opregion->rvda directly.
>
> Similarly for ->alloc_opregion and ->free_opregion.
Thanks for review comment.
Could you please shed light to make same abstraction level.
free_rvda(void *rvda)
{
IS_ERR(rvda)
return;
if (rvda) {
memunmap(opregion->rvda);
rvda = NULL;
}
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ttm: Evict and restore of compressed object (rev7)
== Series Details == Series: drm/i915/ttm: Evict and restore of compressed object (rev7) URL : https://patchwork.freedesktop.org/series/101106/ State : warning == Summary == $ dim checkpatch origin/drm-tip c7781263ce21 drm/i915/gt: use engine instance directly for offset 4b35aa78c844 drm/i915/gt: Use XY_FAST_COLOR_BLT to clear obj on graphics ver 12+ cd1f1f11df1b drm/i915/gt: Optimize the migration and clear loop de8e6525e810 drm/i915/gt: Clear compress metadata for Flat-ccs objects -:44: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #44: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:157: +#define MI_FLUSH_DW_CCS (1<<16) ^ -:47: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #47: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:160: +#define MI_FLUSH_DW_LLC (1<<9) ^ total: 0 errors, 0 warnings, 2 checks, 197 lines checked c00c4ecd5d06 drm/i915/selftest_migrate: Consider the possible roundup of size 886c492b3dfa drm/i915/selftest_migrate: Check CCS meta data clear b875586d6ccb drm/ttm: Add a parameter to add extra pages into ttm_tt -:93: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #93: FILE: drivers/gpu/drm/ttm/ttm_tt.c:150: + uint32_t page_flags, enum ttm_caching caching, -:140: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #140: FILE: include/drm/ttm/ttm_tt.h:151: + uint32_t page_flags, enum ttm_caching caching, total: 0 errors, 0 warnings, 2 checks, 88 lines checked b88b5b478be0 drm/i915/gem: Add extra pages in ttm_tt for ccs data e893bdce4102 drm/i915/migrate: Evict and restore the flatccs capable lmem obj
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ttm: Evict and restore of compressed object (rev7)
== Series Details == Series: drm/i915/ttm: Evict and restore of compressed object (rev7) URL : https://patchwork.freedesktop.org/series/101106/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
On Fri, 01 Apr 2022, "Gupta, Anshuman" wrote:
>> -Original Message-
>> From: Jani Nikula
>> Sent: Friday, April 1, 2022 6:26 PM
>> To: Gupta, Anshuman ; Dixit, Ashutosh
>>
>> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
>> ;
>> Vivi, Rodrigo
>> Subject: RE: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime
>> status
>>
>> On Fri, 01 Apr 2022, "Gupta, Anshuman" wrote:
>> >> -Original Message-
>> >> From: Jani Nikula
>> >> Sent: Friday, April 1, 2022 5:31 PM
>> >> To: Dixit, Ashutosh ; Gupta, Anshuman
>> >>
>> >> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
>> >> ; Vivi, Rodrigo
>> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children
>> >> runtime status
>> >>
>> >> On Tue, 29 Mar 2022, "Dixit, Ashutosh" wrote:
>> >> > On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
>> >> >>
>> >> >> +#ifdef CONFIG_PM
>> >> >> +static int i915_runtime_dump_child_status(struct device *dev,
>> >> >> +void
>> >> >> +*data) {
>> >> >> + struct seq_file *m = data;
>> >> >> + const char *rpm_status;
>> >> >> +
>> >> >> + /* Early return if runtime_pm is disabled */
>> >> >> + if (dev->power.disable_depth)
>> >> >> + return 0;
>> >> >> +
>> >> >> + switch (dev->power.runtime_status) {
>> >> >> + case RPM_SUSPENDED:
>> >> >> + rpm_status = "suspended";
>> >> >> + break;
>> >> >> + case RPM_SUSPENDING:
>> >> >> + rpm_status = "suspending";
>> >> >> + break;
>> >> >> + case RPM_RESUMING:
>> >> >> + rpm_status = "resuming";
>> >> >> + break;
>> >> >> + case RPM_ACTIVE:
>> >> >> + rpm_status = "active";
>> >> >> + break;
>> >> >> + default:
>> >> >> + rpm_status = "unknown";
>> >> >> + }
>> >> >> +
>> >> >> + seq_printf(m, "\t%s %s: Runtime status: %s\n",
>> >> >> dev_driver_string(dev),
>> >> >> + dev_name(dev), rpm_status);
>> >> >> +
>> >> >> + return 0;
>> >> >> +}
>> >> >> +#endif
>> >> >
>> >> > Maybe a nit, but perhaps defining a const array is better than
>> >> > having a switch statement? Similar to what is done in
>> >> > rtpm_status_str(). The function itself is very similar to
>> >> > rtpm_status_str() so can probably benefit from that similarity. Can
>> >> > perhaps even be nearly identical to
>> >> > rtpm_status_str() (since that is static in the genpd (generic power
>> >> > domain) code).
>> >> >
>> >> > See also 2bd5306a8764 ("PM / Domains: add debugfs listing of struct
>> >> > generic_pm_domain-s"), though I am not sure if genpd's are
>> >> > applicable in our case and certainly look way out of scope for now.
>> >> > Thanks.
>> >>
>> >> See also /sys/devices/i915/power/runtime_status and
>> >> /sys/devices/i915/power/runtime_active_kids.
>> >>
>> >> Kinda feels like the info should be made available there?
>> > runtime_active_kids we are already printing by dev_priv->drm.dev-
>> >power.child_count.
>> > About runtime_status , we already prints usage count and pci device power
>> state, IMO that is sufficient for debug ?
>> > If it is really needed , I will add dev->power.runtime_status in next
>> > revision.
>>
>> My point is, the patch at hand adds runtime pm status printing that isn't
>> specific
>> to drm or i915 into i915 debugfs. Why?
>>
>> What is the reason we should take on the burden of maintaining this while the
>> right place for it might be in runtime pm code, benefiting other drivers in
>> addition to ours?
> Benefit is there to debug CI runtime suspend failures , we need to know the
> culprit child blocking i915 runtime PM.
> runtime_active_kids just revels the count , it doesn't reveal the culprit
> children.
I understand. But how is that problem or the information specific to
i915? Why should this be added to i915 instead of runtime pm infra?
Surely this is not even a new problem; how do others currently figure
this information out?
So I'm not going to block this if you all think this is a good idea. But
the point is, the first solution should not be to add some i915 specific
stuff when a more generic solution might exist or be preferred.
BR,
Jani.
> Thanks,
> Anshuman.
>>
>> BR,
>> Jani.
>>
>>
>> > Thanks,
>> > Anshuman Gupta.
>> >
>> >
>> >
>> >
>> >>
>> >> BR,
>> >> Jani.
>> >>
>> >> >
>> >> >> +
>> >> >> static int i915_runtime_pm_status(struct seq_file *m, void
>> >> >>*unused)
>> >> >> {
>> >> >>struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> >> >> @@
>> >> >>-500,6 +534,10 @@ static int i915_runtime_pm_status(struct seq_file
>> >> >>*m, void *unused)
>> >> >> #ifdef CONFIG_PM
>> >> >>seq_printf(m, "Usage count: %d\n",
>> >> >> atomic_read(&dev_priv->drm.dev->power.usage_count));
>> >> >> + seq_printf(m, "Runtime active children: %d\n",
>> >> >> + atomic_read(&dev_priv->drm.dev->power.child_count));
>> >> >> +
Re: [Intel-gfx] [PATCH v2 00/12] drm/edid: cleanup and refactoring around validity checks
On Fri, Apr 01, 2022 at 11:55:21AM +0300, Jani Nikula wrote: > On Thu, 31 Mar 2022, Jani Nikula wrote: > > v2 of https://patchwork.freedesktop.org/series/101931/ > > > > Rebased, review comments addressed. > > Ville, care to double check patches 1 & 7 please? Looks fine by me Reviewed-by: Ville Syrjälä > > Thanks, > Jani. > > > > > > BR, > > Jani. > > > > > > > > Jani Nikula (12): > > drm/edid: use struct edid * in drm_do_get_edid() > > drm/edid: clean up EDID block checksum functions > > drm/edid: add edid_block_tag() helper to get the EDID extension tag > > drm/edid: make drm_edid_header_is_valid() accept void pointer > > drm/edid: clean up edid_is_zero() > > drm/edid: split out edid_header_fix() > > drm/edid: split drm_edid_block_valid() to check and act parts > > drm/edid: use a better variable name for EDID block read retries > > drm/edid: simplify block check when filtering invalid blocks > > drm/edid: split out invalid block filtering to a separate function > > drm/edid: track invalid blocks in drm_do_get_edid() > > drm/edid: reduce magic when updating the EDID block checksum > > > > drivers/gpu/drm/drm_edid.c | 295 + > > include/drm/drm_edid.h | 2 +- > > 2 files changed, 173 insertions(+), 124 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Ville Syrjälä Intel
[Intel-gfx] [PATCH i-g-t 0/3] Per client GPU utilisation
From: Tvrtko Ursulin Only first three patches for review purposes (first stage) - adding the test and intel_gpu_top support. Tvrtko Ursulin (3): lib: Helper library for parsing i915 fdinfo output tests/i915/drm_fdinfo: Basic and functional tests for GPU busyness exported via fdinfo intel-gpu-top: Add support for per client stats lib/igt_drm_fdinfo.c| 188 ++ lib/igt_drm_fdinfo.h| 69 lib/meson.build | 7 + man/intel_gpu_top.rst | 4 + tests/i915/drm_fdinfo.c | 557 +++ tests/meson.build | 8 + tools/intel_gpu_top.c | 806 +++- tools/meson.build | 2 +- 8 files changed, 1638 insertions(+), 3 deletions(-) create mode 100644 lib/igt_drm_fdinfo.c create mode 100644 lib/igt_drm_fdinfo.h create mode 100644 tests/i915/drm_fdinfo.c -- 2.32.0
[Intel-gfx] [PATCH i-g-t 1/3] lib: Helper library for parsing i915 fdinfo output
From: Tvrtko Ursulin
Tests and intel_gpu_top will share common code for parsing this file.
v2:
* Fix key-value parsing if valid key line ends with ':'.
* Return number of drm keys found.
* Add DRM_CLIENT_FDINFO_MAX_ENGINES. (Umesh)
* Always zero terminate read buffer. (Umesh)
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 188 +++
lib/igt_drm_fdinfo.h | 69
lib/meson.build | 7 ++
3 files changed, 264 insertions(+)
create mode 100644 lib/igt_drm_fdinfo.c
create mode 100644 lib/igt_drm_fdinfo.h
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
new file mode 100644
index ..b422f67a4ace
--- /dev/null
+++ b/lib/igt_drm_fdinfo.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h"
+
+#include "igt_drm_fdinfo.h"
+
+static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name)
+{
+ size_t count;
+ int fd;
+
+ fd = openat(at, name, O_RDONLY);
+ if (fd < 0)
+ return 0;
+
+ buf[sz - 1] = 0;
+ count = read(fd, buf, sz);
+ buf[sz - 1] = 0;
+ close(fd);
+
+ return count;
+}
+
+static int parse_engine(char *line, struct drm_client_fdinfo *info,
+ size_t prefix_len, uint64_t *val)
+{
+ static const char *e2class[] = {
+ "render",
+ "copy",
+ "video",
+ "video-enhance",
+ };
+ ssize_t name_len;
+ char *name, *p;
+ int found = -1;
+ unsigned int i;
+
+ p = index(line, ':');
+ if (!p || p == line)
+ return -1;
+
+ name_len = p - line - prefix_len;
+ if (name_len < 1)
+ return -1;
+
+ name = line + prefix_len;
+
+ for (i = 0; i < ARRAY_SIZE(e2class); i++) {
+ if (!strncmp(name, e2class[i], name_len)) {
+ found = i;
+ break;
+ }
+ }
+
+ if (found >= 0) {
+ while (*++p && isspace(*p));
+ *val = strtoull(p, NULL, 10);
+ }
+
+ return found;
+}
+
+static const char *find_kv(const char *buf, const char *key, size_t keylen)
+{
+ const char *p = buf;
+
+ if (strncmp(buf, key, keylen))
+ return NULL;
+
+ p = index(buf, ':');
+ if (!p || p == buf)
+ return NULL;
+ if ((p - buf) != keylen)
+ return NULL;
+
+ p++;
+ while (*p && isspace(*p))
+ p++;
+
+ return *p ? p : NULL;
+}
+
+unsigned int
+__igt_parse_drm_fdinfo(int dir, const char *fd, struct drm_client_fdinfo *info)
+{
+ char buf[4096], *_buf = buf;
+ char *l, *ctx = NULL;
+ unsigned int good = 0, num_capacity = 0;
+ size_t count;
+
+ count = read_fdinfo(buf, sizeof(buf), dir, fd);
+ if (!count)
+ return 0;
+
+ while ((l = strtok_r(_buf, "\n", &ctx))) {
+ uint64_t val = 0;
+ const char *v;
+ int idx;
+
+ _buf = NULL;
+
+ if ((v = find_kv(l, "drm-driver", strlen("drm-driver" {
+ strncpy(info->driver, v, sizeof(info->driver) - 1);
+ good++;
+ } else if ((v = find_kv(l, "drm-pdev", strlen("drm-pdev" {
+ strncpy(info->pdev, v, sizeof(info->pdev) - 1);
+ } else if ((v = find_kv(l, "drm-client-id",
+strlen("drm-client-id" {
+ info->id = atol(v);
+ good++;
+ } else if (!strncmp(l, "drm-engine-", 11) &&
+ strncmp(l,
[Intel-gfx] [PATCH i-g-t 2/3] tests/i915/drm_fdinfo: Basic and functional tests for GPU busyness exported via fdinfo
From: Tvrtko Ursulin
Mostly inherited from the perf_pmu, some basic tests, and some tests to
verify exported GPU busyness is as expected.
v2:
* Skip when kernel does not export drm keys in fdinfo.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
---
tests/i915/drm_fdinfo.c | 557
tests/meson.build | 8 +
2 files changed, 565 insertions(+)
create mode 100644 tests/i915/drm_fdinfo.c
diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
new file mode 100644
index ..3475d35b23b9
--- /dev/null
+++ b/tests/i915/drm_fdinfo.c
@@ -0,0 +1,557 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt.h"
+#include "igt_core.h"
+#include "igt_device.h"
+#include "igt_drm_fdinfo.h"
+#include "i915/gem.h"
+#include "intel_ctx.h"
+
+IGT_TEST_DESCRIPTION("Test the i915 drm fdinfo data");
+
+const double tolerance = 0.05f;
+const unsigned long batch_duration_ns = 500e6;
+
+#define __assert_within_epsilon(x, ref, tol_up, tol_down) \
+ igt_assert_f((double)(x) <= (1.0 + (tol_up)) * (double)(ref) && \
+(double)(x) >= (1.0 - (tol_down)) * (double)(ref), \
+"'%s' != '%s' (%f not within +%.1f%%/-%.1f%% tolerance of
%f)\n",\
+#x, #ref, (double)(x), \
+(tol_up) * 100.0, (tol_down) * 100.0, \
+(double)(ref))
+
+#define assert_within_epsilon(x, ref, tolerance) \
+ __assert_within_epsilon(x, ref, tolerance, tolerance)
+
+static void basics(int i915, unsigned int num_classes)
+{
+ struct drm_client_fdinfo info = { };
+ unsigned int ret;
+
+ ret = igt_parse_drm_fdinfo(i915, &info);
+ igt_assert(ret);
+
+ igt_assert(!strcmp(info.driver, "i915"));
+
+ igt_assert_eq(info.num_engines, num_classes);
+}
+
+/*
+ * Helper for cases where we assert on time spent sleeping (directly or
+ * indirectly), so make it more robust by ensuring the system sleep time
+ * is within test tolerance to start with.
+ */
+static unsigned int measured_usleep(unsigned int usec)
+{
+ struct timespec ts = { };
+ unsigned int slept;
+
+ slept = igt_nsec_elapsed(&ts);
+ igt_assert(slept == 0);
+ do {
+ usleep(usec - slept);
+ slept = igt_nsec_elapsed(&ts) / 1000;
+ } while (slept < usec);
+
+ return igt_nsec_elapsed(&ts);
+}
+
+#define TEST_BUSY (1)
+#define FLAG_SYNC (2)
+#define TEST_TRAILING_IDLE (4)
+#define FLAG_HANG (8)
+#define TEST_ISOLATION (16)
+
+static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ struct igt_spin_factory opts = {
+ .ahnd = ahnd,
+ .ctx = ctx,
+ .engine = e->flags,
+ };
+
+ if (gem_class_can_store_dword(fd, e->class))
+ opts.flags |= IGT_SPIN_POLL_RUN;
+
+ return __igt_spin_factory(fd, &opts);
+}
+
+static unsigned long __spin_wait(int fd, igt_spin_t *spin)
+{
+ struct timespec start = { };
+
+ igt_nsec_elapsed(&start);
+
+ if (igt_spin_has_poll(spin)) {
+ unsigned long timeout = 0;
+
+ while (!igt_spin_has_started(spin)) {
+ unsigned long t = igt_nsec_elapsed(&start);
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ if ((t - timeout) > 250e6) {
+ timeout = t;
+ igt_warn("Spinner not running after %.2fms\n",
+(double)t / 1e6);
+ igt_assert(t < 2e9);
+ }
+ }
+ } else {
+ igt_debug("__spin_wait - usleep mode\n");
+ usleep(500e3)
[Intel-gfx] [PATCH i-g-t 3/3] intel-gpu-top: Add support for per client stats
From: Tvrtko Ursulin
Use the i915 exported data in /proc//fdinfo to show GPU utilization
per DRM client.
Example of the output:
intel-gpu-top: Intel Tigerlake (Gen12) @ /dev/dri/card0 - 220/ 221 MHz
70% RC6; 0.62/ 7.08 W; 760 irqs/s
ENGINES BUSY MI_SEMA MI_WAIT
Render/3D 23.06% |██▊ | 0% 0%
Blitter0.00% | | 0% 0%
Video5.40% |█▋ | 0% 0%
VideoEnhance 20.67% |██ | 0% 0%
PID NAME Render/3DBlitter VideoVideoEnhance
3082 mpv | || ||▌ ||██|
3117 neverball |█▉|| || || |
1 systemd |▍ || || || |
2338 gnome-shell | || || || |
v2:
* Removed hardcoded array size from client add/update by passing in
drm_fd_info directly.
* Added some asserts and simplified a couple expressions. (Umesh)
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
---
man/intel_gpu_top.rst | 4 +
tools/intel_gpu_top.c | 806 +-
tools/meson.build | 2 +-
3 files changed, 809 insertions(+), 3 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index b3b765b05feb..f4dbfc5b44d9 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -56,6 +56,10 @@ Supported keys:
'q'Exit from the tool.
'h'Show interactive help.
'1'Toggle between aggregated engine class and physical engine mode.
+'n'Toggle display of numeric client busyness overlay.
+'s'Toggle between sort modes (runtime, total runtime, pid, client id).
+'i'Toggle display of clients which used no GPU time.
+'H'Toggle between per PID aggregation and individual clients.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index bc11fce2bb1e..1984c10dca29 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -43,8 +43,10 @@
#include
#include
#include
+#include
#include "igt_perf.h"
+#include "igt_drm_fdinfo.h"
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
@@ -311,7 +313,8 @@ static int engine_cmp(const void *__a, const void *__b)
return a->instance - b->instance;
}
-#define is_igpu_pci(x) (strcmp(x, ":00:02.0") == 0)
+#define IGPU_PCI ":00:02.0"
+#define is_igpu_pci(x) (strcmp(x, IGPU_PCI) == 0)
#define is_igpu(x) (strcmp(x, "i915") == 0)
static struct engines *discover_engines(char *device)
@@ -635,6 +638,552 @@ static void pmu_sample(struct engines *engines)
}
}
+enum client_status {
+ FREE = 0, /* mbz */
+ ALIVE,
+ PROBE
+};
+
+struct clients;
+
+struct client {
+ struct clients *clients;
+
+ enum client_status status;
+ unsigned int id;
+ unsigned int pid;
+ char name[24];
+ char print_name[24];
+ unsigned int samples;
+ unsigned long total_runtime;
+ unsigned long last_runtime;
+ unsigned long *val;
+ uint64_t *last;
+};
+
+struct clients {
+ unsigned int num_clients;
+ unsigned int active_clients;
+
+ unsigned int num_classes;
+ struct engine_class *class;
+
+ char pci_slot[64];
+
+ struct client *client;
+};
+
+#define for_each_client(clients, c, tmp) \
+ for ((tmp) = (clients)->num_clients, c = (clients)->client; \
+(tmp > 0); (tmp)--, (c)++)
+
+static struct clients *init_clients(const char *pci_slot)
+{
+ struct clients *clients;
+
+ clients = malloc(sizeof(*clients));
+ if (!clients)
+ return NULL;
+
+ memset(clients, 0, sizeof(*clients));
+
+ strncpy(clients->pci_slot, pci_slot, sizeof(clients->pci_slot));
+
+ return clients;
+}
+
+static struct client *
+find_client(struct clients *clients, enum client_status status, unsigned int
id)
+{
+ unsigned int start, num;
+ struct client *c;
+
+ start = status == FREE ? clients->active_clients : 0; /* Free block at
the end. */
+ num = clients->num_clients - start;
+
+ for (c = &clients->client[start]; num; c++, num--) {
+ if (status != c->status)
+ continue;
+
+ if (status == FREE || c->id == id)
+ return c;
+ }
+
+ return NULL;
+}
+
+static void
+update_client(struct client *c, unsigned int pid, char *name,
+ const struct drm_client_fdinfo *info)
+{
+ unsigned int i;
+
+ if (c->pid != pid)
+ c->pid = pid;
+
+ if (strcmp(c->name, name)) {
+ char *p;
+
+ strncpy(c->name, name, sizeof(c->name) - 1);
+ strncpy(c->print_name, name, size
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/ttm: Evict and restore of compressed object (rev7)
== Series Details == Series: drm/i915/ttm: Evict and restore of compressed object (rev7) URL : https://patchwork.freedesktop.org/series/101106/ State : success == Summary == CI Bug Log - changes from CI_DRM_11438 -> Patchwork_22758 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/index.html Participating hosts (42 -> 41) -- Additional (4): bat-adlm-1 fi-icl-u2 fi-kbl-guc fi-kbl-8809g Missing(5): fi-kbl-soraka shard-tglu fi-bsw-cyan bat-rpls-2 fi-bdw-samus Known issues Here are the changes found in Patchwork_22758 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-guc: NOTRUN -> [SKIP][3] ([fdo#109271]) +18 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-guc/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4] ([i915#4962]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-guc/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][10] -> [INCOMPLETE][11] ([i915#4785]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_busy@basic: - fi-kbl-guc: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1845]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-guc/igt@kms_b...@basic.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_chamelium@vga-hpd-fast: - fi-kbl-guc: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-kbl-guc/igt@kms_chamel...@vga-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109278]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1: - fi-tgl-u2: [PASS][17] -> [DMESG-WARN][18] ([i915#402]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][19] ([fdo#109285]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_2
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor GVT-g MMIO tracking table and handlers
== Series Details == Series: Refactor GVT-g MMIO tracking table and handlers URL : https://patchwork.freedesktop.org/series/102073/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/intel_gvt_mmio_table.o drivers/gpu/drm/i915/intel_gvt_mmio_table.c: In function ‘iterate_skl_plus_mmio’: drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1021:9: error: ‘DMC_SSP_BASE’ undeclared (first use in this function); did you mean ‘FBC_CFB_BASE’? MMIO_D(DMC_SSP_BASE); ^~~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:17:56: note: in definition of macro ‘MMIO_F’ ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \ ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1021:2: note: in expansion of macro ‘MMIO_D’ MMIO_D(DMC_SSP_BASE); ^~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1021:9: note: each undeclared identifier is reported only once for each function it appears in MMIO_D(DMC_SSP_BASE); ^~~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:17:56: note: in definition of macro ‘MMIO_F’ ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \ ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1021:2: note: in expansion of macro ‘MMIO_D’ MMIO_D(DMC_SSP_BASE); ^~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1022:9: error: ‘DMC_HTP_SKL’ undeclared (first use in this function); did you mean ‘D_PRE_SKL’? MMIO_D(DMC_HTP_SKL); ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:17:56: note: in definition of macro ‘MMIO_F’ ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \ ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1022:2: note: in expansion of macro ‘MMIO_D’ MMIO_D(DMC_HTP_SKL); ^~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1023:9: error: ‘DMC_LAST_WRITE’ undeclared (first use in this function); did you mean ‘DRM_LIST_WAIT’? MMIO_D(DMC_LAST_WRITE); ^~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:17:56: note: in definition of macro ‘MMIO_F’ ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \ ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1023:2: note: in expansion of macro ‘MMIO_D’ MMIO_D(DMC_LAST_WRITE); ^~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1080:15: error: ‘DMC_MMIO_START_RANGE’ undeclared (first use in this function); did you mean ‘DRM_MM_INSERT_ONCE’? MMIO_F(_MMIO(DMC_MMIO_START_RANGE), 0x3000); ^~~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:17:56: note: in definition of macro ‘MMIO_F’ ret = iter->handle_mmio_cb(iter, i915_mmio_reg_offset(reg), s); \ ^~~ drivers/gpu/drm/i915/intel_gvt_mmio_table.c:1080:9: note: in expansion of macro ‘_MMIO’ MMIO_F(_MMIO(DMC_MMIO_START_RANGE), 0x3000); ^ scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/intel_gvt_mmio_table.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_gvt_mmio_table.o] Error 1 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1831: recipe for target 'drivers' failed make: *** [drivers] Error 2
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 03/11] intel-gpu-top: Add support for per client stats
On 31/03/2022 23:08, Umesh Nerlige Ramappa wrote:
lgtm, I just have a few nits and questions below:
Regardless, this is
Reviewed-by: Umesh Nerlige Ramappa
Thanks!
I've sent the updated series with only first three patches for first
stage. Only first patch misses the r-b now.
Rest of the comments below.
On Tue, Feb 22, 2022 at 01:55:57PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Use the i915 exported data in /proc//fdinfo to show GPU utilization
per DRM client.
Example of the output:
intel-gpu-top: Intel Tigerlake (Gen12) @ /dev/dri/card0 - 220/ 221 MHz
70% RC6; 0.62/ 7.08 W; 760 irqs/s
ENGINES BUSY MI_SEMA MI_WAIT
Render/3D 23.06% |██▊ | 0% 0%
Blitter 0.00% | | 0% 0%
Video 5.40% |█▋ | 0% 0%
VideoEnhance 20.67% |██ | 0% 0%
PID NAME Render/3D Blitter Video VideoEnhance
3082 mpv | || ||▌ ||██ |
3117 neverball |█▉ || || || |
1 systemd |▍ || || || |
2338 gnome-shell | || || || |
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 4 +
tools/intel_gpu_top.c | 801 +-
tools/meson.build | 2 +-
3 files changed, 804 insertions(+), 3 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rst
index b3b765b05feb..f4dbfc5b44d9 100644
--- a/man/intel_gpu_top.rst
+++ b/man/intel_gpu_top.rst
@@ -56,6 +56,10 @@ Supported keys:
'q' Exit from the tool.
'h' Show interactive help.
'1' Toggle between aggregated engine class and physical engine
mode.
+ 'n' Toggle display of numeric client busyness overlay.
+ 's' Toggle between sort modes (runtime, total runtime, pid,
client id).
+ 'i' Toggle display of clients which used no GPU time.
+ 'H' Toggle between per PID aggregation and individual clients.
DEVICE SELECTION
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index bc11fce2bb1e..73815cdea8aa 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -43,8 +43,10 @@
#include
#include
#include
+#include
#include "igt_perf.h"
+#include "igt_drm_fdinfo.h"
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
@@ -311,7 +313,8 @@ static int engine_cmp(const void *__a, const void
*__b)
return a->instance - b->instance;
}
-#define is_igpu_pci(x) (strcmp(x, ":00:02.0") == 0)
+#define IGPU_PCI ":00:02.0"
+#define is_igpu_pci(x) (strcmp(x, IGPU_PCI) == 0)
#define is_igpu(x) (strcmp(x, "i915") == 0)
static struct engines *discover_engines(char *device)
@@ -635,6 +638,547 @@ static void pmu_sample(struct engines *engines)
}
}
+enum client_status {
+ FREE = 0, /* mbz */
+ ALIVE,
+ PROBE
+};
+
+struct clients;
+
+struct client {
+ struct clients *clients;
+
+ enum client_status status;
+ unsigned int id;
+ unsigned int pid;
+ char name[24];
+ char print_name[24];
+ unsigned int samples;
+ unsigned long total_runtime;
+ unsigned long last_runtime;
+ unsigned long *val;
+ uint64_t *last;
+};
+
+struct clients {
+ unsigned int num_clients;
+ unsigned int active_clients;
+
+ unsigned int num_classes;
+ struct engine_class *class;
+
+ char pci_slot[64];
+
+ struct client *client;
+};
+
+#define for_each_client(clients, c, tmp) \
+ for ((tmp) = (clients)->num_clients, c = (clients)->client; \
+ (tmp > 0); (tmp)--, (c)++)
+
+static struct clients *init_clients(const char *pci_slot)
+{
+ struct clients *clients;
+
+ clients = malloc(sizeof(*clients));
+ if (!clients)
+ return NULL;
+
+ memset(clients, 0, sizeof(*clients));
+
+ strncpy(clients->pci_slot, pci_slot, sizeof(clients->pci_slot));
+
+ return clients;
+}
+
+static struct client *
+find_client(struct clients *clients, enum client_status status,
unsigned int id)
+{
+ unsigned int start, num;
+ struct client *c;
+
+ start = status == FREE ? clients->active_clients : 0; /* Free
block at the end. */
+ num = clients->num_clients - start;
+
+ for (c = &clients->client[start]; num; c++, num--) {
+ if (status != c->status)
+ continue;
+
+ if (status == FREE || c->id == id)
+ return c;
+ }
+
+ return NULL;
+}
+
+static void
+update_client(struct client *c, unsigned int pid, char *name,
uint64_t val[16])
+{
+ unsigned int i;
+
+ if (c->pid != pid)
+ c->pid = pid;
+
+ if (strcmp(c->name, name)) {
+ char *p;
+
+ strncpy(c->name, name, sizeof(c->name) - 1);
+ strncpy(c->print_name, name, sizeof(c->print_name) - 1);
+
+ p = c->print_name;
+ while (*p) {
[Intel-gfx] [CI 0/8] Per client GPU utilisation
From: Tvrtko Ursulin Test-with: 20220401141155.3122817-1-tvrtko.ursu...@linux.intel.com Tvrtko Ursulin (8): drm/i915: Explicitly track DRM clients drm/i915: Make GEM contexts track DRM clients drm/i915: Track runtime spent in closed and unreachable GEM contexts drm/i915: Track all user contexts per client drm/i915: Track context current active time drm: Document fdinfo format specification drm/i915: Count engine instances per uabi class drm/i915: Expose client engine utilisation via fdinfo Documentation/gpu/drm-usage-stats.rst | 112 + Documentation/gpu/i915.rst| 28 Documentation/gpu/index.rst | 1 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 43 - .../gpu/drm/i915/gem/i915_gem_context_types.h | 6 + drivers/gpu/drm/i915/gt/intel_context.c | 27 ++- drivers/gpu/drm/i915/gt/intel_context.h | 15 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 24 ++- drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 +- .../drm/i915/gt/intel_execlists_submission.c | 23 ++- .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 4 + drivers/gpu/drm/i915/gt/intel_lrc.c | 27 +-- drivers/gpu/drm/i915/gt/intel_lrc.h | 27 ++- drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +- drivers/gpu/drm/i915/i915_driver.c| 9 + drivers/gpu/drm/i915/i915_drm_client.c| 154 ++ drivers/gpu/drm/i915/i915_drm_client.h| 68 drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_file_private.h | 3 + drivers/gpu/drm/i915/i915_gem.c | 21 ++- drivers/gpu/drm/i915/i915_gpu_error.c | 9 +- drivers/gpu/drm/i915/i915_gpu_error.h | 2 +- 23 files changed, 569 insertions(+), 60 deletions(-) create mode 100644 Documentation/gpu/drm-usage-stats.rst create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h -- 2.32.0
[Intel-gfx] [CI 1/8] drm/i915: Explicitly track DRM clients
From: Tvrtko Ursulin
Tracking DRM clients more explicitly will allow later patches to
accumulate past and current GPU usage in a centralised place and also
consolidate access to owning task pid/name.
Unique client id is also assigned for the purpose of distinguishing/
consolidating between multiple file descriptors owned by the same process.
v2:
Chris Wilson:
* Enclose new members into dedicated structs.
* Protect against failed sysfs registration.
v3:
* sysfs_attr_init.
v4:
* Fix for internal clients.
v5:
* Use cyclic ida for client id. (Chris)
* Do not leak pid reference. (Chris)
* Tidy code with some locals.
v6:
* Use xa_alloc_cyclic to simplify locking. (Chris)
* No need to unregister individial sysfs files. (Chris)
* Rebase on top of fpriv kref.
* Track client closed status and reflect in sysfs.
v7:
* Make drm_client more standalone concept.
v8:
* Simplify sysfs show. (Chris)
* Always track name and pid.
v9:
* Fix cyclic id assignment.
v10:
* No need for a mutex around xa_alloc_cyclic.
* Refactor sysfs into own function.
* Unregister sysfs before freeing pid and name.
* Move clients setup into own function.
v11:
* Call clients init directly from driver init. (Chris)
v12:
* Do not fail client add on id wrap. (Maciej)
v13 (Lucas): Rebase.
v14:
* Dropped sysfs bits.
v15:
* Dropped tracking of pid/ and name.
* Dropped RCU freeing of the client object.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson # v11
Reviewed-by: Aravind Iddamsetty # v11
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/i915_driver.c | 6 +++
drivers/gpu/drm/i915/i915_drm_client.c | 68
drivers/gpu/drm/i915/i915_drm_client.h | 50 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_file_private.h | 3 ++
drivers/gpu/drm/i915/i915_gem.c | 21 ++--
7 files changed, 149 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_drm_client.c
create mode 100644 drivers/gpu/drm/i915/i915_drm_client.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c1d5540f6052..6d4c628ae355 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -32,6 +32,7 @@ subdir-ccflags-y += -I$(srctree)/$(src)
# core driver code
i915-y += i915_driver.o \
+ i915_drm_client.o \
i915_config.o \
i915_getparam.o \
i915_ioctl.o \
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 15808ecc421a..b2df273e6d7b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -77,6 +77,7 @@
#include "i915_file_private.h"
#include "i915_debugfs.h"
#include "i915_driver.h"
+#include "i915_drm_client.h"
#include "i915_drv.h"
#include "i915_getparam.h"
#include "i915_ioc32.h"
@@ -355,6 +356,8 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
intel_root_gt_init_early(dev_priv);
+ i915_drm_clients_init(&dev_priv->clients, dev_priv);
+
i915_gem_init_early(dev_priv);
/* This must be called before any calls to HAS_PCH_* */
@@ -375,6 +378,7 @@ static int i915_driver_early_probe(struct drm_i915_private
*dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
intel_gt_driver_late_release_all(dev_priv);
+ i915_drm_clients_fini(&dev_priv->clients);
intel_region_ttm_device_fini(dev_priv);
err_ttm:
vlv_suspend_cleanup(dev_priv);
@@ -394,6 +398,7 @@ static void i915_driver_late_release(struct
drm_i915_private *dev_priv)
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
intel_gt_driver_late_release_all(dev_priv);
+ i915_drm_clients_fini(&dev_priv->clients);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
@@ -1009,6 +1014,7 @@ static void i915_driver_postclose(struct drm_device *dev,
struct drm_file *file)
struct drm_i915_file_private *file_priv = file->driver_priv;
i915_gem_context_close(file);
+ i915_drm_client_put(file_priv->client);
kfree_rcu(file_priv, rcu);
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
new file mode 100644
index ..e61e9ba15256
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include "i915_drm_client.h"
+#include "i915_gem.h"
+#include "i915_utils.h"
+
+void i915_drm_clients_init(struct i915_drm_clients *clients,
+ struct drm_i915_private *i915)
+{
+ clients->i915 = i915;
+ clients->next_id = 0;
+
+ xa_init_flags(&clients->xarray, XA_FLAGS_ALLO
[Intel-gfx] [CI 2/8] drm/i915: Make GEM contexts track DRM clients
From: Tvrtko Ursulin
Make GEM contexts keep a reference to i915_drm_client for the whole of
of their lifetime which will come handy in following patches.
v2: Don't bother supporting selftests contexts from debugfs. (Chris)
v3 (Lucas): Finish constructing ctx before adding it to the list
v4 (Ram): Rebase.
v5: Trivial rebase for proto ctx changes.
v6: Rebase after clients no longer track name and pid.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Chris Wilson # v5
Reviewed-by: Aravind Iddamsetty # v5
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 5394fbed8bf0..6781ee34646c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1257,6 +1257,9 @@ static void i915_gem_context_release_work(struct
work_struct *work)
if (ctx->pxp_wakeref)
intel_runtime_pm_put(&ctx->i915->runtime_pm, ctx->pxp_wakeref);
+ if (ctx->client)
+ i915_drm_client_put(ctx->client);
+
mutex_destroy(&ctx->engines_mutex);
mutex_destroy(&ctx->lut_mutex);
@@ -1663,6 +1666,8 @@ static void gem_context_register(struct i915_gem_context
*ctx,
ctx->file_priv = fpriv;
ctx->pid = get_task_pid(current, PIDTYPE_PID);
+ ctx->client = i915_drm_client_get(fpriv->client);
+
snprintf(ctx->name, sizeof(ctx->name), "%s[%d]",
current->comm, pid_nr(ctx->pid));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 282cdb8a5c5a..93d24f189ba9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -293,6 +293,9 @@ struct i915_gem_context {
/** @link: place with &drm_i915_private.context_list */
struct list_head link;
+ /** @client: struct i915_drm_client */
+ struct i915_drm_client *client;
+
/**
* @ref: reference count
*
--
2.32.0
[Intel-gfx] [CI 3/8] drm/i915: Track runtime spent in closed and unreachable GEM contexts
From: Tvrtko Ursulin
As contexts are abandoned we want to remember how much GPU time they used
(per class) so later we can used it for smarter purposes.
As GEM contexts are closed we want to have the DRM client remember how
much GPU time they used (per class) so later we can used it for smarter
purposes.
v2:
* Size past runtimes array by uabi class, not internal.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty # v1
Reviewed-by: Chris Wilson # v1
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
drivers/gpu/drm/i915/i915_drm_client.h | 9
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 6781ee34646c..50cc87b0cf97 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1031,23 +1031,44 @@ static void free_engines_rcu(struct rcu_head *rcu)
free_engines(engines);
}
+static void accumulate_runtime(struct i915_drm_client *client,
+ struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ if (!client)
+ return;
+
+ /* Transfer accumulated runtime to the parent GEM context. */
+ for_each_gem_engine(ce, engines, it) {
+ unsigned int class = ce->engine->uabi_class;
+
+ GEM_BUG_ON(class >= ARRAY_SIZE(client->past_runtime));
+ atomic64_add(intel_context_get_total_runtime_ns(ce),
+&client->past_runtime[class]);
+ }
+}
+
static int
engines_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
{
struct i915_gem_engines *engines =
container_of(fence, typeof(*engines), fence);
+ struct i915_gem_context *ctx = engines->ctx;
switch (state) {
case FENCE_COMPLETE:
if (!list_empty(&engines->link)) {
- struct i915_gem_context *ctx = engines->ctx;
unsigned long flags;
spin_lock_irqsave(&ctx->stale.lock, flags);
list_del(&engines->link);
spin_unlock_irqrestore(&ctx->stale.lock, flags);
}
- i915_gem_context_put(engines->ctx);
+ accumulate_runtime(ctx->client, engines);
+ i915_gem_context_put(ctx);
+
break;
case FENCE_FREE:
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h
b/drivers/gpu/drm/i915/i915_drm_client.h
index e8986ad51176..cbc3161ab021 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -9,6 +9,10 @@
#include
#include
+#include "gt/intel_engine_types.h"
+
+#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
+
struct drm_i915_private;
struct i915_drm_clients {
@@ -24,6 +28,11 @@ struct i915_drm_client {
unsigned int id;
struct i915_drm_clients *clients;
+
+ /**
+* @past_runtime: Accumulation of pphwsp runtimes from closed contexts.
+*/
+ atomic64_t past_runtime[I915_LAST_UABI_ENGINE_CLASS + 1];
};
void i915_drm_clients_init(struct i915_drm_clients *clients,
--
2.32.0
[Intel-gfx] [CI 4/8] drm/i915: Track all user contexts per client
From: Tvrtko Ursulin
We soon want to start answering questions like how much GPU time is the
context belonging to a client which exited still using.
To enable this we start tracking all context belonging to a client on a
separate list.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 13 +
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 3 +++
drivers/gpu/drm/i915/i915_drm_client.c| 2 ++
drivers/gpu/drm/i915/i915_drm_client.h| 5 +
4 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 50cc87b0cf97..92652528b7f9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1491,6 +1491,8 @@ static void set_closed_name(struct i915_gem_context *ctx)
static void context_close(struct i915_gem_context *ctx)
{
+ struct i915_drm_client *client;
+
/* Flush any concurrent set_engines() */
mutex_lock(&ctx->engines_mutex);
unpin_engines(__context_engines_static(ctx));
@@ -1515,6 +1517,13 @@ static void context_close(struct i915_gem_context *ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
+ client = ctx->client;
+ if (client) {
+ spin_lock(&client->ctx_lock);
+ list_del_rcu(&ctx->client_link);
+ spin_unlock(&client->ctx_lock);
+ }
+
mutex_unlock(&ctx->mutex);
/*
@@ -1696,6 +1705,10 @@ static void gem_context_register(struct i915_gem_context
*ctx,
old = xa_store(&fpriv->context_xa, id, ctx, GFP_KERNEL);
WARN_ON(old);
+ spin_lock(&ctx->client->ctx_lock);
+ list_add_tail_rcu(&ctx->client_link, &ctx->client->ctx_list);
+ spin_unlock(&ctx->client->ctx_lock);
+
spin_lock(&i915->gem.contexts.lock);
list_add_tail(&ctx->link, &i915->gem.contexts.list);
spin_unlock(&i915->gem.contexts.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 93d24f189ba9..5946dcb11cf5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -296,6 +296,9 @@ struct i915_gem_context {
/** @client: struct i915_drm_client */
struct i915_drm_client *client;
+ /** link: &drm_client.context_list */
+ struct list_head client_link;
+
/**
* @ref: reference count
*
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index e61e9ba15256..91a8559bebf7 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -38,6 +38,8 @@ struct i915_drm_client *i915_drm_client_add(struct
i915_drm_clients *clients)
goto err;
kref_init(&client->kref);
+ spin_lock_init(&client->ctx_lock);
+ INIT_LIST_HEAD(&client->ctx_list);
client->clients = clients;
return client;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h
b/drivers/gpu/drm/i915/i915_drm_client.h
index cbc3161ab021..191368386ace 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -7,6 +7,8 @@
#define __I915_DRM_CLIENT_H__
#include
+#include
+#include
#include
#include "gt/intel_engine_types.h"
@@ -27,6 +29,9 @@ struct i915_drm_client {
unsigned int id;
+ spinlock_t ctx_lock; /* For add/remove from ctx_list. */
+ struct list_head ctx_list; /* List of contexts belonging to client. */
+
struct i915_drm_clients *clients;
/**
--
2.32.0
[Intel-gfx] [CI 5/8] drm/i915: Track context current active time
From: Tvrtko Ursulin
Track context active (on hardware) status together with the start
timestamp.
This will be used to provide better granularity of context
runtime reporting in conjunction with already tracked pphwsp accumulated
runtime.
The latter is only updated on context save so does not give us visibility
to any currently executing work.
As part of the patch the existing runtime tracking data is moved under the
new ce->stats member and updated under the seqlock. This provides the
ability to atomically read out accumulated plus active runtime.
v2:
* Rename and make __intel_context_get_active_time unlocked.
v3:
* Use GRAPHICS_VER.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Aravind Iddamsetty # v1
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_context.c | 27 ++-
drivers/gpu/drm/i915/gt/intel_context.h | 15 ---
drivers/gpu/drm/i915/gt/intel_context_types.h | 24 +++--
.../drm/i915/gt/intel_execlists_submission.c | 23
.../gpu/drm/i915/gt/intel_gt_clock_utils.c| 4 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 27 ++-
drivers/gpu/drm/i915/gt/intel_lrc.h | 27 ++-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
10 files changed, 118 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index d87145b8fca0..4070cb5711d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -386,7 +386,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
ce->ring = NULL;
ce->ring_size = SZ_4K;
- ewma_runtime_init(&ce->runtime.avg);
+ ewma_runtime_init(&ce->stats.runtime.avg);
ce->vm = i915_vm_get(engine->gt->vm);
@@ -576,6 +576,31 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
child->parallel.parent = parent;
}
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+{
+ u64 total, active;
+
+ total = ce->stats.runtime.total;
+ if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+ total *= ce->engine->gt->clock_period_ns;
+
+ active = READ_ONCE(ce->stats.active);
+ if (active)
+ active = intel_context_clock() - active;
+
+ return total + active;
+}
+
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+{
+ u64 avg = ewma_runtime_read(&ce->stats.runtime.avg);
+
+ if (ce->ops->flags & COPS_RUNTIME_CYCLES)
+ avg *= ce->engine->gt->clock_period_ns;
+
+ return avg;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_context.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index d8c74bbf9aae..b7d3214d2cdd 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -351,18 +351,13 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
}
-static inline u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
-{
- const u32 period = ce->engine->gt->clock_period_ns;
-
- return READ_ONCE(ce->runtime.total) * period;
-}
+u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
-static inline u64 intel_context_get_avg_runtime_ns(struct intel_context *ce)
+static inline u64 intel_context_clock(void)
{
- const u32 period = ce->engine->gt->clock_period_ns;
-
- return mul_u32_u32(ewma_runtime_read(&ce->runtime.avg), period);
+ /* As we mix CS cycles with CPU clocks, use the raw monotonic clock. */
+ return ktime_get_raw_fast_ns();
}
#endif /* __INTEL_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 30cd81ad8911..09f82545789f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -35,6 +35,9 @@ struct intel_context_ops {
#define COPS_HAS_INFLIGHT_BIT 0
#define COPS_HAS_INFLIGHT BIT(COPS_HAS_INFLIGHT_BIT)
+#define COPS_RUNTIME_CYCLES_BIT 1
+#define COPS_RUNTIME_CYCLES BIT(COPS_RUNTIME_CYCLES_BIT)
+
int (*alloc)(struct intel_context *ce);
void (*ban)(struct intel_context *ce, struct i915_request *rq);
@@ -134,14 +137,19 @@ struct intel_context {
} lrc;
u32 tag; /* cookie passed to HW to track this context on submission */
- /* Time on GPU as tracked by the hw. */
- struct {
- struct ewma_runtime avg;
- u64 total;
- u32 last;
- I915_SEL
[Intel-gfx] [CI 6/8] drm: Document fdinfo format specification
From: Tvrtko Ursulin Proposal to standardise the fdinfo text format as optionally output by DRM drivers. Idea is that a simple but, well defined, spec will enable generic userspace tools to be written while at the same time avoiding a more heavy handed approach of adding a mid-layer to DRM. i915 implements a subset of the spec, everything apart from the memory stats currently, and a matching intel_gpu_top tool exists. Open is to see if AMD can migrate to using the proposed GPU utilisation key-value pairs, or if they are not workable to see whether to go vendor specific, or if a standardised alternative can be found which is workable for both drivers. Same for the memory utilisation key-value pairs proposal. v2: * Update for removal of name and pid. v3: * 'Drm-driver' tag will be obtained from struct drm_driver.name. (Daniel) v4: * Added drm-engine-capacity- tag. Signed-off-by: Tvrtko Ursulin Cc: David M Nieto Cc: Christian König Cc: Daniel Vetter Cc: Daniel Stone Cc: Chris Healy Acked-by: Christian König Reviewed-by: Umesh Nerlige Ramappa --- Documentation/gpu/drm-usage-stats.rst | 106 ++ Documentation/gpu/index.rst | 1 + 2 files changed, 107 insertions(+) create mode 100644 Documentation/gpu/drm-usage-stats.rst diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst new file mode 100644 index ..b8cc28f4da6f --- /dev/null +++ b/Documentation/gpu/drm-usage-stats.rst @@ -0,0 +1,106 @@ +.. _drm-client-usage-stats: + +== +DRM client usage stats +== + +DRM drivers can choose to export partly standardised text output via the +`fops->show_fdinfo()` as part of the driver specific file operations registered +in the `struct drm_driver` object registered with the DRM core. + +One purpose of this output is to enable writing as generic as practicaly +feasible `top(1)` like userspace monitoring tools. + +Given the differences between various DRM drivers the specification of the +output is split between common and driver specific parts. Having said that, +wherever possible effort should still be made to standardise as much as +possible. + +File format specification += + +- File shall contain one key value pair per one line of text. +- Colon character (`:`) must be used to delimit keys and values. +- All keys shall be prefixed with `drm-`. +- Whitespace between the delimiter and first non-whitespace character shall be + ignored when parsing. +- Neither keys or values are allowed to contain whitespace characters. +- Numerical key value pairs can end with optional unit string. +- Data type of the value is fixed as defined in the specification. + +Key types +- + +1. Mandatory, fully standardised. +2. Optional, fully standardised. +3. Driver specific. + +Data types +-- + +- - Unsigned integer without defining the maximum value. +- - String excluding any above defined reserved characters or whitespace. + +Mandatory fully standardised keys +- + +- drm-driver: + +String shall contain the name this driver registered as via the respective +`struct drm_driver` data structure. + +Optional fully standardised keys + + +- drm-pdev: + +For PCI devices this should contain the PCI slot address of the device in +question. + +- drm-client-id: + +Unique value relating to the open DRM file descriptor used to distinguish +duplicated and shared file descriptors. Conceptually the value should map 1:1 +to the in kernel representation of `struct drm_file` instances. + +Uniqueness of the value shall be either globally unique, or unique within the +scope of each device, in which case `drm-pdev` shall be present as well. + +Userspace should make sure to not double account any usage statistics by using +the above described criteria in order to associate data to individual clients. + +- drm-engine-: ns + +GPUs usually contain multiple execution engines. Each shall be given a stable +and unique name (str), with possible values documented in the driver specific +documentation. + +Value shall be in specified time units which the respective GPU engine spent +busy executing workloads belonging to this client. + +Values are not required to be constantly monotonic if it makes the driver +implementation easier, but are required to catch up with the previously reported +larger value within a reasonable period. Upon observing a value lower than what +was previously read, userspace is expected to stay with that larger previous +value until a monotonic update is seen. + +- drm-engine-capacity-: + +Engine identifier string must be the same as the one specified in the +drm-engine- tag and shall contain a greater than zero number in case the +exported engine corresponds to a group of identical hardware engines. + +In the absence of this tag parser shall assume capacity of one. Zero capacity +is not allowed.
[Intel-gfx] [CI 7/8] drm/i915: Count engine instances per uabi class
From: Tvrtko Ursulin
This will be useful to have at hand in a following patch.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index b8c9b6b89003..0f6cd96b459f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -193,7 +193,6 @@ static void add_legacy_ring(struct legacy_ring *ring,
void intel_engines_driver_register(struct drm_i915_private *i915)
{
struct legacy_ring ring = {};
- u8 uabi_instances[5] = {};
struct list_head *it, *next;
struct rb_node **p, *prev;
LIST_HEAD(engines);
@@ -214,8 +213,10 @@ void intel_engines_driver_register(struct drm_i915_private
*i915)
GEM_BUG_ON(engine->class >= ARRAY_SIZE(uabi_classes));
engine->uabi_class = uabi_classes[engine->class];
- GEM_BUG_ON(engine->uabi_class >= ARRAY_SIZE(uabi_instances));
- engine->uabi_instance = uabi_instances[engine->uabi_class]++;
+ GEM_BUG_ON(engine->uabi_class >=
+ ARRAY_SIZE(i915->engine_uabi_class_count));
+ engine->uabi_instance =
+ i915->engine_uabi_class_count[engine->uabi_class]++;
/* Replace the internal name with the final user facing name */
memcpy(old, engine->name, sizeof(engine->name));
@@ -245,8 +246,8 @@ void intel_engines_driver_register(struct drm_i915_private
*i915)
int class, inst;
int errors = 0;
- for (class = 0; class < ARRAY_SIZE(uabi_instances); class++) {
- for (inst = 0; inst < uabi_instances[class]; inst++) {
+ for (class = 0; class <
ARRAY_SIZE(i915->engine_uabi_class_count); class++) {
+ for (inst = 0; inst <
i915->engine_uabi_class_count[class]; inst++) {
engine = intel_engine_lookup_user(i915,
class, inst);
if (!engine) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bbda3e01d03d..7f33cf2afb9e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,6 +500,7 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
+ unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
struct resource mch_res;
--
2.32.0
[Intel-gfx] [CI 8/8] drm/i915: Expose client engine utilisation via fdinfo
From: Tvrtko Ursulin
Similar to AMD commit
874442541133 ("drm/amdgpu: Add show_fdinfo() interface"), using the
infrastructure added in previous patches, we add basic client info
and GPU engine utilisation for i915.
Example of the output:
pos:0
flags: 012
mnt_id: 21
drm-driver: i915
drm-pdev: :00:02.0
drm-client-id: 7
drm-engine-render: 9288864723 ns
drm-engine-copy:2035071108 ns
drm-engine-video: 0 ns
drm-engine-video-enhance: 0 ns
v2:
* Update for removal of name and pid.
v3:
* Use drm_driver.name.
v4:
* Added drm-engine-capacity- tag.
* Fix typo. (Umesh)
v5:
* Don't output engine data before Gen8.
Signed-off-by: Tvrtko Ursulin
Cc: David M Nieto
Cc: Christian König
Cc: Daniel Vetter
Cc: Chris Healy
Acked-by: Christian König
Reviewed-by: Umesh Nerlige Ramappa
---
Documentation/gpu/drm-usage-stats.rst | 6 ++
Documentation/gpu/i915.rst | 28 +
drivers/gpu/drm/i915/i915_driver.c | 3 +
drivers/gpu/drm/i915/i915_drm_client.c | 84 ++
drivers/gpu/drm/i915/i915_drm_client.h | 4 ++
5 files changed, 125 insertions(+)
diff --git a/Documentation/gpu/drm-usage-stats.rst
b/Documentation/gpu/drm-usage-stats.rst
index b8cc28f4da6f..6c9f166a8d6f 100644
--- a/Documentation/gpu/drm-usage-stats.rst
+++ b/Documentation/gpu/drm-usage-stats.rst
@@ -104,3 +104,9 @@ object belong to this client, in the respective memory
region.
Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
indicating kibi- or mebi-bytes.
+
+===
+Driver specific implementations
+===
+
+:ref:`i915-usage-stats`
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 0f08693d05cd..54060cd6c419 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -697,3 +697,31 @@ The style guide for ``i915_reg.h``.
.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
:doc: The i915 register macro definition style guide
+
+.. _i915-usage-stats:
+
+i915 DRM client usage stats implementation
+==
+
+The drm/i915 driver implements the DRM client usage stats specification as
+documented in :ref:`drm-client-usage-stats`.
+
+Example of the output showing the implemented key value pairs and entirety of
+the currently possible format options:
+
+::
+
+ pos:0
+ flags: 012
+ mnt_id: 21
+ drm-driver: i915
+ drm-pdev: :00:02.0
+ drm-client-id: 7
+ drm-engine-render: 9288864723 ns
+ drm-engine-copy:2035071108 ns
+ drm-engine-video: 0 ns
+ drm-engine-capacity-video: 2
+ drm-engine-video-enhance: 0 ns
+
+Possible `drm-engine-` key names are: `render`, `copy`, `video` and
+`video-enhance`.
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index b2df273e6d7b..3ffb617d75c9 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1745,6 +1745,9 @@ static const struct file_operations i915_driver_fops = {
.read = drm_read,
.compat_ioctl = i915_ioc32_compat_ioctl,
.llseek = noop_llseek,
+#ifdef CONFIG_PROC_FS
+ .show_fdinfo = i915_drm_client_fdinfo,
+#endif
};
static int
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c
b/drivers/gpu/drm/i915/i915_drm_client.c
index 91a8559bebf7..e539f6b23060 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -7,7 +7,13 @@
#include
#include
+#include
+
+#include
+
+#include "gem/i915_gem_context.h"
#include "i915_drm_client.h"
+#include "i915_file_private.h"
#include "i915_gem.h"
#include "i915_utils.h"
@@ -68,3 +74,81 @@ void i915_drm_clients_fini(struct i915_drm_clients *clients)
GEM_BUG_ON(!xa_empty(&clients->xarray));
xa_destroy(&clients->xarray);
}
+
+#ifdef CONFIG_PROC_FS
+static const char * const uabi_class_names[] = {
+ [I915_ENGINE_CLASS_RENDER] = "render",
+ [I915_ENGINE_CLASS_COPY] = "copy",
+ [I915_ENGINE_CLASS_VIDEO] = "video",
+ [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+};
+
+static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ u64 total = 0;
+
+ for_each_gem_engine(ce, rcu_dereference(ctx->engines), it) {
+ if (ce->engine->uabi_class != class)
+ continue;
+
+ total += intel_context_get_total_runtime_ns(ce);
+ }
+
+ return total;
+}
+
+static void
+show_client_class(struct seq_file *m,
+ struct i915_drm_client *client,
+ unsigned int class)
+{
+ const struct list_head *list = &client->ctx_list;
+ u64 total = atomic64_read(&client->past_runtime[class]);
+ const unsigned int capacity =
+ client->clients->i915->engine_uabi_class_c
Re: [Intel-gfx] [PATCH v7 7/9] drm/ttm: Add a parameter to add extra pages into ttm_tt
Christian, Joonas and vivi
Once the premerge results are greeen, if this patch can be merged into
drm-intel-gt-next along with other patches could you please ack the
request to merge into drm-intel-gt-next?
Thanks
Ram
On 2022-04-01 at 18:07:49 +0530, Ramalingam C wrote:
> Add a parameter called "extra_pages" for ttm_tt_init, to indicate that
> driver needs extra pages in ttm_tt.
>
> v2:
> Used imperative wording [Thomas and Christian]
>
> Signed-off-by: Ramalingam C
> cc: Christian Koenig
> cc: Hellstrom Thomas
> Reviewed-by: Thomas Hellstrom
> Reviewed-by: Christian Konig
> Reviewed-by: Nirmoy Das
> ---
> drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 2 +-
> drivers/gpu/drm/qxl/qxl_ttm.c | 2 +-
> drivers/gpu/drm/ttm/ttm_agp_backend.c | 2 +-
> drivers/gpu/drm/ttm/ttm_tt.c | 12 +++-
> drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +-
> include/drm/ttm/ttm_tt.h | 4 +++-
> 7 files changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
> b/drivers/gpu/drm/drm_gem_vram_helper.c
> index dc7f938bfff2..123045b58fec 100644
> --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> @@ -867,7 +867,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct
> ttm_buffer_object *bo,
> if (!tt)
> return NULL;
>
> - ret = ttm_tt_init(tt, bo, page_flags, ttm_cached);
> + ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
> if (ret < 0)
> goto err_ttm_tt_init;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index c40aca99442f..a878910a563c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -293,7 +293,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct
> ttm_buffer_object *bo,
> i915_tt->is_shmem = true;
> }
>
> - ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching);
> + ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0);
> if (ret)
> goto err_free;
>
> diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> index 95df5750f47f..9ba871bd19b1 100644
> --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> @@ -113,7 +113,7 @@ static struct ttm_tt *qxl_ttm_tt_create(struct
> ttm_buffer_object *bo,
> ttm = kzalloc(sizeof(struct ttm_tt), GFP_KERNEL);
> if (ttm == NULL)
> return NULL;
> - if (ttm_tt_init(ttm, bo, page_flags, ttm_cached)) {
> + if (ttm_tt_init(ttm, bo, page_flags, ttm_cached, 0)) {
> kfree(ttm);
> return NULL;
> }
> diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
> b/drivers/gpu/drm/ttm/ttm_agp_backend.c
> index 6ddc16f0fe2b..d27691f2e451 100644
> --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
> +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
> @@ -134,7 +134,7 @@ struct ttm_tt *ttm_agp_tt_create(struct ttm_buffer_object
> *bo,
> agp_be->mem = NULL;
> agp_be->bridge = bridge;
>
> - if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined)) {
> + if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined, 0)) {
> kfree(agp_be);
> return NULL;
> }
> diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> index d234aab800a0..1a66d9fc589a 100644
> --- a/drivers/gpu/drm/ttm/ttm_tt.c
> +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> @@ -134,9 +134,10 @@ void ttm_tt_destroy(struct ttm_device *bdev, struct
> ttm_tt *ttm)
> static void ttm_tt_init_fields(struct ttm_tt *ttm,
> struct ttm_buffer_object *bo,
> uint32_t page_flags,
> -enum ttm_caching caching)
> +enum ttm_caching caching,
> +unsigned long extra_pages)
> {
> - ttm->num_pages = PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT;
> + ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
> extra_pages;
> ttm->caching = ttm_cached;
> ttm->page_flags = page_flags;
> ttm->dma_address = NULL;
> @@ -146,9 +147,10 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
> }
>
> int ttm_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo,
> - uint32_t page_flags, enum ttm_caching caching)
> + uint32_t page_flags, enum ttm_caching caching,
> + unsigned long extra_pages)
> {
> - ttm_tt_init_fields(ttm, bo, page_flags, caching);
> + ttm_tt_init_fields(ttm, bo, page_flags, caching, extra_pages);
>
> if (ttm_tt_alloc_page_directory(ttm)) {
> pr_err("Failed allocating page table\n");
> @@ -180,7 +182,7 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct
> ttm_buffer_object *bo,
> {
> int ret;
>
> - ttm_t
Re: [Intel-gfx] [PATCH 1/3] drm/i915/dmc: abstract GPU error state dump
On Fri, Apr 01, 2022 at 10:43:19AM +0300, Jani Nikula wrote:
On Wed, 30 Mar 2022, Jani Nikula wrote:
Only intel_dmc.c should be accessing dmc details directly.
Need to add an i915_error_printf() stub for
CONFIG_DRM_I915_CAPTURE_ERROR=n.
v2: Add the stub (kernel test robot )
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi # v1
Just as I pushed to din, I realized I jumped the gun a bit, I meant to
wait for rb confirmation on v2. The diff isn't big, but generally I
prefer erring on the side of caution. Sorry.
v2 looks good to me. I missed this update when you sent.
thanks
Lucas De Marchi
And thanks for review on v1. :)
BR,
Jani.
---
drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++
drivers/gpu/drm/i915/display/intel_dmc.h | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c| 10 +-
drivers/gpu/drm/i915/i915_gpu_error.h| 6 ++
4 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5de13f978e57..f0eb3de8de60 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -811,6 +811,21 @@ void intel_dmc_ucode_fini(struct drm_i915_private
*dev_priv)
kfree(dev_priv->dmc.dmc_info[id].payload);
}
+void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
+struct drm_i915_private *i915)
+{
+ struct intel_dmc *dmc = &i915->dmc;
+
+ if (!HAS_DMC(i915))
+ return;
+
+ i915_error_printf(m, "DMC loaded: %s\n",
+ str_yes_no(intel_dmc_has_payload(i915)));
+ i915_error_printf(m, "DMC fw version: %d.%d\n",
+ DMC_VERSION_MAJOR(dmc->version),
+ DMC_VERSION_MINOR(dmc->version));
+}
+
static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
{
struct drm_i915_private *i915 = m->private;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
b/drivers/gpu/drm/i915/display/intel_dmc.h
index b9f608057700..dd8880d2cbed 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -10,6 +10,7 @@
#include "intel_wakeref.h"
#include
+struct drm_i915_error_state_buf;
struct drm_i915_private;
#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
@@ -55,6 +56,8 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
void intel_dmc_ucode_resume(struct drm_i915_private *i915);
bool intel_dmc_has_payload(struct drm_i915_private *i915);
void intel_dmc_debugfs_register(struct drm_i915_private *i915);
+void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
+struct drm_i915_private *i915);
void assert_dmc_loaded(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 795f91a88d1d..25f4e178b410 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -848,15 +848,7 @@ static void __err_print_to_sgl(struct
drm_i915_error_state_buf *m,
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
- if (HAS_DMC(m->i915)) {
- struct intel_dmc *dmc = &m->i915->dmc;
-
- err_printf(m, "DMC loaded: %s\n",
- str_yes_no(intel_dmc_has_payload(m->i915) != 0));
- err_printf(m, "DMC fw version: %d.%d\n",
- DMC_VERSION_MAJOR(dmc->version),
- DMC_VERSION_MINOR(dmc->version));
- }
+ intel_dmc_print_error_state(m, m->i915);
err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 09159ff01411..7977a01a708f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -298,6 +298,12 @@ void i915_disable_error_state(struct drm_i915_private
*i915, int err);
#else
+__printf(2, 3)
+static inline void
+i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
+{
+}
+
static inline void
i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask,
u32 dump_flags)
{
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11407 -> Patchwork_22688
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/index.html
Participating hosts (48 -> 47)
--
Additional (1): fi-pnv-d510
Missing(2): fi-bsw-cyan fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22688 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-adl-ddr5:NOTRUN -> [SKIP][1] ([i915#2575]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-adl-ddr5/igt@amdgpu/amd_ba...@cs-sdma.html
* igt@core_hotunplug@unbind-rebind:
- fi-hsw-g3258: [PASS][2] -> [INCOMPLETE][3] ([i915#5441])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-hsw-g3258/igt@core_hotunp...@unbind-rebind.html
- fi-glk-dsi: [PASS][4] -> [INCOMPLETE][5] ([i915#5441])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-glk-dsi/igt@core_hotunp...@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@gem_render_linear_blits@basic:
- fi-pnv-d510:NOTRUN -> [INCOMPLETE][7] ([i915#5441])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@gem_render_linear_bl...@basic.html
* igt@gem_tiled_blits@basic:
- fi-cfl-8109u: [PASS][8] -> [INCOMPLETE][9] ([i915#5441])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-cfl-8109u/igt@gem_tiled_bl...@basic.html
- fi-kbl-7567u: [PASS][10] -> [INCOMPLETE][11] ([i915#5441])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-kbl-7567u/igt@gem_tiled_bl...@basic.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: NOTRUN -> ([INCOMPLETE][12], [INCOMPLETE][13])
([i915#4418])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-bwr-2160:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#5341])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-bwr-2160/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-bwr-2160:NOTRUN -> [SKIP][15] ([fdo#109271]) +45 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-bwr-2160/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][16] ([i915#2403] / [i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-pnv-d510/igt@run...@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][17] ([i915#4312] / [k.org#202321])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-glk-dsi/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][18] ([i915#4312])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-adl-ddr5:[INCOMPLETE][19] ([i915#5441]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/fi-adl-ddr5/igt@core_hotunp...@unbind-rebind.html
- bat-dg1-6: [INCOMPLETE][21] ([i915#5441]) -> ([PASS][22],
[PASS][23])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/bat-dg1-6/igt@core_hotunp...@unbind-rebind.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/bat-dg1-6/igt@core_hotunp...@unbind-rebind.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/bat-dg1-6/igt@core_hotunp...@unbind-rebind.html
- {bat-hsw-1}:[INCOMPLETE][24] ([i915#5441]) -> ([PASS][25],
[PASS][26])
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI
Re: [Intel-gfx] [PATCH v2 11/11] drm/i915: Allow static DRRS on LVDS
On Thu, Mar 31, 2022 at 05:05:31PM +0300, Ville Syrjälä wrote: > On Thu, Mar 31, 2022 at 04:59:11PM +0300, Jani Nikula wrote: > > On Thu, 31 Mar 2022, Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > > > Nothing special about static DRRS on LVDS, it's just your > > > bog standard modeset. Let's allow it. > > > > > > Signed-off-by: Ville Syrjälä > > > --- > > > drivers/gpu/drm/i915/display/intel_lvds.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c > > > b/drivers/gpu/drm/i915/display/intel_lvds.c > > > index 73129d21f5e5..e8478161f8b9 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_lvds.c > > > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c > > > @@ -968,7 +968,8 @@ void intel_lvds_init(struct drm_i915_private > > > *dev_priv) > > > intel_connector->edid = edid; > > > > > > /* Try EDID first */ > > > - intel_panel_add_edid_fixed_modes(intel_connector, false); > > > + intel_panel_add_edid_fixed_modes(intel_connector, > > > + dev_priv->vbt.drrs_type != > > > DRRS_TYPE_NONE); > > > > I guess the final question on this, and the previous patch for that > > matter, is why would the VBT block your regular modeset between two > > different refresh rates? > > > > It does sound like the VBT setting is more about OEM decided policy than > > anything else. > > Or just lack of validation. After staring at a bunch of VBTs from these laptops with high refresh rate panels it seems some of them do not declare DRRS support at all. So it looks like the other thing we need to consider here is VRR support. There's also a newish field in VBT for VRR which seems like something we need to start looking at (currently we only look at DPCD+EDID for that). And the even bigger problem is that several of the VBTs have panel_type=0xff, so looks like we really need to make that PNPID matching stuff happen :/ Filed a bug to track that one separately https://gitlab.freedesktop.org/drm/intel/-/issues/5545 -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH i-g-t 1/3] lib: Helper library for parsing i915 fdinfo output
lgtm, thanks for clarifications on the other patch.
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Fri, Apr 01, 2022 at 03:11:53PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Tests and intel_gpu_top will share common code for parsing this file.
v2:
* Fix key-value parsing if valid key line ends with ':'.
* Return number of drm keys found.
* Add DRM_CLIENT_FDINFO_MAX_ENGINES. (Umesh)
* Always zero terminate read buffer. (Umesh)
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 188 +++
lib/igt_drm_fdinfo.h | 69
lib/meson.build | 7 ++
3 files changed, 264 insertions(+)
create mode 100644 lib/igt_drm_fdinfo.c
create mode 100644 lib/igt_drm_fdinfo.h
diff --git a/lib/igt_drm_fdinfo.c b/lib/igt_drm_fdinfo.c
new file mode 100644
index ..b422f67a4ace
--- /dev/null
+++ b/lib/igt_drm_fdinfo.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "drmtest.h"
+
+#include "igt_drm_fdinfo.h"
+
+static size_t read_fdinfo(char *buf, const size_t sz, int at, const char *name)
+{
+ size_t count;
+ int fd;
+
+ fd = openat(at, name, O_RDONLY);
+ if (fd < 0)
+ return 0;
+
+ buf[sz - 1] = 0;
+ count = read(fd, buf, sz);
+ buf[sz - 1] = 0;
+ close(fd);
+
+ return count;
+}
+
+static int parse_engine(char *line, struct drm_client_fdinfo *info,
+ size_t prefix_len, uint64_t *val)
+{
+ static const char *e2class[] = {
+ "render",
+ "copy",
+ "video",
+ "video-enhance",
+ };
+ ssize_t name_len;
+ char *name, *p;
+ int found = -1;
+ unsigned int i;
+
+ p = index(line, ':');
+ if (!p || p == line)
+ return -1;
+
+ name_len = p - line - prefix_len;
+ if (name_len < 1)
+ return -1;
+
+ name = line + prefix_len;
+
+ for (i = 0; i < ARRAY_SIZE(e2class); i++) {
+ if (!strncmp(name, e2class[i], name_len)) {
+ found = i;
+ break;
+ }
+ }
+
+ if (found >= 0) {
+ while (*++p && isspace(*p));
+ *val = strtoull(p, NULL, 10);
+ }
+
+ return found;
+}
+
+static const char *find_kv(const char *buf, const char *key, size_t keylen)
+{
+ const char *p = buf;
+
+ if (strncmp(buf, key, keylen))
+ return NULL;
+
+ p = index(buf, ':');
+ if (!p || p == buf)
+ return NULL;
+ if ((p - buf) != keylen)
+ return NULL;
+
+ p++;
+ while (*p && isspace(*p))
+ p++;
+
+ return *p ? p : NULL;
+}
+
+unsigned int
+__igt_parse_drm_fdinfo(int dir, const char *fd, struct drm_client_fdinfo *info)
+{
+ char buf[4096], *_buf = buf;
+ char *l, *ctx = NULL;
+ unsigned int good = 0, num_capacity = 0;
+ size_t count;
+
+ count = read_fdinfo(buf, sizeof(buf), dir, fd);
+ if (!count)
+ return 0;
+
+ while ((l = strtok_r(_buf, "\n", &ctx))) {
+ uint64_t val = 0;
+ const char *v;
+ int idx;
+
+ _buf = NULL;
+
+ if ((v = find_kv(l, "drm-driver", strlen("drm-driver" {
+ strncpy(info->driver, v, sizeof(info->driver) - 1);
+ good++;
+ } else if ((v = find_kv(l, "drm-pdev", strlen("drm-pdev" {
+ strncpy(info->pdev, v, sizeof(info->pdev) - 1);
+ } else if ((v = find_kv(l, "drm-client-id",
+strlen("drm-client-id" {
+
Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime status
> -Original Message-
> From: Jani Nikula
> Sent: Friday, April 1, 2022 7:40 PM
> To: Gupta, Anshuman ; Dixit, Ashutosh
>
> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> ;
> Vivi, Rodrigo
> Subject: RE: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children runtime
> status
>
> On Fri, 01 Apr 2022, "Gupta, Anshuman" wrote:
> >> -Original Message-
> >> From: Jani Nikula
> >> Sent: Friday, April 1, 2022 6:26 PM
> >> To: Gupta, Anshuman ; Dixit, Ashutosh
> >>
> >> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> >> ; Vivi, Rodrigo
> >> Subject: RE: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915 children
> >> runtime status
> >>
> >> On Fri, 01 Apr 2022, "Gupta, Anshuman"
> wrote:
> >> >> -Original Message-
> >> >> From: Jani Nikula
> >> >> Sent: Friday, April 1, 2022 5:31 PM
> >> >> To: Dixit, Ashutosh ; Gupta, Anshuman
> >> >>
> >> >> Cc: intel-gfx@lists.freedesktop.org; Wilson, Chris P
> >> >> ; Vivi, Rodrigo
> >> >> Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Dump i915
> >> >> children runtime status
> >> >>
> >> >> On Tue, 29 Mar 2022, "Dixit, Ashutosh"
> wrote:
> >> >> > On Mon, 28 Mar 2022 03:22:27 -0700, Anshuman Gupta wrote:
> >> >> >>
> >> >> >> +#ifdef CONFIG_PM
> >> >> >> +static int i915_runtime_dump_child_status(struct device *dev,
> >> >> >> +void
> >> >> >> +*data) {
> >> >> >> +struct seq_file *m = data;
> >> >> >> +const char *rpm_status;
> >> >> >> +
> >> >> >> +/* Early return if runtime_pm is disabled */
> >> >> >> +if (dev->power.disable_depth)
> >> >> >> +return 0;
> >> >> >> +
> >> >> >> +switch (dev->power.runtime_status) {
> >> >> >> +case RPM_SUSPENDED:
> >> >> >> +rpm_status = "suspended";
> >> >> >> +break;
> >> >> >> +case RPM_SUSPENDING:
> >> >> >> +rpm_status = "suspending";
> >> >> >> +break;
> >> >> >> +case RPM_RESUMING:
> >> >> >> +rpm_status = "resuming";
> >> >> >> +break;
> >> >> >> +case RPM_ACTIVE:
> >> >> >> +rpm_status = "active";
> >> >> >> +break;
> >> >> >> +default:
> >> >> >> +rpm_status = "unknown";
> >> >> >> +}
> >> >> >> +
> >> >> >> +seq_printf(m, "\t%s %s: Runtime status: %s\n",
> dev_driver_string(dev),
> >> >> >> + dev_name(dev), rpm_status);
> >> >> >> +
> >> >> >> +return 0;
> >> >> >> +}
> >> >> >> +#endif
> >> >> >
> >> >> > Maybe a nit, but perhaps defining a const array is better than
> >> >> > having a switch statement? Similar to what is done in
> >> >> > rtpm_status_str(). The function itself is very similar to
> >> >> > rtpm_status_str() so can probably benefit from that similarity.
> >> >> > Can perhaps even be nearly identical to
> >> >> > rtpm_status_str() (since that is static in the genpd (generic
> >> >> > power
> >> >> > domain) code).
> >> >> >
> >> >> > See also 2bd5306a8764 ("PM / Domains: add debugfs listing of
> >> >> > struct generic_pm_domain-s"), though I am not sure if genpd's
> >> >> > are applicable in our case and certainly look way out of scope for
> >> >> > now.
> Thanks.
> >> >>
> >> >> See also /sys/devices/i915/power/runtime_status and
> >> >> /sys/devices/i915/power/runtime_active_kids.
> >> >>
> >> >> Kinda feels like the info should be made available there?
> >> > runtime_active_kids we are already printing by dev_priv->drm.dev-
> >> >power.child_count.
> >> > About runtime_status , we already prints usage count and pci device
> >> >power
> >> state, IMO that is sufficient for debug ?
> >> > If it is really needed , I will add dev->power.runtime_status in next
> >> > revision.
> >>
> >> My point is, the patch at hand adds runtime pm status printing that
> >> isn't specific to drm or i915 into i915 debugfs. Why?
> >>
> >> What is the reason we should take on the burden of maintaining this
> >> while the right place for it might be in runtime pm code, benefiting
> >> other drivers in addition to ours?
> > Benefit is there to debug CI runtime suspend failures , we need to know the
> culprit child blocking i915 runtime PM.
> > runtime_active_kids just revels the count , it doesn't reveal the culprit
> > children.
>
> I understand. But how is that problem or the information specific to i915? Why
> should this be added to i915 instead of runtime pm infra?
> Surely this is not even a new problem; how do others currently figure this
> information out?
>
> So I'm not going to block this if you all think this is a good idea. But the
> point is,
> the first solution should not be to add some i915 specific stuff when a more
> generic solution might exist or be preferred.
Hi Rafael,
Could you please provide your input, about generic interface to dump the
active children of a device.
Thanks,
Anshuman Gupta.
>
>
> BR,
> Jani.
>
>
>
>
> > Thanks,
> > Anshuman.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> > Thanks,
> >> > Anshuman Gupta.
> >> >
> >> >
> >> >
> >> >
> >> >>
> >> >>
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per client GPU utilisation (rev4)
== Series Details == Series: Per client GPU utilisation (rev4) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ dim checkpatch origin/drm-tip 037908479101 drm/i915: Explicitly track DRM clients -:130: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #130: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 234 lines checked 8f73b6a749d5 drm/i915: Make GEM contexts track DRM clients 481b0788b111 drm/i915: Track runtime spent in closed and unreachable GEM contexts f5a45bb5ac9c drm/i915: Track all user contexts per client 07ad43cd0f97 drm/i915: Track context current active time -:140: WARNING:LINE_SPACING: Missing a blank line after declarations #140: FILE: drivers/gpu/drm/i915/gt/intel_context_types.h:149: + u32 last; + I915_SELFTEST_DECLARE(u32 num_underflow); total: 0 errors, 1 warnings, 0 checks, 308 lines checked 7d0f31c44ba2 drm: Document fdinfo format specification -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:50: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #50: FILE: Documentation/gpu/drm-usage-stats.rst:1: +.. _drm-client-usage-stats: total: 0 errors, 2 warnings, 0 checks, 113 lines checked 7703ec507d49 drm/i915: Count engine instances per uabi class 3deb854ecac2 drm/i915: Expose client engine utilisation via fdinfo
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Evict and restore of compressed object (rev7)
== Series Details ==
Series: drm/i915/ttm: Evict and restore of compressed object (rev7)
URL : https://patchwork.freedesktop.org/series/101106/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11438_full -> Patchwork_22758_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22758_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22758_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22758_full:
### IGT changes ###
Possible regressions
* {igt@gem_lmem_swapping@parallel-random-verify-ccs} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-tglb7/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-iclb: NOTRUN -> [SKIP][2] +3 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-iclb6/igt@gem_lmem_swapp...@verify-random-ccs.html
New tests
-
New tests have been introduced between CI_DRM_11438_full and
Patchwork_22758_full:
### New IGT tests (2) ###
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_22758_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [FAIL][18],
[FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26], [PASS][27]) ([i915#5032]) -> ([PASS][28], [PASS][29],
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35],
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47],
[PASS][48], [PASS][49], [PASS][50], [PASS][51])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl8/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl8/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl1/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl1/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl1/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl10/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl10/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-skl9/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-skl9/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-skl9/boot.html
[31]:
http
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per client GPU utilisation (rev4)
== Series Details == Series: Per client GPU utilisation (rev4) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Per client GPU utilisation (rev4)
== Series Details == Series: Per client GPU utilisation (rev4) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:417: warning: Function parameter or member 'client_link' not described in 'i915_gem_context'
Re: [Intel-gfx] [PATCH v2 00/12] drm/edid: cleanup and refactoring around validity checks
On Fri, 01 Apr 2022, Ville Syrjälä wrote: > On Fri, Apr 01, 2022 at 11:55:21AM +0300, Jani Nikula wrote: >> On Thu, 31 Mar 2022, Jani Nikula wrote: >> > v2 of https://patchwork.freedesktop.org/series/101931/ >> > >> > Rebased, review comments addressed. >> >> Ville, care to double check patches 1 & 7 please? > > Looks fine by me > Reviewed-by: Ville Syrjälä Thanks, pushed the lot to drm-misc-next. BR, Jani. > >> >> Thanks, >> Jani. >> >> >> > >> > BR, >> > Jani. >> > >> > >> > >> > Jani Nikula (12): >> > drm/edid: use struct edid * in drm_do_get_edid() >> > drm/edid: clean up EDID block checksum functions >> > drm/edid: add edid_block_tag() helper to get the EDID extension tag >> > drm/edid: make drm_edid_header_is_valid() accept void pointer >> > drm/edid: clean up edid_is_zero() >> > drm/edid: split out edid_header_fix() >> > drm/edid: split drm_edid_block_valid() to check and act parts >> > drm/edid: use a better variable name for EDID block read retries >> > drm/edid: simplify block check when filtering invalid blocks >> > drm/edid: split out invalid block filtering to a separate function >> > drm/edid: track invalid blocks in drm_do_get_edid() >> > drm/edid: reduce magic when updating the EDID block checksum >> > >> > drivers/gpu/drm/drm_edid.c | 295 + >> > include/drm/drm_edid.h | 2 +- >> > 2 files changed, 173 insertions(+), 124 deletions(-) >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.BAT: failure for Per client GPU utilisation (rev4)
== Series Details ==
Series: Per client GPU utilisation (rev4)
URL : https://patchwork.freedesktop.org/series/100573/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11439 -> Patchwork_22760
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22760 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22760, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/index.html
Participating hosts (43 -> 41)
--
Additional (1): fi-pnv-d510
Missing(3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22760:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@guc:
- bat-dg1-6: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11439/bat-dg1-6/igt@i915_selftest@l...@guc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/bat-dg1-6/igt@i915_selftest@l...@guc.html
Known issues
Here are the changes found in Patchwork_22760 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11439/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#5341])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +57 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/fi-pnv-d510/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][7] ([i915#3576]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11439/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [DMESG-WARN][9] ([i915#402]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11439/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-
* IGT: IGT_6405 -> IGTPW_6859
* Linux: CI_DRM_11439 -> Patchwork_22760
CI-20190529: 20190529
CI_DRM_11439: 8ee0d50f44b1f5e36ee255bbff836d7c1f338ee2 @
git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6859: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6859/index.html
IGT_6405: 50f7bc405cc1411f57855ed23322c6c4d2510b58 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22760: 3deb854ecac2ffa5e2d99fabf5faa01215f1ef18 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3deb854ecac2 drm/i915: Expose client engine utilisation via fdinfo
7703ec507d49 drm/i915: Count engine instances per uabi class
7d0f31c44ba2 drm: Document fdinfo format specification
07ad43cd0f97 drm/i915: Track context current active time
f5a45bb5ac9c drm/i915: Track all user contexts per client
481b0788b111 drm/i915: Track runtime spent in closed and unreachable GEM
contexts
8f73b6a749d5 drm/i915: Make GEM contexts track DRM clients
037908479101 drm/i915: Explicitly track DRM clients
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22760/index.html
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11407_full -> Patchwork_22688_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22688_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22688_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 13)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22688_full:
### IGT changes ###
Possible regressions
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-snb7/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-snb4/igt@kms_vbl...@pipe-b-ts-continuation-dpms-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-uc-ro-default:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-rkl-5/igt@gem_exec_fl...@basic-uc-ro-default.html
Known issues
Here are the changes found in Patchwork_22688_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-iclb: NOTRUN -> [INCOMPLETE][4] ([i915#5441]) +3 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb8/igt@api_intel...@blit-reloc-purge-cache.html
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][5] ([i915#658]) +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb5/igt@feature_discov...@psr2.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#4525]) +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2846])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) +2 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-skl6/igt@gem_lmem_swapp...@heavy-multi.html
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4613]) +1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb7/igt@gem_lmem_swapp...@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk9/igt@gem_lmem_swapp...@parallel-random.html
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1
similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_lmem_swapp...@parallel-random.html
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl3/igt@gem_lmem_swapp...@parallel-random.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-kbl: NOTRUN -> [DMESG-FAIL][18] ([i915#5441])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl7
[Intel-gfx] [drm-tip:drm-tip 4/8] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:33: error: no member named 'tbo' in 'struct ttm_range_mgr_node'
tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
head: e797b8d09704b91463456234efdf04dc8f8c385d
commit: edc1a46d62b7a03d53067f598db831092f9e1b05 [4/8] Merge remote-tracking
branch 'drm-misc/drm-misc-next' into drm-tip
config: arm-randconfig-r033-20220401
(https://download.01.org/0day-ci/archive/20220402/202204020126.nuhkg49n-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
cc2e2b80a1f36a28fa7c96c38c2674b10868f09f)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm cross compiling tool for clang build
# apt-get install binutils-arm-linux-gnueabi
git remote add drm-tip git://anongit.freedesktop.org/drm/drm-tip
git fetch --no-tags drm-tip drm-tip
git checkout edc1a46d62b7a03d53067f598db831092f9e1b05
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=arm SHELL=/bin/bash drivers/gpu/drm/amd/amdgpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:200:33: error: no member named
>> 'tbo' in 'struct ttm_range_mgr_node'
amdgpu_ttm_recover_gart(node->tbo);
^
1 error generated.
vim +200 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
bb990bb09235a3 Christian König 2016-09-09 182
a614b336f1c16d Christian König 2021-02-11 183 /**
a614b336f1c16d Christian König 2021-02-11 184 * amdgpu_gtt_mgr_recover -
re-init gart
a614b336f1c16d Christian König 2021-02-11 185 *
1dd8b1b987fad9 Nirmoy Das 2022-01-07 186 * @mgr: amdgpu_gtt_mgr pointer
a614b336f1c16d Christian König 2021-02-11 187 *
a614b336f1c16d Christian König 2021-02-11 188 * Re-init the gart for each
known BO in the GTT.
a614b336f1c16d Christian König 2021-02-11 189 */
1b08dfb889b2c5 Christian König 2022-01-18 190 void
amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
c1c7ce8f5687bb Christian König 2017-10-16 191 {
77ef271faee9c3 Christian König 2021-07-16 192 struct
ttm_range_mgr_node *node;
c1c7ce8f5687bb Christian König 2017-10-16 193 struct drm_mm_node
*mm_node;
1dd8b1b987fad9 Nirmoy Das 2022-01-07 194 struct amdgpu_device
*adev;
c1c7ce8f5687bb Christian König 2017-10-16 195
19a1d9350be632 Nirmoy Das 2021-05-28 196 adev =
container_of(mgr, typeof(*adev), mman.gtt_mgr);
c1c7ce8f5687bb Christian König 2017-10-16 197 spin_lock(&mgr->lock);
c1c7ce8f5687bb Christian König 2017-10-16 198
drm_mm_for_each_node(mm_node, &mgr->mm) {
77ef271faee9c3 Christian König 2021-07-16 199 node =
container_of(mm_node, typeof(*node), mm_nodes[0]);
1b08dfb889b2c5 Christian König 2022-01-18 @200
amdgpu_ttm_recover_gart(node->tbo);
c1c7ce8f5687bb Christian König 2017-10-16 201 }
c1c7ce8f5687bb Christian König 2017-10-16 202 spin_unlock(&mgr->lock);
c1c7ce8f5687bb Christian König 2017-10-16 203
19a1d9350be632 Nirmoy Das 2021-05-28 204
amdgpu_gart_invalidate_tlb(adev);
c1c7ce8f5687bb Christian König 2017-10-16 205 }
c1c7ce8f5687bb Christian König 2017-10-16 206
:: The code at line 200 was first introduced by commit
:: 1b08dfb889b2c584b444538c9500af24ba0a6dc7 drm/amdgpu: remove gart.ready
flag
:: TO: Christian König
:: CC: Alex Deucher
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Re: [Intel-gfx] [PATCH v8 3/3] i915/gvt: Use the initial HW state snapshot saved in i915
This version still seems unhappy (same hardware as the last report): [ 38.650768] vfio_mdev 6814f392-50ac-4236-ae3d-26d472fd8aae: Adding to iommu group 0 [ 38.880317] L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details. [ 39.736514] kvm [3037]: vcpu0, guest rIP: 0x81003e6e disabled perfctr wrmsr: 0xc2 data 0x [ 43.387606] general protection fault, probably for non-canonical address 0xd2ff1d88269987a: [#1] PREEMPT SMP PTI [ 43.387612] CPU: 0 PID: 3050 Comm: qemu-system-x86 Tainted: GE 5.17.0+ #1296 [ 43.387615] Hardware name: LENOVO 20KH006JGE/20KH006JGE, BIOS N23ET62W (1.37 ) 02/19/2019 [ 43.387616] RIP: 0010:__x86_indirect_thunk_array+0x10/0x20 [ 43.387621] Code: 43 54 e9 13 05 c4 ff 53 43 54 e9 db 8c c4 ff 53 43 54 e9 b3 4a d1 ff 53 43 54 e8 07 00 00 00 f3 90 0f ae e8 eb f9 48 89 04 24 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 e8 07 00 00 00 f3 [ 43.387623] RSP: 0018:c0214461fe10 EFLAGS: 00010286 [ 43.387626] RAX: 0d2ff1d88269987a RBX: 9d5808ae RCX: 0004 [ 43.387627] RDX: c0214461fe80 RSI: 00145000 RDI: c021422c3000 [ 43.387628] RBP: c021422c3000 R08: 0001 R09: 000a2800 [ 43.387630] R10: c0214461fe80 R11: c0214461fe80 R12: 0004 [ 43.387631] R13: fd145000 R14: 00145000 R15: c021422c3008 [ 43.387632] FS: 7f50c5576700() GS:9d5b9260() knlGS: [ 43.387633] CS: 0010 DS: ES: CR0: 80050033 [ 43.387635] CR2: CR3: 000103de8005 CR4: 003726f0 [ 43.387636] Call Trace: [ 43.387638] [ 43.387640] ? intel_vgpu_emulate_mmio_read+0xe9/0x390 [ 43.387645] ? intel_vgpu_rw.isra.0+0x1a7/0x1e0 [ 43.387648] ? intel_vgpu_read+0x15c/0x200 [ 43.387650] ? vfs_read+0x9b/0x190 [ 43.387655] ? __x64_sys_pread64+0x8d/0xc0 [ 43.387658] ? do_syscall_64+0x3b/0x90 [ 43.387661] ? entry_SYSCALL_64_after_hwframe+0x44/0xae [ 43.387664] [ 43.387665] Modules linked in: cmac(E) ctr(E) ccm(E) rfcomm(E) sd_mod(E) sg(E) uvcvideo(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) btusb(E) videodev(E) btrtl(E) btbcm(E) btintel(E) mc(E) uas(E) usb_storage(E) scsi_mod(E) scsi_common(E) bnep(E) snd_hda_codec_hdmi(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) bluetooth(E) crc16(E) jitterentropy_rng(E) sha512_generic(E) coretemp(E) drbg(E) crc32_pclmul(E) ansi_cprng(E) ecdh_generic(E) ghash_clmulni_intel(E) ecc(E) wmi_bmof(E) intel_wmi_thunderbolt(E) intel_rapl_msr(E) joydev(E) aesni_intel(E) iwlmvm(E) libaes(E) snd_soc_skl(E) snd_soc_hdac_hda(E) crypto_simd(E) snd_ctl_led(E) snd_hda_ext_core(E) snd_soc_core(E) cryptd(E) snd_soc_acpi_intel_match(E) snd_soc_acpi(E) mac80211(E) snd_hda_codec_realtek(E) snd_soc_sst_ipc(E) snd_hda_codec_generic(E) snd_soc_sst_dsp(E) kvm_intel(E) libarc4(E) intel_cstate(E) snd_hda_intel(E) iwlwifi(E) snd_intel_dspcfg(E) intel_uncore(E) snd_hda_codec(E) pcspkr(E) [ 43.387700] serio_raw(E) snd_hwdep(E) iTCO_wdt(E) efi_pstore(E) iTCO_vendor_support(E) snd_hda_core(E) tpm_crb(E) watchdog(E) thinkpad_acpi(E) snd_pcm(E) nvram(E) processor_thermal_device_pci_legacy(E) intel_soc_dts_iosf(E) ledtrig_audio(E) cfg80211(E) snd_timer(E) processor_thermal_device(E) platform_profile(E) tpm_tis(E) processor_thermal_rfim(E) processor_thermal_mbox(E) tpm_tis_core(E) snd(E) mei_me(E) ucsi_acpi(E) processor_thermal_rapl(E) tpm(E) typec_ucsi(E) soundcore(E) int3403_thermal(E) intel_rapl_common(E) mei(E) intel_pch_thermal(E) typec(E) rng_core(E) wmi(E) int340x_thermal_zone(E) rfkill(E) ac(E) battery(E) int3400_thermal(E) acpi_thermal_rel(E) evdev(E) acpi_pad(E) parport_pc(E) ppdev(E) lp(E) parport(E) efivarfs(E) ip_tables(E) x_tables(E) autofs4(E) i2c_designware_platform(E) i2c_designware_core(E) e1000e(E) nvme(E) xhci_pci(E) crc32c_intel(E) ptp(E) nvme_core(E) xhci_hcd(E) psmouse(E) t10_pi(E) i2c_i801(E) pps_core(E) i2c_smbus(E) thunderbolt(E) usbcore(E) [ 43.387733] crc64_rocksoft(E) crc64(E) crc_t10dif(E) crct10dif_generic(E) intel_lpss_pci(E) crct10dif_pclmul(E) crct10dif_common(E) intel_lpss(E) idma64(E) usb_common(E) mfd_core(E) [ 43.387741] ---[ end trace ]---
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ttm: Evict and restore of compressed object (rev7)
On 2022-04-01 at 15:59:01 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ttm: Evict and restore of compressed object (rev7)
> URL : https://patchwork.freedesktop.org/series/101106/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11438_full -> Patchwork_22758_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_22758_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22758_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (11 -> 11)
> --
>
> No changes in participating hosts
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_22758_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * {igt@gem_lmem_swapping@parallel-random-verify-ccs} (NEW):
> - shard-tglb: NOTRUN -> [SKIP][1] +3 similar issues
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-tglb7/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
>
> * igt@gem_lmem_swapping@verify-random-ccs:
> - shard-iclb: NOTRUN -> [SKIP][2] +3 similar issues
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22758/shard-iclb6/igt@gem_lmem_swapp...@verify-random-ccs.html
>
on TGL and ICL CCS tests are supposed to skip.
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_11438_full and
> Patchwork_22758_full:
>
> ### New IGT tests (2) ###
>
> * igt@gem_lmem_swapping@heavy-verify-random-ccs:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
> * igt@gem_lmem_swapping@parallel-random-verify-ccs:
> - Statuses : 7 skip(s)
> - Exec time: [0.0] s
>
Except on DG2 on other platforms CCS tests will skip.
Changes looking good to merge. Thanks
Ram.
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_22758_full that come from known
> issues:
>
> ### CI changes ###
>
> Possible fixes
>
> * boot:
> - shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
> [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
> [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [FAIL][18],
> [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [PASS][23], [PASS][24],
> [PASS][25], [PASS][26], [PASS][27]) ([i915#5032]) -> ([PASS][28], [PASS][29],
> [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35],
> [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
> [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47],
> [PASS][48], [PASS][49], [PASS][50], [PASS][51])
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl9/boot.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl8/boot.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl8/boot.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl7/boot.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl6/boot.html
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl4/boot.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
>[21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
>[22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl3/boot.html
>[23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl1/boot.html
>[24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438/shard-skl1/boot.html
>[25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11438
Re: [Intel-gfx] [PATCH v8 3/3] i915/gvt: Use the initial HW state snapshot saved in i915
Hi Chirs: Thanks for the testing. I will find a kabelake and try it. :) -Original Message- From: Christoph Hellwig Sent: Friday, April 1, 2022 8:22 PM To: Zhi Wang Cc: dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; intel-gfx@lists.freedesktop.org; intel-gvt-...@lists.freedesktop.org; Zhi Wang ; Christoph Hellwig ; Jason Gunthorpe ; Jani Nikula ; Joonas Lahtinen ; Vivi Rodrigo ; Zhenyu Wang Subject: Re: [PATCH v8 3/3] i915/gvt: Use the initial HW state snapshot saved in i915 This version still seems unhappy (same hardware as the last report): [ 38.650768] vfio_mdev 6814f392-50ac-4236-ae3d-26d472fd8aae: Adding to iommu group 0 [ 38.880317] L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details. [ 39.736514] kvm [3037]: vcpu0, guest rIP: 0x81003e6e disabled perfctr wrmsr: 0xc2 data 0x [ 43.387606] general protection fault, probably for non-canonical address 0xd2ff1d88269987a: [#1] PREEMPT SMP PTI [ 43.387612] CPU: 0 PID: 3050 Comm: qemu-system-x86 Tainted: G E 5.17.0+ #1296 [ 43.387615] Hardware name: LENOVO 20KH006JGE/20KH006JGE, BIOS N23ET62W (1.37 ) 02/19/2019 [ 43.387616] RIP: 0010:__x86_indirect_thunk_array+0x10/0x20 [ 43.387621] Code: 43 54 e9 13 05 c4 ff 53 43 54 e9 db 8c c4 ff 53 43 54 e9 b3 4a d1 ff 53 43 54 e8 07 00 00 00 f3 90 0f ae e8 eb f9 48 89 04 24 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 e8 07 00 00 00 f3 [ 43.387623] RSP: 0018:c0214461fe10 EFLAGS: 00010286 [ 43.387626] RAX: 0d2ff1d88269987a RBX: 9d5808ae RCX: 0004 [ 43.387627] RDX: c0214461fe80 RSI: 00145000 RDI: c021422c3000 [ 43.387628] RBP: c021422c3000 R08: 0001 R09: 000a2800 [ 43.387630] R10: c0214461fe80 R11: c0214461fe80 R12: 0004 [ 43.387631] R13: fd145000 R14: 00145000 R15: c021422c3008 [ 43.387632] FS: 7f50c5576700() GS:9d5b9260() knlGS: [ 43.387633] CS: 0010 DS: ES: CR0: 80050033 [ 43.387635] CR2: CR3: 000103de8005 CR4: 003726f0 [ 43.387636] Call Trace: [ 43.387638] [ 43.387640] ? intel_vgpu_emulate_mmio_read+0xe9/0x390 [ 43.387645] ? intel_vgpu_rw.isra.0+0x1a7/0x1e0 [ 43.387648] ? intel_vgpu_read+0x15c/0x200 [ 43.387650] ? vfs_read+0x9b/0x190 [ 43.387655] ? __x64_sys_pread64+0x8d/0xc0 [ 43.387658] ? do_syscall_64+0x3b/0x90 [ 43.387661] ? entry_SYSCALL_64_after_hwframe+0x44/0xae [ 43.387664] [ 43.387665] Modules linked in: cmac(E) ctr(E) ccm(E) rfcomm(E) sd_mod(E) sg(E) uvcvideo(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) btusb(E) videodev(E) btrtl(E) btbcm(E) btintel(E) mc(E) uas(E) usb_storage(E) scsi_mod(E) scsi_common(E) bnep(E) snd_hda_codec_hdmi(E) x86_pkg_temp_thermal(E) intel_powerclamp(E) bluetooth(E) crc16(E) jitterentropy_rng(E) sha512_generic(E) coretemp(E) drbg(E) crc32_pclmul(E) ansi_cprng(E) ecdh_generic(E) ghash_clmulni_intel(E) ecc(E) wmi_bmof(E) intel_wmi_thunderbolt(E) intel_rapl_msr(E) joydev(E) aesni_intel(E) iwlmvm(E) libaes(E) snd_soc_skl(E) snd_soc_hdac_hda(E) crypto_simd(E) snd_ctl_led(E) snd_hda_ext_core(E) snd_soc_core(E) cryptd(E) snd_soc_acpi_intel_match(E) snd_soc_acpi(E) mac80211(E) snd_hda_codec_realtek(E) snd_soc_sst_ipc(E) snd_hda_codec_generic(E) snd_soc_sst_dsp(E) kvm_intel(E) libarc4(E) intel_cstate(E) snd_hda_intel(E) iwlwifi(E) snd_intel_dspcfg(E) intel_uncore(E) snd_hda_codec(E) pcspkr(E) [ 43.387700] serio_raw(E) snd_hwdep(E) iTCO_wdt(E) efi_pstore(E) iTCO_vendor_support(E) snd_hda_core(E) tpm_crb(E) watchdog(E) thinkpad_acpi(E) snd_pcm(E) nvram(E) processor_thermal_device_pci_legacy(E) intel_soc_dts_iosf(E) ledtrig_audio(E) cfg80211(E) snd_timer(E) processor_thermal_device(E) platform_profile(E) tpm_tis(E) processor_thermal_rfim(E) processor_thermal_mbox(E) tpm_tis_core(E) snd(E) mei_me(E) ucsi_acpi(E) processor_thermal_rapl(E) tpm(E) typec_ucsi(E) soundcore(E) int3403_thermal(E) intel_rapl_common(E) mei(E) intel_pch_thermal(E) typec(E) rng_core(E) wmi(E) int340x_thermal_zone(E) rfkill(E) ac(E) battery(E) int3400_thermal(E) acpi_thermal_rel(E) evdev(E) acpi_pad(E) parport_pc(E) ppdev(E) lp(E) parport(E) efivarfs(E) ip_tables(E) x_tables(E) autofs4(E) i2c_designware_platform(E) i2c_designware_core(E) e1000e(E) nvme(E) xhci_pci(E) crc32c_intel(E) ptp(E) nvme_core(E) xhci_hcd(E) psmouse(E) t10_pi(E) i2c_i801(E) pps_core(E) i2c_smbus(E) thunderbolt(E) usbcore(E) [ 43.387733] crc64_rocksoft(E) crc64(E) crc_t10dif(E) crct10dif_generic(E) intel_lpss_pci(E) crct10dif_pclmul(E) crct10dif_common(E) intel_lpss(E) idma64(E) usb_common(E) mfd_core(E) [ 43.387741] ---[ end trace ]---
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per client GPU utilisation (rev5)
== Series Details == Series: Per client GPU utilisation (rev5) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7e9efd72439e drm/i915: Explicitly track DRM clients -:130: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #130: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 234 lines checked 20138e4593a9 drm/i915: Make GEM contexts track DRM clients 8112c9dac44d drm/i915: Track runtime spent in closed and unreachable GEM contexts 2f89085834a4 drm/i915: Track all user contexts per client f8aa16bf3954 drm/i915: Track context current active time -:140: WARNING:LINE_SPACING: Missing a blank line after declarations #140: FILE: drivers/gpu/drm/i915/gt/intel_context_types.h:149: + u32 last; + I915_SELFTEST_DECLARE(u32 num_underflow); total: 0 errors, 1 warnings, 0 checks, 308 lines checked d68a3dd18e32 drm: Document fdinfo format specification -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:50: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #50: FILE: Documentation/gpu/drm-usage-stats.rst:1: +.. _drm-client-usage-stats: total: 0 errors, 2 warnings, 0 checks, 113 lines checked 358f40a1b272 drm/i915: Count engine instances per uabi class 0fa662dc40c3 drm/i915: Expose client engine utilisation via fdinfo
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Per client GPU utilisation (rev5)
== Series Details == Series: Per client GPU utilisation (rev5) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Per client GPU utilisation (rev5)
== Series Details == Series: Per client GPU utilisation (rev5) URL : https://patchwork.freedesktop.org/series/100573/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/gem/i915_gem_context_types.h:417: warning: Function parameter or member 'client_link' not described in 'i915_gem_context'
[Intel-gfx] ✓ Fi.CI.BAT: success for Per client GPU utilisation (rev5)
== Series Details ==
Series: Per client GPU utilisation (rev5)
URL : https://patchwork.freedesktop.org/series/100573/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11440 -> Patchwork_22761
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/index.html
Participating hosts (45 -> 41)
--
Additional (2): bat-rpls-2 fi-pnv-d510
Missing(6): shard-tglu bat-dg2-8 fi-bsw-cyan fi-icl-u2 bat-jsl-2
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22761 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: [PASS][3] -> [INCOMPLETE][4] ([i915#5127])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][6] -> [INCOMPLETE][7] ([i915#2940])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#5341])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][10] ([i915#3194]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][12] ([i915#4494] / [i915#4957]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][16] ([i915#4528]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [DMESG-WARN][18] ([i915#402]) -> [PASS][19] +1
similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
* igt@kms_force_connector_basic@force-connector-state:
- {bat-adlp-6}: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +1
similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlp-6/igt@kms_force_connector_ba...@force-connector-state.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22761/bat-adlp-6/igt@kms_force_connector_ba...@force-connector-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=10
Re: [Intel-gfx] [PATCH v4 RFC] drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES
Daniel Vetter writes:
> On Wed, Mar 30, 2022 at 02:53:11PM -0700, Matt Atwood wrote:
>> Newer platforms have DSS that aren't necessarily available for both
>> geometry and compute, two queries will need to exist. This introduces
>> the first, when passing a valid engine class and engine instance in the
>> flags returns a topology describing geometry.
>>
>> v2: fix white space errors
>> v3: change flags from hosting 2 8 bit numbers to holding a
>> i915_engine_class_instance struct
>> v4: add error if non rcs engine passed.
>>
>> Cc: Ashutosh Dixit
>> Cc: Matt Roper
>> Cc: Joonas Lahtinen
>> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143
>>
>> Signed-off-by: Matt Atwood
>> ---
>> drivers/gpu/drm/i915/i915_query.c | 71 ++-
>> include/uapi/drm/i915_drm.h | 26 +++
>> 2 files changed, 69 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c
>> b/drivers/gpu/drm/i915/i915_query.c
>> index b5ca00cb6cf6..32be84c95956 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -9,6 +9,7 @@
>> #include "i915_drv.h"
>> #include "i915_perf.h"
>> #include "i915_query.h"
>> +#include "gt/intel_engine_user.h"
>> #include
>>
>> static int copy_query_item(void *query_hdr, size_t query_sz,
>> @@ -28,36 +29,30 @@ static int copy_query_item(void *query_hdr, size_t
>> query_sz,
>> return 0;
>> }
>>
>> -static int query_topology_info(struct drm_i915_private *dev_priv,
>> - struct drm_i915_query_item *query_item)
>> +static int fill_topology_info(const struct sseu_dev_info *sseu,
>> + struct drm_i915_query_item *query_item,
>> + const u8 *subslice_mask)
>> {
>> -const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>> struct drm_i915_query_topology_info topo;
>> u32 slice_length, subslice_length, eu_length, total_length;
>> int ret;
>>
>> -if (query_item->flags != 0)
>> -return -EINVAL;
>> +BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>>
>> if (sseu->max_slices == 0)
>> return -ENODEV;
>>
>> -BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>> -
>> slice_length = sizeof(sseu->slice_mask);
>> subslice_length = sseu->max_slices * sseu->ss_stride;
>> eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
>> total_length = sizeof(topo) + slice_length + subslice_length +
>> eu_length;
>>
>> -ret = copy_query_item(&topo, sizeof(topo), total_length,
>> - query_item);
>> +ret = copy_query_item(&topo, sizeof(topo), total_length, query_item);
>> +
>> if (ret != 0)
>> return ret;
>>
>> -if (topo.flags != 0)
>> -return -EINVAL;
>> -
>> memset(&topo, 0, sizeof(topo));
>> topo.max_slices = sseu->max_slices;
>> topo.max_subslices = sseu->max_subslices;
>> @@ -69,27 +64,64 @@ static int query_topology_info(struct drm_i915_private
>> *dev_priv,
>> topo.eu_stride = sseu->eu_stride;
>>
>> if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>> - &topo, sizeof(topo)))
>> + &topo, sizeof(topo)))
>> return -EFAULT;
>>
>> if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + sizeof(topo)),
>> - &sseu->slice_mask, slice_length))
>> + &sseu->slice_mask, slice_length))
>> return -EFAULT;
>>
>> if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> - sizeof(topo) + slice_length),
>> - sseu->subslice_mask, subslice_length))
>> + sizeof(topo) + slice_length),
>> + subslice_mask, subslice_length))
>> return -EFAULT;
>>
>> if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> - sizeof(topo) +
>> - slice_length + subslice_length),
>> - sseu->eu_mask, eu_length))
>> + sizeof(topo) +
>> + slice_length + subslice_length),
>> + sseu->eu_mask, eu_length))
>> return -EFAULT;
>>
>> return total_length;
>> }
>>
>> +static int query_topology_info(struct drm_i915_private *dev_priv,
>> + struct drm_i915_query_item *query_item)
>> +{
>> +const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu;
>> +
>> +if (query_item->flags != 0)
>> +return -EINVAL;
>> +
>> +return fill_topology_info(sseu, query_item, sseu->subslice_mask);
>> +}
>> +
>> +static int query_geometry_subslices(struct drm_i915_private *i915,
>> +struct drm_i915_q
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11407_full -> Patchwork_22688_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (11 -> 13)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22688_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-uc-ro-default:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-rkl-5/igt@gem_exec_fl...@basic-uc-ro-default.html
Known issues
Here are the changes found in Patchwork_22688_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-iclb: NOTRUN -> [INCOMPLETE][2] ([i915#5441]) +3 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb8/igt@api_intel...@blit-reloc-purge-cache.html
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#658]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb5/igt@feature_discov...@psr2.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#4525]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2846])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: NOTRUN -> [FAIL][10] ([i915#2842]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-skl6/igt@gem_lmem_swapp...@heavy-multi.html
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb7/igt@gem_lmem_swapp...@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk9/igt@gem_lmem_swapp...@parallel-random.html
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_lmem_swapp...@parallel-random.html
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl3/igt@gem_lmem_swapp...@parallel-random.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-kbl: NOTRUN -> [DMESG-FAIL][16] ([i915#5441])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl7/igt@gem_pp...@blt-vs-render-ctx0.html
- shard-tglb: NOTRUN -> [DMESG-FAIL][17] ([i915#5441])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-tglb6/igt@gem_pp...@blt-vs-render-ctx0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][18] ([i915#2658])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk5/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb5/igt@gem_...@reject-modify-context-protection-off-3.html
* igt@gem_rende
[Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates
Frontbuffer rendering and page flips can race with each other
and this can potentialy cause issues with PSR2 selective fetch.
And because pipe/crtc updates are time sentive we can't grab the
PSR lock after intel_pipe_update_start() and before
intel_pipe_update_end().
So here adding the lock and unlock functions and calls, the
proper PSR2 selective fetch handling will come in a separated patch.
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 69 ---
drivers/gpu/drm/i915/display/intel_psr.h | 5 +-
3 files changed, 70 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index f655c16228776..a5439182d5ae4 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -507,6 +507,8 @@ void intel_pipe_update_start(struct intel_crtc_state
*new_crtc_state)
VBLANK_EVASION_TIME_US);
max = vblank_start - 1;
+ intel_psr_lock(new_crtc_state);
+
if (min <= 0 || max <= 0)
goto irq_disable;
@@ -518,7 +520,7 @@ void intel_pipe_update_start(struct intel_crtc_state
*new_crtc_state)
* VBL interrupts will start the PSR exit and prevent a PSR
* re-entry as well.
*/
- intel_psr_wait_for_idle(new_crtc_state);
+ intel_psr_wait_for_idle_locked(new_crtc_state);
local_irq_disable();
@@ -683,6 +685,8 @@ void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state)
local_irq_enable();
+ intel_psr_unlock(new_crtc_state);
+
if (intel_vgpu_active(dev_priv))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 2da2468f555ec..58597480054eb 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1548,10 +1548,19 @@ void intel_psr2_program_plane_sel_fetch(struct
intel_plane *plane,
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct intel_encoder *encoder;
if (!crtc_state->enable_psr2_sel_fetch)
return;
+ for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+crtc_state->uapi.encoder_mask) {
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ lockdep_assert_held(&intel_dp->psr.lock);
+ break;
+ }
+
intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
crtc_state->psr2_man_track_ctl);
}
@@ -1919,13 +1928,13 @@ static int _psr1_ready_for_pipe_update_locked(struct
intel_dp *intel_dp)
}
/**
- * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
+ * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
* @new_crtc_state: new CRTC state
*
* This function is expected to be called from pipe_update_start() where it is
* not expected to race with PSR enable or disable.
*/
-void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
+void intel_psr_wait_for_idle_locked(const struct intel_crtc_state
*new_crtc_state)
{
struct drm_i915_private *dev_priv =
to_i915(new_crtc_state->uapi.crtc->dev);
struct intel_encoder *encoder;
@@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct
intel_crtc_state *new_crtc_state)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
int ret;
- mutex_lock(&intel_dp->psr.lock);
+ lockdep_assert_held(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled) {
- mutex_unlock(&intel_dp->psr.lock);
+ if (!intel_dp->psr.enabled)
continue;
- }
if (intel_dp->psr.psr2_enabled)
ret = _psr2_ready_for_pipe_update_locked(intel_dp);
@@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct
intel_crtc_state *new_crtc_state)
if (ret)
drm_err(&dev_priv->drm, "PSR wait timed out, atomic
update may fail\n");
-
- mutex_unlock(&intel_dp->psr.lock);
}
}
@@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp *intel_dp)
return ret;
}
+
+/**
+ * intel_psr_lock - grab psr.lock mutex
+ * @crtc_state: the crtc state
+ *
+ * This is initially meant to be used by around CRTC update, when
+ * vblank sensitive registers are updated and we need grab the lock
+ * before it to avoid vblank evasion.
+ */
+void intel_psr_lock(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_priv
[Intel-gfx] [PATCH 1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
"SF Partial Frame Enable" also on full update") and also setting
partial frame enable when psr_force_hw_tracking_exit() is called.
Also as PSR2_MAN_TRK_CTL is a double buffered registers do a RMW
is not a good idea so here also setting the man_trk_ctl_enable_bit()
that is required in TGL and only doing a register write.
v2:
- not doing a rmw
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 80002ca6a6ebe..2da2468f555ec 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1436,6 +1436,11 @@ void intel_psr_resume(struct intel_dp *intel_dp)
mutex_unlock(&psr->lock);
}
+static inline u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
+{
+ return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
+}
+
static inline u32 man_trk_ctl_single_full_frame_bit_get(struct
drm_i915_private *dev_priv)
{
return IS_ALDERLAKE_P(dev_priv) ?
@@ -1455,9 +1460,11 @@ static void psr_force_hw_tracking_exit(struct intel_dp
*intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (intel_dp->psr.psr2_sel_fetch_enabled)
- intel_de_rmw(dev_priv,
-PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0,
-man_trk_ctl_single_full_frame_bit_get(dev_priv));
+ intel_de_write(dev_priv,
+ PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+ man_trk_ctl_enable_bit_get(dev_priv) |
+ man_trk_ctl_partial_frame_bit_get(dev_priv) |
+ man_trk_ctl_single_full_frame_bit_get(dev_priv));
/*
* Display WA #0884: skl+
@@ -1554,10 +1561,7 @@ static void psr2_man_trk_ctl_calc(struct
intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 val = 0;
-
- if (!IS_ALDERLAKE_P(dev_priv))
- val = PSR2_MAN_TRK_CTL_ENABLE;
+ u32 val = man_trk_ctl_enable_bit_get(dev_priv);
/* SF partial frame enable has to be set even on full update */
val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
--
2.35.1
[Intel-gfx] [PATCH 3/3] drm/i915/display/psr: Use continuos full frame to handle frontbuffer invalidations
Instead of exit PSR when a frontbuffer invalidation happens, we can
enable the PSR2 selective fetch continuous full frame, that will keep
the panel updated like PSR was disabled but without keeping PSR active.
So as soon as the frontbuffer flush happens we can disable the
continuous full frame and start to do selective fetches much quicker
than the path that would enable PSR, that will wait a few frames
to actually activate PSR.
Also this approach has proven to fix some glitches found in Alderlake-P
when there are a lot of invalidations happening together with page
flips.
Some may ask why it is writing to CURSURFLIVE(), it is because
that is the way that hardware team provided us to poke display to
handle PSR updates, and it is being used since display 9.
v2:
- handling possible race conditions between frontbuffer rendering and
page flips
Cc: Khaled Almahallawy
Cc: Shawn C Lee
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 88 ---
2 files changed, 77 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 96024f7d839d4..cfd042117b109 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1525,6 +1525,7 @@ struct intel_psr {
bool colorimetry_support;
bool psr2_enabled;
bool psr2_sel_fetch_enabled;
+ bool psr2_sel_fetch_cff_enabled;
bool req_psr2_sdp_prior_scanline;
u8 sink_sync_latency;
ktime_t last_entry_attempt;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 58597480054eb..5b1963b7743dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1221,6 +1221,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
intel_dp->psr.dc3co_exit_delay = val;
intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
intel_dp->psr.psr2_sel_fetch_enabled =
crtc_state->enable_psr2_sel_fetch;
+ intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
intel_dp->psr.req_psr2_sdp_prior_scanline =
crtc_state->req_psr2_sdp_prior_scanline;
@@ -1455,6 +1456,13 @@ static inline u32
man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev
PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
}
+static inline u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private
*dev_priv)
+{
+ return IS_ALDERLAKE_P(dev_priv) ?
+ ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
+ PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
+}
+
static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1558,6 +1566,8 @@ void intel_psr2_program_trans_man_trk_ctl(const struct
intel_crtc_state *crtc_st
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
lockdep_assert_held(&intel_dp->psr.lock);
+ if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
+ return;
break;
}
@@ -2135,6 +2145,27 @@ static void intel_psr_work(struct work_struct *work)
mutex_unlock(&intel_dp->psr.lock);
}
+static void _psr_invalidate_handle(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ u32 val;
+
+ if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
+ return;
+
+ val = man_trk_ctl_enable_bit_get(dev_priv) |
+ man_trk_ctl_partial_frame_bit_get(dev_priv) |
+ man_trk_ctl_continuos_full_frame(dev_priv);
+ intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
+ intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
+ intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
+ } else {
+ intel_psr_exit(intel_dp);
+ }
+}
+
/**
* intel_psr_invalidate - Invalidade PSR
* @dev_priv: i915 device
@@ -2171,7 +2202,7 @@ void intel_psr_invalidate(struct drm_i915_private
*dev_priv,
intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
if (pipe_frontbuffer_bits)
- intel_psr_exit(intel_dp);
+ _psr_invalidate_handle(intel_dp);
mutex_unlock(&intel_dp->psr.lock);
}
@@ -2203,6 +2234,42 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp,
unsigned int frontbuffer_bits,
intel_dp->psr.dc3co_exit_delay);
}
+static void _psr_flush_handle(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare() (rev3)
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11407_full -> Patchwork_22688_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (11 -> 13)
--
Additional (2): shard-rkl shard-dg1
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22688_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-uc-ro-default:
- {shard-rkl}:NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-rkl-5/igt@gem_exec_fl...@basic-uc-ro-default.html
Known issues
Here are the changes found in Patchwork_22688_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-iclb: NOTRUN -> [INCOMPLETE][2] ([i915#5441]) +3 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb8/igt@api_intel...@blit-reloc-purge-cache.html
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][3] ([i915#658]) +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb5/igt@feature_discov...@psr2.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#4525]) +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb3/igt@gem_exec_balan...@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2846])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11407/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: NOTRUN -> [FAIL][10] ([i915#2842]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk3/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-skl6/igt@gem_lmem_swapp...@heavy-multi.html
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#4613]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb7/igt@gem_lmem_swapp...@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk9/igt@gem_lmem_swapp...@parallel-random.html
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl6/igt@gem_lmem_swapp...@parallel-random.html
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-apl3/igt@gem_lmem_swapp...@parallel-random.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-kbl: NOTRUN -> [DMESG-FAIL][16] ([i915#5441])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-kbl7/igt@gem_pp...@blt-vs-render-ctx0.html
- shard-tglb: NOTRUN -> [DMESG-FAIL][17] ([i915#5441])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-tglb6/igt@gem_pp...@blt-vs-render-ctx0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][18] ([i915#2658])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-glk5/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22688/shard-iclb5/igt@gem_...@reject-modify-context-protection-off-3.html
* igt@gem_rende
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details == Series: series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch URL : https://patchwork.freedesktop.org/series/102095/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_psr.c:2549: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead ./drivers/gpu/drm/i915/display/intel_psr.c:2549: warning: expecting prototype for intel_psr_lock(). Prototype was for intel_psr_unlock() instead
[Intel-gfx] ✓ Fi.CI.IGT: success for Per client GPU utilisation (rev5)
== Series Details == Series: Per client GPU utilisation (rev5) URL : https://patchwork.freedesktop.org/series/100573/ State : success == Summary == CI Bug Log - changes from CI_DRM_11440_full -> Patchwork_22761_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts New tests - New tests have been introduced between CI_DRM_11440_full and Patchwork_22761_full: ### New IGT tests (51) ### * igt@drm_fdinfo@all-busy-check-all: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 0.60] s * igt@drm_fdinfo@all-busy-idle-check-all: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 0.67] s * igt@drm_fdinfo@basics: - Statuses : 4 pass(s) 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy-check-all: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy-check-all@bcs0: - Statuses : 4 pass(s) - Exec time: [0.52, 0.53] s * igt@drm_fdinfo@busy-check-all@rcs0: - Statuses : 4 pass(s) - Exec time: [0.52, 0.53] s * igt@drm_fdinfo@busy-check-all@vcs0: - Statuses : 4 pass(s) - Exec time: [0.52, 0.53] s * igt@drm_fdinfo@busy-check-all@vcs1: - Statuses : 1 pass(s) - Exec time: [0.52] s * igt@drm_fdinfo@busy-check-all@vecs0: - Statuses : 4 pass(s) - Exec time: [0.52, 0.53] s * igt@drm_fdinfo@busy-hang: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy-hang@bcs0: - Statuses : 6 pass(s) - Exec time: [1.03, 1.13] s * igt@drm_fdinfo@busy-hang@rcs0: - Statuses : 6 pass(s) - Exec time: [1.02, 1.10] s * igt@drm_fdinfo@busy-hang@vcs0: - Statuses : 6 pass(s) - Exec time: [1.03, 1.12] s * igt@drm_fdinfo@busy-hang@vcs1: - Statuses : 2 pass(s) - Exec time: [1.02, 1.10] s * igt@drm_fdinfo@busy-hang@vecs0: - Statuses : 6 pass(s) - Exec time: [1.02, 1.10] s * igt@drm_fdinfo@busy-idle: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy-idle-check-all: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@busy-idle-check-all@bcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.70] s * igt@drm_fdinfo@busy-idle-check-all@rcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.69] s * igt@drm_fdinfo@busy-idle-check-all@vcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.68] s * igt@drm_fdinfo@busy-idle-check-all@vcs1: - Statuses : 3 pass(s) - Exec time: [0.62, 0.63] s * igt@drm_fdinfo@busy-idle-check-all@vecs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.69] s * igt@drm_fdinfo@busy-idle@bcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.71] s * igt@drm_fdinfo@busy-idle@rcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.69] s * igt@drm_fdinfo@busy-idle@vcs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.70] s * igt@drm_fdinfo@busy-idle@vcs1: - Statuses : 3 pass(s) - Exec time: [0.62, 0.64] s * igt@drm_fdinfo@busy-idle@vecs0: - Statuses : 6 pass(s) - Exec time: [0.62, 0.69] s * igt@drm_fdinfo@busy@bcs0: - Statuses : 5 pass(s) - Exec time: [0.52, 0.59] s * igt@drm_fdinfo@busy@rcs0: - Statuses : 5 pass(s) - Exec time: [0.52, 0.58] s * igt@drm_fdinfo@busy@vcs0: - Statuses : 5 pass(s) - Exec time: [0.52, 0.58] s * igt@drm_fdinfo@busy@vcs1: - Statuses : 2 pass(s) - Exec time: [0.51, 0.52] s * igt@drm_fdinfo@busy@vecs0: - Statuses : 5 pass(s) - Exec time: [0.51, 0.58] s * igt@drm_fdinfo@idle: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@idle@bcs0: - Statuses : 6 pass(s) - Exec time: [0.50, 0.51] s * igt@drm_fdinfo@idle@rcs0: - Statuses : 6 pass(s) - Exec time: [0.50, 0.52] s * igt@drm_fdinfo@idle@vcs0: - Statuses : 6 pass(s) - Exec time: [0.50, 0.52] s * igt@drm_fdinfo@idle@vcs1: - Statuses : 3 pass(s) - Exec time: [0.50] s * igt@drm_fdinfo@idle@vecs0: - Statuses : 6 pass(s) - Exec time: [0.50, 0.52] s * igt@drm_fdinfo@isolation@bcs0: - Statuses : 6 pass(s) - Exec time: [0.52, 0.59] s * igt@drm_fdinfo@isolation@rcs0: - Statuses : 6 pass(s) - Exec time: [0.52, 0.64] s * igt@drm_fdinfo@isolation@vcs0: - Statuses : 6 pass(s) - Exec time: [0.52, 0.60] s * igt@drm_fdinfo@isolation@vcs1: - Statuses : 2 pass(s) - Exec time: [0.52] s * igt@drm_fdinfo@isolation@vecs0: - Statuses : 6 pass(s) - Exec time: [0.52, 0.59] s * igt@drm_fdinfo@most-busy-check-all: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt@drm_fdinfo@most-busy-check-all@bcs0: - Statuses : 6 pass(s) - Exec time: [0.51, 0.55] s * igt@drm_fdinfo@most-busy-check-all@rcs0: - Statuses : 6 pass(s)
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details ==
Series: series starting with [1/3] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL : https://patchwork.freedesktop.org/series/102095/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11440 -> Patchwork_22762
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/index.html
Participating hosts (46 -> 42)
--
Additional (2): fi-kbl-soraka bat-rpls-2
Missing(6): shard-tglu bat-dg2-8 fi-bsw-cyan fi-icl-u2 shard-rkl
fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22762:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {bat-adlp-6}: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlp-6/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/bat-adlp-6/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
Known issues
Here are the changes found in Patchwork_22762 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: [PASS][6] -> [INCOMPLETE][7] ([i915#5127])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][11] -> [INCOMPLETE][12] ([i915#4785])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] /
[i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][16] ([i915#3194]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-adlm-1}: [INCOMPLETE][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlm-1/igt@i915_pm_...@basic-pci-d3-state.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchw
Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates
Hi "José,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.17 next-20220401]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a011
(https://download.01.org/0day-ci/archive/20220402/202204020818.qezcpujb-...@intel.com/config)
compiler: gcc-11 (Debian 11.2.0-19) 11.2.0
reproduce (this is a W=1 build):
#
https://github.com/intel-lab-lkp/linux/commit/955b4bf1a2fd2e6652980814983464f3db8f955f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review
Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
git checkout 955b4bf1a2fd2e6652980814983464f3db8f955f
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_psr.c:2485: warning: expecting prototype
>> for intel_psr_lock(). Prototype was for intel_psr_unlock() instead
vim +2485 drivers/gpu/drm/i915/display/intel_psr.c
2477
2478 /**
2479 * intel_psr_lock - grab psr.lock mutex
2480 * @crtc_state: the crtc state
2481 *
2482 * Release the PSR lock that was held during pipe update.
2483 */
2484 void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> 2485 {
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Re: [Intel-gfx] [PATCH 2/3] drm/i915/display/psr: Lock and unlock PSR around pipe updates
Hi "José,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.17 next-20220401]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/intel-lab-lkp/linux/commits/Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a005
(https://download.01.org/0day-ci/archive/20220402/202204020818.p5bapjre-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
cc2e2b80a1f36a28fa7c96c38c2674b10868f09f)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/intel-lab-lkp/linux/commit/955b4bf1a2fd2e6652980814983464f3db8f955f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review
Jos-Roberto-de-Souza/drm-i915-display-psr-Set-partial-frame-enable-when-forcing-full-frame-fetch/20220402-062837
git checkout 955b4bf1a2fd2e6652980814983464f3db8f955f
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_psr.c:2485: warning: expecting prototype
>> for intel_psr_lock(). Prototype was for intel_psr_unlock() instead
vim +2485 drivers/gpu/drm/i915/display/intel_psr.c
2477
2478 /**
2479 * intel_psr_lock - grab psr.lock mutex
2480 * @crtc_state: the crtc state
2481 *
2482 * Release the PSR lock that was held during pipe update.
2483 */
2484 void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
> 2485 {
--
0-DAY CI Kernel Test Service
https://01.org/lkp
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch
== Series Details == Series: series starting with [1/3] drm/i915/display/psr: Set partial frame enable when forcing full frame fetch URL : https://patchwork.freedesktop.org/series/102095/ State : success == Summary == CI Bug Log - changes from CI_DRM_11440_full -> Patchwork_22762_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22762_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [PASS][1] -> [TIMEOUT][2] ([i915#3063]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb5/igt@gem_...@in-flight-contexts-10ms.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb6/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@kms: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#232]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb6/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb2/igt@gem_...@kms.html * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-iclb1/igt@gem_exec_balan...@parallel-balancer.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html * igt@gem_exec_fair@basic-deadline: - shard-apl: NOTRUN -> [FAIL][7] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-tglb1/igt@gem_exec_par...@no-blt.html * igt@gem_exec_suspend@basic-s3@smem: - shard-kbl: NOTRUN -> [DMESG-WARN][14] ([i915#180]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl6/igt@gem_exec_suspend@basic...@smem.html * igt@gem_lmem_swapping@heavy-multi: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-skl4/igt@gem_lmem_swapp...@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl3/igt@gem_pwr...@basic-exhaustion.html - shard-apl: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][19] ([i915#3318]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl7/igt@gem_userptr_bl...@vma-merge.html - shard-kbl: NOTRUN -> [FAIL][20] ([i915#3318]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-kbl1/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-fd: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1436]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/shard-apl7/igt@gem_workarou...@suspend-resume-fd.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22762/shard-apl6/igt@gem_workarou...@suspend-resume-fd.html * igt@gen9_exec_parse@allowed-all: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Splitting intel-gtt calls for non-x86 platforms (rev7)
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms (rev7)
URL : https://patchwork.freedesktop.org/series/101552/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
270de0551c0b drm/i915/gt: Split intel-gtt functions by arch
-:368: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#368: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:221:
+void intel_ggtt_bind_vma(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
-:377: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#377: FILE: drivers/gpu/drm/i915/gt/intel_ggtt.c:245:
+void intel_ggtt_unbind_vma(struct i915_address_space *vm,
struct i915_vma_resource *vma_res)
-:852: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#852:
new file mode 100644
-:1174: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1174: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.c:318:
+static void gen5_ggtt_clear_range(struct i915_address_space *vm,
+u64 start, u64 length)
-:1398: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#1398: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.c:542:
+ if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
^
-:1398: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#1398: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.c:542:
+ if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
^
-:1540: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#1540: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.h:24:
+}
+static inline int intel_gt_gmch_gen5_probe(struct i915_ggtt *ggtt)
-:1545: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#1545: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.h:29:
+}
+static inline int intel_gt_gmch_gen6_probe(struct i915_ggtt *ggtt)
-:1550: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#1550: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.h:34:
+}
+static inline int intel_gt_gmch_gen8_probe(struct i915_ggtt *ggtt)
-:1555: CHECK:LINE_SPACING: Please use a blank line after
function/struct/union/enum declarations
#1555: FILE: drivers/gpu/drm/i915/gt/intel_gt_gmch.h:39:
+}
+static inline int intel_gt_gmch_gen5_enable_hw(struct drm_i915_private *i915)
-:1572: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1572: FILE: drivers/gpu/drm/i915/gt/intel_gtt.h:553:
+void intel_ggtt_bind_vma(struct i915_address_space *vm,
+ struct i915_vm_pt_stash *stash,
-:1577: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1577: FILE: drivers/gpu/drm/i915/gt/intel_gtt.h:558:
+void intel_ggtt_unbind_vma(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res);
total: 0 errors, 1 warnings, 11 checks, 1520 lines checked
96ebea61b475 drm/i915: Require INTEL_GTT to depend on X86
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Splitting intel-gtt calls for non-x86 platforms (rev7)
== Series Details == Series: Splitting intel-gtt calls for non-x86 platforms (rev7) URL : https://patchwork.freedesktop.org/series/101552/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for Splitting intel-gtt calls for non-x86 platforms (rev7)
== Series Details ==
Series: Splitting intel-gtt calls for non-x86 platforms (rev7)
URL : https://patchwork.freedesktop.org/series/101552/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11440 -> Patchwork_22763
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22763 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22763, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/index.html
Participating hosts (47 -> 41)
--
Additional (1): bat-rpls-2
Missing(7): shard-tglu bat-dg2-8 bat-adlm-1 fi-bsw-cyan shard-rkl
shard-dg1 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22763:
### IGT changes ###
Possible regressions
* igt@gem_exec_fence@nb-await@bcs0:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-icl-u2/igt@gem_exec_fence@nb-aw...@bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-icl-u2/igt@gem_exec_fence@nb-aw...@bcs0.html
Known issues
Here are the changes found in Patchwork_22763 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-blb-e6850: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-blb-e6850/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][5] -> [INCOMPLETE][6] ([i915#3303] /
[i915#4785])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][7] ([i915#3690] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-icl-u2/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] /
[i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [FAIL][9] ([i915#3194]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-blb-e6850/igt@core_hotunp...@unbind-rebind.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-hsw-4770:[INCOMPLETE][13] ([i915#4785]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][17] ([i915#3576]) -> [PASS][18] +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/bat-adlp-6/igt@kms_busy@ba...@flip.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/bat-adlp-6/igt@kms_busy@ba...@flip.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11440/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22763/fi-tgl-u2/igt@kms_flip@basic-plain-f...@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or
Re: [Intel-gfx] [PATCH v7 7/9] drm/ttm: Add a parameter to add extra pages into ttm_tt
On 2022-04-01 at 16:31:19 +0200, Christian König wrote:
> I would be nicer to push this through drm-misc-next, but the intel branch
> works for me as well.
Hi Christian
I have pushed this patch into drm-misc-next.
Regards,
Ram.
>
> Regards,
> Christian.
>
> Am 01.04.22 um 16:28 schrieb Ramalingam C:
> > Christian, Joonas and vivi
> >
> > Once the premerge results are greeen, if this patch can be merged into
> > drm-intel-gt-next along with other patches could you please ack the
> > request to merge into drm-intel-gt-next?
> >
> > Thanks
> > Ram
> >
> > On 2022-04-01 at 18:07:49 +0530, Ramalingam C wrote:
> > > Add a parameter called "extra_pages" for ttm_tt_init, to indicate that
> > > driver needs extra pages in ttm_tt.
> > >
> > > v2:
> > >Used imperative wording [Thomas and Christian]
> > >
> > > Signed-off-by: Ramalingam C
> > > cc: Christian Koenig
> > > cc: Hellstrom Thomas
> > > Reviewed-by: Thomas Hellstrom
> > > Reviewed-by: Christian Konig
> > > Reviewed-by: Nirmoy Das
> > > ---
> > > drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
> > > drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 2 +-
> > > drivers/gpu/drm/qxl/qxl_ttm.c | 2 +-
> > > drivers/gpu/drm/ttm/ttm_agp_backend.c | 2 +-
> > > drivers/gpu/drm/ttm/ttm_tt.c | 12 +++-
> > > drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 +-
> > > include/drm/ttm/ttm_tt.h | 4 +++-
> > > 7 files changed, 15 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
> > > b/drivers/gpu/drm/drm_gem_vram_helper.c
> > > index dc7f938bfff2..123045b58fec 100644
> > > --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> > > +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> > > @@ -867,7 +867,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct
> > > ttm_buffer_object *bo,
> > > if (!tt)
> > > return NULL;
> > > - ret = ttm_tt_init(tt, bo, page_flags, ttm_cached);
> > > + ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0);
> > > if (ret < 0)
> > > goto err_ttm_tt_init;
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > > index c40aca99442f..a878910a563c 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> > > @@ -293,7 +293,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct
> > > ttm_buffer_object *bo,
> > > i915_tt->is_shmem = true;
> > > }
> > > - ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching);
> > > + ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0);
> > > if (ret)
> > > goto err_free;
> > > diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> > > index 95df5750f47f..9ba871bd19b1 100644
> > > --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> > > +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> > > @@ -113,7 +113,7 @@ static struct ttm_tt *qxl_ttm_tt_create(struct
> > > ttm_buffer_object *bo,
> > > ttm = kzalloc(sizeof(struct ttm_tt), GFP_KERNEL);
> > > if (ttm == NULL)
> > > return NULL;
> > > - if (ttm_tt_init(ttm, bo, page_flags, ttm_cached)) {
> > > + if (ttm_tt_init(ttm, bo, page_flags, ttm_cached, 0)) {
> > > kfree(ttm);
> > > return NULL;
> > > }
> > > diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c
> > > b/drivers/gpu/drm/ttm/ttm_agp_backend.c
> > > index 6ddc16f0fe2b..d27691f2e451 100644
> > > --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c
> > > +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
> > > @@ -134,7 +134,7 @@ struct ttm_tt *ttm_agp_tt_create(struct
> > > ttm_buffer_object *bo,
> > > agp_be->mem = NULL;
> > > agp_be->bridge = bridge;
> > > - if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined)) {
> > > + if (ttm_tt_init(&agp_be->ttm, bo, page_flags, ttm_write_combined, 0)) {
> > > kfree(agp_be);
> > > return NULL;
> > > }
> > > diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
> > > index d234aab800a0..1a66d9fc589a 100644
> > > --- a/drivers/gpu/drm/ttm/ttm_tt.c
> > > +++ b/drivers/gpu/drm/ttm/ttm_tt.c
> > > @@ -134,9 +134,10 @@ void ttm_tt_destroy(struct ttm_device *bdev, struct
> > > ttm_tt *ttm)
> > > static void ttm_tt_init_fields(struct ttm_tt *ttm,
> > > struct ttm_buffer_object *bo,
> > > uint32_t page_flags,
> > > -enum ttm_caching caching)
> > > +enum ttm_caching caching,
> > > +unsigned long extra_pages)
> > > {
> > > - ttm->num_pages = PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT;
> > > + ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) +
> > > extra_pages;
> > > ttm->caching = ttm_cached;
> > > ttm->page
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/rps: Centralize computation of freq caps (rev5)
== Series Details == Series: drm/i915/rps: Centralize computation of freq caps (rev5) URL : https://patchwork.freedesktop.org/series/101606/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map
On Tue, Mar 22, 2022 at 02:14:37PM +0530, Mullati Siva wrote:
From: Siva Mullati
Convert CT commands and descriptors to use iosys_map rather
than plain pointer and save it in the intel_guc_ct_buffer struct.
This will help with ct_write and ct_read for cmd send and receive
after the initialization by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 127 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index f01325cd1b62..1c21ced44106 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
#define CT_PROBE_ERROR(_ct, _fmt, ...) \
i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__)
+#define ct_desc_read(desc_map_, field_) \
+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_)
+#define ct_desc_write(desc_map_, field_, val_) \
+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_,
val_)
+
/**
* DOC: CTB Blob
*
@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct
intel_guc_ct *ct)
#define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE)
#define G2H_ROOM_BUFFER_SIZE(CTB_G2H_BUFFER_SIZE / 4)
+#define CTB_SEND_DESC_OFFSET (0X)
0, or even better... 0u, so you don't have to cast to unsigned in other
places
+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE)
+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE)
+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE)
+
struct ct_request {
struct list_head link;
u32 fence;
@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
init_waitqueue_head(&ct->wq);
}
-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc)
+static void guc_ct_buffer_desc_init(struct iosys_map *desc)
{
- memset(desc, 0, sizeof(*desc));
+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
}
static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb)
@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct
intel_guc_ct_buffer *ctb)
space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space;
atomic_set(&ctb->space, space);
- guc_ct_buffer_desc_init(ctb->desc);
+ guc_ct_buffer_desc_init(&ctb->desc_map);
}
static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb,
- struct guc_ct_buffer_desc *desc,
- u32 *cmds, u32 size_in_bytes, u32 resv_space)
+ struct iosys_map *desc,
+ struct iosys_map *cmds,
+ u32 size_in_bytes, u32 resv_space)
{
GEM_BUG_ON(size_in_bytes % 4);
- ctb->desc = desc;
- ctb->cmds = cmds;
+ ctb->desc_map = *desc;
+ ctb->cmds_map = *cmds;
ctb->size = size_in_bytes / 4;
ctb->resv_space = resv_space / 4;
@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct,
bool send,
int intel_guc_ct_init(struct intel_guc_ct *ct)
{
struct intel_guc *guc = ct_to_guc(ct);
- struct guc_ct_buffer_desc *desc;
+ struct iosys_map blob_map;
+ struct iosys_map desc_map;
+ struct iosys_map cmds_map;
u32 blob_size;
u32 cmds_size;
u32 resv_space;
void *blob;
- u32 *cmds;
int err;
err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO);
@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct)
CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma),
blob_size);
- /* store pointers to desc and cmds for send ctb */
- desc = blob;
- cmds = blob + 2 * CTB_DESC_SIZE;
+ if (i915_gem_object_is_lmem(ct->vma->obj))
+ iosys_map_set_vaddr_iomem(&blob_map,
+ (void __iomem *)blob);
+ else
+ iosys_map_set_vaddr(&blob_map, blob);
+
+ /* store sysmap to desc_map and cmds_map for send ctb */
+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET);
+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET);
cmds_size = CTB_H2G_BUFFER_SIZE;
resv_space = 0;
- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send",
-ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size,
-resv_space);
+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send",
+(u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET,
+cmds_size, resv_space);
- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space);
+ guc_ct_buffer_init(&ct->ctbs.send,
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rps: Centralize computation of freq caps (rev5)
== Series Details ==
Series: drm/i915/rps: Centralize computation of freq caps (rev5)
URL : https://patchwork.freedesktop.org/series/101606/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11441 -> Patchwork_22764
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/index.html
Participating hosts (45 -> 41)
--
Additional (1): bat-adlm-1
Missing(5): shard-tglu fi-bsw-cyan fi-icl-u2 bat-jsl-2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22764:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ringfill@basic-all:
- {bat-dg2-8}:[PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/bat-dg2-8/igt@gem_ringf...@basic-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/bat-dg2-8/igt@gem_ringf...@basic-all.html
Known issues
Here are the changes found in Patchwork_22764 that come from known issues:
### CI changes ###
Possible fixes
* boot:
- fi-snb-2600:[FAIL][3] ([i915#4338]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/fi-snb-2600/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-snb-2600/boot.html
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#109315]) +17
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: [PASS][6] -> [INCOMPLETE][7] ([i915#5127])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][8] ([i915#4494] / [i915#4957])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-ivb-3770:[PASS][9] -> [INCOMPLETE][10] ([i915#5370])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-ivb-3770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][11] ([fdo#109271]) +40 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-tgl-u2/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-snb-2600:NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#5341])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-snb-2600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@runner@aborted:
- fi-ivb-3770:NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-ivb-3770/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [INCOMPLETE][17] ([i915#4418]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}: [DMESG-FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][21] ([i915#4785]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1144
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/rps: Centralize computation of freq caps (rev5)
== Series Details == Series: drm/i915/rps: Centralize computation of freq caps (rev5) URL : https://patchwork.freedesktop.org/series/101606/ State : success == Summary == CI Bug Log - changes from CI_DRM_11441_full -> Patchwork_22764_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22764_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#2842]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/shard-apl6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-apl3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/shard-glk3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-glk3/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-apl: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271]) +162 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-skl6/igt@gem_exec_par...@no-vebox.html * igt@gem_exec_suspend@basic-s3@smem: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11441/shard-kbl7/igt@gem_exec_suspend@basic...@smem.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-kbl1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_lmem_swapping@heavy-random: - shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-skl6/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271]) +99 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-kbl3/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-tglb: NOTRUN -> [SKIP][16] ([fdo#111644] / [i915#1397] / [i915#2411]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-tglb3/igt@i915_pm_...@modeset-non-lpsp-stress.html - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#110892]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-iclb2/igt@i915_pm_...@modeset-non-lpsp-stress.html * igt@kms_atomic@atomic_plane_damage: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#4765]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-iclb2/igt@kms_atomic@atomic_plane_damage.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#5286]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-tglb3/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html - shard-iclb: NOTRUN -> [SKIP][20] ([i915#5286]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-iclb2/igt@kms_big...@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][21] ([i915#3743]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22764/shard-skl1/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-as
