[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix i915 error_state_read ptr use (rev2)
== Series Details == Series: Fix i915 error_state_read ptr use (rev2) URL : https://patchwork.freedesktop.org/series/100768/ State : warning == Summary == $ dim checkpatch origin/drm-tip 729b7794c19d drm/i915/reset: Fix error_state_read ptr + offset use -:18: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #18: 5014 [ 5590.803000] BUG: unable to handle page fault for address: a0b0e000 total: 0 errors, 1 warnings, 0 checks, 20 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for Fix i915 error_state_read ptr use (rev2)
== Series Details ==
Series: Fix i915 error_state_read ptr use (rev2)
URL : https://patchwork.freedesktop.org/series/100768/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11291 -> Patchwork_22425
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/index.html
Participating hosts (40 -> 40)
--
Additional (1): fi-pnv-d510
Missing(1): fi-bsw-cyan
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22425:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ringfill@basic-all:
- {bat-dg2-9}:[PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-dg2-9/igt@gem_ringf...@basic-all.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/bat-dg2-9/igt@gem_ringf...@basic-all.html
* igt@i915_selftest@live@objects:
- {fi-jsl-1}: [PASS][3] -> [INCOMPLETE][4] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-jsl-1/igt@i915_selftest@l...@objects.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-jsl-1/igt@i915_selftest@l...@objects.html
Known issues
Here are the changes found in Patchwork_22425 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: NOTRUN -> [FAIL][6] ([i915#4547])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271]) +57 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-pnv-d510/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][8] ([i915#4547]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][10] ([i915#3921]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][12] ([i915#2867]) -> [PASS][13] +17
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][14] ([i915#3576]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-adlp-6/igt@kms_busy@ba...@modeset.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/bat-adlp-6/igt@kms_busy@ba...@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
Build changes
-
* Linux: CI_DRM_11291 -> Patchwork_22425
CI-20190529: 20190529
CI_DRM_11291: 1e3f898ee67cb2fd8c58799ae8a094f73054c8b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6359: 57049558c452272b27eeb099fac07e55a924bbf9 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22425: 729b7794c19dc6323062363321f9a38673aba221 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
729b7794c19d drm/i915/reset: Fix error_state_read ptr + offset use
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: avoid concurrent writes to aux_inv (rev2)
== Series Details == Series: drm/i915: avoid concurrent writes to aux_inv (rev2) URL : https://patchwork.freedesktop.org/series/100772/ State : warning == Summary == $ dim checkpatch origin/drm-tip f070e684b15e drm/i915: avoid concurrent writes to aux_inv -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: GPU hangs have been observed when multiple engines write to the same aux_inv total: 0 errors, 1 warnings, 0 checks, 114 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: avoid concurrent writes to aux_inv (rev2)
== Series Details == Series: drm/i915: avoid concurrent writes to aux_inv (rev2) URL : https://patchwork.freedesktop.org/series/100772/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: avoid concurrent writes to aux_inv (rev2)
== Series Details ==
Series: drm/i915: avoid concurrent writes to aux_inv (rev2)
URL : https://patchwork.freedesktop.org/series/100772/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11291 -> Patchwork_22426
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22426 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22426, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/index.html
Participating hosts (40 -> 40)
--
Additional (1): bat-jsl-2
Missing(1): fi-bsw-cyan
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22426:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gt_engines:
- fi-tgl-1115g4: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-tgl-1115g4/igt@i915_selftest@live@gt_engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-tgl-1115g4/igt@i915_selftest@live@gt_engines.html
Known issues
Here are the changes found in Patchwork_22426 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][4] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@i915_module_load@reload:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-bsw-kefka/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-bsw-kefka/igt@i915_module_l...@reload.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][7] ([i915#4547]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#2867]) -> [PASS][12] +17
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][13] ([i915#3576]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
Warnings
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][15] ([i915#4494] / [i915#4957]) ->
[DMESG-FAIL][16] ([i915#4957])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][17] ([i915#4312]) -> [FAIL][18] ([i915#2722] /
[i915#4312])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-skl-6600u/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22426/fi-skl-6600u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[
Re: [Intel-gfx] [PATCH v6 01/13] drm/i915/guc: Update GuC ADS size for error capture lists
Hi Alan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm/drm-next next-20220225]
[cannot apply to drm-tip/drm-tip drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Alan-Previn/Add-GuC-Error-Capture-Support/20220226-135414
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a011
(https://download.01.org/0day-ci/archive/20220226/202202261725.qsv41wrm-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/4c1018d0e536adbe13cf0b71049b0a94073eec7e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Alan-Previn/Add-GuC-Error-Capture-Support/20220226-135414
git checkout 4c1018d0e536adbe13cf0b71049b0a94073eec7e
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:222:1: warning: no previous
>> prototype for 'intel_guc_capture_getlistsize' [-Wmissing-prototypes]
222 | intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32
type, u32 classid,
| ^
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:252:1: warning: no previous
>> prototype for 'intel_guc_capture_getlist' [-Wmissing-prototypes]
252 | intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32
type, u32 classid,
| ^
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:321:6: warning: no previous
>> prototype for 'intel_guc_capture_destroy' [-Wmissing-prototypes]
321 | void intel_guc_capture_destroy(struct intel_guc *guc)
| ^
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:332:5: warning: no previous
>> prototype for 'intel_guc_capture_init' [-Wmissing-prototypes]
332 | int intel_guc_capture_init(struct intel_guc *guc)
| ^~
vim +/intel_guc_capture_getlistsize +222
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
220
221 int
> 222 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32
> type, u32 classid,
223size_t *size)
224 {
225 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
226 struct __guc_state_capture_priv *gc = guc->capture.priv;
227 struct __guc_capture_ads_cache *cache =
&gc->ads_cache[owner][type][classid];
228 int num_regs;
229
230 if (!gc->reglists)
231 return -ENODEV;
232
233 if (cache->is_valid) {
234 *size = cache->size;
235 return cache->status;
236 }
237
238 num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
239 if (!num_regs) {
240 guc_capture_warn_with_list_info(i915, "Missing register
list size",
241 owner, type, classid);
242 return -ENODATA;
243 }
244
245 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
246 (num_regs * sizeof(struct guc_mmio_reg)));
247
248 return 0;
249 }
250
251 int
> 252 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type,
> u32 classid,
253void **listptr)
254 {
255 struct __guc_state_capture_priv *gc = guc->capture.priv;
256 struct __guc_capture_ads_cache *cache =
&gc->ads_cache[owner][type][classid];
257 struct guc_debug_capture_list *listnode;
258 u8 *caplist, *tmp;
259 size_t size = 0;
260 int ret, num_regs;
261
262 if (!gc->reglists)
263 return -ENODEV;
264
265 if (cache->is_valid) {
266 *listptr = cache->list;
267 return cache->status;
268 }
269
270 ret = intel_guc_capture_getlistsize(guc, owner, type, classid,
&size);
271 if (ret) {
272 cache->list = NULL;
273
Re: [Intel-gfx] [PATCH v6 01/13] drm/i915/guc: Update GuC ADS size for error capture lists
Hi Alan,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm/drm-next next-20220225]
[cannot apply to drm-tip/drm-tip drm-exynos/exynos-drm-next
tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Alan-Previn/Add-GuC-Error-Capture-Support/20220226-135414
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a005
(https://download.01.org/0day-ci/archive/20220226/202202261716.sl8xnkv3-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/4c1018d0e536adbe13cf0b71049b0a94073eec7e
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Alan-Previn/Add-GuC-Error-Capture-Support/20220226-135414
git checkout 4c1018d0e536adbe13cf0b71049b0a94073eec7e
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:222:1: warning: no previous
>> prototype for function 'intel_guc_capture_getlistsize' [-Wmissing-prototypes]
intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type,
u32 classid,
^
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:221:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
int
^
static
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:252:1: warning: no previous
>> prototype for function 'intel_guc_capture_getlist' [-Wmissing-prototypes]
intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32
classid,
^
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:251:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
int
^
static
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:321:6: warning: no previous
>> prototype for function 'intel_guc_capture_destroy' [-Wmissing-prototypes]
void intel_guc_capture_destroy(struct intel_guc *guc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:321:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
void intel_guc_capture_destroy(struct intel_guc *guc)
^
static
>> drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:332:5: warning: no previous
>> prototype for function 'intel_guc_capture_init' [-Wmissing-prototypes]
int intel_guc_capture_init(struct intel_guc *guc)
^
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:332:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
int intel_guc_capture_init(struct intel_guc *guc)
^
static
4 warnings generated.
vim +/intel_guc_capture_getlistsize +222
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
220
221 int
> 222 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32
> type, u32 classid,
223size_t *size)
224 {
225 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
226 struct __guc_state_capture_priv *gc = guc->capture.priv;
227 struct __guc_capture_ads_cache *cache =
&gc->ads_cache[owner][type][classid];
228 int num_regs;
229
230 if (!gc->reglists)
231 return -ENODEV;
232
233 if (cache->is_valid) {
234 *size = cache->size;
235 return cache->status;
236 }
237
238 num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
239 if (!num_regs) {
240 guc_capture_warn_with_list_info(i915, "Missing register
list size",
241 owner, type, classid);
242 return -ENODATA;
243 }
244
245 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +
246 (num_regs * sizeof(struct
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
== Series Details == Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5) URL : https://patchwork.freedesktop.org/series/100633/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
== Series Details ==
Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
URL : https://patchwork.freedesktop.org/series/100633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11291 -> Patchwork_22427
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/index.html
Participating hosts (40 -> 41)
--
Additional (2): bat-jsl-2 fi-pnv-d510
Missing(1): fi-bsw-cyan
Known issues
Here are the changes found in Patchwork_22427 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-fd-close:
- fi-bdw-gvtdvm: [PASS][1] -> [INCOMPLETE][2] ([i915#2295])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-bdw-gvtdvm/igt@gem_ba...@create-fd-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/fi-bdw-gvtdvm/igt@gem_ba...@create-fd-close.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/fi-pnv-d510/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][4] ([i915#2867]) -> [PASS][5] +17
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/fi-tgl-dsi/igt@i915_selftest@l...@perf.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][6] ([i915#3576]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-adlp-6/igt@kms_busy@ba...@modeset.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/bat-adlp-6/igt@kms_busy@ba...@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11291 -> Patchwork_22427
CI-20190529: 20190529
CI_DRM_11291: 1e3f898ee67cb2fd8c58799ae8a094f73054c8b9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6359: 57049558c452272b27eeb099fac07e55a924bbf9 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22427: 3896173b2d38d6de2a00a94187209d38bbf1d6c4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3896173b2d38 drm/i915/psr: Set "SF Partial Frame Enable" also on full update
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/index.html
[Intel-gfx] [PATCH v7 00/13] Add GuC Error Capture Support
This series: 1. Enables support of GuC to report error-state-capture using a list of MMIO registers the driver registers and GuC will dump, log and notify right before a GuC triggered engine-reset event. 2. Updates the ADS blob creation to register said lists of global, engine class and engine instance registers with GuC. 3. Defines tables of register lists that are global or engine class or engine instance in scope. 4. Updates usage and buffer-state data for the regions of the shared GuC log-buffer to accomdate both the existing relay logging of general debug logs along with the new error state capture usage. 5. Using a pool of preallocated memory, provide ability to extract and format the GuC reported register-capture data into chunks consistent with existing i915 error- state collection flows and structures. 6. Connects the i915_gpu_coredump reporting function to the GuC error capture module to print all GuC error state capture dumps that is reported. This is the 7th rev of this series with the first 3 revs labelled as RFC. Prior receipts of rvb's: - Patch #5, #12 have received R-v-b's from Umesh Nerlige Ramappa - Patch #6 has received an R-v-b from Matthew Brost Changes from prior revs: v7: - Rebased on lastest drm_tip that has the ADS now using shmem based ads_blob_write utilities. Stress test was performed with this patch included to fix a legacy bug: https://patchwork.freedesktop.org/series/100768/ v6: - In patch #1, ADS reg-list population, we now alloc regular memory to create the lists and cache them for simpler and faster use by GuC ADS module at init, suspend-resume and reset cycles. This was in response to review comments from Lucas De Marchi that also wanted to ensure the GuC ADS module owns the final copying into the ADS phyical memory. - Thanks to Jani Nikula for pointing out that patch #2 and #3 should ensure static tables as constant and dynamic lists should be allocated and cached but attached to the GT level for the case of multiple cards with different fusings for steered registers. These are addressed now along with multiple code style fixups (thanks to review comment from Umesh) and splitting the steered register list generation as a seperate patch. - The extraction functionality, Patch #10 and #11 (was patch #7), has fixed all of Umesh's review comments related to the code styling. Additionally, it was discovered during stress tests that the extraction function could be called by the ct processing thread at the same time as the start of a GT reset event. Thus, a redesign was done whereby the linked list of processed capture-output-nodes are allocated up front and reused throughout the driver's life to ensure no memory locks are taken during extraction. - For patch #6 (now 7, 8 and 9), updates to intel_guc_log was split into smaller chunks and the log_state structure was returned back to inside of the intel_guc_log struct as opposed to the intel_guc struct in prior rev. This is in response to review comments by Matt Brost. - #Patch 13 (previously #10) is mostly identical but addresses all of the code styling comments reviews from Umesh. v5: - Added Gen9->Gen11 register list for CI coverage that included Gen9 with GuC submission. - Redesigned the extraction of the GuC error-capture dumps by grouping them into complete per-engine-reset nodes. Complete here means each node includes the global, engine-class and engine-instance register lists in a single structure. - Extraction is decoupled from the print-out. We now do the extraction immediately when receiving the G2H for error-capture notification. A link list of nodes is maintained with a FIFO based threshold while awaiting retrieval from i915_gpu_coredump's capture_engine function. - Added new plumbing through the i915_gpu_coredump allocation and capture functions to include a flag that is used indicate that GuC had triggered the reset. This new plumbing guarantees an exact match from i915_gpu_coredump's per-engine vma recording and node-retrieval from the guc-error-capture. - Broke the coredump gt_global capture and recording functions into smaller subsets so we can reuse as much of the existing legacy register reading + printing functions and only rely on GuC error-capture for the smaller subset of registers that are tied to engine workload execution. - Updated the register list to follow the legacy execlist format of printout. v4:
[Intel-gfx] [PATCH v7 03/13] drm/i915/guc: Add XE_LP steered register lists support
Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 9 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 175 --
2 files changed, 173 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 858f85478636..27b89539d0d5 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -51,6 +51,7 @@ struct __guc_mmio_reg_descr_group {
u32 owner; /* see enum guc_capture_owner */
u32 type; /* see enum guc_capture_type */
u32 engine; /* as per MAX_ENGINE_CLASS */
+ struct __guc_mmio_reg_descr *extlist; /* only used for steered
registers */
};
/**
@@ -78,6 +79,14 @@ struct __guc_state_capture_priv {
*/
const struct __guc_mmio_reg_descr_group *reglists;
+ /**
+* @extlists: allocated table of steered register lists used for
error-capture state.
+*
+* NOTE: steered registers have multiple instances depending on the HW
configuration
+* (slices or dual-sub-slices) and thus depends on HW fuses discovered
at startup
+*/
+ struct __guc_mmio_reg_descr_group *extlists;
+
/**
* @ads_cache: cached register lists that is ADS format ready
*/
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index fb3ca734ef97..6370943ea300 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -133,6 +133,7 @@ static const struct __guc_mmio_reg_descr empty_regs_list[]
= {
TO_GCAP_DEF_OWNER(regsowner), \
TO_GCAP_DEF_TYPE(regstype), \
class, \
+ NULL, \
}
/* List of lists */
@@ -150,28 +151,33 @@ static const struct __guc_mmio_reg_descr_group
xe_lpd_lists[] = {
};
static const struct __guc_mmio_reg_descr_group *
-guc_capture_get_device_reglist(struct intel_guc *guc)
+guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists,
+u32 owner, u32 type, u32 id)
{
- struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ int i;
- if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915) ||
- IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
- return xe_lpd_lists;
+ if (!reglists)
+ return NULL;
+
+ for (i = 0; reglists[i].list; ++i) {
+ if (reglists[i].owner == owner && reglists[i].type == type &&
+ (reglists[i].engine == id || reglists[i].type ==
GUC_CAPTURE_LIST_TYPE_GLOBAL))
+ return ®lists[i];
}
return NULL;
}
-static const struct __guc_mmio_reg_descr_group *
-guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists,
-u32 owner, u32 type, u32 id)
+static struct __guc_mmio_reg_descr_group *
+guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists,
+u32 owner, u32 type, u32 id)
{
int i;
if (!reglists)
return NULL;
- for (i = 0; reglists[i].list; ++i) {
+ for (i = 0; reglists[i].extlist; ++i) {
if (reglists[i].owner == owner && reglists[i].type == type &&
(reglists[i].engine == id || reglists[i].type ==
GUC_CAPTURE_LIST_TYPE_GLOBAL))
return ®lists[i];
@@ -180,6 +186,127 @@ guc_capture_get_one_list(const struct
__guc_mmio_reg_descr_group *reglists,
return NULL;
}
+static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group
*reglists)
+{
+ int i = 0;
+
+ if (!reglists)
+ return;
+
+ while (reglists[i].extlist)
+ kfree(reglists[i++].extlist);
+}
+
+struct __ext_steer_reg {
+ const char *name;
+ i915_reg_t reg;
+};
+
+static const struct __ext_steer_reg xe_extregs[] = {
+ {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
+ {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
+};
+
+static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
+ const struct __ext_steer_reg *extlist,
+ int slice_id, int subslice_id)
+{
+ ext->reg = extlist->reg;
+ ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id);
+ ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id);
+ ext->regname = extlist->name;
+}
+
+static int
+__alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist,
+const struct __guc_mmio_reg_descr_group *rootlist, int
num_regs)
+{
+ struct __guc_mmio_reg_descr *list;
+
+ list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr),
GFP_KERNEL);
+ if (!list)
[Intel-gfx] [PATCH v7 06/13] drm/i915/guc: Add GuC's error state capture output structures.
Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.
Signed-off-by: Alan Previn
Reviewed-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 27b89539d0d5..d5cb7d5d4ca7 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -54,6 +54,53 @@ struct __guc_mmio_reg_descr_group {
struct __guc_mmio_reg_descr *extlist; /* only used for steered
registers */
};
+/**
+ * struct guc_state_capture_header_t / struct guc_state_capture_t /
+ * guc_state_capture_group_header_t / guc_state_capture_group_t
+ *
+ * Prior to resetting engines that have hung or faulted, GuC microkernel
+ * reports the engine error-state (register values that was read) by
+ * logging them into the shared GuC log buffer using these hierarchy
+ * of structures.
+ */
+struct guc_state_capture_header_t {
+ u32 owner;
+#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
+ u32 info;
+#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
+#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
+#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
+ u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0
*/
+ u32 guc_id; /* if type-instance, context index of hung context, else
set to ~0 */
+ u32 num_mmios;
+#define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
+} __packed;
+
+struct guc_state_capture_t {
+ struct guc_state_capture_header_t header;
+ struct guc_mmio_reg mmio_entries[0];
+} __packed;
+
+enum guc_capture_group_types {
+ GUC_STATE_CAPTURE_GROUP_TYPE_FULL,
+ GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL,
+ GUC_STATE_CAPTURE_GROUP_TYPE_MAX,
+};
+
+struct guc_state_capture_group_header_t {
+ u32 owner;
+#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
+ u32 info;
+#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
+#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
+} __packed;
+
+/* this is the top level structure where an error-capture dump starts */
+struct guc_state_capture_group_t {
+ struct guc_state_capture_group_header_t grp_header;
+ struct guc_state_capture_t capture_entries[0];
+} __packed;
+
/**
* struct __guc_capture_ads_cache
*
--
2.25.1
[Intel-gfx] [PATCH v7 05/13] drm/i915/guc: Add Gen9 registers for GuC error state capture.
Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
1 file changed, 59 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index c8441ca1566b..eb22f979d720 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -22,15 +22,24 @@
* NOTE1: For engine-registers, GuC only needs the register offsets
*from the engine-mmio-base
*/
+#define COMMON_BASE_GLOBAL() \
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}
+
+#define COMMON_GEN9BASE_GLOBAL() \
+ {GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0"}, \
+ {GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1"}, \
+ {ERROR_GEN6, 0, 0, "ERROR_GEN6"}, \
+ {DONE_REG, 0, 0, "DONE_REG"}, \
+ {HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN"}
+
#define COMMON_GEN12BASE_GLOBAL() \
{GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
{GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
- {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}, \
{GEN12_AUX_ERR_DBG,0, 0, "AUX_ERR_DBG"}, \
{GEN12_GAM_DONE, 0, 0, "GAM_DONE"}, \
{GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG"}
-#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+#define COMMON_BASE_ENGINE_INSTANCE() \
{RING_PSMI_CTL(0), 0, 0, "RC PSMI"}, \
{RING_ESR(0), 0, 0, "ESR"}, \
{RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW"}, \
@@ -64,11 +73,13 @@
{GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW"}, \
{GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW"}
-#define COMMON_GEN12BASE_HAS_EU() \
+#define COMMON_BASE_HAS_EU() \
{EIR, 0, 0, "EIR"}
+#define COMMON_BASE_RENDER() \
+ {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}
+
#define COMMON_GEN12BASE_RENDER() \
- {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
{GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
{GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
@@ -80,28 +91,26 @@
/* XE_LPD - Global */
static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
+ COMMON_BASE_GLOBAL(),
+ COMMON_GEN9BASE_GLOBAL(),
COMMON_GEN12BASE_GLOBAL(),
};
/* XE_LPD - Render / Compute Per-Class */
static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
- COMMON_GEN12BASE_HAS_EU(),
+ COMMON_BASE_HAS_EU(),
+ COMMON_BASE_RENDER(),
COMMON_GEN12BASE_RENDER(),
};
-/* XE_LPD - Render / Compute Per-Engine-Instance */
+/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
- COMMON_GEN12BASE_ENGINE_INSTANCE(),
+ COMMON_BASE_ENGINE_INSTANCE(),
};
-/* XE_LPD - Media Decode/Encode Per-Class */
-static const struct __guc_mmio_reg_descr xe_lpd_vd_class_regs[] = {
- COMMON_GEN12BASE_ENGINE_INSTANCE(),
-};
-
-/* XE_LPD - Media Decode/Encode Per-Engine-Instance */
+/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {
- COMMON_GEN12BASE_ENGINE_INSTANCE(),
+ COMMON_BASE_ENGINE_INSTANCE(),
};
/* XE_LPD - Video Enhancement Per-Class */
@@ -109,18 +118,33 @@ static const struct __guc_mmio_reg_descr
xe_lpd_vec_class_regs[] = {
COMMON_GEN12BASE_VEC(),
};
-/* XE_LPD - Video Enhancement Per-Engine-Instance */
+/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {
- COMMON_GEN12BASE_ENGINE_INSTANCE(),
+ COMMON_BASE_ENGINE_INSTANCE(),
};
-/* XE_LPD - Blitter Per-Engine-Instance */
+/* GEN9/XE_LPD - Blitter Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
- COMMON_GEN12BASE_ENGINE_INSTANCE(),
+ COMMON_BASE_ENGINE_INSTANCE(),
};
-/* XE_LPD - Blitter Per-Class */
-/* XE_LPD - Media Decode/Encode Per-Class */
+/* GEN9 - Global */
+static const struct __guc_mmio_reg_descr default_global_regs[] = {
+ COMMON_BASE_GLOBAL(),
+ COMMON_GEN9BASE_GLOBAL(),
+};
+
+static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
+ COMMON_BASE_HAS_EU(),
+ COMMON_BASE_RENDER(),
+};
+
+/*
+ * Empty lists:
+ * GEN9/XE_LPD - Blitter Per-Class
+ * GEN9/XE_LPD - Media Decode/Encode Per-Class
+ * GEN9 - VEC Class
+ */
static const struct __guc_mmio_reg_descr empty_regs_list[] = {
};
@@ -137,6 +161,19 @@ static const struct __guc_mmio_reg_d
[Intel-gfx] [PATCH v7 07/13] drm/i915/guc: Update GuC-log relay function names
For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 35 --
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index b53f61f3101f..bf3abb7e69b0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -11,7 +11,7 @@
#include "i915_memcpy.h"
#include "intel_guc_log.h"
-static void guc_log_capture_logs(struct intel_guc_log *log);
+static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log);
/**
* DOC: GuC firmware log
@@ -197,7 +197,7 @@ static unsigned int guc_get_log_buffer_size(enum
guc_log_buffer_type type)
return 0;
}
-static void guc_read_update_log_buffer(struct intel_guc_log *log)
+static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy,
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
@@ -222,7 +222,7 @@ static void guc_read_update_log_buffer(struct intel_guc_log
*log)
* Used rate limited to avoid deluge of messages, logs might be
* getting consumed by User at a slow rate.
*/
- DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+ DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
log->relay.full_count++;
goto out_unlock;
@@ -300,15 +300,15 @@ static void guc_read_update_log_buffer(struct
intel_guc_log *log)
mutex_unlock(&log->relay.lock);
}
-static void capture_logs_work(struct work_struct *work)
+static void copy_debug_logs_work(struct work_struct *work)
{
struct intel_guc_log *log =
container_of(work, struct intel_guc_log, relay.flush_work);
- guc_log_capture_logs(log);
+ guc_log_copy_debuglogs_for_relay(log);
}
-static int guc_log_map(struct intel_guc_log *log)
+static int guc_log_relay_map(struct intel_guc_log *log)
{
void *vaddr;
@@ -331,7 +331,7 @@ static int guc_log_map(struct intel_guc_log *log)
return 0;
}
-static void guc_log_unmap(struct intel_guc_log *log)
+static void guc_log_relay_unmap(struct intel_guc_log *log)
{
lockdep_assert_held(&log->relay.lock);
@@ -342,7 +342,7 @@ static void guc_log_unmap(struct intel_guc_log *log)
void intel_guc_log_init_early(struct intel_guc_log *log)
{
mutex_init(&log->relay.lock);
- INIT_WORK(&log->relay.flush_work, capture_logs_work);
+ INIT_WORK(&log->relay.flush_work, copy_debug_logs_work);
log->relay.started = false;
}
@@ -357,8 +357,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
lockdep_assert_held(&log->relay.lock);
GEM_BUG_ON(!log->vma);
-/* Keep the size of sub buffers same as shared log buffer */
- subbuf_size = log->vma->size;
+/*
+ * Keep the size of sub buffers same as shared log buffer
+ * but GuC log-events excludes the error-state-capture logs
+ */
+ subbuf_size = log->vma->size - CAPTURE_BUFFER_SIZE;
/*
* Store up to 8 snapshots, which is large enough to buffer sufficient
@@ -393,13 +396,13 @@ static void guc_log_relay_destroy(struct intel_guc_log
*log)
log->relay.channel = NULL;
}
-static void guc_log_capture_logs(struct intel_guc_log *log)
+static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
- guc_read_update_log_buffer(log);
+ _guc_log_copy_debuglogs_for_relay(log);
/*
* Generally device is expected to be active only at this
@@ -565,7 +568,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
if (ret)
goto out_unlock;
- ret = guc_log_map(log);
+ ret = guc_log_relay_map(log);
if (ret)
goto out_relay;
@@ -615,8 +618,8 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
with_intel_runtime_pm(guc_to_gt(guc)->uncore->rpm, wakeref)
guc_action_flush_log(guc);
- /* GuC would have updated log buffer by now, so capture it */
- guc_log_capture_logs(log);
+ /* GuC would have updated log buffer by now, so copy it */
+ guc_log_copy_debuglogs_for_relay(log);
}
/*
@@ -645,7 +648,7 @@ void intel_guc_log_relay_close(struct intel_guc_log *log)
mutex_lock(&log->relay.lock);
GEM_BUG_ON(!intel_guc_log_relay_created(log));
- guc_log_unmap(log);
+ guc_l
[Intel-gfx] [PATCH v7 08/13] drm/i915/guc: Add capture region into intel_guc_log
GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.
Since the error-capture region is accessed at non-deterministic
times (as part of GuC triggered context reset) while debug-log-
events region is accessed as part of relay logging or during
debugfs triggered dumps, move the mapping and unmapping of the
shared buffer into intel_guc_log_create and intel_guc_log_destroy
so that it's always mapped throughout life of GuC operation.
Additionally, while here, update the guc log region layout
diagram to follow the order according to the enum definition
as per the GuC interface.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 58 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h | 3 +-
2 files changed, 36 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index bf3abb7e69b0..2cc52f1eedf3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -25,7 +25,8 @@ static void guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log);
static int guc_action_flush_log_complete(struct intel_guc *guc)
{
u32 action[] = {
- INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
+ INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE,
+ GUC_DEBUG_LOG_BUFFER
};
return intel_guc_send(guc, action, ARRAY_SIZE(action));
@@ -136,7 +137,7 @@ static void guc_move_to_next_buf(struct intel_guc_log *log)
smp_wmb();
/* All data has been written, so now move the offset of sub buffer. */
- relay_reserve(log->relay.channel, log->vma->obj->base.size);
+ relay_reserve(log->relay.channel, log->vma->obj->base.size -
CAPTURE_BUFFER_SIZE);
/* Switch to the next sub buffer */
relay_flush(log->relay.channel);
@@ -212,7 +213,7 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
goto out_unlock;
/* Get the pointer to shared GuC log buffer */
- log_buf_state = src_data = log->relay.buf_addr;
+ log_buf_state = src_data = log->buf_addr;
/* Get the pointer to local buffer to store the logs */
log_buf_snapshot_state = dst_data = guc_get_write_buffer(log);
@@ -232,7 +233,8 @@ static void _guc_log_copy_debuglogs_for_relay(struct
intel_guc_log *log)
src_data += PAGE_SIZE;
dst_data += PAGE_SIZE;
- for (type = GUC_DEBUG_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+ /* For relay logging, we exclude error state capture */
+ for (type = GUC_DEBUG_LOG_BUFFER; type <= GUC_CRASH_DUMP_LOG_BUFFER;
type++) {
/*
* Make a copy of the state structure, inside GuC log buffer
* (which is uncached mapped), on the stack to avoid reading
@@ -310,23 +312,17 @@ static void copy_debug_logs_work(struct work_struct *work)
static int guc_log_relay_map(struct intel_guc_log *log)
{
- void *vaddr;
-
lockdep_assert_held(&log->relay.lock);
- if (!log->vma)
+ if (!log->vma || !log->buf_addr)
return -ENODEV;
/*
-* Create a WC (Uncached for read) vmalloc mapping of log
-* buffer pages, so that we can directly get the data
-* (up-to-date) from memory.
+* WC vmalloc mapping of log buffer pages was done at
+* GuC Log Init time, but lets keep a ref for book-keeping
*/
- vaddr = i915_gem_object_pin_map_unlocked(log->vma->obj, I915_MAP_WC);
- if (IS_ERR(vaddr))
- return PTR_ERR(vaddr);
-
- log->relay.buf_addr = vaddr;
+ i915_gem_object_get(log->vma->obj);
+ log->relay.buf_in_use = true;
return 0;
}
@@ -335,8 +331,8 @@ static void guc_log_relay_unmap(struct intel_guc_log *log)
{
lockdep_assert_held(&log->relay.lock);
- i915_gem_object_unpin_map(log->vma->obj);
- log->relay.buf_addr = NULL;
+ i915_gem_object_put(log->vma->obj);
+ log->relay.buf_in_use = false;
}
void intel_guc_log_init_early(struct intel_guc_log *log)
@@ -442,6 +438,7 @@ int intel_guc_log_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
struct i915_vma *vma;
+ void *vaddr;
u32 guc_log_size;
int ret;
@@ -449,20 +446,21 @@ int intel_guc_log_create(struct intel_guc_log *log)
/*
* GuC Log buffer Layout
+* (this ordering must follow "enum guc_log_buffer_type" definition)
*
* +===+ 00B
-* |Crash dump state header|
-* +---+ 32B
* | Debug state header |
+* +--
[Intel-gfx] [PATCH v7 01/13] drm/i915/guc: Update GuC ADS size for error capture lists
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Also, populate the lists of registers we want GuC to report back to
Host on engine reset events. This list should include global,
engine-class and engine-instance registers for every engine-class
type on the current hardware.
NOTE: Start with a sample table of register lists to layout the
framework before adding real registers in subsequent patch.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 89 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 13 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 132 ++-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 352 ++
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 22 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 8 +
8 files changed, 611 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9d588d936e3d..547adc36d4e9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -184,6 +184,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_uc_fw.o \
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
+ gt/uc/intel_guc_capture.o \
gt/uc/intel_guc_ct.o \
gt/uc/intel_guc_debugfs.o \
gt/uc/intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
new file mode 100644
index ..858f85478636
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021-2022 Intel Corporation
+ */
+
+#ifndef _INTEL_GUC_CAPTURE_FWIF_H
+#define _INTEL_GUC_CAPTURE_FWIF_H
+
+#include
+#include "intel_guc_fwif.h"
+
+struct intel_guc;
+struct file;
+
+/**
+ * struct guc_debug_capture_list_header / struct guc_debug_capture_list
+ *
+ * As part of ADS registration, these header structures (followed by
+ * an array of 'struct guc_mmio_reg' entries) are used to register with
+ * GuC microkernel the list of registers we want it to dump out prior
+ * to a engine reset.
+ */
+struct guc_debug_capture_list_header {
+ u32 info;
+#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
+} __packed;
+
+struct guc_debug_capture_list {
+ struct guc_debug_capture_list_header header;
+} __packed;
+
+/**
+ * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
+ *
+ * intel_guc_capture module uses these structures to maintain static
+ * tables (per unique platform) that consists of lists of registers
+ * (offsets, names, flags,...) that are used at the ADS regisration
+ * time as well as during runtime processing and reporting of error-
+ * capture states generated by GuC just prior to engine reset events.
+ */
+struct __guc_mmio_reg_descr {
+ i915_reg_t reg;
+ u32 flags;
+ u32 mask;
+ const char *regname;
+};
+
+struct __guc_mmio_reg_descr_group {
+ const struct __guc_mmio_reg_descr *list;
+ u32 num_regs;
+ u32 owner; /* see enum guc_capture_owner */
+ u32 type; /* see enum guc_capture_type */
+ u32 engine; /* as per MAX_ENGINE_CLASS */
+};
+
+/**
+ * struct __guc_capture_ads_cache
+ *
+ * A structure to cache register lists that were populated and registered
+ * with GuC at startup during ADS registration. This allows much quicker
+ * GuC resets without re-parsing all the tables for the given gt.
+ */
+struct __guc_capture_ads_cache {
+ bool is_valid;
+ struct file *file;
+ size_t size;
+ int status;
+};
+
+/**
+ * struct __guc_state_capture_priv
+ *
+ * Internal context of the intel_guc_capture module.
+ */
+struct __guc_state_capture_priv {
+ /**
+* @reglists: static table of register lists used for error-capture
state.
+*/
+ const struct __guc_mmio_reg_descr_group *reglists;
+
+ /**
+* @ads_cache: cached register lists that is ADS format ready
+*/
+ struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
+ [GUC_CAPTURE_LIST_TYPE_MAX]
+ [GUC_MAX_ENGINE_CLASSES];
+};
+
+#endif /* _INTEL_GUC_CAPTURE_FWIF_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 447a976c9f25..cda7e4bb8bac 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -9,8 +9,9 @@
#include "gt/intel_gt_pm_irq.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc.h"
-#include "intel_guc_slpc.h"
#include "intel_guc_a
[Intel-gfx] [PATCH v7 04/13] drm/i915/guc: Add DG2 registers for GuC error state capture.
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 6370943ea300..c8441ca1566b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -285,20 +285,96 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc
*guc,
guc->capture.priv->extlists = extlists;
}
+static const struct __ext_steer_reg xehpg_extregs[] = {
+ {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
+};
+
+static bool __has_xehpg_extregs(u32 ipver)
+{
+ return (ipver >= IP_VER(12, 55));
+}
+
+static void
+guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
+ const struct __guc_mmio_reg_descr_group
*lists,
+ u32 ipver)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ struct sseu_dev_info *sseu;
+ int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
+ const struct __guc_mmio_reg_descr_group *list;
+ struct __guc_mmio_reg_descr_group *extlists;
+ struct __guc_mmio_reg_descr *extarray;
+
+ /* In XE_LP / HPG we only have render-class steering registers during
error-capture */
+ list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
+ GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
GUC_RENDER_CLASS);
+ /* skip if extlists was previously allocated */
+ if (!list || guc->capture.priv->extlists)
+ return;
+
+ num_steer_regs = ARRAY_SIZE(xe_extregs);
+ if (__has_xehpg_extregs(ipver))
+ num_steer_regs += ARRAY_SIZE(xehpg_extregs);
+
+ sseu = >->info.sseu;
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {
+ num_tot_regs += num_steer_regs;
+ }
+
+ if (!num_tot_regs)
+ return;
+
+ /* allocate an extra for an end marker */
+ extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group),
GFP_KERNEL);
+ if (!extlists)
+ return;
+
+ if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {
+ kfree(extlists);
+ return;
+ }
+
+ extarray = extlists[0].extlist;
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {
+ for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {
+ __fill_ext_reg(extarray, &xe_extregs[i], slice,
subslice);
+ ++extarray;
+ }
+ if (__has_xehpg_extregs(ipver)) {
+ for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {
+ __fill_ext_reg(extarray, &xehpg_extregs[i],
slice, subslice);
+ ++extarray;
+ }
+ }
+ }
+
+ drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
+ guc->capture.priv->extlists = extlists;
+}
+
static const struct __guc_mmio_reg_descr_group *
guc_capture_get_device_reglist(struct intel_guc *guc)
{
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915) ||
- IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
+ IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915) ||
+ IS_DG2(i915) || IS_XEHPSDV(i915)) {
/*
* For certain engine classes, there are slice and subslice
* level registers requiring steering. We allocate and populate
* these at init time based on hw config add it as an extension
* list at the end of the pre-populated render list.
*/
- guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);
+ if (IS_DG2(i915))
+ guc_capture_alloc_steered_lists_xe_hpg(guc,
xe_lpd_lists, IP_VER(12, 55));
+ else if (IS_XEHPSDV(i915))
+ guc_capture_alloc_steered_lists_xe_hpg(guc,
xe_lpd_lists, IP_VER(12, 50));
+ else
+ guc_capture_alloc_steered_lists_xe_lpd(guc,
xe_lpd_lists);
+
return xe_lpd_lists;
}
--
2.25.1
[Intel-gfx] [PATCH v7 13/13] drm/i915/guc: Print the GuC error capture output register list.
Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.
Since GuC could have reported multiple engine register dumps
in a single notification event, parse the captured data
(appearing as a stream of structures) to identify each dump as
a different 'engine-capture-group-output'.
Finally, for each 'engine-capture-group-output' that is found,
verify if the engine register dump corresponds to the
engine_coredump content that was previously populated by the
i915_gpu_coredump function. That function would have copied
the context's vma's including the bacth buffer during the
G2H-context-reset notification that occurred earlier. Perform
this verification check by comparing guc_id, lrca and engine-
instance obtained from the 'engine-capture-group-output' vs a
copy of that same info taken during i915_gpu_coredump. If
they match, then print those vma's as well (such as the batch
buffers).
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 3 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 162 ++
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +-
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 16 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 5 +
8 files changed, 184 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index e855c801ba28..4643745e5d09 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1629,9 +1629,7 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (intel_engine_uses_guc(engine)) {
- /* nothing to print yet */
- } else if (HAS_EXECLISTS(dev_priv)) {
+ if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
struct i915_request * const *port, *rq;
const u32 *hws =
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 908c6b1dd51a..08327294c1e3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -438,6 +438,9 @@ int intel_guc_engine_failure_process_msg(struct intel_guc
*guc,
int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
+struct intel_engine_cs *
+intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
+
void intel_guc_find_hung_context(struct intel_engine_cs *engine);
int intel_guc_global_policies_update(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 621c0b4537a9..2f96bdf2b90f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -746,6 +746,21 @@ int intel_guc_capture_output_min_size_est(struct intel_guc
*guc)
*intel_engine_coredump struct (if the
context and
*engine of the event notification matches
a node
*in the link list).
+ *
+ * User Sysfs / Debugfs
+ *
+ * --> i915_gpu_coredump_copy_to_buffer->
+ * L--> err_print_to_sgl --> err_print_gt
+ *L--> error_print_guc_captures
+ * L--> intel_guc_capture_print_node prints the
+ * register lists values of the attached node
+ * on the error-engine-dump being reported.
+ * L--> i915_reset_error_state ...
-->__i915_gpu_coredump_free
+ *L--> ... cleanup_gt -->
+ * L--> intel_guc_capture_free_node returns the
+ * capture-output-node back to the internal
+ * cachelist for reuse.
+ *
*/
static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
@@ -1346,9 +1361,156 @@ static void __guc_capture_process_output(struct
intel_guc *guc)
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+static const char *
+guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type,
+ u32 class, u32 id, u32 offset, u32 *is_ext)
+{
+ const struct __guc_mmio_reg_descr_group *reglists =
guc->capture.priv->reglists;
+ struct __guc_mmio_reg_descr_group *extlists =
guc->capture.priv->extlists;
+
[Intel-gfx] [PATCH v7 02/13] drm/i915/guc: Add XE_LP static registers for GuC error capture.
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
2 files changed, 97 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 647a118aa3c3..fb3ca734ef97 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -19,43 +19,109 @@
/*
* Define all device tables of GuC error capture register lists
- * NOTE: For engine-registers, GuC only needs the register offsets
- * from the engine-mmio-base
+ * NOTE1: For engine-registers, GuC only needs the register offsets
+ *from the engine-mmio-base
*/
+#define COMMON_GEN12BASE_GLOBAL() \
+ {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
+ {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}, \
+ {GEN12_AUX_ERR_DBG,0, 0, "AUX_ERR_DBG"}, \
+ {GEN12_GAM_DONE, 0, 0, "GAM_DONE"}, \
+ {GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG"}
+
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+ {RING_PSMI_CTL(0), 0, 0, "RC PSMI"}, \
+ {RING_ESR(0), 0, 0, "ESR"}, \
+ {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW"}, \
+ {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW"}, \
+ {RING_IPEIR(0),0, 0, "IPEIR"}, \
+ {RING_IPEHR(0),0, 0, "IPEHR"}, \
+ {RING_INSTPS(0), 0, 0, "INSTPS"}, \
+ {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
+ {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
+ {RING_BBSTATE(0), 0, 0, "BB_STATE"}, \
+ {CCID(0), 0, 0, "CCID"}, \
+ {RING_ACTHD(0),0, 0, "ACTHD_LDW"}, \
+ {RING_ACTHD_UDW(0),0, 0, "ACTHD_UDW"}, \
+ {RING_INSTPM(0), 0, 0, "INSTPM"}, \
+ {RING_INSTDONE(0), 0, 0, "INSTDONE"}, \
+ {RING_NOPID(0),0, 0, "RING_NOPID"}, \
+ {RING_START(0),0, 0, "START"}, \
+ {RING_HEAD(0), 0, 0, "HEAD"}, \
+ {RING_TAIL(0), 0, 0, "TAIL"}, \
+ {RING_CTL(0), 0, 0, "CTL"}, \
+ {RING_MI_MODE(0), 0, 0, "MODE"}, \
+ {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
+ {RING_HWS_PGA(0), 0, 0, "HWS"}, \
+ {RING_MODE_GEN7(0),0, 0, "GFX_MODE"}, \
+ {GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW"}
+
+#define COMMON_GEN12BASE_HAS_EU() \
+ {EIR, 0, 0, "EIR"}
+
+#define COMMON_GEN12BASE_RENDER() \
+ {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
+ {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
+ {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
+
+#define COMMON_GEN12BASE_VEC() \
+ {GEN12_SFC_DONE(0),0, 0, "SFC_DONE[0]"}, \
+ {GEN12_SFC_DONE(1),0, 0, "SFC_DONE[1]"}, \
+ {GEN12_SFC_DONE(2),0, 0, "SFC_DONE[2]"}, \
+ {GEN12_SFC_DONE(3),0, 0, "SFC_DONE[3]"}
+
/* XE_LPD - Global */
static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
- {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
+ COMMON_GEN12BASE_GLOBAL(),
};
/* XE_LPD - Render / Compute Per-Class */
static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
- {EIR, 0, 0, "EIR"}
+ COMMON_GEN12BASE_HAS_EU(),
+ COMMON_GEN12BASE_RENDER(),
};
/* XE_LPD - Render / Compute Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
- {RING_HEAD(0), 0, 0, "RING_HEAD"},
- {RING_TAIL(0), 0, 0, "RING_TAIL"},
+ COMMON_GEN12BASE_ENGINE_INSTANCE(),
};
/* XE_LPD - Media Decode/Encode Per-Class */
static const struct __guc_mmio_reg_descr xe_lpd_vd_class_regs[] = {
+ COMMON_GEN12BASE_ENGINE_INSTANCE(),
};
/* XE_LPD - Media Decode/Encode Per-Engine-Instance */
static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_reg
[Intel-gfx] [PATCH v7 09/13] drm/i915/guc: Check sizing of guc_capture output
Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 47 +++
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 7 ++-
3 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index eb22f979d720..ed78995bcc35 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -644,6 +644,53 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32
owner, u32 type, u32 classi
return 0;
}
+#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3
+int intel_guc_capture_output_min_size_est(struct intel_guc *guc)
+{
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int worst_min_size = 0, num_regs = 0;
+ size_t tmp = 0;
+
+ /*
+* If every single engine-instance suffered a failure in quick
succession but
+* were all unrelated, then a burst of multiple error-capture events
would dump
+* registers for every one engine instance, one at a time. In this
case, GuC
+* would even dump the global-registers repeatedly.
+*
+* For each engine instance, there would be 1 x
guc_state_capture_group_t output
+* followed by 3 x guc_state_capture_t lists. The latter is how the
register
+* dumps are split across different register types (where the '3' are
global vs class
+* vs instance). Finally, let's multiply the whole thing by 3x (just so
we are
+* not limited to just 1 round of data in a worst case full register
dump log)
+*
+* NOTE: intel_guc_log that allocates the log buffer would round this
size up to
+* a power of two.
+*/
+
+ for_each_engine(engine, gt, id) {
+ worst_min_size += sizeof(struct
guc_state_capture_group_header_t) +
+ (3 * sizeof(struct
guc_state_capture_header_t));
+
+ if (!intel_guc_capture_getlistsize(guc, 0,
GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp))
+ num_regs += tmp;
+
+ if (!intel_guc_capture_getlistsize(guc, 0,
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
+ engine->class, &tmp)) {
+ num_regs += tmp;
+ }
+ if (!intel_guc_capture_getlistsize(guc, 0,
GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
+ engine->class, &tmp)) {
+ num_regs += tmp;
+ }
+ }
+
+ worst_min_size += (num_regs * sizeof(struct guc_mmio_reg));
+
+ return (worst_min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER);
+}
+
static void
guc_capture_free_ads_cache(struct __guc_state_capture_priv *gc)
{
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
index f05365239a2f..24a11f33f7d9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
@@ -12,6 +12,7 @@ struct file;
struct guc_gt_system_info;
struct intel_guc;
+int intel_guc_capture_output_min_size_est(struct intel_guc *guc);
int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32
classid,
struct file **fileptr);
int intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type,
u32 classid,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 2cc52f1eedf3..e9a865c2f4cb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -6,10 +6,11 @@
#include
#include "gt/intel_gt.h"
+#include "intel_guc_capture.h"
+#include "intel_guc_log.h"
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
-#include "intel_guc_log.h"
static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log);
@@ -464,6 +465,10 @@ int intel_guc_log_create(struct intel_guc_log *log)
* | Capture logs |
* +===+ + CAPTURE_SIZE
*/
+ if (intel_guc_capture_output_min_size_est(guc) > CAPTURE_BUFFER_SIZE)
+ DRM_WARN("GuC log buffer for state_capture maybe too small. %d
< %d\n",
+CAPTURE_BUFFER_SIZE,
intel_guc_capture_output_min_size_est(guc));
+
guc_log_size = PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
CAPTURE_BUFFER_SIZE;
--
2.25.1
[Intel-gfx] [PATCH v7 10/13] drm/i915/guc: Extract GuC error capture lists on G2H notification.
- Upon the G2H Notify-Err-Capture event, parse through the
GuC Log Buffer (error-capture-subregion) and generate one or
more capture-nodes. A single node represents a single "engine-
instance-capture-dump" and contains at least 3 register lists:
global, engine-class and engine-instance. An internal link
list is maintained to store one or more nodes.
- Because the link-list node generation happen before the call
to i915_gpu_codedump, duplicate global and engine-class register
lists for each engine-instance register dump if we find
dependent-engine resets in a engine-capture-group.
- When i915_gpu_coredump calls into capture_engine, (in a
subsequent patch) we detach the matching node (guc-id,
LRCA, etc) from the link list above and attach it to
i915_gpu_coredump's intel_engine_coredump structure when have
matching LRCA/guc-id/engine-instance.
Additional notes to be aware of:
- GuC generates the error capture dump into the GuC log buffer but
this buffer is one big log buffer with 3 independent subregions
within it. Each subregion is populated with different content
and used in different ways and timings but all regions operate
behave as independent ring buffers. Each guc-log subregion
(general-logs, crash-dump and error- capture) has it's own
guc_log_buffer_state that contain independent read and write
pointers.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 7 +
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 56 ++
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 546 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c| 26 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.h| 4 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +-
7 files changed, 639 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..ae6448fcaf90 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -173,4 +173,11 @@ enum intel_guc_sleep_state_status {
#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
#define GUC_LOG_CONTROL_DEFAULT_LOGGING(1 << 8)
+enum intel_guc_state_capture_event_status {
+ INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,
+ INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,
+};
+
+#define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x00FF
+
#endif /* _ABI_GUC_ACTIONS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index d5cb7d5d4ca7..2b09aa05d8b7 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -12,6 +12,52 @@
struct intel_guc;
struct file;
+/**
+ * struct __guc_capture_bufstate
+ *
+ * Book-keeping structure used to track read and write pointers
+ * as we extract error capture data from the GuC-log-buffer's
+ * error-capture region as a stream of dwords.
+ */
+struct __guc_capture_bufstate {
+ u32 size;
+ void *data;
+ u32 rd;
+ u32 wr;
+};
+
+/**
+ * struct __guc_capture_parsed_output - extracted error capture node
+ *
+ * A single unit of extracted error-capture output data grouped together
+ * at an engine-instance level. We keep these nodes in a linked list.
+ * See outlist below.
+ */
+struct __guc_capture_parsed_output {
+ /*
+* A single set of 3 capture lists: a global-list
+* an engine-class-list and an engine-instance list.
+* outlist in __guc_capture_parsed_output will keep
+* a linked list of these nodes that will eventually
+* be detached from outlist and attached into to
+* i915_gpu_codedump in response to a context reset
+*/
+ struct list_head link;
+ bool is_partial;
+ u32 eng_class;
+ u32 eng_inst;
+ u32 guc_id;
+ u32 lrca;
+ struct gcap_reg_list_info {
+ u32 vfid;
+ u32 num_regs;
+ struct guc_mmio_reg *regs;
+ } reginfo[GUC_CAPTURE_LIST_TYPE_MAX];
+#define GCAP_PARSED_REGLIST_INDEX_GLOBAL BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL)
+#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS
BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS)
+#define GCAP_PARSED_REGLIST_INDEX_ENGINST
BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
+};
+
/**
* struct guc_debug_capture_list_header / struct guc_debug_capture_list
*
@@ -140,6 +186,16 @@ struct __guc_state_capture_priv {
struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
[GUC_CAPTURE_LIST_TYPE_MAX]
[GUC_MAX_ENGINE_CLASSES];
+
+ /**
+* @outlist: allocated nodes with parsed engine-instance error capture
data
+*
+* A linked list of parsed GuC
[Intel-gfx] [PATCH v7 11/13] drm/i915/guc: Pre-allocate output nodes for extraction
In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(&guc->ct.requests.worker) can cause the G2H message
handler to trigger intel_guc_capture_store_snapshot upon
receiving new G2H error-capture notifications. This can happen
despite the prior call to disable_submission(guc);. However,
there's no race-free way for intel_guc_capture_store_snapshot to
know that we are in the midst of a reset. That said, we can never
dynamically allocate the output nodes in this handler. Thus, we
shall pre-allocate a fixed number of empty nodes up front (at the
time of ADS registration) that we can consume from or return to
an internal cached list of nodes.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 19 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 178 ++
2 files changed, 160 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 2b09aa05d8b7..a77a6274e0b0 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -31,7 +31,7 @@ struct __guc_capture_bufstate {
*
* A single unit of extracted error-capture output data grouped together
* at an engine-instance level. We keep these nodes in a linked list.
- * See outlist below.
+ * See cachelist and outlist below.
*/
struct __guc_capture_parsed_output {
/*
@@ -188,7 +188,22 @@ struct __guc_state_capture_priv {
[GUC_MAX_ENGINE_CLASSES];
/**
-* @outlist: allocated nodes with parsed engine-instance error capture
data
+* @cachelist: Pool of pre-allocated nodes for error capture output
+*
+* We need this pool of pre-allocated nodes because we cannot
+* dynamically allocate new nodes when receiving the G2H notification
+* because the event handlers for all G2H event-processing is called
+* by the ct processing worker queue and when that queue is being
+* processed, there is no absoluate guarantee that we are not in the
+* midst of a GT reset operation (which doesn't allow allocations).
+*/
+ struct list_head cachelist;
+#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES *
GUC_MAX_INSTANCES_PER_CLASS)
+#define PREALLOC_NODES_DEFAULT_NUMREGS 64
+ int max_mmio_per_node;
+
+ /**
+* @outlist: Pool of pre-allocated nodes for error capture output
*
* A linked list of parsed GuC error-capture output data before
* reporting with formatting via i915_gpu_coredump. Each node in this
linked list shall
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 9308157d9a74..7bd297515504 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -583,6 +583,8 @@ intel_guc_capture_getlistsize(struct intel_guc *guc, u32
owner, u32 type, u32 cl
return 0;
}
+static void guc_capture_create_prealloc_nodes(struct intel_guc *guc);
+
int
intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32
classid,
struct file **fileoutptr)
@@ -604,6 +606,12 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32
owner, u32 type, u32 classi
return cache->status;
}
+ /*
+* ADS population of input registers is a good
+* time to pre-allocate cachelist output nodes
+*/
+ guc_capture_create_prealloc_nodes(guc);
+
ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size);
if (ret) {
cache->is_valid = true;
@@ -721,7 +729,8 @@ int intel_guc_capture_output_min_size_est(struct intel_guc
*guc)
*err-state-captured register-list we find, we
alloc 'C':
* --> alloc C: A capture-output-node structure that includes misc
capture info along
* with 3 register list dumps (global, engine-class and
engine-instance)
- * This node is dynamically allocated and populated with the
error-capture
+ * This node is created from a pre-allocated list of blank
nodes in
+ * guc->capture->priv->cachelist and populated with the
error-capture
* data from GuC and then it's added into
guc->capture->priv->outlist linked
* list. This list is used for matchup and printout by
i915_gpu_coredump
* and err_print_gt, (when user invokes the error capture
sysfs).
@@ -865,19 +874,20 @@ guc_capture_delete_one_node(struct intel_guc *guc, struct
__guc_capture_parsed_o
}
static void
-guc_
[Intel-gfx] [PATCH v7 12/13] drm/i915/guc: Plumb GuC-capture into gpu_coredump
Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.
Using that flag, ensure all coredump functions that
read or print mmio-register values related to work submission
or command-streamer engines are skipped and replaced with
a calls guc-capture module equivalent functions to retrieve
or print the register dump.
While here, split out display related register reading
and printing into its own function that is called agnostic
to whether GuC had triggered the reset.
For now, introduce an empty printing function that can
filled in on a subsequent patch just to handle formatting.
Signed-off-by: Alan Previn
Reviewed-by: Umesh Nerlige Ramappa
---
.../drm/i915/gt/intel_execlists_submission.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 69 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 10 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 266 --
drivers/gpu/drm/i915/i915_gpu_error.h | 30 +-
8 files changed, 288 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 961d795220a3..fc7c27df5d44 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2231,11 +2231,11 @@ static struct execlists_capture *capture_regs(struct
intel_engine_cs *engine)
if (!cap->error)
goto err_cap;
- cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp);
+ cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp,
CORE_DUMP_FLAG_NONE);
if (!cap->error->gt)
goto err_gpu;
- cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp);
+ cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp,
CORE_DUMP_FLAG_NONE);
if (!cap->error->gt->engine)
goto err_gt;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 82713264b96c..2d120bd391a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1318,7 +1318,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
- i915_capture_error_state(gt, engine_mask);
+ i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_NONE);
intel_gt_clear_error_registers(gt, engine_mask);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 7bd297515504..621c0b4537a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -734,6 +734,18 @@ int intel_guc_capture_output_min_size_est(struct intel_guc
*guc)
* data from GuC and then it's added into
guc->capture->priv->outlist linked
* list. This list is used for matchup and printout by
i915_gpu_coredump
* and err_print_gt, (when user invokes the error capture
sysfs).
+ *
+ * GUC --> notify context reset:
+ * -
+ * --> G2H CONTEXT RESET
+ * L--> guc_handle_context_reset --> i915_capture_error_state
+ * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) -->
gt_record_engines
+ * --> capture_engine(..IS_GUC_CAPTURE)
+ * L--> intel_guc_capture_get_matching_node is
where
+ *detach C from internal linked list and
add it into
+ *intel_engine_coredump struct (if the
context and
+ *engine of the event notification matches
a node
+ *in the link list).
*/
static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
@@ -1332,6 +1344,63 @@ static void __guc_capture_process_output(struct
intel_guc *guc)
__guc_capture_flushlog_complete(guc);
}
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+
+int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf,
+ const struct intel_engine_coredump *ee)
+{
+ return 0;
+}
+
+#endif //CONFIG_DRM_I915_CAPTURE_ERROR
+
+void intel_guc_capture_free_node(struct intel_engine_coredump *ee)
+{
+ if (!ee || !ee->guc_capture_node)
+ return;
+
+ guc_capture_add_node_to_cachelist(ee->capture->priv,
ee->guc_capture_node);
+ ee->capture = NULL;
+ ee->guc_capture_node = NULL;
+}
+
+void intel_guc_capture_ge
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev7)
== Series Details ==
Series: Add GuC Error Capture Support (rev7)
URL : https://patchwork.freedesktop.org/series/97187/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fa51e0f956f6 drm/i915/guc: Update GuC ADS size for error capture lists
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#32:
new file mode 100644
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:595:
+ u32 null_header[2]={0};
^
-:300: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#300: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:632:
+ if (!info_map_read(&info_map, engine_enabled_masks[j]))
{
+
-:468: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible
side-effects?
#468: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:63:
+#define MAKE_REGLIST(regslist, regsowner, regstype, class) \
+ { \
+ regslist, \
+ ARRAY_SIZE(regslist), \
+ TO_GCAP_DEF_OWNER(regsowner), \
+ TO_GCAP_DEF_TYPE(regstype), \
+ class, \
+ }
-:512: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (16, 16)
#512: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:107:
+ if (reglists[i].owner == owner && reglists[i].type == type &&
[...]
+ return ®lists[i];
-:705: WARNING:TYPO_SPELLING: 'cant' may be misspelled - perhaps 'can't'?
#705: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:300:
+ drm_warn(&i915->drm, "GuC-capture: cant create shmem for
caplist = 0x%016lx", PTR_ERR(file));
-:705: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#705: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:300:
+ drm_warn(&i915->drm, "GuC-capture: cant create shmem for
caplist = 0x%016lx", PTR_ERR(file));
total: 1 errors, 4 warnings, 2 checks, 734 lines checked
47efff77442d drm/i915/guc: Add XE_LP static registers for GuC error capture.
-:25: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#25: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:25:
+#define COMMON_GEN12BASE_GLOBAL() \
+ {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
+ {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}, \
+ {GEN12_AUX_ERR_DBG,0, 0, "AUX_ERR_DBG"}, \
+ {GEN12_GAM_DONE, 0, 0, "GAM_DONE"}, \
+ {GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG"}
-:33: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#33: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:33:
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+ {RING_PSMI_CTL(0), 0, 0, "RC PSMI"}, \
+ {RING_ESR(0), 0, 0, "ESR"}, \
+ {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW"}, \
+ {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW"}, \
+ {RING_IPEIR(0),0, 0, "IPEIR"}, \
+ {RING_IPEHR(0),0, 0, "IPEHR"}, \
+ {RING_INSTPS(0), 0, 0, "INSTPS"}, \
+ {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
+ {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
+ {RING_BBSTATE(0), 0, 0, "BB_STATE"}, \
+ {CCID(0), 0, 0, "CCID"}, \
+ {RING_ACTHD(0),0, 0, "ACTHD_LDW"}, \
+ {RING_ACTHD_UDW(0),0, 0, "ACTHD_UDW"}, \
+ {RING_INSTPM(0), 0, 0, "INSTPM"}, \
+ {RING_INSTDONE(0), 0, 0, "INSTDONE"}, \
+ {RING_NOPID(0),0, 0, "RING_NOPID"}, \
+ {RING_START(0),0, 0, "START"}, \
+ {RING_HEAD(0), 0, 0, "HEAD"}, \
+ {RING_TAIL(0), 0, 0, "TAIL"}, \
+ {RING_CTL(0), 0, 0, "CTL"}, \
+ {RING_MI_MODE(0), 0, 0, "MODE"}, \
+ {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
+ {RING_HWS_PGA(0), 0, 0, "HWS"}, \
+ {RING_MODE_GEN7(0),0, 0, "GFX_MODE"}, \
+ {GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW"}
-:70: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#70:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add GuC Error Capture Support (rev7)
== Series Details == Series: Add GuC Error Capture Support (rev7) URL : https://patchwork.freedesktop.org/series/97187/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.BAT: failure for Add GuC Error Capture Support (rev7)
== Series Details ==
Series: Add GuC Error Capture Support (rev7)
URL : https://patchwork.freedesktop.org/series/97187/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11291 -> Patchwork_22428
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22428 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22428, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/index.html
Participating hosts (40 -> 41)
--
Additional (2): bat-jsl-2 fi-pnv-d510
Missing(1): fi-bsw-cyan
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22428:
### IGT changes ###
Possible regressions
* igt@i915_hangman@error-state-basic:
- bat-dg1-5: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-dg1-5/igt@i915_hang...@error-state-basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-dg1-5/igt@i915_hang...@error-state-basic.html
- bat-dg1-6: [PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-dg1-6/igt@i915_hang...@error-state-basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-dg1-6/igt@i915_hang...@error-state-basic.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_hangman@error-state-basic:
- {bat-adlp-6}: [PASS][5] -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-adlp-6/igt@i915_hang...@error-state-basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-adlp-6/igt@i915_hang...@error-state-basic.html
* igt@runner@aborted:
- {bat-dg2-9}:[FAIL][7] ([i915#4312]) -> [FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/bat-dg2-9/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-dg2-9/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_22428 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#4547])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@i915_hangman@error-state-basic:
- fi-kbl-guc: [PASS][10] -> [DMESG-WARN][11] ([i915#1610])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-kbl-guc/igt@i915_hang...@error-state-basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-kbl-guc/igt@i915_hang...@error-state-basic.html
- fi-skl-guc: [PASS][12] -> [DMESG-WARN][13] ([i915#1610])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-skl-guc/igt@i915_hang...@error-state-basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-skl-guc/igt@i915_hang...@error-state-basic.html
- fi-cfl-guc: [PASS][14] -> [DMESG-WARN][15] ([i915#1610])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/fi-cfl-guc/igt@i915_hang...@error-state-basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-cfl-guc/igt@i915_hang...@error-state-basic.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][16] ([fdo#109271]) +57 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-pnv-d510/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][17] ([i915#4312])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-dg1-5/igt@run...@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][18] ([i915#2426] / [i915#4312])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-kbl-guc/igt@run...@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][19] ([i915#2426])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-rkl-guc/igt@run...@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][20] ([i915#4312])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/bat-dg1-6/igt@run...@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][21] ([i915#2426] / [i915#4312])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-cfl-guc/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][22] ([i915#2426] / [i915#4312])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22428/fi-skl-guc/igt@run...@aborted.html
Possible fixes
[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix prime_mmap to work when using LMEM
== Series Details == Series: Fix prime_mmap to work when using LMEM URL : https://patchwork.freedesktop.org/series/100737/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11286_full -> Patchwork_22411_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22411_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22411_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22411_full: ### IGT changes ### Possible regressions * igt@drm_mm@all@color_evict: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-skl4/igt@drm_mm@all@color_evict.html Known issues Here are the changes found in Patchwork_22411_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [FAIL][47], [PASS][48], [PASS][49], [PASS][50], [FAIL][51]) ([i915#4386]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl2/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl3/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl7/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11286/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22411/shard-apl6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/doc: Fix typos and update outdated structure and API names
== Series Details == Series: series starting with [1/3] drm/doc: Fix typos and update outdated structure and API names URL : https://patchwork.freedesktop.org/series/100738/ State : success == Summary == CI Bug Log - changes from CI_DRM_11288_full -> Patchwork_22412_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22412_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [FAIL][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl3/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-apl8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl3/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl3/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl3/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl4/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl4/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl4/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl4/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl2/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl1/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl1/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl1/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl1/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl7/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22412/shard-apl7/boot.html
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev5)
== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev5) URL : https://patchwork.freedesktop.org/series/100136/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11288_full -> Patchwork_22413_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22413_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22413_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22413_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-fds-priority-all: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-kbl1/igt@gem_exec_whis...@basic-fds-priority-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-kbl6/igt@gem_exec_whis...@basic-fds-priority-all.html Known issues Here are the changes found in Patchwork_22413_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-3x: - shard-iclb: NOTRUN -> [SKIP][3] ([i915#1839]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-iclb3/igt@feature_discov...@display-3x.html * igt@gem_create@create-massive: - shard-iclb: NOTRUN -> [DMESG-WARN][4] ([i915#4991]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-iclb3/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [TIMEOUT][6] ([i915#3063] / [i915#3648]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-tglb7/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-tglb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-bb-first: - shard-kbl: NOTRUN -> [DMESG-WARN][7] ([i915#5076]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-kbl6/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_capture@pi@vecs0: - shard-tglb: NOTRUN -> [INCOMPLETE][8] ([i915#1373] / [i915#3371]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-tglb6/igt@gem_exec_capture@p...@vecs0.html - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#3371]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-iclb8/igt@gem_exec_capture@p...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-iclb2/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2846]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-glk1/igt@gem_exec_f...@basic-deadline.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-glk6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-tglb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-kbl6/igt@gem_exec_fair@basic-n...@vecs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-kbl4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: NOTRUN -> [FAIL][19] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-iclb: [PASS][20] -> [DMESG-WARN][21] ([i915#4391]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11288/shard-iclb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22413/shard-iclb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1
Re: [Intel-gfx] [PATCH 5/6] drm/rcar_du: changes to rcar-du driver resulting from drm_writeback_connector structure changes
On Wed, Feb 2, 2022 at 7:41 AM Jani Nikula wrote:
>
> On Wed, 02 Feb 2022, Laurent Pinchart
> wrote:
> > Hi Jani,
> >
> > On Wed, Feb 02, 2022 at 03:15:03PM +0200, Jani Nikula wrote:
> >> On Wed, 02 Feb 2022, Laurent Pinchart wrote:
> >> > On Wed, Feb 02, 2022 at 02:24:28PM +0530, Kandpal Suraj wrote:
> >> >> Changing rcar_du driver to accomadate the change of
> >> >> drm_writeback_connector.base and drm_writeback_connector.encoder
> >> >> to a pointer the reason for which is explained in the
> >> >> Patch(drm: add writeback pointers to drm_connector).
> >> >>
> >> >> Signed-off-by: Kandpal Suraj
> >> >> ---
> >> >> drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 2 ++
> >> >> drivers/gpu/drm/rcar-du/rcar_du_writeback.c | 8 +---
> >> >> 2 files changed, 7 insertions(+), 3 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
> >> >> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
> >> >> index 66e8839db708..68f387a04502 100644
> >> >> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
> >> >> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
> >> >> @@ -72,6 +72,8 @@ struct rcar_du_crtc {
> >> >> const char *const *sources;
> >> >> unsigned int sources_count;
> >> >>
> >> >> + struct drm_connector connector;
> >> >> + struct drm_encoder encoder;
> >> >
> >> > Those fields are, at best, poorly named. Furthermore, there's no need in
> >> > this driver or in other drivers using drm_writeback_connector to create
> >> > an encoder or connector manually. Let's not polute all drivers because
> >> > i915 doesn't have its abstractions right.
> >>
> >> i915 uses the quite common model for struct inheritance:
> >>
> >> struct intel_connector {
> >> struct drm_connector base;
> >> /* ... */
> >> }
> >>
> >> Same with at least amd, ast, fsl-dcu, hisilicon, mga200, msm, nouveau,
> >> radeon, tilcdc, and vboxvideo.
> >>
> >> We could argue about the relative merits of that abstraction, but I
> >> think the bottom line is that it's popular and the drivers using it are
> >> not going to be persuaded to move away from it.
> >
> > Nobody said inheritance is bad.
> >
> >> It's no coincidence that the drivers who've implemented writeback so far
> >> (komeda, mali, rcar-du, vc4, and vkms) do not use the abstraction,
> >> because the drm_writeback_connector midlayer does, forcing the issue.
> >
> > Are you sure it's not a coincidence ? :-)
> >
> > The encoder and especially connector created by drm_writeback_connector
> > are there only because KMS requires a drm_encoder and a drm_connector to
> > be exposed to userspace (and I could argue that using a connector for
> > writeback is a hack, but that won't change). The connector is "virtual",
> > I still fail to see why i915 or any other driver would need to wrap it
> > into something else. The whole point of the drm_writeback_connector
> > abstraction is that drivers do not have to manage the writeback
> > drm_connector manually, they shouldn't touch it at all.
>
> The thing is, drm_writeback_connector_init() calling
> drm_connector_init() on the drm_connector embedded in
> drm_writeback_connector leads to that connector being added to the
> drm_device's list of connectors. Ditto for the encoder.
>
> All the driver code that handles drm_connectors would need to take into
> account they might not be embedded in intel_connector. Throughout the
> driver. Ditto for the encoders.
The assumption that a connector is embedded in intel_connector doesn't
really play that well with how bridge and panel connectors work.. so
in general this seems like a good thing to unwind.
But as a point of practicality, i915 is a large driver covering a lot
of generations of hw with a lot of users. So I can understand
changing this design isn't something that can happen quickly or
easily. IMO we should allow i915 to create it's own connector for
writeback, and just document clearly that this isn't the approach new
drivers should take. I mean, I understand idealism, but sometimes a
dose of pragmatism is needed. :-)
BR,
-R
> The point is, you can't initialize a connector or an encoder for a
> drm_device in isolation of the rest of the driver, even if it were
> supposed to be hidden away.
>
> BR,
> Jani.
>
[Intel-gfx] ✓ Fi.CI.IGT: success for iommu/vt-d: Add RPLS to quirk list to skip TE disabling (rev2)
== Series Details == Series: iommu/vt-d: Add RPLS to quirk list to skip TE disabling (rev2) URL : https://patchwork.freedesktop.org/series/100165/ State : success == Summary == CI Bug Log - changes from CI_DRM_11289_full -> Patchwork_22414_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22414_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@chamelium: - shard-iclb: NOTRUN -> [SKIP][1] ([fdo#111827]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb4/igt@feature_discov...@chamelium.html * igt@feature_discovery@display-3x: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb7/igt@feature_discov...@display-3x.html * igt@gem_create@create-massive: - shard-iclb: NOTRUN -> [DMESG-WARN][3] ([i915#4991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb7/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#4991]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-apl6/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb6/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-tglb1/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-bb-first: - shard-kbl: NOTRUN -> [DMESG-WARN][7] ([i915#5076]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-kbl6/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_capture@pi@vecs0: - shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([i915#1373] / [i915#3371]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb1/igt@gem_exec_capture@p...@vecs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-tglb7/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-glk3/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb7/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_huc_copy@huc-copy: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-kbl7/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb8/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-skl1/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][17] ([i915#2658]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-kbl7/igt@gem_pwr...@basic-exhaustion.html - shard-tglb: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-tglb3/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-protected-buffer: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb7/igt@gem_...@create-protected-buffer.html * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#768]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb6/igt@gem_render_c...@y-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@vma-merge: - shard-iclb: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22414/shard-iclb6/igt@gem_userptr_bl...@vma-merge.html * igt@gen7_exec_parse@basic-offset: - shard-apl:
Re: [Intel-gfx] [PATCH v7 01/13] drm/i915/guc: Update GuC ADS size for error capture lists
On 2/26/2022 1:55 AM, Alan Previn wrote:
-static void guc_capture_list_init(struct intel_guc *guc)
+static int
+guc_capture_prep_lists(struct intel_guc *guc)
{
...
- /* FIXME: Populate a proper capture list */
+ /* first, set aside the first page for a capture_list with zero
descriptors */
+ total_size = PAGE_SIZE;
+ if (!iosys_map_is_null(&guc->ads_map)) {
+ file = shmem_create_from_data("guc-err-cap", null_header,
sizeof(null_header));
Alan: CI caught a bug - above line was triggering memory allocation
i completely forgot ... will fix to match the other ADS err-capture lists
in this function - i.e. intel_guc_capture will allocate on first boot
and cache it.
+ if (!IS_ERR(file)) {
+ shmem_read_to_iosys_map(file, 0, &guc->ads_map,
+ ggtt, sizeof(null_header));
+ fput(file);
+ } else {
+ drm_dbg(&i915->drm, "GuC-capture: failed shmem for nulllist
= 0x%016lx",
+ PTR_ERR(file));
+ }
+ null_ggtt = ggtt;
+ ggtt += PAGE_SIZE;
+ }
[Intel-gfx] ✓ Fi.CI.IGT: success for PCI: vmd: Prevent recursive locking on interrupt allocation
== Series Details == Series: PCI: vmd: Prevent recursive locking on interrupt allocation URL : https://patchwork.freedesktop.org/series/100743/ State : success == Summary == CI Bug Log - changes from CI_DRM_11289_full -> Patchwork_22415_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22415_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [FAIL][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk2/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk3/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk7/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk7/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk7/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk8/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk8/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk8/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk9/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk7/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk6/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk6/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk5/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk5/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22415/shard-glk3/boot.html [44]: https://intel-gfx-ci
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/7] drm/i915: add io_size plumbing
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: add io_size plumbing
URL : https://patchwork.freedesktop.org/series/100746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11289_full -> Patchwork_22416_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22416_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@perf@non-zero-reason:
- {shard-tglu}: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglu-1/igt@p...@non-zero-reason.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-tglu-6/igt@p...@non-zero-reason.html
Known issues
Here are the changes found in Patchwork_22416_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][3] ([fdo#111827])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb5/igt@feature_discov...@chamelium.html
* igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][4] ([i915#1839])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb3/igt@feature_discov...@display-3x.html
* igt@gem_create@create-massive:
- shard-iclb: NOTRUN -> [DMESG-WARN][5] ([i915#4991])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb3/igt@gem_cre...@create-massive.html
- shard-apl: NOTRUN -> [DMESG-WARN][6] ([i915#4991])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-apl8/igt@gem_cre...@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +6 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#232])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb6/igt@gem_...@unwedge-stress.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-tglb3/igt@gem_...@unwedge-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-kbl: NOTRUN -> [DMESG-WARN][11] ([i915#5076])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-kbl3/igt@gem_exec_balan...@parallel-bb-first.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#4547])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-skl7/igt@gem_exec_capture@p...@rcs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-skl7/igt@gem_exec_capture@p...@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb3/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_nop@basic-series:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/igt@gem_exec_...@basic-series.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-glk3/igt@gem_exec_...@basic-series.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109283])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22416/shard-iclb3/igt@gem_exec_par...@rsvd2-dir
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Initialize GuC submission locks and queues early (rev2)
== Series Details == Series: drm/i915/guc: Initialize GuC submission locks and queues early (rev2) URL : https://patchwork.freedesktop.org/series/100138/ State : success == Summary == CI Bug Log - changes from CI_DRM_11289_full -> Patchwork_22417_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22417_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-3x: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@feature_discov...@display-3x.html * igt@gem_create@create-massive: - shard-iclb: NOTRUN -> [DMESG-WARN][2] ([i915#4991]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#4991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-apl2/igt@gem_cre...@create-massive.html * igt@gem_eio@in-flight-1us: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb7/igt@gem_...@in-flight-1us.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-tglb1/igt@gem_...@in-flight-1us.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#232]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb6/igt@gem_...@unwedge-stress.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-tglb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_balancer@parallel-bb-first: - shard-kbl: NOTRUN -> [DMESG-WARN][8] ([i915#5076]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-kbl3/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#4547]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-skl8/igt@gem_exec_capture@p...@rcs0.html - shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([i915#3371]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-iclb1/igt@gem_exec_capture@p...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_capture@pi@vcs0: - shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([i915#3371]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb1/igt@gem_exec_capture@p...@vcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-tglb1/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-glk6/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109283]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-skl1/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-tglb: NOTRUN -> [WARN][21] ([i915#2658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-tglb5/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-protected-buffer: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#4270]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_...@create-protected-buffer.html * igt@gem_render_copy@y-tiled-to-vebox-y-tiled: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#768]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22417/shard-iclb3/igt@gem_render_c...@y-tile
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Fix assert in i915_ggtt_pin
== Series Details == Series: series starting with [1/2] drm/i915: Fix assert in i915_ggtt_pin URL : https://patchwork.freedesktop.org/series/100752/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11289_full -> Patchwork_22418_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22418_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22418_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22418_full: ### IGT changes ### Possible regressions * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - shard-iclb: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@kms_big...@x-tiled-32bpp-rotate-180.html Known issues Here are the changes found in Patchwork_22418_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-3x: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@feature_discov...@display-3x.html * igt@gem_create@create-massive: - shard-iclb: NOTRUN -> [DMESG-WARN][3] ([i915#4991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@gem_cre...@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#4991]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-apl1/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb6/igt@gem_...@unwedge-stress.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-tglb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-skl7/igt@gem_exec_capture@p...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-skl8/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-iclb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11289/shard-glk5/igt@gem_exec_fair@basic-n...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-glk7/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_params@rsvd2-dirt: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109283]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@gem_exec_par...@rsvd2-dirt.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-kbl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-kbl4/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_pwrite@basic-exhaustion: - shard-tglb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-tglb1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-protected-buffer: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#4270]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22418/shard-iclb8/igt@gem_...@create-protected-b
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915/vlv_dsi: Add DMI quirk for wrong panel modeline in BIOS on Asus TF103C (v2)
== Series Details == Series: series starting with [1/5] drm/i915/vlv_dsi: Add DMI quirk for wrong panel modeline in BIOS on Asus TF103C (v2) URL : https://patchwork.freedesktop.org/series/100766/ State : success == Summary == CI Bug Log - changes from CI_DRM_11290_full -> Patchwork_22420_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22420_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [FAIL][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk7/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk8/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk8/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11290/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk5/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22420/shard-glk3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_
[Intel-gfx] ✓ Fi.CI.IGT: success for Fix i915 error_state_read ptr use (rev2)
== Series Details == Series: Fix i915 error_state_read ptr use (rev2) URL : https://patchwork.freedesktop.org/series/100768/ State : success == Summary == CI Bug Log - changes from CI_DRM_11291_full -> Patchwork_22425_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22425_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([FAIL][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk7/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk8/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk5/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk8/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk7/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk7/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk6/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk6/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk6/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk5/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk5/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk5/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22425/shard-glk3/boot.html [44]: https://intel-gfx-ci.01.org/tree/dr
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5)
== Series Details == Series: drm/i915/psr: Set "SF Partial Frame Enable" also on full update (rev5) URL : https://patchwork.freedesktop.org/series/100633/ State : success == Summary == CI Bug Log - changes from CI_DRM_11291_full -> Patchwork_22427_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22427_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [FAIL][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl2/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl3/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl4/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl3/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl4/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl4/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11291/shard-apl4/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl6/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl1/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl8/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl8/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl3/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl3/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl8/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22427/shard-apl4/boot.html [44]: https://i
