[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/selftests: Disable runtime pm wakeref tracking for the mock device (rev3)
== Series Details == Series: drm/i915/selftests: Disable runtime pm wakeref tracking for the mock device (rev3) URL : https://patchwork.freedesktop.org/series/99708/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher optimize plane updates (rev3)
== Series Details ==
Series: drm/i915: Futher optimize plane updates (rev3)
URL : https://patchwork.freedesktop.org/series/99149/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22234_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22234_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22234_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 12)
--
Additional (1): shard-rkl
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22234_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-iclb1/igt@gem_exec_balan...@parallel-ordering.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-rkl-1/igt@syncobj_timel...@invalid-transfer-non-existent-point.html
Known issues
Here are the changes found in Patchwork_22234_full that come from known
issues:
### CI changes ###
Issues hit
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6],
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30],
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36],
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42],
[PASS][43], [PASS][44], [PASS][45], [FAIL][46], [PASS][47], [PASS][48],
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk7/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk6/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk5/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk4/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk4/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk3/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk3/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk2/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk1/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk7/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk9/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk9/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk8/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk8/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk8/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22234/shard-glk8/
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Disable runtime pm wakeref tracking for the mock device (rev3)
== Series Details ==
Series: drm/i915/selftests: Disable runtime pm wakeref tracking for the mock
device (rev3)
URL : https://patchwork.freedesktop.org/series/99708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11207 -> Patchwork_22236
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/index.html
Participating hosts (45 -> 43)
--
Additional (1): bat-rpls-1
Missing(3): fi-bsw-cyan fi-icl-u2 shard-tglu
Known issues
Here are the changes found in Patchwork_22236 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][1] ([i915#4547])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u: [PASS][4] -> [INCOMPLETE][5] ([i915#151])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-kbl-7500u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] /
[i915#4957])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#5026])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#4269])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#1814] /
[i915#2722] / [i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-kbl-7500u/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#2403] /
[i915#2426] / [i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][14] ([i915#4494] / [i915#4957]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: [INCOMPLETE][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-kbl-soraka/igt@i915_selftest@l...@requests.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/fi-kbl-soraka/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
Build cha
Re: [Intel-gfx] [GVT PULL] gvt-fixes for drm-intel-fixes
+Tvrtko On Wed, 09 Feb 2022, "Wang, Zhi A" wrote: > Hi folks: > > Ping. This pull seems not got merged. > > Thanks, > Zhi. > > -Original Message- > From: Zhi Wang > Sent: Saturday, January 15, 2022 12:46 PM > To: Vivi, Rodrigo ; jani.nik...@linux.intel.com; > joonas.lahti...@linux.intel.com > Cc: intel-gvt-...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; > Wang, Zhi A > Subject: [GVT PULL] gvt-fixes for drm-intel-fixes > > Hi folks: > > Here is the gvt-fixes pull for drm-intel-fixes. It contains: > > - Make DRM_I915_GVT depend on X86 (Siva Mullati) > - Clean kernel doc in gtt.c (Randy Dunlap) > > This pull has been tested by: dim apply-pull drm-intel-fixes < this_email.eml > > Zhi. > > The following changes since commit d46f329a3f6048e04736e86cb13c880645048792: > > drm/i915: Increment composite fence seqno (2021-12-27 11:33:40 +0200) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux.git tags/gvt-fixes-2022-01-13 > > for you to fetch changes up to d72d69abfdb6e0375981cfdda8eb45143f12c77d: > > drm/i915/gvt: Make DRM_I915_GVT depend on X86 (2022-01-13 18:13:12 +) > > > gvt-fixes-2022-01-13 > > - Make DRM_I915_GVT depend on X86 (Siva Mullati) > - Clean kernel doc in gtt.c (Randy Dunlap) > > > Randy Dunlap (1): > drm/i915/gvt: clean up kernel-doc in gtt.c > > Siva Mullati (1): > drm/i915/gvt: Make DRM_I915_GVT depend on X86 > > drivers/gpu/drm/i915/Kconfig | 1 + > drivers/gpu/drm/i915/gvt/gtt.c | 4 ++-- > 2 files changed, 3 insertions(+), 2 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clarify vma lifetime
== Series Details ==
Series: drm/i915: Clarify vma lifetime
URL : https://patchwork.freedesktop.org/series/99948/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22235_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22235_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22235_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 12)
--
Additional (1): shard-rkl
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22235_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: NOTRUN -> [DMESG-FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-iclb2/igt@gem_exec_balan...@parallel-ordering.html
* igt@kms_flip@flip-vs-fences-interruptible@a-vga1:
- shard-snb: [PASS][2] -> [INCOMPLETE][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-snb5/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-snb7/igt@kms_flip@flip-vs-fences-interrupti...@a-vga1.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [PASS][4] -> [SKIP][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb4/igt@kms_frontbuffer_track...@fbc-suspend.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-iclb5/igt@kms_frontbuffer_track...@fbc-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- {shard-rkl}:NOTRUN -> ([DMESG-WARN][6], [DMESG-WARN][7])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-rkl-4/igt@syncobj_timel...@invalid-transfer-non-existent-point.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-rkl-2/igt@syncobj_timel...@invalid-transfer-non-existent-point.html
* igt@syncobj_timeline@transfer-timeline-point:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-rkl-2/igt@syncobj_timel...@transfer-timeline-point.html
Known issues
Here are the changes found in Patchwork_22235_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_capture@pi@vecs0:
- shard-iclb: NOTRUN -> [INCOMPLETE][9] ([i915#3371])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-iclb5/igt@gem_exec_capture@p...@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2849])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_exec_schedule@submit-early-slice@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][16] ([i915#3797])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-skl6/igt@gem_exec_schedule@submit-early-sl...@vcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#1895])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb2/igt@gem_exec_whis...@basic-queues-forked-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-iclb2/igt@gem_exec_whis...@basic-queues-forked-all.html
* igt@gem_lmem_swapping@heavy-random:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22235/shard-kbl3/igt@gem_lmem_swapp...@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl:
Re: [Intel-gfx] [RFC 00/12] locking: Separate lock tracepoints from lockdep/lock_stat (v1)
On Wed, Feb 09, 2022 at 03:17:38PM -0500, Waiman Long wrote: > > On 2/9/22 14:45, Namhyung Kim wrote: > > On Wed, Feb 9, 2022 at 11:28 AM Mathieu Desnoyers > > wrote: > > > - On Feb 9, 2022, at 2:22 PM, Namhyung Kim namhy...@kernel.org wrote: > > > > I'm also concerning dynamic allocated locks in a data structure. > > > > If we keep the info in a hash table, we should delete it when the > > > > lock is gone. I'm not sure we have a good place to hook it up all. > > > I was wondering about this use case as well. Can we make it mandatory to > > > declare the lock "class" (including the name) statically, even though the > > > lock per-se is allocated dynamically ? Then the initialization of the lock > > > embedded within the data structure would simply refer to the lock class > > > definition. > > Isn't it still the same if we have static lock classes that the entry needs > > to be deleted from the hash table when it frees the data structure? > > I'm more concerned about free than alloc as there seems to be no > > API to track that in a place. > > We may have to invent some new APIs to do that. For example, > spin_lock_exit() can be the counterpart of spin_lock_init() and so on. Of > course, existing kernel code have to be modified to designate the point > after which a lock is no longer being used or is freed. The canonical name is _destroy(). We even have mutex_destroy() except it's usage isn't mandatory. The easy way out is doing as lockdep does and hook into the memory allocators and check every free'd hunk of memory for a lock. It does hoever mean your data structure of choice needs to be able to answer: do I have an entry in @range. Which mostly disqualifies a hash-table. Still, I really don't think you need any of this, it's just bloat. A very limited stack unwind for one of the two tracepoints should allow you to find the offending lock just fine.
[Intel-gfx] [PULL] drm-misc-fixes
Hi Dave and Daniel, here's this week's PR for drm-misc-fixes. The most notable thing is the addition of the new fbdev core module. Best regards Thomas drm-misc-fixes-2022-02-10: * drm/panel: simple: Fix assignments from panel_dpi_probe() * drm/privacy-screen: Cleanups * drm/rockchip: Fix HDMI error cleanup; Fix RK3399 VOP register fields * drm/vc4: HDMI fixes; Cleanups * fbdev: Add fbdev core module with Daniel as maintainer; Cleanups The following changes since commit 622c9a3a7868e1eeca39c55305ca3ebec4742b64: drm: mxsfb: Fix NULL pointer dereference (2022-02-03 09:31:16 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2022-02-10 for you to fetch changes up to 9da1e9ab82c92d0e89fe44cad2cd7c2d18d64070: drm/rockchip: vop: Correct RK3399 VOP register fields (2022-02-08 18:10:36 +0100) * drm/panel: simple: Fix assignments from panel_dpi_probe() * drm/privacy-screen: Cleanups * drm/rockchip: Fix HDMI error cleanup; Fix RK3399 VOP register fields * drm/vc4: HDMI fixes; Cleanups * fbdev: Add fbdev core module with Daniel as maintainer; Cleanups Brian Norris (1): drm/rockchip: vop: Correct RK3399 VOP register fields Christoph Niedermaier (1): drm/panel: simple: Assign data from panel_dpi_probe() correctly Daniel Vetter (1): MAINTAINERS: Add entry for fbdev core Dave Stevenson (3): drm/vc4: hdmi: Ensure we don't use 2711 HPD registers on Pi0-3 drm/vc4: hdmi: Don't try disabling SCDC on Pi0-3. drm/vc4: hdmi: Allow DBLCLK modes even if horz timing is odd. Hans de Goede (1): drm/privacy-screen: Fix sphinx warning Helge Deller (1): fbcon: Avoid 'cap' set but not used warning Maxime Ripard (1): drm/vc4: crtc: Fix redundant variable assignment Sascha Hauer (1): drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Yizhuo Zhai (1): fbdev: fbmem: Fix the implicit type casting MAINTAINERS | 6 ++ drivers/gpu/drm/drm_privacy_screen.c| 2 +- drivers/gpu/drm/panel/panel-simple.c| 1 + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++--- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 +--- drivers/gpu/drm/vc4/vc4_crtc.c | 1 - drivers/gpu/drm/vc4/vc4_hdmi.c | 29 - drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ drivers/video/fbdev/core/fbcon.c| 7 +++ drivers/video/fbdev/core/fbmem.c| 2 ++ 10 files changed, 48 insertions(+), 25 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Disable runtime pm wakeref tracking for the mock device (rev3)
== Series Details == Series: drm/i915/selftests: Disable runtime pm wakeref tracking for the mock device (rev3) URL : https://patchwork.freedesktop.org/series/99708/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11207_full -> Patchwork_22236_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22236_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22236_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22236_full: ### IGT changes ### Possible regressions * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-iclb2/igt@gem_exec_balan...@parallel-ordering.html Known issues Here are the changes found in Patchwork_22236_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@psr2: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#658]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-iclb1/igt@feature_discov...@psr2.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: NOTRUN -> [DMESG-WARN][3] ([i915#5076]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-iclb1/igt@gem_exec_balan...@parallel-contexts.html * igt@gem_exec_capture@pi@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-skl1/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-apl6/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2849]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_schedule@submit-early-slice@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][13] ([i915#3797]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-skl3/igt@gem_exec_schedule@submit-early-sl...@vcs0.html * igt@gem_exec_schedule@wide@vcs0: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/shard-glk9/igt@gem_exec_schedule@w...@vcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-glk6/igt@gem_exec_schedule@w...@vcs0.html * igt@gem_lmem_swapping@heavy-random: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-kbl4/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-apl1/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@verify: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-skl9/igt@gem_lmem_swapp...@verify.html * igt@gem_pread@exhaustion: - shard-tglb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22236/shard-tglb3/igt@gem_pr...@exhaustion.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-iclb: NOTRUN -> [SKIP][2
Re: [Intel-gfx] [RFC 00/12] locking: Separate lock tracepoints from lockdep/lock_stat (v1)
On Wed, Feb 09, 2022 at 04:32:58PM -0800, Namhyung Kim wrote: > On Wed, Feb 9, 2022 at 1:09 AM Peter Zijlstra wrote: > > > > On Tue, Feb 08, 2022 at 10:41:56AM -0800, Namhyung Kim wrote: > > > > > Eventually I'm mostly interested in the contended locks only and I > > > want to reduce the overhead in the fast path. By moving that, it'd be > > > easy to track contended locks with timing by using two tracepoints. > > > > So why not put in two new tracepoints and call it a day? > > > > Why muck about with all that lockdep stuff just to preserve the name > > (and in the process continue to blow up data structures etc..). This > > leaves distros in a bind, will they enable this config and provide > > tracepoints while bloating the data structures and destroying things > > like lockref (which relies on sizeof(spinlock_t)), or not provide this > > at all. > > If it's only lockref, is it possible to change it to use arch_spinlock_t > so that it can remain in 4 bytes? It'd be really nice if we can keep > spin lock size, but it'd be easier to carry the name with it for > analysis IMHO. It's just vile and disgusting to blow up the lock size for convenience like this. And no, there's more of that around. A lot of effort has been spend to make sure spinlocks are 32bit and we're not going to give that up for something as daft as this. Just think harder on the analysis side. Like said; I'm thinking the caller IP should be good enough most of the time.
Re: [Intel-gfx] [GVT PULL] gvt-fixes for drm-intel-fixes
Feel free to let me know if I need to re-base on the newest tag since it has been quite some time. On 2/10/22 8:51 AM, Jani Nikula wrote: > > +Tvrtko > > On Wed, 09 Feb 2022, "Wang, Zhi A" wrote: >> Hi folks: >> >> Ping. This pull seems not got merged. >> >> Thanks, >> Zhi. >> >> -Original Message- >> From: Zhi Wang >> Sent: Saturday, January 15, 2022 12:46 PM >> To: Vivi, Rodrigo ; jani.nik...@linux.intel.com; >> joonas.lahti...@linux.intel.com >> Cc: intel-gvt-...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; >> Wang, Zhi A >> Subject: [GVT PULL] gvt-fixes for drm-intel-fixes >> >> Hi folks: >> >> Here is the gvt-fixes pull for drm-intel-fixes. It contains: >> >> - Make DRM_I915_GVT depend on X86 (Siva Mullati) >> - Clean kernel doc in gtt.c (Randy Dunlap) >> >> This pull has been tested by: dim apply-pull drm-intel-fixes < this_email.eml >> >> Zhi. >> >> The following changes since commit d46f329a3f6048e04736e86cb13c880645048792: >> >> drm/i915: Increment composite fence seqno (2021-12-27 11:33:40 +0200) >> >> are available in the Git repository at: >> >> https://github.com/intel/gvt-linux.git tags/gvt-fixes-2022-01-13 >> >> for you to fetch changes up to d72d69abfdb6e0375981cfdda8eb45143f12c77d: >> >> drm/i915/gvt: Make DRM_I915_GVT depend on X86 (2022-01-13 18:13:12 +) >> >> >> gvt-fixes-2022-01-13 >> >> - Make DRM_I915_GVT depend on X86 (Siva Mullati) >> - Clean kernel doc in gtt.c (Randy Dunlap) >> >> >> Randy Dunlap (1): >> drm/i915/gvt: clean up kernel-doc in gtt.c >> >> Siva Mullati (1): >> drm/i915/gvt: Make DRM_I915_GVT depend on X86 >> >> drivers/gpu/drm/i915/Kconfig | 1 + >> drivers/gpu/drm/i915/gvt/gtt.c | 4 ++-- >> 2 files changed, 3 insertions(+), 2 deletions(-) >
[Intel-gfx] [PATCH] drm/i915/fbc: Fix the plane end Y offset check
From: Ville Syrjälä
We lost the required >>16 when I refactored the FBC plane state
checks. Bring it back so the check does what it's supposed to.
Cc: Mika Kahola
Fixes: 2e6c99f88679 ("drm/i915/fbc: Nuke lots of crap from
intel_fbc_state_cache")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index bcdffe62f3cb..87f4af3fd523 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1125,7 +1125,8 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
if (DISPLAY_VER(i915) >= 11 &&
- (plane_state->view.color_plane[0].y +
drm_rect_height(&plane_state->uapi.src)) & 3) {
+ (plane_state->view.color_plane[0].y +
+(drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
plane_state->no_fbc_reason = "plane end Y offset misaligned";
return false;
}
--
2.34.1
Re: [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
On 10/02/2022 01:26, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..ec8d91b088ff 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström
*/
+#include
I thought linux/cacheflush.h would be correct.
Regards,
Tvrtko
#include
#include
#include
@@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
[Intel-gfx] [PATCH 0/5] drm/i915/opregion: fixes and cleanups, RESEND
Resend of https://patchwork.freedesktop.org/series/98836/ Jani Nikula (5): drm/i915/opregion: check port number bounds for SWSCI display power state drm/i915/opregion: abstract the check for valid swsci function drm/i915/opregion: early exit from encoder notify if SWSCI isn't there drm/i915/opregion: handle SWSCI Mailbox #2 obsoletion drm/i915/opregion: debug log about Mailbox #2 for backlight drivers/gpu/drm/i915/display/intel_opregion.c | 78 +++ 1 file changed, 62 insertions(+), 16 deletions(-) -- 2.30.2
[Intel-gfx] [PATCH 1/5] drm/i915/opregion: check port number bounds for SWSCI display power state
The mapping from enum port to whatever port numbering scheme is used by
the SWSCI Display Power State Notification is odd, and the memory of it
has faded. In any case, the parameter only has space for ports numbered
[0..4], and UBSAN reports bit shift beyond it when the platform has port
F or more.
Since the SWSCI functionality is supposed to be obsolete for new
platforms (i.e. ones that might have port F or more), just bail out
early if the mapped and mangled port number is beyond what the Display
Power State Notification can support.
Fixes: 9c4b0a683193 ("drm/i915: add opregion function to notify bios of encoder
enable/disable")
Cc: # v3.13+
Cc: Ville Syrjälä
Cc: Lucas De Marchi
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4800
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_opregion.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index af9d30f56cc1..ad1afe9df6c3 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -363,6 +363,21 @@ int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder,
port++;
}
+ /*
+* The port numbering and mapping here is bizarre. The now-obsolete
+* swsci spec supports ports numbered [0..4]. Port E is handled as a
+* special case, but port F and beyond are not. The functionality is
+* supposed to be obsolete for new platforms. Just bail out if the port
+* number is out of bounds after mapping.
+*/
+ if (port > 4) {
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] port %c (index %u) out of bounds
for display power state notification\n",
+ intel_encoder->base.base.id,
intel_encoder->base.name,
+ port_name(intel_encoder->port), port);
+ return -EINVAL;
+ }
+
if (!enable)
parm |= 4 << 8;
--
2.30.2
[Intel-gfx] [PATCH 2/5] drm/i915/opregion: abstract the check for valid swsci function
Add a reusable function for checking the SWSCI function.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_opregion.c | 30 +--
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index ad1afe9df6c3..e540e5b9073b 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -245,14 +245,10 @@ struct opregion_asle_ext {
#define MAX_DSLP 1500
-static int swsci(struct drm_i915_private *dev_priv,
-u32 function, u32 parm, u32 *parm_out)
+static int check_swsci_function(struct drm_i915_private *i915, u32 function)
{
- struct opregion_swsci *swsci = dev_priv->opregion.swsci;
- struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
- u32 main_function, sub_function, scic;
- u16 swsci_val;
- u32 dslp;
+ struct opregion_swsci *swsci = i915->opregion.swsci;
+ u32 main_function, sub_function;
if (!swsci)
return -ENODEV;
@@ -264,15 +260,31 @@ static int swsci(struct drm_i915_private *dev_priv,
/* Check if we can call the function. See swsci_setup for details. */
if (main_function == SWSCI_SBCB) {
- if ((dev_priv->opregion.swsci_sbcb_sub_functions &
+ if ((i915->opregion.swsci_sbcb_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
} else if (main_function == SWSCI_GBDA) {
- if ((dev_priv->opregion.swsci_gbda_sub_functions &
+ if ((i915->opregion.swsci_gbda_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
}
+ return 0;
+}
+
+static int swsci(struct drm_i915_private *dev_priv,
+u32 function, u32 parm, u32 *parm_out)
+{
+ struct opregion_swsci *swsci = dev_priv->opregion.swsci;
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ u32 scic, dslp;
+ u16 swsci_val;
+ int ret;
+
+ ret = check_swsci_function(dev_priv, function);
+ if (ret)
+ return ret;
+
/* Driver sleep timeout in ms. */
dslp = swsci->dslp;
if (!dslp) {
--
2.30.2
[Intel-gfx] [PATCH 3/5] drm/i915/opregion: early exit from encoder notify if SWSCI isn't there
Newer platforms aren't supposed to have mailbox #2 or SWSCI support. Bail out early from encoder notify if that is the case, skipping the out-of-bounds checks and debug messages. Cc: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_opregion.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index e540e5b9073b..ce3d44cc2461 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -358,11 +358,17 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, u32 parm = 0; u32 type = 0; u32 port; + int ret; /* don't care about old stuff for now */ if (!HAS_DDI(dev_priv)) return 0; + /* Avoid port out of bounds checks if SWSCI isn't there. */ + ret = check_swsci_function(dev_priv, SWSCI_SBCB_DISPLAY_POWER_STATE); + if (ret) + return ret; + if (intel_encoder->type == INTEL_OUTPUT_DSI) port = 0; else -- 2.30.2
[Intel-gfx] [PATCH 4/5] drm/i915/opregion: handle SWSCI Mailbox #2 obsoletion
Opregion Mailbox #2 is obsolete for SWSCI usage in opregion v2.x, and
repurposed in opregion v3.x. Warn about obsole mailbox presence in v2.x,
and ignore with an error for v3.x.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_opregion.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index ce3d44cc2461..6e32ed6bbf4e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -932,9 +932,17 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
}
if (mboxes & MBOX_SWSCI) {
- drm_dbg(&dev_priv->drm, "SWSCI supported\n");
- opregion->swsci = base + OPREGION_SWSCI_OFFSET;
- swsci_setup(dev_priv);
+ u8 major = opregion->header->over.major;
+
+ if (major >= 3) {
+ drm_err(&dev_priv->drm, "SWSCI Mailbox #2 present for
opregion v3.x, ignoring\n");
+ } else {
+ if (major >= 2)
+ drm_warn(&dev_priv->drm, "SWSCI Mailbox #2
present for opregion v2.x\n");
+ drm_dbg(&dev_priv->drm, "SWSCI supported\n");
+ opregion->swsci = base + OPREGION_SWSCI_OFFSET;
+ swsci_setup(dev_priv);
+ }
}
if (mboxes & MBOX_ASLE) {
--
2.30.2
[Intel-gfx] [PATCH 5/5] drm/i915/opregion: debug log about Mailbox #2 for backlight
Start debug logging about the presence of the new Mailbox #2 for
backlight. Actual support is to be added later.
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_opregion.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index 6e32ed6bbf4e..b1ad11b2ebb3 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -47,10 +47,11 @@
#define OPREGION_ASLE_EXT_OFFSET 0x1C00
#define OPREGION_SIGNATURE "IntelGraphicsMem"
-#define MBOX_ACPI (1<<0)
-#define MBOX_SWSCI (1<<1)
-#define MBOX_ASLE (1<<2)
-#define MBOX_ASLE_EXT (1<<4)
+#define MBOX_ACPI BIT(0) /* Mailbox #1 */
+#define MBOX_SWSCI BIT(1) /* Mailbox #2 (obsolete from v2.x) */
+#define MBOX_ASLE BIT(2) /* Mailbox #3 */
+#define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */
+#define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */
struct opregion_header {
u8 signature[16];
@@ -957,6 +958,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
}
+ if (mboxes & MBOX_BACKLIGHT) {
+ drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
+ }
+
if (intel_load_vbt_firmware(dev_priv) == 0)
goto out;
--
2.30.2
Re: [Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register
On Thu, 10 Feb 2022, Chuansheng Liu wrote:
> Current DMC_DEBUG3(_MMIO(0x101090)) address is for TGL,
> it is not wrong for DG1. Just like commit 5bcc95ca382e
wrong, not "not wrong".
BR,
Jani.
> ("drm/i915/dg1: Update DMC_DEBUG register"), correct
> this issue for DG1 platform to avoid wrong register
> being read.
>
> BSpec: 49788
>
> Signed-off-by: Chuansheng Liu
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f4de004d470f..f6c4ad8fce19 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -474,8 +474,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>* reg for DC3CO debugging and validation,
>* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
>*/
> - seq_printf(m, "DC3CO count: %d\n",
> -intel_de_read(dev_priv, DMC_DEBUG3));
> + seq_printf(m, "DC3CO count: %d\n", intel_de_read(dev_priv,
> IS_DGFX(dev_priv) ?
> + DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3));
> } else {
> dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
>SKL_DMC_DC3_DC5_COUNT;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 87c92314ee26..9c215a6df659 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5632,7 +5632,8 @@
> #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
>
> -#define DMC_DEBUG3 _MMIO(0x101090)
> +#define TGL_DMC_DEBUG3 _MMIO(0x101090)
> +#define DG1_DMC_DEBUG3 _MMIO(0x13415c)
>
> /* Display Internal Timeout Register */
> #define RM_TIMEOUT _MMIO(0x42060)
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave, Daniel, An assortment of fixes for -rc4, mostly display, one TTM migration fixup, one fix for platforms without runtime PM and one !x86 build fix. Regards, Tvrtko drm-intel-fixes-2022-02-10: - Build fix for non-x86 platforms after remap_io_mmapping changes. (Lucas De Marchi) - Correctly propagate errors during object migration blits. (Thomas Hellström) - Disable DRRS support on HSW/IVB where it is not implemented yet. (Ville Syrjälä) - Correct pipe dbuf BIOS configuration during readout. (Ville Syrjälä) - Properly sanitise BIOS buf configuration on ADL-P+ for !join_mbus cases. (Ville Syrjälä) - Fix oops due to missing stack depot. (Ville Syrjälä) - Workaround broken BIOS DBUF configuration on TGL/RKL. (Ville Syrjälä) The following changes since commit dfd42facf1e4ada021b939b4e19c935dcdd55566: Linux 5.17-rc3 (2022-02-06 12:20:50 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2022-02-10 for you to fetch changes up to 4e6f55120c7eccf6f9323bb681632e23cbcb3f3c: drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL (2022-02-07 12:56:50 +) - Build fix for non-x86 platforms after remap_io_mmapping changes. (Lucas De Marchi) - Correctly propagate errors during object migration blits. (Thomas Hellström) - Disable DRRS support on HSW/IVB where it is not implemented yet. (Ville Syrjälä) - Correct pipe dbuf BIOS configuration during readout. (Ville Syrjälä) - Properly sanitise BIOS buf configuration on ADL-P+ for !join_mbus cases. (Ville Syrjälä) - Fix oops due to missing stack depot. (Ville Syrjälä) - Workaround broken BIOS DBUF configuration on TGL/RKL. (Ville Syrjälä) Lucas De Marchi (1): drm/i915: Fix header test for !CONFIG_X86 Thomas Hellström (1): drm/i915/ttm: Return some errors instead of trying memcpy move Ville Syrjälä (5): drm/i915: Fix oops due to missing stack depot drm/i915: Disable DRRS on IVB/HSW port != A drm/i915: Allow !join_mbus cases for adlp+ dbuf configuration drm/i915: Populate pipe dbuf slices more accurately during readout drm/i915: Workaround broken BIOS DBUF configuration on TGL/RKL drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_drrs.c| 8 ++ drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 14 ++- drivers/gpu/drm/i915/i915_mm.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 143 ++- drivers/gpu/drm/i915/intel_pm.h | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +- 7 files changed, 142 insertions(+), 30 deletions(-)
Re: [Intel-gfx] [PATCH] drm/i915/display/tgl+: Implement new PLL programming step
On Tue, 08 Feb 2022, José Roberto de Souza wrote:
> A new programming step was added to combo and TC PLL sequences.
> If override_AFC_startup is set in VBT, driver should overwrite
> AFC_startup value to 0x7 in PLL's div0 register.
>
> The current understating is that only TGL needs this and all display
> 12 and newer platforms will have a older VBT or a newer VBT with
> override_AFC_startup set to 0 but in any case there is a
> drm_warn_on_once() to let us know if this is not true.
>
> BSpec: 49204
> BSpec: 20122 (pending aproval, check working copies)
> BSpec: 49968
> BSpec: 71360
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 4 ++
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 6 ++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 13 +++
> 6 files changed, 57 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index aec0efd5350ef..a4134b63f2d49 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -596,6 +596,10 @@ parse_general_features(struct drm_i915_private *i915,
> } else {
> i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
> }
> +
> + if (bdb->version >= 249)
> + i915->vbt.override_afc_startup_bit =
> general->override_afc_startup_bit;
Please drop _bit suffix for single bits. No need to duplicate VBT
idiosyncrasies in kernel.
BR,
Jani.
> +
> drm_dbg_kms(&i915->drm,
> "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d
> lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d
> fdi_rx_polarity_inverted %d\n",
> i915->vbt.int_tv_support,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6723c3de5a80c..a60917b926de9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2748,6 +2748,9 @@ static void icl_calc_dpll_state(struct drm_i915_private
> *i915,
> pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
> else
> pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
> +
> + if (i915->vbt.override_afc_startup_bit)
> + pll_state->div0 =
> TGL_DPLL0_DIV0_AFC_STARTUP(TGL_DPLL0_DIV0_AFC_STARTUP_OVERRIDE_VAL);
> }
>
> static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> @@ -2949,6 +2952,8 @@ static bool icl_calc_mg_pll_state(struct
> intel_crtc_state *crtc_state,
>DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
>DKL_PLL_DIV0_FBPREDIV(m1div) |
>DKL_PLL_DIV0_FBDIV_INT(m2div_int);
> + if (dev_priv->vbt.override_afc_startup_bit)
> + pll_state->mg_pll_div0 |=
> DKL_PLL_DIV0_AFC_STARTUP(TGL_DPLL0_DIV0_AFC_STARTUP_OVERRIDE_VAL);
>
> pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
>
> DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
> @@ -3448,10 +3453,10 @@ static bool dkl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
>
> hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port));
> - hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK |
> - DKL_PLL_DIV0_PROP_COEFF_MASK |
> - DKL_PLL_DIV0_FBPREDIV_MASK |
> - DKL_PLL_DIV0_FBDIV_INT_MASK);
> + val = DKL_PLL_DIV0_MASK;
> + if (dev_priv->vbt.override_afc_startup_bit)
> + val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
> + hw_state->mg_pll_div0 &= val;
>
> hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port));
> hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
> @@ -3513,6 +3518,10 @@ static bool icl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
>TGL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = intel_de_read(dev_priv,
>TGL_DPLL_CFGCR1(id));
> + if (dev_priv->vbt.override_afc_startup_bit) {
> + hw_state->div0 = intel_de_read(dev_priv,
> TGL_DPLL0_DIV0(id));
> + hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
> + }
> } else {
> if (IS_JSL_EHL(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> hw_state->cfgcr0 = intel_de_read(dev_priv,
> @@ -3554,7 +3563,7 @@ static void icl_dpll_write(struct
Re: [Intel-gfx] [GVT PULL] gvt-fixes for drm-intel-fixes
On 10/02/2022 10:14, Wang, Zhi A wrote: Feel free to let me know if I need to re-base on the newest tag since it has been quite some time. Sorry I did not see this. I will pull it next Monday. If you can extra remind me it would be appreciated. Current base for fixes is 5.17-rc3 but given how little you have in there I don't think there should be a problem with your base. Regards, Tvrtko On 2/10/22 8:51 AM, Jani Nikula wrote: +Tvrtko On Wed, 09 Feb 2022, "Wang, Zhi A" wrote: Hi folks: Ping. This pull seems not got merged. Thanks, Zhi. -Original Message- From: Zhi Wang Sent: Saturday, January 15, 2022 12:46 PM To: Vivi, Rodrigo ; jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com Cc: intel-gvt-...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Wang, Zhi A Subject: [GVT PULL] gvt-fixes for drm-intel-fixes Hi folks: Here is the gvt-fixes pull for drm-intel-fixes. It contains: - Make DRM_I915_GVT depend on X86 (Siva Mullati) - Clean kernel doc in gtt.c (Randy Dunlap) This pull has been tested by: dim apply-pull drm-intel-fixes < this_email.eml Zhi. The following changes since commit d46f329a3f6048e04736e86cb13c880645048792: drm/i915: Increment composite fence seqno (2021-12-27 11:33:40 +0200) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-fixes-2022-01-13 for you to fetch changes up to d72d69abfdb6e0375981cfdda8eb45143f12c77d: drm/i915/gvt: Make DRM_I915_GVT depend on X86 (2022-01-13 18:13:12 +) gvt-fixes-2022-01-13 - Make DRM_I915_GVT depend on X86 (Siva Mullati) - Clean kernel doc in gtt.c (Randy Dunlap) Randy Dunlap (1): drm/i915/gvt: clean up kernel-doc in gtt.c Siva Mullati (1): drm/i915/gvt: Make DRM_I915_GVT depend on X86 drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/gvt/gtt.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-)
Re: [Intel-gfx] [PATCH 5/5] drm/i915/opregion: debug log about Mailbox #2 for backlight
On Thu, Feb 10, 2022 at 12:36:46PM +0200, Jani Nikula wrote:
> Start debug logging about the presence of the new Mailbox #2 for
> backlight. Actual support is to be added later.
>
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_opregion.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 6e32ed6bbf4e..b1ad11b2ebb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -47,10 +47,11 @@
> #define OPREGION_ASLE_EXT_OFFSET 0x1C00
>
> #define OPREGION_SIGNATURE "IntelGraphicsMem"
> -#define MBOX_ACPI (1<<0)
> -#define MBOX_SWSCI (1<<1)
> -#define MBOX_ASLE (1<<2)
> -#define MBOX_ASLE_EXT (1<<4)
> +#define MBOX_ACPIBIT(0) /* Mailbox #1 */
> +#define MBOX_SWSCI BIT(1) /* Mailbox #2 (obsolete from v2.x) */
> +#define MBOX_ASLEBIT(2) /* Mailbox #3 */
> +#define MBOX_ASLE_EXTBIT(4) /* Mailbox #5 */
> +#define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x)
> */
Opregion is such a lovely turd.
Series is
Reviewed-by: Ville Syrjälä
>
> struct opregion_header {
> u8 signature[16];
> @@ -957,6 +958,10 @@ int intel_opregion_setup(struct drm_i915_private
> *dev_priv)
> opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
> }
>
> + if (mboxes & MBOX_BACKLIGHT) {
> + drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
> + }
> +
> if (intel_load_vbt_firmware(dev_priv) == 0)
> goto out;
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [RFC PATCH 0/1] Splitting up platform-specific calls
On 09/02/2022 05:25, Casey Bowman wrote: On 2/7/22 07:36, Tvrtko Ursulin wrote: On 20/01/2022 22:16, Casey Bowman wrote: In this RFC I would like to ask the community their thoughts on how we can best handle splitting architecture-specific calls. I would like to address the following: 1. How do we want to split architecture calls? Different object files per platform? Separate function calls within the same object file? If we are talking about per-platform divergence of significant functions (not necessarily in size but their height position in the i915 stack) I agree with Jani that top-level per platform organisation is not the best choice. On the other hand I doubt that there should be many, if any, such functions. In practice I think it should be only low level stuff which diverges. I agree, as said with my reply to Jani, I think maybe going forward for arch-specific code, #if IS_ENABLED calls should be used sparingly, only in the cases where we do have that arch-specific implementation (like low level calls), instead of just a 'return null', as in my case. On a concrete example.. 2. How do we address dummy functions? If we have a function call that is used for one or more platforms, but is not used in another, what should we do for this case? ... depends on the situation. Sometimes a flavour of "warn on once" can be okay I guess, but also why not build bug on? Because.. True, with Jani's and your comments, I'm thinking that in the case of when we look at a potential arch-specific function where we're just returning null or something similar, we should be re-evaluating the function and seeing if we should make a different change there. I've given an example of splitting an architecture call in my patch with run_as_guest() being split into different implementations for x86 and arm64 in separate object files, sharing a single header. ... run_as_guest may be a very tricky example, given it is called from intel_vtd_active which has a number of callers. What is correct behaviour on Arm in this example? None of these call sites will run on Arm? Or that you expect the warn on added in this patch to trigger as a demonstration? If so, what is the plan going forward? We can take one example and talk about it hypothetically: ./i915_driver.c: drm_printf(p, "iommu: %s\n", enableddisabled(intel_vtd_active(i915))); What is the "fix" (refactor) for Arm here? Looks like a new top-level function is needed which does not carry the intel_vtd_ prefix but something more generic. That one could then legitimately "warn on once", while for intel_vtd_active it would be wrong to do so. Good point, run_as_guest might be a bit more challenging of an example. In my mind, I was thinking of just simply returning null for arm64 here as I don't believe arm64 would be making use of iommu for our cases (at least, in the short term). I think this example function specifically needs to get reworked, as you mentioned, in some way, possibly refactoring intel_vtd_active or something along those lines. And when I say it is needed.. well perhaps it is not strictly needed in this case, but in some other cases I think we go back to the problem I stated some months ago and that is that I suspect use of intel_vtd_active is overloaded. I think it is currently used to answer all these questions: 1. Is the IOMMU active, just for information.; 2. Is the IOMMU active and we want to counteract the performance hit by say using huge pages, adjusting the display bandwidth calculations or whatever. (In which case we also may want to distinguish between pass-through and translation modes.); 3. Is a potentially buggy IOMMU active and we need to work around it. All these under one kind of worked with one iommu implementation but does it with a different IOMMU? Which I mean leads to end conclusion that this particular function is a tricky example to answer the questions asked. :) Another suggestion from Michael (michael.ch...@intel.com) involved using a single object file, a single header, and splitting various functions calls via ifdefs in the header file. In principle, mostly what you have outlined sounds acceptable to me, with the difference that I would not use i915_platform, but for this particular example something like i915_hypervisor prefix. Then I would prepare i915 with the same scheme kernel uses, not just for source file divergence, but header file as well. That is: some_source.c: #include "i915_hypervisor.h" i915_hypervisor.h: #include "platform/i915_hypervisor.h" Then in i915 root you could have: platforms/x86/include/platform/i915_hypervisor.h platforms/arm/include/platform/i915_hypervisor.h And some kbuild stuff to make that work. Is this doable and does it make sense? Per-platform source files could live in there as well. Same scheme for i915_clflush would work as well. I like the idea of getting more specific for the calls here, but I'm som
Re: [Intel-gfx] [PATCH v2 01/19] fbcon: delete a few unneeded forward decl
Am 08.02.22 um 22:08 schrieb Daniel Vetter: I didn't bother with any code movement to fix the others, these just got a bit in the way. v2: Rebase on top of Helge's reverts. Acked-by: Sam Ravnborg (v1) Reviewed-by: Geert Uytterhoeven (v1) Signed-off-by: Daniel Vetter Cc: Helge Deller Cc: Daniel Vetter Cc: Thomas Zimmermann Cc: Du Cheng Cc: Tetsuo Handa Cc: Claudio Suarez Cc: Greg Kroah-Hartman Acked-by: Thomas Zimmermann --- drivers/video/fbdev/core/fbcon.c | 17 + 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index 2fc1b80a26ad..235eaab37d84 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -163,29 +163,14 @@ static int fbcon_cursor_noblink; * Interface used by the world */ -static const char *fbcon_startup(void); -static void fbcon_init(struct vc_data *vc, int init); -static void fbcon_deinit(struct vc_data *vc); -static void fbcon_clear(struct vc_data *vc, int sy, int sx, int height, - int width); -static void fbcon_putc(struct vc_data *vc, int c, int ypos, int xpos); -static void fbcon_putcs(struct vc_data *vc, const unsigned short *s, - int count, int ypos, int xpos); static void fbcon_clear_margins(struct vc_data *vc, int bottom_only); -static void fbcon_cursor(struct vc_data *vc, int mode); static void fbcon_bmove(struct vc_data *vc, int sy, int sx, int dy, int dx, int height, int width); -static int fbcon_switch(struct vc_data *vc); -static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch); static void fbcon_set_palette(struct vc_data *vc, const unsigned char *table); /* * Internal routines */ -static __inline__ void ywrap_up(struct vc_data *vc, int count); -static __inline__ void ywrap_down(struct vc_data *vc, int count); -static __inline__ void ypan_up(struct vc_data *vc, int count); -static __inline__ void ypan_down(struct vc_data *vc, int count); static void fbcon_bmove_rec(struct vc_data *vc, struct fbcon_display *p, int sy, int sx, int dy, int dx, int height, int width, u_int y_break); static void fbcon_set_disp(struct fb_info *info, struct fb_var_screeninfo *var, @@ -194,8 +179,8 @@ static void fbcon_redraw_move(struct vc_data *vc, struct fbcon_display *p, int line, int count, int dy); static void fbcon_modechanged(struct fb_info *info); static void fbcon_set_all_vcs(struct fb_info *info); -static void fbcon_start(void); static void fbcon_exit(void); + static struct device *fbcon_device; #ifdef CONFIG_FRAMEBUFFER_CONSOLE_ROTATION -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev OpenPGP_signature Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v2 02/19] fbcon: Move fbcon_bmove(_rec) functions
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
Avoids two forward declarations, and more importantly, matches what
I've done in my fbcon scrolling restore patches - so I need this to
avoid a bunch of conflicts in rebasing since we ended up merging
Helge's series instead.
Signed-off-by: Daniel Vetter
Cc: Helge Deller
Cc: Daniel Vetter
Cc: Thomas Zimmermann
Cc: Du Cheng
Cc: Tetsuo Handa
Cc: Claudio Suarez
Cc: Greg Kroah-Hartman
Acked-by: Thomas Zimmermann
---
drivers/video/fbdev/core/fbcon.c | 134 +++
1 file changed, 65 insertions(+), 69 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 235eaab37d84..e925bb608e25 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -164,15 +164,11 @@ static int fbcon_cursor_noblink;
*/
static void fbcon_clear_margins(struct vc_data *vc, int bottom_only);
-static void fbcon_bmove(struct vc_data *vc, int sy, int sx, int dy, int dx,
- int height, int width);
static void fbcon_set_palette(struct vc_data *vc, const unsigned char *table);
/*
* Internal routines
*/
-static void fbcon_bmove_rec(struct vc_data *vc, struct fbcon_display *p, int
sy, int sx,
- int dy, int dx, int height, int width, u_int
y_break);
static void fbcon_set_disp(struct fb_info *info, struct fb_var_screeninfo
*var,
int unit);
static void fbcon_redraw_move(struct vc_data *vc, struct fbcon_display *p,
@@ -1667,6 +1663,71 @@ static void fbcon_redraw(struct vc_data *vc, struct
fbcon_display *p,
}
}
+static void fbcon_bmove_rec(struct vc_data *vc, struct fbcon_display *p, int sy, int sx,
+ int dy, int dx, int height, int width, u_int
y_break)
+{
+ struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
+ struct fbcon_ops *ops = info->fbcon_par;
+ u_int b;
+
+ if (sy < y_break && sy + height > y_break) {
+ b = y_break - sy;
+ if (dy < sy) { /* Avoid trashing self */
+ fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
+ y_break);
+ fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
+ height - b, width, y_break);
+ } else {
+ fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
+ height - b, width, y_break);
+ fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
+ y_break);
+ }
+ return;
+ }
+
+ if (dy < y_break && dy + height > y_break) {
+ b = y_break - dy;
+ if (dy < sy) { /* Avoid trashing self */
+ fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
+ y_break);
+ fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
+ height - b, width, y_break);
+ } else {
+ fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
+ height - b, width, y_break);
+ fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
+ y_break);
+ }
+ return;
+ }
+ ops->bmove(vc, info, real_y(p, sy), sx, real_y(p, dy), dx,
+ height, width);
+}
+
+static void fbcon_bmove(struct vc_data *vc, int sy, int sx, int dy, int dx,
+ int height, int width)
+{
+ struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
+ struct fbcon_display *p = &fb_display[vc->vc_num];
+
+ if (fbcon_is_inactive(vc, info))
+ return;
+
+ if (!width || !height)
+ return;
+
+ /* Split blits that cross physical y_wrap case.
+* Pathological case involves 4 blits, better to use recursive
+* code rather than unrolled case
+*
+* Recursive invocations don't need to erase the cursor over and
+* over again, so we use fbcon_bmove_rec()
+*/
+ fbcon_bmove_rec(vc, p, sy, sx, dy, dx, height, width,
+ p->vrows - p->yscroll);
+}
+
static bool fbcon_scroll(struct vc_data *vc, unsigned int t, unsigned int b,
enum con_scroll dir, unsigned int count)
{
@@ -1867,71 +1928,6 @@ static bool fbcon_scroll(struct vc_data *vc, unsigned
int t, unsigned int b,
}
-static void fbcon_bmove(struct vc_data *vc, int sy, int sx, int dy, int dx,
- int height, int width)
-{
- struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
- struct fbcon_display *p = &fb_display[vc->vc_num];
-
- if (fbcon_is_inactive(vc, info))
- return;
-
-
Re: [Intel-gfx] [PATCH v2 03/19] fbcon: Introduce wrapper for console->fb_info lookup
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
Half of it is protected by console_lock, but the other half is a lot
more awkward: Registration/deregistration of fbdev are serialized, but
we don't really clear out anything in con2fb_map and so there's
potential for use-after free mixups.
First step is to encapsulate the lookup.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Helge Deller
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: Tetsuo Handa
Cc: Du Cheng
Cc: Claudio Suarez
Cc: Thomas Zimmermann
Acked-by: Thomas Zimmermann
---
drivers/video/fbdev/core/fbcon.c | 76 ++--
1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index e925bb608e25..b75e638cb83d 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -110,6 +110,18 @@ static struct fbcon_display fb_display[MAX_NR_CONSOLES];
static signed char con2fb_map[MAX_NR_CONSOLES];
static signed char con2fb_map_boot[MAX_NR_CONSOLES];
+static struct fb_info *fbcon_info_from_console(int console)
+{
+ WARN_CONSOLE_UNLOCKED();
+
+ /*
+* Note that only con2fb_map is protected by the console lock,
+* registered_fb is protected by a separate mutex. This lookup can
+* therefore race.
+*/
+ return registered_fb[con2fb_map[console]];
+}
+
static int logo_lines;
/* logo_shown is an index to vc_cons when >= 0; otherwise follows FBCON_LOGO
enums. */
@@ -199,7 +211,7 @@ static void fbcon_rotate(struct fb_info *info, u32 rotate)
if (!ops || ops->currcon == -1)
return;
- fb_info = registered_fb[con2fb_map[ops->currcon]];
+ fb_info = fbcon_info_from_console(ops->currcon);
if (info == fb_info) {
struct fbcon_display *p = &fb_display[ops->currcon];
@@ -226,7 +238,7 @@ static void fbcon_rotate_all(struct fb_info *info, u32
rotate)
for (i = first_fb_vc; i <= last_fb_vc; i++) {
vc = vc_cons[i].d;
if (!vc || vc->vc_mode != KD_TEXT ||
- registered_fb[con2fb_map[i]] != info)
+ fbcon_info_from_console(i) != info)
continue;
p = &fb_display[vc->vc_num];
@@ -356,7 +368,7 @@ static void fb_flashcursor(struct work_struct *work)
vc = vc_cons[ops->currcon].d;
if (!vc || !con_is_visible(vc) ||
- registered_fb[con2fb_map[vc->vc_num]] != info ||
+ fbcon_info_from_console(vc->vc_num) != info ||
vc->vc_deccm != 1) {
console_unlock();
return;
@@ -791,7 +803,7 @@ static void con2fb_init_display(struct vc_data *vc, struct
fb_info *info,
if (show_logo) {
struct vc_data *fg_vc = vc_cons[fg_console].d;
struct fb_info *fg_info =
- registered_fb[con2fb_map[fg_console]];
+ fbcon_info_from_console(fg_console);
fbcon_prepare_logo(fg_vc, fg_info, fg_vc->vc_cols,
fg_vc->vc_rows, fg_vc->vc_cols,
@@ -1014,7 +1026,7 @@ static void fbcon_init(struct vc_data *vc, int init)
if (con2fb_map[vc->vc_num] == -1)
con2fb_map[vc->vc_num] = info_idx;
- info = registered_fb[con2fb_map[vc->vc_num]];
+ info = fbcon_info_from_console(vc->vc_num);
if (logo_shown < 0 && console_loglevel <= CONSOLE_LOGLEVEL_QUIET)
logo_shown = FBCON_LOGO_DONTSHOW;
@@ -1231,7 +1243,7 @@ static void fbcon_deinit(struct vc_data *vc)
static void fbcon_clear(struct vc_data *vc, int sy, int sx, int height,
int width)
{
- struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
+ struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
@@ -1269,7 +1281,7 @@ static void fbcon_clear(struct vc_data *vc, int sy, int
sx, int height,
static void fbcon_putcs(struct vc_data *vc, const unsigned short *s,
int count, int ypos, int xpos)
{
- struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
+ struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fbcon_ops *ops = info->fbcon_par;
@@ -1289,7 +1301,7 @@ static void fbcon_putc(struct vc_data *vc, int c, int ypos, int xpos)
static void fbcon_clear_margins(struct vc_data *vc, int bottom_only)
{
- struct fb_info *info = registered_fb[con2fb_map[vc->vc_num]];
+ struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
if (!fbcon_is_inactive(vc, info))
@@ -1298,7 +1310,7 @@ static void fbcon_clear_margins(struct vc_data *vc, int
bottom_only)
static void fbcon_cursor(struct vc_data *vc, int mode)
Re: [Intel-gfx] [PATCH v2 04/19] fbcon: delete delayed loading code
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
Before
commit 6104c37094e729f3d4ce65797002112735d49cd1
Author: Daniel Vetter
Date: Tue Aug 1 17:32:07 2017 +0200
fbcon: Make fbcon a built-time depency for fbdev
it was possible to load fbcon and fbdev drivers in any order, which
means that fbcon init had to handle the case where fbdev drivers where
already registered.
This is no longer possible, hence delete that code.
Note that the exit case is a bit more complex and will be done in a
separate patch.
Since I had to audit the entire fbcon load code I also spotted a wrong
function name in a comment in fbcon_startup(), which this patch also
fixes.
v2: Explain why we also fix the comment (Sam)
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Helge Deller
Cc: Daniel Vetter
Cc: Claudio Suarez
Cc: Greg Kroah-Hartman
Cc: Tetsuo Handa
Cc: Du Cheng
Acked-by: Thomas Zimmermann
---
drivers/video/fbdev/core/fbcon.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index b75e638cb83d..83f0223f5333 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -944,7 +944,7 @@ static const char *fbcon_startup(void)
return display_desc;
/*
* Instead of blindly using registered_fb[0], we use info_idx, set by
-* fb_console_init();
+* fbcon_fb_registered();
*/
info = registered_fb[info_idx];
if (!info)
@@ -3299,17 +3299,6 @@ static void fbcon_start(void)
return;
}
#endif
-
- if (num_registered_fb) {
- int i;
-
- for_each_registered_fb(i) {
- info_idx = i;
- break;
- }
-
- do_fbcon_takeover(0);
- }
}
static void fbcon_exit(void)
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v2 05/19] fbdev/sysfs: Fix locking
Am 08.02.22 um 22:08 schrieb Daniel Vetter: fb_set_var requires we hold the fb_info lock. Or at least this now matches what the ioctl does ... Note that ps3fb and sh_mobile_lcdcfb are busted in different ways here, but I will not fix them up. Also in practice this isn't a big deal, because really variable fbdev state is actually protected by console_lock (because fbcon just doesn't bother with lock_fb_info() at all), and lock_fb_info protecting anything is really just a neat lie. But that's a much bigger fish to fry. Acked-by: Sam Ravnborg Signed-off-by: Daniel Vetter Cc: Helge Deller Cc: Daniel Vetter Cc: Qing Wang Cc: Sam Ravnborg Acked-by: Thomas Zimmermann --- drivers/video/fbdev/core/fbsysfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/fbdev/core/fbsysfs.c b/drivers/video/fbdev/core/fbsysfs.c index 26892940c213..8c1ee9ecec3d 100644 --- a/drivers/video/fbdev/core/fbsysfs.c +++ b/drivers/video/fbdev/core/fbsysfs.c @@ -91,9 +91,11 @@ static int activate(struct fb_info *fb_info, struct fb_var_screeninfo *var) var->activate |= FB_ACTIVATE_FORCE; console_lock(); + lock_fb_info(fb_info); err = fb_set_var(fb_info, var); if (!err) fbcon_update_vcs(fb_info, var->activate & FB_ACTIVATE_ALL); + unlock_fb_info(fb_info); console_unlock(); if (err) return err; -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev OpenPGP_signature Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v2 06/19] fbcon: Use delayed work for cursor
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
Allows us to delete a bunch of hand-rolled stuff. Also to simplify the
code we initialize the cursor_work completely when we allocate the
fbcon_ops structure, instead of trying to cope with console
re-initialization.
The motiviation here is that fbcon code stops using the fb_info.queue,
which helps with locking issues around cleanup and all that in a later
patch.
Also note that this allows us to ditch the hand-rolled work cleanup in
fbcon_exit - we already call fbcon_del_cursor_timer, which takes care
of everything. Plus this was racy anyway.
Signed-off-by: Daniel Vetter
Cc: Daniel Vetter
Cc: Claudio Suarez
Cc: Du Cheng
Cc: Thomas Zimmermann
Cc: Greg Kroah-Hartman
Cc: Tetsuo Handa
---
drivers/video/fbdev/core/fbcon.c | 85 +---
drivers/video/fbdev/core/fbcon.h | 4 +-
2 files changed, 35 insertions(+), 54 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 83f0223f5333..a368ed602e2e 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -350,8 +350,8 @@ static int get_color(struct vc_data *vc, struct fb_info
*info,
static void fb_flashcursor(struct work_struct *work)
{
- struct fb_info *info = container_of(work, struct fb_info, queue);
- struct fbcon_ops *ops = info->fbcon_par;
+ struct fbcon_ops *ops = container_of(work, struct fbcon_ops,
cursor_work.work);
+ struct fb_info *info;
struct vc_data *vc = NULL;
int c;
int mode;
@@ -364,7 +364,10 @@ static void fb_flashcursor(struct work_struct *work)
if (ret == 0)
return;
- if (ops && ops->currcon != -1)
+ /* protected by console_lock */
+ info = ops->info;
+
+ if (ops->currcon != -1)
vc = vc_cons[ops->currcon].d;
if (!vc || !con_is_visible(vc) ||
@@ -380,42 +383,25 @@ static void fb_flashcursor(struct work_struct *work)
ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
get_color(vc, info, c, 0));
console_unlock();
-}
-static void cursor_timer_handler(struct timer_list *t)
-{
- struct fbcon_ops *ops = from_timer(ops, t, cursor_timer);
- struct fb_info *info = ops->info;
-
- queue_work(system_power_efficient_wq, &info->queue);
- mod_timer(&ops->cursor_timer, jiffies + ops->cur_blink_jiffies);
+ queue_delayed_work(system_power_efficient_wq, &ops->cursor_work,
+ ops->cur_blink_jiffies);
}
-static void fbcon_add_cursor_timer(struct fb_info *info)
+static void fbcon_add_cursor_work(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
- if ((!info->queue.func || info->queue.func == fb_flashcursor) &&
- !(ops->flags & FBCON_FLAGS_CURSOR_TIMER) &&
- !fbcon_cursor_noblink) {
- if (!info->queue.func)
- INIT_WORK(&info->queue, fb_flashcursor);
-
- timer_setup(&ops->cursor_timer, cursor_timer_handler, 0);
- mod_timer(&ops->cursor_timer, jiffies + ops->cur_blink_jiffies);
- ops->flags |= FBCON_FLAGS_CURSOR_TIMER;
- }
+ if (!fbcon_cursor_noblink)
+ queue_delayed_work(system_power_efficient_wq, &ops->cursor_work,
+ ops->cur_blink_jiffies);
}
-static void fbcon_del_cursor_timer(struct fb_info *info)
+static void fbcon_del_cursor_work(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
- if (info->queue.func == fb_flashcursor &&
- ops->flags & FBCON_FLAGS_CURSOR_TIMER) {
- del_timer_sync(&ops->cursor_timer);
- ops->flags &= ~FBCON_FLAGS_CURSOR_TIMER;
- }
+ cancel_delayed_work_sync(&ops->cursor_work);
}
#ifndef MODULE
@@ -714,6 +700,8 @@ static int con2fb_acquire_newinfo(struct vc_data *vc,
struct fb_info *info,
ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
if (!ops)
err = -ENOMEM;
+
+ INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
There's similar code in fbcon_startup() when there should be a single
init function for fbcon_ops. Maybe something for later.
Acked-by: Thomas Zimmermann
}
if (!err) {
@@ -751,7 +739,7 @@ static int con2fb_release_oldinfo(struct vc_data *vc,
struct fb_info *oldinfo,
}
if (!err) {
- fbcon_del_cursor_timer(oldinfo);
+ fbcon_del_cursor_work(oldinfo);
kfree(ops->cursor_state.mask);
kfree(ops->cursor_data);
kfree(ops->cursor_src);
@@ -867,7 +855,7 @@ static int set_con2fb_map(int unit, int newidx, int user)
logo_shown != FBCON_LOGO_DONTSHOW);
if (!found)
- fbcon_add_cursor_timer(info);
+ fbcon_add_cursor_wor
Re: [Intel-gfx] [PATCH v2 08/19] fb: Delete fb_info->queue
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
It was only used by fbcon, and that now switched to its own,
private work.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Helge Deller
Cc: linux-fb...@vger.kernel.org
Acked-by: Thomas Zimmermann
---
include/linux/fb.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 3d7306c9a706..23b19cf8bccd 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -449,7 +449,6 @@ struct fb_info {
struct fb_var_screeninfo var; /* Current var */
struct fb_fix_screeninfo fix; /* Current fix */
struct fb_monspecs monspecs;/* Current Monitor specs */
- struct work_struct queue; /* Framebuffer event queue */
struct fb_pixmap pixmap;/* Image hardware mapper */
struct fb_pixmap sprite;/* Cursor hardware mapper */
struct fb_cmap cmap;/* Current cmap */
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
OpenPGP_signature
Description: OpenPGP digital signature
Re: [Intel-gfx] [PATCH v2 09/19] fbcon: Extract fbcon_open/release helpers
Hi
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
There's two minor behaviour changes in here:
- in error paths we now consistently call fb_ops->fb_release
- fb_release really can't fail (fbmem.c ignores it too) and there's no
reasonable cleanup we can do anyway.
Note that everything in fbcon.c is protected by the big console_lock()
lock (especially all the global variables), so the minor changes in
ordering of setup/cleanup do not matter.
v2: Explain a bit better why this is all correct (Sam)
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Daniel Vetter
Cc: Claudio Suarez
Cc: Greg Kroah-Hartman
Cc: Tetsuo Handa
Cc: Du Cheng
---
drivers/video/fbdev/core/fbcon.c | 107 +++
1 file changed, 53 insertions(+), 54 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 058e885d24f6..3e1a3e7bf527 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -682,19 +682,37 @@ static int fbcon_invalid_charcount(struct fb_info *info,
unsigned charcount)
#endif /* CONFIG_MISC_TILEBLITTING */
+static int fbcon_open(struct fb_info *info)
+{
+ if (!try_module_get(info->fbops->owner))
+ return -ENODEV;
+
+ if (info->fbops->fb_open &&
+ info->fbops->fb_open(info, 0)) {
+ module_put(info->fbops->owner);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static void fbcon_release(struct fb_info *info)
+{
+ if (info->fbops->fb_release)
+ info->fbops->fb_release(info, 0);
+
+ module_put(info->fbops->owner);
+}
static int con2fb_acquire_newinfo(struct vc_data *vc, struct fb_info *info,
int unit, int oldidx)
{
struct fbcon_ops *ops = NULL;
- int err = 0;
-
- if (!try_module_get(info->fbops->owner))
- err = -ENODEV;
+ int err;
- if (!err && info->fbops->fb_open &&
- info->fbops->fb_open(info, 0))
- err = -ENODEV;
+ err = fbcon_open(info);
+ if (err)
+ return err;
if (!err) {
ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
@@ -715,7 +733,7 @@ static int con2fb_acquire_newinfo(struct vc_data *vc,
struct fb_info *info,
if (err) {
con2fb_map[unit] = oldidx;
- module_put(info->fbops->owner);
+ fbcon_release(info);
}
return err;
@@ -726,45 +744,34 @@ static int con2fb_release_oldinfo(struct vc_data *vc,
struct fb_info *oldinfo,
int oldidx, int found)
{
struct fbcon_ops *ops = oldinfo->fbcon_par;
- int err = 0, ret;
+ int ret;
- if (oldinfo->fbops->fb_release &&
- oldinfo->fbops->fb_release(oldinfo, 0)) {
- con2fb_map[unit] = oldidx;
We don't need oldidx any longer?
There's some logic wrt to the parameter 'found' here and in
set_con2fb_map() that appears to be relevant.
Best regards
Thomas
- if (!found && newinfo->fbops->fb_release)
- newinfo->fbops->fb_release(newinfo, 0);
- if (!found)
- module_put(newinfo->fbops->owner);
- err = -ENODEV;
- }
+ fbcon_release(oldinfo);
- if (!err) {
- fbcon_del_cursor_work(oldinfo);
- kfree(ops->cursor_state.mask);
- kfree(ops->cursor_data);
- kfree(ops->cursor_src);
- kfree(ops->fontbuffer);
- kfree(oldinfo->fbcon_par);
- oldinfo->fbcon_par = NULL;
- module_put(oldinfo->fbops->owner);
- /*
- If oldinfo and newinfo are driving the same hardware,
- the fb_release() method of oldinfo may attempt to
- restore the hardware state. This will leave the
- newinfo in an undefined state. Thus, a call to
- fb_set_par() may be needed for the newinfo.
- */
- if (newinfo && newinfo->fbops->fb_set_par) {
- ret = newinfo->fbops->fb_set_par(newinfo);
+ fbcon_del_cursor_work(oldinfo);
+ kfree(ops->cursor_state.mask);
+ kfree(ops->cursor_data);
+ kfree(ops->cursor_src);
+ kfree(ops->fontbuffer);
+ kfree(oldinfo->fbcon_par);
+ oldinfo->fbcon_par = NULL;
+ /*
+ If oldinfo and newinfo are driving the same hardware,
+ the fb_release() method of oldinfo may attempt to
+ restore the hardware state. This will leave the
+ newinfo in an undefined state. Thus, a call to
+ fb_set_par() may be needed for the newinfo.
+ */
+ if (newinfo && newinfo->fbops->fb_set_par) {
+ ret = newinfo->fbops->fb_set_par(newinfo);
- if (ret)
- printk(KERN_ERR "con2fb_release_oldinfo: "
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher optimize plane updates (rev4)
== Series Details ==
Series: drm/i915: Futher optimize plane updates (rev4)
URL : https://patchwork.freedesktop.org/series/99149/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11211 -> Patchwork_22237
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/index.html
Participating hosts (47 -> 43)
--
Missing(4): fi-bsw-cyan fi-pnv-d510 shard-tglu bat-dg1-5
Known issues
Here are the changes found in Patchwork_22237 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][2] -> [INCOMPLETE][3] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
- fi-bdw-5557u: [PASS][4] -> [INCOMPLETE][5] ([i915#146])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][6] -> [INCOMPLETE][7] ([i915#3303])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] /
[i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][11] ([i915#4269]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
Build changes
-
* Linux: CI_DRM_11211 -> Patchwork_22237
CI-20190529: 20190529
CI_DRM_11211: 6b5e0f742803676e8494c3c271cc7d2cf31d6413 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22237: c889ad1dd83b85c8969047e60f5a6645584b505c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c889ad1dd83b drm/i915: Make pre-skl sprite plane registers unlocked
8cd109922365 drm/i915: Make most pre-skl primary plane registers unlocked
f47e2e98562b drm/i915: Make cursor plane registers unlocked
928940a98d5a drm/i915: Make skl+ universal plane registers unlocked
ee284be638cf drm/i915: Optimize icl+ universal plane programming
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/index.html
Re: [Intel-gfx] [PATCH v2 06/19] fbcon: Use delayed work for cursor
On 2022/02/09 6:08, Daniel Vetter wrote:
> @@ -714,6 +700,8 @@ static int con2fb_acquire_newinfo(struct vc_data *vc,
> struct fb_info *info,
> ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
> if (!ops)
> err = -ENOMEM;
> +
> + INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
> }
>
> if (!err) {
Memory allocation fault injection will hit NULL pointer dereference.
[Intel-gfx] [PATCH v2 00/15] Initial support for small BAR recovery
Starting from DG2 we will have resizable BAR support for device local-memory, but in some cases the final BAR size might still be smaller than the total local-memory size. In such cases only part of local-memory will be CPU accessible, while the remainder is only accessible via the GPU. This series adds the basic enablers needed to ensure that the entire local-memory range is usable. Needs to be applied on top of Arun' in-progress series[1]. [1] https://patchwork.freedesktop.org/series/99430/ v2: - Various improvements and fixes as suggested by Thomas. -- 2.34.1
[Intel-gfx] [PATCH v2 01/15] drm/i915: add io_size plumbing
With small LMEM-BAR we need to be able to differentiate between the
total size of LMEM, and how much of it is CPU mappable. The end goal is
to be able to utilize the entire range, even if part of is it not CPU
accessible.
v2: also update intelfb_create
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 +-
drivers/gpu/drm/i915/intel_memory_region.c | 6 +-
drivers/gpu/drm/i915/intel_memory_region.h | 2 ++
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 8
drivers/gpu/drm/i915/selftests/mock_region.c | 6 --
drivers/gpu/drm/i915/selftests/mock_region.h | 3 ++-
11 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 41d279db2be6..244acf462065 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -248,7 +248,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct intel_memory_region *mem = obj->mm.region;
info->apertures->ranges[0].base = mem->io_start;
- info->apertures->ranges[0].size = mem->total;
+ info->apertures->ranges[0].size = mem->io_size;
/* Use fbdev's framebuffer from lmem for discrete */
info->fix.smem_start =
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 6c57b0a79c8a..a9aca11cedbb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -696,7 +696,7 @@ struct intel_memory_region *i915_gem_shmem_setup(struct
drm_i915_private *i915,
{
return intel_memory_region_create(i915, 0,
totalram_pages() << PAGE_SHIFT,
- PAGE_SIZE, 0,
+ PAGE_SIZE, 0, 0,
type, instance,
&shmem_region_ops);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 1de73a644965..b79f5f5e7df0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -491,6 +491,7 @@ static int i915_gem_init_stolen(struct intel_memory_region
*mem)
/* Exclude the reserved region from driver use */
mem->region.end = reserved_base - 1;
+ mem->io_size = resource_size(&mem->region);
/* It is possible for the reserved area to end before the end of stolen
* memory, so just consider the start. */
@@ -747,7 +748,7 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
if (!io_mapping_init_wc(&mem->iomap,
mem->io_start,
- resource_size(&mem->region)))
+ mem->io_size))
return -EIO;
/*
@@ -802,7 +803,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
-min_page_size, io_start,
+min_page_size,
+io_start, lmem_size,
type, instance,
&i915_region_stolen_lmem_ops);
if (IS_ERR(mem))
@@ -833,7 +835,7 @@ i915_gem_stolen_smem_setup(struct drm_i915_private *i915,
u16 type,
mem = intel_memory_region_create(i915,
intel_graphics_stolen_res.start,
resource_size(&intel_graphics_stolen_res),
-PAGE_SIZE, 0, type, instance,
+PAGE_SIZE, 0, 0, type, instance,
&i915_region_stolen_smem_ops);
if (IS_ERR(mem))
return mem;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 1eb2fd81c5b6..e9399f7b3e67 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1101,7 +1101,7 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
mr = intel_memory_region_create(i915, 0,
totalram_pages() << PAGE_SHIFT,
-
[Intel-gfx] [PATCH v2 02/15] drm/i915/ttm: require mappable by default
On devices with non-mappable LMEM ensure we always allocate the pages
within the mappable portion. For now we assume that all LMEM buffers
will require CPU access, which is also inline with pretty much all
current kernel internal users. In the next patch we will introduce a new
flag to override this behaviour.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 4
drivers/gpu/drm/i915/intel_region_ttm.c | 5 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index e9399f7b3e67..41e94d09e742 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -128,6 +128,10 @@ i915_ttm_place_from_region(const struct
intel_memory_region *mr,
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ if (mr->io_size && mr->io_size < mr->total) {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
static void
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915/intel_region_ttm.c
index f2b888c16958..4689192d5e8d 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -199,6 +199,11 @@ intel_region_ttm_resource_alloc(struct intel_memory_region
*mem,
struct ttm_resource *res;
int ret;
+ if (mem->io_size && mem->io_size < mem->total) {
+ place.fpfn = 0;
+ place.lpfn = mem->io_size >> PAGE_SHIFT;
+ }
+
mock_bo.base.size = size;
place.flags = flags;
--
2.34.1
[Intel-gfx] [PATCH v2 03/15] drm/i915: add I915_BO_ALLOC_GPU_ONLY
If the user doesn't require CPU access for the buffer, then
ALLOC_GPU_ONLY should be used, in order to prioritise allocating in the
non-mappable portion of LMEM, on devices with small BAR.
v2(Thomas):
- The BO_ALLOC_TOPDOWN naming here is poor, since this is pure lies on
systems that don't even have small BAR. A better name is GPU_ONLY,
which is accurate regardless of the configuration.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_object_types.h| 17 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 5 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 ++---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/i915_vma.c | 3 +++
drivers/gpu/drm/i915/intel_region_ttm.c | 11 ---
drivers/gpu/drm/i915/selftests/mock_region.c| 7 +--
8 files changed, 45 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0098a32490f0..fd54eb8f4826 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -319,16 +319,23 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
/* Object needs to be restored early using memcpy during resume */
#define I915_BO_ALLOC_PM_EARLYBIT(5)
+/*
+ * Object is likely never accessed by the CPU. This will prioritise the BO to
be
+ * allocated in the non-mappable portion of lmem. This is merely a hint, and if
+ * dealing with userspace objects the CPU fault handler is free to ignore this.
+ */
+#define I915_BO_ALLOC_GPU_ONLY BIT(6)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
I915_BO_ALLOC_PM_VOLATILE | \
-I915_BO_ALLOC_PM_EARLY)
-#define I915_BO_READONLY BIT(6)
-#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(8)
-#define I915_BO_WAS_BOUND_BIT 9
+I915_BO_ALLOC_PM_EARLY | \
+I915_BO_ALLOC_GPU_ONLY)
+#define I915_BO_READONLY BIT(7)
+#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(9)
+#define I915_BO_WAS_BOUND_BIT 10
/**
* @mem_flags - Mutable placement-related flags
*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 060fe29f5929..a4d8dc163691 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -356,6 +356,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
!i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
+ if (WARN_ON_ONCE(obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ return ERR_PTR(-EINVAL);
+
assert_object_held(obj);
pinned = !(type & I915_MAP_OVERRIDE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index a4350227e9ae..873d52f872c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -45,6 +45,11 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+ if (WARN_ON_ONCE(flags & I915_BO_ALLOC_GPU_ONLY &&
+(flags & I915_BO_ALLOC_CPU_CLEAR ||
+ flags & I915_BO_ALLOC_PM_EARLY)))
+ return ERR_PTR(-EINVAL);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 41e94d09e742..36e77fcf2ef9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -127,10 +127,14 @@ i915_ttm_place_from_region(const struct
intel_memory_region *mr,
place->mem_type = intel_region_to_ttm_type(mr);
if (flags & I915_BO_ALLOC_CONTIGUOUS)
- place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mr->io_size && mr->io_size < mr->total) {
- place->fpfn = 0;
- place->lpfn = mr->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_GPU_ONLY) {
+ place->flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
}
@@ -888,6 +892,9 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
[Intel-gfx] [PATCH v2 04/15] drm/i915/buddy: track available visible size
Track the total amount of available visible memory, and also track
per-resource the amount of used visible memory. For now this is useful
for our debug output, and deciding if it is even worth calling into the
buddy allocator. In the future tracking the per-resource visible usage
will be useful for when deciding if we should attempt to evict certain
buffers.
v2:
- s/place->lpfn/lpfn/, that way we can avoid scanning the list if the
entire range is already mappable.
- Move the end declaration inside the if block(Thomas).
- Make sure to also account for reserved memory.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 68 ++-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 8 ++-
drivers/gpu/drm/i915/intel_region_ttm.c | 1 +
3 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 76d5211c25eb..e47a3d46c6ff 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -19,6 +19,9 @@ struct i915_ttm_buddy_manager {
struct drm_buddy mm;
struct list_head reserved;
struct mutex lock;
+ unsigned long visible_size;
+ unsigned long visible_avail;
+ unsigned long visible_reserved;
u64 default_page_size;
};
@@ -87,6 +90,12 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
n_pages = size >> ilog2(mm->chunk_size);
mutex_lock(&bman->lock);
+ if (lpfn <= bman->visible_size && n_pages > bman->visible_avail) {
+ mutex_unlock(&bman->lock);
+ err = -ENOSPC;
+ goto err_free_res;
+ }
+
err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
(u64)lpfn << PAGE_SHIFT,
(u64)n_pages << PAGE_SHIFT,
@@ -107,6 +116,31 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
mutex_unlock(&bman->lock);
}
+ if (lpfn <= bman->visible_size) {
+ bman_res->used_visible_size = bman_res->base.num_pages;
+ } else {
+ struct drm_buddy_block *block;
+
+ list_for_each_entry(block, &bman_res->blocks, link) {
+ unsigned long start =
+ drm_buddy_block_offset(block) >> PAGE_SHIFT;
+
+ if (start < bman->visible_size) {
+ unsigned long end = start +
+ (drm_buddy_block_size(mm, block) >>
PAGE_SHIFT);
+
+ bman_res->used_visible_size +=
+ min(end, bman->visible_size) - start;
+ }
+ }
+ }
+
+ if (bman_res->used_visible_size) {
+ mutex_lock(&bman->lock);
+ bman->visible_avail -= bman_res->used_visible_size;
+ mutex_unlock(&bman->lock);
+ }
+
*res = &bman_res->base;
return 0;
@@ -128,6 +162,7 @@ static void i915_ttm_buddy_man_free(struct
ttm_resource_manager *man,
mutex_lock(&bman->lock);
drm_buddy_free_list(&bman->mm, &bman_res->blocks);
+ bman->visible_avail += bman_res->used_visible_size;
mutex_unlock(&bman->lock);
ttm_resource_fini(man, res);
@@ -143,6 +178,12 @@ static void i915_ttm_buddy_man_debug(struct
ttm_resource_manager *man,
mutex_lock(&bman->lock);
drm_printf(printer, "default_page_size: %lluKiB\n",
bman->default_page_size >> 10);
+ drm_printf(printer, "visible_avail: %lluMiB\n",
+ (u64)bman->visible_avail << PAGE_SHIFT >> 20);
+ drm_printf(printer, "visible_size: %lluMiB\n",
+ (u64)bman->visible_size << PAGE_SHIFT >> 20);
+ drm_printf(printer, "visible_reserved: %lluMiB\n",
+ (u64)bman->visible_reserved << PAGE_SHIFT >> 20);
drm_buddy_print(&bman->mm, printer);
@@ -164,6 +205,7 @@ static const struct ttm_resource_manager_func
i915_ttm_buddy_manager_func = {
* @type: Memory type we want to manage
* @use_tt: Set use_tt for the manager
* @size: The size in bytes to manage
+ * @visible_size: The CPU visible size in bytes to manage
* @default_page_size: The default minimum page size in bytes for allocations,
* this must be at least as large as @chunk_size, and can be overridden by
* setting the BO page_alignment, to be larger or smaller as needed.
@@ -187,7 +229,7 @@ static const struct ttm_resource_manager_func
i915_ttm_buddy_manager_func = {
*/
int i915_ttm_buddy_man_init(struct ttm_device *bdev,
unsigned int type, bool use_tt,
- u64 size, u64 default_page_size,
+ u64 size, u64 visible_size, u64 default_p
[Intel-gfx] [PATCH v2 07/15] drm/i915/selftests: mock test io_size
Check that mappable vs non-mappable matches our expectations.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
.../drm/i915/selftests/intel_memory_region.c | 143 ++
1 file changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 247f65f02bbf..56dec9723601 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -17,6 +17,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_engine_pm.h"
@@ -512,6 +513,147 @@ static int igt_mock_max_segment(void *arg)
return err;
}
+static u64 igt_object_mappable_total(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = obj->mm.region;
+ struct i915_ttm_buddy_resource *bman_res =
+ to_ttm_buddy_resource(obj->mm.res);
+ struct drm_buddy *mm = bman_res->mm;
+ struct drm_buddy_block *block;
+ u64 total;
+
+ total = 0;
+ list_for_each_entry(block, &bman_res->blocks, link) {
+ u64 start = drm_buddy_block_offset(block);
+ u64 end = start + drm_buddy_block_size(mm, block);
+
+ if (start < mr->io_size)
+ total += min_t(u64, end, mr->io_size) - start;
+ }
+
+ return total;
+}
+
+static int igt_mock_io_size(void *arg)
+{
+ struct intel_memory_region *mr = arg;
+ struct drm_i915_private *i915 = mr->i915;
+ struct drm_i915_gem_object *obj;
+ u64 mappable_theft_total;
+ u64 io_size;
+ u64 total;
+ u64 ps;
+ u64 rem;
+ u64 size;
+ I915_RND_STATE(prng);
+ LIST_HEAD(objects);
+ int err = 0;
+
+ ps = SZ_4K;
+ if (i915_prandom_u64_state(&prng) & 1)
+ ps = SZ_64K; /* For something like DG2 */
+
+ div64_u64_rem(i915_prandom_u64_state(&prng), SZ_8G, &total);
+ total = round_down(total, ps);
+ total = max_t(u64, total, SZ_1G);
+
+ div64_u64_rem(i915_prandom_u64_state(&prng), total - ps, &io_size);
+ io_size = round_down(io_size, ps);
+ io_size = max_t(u64, io_size, SZ_256M); /* 256M seems to be the common
lower limit */
+
+ pr_info("%s with ps=%llx, io_size=%llx, total=%llx\n",
+ __func__, ps, io_size, total);
+
+ mr = mock_region_create(i915, 0, total, ps, 0, io_size);
+ if (IS_ERR(mr)) {
+ err = PTR_ERR(mr);
+ goto out_err;
+ }
+
+ mappable_theft_total = 0;
+ rem = total - io_size;
+ do {
+ div64_u64_rem(i915_prandom_u64_state(&prng), rem, &size);
+ size = round_down(size, ps);
+ size = max(size, ps);
+
+ obj = igt_object_create(mr, &objects, size,
+ I915_BO_ALLOC_GPU_ONLY);
+ if (IS_ERR(obj)) {
+ pr_err("%s TOPDOWN failed with rem=%llx, size=%llx\n",
+ __func__, rem, size);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ mappable_theft_total += igt_object_mappable_total(obj);
+ rem -= size;
+ } while (rem);
+
+ pr_info("%s mappable theft=(%lluMiB/%lluMiB), total=%lluMiB\n",
+ __func__,
+ (u64)mappable_theft_total >> 20,
+ (u64)io_size >> 20,
+ (u64)total >> 20);
+
+ /*
+* Even if we allocate all of the non-mappable portion, we should still
+* be able to dip into the mappable portion.
+*/
+ obj = igt_object_create(mr, &objects, io_size,
+ I915_BO_ALLOC_GPU_ONLY);
+ if (IS_ERR(obj)) {
+ pr_err("%s allocation unexpectedly failed\n", __func__);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ close_objects(mr, &objects);
+
+ rem = io_size;
+ do {
+ div64_u64_rem(i915_prandom_u64_state(&prng), rem, &size);
+ size = round_down(size, ps);
+ size = max(size, ps);
+
+ obj = igt_object_create(mr, &objects, size, 0);
+ if (IS_ERR(obj)) {
+ pr_err("%s MAPPABLE failed with rem=%llx, size=%llx\n",
+ __func__, rem, size);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ if (igt_object_mappable_total(obj) != size) {
+ pr_err("%s allocation is not mappable(size=%llx)\n",
+ __func__, size);
+ err = -EINVAL;
+
[Intel-gfx] [PATCH v2 11/15] drm/i915/selftests: handle allocation failures
If we have to contend with non-mappable LMEM, then we need to ensure the
object fits within the mappable portion, like in the selftests, where we
later try to CPU access the pages. However if it can't then we need to
gracefully handle this, without throwing an error.
Also it looks like TTM will return -ENOMEM, in ttm_bo_mem_space() after
exhausting all possible placements.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 8 +++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 42db9cd30978..3caa178bbd07 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1344,7 +1344,7 @@ static int igt_ppgtt_smoke_huge(void *arg)
err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
- if (err == -ENXIO || err == -E2BIG) {
+ if (err == -ENXIO || err == -E2BIG || err == -ENOMEM) {
i915_gem_object_put(obj);
size >>= 1;
goto try_again;
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 56dec9723601..ba32893e0873 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -822,8 +822,14 @@ static int igt_lmem_create_with_ps(void *arg)
i915_gem_object_lock(obj, NULL);
err = i915_gem_object_pin_pages(obj);
- if (err)
+ if (err) {
+ if (err == -ENXIO || err == -E2BIG || err == -ENOMEM) {
+ pr_info("%s not enough lmem for ps(%u)
err=%d\n",
+ __func__, ps, err);
+ err = 0;
+ }
goto out_put;
+ }
daddr = i915_gem_object_get_dma_address(obj, 0);
if (!IS_ALIGNED(daddr, ps)) {
--
2.34.1
[Intel-gfx] [PATCH v2 06/15] drm/i915/buddy: tweak 2big check
Otherwise we get -EINVAL, instead of the more useful -E2BIG if the
allocation doesn't fit within the pfn range, like with mappable lmem.
The hugepages selftest, for example, needs this to know if a smaller
size is needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 0ac6b2463fd5..92d49a3c378c 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -82,7 +82,7 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
lpfn = pages;
}
- if (size > mm->size) {
+ if (size > lpfn << PAGE_SHIFT) {
err = -E2BIG;
goto err_free_res;
}
--
2.34.1
[Intel-gfx] [PATCH v2 08/15] drm/i915/ttm: make eviction mappable aware
If we need to make room for some mappable object, then we should
only victimize objects that have one or pages that occupy the visible
portion of LMEM. Let's also create a new priority hint for objects that
are placed in mappable memory, where we know that CPU access was
requested, that way we hopefully victimize these last.
v2(Thomas): s/TTM_PL_PRIV/I915_PL_LMEM0/
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 65 -
1 file changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 36e77fcf2ef9..3790e569d6a9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -5,8 +5,10 @@
#include
#include
+#include
#include "i915_drv.h"
+#include "i915_ttm_buddy_manager.h"
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
@@ -20,6 +22,7 @@
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
#define I915_TTM_PRIO_HAS_PAGES 2
+#define I915_TTM_PRIO_NEEDS_CPU_ACCESS 3
/*
* Size of struct ttm_place vector in on-stack struct ttm_placement allocs
@@ -337,6 +340,7 @@ static bool i915_ttm_eviction_valuable(struct
ttm_buffer_object *bo,
const struct ttm_place *place)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct ttm_resource *res = bo->resource;
if (!obj)
return false;
@@ -350,7 +354,48 @@ static bool i915_ttm_eviction_valuable(struct
ttm_buffer_object *bo,
return false;
/* Will do for now. Our pinned objects are still on TTM's LRU lists */
- return i915_gem_object_evictable(obj);
+ if (!i915_gem_object_evictable(obj))
+ return false;
+
+ switch (res->mem_type) {
+ case I915_PL_LMEM0: {
+ struct ttm_resource_manager *man =
+ ttm_manager_type(bo->bdev, res->mem_type);
+ struct i915_ttm_buddy_resource *bman_res =
+ to_ttm_buddy_resource(res);
+ struct drm_buddy *mm = bman_res->mm;
+ struct drm_buddy_block *block;
+
+ if (!place->fpfn && !place->lpfn)
+ return true;
+
+ GEM_BUG_ON(!place->lpfn);
+
+ /*
+* If we just want something mappable then we can quickly check
+* if the current victim resource is using any of the CPU
+* visible portion.
+*/
+ if (!place->fpfn &&
+ place->lpfn == i915_ttm_buddy_man_visible_size(man))
+ return bman_res->used_visible_size > 0;
+
+ /* Real range allocation */
+ list_for_each_entry(block, &bman_res->blocks, link) {
+ unsigned long fpfn =
+ drm_buddy_block_offset(block) >> PAGE_SHIFT;
+ unsigned long lpfn = fpfn +
+ (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
+
+ if (place->fpfn < lpfn && place->lpfn > fpfn)
+ return true;
+ }
+ return false;
+ } default:
+ break;
+ }
+
+ return true;
}
static void i915_ttm_evict_flags(struct ttm_buffer_object *bo,
@@ -850,7 +895,23 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj)
} else if (!i915_gem_object_has_pages(obj)) {
bo->priority = I915_TTM_PRIO_NO_PAGES;
} else {
- bo->priority = I915_TTM_PRIO_HAS_PAGES;
+ struct ttm_resource_manager *man =
+ ttm_manager_type(bo->bdev, bo->resource->mem_type);
+
+ /*
+* If we need to place an LMEM resource which doesn't need CPU
+* access then we should try not to victimize mappable objects
+* first, since we likely end up stealing more of the mappable
+* portion. And likewise when we try to find space for a mappble
+* object, we know not to ever victimize objects that don't
+* occupy any mappable pages.
+*/
+ if (i915_ttm_cpu_maps_iomem(bo->resource) &&
+ i915_ttm_buddy_man_visible_size(man) < man->size &&
+ !(obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ bo->priority = I915_TTM_PRIO_NEEDS_CPU_ACCESS;
+ else
+ bo->priority = I915_TTM_PRIO_HAS_PAGES;
}
ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);
--
2.34.1
[Intel-gfx] [PATCH v2 09/15] drm/i915/ttm: mappable migration on fault
The end goal is to have userspace tell the kernel what buffers will
require CPU access, however if we ever reach the CPU fault handler, and
the current resource is not mappable, then we should attempt to migrate
the buffer to the mappable portion of LMEM, or even system memory, if the
allowable placements permit it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 54 ++---
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 3790e569d6a9..780513e98fdc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -636,11 +636,24 @@ static void i915_ttm_swap_notify(struct ttm_buffer_object
*bo)
i915_ttm_purge(obj);
}
+static bool i915_ttm_resource_mappable(struct ttm_resource *res)
+{
+ struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+
+ if (!i915_ttm_cpu_maps_iomem(res))
+ return true;
+
+ return bman_res->used_visible_size == bman_res->base.num_pages;
+}
+
static int i915_ttm_io_mem_reserve(struct ttm_device *bdev, struct
ttm_resource *mem)
{
if (!i915_ttm_cpu_maps_iomem(mem))
return 0;
+ if (!i915_ttm_resource_mappable(mem))
+ return -EINVAL;
+
mem->bus.caching = ttm_write_combined;
mem->bus.is_iomem = true;
@@ -779,14 +792,15 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object
*obj)
* Gem forced migration using the i915_ttm_migrate() op, is allowed even
* to regions that are not in the object's list of allowable placements.
*/
-static int i915_ttm_migrate(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mr)
+static int __i915_ttm_migrate(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr,
+ unsigned int flags)
{
struct ttm_place requested;
struct ttm_placement placement;
int ret;
- i915_ttm_place_from_region(mr, &requested, obj->flags);
+ i915_ttm_place_from_region(mr, &requested, flags);
placement.num_placement = 1;
placement.num_busy_placement = 1;
placement.placement = &requested;
@@ -809,6 +823,12 @@ static int i915_ttm_migrate(struct drm_i915_gem_object
*obj,
return 0;
}
+static int i915_ttm_migrate(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr)
+{
+ return __i915_ttm_migrate(obj, mr, obj->flags);
+}
+
static void i915_ttm_put_pages(struct drm_i915_gem_object *obj,
struct sg_table *st)
{
@@ -953,9 +973,6 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
- if (obj->flags & I915_BO_ALLOC_GPU_ONLY)
- return -EINVAL;
-
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
@@ -970,6 +987,31 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
return VM_FAULT_SIGBUS;
}
+ if (!i915_ttm_resource_mappable(bo->resource)) {
+ int err = -ENODEV;
+ int i;
+
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ struct intel_memory_region *mr = obj->mm.placements[i];
+ unsigned int flags;
+
+ if (!mr->io_size && mr->type != INTEL_MEMORY_SYSTEM)
+ continue;
+
+ flags = obj->flags;
+ flags &= ~I915_BO_ALLOC_TOPDOWN;
+ err = __i915_ttm_migrate(obj, mr, flags);
+ if (!err)
+ break;
+ }
+
+ if (err) {
+ drm_dbg(dev, "Unable to make resource CPU
accessible\n");
+ dma_resv_unlock(bo->base.resv);
+ return VM_FAULT_SIGBUS;
+ }
+ }
+
if (drm_dev_enter(dev, &idx)) {
ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
TTM_BO_VM_NUM_PREFAULT);
--
2.34.1
[Intel-gfx] [PATCH v2 12/15] drm/i915/create: apply ALLOC_GPU_ONLY by default
Starting from DG2+, when dealing with LMEM, we assume that by default all userspace allocations should be placed in the non-mappable portion of LMEM. Note that dumb buffers are not included here, since these are not "GPU accelerated" and likely need CPU access. In a later patch userspace will be able to provide a hint if CPU access to the buffer is needed. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 9402d4bf4ffc..cc9ddb943f96 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -424,6 +424,15 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements = 1; } + /* +* TODO: add a userspace hint to force CPU_ACCESS for the object, which +* can override this. +*/ + if (!IS_DG1(i915) && (ext_data.n_placements > 1 || + ext_data.placements[0]->type != + INTEL_MEMORY_SYSTEM)) + ext_data.flags |= I915_BO_ALLOC_GPU_ONLY; + obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements, ext_data.n_placements, -- 2.34.1
[Intel-gfx] [PATCH v2 05/15] drm/i915/buddy: adjust res->start
Differentiate between mappable vs non-mappable resources, also if this is an actual range allocation ensure we set res->start as the starting pfn. Later when we need to do non-mappable -> mappable moves then we want TTM to see that the current placement is not compatible, which should result in an actual move, instead of being turned into a noop. Signed-off-by: Matthew Auld Cc: Thomas Hellström Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c index e47a3d46c6ff..0ac6b2463fd5 100644 --- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c @@ -141,6 +141,13 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource_manager *man, mutex_unlock(&bman->lock); } + if (place->lpfn - place->fpfn == n_pages) + bman_res->base.start = place->fpfn; + else if (lpfn <= bman->visible_size) + bman_res->base.start = 0; + else + bman_res->base.start = bman->visible_size; + *res = &bman_res->base; return 0; -- 2.34.1
[Intel-gfx] [PATCH v2 10/15] drm/i915/selftests: exercise mmap migration
Exercise each of the migration scenarios, verifying that the final
placement and buffer contents match our expectations.
v2(Thomas): Replace for_i915_gem_ww() block with simpler object_lock()
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 304 ++
2 files changed, 305 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 780513e98fdc..7940dfec1d56 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -999,7 +999,7 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
continue;
flags = obj->flags;
- flags &= ~I915_BO_ALLOC_TOPDOWN;
+ flags &= ~I915_BO_ALLOC_GPU_ONLY;
err = __i915_ttm_migrate(obj, mr, flags);
if (!err)
break;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index ba29767348be..7a73a0b015b9 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -10,6 +10,7 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_migrate.h"
#include "gem/i915_gem_region.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
@@ -999,6 +1000,308 @@ static int igt_mmap(void *arg)
return 0;
}
+static void igt_close_objects(struct drm_i915_private *i915,
+ struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj, *on;
+
+ list_for_each_entry_safe(obj, on, objects, st_link) {
+ i915_gem_object_lock(obj, NULL);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+ /* No polluting the memory region between tests */
+ __i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
+ list_del(&obj->st_link);
+ i915_gem_object_put(obj);
+ }
+
+ cond_resched();
+
+ i915_gem_drain_freed_objects(i915);
+}
+
+static void igt_make_evictable(struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj;
+
+ list_for_each_entry(obj, objects, st_link) {
+ i915_gem_object_lock(obj, NULL);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_unlock(obj);
+ }
+
+ cond_resched();
+}
+
+static int igt_fill_mappable(struct intel_memory_region *mr,
+struct list_head *objects)
+{
+ u64 size, total;
+ int err;
+
+ total = 0;
+ size = mr->io_size;
+ do {
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_region(mr, size, 0, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_close;
+ }
+
+ list_add(&obj->st_link, objects);
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ if (err != -ENXIO && err != -ENOMEM)
+ goto err_close;
+
+ if (size == mr->min_page_size) {
+ err = 0;
+ break;
+ }
+
+ size >>= 1;
+ continue;
+ }
+
+ total += obj->base.size;
+ } while (1);
+
+ pr_info("%s filled=%lluMiB\n", __func__, total >> 20);
+ return 0;
+
+err_close:
+ igt_close_objects(mr->i915, objects);
+ return err;
+}
+
+static int ___igt_mmap_migrate(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ unsigned long addr,
+ bool unfaultable)
+{
+ struct vm_area_struct *area;
+ int err = 0, i;
+
+ pr_info("igt_mmap(%s, %d) @ %lx\n",
+ obj->mm.region->name, I915_MMAP_TYPE_FIXED, addr);
+
+ mmap_read_lock(current->mm);
+ area = vma_lookup(current->mm, addr);
+ mmap_read_unlock(current->mm);
+ if (!area) {
+ pr_err("%s: Did not create a vm_area_struct for the mmap\n",
+ obj->mm.region->name);
+ err = -EINVAL;
+ goto out_unmap;
+ }
+
+ for (i = 0; i < obj->base.size / sizeof(u32); i++) {
+ u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));
+ u32 x;
+
+ if (get_user(x, ux)) {
+ err = -
[Intel-gfx] [PATCH v2 14/15] drm/i915/uapi: forbid ALLOC_GPU_ONLY for error capture
On platforms where there might be non-mappable LMEM, force userspace to
mark the buffers with the correct hint. When dumping the BO contents
during capture we need CPU access. Note this only applies to buffers
that can be placed in LMEM, and also doesn't impact DG1.
v2(Reported-by: kernel test robot ):
- Also update the function signature on !CONFIG_DRM_I915_CAPTURE_ERROR
builds.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..017f928cbcaf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1965,7 +1965,7 @@ eb_find_first_request_added(struct i915_execbuffer *eb)
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
/* Stage with GFP_KERNEL allocations before we enter the signaling critical
path */
-static void eb_capture_stage(struct i915_execbuffer *eb)
+static int eb_capture_stage(struct i915_execbuffer *eb)
{
const unsigned int count = eb->buffer_count;
unsigned int i = count, j;
@@ -1978,6 +1978,9 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
if (!(flags & EXEC_OBJECT_CAPTURE))
continue;
+ if (vma->obj->flags & I915_BO_ALLOC_GPU_ONLY)
+ return -EINVAL;
+
for_each_batch_create_order(eb, j) {
struct i915_capture_list *capture;
@@ -1990,6 +1993,8 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
eb->capture_lists[j] = capture;
}
}
+
+ return 0;
}
/* Commit once we're in the critical path */
@@ -2031,7 +2036,7 @@ static void eb_capture_list_clear(struct i915_execbuffer
*eb)
#else
-static void eb_capture_stage(struct i915_execbuffer *eb)
+static int eb_capture_stage(struct i915_execbuffer *eb)
{
}
@@ -3418,7 +3423,9 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
ww_acquire_done(&eb.ww.ctx);
- eb_capture_stage(&eb);
+ err = eb_capture_stage(&eb);
+ if (err)
+ goto err_vma;
out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
if (IS_ERR(out_fence)) {
--
2.34.1
[Intel-gfx] [PATCH v2 13/15] drm/i915/uapi: add NEEDS_CPU_ACCESS hint
If set, force the allocation to be placed in the mappable portion of
LMEM. One big restriction here is that system memory must be given as a
potential placement for the object, that way we can always spill the
object into system memory if we can't make space.
XXX: Still very much WIP and needs IGTs. Including now just for the sake
of having more complete picture.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 28 ---
include/uapi/drm/i915_drm.h| 31 +-
2 files changed, 49 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index cc9ddb943f96..2737977f81a4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -238,6 +238,7 @@ struct create_ext {
struct drm_i915_private *i915;
struct intel_memory_region *placements[INTEL_REGION_UNKNOWN];
unsigned int n_placements;
+ unsigned int placement_mask;
unsigned long flags;
};
@@ -334,6 +335,7 @@ static int set_placements(struct
drm_i915_gem_create_ext_memory_regions *args,
for (i = 0; i < args->num_regions; i++)
ext_data->placements[i] = placements[i];
+ ext_data->placement_mask = mask;
return 0;
out_dump:
@@ -408,7 +410,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_gem_object *obj;
int ret;
- if (args->flags)
+ if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
@@ -424,14 +426,22 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void
*data,
ext_data.n_placements = 1;
}
- /*
-* TODO: add a userspace hint to force CPU_ACCESS for the object, which
-* can override this.
-*/
- if (!IS_DG1(i915) && (ext_data.n_placements > 1 ||
- ext_data.placements[0]->type !=
- INTEL_MEMORY_SYSTEM))
- ext_data.flags |= I915_BO_ALLOC_GPU_ONLY;
+ if (args->flags & I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS) {
+ if (ext_data.n_placements == 1)
+ return -EINVAL;
+
+ /*
+* We always need to be able to spill to system memory, if we
+* can't place in the mappable part of LMEM.
+*/
+ if (!(ext_data.placement_mask & BIT(INTEL_REGION_SMEM)))
+ return -EINVAL;
+ } else {
+ if (!IS_DG1(i915) && (ext_data.n_placements > 1 ||
+ ext_data.placements[0]->type !=
+ INTEL_MEMORY_SYSTEM))
+ ext_data.flags |= I915_BO_ALLOC_GPU_ONLY;
+ }
obj = __i915_gem_object_create_user_ext(i915, args->size,
ext_data.placements,
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 914ebd9290e5..925685bd261e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3157,7 +3157,36 @@ struct drm_i915_gem_create_ext {
* Object handles are nonzero.
*/
__u32 handle;
- /** @flags: MBZ */
+ /**
+* @flags: Optional flags.
+*
+* Supported values:
+*
+* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that
+* the object will need to be accessed via the CPU.
+*
+* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and
+* only strictly required on platforms where only some of the device
+* memory is directly visible or mappable through the CPU, like on DG2+.
+*
+* One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+* ensure we can always spill the allocation to system memory, if we
+* can't place the object in the mappable part of
+* I915_MEMORY_CLASS_DEVICE.
+*
+* Note that buffers that need to be captured with EXEC_OBJECT_CAPTURE,
+* will need to enable this hint, if the object can also be placed in
+* I915_MEMORY_CLASS_DEVICE, starting from DG2+. The execbuf call will
+* throw an error otherwise. This also means that such objects will need
+* I915_MEMORY_CLASS_SYSTEM set as a possible placement.
+*
+* Without this hint, the kernel will assume that non-mappable
+* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+* kernel can still migrate the object to the mappable part, as a last
+* resort, if userspace ever CPU faults this object, but this might be
+* expensive, and so ideally should be avoided.
+*/
+#define I915_GEM_CREAT
[Intel-gfx] [PATCH v2 15/15] drm/i915/lmem: don't treat small BAR as an error
Just pass along the probed io_size. The backend should be able to utilize the entire range here, even if some of it is non-mappable. It does leave open with what to do with stolen local-memory. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 01838b8ce4c7..ad3cf348b4a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -201,6 +201,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_memory_region *mem; resource_size_t min_page_size; resource_size_t io_start; + resource_size_t io_size; resource_size_t lmem_size; int err; @@ -211,7 +212,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); io_start = pci_resource_start(pdev, 2); - if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) + io_size = min(pci_resource_len(pdev, 2), lmem_size); + if (!io_size) return ERR_PTR(-ENODEV); min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K : @@ -221,7 +223,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) lmem_size, min_page_size, io_start, -lmem_size, +io_size, INTEL_MEMORY_LOCAL, 0, &intel_region_lmem_ops); -- 2.34.1
Re: [Intel-gfx] [PATCH 07/20] drm/i915/hdmi: Simplify intel_hdmi_mode_clock_valid()
LGTM
Reviewed-by: Ankit Nautiyal
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Just loop over the possible bpc values instead of
using an ugly if construct.
A slight change in behaviour is that we now call
intel_hdmi_{source,sink}_bpc_possible() even for 8bpc,
but that is fine since 8bpc is always supported.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 37 +--
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b5af986b2778..c6586d10a9d0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1934,25 +1934,30 @@ intel_hdmi_mode_clock_valid(struct drm_connector
*connector, int clock,
{
struct drm_i915_private *i915 = to_i915(connector->dev);
struct intel_hdmi *hdmi =
intel_attached_hdmi(to_intel_connector(connector));
- enum drm_mode_status status;
+ enum drm_mode_status status = MODE_OK;
+ int bpc;
- /* check if we can do 8bpc */
- status = hdmi_port_clock_valid(hdmi, intel_hdmi_tmds_clock(clock, 8,
ycbcr420_output),
- true, has_hdmi_sink);
+ /*
+* Try all color depths since valid port clock range
+* can have holes. Any mode that can be used with at
+* least one color depth is accepted.
+*/
+ for (bpc = 12; bpc >= 8; bpc -= 2) {
+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
ycbcr420_output);
- /* if we can't do 8bpc we may still be able to do 12bpc */
- if (status != MODE_OK &&
- intel_hdmi_source_bpc_possible(i915, 12) &&
- intel_hdmi_sink_bpc_possible(connector, 12, has_hdmi_sink,
ycbcr420_output))
- status = hdmi_port_clock_valid(hdmi,
intel_hdmi_tmds_clock(clock, 12, ycbcr420_output),
- true, has_hdmi_sink);
+ if (!intel_hdmi_source_bpc_possible(i915, bpc))
+ continue;
- /* if we can't do 8,12bpc we may still be able to do 10bpc */
- if (status != MODE_OK &&
- intel_hdmi_source_bpc_possible(i915, 10) &&
- intel_hdmi_sink_bpc_possible(connector, 10, has_hdmi_sink,
ycbcr420_output))
- status = hdmi_port_clock_valid(hdmi,
intel_hdmi_tmds_clock(clock, 10, ycbcr420_output),
- true, has_hdmi_sink);
+ if (!intel_hdmi_sink_bpc_possible(connector, bpc,
has_hdmi_sink, ycbcr420_output))
+ continue;
+
+ status = hdmi_port_clock_valid(hdmi, tmds_clock, true,
has_hdmi_sink);
+ if (status == MODE_OK)
+ return MODE_OK;
+ }
+
+ /* can never happen */
+ drm_WARN_ON(&i915->drm, status == MODE_OK);
return status;
}
Re: [Intel-gfx] [PATCH 08/20] drm/i915/dp: Reuse intel_hdmi_tmds_clock()
LGTM
Reviewed-by: Ankit Nautiyal
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Reuse intel_hdmi_tmds_clock() for DP->HDMI TMDS clock calculations.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 20 +---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
3 files changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5cc99ffc1841..45e4bf54e1de 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -814,9 +814,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_CLOCK_HIGH;
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
- tmds_clock = target_clock;
- if (drm_mode_is_420_only(info, mode))
- tmds_clock /= 2;
+ tmds_clock = intel_hdmi_tmds_clock(target_clock, 8,
+ drm_mode_is_420_only(info, mode));
if (intel_dp->dfp.min_tmds_clock &&
tmds_clock < intel_dp->dfp.min_tmds_clock)
@@ -1070,21 +1069,12 @@ static bool intel_dp_hdmi_ycbcr420(struct intel_dp
*intel_dp,
intel_dp->dfp.ycbcr_444_to_420);
}
-static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state,
int bpc)
-{
- int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
-
- if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
- clock /= 2;
-
- return clock;
-}
-
static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
const struct intel_crtc_state
*crtc_state, int bpc)
{
- int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
+ int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+ int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
+ intel_dp_hdmi_ycbcr420(intel_dp,
crtc_state));
if (intel_dp->dfp.min_tmds_clock &&
tmds_clock < intel_dp->dfp.min_tmds_clock)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c6586d10a9d0..f1d42279a2df 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1868,7 +1868,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_OK;
}
-static int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
+int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
{
/* YCBCR420 TMDS rate requirement is half the pixel clock */
if (ycbcr420_output)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index ee144db67e66..d892cbff0da0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -47,6 +47,7 @@ bool intel_hdmi_limited_color_range(const struct
intel_crtc_state *crtc_state,
const struct drm_connector_state
*conn_state);
bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
int bpc, bool has_hdmi_sink, bool ycbcr420_output);
+int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output);
int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width,
int num_slices, int output_format, bool hdmi_all_bpp,
int hdmi_max_chunk_bytes);
Re: [Intel-gfx] [PATCH v2 10/19] fbcon: Ditch error handling for con2fb_release_oldinfo
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
It doesn't ever fail anymore.
Acked-by: Sam Ravnborg
Signed-off-by: Daniel Vetter
Cc: Daniel Vetter
Cc: Thomas Zimmermann
Cc: Greg Kroah-Hartman
Cc: Claudio Suarez
Cc: Du Cheng
Cc: Tetsuo Handa
Acked-by: Thomas Zimmermann
---
drivers/video/fbdev/core/fbcon.c | 37 +++-
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index 3e1a3e7bf527..a60891005d44 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -739,9 +739,8 @@ static int con2fb_acquire_newinfo(struct vc_data *vc,
struct fb_info *info,
return err;
}
-static int con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo,
- struct fb_info *newinfo, int unit,
- int oldidx, int found)
+static void con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo,
+ struct fb_info *newinfo)
{
struct fbcon_ops *ops = oldinfo->fbcon_par;
int ret;
@@ -770,8 +769,6 @@ static int con2fb_release_oldinfo(struct vc_data *vc,
struct fb_info *oldinfo,
"detected unhandled fb_set_par error, "
"error code %d\n", ret);
}
-
- return 0;
}
static void con2fb_init_display(struct vc_data *vc, struct fb_info *info,
@@ -825,7 +822,7 @@ static int set_con2fb_map(int unit, int newidx, int user)
int oldidx = con2fb_map[unit];
struct fb_info *info = registered_fb[newidx];
struct fb_info *oldinfo = NULL;
- int found, err = 0;
+ int found, err = 0, show_logo;
WARN_CONSOLE_UNLOCKED();
@@ -854,18 +851,15 @@ static int set_con2fb_map(int unit, int newidx, int user)
* fbcon should release it.
*/
if (!err && oldinfo && !search_fb_in_map(oldidx))
- err = con2fb_release_oldinfo(vc, oldinfo, info, unit, oldidx,
-found);
+ con2fb_release_oldinfo(vc, oldinfo, info);
- if (!err) {
- int show_logo = (fg_console == 0 && !user &&
-logo_shown != FBCON_LOGO_DONTSHOW);
+ show_logo = (fg_console == 0 && !user &&
+logo_shown != FBCON_LOGO_DONTSHOW);
- if (!found)
- fbcon_add_cursor_work(info);
- con2fb_map_boot[unit] = newidx;
- con2fb_init_display(vc, info, unit, show_logo);
- }
+ if (!found)
+ fbcon_add_cursor_work(info);
+ con2fb_map_boot[unit] = newidx;
+ con2fb_init_display(vc, info, unit, show_logo);
if (!search_fb_in_map(info_idx))
info_idx = newidx;
@@ -2769,7 +2763,7 @@ static inline void fbcon_unbind(void) {}
/* called with console_lock held */
void fbcon_fb_unbind(struct fb_info *info)
{
- int i, new_idx = -1, ret = 0;
+ int i, new_idx = -1;
int idx = info->node;
WARN_CONSOLE_UNLOCKED();
@@ -2803,13 +2797,8 @@ void fbcon_fb_unbind(struct fb_info *info)
if (con2fb_map[i] == idx) {
con2fb_map[i] = -1;
if (!search_fb_in_map(idx)) {
- ret =
con2fb_release_oldinfo(vc_cons[i].d,
-info,
NULL, i,
-idx, 0);
- if (ret) {
- con2fb_map[i] = idx;
- return;
- }
+ con2fb_release_oldinfo(vc_cons[i].d,
+ info, NULL);
}
}
}
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Ivo Totev
OpenPGP_signature
Description: OpenPGP digital signature
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Fix the plane end Y offset check
== Series Details ==
Series: drm/i915/fbc: Fix the plane end Y offset check
URL : https://patchwork.freedesktop.org/series/99958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11212 -> Patchwork_22238
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/index.html
Participating hosts (48 -> 42)
--
Additional (1): bat-jsl-2
Missing(7): shard-tglu fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600
fi-pnv-d510 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22238 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-rkl-guc: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-rkl-guc/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] ([i915#4547])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][5] ([i915#3921])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-bdw-5557u/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271]) +13 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][8] ([i915#2940]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-rkl-guc: [INCOMPLETE][10] -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-rkl-guc/igt@i915_selftest@l...@hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][12] ([i915#4269]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][14] ([i915#2722] / [i915#4312]) -> [FAIL][15]
([i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/fi-skl-6600u/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/fi-skl-6600u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11212 -> Patchwork_22238
CI-20190529: 20190529
CI_DRM_11212: 9ee4234aacecaa5b0c3c0e6b5cc5790255680302 @
g
Re: [Intel-gfx] [PATCH v2 11/19] fbcon: move more common code into fb_open()
Am 08.02.22 um 22:08 schrieb Daniel Vetter:
No idea why con2fb_acquire_newinfo() initializes much less than
fbcon_startup(), but so be it. From a quick look most of the
un-initialized stuff should be fairly harmless, but who knows.
Note that the error handling for the con2fb_acquire_newinfo() failure
case was very strange: Callers updated con2fb_map to the new value
before calling this function, but upon error con2fb_acquire_newinfo
reset it to the old value. Since I removed the call to fbcon_release
anyway that strange error path was sticking out like a sore thumb,
hence I removed it. Which also allows us to remove the oldidx
parameter from that function.
v2: Explain what's going on with oldidx and error paths (Sam)
v3: Drop unused variable (0day)
Acked-by: Sam Ravnborg (v2)
Cc: kernel test robot
Signed-off-by: Daniel Vetter
Cc: Daniel Vetter
Cc: Greg Kroah-Hartman
Cc: Tetsuo Handa
Cc: Thomas Zimmermann
Cc: Claudio Suarez
Cc: Du Cheng
Acked-by: Thomas Zimmermann
That's the init function I was looking for, I guess.
---
drivers/video/fbdev/core/fbcon.c | 75 +---
1 file changed, 30 insertions(+), 45 deletions(-)
diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c
index a60891005d44..f0213a0e3870 100644
--- a/drivers/video/fbdev/core/fbcon.c
+++ b/drivers/video/fbdev/core/fbcon.c
@@ -682,8 +682,18 @@ static int fbcon_invalid_charcount(struct fb_info *info,
unsigned charcount)
#endif /* CONFIG_MISC_TILEBLITTING */
+static void fbcon_release(struct fb_info *info)
+{
+ if (info->fbops->fb_release)
+ info->fbops->fb_release(info, 0);
+
+ module_put(info->fbops->owner);
+}
+
static int fbcon_open(struct fb_info *info)
{
+ struct fbcon_ops *ops;
+
if (!try_module_get(info->fbops->owner))
return -ENODEV;
@@ -693,48 +703,31 @@ static int fbcon_open(struct fb_info *info)
return -ENODEV;
}
- return 0;
-}
+ ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
+ if (!ops) {
+ fbcon_release(info);
+ return -ENOMEM;
+ }
-static void fbcon_release(struct fb_info *info)
-{
- if (info->fbops->fb_release)
- info->fbops->fb_release(info, 0);
+ INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
+ ops->info = info;
+ info->fbcon_par = ops;
+ ops->cur_blink_jiffies = HZ / 5;
- module_put(info->fbops->owner);
+ return 0;
}
static int con2fb_acquire_newinfo(struct vc_data *vc, struct fb_info *info,
- int unit, int oldidx)
+ int unit)
{
- struct fbcon_ops *ops = NULL;
int err;
err = fbcon_open(info);
if (err)
return err;
- if (!err) {
- ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
- if (!ops)
- err = -ENOMEM;
-
- INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
- }
-
- if (!err) {
- ops->cur_blink_jiffies = HZ / 5;
- ops->info = info;
- info->fbcon_par = ops;
-
- if (vc)
- set_blitting_type(vc, info);
- }
-
- if (err) {
- con2fb_map[unit] = oldidx;
- fbcon_release(info);
- }
+ if (vc)
+ set_blitting_type(vc, info);
return err;
}
@@ -842,9 +835,11 @@ static int set_con2fb_map(int unit, int newidx, int user)
found = search_fb_in_map(newidx);
- con2fb_map[unit] = newidx;
- if (!err && !found)
- err = con2fb_acquire_newinfo(vc, info, unit, oldidx);
+ if (!err && !found) {
+ err = con2fb_acquire_newinfo(vc, info, unit);
+ if (!err)
+ con2fb_map[unit] = newidx;
+ }
/*
* If old fb is not mapped to any of the consoles,
@@ -941,20 +936,10 @@ static const char *fbcon_startup(void)
if (fbcon_open(info))
return NULL;
- ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
- if (!ops) {
- fbcon_release(info);
- return NULL;
- }
-
- INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
-
+ ops = info->fbcon_par;
ops->currcon = -1;
ops->graphics = 1;
ops->cur_rotate = -1;
- ops->cur_blink_jiffies = HZ / 5;
- ops->info = info;
- info->fbcon_par = ops;
p->con_rotate = initial_rotation;
if (p->con_rotate == -1)
@@ -1024,7 +1009,7 @@ static void fbcon_init(struct vc_data *vc, int init)
return;
if (!info->fbcon_par)
- con2fb_acquire_newinfo(vc, info, vc->vc_num, -1);
+ con2fb_acquire_newinfo(vc, info, vc->vc_num);
/* If we are not the first console on this
fb, copy the font from that console */
--
Re: [Intel-gfx] [PATCH 0/6] More GT register cleanup
On Tue, 08 Feb 2022, Matt Roper wrote: > Another collection of cleanup patches for intel_gt_regs.h to make it a > bit less painful to work with. I didn't review this but I agree with what's being done. Acked-by: Jani Nikula > > Cc: Jani Nikula > > Matt Roper (6): > drm/i915/gt: Drop duplicate register definition for VDBOX_CGCTL3F18 > drm/i915/gt: Move SFC lock bits to intel_engine_regs.h > drm/i915/gt: Use parameterized RING_MI_MODE > drm/i915/gt: Cleanup spacing of intel_gt_regs.h > drm/i915/gt: Use consistent offset notation in intel_gt_regs.h > drm/i915/gt: Order GT registers by MMIO offset > > drivers/gpu/drm/i915/gt/intel_engine_regs.h | 23 + > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2623 +-- > drivers/gpu/drm/i915/gt/intel_reset.c | 14 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c |6 +- > drivers/gpu/drm/i915/intel_uncore.c |2 +- > 5 files changed, 1333 insertions(+), 1335 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 0/6] More GT register cleanup
On Thu, 10 Feb 2022, Jani Nikula wrote: > On Tue, 08 Feb 2022, Matt Roper wrote: >> Another collection of cleanup patches for intel_gt_regs.h to make it a >> bit less painful to work with. > > I didn't review this but I agree with what's being done. > > Acked-by: Jani Nikula PS. We somehow ended up with both _reg.h and _regs.h. Would be nice to settle on one or the other. Which one? BR, Jani. > >> >> Cc: Jani Nikula >> >> Matt Roper (6): >> drm/i915/gt: Drop duplicate register definition for VDBOX_CGCTL3F18 >> drm/i915/gt: Move SFC lock bits to intel_engine_regs.h >> drm/i915/gt: Use parameterized RING_MI_MODE >> drm/i915/gt: Cleanup spacing of intel_gt_regs.h >> drm/i915/gt: Use consistent offset notation in intel_gt_regs.h >> drm/i915/gt: Order GT registers by MMIO offset >> >> drivers/gpu/drm/i915/gt/intel_engine_regs.h | 23 + >> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2623 +-- >> drivers/gpu/drm/i915/gt/intel_reset.c | 14 +- >> drivers/gpu/drm/i915/gt/intel_workarounds.c |6 +- >> drivers/gpu/drm/i915/intel_uncore.c |2 +- >> 5 files changed, 1333 insertions(+), 1335 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher optimize plane updates (rev4)
== Series Details ==
Series: drm/i915: Futher optimize plane updates (rev4)
URL : https://patchwork.freedesktop.org/series/99149/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11211_full -> Patchwork_22237_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22237_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22237_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22237_full:
### IGT changes ###
Possible regressions
* igt@kms_async_flips@async-flip-with-page-flip-events:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-kbl3/igt@kms_async_fl...@async-flip-with-page-flip-events.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-kbl6/igt@kms_async_fl...@async-flip-with-page-flip-events.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-tglb2/igt@kms_plane_multi...@atomic-pipe-b-tiling-x.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-tglb8/igt@kms_plane_multi...@atomic-pipe-b-tiling-x.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_flush@basic-wb-rw-before-default:
- {shard-rkl}:NOTRUN -> ([PASS][5], [INCOMPLETE][6])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-rkl-4/igt@gem_exec_fl...@basic-wb-rw-before-default.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-rkl-5/igt@gem_exec_fl...@basic-wb-rw-before-default.html
* igt@gem_mmap_offset@open-flood:
- {shard-rkl}:[PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-rkl-6/igt@gem_mmap_off...@open-flood.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-rkl-5/igt@gem_mmap_off...@open-flood.html
* igt@syncobj_timeline@transfer-timeline-point:
- {shard-rkl}:NOTRUN -> [DMESG-WARN][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-rkl-1/igt@syncobj_timel...@transfer-timeline-point.html
Known issues
Here are the changes found in Patchwork_22237_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_read@invalid-buffer:
- shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] /
[i915#1888])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-glk3/igt@drm_r...@invalid-buffer.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-glk2/igt@drm_r...@invalid-buffer.html
* igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#658]) +1 similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-iclb6/igt@feature_discov...@psr2.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-kbl3/igt@gem_ctx_isolation@preservation...@bcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-kbl7/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#4525])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-iclb6/igt@gem_exec_balan...@parallel-contexts.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][16] -> [INCOMPLETE][17] ([i915#4547])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-skl4/igt@gem_exec_capture@p...@rcs0.html
* igt@gem_exec_capture@pi@vecs0:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#3371])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-tglb6/igt@gem_exec_capture@p...@vecs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22237/shard-tglb6/igt@gem_exec_capture@p...@vecs0.html
* igt@gem_exec_endless@dispatch@vcs0:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#3778])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11211/shard-tglb3/igt@gem_exec_endless@dispa...@vcs0.html
[21]:
https://intel
Re: [Intel-gfx] [PATCH v2 00/15] Initial support for small BAR recovery
Patches: 1, 2, 3, 5, 6, 11 are Acked-by: Nirmoy Das Patches: 5,6 are Reviewed-by: Nirmoy Das Sorry for partial reviews, I still need to go through more i915 code. Regards, Nirmoy On 10/02/2022 13:12, Matthew Auld wrote: Starting from DG2 we will have resizable BAR support for device local-memory, but in some cases the final BAR size might still be smaller than the total local-memory size. In such cases only part of local-memory will be CPU accessible, while the remainder is only accessible via the GPU. This series adds the basic enablers needed to ensure that the entire local-memory range is usable. Needs to be applied on top of Arun' in-progress series[1]. [1] https://patchwork.freedesktop.org/series/99430/ v2: - Various improvements and fixes as suggested by Thomas.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/opregion: fixes and cleanups, RESEND
== Series Details ==
Series: drm/i915/opregion: fixes and cleanups, RESEND
URL : https://patchwork.freedesktop.org/series/99961/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c30930dcbba4 drm/i915/opregion: check port number bounds for SWSCI display
power state
e7b41b2e3f18 drm/i915/opregion: abstract the check for valid swsci function
a0ed59d6871b drm/i915/opregion: early exit from encoder notify if SWSCI isn't
there
3d8fdd12c465 drm/i915/opregion: handle SWSCI Mailbox #2 obsoletion
32a509a8f08f drm/i915/opregion: debug log about Mailbox #2 for backlight
-:40: WARNING:BRACES: braces {} are not necessary for single statement blocks
#40: FILE: drivers/gpu/drm/i915/display/intel_opregion.c:961:
+ if (mboxes & MBOX_BACKLIGHT) {
+ drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
+ }
total: 0 errors, 1 warnings, 0 checks, 25 lines checked
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial support for small BAR recovery (rev3)
== Series Details == Series: Initial support for small BAR recovery (rev3) URL : https://patchwork.freedesktop.org/series/99370/ State : failure == Summary == Applying: drm/i915: add io_size plumbing Applying: drm/i915/ttm: require mappable by default Applying: drm/i915: add I915_BO_ALLOC_GPU_ONLY Applying: drm/i915/buddy: track available visible size Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_ttm_buddy_manager.c M drivers/gpu/drm/i915/i915_ttm_buddy_manager.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_ttm_buddy_manager.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_ttm_buddy_manager.h Auto-merging drivers/gpu/drm/i915/i915_ttm_buddy_manager.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_ttm_buddy_manager.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0004 drm/i915/buddy: track available visible size When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
Re: [Intel-gfx] [PATCH] drm/i915/fbc: Fix the plane end Y offset check
> -Original Message-
> From: Ville Syrjala
> Sent: Thursday, February 10, 2022 12:31 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika
> Subject: [PATCH] drm/i915/fbc: Fix the plane end Y offset check
>
> From: Ville Syrjälä
>
> We lost the required >>16 when I refactored the FBC plane state checks. Bring
> it
> back so the check does what it's supposed to.
>
> Cc: Mika Kahola
> Fixes: 2e6c99f88679 ("drm/i915/fbc: Nuke lots of crap from
> intel_fbc_state_cache")
> Signed-off-by: Ville Syrjälä
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index bcdffe62f3cb..87f4af3fd523 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1125,7 +1125,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>
> /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
> if (DISPLAY_VER(i915) >= 11 &&
> - (plane_state->view.color_plane[0].y +
> drm_rect_height(&plane_state->uapi.src)) & 3) {
> + (plane_state->view.color_plane[0].y +
> + (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
> plane_state->no_fbc_reason = "plane end Y offset misaligned";
> return false;
> }
> --
> 2.34.1
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/opregion: fixes and cleanups, RESEND
== Series Details == Series: drm/i915/opregion: fixes and cleanups, RESEND URL : https://patchwork.freedesktop.org/series/99961/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11213 -> Patchwork_22239 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22239 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22239, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/index.html Participating hosts (47 -> 43) -- Additional (1): fi-icl-u2 Missing(5): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22239: ### IGT changes ### Possible regressions * igt@core_hotunplug@unbind-rebind: - fi-rkl-guc: [PASS][1] -> [DMESG-WARN][2] +37 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html * igt@i915_module_load@reload: - fi-kbl-8809g: [PASS][3] -> [DMESG-WARN][4] +36 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-kbl-8809g/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-kbl-8809g/igt@i915_module_l...@reload.html - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-skl-6600u/igt@i915_module_l...@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-skl-6600u/igt@i915_module_l...@reload.html - fi-kbl-guc: [PASS][7] -> [DMESG-WARN][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-kbl-guc/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-kbl-guc/igt@i915_module_l...@reload.html * igt@i915_pm_rpm@module-reload: - fi-cfl-8700k: [PASS][9] -> [DMESG-WARN][10] +37 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-cfl-8700k/igt@i915_pm_...@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-cfl-8700k/igt@i915_pm_...@module-reload.html - fi-kbl-x1275: [PASS][11] -> [DMESG-WARN][12] +37 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-kbl-x1275/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@client: - fi-ivb-3770:[PASS][13] -> [DMESG-WARN][14] +36 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-ivb-3770/igt@i915_selftest@l...@client.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-ivb-3770/igt@i915_selftest@l...@client.html * igt@i915_selftest@live@gem: - fi-snb-2600:[PASS][15] -> [DMESG-WARN][16] +36 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-snb-2600/igt@i915_selftest@l...@gem.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-snb-2600/igt@i915_selftest@l...@gem.html * igt@i915_selftest@live@gem_contexts: - fi-pnv-d510:NOTRUN -> [DMESG-WARN][17] +23 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-pnv-d510/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gem_migrate: - fi-skl-guc: [PASS][18] -> [DMESG-WARN][19] +37 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-skl-guc/igt@i915_selftest@live@gem_migrate.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-skl-guc/igt@i915_selftest@live@gem_migrate.html * igt@i915_selftest@live@gt_engines: - fi-kbl-7500u: [PASS][20] -> [DMESG-WARN][21] +37 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-kbl-7500u/igt@i915_selftest@live@gt_engines.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-kbl-7500u/igt@i915_selftest@live@gt_engines.html - fi-bsw-nick:[PASS][22] -> [FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11213/fi-bsw-nick/igt@i915_selftest@live@gt_engines.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22239/fi-bsw-nick/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_heartbeat: - fi-pnv-d510:[PASS][24] -> [DMESG-WARN][25] +11 similar issues [24]: https://intel-gfx-ci.01.o
[Intel-gfx] [PATCH v4 00/14] drm/i915: drm_i915.h cleanup
I've sent parts of this before. Another rebase round. Jani Nikula (14): drm/i915: split out i915_gem_internal.h from i915_drv.h drm/i915: remove leftover i915_gem_pm.h declarations from i915_drv.h drm/i915: split out gem/i915_gem_dmabuf.h from i915_drv.h drm/i915: split out gem/i915_gem_create.h from i915_drv.h drm/i915: split out gem/i915_gem_domain.h from i915_drv.h drm/i915: move i915_cache_level_str() static in i915_debugfs.c drm/i915: move i915_gem_vm_lookup() where it's used drm/i915: move i915_reset_count()/i915_reset_engine_count() out of i915_drv.h drm/i915: split out i915_file_private.h from i915_drv.h drm/i915: don't include drm_cache.h in i915_drv.h drm/i915: include shmem_fs.h only where needed drm/i915: include some drm headers only where needed drm/i915: axe lots of unnecessary includes from i915_drv.h drm/i915: fix drm_i915.h include grouping and sorting drivers/gpu/drm/i915/display/intel_dpt.c | 4 +- drivers/gpu/drm/i915/display/intel_dsb.c | 2 + drivers/gpu/drm/i915/display/intel_fb_pin.c | 1 + drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 ++ drivers/gpu/drm/i915/gem/i915_gem_create.c| 3 + drivers/gpu/drm/i915/gem/i915_gem_create.h| 17 ++ drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h| 18 ++ drivers/gpu/drm/i915/gem/i915_gem_domain.c| 5 +- drivers/gpu/drm/i915/gem/i915_gem_domain.h| 15 ++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.h | 23 +++ drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_object.c| 5 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 + drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 + .../gpu/drm/i915/gem/selftests/huge_pages.c | 3 +- .../drm/i915/gem/selftests/i915_gem_context.c | 1 + .../drm/i915/gem/selftests/i915_gem_mman.c| 4 +- .../drm/i915/gem/selftests/igt_gem_utils.c| 1 + .../gpu/drm/i915/gem/selftests/mock_context.c | 1 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- drivers/gpu/drm/i915/gt/intel_gt.c| 7 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 + drivers/gpu/drm/i915/gt/intel_reset.c | 1 + drivers/gpu/drm/i915/gt/intel_ring.c | 1 + .../gpu/drm/i915/gt/intel_ring_submission.c | 4 + drivers/gpu/drm/i915/gt/intel_timeline.c | 5 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 + drivers/gpu/drm/i915/gt/selftest_migrate.c| 2 + drivers/gpu/drm/i915/gt/selftest_rps.c| 2 + .../gpu/drm/i915/gt/selftest_workarounds.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 + drivers/gpu/drm/i915/gvt/dmabuf.c | 5 + drivers/gpu/drm/i915/i915_cmd_parser.c| 2 + drivers/gpu/drm/i915/i915_debugfs.c | 11 ++ drivers/gpu/drm/i915/i915_driver.c| 3 + drivers/gpu/drm/i915/i915_drv.h | 184 +- drivers/gpu/drm/i915/i915_file_private.h | 108 ++ drivers/gpu/drm/i915/i915_gem.c | 7 +- drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.h | 11 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 2 + drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +- .../gpu/drm/i915/selftests/i915_gem_evict.c | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 1 + drivers/gpu/drm/i915/selftests/i915_vma.c | 1 + drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + 61 files changed, 329 insertions(+), 199 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_domain.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_internal.h create mode 100644 drivers/gpu/drm/i915/i915_file_private.h -- 2.30.2
[Intel-gfx] [PATCH v4 01/14] drm/i915: split out i915_gem_internal.h from i915_drv.h
We already have the i915_gem_internal.c file. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsb.c | 2 ++ drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.h | 23 +++ .../gpu/drm/i915/gem/selftests/huge_pages.c | 3 ++- .../drm/i915/gem/selftests/i915_gem_context.c | 1 + .../drm/i915/gem/selftests/i915_gem_mman.c| 4 +++- .../drm/i915/gem/selftests/igt_gem_utils.c| 1 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 + drivers/gpu/drm/i915/gt/intel_gt.c| 7 +++--- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 ++ drivers/gpu/drm/i915/gt/intel_ring.c | 1 + .../gpu/drm/i915/gt/intel_ring_submission.c | 2 ++ drivers/gpu/drm/i915/gt/intel_timeline.c | 3 ++- drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 ++ drivers/gpu/drm/i915/gt/selftest_migrate.c| 2 ++ drivers/gpu/drm/i915/gt/selftest_rps.c| 2 ++ .../gpu/drm/i915/gt/selftest_workarounds.c| 1 + drivers/gpu/drm/i915/i915_drv.h | 9 drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/selftests/i915_gem.c | 3 ++- .../gpu/drm/i915/selftests/i915_gem_evict.c | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 1 + drivers/gpu/drm/i915/selftests/i915_vma.c | 1 + drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + 31 files changed, 67 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_internal.h diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 83a69a4a4fea..b34a67309976 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -4,6 +4,8 @@ * */ +#include "gem/i915_gem_internal.h" + #include "i915_drv.h" #include "intel_de.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 5358f03b52db..76845d34ad0c 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -28,6 +28,7 @@ #include +#include "gem/i915_gem_internal.h" #include "gem/i915_gem_pm.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_ring.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c b/drivers/gpu/drm/i915/gem/i915_gem_internal.c index c5150a1ee3d2..c698f95af15f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c @@ -10,6 +10,7 @@ #include "i915_drv.h" #include "i915_gem.h" +#include "i915_gem_internal.h" #include "i915_gem_object.h" #include "i915_scatterlist.h" #include "i915_utils.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.h b/drivers/gpu/drm/i915/gem/i915_gem_internal.h new file mode 100644 index ..6664e06112fc --- /dev/null +++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __I915_GEM_INTERNAL_H__ +#define __I915_GEM_INTERNAL_H__ + +#include + +struct drm_i915_gem_object; +struct drm_i915_gem_object_ops; +struct drm_i915_private; + +struct drm_i915_gem_object * +i915_gem_object_create_internal(struct drm_i915_private *i915, + phys_addr_t size); +struct drm_i915_gem_object * +__i915_gem_object_create_internal(struct drm_i915_private *i915, + const struct drm_i915_gem_object_ops *ops, + phys_addr_t size); + +#endif /* __I915_GEM_INTERNAL_H__ */ diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index f36191ebf964..8424ee8c5eb8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -8,9 +8,10 @@ #include "i915_selftest.h" -#include "gem/i915_gem_region.h" +#include "gem/i915_gem_internal.h" #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_pm.h" +#include "gem/i915_gem_region.h" #include "gt/intel_gt.h" diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 7cc4fa8f8c56..bd60d42238fb 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -6,6 +6,7 @@ #include +#include "gem/i915_gem_internal.h" #include "gem/i915_gem_pm.h" #include "gt/intel_engine
[Intel-gfx] [PATCH v4 02/14] drm/i915: remove leftover i915_gem_pm.h declarations from i915_drv.h
Remove the duplicates. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 3 --- drivers/gpu/drm/i915/i915_gem.c | 1 + 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f5d71f0ee0e7..5d6ee867b3a7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1624,9 +1624,6 @@ void i915_gem_driver_register(struct drm_i915_private *i915); void i915_gem_driver_unregister(struct drm_i915_private *i915); void i915_gem_driver_remove(struct drm_i915_private *dev_priv); void i915_gem_driver_release(struct drm_i915_private *dev_priv); -void i915_gem_suspend(struct drm_i915_private *dev_priv); -void i915_gem_suspend_late(struct drm_i915_private *dev_priv); -void i915_gem_resume(struct drm_i915_private *dev_priv); int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e3a2c2a0e156..a70750c48047 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -44,6 +44,7 @@ #include "gem/i915_gem_context.h" #include "gem/i915_gem_ioctls.h" #include "gem/i915_gem_mman.h" +#include "gem/i915_gem_pm.h" #include "gem/i915_gem_region.h" #include "gem/i915_gem_userptr.h" #include "gt/intel_engine_user.h" -- 2.30.2
[Intel-gfx] [PATCH v4 03/14] drm/i915: split out gem/i915_gem_dmabuf.h from i915_drv.h
We already have the gem/i915_gem_dmabuf.c file.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h | 18 ++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 ++
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 ++
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/i915_drv.h| 5 -
6 files changed, 24 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 14fdb0796c52..13917231ae81 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -11,6 +11,7 @@
#include
+#include "gem/i915_gem_dmabuf.h"
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
new file mode 100644
index ..6e0405d47ce1
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_GEM_DMABUF_H__
+#define __I915_GEM_DMABUF_H__
+
+struct drm_gem_object;
+struct drm_device;
+struct dma_buf;
+
+struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
+struct dma_buf *dma_buf);
+
+struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int
flags);
+
+#endif /* __I915_GEM_DMABUF_H__ */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index e03e362d320b..04df294dc5ca 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -26,9 +26,11 @@
#include "display/intel_frontbuffer.h"
#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
+#include "i915_gem_dmabuf.h"
#include "i915_gem_mman.h"
#include "i915_gem_object.h"
#include "i915_gem_ttm.h"
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 6dd3757cdf87..893206a92002 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -31,6 +31,8 @@
#include
#include
+#include "gem/i915_gem_dmabuf.h"
+
#include "i915_drv.h"
#include "i915_reg.h"
#include "gvt.h"
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 76c84b35884f..eb90d04ba35a 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -62,6 +62,7 @@
#include "display/intel_vga.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_dmabuf.h"
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d6ee867b3a7..82f8fc9c2b88 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1630,11 +1630,6 @@ int i915_gem_open(struct drm_i915_private *i915, struct
drm_file *file);
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
-struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
- struct dma_buf *dma_buf);
-
-struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int
flags);
-
static inline struct i915_address_space *
i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
--
2.30.2
[Intel-gfx] [PATCH v4 04/14] drm/i915: split out gem/i915_gem_create.h from i915_drv.h
We already have the gem/i915_gem_create.c file. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_create.h | 17 + drivers/gpu/drm/i915/i915_driver.c | 1 + drivers/gpu/drm/i915/i915_drv.h| 4 4 files changed, 19 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.h diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 9402d4bf4ffc..0deff550d324 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -9,6 +9,7 @@ #include "pxp/intel_pxp.h" #include "i915_drv.h" +#include "i915_gem_create.h" #include "i915_trace.h" #include "i915_user_extensions.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.h b/drivers/gpu/drm/i915/gem/i915_gem_create.h new file mode 100644 index ..9536aa906001 --- /dev/null +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef __I915_GEM_CREATE_H__ +#define __I915_GEM_CREATE_H__ + +struct drm_file; +struct drm_device; +struct drm_mode_create_dumb; + +int i915_gem_dumb_create(struct drm_file *file_priv, +struct drm_device *dev, +struct drm_mode_create_dumb *args); + +#endif /* __I915_GEM_CREATE_H__ */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index eb90d04ba35a..4a41c38cf06f 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -62,6 +62,7 @@ #include "display/intel_vga.h" #include "gem/i915_gem_context.h" +#include "gem/i915_gem_create.h" #include "gem/i915_gem_dmabuf.h" #include "gem/i915_gem_ioctls.h" #include "gem/i915_gem_mman.h" diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 82f8fc9c2b88..4f057a45654a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1602,10 +1602,6 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj, void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); -int i915_gem_dumb_create(struct drm_file *file_priv, -struct drm_device *dev, -struct drm_mode_create_dumb *args); - int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); static inline u32 i915_reset_count(struct i915_gpu_error *error) -- 2.30.2
[Intel-gfx] [PATCH v4 05/14] drm/i915: split out gem/i915_gem_domain.h from i915_drv.h
We already have the gem/i915_gem_domain.c file.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dpt.c| 4 +++-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 5 +++--
drivers/gpu/drm/i915/gem/i915_gem_domain.h | 15 +++
drivers/gpu/drm/i915/i915_drv.h | 3 ---
5 files changed, 22 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_domain.h
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index c2f8f853db90..05dd7dba3a5c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -3,11 +3,13 @@
* Copyright © 2021 Intel Corporation
*/
+#include "gem/i915_gem_domain.h"
+#include "gt/gen8_ppgtt.h"
+
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dpt.h"
#include "intel_fb.h"
-#include "gt/gen8_ppgtt.h"
struct i915_dpt {
struct i915_address_space vm;
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index c4b3d76341f3..a307b4993bcf 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -7,6 +7,7 @@
* DOC: display pinning helpers
*/
+#include "gem/i915_gem_domain.h"
#include "gem/i915_gem_object.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 26532c07d467..3e5d6057b3ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -9,12 +9,13 @@
#include "i915_drv.h"
#include "i915_gem_clflush.h"
+#include "i915_gem_domain.h"
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
-#include "i915_gem_object.h"
-#include "i915_vma.h"
#include "i915_gem_lmem.h"
#include "i915_gem_mman.h"
+#include "i915_gem_object.h"
+#include "i915_vma.h"
static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.h
b/drivers/gpu/drm/i915/gem/i915_gem_domain.h
new file mode 100644
index ..9622df962bfc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __I915_GEM_DOMAIN_H__
+#define __I915_GEM_DOMAIN_H__
+
+struct drm_i915_gem_object;
+enum i915_cache_level;
+
+int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+ enum i915_cache_level cache_level);
+
+#endif /* __I915_GEM_DOMAIN_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4f057a45654a..4dbab34045e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1623,9 +1623,6 @@ void i915_gem_driver_release(struct drm_i915_private
*dev_priv);
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
-int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
- enum i915_cache_level cache_level);
-
static inline struct i915_address_space *
i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
--
2.30.2
[Intel-gfx] [PATCH v4 06/14] drm/i915: move i915_cache_level_str() static in i915_debugfs.c
Move the function next to the only user.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +++
drivers/gpu/drm/i915/i915_drv.h | 2 --
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 85f86d71603d..e53008b4dd05 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1230,17 +1230,6 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs
*engine)
ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
}
-const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
-{
- switch (type) {
- case I915_CACHE_NONE: return " uncached";
- case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
- case I915_CACHE_L3_LLC: return " L3+LLC";
- case I915_CACHE_WT: return " WT";
- default: return "";
- }
-}
-
static u32
read_subslice_reg(const struct intel_engine_cs *engine,
int slice, int subslice, i915_reg_t reg)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca52ee0742ce..5ddd1929254a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -137,6 +137,17 @@ static const char *stringify_vma_type(const struct
i915_vma *vma)
return "ppgtt";
}
+static const char *i915_cache_level_str(struct drm_i915_private *i915, int
type)
+{
+ switch (type) {
+ case I915_CACHE_NONE: return " uncached";
+ case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
+ case I915_CACHE_L3_LLC: return " L3+LLC";
+ case I915_CACHE_WT: return " WT";
+ default: return "";
+ }
+}
+
void
i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dbab34045e8..306bc87dadcc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1646,8 +1646,6 @@ static inline bool
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_objec
i915_gem_object_is_tiled(obj);
}
-const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
-
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
--
2.30.2
[Intel-gfx] [PATCH v4 07/14] drm/i915: move i915_gem_vm_lookup() where it's used
Move the function next to the only user. Arguably it's perhaps not the
best place, but it's much better than having a static inline in a
header.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +++
drivers/gpu/drm/i915/i915_drv.h | 14 --
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ebbac2ea0833..fff09df0009e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -343,6 +343,21 @@ static int proto_context_register(struct
drm_i915_file_private *fpriv,
return ret;
}
+
+static struct i915_address_space *
+i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
+{
+ struct i915_address_space *vm;
+
+ xa_lock(&file_priv->vm_xa);
+ vm = xa_load(&file_priv->vm_xa, id);
+ if (vm)
+ kref_get(&vm->ref);
+ xa_unlock(&file_priv->vm_xa);
+
+ return vm;
+}
+
static int set_proto_ctx_vm(struct drm_i915_file_private *fpriv,
struct i915_gem_proto_context *pc,
const struct drm_i915_gem_context_param *args)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 306bc87dadcc..bc51b2336e05 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1623,20 +1623,6 @@ void i915_gem_driver_release(struct drm_i915_private
*dev_priv);
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
-static inline struct i915_address_space *
-i915_gem_vm_lookup(struct drm_i915_file_private *file_priv, u32 id)
-{
- struct i915_address_space *vm;
-
- xa_lock(&file_priv->vm_xa);
- vm = xa_load(&file_priv->vm_xa, id);
- if (vm)
- kref_get(&vm->ref);
- xa_unlock(&file_priv->vm_xa);
-
- return vm;
-}
-
/* i915_gem_tiling.c */
static inline bool i915_gem_object_needs_bit17_swizzle(struct
drm_i915_gem_object *obj)
{
--
2.30.2
[Intel-gfx] [PATCH v4 08/14] drm/i915: move i915_reset_count()/i915_reset_engine_count() out of i915_drv.h
It doesn't help much, as i915_drv.h includes i915_gpu_error.h, but it's
a step in the right direction.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 11 ---
drivers/gpu/drm/i915/i915_gpu_error.h | 11 +++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bc51b2336e05..95091ee4870f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1604,17 +1604,6 @@ void i915_gem_runtime_suspend(struct drm_i915_private
*dev_priv);
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
-static inline u32 i915_reset_count(struct i915_gpu_error *error)
-{
- return atomic_read(&error->reset_count);
-}
-
-static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
- const struct intel_engine_cs *engine)
-{
- return atomic_read(&error->reset_engine_count[engine->uabi_class]);
-}
-
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
void i915_gem_driver_register(struct drm_i915_private *i915);
void i915_gem_driver_unregister(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 5aedf5129814..903d838e2e63 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -210,6 +210,17 @@ struct drm_i915_error_state_buf {
int err;
};
+static inline u32 i915_reset_count(struct i915_gpu_error *error)
+{
+ return atomic_read(&error->reset_count);
+}
+
+static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
+ const struct intel_engine_cs *engine)
+{
+ return atomic_read(&error->reset_engine_count[engine->uabi_class]);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
__printf(2, 3)
--
2.30.2
[Intel-gfx] [PATCH v4 09/14] drm/i915: split out i915_file_private.h from i915_drv.h
Limit the scope of struct drm_i915_file_private to the files that
actually need it.
Cc: Tvrtko Ursulin
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.c| 1 +
drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 1 +
.../gpu/drm/i915/gem/selftests/mock_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/i915_driver.c| 1 +
drivers/gpu/drm/i915/i915_drv.h | 93 ---
drivers/gpu/drm/i915/i915_file_private.h | 108 ++
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 1 +
11 files changed, 117 insertions(+), 94 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_file_private.h
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fff09df0009e..77bebaa4fe2e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -79,6 +79,7 @@
#include "pxp/intel_pxp.h"
+#include "i915_file_private.h"
#include "i915_gem_context.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..13c975da7747 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -25,6 +25,7 @@
#include "i915_cmd_parser.h"
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_evict.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 04df294dc5ca..fb90c35543f2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -28,6 +28,7 @@
#include "pxp/intel_pxp.h"
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_dmabuf.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_throttle.c
b/drivers/gpu/drm/i915/gem/i915_gem_throttle.c
index 75501db71041..af85d0c28168 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_throttle.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_throttle.c
@@ -9,6 +9,7 @@
#include
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
index c0a8ef368044..6d6082b5f31f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
@@ -4,6 +4,7 @@
* Copyright © 2016 Intel Corporation
*/
+#include "i915_file_private.h"
#include "mock_context.h"
#include "selftests/mock_drm.h"
#include "selftests/mock_gtt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 59beb69ff6f2..13e3a7b236b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -14,6 +14,7 @@
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_gpu_error.h"
#include "i915_irq.h"
#include "intel_breadcrumbs.h"
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index 4a41c38cf06f..1c67ff735f18 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -73,6 +73,7 @@
#include "pxp/intel_pxp_pm.h"
+#include "i915_file_private.h"
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95091ee4870f..39bc632289c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -48,7 +48,6 @@
#include
#include
#include
-#include
#include
#include
@@ -180,98 +179,6 @@ struct i915_hotplug {
I915_GEM_DOMAIN_INSTRUCTION | \
I915_GEM_DOMAIN_VERTEX)
-struct drm_i915_file_private {
- struct drm_i915_private *dev_priv;
-
- union {
- struct drm_file *file;
- struct rcu_head rcu;
- };
-
- /** @proto_context_lock: Guards all struct i915_gem_proto_context
-* operations
-*
-* This not only guards @proto_context_xa, but is always held
-* whenever we manipulate any struct i915_gem_proto_context,
-* including finalizing it on first actual use of the GEM context.
-*
-* See i915_gem_proto_context.
-*/
- struct mutex proto_context_lock;
-
- /** @proto_context_xa: xarray of struct i915_gem_proto_context
-*
-* Historically, the context uA
[Intel-gfx] [PATCH v4 10/14] drm/i915: don't include drm_cache.h in i915_drv.h
Include it only in files that use it. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_mman.c| 2 ++ drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 ++ drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 ++ drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 ++ drivers/gpu/drm/i915/gt/intel_timeline.c| 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c| 2 ++ drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem.c | 4 +++- drivers/gpu/drm/i915/i915_gpu_error.c | 1 + 14 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c index 8a248003dfae..ce91b23385cf 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c @@ -4,6 +4,8 @@ * Copyright © 2016 Intel Corporation */ +#include + #include "display/intel_frontbuffer.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 77bebaa4fe2e..238c3d7da9a7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -67,6 +67,7 @@ #include #include +#include #include #include "gt/gen6_ppgtt.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 30507fe86b4c..efe69d6b86f4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -9,6 +9,8 @@ #include #include +#include + #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index fb90c35543f2..2d593d573ef1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -24,6 +24,8 @@ #include +#include + #include "display/intel_frontbuffer.h" #include "pxp/intel_pxp.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 060fe29f5929..183b861620b8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -4,6 +4,8 @@ * Copyright © 2014-2016 Intel Corporation */ +#include + #include "i915_drv.h" #include "i915_gem_object.h" #include "i915_scatterlist.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 6c57b0a79c8a..333a76b60112 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -7,6 +7,8 @@ #include #include +#include + #include "gem/i915_gem_region.h" #include "i915_drv.h" #include "i915_gemfs.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index b128ccd2fb98..6d7ec3bf1f32 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -3,6 +3,8 @@ * Copyright © 2008-2021 Intel Corporation */ +#include + #include "gem/i915_gem_internal.h" #include "gen2_engine_cs.h" diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 2962be6d4d00..b9640212d659 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -3,6 +3,8 @@ * Copyright © 2016-2018 Intel Corporation */ +#include + #include "gem/i915_gem_internal.h" #include "i915_active.h" diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index ddbea939b1dc..733465658e0f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -3,6 +3,8 @@ * Copyright © 2021 Intel Corporation */ +#include + #include "i915_drv.h" #include "i915_reg.h" #include "intel_guc_slpc.h" diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index ba4f0970749b..c88113044494 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -5,6 +5,8 @@ #include #include + +#include #include #include "gem/i915_gem_lmem.h" diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index aea4c30645ff..5f6e41636655 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -25,6 +25,8 @@ * */ +#include + #include "gt/intel_engine.h" #include "gt/intel_engine_regs.h" #include "gt/inte
[Intel-gfx] [PATCH v4 11/14] drm/i915: include shmem_fs.h only where needed
Don't include shmem_fs.h in i915_drv.h, reducing the build dependencies. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 - 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 333a76b60112..4efa821f3cb1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -5,6 +5,7 @@ */ #include +#include #include #include diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 1eb2fd81c5b6..8419096d4056 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -3,6 +3,8 @@ * Copyright © 2021 Intel Corporation */ +#include + #include #include diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 75784873a9a8..233e16916a78 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -46,7 +46,6 @@ #include #include #include -#include #include #include -- 2.30.2
[Intel-gfx] [PATCH v4 12/14] drm/i915: include some drm headers only where needed
Include drm_fourcc.h, drm_plane.h, and drm_color_mgmt.h where needed, so we can drop the includes for drm_atomic.h and drm_fourcc.h from i915_drv.h, reducing the build dependencies. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 2 ++ drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +++ drivers/gpu/drm/i915/i915_drv.h| 2 -- drivers/gpu/drm/i915/i915_pci.c| 1 + 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 0deff550d324..c6eb023d3d86 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -3,6 +3,8 @@ * Copyright © 2020 Intel Corporation */ +#include + #include "gem/i915_gem_ioctls.h" #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_region.h" diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 893206a92002..c95c25d2addb 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -31,6 +31,9 @@ #include #include +#include +#include + #include "gem/i915_gem_dmabuf.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 233e16916a78..6d28f16f71e6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -31,7 +31,6 @@ #define _I915_DRV_H_ #include -#include #include @@ -52,7 +51,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 467252f885c2..8246cbe9b01d 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -22,6 +22,7 @@ * */ +#include #include #include -- 2.30.2
[Intel-gfx] [PATCH v4 13/14] drm/i915: axe lots of unnecessary includes from i915_drv.h
It's fairly difficult to ensure these are actually not needed due to indirect includes via other files. However, it's easier to add them back as needed and, most importantly, where needed instead of exhaustively proving they're unnecessary. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 18 -- 1 file changed, 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6d28f16f71e6..3bb2c48018a0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -34,25 +34,12 @@ #include -#include #include #include -#include -#include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include #include -#include #include #include "i915_params.h" @@ -89,17 +76,12 @@ #include "intel_runtime_pm.h" #include "intel_step.h" #include "intel_uncore.h" -#include "intel_wakeref.h" #include "intel_wopcm.h" #include "i915_gem.h" -#include "i915_gem_gtt.h" #include "i915_gpu_error.h" #include "i915_perf_types.h" -#include "i915_request.h" #include "i915_scheduler.h" -#include "gt/intel_timeline.h" -#include "i915_vma.h" struct dpll; struct drm_i915_clock_gating_funcs; -- 2.30.2
[Intel-gfx] [PATCH v4 14/14] drm/i915: fix drm_i915.h include grouping and sorting
Group and sort includes in i915_drv.h similar to other places. Cc: Tvrtko Ursulin Cc: Daniel Vetter Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 16 +++- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3bb2c48018a0..418091484e02 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -42,9 +42,6 @@ #include #include -#include "i915_params.h" -#include "i915_utils.h" - #include "display/intel_bios.h" #include "display/intel_cdclk.h" #include "display/intel_display.h" @@ -59,9 +56,9 @@ #include "display/intel_opregion.h" #include "gem/i915_gem_context_types.h" +#include "gem/i915_gem_lmem.h" #include "gem/i915_gem_shrinker.h" #include "gem/i915_gem_stolen.h" -#include "gem/i915_gem_lmem.h" #include "gt/intel_engine.h" #include "gt/intel_gt_types.h" @@ -69,6 +66,12 @@ #include "gt/intel_workarounds.h" #include "gt/uc/intel_uc.h" +#include "i915_gem.h" +#include "i915_gpu_error.h" +#include "i915_params.h" +#include "i915_perf_types.h" +#include "i915_scheduler.h" +#include "i915_utils.h" #include "intel_device_info.h" #include "intel_memory_region.h" #include "intel_pch.h" @@ -78,11 +81,6 @@ #include "intel_uncore.h" #include "intel_wopcm.h" -#include "i915_gem.h" -#include "i915_gpu_error.h" -#include "i915_perf_types.h" -#include "i915_scheduler.h" - struct dpll; struct drm_i915_clock_gating_funcs; struct drm_i915_gem_object; -- 2.30.2
Re: [Intel-gfx] [PATCH v11 1/5] drm: improve drm_buddy_alloc function
On 27/01/2022 14:11, Arunpravin wrote:
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915 driver to drm buddy
v2:
merged below changes to keep the build unbroken
- drm_buddy_alloc_range() becomes obsolete and may be removed
- enable ttm range allocation (fpfn / lpfn) support in i915 driver
- apply enhanced drm_buddy_alloc() function to i915 driver
v3(Matthew Auld):
- Fix alignment issues and remove unnecessary list_empty check
- add more validation checks for input arguments
- make alloc_range() block allocations as bottom-up
- optimize order computation logic
- replace uint64_t with u64, which is preferred in the kernel
v4(Matthew Auld):
- keep drm_buddy_alloc_range() function implementation for generic
actual range allocations
- keep alloc_range() implementation for end bias allocations
v5(Matthew Auld):
- modify drm_buddy_alloc() passing argument place->lpfn to lpfn
as place->lpfn will currently always be zero for i915
v6(Matthew Auld):
- fixup potential uaf - If we are unlucky and can't allocate
enough memory when splitting blocks, where we temporarily
end up with the given block and its buddy on the respective
free list, then we need to ensure we delete both blocks,
and no just the buddy, before potentially freeing them
- fix warnings reported by kernel test robot
v7(Matthew Auld):
- revert fixup potential uaf
- keep __alloc_range() add node to the list logic same as
drm_buddy_alloc_blocks() by having a temporary list variable
- at drm_buddy_alloc_blocks() keep i915 range_overflows macro
and add a new check for end variable
v8:
- fix warnings reported by kernel test robot
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 315 +-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 67 ++--
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
include/drm/drm_buddy.h | 13 +-
4 files changed, 280 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index d60878bc9c20..cfc160a1ef1a 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -282,23 +282,97 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct
list_head *objects)
}
EXPORT_SYMBOL(drm_buddy_free_list);
-/**
- * drm_buddy_alloc_blocks - allocate power-of-two blocks
- *
- * @mm: DRM buddy manager to allocate from
- * @order: size of the allocation
- *
- * The order value here translates to:
- *
- * 0 = 2^0 * mm->chunk_size
- * 1 = 2^1 * mm->chunk_size
- * 2 = 2^2 * mm->chunk_size
- *
- * Returns:
- * allocated ptr to the &drm_buddy_block on success
- */
-struct drm_buddy_block *
-drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned int order)
+static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= e2 && e1 >= s2;
+}
+
+static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= s2 && e1 >= e2;
+}
+
+static struct drm_buddy_block *
+alloc_range_bias(struct drm_buddy *mm,
+u64 start, u64 end,
+unsigned int order)
+{
+ struct drm_buddy_block *block;
+ struct drm_buddy_block *buddy;
+ LIST_HEAD(dfs);
+ int err;
+ int i;
+
+ end = end - 1;
+
+ for (i = 0; i < mm->n_roots; ++i)
+ list_add_tail(&mm->roots[i]->tmp_link, &dfs);
+
+ do {
+ u64 block_start;
+ u64 block_end;
+
+ block = list_first_entry_or_null(&dfs,
+struct drm_buddy_block,
+tmp_link);
+ if (!block)
+ break;
+
+ list_del(&block->tmp_link);
+
+ if (drm_buddy_block_order(block) < order)
+ continue;
+
+ block_start = drm_buddy_block_offset(block);
+ block_end = block_start + drm_buddy_block_size(mm, block) - 1;
+
+ if (!overlaps(start, end, block_start, block_end))
+ continue;
+
+ if (drm_buddy_block_is_allocated(block))
+ continue;
+
+ if (contains(start, end, block_start, block_end) &&
+ order == drm_buddy_block_order(block)) {
+ /*
+* Find the free block within the range.
+*/
+ if (drm_buddy_block_is_free(block))
+ return block;
+
+ continue;
+ }
+
+ if (!drm_buddy_block_is_split(block)) {
+ err = split
[Intel-gfx] [PATCH v2] drm/i915/opregion: handle SWSCI Mailbox #2 obsoletion
Opregion Mailbox #2 is obsolete for SWSCI usage in opregion v2.x, and
repurposed in opregion v3.x. Warn about obsole mailbox presence in v2.x,
and ignore with an error for v3.x.
v2: Demote drm_warn() to drm_dbg() on opregion v2.x
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_opregion.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/drm/i915/display/intel_opregion.c
index ce3d44cc2461..11de19da0948 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -932,9 +932,17 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
}
if (mboxes & MBOX_SWSCI) {
- drm_dbg(&dev_priv->drm, "SWSCI supported\n");
- opregion->swsci = base + OPREGION_SWSCI_OFFSET;
- swsci_setup(dev_priv);
+ u8 major = opregion->header->over.major;
+
+ if (major >= 3) {
+ drm_err(&dev_priv->drm, "SWSCI Mailbox #2 present for
opregion v3.x, ignoring\n");
+ } else {
+ if (major >= 2)
+ drm_dbg(&dev_priv->drm, "SWSCI Mailbox #2
present for opregion v2.x\n");
+ drm_dbg(&dev_priv->drm, "SWSCI supported\n");
+ opregion->swsci = base + OPREGION_SWSCI_OFFSET;
+ swsci_setup(dev_priv);
+ }
}
if (mboxes & MBOX_ASLE) {
--
2.30.2
Re: [Intel-gfx] [PATCH 5/5] drm/i915/opregion: debug log about Mailbox #2 for backlight
On Thu, 10 Feb 2022, Ville Syrjälä wrote:
> On Thu, Feb 10, 2022 at 12:36:46PM +0200, Jani Nikula wrote:
>> Start debug logging about the presence of the new Mailbox #2 for
>> backlight. Actual support is to be added later.
>>
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_opregion.c | 13 +
>> 1 file changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
>> b/drivers/gpu/drm/i915/display/intel_opregion.c
>> index 6e32ed6bbf4e..b1ad11b2ebb3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
>> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
>> @@ -47,10 +47,11 @@
>> #define OPREGION_ASLE_EXT_OFFSET0x1C00
>>
>> #define OPREGION_SIGNATURE "IntelGraphicsMem"
>> -#define MBOX_ACPI (1<<0)
>> -#define MBOX_SWSCI (1<<1)
>> -#define MBOX_ASLE (1<<2)
>> -#define MBOX_ASLE_EXT (1<<4)
>> +#define MBOX_ACPI BIT(0) /* Mailbox #1 */
>> +#define MBOX_SWSCI BIT(1) /* Mailbox #2 (obsolete from v2.x) */
>> +#define MBOX_ASLE BIT(2) /* Mailbox #3 */
>> +#define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */
>> +#define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x)
>> */
>
> Opregion is such a lovely turd.
Tell me about it. I had to send v2 of patch 4/5 demoting the warn to dbg
because CI apparently has swsci mbox & version combos that supposedly
shouldn't exist. *sigh*.
> Series is
> Reviewed-by: Ville Syrjälä
Thanks,
Jani.
>
>>
>> struct opregion_header {
>> u8 signature[16];
>> @@ -957,6 +958,10 @@ int intel_opregion_setup(struct drm_i915_private
>> *dev_priv)
>> opregion->asle_ext = base + OPREGION_ASLE_EXT_OFFSET;
>> }
>>
>> +if (mboxes & MBOX_BACKLIGHT) {
>> +drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
>> +}
>> +
>> if (intel_load_vbt_firmware(dev_priv) == 0)
>> goto out;
>>
>> --
>> 2.30.2
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: drm_i915.h cleanup
== Series Details == Series: drm/i915: drm_i915.h cleanup URL : https://patchwork.freedesktop.org/series/99979/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2e49d59d1b68 drm/i915: split out i915_gem_internal.h from i915_drv.h -:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #50: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 286 lines checked 59b695819bdb drm/i915: remove leftover i915_gem_pm.h declarations from i915_drv.h 80fa6e91fdb3 drm/i915: split out gem/i915_gem_dmabuf.h from i915_drv.h -:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #25: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 62 lines checked d530ee1287c2 drm/i915: split out gem/i915_gem_create.h from i915_drv.h -:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #25: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 41 lines checked 08e14a541597 drm/i915: split out gem/i915_gem_domain.h from i915_drv.h -:64: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #64: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 60 lines checked 615db0e2922f drm/i915: move i915_cache_level_str() static in i915_debugfs.c -:47: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line #47: FILE: drivers/gpu/drm/i915/i915_debugfs.c:144: + case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; total: 1 errors, 0 warnings, 0 checks, 42 lines checked abc075a2bd16 drm/i915: move i915_gem_vm_lookup() where it's used -:22: CHECK:LINE_SPACING: Please don't use multiple blank lines #22: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:346: + total: 0 errors, 0 warnings, 1 checks, 41 lines checked 88223875cb87 drm/i915: move i915_reset_count()/i915_reset_engine_count() out of i915_drv.h 7ae42d3f0003 drm/i915: split out i915_file_private.h from i915_drv.h -:209: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #209: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 279 lines checked 7130b228f332 drm/i915: don't include drm_cache.h in i915_drv.h 77dc444c0e4e drm/i915: include shmem_fs.h only where needed f23b4aa08e52 drm/i915: include some drm headers only where needed 93ece4d15229 drm/i915: axe lots of unnecessary includes from i915_drv.h 87ebd22e9262 drm/i915: fix drm_i915.h include grouping and sorting
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: drm_i915.h cleanup
== Series Details == Series: drm/i915: drm_i915.h cleanup URL : https://patchwork.freedesktop.org/series/99979/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register
DMC_DEBUGU3 changes from DG1+
Bspec: 49788
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004d470f..87fc4b9b7b93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -474,8 +474,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
* reg for DC3CO debugging and validation,
* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
*/
- seq_printf(m, "DC3CO count: %d\n",
- intel_de_read(dev_priv, DMC_DEBUG3));
+ if (IS_DGFX(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv, DG1_DMC_DEBUG3));
+ else
+ seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv, DMC_DEBUG3));
} else {
dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
SKL_DMC_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c92314ee26..802962e3977c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5633,6 +5633,7 @@
#define DG1_DMC_DEBUG_DC5_COUNT_MMIO(0x134154)
#define DMC_DEBUG3 _MMIO(0x101090)
+#define DG1_DMC_DEBUG3 _MMIO(0x13415C)
/* Display Internal Timeout Register */
#define RM_TIMEOUT _MMIO(0x42060)
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: drm_i915.h cleanup
== Series Details ==
Series: drm/i915: drm_i915.h cleanup
URL : https://patchwork.freedesktop.org/series/99979/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11214 -> Patchwork_22241
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/index.html
Participating hosts (45 -> 41)
--
Additional (1): fi-adl-ddr4
Missing(5): fi-hsw-4200u fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22241 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [PASS][3] -> [DMESG-FAIL][4] ([i915#3987])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#5026])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][7] ([i915#2426] / [i915#4312])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-bdw-5557u/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#2403] /
[i915#2426] / [i915#4312])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][9] ([i915#4785]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@sanitycheck:
- fi-skl-6600u: [SKIP][11] ([fdo#109271]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-skl-6600u/igt@i915_selftest@l...@sanitycheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/fi-skl-6600u/igt@i915_selftest@l...@sanitycheck.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][13] ([i915#5068]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22241/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3138]: https://gitlab.freedesktop.org/drm/intel/issues/3138
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
Build changes
-
* Linux: CI_DRM_11214 -> Patchwork_22241
CI-20190529: 20190529
CI_DRM_11214: b9ddf3cdcb94017765655d8d31adc1bb70b11046 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22241: 87ebd22e92626dd1f4961891c249525601dbf7ef @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
87ebd22e9262 drm/i915: fix drm_i915.h include grouping and sorting
93ece4d15229 drm/i915: axe lots of unnecessary includes from i915_drv.h
f23b4aa08e52 drm/i915: include some drm headers only where needed
77dc444c0e4e drm/i915: include shmem_fs.h o
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/opregion: fixes and cleanups, RESEND (rev2)
== Series Details ==
Series: drm/i915/opregion: fixes and cleanups, RESEND (rev2)
URL : https://patchwork.freedesktop.org/series/99961/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a8ab1a151539 drm/i915/opregion: check port number bounds for SWSCI display
power state
e88f72d2c213 drm/i915/opregion: abstract the check for valid swsci function
5eaa46766bee drm/i915/opregion: early exit from encoder notify if SWSCI isn't
there
7589a849f6e4 drm/i915/opregion: handle SWSCI Mailbox #2 obsoletion
775f1f2bd450 drm/i915/opregion: debug log about Mailbox #2 for backlight
-:40: WARNING:BRACES: braces {} are not necessary for single statement blocks
#40: FILE: drivers/gpu/drm/i915/display/intel_opregion.c:961:
+ if (mboxes & MBOX_BACKLIGHT) {
+ drm_dbg(&dev_priv->drm, "Mailbox #2 for backlight present\n");
+ }
total: 0 errors, 1 warnings, 0 checks, 25 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Fix the plane end Y offset check
== Series Details ==
Series: drm/i915/fbc: Fix the plane end Y offset check
URL : https://patchwork.freedesktop.org/series/99958/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11212_full -> Patchwork_22238_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22238_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_create@madvise@smem:
- {shard-rkl}:[DMESG-WARN][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-rkl-5/igt@gem_exec_create@madv...@smem.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-rkl-5/igt@gem_exec_create@madv...@smem.html
* igt@gem_userptr_blits@stress-mm:
- {shard-rkl}:[PASS][3] -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-rkl-2/igt@gem_userptr_bl...@stress-mm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-rkl-5/igt@gem_userptr_bl...@stress-mm.html
* igt@i915_hangman@gt-engine-hang@rcs0:
- {shard-rkl}:[PASS][5] -> [INCOMPLETE][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-rkl-1/igt@i915_hangman@gt-engine-h...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-rkl-5/igt@i915_hangman@gt-engine-h...@rcs0.html
Known issues
Here are the changes found in Patchwork_22238_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-skl: ([PASS][7], [PASS][8], [PASS][9], [PASS][10],
[PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16],
[PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22],
[FAIL][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28],
[PASS][29], [PASS][30]) ([i915#5032]) -> ([PASS][31], [PASS][32], [PASS][33],
[PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39],
[PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45],
[PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51],
[PASS][52], [PASS][53], [PASS][54])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl9/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl9/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl8/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl8/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl7/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl7/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl7/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl6/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl6/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl6/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl4/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl4/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl4/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl3/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl3/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl3/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl2/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl2/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl1/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl1/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl1/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl10/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl10/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11212/shard-skl10/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-skl9/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-skl9/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-skl9/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-skl8/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22238/shard-s
Re: [Intel-gfx] [PATCH] drm/i915/dg1: Update DMC_DEBUG3 register
On 10/02/2022 16:44, Anusha Srivatsa wrote:
DMC_DEBUGU3 changes from DG1+
Bspec: 49788
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 --
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f4de004d470f..87fc4b9b7b93 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -474,8 +474,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
* reg for DC3CO debugging and validation,
* but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
*/
- seq_printf(m, "DC3CO count: %d\n",
- intel_de_read(dev_priv, DMC_DEBUG3));
+ if (IS_DGFX(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv, DG1_DMC_DEBUG3));
+ else
+ seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv, DMC_DEBUG3));
Nicer not to duplicate it all and use ternary:
seq_printf(m, "DC3CO count: %d\n",
intel_de_read(dev_priv,
IS_DGFX(dev_priv) ?
DG1_DMC_DEBUG3 : DMC_DEBUG3));
?
Regards,
Tvrtko
} else {
dc5_reg = IS_BROXTON(dev_priv) ? BXT_DMC_DC3_DC5_COUNT :
SKL_DMC_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87c92314ee26..802962e3977c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5633,6 +5633,7 @@
#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
#define DMC_DEBUG3 _MMIO(0x101090)
+#define DG1_DMC_DEBUG3 _MMIO(0x13415C)
/* Display Internal Timeout Register */
#define RM_TIMEOUT_MMIO(0x42060)
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/opregion: fixes and cleanups, RESEND (rev2)
== Series Details ==
Series: drm/i915/opregion: fixes and cleanups, RESEND (rev2)
URL : https://patchwork.freedesktop.org/series/99961/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11214 -> Patchwork_22242
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/index.html
Participating hosts (46 -> 37)
--
Additional (3): fi-icl-u2 fi-adl-ddr4 fi-pnv-d510
Missing(12): fi-bdw-samus shard-tglu bat-dg1-6 fi-hsw-4200u fi-bsw-cyan
bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1
Known issues
Here are the changes found in Patchwork_22242 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-skl-6600u/igt@i915_selft...@live.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-blb-e6850/igt@i915_selftest@l...@gem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-x1275: [PASS][7] -> [DMESG-FAIL][8] ([i915#2291] /
[i915#541])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-kbl-x1275/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[PASS][9] -> [INCOMPLETE][10] ([i915#3921])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#109278]) +2 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109285])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510:NOTRUN -> [SKIP][14] ([fdo#109271]) +57 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-pnv-d510/igt@prime_v...@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#3301])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-icl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2403] /
[i915#2426] / [i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][17] ([i915#4269]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
Warnings
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][19] ([i915#4785]) -> [INCOMPLETE][20]
([i915#3303])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22242/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
Re: [Intel-gfx] [PATCH v4 00/14] drm/i915: drm_i915.h cleanup
On 10/02/2022 15:45, Jani Nikula wrote: I've sent parts of this before. Another rebase round. All look good to me. Acked-by: Tvrtko Ursulin Going forward you can maybe impress the readers even more by including the before/after of your header tree / depth counter script. :) Regards, Tvrtko Jani Nikula (14): drm/i915: split out i915_gem_internal.h from i915_drv.h drm/i915: remove leftover i915_gem_pm.h declarations from i915_drv.h drm/i915: split out gem/i915_gem_dmabuf.h from i915_drv.h drm/i915: split out gem/i915_gem_create.h from i915_drv.h drm/i915: split out gem/i915_gem_domain.h from i915_drv.h drm/i915: move i915_cache_level_str() static in i915_debugfs.c drm/i915: move i915_gem_vm_lookup() where it's used drm/i915: move i915_reset_count()/i915_reset_engine_count() out of i915_drv.h drm/i915: split out i915_file_private.h from i915_drv.h drm/i915: don't include drm_cache.h in i915_drv.h drm/i915: include shmem_fs.h only where needed drm/i915: include some drm headers only where needed drm/i915: axe lots of unnecessary includes from i915_drv.h drm/i915: fix drm_i915.h include grouping and sorting drivers/gpu/drm/i915/display/intel_dpt.c | 4 +- drivers/gpu/drm/i915/display/intel_dsb.c | 2 + drivers/gpu/drm/i915/display/intel_fb_pin.c | 1 + drivers/gpu/drm/i915/display/intel_overlay.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 ++ drivers/gpu/drm/i915/gem/i915_gem_create.c| 3 + drivers/gpu/drm/i915/gem/i915_gem_create.h| 17 ++ drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h| 18 ++ drivers/gpu/drm/i915/gem/i915_gem_domain.c| 5 +- drivers/gpu/drm/i915/gem/i915_gem_domain.h| 15 ++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_internal.h | 23 +++ drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_object.c| 5 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 + drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 + .../gpu/drm/i915/gem/selftests/huge_pages.c | 3 +- .../drm/i915/gem/selftests/i915_gem_context.c | 1 + .../drm/i915/gem/selftests/i915_gem_mman.c| 4 +- .../drm/i915/gem/selftests/igt_gem_utils.c| 1 + .../gpu/drm/i915/gem/selftests/mock_context.c | 1 + drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- drivers/gpu/drm/i915/gt/intel_gt.c| 7 +- .../gpu/drm/i915/gt/intel_gt_buffer_pool.c| 1 + drivers/gpu/drm/i915/gt/intel_gtt.c | 1 + drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 + drivers/gpu/drm/i915/gt/intel_reset.c | 1 + drivers/gpu/drm/i915/gt/intel_ring.c | 1 + .../gpu/drm/i915/gt/intel_ring_submission.c | 4 + drivers/gpu/drm/i915/gt/intel_timeline.c | 5 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 1 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 + drivers/gpu/drm/i915/gt/selftest_migrate.c| 2 + drivers/gpu/drm/i915/gt/selftest_rps.c| 2 + .../gpu/drm/i915/gt/selftest_workarounds.c| 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 + drivers/gpu/drm/i915/gvt/dmabuf.c | 5 + drivers/gpu/drm/i915/i915_cmd_parser.c| 2 + drivers/gpu/drm/i915/i915_debugfs.c | 11 ++ drivers/gpu/drm/i915/i915_driver.c| 3 + drivers/gpu/drm/i915/i915_drv.h | 184 +- drivers/gpu/drm/i915/i915_file_private.h | 108 ++ drivers/gpu/drm/i915/i915_gem.c | 7 +- drivers/gpu/drm/i915/i915_gpu_error.c | 1 + drivers/gpu/drm/i915/i915_gpu_error.h | 11 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_perf.c | 2 + drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +- .../gpu/drm/i915/selftests/i915_gem_evict.c | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 1 + drivers/gpu/drm/i915/selftests/i915_vma.c | 1 + drivers/gpu/drm/i915/selftests/igt_spinner.c | 1 + 61 files changed, 329 insertions(+), 199 deletions(-) create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_create.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_domain.h create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_internal.h create mode 100644 drivers/gpu/drm/i915/i
Re: [Intel-gfx] [PATCH v11 5/5] drm/amdgpu: add drm buddy support to amdgpu
On 08/02/2022 11:20, Arunpravin wrote:
On 04/02/22 6:53 pm, Christian König wrote:
Am 04.02.22 um 12:22 schrieb Arunpravin:
On 28/01/22 7:48 pm, Matthew Auld wrote:
On Thu, 27 Jan 2022 at 14:11, Arunpravin
wrote:
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
v2(Matthew Auld):
- replace spinlock with mutex as we call kmem_cache_zalloc
(..., GFP_KERNEL) in drm_buddy_alloc() function
- lock drm_buddy_block_trim() function as it calls
mark_free/mark_split are all globally visible
v3(Matthew Auld):
- remove trim method error handling as we address the failure case
at drm_buddy_block_trim() function
v4:
- fix warnings reported by kernel test robot
v5:
- fix merge conflict issue
v6:
- fix warnings reported by kernel test robot
Signed-off-by: Arunpravin
---
drivers/gpu/drm/Kconfig | 1 +
.../gpu/drm/amd/amdgpu/amdgpu_res_cursor.h| 97 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 259 ++
4 files changed, 231 insertions(+), 133 deletions(-)
-/**
- * amdgpu_vram_mgr_virt_start - update virtual start address
- *
- * @mem: ttm_resource to update
- * @node: just allocated node
- *
- * Calculate a virtual BO start address to easily check if everything is CPU
- * accessible.
- */
-static void amdgpu_vram_mgr_virt_start(struct ttm_resource *mem,
- struct drm_mm_node *node)
-{
- unsigned long start;
-
- start = node->start + node->size;
- if (start > mem->num_pages)
- start -= mem->num_pages;
- else
- start = 0;
- mem->start = max(mem->start, start);
-}
-
/**
* amdgpu_vram_mgr_new - allocate new ranges
*
@@ -366,13 +357,13 @@ static int amdgpu_vram_mgr_new(struct
ttm_resource_manager *man,
const struct ttm_place *place,
struct ttm_resource **res)
{
- unsigned long lpfn, num_nodes, pages_per_node, pages_left, pages;
+ unsigned long lpfn, pages_per_node, pages_left, pages, n_pages;
+ u64 vis_usage = 0, mem_bytes, max_bytes, min_page_size;
struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
struct amdgpu_device *adev = to_amdgpu_device(mgr);
- uint64_t vis_usage = 0, mem_bytes, max_bytes;
- struct ttm_range_mgr_node *node;
- struct drm_mm *mm = &mgr->mm;
- enum drm_mm_insert_mode mode;
+ struct amdgpu_vram_mgr_node *node;
+ struct drm_buddy *mm = &mgr->mm;
+ struct drm_buddy_block *block;
unsigned i;
int r;
@@ -391,10 +382,9 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
goto error_sub;
}
- if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
+ if (place->flags & TTM_PL_FLAG_CONTIGUOUS)
pages_per_node = ~0ul;
- num_nodes = 1;
- } else {
+ else {
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
pages_per_node = HPAGE_PMD_NR;
#else
@@ -403,11 +393,9 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
#endif
pages_per_node = max_t(uint32_t, pages_per_node,
tbo->page_alignment);
- num_nodes = DIV_ROUND_UP_ULL(PFN_UP(mem_bytes), pages_per_node);
}
- node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
- GFP_KERNEL | __GFP_ZERO);
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node) {
r = -ENOMEM;
goto error_sub;
@@ -415,9 +403,17 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
ttm_resource_init(tbo, place, &node->base);
- mode = DRM_MM_INSERT_BEST;
+ INIT_LIST_HEAD(&node->blocks);
+
if (place->flags & TTM_PL_FLAG_TOPDOWN)
- mode = DRM_MM_INSERT_HIGH;
+ node->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+
+ if (place->fpfn || lpfn != man->size)
+ /* Allocate blocks in desired range */
+ node->flags |= DRM_BUDDY_RANGE_ALLOCATION;
+
+ min_page_size = mgr->default_page_size;
+ BUG_ON(min_page_size < mm->chunk_size);
pages_left = node->base.num_pages;
@@ -425,36 +421,61 @@ static int amdgpu_vram_mgr_new(struct
ttm_resource_manager *man,
pages = min(pages_left, 2UL << (30 - PAGE_SHIFT));
i = 0;
- spin_lock(&mgr->lock);
while (pages_left) {
- uint32_t alignment = tbo->page_alignment;
-
if (pages >= pages_per_node)
- alignment = pages_per_node;
-
- r = drm_mm_insert_node_in_range(mm, &node->mm_nodes[i], pages,
- alignment, 0, place->fpfn,
-
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg1: Update DMC_DEBUG3 register (rev2)
== Series Details == Series: drm/i915/dg1: Update DMC_DEBUG3 register (rev2) URL : https://patchwork.freedesktop.org/series/99942/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: Update DMC_DEBUG3 register (rev2)
== Series Details ==
Series: drm/i915/dg1: Update DMC_DEBUG3 register (rev2)
URL : https://patchwork.freedesktop.org/series/99942/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11214 -> Patchwork_22243
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/index.html
Participating hosts (46 -> 43)
--
Additional (2): fi-adl-ddr4 fi-pnv-d510
Missing(5): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22243 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +39 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#4957])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:NOTRUN -> [DMESG-FAIL][8] ([i915#2927])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#2403] /
[i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-pnv-d510/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][10] ([i915#4785]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@sanitycheck:
- fi-skl-6600u: [SKIP][12] ([fdo#109271]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-skl-6600u/igt@i915_selftest@l...@sanitycheck.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-skl-6600u/igt@i915_selftest@l...@sanitycheck.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][14] ([i915#5068]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][16] ([i915#4269]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11214/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22243/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3138]: https://gitlab.freedesktop.org/drm/intel/issues/3138
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5068]: https://gitlab.freedeskto
[Intel-gfx] [PATCH v10 4/6] drm/i915/gt: Re-work reset_csb
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 6186a5e4b191..11b864fd68a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
[Intel-gfx] [PATCH v10 6/6] drm/i915/gt: replace cache_clflush_range
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c| 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx,
1)));
}
} while (1);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx;
}
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
I915_GTT_PAGE_SIZE_2M {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct
i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
- clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+ drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 11b864fd68a5..67dd4b1fc185 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs
*engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val,
unsigned int count)
void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
- clflush_cache_range(&vaddr[idx], sizeof(u64));
+ drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
}
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i91
[Intel-gfx] [PATCH v10 0/6] Use drm_clflush* instead of clflush
This patch series re-work a few i915 functions to use drm_clflush_virt_range instead of calling clflush or clflushopt directly. This will prevent errors when building for non-x86 architectures. v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added more patches to convert additional clflush/clflushopt to use drm_clflush*. (Michael Cheng) v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran v4: Remove extra memory barriers v5: s/cache_clflush_range/drm_clflush_virt_range v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also added in arm64 support for drm_clflush_virt_range. v7: Re-order patches, and use correct macro for dcache flush for arm64. v8: Remove ifdef for asm/cacheflush. v9: Rebased v10: Replaced asm/cacheflush with linux/cacheflush Michael Cheng (6): drm: Add arch arm64 for drm_clflush_virt_range drm/i915/gt: Re-work intel_write_status_page drm/i915/gt: Drop invalidate_csb_entries drm/i915/gt: Re-work reset_csb drm/i915/: Re-work clflush_write32 drm/i915/gt: replace cache_clflush_range drivers/gpu/drm/drm_cache.c | 6 ++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 8 +++- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +-- drivers/gpu/drm/i915/gt/intel_engine.h| 13 .../drm/i915/gt/intel_execlists_submission.c | 20 +++ drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 8 files changed, 29 insertions(+), 36 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH v10 3/6] drm/i915/gt: Drop invalidate_csb_entries
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng
---
.../gpu/drm/i915/gt/intel_execlists_submission.c| 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..6186a5e4b191 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists *
const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct
i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs
*engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size *
+ sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
[Intel-gfx] [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..2e233f53331e 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström
*/
+#include
#include
#include
#include
@@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
+
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
--
2.25.1
[Intel-gfx] [PATCH v10 2/6] drm/i915/gt: Re-work intel_write_status_page
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include
#include
+#include
#include
#include
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine,
int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
[Intel-gfx] [PATCH v10 5/6] drm/i915/: Re-work clflush_write32
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value,
unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
