Re: [Intel-gfx] [PATCH] drm/i915: remove writeback hook
On 14/12/2021 18:07, Matthew Auld wrote:
Ditch the writeback hook and drop i915_gem_object_writeback(). We
already support the shrinker_release_pages hook which can just call
shmem_writeback directly.
Looks like a good cleanup to me.
Reviewed-by: Tvrtko Ursulin
A couple of bike shedding comments/question only below.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 --
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 19 ++-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 12
5 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 66f20b803b01..aaf9183e601b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -455,7 +455,6 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
int i915_gem_object_truncate(struct drm_i915_gem_object *obj);
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
/**
* i915_gem_object_pin_map - return a contiguous mapping of the entire object
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index f9f7e44099fe..00c844caeabd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,7 +57,6 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
- void (*writeback)(struct drm_i915_gem_object *obj);
int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
bool no_gpu_wait,
bool should_writeback);
Perhaps a simple shrink for the vfunc name would suffice and match
better with the neighbouring names?
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 49c6e55c68ce..52e975f57956 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -168,16 +168,6 @@ int i915_gem_object_truncate(struct drm_i915_gem_object
*obj)
return 0;
}
-/* Try to discard unwanted pages */
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj)
-{
- assert_object_held_shared(obj);
- GEM_BUG_ON(i915_gem_object_has_pages(obj));
-
- if (obj->ops->writeback)
- obj->ops->writeback(obj);
-}
-
static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
{
struct radix_tree_iter iter;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index cc9fe258fba7..7fdf4fa10b0e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,6 +331,23 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
}
+static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
+ bool no_gpu_wait,
+ bool writeback)
+{
+ switch (obj->mm.madv) {
+ case I915_MADV_DONTNEED:
+ return i915_gem_object_truncate(obj);
+ case __I915_MADV_PURGED:
+ return 0;
+ }
+
+ if (writeback)
+ shmem_writeback(obj);
+
+ return 0;
+}
+
void
__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -503,7 +520,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
- .writeback = shmem_writeback,
+ .shrinker_release_pages = shmem_shrinker_release_pages,
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 157a9765f483..fd54e05521f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -61,18 +61,6 @@ static int try_to_writeback(struct drm_i915_gem_object *obj,
unsigned int flags)
return obj->ops->shrinker_release_pages(obj,
!(flags &
I915_SHRINK_ACTIVE),
flags &
I915_SHRINK_WRITEBACK);
Maybe flags would be better than two booleans? (Usually more than one is
one two many when readability is concer
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Ville Syrjälä > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > On Mon, 13 Dec 2021, Ville Syrjala wrote: > > > > > > This one is only used in gvt, anyway. And that actually makes me wonder > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > gvt with register define changes but I've always caught it before > > pushing. I think I have gvt enabled in my "make sure all commits build > > before I push" test config, so maybe that's where I caught most of them. > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > builds? > > Actually cc Tomi.. GVT-d is enabled and tested by fi-bdw-gvtdvm. Tomi
Re: [Intel-gfx] [PATCH 0/3] drm/dp: Move DisplayPort helpers into own module
On Mon, 13 Dec 2021, Thomas Zimmermann wrote: > Hi > > Am 13.12.21 um 14:34 schrieb Jani Nikula: >> On Mon, 13 Dec 2021, Thomas Zimmermann wrote: >>> Split-off DisplayPort functions from KMS helper library and move them >>> into their own module. Reduces the size of drm_kms_helper.ko by ~50%. >>> >>> This patchset is part of an on-going effort to reduce the minimum >>> binary size of the DRM core and helpers. It's helpful for systems with >>> early-boot DRM graphics, which requires DRM to be linked into the >>> kernel image. >> >> Would it be time to add a subdirectory for each non-driver, non-core drm >> module? We've touched this topic before. I find it increasingly hard to >> remember which files are part of helpers. This would also help with the >> arbitrary drm_dp_helper_mod.c naming. >> >> Perhaps drivers/gpu/drm/drm_dp/? > > It's probably worth it, but I'd prefer a separate patchset and > discussion over this. It affects several modules. I guess the only thing here that we need to get right from the start is the new module name, everything else is relatively easy to change later. drm_dp_helper.ko seems fine by me. Note that this will also affect the drm_kms_helper.ko module parameters dp_aux_i2c_speed_khz, dp_aux_i2c_transfer_size and drm_dp_cec_unregister_delay, which will move to drm_dp_helper.ko. See the monstrosity near the top of drm_kms_helper_common.c I had to add for backward compatibility when I moved drm_edid_load.c from drm_kms_helper.ko to drm.ko. That was perhaps different, as these seem more like debug knobs, but at a minimum this needs to be mentioned in the commit message, and certainly needs acks from Dave and/or Daniel. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 0/7] drm/i915: Asynchronous vma unbinding
This patch series introduces infrastructure for asynchronous vma unbinding. The single enabled use-case is initially at buffer object migration where we otherwise sync when unbinding vmas before migration. This in theory allows us to pipeline any number of migrations, but in practice the number is restricted by a sync wait when filling the migration context ring. We might want to look at that moving forward if needed. The other main use-case is to be able to pipeline vma evictions, for example with softpinning where a new vma wants to reuse the vm range of an already active vma. We can't support this just yet because we need dma_resv locking around vma eviction for that, which is under implementation. Patch 1 and 2 are mainly a fix and a subsequent rearrangement of code, Patch 3 is needed for consistent bind locking, Patch 4 introduces vma resource first for error capture purposes. Patch 5 changes the vm backend interface to take vma resources rather than vmas, Patch 6 introduces the async unbinding itself, and finally Patch 7 realizes we have duplicated functionality and removes the vma snapshots. Thomas Hellström (7): drm/i915: Avoid using the i915_fence_array when collecting dependencies drm/i915: Break out the i915_deps utility drm/i915: Require the vm mutex for i915_vma_bind() drm/i915: Initial introduction of vma resources drm/i915: Use the vma resource as argument for gtt binding / unbinding drm/i915: Use vma resources for async unbinding drm/i915: Use struct vma_resource instead of struct vma_snapshot drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/display/intel_dpt.c | 27 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 67 +++- .../gpu/drm/i915/gem/i915_gem_object_types.h | 27 +- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 303 ++- .../gpu/drm/i915/gem/selftests/huge_pages.c | 37 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 19 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 37 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 70 ++-- drivers/gpu/drm/i915/gt/intel_gtt.c | 4 + drivers/gpu/drm/i915/gt/intel_gtt.h | 18 +- drivers/gpu/drm/i915/gt/intel_migrate.c | 24 +- drivers/gpu/drm/i915/gt/intel_migrate.h | 9 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 22 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 13 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_deps.c | 249 drivers/gpu/drm/i915/i915_deps.h | 46 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 3 + drivers/gpu/drm/i915/i915_gpu_error.c | 87 ++--- drivers/gpu/drm/i915/i915_request.c | 34 +- drivers/gpu/drm/i915/i915_request.h | 8 +- drivers/gpu/drm/i915/i915_vma.c | 207 +- drivers/gpu/drm/i915/i915_vma.h | 33 +- drivers/gpu/drm/i915/i915_vma_resource.c | 357 ++ drivers/gpu/drm/i915/i915_vma_resource.h | 223 +++ drivers/gpu/drm/i915/i915_vma_snapshot.c | 134 --- drivers/gpu/drm/i915/i915_vma_snapshot.h | 112 -- drivers/gpu/drm/i915/i915_vma_types.h | 5 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 159 +--- drivers/gpu/drm/i915/selftests/mock_gtt.c | 12 +- 34 files changed, 1528 insertions(+), 836 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_deps.c create mode 100644 drivers/gpu/drm/i915/i915_deps.h create mode 100644 drivers/gpu/drm/i915/i915_vma_resource.c create mode 100644 drivers/gpu/drm/i915/i915_vma_resource.h delete mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.c delete mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.h -- 2.31.1
[Intel-gfx] [PATCH 1/7] drm/i915: Avoid using the i915_fence_array when collecting dependencies
Since the gt migration code was using only a single fence for
dependencies, these were collected in a dma_fence_array. However, it
turns out that it's illegal to use some dma_fences in a dma_fence_array,
in particular other dma_fence_arrays and dma_fence_chains, and this
causes trouble for us moving forward.
Have the gt migration code instead take a const struct i915_deps for
dependencies. This means we can skip the dma_fence_array creation
and instead pass the struct i915_deps instead to circumvent the
problem.
Fixes: 5652df829b3c ("drm/i915/ttm: Update i915_gem_obj_copy_ttm() to be
asynchronous")
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 115 +--
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h | 17 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 24 ++--
drivers/gpu/drm/i915/gt/intel_migrate.h | 9 +-
drivers/gpu/drm/i915/i915_request.c | 22
drivers/gpu/drm/i915/i915_request.h | 2 +
6 files changed, 86 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..09463874ef24 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -3,8 +3,6 @@
* Copyright © 2021 Intel Corporation
*/
-#include
-
#include
#include "i915_drv.h"
@@ -65,32 +63,13 @@ void i915_ttm_migrate_set_failure_modes(bool gpu_migration,
* A struct i915_deps need to be initialized using i915_deps_init().
* If i915_deps_add_dependency() or i915_deps_add_resv() return an
* error code they will internally call i915_deps_fini(), which frees
- * all internal references and allocations. After a call to
- * i915_deps_to_fence(), or i915_deps_sync(), the struct should similarly
- * be viewed as uninitialized.
+ * all internal references and allocations.
*
* We might want to break this out into a separate file as a utility.
*/
#define I915_DEPS_MIN_ALLOC_CHUNK 8U
-/**
- * struct i915_deps - Collect dependencies into a single dma-fence
- * @single: Storage for pointer if the collection is a single fence.
- * @fence: Allocated array of fence pointers if more than a single fence;
- * otherwise points to the address of @single.
- * @num_deps: Current number of dependency fences.
- * @fences_size: Size of the @fences array in number of pointers.
- * @gfp: Allocation mode.
- */
-struct i915_deps {
- struct dma_fence *single;
- struct dma_fence **fences;
- unsigned int num_deps;
- unsigned int fences_size;
- gfp_t gfp;
-};
-
static void i915_deps_reset_fences(struct i915_deps *deps)
{
if (deps->fences != &deps->single)
@@ -163,7 +142,7 @@ static int i915_deps_grow(struct i915_deps *deps, struct
dma_fence *fence,
return ret;
}
-static int i915_deps_sync(struct i915_deps *deps,
+static int i915_deps_sync(const struct i915_deps *deps,
const struct ttm_operation_ctx *ctx)
{
struct dma_fence **fences = deps->fences;
@@ -183,7 +162,6 @@ static int i915_deps_sync(struct i915_deps *deps,
break;
}
- i915_deps_fini(deps);
return ret;
}
@@ -221,34 +199,6 @@ static int i915_deps_add_dependency(struct i915_deps *deps,
return i915_deps_grow(deps, fence, ctx);
}
-static struct dma_fence *i915_deps_to_fence(struct i915_deps *deps,
- const struct ttm_operation_ctx *ctx)
-{
- struct dma_fence_array *array;
-
- if (deps->num_deps == 0)
- return NULL;
-
- if (deps->num_deps == 1) {
- deps->num_deps = 0;
- return deps->fences[0];
- }
-
- /*
-* TODO: Alter the allocation mode here to not try too hard to
-* make things async.
-*/
- array = dma_fence_array_create(deps->num_deps, deps->fences, 0, 0,
- false);
- if (!array)
- return ERR_PTR(i915_deps_sync(deps, ctx));
-
- deps->fences = NULL;
- i915_deps_reset_fences(deps);
-
- return &array->base;
-}
-
static int i915_deps_add_resv(struct i915_deps *deps, struct dma_resv *resv,
bool all, const bool no_excl,
const struct ttm_operation_ctx *ctx)
@@ -387,7 +337,7 @@ static struct dma_fence *i915_ttm_accel_move(struct
ttm_buffer_object *bo,
struct ttm_resource *dst_mem,
struct ttm_tt *dst_ttm,
struct sg_table *dst_st,
-struct dma_fence *dep)
+const struct i915_deps *deps)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
bdev);
@@ -4
[Intel-gfx] [PATCH 2/7] drm/i915: Break out the i915_deps utility
Since it's starting to be used outside the i915 TTM move code, move it
to a separate set of files.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 181 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h | 17 --
drivers/gpu/drm/i915/i915_deps.c | 249 +++
drivers/gpu/drm/i915/i915_deps.h | 46
drivers/gpu/drm/i915/i915_request.c | 2 +-
6 files changed, 298 insertions(+), 198 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_deps.c
create mode 100644 drivers/gpu/drm/i915/i915_deps.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6ddd2d2bbaaf..1b62b9f65196 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -163,6 +163,7 @@ i915-y += \
i915_active.o \
i915_buddy.o \
i915_cmd_parser.o \
+ i915_deps.o \
i915_gem_evict.o \
i915_gem_gtt.o \
i915_gem_ww.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 09463874ef24..4b6f3cda15b6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -5,6 +5,7 @@
#include
+#include "i915_deps.h"
#include "i915_drv.h"
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
@@ -41,186 +42,6 @@ void i915_ttm_migrate_set_failure_modes(bool gpu_migration,
}
#endif
-/**
- * DOC: Set of utilities to dynamically collect dependencies and
- * eventually coalesce them into a single fence which is fed into
- * the GT migration code, since it only accepts a single dependency
- * fence.
- * The single fence returned from these utilities, in the case of
- * dependencies from multiple fence contexts, a struct dma_fence_array,
- * since the i915 request code can break that up and await the individual
- * fences.
- *
- * Once we can do async unbinding, this is also needed to coalesce
- * the migration fence with the unbind fences.
- *
- * While collecting the individual dependencies, we store the refcounted
- * struct dma_fence pointers in a realloc-managed pointer array, since
- * that can be easily fed into a dma_fence_array. Other options are
- * available, like for example an xarray for similarity with drm/sched.
- * Can be changed easily if needed.
- *
- * A struct i915_deps need to be initialized using i915_deps_init().
- * If i915_deps_add_dependency() or i915_deps_add_resv() return an
- * error code they will internally call i915_deps_fini(), which frees
- * all internal references and allocations.
- *
- * We might want to break this out into a separate file as a utility.
- */
-
-#define I915_DEPS_MIN_ALLOC_CHUNK 8U
-
-static void i915_deps_reset_fences(struct i915_deps *deps)
-{
- if (deps->fences != &deps->single)
- kfree(deps->fences);
- deps->num_deps = 0;
- deps->fences_size = 1;
- deps->fences = &deps->single;
-}
-
-static void i915_deps_init(struct i915_deps *deps, gfp_t gfp)
-{
- deps->fences = NULL;
- deps->gfp = gfp;
- i915_deps_reset_fences(deps);
-}
-
-static void i915_deps_fini(struct i915_deps *deps)
-{
- unsigned int i;
-
- for (i = 0; i < deps->num_deps; ++i)
- dma_fence_put(deps->fences[i]);
-
- if (deps->fences != &deps->single)
- kfree(deps->fences);
-}
-
-static int i915_deps_grow(struct i915_deps *deps, struct dma_fence *fence,
- const struct ttm_operation_ctx *ctx)
-{
- int ret;
-
- if (deps->num_deps >= deps->fences_size) {
- unsigned int new_size = 2 * deps->fences_size;
- struct dma_fence **new_fences;
-
- new_size = max(new_size, I915_DEPS_MIN_ALLOC_CHUNK);
- new_fences = kmalloc_array(new_size, sizeof(*new_fences),
deps->gfp);
- if (!new_fences)
- goto sync;
-
- memcpy(new_fences, deps->fences,
- deps->fences_size * sizeof(*new_fences));
- swap(new_fences, deps->fences);
- if (new_fences != &deps->single)
- kfree(new_fences);
- deps->fences_size = new_size;
- }
- deps->fences[deps->num_deps++] = dma_fence_get(fence);
- return 0;
-
-sync:
- if (ctx->no_wait_gpu && !dma_fence_is_signaled(fence)) {
- ret = -EBUSY;
- goto unref;
- }
-
- ret = dma_fence_wait(fence, ctx->interruptible);
- if (ret)
- goto unref;
-
- ret = fence->error;
- if (ret)
- goto unref;
-
- return 0;
-
-unref:
- i915_deps_fini(deps);
- return ret;
-}
-
-static int i915_deps_sync(const struct i915_deps *deps,
- const struct ttm_operation_ctx *ctx)
-{
- struct dma_fence **fences = de
[Intel-gfx] [PATCH 3/7] drm/i915: Require the vm mutex for i915_vma_bind()
Protect updates of struct i915_vma flags and async binding / unbinding
with the vm::mutex. This means that i915_vma_bind() needs to assert
vm::mutex held. In order to make that possible drop the caching of
kmap_atomic() maps around i915_vma_bind().
An alternative would be to use kmap_local() but since we block cpu
unplugging during sleeps inside kmap_local() sections this may have
unwanted side-effects. Particularly since we might wait for gpu while
holding the vm mutex.
This change may theoretically increase execbuf cpu-usage on snb, but
at least on non-highmem systems that increase should be very small.
Signed-off-by: Thomas Hellström
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 50 ++-
drivers/gpu/drm/i915/i915_vma.c | 1 +
2 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 2213f7b613da..6013f7e18f60 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1109,6 +1109,47 @@ static inline struct i915_ggtt *cache_to_ggtt(struct
reloc_cache *cache)
return &i915->ggtt;
}
+static void reloc_cache_unmap(struct reloc_cache *cache)
+{
+ void *vaddr;
+
+ if (!cache->vaddr)
+ return;
+
+ vaddr = unmask_page(cache->vaddr);
+ if (cache->vaddr & KMAP)
+ kunmap_atomic(vaddr);
+ else
+ io_mapping_unmap_atomic((void __iomem *)vaddr);
+}
+
+static void reloc_cache_remap(struct reloc_cache *cache,
+ struct drm_i915_gem_object *obj)
+{
+ void *vaddr;
+
+ if (!cache->vaddr)
+ return;
+
+ if (cache->vaddr & KMAP) {
+ struct page *page = i915_gem_object_get_page(obj, cache->page);
+
+ vaddr = kmap_atomic(page);
+ cache->vaddr = unmask_flags(cache->vaddr) |
+ (unsigned long)vaddr;
+ } else {
+ struct i915_ggtt *ggtt = cache_to_ggtt(cache);
+ unsigned long offset;
+
+ offset = cache->node.start;
+ if (!drm_mm_node_allocated(&cache->node))
+ offset += cache->page << PAGE_SHIFT;
+
+ cache->vaddr = (unsigned long)
+ io_mapping_map_atomic_wc(&ggtt->iomap, offset);
+ }
+}
+
static void reloc_cache_reset(struct reloc_cache *cache, struct
i915_execbuffer *eb)
{
void *vaddr;
@@ -1373,10 +1414,17 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* batchbuffers.
*/
if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
- GRAPHICS_VER(eb->i915) == 6) {
+ GRAPHICS_VER(eb->i915) == 6 &&
+ !i915_vma_is_bound(target->vma, I915_VMA_GLOBAL_BIND)) {
+ struct i915_vma *vma = target->vma;
+
+ reloc_cache_unmap(&eb->reloc_cache);
+ mutex_lock(&vma->vm->mutex);
err = i915_vma_bind(target->vma,
target->vma->obj->cache_level,
PIN_GLOBAL, NULL);
+ mutex_unlock(&vma->vm->mutex);
+ reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
if (err)
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 927f0d4f8e11..d792a3d0da7a 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -398,6 +398,7 @@ int i915_vma_bind(struct i915_vma *vma,
u32 bind_flags;
u32 vma_flags;
+ lockdep_assert_held(&vma->vm->mutex);
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
GEM_BUG_ON(vma->size > vma->node.size);
--
2.31.1
[Intel-gfx] [PATCH 4/7] drm/i915: Initial introduction of vma resources
Introduce vma resources, sort of similar to TTM resources, needed for
asynchronous bind management. Initially we will use them to hold
completion of unbinding when we capture data from a vma, but they will
be used extensively in upcoming patches for asynchronous vma unbinding.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 +-
drivers/gpu/drm/i915/i915_vma.c | 55 +++-
drivers/gpu/drm/i915/i915_vma.h | 19 ++-
drivers/gpu/drm/i915/i915_vma_resource.c | 124 ++
drivers/gpu/drm/i915/i915_vma_resource.h | 70 ++
drivers/gpu/drm/i915/i915_vma_snapshot.c | 15 +--
drivers/gpu/drm/i915/i915_vma_snapshot.h | 7 +-
drivers/gpu/drm/i915/i915_vma_types.h | 5 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 99 --
10 files changed, 334 insertions(+), 63 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_vma_resource.c
create mode 100644 drivers/gpu/drm/i915/i915_vma_resource.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1b62b9f65196..98433ad74194 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -174,6 +174,7 @@ i915-y += \
i915_trace_points.o \
i915_ttm_buddy_manager.o \
i915_vma.o \
+ i915_vma_resource.o \
i915_vma_snapshot.o \
intel_wopcm.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 6013f7e18f60..b6faae1f9081 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1422,7 +1422,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
mutex_lock(&vma->vm->mutex);
err = i915_vma_bind(target->vma,
target->vma->obj->cache_level,
- PIN_GLOBAL, NULL);
+ PIN_GLOBAL, NULL, NULL);
mutex_unlock(&vma->vm->mutex);
reloc_cache_remap(&eb->reloc_cache, ev->vma->obj);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d792a3d0da7a..4308659bf552 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -37,6 +37,7 @@
#include "i915_sw_fence_work.h"
#include "i915_trace.h"
#include "i915_vma.h"
+#include "i915_vma_resource.h"
static struct kmem_cache *slab_vmas;
@@ -385,6 +386,8 @@ static int i915_vma_verify_bind_complete(struct i915_vma
*vma)
* @cache_level: mapping cache level
* @flags: flags like global or local mapping
* @work: preallocated worker for allocating and binding the PTE
+ * @vma_res: pointer to a preallocated vma resource. The resource is either
+ * consumed or freed.
*
* DMA addresses are taken from the scatter-gather table of this object (or of
* this VMA in case of non-default GGTT views) and PTE entries set up.
@@ -393,7 +396,8 @@ static int i915_vma_verify_bind_complete(struct i915_vma
*vma)
int i915_vma_bind(struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags,
- struct i915_vma_work *work)
+ struct i915_vma_work *work,
+ struct i915_vma_resource *vma_res)
{
u32 bind_flags;
u32 vma_flags;
@@ -404,11 +408,15 @@ int i915_vma_bind(struct i915_vma *vma,
if (GEM_DEBUG_WARN_ON(range_overflows(vma->node.start,
vma->node.size,
- vma->vm->total)))
+ vma->vm->total))) {
+ kfree(vma_res);
return -ENODEV;
+ }
- if (GEM_DEBUG_WARN_ON(!flags))
+ if (GEM_DEBUG_WARN_ON(!flags)) {
+ kfree(vma_res);
return -EINVAL;
+ }
bind_flags = flags;
bind_flags &= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
@@ -417,11 +425,21 @@ int i915_vma_bind(struct i915_vma *vma,
vma_flags &= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
bind_flags &= ~vma_flags;
- if (bind_flags == 0)
+ if (bind_flags == 0) {
+ kfree(vma_res);
return 0;
+ }
GEM_BUG_ON(!vma->pages);
+ if (vma->resource || !vma_res) {
+ /* Rebinding with an additional I915_VMA_*_BIND */
+ GEM_WARN_ON(!vma_flags);
+ kfree(vma_res);
+ } else {
+ i915_vma_resource_init(vma_res);
+ vma->resource = vma_res;
+ }
trace_i915_vma_bind(vma, bind_flags);
if (work && bind_flags & vma->vm->bind_async_flags) {
struct dma_fence *prev;
@@ -897,6 +915,7 @
[Intel-gfx] [PATCH 5/7] drm/i915: Use the vma resource as argument for gtt binding / unbinding
When introducing asynchronous unbinding, the vma itself may no longer
be alive when the actual binding or unbinding takes place.
Update the gtt i915_vma_ops accordingly to take a struct i915_vma_resource
instead of a struct i915_vma for the bind_vma() and unbind_vma() ops.
Similarly change the insert_entries() op for struct i915_address_space.
Replace a couple of i915_vma_snapshot members with their newly introduced
i915_vma_resource counterparts, since they have the same lifetime.
Also make sure to avoid changing the struct i915_vma_flags (in particular
the bind flags) async. That should now only be done sync under the
vm mutex.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/display/intel_dpt.c | 27 ++---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 27 +
.../gpu/drm/i915/gem/selftests/huge_pages.c | 37 +++
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 19 ++--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 37 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 68 ++---
drivers/gpu/drm/i915/gt/intel_gtt.h | 15 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 22 +++--
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 13 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 6 +-
drivers/gpu/drm/i915/i915_vma.c | 24 -
drivers/gpu/drm/i915/i915_vma.h | 11 +--
drivers/gpu/drm/i915/i915_vma_resource.c | 9 +-
drivers/gpu/drm/i915/i915_vma_resource.h | 99 ++-
drivers/gpu/drm/i915/i915_vma_snapshot.c | 4 -
drivers/gpu/drm/i915/i915_vma_snapshot.h | 8 --
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 64
drivers/gpu/drm/i915/selftests/mock_gtt.c | 12 +--
21 files changed, 305 insertions(+), 206 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 963ca7155b06..f9f2a4ef38cd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -48,7 +48,7 @@ static void dpt_insert_page(struct i915_address_space *vm,
}
static void dpt_insert_entries(struct i915_address_space *vm,
- struct i915_vma *vma,
+ struct i915_vma_resource *vma_res,
enum i915_cache_level level,
u32 flags)
{
@@ -64,8 +64,8 @@ static void dpt_insert_entries(struct i915_address_space *vm,
* not to allow the user to override access to a read only page.
*/
- i = vma->node.start / I915_GTT_PAGE_SIZE;
- for_each_sgt_daddr(addr, sgt_iter, vma->pages)
+ i = vma_res->start / I915_GTT_PAGE_SIZE;
+ for_each_sgt_daddr(addr, sgt_iter, vma_res->bi.pages)
gen8_set_pte(&base[i++], pte_encode | addr);
}
@@ -76,35 +76,38 @@ static void dpt_clear_range(struct i915_address_space *vm,
static void dpt_bind_vma(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
-struct i915_vma *vma,
+struct i915_vma_resource *vma_res,
enum i915_cache_level cache_level,
u32 flags)
{
- struct drm_i915_gem_object *obj = vma->obj;
u32 pte_flags;
+ if (vma_res->bound_flags)
+ return;
+
/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
pte_flags = 0;
- if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
+ if (vm->has_read_only && vma_res->bi.readonly)
pte_flags |= PTE_READ_ONLY;
- if (i915_gem_object_is_lmem(obj))
+ if (vma_res->bi.lmem)
pte_flags |= PTE_LM;
- vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
+ vm->insert_entries(vm, vma_res, cache_level, pte_flags);
- vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+ vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
/*
* Without aliasing PPGTT there's no difference between
* GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
* upgrade to both bound if we bind either to avoid double-binding.
*/
- atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
+ vma_res->bound_flags = I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
}
-static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
+static void dpt_unbind_vma(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res)
{
- vm->clear_range(vm, vma->node.start, vma->size);
+ vm->clear_range(vm, vma_res->start, vma_res->vma_size);
}
static void dpt_cleanup(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_t
[Intel-gfx] [PATCH 6/7] drm/i915: Use vma resources for async unbinding
Implement async (non-blocking) unbinding by not syncing the vma before
calling unbind on the vma_resource.
Add the resulting unbind fence to the object's dma_resv from where it is
picked up by the ttm migration code.
Ideally these unbind fences should be coalesced with the migration blit
fence to avoid stalling the migration blit waiting for unbind, as they
can certainly go on in parallel, but since we don't yet have a
reasonable data structure to use to coalesce fences and attach the
resulting fence to a timeline, we defer that for now.
Note that with async unbinding, even while the unbind waits for the
preceding bind to complete before unbinding, the vma itself might have been
destroyed in the process, clearing the vma pages. Therefore we can
only allow async unbinding if we have a refcounted sg-list and keep a
refcount on that for the vma resource pages to stay intact until
binding occurs. If this condition is not met, a request for an async
unbind is diverted to a sync unbind.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 11 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 4 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 3 +
drivers/gpu/drm/i915/i915_vma.c | 171 ++--
drivers/gpu/drm/i915/i915_vma.h | 3 +-
drivers/gpu/drm/i915/i915_vma_resource.c | 274 +--
drivers/gpu/drm/i915/i915_vma_resource.h | 38 +++
10 files changed, 464 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4b6f3cda15b6..ab0bc988b814 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -142,7 +142,16 @@ int i915_ttm_move_notify(struct ttm_buffer_object *bo)
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
int ret;
- ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
+ /*
+* Note: The async unbinding here will actually transform the
+* blocking wait for unbind into a wait before finally submitting
+* evict / migration blit and thus stall the migration timeline
+* which may not be good for overall throughput. We should make
+* sure we await the unbind fences *after* the migration blit
+* instead of *before* as we currently do.
+*/
+ ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE |
+I915_GEM_OBJECT_UNBIND_ASYNC);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index b257a2555d0d..dc3c87565d29 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -145,7 +145,7 @@ void i915_ggtt_suspend_vm(struct i915_address_space *vm)
continue;
if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
- __i915_vma_evict(vma);
+ __i915_vma_evict(vma, false);
drm_mm_remove_node(&vma->node);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 30683c06b344..b582a4c6c3c7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -161,6 +161,9 @@ static void __i915_vm_release(struct work_struct *work)
struct i915_address_space *vm =
container_of(work, struct i915_address_space, release_work);
+ /* Synchronize async unbinds. */
+ i915_vma_resource_bind_dep_sync_all(vm);
+
vm->cleanup(vm);
i915_address_space_fini(vm);
@@ -189,6 +192,7 @@ void i915_address_space_init(struct i915_address_space *vm,
int subclass)
if (!kref_read(&vm->resv_ref))
kref_init(&vm->resv_ref);
+ vm->pending_unbind = RB_ROOT_CACHED;
INIT_WORK(&vm->release_work, __i915_vm_release);
atomic_set(&vm->open, 1);
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 19c2497630e8..b9bd60cb2687 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -267,6 +267,9 @@ struct i915_address_space {
/* Flags used when creating page-table objects for this vm */
unsigned long lmem_pt_obj_flags;
+ /* Interval tree for pending unbind vma resources */
+ struct rb_root_cached pending_unbind;
+
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fd096d821b48..74c760a454ff 100644
--- a/drivers/gpu/drm/i91
[Intel-gfx] [PATCH 7/7] drm/i915: Use struct vma_resource instead of struct vma_snapshot
There is always a struct vma_resource guaranteed to be alive when we
access a corresponding struct vma_snapshot.
So ditch the latter and instead of allocating vma_snapshots, reference
the already existning vma_resource.
This requires a couple of extra members in struct vma_resource but that's
a small price to pay for the simplification.
Signed-off-by: Thomas Hellström
---
drivers/gpu/drm/i915/Makefile | 1 -
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 15 +--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 87 ++--
drivers/gpu/drm/i915/i915_request.c | 12 +-
drivers/gpu/drm/i915/i915_request.h | 6 +-
drivers/gpu/drm/i915/i915_vma.c | 14 +-
drivers/gpu/drm/i915/i915_vma_resource.c | 2 +
drivers/gpu/drm/i915/i915_vma_resource.h | 26 +++-
drivers/gpu/drm/i915/i915_vma_snapshot.c | 125 --
drivers/gpu/drm/i915/i915_vma_snapshot.h | 101 --
11 files changed, 85 insertions(+), 313 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.c
delete mode 100644 drivers/gpu/drm/i915/i915_vma_snapshot.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 98433ad74194..aa86ac33effc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -175,7 +175,6 @@ i915-y += \
i915_ttm_buddy_manager.o \
i915_vma.o \
i915_vma_resource.o \
- i915_vma_snapshot.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b6faae1f9081..51649bbb8cc3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -29,7 +29,6 @@
#include "i915_gem_ioctls.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
-#include "i915_vma_snapshot.h"
struct eb_vma {
struct i915_vma *vma;
@@ -1952,7 +1951,6 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
{
const unsigned int count = eb->buffer_count;
unsigned int i = count, j;
- struct i915_vma_snapshot *vsnap;
while (i--) {
struct eb_vma *ev = &eb->vma[i];
@@ -1962,11 +1960,6 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
if (!(flags & EXEC_OBJECT_CAPTURE))
continue;
- vsnap = i915_vma_snapshot_alloc(GFP_KERNEL);
- if (!vsnap)
- continue;
-
- i915_vma_snapshot_init(vsnap, vma, "user");
for_each_batch_create_order(eb, j) {
struct i915_capture_list *capture;
@@ -1975,10 +1968,9 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
continue;
capture->next = eb->capture_lists[j];
- capture->vma_snapshot = i915_vma_snapshot_get(vsnap);
+ capture->vma_res = i915_vma_resource_get(vma->resource);
eb->capture_lists[j] = capture;
}
- i915_vma_snapshot_put(vsnap);
}
}
@@ -3281,9 +3273,8 @@ eb_requests_create(struct i915_execbuffer *eb, struct
dma_fence *in_fence,
* _onstack interface.
*/
if (eb->batches[i]->vma)
-
i915_vma_snapshot_init_onstack(&eb->requests[i]->batch_snapshot,
- eb->batches[i]->vma,
- "batch");
+ eb->requests[i]->batch_res =
+
i915_vma_resource_get(eb->batches[i]->vma->resource);
if (eb->batch_pool) {
GEM_BUG_ON(intel_context_is_parallel(eb->context));
intel_gt_buffer_pool_mark_active(eb->batch_pool,
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 74aa90587061..d1daa4cc2895 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1708,18 +1708,15 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
{
- struct i915_vma_snapshot *vsnap = &rq->batch_snapshot;
+ struct i915_vma_resource *vma_res = rq->batch_res;
void *ring;
int size;
- if (!i915_vma_snapshot_present(vsnap))
- vsnap = NULL;
-
drm_printf(m,
"[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
rq->head, rq->postfix, rq->tail,
- vsnap ? upper_32_bits(vsnap->vma_resource->start) : ~0u,
- vsnap ? lower_32_bits(vsnap-
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Increment composite fence seqno
== Series Details == Series: drm/i915: Increment composite fence seqno URL : https://patchwork.freedesktop.org/series/98034/ State : success == Summary == CI Bug Log - changes from CI_DRM_11003_full -> Patchwork_21850_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21850_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][1], [FAIL][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [FAIL][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk6/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk8/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk2/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk3/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk3/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk3/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk7/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk5/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk5/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk6/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk5/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11003/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk2/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk3/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk3/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk5/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk6/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21850/shard-glk6/boot.html [44]: https://intel-gfx-ci.01.org/tree/dr
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, First, a heads up that I will be on vacation for the next weeks so Jani will cover the drm-intel-fixes for the next rounds. Now, here goes drm-intel-fixes-2021-12-15: Fix a bound check in the DMC fw load. Thanks, Rodrigo. The following changes since commit 2585cf9dfaaddf00b069673f27bb3f8530e2039c: Linux 5.16-rc5 (2021-12-12 14:53:01 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-12-15 for you to fetch changes up to 53b3495273282aa844c4613d19c3b30558c70c84: drm/i915/display: Fix an unsigned subtraction which can never be negative. (2021-12-14 04:11:10 -0500) Fix a bound check in the DMC fw load. Harshit Mogalapalli (1): drm/i915/display: Fix an unsigned subtraction which can never be negative. drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
[Intel-gfx] [PATCH v2 0/5] drm/dp: Move DisplayPort helpers into own module
Split-off DisplayPort functions from KMS helper library and move them
into their own module. Reduces the size of drm_kms_helper.ko by ~50%.
This patchset is part of an on-going effort to reduce the minimum
binary size of the DRM core and helpers. It's helpful for systems with
early-boot DRM graphics, which requires DRM to be linked into the
kernel image.
v2:
* move helper library into subdirectory (Jani)
* also move DP AUX bus helpers
Thomas Zimmermann (5):
drm/dp_mst: Remove trailing whitespace.
drm/dp: Move DP declarations into separate header file
drm/dp: Move DisplayPort helpers into separate helper module
drm/dp: Move public DisplayPort headers into dp/
drm/dp: Move DisplayPort AUX bus helpers into dp/
drivers/gpu/drm/Kconfig | 8 +
drivers/gpu/drm/Makefile | 12 +++
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +--
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +--
.../drm/amd/display/dc/core/dc_link_dpcd.c| 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +-
drivers/gpu/drm/amd/display/dc/os_types.h | 2 +-
.../gpu/drm/amd/display/include/dpcd_defs.h | 2 +-
.../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 +-
drivers/gpu/drm/bridge/Kconfig| 4 +++
drivers/gpu/drm/bridge/analogix/Kconfig | 2 ++
.../drm/bridge/analogix/analogix-anx6345.c| 2 +-
.../drm/bridge/analogix/analogix-anx78xx.c| 2 +-
.../drm/bridge/analogix/analogix-i2c-dptx.c | 2 +-
.../drm/bridge/analogix/analogix_dp_core.h| 2 +-
drivers/gpu/drm/bridge/analogix/anx7625.c | 2 +-
drivers/gpu/drm/bridge/cadence/Kconfig| 1 +
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 2 +-
.../drm/bridge/cadence/cdns-mhdp8546-core.h | 2 +-
drivers/gpu/drm/bridge/parade-ps8640.c| 4 +--
drivers/gpu/drm/bridge/tc358767.c | 2 +-
drivers/gpu/drm/bridge/tc358775.c | 2 +-
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 +--
drivers/gpu/drm/dp/Makefile | 9 +
.../gpu/drm/{drm_dp_helper.c => dp/drm_dp.c} | 6 ++--
drivers/gpu/drm/{ => dp}/drm_dp_aux_bus.c | 4 +--
drivers/gpu/drm/{ => dp}/drm_dp_aux_dev.c | 6 ++--
drivers/gpu/drm/{ => dp}/drm_dp_cec.c | 2 +-
.../drm/{ => dp}/drm_dp_dual_mode_helper.c| 2 +-
drivers/gpu/drm/dp/drm_dp_helper_internal.h | 33 +++
drivers/gpu/drm/dp/drm_dp_helper_mod.c| 22 +
.../gpu/drm/{ => dp}/drm_dp_mst_topology.c| 6 ++--
.../{ => dp}/drm_dp_mst_topology_internal.h | 2 +-
drivers/gpu/drm/drm_crtc_helper_internal.h| 27 ---
drivers/gpu/drm/drm_dsc.c | 2 +-
drivers/gpu/drm/drm_kms_helper_common.c | 14
drivers/gpu/drm/gma500/cdv_intel_dp.c | 2 +-
drivers/gpu/drm/gma500/intel_bios.c | 2 +-
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_types.h| 4 +--
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 +--
.../drm/i915/display/intel_dp_link_training.h | 2 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/dp/dp_audio.c | 2 +-
drivers/gpu/drm/msm/dp/dp_aux.h | 2 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +-
drivers/gpu/drm/msm/edp/edp.h | 2 +-
drivers/gpu/drm/msm/edp/edp_ctrl.c| 2 +-
drivers/gpu/drm/nouveau/Kconfig | 1 +
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 4 +--
drivers/gpu/drm/panel/panel-edp.c | 4 +--
.../gpu/drm/panel/panel-samsung-atna33xc20.c | 4 +--
drivers/gpu/drm/radeon/atombios_dp.c | 2 +-
drivers/gpu/drm/radeon/radeon_connectors.c| 2 +-
drivers/gpu/drm/radeon/radeon_dp_mst.c| 2 +-
drivers/gpu/drm/radeon/radeon_mode.h | 4 +--
drivers/gpu/drm/rockchip/Kconfig | 1 +
.../gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c| 2 +-
drivers/gpu/drm/rockchip/cdn-dp-core.h| 2 +-
drivers/gpu/drm/rockchip/rockchip_lvds.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_rgb.c | 2 +-
.../drm/selftests/test-drm_dp_mst_helper.c| 2 +-
drivers/gpu/drm/tegra/Kconfig | 1 +
d
[Intel-gfx] [PATCH v2 4/5] drm/dp: Move public DisplayPort headers into dp/
Move all public DisplayPort headers into dp and update users. No
functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h| 4 ++--
drivers/gpu/drm/amd/amdgpu/atombios_dp.c| 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++--
drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c | 2 +-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +-
drivers/gpu/drm/amd/display/dc/os_types.h | 2 +-
drivers/gpu/drm/amd/display/include/dpcd_defs.h | 2 +-
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 +-
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 2 +-
drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 2 +-
drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c | 2 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
drivers/gpu/drm/bridge/analogix/anx7625.c | 2 +-
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 2 +-
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h | 2 +-
drivers/gpu/drm/bridge/parade-ps8640.c | 2 +-
drivers/gpu/drm/bridge/tc358767.c | 2 +-
drivers/gpu/drm/bridge/tc358775.c | 2 +-
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +-
drivers/gpu/drm/dp/drm_dp.c | 4 ++--
drivers/gpu/drm/dp/drm_dp_aux_dev.c | 4 ++--
drivers/gpu/drm/dp/drm_dp_cec.c | 2 +-
drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c| 2 +-
drivers/gpu/drm/dp/drm_dp_mst_topology.c| 2 +-
drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h | 2 +-
drivers/gpu/drm/drm_dp_aux_bus.c| 2 +-
drivers/gpu/drm/drm_dsc.c | 2 +-
drivers/gpu/drm/gma500/cdv_intel_dp.c | 2 +-
drivers/gpu/drm/gma500/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c| 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c| 4 ++--
drivers/gpu/drm/i915/display/intel_dp_link_training.h | 2 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +-
drivers/gpu/drm/msm/dp/dp_audio.c | 2 +-
drivers/gpu/drm/msm/dp/dp_aux.h | 2 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c| 2 +-
drivers/gpu/drm/msm/edp/edp.h | 2 +-
drivers/gpu/drm/msm/edp/edp_ctrl.c | 2 +-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_connector.h | 2 +-
drivers/gpu/drm/nouveau/nouveau_dp.c| 2 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 4 ++--
drivers/gpu/drm/panel/panel-edp.c | 2 +-
drivers/gpu/drm/panel/panel-samsung-atna33xc20.c| 2 +-
drivers/gpu/drm/radeon/atombios_dp.c| 2 +-
drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +-
drivers/gpu/drm/radeon/radeon_mode.h| 4 ++--
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_lvds.c| 2 +-
drivers/gpu/drm/rockchip/rockchip_rgb.c | 2 +-
drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 2 +-
drivers/gpu/drm/tegra/dp.c | 2 +-
drivers/gpu/drm/tegra/dpaux.c | 2 +-
drivers/gpu/drm/tegra/sor.c | 2 +-
drivers/gpu/drm/xlnx/zynqmp_dp.c| 2 +-
include/drm/{ => dp}/drm_dp_dual_mode_helper.h | 0
include/drm/{ => dp}/drm_dp_helper.h| 0
include/drm/{ => dp}/drm_dp_mst_helper.h| 2 +-
include/drm/drm_dsc.h | 2 +-
69 files changed, 75 insertions(+), 75 deletions(-)
rename include/drm/{ => dp}/drm_dp_dual_mode_helper.h (100%)
rename include/drm/{ => dp}/drm_dp_helper.h (100%)
renam
[Intel-gfx] [PATCH v2 3/5] drm/dp: Move DisplayPort helpers into separate helper module
Move DisplayPort functions into a separate module to reduce the size
of the KMS helpers. Select DRM_DP_HELPER for all users of the code. To
avoid naming conflicts, rename drm_dp_helper.c to drm_dp.c
This change can help to reduce the size of the kernel binary. Some
numbers from a x86-64 test build:
Before:
drm_kms_helper.ko: 447480 bytes
After:
drm_dp_helper.ko: 216632 bytes
drm_kms_helper.ko: 239424 bytes
For early-boot graphics, generic DRM drivers, such as simpledrm,
require DRM KMS helpers to be built into the kernel. Generic helper
functions for DisplayPort take up a significant portion of DRM KMS
helper library. These functions are not used by generic drivers and
can be loaded as a module.
v2:
* move DP helper code into dp/ (Jani)
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/Kconfig | 8 +++
drivers/gpu/drm/Makefile | 10 -
drivers/gpu/drm/bridge/Kconfig| 4
drivers/gpu/drm/bridge/analogix/Kconfig | 2 ++
drivers/gpu/drm/bridge/cadence/Kconfig| 1 +
drivers/gpu/drm/dp/Makefile | 7 ++
.../gpu/drm/{drm_dp_helper.c => dp/drm_dp.c} | 0
drivers/gpu/drm/{ => dp}/drm_dp_aux_dev.c | 0
drivers/gpu/drm/{ => dp}/drm_dp_cec.c | 0
.../drm/{ => dp}/drm_dp_dual_mode_helper.c| 0
.../gpu/drm/{ => dp}/drm_dp_helper_internal.h | 0
drivers/gpu/drm/dp/drm_dp_helper_mod.c| 22 +++
.../gpu/drm/{ => dp}/drm_dp_mst_topology.c| 0
.../{ => dp}/drm_dp_mst_topology_internal.h | 0
drivers/gpu/drm/drm_kms_helper_common.c | 15 -
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/nouveau/Kconfig | 1 +
drivers/gpu/drm/rockchip/Kconfig | 1 +
drivers/gpu/drm/tegra/Kconfig | 1 +
drivers/gpu/drm/xlnx/Kconfig | 1 +
21 files changed, 54 insertions(+), 21 deletions(-)
create mode 100644 drivers/gpu/drm/dp/Makefile
rename drivers/gpu/drm/{drm_dp_helper.c => dp/drm_dp.c} (100%)
rename drivers/gpu/drm/{ => dp}/drm_dp_aux_dev.c (100%)
rename drivers/gpu/drm/{ => dp}/drm_dp_cec.c (100%)
rename drivers/gpu/drm/{ => dp}/drm_dp_dual_mode_helper.c (100%)
rename drivers/gpu/drm/{ => dp}/drm_dp_helper_internal.h (100%)
create mode 100644 drivers/gpu/drm/dp/drm_dp_helper_mod.c
rename drivers/gpu/drm/{ => dp}/drm_dp_mst_topology.c (100%)
rename drivers/gpu/drm/{ => dp}/drm_dp_mst_topology_internal.h (100%)
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index b1f22e457fd0..91f54aeb0b7c 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -80,6 +80,12 @@ config DRM_DEBUG_SELFTEST
If in doubt, say "N".
+config DRM_DP_HELPER
+ tristate
+ depends on DRM
+ help
+ DRM helpers for DisplayPort.
+
config DRM_KMS_HELPER
tristate
depends on DRM
@@ -236,6 +242,7 @@ config DRM_RADEON
depends on DRM && PCI && MMU
depends on AGP || !AGP
select FW_LOADER
+ select DRM_DP_HELPER
select DRM_KMS_HELPER
select DRM_TTM
select DRM_TTM_HELPER
@@ -256,6 +263,7 @@ config DRM_AMDGPU
tristate "AMD GPU"
depends on DRM && PCI && MMU
select FW_LOADER
+ select DRM_DP_HELPER
select DRM_KMS_HELPER
select DRM_SCHED
select DRM_TTM
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 301a44dc18e3..69be80ef1d31 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -48,21 +48,18 @@ obj-$(CONFIG_DRM_VRAM_HELPER) += drm_vram_helper.o
drm_ttm_helper-y := drm_gem_ttm_helper.o
obj-$(CONFIG_DRM_TTM_HELPER) += drm_ttm_helper.o
-drm_kms_helper-y := drm_bridge_connector.o drm_crtc_helper.o drm_dp_helper.o \
+drm_kms_helper-y := drm_bridge_connector.o drm_crtc_helper.o \
drm_dsc.o drm_encoder_slave.o drm_flip_work.o drm_hdcp.o \
drm_probe_helper.o \
- drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
- drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
+ drm_plane_helper.o drm_atomic_helper.o \
+ drm_kms_helper_common.o \
drm_simple_kms_helper.o drm_modeset_helper.o \
drm_scdc_helper.o drm_gem_atomic_helper.o \
drm_gem_framebuffer_helper.o \
drm_atomic_state_helper.o drm_damage_helper.o \
drm_format_helper.o drm_self_refresh_helper.o drm_rect.o
-
drm_kms_helper-$(CONFIG_DRM_PANEL_BRIDGE) += bridge/panel.o
drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
-drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
-drm_kms_helper-$(CONFIG_DRM_DP_CEC) += drm_dp_cec.o
obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/
[Intel-gfx] [PATCH v2 2/5] drm/dp: Move DP declarations into separate header file
Split the DP declarations from other helpers before moving the
DP functions into a separate module.
v2:
* forward-declare struct drm_dp_aux (Jani)
* add include guards in drm_dp_helper_internal.h
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_crtc_helper_internal.h | 27 --
drivers/gpu/drm/drm_dp_aux_dev.c | 2 +-
drivers/gpu/drm/drm_dp_helper.c| 2 +-
drivers/gpu/drm/drm_dp_helper_internal.h | 33 ++
drivers/gpu/drm/drm_dp_mst_topology.c | 2 +-
drivers/gpu/drm/drm_kms_helper_common.c| 1 +
6 files changed, 37 insertions(+), 30 deletions(-)
create mode 100644 drivers/gpu/drm/drm_dp_helper_internal.h
diff --git a/drivers/gpu/drm/drm_crtc_helper_internal.h
b/drivers/gpu/drm/drm_crtc_helper_internal.h
index 61e09f8a8d0f..28e04e750130 100644
--- a/drivers/gpu/drm/drm_crtc_helper_internal.h
+++ b/drivers/gpu/drm/drm_crtc_helper_internal.h
@@ -28,36 +28,9 @@
#include
#include
-#include
#include
#include
-/* drm_dp_aux_dev.c */
-#ifdef CONFIG_DRM_DP_AUX_CHARDEV
-int drm_dp_aux_dev_init(void);
-void drm_dp_aux_dev_exit(void);
-int drm_dp_aux_register_devnode(struct drm_dp_aux *aux);
-void drm_dp_aux_unregister_devnode(struct drm_dp_aux *aux);
-#else
-static inline int drm_dp_aux_dev_init(void)
-{
- return 0;
-}
-
-static inline void drm_dp_aux_dev_exit(void)
-{
-}
-
-static inline int drm_dp_aux_register_devnode(struct drm_dp_aux *aux)
-{
- return 0;
-}
-
-static inline void drm_dp_aux_unregister_devnode(struct drm_dp_aux *aux)
-{
-}
-#endif
-
/* drm_probe_helper.c */
enum drm_mode_status drm_crtc_mode_valid(struct drm_crtc *crtc,
const struct drm_display_mode *mode);
diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 06b374cae956..0618dfe16660 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -40,7 +40,7 @@
#include
#include
-#include "drm_crtc_helper_internal.h"
+#include "drm_dp_helper_internal.h"
struct drm_dp_aux_dev {
unsigned index;
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 23f9073bc473..e995a0262ed7 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -35,7 +35,7 @@
#include
#include
-#include "drm_crtc_helper_internal.h"
+#include "drm_dp_helper_internal.h"
struct dp_aux_backlight {
struct backlight_device *base;
diff --git a/drivers/gpu/drm/drm_dp_helper_internal.h
b/drivers/gpu/drm/drm_dp_helper_internal.h
new file mode 100644
index ..8917fc3af9ec
--- /dev/null
+++ b/drivers/gpu/drm/drm_dp_helper_internal.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef DRM_DP_HELPER_INTERNAL_H
+#define DRM_DP_HELPER_INTERNAL_H
+
+struct drm_dp_aux;
+
+#ifdef CONFIG_DRM_DP_AUX_CHARDEV
+int drm_dp_aux_dev_init(void);
+void drm_dp_aux_dev_exit(void);
+int drm_dp_aux_register_devnode(struct drm_dp_aux *aux);
+void drm_dp_aux_unregister_devnode(struct drm_dp_aux *aux);
+#else
+static inline int drm_dp_aux_dev_init(void)
+{
+ return 0;
+}
+
+static inline void drm_dp_aux_dev_exit(void)
+{
+}
+
+static inline int drm_dp_aux_register_devnode(struct drm_dp_aux *aux)
+{
+ return 0;
+}
+
+static inline void drm_dp_aux_unregister_devnode(struct drm_dp_aux *aux)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7f0ff96261cf..9f7b0b606924 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -45,7 +45,7 @@
#include
#include
-#include "drm_crtc_helper_internal.h"
+#include "drm_dp_helper_internal.h"
#include "drm_dp_mst_topology_internal.h"
/**
diff --git a/drivers/gpu/drm/drm_kms_helper_common.c
b/drivers/gpu/drm/drm_kms_helper_common.c
index 47e92400548d..88260d26409c 100644
--- a/drivers/gpu/drm/drm_kms_helper_common.c
+++ b/drivers/gpu/drm/drm_kms_helper_common.c
@@ -29,6 +29,7 @@
#include
+#include "drm_dp_helper_internal.h"
#include "drm_crtc_helper_internal.h"
MODULE_AUTHOR("David Airlie, Jesse Barnes");
--
2.34.1
[Intel-gfx] [PATCH v2 1/5] drm/dp_mst: Remove trailing whitespace.
Fix coding style.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index f3d79eda94bb..7f0ff96261cf 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -4811,7 +4811,7 @@ static void drm_dp_mst_dump_mstb(struct seq_file *m,
seq_printf(m, "%smstb - [%p]: num_ports: %d\n", prefix, mstb,
mstb->num_ports);
list_for_each_entry(port, &mstb->ports, next) {
- seq_printf(m, "%sport %d - [%p] (%s - %s): ddps: %d, ldps: %d,
sdp: %d/%d, fec: %s, conn: %p\n",
+ seq_printf(m, "%sport %d - [%p] (%s - %s): ddps: %d, ldps: %d,
sdp: %d/%d, fec: %s, conn: %p\n",
prefix,
port->port_num,
port,
--
2.34.1
[Intel-gfx] [PATCH v2 5/5] drm/dp: Move DisplayPort AUX bus helpers into dp/
Move drm_dp_aux_bus.c and its header file into the DP subdirectory
and update all users. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/Makefile | 2 --
drivers/gpu/drm/bridge/parade-ps8640.c | 2 +-
drivers/gpu/drm/bridge/ti-sn65dsi86.c| 2 +-
drivers/gpu/drm/dp/Makefile | 2 ++
drivers/gpu/drm/{ => dp}/drm_dp_aux_bus.c| 2 +-
drivers/gpu/drm/panel/panel-edp.c| 2 +-
drivers/gpu/drm/panel/panel-samsung-atna33xc20.c | 2 +-
include/drm/{ => dp}/drm_dp_aux_bus.h| 0
8 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/gpu/drm/{ => dp}/drm_dp_aux_bus.c (99%)
rename include/drm/{ => dp}/drm_dp_aux_bus.h (100%)
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 69be80ef1d31..700abeb4945e 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,8 +31,6 @@ drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
drm-$(CONFIG_DRM_PRIVACY_SCREEN) += drm_privacy_screen.o
drm_privacy_screen_x86.o
-obj-$(CONFIG_DRM_DP_AUX_BUS) += drm_dp_aux_bus.o
-
obj-$(CONFIG_DRM_NOMODESET) += drm_nomodeset.o
drm_cma_helper-y := drm_gem_cma_helper.o
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c
b/drivers/gpu/drm/bridge/parade-ps8640.c
index d6a1adbe57d4..89ac4891459a 100644
--- a/drivers/gpu/drm/bridge/parade-ps8640.c
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c
@@ -14,7 +14,7 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 74fcaa0150fd..ceda36c69446 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -26,7 +26,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/gpu/drm/dp/Makefile b/drivers/gpu/drm/dp/Makefile
index 5b892aeff5ab..75faffc706b1 100644
--- a/drivers/gpu/drm/dp/Makefile
+++ b/drivers/gpu/drm/dp/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: MIT
+obj-$(CONFIG_DRM_DP_AUX_BUS) += drm_dp_aux_bus.o
+
drm_dp_helper-y := drm_dp.o drm_dp_dual_mode_helper.o drm_dp_helper_mod.o
drm_dp_mst_topology.o
drm_dp_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
drm_dp_helper-$(CONFIG_DRM_DP_CEC) += drm_dp_cec.o
diff --git a/drivers/gpu/drm/drm_dp_aux_bus.c
b/drivers/gpu/drm/dp/drm_dp_aux_bus.c
similarity index 99%
rename from drivers/gpu/drm/drm_dp_aux_bus.c
rename to drivers/gpu/drm/dp/drm_dp_aux_bus.c
index 565edf6b1732..415afce3cf96 100644
--- a/drivers/gpu/drm/drm_dp_aux_bus.c
+++ b/drivers/gpu/drm/dp/drm_dp_aux_bus.c
@@ -19,7 +19,7 @@
#include
#include
-#include
+#include
#include
/**
diff --git a/drivers/gpu/drm/panel/panel-edp.c
b/drivers/gpu/drm/panel/panel-edp.c
index 6a6ca891ee2e..99ca1bd0091c 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -36,7 +36,7 @@
#include
#include
-#include
+#include
#include
#include
diff --git a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c
b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c
index bffeadaaf9a2..20666b6217e7 100644
--- a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c
+++ b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c
@@ -14,7 +14,7 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/include/drm/drm_dp_aux_bus.h b/include/drm/dp/drm_dp_aux_bus.h
similarity index 100%
rename from include/drm/drm_dp_aux_bus.h
rename to include/drm/dp/drm_dp_aux_bus.h
--
2.34.1
Re: [Intel-gfx] [PATCH v2 3/5] drm/dp: Move DisplayPort helpers into separate helper module
On Wed, 15 Dec 2021, Thomas Zimmermann wrote: > * move DP helper code into dp/ (Jani) I suggested adding the subdirectory, but I'm going to bikeshed the name, which I didn't suggest. $ find drivers/gpu/drm -mindepth 1 -maxdepth 1 -type d | wc -l 68 Assuming we move more of the drm modules to subdirectories, how are they going to stand out from drivers? I suggested drm_dp, which I understand results in tautology, but hey, all the filenames under drm/ also have drm_*.[ch]. And I find that very useful for git greps and other code archeology. With just the dp name, you'd have to know and list all the drm subdirectories when looking up stuff that's part of drm but not drivers. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 1/2] drm/i915: remove writeback hook
Ditch the writeback hook and drop i915_gem_object_writeback(). We
already support the shrinker_release_pages hook which can just call
shmem_writeback directly.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 -
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 10 --
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 19 ++-
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 12
5 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 66f20b803b01..aaf9183e601b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -455,7 +455,6 @@ i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
int i915_gem_object_truncate(struct drm_i915_gem_object *obj);
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj);
/**
* i915_gem_object_pin_map - return a contiguous mapping of the entire object
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index f9f7e44099fe..00c844caeabd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,7 +57,6 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
- void (*writeback)(struct drm_i915_gem_object *obj);
int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
bool no_gpu_wait,
bool should_writeback);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 89b70f5cde7a..820eee5e954e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -168,16 +168,6 @@ int i915_gem_object_truncate(struct drm_i915_gem_object
*obj)
return 0;
}
-/* Try to discard unwanted pages */
-void i915_gem_object_writeback(struct drm_i915_gem_object *obj)
-{
- assert_object_held_shared(obj);
- GEM_BUG_ON(i915_gem_object_has_pages(obj));
-
- if (obj->ops->writeback)
- obj->ops->writeback(obj);
-}
-
static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
{
struct radix_tree_iter iter;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index cc9fe258fba7..7fdf4fa10b0e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,6 +331,23 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
}
+static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
+ bool no_gpu_wait,
+ bool writeback)
+{
+ switch (obj->mm.madv) {
+ case I915_MADV_DONTNEED:
+ return i915_gem_object_truncate(obj);
+ case __I915_MADV_PURGED:
+ return 0;
+ }
+
+ if (writeback)
+ shmem_writeback(obj);
+
+ return 0;
+}
+
void
__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -503,7 +520,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
- .writeback = shmem_writeback,
+ .shrinker_release_pages = shmem_shrinker_release_pages,
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index 157a9765f483..fd54e05521f6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -61,18 +61,6 @@ static int try_to_writeback(struct drm_i915_gem_object *obj,
unsigned int flags)
return obj->ops->shrinker_release_pages(obj,
!(flags &
I915_SHRINK_ACTIVE),
flags &
I915_SHRINK_WRITEBACK);
-
- switch (obj->mm.madv) {
- case I915_MADV_DONTNEED:
- i915_gem_object_truncate(obj);
- return 0;
- case __I915_MADV_PURGED:
- return 0;
- }
-
- if (flags & I915_SHRINK_WRITEBACK)
- i915_gem_object_writeback(obj);
-
return 0;
}
--
2.31.1
[Intel-gfx] [PATCH 2/2] drm/i915: clean up shrinker_release_pages
Add some proper flags for the different modes, and shorten the name to
something more snappy.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 23 ---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 8 +++
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 16 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 10
4 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 00c844caeabd..6f446cca4322 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,9 +57,26 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
- int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool should_writeback);
+ /**
+* shrink - Perform further backend specific actions to facilate
+* shrinking.
+* @obj: The gem object
+* @flags: Extra flags to control shrinking behaviour in the backend
+*
+* Possible values for @flags:
+*
+* I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of the
+* backing pages, if supported.
+*
+* I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
+* idle. Active objects can be considered later. The TTM backend for
+* example might have aync migrations going on, which don't use any
+* i915_vma to track the active GTT binding, and hence having an unbound
+* object might not be enough.
+*/
+#define I915_GEM_OBJECT_SHRINK_WRITEBACK BIT(0)
+#define I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT BIT(1)
+ int (*shrink)(struct drm_i915_gem_object *obj, unsigned int flags);
int (*pread)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *arg);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 7fdf4fa10b0e..6c57b0a79c8a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,9 +331,7 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
}
-static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool writeback)
+static int shmem_shrink(struct drm_i915_gem_object *obj, unsigned int flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
@@ -342,7 +340,7 @@ static int shmem_shrinker_release_pages(struct
drm_i915_gem_object *obj,
return 0;
}
- if (writeback)
+ if (flags & I915_GEM_OBJECT_SHRINK_WRITEBACK)
shmem_writeback(obj);
return 0;
@@ -520,7 +518,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
- .shrinker_release_pages = shmem_shrinker_release_pages,
+ .shrink = shmem_shrink,
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index fd54e05521f6..968ca0fdd57b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -57,10 +57,18 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object
*obj,
static int try_to_writeback(struct drm_i915_gem_object *obj, unsigned int
flags)
{
- if (obj->ops->shrinker_release_pages)
- return obj->ops->shrinker_release_pages(obj,
- !(flags &
I915_SHRINK_ACTIVE),
- flags &
I915_SHRINK_WRITEBACK);
+ if (obj->ops->shrink) {
+ unsigned int shrink_flags = 0;
+
+ if (!(flags & I915_SHRINK_ACTIVE))
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT;
+
+ if (flags & I915_SHRINK_WRITEBACK)
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_WRITEBACK;
+
+ return obj->ops->shrink(obj, shrink_flags);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 923cc7ad8d70..21277f3c64e7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -424,16 +424,14 @@ int i915_ttm_purge(struct drm_i915_gem_object *obj)
return 0;
}
Re: [Intel-gfx] [PATCH 2/7] drm/i915: Break out the i915_deps utility
On Wed, 15 Dec 2021, Thomas Hellström wrote:
> Since it's starting to be used outside the i915 TTM move code, move it
> to a separate set of files.
Sure, but why the top level instead of gem/?
BR,
Jani.
>
> Signed-off-by: Thomas Hellström
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 181 +-
> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h | 17 --
> drivers/gpu/drm/i915/i915_deps.c | 249 +++
> drivers/gpu/drm/i915/i915_deps.h | 46
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> 6 files changed, 298 insertions(+), 198 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/i915_deps.c
> create mode 100644 drivers/gpu/drm/i915/i915_deps.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 6ddd2d2bbaaf..1b62b9f65196 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -163,6 +163,7 @@ i915-y += \
> i915_active.o \
> i915_buddy.o \
> i915_cmd_parser.o \
> + i915_deps.o \
> i915_gem_evict.o \
> i915_gem_gtt.o \
> i915_gem_ww.o \
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> index 09463874ef24..4b6f3cda15b6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
> @@ -5,6 +5,7 @@
>
> #include
>
> +#include "i915_deps.h"
> #include "i915_drv.h"
> #include "intel_memory_region.h"
> #include "intel_region_ttm.h"
> @@ -41,186 +42,6 @@ void i915_ttm_migrate_set_failure_modes(bool
> gpu_migration,
> }
> #endif
>
> -/**
> - * DOC: Set of utilities to dynamically collect dependencies and
> - * eventually coalesce them into a single fence which is fed into
> - * the GT migration code, since it only accepts a single dependency
> - * fence.
> - * The single fence returned from these utilities, in the case of
> - * dependencies from multiple fence contexts, a struct dma_fence_array,
> - * since the i915 request code can break that up and await the individual
> - * fences.
> - *
> - * Once we can do async unbinding, this is also needed to coalesce
> - * the migration fence with the unbind fences.
> - *
> - * While collecting the individual dependencies, we store the refcounted
> - * struct dma_fence pointers in a realloc-managed pointer array, since
> - * that can be easily fed into a dma_fence_array. Other options are
> - * available, like for example an xarray for similarity with drm/sched.
> - * Can be changed easily if needed.
> - *
> - * A struct i915_deps need to be initialized using i915_deps_init().
> - * If i915_deps_add_dependency() or i915_deps_add_resv() return an
> - * error code they will internally call i915_deps_fini(), which frees
> - * all internal references and allocations.
> - *
> - * We might want to break this out into a separate file as a utility.
> - */
> -
> -#define I915_DEPS_MIN_ALLOC_CHUNK 8U
> -
> -static void i915_deps_reset_fences(struct i915_deps *deps)
> -{
> - if (deps->fences != &deps->single)
> - kfree(deps->fences);
> - deps->num_deps = 0;
> - deps->fences_size = 1;
> - deps->fences = &deps->single;
> -}
> -
> -static void i915_deps_init(struct i915_deps *deps, gfp_t gfp)
> -{
> - deps->fences = NULL;
> - deps->gfp = gfp;
> - i915_deps_reset_fences(deps);
> -}
> -
> -static void i915_deps_fini(struct i915_deps *deps)
> -{
> - unsigned int i;
> -
> - for (i = 0; i < deps->num_deps; ++i)
> - dma_fence_put(deps->fences[i]);
> -
> - if (deps->fences != &deps->single)
> - kfree(deps->fences);
> -}
> -
> -static int i915_deps_grow(struct i915_deps *deps, struct dma_fence *fence,
> - const struct ttm_operation_ctx *ctx)
> -{
> - int ret;
> -
> - if (deps->num_deps >= deps->fences_size) {
> - unsigned int new_size = 2 * deps->fences_size;
> - struct dma_fence **new_fences;
> -
> - new_size = max(new_size, I915_DEPS_MIN_ALLOC_CHUNK);
> - new_fences = kmalloc_array(new_size, sizeof(*new_fences),
> deps->gfp);
> - if (!new_fences)
> - goto sync;
> -
> - memcpy(new_fences, deps->fences,
> -deps->fences_size * sizeof(*new_fences));
> - swap(new_fences, deps->fences);
> - if (new_fences != &deps->single)
> - kfree(new_fences);
> - deps->fences_size = new_size;
> - }
> - deps->fences[deps->num_deps++] = dma_fence_get(fence);
> - return 0;
> -
> -sync:
> - if (ctx->no_wait_gpu && !dma_fence_is_signaled(fence)) {
> - ret = -EBUSY;
> - goto unref;
> - }
> -
> - ret = dma_fence_wait(fence, ctx->interruptible);
> - if (ret)
> - goto unref;
> -
> - ret = fence->error;
> -
Re: [Intel-gfx] [PATCH v2 3/5] drm/dp: Move DisplayPort helpers into separate helper module
Hi Am 15.12.21 um 12:04 schrieb Jani Nikula: On Wed, 15 Dec 2021, Thomas Zimmermann wrote: * move DP helper code into dp/ (Jani) I suggested adding the subdirectory, but I'm going to bikeshed the name, which I didn't suggest. $ find drivers/gpu/drm -mindepth 1 -maxdepth 1 -type d | wc -l 68 Assuming we move more of the drm modules to subdirectories, how are they going to stand out from drivers? I suggested drm_dp, which I understand results in tautology, but hey, all the filenames under drm/ also have drm_*.[ch]. And I find that very useful for git greps and other code archeology. With just the dp name, you'd have to know and list all the drm subdirectories when looking up stuff that's part of drm but not drivers. I think we have enough filename prefixes already. drm/drm_dp/drm_dp_ is just ridiculous. Best regards Thomas BR, Jani. -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Ivo Totev OpenPGP_signature Description: OpenPGP digital signature
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Asynchronous vma unbinding
== Series Details == Series: drm/i915: Asynchronous vma unbinding URL : https://patchwork.freedesktop.org/series/98055/ State : warning == Summary == $ dim checkpatch origin/drm-tip 40ccf1d6e849 drm/i915: Avoid using the i915_fence_array when collecting dependencies c45e38a63dd7 drm/i915: Break out the i915_deps utility -:254: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #254: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 532 lines checked 4ffb2d025bd5 drm/i915: Require the vm mutex for i915_vma_bind() aea239ccfd55 drm/i915: Initial introduction of vma resources -:245: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #245: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 626 lines checked af7795ce58dc drm/i915: Use the vma resource as argument for gtt binding / unbinding 7fa874798925 drm/i915: Use vma resources for async unbinding -:459: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_node' - possible side-effects? #459: FILE: drivers/gpu/drm/i915/i915_vma_resource.c:38: +#define VMA_RES_LAST(_node) ((_node)->start + (_node)->node_size - 1) total: 0 errors, 0 warnings, 1 checks, 763 lines checked 9c26545a94e5 drm/i915: Use struct vma_resource instead of struct vma_snapshot -:587: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #587: deleted file mode 100644 total: 0 errors, 1 warnings, 0 checks, 486 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Asynchronous vma unbinding
== Series Details == Series: drm/i915: Asynchronous vma unbinding URL : https://patchwork.freedesktop.org/series/98055/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Asynchronous vma unbinding
== Series Details ==
Series: drm/i915: Asynchronous vma unbinding
URL : https://patchwork.freedesktop.org/series/98055/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11004 -> Patchwork_21851
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/index.html
Participating hosts (41 -> 34)
--
Additional (1): fi-icl-u2
Missing(8): bat-dg1-6 bat-dg1-5 fi-skl-guc fi-bsw-cyan bat-adlp-6
fi-pnv-d510 fi-bdw-samus bat-jsl-1
Known issues
Here are the changes found in Patchwork_21851 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html
* igt@debugfs_test@read_all_entries:
- fi-apl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1610])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-apl-guc/igt@debugfs_test@read_all_entries.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-apl-guc/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][6] -> [INCOMPLETE][7] ([i915#146])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109278]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#4269])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#3301])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-icl-u2/igt@prime_v...@basic-userptr.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-dsi}: [DMESG-WARN][16] ([i915#1982] / [i915#2411]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][18] ([i915#2940]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][20] -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignore
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/dp: Move DisplayPort helpers into own module (rev2)
== Series Details == Series: drm/dp: Move DisplayPort helpers into own module (rev2) URL : https://patchwork.freedesktop.org/series/97961/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/selftests/test-drm_dp_mst_helper.o drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c:13:10: fatal error: ../drm_dp_mst_topology_internal.h: No such file or directory #include "../drm_dp_mst_topology_internal.h" ^~~ compilation terminated. scripts/Makefile.build:287: recipe for target 'drivers/gpu/drm/selftests/test-drm_dp_mst_helper.o' failed make[4]: *** [drivers/gpu/drm/selftests/test-drm_dp_mst_helper.o] Error 1 scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm/selftests' failed make[3]: *** [drivers/gpu/drm/selftests] Error 2 scripts/Makefile.build:549: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:549: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1846: recipe for target 'drivers' failed make: *** [drivers] Error 2
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915: remove writeback hook
== Series Details == Series: series starting with [1/2] drm/i915: remove writeback hook URL : https://patchwork.freedesktop.org/series/98061/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: remove writeback hook
== Series Details ==
Series: series starting with [1/2] drm/i915: remove writeback hook
URL : https://patchwork.freedesktop.org/series/98061/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11004 -> Patchwork_21853
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/index.html
Participating hosts (41 -> 33)
--
Missing(8): bat-dg1-6 bat-dg1-5 fi-skl-guc fi-bsw-cyan bat-adlp-6
fi-pnv-d510 fi-bdw-samus bat-jsl-1
Known issues
Here are the changes found in Patchwork_21853 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html
* igt@gem_exec_suspend@basic-s3:
- fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html
- fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] ([i915#4547])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#2722] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-dsi}: [DMESG-WARN][10] ([i915#1982] / [i915#2411]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
Build changes
-
* Linux: CI_DRM_11004 -> Patchwork_21853
CI-20190529: 20190529
CI_DRM_11004: 636384ba8470ed9d16693aaff3e6ad13f52226be @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6307: be84fe4f151bc092e068cab5cd0cd19c34948b40 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21853: 8ea115b08d86430bd237f3726763faf87cb1dce9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8ea115b08d86 drm/i915: clean up shrinker_release_pages
8ce0825fdd81 drm/i915: remove writeback hook
== Logs ==
For more details see:
https://intel-gfx-
Re: [Intel-gfx] [PATCH] drm/i915/dg1: Read OPROM via SPI controller
On Tue, 14 Dec 2021, Lucas De Marchi wrote:
> On Tue, Dec 14, 2021 at 11:42:41AM +0200, Jani Nikula wrote:
>>On Fri, 17 Sep 2021, Lucas De Marchi wrote:
>>> From: Clint Taylor
>>>
>>> Read OPROM SPI through MMIO and find VBT entry since we can't use
>>> OpRegion and PCI mapping may not work on some systems due to most BIOSes
>>> not leaving the Option ROM mapped.
>>
>>What happened here, still not merged? :o
>
> I don't understand neither. I got nacks, because of the other approach
> to get the VBT from opregion. In that case reading via spi
> controller directly would not be needed. However the other approach is
> still not applied and meanwhile DG1 and DG2 have to fallback to our fake
> vbt.
>
> So I actually think we should go ahead and just merge this.
Agreed.
This has been posted a few times with an accompanying "drm/i915/oprom:
Basic sanitization" patch [1]. I don't like the idea of posting a series
with one patch adding a function and the next one completely rewriting
the same function. However, cleanup of that combo has not happened, and
IIUC as a standalone patch this moves things forward and does no harm.
This seems to still apply fine. I've hit the retest button to get
current test results, and I suggest we merge this, and let's iterate
from there.
BR,
Jani.
[1] https://lore.kernel.org/all/20210412090526.30547-15-matthew.a...@intel.com/
>
> Lucas De Marchi
>
>>
>>BR,
>>Jani.
>>
>>
>>
>>>
>>> Cc: Ville Syrjälä
>>> Cc: Tomas Winkler
>>> Signed-off-by: Clint Taylor
>>> Signed-off-by: Lucas De Marchi
>>> Signed-off-by: Jani Nikula
>>> ---
>>> drivers/gpu/drm/i915/display/intel_bios.c | 80 +--
>>> drivers/gpu/drm/i915/i915_reg.h | 8 +++
>>> 2 files changed, 82 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
>>> b/drivers/gpu/drm/i915/display/intel_bios.c
>>> index 3c25926092de..7f179dbdec1b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>>> @@ -2280,6 +2280,66 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
>>> size)
>>> return vbt;
>>> }
>>>
>>> +static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
>>> +{
>>> + u32 count, data, found, store = 0;
>>> + u32 static_region, oprom_offset;
>>> + u32 oprom_size = 0x20;
>>> + u16 vbt_size;
>>> + u32 *vbt;
>>> +
>>> + static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
>>> + static_region &= OPTIONROM_SPI_REGIONID_MASK;
>>> + intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
>>> +
>>> + oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
>>> + oprom_offset &= OROM_OFFSET_MASK;
>>> +
>>> + for (count = 0; count < oprom_size; count += 4) {
>>> + intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS,
>>> oprom_offset + count);
>>> + data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
>>> +
>>> + if (data == *((const u32 *)"$VBT")) {
>>> + found = oprom_offset + count;
>>> + break;
>>> + }
>>> + }
>>> +
>>> + if (count >= oprom_size)
>>> + goto err_not_found;
>>> +
>>> + /* Get VBT size and allocate space for the VBT */
>>> + intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
>>> + offsetof(struct vbt_header, vbt_size));
>>> + vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
>>> + vbt_size &= 0x;
>>> +
>>> + vbt = kzalloc(vbt_size, GFP_KERNEL);
>>> + if (!vbt) {
>>> + drm_err(&i915->drm, "Unable to allocate %u bytes for VBT
>>> storage\n",
>>> + vbt_size);
>>> + goto err_not_found;
>>> + }
>>> +
>>> + for (count = 0; count < vbt_size; count += 4) {
>>> + intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
>>> count);
>>> + data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
>>> + *(vbt + store++) = data;
>>> + }
>>> +
>>> + if (!intel_bios_is_valid_vbt(vbt, vbt_size))
>>> + goto err_free_vbt;
>>> +
>>> + drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
>>> +
>>> + return (struct vbt_header *)vbt;
>>> +
>>> +err_free_vbt:
>>> + kfree(vbt);
>>> +err_not_found:
>>> + return NULL;
>>> +}
>>> +
>>> static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
>>> {
>>> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> @@ -2329,6 +2389,8 @@ static struct vbt_header *oprom_get_vbt(struct
>>> drm_i915_private *i915)
>>>
>>> pci_unmap_rom(pdev, oprom);
>>>
>>> + drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
>>> +
>>> return vbt;
>>>
>>> err_free_vbt:
>>> @@ -2363,17 +2425,23 @@ void intel_bios_init(struct drm_i915_private *i915)
>>>
>>> init_vbt_defaults(i915);
>>>
>>> - /* If the OpRegion does not have VBT, look in PCI ROM. */
>>> + /*
>>> +* If the OpRegion does not h
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg1: Read OPROM via SPI controller (rev2)
== Series Details ==
Series: drm/i915/dg1: Read OPROM via SPI controller (rev2)
URL : https://patchwork.freedesktop.org/series/94826/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0152dbed149b drm/i915/dg1: Read OPROM via SPI controller
-:63: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#63: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2374:
+ if (!vbt) {
+ drm_err(&i915->drm, "Unable to allocate %u bytes for VBT
storage\n",
total: 0 errors, 1 warnings, 0 checks, 117 lines checked
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg1: Read OPROM via SPI controller (rev2)
== Series Details == Series: drm/i915/dg1: Read OPROM via SPI controller (rev2) URL : https://patchwork.freedesktop.org/series/94826/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > From: Ville Syrjälä > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > On Mon, 13 Dec 2021, Ville Syrjala > > > > wrote: > > > > > > > > This one is only used in gvt, anyway. And that actually makes me wonder > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > gvt with register define changes but I've always caught it before > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > before I push" test config, so maybe that's where I caught most of them. > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > builds? > > > > Actually cc Tomi.. > > GVT-d is enabled and tested by fi-bdw-gvtdvm. We're talking about the other gvt (whatever it was called), ie. CONFIG_DRM_I915_GVT. -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Ville Syrjälä > On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > > From: Ville Syrjälä > > > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > > On Mon, 13 Dec 2021, Ville Syrjala > wrote: > > > > > > > > > > This one is only used in gvt, anyway. And that actually makes me > wonder > > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > > gvt with register define changes but I've always caught it before > > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > > before I push" test config, so maybe that's where I caught most of > them. > > > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > > builds? > > > > > > Actually cc Tomi.. > > > > GVT-d is enabled and tested by fi-bdw-gvtdvm. > > We're talking about the other gvt (whatever it was called), ie. > CONFIG_DRM_I915_GVT. This kconfig entry doesn't exist in default CI kconfig, even as 'is not set' placeholder: https://gitlab.freedesktop.org/gfx-ci/i915-infra/-/blob/master/kconfig/debug If the config entry is exact, I'll probably need to upgrade the default config from 5.13 and add it with requirements. Not today, but maybe soon. Tomi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: Read OPROM via SPI controller (rev2)
== Series Details ==
Series: drm/i915/dg1: Read OPROM via SPI controller (rev2)
URL : https://patchwork.freedesktop.org/series/94826/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11004 -> Patchwork_21854
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/index.html
Participating hosts (41 -> 33)
--
Missing(8): bat-dg1-6 bat-dg1-5 fi-skl-guc fi-bsw-cyan bat-adlp-6
fi-pnv-d510 fi-bdw-samus bat-jsl-1
Known issues
Here are the changes found in Patchwork_21854 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17
similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html
* igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#1888])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] ([i915#4547])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#4269])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-dsi}: [DMESG-WARN][10] ([i915#1982] / [i915#2411]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][14] ([i915#4785]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
Build changes
-
* Linux: CI_DRM_11004 -> Patchwork_21854
CI-20190529: 20190529
CI_DRM_11004: 636384ba8470ed9d16693aaff3e6ad13f52226be @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6307: be84fe4f151bc092e068cab5cd0cd19c34948b40 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21854: 0152dbed149b311684ce3e1893e48ead2bc622bb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0152dbed149b drm/i915/dg1: Read OPROM via SPI controller
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/index.html
[Intel-gfx] [PATCH 0/5] Add driver for GSC controller
GSC is a graphics system controller, based on CSE, it provides a chassis controller for graphics discrete cards, as well as it supports media protection (HDCP 2.2) on selected devices. There are two MEI interfaces in GSC: HECI1, the one that provides media protection and HECI2 the one that provides firmware interface. This series includes instantiation of the platform devices for HECIs and mei-gsc platform device driver that binds to the platform device. Greg KH, please review and ACK the MEI patches. We are pushing all through gfx tree as the platform device belongs there. Alexander Usyskin (2): mei: gsc: setup char driver alive in spite of firmware handshake failure mei: gsc: retrieve the firmware version Tomas Winkler (3): drm/i915/gsc: add gsc as a mei platform device mei: add gsc driver mei: gsc: add runtime pm handlers drivers/gpu/drm/i915/Kconfig | 1 + drivers/gpu/drm/i915/Makefile| 3 + drivers/gpu/drm/i915/gt/intel_gsc.c | 156 drivers/gpu/drm/i915/gt/intel_gsc.h | 35 +++ drivers/gpu/drm/i915/gt/intel_gt.c | 3 + drivers/gpu/drm/i915/gt/intel_gt.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 + drivers/gpu/drm/i915/i915_driver.c | 10 + drivers/gpu/drm/i915/i915_drv.h | 8 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 3 + drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/misc/mei/Kconfig | 12 + drivers/misc/mei/Makefile| 3 + drivers/misc/mei/bus-fixup.c | 25 ++ drivers/misc/mei/gsc-me.c| 293 +++ drivers/misc/mei/hw-me.c | 29 ++- drivers/misc/mei/hw-me.h | 2 + 19 files changed, 606 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h create mode 100644 drivers/misc/mei/gsc-me.c -- 2.32.0
[Intel-gfx] [PATCH 1/5] drm/i915/gsc: add gsc as a mei platform device
From: Tomas Winkler
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection (HDCP 2.2) on selected devices.
There are two MEI interfaces in GSC HECI1, the one that provides media
protection and HECI2 the one that provides firmware interface.
Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000.
GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled
via bit 15 and HECI2 via bit 14 in the interrupt register.
This patch exports GSC as platform device for mei driver to bind to.
CC: Rodrigo Vivi
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Alexander Usyskin
---
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile| 3 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 156 +++
drivers/gpu/drm/i915/gt/intel_gsc.h | 35 +
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 14 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_driver.c | 10 ++
drivers/gpu/drm/i915/i915_drv.h | 8 ++
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
13 files changed, 244 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index a4c94dc2e216..168e1c015eb6 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -27,6 +27,7 @@ config DRM_I915
select CEC_CORE if CEC_NOTIFIER
select VMAP_PFN
select DRM_TTM
+ select MFD_CORE
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 213c5f9fae32..7f87f6f5fd60 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -193,6 +193,9 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_huc_debugfs.o \
gt/uc/intel_huc_fw.o
+# graphics security controller (GSC) support
+i915-y += gt/intel_gsc.o
+
# modesetting core code
i915-y += \
display/intel_atomic.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c
b/drivers/gpu/drm/i915/gt/intel_gsc.c
new file mode 100644
index ..670b199ef99d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2020, Intel Corporation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include "i915_reg.h"
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "intel_gsc.h"
+
+#define GSC_BAR_LENGTH 0x0FFC
+
+static void gsc_irq_mask(struct irq_data *d)
+{
+ /* generic irq handling */
+}
+
+static void gsc_irq_unmask(struct irq_data *d)
+{
+ /* generic irq handling */
+}
+
+static struct irq_chip gsc_irq_chip = {
+ .name = "gsc_irq_chip",
+ .irq_mask = gsc_irq_mask,
+ .irq_unmask = gsc_irq_unmask,
+};
+
+static int gsc_irq_init(struct drm_i915_private *dev_priv, int irq)
+{
+ irq_set_chip_and_handler_name(irq, &gsc_irq_chip,
+ handle_simple_irq, "gsc_irq_handler");
+
+ return irq_set_chip_data(irq, dev_priv);
+}
+
+/* gscfi (graphics system controller firmware interface) resources */
+static const struct resource gscfi_dg1_resources[] = {
+ DEFINE_RES_IRQ_NAMED(0, "gscfi-irq"),
+ DEFINE_RES_MEM_NAMED(GSC_DG1_HECI2_BASE,
+GSC_BAR_LENGTH,
+"gscfi-mmio"),
+};
+
+static const struct mfd_cell intel_gsc_dg1_cell[] = {
+ {
+ .id = 0,
+ },
+ {
+ .id = 1,
+ .name = "mei-gscfi",
+ .num_resources = ARRAY_SIZE(gscfi_dg1_resources),
+ .resources = gscfi_dg1_resources,
+ }
+};
+
+static void intel_gsc_destroy_one(struct intel_gsc_intf *intf)
+{
+ if (intf->irq >= 0)
+ irq_free_desc(intf->irq);
+ intf->irq = -1;
+}
+
+static void intel_gsc_init_one(struct drm_i915_private *dev_priv,
+ struct intel_gsc_intf *intf,
+ unsigned int intf_id)
+{
+ struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+ int ret;
+
+ intf->irq = -1;
+ intf->id = intf_id;
+
+ if (intf_id == 0 && !HAS_HECI_PXP(dev_priv))
+ return;
+
+ dev_dbg(&pdev->dev, "init gsc one with id %d\n", intf_id);
+ intf->irq = irq_alloc_desc(0);
+ if (intf->irq < 0) {
+ dev_err(&pdev->dev, "gsc irq error %d\n", intf->irq);
+
[Intel-gfx] [PATCH 2/5] mei: add gsc driver
From: Tomas Winkler
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection (HDCP 2.2) on selected devices.
mei_gsc binds to a platform devices exposed by Intel discrete
driver i915 via MFD framework.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 12 +++
drivers/misc/mei/Makefile | 3 +
drivers/misc/mei/gsc-me.c | 214 ++
drivers/misc/mei/hw-me.c | 27 -
drivers/misc/mei/hw-me.h | 2 +
5 files changed, 256 insertions(+), 2 deletions(-)
create mode 100644 drivers/misc/mei/gsc-me.c
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index 0e0bcd0da852..712d72e25138 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -49,3 +49,15 @@ config INTEL_MEI_TXE
source "drivers/misc/mei/hdcp/Kconfig"
source "drivers/misc/mei/pxp/Kconfig"
+config INTEL_MEI_GSC
+ tristate "Intel MEI GSC embedded device"
+ select INTEL_MEI
+ select INTEL_MEI_ME
+ depends on X86 && PCI
+ depends on DRM_I915
+ help
+ Intel platform driver for MEI devices embedded in a graphics device.
+
+ MEI device can be embedded in a standalone Intel graphics devices,
+ to support range of security tasks.
+ Currently supported device is DG1.
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index d8e5165917f2..fb740d754900 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) += mei-me.o
mei-me-objs := pci-me.o
mei-me-objs += hw-me.o
+obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o
+mei-gsc-objs := gsc-me.o
+
obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o
mei-txe-objs := pci-txe.o
mei-txe-objs += hw-txe.o
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
new file mode 100644
index ..901d6e0ce6cd
--- /dev/null
+++ b/drivers/misc/mei/gsc-me.c
@@ -0,0 +1,214 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2020, Intel Corporation. All rights reserved.
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mei_dev.h"
+#include "hw-me.h"
+#include "hw-me-regs.h"
+
+#include "mei-trace.h"
+
+#define MEI_GSC_RPM_TIMEOUT 500
+
+static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+
+ *val = ioread32(hw->mem_addr + where + 0xC00);
+
+ return 0;
+}
+
+static int mei_gsc_probe(struct platform_device *platdev)
+{
+ struct mei_device *dev;
+ struct mei_me_hw *hw;
+ struct resource *bar;
+ struct device *device;
+ const struct platform_device_id *ent;
+ const struct mei_cfg *cfg;
+ int ret;
+
+ ent = platform_get_device_id(platdev);
+ cfg = mei_me_get_cfg(ent->driver_data);
+ if (!cfg)
+ return -ENODEV;
+
+ device = &platdev->dev;
+
+ dev = mei_me_dev_init(device, cfg);
+ if (IS_ERR(dev)) {
+ ret = PTR_ERR(dev);
+ goto err;
+ }
+
+ bar = platform_get_resource(platdev, IORESOURCE_MEM, 0);
+
+ hw = to_me_hw(dev);
+ hw->mem_addr = devm_ioremap_resource(device, bar);
+ if (IS_ERR(hw->mem_addr)) {
+ dev_err(device, "mmio not mapped\n");
+ ret = PTR_ERR(hw->mem_addr);
+ goto err;
+ }
+
+ hw->irq = platform_get_irq(platdev, 0);
+ if (hw->irq < 0) {
+ ret = hw->irq;
+ goto err;
+ }
+ hw->read_fws = mei_gsc_read_hfs;
+
+ platform_set_drvdata(platdev, dev);
+
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
+
+ pm_runtime_get_noresume(device);
+ pm_runtime_set_active(device);
+ pm_runtime_enable(device);
+
+ if (mei_start(dev)) {
+ dev_err(device, "init hw failure.\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
+ pm_runtime_use_autosuspend(device);
+
+ ret = mei_register(dev, device);
+ if (ret)
+ goto register_err;
+
+ pm_runtime_put_noidle(device);
+ return 0;
+
+register_err:
+ mei_stop(dev);
+
+err:
+ dev_err(device, "probe failed: %d\n", ret);
+ platform_set_drvdata(platdev, NULL);
+ return ret;
+}
+
+static int mei_gsc_remove(struct platform_device *platdev)
+{
+
[Intel-gfx] [PATCH 3/5] mei: gsc: setup char driver alive in spite of firmware handshake failure
Continue to char device setup in spite of firmware handshake failure.
In order to provide access to the firmware status registers and other
information are valuable for debug and manufacturing.
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/gsc-me.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 901d6e0ce6cd..c6bf869d910b 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -86,11 +86,12 @@ static int mei_gsc_probe(struct platform_device *platdev)
pm_runtime_set_active(device);
pm_runtime_enable(device);
- if (mei_start(dev)) {
- dev_err(device, "init hw failure.\n");
- ret = -ENODEV;
- goto err;
- }
+ /* Continue to char device setup in spite of firmware handshake failure.
+* In order to provide access to the firmware status registers to the
user
+* space via sysfs.
+*/
+ if (mei_start(dev))
+ dev_warn(device, "init hw failure.\n");
pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
pm_runtime_use_autosuspend(device);
--
2.32.0
[Intel-gfx] [PATCH 5/5] mei: gsc: retrieve the firmware version
GSC has a different MKHI client GUID with same message structure
as MEI to retrieve the firmware version.
Add a bus-fixup to retrieve the firmware version of the
GSC devices.
CC: Ashutosh Dixit
Signed-off-by: Alexander Usyskin
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/bus-fixup.c | 25 +
drivers/misc/mei/hw-me.c | 2 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 67844089db21..59506ba6fc48 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -30,6 +30,12 @@ static const uuid_le mei_nfc_info_guid = MEI_UUID_NFC_INFO;
#define MEI_UUID_MKHIF_FIX UUID_LE(0x55213584, 0x9a29, 0x4916, \
0xba, 0xdf, 0xf, 0xb7, 0xed, 0x68, 0x2a, 0xeb)
+#define MEI_UUID_IGSC_MKHI UUID_LE(0xE2C2AFA2, 0x3817, 0x4D19, \
+ 0x9D, 0x95, 0x06, 0xB1, 0x6B, 0x58, 0x8A, 0x5D)
+
+#define MEI_UUID_IGSC_MKHI_FIX UUID_LE(0x46E0C1FB, 0xA546, 0x414F, \
+ 0x91, 0x70, 0xB7, 0xF4, 0x6D, 0x57, 0xB4, 0xAD)
+
#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, \
0xA5, 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04)
@@ -241,6 +247,23 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev)
mei_cldev_disable(cldev);
}
+static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
+{
+ int ret;
+
+ /* No need to enable the client if nothing is needed from it */
+ if (!cldev->bus->fw_f_fw_ver_supported)
+ return;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret)
+ return;
+
+ ret = mei_fwver(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "FW version command failed %d\n", ret);
+ mei_cldev_disable(cldev);
+}
/**
* mei_wd - wd client on the bus, change protocol version
* as the API has changed.
@@ -492,6 +515,8 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc),
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
MEI_FIXUP(MEI_UUID_PAVP, whitelist),
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 9748d14849a1..7e77328142ff 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1577,12 +1577,14 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = {
static const struct mei_cfg mei_me_gsc_cfg = {
MEI_CFG_TYPE_GSC,
MEI_CFG_PCH8_HFS,
+ MEI_CFG_FW_VER_SUPP,
};
/* Graphics System Controller Firmware Interface */
static const struct mei_cfg mei_me_gscfi_cfg = {
MEI_CFG_TYPE_GSCFI,
MEI_CFG_PCH8_HFS,
+ MEI_CFG_FW_VER_SUPP,
};
/*
--
2.32.0
[Intel-gfx] [PATCH 4/5] mei: gsc: add runtime pm handlers
From: Tomas Winkler
Implement runtime handlers for mei-gsc, to track
idle state of the device properly.
CC: Rodrigo Vivi
Signed-off-by: Tomas Winkler
Signed-off-by: Alexander Usyskin
---
drivers/misc/mei/gsc-me.c | 80 ++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c6bf869d910b..51b00e5ea122 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -167,7 +167,85 @@ static int __maybe_unused mei_gsc_pm_resume(struct device
*device)
return 0;
}
-static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend,
mei_gsc_pm_resume);
+static int __maybe_unused mei_gsc_pm_runtime_idle(struct device *device)
+{
+ struct mei_device *dev;
+
+ dev_dbg(device, "rpm: me: runtime_idle\n");
+
+ dev = dev_get_drvdata(device);
+ if (!dev)
+ return -ENODEV;
+ if (mei_write_is_idle(dev))
+ pm_runtime_autosuspend(device);
+
+ return -EBUSY;
+}
+
+static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
+{
+ struct mei_device *dev;
+ struct mei_me_hw *hw;
+ int ret;
+
+ dev_dbg(device, "rpm: me: runtime suspend\n");
+
+ dev = dev_get_drvdata(device);
+ if (!dev)
+ return -ENODEV;
+
+ mutex_lock(&dev->device_lock);
+
+ if (mei_write_is_idle(dev)) {
+ hw = to_me_hw(dev);
+ hw->pg_state = MEI_PG_ON;
+ ret = 0;
+ } else {
+ ret = -EAGAIN;
+ }
+
+ mutex_unlock(&dev->device_lock);
+
+ dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
+
+ return ret;
+}
+
+static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
+{
+ struct mei_device *dev;
+ struct mei_me_hw *hw;
+ irqreturn_t irq_ret;
+
+ dev_dbg(device, "rpm: me: runtime resume\n");
+
+ dev = dev_get_drvdata(device);
+ if (!dev)
+ return -ENODEV;
+
+ mutex_lock(&dev->device_lock);
+
+ hw = to_me_hw(dev);
+ hw->pg_state = MEI_PG_OFF;
+
+ mutex_unlock(&dev->device_lock);
+
+ irq_ret = mei_me_irq_thread_handler(1, dev);
+ if (irq_ret != IRQ_HANDLED)
+ dev_err(dev->dev, "thread handler fail %d\n", irq_ret);
+
+ dev_dbg(device, "rpm: me: runtime resume ret = 0\n");
+
+ return 0;
+}
+
+static const struct dev_pm_ops mei_gsc_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mei_gsc_pm_suspend,
+ mei_gsc_pm_resume)
+ SET_RUNTIME_PM_OPS(mei_gsc_pm_runtime_suspend,
+ mei_gsc_pm_runtime_resume,
+ mei_gsc_pm_runtime_idle)
+};
static const struct platform_device_id gsc_devtypes[] = {
{
--
2.32.0
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller
== Series Details == Series: Add driver for GSC controller URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim checkpatch origin/drm-tip 06f5f59f4a16 drm/i915/gsc: add gsc as a mei platform device -:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #51: new file mode 100644 -:426: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #426: FILE: drivers/gpu/drm/i915/i915_drv.h:1514: +#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv)) total: 0 errors, 1 warnings, 1 checks, 377 lines checked 9dfea09ecd68 mei: add gsc driver -:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #51: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 312 lines checked 7f7bb1a175b6 mei: gsc: setup char driver alive in spite of firmware handshake failure fc8d249d1524 mei: gsc: add runtime pm handlers 1ec071a0e301 mei: gsc: retrieve the firmware version
Re: [Intel-gfx] [PATCH 1/5] drm/i915/gsc: add gsc as a mei platform device
On Wed, Dec 15, 2021 at 03:56:18PM +0200, Alexander Usyskin wrote: > From: Tomas Winkler > > GSC is a graphics system controller, based on CSE, it provides > a chassis controller for graphics discrete cards, as well as it > supports media protection (HDCP 2.2) on selected devices. > > There are two MEI interfaces in GSC HECI1, the one that provides media > protection and HECI2 the one that provides firmware interface. > > Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. > GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled > via bit 15 and HECI2 via bit 14 in the interrupt register. > > This patch exports GSC as platform device for mei driver to bind to. This is NOT a platform device. It is part of a PCI device, which is NOT a platform device. I keep having to say this. Please use the auxbus interface instead if you want to split a PCI device up into sub-child-devices and bind drivers to them. That is what it was created for, and this SHOULD have been caught by the other Intel reviewers who signed-off on this patch. so no, I will not ack this, it is not ok at all, sorry. greg k-h
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller
== Series Details == Series: Add driver for GSC controller URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/fbc: Parametrize FBC register offsets
> From: Sarvela, Tomi P > > From: Ville Syrjälä > > On Wed, Dec 15, 2021 at 09:05:03AM +, Sarvela, Tomi P wrote: > > > > From: Ville Syrjälä > > > > > > > > On Tue, Dec 14, 2021 at 06:25:43PM +0200, Ville Syrjälä wrote: > > > > > On Mon, Dec 13, 2021 at 09:54:04PM +0200, Jani Nikula wrote: > > > > > > On Mon, 13 Dec 2021, Ville Syrjala > > wrote: > > > > > > > > > > > > This one is only used in gvt, anyway. And that actually makes me > > wonder > > > > > > if this should be breaking the build. Does CI not have gvt enabled? > > > > > > > > > > Hmm. I thought it was enabled in CI, but maybe not. I've often broken > > > > > gvt with register define changes but I've always caught it before > > > > > pushing. I think I have gvt enabled in my "make sure all commits build > > > > > before I push" test config, so maybe that's where I caught most of > > them. > > > > > > > > > > Tomi, can we enable gvt in ci builds to make sure it at least still > > > > > builds? > > > > > > > > Actually cc Tomi.. > > > > > > GVT-d is enabled and tested by fi-bdw-gvtdvm. > > > > We're talking about the other gvt (whatever it was called), ie. > > CONFIG_DRM_I915_GVT. > > This kconfig entry doesn't exist in default CI kconfig, even as 'is not set' > placeholder: > https://gitlab.freedesktop.org/gfx-ci/i915-infra/- > /blob/master/kconfig/debug > > If the config entry is exact, I'll probably need to upgrade the default config > from 5.13 and add it with requirements. Not today, but maybe soon. kconfigs debug, debug-kasan and debug-gcov have been updated to v5.15 with 'make olddefconfig', and CONFIG_DRM_I915_GVT=y has been set. First CI_DRM to use this kconfig will be CI_DRM_11005. Tomi
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Asynchronous vma unbinding
== Series Details == Series: drm/i915: Asynchronous vma unbinding URL : https://patchwork.freedesktop.org/series/98055/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11004_full -> Patchwork_21851_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21851_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21851_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21851_full: ### IGT changes ### Possible regressions * igt@gem_softpin@allocator-evict-all-engines: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-iclb3/igt@gem_soft...@allocator-evict-all-engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-iclb7/igt@gem_soft...@allocator-evict-all-engines.html * igt@gem_softpin@noreloc-s3: - shard-skl: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-skl8/igt@gem_soft...@noreloc-s3.html - shard-snb: [PASS][4] -> [DMESG-WARN][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-snb2/igt@gem_soft...@noreloc-s3.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-snb4/igt@gem_soft...@noreloc-s3.html Known issues Here are the changes found in Patchwork_21851_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#3002]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-skl6/igt@gem_cre...@create-massive.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-iclb5/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-kbl2/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_whisper@basic-queues-priority-all: - shard-glk: [PASS][12] -> [DMESG-WARN][13] ([i915#118]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-glk4/igt@gem_exec_whis...@basic-queues-priority-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-glk8/igt@gem_exec_whis...@basic-queues-priority-all.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-skl4/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-skl10/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-tglb1/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-apl7/igt@gem_lmem_swapp...@random.html - shard-iclb: NOTRUN -> [SKIP][18] ([i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-iclb5/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@smem-oom: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-kbl1/igt@gem_lmem_swapp...@smem-oom.html * igt@gem_pwrite@basic-exhaustion: - shard-iclb: NOTRUN -> [WARN][20] ([i915#2658]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21851/shard-iclb5/igt@gem_pwr...@b
[Intel-gfx] ✓ Fi.CI.BAT: success for Add driver for GSC controller
== Series Details ==
Series: Add driver for GSC controller
URL : https://patchwork.freedesktop.org/series/98066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11004 -> Patchwork_21855
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_21855 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21855, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/index.html
Participating hosts (41 -> 34)
--
Additional (1): fi-icl-u2
Missing(8): bat-dg1-6 bat-dg1-5 fi-skl-guc fi-bsw-cyan bat-adlp-6
fi-pnv-d510 fi-bdw-samus bat-jsl-1
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21855:
### IGT changes ###
Warnings
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][1] ([i915#4785]) -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_21855 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [PASS][6] -> [FAIL][7] ([i915#1888])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][8] -> [FAIL][9] ([i915#4547])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#2190])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4613]) +3 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109278]) +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#3301])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-icl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][16] ([i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_pm_rpm@basic-rte:
- {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982] / [i915#2411]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/fi-tgl-dsi/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][19] ([i915#2940]) -> [
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: remove writeback hook
== Series Details == Series: series starting with [1/2] drm/i915: remove writeback hook URL : https://patchwork.freedesktop.org/series/98061/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11004_full -> Patchwork_21853_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21853_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21853_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21853_full: ### IGT changes ### Possible regressions * igt@kms_psr@suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-skl9/igt@kms_...@suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-skl7/igt@kms_...@suspend.html Known issues Here are the changes found in Patchwork_21853_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063] / [i915#3648]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb8/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-tglb5/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-iclb7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-skl10/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-skl4/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-tglb8/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@random: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21853/shard-iclb7/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@smem-oom: - shard-apl: NOTRUN ->
Re: [Intel-gfx] [PATCH 2/2] drm/i915: clean up shrinker_release_pages
On 15/12/2021 11:07, Matthew Auld wrote:
Add some proper flags for the different modes, and shorten the name to
something more snappy.
Looks good to me - but since it touches TTM I leave for Thomas to approve.
Regards,
Tvrtko
P.S. I hope writing the patch means you thought it is an improvement as
well, rather than feeling I was asking for it to be done.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 23 ---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 8 +++
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 16 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 10
4 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 00c844caeabd..6f446cca4322 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,9 +57,26 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
- int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool should_writeback);
+ /**
+* shrink - Perform further backend specific actions to facilate
+* shrinking.
+* @obj: The gem object
+* @flags: Extra flags to control shrinking behaviour in the backend
+*
+* Possible values for @flags:
+*
+* I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of the
+* backing pages, if supported.
+*
+* I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
+* idle. Active objects can be considered later. The TTM backend for
+* example might have aync migrations going on, which don't use any
+* i915_vma to track the active GTT binding, and hence having an unbound
+* object might not be enough.
+*/
+#define I915_GEM_OBJECT_SHRINK_WRITEBACK BIT(0)
+#define I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT BIT(1)
+ int (*shrink)(struct drm_i915_gem_object *obj, unsigned int flags);
int (*pread)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *arg);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 7fdf4fa10b0e..6c57b0a79c8a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,9 +331,7 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
}
-static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool writeback)
+static int shmem_shrink(struct drm_i915_gem_object *obj, unsigned int flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
@@ -342,7 +340,7 @@ static int shmem_shrinker_release_pages(struct
drm_i915_gem_object *obj,
return 0;
}
- if (writeback)
+ if (flags & I915_GEM_OBJECT_SHRINK_WRITEBACK)
shmem_writeback(obj);
return 0;
@@ -520,7 +518,7 @@ const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
- .shrinker_release_pages = shmem_shrinker_release_pages,
+ .shrink = shmem_shrink,
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index fd54e05521f6..968ca0fdd57b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -57,10 +57,18 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object
*obj,
static int try_to_writeback(struct drm_i915_gem_object *obj, unsigned int flags)
{
- if (obj->ops->shrinker_release_pages)
- return obj->ops->shrinker_release_pages(obj,
- !(flags &
I915_SHRINK_ACTIVE),
- flags &
I915_SHRINK_WRITEBACK);
+ if (obj->ops->shrink) {
+ unsigned int shrink_flags = 0;
+
+ if (!(flags & I915_SHRINK_ACTIVE))
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT;
+
+ if (flags & I915_SHRINK_WRITEBACK)
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_WRITEBACK;
+
+ return obj->ops->shrink(obj, shrink_flags);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tt
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Use struct vma_resource instead of struct vma_snapshot
Hi "Thomas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20211214]
[cannot apply to drm-exynos/exynos-drm-next drm/drm-next
drm-intel/for-linux-next tegra-drm/drm/tegra/for-next airlied/drm-next
v5.16-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-r002-20211214
(https://download.01.org/0day-ci/archive/20211215/202112152305.rfwvqjls-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/ede025870be746e37b5bcde123cdf741aa685fab
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
git checkout ede025870be746e37b5bcde123cdf741aa685fab
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/i915_request.h:43,
from drivers/gpu/drm/i915/i915_active.h:13,
from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:16,
from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30,
from drivers/gpu/drm/i915/i915_vma.c:28:
drivers/gpu/drm/i915/i915_vma_resource.h:176:15: error: 'struct
intel_memory_region' declared inside parameter list will not be visible outside
of this definition or declaration [-Werror]
176 |struct intel_memory_region *mr,
| ^~~
drivers/gpu/drm/i915/i915_vma.c: In function
'i915_vma_resource_init_from_vma':
>> drivers/gpu/drm/i915/i915_vma.c:394:48: error: passing argument 8 of
>> 'i915_vma_resource_init' from incompatible pointer type
>> [-Werror=incompatible-pointer-types]
394 | i915_gem_object_is_lmem(obj), obj->mm.region,
| ~~~^~~
||
|struct
intel_memory_region *
In file included from drivers/gpu/drm/i915/i915_request.h:43,
from drivers/gpu/drm/i915/i915_active.h:13,
from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:16,
from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30,
from drivers/gpu/drm/i915/i915_vma.c:28:
drivers/gpu/drm/i915/i915_vma_resource.h:176:36: note: expected 'struct
intel_memory_region *' but argument is of type 'struct intel_memory_region *'
176 |struct intel_memory_region *mr,
|^~
cc1: all warnings being treated as errors
vim +/i915_vma_resource_init +394 drivers/gpu/drm/i915/i915_vma.c
385
386 I915_SELFTEST_EXPORT void
387 i915_vma_resource_init_from_vma(struct i915_vma_resource *vma_res,
388 struct i915_vma *vma)
389 {
390 struct drm_i915_gem_object *obj = vma->obj;
391
392 i915_vma_resource_init(vma_res, vma->vm, vma->pages,
&vma->page_sizes,
393 obj->mm.rsgt,
i915_gem_object_is_readonly(obj),
> 394 i915_gem_object_is_lmem(obj),
> obj->mm.region,
395 vma->ops, vma->private, vma->node.start,
396 vma->node.size, vma->size);
397 }
398
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [PATCH v4 12/16] uapi/drm/dg2: Introduce format modifier for DG2 clear color
On 09/12/2021 17:45, Ramalingam C wrote:
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_fb.c| 8
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 -
include/uapi/drm/drm_fourcc.h | 8
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index e15216f1cb82..f10e77cb5b4a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -144,6 +144,12 @@ static const struct intel_modifier_desc intel_modifiers[]
= {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
.display_ver = { 13, 14 },
.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+ }, {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .display_ver = { 13, 14 },
+ .plane_caps = INTEL_PLANE_CAP_TILING_4 |
INTEL_PLANE_CAP_CCS_RC_CC,
+
+ .ccs.cc_planes = BIT(1),
}, {
.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
.display_ver = { 13, 14 },
@@ -559,6 +565,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb,
int color_plane)
else
return 512;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_4_TILED:
/*
@@ -763,6 +770,7 @@ unsigned int intel_surf_alignment(const struct
drm_framebuffer *fb,
case I915_FORMAT_MOD_Yf_TILED:
return 1 * 1024 * 1024;
case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
return 16 * 1024;
default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d80424194c75..9a89df9c0243 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -772,6 +772,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
return PLANE_CTL_TILED_4 |
PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
PLANE_CTL_CLEAR_COLOR_DISABLE;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ return PLANE_CTL_TILED_4 |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
case I915_FORMAT_MOD_Y_TILED_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return PLANE_CTL_TILED_Y |
PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2337,10 +2339,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
break;
case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
if (HAS_4TILE(dev_priv)) {
- if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+ PLANE_CTL_CLEAR_COLOR_DISABLE;
+
+ if ((val & rc_mask) == rc_mask)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+ else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+ fb->modifier =
I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
else
fb->modifier = I915_FORMAT_MOD_4_TILED;
} else {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 51fdda26844a..b155f69f2344 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -598,6 +598,14 @@ extern "C" {
*/
#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
My colleague Nanley (Cc) had some requests for clarifications on this
new modifier.
In particular in which plane is the clear color located.
I guess it wouldn't hurt to also state for each of the new modifiers
defined in this series, how many planes and what data they contain.
Thanks,
-Lionel
+/*
+ * Intel color control surfaces (CCS) for DG2 clear color render compression.
+ *
+ * DG2 uses a unified compression format for clear color render compression.
+ * The general layout is a tiled layout using 4Kb tiles i.e. Tile4 layout.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
/*
* Tiled, NV12MT, grouped in 64 (pi
Re: [Intel-gfx] [PATCH 2/2] drm/i915: clean up shrinker_release_pages
On 15/12/2021 15:55, Tvrtko Ursulin wrote:
On 15/12/2021 11:07, Matthew Auld wrote:
Add some proper flags for the different modes, and shorten the name to
something more snappy.
Looks good to me - but since it touches TTM I leave for Thomas to approve.
Regards,
Tvrtko
P.S. I hope writing the patch means you thought it is an improvement as
well, rather than feeling I was asking for it to be done.
Yes, I do see both patches as an improvement :)
Suggested-by: Tvrtko Ursulin
Signed-off-by: Matthew Auld
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 23 ---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 8 +++
drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 16 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 10
4 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 00c844caeabd..6f446cca4322 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -57,9 +57,26 @@ struct drm_i915_gem_object_ops {
void (*put_pages)(struct drm_i915_gem_object *obj,
struct sg_table *pages);
int (*truncate)(struct drm_i915_gem_object *obj);
- int (*shrinker_release_pages)(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool should_writeback);
+ /**
+ * shrink - Perform further backend specific actions to facilate
+ * shrinking.
+ * @obj: The gem object
+ * @flags: Extra flags to control shrinking behaviour in the backend
+ *
+ * Possible values for @flags:
+ *
+ * I915_GEM_OBJECT_SHRINK_WRITEBACK - Try to perform writeback of
the
+ * backing pages, if supported.
+ *
+ * I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT - Don't wait for the object to
+ * idle. Active objects can be considered later. The TTM backend
for
+ * example might have aync migrations going on, which don't use any
+ * i915_vma to track the active GTT binding, and hence having an
unbound
+ * object might not be enough.
+ */
+#define I915_GEM_OBJECT_SHRINK_WRITEBACK BIT(0)
+#define I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT BIT(1)
+ int (*shrink)(struct drm_i915_gem_object *obj, unsigned int flags);
int (*pread)(struct drm_i915_gem_object *obj,
const struct drm_i915_gem_pread *arg);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 7fdf4fa10b0e..6c57b0a79c8a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -331,9 +331,7 @@ shmem_writeback(struct drm_i915_gem_object *obj)
__shmem_writeback(obj->base.size, obj->base.filp->f_mapping);
}
-static int shmem_shrinker_release_pages(struct drm_i915_gem_object *obj,
- bool no_gpu_wait,
- bool writeback)
+static int shmem_shrink(struct drm_i915_gem_object *obj, unsigned int
flags)
{
switch (obj->mm.madv) {
case I915_MADV_DONTNEED:
@@ -342,7 +340,7 @@ static int shmem_shrinker_release_pages(struct
drm_i915_gem_object *obj,
return 0;
}
- if (writeback)
+ if (flags & I915_GEM_OBJECT_SHRINK_WRITEBACK)
shmem_writeback(obj);
return 0;
@@ -520,7 +518,7 @@ const struct drm_i915_gem_object_ops
i915_gem_shmem_ops = {
.get_pages = shmem_get_pages,
.put_pages = shmem_put_pages,
.truncate = shmem_truncate,
- .shrinker_release_pages = shmem_shrinker_release_pages,
+ .shrink = shmem_shrink,
.pwrite = shmem_pwrite,
.pread = shmem_pread,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
index fd54e05521f6..968ca0fdd57b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
@@ -57,10 +57,18 @@ static bool unsafe_drop_pages(struct
drm_i915_gem_object *obj,
static int try_to_writeback(struct drm_i915_gem_object *obj,
unsigned int flags)
{
- if (obj->ops->shrinker_release_pages)
- return obj->ops->shrinker_release_pages(obj,
- !(flags & I915_SHRINK_ACTIVE),
- flags & I915_SHRINK_WRITEBACK);
+ if (obj->ops->shrink) {
+ unsigned int shrink_flags = 0;
+
+ if (!(flags & I915_SHRINK_ACTIVE))
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_NO_GPU_WAIT;
+
+ if (flags & I915_SHRINK_WRITEBACK)
+ shrink_flags |= I915_GEM_OBJECT_SHRINK_WRITEBACK;
+
+ return obj->ops->shrink(obj, shrink_flags);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 923cc7ad8d70..21277f3c64e7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -424,16 +424,14 @@ int i915_
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg1: Read OPROM via SPI controller (rev2)
== Series Details == Series: drm/i915/dg1: Read OPROM via SPI controller (rev2) URL : https://patchwork.freedesktop.org/series/94826/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11004_full -> Patchwork_21854_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21854_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21854_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21854_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock@requests: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl7/igt@i915_selftest@m...@requests.html Known issues Here are the changes found in Patchwork_21854_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl10/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063] / [i915#3648]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb8/igt@gem_...@unwedge-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-tglb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-skl9/igt@gem_exec_capture@p...@bcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl3/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-iclb7/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-tglb6/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][11] -> [SKIP][12] ([fdo#109271]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_schedule@u-submit-golden-slice@vecs0: - shard-skl: NOTRUN -> [INCOMPLETE][15] ([i915#3797]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl3/igt@gem_exec_schedule@u-submit-golden-sl...@vecs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl10/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-skl1/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][18] ([i915#4613]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-tglb5/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@random: - shard-iclb: NOTRUN -> [SKIP][19] ([i915#4613]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21854/shard-iclb7/igt@gem_lmem_swapp...@random.html * igt@gem_lmem_swapping@smem-oom: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +4
Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/gt: Clear compress metadata for Xe_HP platforms
The fixes below fix gem_lmem_swapping@basic igt test
On 09/12/2021 15:45, Ramalingam C wrote:
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
Address of CCS buffer associated main BO is automatically calculated
by device itself. KMD/UMD can only access this buffer indirectly using
XY_CTRL_SURF_COPY_BLT cmd via the address of device memory buffer.
v2: Fixed issues with platform naming [Lucas]
Cc: CQ Tang
Signed-off-by: Ayaz A Siddiqui
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 14 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 120 ++-
2 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index f8253012d166..07bf5a1753bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -203,6 +203,20 @@
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
+#define XY_CTRL_SURF_INSTR_SIZE 5
+#define MI_FLUSH_DW_SIZE 3
+#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
+#define SRC_ACCESS_TYPE_SHIFT21
+#define DST_ACCESS_TYPE_SHIFT20
+#define CCS_SIZE_SHIFT 8
+#define XY_CTRL_SURF_MOCS_SHIFT 25
+#define NUM_CCS_BYTES_PER_BLOCK 256
+#define NUM_CCS_BLKS_PER_XFER1024
+#define INDIRECT_ACCESS 0
+#define DIRECT_ACCESS1
+#define MI_FLUSH_LLC BIT(9)
+#define MI_FLUSH_CCS BIT(16)
+
#define COLOR_BLT_CMD (2 << 29 | 0x40 << 22 | (5 - 2))
#define XY_COLOR_BLT_CMD (2 << 29 | 0x50 << 22)
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 19a01878fee3..64ffaacac1e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -16,6 +16,7 @@ struct insert_pte_data {
};
#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >> 8 : 0)
do the rounding here. Don't manually round, use kernel macros:
-#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ? (size) >>
8 : 0)
+#define GET_CCS_SIZE(i915, size) (HAS_FLAT_CCS(i915) ?
DIV_ROUND_UP(size, NUM_CCS_BYTES_PER_BLOCK ) : 0)
static bool engine_supports_migration(struct intel_engine_cs *engine)
{
@@ -488,15 +489,104 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
-static int emit_clear(struct i915_request *rq, int size, u32 value)
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Mask the 3 LSB to use the PPGTT address space */
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_SIZE(i915, size))
+ return 0;
+
+ /*
+* XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+* blocks. one XY_CTRL_SURF_COPY_BLT command can
+* trnasfer upto 1024 blocks.
+*/
+ num_blks = (GET_CCS_SIZE(i915, size) +
+ (NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
- num_blks = (GET_CCS_SIZE(i915, size) +
- (NUM_CCS_BYTES_PER_BLOCK - 1)) >> 8;
+ num_blks = GET_CCS_SIZE(i915, size);
+ num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+* We need to add a flush before and after
+* XY_CTRL_SURF_COPY_BLT
+*/
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+u8 src_mem_access, u8 dst_mem_access,
+int src_mocs, int dst_mocs,
+u16 num_ccs_blocks)
+{
+ int i = num_ccs_blocks;
+
+ /*
+* The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+* data in and out of the CCS region.
+*
+* We can copy at most 1024 blocks of 256 bytes using one
+* XY_CTRL_SURF_COPY_BLT instruction.
+*
+* In case we need to copy more than 1024 blocks, we need to add
+* another instruction to the same batch buffer.
+*
+* 1024 bl
Re: [Intel-gfx] [PATCH 1/7] drm/i915: Avoid using the i915_fence_array when collecting dependencies
Hi "Thomas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next
next-20211214]
[cannot apply to drm-intel/for-linux-next v5.16-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a003-20211214
(https://download.01.org/0day-ci/archive/20211216/202112160151.zgytb4fp-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/0f61eb08a6b9d7fa9f19eaa071ad5591de123633
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
git checkout 0f61eb08a6b9d7fa9f19eaa071ad5591de123633
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:634:5: warning: no previous
>> prototype for 'prev_deps' [-Wmissing-prototypes]
634 | int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx
*ctx,
| ^
vim +/prev_deps +634 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
633
> 634 int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx
> *ctx,
635struct i915_deps *deps)
636 {
637 int ret;
638
639 ret = i915_deps_add_dependency(deps, bo->moving, ctx);
640 if (!ret)
641 /*
642 * TODO: Only await excl fence here, and shared fences
before
643 * signaling the migration fence.
644 */
645 ret = i915_deps_add_resv(deps, bo->base.resv, true,
false, ctx);
646
647 return ret;
648 }
649
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] ✓ Fi.CI.IGT: success for Add driver for GSC controller
== Series Details == Series: Add driver for GSC controller URL : https://patchwork.freedesktop.org/series/98066/ State : success == Summary == CI Bug Log - changes from CI_DRM_11004_full -> Patchwork_21855_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21855_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][1] ([i915#1839]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-iclb5/igt@feature_discov...@display-4x.html * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-skl4/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-kbl7/igt@gem_ctx_isolation@preservation...@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-kbl4/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-skl9/igt@gem_exec_capture@p...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-skl6/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][7] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html - shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-iclb6/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: NOTRUN -> [FAIL][9] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-apl8/igt@gem_exec_fair@basic-pace-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-apl3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-contexts-all: - shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#118]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11004/shard-glk7/igt@gem_exec_whis...@basic-contexts-all.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-glk3/igt@gem_exec_whis...@basic-contexts-all.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2190]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-skl1/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html - shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +3 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21855/shard-skl6/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#4613]) +2 similar issues [23]: https://in
Re: [Intel-gfx] [PATCH 1/7] drm/i915: Avoid using the i915_fence_array when collecting dependencies
Hi "Thomas,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next
next-20211214]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next
airlied/drm-next v5.16-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a013-20211214
(https://download.01.org/0day-ci/archive/20211216/202112160101.aqbkqxoo-...@intel.com/config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project
dd245bab9fbb364faa1581e4f92ba3119a872fba)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
#
https://github.com/0day-ci/linux/commit/0f61eb08a6b9d7fa9f19eaa071ad5591de123633
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859
git checkout 0f61eb08a6b9d7fa9f19eaa071ad5591de123633
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1
O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:634:5: warning: no previous
>> prototype for function 'prev_deps' [-Wmissing-prototypes]
int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
^
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:634:1: note: declare 'static'
if the function is not intended to be used outside of this translation unit
int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
^
static
1 warning generated.
vim +/prev_deps +634 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
633
> 634 int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx
> *ctx,
635struct i915_deps *deps)
636 {
637 int ret;
638
639 ret = i915_deps_add_dependency(deps, bo->moving, ctx);
640 if (!ret)
641 /*
642 * TODO: Only await excl fence here, and shared fences
before
643 * signaling the migration fence.
644 */
645 ret = i915_deps_add_resv(deps, bo->base.resv, true,
false, ctx);
646
647 return ret;
648 }
649
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [PATCH 7/7] drm/i915: Use struct vma_resource instead of struct vma_snapshot
Hi "Thomas, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-tip/drm-tip] [also build test WARNING on next-20211214] [cannot apply to drm-exynos/exynos-drm-next drm/drm-next drm-intel/for-linux-next v5.16-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-a003-20211214 (https://download.01.org/0day-ci/archive/20211216/202112160255.kmo6u2nc-...@intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/ede025870be746e37b5bcde123cdf741aa685fab git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Thomas-Hellstr-m/drm-i915-Asynchronous-vma-unbinding/20211215-183859 git checkout ede025870be746e37b5bcde123cdf741aa685fab # save the config file to linux build tree mkdir build_dir make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/i915_request.h:43, from drivers/gpu/drm/i915/i915_active.h:13, from drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h:12, from drivers/gpu/drm/i915/i915_vma.h:33, from drivers/gpu/drm/i915/display/intel_display_types.h:50, from drivers/gpu/drm/i915/i915_driver.c:51: >> drivers/gpu/drm/i915/i915_vma_resource.h:176:15: warning: 'struct >> intel_memory_region' declared inside parameter list will not be visible >> outside of this definition or declaration 176 |struct intel_memory_region *mr, | ^~~ -- In file included from drivers/gpu/drm/i915/i915_request.h:43, from drivers/gpu/drm/i915/i915_active.h:13, from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:16, from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30, from drivers/gpu/drm/i915/i915_drv.h:74, from drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:9: >> drivers/gpu/drm/i915/i915_vma_resource.h:176:15: warning: 'struct >> intel_memory_region' declared inside parameter list will not be visible >> outside of this definition or declaration 176 |struct intel_memory_region *mr, | ^~~ drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c:464:5: warning: no previous prototype for 'prev_deps' [-Wmissing-prototypes] 464 | int prev_deps(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx, | ^ -- In file included from drivers/gpu/drm/i915/i915_request.h:43, from drivers/gpu/drm/i915/i915_active.h:13, from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:16, from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30, from drivers/gpu/drm/i915/i915_vma.c:28: >> drivers/gpu/drm/i915/i915_vma_resource.h:176:15: warning: 'struct >> intel_memory_region' declared inside parameter list will not be visible >> outside of this definition or declaration 176 |struct intel_memory_region *mr, | ^~~ drivers/gpu/drm/i915/i915_vma.c: In function 'i915_vma_resource_init_from_vma': drivers/gpu/drm/i915/i915_vma.c:394:48: error: passing argument 8 of 'i915_vma_resource_init' from incompatible pointer type [-Werror=incompatible-pointer-types] 394 | i915_gem_object_is_lmem(obj), obj->mm.region, | ~~~^~~ || |struct intel_memory_region * In file included from drivers/gpu/drm/i915/i915_request.h:43, from drivers/gpu/drm/i915/i915_active.h:13, from drivers/gpu/drm/i915/gem/i915_gem_object_types.h:16, from drivers/gpu/drm/i915/display/intel_frontbuffer.h:30, from drivers/gpu/drm/i915/i915_vma.c:28: drivers/gpu/drm/i915/i915_vma_resource.h:176:36: note: expected 'struct intel_memory_region *' but argument is of type 'struct intel_memory_region *' 176 |struct intel_memory_region *mr, |~~~
Re: [Intel-gfx] [PATCH 09/20] drm/i915/dp: Extract intel_dp_tmds_clock_valid()
On Fri, Dec 10, 2021 at 10:50:09AM +0530, Nautiyal, Ankit K wrote:
>
> On 10/15/2021 7:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We're currently duplicating the DFP min/max TMDS clock checks
> > in .mode_valid() and .compute_config(). Extract a helper suitable
> > for both use cases.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 59 +++--
> > 1 file changed, 26 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 45e4bf54e1de..b3b8e74fac9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -781,6 +781,25 @@ static bool intel_dp_hdisplay_bad(struct
> > drm_i915_private *dev_priv,
> > return hdisplay == 4096 && !HAS_DDI(dev_priv);
> > }
> >
> > +static enum drm_mode_status
> > +intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
> > + int clock, int bpc, bool ycbcr420_output)
> > +{
> > + int tmds_clock;
> > +
> > + tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
> > +
> > + if (intel_dp->dfp.min_tmds_clock &&
> > + tmds_clock < intel_dp->dfp.min_tmds_clock)
> > + return MODE_CLOCK_LOW;
> > +
> > + if (intel_dp->dfp.max_tmds_clock &&
> > + tmds_clock > intel_dp->dfp.max_tmds_clock)
> > + return MODE_CLOCK_HIGH;
> > +
> > + return MODE_OK;
> > +}
>
>
> This looks good to me, a common helper to check if the tmds clock
> calculated for the the bpc selected and 420 format is within the limits
> of the DFP tmds limitations.
>
> There are however some HDMI2.1 protocol converters that support higher
> mode with Fixed Rate Link (where the TMDS clock lane is used as an
> additional lane with hdmi2.1 sinks)
>
> In that case, we would need to skip the tmds check, as the TMDS clock
> will not be sufficient for modes that can be supported with FRL mode,
> and all those higher modes will get pruned.
>
> These PCONs will have additional fields in DPCD caps for maximum FRL
> rate in Gbps (stored in dfp->max_frl_rate), which we can use to check if
> the mode rate would be supported, if FRL mode is used.
>
> I was wondering if we add a similar check for this case or add another
> argument to this function "is_frl_mode" and have the bw check there.
I guess we should pull the FRL stuff into its own helper functions,
assuming there is something that can be shared between .mode_valid()
and .compute_config().
But looking at the FRL code it looks a bit sketchy. It doesn't seem
to account for any link bandwidth overhead from the 16b18b encoding
or whatever else overhead there is (the spec seems to have quite a
lot to say on this topic). Also it uses intel_dp_mode_min_output_bpp()
for the bandwidth calculation which seems wrong.
intel_dp_mode_min_output_bpp() deals with the DP side of the link
where min bpc can be as low as 6, but for the HDMI side min bpc
is always 8.
So looks to me like there's a bunch of stuff that needs fixing here.
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 6/7] drm/amdgpu: Ensure kunmap is called on error
On Tue, Dec 14, 2021 at 08:09:29AM +0100, Christian König wrote:
> Am 14.12.21 um 04:37 schrieb Ira Weiny:
> > On Mon, Dec 13, 2021 at 09:37:32PM +0100, Christian König wrote:
> > > Am 11.12.21 um 00:24 schrieb ira.we...@intel.com:
> > > > From: Ira Weiny
> > > >
> > > > The default case leaves the buffer object mapped in error.
> > > >
> > > > Add amdgpu_bo_kunmap() to that case to ensure the mapping is cleaned up.
> > > Mhm, good catch. But why do you want to do this in the first place?
> > I'm not sure I understand the question.
> >
> > Any mapping of memory should be paired with an unmapping when no longer
> > needed.
> > And this is supported by the call to amdgpu_bo_kunmap() in the other
> > non-default cases.
> >
> > Do you believe the mapping is not needed?
>
> No, the unmapping is not needed here. See the function amdgpu_bo_kmap(), it
> either creates the mapping or return the cached pointer.
Ah I missed that. Thanks.
>
> A call to amdgpu_bo_kunmap() is only done in a few places where we know that
> the created mapping most likely won't be needed any more. If that's not done
> the mapping is automatically destroyed when the BO is moved or freed up.
>
> I mean good bug fix, but you seem to see this as some kind of prerequisite
> to some follow up work converting TTM to use kmap_local() which most likely
> won't work in the first place.
Sure. I see now that it is more complicated than I thought but I never thought
of this as a strict prerequisite. Just something I found while trying to
figure out how this works.
How much of a speed up is it to maintain the ttm_bo_map_kmap map type? Could
this all be done with vmap and just remove the kmap stuff?
Ira
>
> Regards,
> Christian.
>
> >
> > Ira
> >
> > > Christian.
> > >
> > > > Signed-off-by: Ira Weiny
> > > >
> > > > ---
> > > > NOTE: It seems like this function could use a fair bit of refactoring
> > > > but this is the easiest way to fix the actual bug.
> > > > ---
> > > >drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 +
> > > >1 file changed, 1 insertion(+)
> > > > nice
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > > > index 6f8de11a17f1..b3ffd0f6b35f 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> > > > @@ -889,6 +889,7 @@ static int amdgpu_uvd_cs_msg(struct
> > > > amdgpu_uvd_cs_ctx *ctx,
> > > > return 0;
> > > > default:
> > > > + amdgpu_bo_kunmap(bo);
> > > > DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
> > > > }
>
[Intel-gfx] [CI] PR for new GuC v69.0.3
The following changes since commit b0e898fbaf377c99a36aac6fdeb7250003648ca4: linux-firmware: Update firmware file for Intel Bluetooth 9462 (2021-11-23 12:31:45 -0500) are available in the Git repository at: ssh://git.freedesktop.org/git/drm/drm-firmware guc_v69.0.3 for you to fetch changes up to 548b304a35b77cd43c1242e0eae68f775bd0df2a: i915: Add GuC v69.0.3 for all platforms (2021-12-15 13:28:54 -0800) John Harrison (1): i915: Add GuC v69.0.3 for all platforms WHENCE | 30 ++ i915/adlp_guc_69.0.3.bin | Bin 0 -> 356416 bytes i915/bxt_guc_69.0.3.bin | Bin 0 -> 216768 bytes i915/cml_guc_69.0.3.bin | Bin 0 -> 217664 bytes i915/dg1_guc_69.0.3.bin | Bin 0 -> 323968 bytes i915/ehl_guc_69.0.3.bin | Bin 0 -> 343360 bytes i915/glk_guc_69.0.3.bin | Bin 0 -> 217216 bytes i915/icl_guc_69.0.3.bin | Bin 0 -> 343360 bytes i915/kbl_guc_69.0.3.bin | Bin 0 -> 217664 bytes i915/skl_guc_69.0.3.bin | Bin 0 -> 216704 bytes i915/tgl_guc_69.0.3.bin | Bin 0 -> 343296 bytes 11 files changed, 30 insertions(+) create mode 100644 i915/adlp_guc_69.0.3.bin create mode 100644 i915/bxt_guc_69.0.3.bin create mode 100644 i915/cml_guc_69.0.3.bin create mode 100644 i915/dg1_guc_69.0.3.bin create mode 100644 i915/ehl_guc_69.0.3.bin create mode 100644 i915/glk_guc_69.0.3.bin create mode 100644 i915/icl_guc_69.0.3.bin create mode 100644 i915/kbl_guc_69.0.3.bin create mode 100644 i915/skl_guc_69.0.3.bin create mode 100644 i915/tgl_guc_69.0.3.bin
[Intel-gfx] [PATCH] drm/i915/guc: Check for wedged before doing stuff
From: John Harrison A fault injection probe test hit a BUG_ON in a GuC error path. It showed that the GuC code could potentially attempt to do many things when the device is actually wedged. So, add a check in to prevent that. Signed-off-by: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 9739da6f..88f002c4d41b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1350,7 +1350,8 @@ submission_disabled(struct intel_guc *guc) struct i915_sched_engine * const sched_engine = guc->sched_engine; return unlikely(!sched_engine || - !__tasklet_is_enabled(&sched_engine->tasklet)); + !__tasklet_is_enabled(&sched_engine->tasklet) || + test_bit(I915_WEDGED, &guc_to_gt(guc)->reset.flags)); } static void disable_submission(struct intel_guc *guc) -- 2.25.1
Re: [Intel-gfx] i915 Updates: ADL-P DMC v2.14
Bump! :) Thanks, - Madhumitha On Wed, 2021-12-08 at 18:11 +, Srivatsa, Anusha wrote: > Ping :) > Can these updates be merged to linux-firmware? > > > Thanks, > Anusha > > > -Original Message- > > From: Tolakanahalli Pradeep, Madhumitha > > > > Sent: Thursday, December 2, 2021 6:48 AM > > To: Hutchings, Ben ; > > intel-gfx@lists.freedesktop.org; > > k...@mcmartin.ca; jwbo...@kernel.org > > Cc: Srivatsa, Anusha ; linux- > > firmw...@kernel.org > > Subject: [Intel-gfx] i915 Updates: ADL-P DMC v2.14 > > > > Hi Ben, Josh, Kyle, > > > > Kindly add the below i915 changes to linux-firmware: > > > > The following changes since commit > > b0e898fbaf377c99a36aac6fdeb7250003648ca4: > > > > linux-firmware: Update firmware file for Intel Bluetooth 9462 > > (2021- > > 11-23 12:31:45 -0500) > > > > are available in the Git repository at: > > > > git://anongit.freedesktop.org/drm/drm-firmware > > adlp_dmc_v2.14_update > > > > for you to fetch changes up to > > 2a2aa410c2eaebe5807d1fd321e42b8f53288d91: > > > > i915: Add DMC firmware v2.14 for ADL-P (2021-12-01 16:50:30 - > > 0800) > > > > > > Madhumitha Tolakanahalli Pradeep (1): > > i915: Add DMC firmware v2.14 for ADL-P > > > > WHENCE | 3 +++ > > i915/adlp_dmc_ver2_14.bin | Bin 0 -> 77300 bytes > > 2 files changed, 3 insertions(+) > > create mode 100644 i915/adlp_dmc_ver2_14.bin > > > > Thanks! > > - Madhumitha > > >
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Check for wedged before doing stuff
== Series Details == Series: drm/i915/guc: Check for wedged before doing stuff URL : https://patchwork.freedesktop.org/series/98099/ State : success == Summary == CI Bug Log - changes from CI_DRM_11005 -> Patchwork_21856 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/index.html Participating hosts (43 -> 33) -- Missing(10): bat-dg1-6 bat-dg1-5 fi-bdw-gvtdvm fi-icl-u2 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21856 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271]) +21 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-skl-6600u: [INCOMPLETE][8] ([i915#4547]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_11005 -> Patchwork_21856 CI-20190529: 20190529 CI_DRM_11005: 2e6d871494af25300763592917a5a133a14d0f12 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6309: 61f0995ecaf1ce99d7046a325d8d926f27d8d2dd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21856: e4ef4fc9d52fcae74d5d46c583ed8723e9caeda8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e4ef4fc9d52f drm/i915/guc: Check for wedged before doing stuff == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/index.html
Re: [Intel-gfx] [PATCH] drm/i915/guc: Check for wedged before doing stuff
On Wed, Dec 15, 2021 at 02:45:56PM -0800, john.c.harri...@intel.com wrote: > From: John Harrison > > A fault injection probe test hit a BUG_ON in a GuC error path. It > showed that the GuC code could potentially attempt to do many things > when the device is actually wedged. So, add a check in to prevent that. > > Signed-off-by: John Harrison Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 9739da6f..88f002c4d41b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1350,7 +1350,8 @@ submission_disabled(struct intel_guc *guc) > struct i915_sched_engine * const sched_engine = guc->sched_engine; > > return unlikely(!sched_engine || > - !__tasklet_is_enabled(&sched_engine->tasklet)); > + !__tasklet_is_enabled(&sched_engine->tasklet) || > + test_bit(I915_WEDGED, &guc_to_gt(guc)->reset.flags)); > } > > static void disable_submission(struct intel_guc *guc) > -- > 2.25.1 >
Re: [Intel-gfx] [PATCH 4/4] drm/i915: Improve long running OCL w/a for GuC submission
On 12/10/2021 10:58 PM, john.c.harri...@intel.com wrote:
From: John Harrison
A workaround was added to the driver to allow OpenCL workloads to run
'forever' by disabling pre-emption on the RCS engine for Gen12.
It is not totally unbound as the heartbeat will kick in eventually
and cause a reset of the hung engine.
However, this does not work well in GuC submission mode. In GuC mode,
the pre-emption timeout is how GuC detects hung contexts and triggers
a per engine reset. Thus, disabling the timeout means also losing all
per engine reset ability. A full GT reset will still occur when the
heartbeat finally expires, but that is a much more destructive and
undesirable mechanism.
The purpose of the workaround is actually to give OpenCL tasks longer
to reach a pre-emption point after a pre-emption request has been
issued. This is necessary because Gen12 does not support mid-thread
pre-emption and OpenCL can have long running threads.
So, rather than disabling the timeout completely, just set it to a
'long' value. Likewise, bump the heartbeat interval. That gives the
OpenCL thread sufficient time to reach a pre-emption point without
being killed off either by the GuC or by the heartbeat.
Signed-off-by: John Harrison
On the approach and the code:
Reviewed-by: Daniele Ceraolo Spurio
Please get an ack from the interested parties on the actual numbers used
for the timeouts (they look big enough to me, but I'm not familiar with
the compute use-case).
Daniele
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 42 +--
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 352254e001b4..26af8d60fe2b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -382,9 +382,45 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id,
engine->props.timeslice_duration_ms =
CONFIG_DRM_I915_TIMESLICE_DURATION;
- /* Override to uninterruptible for OpenCL workloads. */
- if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
- engine->props.preempt_timeout_ms = 0;
+ /*
+* Mid-thread pre-emption is not available in Gen12. Unfortunately,
+* some OpenCL workloads run quite long threads. That means they get
+* reset due to not pre-empting in a timely manner.
+* The execlist solution was to disable pre-emption completely.
+* However, pre-emption timeouts are the way GuC detects hung contexts
+* and triggers engine resets. Thus, without pre-emption, there is no
+* per engine reset. And full GT reset is much more intrusive. So keep
+* the timeout for GuC submission platforms and just bump it to be
+* much larger. Also bump the heartbeat timeout to match, otherwise
+* the heartbeat can expire before the pre-emption can timeout and
+* thus trigger a full GT reset anyway.
+*/
+ if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS) {
+ if (intel_uc_wants_guc_submission(>->uc)) {
+ const unsigned long min_preempt = 7500;
+ const unsigned long min_beat = 5000;
+
+ if (engine->props.preempt_timeout_ms &&
+ engine->props.preempt_timeout_ms < min_preempt) {
+ drm_info(>->i915->drm, "Bumping pre-emption
timeout from %ld to %ld on %s to allow slow compute pre-emption\n",
+engine->props.preempt_timeout_ms,
+min_preempt, engine->name);
+
+ engine->props.preempt_timeout_ms = min_preempt;
+ }
+
+ if (engine->props.heartbeat_interval_ms &&
+ engine->props.heartbeat_interval_ms < min_beat) {
+ drm_info(>->i915->drm, "Bumping heartbeat interval
from %ld to %ld on %s to allow slow compute pre-emption\n",
+engine->props.heartbeat_interval_ms,
+min_beat, engine->name);
+
+ engine->props.heartbeat_interval_ms = min_beat;
+ }
+ } else {
+ engine->props.preempt_timeout_ms = 0;
+ }
+ }
engine->defaults = engine->props; /* never to change again */
Re: [Intel-gfx] [PATCH 3/4] drm/i915/guc: Flag an error if an engine reset fails
On 12/10/2021 10:58 PM, john.c.harri...@intel.com wrote:
From: John Harrison
If GuC encounters an error during engine reset, the i915 driver
promotes to full GT reset. This includes an info message about why the
reset is happening. However, that is not treated as a failure by any
of the CI systems because resets are an expected occurrance during
testing. This kind of failure is a major problem and should never
happen. So, complain more loudly and make sure CI notices.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9739da6f..6015815f1da0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4018,11 +4018,12 @@ int intel_guc_engine_failure_process_msg(struct
intel_guc *guc,
const u32 *msg, u32 len)
{
struct intel_engine_cs *engine;
+ struct intel_gt *gt = guc_to_gt(guc);
u8 guc_class, instance;
u32 reason;
if (unlikely(len != 3)) {
- drm_err(&guc_to_gt(guc)->i915->drm, "Invalid length %u", len);
+ drm_err(>->i915->drm, "Invalid length %u", len);
return -EPROTO;
}
@@ -4032,12 +4033,19 @@ int intel_guc_engine_failure_process_msg(struct intel_guc *guc,
engine = guc_lookup_engine(guc, guc_class, instance);
if (unlikely(!engine)) {
- drm_err(&guc_to_gt(guc)->i915->drm,
+ drm_err(>->i915->drm,
"Invalid engine %d:%d", guc_class, instance);
return -EPROTO;
}
- intel_gt_handle_error(guc_to_gt(guc), engine->mask,
+ /*
+* This is an unexpected failure of a hardware feature. So, log a real
+* error message not just the informational that comes with the reset.
+*/
+ drm_err(>->i915->drm, "GuC engine reset request failed on %d:%d (%s)
because %d",
In the error handling called below, the reason is logged as 0x%08x, so
IMO we should do the same here for consistency.
With that:
Reviewed-by: Daniele Ceraolo Spurio
Daniele
+ guc_class, instance, engine->name, reason);
+
+ intel_gt_handle_error(gt, engine->mask,
I915_ERROR_CAPTURE,
"GuC failed to reset %s (reason=0x%08x)\n",
engine->name, reason);
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Check for wedged before doing stuff
== Series Details == Series: drm/i915/guc: Check for wedged before doing stuff URL : https://patchwork.freedesktop.org/series/98099/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11005_full -> Patchwork_21856_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21856_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21856_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21856_full: ### IGT changes ### Possible regressions * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-skl6/igt@p...@gen8-unprivileged-single-ctx-counters.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-skl10/igt@p...@gen8-unprivileged-single-ctx-counters.html Warnings * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-tglb: [SKIP][3] ([fdo#109506] / [i915#2411]) -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-tglb7/igt@i915_pm_...@gem-execbuf-stress-pc8.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-tglb8/igt@i915_pm_...@gem-execbuf-stress-pc8.html Known issues Here are the changes found in Patchwork_21856_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29]) ([i915#4386]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl4/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl4/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl2/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl2/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl1/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl1/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl1/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl4/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl4/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl4/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11005/shard-apl6/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-apl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-apl1/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-apl1/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21856/shard-apl1/boot.html [34]: htt
[Intel-gfx] [PATCH v2] drm/i915/dg1: Read OPROM via SPI controller
From: Clint Taylor
Read OPROM SPI through MMIO and find VBT entry since we can't use
OpRegion and PCI mapping may not work on some systems due to most BIOSes
not leaving the Option ROM mapped.
v2: Remove message with allocation failure
Cc: Ville Syrjälä
Cc: Tomas Winkler
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 77 +--
drivers/gpu/drm/i915/i915_reg.h | 8 +++
2 files changed, 79 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 9d989c9f5da4..76a8f001f4c4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2335,6 +2335,63 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t
size)
return vbt;
}
+static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915)
+{
+ u32 count, data, found, store = 0;
+ u32 static_region, oprom_offset;
+ u32 oprom_size = 0x20;
+ u16 vbt_size;
+ u32 *vbt;
+
+ static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS);
+ static_region &= OPTIONROM_SPI_REGIONID_MASK;
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region);
+
+ oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET);
+ oprom_offset &= OROM_OFFSET_MASK;
+
+ for (count = 0; count < oprom_size; count += 4) {
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS,
oprom_offset + count);
+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+
+ if (data == *((const u32 *)"$VBT")) {
+ found = oprom_offset + count;
+ break;
+ }
+ }
+
+ if (count >= oprom_size)
+ goto err_not_found;
+
+ /* Get VBT size and allocate space for the VBT */
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
+ offsetof(struct vbt_header, vbt_size));
+ vbt_size = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+ vbt_size &= 0x;
+
+ vbt = kzalloc(vbt_size, GFP_KERNEL);
+ if (!vbt)
+ goto err_not_found;
+
+ for (count = 0; count < vbt_size; count += 4) {
+ intel_uncore_write(&i915->uncore, PRIMARY_SPI_ADDRESS, found +
count);
+ data = intel_uncore_read(&i915->uncore, PRIMARY_SPI_TRIGGER);
+ *(vbt + store++) = data;
+ }
+
+ if (!intel_bios_is_valid_vbt(vbt, vbt_size))
+ goto err_free_vbt;
+
+ drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n");
+
+ return (struct vbt_header *)vbt;
+
+err_free_vbt:
+ kfree(vbt);
+err_not_found:
+ return NULL;
+}
+
static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -2384,6 +2441,8 @@ static struct vbt_header *oprom_get_vbt(struct
drm_i915_private *i915)
pci_unmap_rom(pdev, oprom);
+ drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
+
return vbt;
err_free_vbt:
@@ -2418,17 +2477,23 @@ void intel_bios_init(struct drm_i915_private *i915)
init_vbt_defaults(i915);
- /* If the OpRegion does not have VBT, look in PCI ROM. */
+ /*
+* If the OpRegion does not have VBT, look in SPI flash through MMIO or
+* PCI mapping
+*/
+ if (!vbt && IS_DGFX(i915)) {
+ oprom_vbt = spi_oprom_get_vbt(i915);
+ vbt = oprom_vbt;
+ }
+
if (!vbt) {
oprom_vbt = oprom_get_vbt(i915);
- if (!oprom_vbt)
- goto out;
-
vbt = oprom_vbt;
-
- drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n");
}
+ if (!vbt)
+ goto out;
+
bdb = get_bdb_header(vbt);
i915->vbt.version = bdb->version;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 698a023e70f5..3240b3eb1ddd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -12974,6 +12974,14 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
+#define PRIMARY_SPI_TRIGGER_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
+#define SPI_STATIC_REGIONS _MMIO(0x102090)
+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
+#define OROM_OFFSET_MMIO(0x1020c0)
+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
+
/* This register controls the Display State Buffer (DSB) engines. */
#define _DSBSL_INSTANCE_BASE
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg1: Read OPROM via SPI controller (rev3)
== Series Details == Series: drm/i915/dg1: Read OPROM via SPI controller (rev3) URL : https://patchwork.freedesktop.org/series/94826/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg1: Read OPROM via SPI controller (rev3)
== Series Details == Series: drm/i915/dg1: Read OPROM via SPI controller (rev3) URL : https://patchwork.freedesktop.org/series/94826/ State : success == Summary == CI Bug Log - changes from CI_DRM_11006 -> Patchwork_21857 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/index.html Participating hosts (41 -> 34) -- Additional (2): fi-icl-u2 fi-rkl-guc Missing(9): fi-kbl-soraka bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 fi-pnv-d510 fi-bdw-samus bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21857 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][4] -> [FAIL][5] ([i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11006/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-rkl-guc: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@gem_lmem_swapp...@verify-random.html * igt@gem_tiled_pread_basic: - fi-rkl-guc: NOTRUN -> [SKIP][9] ([i915#3282]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-guc: NOTRUN -> [SKIP][10] ([i915#3012]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][11] -> [INCOMPLETE][12] ([i915#4785]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11006/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-edid-read: - fi-rkl-guc: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-rkl-guc: NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109278]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-guc: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@kms_force_connector_ba...@force-load-detect.html - fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-rkl-guc: NOTRUN -> [SKIP][19] ([i915#533]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21857/fi-rkl-guc/igt@kms_pipe_crc_ba...@compare-crc-san
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 07/11] tests/i915/i915_hangman: Add alive-ness test after error capture
On Mon, Dec 13, 2021 at 03:29:10PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> Added a an extra step to the i915_hangman tests to check that the
> system is still alive after the hang and recovery. This submits a
> simple batch to each engine which does a write to memory and checks
> that the write occurred.
>
> Signed-off-by: John Harrison
> ---
> tests/i915/i915_hangman.c | 115 ++
> 1 file changed, 115 insertions(+)
>
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index b77705206..20653b479 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -47,8 +47,113 @@
> static int device = -1;
> static int sysfs = -1;
>
> +#define OFFSET_ALIVE 10
> +
> IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>
> +/* Requires master for STORE_DWORD on gen4/5 */
> +static void store(int fd, const struct intel_execution_engine2 *e,
> + int fence, uint32_t target, unsigned offset_value)
> +{
> + const int SCRATCH = 0;
> + const int BATCH = 1;
> + const int gen = intel_gen(intel_get_drm_devid(fd));
> + struct drm_i915_gem_exec_object2 obj[2];
> + struct drm_i915_gem_relocation_entry reloc;
> + struct drm_i915_gem_execbuffer2 execbuf;
> + uint32_t batch[16];
> + int i;
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.buffer_count = ARRAY_SIZE(obj);
> + execbuf.flags = e->flags;
> + if (fence != -1) {
> + execbuf.flags |= I915_EXEC_FENCE_IN;
> + execbuf.rsvd2 = fence;
> + }
> + if (gen < 6)
> + execbuf.flags |= I915_EXEC_SECURE;
> +
> + memset(obj, 0, sizeof(obj));
> + obj[SCRATCH].handle = target;
> +
> + obj[BATCH].handle = gem_create(fd, 4096);
> + obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> + obj[BATCH].relocation_count = 1;
> + memset(&reloc, 0, sizeof(reloc));
> +
> + i = 0;
> + reloc.target_handle = obj[SCRATCH].handle;
> + reloc.presumed_offset = -1;
> + reloc.offset = sizeof(uint32_t) * (i + 1);
> + reloc.delta = sizeof(uint32_t) * offset_value;
> + reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> + reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> + batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> + if (gen >= 8) {
> + batch[++i] = reloc.delta;
> + batch[++i] = 0;
> + } else if (gen >= 4) {
> + batch[++i] = 0;
> + batch[++i] = reloc.delta;
> + reloc.offset += sizeof(uint32_t);
> + } else {
> + batch[i]--;
> + batch[++i] = reloc.delta;
> + }
> + batch[++i] = offset_value;
> + batch[++i] = MI_BATCH_BUFFER_END;
> + gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> + gem_execbuf(fd, &execbuf);
> + gem_close(fd, obj[BATCH].handle);
> +}
> +
> +static void check_alive(void)
> +{
> + const struct intel_execution_engine2 *engine;
> + const intel_ctx_t *ctx;
> + uint32_t scratch, *out;
> + int fd, i = 0;
> + uint64_t ahnd;
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> + igt_require(gem_class_can_store_dword(fd, 0));
> +
> + ctx = intel_ctx_create_all_physical(fd);
> + ahnd = get_reloc_ahnd(fd, ctx->id);
> + scratch = gem_create(fd, 4096);
> + out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
> + gem_set_domain(fd, scratch,
> + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +
> + for_each_physical_engine(fd, engine) {
> + igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
> + i++;
> + }
> +
> + i = 0;
> + for_each_ctx_engine(fd, ctx, engine) {
> + if (!gem_class_can_store_dword(fd, engine->class))
> + continue;
> +
> + /* +OFFSET_ALIVE to ensure engine zero doesn't get a false
> negative */
> + store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
You need to pass ctx + ahnd to store() to add softpin path. Relocs
won't work above Tigerlake.
--
Zbigniew
> + i++;
> + }
> +
> + gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
> +
> + while (i--)
> + igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
> +
> + munmap(out, 4096);
> + gem_close(fd, scratch);
> + put_ahnd(ahnd);
> + intel_ctx_destroy(fd, ctx);
> + close(fd);
> +}
> +
> static bool has_error_state(int dir)
> {
> bool result;
> @@ -230,6 +335,8 @@ static void test_error_state_capture(const intel_ctx_t
> *ctx,
> check_error_state(e->name, offset, batch);
> munmap(batch, 4096);
> put_ahnd(ahnd);
> +
> + check_alive();
> }
>
> static void
> @@ -288,6 +395,8 @@ test_engine_hang(const intel_ctx_t *ctx,
> put_ahnd(ahndN);
> }
> put_ahnd(ahnd);
> +
> + check_alive();
> }
>
> static
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function
On Mon, Dec 13, 2021 at 03:29:11PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> A lot of tests use almost identical code for creating a batch buffer
> which does a single write to memory. This patch collects two such
> instances into a common helper function. Unfortunately, the other
> instances are all subtly different enough to make it not so trivial to
> try to use the helper. It could be done but it is unclear if it is
> worth the effort at this point. This patch proves the concept, if
> people like it enough then it can be extended.
>
> Signed-off-by: John Harrison
> ---
> lib/igt_store.c | 114
> lib/igt_store.h | 30 ++
> lib/meson.build | 1 +
> tests/i915/gem_exec_fence.c | 77 ++--
> tests/i915/i915_hangman.c | 61 +--
> 5 files changed, 152 insertions(+), 131 deletions(-)
> create mode 100644 lib/igt_store.c
> create mode 100644 lib/igt_store.h
>
> diff --git a/lib/igt_store.c b/lib/igt_store.c
> new file mode 100644
> index 0..6d9869b58
> --- /dev/null
> +++ b/lib/igt_store.c
> @@ -0,0 +1,114 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
Use SPDX. I like idea of extracting this.
> +
> +#include "i915/gem_create.h"
> +#include "igt_core.h"
> +#include "drmtest.h"
> +#include "igt_store.h"
> +#include "intel_chipset.h"
> +#include "intel_reg.h"
> +#include "ioctl_wrappers.h"
> +#include "lib/intel_allocator.h"
> +
> +/**
> + * SECTION:igt_store_word
> + * @short_description: Library for writing a value to memory
> + * @title: StoreWord
> + * @include: igt.h
> + *
> + * A lot of igt testcases need some mechanism for writing a value to memory
> + * as a test that a batch buffer has executed.
> + *
> + * NB: Requires master for STORE_DWORD on gen4/5.
> + */
> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + int fence, uint32_t target_handle,
> + uint64_t target_offset, uint32_t target_value)
> +{
> + const int SCRATCH = 0;
> + const int BATCH = 1;
> + const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> + struct drm_i915_gem_exec_object2 obj[2];
> + struct drm_i915_gem_relocation_entry reloc;
> + struct drm_i915_gem_execbuffer2 execbuf;
> + uint32_t batch[16], delta;
> + uint64_t bb_offset;
> + int i;
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.buffer_count = ARRAY_SIZE(obj);
> + execbuf.flags = e->flags;
> + execbuf.rsvd1 = ctx->id;
> + if (fence != -1) {
> + execbuf.flags |= I915_EXEC_FENCE_IN;
> + execbuf.rsvd2 = fence;
> + }
> + if (gen < 6)
> + execbuf.flags |= I915_EXEC_SECURE;
> +
> + memset(obj, 0, sizeof(obj));
> + obj[SCRATCH].handle = target_handle;
> +
> + obj[BATCH].handle = gem_create(fd, 4096);
> + obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> + obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> + bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> + memset(&reloc, 0, sizeof(reloc));
> +
> + i = 0;
> + delta = sizeof(uint32_t) * target_value;/* why value not
> offset??? */
I guess I know why there's problem here. target_offset is address in vm
passed by the caller. This is regarding to some limitations of allocator
infrastructure - for "reloc" pseudo-allocator you would get new offset
(internally it returns offset and then add size for new "allocation").
With this we don't need to wait for rebind offset for new execbuf.
With "simple" allocator put will release offset so new allocation will
reuse same offset. Ashutosh p
