[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Additional DG2 workarounds
== Series Details == Series: i915: Additional DG2 workarounds URL : https://patchwork.freedesktop.org/series/96824/ State : success == Summary == CI Bug Log - changes from CI_DRM_10872_full -> Patchwork_21565_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_21565_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21565_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 12) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21565_full: ### IGT changes ### Warnings * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-tglb: [SKIP][1] ([fdo#111615]) -> [SKIP][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-tglb5/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-tglb2/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html ### Piglit changes ### Warnings * spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-abs-dvec3: - pig-snb-2600: [FAIL][3] ([i915#4517]) -> [FAIL][4] +25292 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/pig-snb-2600/spec@arb_gpu_shader_fp64@execution@built-in-functi...@fs-abs-dvec3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/pig-snb-2600/spec@arb_gpu_shader_fp64@execution@built-in-functi...@fs-abs-dvec3.html Known issues Here are the changes found in Patchwork_21565_full that come from known issues: ### IGT changes ### Issues hit * igt@feature_discovery@display-3x: - shard-tglb: NOTRUN -> [SKIP][5] ([i915#1839]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-tglb2/igt@feature_discov...@display-3x.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +5 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-kbl2/igt@gem_ctx_isolation@preservation...@vcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html - shard-skl: NOTRUN -> [INCOMPLETE][8] ([i915#198]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-skl6/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_ctx_persistence@many-contexts: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2410]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-iclb5/igt@gem_ctx_persiste...@many-contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-iclb3/igt@gem_ctx_persiste...@many-contexts.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-tglb2/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][14] -> [FAIL][15] ([i915#2842] / [i915#3468]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-apl3/igt@gem_exec_fair@basic-n...@vecs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-kbl7/igt@gem_exec_fair@basic-p...@vecs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html * igt@gem_pwrite@basic-exhaustion: - shard-apl: NOTRUN -> [WARN][18] ([i915#2658]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-apl7/igt@gem_pwr...@basic-exhaustion.html - shard-skl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21565/shard-skl10/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@coherency-sync: - shard-tglb: NOTRUN -> [SKIP][20] ([fdo#110542]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/
Re: [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes
On Thu, 11 Nov 2021 21:58:35 +
"Shankar, Uma" wrote:
> > -Original Message-
> > From: Harry Wentland
> > Sent: Friday, November 12, 2021 2:41 AM
> > To: Shankar, Uma ; Ville Syrjälä
> >
> > Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> > ppaala...@gmail.com; brian.star...@arm.com; sebast...@sebastianwick.net;
> > shashank.sha...@amd.com
> > Subject: Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct
> > for
> > HDR planes
> >
> >
> >
> > On 2021-11-11 15:42, Shankar, Uma wrote:
> > >
> > >
> > >> -Original Message-
> > >> From: Ville Syrjälä
> > >> Sent: Thursday, November 11, 2021 10:13 PM
> > >> To: Harry Wentland
> > >> Cc: Shankar, Uma ;
> > >> intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org;
> > >> ppaala...@gmail.com; brian.star...@arm.com;
> > >> sebast...@sebastianwick.net; shashank.sha...@amd.com
> > >> Subject: Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range
> > >> struct for HDR planes
> > >>
> > >> On Thu, Nov 11, 2021 at 10:17:17AM -0500, Harry Wentland wrote:
> > >>>
> > >>>
> > >>> On 2021-09-06 17:38, Uma Shankar wrote:
> > Define the structure with XE_LPD degamma lut ranges. HDR and SDR
> > planes have different capabilities, implemented respective
> > structure for the HDR planes.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 52
> > ++
> > 1 file changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index afcb4bf3826c..6403bd74324b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -2092,6 +2092,58 @@ static void icl_read_luts(struct
> > intel_crtc_state
> > >> *crtc_state)
> > }
> > }
> >
> > + /* FIXME input bpc? */
> > +__maybe_unused
> > +static const struct drm_color_lut_range d13_degamma_hdr[] = {
> > + /* segment 1 */
> > + {
> > + .flags = (DRM_MODE_LUT_GAMMA |
> > +DRM_MODE_LUT_REFLECT_NEGATIVE |
> > +DRM_MODE_LUT_INTERPOLATE |
> > +DRM_MODE_LUT_NON_DECREASING),
> > + .count = 128,
> > + .input_bpc = 24, .output_bpc = 16,
> > + .start = 0, .end = (1 << 24) - 1,
> > + .min = 0, .max = (1 << 24) - 1,
> > + },
> > + /* segment 2 */
> > + {
> > + .flags = (DRM_MODE_LUT_GAMMA |
> > +DRM_MODE_LUT_REFLECT_NEGATIVE |
> > +DRM_MODE_LUT_INTERPOLATE |
> > +DRM_MODE_LUT_REUSE_LAST |
> > +DRM_MODE_LUT_NON_DECREASING),
> > + .count = 1,
> > + .input_bpc = 24, .output_bpc = 16,
> > + .start = (1 << 24) - 1, .end = 1 << 24,
> > + .min = 0, .max = (1 << 27) - 1,
> > + },
> > + /* Segment 3 */
> > + {
> > + .flags = (DRM_MODE_LUT_GAMMA |
> > +DRM_MODE_LUT_REFLECT_NEGATIVE |
> > +DRM_MODE_LUT_INTERPOLATE |
> > +DRM_MODE_LUT_REUSE_LAST |
> > +DRM_MODE_LUT_NON_DECREASING),
> > + .count = 1,
> > + .input_bpc = 24, .output_bpc = 16,
> > + .start = 1 << 24, .end = 3 << 24,
> > + .min = 0, .max = (1 << 27) - 1,
> > + },
> > + /* Segment 4 */
> > + {
> > + .flags = (DRM_MODE_LUT_GAMMA |
> > +DRM_MODE_LUT_REFLECT_NEGATIVE |
> > +DRM_MODE_LUT_INTERPOLATE |
> > +DRM_MODE_LUT_REUSE_LAST |
> > +DRM_MODE_LUT_NON_DECREASING),
> > + .count = 1,
> > + .input_bpc = 24, .output_bpc = 16,
> > + .start = 3 << 24, .end = 7 << 24,
> > + .min = 0, .max = (1 << 27) - 1,
> > + },
> > +};
> > >>>
> > >>> If I understand this right, userspace would need this definition in
> > >>> order to populate the degamma blob. Should this sit in a UAPI header?
Are you asking whether 'struct drm_color_lut_range` is defined in any
userspace visible header?
It seems to be in patch 2.
> > >
> > > Hi Harry, Pekka and Ville,
> > > Sorry for being a bit late on the replies, got side tracked with various
> > > issues.
> > > I am back on this. Apologies for delay.
> > >
> > >> My original idea (not sure it's fully realized in this series) is to
> > >> have a new GAMMA_MODE/etc.
Re: [Intel-gfx] [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955
On Thu, 11 Nov 2021, Matt Roper wrote:
> This workaround is documented a bit strangely in the bspec; it's listed
> as an A0 workaround, but the description clarifies that the workaround
> is implicitly handled by the hardware and what the driver really needs
> to do is program a chicken bit to reenable some internal behavior.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ceee8ac6671..5d50d06f4eb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct
> intel_crtc_state *crtc_state)
> else if (DISPLAY_VER(dev_priv) >= 13)
> tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
>
> + /* Wa_14010547955:dg2 */
> + if (IS_DG2_DISP_STEP(dev_priv, STEP_B0, STEP_FOREVER))
How did we end up with _DISP_ for DG2 when everything else has
_DISPLAY_?
BR,
Jani.
> + tmp |= DG2_RENDER_CCSTAG_4_3_EN;
> +
> intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07d6cf76c389..680ace373e00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8480,8 +8480,9 @@ enum {
> _PIPEB_CHICKEN)
> #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
> #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
> -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
> -#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
> +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
> +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
> +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
>
> #define FF_MODE2 _MMIO(0x6604)
> #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] ALSA: hda: fix general protection fault in azx_runtime_idle
On Thu, 11 Nov 2021 18:39:36 +0100,
Kai Vehmanen wrote:
>
> Hi,
>
> On Thu, 11 Nov 2021, Takashi Iwai wrote:
>
> > A potential problem with the current code is that it doesn't disable
> > the runtime PM at the release procedure. Could you try the patch
> > below? You can put WARN_ON(!chip) at azx_runtime_idle(), too, for
> > catching the invalid runtime call.
> [...]
> > --- a/sound/pci/hda/hda_intel.c
> > +++ b/sound/pci/hda/hda_intel.c
> > @@ -1347,8 +1347,13 @@ static void azx_free(struct azx *chip)
> > if (hda->freed)
> > return;
> >
> > - if (azx_has_pm_runtime(chip) && chip->running)
> > + if (azx_has_pm_runtime(chip) && chip->running) {
> > pm_runtime_get_noresume(&pci->dev);
> > + pm_runtime_forbid(&pci->dev);
> > + pm_runtime_dont_use_autosuspend(&pci->dev);
> > + pm_runtime_disable(&pci->dev);
> > + }
> > +
> > chip->running = 0;
>
> Tested with next-20211019 (first next tag where I've seen test failures)
> and your patch, and this seems to do the trick. I didn't have my drvdata
> patch included when I ran the test. No rpm_idle() calls
> anymore after azx_remove(), so the bug is not hit.
So far, so good...
> > azx_del_card_list(chip);
> > @@ -2320,6 +2325,7 @@ static int azx_probe_continue(struct azx *chip)
> > set_default_power_save(chip);
> >
> > if (azx_has_pm_runtime(chip)) {
> > + pm_runtime_enable(&pci->dev);
> > pm_runtime_use_autosuspend(&pci->dev);
>
> This does generate warnings
> [ 13.495059] snd_hda_intel :00:1f.3: Unbalanced pm_runtime_enable!
>
> And later
> [ 54.770701] Enabling runtime PM for inactive device (:00:1f.3) with
> active children
> [ 54.770718] WARNING: CPU: 0 PID: 10 at drivers/base/power/runtime.c:1439
> pm_runtime_enable+0x98/0xb0
>
> Adding a "pm_runtime_set_active(&pci->dev)" to both azx_free() and
> azx_probe_continue() seems to help and fix still works.
Ah yes, I was confused as if it were already called in hdac_device.c,
but this was about the HD-audio bus controller, not the codec.
Below is the revised one.
Takashi
-- 8< --
From: Takashi Iwai
Subject: [PATCH] ALSA: hda: intel: More comprehensive PM runtime setup for
controller driver
Currently we haven't explicitly enable and allow/forbid the runtime PM
at the probe and the remove phases of HD-audio controller driver, and
this was the reason of a GPF mentioned in the commit e81478bbe7a1
("ALSA: hda: fix general protection fault in azx_runtime_idle");
namely, even after the resources are released, the runtime PM might be
still invoked by the bound graphics driver during the remove of the
controller driver. Although we've fixed it by clearing the drvdata
reference, it'd be also better to cover the runtime PM issue more
properly.
This patch adds a few more pm_runtime_*() calls at the probe and the
remove time for setting and cleaning up the runtime PM. Particularly,
now more explicitly pm_runtime_enable() and _disable() get called as
well as pm_runtime_forbid() call at the remove callback, so that a
use-after-free should be avoided.
Reported-by: Kai Vehmanen
Signed-off-by: Takashi Iwai
---
sound/pci/hda/hda_intel.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index fe51163f2d82..45e85180048c 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1347,8 +1347,14 @@ static void azx_free(struct azx *chip)
if (hda->freed)
return;
- if (azx_has_pm_runtime(chip) && chip->running)
+ if (azx_has_pm_runtime(chip) && chip->running) {
pm_runtime_get_noresume(&pci->dev);
+ pm_runtime_disable(&pci->dev);
+ pm_runtime_set_suspended(&pci->dev);
+ pm_runtime_forbid(&pci->dev);
+ pm_runtime_dont_use_autosuspend(&pci->dev);
+ }
+
chip->running = 0;
azx_del_card_list(chip);
@@ -2322,6 +2328,8 @@ static int azx_probe_continue(struct azx *chip)
if (azx_has_pm_runtime(chip)) {
pm_runtime_use_autosuspend(&pci->dev);
pm_runtime_allow(&pci->dev);
+ pm_runtime_set_active(&pci->dev);
+ pm_runtime_enable(&pci->dev);
pm_runtime_put_autosuspend(&pci->dev);
}
--
2.31.1
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial workarounds for Xe_HP SDV and DG2
On Thu, Nov 11, 2021 at 09:57:34PM +0200, Vudum, Lakshminarayana wrote: > spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-abs-dvec3 test is > not in CI bug log yet. > > So, I can address this failure and re-report the results. FYI @Latvala, Petri piglit results from postmerge are fed to cibuglog only if there's failures to keep the cpu usage required by test listing under control. Because of that, handling premerge failures like this is a bit awkward. Recommendation for this is to just ignore it, looks like snb just had a bad day running anything. -- Petri Latvala > > Lakshmi. > -Original Message- > From: Roper, Matthew D > Sent: Thursday, November 11, 2021 11:14 AM > To: intel-gfx@lists.freedesktop.org > Cc: Vudum, Lakshminarayana > Subject: Re: ✗ Fi.CI.IGT: failure for i915: Initial workarounds for Xe_HP SDV > and DG2 > > On Wed, Nov 03, 2021 at 02:16:42AM +, Patchwork wrote: > > == Series Details == > > > > Series: i915: Initial workarounds for Xe_HP SDV and DG2 > > URL : https://patchwork.freedesktop.org/series/96513/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_10830_full -> Patchwork_21509_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_21509_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_21509_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Participating hosts (10 -> 11) > > -- > > > > Additional (1): pig-snb-2600 > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_21509_full: > > > > ### Piglit changes ### > > > > Possible regressions > > > > * spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-abs-dvec3 > > (NEW): > > - pig-snb-2600: NOTRUN -> [FAIL][1] +25298 similar issues > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21509/pig-snb-2600/ > > spec@arb_gpu_shader_fp64@execution@built-in-functi...@fs-abs-dvec3.htm > > l > > piglit: error: waffle_display_connect failed due to > WAFFLE_ERROR_UNKNOWN: open drm file for gbm failed > > Seems to be a problem with piglit opening the DRM file handle on this new > machine; the Xe_HP SDV and DG2 patches here wouldn't have affected the > behavior of SNB. > > Series applies to drm-intel-gt-next. Thanks Clint and Anusha for the reviews. > > > Matt > > > > > > > New tests > > - > > > > New tests have been introduced between CI_DRM_10830_full and > > Patchwork_21509_full: > > > > ### New Piglit tests (24855) ### > > > > * fast_color_clear@all-colors: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * fast_color_clear@fast-slow-clear-interaction: > > - Statuses : 1 fail(s) > > - Exec time: [0.06] s > > > > * fast_color_clear@fcc-blit-between-clears: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * fast_color_clear@fcc-read-after-clear blit rb: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * fast_color_clear@fcc-read-after-clear blit tex: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * fast_color_clear@fcc-read-after-clear copy rb: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * fast_color_clear@fcc-read-after-clear copy tex: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * fast_color_clear@fcc-read-after-clear read_pixels rb: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * fast_color_clear@fcc-read-after-clear read_pixels tex: > > - Statuses : 1 fail(s) > > - Exec time: [0.07] s > > > > * fast_color_clear@fcc-read-after-clear sample tex: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * fast_color_clear@fcc-read-to-pbo-after-clear: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * fast_color_clear@non-redundant-clear: > > - Statuses : 1 fail(s) > > - Exec time: [0.07] s > > > > * fast_color_clear@redundant-clear: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * hiz@hiz-depth-read-fbo-d24-s0: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * hiz@hiz-depth-read-fbo-d24-s8: > > - Statuses : 1 fail(s) > > - Exec time: [0.06] s > > > > * hiz@hiz-depth-read-fbo-d24s8: > > - Statuses : 1 fail(s) > > - Exec time: [0.04] s > > > > * hiz@hiz-depth-read-window-stencil0: > > - Statuses : 1 fail(s) > > - Exec time: [0.05] s > > > > * hiz@hiz-depth-read-window-stencil1: > > - Statuses : 1 fail(s) > > - Exec
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
== Series Details == Series: ALSA: hda: fix general protection fault in azx_runtime_idle (rev3) URL : https://patchwork.freedesktop.org/series/96784/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3d6b0b3ff97c ALSA: hda: fix general protection fault in azx_runtime_idle -:53: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #53: > [ 54.770701] Enabling runtime PM for inactive device (:00:1f.3) with > active children -:73: WARNING:UNKNOWN_COMMIT_ID: Unknown commit id 'e81478bbe7a1', maybe rebased or not pulled? #73: this was the reason of a GPF mentioned in the commit e81478bbe7a1 total: 0 errors, 2 warnings, 0 checks, 23 lines checked
[Intel-gfx] ✗ Fi.CI.DOCS: warning for ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
== Series Details == Series: ALSA: hda: fix general protection fault in azx_runtime_idle (rev3) URL : https://patchwork.freedesktop.org/series/96784/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Initial workarounds for Xe_HP SDV and DG2
On Fri, Nov 12, 2021 at 12:02:24PM +0200, Petri Latvala wrote: > On Thu, Nov 11, 2021 at 09:57:34PM +0200, Vudum, Lakshminarayana wrote: > > spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-abs-dvec3 test is > > not in CI bug log yet. > > > > So, I can address this failure and re-report the results. FYI @Latvala, > > Petri > > piglit results from postmerge are fed to cibuglog only if there's > failures to keep the cpu usage required by test listing under > control. Because of that, handling premerge failures like this is a > bit awkward. Recommendation for this is to just ignore it, looks like > snb just had a bad day running anything. Having said that, fi-snb-2600 had troubles running anything with this too. Same for a few other platforms. And after merging this, they haven't booted up. An actual regression? fi-ivb-3770 fi-snb-2520m fi-snb-2600 fi-ilk-650 fi-ilk-m540 fi-elk-e7500 fi-bwr-2160 fi-pnv-d510 -- Petri Latvala > > > -- > Petri Latvala > > > > > > Lakshmi. > > -Original Message- > > From: Roper, Matthew D > > Sent: Thursday, November 11, 2021 11:14 AM > > To: intel-gfx@lists.freedesktop.org > > Cc: Vudum, Lakshminarayana > > Subject: Re: ✗ Fi.CI.IGT: failure for i915: Initial workarounds for Xe_HP > > SDV and DG2 > > > > On Wed, Nov 03, 2021 at 02:16:42AM +, Patchwork wrote: > > > == Series Details == > > > > > > Series: i915: Initial workarounds for Xe_HP SDV and DG2 > > > URL : https://patchwork.freedesktop.org/series/96513/ > > > State : failure > > > > > > == Summary == > > > > > > CI Bug Log - changes from CI_DRM_10830_full -> Patchwork_21509_full > > > > > > > > > Summary > > > --- > > > > > > **FAILURE** > > > > > > Serious unknown changes coming with Patchwork_21509_full absolutely > > > need to be > > > verified manually. > > > > > > If you think the reported changes have nothing to do with the changes > > > introduced in Patchwork_21509_full, please notify your bug team to > > > allow them > > > to document this new failure mode, which will reduce false positives in > > > CI. > > > > > > > > > > > > Participating hosts (10 -> 11) > > > -- > > > > > > Additional (1): pig-snb-2600 > > > > > > Possible new issues > > > --- > > > > > > Here are the unknown changes that may have been introduced in > > > Patchwork_21509_full: > > > > > > ### Piglit changes ### > > > > > > Possible regressions > > > > > > * spec@arb_gpu_shader_fp64@execution@built-in-functions@fs-abs-dvec3 > > > (NEW): > > > - pig-snb-2600: NOTRUN -> [FAIL][1] +25298 similar issues > > >[1]: > > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21509/pig-snb-2600/ > > > spec@arb_gpu_shader_fp64@execution@built-in-functi...@fs-abs-dvec3.htm > > > l > > > > piglit: error: waffle_display_connect failed due to > > WAFFLE_ERROR_UNKNOWN: open drm file for gbm failed > > > > Seems to be a problem with piglit opening the DRM file handle on this new > > machine; the Xe_HP SDV and DG2 patches here wouldn't have affected the > > behavior of SNB. > > > > Series applies to drm-intel-gt-next. Thanks Clint and Anusha for the > > reviews. > > > > > > Matt > > > > > > > > > > > New tests > > > - > > > > > > New tests have been introduced between CI_DRM_10830_full and > > > Patchwork_21509_full: > > > > > > ### New Piglit tests (24855) ### > > > > > > * fast_color_clear@all-colors: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.05] s > > > > > > * fast_color_clear@fast-slow-clear-interaction: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.06] s > > > > > > * fast_color_clear@fcc-blit-between-clears: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.04] s > > > > > > * fast_color_clear@fcc-read-after-clear blit rb: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.04] s > > > > > > * fast_color_clear@fcc-read-after-clear blit tex: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.05] s > > > > > > * fast_color_clear@fcc-read-after-clear copy rb: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.05] s > > > > > > * fast_color_clear@fcc-read-after-clear copy tex: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.04] s > > > > > > * fast_color_clear@fcc-read-after-clear read_pixels rb: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.04] s > > > > > > * fast_color_clear@fcc-read-after-clear read_pixels tex: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.07] s > > > > > > * fast_color_clear@fcc-read-after-clear sample tex: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.05] s > > > > > > * fast_color_clear@fcc-read-to-pbo-after-clear: > > > - Statuses : 1 fail(s) > > > - Exec time: [0.05] s > > > > > > * fast_color_clear@non-redundant-clear: > > > - Statuses : 1
Re: [Intel-gfx] [PATCH V3] drm/i915/gt: Hold RPM wakelock during PXP suspend
Hi Tejas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-2022]
[cannot apply to v5.15]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Tejas-Upadhyay/drm-i915-gt-Hold-RPM-wakelock-during-PXP-suspend/2021-204949
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-defconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/c134397c55fb3639fdcea780a83fd5f5402c93de
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Tejas-Upadhyay/drm-i915-gt-Hold-RPM-wakelock-during-PXP-suspend/2021-204949
git checkout c134397c55fb3639fdcea780a83fd5f5402c93de
# save the attached .config to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/intel_gt_pm.c: In function
'intel_gt_suspend_prepare':
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c:304:2: error: too few arguments to
>> function 'intel_pxp_suspend_prepare'
304 | intel_pxp_suspend_prepare(>->pxp);
| ^
In file included from drivers/gpu/drm/i915/gt/intel_gt_pm.c:21:
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h:17:20: note: declared here
17 | static inline void intel_pxp_suspend_prepare(struct intel_pxp *pxp,
bool runtime)
|^
vim +/intel_pxp_suspend_prepare +304 drivers/gpu/drm/i915/gt/intel_gt_pm.c
298
299 void intel_gt_suspend_prepare(struct intel_gt *gt)
300 {
301 user_forcewake(gt, true);
302 wait_for_suspend(gt);
303
> 304 intel_pxp_suspend_prepare(>->pxp);
305 }
306
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
[Intel-gfx] ✓ Fi.CI.BAT: success for ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
== Series Details ==
Series: ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
URL : https://patchwork.freedesktop.org/series/96784/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10875 -> Patchwork_21571
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/index.html
Participating hosts (28 -> 25)
--
Additional (1): fi-tgl-dsi
Missing(4): fi-bsw-cyan fi-pnv-d510 bat-dg1-6 bat-dg1-5
Known issues
Here are the changes found in Patchwork_21571 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2] ([i915#2940])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][3] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][4] ([i915#4269]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
Build changes
-
* Linux: CI_DRM_10875 -> Patchwork_21571
CI-20190529: 20190529
CI_DRM_10875: f73b8d83650f7b8278b0e166e1aba1024eed4e2e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21571: 3d6b0b3ff97c899765d050664162891d13e95183 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3d6b0b3ff97c ALSA: hda: fix general protection fault in azx_runtime_idle
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/index.html
Re: [Intel-gfx] [PATCH 09/17] drm/i915/fbc: Introduce .program_cfb() vfunc
On Thu, 04 Nov 2021, Ville Syrjala wrote:
> +static void i8xx_fbc_program_cfb(struct drm_i915_private *i915)
> +{
> + struct intel_fbc *fbc = &i915->fbc;
> +
> + GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
> + fbc->compressed_fb.start, U32_MAX));
> + GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
> + fbc->compressed_llb.start, U32_MAX));
This is just code movement, but why are we adding GEM_BUG_ON() stuff in
display?
If the macro is useful beyond gem, it should be called something
else. If not, it should not be used in display.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds
On Tue, Nov 02, 2021 at 03:25:10PM -0700, Matt Roper wrote:
> Bspec: 54077,68173,54833
> Cc: Anusha Srivatsa
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 278 +++-
> drivers/gpu/drm/i915/i915_reg.h | 94 +--
> drivers/gpu/drm/i915/intel_pm.c | 21 +-
> 3 files changed, 372 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4aaa210fc003..37fd541a9719 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
>DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> }
>
> +static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> + struct i915_wa_list *wal)
> +{
> + gen12_ctx_gt_tuning_init(engine, wal);
> +
> + /* Wa_16011186671:dg2_g11 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
> + wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
> + wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010469329:dg2_g10 */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> +
> + /*
> + * Wa_22010465075:dg2_g10
> + * Wa_22010613112:dg2_g10
> + * Wa_14010698770:dg2_g10
> + */
> + wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> + }
> +
> + /* Wa_16013271637:dg2 */
> + wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> + MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> +
> + /* Wa_22012532006:dg2 */
> + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
> + IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
> + wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
> + DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> +}
> +
> static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
>struct i915_wa_list *wal)
> {
> @@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> if (engine->class != RENDER_CLASS)
> goto done;
>
> - if (IS_XEHPSDV(i915))
> + if (IS_DG2(i915))
> + dg2_ctx_workarounds_init(engine, wal);
> + else if (IS_XEHPSDV(i915))
> ; /* noop; none at this time */
> else if (IS_DG1(i915))
> dg1_ctx_workarounds_init(engine, wal);
> @@ -1343,12 +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> GLOBAL_INVALIDATION_MODE);
> }
>
> +static void
> +dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> +{
> + struct intel_engine_cs *engine;
> + int id;
> +
> + xehp_init_mcr(gt, wal);
> +
> + /* Wa_14011060649:dg2 */
> + wa_14011060649(gt, wal);
> +
> + /*
> + * Although there are per-engine instances of these registers,
> + * they technically exist outside the engine itself and are not
> + * impacted by engine resets. Furthermore, they're part of the
> + * GuC blacklist so trying to treat them as engine workarounds
> + * will result in GuC initialization failure and a wedged GPU.
> + */
> + for_each_engine(engine, gt, id) {
> + if (engine->class != VIDEO_DECODE_CLASS)
> + continue;
> +
> + /* Wa_16010515920:dg2_g10 */
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
> + wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base),
> + ALNUNIT_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_G10(gt->i915)) {
> + /* Wa_22010523718:dg2 */
> + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> + CG3DDISCFEG_CLKGATE_DIS);
> +
> + /* Wa_14011006942:dg2 */
> + wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> + DSS_ROUTER_CLKGATE_DIS);
> + }
> +
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
> + /* Wa_14010680813:dg2_g10 */
> + wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS |
> + EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS);
> +
> + /* Wa_14010948348:dg2_g10 */
> + wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
> +
> + /* Wa_14011037102:dg2_g10 */
> + wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
> +
> + /* Wa_14011371254:
[Intel-gfx] [PATCH v2] drm/i915/selftest: Disable IRQ for timestamp calculation
gt_pm selftest calculates engine ticks cycles and wall time
cycles by delta of respective engine elapsed TIMESTAMP and ktime
for period of 1000us.
It compares the engine ticks cycles with wall time cycles.
Disable local cpu interrupt so that interrupt handler does not
switch out the thread during measure_clocks() and prevent
miscalculation of engine tick cycles.
Suggested-by: Chris P Wilson
Signed-off-by: Anshuman Gupta
Reviewed-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index b9441217ca3d..4c4953044548 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -40,9 +40,11 @@ static void measure_clocks(struct intel_engine_cs *engine,
{
ktime_t dt[5];
u32 cycles[5];
+ unsigned long flags;
int i;
for (i = 0; i < 5; i++) {
+ local_irq_save(flags);
preempt_disable();
cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP);
dt[i] = ktime_get();
@@ -52,6 +54,7 @@ static void measure_clocks(struct intel_engine_cs *engine,
dt[i] = ktime_sub(ktime_get(), dt[i]);
cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP);
preempt_enable();
+ local_irq_restore(flags);
}
/* Use the median of both cycle/dt; close enough */
--
2.26.2
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/selftest: Disable IRQ for timestamp calculation
== Series Details == Series: drm/i915/selftest: Disable IRQ for timestamp calculation URL : https://patchwork.freedesktop.org/series/96853/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/pmu: Increase the live_engine_busy_stats sample period
== Series Details ==
Series: drm/i915/pmu: Increase the live_engine_busy_stats sample period
URL : https://patchwork.freedesktop.org/series/96840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10872_full -> Patchwork_21568_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_21568_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21568_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21568_full:
### IGT changes ###
Warnings
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-tglb: [SKIP][1] ([fdo#111615]) -> [SKIP][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-tglb5/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-tglb8/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- {shard-rkl}:[SKIP][3] ([i915#1845]) -> [SKIP][4] +2 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-rkl-1/igt@kms_big...@yf-tiled-16bpp-rotate-270.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-rkl-6/igt@kms_big...@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- {shard-rkl}:[SKIP][5] ([fdo#111615]) -> [SKIP][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-rkl-6/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-rkl-6/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
Known issues
Here are the changes found in Patchwork_21568_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#1839])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-tglb8/igt@feature_discov...@display-3x.html
* igt@gem_ctx_persistence@smoketest:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2896])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-tglb7/igt@gem_ctx_persiste...@smoketest.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-tglb1/igt@gem_ctx_persiste...@smoketest.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][10] ([i915#2369])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-skl9/igt@gem_exec_capture@p...@bcs0.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#2842])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-tglb2/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +5
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-kbl7/igt@gem_exec_susp...@basic-s3.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-kbl4/igt@gem_exec_susp...@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#118])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10872/shard-glk1/igt@gem_exec_whis...@basic-contexts-all.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21568/shard-glk5/igt@gem_exec_whis...@basic-contexts-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][20] -> [SKIP][
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Add initial gt/ctx/engine workarounds
This issue was not catched by CI, because of series of unfortunate events.
Before, CI has rebooted without module blocklist, and CI catched boot-time
dmesg correctly and marked it as 'ci@boot' test with failure if there was a
taint.
I've been doing changes to make blocklisting i915 possible and load it as
the first test of IGT: that'd make possible to remove some workarounds
and integrate the result better on our framework.
The test to decide if i915 should be modprobed was slightly off, and
on these runs where i915 failed to load in boot, it was modprobed again,
and modprobe hanged because of existing i915. Results were not collected.
I've added the condition to the conditional modprobe, and the results
from failed boot-time modprobe should be soon available as before,
eg. CI_DRM_10873 later shards with SNB.
Regards,
Tomi
> From: Latvala, Petri
> On Tue, Nov 02, 2021 at 03:25:10PM -0700, Matt Roper wrote:
> > Bspec: 54077,68173,54833
> > Cc: Anusha Srivatsa
> > Signed-off-by: Matt Roper
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 278
> +++-
> > drivers/gpu/drm/i915/i915_reg.h | 94 +--
> > drivers/gpu/drm/i915/intel_pm.c | 21 +-
> > 3 files changed, 372 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 4aaa210fc003..37fd541a9719 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -644,6 +644,42 @@ static void dg1_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> >
> DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
> > }
> >
> > +static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > +struct
> i915_wa_list *wal)
> > +{
> > + gen12_ctx_gt_tuning_init(engine, wal);
> > +
> > + /* Wa_16011186671:dg2_g11 */
> > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0,
> STEP_B0)) {
> > + wa_masked_dis(wal, VFLSKPD,
> DIS_MULT_MISS_RD_SQUASH);
> > + wa_masked_en(wal, VFLSKPD,
> DIS_OVER_FETCH_CACHE);
> > + }
> > +
> > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0,
> STEP_B0)) {
> > + /* Wa_14010469329:dg2_g10 */
> > + wa_masked_en(wal,
> GEN11_COMMON_SLICE_CHICKEN3,
> > +
> XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> > +
> > + /*
> > +* Wa_22010465075:dg2_g10
> > +* Wa_22010613112:dg2_g10
> > +* Wa_14010698770:dg2_g10
> > +*/
> > + wa_masked_en(wal,
> GEN11_COMMON_SLICE_CHICKEN3,
> > +
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > + }
> > +
> > + /* Wa_16013271637:dg2 */
> > + wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> > +
> MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> > +
> > + /* Wa_22012532006:dg2 */
> > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0,
> STEP_C0) ||
> > + IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0,
> STEP_B0))
> > + wa_masked_en(wal,
> GEN9_HALF_SLICE_CHICKEN7,
> > +
> DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> > +}
> > +
> > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs
> *engine,
> >
> struct i915_wa_list *wal)
> > {
> > @@ -730,7 +766,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs
> *engine,
> > if (engine->class != RENDER_CLASS)
> > goto done;
> >
> > - if (IS_XEHPSDV(i915))
> > + if (IS_DG2(i915))
> > + dg2_ctx_workarounds_init(engine, wal);
> > + else if (IS_XEHPSDV(i915))
> > ; /* noop; none at this time */
> > else if (IS_DG1(i915))
> > dg1_ctx_workarounds_init(engine, wal);
> > @@ -1343,12 +1381,117 @@ xehpsdv_gt_workarounds_init(struct intel_gt
> *gt, struct i915_wa_list *wal)
> > GLOBAL_INVALIDATION_MODE);
> > }
> >
> > +static void
> > +dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > +{
> > + struct intel_engine_cs *engine;
> > + int id;
> > +
> > + xehp_init_mcr(gt, wal);
> > +
> > + /* Wa_14011060649:dg2 */
> > + wa_14011060649(gt, wal);
> > +
> > + /*
> > +* Although there are per-engine instances of these registers,
> > +* they technically exist outside the engine itself and are not
> > +* impacted by engine resets. Furthermore, they're part of the
> > +* GuC blacklist so trying to treat them as engine workarounds
> > +* will result in GuC initialization failure and a wedged GPU.
> > +*/
> > + for_each_engine(engine, gt, id) {
> > + if (engine->class != VIDEO_DECODE_CLASS)
> > + continue;
> > +
> > + /* Wa_16010515920:dg2_g10 */
> > + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10,
> STEP_A0, STEP_B0))
> > + wa_write_or(wal,
> VDBOX_CGCTL3F18(engine->mmio_base),
> > +
> ALNUNIT_CLKGATE_DIS);
> > + }
> > +
> > + if (IS_DG2_G10(gt->i915)) {
> > + /* Wa_22010523718:dg2 */
> > + wa_writ
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/ttm: Async migration (rev3)
== Series Details == Series: drm/i915/ttm: Async migration (rev3) URL : https://patchwork.freedesktop.org/series/96798/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1399:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/ttm: Async migration (rev3)
== Series Details == Series: drm/i915/ttm: Async migration (rev3) URL : https://patchwork.freedesktop.org/series/96798/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftest: Disable IRQ for timestamp calculation
== Series Details == Series: drm/i915/selftest: Disable IRQ for timestamp calculation URL : https://patchwork.freedesktop.org/series/96853/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10875 -> Patchwork_21572 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21572 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21572, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/index.html Participating hosts (28 -> 32) -- Additional (9): fi-bxt-dsi fi-rkl-11600 fi-tgl-dsi fi-tgl-u2 fi-bwr-2160 fi-ilk-650 fi-ivb-3770 fi-elk-e7500 fi-snb-2600 Missing(5): fi-kbl-soraka bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21572: ### IGT changes ### Possible regressions * igt@runner@aborted: - fi-bwr-2160:NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-bwr-2160/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_21572 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4006]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@gem_exec_suspend@basic-s3: - fi-tgl-u2: NOTRUN -> [FAIL][4] ([i915#1888]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html - fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html - fi-bxt-dsi: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#3282]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#3012]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-skl-6600u: [PASS][10] -> [FAIL][11] ([i915#3239]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-skl-6600u/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][12] -> [INCOMPLETE][13] ([i915#4432]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-bxt-dsi: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@dp-hpd-fast: - fi-tgl-u2: NOTRUN -> [SKIP][16] ([fdo#109284] / [fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915#4103]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21572/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-tgl-u2: NOTRUN -> [SKIP][18] ([i915#4103]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_2157
Re: [Intel-gfx] [PATCH] ALSA: hda: fix general protection fault in azx_runtime_idle
Hi,
On Fri, 12 Nov 2021, Takashi Iwai wrote:
> On Thu, 11 Nov 2021 18:39:36 +0100, Kai Vehmanen wrote:
> > And later
> > [ 54.770701] Enabling runtime PM for inactive device (:00:1f.3) with
> > active children
> > [ 54.770718] WARNING: CPU: 0 PID: 10 at drivers/base/power/runtime.c:1439
> > pm_runtime_enable+0x98/0xb0
> >
> > Adding a "pm_runtime_set_active(&pci->dev)" to both azx_free() and
> > azx_probe_continue() seems to help and fix still works.
>
> Ah yes, I was confused as if it were already called in hdac_device.c,
> but this was about the HD-audio bus controller, not the codec.
>
> Below is the revised one.
[...]
> Currently we haven't explicitly enable and allow/forbid the runtime PM
> at the probe and the remove phases of HD-audio controller driver, and
> this was the reason of a GPF mentioned in the commit e81478bbe7a1
> ("ALSA: hda: fix general protection fault in azx_runtime_idle");
> namely, even after the resources are released, the runtime PM might be
> still invoked by the bound graphics driver during the remove of the
> controller driver. Although we've fixed it by clearing the drvdata
> reference, it'd be also better to cover the runtime PM issue more
> properly.
>
> This patch adds a few more pm_runtime_*() calls at the probe and the
> remove time for setting and cleaning up the runtime PM. Particularly,
> now more explicitly pm_runtime_enable() and _disable() get called as
> well as pm_runtime_forbid() call at the remove callback, so that a
> use-after-free should be avoided.
>
> Reported-by: Kai Vehmanen
> Signed-off-by: Takashi Iwai
ack, tested this and no warnings anymore.
Reviewed-by: Kai Vehmanen
Tested-by: Kai Vehmanen
Br, Kai
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/ttm: Async migration (rev3)
== Series Details ==
Series: drm/i915/ttm: Async migration (rev3)
URL : https://patchwork.freedesktop.org/series/96798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10875 -> Patchwork_21573
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21573 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21573, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/index.html
Participating hosts (28 -> 33)
--
Additional (8): fi-bxt-dsi fi-rkl-11600 fi-tgl-dsi fi-bwr-2160 fi-ilk-650
fi-ivb-3770 fi-elk-e7500 fi-snb-2600
Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_21573:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-bwr-2160:NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-bwr-2160/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-hsw-4770/igt@run...@aborted.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-hsw-gt1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-hsw-gt1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_21573 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@amdgpu/amd_cs_...@sync-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#2190])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html
- fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#3282])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([i915#3012])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bxt-dsi: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-dsi: NOTRUN -> [SKIP][12] ([fdo#109271]) +30 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html
- fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#533])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-bxt-dsi: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-bxt-dsi/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21573/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915
[Intel-gfx] ✓ Fi.CI.IGT: success for i915: Additional DG2 workarounds (rev2)
== Series Details ==
Series: i915: Additional DG2 workarounds (rev2)
URL : https://patchwork.freedesktop.org/series/96824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10873_full -> Patchwork_21569_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (12 -> 11)
--
Missing(1): pig-snb-2600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21569_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- {shard-rkl}:[SKIP][1] ([i915#1845]) -> [SKIP][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-rkl-1/igt@kms_big...@yf-tiled-16bpp-rotate-270.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-rkl-6/igt@kms_big...@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- {shard-rkl}:NOTRUN -> ([SKIP][3], [SKIP][4]) ([i915#1845])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-rkl-6/igt@kms_big...@yf-tiled-64bpp-rotate-0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-rkl-4/igt@kms_big...@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- {shard-rkl}:([SKIP][5], [SKIP][6]) ([i915#1845]) -> [SKIP][7] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-rkl-1/igt@kms_big...@yf-tiled-8bpp-rotate-270.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-rkl-4/igt@kms_big...@yf-tiled-8bpp-rotate-270.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-rkl-6/igt@kms_big...@yf-tiled-8bpp-rotate-270.html
Known issues
Here are the changes found in Patchwork_21569_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#280])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-tglb2/igt@gem_ctx_s...@invalid-args.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#2481]
/ [i915#3070])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-iclb2/igt@gem_...@unwedge-stress.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-iclb5/igt@gem_...@unwedge-stress.html
* igt@gem_exec_capture@pi@vcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][11] ([i915#2369])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-skl8/igt@gem_exec_capture@p...@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][12] ([i915#2846])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-skl9/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar
issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-tglb3/igt@gem_exec_fair@basic-f...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#2842])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-tglb1/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-kbl4/igt@gem_exec_fair@basic-n...@vcs1.html
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2842])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-glk6/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][21] ([i915#2658]) +1 similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-skl1/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][22] ([i915#4270])
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21569/shard-iclb4/igt@gem_...@create-protected-buffer
[Intel-gfx] [PATCH] drm/i915: Skip remap_io_mapping() for non-x86 platforms
From: "Mullati, Siva"
The _PAGE_CACHE_MASK macro is not defined in non-x86
architectures and it's been used in remap_io_mapping().
Only hw that supports mappable aperture would hit this path
remap_io_mapping(), So skip this code for non-x86 architectures.
Signed-off-by: Mullati, Siva
---
drivers/gpu/drm/i915/i915_mm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 666808cb3a32..5e2a1868b957 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -91,6 +91,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap)
{
+#if defined(CONFIG_X86)
struct remap_pfn r;
int err;
@@ -108,6 +109,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
return err;
}
+#endif
return 0;
}
--
2.33.0
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc/slpc: Check GuC status before freq boost
== Series Details ==
Series: drm/i915/guc/slpc: Check GuC status before freq boost
URL : https://patchwork.freedesktop.org/series/96844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10873_full -> Patchwork_21570_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (12 -> 11)
--
Missing(1): pig-snb-2600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21570_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- {shard-rkl}:NOTRUN -> [SKIP][1] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-rkl-6/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
Known issues
Here are the changes found in Patchwork_21570_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +3 similar
issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-apl2/igt@gem_ctx_isolation@preservation...@bcs0.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-apl2/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#180]) +2 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-kbl7/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#280])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-tglb8/igt@gem_ctx_s...@invalid-args.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#2481]
/ [i915#3070])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-iclb2/igt@gem_...@unwedge-stress.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-iclb4/igt@gem_...@unwedge-stress.html
* igt@gem_exec_capture@pi@vecs0:
- shard-skl: NOTRUN -> [INCOMPLETE][8] ([i915#198] / [i915#2369])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-skl1/igt@gem_exec_capture@p...@vecs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][9] ([i915#2846])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-skl10/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-glk2/igt@gem_exec_fair@basic-throt...@rcs0.html
* igt@gem_exec_schedule@independent@vecs0:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10873/shard-skl9/igt@gem_exec_schedule@independ...@vecs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-skl9/igt@gem_exec_schedule@independ...@vecs0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][15] ([i915#2658]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-skl8/igt@gem_pwr...@basic-exhaustion.html
* igt@gem_pxp@create-protected-buffer:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-iclb3/igt@gem_...@create-protected-buffer.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-iclb3/igt@gem_render_c...@y-tiled-mc-ccs-to-yf-tiled-ccs.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][18] ([i915#3318])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-kbl3/igt@gem_userptr_bl...@vma-merge.html
- shard-skl: NOTRUN -> [FAIL][19] ([i915#3318])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21570/shard-skl6/igt@gem_userptr_bl...@vma-merge.html
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4387])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21
Re: [Intel-gfx] [PATCH] drm/i915: Use per device iommu check
On 12/11/2021 00:53, Lu Baolu wrote:
On 11/11/21 11:06 PM, Tvrtko Ursulin wrote:
On 10/11/2021 12:35, Lu Baolu wrote:
On 2021/11/10 20:08, Tvrtko Ursulin wrote:
On 10/11/2021 12:04, Lu Baolu wrote:
On 2021/11/10 17:30, Tvrtko Ursulin wrote:
On 10/11/2021 07:12, Lu Baolu wrote:
Hi Tvrtko,
On 2021/11/9 20:17, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On igfx + dgfx setups, it appears that intel_iommu=igfx_off
option only
disables the igfx iommu. Stop relying on global
intel_iommu_gfx_mapped
and probe presence of iommu domain per device to accurately
reflect its
status.
Signed-off-by: Tvrtko Ursulin
Cc: Lu Baolu
---
Baolu, is my understanding here correct? Maybe I am confused by
both
intel_iommu_gfx_mapped and dmar_map_gfx being globals in the
intel_iommu
driver. But it certainly appears the setup can assign some iommu
ops (and
assign the discrete i915 to iommu group) when those two are set
to off.
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index e967cd08f23e..9fb38a54f1fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1763,26 +1763,27 @@ static inline bool run_as_guest(void)
#define HAS_D12_PLANE_MINIMIZATION(dev_priv)
(IS_ROCKETLAKE(dev_priv) || \
IS_ALDERLAKE_S(dev_priv))
-static inline bool intel_vtd_active(void)
+static inline bool intel_vtd_active(struct drm_i915_private *i915)
{
-#ifdef CONFIG_INTEL_IOMMU
- if (intel_iommu_gfx_mapped)
+ if (iommu_get_domain_for_dev(i915->drm.dev))
return true;
-#endif
/* Running as a guest, we assume the host is enforcing VT'd */
return run_as_guest();
}
Have you verified this change? I am afraid that
iommu_get_domain_for_dev() always gets a valid iommu domain even
intel_iommu_gfx_mapped == 0.
Yes it seems to work as is:
default:
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: enabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: enabled
intel_iommu=igfx_off:
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: disabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: enabled
On my system dri device 0 is integrated graphics and 1 is discrete.
The drm device 0 has a dedicated iommu. When the user request igfx not
mapped, the VT-d implementation will turn it off to save power. But
for
shared iommu, you definitely will get it enabled.
Sorry I am not following, what exactly do you mean? Is there a
platform with integrated graphics without a dedicated iommu, in
which case intel_iommu=igfx_off results in intel_iommu_gfx_mapped ==
0 and iommu_get_domain_for_dev returning non-NULL?
Your code always work for an igfx with a dedicated iommu. This might be
always true on today's platforms. But from driver's point of view, we
should not make such assumption.
For example, if the iommu implementation decides not to turn off the
graphic iommu (perhaps due to some hw quirk or for graphic
virtualization), your code will be broken.
I tried your suggestion (checking for __IOMMU_DOMAIN_PAGING) and it
works better, however I have observed one odd behaviour (for me at
least).
In short - why does the DMAR mode for the discrete device change
depending on igfx_off parameter?
Consider the laptop has these two graphics cards:
# cat /sys/kernel/debug/dri/0/name
i915 dev=:00:02.0 unique=:00:02.0 # integrated
# cat /sys/kernel/debug/dri/1/name
i915 dev=:03:00.0 unique=:03:00.0 # discrete
Booting with different options:
===
default / intel_iommu=on
# cat /sys/class/iommu/dmar0/devices/:00:02.0/iommu_group/type
DMA-FQ
# cat /sys/class/iommu/dmar2/devices/:03:00.0/iommu_group/type
DMA-FQ
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: enabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: enabled
All good.
intel_iommu=igfx_off
## no dmar0 in sysfs
# cat /sys/class/iommu/dmar2/devices/:03:00.0/iommu_group/type
identity
Unexpected!?
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: disabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: disabled # At least
the i915 patch detects it correctly.
intel_iommu=off
---
## no dmar0 in sysfs
## no dmar2 in sysfs
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: disabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: disabled
All good.
The fact discrete graphics changes from translated to pass-through
when igfx_off is set is surprising to me. Is this a bug?
The existing VT-d implementation doesn't distinguish igfx from dgfx. It
only checks whether the device is of a display class:
#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLA
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Skip remap_io_mapping() for non-x86 platforms
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms URL : https://patchwork.freedesktop.org/series/96855/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH][next] drm/i915: make array states static const
On Wed, 15 Sep 2021, Colin King wrote:
> From: Colin Ian King
>
> Don't populate the read-only array states on the stack but instead it
> static. Also makes the object code smaller.
Finally pushed, sorry for the delay.
BR,
Jani.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cce1a926fcc1..a60710348613 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -893,7 +893,7 @@ static u32
> sanitize_target_dc_state(struct drm_i915_private *dev_priv,
>u32 target_dc_state)
> {
> - u32 states[] = {
> + static const u32 states[] = {
> DC_STATE_EN_UPTO_DC6,
> DC_STATE_EN_UPTO_DC5,
> DC_STATE_EN_DC3CO,
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915: Skip remap_io_mapping() for non-x86 platforms
On Fri, 12 Nov 2021, Mullati Siva wrote:
> From: "Mullati, Siva"
>
> The _PAGE_CACHE_MASK macro is not defined in non-x86
> architectures and it's been used in remap_io_mapping().
> Only hw that supports mappable aperture would hit this path
> remap_io_mapping(), So skip this code for non-x86 architectures.
>
> Signed-off-by: Mullati, Siva
> ---
> drivers/gpu/drm/i915/i915_mm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
> index 666808cb3a32..5e2a1868b957 100644
> --- a/drivers/gpu/drm/i915/i915_mm.c
> +++ b/drivers/gpu/drm/i915/i915_mm.c
> @@ -91,6 +91,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
>unsigned long addr, unsigned long pfn, unsigned long size,
>struct io_mapping *iomap)
> {
> +#if defined(CONFIG_X86)
Please don't add conditional compilation within functions. Please use
#if IS_ENABLED() instead of #if defined or #ifdef.
BR,
Jani.
> struct remap_pfn r;
> int err;
>
> @@ -108,6 +109,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
> zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
> return err;
> }
> +#endif
>
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915: Use per device iommu check
On 12/11/2021 00:58, Lu Baolu wrote:
On 11/11/21 11:18 PM, Tvrtko Ursulin wrote:
On 10/11/2021 14:37, Robin Murphy wrote:
On 2021-11-10 14:11, Tvrtko Ursulin wrote:
On 10/11/2021 12:35, Lu Baolu wrote:
On 2021/11/10 20:08, Tvrtko Ursulin wrote:
On 10/11/2021 12:04, Lu Baolu wrote:
On 2021/11/10 17:30, Tvrtko Ursulin wrote:
On 10/11/2021 07:12, Lu Baolu wrote:
Hi Tvrtko,
On 2021/11/9 20:17, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
On igfx + dgfx setups, it appears that intel_iommu=igfx_off
option only
disables the igfx iommu. Stop relying on global
intel_iommu_gfx_mapped
and probe presence of iommu domain per device to accurately
reflect its
status.
Signed-off-by: Tvrtko Ursulin
Cc: Lu Baolu
---
Baolu, is my understanding here correct? Maybe I am confused
by both
intel_iommu_gfx_mapped and dmar_map_gfx being globals in the
intel_iommu
driver. But it certainly appears the setup can assign some
iommu ops (and
assign the discrete i915 to iommu group) when those two are
set to off.
diff --git a/drivers/gpu/drm/i915/i915_drv.h
b/drivers/gpu/drm/i915/i915_drv.h
index e967cd08f23e..9fb38a54f1fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1763,26 +1763,27 @@ static inline bool run_as_guest(void)
#define HAS_D12_PLANE_MINIMIZATION(dev_priv)
(IS_ROCKETLAKE(dev_priv) || \
IS_ALDERLAKE_S(dev_priv))
-static inline bool intel_vtd_active(void)
+static inline bool intel_vtd_active(struct drm_i915_private
*i915)
{
-#ifdef CONFIG_INTEL_IOMMU
- if (intel_iommu_gfx_mapped)
+ if (iommu_get_domain_for_dev(i915->drm.dev))
return true;
-#endif
/* Running as a guest, we assume the host is enforcing
VT'd */
return run_as_guest();
}
Have you verified this change? I am afraid that
iommu_get_domain_for_dev() always gets a valid iommu domain even
intel_iommu_gfx_mapped == 0.
Yes it seems to work as is:
default:
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: enabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: enabled
intel_iommu=igfx_off:
# grep -i iommu /sys/kernel/debug/dri/*/i915_capabilities
/sys/kernel/debug/dri/0/i915_capabilities:iommu: disabled
/sys/kernel/debug/dri/1/i915_capabilities:iommu: enabled
On my system dri device 0 is integrated graphics and 1 is discrete.
The drm device 0 has a dedicated iommu. When the user request
igfx not
mapped, the VT-d implementation will turn it off to save power.
But for
shared iommu, you definitely will get it enabled.
Sorry I am not following, what exactly do you mean? Is there a
platform with integrated graphics without a dedicated iommu, in
which case intel_iommu=igfx_off results in intel_iommu_gfx_mapped
== 0 and iommu_get_domain_for_dev returning non-NULL?
Your code always work for an igfx with a dedicated iommu. This
might be
always true on today's platforms. But from driver's point of view, we
should not make such assumption.
For example, if the iommu implementation decides not to turn off the
graphic iommu (perhaps due to some hw quirk or for graphic
virtualization), your code will be broken.
If I got it right, this would go back to your earlier recommendation
to have the check look like this:
static bool intel_vtd_active(struct drm_i915_private *i915)
{
struct iommu_domain *domain;
domain = iommu_get_domain_for_dev(i915->drm.dev);
if (domain && (domain->type & __IOMMU_DOMAIN_PAGING))
return true;
...
This would be okay as a first step?
Elsewhere in the thread Robin suggested looking at the dec->dma_ops
and comparing against iommu_dma_ops. These two solution would be
effectively the same?
Effectively, yes. See iommu_setup_dma_ops() - the only way to end up
with iommu_dma_ops is if a managed translation domain is present; if
the IOMMU is present but the default domain type has been set to
passthrough (either globally or forced for the given device) it will
do nothing and leave you with dma-direct, while if the IOMMU has been
ignored entirely then it should never even be called. Thus it neatly
encapsulates what you're after here.
One concern I have is whether the pass-through mode truly does nothing
or addresses perhaps still go through the dmar hardware just with no
translation?
Pass-through mode means the latter.
If latter then most like for like change is actually exactly what the
first version of my patch did. That is replace intel_iommu_gfx_mapped
with a plain non-NULL check on iommu_get_domain_for_dev.
Depends on what you want here,
#1) the graphic device works in iommu pass-through mode
- device have an iommu
- but iommu does no translation
- the dma transactions go through iommu with the same destination
memory address specified by the device;
Do you have any indications of the slowdown this adds?
#2) the graphic device works without a system iomm
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
On 11/11/2021 16:49, Matthew Brost wrote:
On Mon, Nov 01, 2021 at 10:35:09AM +, Tvrtko Ursulin wrote:
On 27/10/2021 21:10, Matthew Brost wrote:
On Wed, Oct 27, 2021 at 01:04:49PM -0700, John Harrison wrote:
On 10/27/2021 12:17, Matthew Brost wrote:
On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
On 10/20/2021 14:47, Matthew Brost wrote:
A weak implementation of parallel submission (multi-bb execbuf IOCTL) for
execlists. Doing as little as possible to support this interface for
execlists - basically just passing submit fences between each request
generated and virtual engines are not allowed. This is on par with what
is there for the existing (hopefully soon deprecated) bonding interface.
We perma-pin these execlists contexts to align with GuC implementation.
v2:
(John Harrison)
- Drop siblings array as num_siblings must be 1
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 44 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
5 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index fb33d0322960..35e87a7d0ea9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -570,10 +570,6 @@ set_proto_ctx_engines_parallel_submit(struct
i915_user_extension __user *base,
struct intel_engine_cs **siblings = NULL;
intel_engine_mask_t prev_mask;
- /* FIXME: This is NIY for execlists */
- if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
- return -ENODEV;
-
if (get_user(slot, &ext->engine_index))
return -EFAULT;
@@ -583,6 +579,12 @@ set_proto_ctx_engines_parallel_submit(struct
i915_user_extension __user *base,
if (get_user(num_siblings, &ext->num_siblings))
return -EFAULT;
+ if (!intel_uc_uses_guc_submission(&i915->gt.uc) && num_siblings != 1) {
+ drm_dbg(&i915->drm, "Only 1 sibling (%d) supported in non-GuC
mode\n",
+ num_siblings);
+ return -EINVAL;
+ }
+
if (slot >= set->num_engines) {
drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
slot, set->num_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5634d14052bc..1bec92e1d8e6 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -79,7 +79,8 @@ static int intel_context_active_acquire(struct intel_context
*ce)
__i915_active_acquire(&ce->active);
- if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine))
+ if (intel_context_is_barrier(ce) || intel_engine_uses_guc(ce->engine) ||
+ intel_context_is_parallel(ce))
return 0;
/* Preallocate tracking nodes */
@@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct intel_context
*parent,
* Callers responsibility to validate that this function is used
* correctly but we use GEM_BUG_ON here ensure that they do.
*/
- GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
GEM_BUG_ON(intel_context_is_pinned(parent));
GEM_BUG_ON(intel_context_is_child(parent));
GEM_BUG_ON(intel_context_is_pinned(child));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index bedb80057046..2865b422300d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -927,8 +927,7 @@ static void execlists_submit_ports(struct intel_engine_cs
*engine)
static bool ctx_single_port_submission(const struct intel_context *ce)
{
- return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
- intel_context_force_single_submission(ce));
+ return intel_context_force_single_submission(ce);
I think this is actually going to break GVT.
Not so much this change here but the whole use of single submission outside
of GVT. It looks like the GVT driver overloads the single submission flag to
tag requests that it owns. If we start using that flag elsewhere when GVT is
active, I think that will cause much confusion within the GVT code.
The correct fix would be to create a new flag just for GVT usage alongside
the single submission one. GVT would then set both but only check for its
own private flag. The parallel code would obviously only set the existing
single submission flag.
Ok, see below.
}
static bool can_merge_ctx(const struct intel_context *prev,
@@ -2598,6 +2597,46 @@ static void execlists_context_cancel_reques
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip remap_io_mapping() for non-x86 platforms
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms URL : https://patchwork.freedesktop.org/series/96855/ State : success == Summary == CI Bug Log - changes from CI_DRM_10875 -> Patchwork_21574 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/index.html Participating hosts (28 -> 32) -- Additional (8): fi-bxt-dsi fi-rkl-11600 fi-tgl-dsi fi-tgl-1115g4 fi-ilk-650 fi-ivb-3770 fi-elk-e7500 fi-snb-2600 Missing(4): fi-bsw-cyan fi-pnv-d510 bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21574 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html - fi-bxt-dsi: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-bxt-dsi/igt@gem_huc_c...@huc-copy.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_module_load@reload: - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/fi-bsw-kefka/igt@i915_module_l...@reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-bsw-kefka/igt@i915_module_l...@reload.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#1155]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html - fi-rkl-11600: NOTRUN -> [SKIP][11] ([i915#3012]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-bxt-dsi: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-bxt-dsi/igt@kms_chamel...@common-hpd-after-suspend.html - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@kms_chamel...@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#4103]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#4103]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-bxt-dsi: NOTRUN -> [SKIP][17] ([fdo#109271]) +30 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-bxt-dsi/igt@kms_force_connector_ba...@force-load-detect.html - fi-tgl-1115g4: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html - fi-rkl-11600: NOTRUN -> [SKIP][19] ([fdo#109285] / [i915#4098]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21574/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-rkl-11600: NOTRU
Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC
On Thu, Nov 11, 2021 at 03:02:04PM -0700, Jim Cromie wrote: > Sean Paul proposed, in: > https://patchwork.freedesktop.org/series/78133/ > drm/trace: Mirror DRM debug logs to tracefs > > His patchset's objective is to be able to independently steer some of > the drm.debug stream to an alternate tracing destination, by splitting > drm_debug_enabled() into syslog & trace flavors, and enabling them > separately. 2 advantages were identified: > > 1- syslog is heavyweight, tracefs is much lighter > 2- separate selection of enabled categories means less traffic > > Dynamic-Debug can do 2nd exceedingly well: > > A- all work is behind jump-label's NOOP, zero off cost. > B- exact site selectivity, precisely the useful traffic. >can tailor enabled set interactively, at shell. > > Since the tracefs interface is effective for drm (the threads suggest > so), adding that interface to dynamic-debug has real potential for > everyone including drm. > > if CONFIG_TRACING: > > Grab Sean's trace_init/cleanup code, use it to provide tracefs > available by default to all pr_debugs. This will likely need some > further per-module treatment; perhaps something reflecting hierarchy > of module,file,function,line, maybe with a tuned flattening. > > endif CONFIG_TRACING > > Add a new +T flag to enable tracing, independent of +p, and add and > use 3 macros: dyndbg_site_is_enabled/logging/tracing(), to encapsulate > the flag checks. Existing code treats T like other flags. I posted a patchset a while ago to do something very similar, but that got stalled for some reason and I unfortunately didn't follow it up: https://lore.kernel.org/lkml/20200825153338.17061-1-vincent.whitchu...@axis.com/ A key difference between that patchset and this patch (besides that small fact that I used +x instead of +T) was that my patchset allowed the dyndbg trace to be emitted to the main buffer and did not force them to be in an instance-specific buffer. That feature is quite important at least for my use case since I often use dyndbg combined with function tracing, and the latter doesn't work on non-main instances according to Documentation/trace/ftrace.rst. For example, here's a random example of a bootargs from one of my recent debugging sessions: trace_event=printk:* ftrace_filter=_mmc*,mmc*,sd*,dw_mci*,mci* ftrace=function trace_buf_size=20M dyndbg="file drivers/mmc/* +x"
Re: [Intel-gfx] [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range struct for HDR planes
On Thu, Nov 11, 2021 at 04:10:41PM -0500, Harry Wentland wrote:
>
>
> On 2021-11-11 15:42, Shankar, Uma wrote:
> >
> >
> >> -Original Message-
> >> From: Ville Syrjälä
> >> Sent: Thursday, November 11, 2021 10:13 PM
> >> To: Harry Wentland
> >> Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
> >> dri-
> >> de...@lists.freedesktop.org; ppaala...@gmail.com; brian.star...@arm.com;
> >> sebast...@sebastianwick.net; shashank.sha...@amd.com
> >> Subject: Re: [RFC v2 05/22] drm/i915/xelpd: Define Degamma Lut range
> >> struct for
> >> HDR planes
> >>
> >> On Thu, Nov 11, 2021 at 10:17:17AM -0500, Harry Wentland wrote:
> >>>
> >>>
> >>> On 2021-09-06 17:38, Uma Shankar wrote:
> Define the structure with XE_LPD degamma lut ranges. HDR and SDR
> planes have different capabilities, implemented respective structure
> for the HDR planes.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 52
> ++
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index afcb4bf3826c..6403bd74324b 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -2092,6 +2092,58 @@ static void icl_read_luts(struct intel_crtc_state
> >> *crtc_state)
> }
> }
>
> + /* FIXME input bpc? */
> +__maybe_unused
> +static const struct drm_color_lut_range d13_degamma_hdr[] = {
> +/* segment 1 */
> +{
> +.flags = (DRM_MODE_LUT_GAMMA |
> + DRM_MODE_LUT_REFLECT_NEGATIVE |
> + DRM_MODE_LUT_INTERPOLATE |
> + DRM_MODE_LUT_NON_DECREASING),
> +.count = 128,
> +.input_bpc = 24, .output_bpc = 16,
> +.start = 0, .end = (1 << 24) - 1,
> +.min = 0, .max = (1 << 24) - 1,
> +},
> +/* segment 2 */
> +{
> +.flags = (DRM_MODE_LUT_GAMMA |
> + DRM_MODE_LUT_REFLECT_NEGATIVE |
> + DRM_MODE_LUT_INTERPOLATE |
> + DRM_MODE_LUT_REUSE_LAST |
> + DRM_MODE_LUT_NON_DECREASING),
> +.count = 1,
> +.input_bpc = 24, .output_bpc = 16,
> +.start = (1 << 24) - 1, .end = 1 << 24,
> +.min = 0, .max = (1 << 27) - 1,
> +},
> +/* Segment 3 */
> +{
> +.flags = (DRM_MODE_LUT_GAMMA |
> + DRM_MODE_LUT_REFLECT_NEGATIVE |
> + DRM_MODE_LUT_INTERPOLATE |
> + DRM_MODE_LUT_REUSE_LAST |
> + DRM_MODE_LUT_NON_DECREASING),
> +.count = 1,
> +.input_bpc = 24, .output_bpc = 16,
> +.start = 1 << 24, .end = 3 << 24,
> +.min = 0, .max = (1 << 27) - 1,
> +},
> +/* Segment 4 */
> +{
> +.flags = (DRM_MODE_LUT_GAMMA |
> + DRM_MODE_LUT_REFLECT_NEGATIVE |
> + DRM_MODE_LUT_INTERPOLATE |
> + DRM_MODE_LUT_REUSE_LAST |
> + DRM_MODE_LUT_NON_DECREASING),
> +.count = 1,
> +.input_bpc = 24, .output_bpc = 16,
> +.start = 3 << 24, .end = 7 << 24,
> +.min = 0, .max = (1 << 27) - 1,
> +},
> +};
> >>>
> >>> If I understand this right, userspace would need this definition in
> >>> order to populate the degamma blob. Should this sit in a UAPI header?
> >
> > Hi Harry, Pekka and Ville,
> > Sorry for being a bit late on the replies, got side tracked with various
> > issues.
> > I am back on this. Apologies for delay.
> >
> >> My original idea (not sure it's fully realized in this series) is to have
> >> a new
> >> GAMMA_MODE/etc. enum property on each crtc (or plane) for which each enum
> >> value points to a kernel provided blob that contains one of these LUT
> >> descriptors.
> >> Userspace can then query them dynamically and pick the best one for its
> >> current use
> >> case.
> >
> > We have this as part of the series Ville. Patch 3 of this series creates a
> > DEGAMMA_MODE
> > property just for this. With that userspace can just query the blob_id's
> > and will get the
> > various degamma mode possible and the respective segment and lut
> > distributions.
> >
> > This will be generic, so for userspace it should just be able to query this
> > and parse and get
> > the lut di
[Intel-gfx] ✗ Fi.CI.IGT: failure for ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
== Series Details ==
Series: ALSA: hda: fix general protection fault in azx_runtime_idle (rev3)
URL : https://patchwork.freedesktop.org/series/96784/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10875_full -> Patchwork_21571_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_21571_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21571_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 12)
--
Additional (1): pig-snb-2600
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21571_full:
### IGT changes ###
Possible regressions
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglb: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-tglb6/igt@kms_big...@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_balancer@parallel-out-fence}:
- {shard-rkl}:NOTRUN -> [SKIP][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-rkl-6/igt@gem_exec_balan...@parallel-out-fence.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- {shard-rkl}:([SKIP][3], [SKIP][4]) ([i915#1845]) -> [SKIP][5]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-rkl-4/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-rkl-2/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-rkl-6/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- {shard-rkl}:[SKIP][6] ([i915#1845]) -> [SKIP][7] +1 similar issue
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-rkl-2/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-rkl-6/igt@kms_big...@yf-tiled-max-hw-stride-64bpp-rotate-0.html
Known issues
Here are the changes found in Patchwork_21571_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-glk8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-glk4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-kbl3/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109283])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-tglb3/igt@gem_exec_par...@rsvd2-dirt.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-kbl2/igt@gem_huc_c...@huc-copy.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][17] ([fdo#111656])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-tglb3/igt@gem_mmap_...@coherency.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4270]) +1 similar issue
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-tglb3/igt@gem_...@verify-pxp-stale-buf-execution.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21571/shard-skl6/igt@gem_userptr_bl...@dmabuf-sync.html
*
[Intel-gfx] [PATCH 5/6] drm/i915: Remove resv from i915_vma
From: Maarten Lankhorst
It's just an alias to vma->obj->base.resv, no need to duplicate it.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Niranjana Vishwanathapura
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/i915_vma.c| 9 -
drivers/gpu/drm/i915/i915_vma.h| 6 +++---
drivers/gpu/drm/i915/i915_vma_types.h | 1 -
4 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ea5b7b2a4d70..9f7c6ecadb90 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1001,7 +1001,7 @@ static int eb_validate_vmas(struct i915_execbuffer *eb)
}
if (!(ev->flags & EXEC_OBJECT_WRITE)) {
- err = dma_resv_reserve_shared(vma->resv, 1);
+ err = dma_resv_reserve_shared(vma->obj->base.resv, 1);
if (err)
return err;
}
@@ -2175,7 +2175,7 @@ static int eb_parse(struct i915_execbuffer *eb)
goto err_trampoline;
}
- err = dma_resv_reserve_shared(shadow->resv, 1);
+ err = dma_resv_reserve_shared(shadow->obj->base.resv, 1);
if (err)
goto err_trampoline;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index fd7594e3e7e7..72c373a170a1 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -116,7 +116,6 @@ vma_create(struct drm_i915_gem_object *obj,
vma->vm = i915_vm_get(vm);
vma->ops = &vm->vma_ops;
vma->obj = obj;
- vma->resv = obj->base.resv;
vma->size = obj->base.size;
vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
@@ -1032,7 +1031,7 @@ int i915_ggtt_pin(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
#ifdef CONFIG_LOCKDEP
- WARN_ON(!ww && dma_resv_held(vma->resv));
+ WARN_ON(!ww && dma_resv_held(vma->obj->base.resv));
#endif
do {
@@ -1251,19 +1250,19 @@ int _i915_vma_move_to_active(struct i915_vma *vma,
}
if (fence) {
- dma_resv_add_excl_fence(vma->resv, fence);
+ dma_resv_add_excl_fence(vma->obj->base.resv, fence);
obj->write_domain = I915_GEM_DOMAIN_RENDER;
obj->read_domains = 0;
}
} else {
if (!(flags & __EXEC_OBJECT_NO_RESERVE)) {
- err = dma_resv_reserve_shared(vma->resv, 1);
+ err = dma_resv_reserve_shared(vma->obj->base.resv, 1);
if (unlikely(err))
return err;
}
if (fence) {
- dma_resv_add_shared_fence(vma->resv, fence);
+ dma_resv_add_shared_fence(vma->obj->base.resv, fence);
obj->write_domain = 0;
}
}
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 312933c06017..4033aa08d5e4 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -234,16 +234,16 @@ static inline void __i915_vma_put(struct i915_vma *vma)
kref_put(&vma->ref, i915_vma_release);
}
-#define assert_vma_held(vma) dma_resv_assert_held((vma)->resv)
+#define assert_vma_held(vma) dma_resv_assert_held((vma)->obj->base.resv)
static inline void i915_vma_lock(struct i915_vma *vma)
{
- dma_resv_lock(vma->resv, NULL);
+ dma_resv_lock(vma->obj->base.resv, NULL);
}
static inline void i915_vma_unlock(struct i915_vma *vma)
{
- dma_resv_unlock(vma->resv);
+ dma_resv_unlock(vma->obj->base.resv);
}
int __must_check
diff --git a/drivers/gpu/drm/i915/i915_vma_types.h
b/drivers/gpu/drm/i915/i915_vma_types.h
index 4ee6e54799f4..f03fa96a1701 100644
--- a/drivers/gpu/drm/i915/i915_vma_types.h
+++ b/drivers/gpu/drm/i915/i915_vma_types.h
@@ -187,7 +187,6 @@ struct i915_vma {
const struct i915_vma_ops *ops;
struct drm_i915_gem_object *obj;
- struct dma_resv *resv; /** Alias of obj->resv */
struct sg_table *pages;
void __iomem *iomap;
--
2.31.1
[Intel-gfx] [PATCH 3/6] drm/i915: Create a full object for mock_ring, v2.
From: Maarten Lankhorst
This allows us to finally get rid of all the assumptions that vma->obj
is NULL.
Changes since v1:
- Ensure the mock_ring vma is pinned to prevent a fault.
- Pin it high to avoid failure in evict_for_vma selftest.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/mock_engine.c | 38 ---
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu/drm/i915/gt/mock_engine.c
index 8b89215afe46..bb99fc03f503 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -35,9 +35,31 @@ static void mock_timeline_unpin(struct intel_timeline *tl)
atomic_dec(&tl->pin_count);
}
+static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
+{
+ struct i915_address_space *vm = &ggtt->vm;
+ struct drm_i915_private *i915 = vm->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma))
+ goto err;
+
+ return vma;
+
+err:
+ i915_gem_object_put(obj);
+ return vma;
+}
+
static struct intel_ring *mock_ring(struct intel_engine_cs *engine)
{
- const unsigned long sz = PAGE_SIZE / 2;
+ const unsigned long sz = PAGE_SIZE;
struct intel_ring *ring;
ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL);
@@ -50,15 +72,11 @@ static struct intel_ring *mock_ring(struct intel_engine_cs
*engine)
ring->vaddr = (void *)(ring + 1);
atomic_set(&ring->pin_count, 1);
- ring->vma = i915_vma_alloc();
- if (!ring->vma) {
+ ring->vma = create_ring_vma(engine->gt->ggtt, PAGE_SIZE);
+ if (IS_ERR(ring->vma)) {
kfree(ring);
return NULL;
}
- i915_active_init(&ring->vma->active, NULL, NULL, 0);
- __set_bit(I915_VMA_GGTT_BIT, __i915_vma_flags(ring->vma));
- __set_bit(DRM_MM_NODE_ALLOCATED_BIT, &ring->vma->node.flags);
- ring->vma->node.size = sz;
intel_ring_update_space(ring);
@@ -67,8 +85,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs
*engine)
static void mock_ring_free(struct intel_ring *ring)
{
- i915_active_fini(&ring->vma->active);
- i915_vma_free(ring->vma);
+ i915_vma_put(ring->vma);
kfree(ring);
}
@@ -125,6 +142,7 @@ static void mock_context_unpin(struct intel_context *ce)
static void mock_context_post_unpin(struct intel_context *ce)
{
+ i915_vma_unpin(ce->ring->vma);
}
static void mock_context_destroy(struct kref *ref)
@@ -169,7 +187,7 @@ static int mock_context_alloc(struct intel_context *ce)
static int mock_context_pre_pin(struct intel_context *ce,
struct i915_gem_ww_ctx *ww, void **unused)
{
- return 0;
+ return i915_vma_pin_ww(ce->ring->vma, ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
}
static int mock_context_pin(struct intel_context *ce, void *unused)
--
2.31.1
[Intel-gfx] [PATCH 2/6] drm/i915: Create a dummy object for gen6 ppgtt
From: Maarten Lankhorst
We currently have to special case vma->obj being NULL because
of gen6 ppgtt and mock_engine. Fix gen6 ppgtt, so we may soon
be able to remove a few checks. As the object only exists as
a fake object pointing to ggtt, we have no backing storage,
so no real object is created. It just has to look real enough.
Also kill pin_mutex, it's not compatible with ww locking,
and we can use the vm lock instead.
v2:
- Drop IS_SHRINKABLE and shorten overly long line
v3:
- Checkpatch fix for alignment
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 44 ---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 123 +++
drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 1 -
drivers/gpu/drm/i915/i915_drv.h | 4 +
4 files changed, 100 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index a57a6b7013c2..c5150a1ee3d2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -145,24 +145,10 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_internal_ops = {
.put_pages = i915_gem_object_put_pages_internal,
};
-/**
- * i915_gem_object_create_internal: create an object with volatile pages
- * @i915: the i915 device
- * @size: the size in bytes of backing storage to allocate for the object
- *
- * Creates a new object that wraps some internal memory for private use.
- * This object is not backed by swappable storage, and as such its contents
- * are volatile and only valid whilst pinned. If the object is reaped by the
- * shrinker, its pages and data will be discarded. Equally, it is not a full
- * GEM object and so not valid for access from userspace. This makes it useful
- * for hardware interfaces like ringbuffers (which are pinned from the time
- * the request is written to the time the hardware stops accessing it), but
- * not for contexts (which need to be preserved when not active for later
- * reuse). Note that it is not cleared upon allocation.
- */
struct drm_i915_gem_object *
-i915_gem_object_create_internal(struct drm_i915_private *i915,
- phys_addr_t size)
+__i915_gem_object_create_internal(struct drm_i915_private *i915,
+ const struct drm_i915_gem_object_ops *ops,
+ phys_addr_t size)
{
static struct lock_class_key lock_class;
struct drm_i915_gem_object *obj;
@@ -179,7 +165,7 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class,
0);
+ i915_gem_object_init(obj, ops, &lock_class, 0);
obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
/*
@@ -199,3 +185,25 @@ i915_gem_object_create_internal(struct drm_i915_private
*i915,
return obj;
}
+
+/**
+ * i915_gem_object_create_internal: create an object with volatile pages
+ * @i915: the i915 device
+ * @size: the size in bytes of backing storage to allocate for the object
+ *
+ * Creates a new object that wraps some internal memory for private use.
+ * This object is not backed by swappable storage, and as such its contents
+ * are volatile and only valid whilst pinned. If the object is reaped by the
+ * shrinker, its pages and data will be discarded. Equally, it is not a full
+ * GEM object and so not valid for access from userspace. This makes it useful
+ * for hardware interfaces like ringbuffers (which are pinned from the time
+ * the request is written to the time the hardware stops accessing it), but
+ * not for contexts (which need to be preserved when not active for later
+ * reuse). Note that it is not cleared upon allocation.
+ */
+struct drm_i915_gem_object *
+i915_gem_object_create_internal(struct drm_i915_private *i915,
+ phys_addr_t size)
+{
+ return __i915_gem_object_create_internal(i915,
&i915_gem_object_internal_ops, size);
+}
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index ae693bf88ef0..4a166d25fe60 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -261,13 +261,10 @@ static void gen6_ppgtt_cleanup(struct i915_address_space
*vm)
{
struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
- __i915_vma_put(ppgtt->vma);
-
gen6_ppgtt_free_pd(ppgtt);
free_scratch(vm);
mutex_destroy(&ppgtt->flush);
- mutex_destroy(&ppgtt->pin_mutex);
free_pd(&ppgtt->base.vm, ppgtt->base.pd);
}
@@ -330,37 +327,6 @@ static const struct i915_vma_ops pd_vma_ops = {
.unbind_vma = pd_vma_unbind,
};
-static struct i915_vma *pd_vma_create
[Intel-gfx] [PATCH 4/6] drm/i915: vma is always backed by an object.
From: Maarten Lankhorst
vma->obj and vma->resv are now never NULL, and some checks can be removed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 48 ---
drivers/gpu/drm/i915/i915_vma.h | 3 --
4 files changed, 22 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ad44860faaf3..e31669657dae 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -219,7 +219,7 @@ int __intel_context_do_pin_ww(struct intel_context *ce,
*/
err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww);
- if (!err && ce->ring->vma->obj)
+ if (!err)
err = i915_gem_object_lock(ce->ring->vma->obj, ww);
if (!err && ce->state)
err = i915_gem_object_lock(ce->state->obj, ww);
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 586dca1731ce..3e6fac0340ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1357,7 +1357,7 @@ int intel_ring_submission_setup(struct intel_engine_cs
*engine)
err = i915_gem_object_lock(timeline->hwsp_ggtt->obj, &ww);
if (!err && gen7_wa_vma)
err = i915_gem_object_lock(gen7_wa_vma->obj, &ww);
- if (!err && engine->legacy.ring->vma->obj)
+ if (!err)
err = i915_gem_object_lock(engine->legacy.ring->vma->obj, &ww);
if (!err)
err = intel_timeline_pin(timeline, &ww);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 8781c4f61952..fd7594e3e7e7 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -40,12 +40,12 @@
static struct kmem_cache *slab_vmas;
-struct i915_vma *i915_vma_alloc(void)
+static struct i915_vma *i915_vma_alloc(void)
{
return kmem_cache_zalloc(slab_vmas, GFP_KERNEL);
}
-void i915_vma_free(struct i915_vma *vma)
+static void i915_vma_free(struct i915_vma *vma)
{
return kmem_cache_free(slab_vmas, vma);
}
@@ -426,10 +426,8 @@ int i915_vma_bind(struct i915_vma *vma,
work->base.dma.error = 0; /* enable the queue_work() */
- if (vma->obj) {
- __i915_gem_object_pin_pages(vma->obj);
- work->pinned = i915_gem_object_get(vma->obj);
- }
+ __i915_gem_object_pin_pages(vma->obj);
+ work->pinned = i915_gem_object_get(vma->obj);
} else {
vma->ops->bind_vma(vma->vm, NULL, vma, cache_level, bind_flags);
}
@@ -670,7 +668,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
}
color = 0;
- if (vma->obj && i915_vm_has_cache_coloring(vma->vm))
+ if (i915_vm_has_cache_coloring(vma->vm))
color = vma->obj->cache_level;
if (flags & PIN_OFFSET_FIXED) {
@@ -795,17 +793,14 @@ static bool try_qad_pin(struct i915_vma *vma, unsigned
int flags)
static int vma_get_pages(struct i915_vma *vma)
{
int err = 0;
- bool pinned_pages = false;
+ bool pinned_pages = true;
if (atomic_add_unless(&vma->pages_count, 1, 0))
return 0;
- if (vma->obj) {
- err = i915_gem_object_pin_pages(vma->obj);
- if (err)
- return err;
- pinned_pages = true;
- }
+ err = i915_gem_object_pin_pages(vma->obj);
+ if (err)
+ return err;
/* Allocations ahoy! */
if (mutex_lock_interruptible(&vma->pages_mutex)) {
@@ -838,8 +833,8 @@ static void __vma_put_pages(struct i915_vma *vma, unsigned
int count)
if (atomic_sub_return(count, &vma->pages_count) == 0) {
vma->ops->clear_pages(vma);
GEM_BUG_ON(vma->pages);
- if (vma->obj)
- i915_gem_object_unpin_pages(vma->obj);
+
+ i915_gem_object_unpin_pages(vma->obj);
}
mutex_unlock(&vma->pages_mutex);
}
@@ -875,7 +870,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
int err;
#ifdef CONFIG_PROVE_LOCKING
- if (debug_locks && !WARN_ON(!ww) && vma->resv)
+ if (debug_locks && !WARN_ON(!ww))
assert_vma_held(vma);
#endif
@@ -983,7 +978,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!vma->pages);
err = i915_vma_bind(vma,
- vma->obj ? vma->obj->cache_level : 0,
+ vma->obj->cache_level,
flags, work);
[Intel-gfx] [PATCH 1/6] drm/i915: move the pre_pin earlier
In intel_context_do_pin_ww, when calling into the pre_pin hook(which is passed the ww context) it could in theory return -EDEADLK(which is very likely with debug kernels), once we start adding more ww locking in there, like in the next patch. If so then we need to be mindful of having to restart the do_pin at this point. If this is the kernel_context, or some other early in-kernel context where we have yet to setup the default_state, then we always inhibit the context restore, and instead rely on the delayed active_release to set the CONTEXT_VALID_BIT for us(if we even care), which should indicate that we have context switched away, and that our newly saved context state should now be valid. However, since we currently grab the active reference before the potential ww dance, we can end up setting the CONTEXT_VALID_BIT much too early, if we need to backoff, and then upon re-trying the do_pin, we could potentially cause the hardware to incorrectly load some garbage context state when later context switching to that context, but at the very least this will trigger the GEM_BUG_ON() in __engine_unpark. For now let's just move any ww dance stuff prior to arming the active reference. For normal user contexts this shouldn't be a concern, since we should already have the default_state ready when initialising the lrc state, and so there should be no concern with active_release somehow prematurely setting the CONTEXT_VALID_BIT. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 5634d14052bc..ad44860faaf3 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -228,17 +228,17 @@ int __intel_context_do_pin_ww(struct intel_context *ce, if (err) return err; - err = i915_active_acquire(&ce->active); + err = ce->ops->pre_pin(ce, ww, &vaddr); if (err) goto err_ctx_unpin; - err = ce->ops->pre_pin(ce, ww, &vaddr); + err = i915_active_acquire(&ce->active); if (err) - goto err_release; + goto err_post_unpin; err = mutex_lock_interruptible(&ce->pin_mutex); if (err) - goto err_post_unpin; + goto err_release; intel_engine_pm_might_get(ce->engine); -- 2.31.1
[Intel-gfx] [PATCH 6/6] drm/i915: Drain the ttm delayed workqueue too
From: Maarten Lankhorst
Lets be thorough here. Users of the TTM backend would likely expect this
behaviour.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matthew Auld
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index da39bf5508ca..9641aab3e2cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1819,6 +1819,7 @@ static inline void i915_gem_drain_freed_objects(struct
drm_i915_private *i915)
*/
while (atomic_read(&i915->mm.free_count)) {
flush_work(&i915->mm.free_work);
+ flush_delayed_work(&i915->bdev.wq);
rcu_barrier();
}
}
--
2.31.1
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skip remap_io_mapping() for non-x86 platforms
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms URL : https://patchwork.freedesktop.org/series/96855/ State : success == Summary == CI Bug Log - changes from CI_DRM_10875_full -> Patchwork_21574_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 10) -- Missing(1): shard-rkl New tests - New tests have been introduced between CI_DRM_10875_full and Patchwork_21574_full: ### New IGT tests (21) ### * igt@api_intel_bb@delta-check: - Statuses : 6 pass(s) - Exec time: [0.00, 0.03] s * igt@gem_userptr_blits@huge-split: - Statuses : 4 pass(s) - Exec time: [0.00, 0.01] s * igt@gem_userptr_blits@vma-merge: - Statuses : 4 fail(s) - Exec time: [20.06, 20.22] s * igt@kms_plane_scaling@plane-scaling@pipe-a-plane-scaling: - Statuses : 6 pass(s) - Exec time: [1.62, 3.85] s * igt@kms_plane_scaling@plane-scaling@pipe-b-plane-scaling: - Statuses : 6 pass(s) - Exec time: [2.49, 4.86] s * igt@kms_plane_scaling@plane-scaling@pipe-c-plane-scaling: - Statuses : 6 pass(s) - Exec time: [2.49, 5.06] s * igt@kms_plane_scaling@plane-scaling@pipe-d-plane-scaling: - Statuses : 1 pass(s) - Exec time: [2.76] s * igt@kms_plane_scaling@scaler-with-pixel-format: - Statuses : - Exec time: [None] s * igt@kms_plane_scaling@scaler-with-pixel-format@pipe-a-scaler-with-pixel-format: - Statuses : 6 pass(s) - Exec time: [1.59, 8.66] s * igt@kms_plane_scaling@scaler-with-pixel-format@pipe-b-scaler-with-pixel-format: - Statuses : 6 pass(s) - Exec time: [1.74, 9.76] s * igt@kms_plane_scaling@scaler-with-pixel-format@pipe-c-scaler-with-pixel-format: - Statuses : 6 pass(s) - Exec time: [1.46, 9.79] s * igt@kms_plane_scaling@scaler-with-rotation@pipe-a-scaler-with-rotation: - Statuses : 6 pass(s) - Exec time: [1.31, 6.95] s * igt@kms_plane_scaling@scaler-with-rotation@pipe-b-scaler-with-rotation: - Statuses : 6 pass(s) - Exec time: [1.47, 8.18] s * igt@kms_plane_scaling@scaler-with-rotation@pipe-c-scaler-with-rotation: - Statuses : 6 pass(s) - Exec time: [1.19, 8.10] s * igt@kms_plane_scaling@scaler-with-rotation@pipe-d-scaler-with-rotation: - Statuses : 1 pass(s) - Exec time: [8.17] s * igt@sysfs_defaults@readonly: - Statuses : - Exec time: [None] s * igt@sysfs_defaults@readonly@bcs0: - Statuses : 6 pass(s) - Exec time: [0.0, 0.01] s * igt@sysfs_defaults@readonly@rcs0: - Statuses : 6 pass(s) - Exec time: [0.0, 0.01] s * igt@sysfs_defaults@readonly@vcs0: - Statuses : 6 pass(s) - Exec time: [0.0, 0.01] s * igt@sysfs_defaults@readonly@vcs1: - Statuses : 2 pass(s) - Exec time: [0.0, 0.00] s * igt@sysfs_defaults@readonly@vecs0: - Statuses : 6 pass(s) - Exec time: [0.0, 0.01] s Known issues Here are the changes found in Patchwork_21574_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [FAIL][49], [PASS][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl8/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10875/shard-apl4/boot.html [15]: https:
Re: [Intel-gfx] [PATCH v3] drm/i915: Skip error capture when wedged on init
On 11/11/2021 13:06, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Trying to capture uninitialised engines when we wedged on init ends in
tears. Skip that together with uC capture, since failure to initialise the
latter can actually be one of the reasons for wedging on init.
v2:
* Use i915_disable_error_state when wedging on init/fini.
v3:
* Handle mock tests.
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Matthew Auld # v1
Assuming this works locally, r-b still stands.
---
drivers/gpu/drm/i915/gt/intel_reset.c| 2 ++
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index 51b56b8e5003..0fbd6dbadce7 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1448,6 +1448,7 @@ void intel_gt_set_wedged_on_init(struct intel_gt *gt)
BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
I915_WEDGED_ON_INIT);
intel_gt_set_wedged(gt);
+ i915_disable_error_state(gt->i915, -ENODEV);
set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
/* Wedged on init is non-recoverable */
@@ -1457,6 +1458,7 @@ void intel_gt_set_wedged_on_init(struct intel_gt *gt)
void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
{
intel_gt_set_wedged(gt);
+ i915_disable_error_state(gt->i915, -ENODEV);
set_bit(I915_WEDGED_ON_FINI, >->reset.flags);
intel_gt_retire_requests(gt); /* cleanup any wedged requests */
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 9ab3f284d1dd..d0e2e61de8d4 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -177,6 +177,8 @@ struct drm_i915_private *mock_gem_device(void)
mock_uncore_init(&i915->uncore, i915);
+ spin_lock_init(&i915->gpu_error.lock);
+
i915_gem_init__mm(i915);
intel_gt_init_early(&i915->gt, i915);
atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
[Intel-gfx] [PATCH] drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms
Pre-HSW platforms don't use the gt SSEU structures; this means that
calling intel_sseu_get_subslices() on slice 0 for these platforms will
trip a GEM_BUG_ON(slice >= sseu->max_slices) warning.
Let's move the DSS lookup for a DG2 workaround into a helper function
that will only get called after we've already decided that we're on a
DG2 platform.
Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 51591119da15..a9727447c037 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2019,11 +2019,18 @@ engine_fake_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
}
}
+
+static bool needs_wa_1308578152(struct intel_engine_cs *engine)
+{
+ u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
+
+ return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+}
+
static void
rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
@@ -2057,7 +2064,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct
i915_wa_list *wal)
/* Wa_1308578152:dg2_g10 when first gslice is fused off */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_C0) &&
- (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0) {
+ needs_wa_1308578152(engine)) {
wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON,
GEN12_REPLAY_MODE_GRANULARITY);
}
--
2.33.0
Re: [Intel-gfx] [PATCH 02/28] drm/i915: use new iterator in i915_gem_object_wait_reservation
On Thu, Nov 11, 2021 at 12:36:47PM +0100, Christian König wrote: > Am 01.11.21 um 10:41 schrieb Tvrtko Ursulin: > > > > On 28/10/2021 16:30, Daniel Vetter wrote: > > > On Thu, Oct 28, 2021 at 10:41:38AM +0200, Christian König wrote: > > > > Am 21.10.21 um 13:13 schrieb Tvrtko Ursulin: > > > > > > > > > > On 21/10/2021 12:06, Maarten Lankhorst wrote: > > > > > > Op 21-10-2021 om 12:38 schreef Christian König: > > > > > > > Am 21.10.21 um 12:35 schrieb Maarten Lankhorst: > > > > > > > > From: Christian König > > > > > > > > > > > > > > > > Simplifying the code a bit. > > > > > > > > > > > > > > > > Signed-off-by: Christian König > > > > > > > > [mlankhorst: Handle timeout = 0 correctly, use new > > > > > > > > i915_request_wait_timeout.] > > > > > > > > Signed-off-by: Maarten Lankhorst > > > > > > > > > > > > > > > > > > > > > > LGTM, do you want to push it or should I pick it up > > > > > > > into drm-misc-next? > > > > > > > > > > > > I think it can be applied to drm-intel-gt-next, after a backmerge. > > > > > > It needs patch 1 too, which fixes > > > > > > > > > > > > i915_request_wait semantics when used in dma-fence. It exports a > > > > > > dma-fence compatible i915_request_wait_timeout function, used in > > > > > > this patch. > > > > > > > > What about the other i915 patches? I guess you then want to merge them > > > > through drm-intel-gt-next as well. > > > > > > > > > I don't think my open has been resolved, at least I haven't > > > > > seen a reply > > > > > from Daniel on the topic of potential for infinite waits > > > > > with untrusted > > > > > clients after this change. +Daniel > > > > > > > > Please resolve that internally and let me know the result. I'm > > > > fine to use > > > > any of the possible approaches, I just need to know which one. > > > > > > I thought I explained this in the patch set from Maarten. This isn't an > > > issue, since the exact same thing can happen if you get interrupts and > > > stuff. > > > > Ah were you trying to point out all this time the infinite wait just got > > moved from inside the "old" dma_resv_get_fences to the new iterator > > caller? > > At least I think so, yes. But Daniel needs to answer that. Well maybe there's also an infinite wait inside the old dma_resv_get_fences, what I mean is that when you have some signals interrupting you, then the infinite wait is already there due to a retry loop outside of the syscall even. Anyway _any_ userspace which wants to use this wait on a shared bo and waits to be safe against the other end adding more rendering has to use something else (like the sync_file export ioctl on the dma-buf that Jason typed). Trying to make this ioctl here against fence addition is just bs. > > Regards, > > > > Tvrtko > > > > > > > > The only proper fix for bounding the waits is a) compositor grabs a > > > stable > > > set of dma_fence from the dma-buf through the proposed fence export > > > ioctl > > > b) compositor waits on that fence (or drm_syncobj). > > > > > > Everything else is cargo-culted nonsense, and very much includes > > > that igt > > > patch that's floating around internally. > > > > > > I can also whack this into drm-next if this is stuck in this silly > > > bikeshed. > > Can we move forward with those patches? I still don't see them in > drm-misc-next. > > I you want I can also pick Maartens modified version here up and send it out > with the reset of the i915 patches once more. > > Everything else is already pushed. Please push to drm-misc-next or wherever (assuming CI is happy) and feel free to add my ack. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/6] drm/i915: move the pre_pin earlier
== Series Details == Series: series starting with [1/6] drm/i915: move the pre_pin earlier URL : https://patchwork.freedesktop.org/series/96859/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Check GuC status before freq boost
On Thu, 11 Nov 2021 23:10:16 -0800, Vinay Belgaumkar wrote:
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 4e1d3cd29164..22c1c12369f2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -183,11 +183,15 @@ static int slpc_unset_param(struct intel_guc_slpc *slpc,
> static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> + struct intel_guc *guc = slpc_to_guc(slpc);
> intel_wakeref_t wakeref;
> int ret = 0;
>
> lockdep_assert_held(&slpc->lock);
>
> + if (!intel_guc_is_ready(guc))
> + return -ENODEV;
> +
Reviewed-by: Ashutosh Dixit
The test wedges/resets the GPU after a request is queued but before it is
retired.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: move the pre_pin earlier
== Series Details == Series: series starting with [1/6] drm/i915: move the pre_pin earlier URL : https://patchwork.freedesktop.org/series/96859/ State : success == Summary == CI Bug Log - changes from CI_DRM_10876 -> Patchwork_21575 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/index.html Participating hosts (34 -> 34) -- Additional (3): fi-tgl-u2 fi-tgl-1115g4 fi-pnv-d510 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21575 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([fdo#109315]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315] / [i915#2575]) +16 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@core_hotunplug@unbind-rebind: - fi-tgl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4006]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@gem_huc_c...@huc-copy.html - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#1155]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109284] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-u2: NOTRUN -> [SKIP][9] ([i915#4103]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#4103]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html - fi-tgl-u2: NOTRUN -> [SKIP][12] ([fdo#109285]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][14] ([fdo#109271]) +53 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-pnv-d510/igt@prime_v...@basic-userptr.html - fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3301]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@prime_v...@basic-userptr.html - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#3301]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-tgl-u2: NOTRUN -> [FAIL][17] ([i915#1602] / [i915#2722] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-tgl-u2/igt@run...@aborted.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][18] ([i915#4269]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109284]: https://bugs.freedesktop.org/show_bug.
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms
== Series Details == Series: drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms URL : https://patchwork.freedesktop.org/series/96861/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms
== Series Details == Series: drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms URL : https://patchwork.freedesktop.org/series/96861/ State : success == Summary == CI Bug Log - changes from CI_DRM_10876 -> Patchwork_21576 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/index.html Participating hosts (34 -> 32) -- Additional (1): fi-tgl-1115g4 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21576 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-elk-e7500: NOTRUN -> [SKIP][1] ([fdo#109271]) +49 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html * igt@amdgpu/amd_basic@query-info: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([fdo#109315]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-ivb-3770:NOTRUN -> [SKIP][3] ([fdo#109271]) +31 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][4] ([fdo#109271]) +35 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@amdgpu/amd_cs_nop@nop-gfx0: - fi-tgl-1115g4: NOTRUN -> [SKIP][5] ([fdo#109315] / [i915#2575]) +16 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html * igt@gem_exec_suspend@basic-s3: - fi-bwr-2160:NOTRUN -> [SKIP][6] ([fdo#109271]) +60 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-bwr-2160/igt@gem_exec_susp...@basic-s3.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#1155]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-snb-2600:NOTRUN -> [SKIP][9] ([fdo#109271]) +37 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html - fi-ivb-3770:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-ivb-3770/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_chamelium@hdmi-crc-fast: - fi-snb-2600:NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC
On Fri, 12 Nov 2021 10:08:41 -0500 Jason Baron wrote: > > A key difference between that patchset and this patch (besides that > > small fact that I used +x instead of +T) was that my patchset allowed > > the dyndbg trace to be emitted to the main buffer and did not force them > > to be in an instance-specific buffer. > > Yes, I agree I'd prefer that we print here to the 'main' buffer - it seems to > keep things simpler and easier to combine the output from different > sources as you mentioned. I do not want anything to print to the "main buffer" that can not be filtered or turned off by the tracing infrastructure itself (aka tracefs file system). Once we allow that, then the trace file will become useless because everything will write to the main buffer and fill it with noise. Events that can be enabled and disabled from tracefs are fine, as they can be limited. This is why I added that nasty warning if people leave around trace_printk(), because it does exactly this (write to the main buffer). It's fine for debugging a custom kernel, but should never be enabled in something that is shipped, or part of mainline. -- Steve
[Intel-gfx] [PATCH] drm/i915: Skip remap_io_mapping() for non-x86 platforms
The _PAGE_CACHE_MASK macro is not defined in non-x86
architectures and it's been used in remap_io_mapping().
Only hw that supports mappable aperture would hit this path
remap_io_mapping(), So skip this code for non-x86 architectures.
Signed-off-by: Mullati Siva
---
drivers/gpu/drm/i915/i915_mm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
index 666808cb3a32..d76feeaf3fd1 100644
--- a/drivers/gpu/drm/i915/i915_mm.c
+++ b/drivers/gpu/drm/i915/i915_mm.c
@@ -91,6 +91,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
struct io_mapping *iomap)
{
+#if IS_ENABLED(CONFIG_X86)
struct remap_pfn r;
int err;
@@ -108,6 +109,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
return err;
}
+#endif
return 0;
}
--
2.33.0
Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC
On 11/12/21 12:07 PM, Steven Rostedt wrote: > On Fri, 12 Nov 2021 10:08:41 -0500 > Jason Baron wrote: > >>> A key difference between that patchset and this patch (besides that >>> small fact that I used +x instead of +T) was that my patchset allowed >>> the dyndbg trace to be emitted to the main buffer and did not force them >>> to be in an instance-specific buffer. >> >> Yes, I agree I'd prefer that we print here to the 'main' buffer - it seems >> to keep things simpler and easier to combine the output from different >> sources as you mentioned. > > I do not want anything to print to the "main buffer" that can not be > filtered or turned off by the tracing infrastructure itself (aka tracefs > file system). > > Once we allow that, then the trace file will become useless because > everything will write to the main buffer and fill it with noise. > > Events that can be enabled and disabled from tracefs are fine, as they can > be limited. This is why I added that nasty warning if people leave around > trace_printk(), because it does exactly this (write to the main buffer). > It's fine for debugging a custom kernel, but should never be enabled in > something that is shipped, or part of mainline. > > -- Steve > Ok, it looks like Vincent's patch defines a dyndbg event and then uses 'trace_dyndbg()' to output to the 'main' log. So all dynamic output to the 'main' ftrace buffer goes through that event if I understand it correctly. Here's a pointer to it for reference: https://lore.kernel.org/lkml/20200825153338.17061-3-vincent.whitchu...@axis.com/ Would you be ok with that approach? Thanks, -Jason
Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC
On 11/12/21 6:49 AM, Vincent Whitchurch wrote: > On Thu, Nov 11, 2021 at 03:02:04PM -0700, Jim Cromie wrote: >> Sean Paul proposed, in: >> https://urldefense.com/v3/__https://patchwork.freedesktop.org/series/78133/__;!!GjvTz_vk!HcKnMRByYkIdyF1apqQjlN5aBIomzJR1an3YWXM6KXs0EftVMQdrewRA8Dki4A$ >> >> drm/trace: Mirror DRM debug logs to tracefs >> >> His patchset's objective is to be able to independently steer some of >> the drm.debug stream to an alternate tracing destination, by splitting >> drm_debug_enabled() into syslog & trace flavors, and enabling them >> separately. 2 advantages were identified: >> >> 1- syslog is heavyweight, tracefs is much lighter >> 2- separate selection of enabled categories means less traffic >> >> Dynamic-Debug can do 2nd exceedingly well: >> >> A- all work is behind jump-label's NOOP, zero off cost. >> B- exact site selectivity, precisely the useful traffic. >>can tailor enabled set interactively, at shell. >> >> Since the tracefs interface is effective for drm (the threads suggest >> so), adding that interface to dynamic-debug has real potential for >> everyone including drm. >> >> if CONFIG_TRACING: >> >> Grab Sean's trace_init/cleanup code, use it to provide tracefs >> available by default to all pr_debugs. This will likely need some >> further per-module treatment; perhaps something reflecting hierarchy >> of module,file,function,line, maybe with a tuned flattening. >> >> endif CONFIG_TRACING >> >> Add a new +T flag to enable tracing, independent of +p, and add and >> use 3 macros: dyndbg_site_is_enabled/logging/tracing(), to encapsulate >> the flag checks. Existing code treats T like other flags. > > I posted a patchset a while ago to do something very similar, but that > got stalled for some reason and I unfortunately didn't follow it up: > > > https://urldefense.com/v3/__https://lore.kernel.org/lkml/20200825153338.17061-1-vincent.whitchu...@axis.com/__;!!GjvTz_vk!HcKnMRByYkIdyF1apqQjlN5aBIomzJR1an3YWXM6KXs0EftVMQdrewRGytKHPg$ > > > A key difference between that patchset and this patch (besides that > small fact that I used +x instead of +T) was that my patchset allowed > the dyndbg trace to be emitted to the main buffer and did not force them > to be in an instance-specific buffer. Yes, I agree I'd prefer that we print here to the 'main' buffer - it seems to keep things simpler and easier to combine the output from different sources as you mentioned. Thanks, -Jason > > That feature is quite important at least for my use case since I often > use dyndbg combined with function tracing, and the latter doesn't work > on non-main instances according to Documentation/trace/ftrace.rst. > > For example, here's a random example of a bootargs from one of my recent > debugging sessions: > > trace_event=printk:* ftrace_filter=_mmc*,mmc*,sd*,dw_mci*,mci* > ftrace=function trace_buf_size=20M dyndbg="file drivers/mmc/* +x" >
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2) URL : https://patchwork.freedesktop.org/series/96855/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH v10 08/10] dyndbg: add print-to-tracefs, selftest with it - RFC
On Fri, 12 Nov 2021 12:32:23 -0500 Jason Baron wrote: > Ok, it looks like Vincent's patch defines a dyndbg event and then uses > 'trace_dyndbg()' to output to the 'main' log. So all dynamic output to > the 'main' ftrace buffer goes through that event if I understand it > correctly. Here's a pointer to it for reference: > > https://lore.kernel.org/lkml/20200825153338.17061-3-vincent.whitchu...@axis.com/ > > Would you be ok with that approach? Yes that approach is fine, because it doesn't actually go to the main log unless you enable the dyndbg trace event in the main buffer. You could also enable that event in an instance and have it go there. -- Steve
Re: [Intel-gfx] [PATCH] drm/i915/execlists: Weak parallel submission support for execlists
On Fri, Nov 12, 2021 at 02:13:50PM +, Tvrtko Ursulin wrote:
>
> On 11/11/2021 16:49, Matthew Brost wrote:
> > On Mon, Nov 01, 2021 at 10:35:09AM +, Tvrtko Ursulin wrote:
> > >
> > > On 27/10/2021 21:10, Matthew Brost wrote:
> > > > On Wed, Oct 27, 2021 at 01:04:49PM -0700, John Harrison wrote:
> > > > > On 10/27/2021 12:17, Matthew Brost wrote:
> > > > > > On Tue, Oct 26, 2021 at 02:58:00PM -0700, John Harrison wrote:
> > > > > > > On 10/20/2021 14:47, Matthew Brost wrote:
> > > > > > > > A weak implementation of parallel submission (multi-bb execbuf
> > > > > > > > IOCTL) for
> > > > > > > > execlists. Doing as little as possible to support this
> > > > > > > > interface for
> > > > > > > > execlists - basically just passing submit fences between each
> > > > > > > > request
> > > > > > > > generated and virtual engines are not allowed. This is on par
> > > > > > > > with what
> > > > > > > > is there for the existing (hopefully soon deprecated) bonding
> > > > > > > > interface.
> > > > > > > >
> > > > > > > > We perma-pin these execlists contexts to align with GuC
> > > > > > > > implementation.
> > > > > > > >
> > > > > > > > v2:
> > > > > > > > (John Harrison)
> > > > > > > > - Drop siblings array as num_siblings must be 1
> > > > > > > >
> > > > > > > > Signed-off-by: Matthew Brost
> > > > > > > > ---
> > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +++--
> > > > > > > > drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
> > > > > > > > .../drm/i915/gt/intel_execlists_submission.c | 44
> > > > > > > > ++-
> > > > > > > > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +
> > > > > > > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -
> > > > > > > > 5 files changed, 52 insertions(+), 10 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > > > > > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > > > > > index fb33d0322960..35e87a7d0ea9 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > > > > > > > @@ -570,10 +570,6 @@
> > > > > > > > set_proto_ctx_engines_parallel_submit(struct
> > > > > > > > i915_user_extension __user *base,
> > > > > > > > struct intel_engine_cs **siblings = NULL;
> > > > > > > > intel_engine_mask_t prev_mask;
> > > > > > > > - /* FIXME: This is NIY for execlists */
> > > > > > > > - if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
> > > > > > > > - return -ENODEV;
> > > > > > > > -
> > > > > > > > if (get_user(slot, &ext->engine_index))
> > > > > > > > return -EFAULT;
> > > > > > > > @@ -583,6 +579,12 @@
> > > > > > > > set_proto_ctx_engines_parallel_submit(struct
> > > > > > > > i915_user_extension __user *base,
> > > > > > > > if (get_user(num_siblings, &ext->num_siblings))
> > > > > > > > return -EFAULT;
> > > > > > > > + if (!intel_uc_uses_guc_submission(&i915->gt.uc) &&
> > > > > > > > num_siblings != 1) {
> > > > > > > > + drm_dbg(&i915->drm, "Only 1 sibling (%d)
> > > > > > > > supported in non-GuC mode\n",
> > > > > > > > + num_siblings);
> > > > > > > > + return -EINVAL;
> > > > > > > > + }
> > > > > > > > +
> > > > > > > > if (slot >= set->num_engines) {
> > > > > > > > drm_dbg(&i915->drm, "Invalid placement value,
> > > > > > > > %d >= %d\n",
> > > > > > > > slot, set->num_engines);
> > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > > > > > > > b/drivers/gpu/drm/i915/gt/intel_context.c
> > > > > > > > index 5634d14052bc..1bec92e1d8e6 100644
> > > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > > > > > > > @@ -79,7 +79,8 @@ static int
> > > > > > > > intel_context_active_acquire(struct intel_context *ce)
> > > > > > > > __i915_active_acquire(&ce->active);
> > > > > > > > - if (intel_context_is_barrier(ce) ||
> > > > > > > > intel_engine_uses_guc(ce->engine))
> > > > > > > > + if (intel_context_is_barrier(ce) ||
> > > > > > > > intel_engine_uses_guc(ce->engine) ||
> > > > > > > > + intel_context_is_parallel(ce))
> > > > > > > > return 0;
> > > > > > > > /* Preallocate tracking nodes */
> > > > > > > > @@ -563,7 +564,6 @@ void intel_context_bind_parent_child(struct
> > > > > > > > intel_context *parent,
> > > > > > > > * Callers responsibility to validate that this
> > > > > > > > function is used
> > > > > > > > * correctly but we use GEM_BUG_ON here ensure that
> > > > > > > > they do.
> > > > > > > > */
> > > > > > > > - GEM_BUG_ON(!intel_engine_uses_guc(parent->engine));
> > > > > > > > GEM_BUG_ON(intel_context_
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2) URL : https://patchwork.freedesktop.org/series/96855/ State : success == Summary == CI Bug Log - changes from CI_DRM_10876 -> Patchwork_21577 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/index.html Participating hosts (34 -> 31) -- Additional (1): fi-pnv-d510 Missing(4): fi-skl-guc fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21577 that come from known issues: ### IGT changes ### Issues hit * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][1] ([fdo#109271]) +53 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][2] ([i915#1602] / [i915#2426] / [i915#4312]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/fi-bdw-5557u/igt@run...@aborted.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][3] ([i915#4269]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 Build changes - * Linux: CI_DRM_10876 -> Patchwork_21577 CI-20190529: 20190529 CI_DRM_10876: 60c931742b2d9635f78dec02e25c76881c2c8699 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21577: 0e29b9daab8f6918df459907c8ce56e642ee3bbb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0e29b9daab8f drm/i915: Skip remap_io_mapping() for non-x86 platforms == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: move the pre_pin earlier
== Series Details == Series: series starting with [1/6] drm/i915: move the pre_pin earlier URL : https://patchwork.freedesktop.org/series/96859/ State : success == Summary == CI Bug Log - changes from CI_DRM_10876_full -> Patchwork_21575_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21575_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vecs0: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-kbl4/igt@gem_ctx_isolation@preservation...@vecs0.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [PASS][2] -> [TIMEOUT][3] ([i915#3063]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-tglb5/igt@gem_...@in-flight-contexts-immediate.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-tglb2/igt@gem_...@in-flight-contexts-immediate.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#2369]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-skl7/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-tglb: NOTRUN -> [FAIL][5] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-tglb3/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-kbl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-kbl3/igt@gem_exec_fair@basic-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-kbl6/igt@gem_exec_fair@basic-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-glk4/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_mmap_gtt@coherency: - shard-tglb: NOTRUN -> [SKIP][18] ([fdo#111656]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-tglb6/igt@gem_mmap_...@coherency.html * igt@gem_pxp@create-regular-buffer: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#4270]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-tglb6/igt@gem_...@create-regular-buffer.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][20] ([i915#3002]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-apl7/igt@gem_userptr_bl...@input-checking.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][21] ([i915#3318]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-apl7/igt@gem_userptr_bl...@vma-merge.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21575/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS
Re: [Intel-gfx] [PATCH 0/2] Nuke PAGE_KERNEL_IO
On Thu, Oct 21, 2021 at 11:15:09AM -0700, Lucas De Marchi wrote: > Last user of PAGE_KERNEL_IO is the i915 driver. While removing it from > there as we seek to bring the driver to other architectures, Daniel > suggested that we could finish the cleanup and remove it altogether, > through the tip tree. So here I'm sending both commits needed for that. > > Lucas De Marchi (2): > drm/i915/gem: stop using PAGE_KERNEL_IO > x86/mm: nuke PAGE_KERNEL_IO > > arch/x86/include/asm/fixmap.h | 2 +- > arch/x86/include/asm/pgtable_types.h | 7 --- > arch/x86/mm/ioremap.c | 2 +- > arch/x86/xen/setup.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++-- > include/asm-generic/fixmap.h | 2 +- > 6 files changed, 6 insertions(+), 13 deletions(-) Acked-by: Peter Zijlstra (Intel)
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms
== Series Details == Series: drm/i915: Don't read query SSEU for non-existent slice 0 on old platforms URL : https://patchwork.freedesktop.org/series/96861/ State : success == Summary == CI Bug Log - changes from CI_DRM_10876_full -> Patchwork_21576_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21576_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50]) ([i915#4386]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl8/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl7/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl1/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl8/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl8/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl3/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl3/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl3/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21576/shard-apl2/boot.html [44]: https:
[Intel-gfx] [PATCH] drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
After a non-blocking modeset on a TypeC port's CRTC - possibly blocked
later in drm_atomic_helper_wait_for_dependencies() - a fastset on the
same CRTC may copy the state of CRTC before this gets updated to reflect
the up-to-date DP-alt vs. TBT-alt TypeC mode DPLL used for the CRTC. In
this case after the first (non-blocking) commit completes enabling the
DPLL required for the up-to-date TypeC mode the following fastset will
update the CRTC state pointing to the wrong DPLL. A subsequent disabling
modeset will try to disable the wrong PLL, triggering a state checker
WARN (and leaving the DPLL which is actually used active for good).
Fix the above race by copying the DPLL state for fastset CRTCs from the
old CRTC state at the point where it's guaranteed to be up-to-date
already. This could be handled in the encoder's update_prepare() hook as
well, but that's a bigger change, which is better done as a follow-up.
Testcase: igt/kms_busy/extended-modeset-hang-newfb-with-reset
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4308
Cc: Ville Syrjala
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_display.c | 25
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac66717..76ebb3c91a75b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1572,10 +1572,24 @@ intel_connector_primary_encoder(struct intel_connector
*connector)
static void intel_encoders_update_prepare(struct intel_atomic_state *state)
{
+ struct intel_crtc_state *new_crtc_state, *old_crtc_state;
+ struct intel_crtc *crtc;
struct drm_connector_state *new_conn_state;
struct drm_connector *connector;
int i;
+ /*
+* Make sure the DPLL state is up-to-date for fastset TypeC ports after
non-blocking commits.
+* TODO: Update the DPLL state for all cases in the
encoder->update_prepare() hook.
+*/
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ new_crtc_state->shared_dpll =
old_crtc_state->shared_dpll;
+ }
+
+ if (!state->modeset)
+ return;
+
for_each_new_connector_in_state(&state->base, connector, new_conn_state,
i) {
struct intel_connector *intel_connector;
@@ -1602,6 +1616,9 @@ static void intel_encoders_update_complete(struct
intel_atomic_state *state)
struct drm_connector *connector;
int i;
+ if (!state->modeset)
+ return;
+
for_each_new_connector_in_state(&state->base, connector, new_conn_state,
i) {
struct intel_connector *intel_connector;
@@ -8670,8 +8687,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
}
- if (state->modeset)
- intel_encoders_update_prepare(state);
+ intel_encoders_update_prepare(state);
intel_dbuf_pre_plane_update(state);
@@ -8683,11 +8699,10 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display->commit_modeset_enables(state);
- if (state->modeset) {
- intel_encoders_update_complete(state);
+ intel_encoders_update_complete(state);
+ if (state->modeset)
intel_set_cdclk_post_plane_update(state);
- }
intel_wait_for_vblank_workers(state);
--
2.27.0
[Intel-gfx] [PATCH 0/9] drm/i915: Register define cleanups
From: Ville Syrjälä A bunch of REG_BIT() stuff a random collection of registers. Some of these are related to areas where I plan to do a bit of additional work on the code itself, and a few are just some easy ones I spotted in the vicinity. Ville Syrjälä (9): drm/i915: Bump DSL linemask to 20 bits drm/i915: Clean up PIPEMISC register defines drm/i915: Clean up SKL_BOTTOM_COLOR defines drm/i915: Clean up PIPECONF bit defines drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines drm/i915: Clean up PIPESRC defines drm/i915: Clean up CRC register defines drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits drm/i915: Clean up FPGA_DBG/CLAIM_ER bits drivers/gpu/drm/i915/display/i9xx_plane.c | 4 +- drivers/gpu/drm/i915/display/icl_dsi.c| 4 +- drivers/gpu/drm/i915/display/intel_display.c | 95 ++--- .../gpu/drm/i915/display/intel_pch_display.c | 20 +- drivers/gpu/drm/i915/gvt/display.c| 4 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 +- drivers/gpu/drm/i915/i915_irq.c | 9 +- drivers/gpu/drm/i915/i915_reg.h | 392 +- 8 files changed, 261 insertions(+), 271 deletions(-) -- 2.32.0
[Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines
From: Ville Syrjälä
Use REG_BIT() for SKL_BOTTOM_COLOR.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e300a202ce2d..8b227dabb10c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6341,8 +6341,8 @@ enum {
/* Skylake+ pipe bottom (background) color */
#define _SKL_BOTTOM_COLOR_A0x70034
-#define SKL_BOTTOM_COLOR_GAMMA_ENABLE(1 << 31)
-#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30)
+#define SKL_BOTTOM_COLOR_GAMMA_ENABLEREG_BIT(31)
+#define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
#define _ICL_PIPE_A_STATUS 0x70058
--
2.32.0
[Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines
From: Ville Syrjälä
Use REG_BIT() & co. for PIPECONF bits, and adjust the
naming of various bits to be more consistent.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 60 +-
.../gpu/drm/i915/display/intel_pch_display.c | 7 +-
drivers/gpu/drm/i915/gvt/display.c| 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 108 +-
6 files changed, 89 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index c05fb861f10c..0f6587bef106 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1048,7 +1048,7 @@ static void gen11_dsi_enable_transcoder(struct
intel_encoder *encoder)
/* wait for transcoder to be enabled */
if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE, 10))
+ PIPECONF_STATE_ENABLE, 10))
drm_err(&dev_priv->drm,
"DSI transcoder not enabled\n");
}
@@ -1317,7 +1317,7 @@ static void gen11_dsi_disable_transcoder(struct
intel_encoder *encoder)
/* wait for transcoder to be disabled */
if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE, 50))
+ PIPECONF_STATE_ENABLE, 50))
drm_err(&dev_priv->drm,
"DSI trancoder not disabled\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e293241450b1..4e29032b29d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -386,13 +386,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state
*old_crtc_state)
if (DISPLAY_VER(dev_priv) >= 4) {
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- i915_reg_t reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
- if (intel_de_wait_for_clear(dev_priv, reg,
- I965_PIPECONF_ACTIVE, 100))
- drm_WARN(&dev_priv->drm, 1,
-"pipe_off wait timed out\n");
+ if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
+ PIPECONF_STATE_ENABLE, 100))
+ drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed
out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
}
@@ -3338,13 +3336,13 @@ static void i9xx_set_pipeconf(const struct
intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) {
case 18:
- pipeconf |= PIPECONF_6BPC;
+ pipeconf |= PIPECONF_BPC_6;
break;
case 24:
- pipeconf |= PIPECONF_8BPC;
+ pipeconf |= PIPECONF_BPC_8;
break;
case 30:
- pipeconf |= PIPECONF_10BPC;
+ pipeconf |= PIPECONF_BPC_10;
break;
default:
/* Case prevented by intel_choose_pipe_bpp_dither. */
@@ -3359,7 +3357,7 @@ static void i9xx_set_pipeconf(const struct
intel_crtc_state *crtc_state)
else
pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
} else {
- pipeconf |= PIPECONF_PROGRESSIVE;
+ pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
@@ -3537,16 +3535,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc
*crtc,
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
switch (tmp & PIPECONF_BPC_MASK) {
- case PIPECONF_6BPC:
+ case PIPECONF_BPC_6:
pipe_config->pipe_bpp = 18;
break;
- case PIPECONF_8BPC:
+ case PIPECONF_BPC_8:
pipe_config->pipe_bpp = 24;
break;
- case PIPECONF_10BPC:
+ case PIPECONF_BPC_10:
pipe_config->pipe_bpp = 30;
break;
default:
+ MISSING_CASE(tmp);
break;
}
}
@@ -3555,8 +3554,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
(tmp & PIPECONF_COLOR_RANG
[Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines
From: Ville Syrjälä
Use REG_GENMASK() & co. when dealing with PIPESRC.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 4 ++--
drivers/gpu/drm/i915/display/intel_display.c | 7 ---
drivers/gpu/drm/i915/i915_reg.h | 4
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 2194f74101ae..f586e39cb378 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
plane_config->base = base;
val = intel_de_read(dev_priv, PIPESRC(pipe));
- fb->width = ((val >> 16) & 0xfff) + 1;
- fb->height = ((val >> 0) & 0xfff) + 1;
+ fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
+ fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
fb->pitches[0] = val & 0xffc0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4e29032b29d6..e1959a17805c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3236,7 +3236,8 @@ static void intel_set_pipe_src_size(const struct
intel_crtc_state *crtc_state)
* always be the user's requested size.
*/
intel_de_write(dev_priv, PIPESRC(pipe),
- ((crtc_state->pipe_src_w - 1) << 16) |
(crtc_state->pipe_src_h - 1));
+ PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
+ PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
}
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
@@ -3307,8 +3308,8 @@ static void intel_get_pipe_src_size(struct intel_crtc
*crtc,
u32 tmp;
tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
- pipe_config->pipe_src_h = (tmp & 0x) + 1;
- pipe_config->pipe_src_w = ((tmp >> 16) & 0x) + 1;
+ pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
+ pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
}
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eea009e76e15..211e2b415e50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4476,6 +4476,10 @@ enum {
#define _VSYNC_A 0x60014
#define _EXITLINE_A0x60018
#define _PIPEASRC 0x6001c
+#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
+#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
+#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
+#define PIPESRC_HEIGHT(h)REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
#define _PIPE_MULT_A 0x6002c
--
2.32.0
[Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
From: Ville Syrjälä
Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
adjust the naming a some bits to be more consistent.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_pch_display.c | 13 +++--
drivers/gpu/drm/i915/i915_reg.h | 58 +--
2 files changed, 33 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 81ab761251ae..155c2d19a6bb 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct
intel_crtc_state *crtc_state)
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) ==
PIPECONF_INTERLACE_IF_ID_ILK) {
if (HAS_PCH_IBX(dev_priv) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- val |= TRANS_LEGACY_INTERLACED_ILK;
+ val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
else
- val |= TRANS_INTERLACED;
+ val |= TRANS_INTERLACE_INTERLACED;
} else {
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
}
intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
@@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
temp = intel_de_read(dev_priv, reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK |
- TRANS_DP_SYNC_MASK |
+ TRANS_DP_VSYNC_ACTIVE_HIGH |
+ TRANS_DP_HSYNC_ACTIVE_HIGH |
TRANS_DP_BPC_MASK);
temp |= TRANS_DP_OUTPUT_ENABLE;
temp |= bpc << 9; /* same format but at 11:9 */
@@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct
drm_i915_private *dev_priv,
pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
PIPECONF_INTERLACE_IF_ID_ILK)
- val |= TRANS_INTERLACED;
+ val |= TRANS_INTERLACE_INTERLACED;
else
- val |= TRANS_PROGRESSIVE;
+ val |= TRANS_INTERLACE_PROGRESSIVE;
intel_de_write(dev_priv, LPT_TRANSCONF, val);
if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2d5b2fa2a4a..eea009e76e15 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8994,22 +8994,19 @@ enum {
#define _PCH_TRANSBCONF 0xf1008
#define PCH_TRANSCONF(pipe)_MMIO_PIPE(pipe, _PCH_TRANSACONF,
_PCH_TRANSBCONF)
#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one
transcoder */
-#define TRANS_DISABLE (0 << 31)
-#define TRANS_ENABLE (1 << 31)
-#define TRANS_STATE_MASK (1 << 30)
-#define TRANS_STATE_DISABLE(0 << 30)
-#define TRANS_STATE_ENABLE (1 << 30)
-#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
-#define TRANS_FRAME_START_DELAY(x)((x) << 27) /* ibx: 0-3 */
-#define TRANS_INTERLACE_MASK (7 << 21)
-#define TRANS_PROGRESSIVE (0 << 21)
-#define TRANS_INTERLACED (3 << 21)
-#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
-#define TRANS_8BPC (0 << 5)
-#define TRANS_10BPC(1 << 5)
-#define TRANS_6BPC (2 << 5)
-#define TRANS_12BPC(3 << 5)
-
+#define TRANS_ENABLE REG_BIT(31)
+#define TRANS_STATE_ENABLEREG_BIT(30)
+#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x)
REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
+#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
+#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
+#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
+#define TRANS_INTERLACE_INTERLACEDREG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
+#define TRANS_BPC_MASKREG_GENMASK(7, 5) /* ibx */
+#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
+#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
+#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
+#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
#define _TRANSA_CHICKEN10xf0060
#define _TRANSB_CHICKEN10xf1060
#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1,
_TRANSB_CHICKEN1)
@@ -9219,22 +9216,19 @@ enum {
#define _TRANS_DP_CTL_B0xe1300
#define _TRANS_DP_CTL_C0xe2300
#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A,
_TRANS_DP_CTL_B)
-#define TRANS_DP_OUTPUT_ENABLE(1 << 31)
-#define TRANS_DP_PORT_SEL_M
[Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits
From: Ville Syrjälä
Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our
definition to match. And while at it let's also add the define
for the current field readback.
We can also get rid of the gen2 vs. gen3+ nonsense since none
of the extra bits ever did anything and just always read
as zero.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++
drivers/gpu/drm/i915/i915_irq.c | 7 ++-
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0ceee8ac6671..6073f94632ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -348,16 +348,10 @@ static bool pipe_scanline_is_moving(struct
drm_i915_private *dev_priv,
{
i915_reg_t reg = PIPEDSL(pipe);
u32 line1, line2;
- u32 line_mask;
- if (DISPLAY_VER(dev_priv) == 2)
- line_mask = DSL_LINEMASK_GEN2;
- else
- line_mask = DSL_LINEMASK_GEN3;
-
- line1 = intel_de_read(dev_priv, reg) & line_mask;
+ line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
msleep(5);
- line2 = intel_de_read(dev_priv, reg) & line_mask;
+ line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
return line1 != line2;
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 038a9ec563c1..eb8c92324aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -836,10 +836,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
vtotal /= 2;
- if (DISPLAY_VER(dev_priv) == 2)
- position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
DSL_LINEMASK_GEN2;
- else
- position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
DSL_LINEMASK_GEN3;
+ position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
PIPEDSL_LINE_MASK;
/*
* On HSW, the DSL reg (0x7) appears to return 0 if we
@@ -858,7 +855,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
*crtc)
for (i = 0; i < 100; i++) {
udelay(1);
- temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
DSL_LINEMASK_GEN3;
+ temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
PIPEDSL_LINE_MASK;
if (temp != position) {
position = temp;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 686f0a1b7860..f5d54ed2efc1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6165,8 +6165,8 @@ enum {
/* Pipe A */
#define _PIPEADSL 0x7
-#define DSL_LINEMASK_GEN20x0fff
-#define DSL_LINEMASK_GEN30x1fff
+#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
+#define PIPEDSL_LINE_MASKREG_GENMASK(19, 0)
#define _PIPEACONF 0x70008
#define PIPECONF_ENABLE (1 << 31)
#define PIPECONF_DISABLE 0
--
2.32.0
[Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines
From: Ville Syrjälä
Use REG_BIT() & co. for PIPEMISC* bits, and while at it
fill in the missing dithering bits since we already had some
of them defined.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
drivers/gpu/drm/i915/i915_reg.h | 35 +++-
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6073f94632ab..e293241450b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
switch (crtc_state->pipe_bpp) {
case 18:
- val |= PIPEMISC_6_BPC;
+ val |= PIPEMISC_BPC_6;
break;
case 24:
- val |= PIPEMISC_8_BPC;
+ val |= PIPEMISC_BPC_8;
break;
case 30:
- val |= PIPEMISC_10_BPC;
+ val |= PIPEMISC_BPC_10;
break;
case 36:
/* Port output 12BPC defined for ADLP+ */
if (DISPLAY_VER(dev_priv) > 12)
- val |= PIPEMISC_12_BPC_ADLP;
+ val |= PIPEMISC_BPC_12_ADLP;
break;
default:
MISSING_CASE(crtc_state->pipe_bpp);
@@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
}
intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
-PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+PIPE_MISC2_BUBBLE_COUNTER_MASK,
scaler_in_use ?
PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
}
@@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
switch (tmp & PIPEMISC_BPC_MASK) {
- case PIPEMISC_6_BPC:
+ case PIPEMISC_BPC_6:
return 18;
- case PIPEMISC_8_BPC:
+ case PIPEMISC_BPC_8:
return 24;
- case PIPEMISC_10_BPC:
+ case PIPEMISC_BPC_10:
return 30;
/*
* PORT OUTPUT 12 BPC defined for ADLP+.
@@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
* on older platforms, need to find a workaround for 12 BPC
* MIPI DSI HW readout.
*/
- case PIPEMISC_12_BPC_ADLP:
+ case PIPEMISC_BPC_12_ADLP:
if (DISPLAY_VER(dev_priv) > 12)
return 36;
fallthrough;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5d54ed2efc1..e300a202ce2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6308,32 +6308,35 @@ enum {
#define _PIPE_MISC_A 0x70030
#define _PIPE_MISC_B 0x71030
-#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
-#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
-#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
-#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
-#define PIPEMISC_PIXEL_ROUNDING_TRUNCREG_BIT(8) /* tgl+ */
+#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
+#define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
+#define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
+#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
+#define PIPEMISC_PIXEL_ROUNDING_TRUNCREG_BIT(8) /* tgl+ */
/*
* For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
* valid values of: 6, 8, 10 BPC.
* ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
* 6, 8, 10, 12 BPC.
*/
-#define PIPEMISC_BPC_MASK(7 << 5)
-#define PIPEMISC_8_BPC (0 << 5)
-#define PIPEMISC_10_BPC (1 << 5)
-#define PIPEMISC_6_BPC (2 << 5)
-#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
-#define PIPEMISC_DITHER_ENABLE (1 << 4)
-#define PIPEMISC_DITHER_TYPE_MASK(3 << 2)
-#define PIPEMISC_DITHER_TYPE_SP (0 << 2)
+#define PIPEMISC_BPC_MASKREG_GENMASK(7, 5)
+#define PIPEMISC_BPC_8
REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
+#define PIPEMISC_BPC_10
REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
+#define PIPEMISC_BPC_6
REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
+#define PIPEMISC_BPC_12_ADLP
REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
+#define PIPEMISC_DITHER_ENABLE REG_BIT(4)
+#define PIPEMISC_DITHER_TYPE_MASKREG_GENMASK(3, 2)
+#define PIPEMISC_DITHER_TYPE_SP
REG_FIELD_PREP(PIPEMISC_DITHER_
[Intel-gfx] [PATCH 8/9] drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits
From: Ville Syrjälä
Use REG_BIT() & co. for DPINVTT/VLV_DPFLIPSTAT bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 94 -
2 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index eb8c92324aee..1021f7ae0dda 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3013,7 +3013,7 @@ static void vlv_display_irq_reset(struct drm_i915_private
*dev_priv)
if (IS_CHERRYVIEW(dev_priv))
intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
else
- intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
+ intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV);
i915_hotplug_interrupt_update_locked(dev_priv, 0x, 0);
intel_uncore_write(uncore, PORT_HOTPLUG_STAT,
intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ba5ab277675..0ceb88828d93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6358,55 +6358,55 @@ enum {
#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE +
0x70028)
-#define PIPEB_LINE_COMPARE_INT_EN(1 << 29)
-#define PIPEB_HLINE_INT_EN (1 << 28)
-#define PIPEB_VBLANK_INT_EN (1 << 27)
-#define SPRITED_FLIP_DONE_INT_EN (1 << 26)
-#define SPRITEC_FLIP_DONE_INT_EN (1 << 25)
-#define PLANEB_FLIP_DONE_INT_EN (1 << 24)
-#define PIPE_PSR_INT_EN (1 << 22)
-#define PIPEA_LINE_COMPARE_INT_EN(1 << 21)
-#define PIPEA_HLINE_INT_EN (1 << 20)
-#define PIPEA_VBLANK_INT_EN (1 << 19)
-#define SPRITEB_FLIP_DONE_INT_EN (1 << 18)
-#define SPRITEA_FLIP_DONE_INT_EN (1 << 17)
-#define PLANEA_FLIPDONE_INT_EN (1 << 16)
-#define PIPEC_LINE_COMPARE_INT_EN(1 << 13)
-#define PIPEC_HLINE_INT_EN (1 << 12)
-#define PIPEC_VBLANK_INT_EN (1 << 11)
-#define SPRITEF_FLIPDONE_INT_EN (1 << 10)
-#define SPRITEE_FLIPDONE_INT_EN (1 << 9)
-#define PLANEC_FLIPDONE_INT_EN (1 << 8)
+#define PIPEB_LINE_COMPARE_INT_ENREG_BIT(29)
+#define PIPEB_HLINE_INT_EN REG_BIT(28)
+#define PIPEB_VBLANK_INT_EN REG_BIT(27)
+#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
+#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
+#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
+#define PIPE_PSR_INT_EN REG_BIT(22)
+#define PIPEA_LINE_COMPARE_INT_ENREG_BIT(21)
+#define PIPEA_HLINE_INT_EN REG_BIT(20)
+#define PIPEA_VBLANK_INT_EN REG_BIT(19)
+#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
+#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
+#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
+#define PIPEC_LINE_COMPARE_INT_ENREG_BIT(13)
+#define PIPEC_HLINE_INT_EN REG_BIT(12)
+#define PIPEC_VBLANK_INT_EN REG_BIT(11)
+#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
+#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
+#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
#define DPINVGTT _MMIO(VLV_DISPLAY_BASE +
0x7002c) /* VLV/CHV only */
-#define SPRITEF_INVALID_GTT_INT_EN (1 << 27)
-#define SPRITEE_INVALID_GTT_INT_EN (1 << 26)
-#define PLANEC_INVALID_GTT_INT_EN(1 << 25)
-#define CURSORC_INVALID_GTT_INT_EN (1 << 24)
-#define CURSORB_INVALID_GTT_INT_EN (1 << 23)
-#define CURSORA_INVALID_GTT_INT_EN (1 << 22)
-#define SPRITED_INVALID_GTT_INT_EN (1 << 21)
-#define SPRITEC_INVALID_GTT_INT_EN (1 << 20)
-#define PLANEB_INVALID_GTT_INT_EN(1 << 19)
-#define SPRITEB_INVALID_GTT_INT_EN (1 << 18)
-#define SPRITEA_INVALID_GTT_INT_EN (1 << 17)
-#define PLANEA_INVALID_GTT_INT_EN(1 << 16)
-#define DPINVGTT_EN_MASK 0xff
-#define DPINVGTT_EN_MASK_CHV 0xfff
-#define SPRITEF_INVALID_GTT_STATUS (1 << 11)
-#define SPRITEE_INVALID_GTT_STATUS (1 << 10)
-#define PLANEC_INVALID_GTT_STATUS(1 << 9)
-#define CURSORC_INVALID_GTT_STATUS (1 << 8)
-#define CURSORB_INVALID_GTT_STATUS (1 << 7)
-#define CURSORA_INVALID_GTT_STATUS (
[Intel-gfx] [PATCH 7/9] drm/i915: Clean up CRC register defines
From: Ville Syrjälä
Use REG_BIT() & co. for the CRC registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 77 ++---
1 file changed, 41 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 211e2b415e50..6ba5ab277675 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4393,47 +4393,52 @@ enum {
/* Pipe A CRC regs */
#define _PIPE_CRC_CTL_A0x60050
-#define PIPE_CRC_ENABLE (1 << 31)
+#define PIPE_CRC_ENABLE REG_BIT(31)
/* skl+ source selection */
-#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28)
-#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28)
-#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28)
-#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28)
-#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28)
-#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28)
-#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28)
-#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28)
+#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
+#define PIPE_CRC_SOURCE_PLANE_1_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
+#define PIPE_CRC_SOURCE_PLANE_2_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
+#define PIPE_CRC_SOURCE_DMUX_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
+#define PIPE_CRC_SOURCE_PLANE_3_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
+#define PIPE_CRC_SOURCE_PLANE_4_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
+#define PIPE_CRC_SOURCE_PLANE_5_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
+#define PIPE_CRC_SOURCE_PLANE_6_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
+#define PIPE_CRC_SOURCE_PLANE_7_SKL
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
/* ivb+ source selection */
-#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
-#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
-#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
+#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
+#define PIPE_CRC_SOURCE_PRIMARY_IVB
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
+#define PIPE_CRC_SOURCE_SPRITE_IVB
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
+#define PIPE_CRC_SOURCE_PF_IVB
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
/* ilk+ source selection */
-#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
-#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
-#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
-/* embedded DP port on the north display block, reserved on ivb */
-#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
-#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
+#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
+#define PIPE_CRC_SOURCE_PRIMARY_ILK
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
+#define PIPE_CRC_SOURCE_SPRITE_ILK
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
+#define PIPE_CRC_SOURCE_PIPE_ILK
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
+/* embedded DP port on the north display block */
+#define PIPE_CRC_SOURCE_PORT_A_ILK
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
+#define PIPE_CRC_SOURCE_FDI_ILK
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
/* vlv source selection */
-#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
-#define PIPE_CRC_SOURCE_HDMIB_VLV(1 << 27)
-#define PIPE_CRC_SOURCE_HDMIC_VLV(2 << 27)
+#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
+#define PIPE_CRC_SOURCE_PIPE_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
+#define PIPE_CRC_SOURCE_HDMIB_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
+#define PIPE_CRC_SOURCE_HDMIC_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
/* with DP port the pipe source is invalid */
-#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
-#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
-#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
+#define PIPE_CRC_SOURCE_DP_D_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
+#define PIPE_CRC_SOURCE_DP_B_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
+#define PIPE_CRC_SOURCE_DP_C_VLV
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
/* gen3+ source selection */
-#define PIPE_CRC_SOURCE_PIPE_I9XX(0 << 28)
-#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
-#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
+#define PIPE_CRC_SOURCE_MASK_I9XXREG_GENMASK(30, 28)
+#define PIPE_CRC_SOURCE_PIPE_I9XX
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
+#define PIPE_CRC_SOURCE_SDVOB_I9XX
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
+#define PIPE_CRC_SOURCE_SDVOC_I9XX
REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
/* with DP/TV port the pipe source is invalid */
-#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
-#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
-#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
-#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
-#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
+#define PIPE_CRC_SOURCE_DP_D_G4X
REG_FIELD_PREP
[Intel-gfx] [PATCH 9/9] drm/i915: Clean up FPGA_DBG/CLAIM_ER bits
From: Ville Syrjälä Use REG_BIT() & co. for FPGA_DBG/CLAIM_ER bits. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0ceb88828d93..a4d6bd380012 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2821,12 +2821,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) #define FPGA_DBG _MMIO(0x42300) -#define FPGA_DBG_RM_NOCLAIM (1 << 31) +#define FPGA_DBG_RM_NOCLAIM REG_BIT(31) #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) -#define CLAIM_ER_CLR (1 << 31) -#define CLAIM_ER_OVERFLOW(1 << 16) -#define CLAIM_ER_CTR_MASK0x +#define CLAIM_ER_CLR REG_BIT(31) +#define CLAIM_ER_OVERFLOWREG_BIT(16) +#define CLAIM_ER_CTR_MASKREG_GENMASK(15, 0) #define DERRMR _MMIO(0x44050) /* Note that HBLANK events are reserved on bdw+ */ -- 2.32.0
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev2) URL : https://patchwork.freedesktop.org/series/96855/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10876_full -> Patchwork_21577_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21577_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21577_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21577_full: ### IGT changes ### Possible regressions * igt@gem_spin_batch@legacy@blt: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-skl7/igt@gem_spin_batch@leg...@blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-skl2/igt@gem_spin_batch@leg...@blt.html Known issues Here are the changes found in Patchwork_21577_full that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@eof: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-skl1/igt@fb...@eof.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-skl10/igt@fb...@eof.html * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#3002]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-apl7/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][6] ([i915#180]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-kbl4/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl7/igt@gem_ctx_isolation@preservation...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-apl3/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#2481] / [i915#3070]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-iclb8/igt@gem_...@unwedge-stress.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-iclb6/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][11] ([i915#2369]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-skl4/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-tglb2/igt@gem_exec_fair@basic-none-r...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-apl6/igt@gem_exec_fair@basic-n...@vcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-glk7/igt@gem_exec_fair@basic-throt...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-glk1/igt@gem_exec_fair@basic-throt...@rcs0.html - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2849]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10876/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21577/shard-iclb3/igt@gem_exec_f
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
== Series Details == Series: drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset URL : https://patchwork.freedesktop.org/series/96867/ State : warning == Summary == $ dim checkpatch origin/drm-tip e2320f3454d5 drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset -:42: WARNING:LONG_LINE_COMMENT: line length of 101 exceeds 100 columns #42: FILE: drivers/gpu/drm/i915/display/intel_display.c:1582: +* Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. total: 0 errors, 1 warnings, 0 checks, 55 lines checked
Re: [Intel-gfx] [PATCH 0/2] Nuke PAGE_KERNEL_IO
On Fri, Nov 12, 2021 at 08:04:03PM +0100, Peter Zijlstra wrote: On Thu, Oct 21, 2021 at 11:15:09AM -0700, Lucas De Marchi wrote: Last user of PAGE_KERNEL_IO is the i915 driver. While removing it from there as we seek to bring the driver to other architectures, Daniel suggested that we could finish the cleanup and remove it altogether, through the tip tree. So here I'm sending both commits needed for that. Lucas De Marchi (2): drm/i915/gem: stop using PAGE_KERNEL_IO x86/mm: nuke PAGE_KERNEL_IO arch/x86/include/asm/fixmap.h | 2 +- arch/x86/include/asm/pgtable_types.h | 7 --- arch/x86/mm/ioremap.c | 2 +- arch/x86/xen/setup.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++-- include/asm-generic/fixmap.h | 2 +- 6 files changed, 6 insertions(+), 13 deletions(-) Acked-by: Peter Zijlstra (Intel) thanks, Peter. The intention was to merge this through the tip tree. Although now I'm not sure. Options: 1) take the first patch through the drm-intel tree and apply the second patch later 2) take everything through the drm tree 3) take everything through the tip tree What's your preference here? Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
== Series Details == Series: drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset URL : https://patchwork.freedesktop.org/series/96867/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH 0/2] Nuke PAGE_KERNEL_IO
On 11/12/21 12:09 PM, Lucas De Marchi wrote: > The intention was to merge this through the tip tree. Although now I'm > not sure. Options: > > 1) take the first patch through the drm-intel tree and apply the > second patch later > 2) take everything through the drm tree > 3) take everything through the tip tree > > What's your preference here? It's fine with me to take it through tip unless that causes a problem for anyone. I was planning on doing queuing it after -rc1.
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
== Series Details == Series: drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset URL : https://patchwork.freedesktop.org/series/96867/ State : success == Summary == CI Bug Log - changes from CI_DRM_10877 -> Patchwork_21578 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/index.html Participating hosts (30 -> 28) -- Additional (1): fi-skl-6700k2 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21578 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_huc_copy@huc-copy: - fi-skl-6700k2: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-6700k2: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/fi-skl-6700k2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][5] ([i915#4269]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_10877 -> Patchwork_21578 CI-20190529: 20190529 CI_DRM_10877: 688d3ea17a90b4acf51de31ef08cd2b23799952e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21578: e2320f3454d596cfa22b211fea730debd127f67d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e2320f3454d5 drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Register define cleanups
== Series Details == Series: drm/i915: Register define cleanups URL : https://patchwork.freedesktop.org/series/96868/ State : warning == Summary == $ dim checkpatch origin/drm-tip 07e09e2bbe21 drm/i915: Bump DSL linemask to 20 bits d6e456b58dab drm/i915: Clean up PIPEMISC register defines 972a671d657e drm/i915: Clean up SKL_BOTTOM_COLOR defines 0a60b5b4e2d5 drm/i915: Clean up PIPECONF bit defines -:347: WARNING:LONG_LINE: line length of 119 exceeds 100 columns #347: FILE: drivers/gpu/drm/i915/i915_reg.h:6176: +#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ -:354: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns #354: FILE: drivers/gpu/drm/i915/i915_reg.h:6183: +#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ -:355: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns #355: FILE: drivers/gpu/drm/i915/i915_reg.h:6184: +#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ -:356: WARNING:LONG_LINE_COMMENT: line length of 129 exceeds 100 columns #356: FILE: drivers/gpu/drm/i915/i915_reg.h:6185: +#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ -:359: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns #359: FILE: drivers/gpu/drm/i915/i915_reg.h:6188: +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ -:360: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns #360: FILE: drivers/gpu/drm/i915/i915_reg.h:6189: +#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ -:362: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns #362: FILE: drivers/gpu/drm/i915/i915_reg.h:6191: +#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ -:372: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #372: FILE: drivers/gpu/drm/i915/i915_reg.h:6201: +#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ -:373: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns #373: FILE: drivers/gpu/drm/i915/i915_reg.h:6202: +#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ -:379: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns #379: FILE: drivers/gpu/drm/i915/i915_reg.h:6208: +#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ -:380: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns #380: FILE: drivers/gpu/drm/i915/i915_reg.h:6209: +#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ -:381: WARNING:LONG_LINE_COMMENT: line length of 112 exceeds 100 columns #381: FILE: drivers/gpu/drm/i915/i915_reg.h:6210: +#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ total: 0 errors, 12 warnings, 0 checks, 340 lines checked 0a96d6cd3a6a drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines -:82: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns #82: FILE: drivers/gpu/drm/i915/i915_reg.h:9000: +#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ total: 0 errors, 1 warnings, 0 checks, 104 lines checked 9f255d46dcb8 drm/i915: Clean up PIPESRC defines 8a7681e19c01 drm/i915: Clean up CRC register defines 1b63beb57cdd drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits f89511a6ac52 drm/i915: Clean up FPGA_DBG/CLAIM_ER bits
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Register define cleanups
== Series Details == Series: drm/i915: Register define cleanups URL : https://patchwork.freedesktop.org/series/96868/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Increase the live_engine_busy_stats sample period
On Thu, Nov 11, 2021 at 06:52:22PM -0800, Umesh Nerlige Ramappa wrote: > Irrespective of the backend for request submissions, busyness for an > engine with an active context is calculated using: > > busyness = total + (current_time - context_switch_in_time) > > In execlists mode of operation, the context switch events are handled > by the CPU. Context switch in/out time and current_time are captured > in CPU time domain using ktime_get(). > > In GuC mode of submission, context switch events are handled by GuC and > the times in the above formula are captured in GT clock domain. This > information is shared with the CPU through shared memory. This results > in 2 caveats: > > 1) The time taken between start of a batch and the time that CPU is able > to see the context_switch_in_time in shared memory is dependent on GuC > and memory bandwidth constraints. > > 2) Determining current_time requires an MMIO read that can take anywhere > between a few us to a couple ms. A reference CPU time is captured soon > after reading the MMIO so that the caller can compare the cpu delta > between 2 busyness samples. The issue here is that the CPU delta and the > busyness delta can be skewed because of the time taken to read the > register. > > These 2 factors affect the accuracy of the selftest - > live_engine_busy_stats. For (1) the selftest waits until busyness stats > are visible to the CPU. The effects of (2) are more prominent for the > current busyness sample period of 100 us. Increase the busyness sample > period from 100 us to 10 ms to overccome (2). > > Signed-off-by: Umesh Nerlige Ramappa Explaination of increased wait period makes sense to me. With that: Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index 0bfd738dbf3a..96cc565afa78 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -316,7 +316,7 @@ static int live_engine_busy_stats(void *arg) > ENGINE_TRACE(engine, "measuring busy time\n"); > preempt_disable(); > de = intel_engine_get_busy_time(engine, &t[0]); > - udelay(100); > + udelay(1); > de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); > preempt_enable(); > dt = ktime_sub(t[1], t[0]); > -- > 2.20.1 >
Re: [Intel-gfx] [PATCH 0/2] Nuke PAGE_KERNEL_IO
On 10/21/21 11:15, Lucas De Marchi wrote: Last user of PAGE_KERNEL_IO is the i915 driver. While removing it from there as we seek to bring the driver to other architectures, Daniel suggested that we could finish the cleanup and remove it altogether, through the tip tree. So here I'm sending both commits needed for that. Lucas De Marchi (2): drm/i915/gem: stop using PAGE_KERNEL_IO x86/mm: nuke PAGE_KERNEL_IO arch/x86/include/asm/fixmap.h | 2 +- arch/x86/include/asm/pgtable_types.h | 7 --- arch/x86/mm/ioremap.c | 2 +- arch/x86/xen/setup.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++-- include/asm-generic/fixmap.h | 2 +- 6 files changed, 6 insertions(+), 13 deletions(-) Acked-by: Andy Lutomirski
[Intel-gfx] [PATCH 2/3] drm/i915/rpl-s: Add PCH ID
Add the PCH ID for the same.
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_pch.c | 1 +
drivers/gpu/drm/i915/intel_pch.h | 1 +
include/drm/i915_pciids.h| 5 -
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index d1d4b97b86f5..da8f82c2342f 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -129,6 +129,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
return PCH_JSP;
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
+ case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
!IS_ALDERLAKE_P(dev_priv));
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 7c0d83d292dc..6bff77521094 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -57,6 +57,7 @@ enum intel_pch {
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80
#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180
+#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 00deb011b74c..0e112f56a9a8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -675,6 +675,9 @@
INTEL_VGA_DEVICE(0xA788, info), \
INTEL_VGA_DEVICE(0xA789, info), \
INTEL_VGA_DEVICE(0xA78A, info), \
- INTEL_VGA_DEVICE(0xA78B, info)
+ INTEL_VGA_DEVICE(0xA78B, info), \
+ INTEL_VGA_DEVICE(0x4690, info), \
+ INTEL_VGA_DEVICE(0x4692, info), \
+ INTEL_VGA_DEVICE(0x4693, info)
#endif /* _I915_PCIIDS_H */
--
2.25.1
[Intel-gfx] [PATCH 3/3] drm/i915/rpl-s: Enable guc submission by default
Though, RPL-S is defined as subplatform of ADL-S, unlike
ADL-S, it has GuC submission by default.
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 2fef3b0bbe95..7088f5370e7f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -35,7 +35,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
}
/* Intermediate platforms are HuC authentication only */
- if (IS_ALDERLAKE_S(i915)) {
+ if ((IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915))) {
i915->params.enable_guc = ENABLE_GUC_LOAD_HUC;
return;
}
--
2.25.1
[Intel-gfx] [PATCH 0/3] Introduce Raptor Lake S
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S). The series introduces it as a subplatform of ADL-S. The one difference is the GuC submission which is default on RPL-S but was not the case with ADL-S. Anusha Srivatsa (3): drm/i915/rpl-s: Add PCI IDS drm/i915/rpl-s: Add PCH ID drm/i915/rpl-s: Enable guc submission by default arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.c | 7 +++ drivers/gpu/drm/i915/intel_device_info.h | 3 +++ drivers/gpu/drm/i915/intel_pch.c | 1 + drivers/gpu/drm/i915/intel_pch.h | 1 + include/drm/i915_pciids.h| 14 ++ 9 files changed, 31 insertions(+), 1 deletion(-) -- 2.25.1
[Intel-gfx] [PATCH 1/3] drm/i915/rpl-s: Add PCI IDS
Adding PCI ids for RPL-S. Introducing RPL-S as a
subplatform of ADL-S. From graphics POV,RPL-S is
the same as ADL-S.
BSpec: 53655
Cc: Matt Roper
Cc: Swathi Dhanavanthri
Signed-off-by: Anusha Srivatsa
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 7 +++
drivers/gpu/drm/i915/intel_device_info.h | 3 +++
include/drm/i915_pciids.h| 11 +++
6 files changed, 25 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 391a4e2b8604..fd2d3ab38ebb 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -554,6 +554,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
INTEL_ADLP_IDS(&gen11_early_ops),
+ INTEL_RPLS_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0,
0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 21ff781b8149..406b9204d34b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1470,6 +1470,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
+#define IS_RAPTORLAKE_S(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e6795853dc3..9c33ae887f2e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1117,6 +1117,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_ADLS_IDS(&adl_s_info),
INTEL_ADLP_IDS(&adl_p_info),
INTEL_DG1_IDS(&dg1_info),
+ INTEL_RPLS_IDS(&adl_s_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 6e6b317bc33c..565b50c3f34f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,6 +182,10 @@ static const u16 subplatform_portf_ids[] = {
INTEL_ICL_PORT_F_IDS(0),
};
+static const u16 subplatform_rpl_ids[] = {
+ INTEL_RPLS_IDS(0),
+};
+
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -218,6 +222,9 @@ void intel_device_info_subplatform_init(struct
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_portf_ids,
ARRAY_SIZE(subplatform_portf_ids))) {
mask = BIT(INTEL_SUBPLATFORM_PORTF);
+ } else if (find_devid(devid, subplatform_rpl_ids,
+ ARRAY_SIZE(subplatform_rpl_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_RPL);
}
if (IS_TIGERLAKE(i915)) {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 669f0d26c3c3..186e773fd0da 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -110,6 +110,9 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_G10 0
#define INTEL_SUBPLATFORM_G11 1
+/* RPL */
+#define INTEL_SUBPLATFORM_RPL 0
+
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index c00ac54692d7..00deb011b74c 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -666,4 +666,15 @@
INTEL_VGA_DEVICE(0x46C2, info), \
INTEL_VGA_DEVICE(0x46C3, info)
+/* RPL-S */
+#define INTEL_RPLS_IDS(info) \
+ INTEL_VGA_DEVICE(0xA780, info), \
+ INTEL_VGA_DEVICE(0xA781, info), \
+ INTEL_VGA_DEVICE(0xA782, info), \
+ INTEL_VGA_DEVICE(0xA783, info), \
+ INTEL_VGA_DEVICE(0xA788, info), \
+ INTEL_VGA_DEVICE(0xA789, info), \
+ INTEL_VGA_DEVICE(0xA78A, info), \
+ INTEL_VGA_DEVICE(0xA78B, info)
+
#endif /* _I915_PCIIDS_H */
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Register define cleanups
== Series Details == Series: drm/i915: Register define cleanups URL : https://patchwork.freedesktop.org/series/96868/ State : success == Summary == CI Bug Log - changes from CI_DRM_10877 -> Patchwork_21579 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/index.html Participating hosts (30 -> 29) -- Additional (2): fi-skl-6700k2 fi-pnv-d510 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21579 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_huc_copy@huc-copy: - fi-skl-6700k2: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-6700k2: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-skl-6700k2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +53 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/fi-pnv-d510/igt@prime_v...@basic-userptr.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_10877 -> Patchwork_21579 CI-20190529: 20190529 CI_DRM_10877: 688d3ea17a90b4acf51de31ef08cd2b23799952e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21579: f89511a6ac520ed572057ab4153692b6c59cb1d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f89511a6ac52 drm/i915: Clean up FPGA_DBG/CLAIM_ER bits 1b63beb57cdd drm/i915: Clean up DPINVGTT/VLV_DPFLIPSTAT bits 8a7681e19c01 drm/i915: Clean up CRC register defines 9f255d46dcb8 drm/i915: Clean up PIPESRC defines 0a96d6cd3a6a drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines 0a60b5b4e2d5 drm/i915: Clean up PIPECONF bit defines 972a671d657e drm/i915: Clean up SKL_BOTTOM_COLOR defines d6e456b58dab drm/i915: Clean up PIPEMISC register defines 07e09e2bbe21 drm/i915: Bump DSL linemask to 20 bits == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/index.html
Re: [Intel-gfx] [PATCH] drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
On Fri, Nov 12, 2021 at 09:09:04PM +0200, Imre Deak wrote:
> After a non-blocking modeset on a TypeC port's CRTC - possibly blocked
> later in drm_atomic_helper_wait_for_dependencies() - a fastset on the
> same CRTC may copy the state of CRTC before this gets updated to reflect
> the up-to-date DP-alt vs. TBT-alt TypeC mode DPLL used for the CRTC. In
> this case after the first (non-blocking) commit completes enabling the
> DPLL required for the up-to-date TypeC mode the following fastset will
> update the CRTC state pointing to the wrong DPLL. A subsequent disabling
> modeset will try to disable the wrong PLL, triggering a state checker
> WARN (and leaving the DPLL which is actually used active for good).
>
> Fix the above race by copying the DPLL state for fastset CRTCs from the
> old CRTC state at the point where it's guaranteed to be up-to-date
> already. This could be handled in the encoder's update_prepare() hook as
> well, but that's a bigger change, which is better done as a follow-up.
>
> Testcase: igt/kms_busy/extended-modeset-hang-newfb-with-reset
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4308
> Cc: Ville Syrjala
> Signed-off-by: Imre Deak
This is getting a bit unpleasant. Maybe we should just get rid of
shared_dpll entirely and track the currently active pll entirely
elsewhere, I guess maybe in intel_crtc? That would at least make it
a bit more clear that it's no longer your normal pre-computed state
thing. Though that would have some implications for state readout,
so might turn a bit hairy as well. Dunno.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 25
> 1 file changed, 20 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ceee8ac66717..76ebb3c91a75b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1572,10 +1572,24 @@ intel_connector_primary_encoder(struct
> intel_connector *connector)
>
> static void intel_encoders_update_prepare(struct intel_atomic_state *state)
> {
> + struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> + struct intel_crtc *crtc;
> struct drm_connector_state *new_conn_state;
> struct drm_connector *connector;
> int i;
>
> + /*
> + * Make sure the DPLL state is up-to-date for fastset TypeC ports after
> non-blocking commits.
> + * TODO: Update the DPLL state for all cases in the
> encoder->update_prepare() hook.
> + */
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> + if (!intel_crtc_needs_modeset(new_crtc_state))
> + new_crtc_state->shared_dpll =
> old_crtc_state->shared_dpll;
> + }
Don't we want to copy the pll state as well?
> +
> + if (!state->modeset)
> + return;
> +
> for_each_new_connector_in_state(&state->base, connector, new_conn_state,
> i) {
> struct intel_connector *intel_connector;
> @@ -1602,6 +1616,9 @@ static void intel_encoders_update_complete(struct
> intel_atomic_state *state)
> struct drm_connector *connector;
> int i;
>
> + if (!state->modeset)
> + return;
> +
> for_each_new_connector_in_state(&state->base, connector, new_conn_state,
> i) {
> struct intel_connector *intel_connector;
> @@ -8670,8 +8687,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
> }
>
> - if (state->modeset)
> - intel_encoders_update_prepare(state);
> + intel_encoders_update_prepare(state);
>
> intel_dbuf_pre_plane_update(state);
>
> @@ -8683,11 +8699,10 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display->commit_modeset_enables(state);
>
> - if (state->modeset) {
> - intel_encoders_update_complete(state);
> + intel_encoders_update_complete(state);
>
> + if (state->modeset)
> intel_set_cdclk_post_plane_update(state);
> - }
>
> intel_wait_for_vblank_workers(state);
>
> --
> 2.27.0
--
Ville Syrjälä
Intel
[Intel-gfx] [PATCH] drm/i915/dp: Perform 30ms delay after source OUI write
While working on supporting the Intel HDR backlight interface, I noticed
that there's a couple of laptops that will very rarely manage to boot up
without detecting Intel HDR backlight support - even though it's supported
on the system. One example of such a laptop is the Lenovo P17 1st
generation.
Following some investigation Ville Syrjälä did through the docs they have
available to them, they discovered that there's actually supposed to be a
30ms wait after writing the source OUI before we begin setting up the rest
of the backlight interface.
This seems to be correct, as adding this 30ms delay seems to have
completely fixed the probing issues I was previously seeing. So - let's
start performing a 30ms wait after writing the OUI, which we do in a manner
similar to how we keep track of PPS delays (e.g. record the timestamp of
the OUI write, and then wait for however many ms are left since that
timestamp right before we interact with the backlight) in order to avoid
waiting any longer then we need to. As well, this also avoids us performing
this delay on systems where we don't end up using the HDR backlight
interface.
Signed-off-by: Lyude Paul
Fixes: 4a8d79901d5b ("drm/i915/dp: Enable Intel's HDR backlight interface (only
SDR for now)")
Cc: Ville Syrjälä
Cc: # v5.12+
---
drivers/gpu/drm/i915/display/intel_display_types.h| 3 +++
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 11 +++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index ea1e8a6e10b0..b9c967837872 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1653,6 +1653,9 @@ struct intel_dp {
struct intel_dp_pcon_frl frl;
struct intel_psr psr;
+
+ /* When we last wrote the OUI for eDP */
+ unsigned long last_oui_write;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0a424bf69396..77d9a9390c1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include
#include
@@ -2010,6 +2011,8 @@ intel_edp_init_source_oui(struct intel_dp *intel_dp, bool
careful)
if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui))
< 0)
drm_err(&i915->drm, "Failed to write source OUI\n");
+
+ intel_dp->last_oui_write = jiffies;
}
/* If the device supports it, try to set the power state appropriately */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 569d17b4d00f..2c35b999ec2c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -96,6 +96,13 @@
#define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_10x359
/* Intel EDP backlight callbacks */
+static void
+wait_for_oui(struct drm_i915_private *i915, struct intel_dp *intel_dp)
+{
+ drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
+ wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
+}
+
static bool
intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
{
@@ -106,6 +113,8 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector
*connector)
int ret;
u8 tcon_cap[4];
+ wait_for_oui(i915, intel_dp);
+
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap,
sizeof(tcon_cap));
if (ret != sizeof(tcon_cap))
return false;
@@ -204,6 +213,8 @@ intel_dp_aux_hdr_enable_backlight(const struct
intel_crtc_state *crtc_state,
int ret;
u8 old_ctrl, ctrl;
+ wait_for_oui(i915, intel_dp);
+
ret = drm_dp_dpcd_readb(&intel_dp->aux,
INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
if (ret != 1) {
drm_err(&i915->drm, "Failed to read current backlight control
mode: %d\n", ret);
--
2.31.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Raptor Lake S
== Series Details == Series: Introduce Raptor Lake S URL : https://patchwork.freedesktop.org/series/96869/ State : warning == Summary == $ dim checkpatch origin/drm-tip 47ee6a9cad2e drm/i915/rpl-s: Add PCI IDS -:100: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #100: FILE: include/drm/i915_pciids.h:670: +#define INTEL_RPLS_IDS(info) \ + INTEL_VGA_DEVICE(0xA780, info), \ + INTEL_VGA_DEVICE(0xA781, info), \ + INTEL_VGA_DEVICE(0xA782, info), \ + INTEL_VGA_DEVICE(0xA783, info), \ + INTEL_VGA_DEVICE(0xA788, info), \ + INTEL_VGA_DEVICE(0xA789, info), \ + INTEL_VGA_DEVICE(0xA78A, info), \ + INTEL_VGA_DEVICE(0xA78B, info) -:100: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #100: FILE: include/drm/i915_pciids.h:670: +#define INTEL_RPLS_IDS(info) \ + INTEL_VGA_DEVICE(0xA780, info), \ + INTEL_VGA_DEVICE(0xA781, info), \ + INTEL_VGA_DEVICE(0xA782, info), \ + INTEL_VGA_DEVICE(0xA783, info), \ + INTEL_VGA_DEVICE(0xA788, info), \ + INTEL_VGA_DEVICE(0xA789, info), \ + INTEL_VGA_DEVICE(0xA78A, info), \ + INTEL_VGA_DEVICE(0xA78B, info) total: 1 errors, 0 warnings, 1 checks, 65 lines checked ad883b7bc4b6 drm/i915/rpl-s: Add PCH ID 5560fe514f56 drm/i915/rpl-s: Enable guc submission by default
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Raptor Lake S
== Series Details == Series: Introduce Raptor Lake S URL : https://patchwork.freedesktop.org/series/96869/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:28:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:33:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:51:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:57:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1399:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Introduce Raptor Lake S
== Series Details == Series: Introduce Raptor Lake S URL : https://patchwork.freedesktop.org/series/96869/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
Re: [Intel-gfx] [PATCH v4 12/14] dt-bindings: msm/dp: Add bindings for HDCP registers
On Thu, Nov 04, 2021 at 11:04:29PM -0400, Sean Paul wrote: > From: Sean Paul > > This patch adds the bindings for the MSM DisplayPort HDCP registers > which are required to write the HDCP key into the display controller as > well as the registers to enable HDCP authentication/key > exchange/encryption. > > We'll use a new compatible string for this since the fields are optional. > > Cc: Rob Herring > Cc: Stephen Boyd > Signed-off-by: Sean Paul > Link: > https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-13-s...@poorly.run > #v1 > Link: > https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-13-s...@poorly.run > #v2 > Link: > https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-13-s...@poorly.run > #v3 > > Changes in v2: > -Drop register range names (Stephen) > -Fix yaml errors (Rob) > Changes in v3: > -Add new compatible string for dp-hdcp > -Add descriptions to reg > -Add minItems/maxItems to reg > -Make reg depend on the new hdcp compatible string > Changes in v4: > -Rebase on Bjorn's multi-dp patchset > --- > .../devicetree/bindings/display/msm/dp-controller.yaml| 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index b36d74c1da7c..f6e4b102373a 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -21,12 +21,16 @@ properties: >- qcom,sc8180x-edp > >reg: > +minItems: 5 > +maxItems: 7 This should be a warning. Not sure why the bot didn't run. You just need 'minItems: 5' > items: >- description: ahb register block >- description: aux register block >- description: link register block >- description: p0 register block >- description: p1 register block > + - description: (Optional) Registers for HDCP device key injection > + - description: (Optional) Registers for HDCP TrustZone interaction > >interrupts: > maxItems: 1 > @@ -111,7 +115,9 @@ examples: ><0xae90200 0x200>, ><0xae90400 0xc00>, ><0xae91000 0x400>, > - <0xae91400 0x400>; > + <0xae91400 0x400>, > + <0x0aed1000 0x174>, > + <0x0aee1000 0x2c>; Be consistent and drop the leading 0. > interrupt-parent = <&mdss>; > interrupts = <12>; > clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > -- > Sean Paul, Software Engineer, Google / Chromium OS > >
Re: [Intel-gfx] [PATCH] drm/i915: Skip remap_io_mapping() for non-x86 platforms
On Fri, 12 Nov 2021, Mullati Siva wrote:
> The _PAGE_CACHE_MASK macro is not defined in non-x86
> architectures and it's been used in remap_io_mapping().
> Only hw that supports mappable aperture would hit this path
> remap_io_mapping(), So skip this code for non-x86 architectures.
Patch changelog goes here.
> Signed-off-by: Mullati Siva
> ---
> drivers/gpu/drm/i915/i915_mm.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c
> index 666808cb3a32..d76feeaf3fd1 100644
> --- a/drivers/gpu/drm/i915/i915_mm.c
> +++ b/drivers/gpu/drm/i915/i915_mm.c
> @@ -91,6 +91,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
>unsigned long addr, unsigned long pfn, unsigned long size,
>struct io_mapping *iomap)
> {
> +#if IS_ENABLED(CONFIG_X86)
My feedback to the previous version was:
Please don't add conditional compilation within functions.
I mean it.
> struct remap_pfn r;
> int err;
>
> @@ -108,6 +109,7 @@ int remap_io_mapping(struct vm_area_struct *vma,
> zap_vma_ptes(vma, addr, (r.pfn - pfn) << PAGE_SHIFT);
> return err;
> }
> +#endif
>
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Raptor Lake S
== Series Details == Series: Introduce Raptor Lake S URL : https://patchwork.freedesktop.org/series/96869/ State : success == Summary == CI Bug Log - changes from CI_DRM_10877 -> Patchwork_21580 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/index.html Participating hosts (30 -> 29) -- Additional (2): fi-skl-6700k2 fi-pnv-d510 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21580 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_ctx_create@basic: - fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-pnv-d510/igt@gem_ctx_cre...@basic.html * igt@gem_exec_parallel@engines@userptr: - fi-pnv-d510:NOTRUN -> [INCOMPLETE][3] ([i915#299]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-pnv-d510/igt@gem_exec_parallel@engi...@userptr.html * igt@gem_huc_copy@huc-copy: - fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][5] -> [INCOMPLETE][6] ([i915#2940]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-6700k2: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6700k2: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-skl-6700k2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-pnv-d510:NOTRUN -> [FAIL][9] ([i915#2403] / [i915#2722] / [i915#4312]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-pnv-d510/igt@run...@aborted.html - fi-bsw-nick:NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/fi-bsw-nick/igt@run...@aborted.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_10877 -> Patchwork_21580 CI-20190529: 20190529 CI_DRM_10877: 688d3ea17a90b4acf51de31ef08cd2b23799952e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21580: 5560fe514f56b4d9f6a539d7c0b75ca6ccee488e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5560fe514f56 drm/i915/rpl-s: Enable guc submission by default ad883b7bc4b6 drm/i915/rpl-s: Add PCH ID 47ee6a9cad2e drm/i915/rpl-s: Add PCI IDS == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21580/index.html
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/dp: Perform 30ms delay after source OUI write
== Series Details == Series: drm/i915/dp: Perform 30ms delay after source OUI write URL : https://patchwork.freedesktop.org/series/96871/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Function parameter or member 'fbc' not described in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:635: warning: Excess function parameter 'i915' description in 'intel_fbc_is_active' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Function parameter or member 'fbc' not described in 'intel_fbc_handle_fifo_underrun_irq' ./drivers/gpu/drm/i915/display/intel_fbc.c:1638: warning: Excess function parameter 'i915' description in 'intel_fbc_handle_fifo_underrun_irq'
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset
== Series Details == Series: drm/i915: Fix fastsets on TypeC ports following a non-blocking modeset URL : https://patchwork.freedesktop.org/series/96867/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10877_full -> Patchwork_21578_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21578_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21578_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21578_full: ### IGT changes ### Possible regressions * igt@perf_pmu@busy-start@rcs0: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb5/igt@perf_pmu@busy-st...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-tglb8/igt@perf_pmu@busy-st...@rcs0.html Known issues Here are the changes found in Patchwork_21578_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-apl3/igt@gem_cre...@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#2369] / [i915#3063] / [i915#3648]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb5/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-tglb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][6] -> [INCOMPLETE][7] ([i915#2369]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-skl10/igt@gem_exec_capture@p...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-skl2/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][8] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-skl8/igt@gem_exec_f...@basic-deadline.html - shard-apl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-apl4/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842] / [i915#3468]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-apl7/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-tglb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-tglb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#2842]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-kbl: [PASS][19] -> [SKIP][20] ([fdo#109271]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-kbl2/igt@gem_exec_fair@basic-s...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-kbl6/igt@gem_exec_fair@basic-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2849]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21578/shard-ic
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Perform 30ms delay after source OUI write
== Series Details == Series: drm/i915/dp: Perform 30ms delay after source OUI write URL : https://patchwork.freedesktop.org/series/96871/ State : success == Summary == CI Bug Log - changes from CI_DRM_10877 -> Patchwork_21581 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/index.html Participating hosts (30 -> 29) -- Additional (2): fi-skl-6700k2 fi-pnv-d510 Missing(3): fi-bsw-cyan bat-dg1-6 bat-dg1-5 Known issues Here are the changes found in Patchwork_21581 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_huc_copy@huc-copy: - fi-skl-6700k2: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-skl-6700k2/igt@gem_huc_c...@huc-copy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-6700k2: NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#533]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-skl-6700k2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +53 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-pnv-d510/igt@prime_v...@basic-userptr.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][6] ([i915#4269]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_10877 -> Patchwork_21581 CI-20190529: 20190529 CI_DRM_10877: 688d3ea17a90b4acf51de31ef08cd2b23799952e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6280: 246bfd31dba6bf184b26b170d91d72c90a54be6b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21581: 56dd8cd7dadd44a32e1339993802920b322f1dad @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 56dd8cd7dadd drm/i915/dp: Perform 30ms delay after source OUI write == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21581/index.html
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Register define cleanups
== Series Details == Series: drm/i915: Register define cleanups URL : https://patchwork.freedesktop.org/series/96868/ State : success == Summary == CI Bug Log - changes from CI_DRM_10877_full -> Patchwork_21579_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21579_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50]) ([i915#4392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10877/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk1/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk2/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk6/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21579/shard-glk5/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patch
Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE
On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote:
> Certain functions within i915 uses macros that are defined for
> specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
> (Some architectures don't even have these macros defined, like ARM64).
>
> Instead of re-using bits defined for the CPU, we should use bits
> defined for i915. This patch introduces two new macros,
> I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
> replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
On older platforms we already had our own definition of GEN6_PTE_VALID
(the spec uses "present" and "valid" interchangeably) which we were
using to encode our ggtt ptes up through HSW; it might be better to go
back to using that rather than adding a new define.
It looks like BYT is when the writable bit showed up, and we did add a
new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we
switched over to using the CPU page table flags instead and never used
it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE
as well.
>
> Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
> same throughout the generations.
This last sentence seems a bit confusing --- it's true that bit 0 has
always been a present/valid flag, but bit 1 wasn't a writable bit until
BYT; there just wasn't a writable bit at all (e.g., bspec page 229).
It might be worth tossing a few bspec references on the commit message
here, just for future reference. E.g.,
Bspec: 253, 45039
Matt
>
> Signed-off-by: Michael Cheng
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
> drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
> 4 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 9966e9dc5218..f89b50ffc286 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -18,7 +18,7 @@
> static u64 gen8_pde_encode(const dma_addr_t addr,
> const enum i915_cache_level level)
> {
> - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
> + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
>
> if (level != I915_CACHE_NONE)
> pde |= PPAT_CACHED_PDE;
> @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> u32 flags)
> {
> - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
> + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
>
> if (unlikely(flags & PTE_READ_ONLY))
> - pte &= ~_PAGE_RW;
> + pte &= ~I915_PAGE_RW;
>
> if (flags & PTE_LM)
> pte |= GEN12_PPGTT_PTE_LM;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 1fb4a03d7ac3..3f8e1ee0fbfa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>enum i915_cache_level level,
>u32 flags)
> {
> - gen8_pte_t pte = addr | _PAGE_PRESENT;
> + gen8_pte_t pte = addr | I915_PAGE_PRESENT;
>
> if (flags & PTE_LM)
> pte |= GEN12_GGTT_PTE_LM;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index dfeaef680aac..fba9c0c18f4a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -39,6 +39,9 @@
>
> #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for preallocation
> */
>
> +#define I915_PAGE_PRESENT BIT_ULL(0)
> +#define I915_PAGE_RW BIT_ULL(1)
> +
> #define I915_GTT_PAGE_SIZE_4KBIT_ULL(12)
> #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
> #define I915_GTT_PAGE_SIZE_2MBIT_ULL(21)
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 53d0cb327539..8f6a055854f7 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct
> intel_gvt_gtt_entry *e)
> || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
> return (e->val64 != 0);
> else
> - return (e->val64 & _PAGE_PRESENT);
> + return (e->val64 & I915_PAGE_PRESENT);
> }
>
> static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
> {
> - e->val64 &= ~_PAGE_PRESENT;
> + e->val64 &= ~I915_PAGE_PRESENT;
> }
>
> static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
> {
> - e->val64 |= _PAGE_PRESENT;
> + e->val64 |= I915_PAGE_PRESENT;
> }
>
> static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
> @@ -2439,7 +2439,7 @@ static int alloc_scratc
Re: [Intel-gfx] [PATCH v4 1/3] drm/i915: Introduce new macros for i915 PTE
On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote:
> On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote:
> > Certain functions within i915 uses macros that are defined for
> > specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
> > (Some architectures don't even have these macros defined, like ARM64).
> >
> > Instead of re-using bits defined for the CPU, we should use bits
> > defined for i915. This patch introduces two new macros,
> > I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
> > replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
>
> On older platforms we already had our own definition of GEN6_PTE_VALID
> (the spec uses "present" and "valid" interchangeably) which we were
> using to encode our ggtt ptes up through HSW; it might be better to go
> back to using that rather than adding a new define.
>
> It looks like BYT is when the writable bit showed up, and we did add a
> new define there (BYT_PTE_WRITEABLE), but on the next platform (BDW) we
> switched over to using the CPU page table flags instead and never used
> it again. So we could probably replace _PAGE_RW with BYT_PTE_WRITEABLE
> as well.
Okay, I should have looked at the rest of the series before reviewing
the first patch; it looks like your next two patches replace
GEN6_PTE_VALID and BYT_PTE_WRITEABLE with the new definitions here. I
still think it might be preferable to reuse the existing macros (which
also help clarify the platforms that those bits first showed up in the
PTE on) rather than replacing them with new macros, but I don't feel
super strongly about it if other reviewers feel differently.
Matt
>
> >
> > Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
> > same throughout the generations.
>
> This last sentence seems a bit confusing --- it's true that bit 0 has
> always been a present/valid flag, but bit 1 wasn't a writable bit until
> BYT; there just wasn't a writable bit at all (e.g., bspec page 229).
>
> It might be worth tossing a few bspec references on the commit message
> here, just for future reference. E.g.,
>
> Bspec: 253, 45039
>
>
> Matt
>
> >
> > Signed-off-by: Michael Cheng
> > ---
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++
> > drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
> > 4 files changed, 13 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > index 9966e9dc5218..f89b50ffc286 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > @@ -18,7 +18,7 @@
> > static u64 gen8_pde_encode(const dma_addr_t addr,
> >const enum i915_cache_level level)
> > {
> > - u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
> > + u64 pde = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
> >
> > if (level != I915_CACHE_NONE)
> > pde |= PPAT_CACHED_PDE;
> > @@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
> >enum i915_cache_level level,
> >u32 flags)
> > {
> > - gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
> > + gen8_pte_t pte = addr | I915_PAGE_PRESENT | I915_PAGE_RW;
> >
> > if (unlikely(flags & PTE_READ_ONLY))
> > - pte &= ~_PAGE_RW;
> > + pte &= ~I915_PAGE_RW;
> >
> > if (flags & PTE_LM)
> > pte |= GEN12_PPGTT_PTE_LM;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index 1fb4a03d7ac3..3f8e1ee0fbfa 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -207,7 +207,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > enum i915_cache_level level,
> > u32 flags)
> > {
> > - gen8_pte_t pte = addr | _PAGE_PRESENT;
> > + gen8_pte_t pte = addr | I915_PAGE_PRESENT;
> >
> > if (flags & PTE_LM)
> > pte |= GEN12_GGTT_PTE_LM;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> > b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > index dfeaef680aac..fba9c0c18f4a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > @@ -39,6 +39,9 @@
> >
> > #define NALLOC 3 /* 1 normal, 1 for concurrent threads, 1 for
> > preallocation */
> >
> > +#define I915_PAGE_PRESENT BIT_ULL(0)
> > +#define I915_PAGE_RW BIT_ULL(1)
> > +
> > #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
> > #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
> > #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
> > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> > index 53d0cb327539..8f6a055854f7 100644
> > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > @@ -446,17 +446,17 @@ static bool gen8_gtt_test_
