[Intel-gfx] ✗ Fi.CI.IGT: failure for Bump DMC version on ADLP to v2.11

[Patchwork]

== Series Details ==

Series: Bump DMC version on ADLP to v2.11
URL   : https://patchwork.freedesktop.org/series/93081/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10406_full -> Patchwork_20721_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20721_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20721_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20721_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_userptr_blits@huge-split:
- shard-apl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-apl6/igt@gem_userptr_bl...@huge-split.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-apl7/igt@gem_userptr_bl...@huge-split.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_busy@extended-modeset-hang-oldfb-with-reset:
- {shard-rkl}:NOTRUN -> [SKIP][3] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-rkl-1/igt@kms_b...@extended-modeset-hang-oldfb-with-reset.html

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7]) 
([i915#3002] / [i915#3621] / [i915#3810]) -> ([FAIL][8], [FAIL][9], [FAIL][10], 
[FAIL][11]) ([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-rkl-6/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-rkl-1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-rkl-1/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-rkl-2/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-rkl-6/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-rkl-1/igt@run...@aborted.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-rkl-2/igt@run...@aborted.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-rkl-6/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20721_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-apl:  NOTRUN -> [DMESG-WARN][12] ([i915#3002])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-apl6/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][13] -> [DMESG-WARN][14] ([i915#180])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1099])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-persistence.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][16] -> [TIMEOUT][17] ([i915#2369] / 
[i915#3063] / [i915#3648])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-tglb3/igt@gem_...@unwedge-stress.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-tglb6/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar 
issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_mmap_gtt@basic-small-bo-tiledx:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#3502])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10406/shard-iclb8/igt@gem_mmap_...@basic-small-bo-tiledx.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20721/shard-iclb5/igt@gem_mmap_...@basic-small-bo-tiledx.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][23] -> [FAIL][24] ([i915#307])
   [23]: 
https:/

Re: [Intel-gfx] [PATCH 03/33] drm/i915: Hold reference to intel_context over life of i915_request

[Daniel Vetter]

On Tue, Jul 27, 2021 at 2:06 AM Matthew Brost  wrote:
> Hold a reference to the intel_context over life of an i915_request.
> Without this an i915_request can exist after the context has been
> destroyed (e.g. request retired, context closed, but user space holds a
> reference to the request from an out fence). In the case of GuC
> submission + virtual engine, the engine that the request references is
> also destroyed which can trigger bad pointer dref in fence ops (e.g.
> i915_fence_get_driver_name). We could likely change
> i915_fence_get_driver_name to avoid touching the engine but let's just
> be safe and hold the intel_context reference.
>
> v2:
>  (John Harrison)
>   - Update comment explaining how GuC mode and execlists mode deal with
> virtual engines differently
>
> Signed-off-by: Matthew Brost 
> Reviewed-by: John Harrison 

Please also update the comment in the header for i915_request. That is
back from 2016 or so, when the context was actually fully refcounted
...

It would also be good to record a bit more the history here and all
the back&forth (and maybe why).

Don't ask why I've stumbled over this.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_request.c | 55 -
>  1 file changed, 23 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c 
> b/drivers/gpu/drm/i915/i915_request.c
> index 39a21d96577e..57c9187aff74 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -125,39 +125,17 @@ static void i915_fence_release(struct dma_fence *fence)
> i915_sw_fence_fini(&rq->semaphore);
>
> /*
> -* Keep one request on each engine for reserved use under mempressure
> -*
> -* We do not hold a reference to the engine here and so have to be
> -* very careful in what rq->engine we poke. The virtual engine is
> -* referenced via the rq->context and we released that ref during
> -* i915_request_retire(), ergo we must not dereference a virtual
> -* engine here. Not that we would want to, as the only consumer of
> -* the reserved engine->request_pool is the power management parking,
> -* which must-not-fail, and that is only run on the physical engines.
> -*
> -* Since the request must have been executed to be have completed,
> -* we know that it will have been processed by the HW and will
> -* not be unsubmitted again, so rq->engine and rq->execution_mask
> -* at this point is stable. rq->execution_mask will be a single
> -* bit if the last and _only_ engine it could execution on was a
> -* physical engine, if it's multiple bits then it started on and
> -* could still be on a virtual engine. Thus if the mask is not a
> -* power-of-two we assume that rq->engine may still be a virtual
> -* engine and so a dangling invalid pointer that we cannot dereference
> -*
> -* For example, consider the flow of a bonded request through a 
> virtual
> -* engine. The request is created with a wide engine mask (all engines
> -* that we might execute on). On processing the bond, the request mask
> -* is reduced to one or more engines. If the request is subsequently
> -* bound to a single engine, it will then be constrained to only
> -* execute on that engine and never returned to the virtual engine
> -* after timeslicing away, see __unwind_incomplete_requests(). Thus we
> -* know that if the rq->execution_mask is a single bit, rq->engine
> -* can be a physical engine with the exact corresponding mask.
> +* Keep one request on each engine for reserved use under mempressure,
> +* do not use with virtual engines as this really is only needed for
> +* kernel contexts.
>  */
> -   if (is_power_of_2(rq->execution_mask) &&
> -   !cmpxchg(&rq->engine->request_pool, NULL, rq))
> +   if (!intel_engine_is_virtual(rq->engine) &&
> +   !cmpxchg(&rq->engine->request_pool, NULL, rq)) {
> +   intel_context_put(rq->context);
> return;
> +   }
> +
> +   intel_context_put(rq->context);
>
> kmem_cache_free(global.slab_requests, rq);
>  }
> @@ -956,7 +934,19 @@ __i915_request_create(struct intel_context *ce, gfp_t 
> gfp)
> }
> }
>
> -   rq->context = ce;
> +   /*
> +* Hold a reference to the intel_context over life of an i915_request.
> +* Without this an i915_request can exist after the context has been
> +* destroyed (e.g. request retired, context closed, but user space 
> holds
> +* a reference to the request from an out fence). In the case of GuC
> +* submission + virtual engine, the engine that the request references
> +* is also destroyed which can trigger bad pointer dref in fence ops
> +* (e.g. i915_fence_get_

[Intel-gfx] [PATCH] drm/i915/gt: Fix a lockdep warning with disable interrupts

[Jun Miao]

When disable local interrupt irq of CPU hardware, some spin_lock
are called by inside signal_irq_work(), intel_breadcrumbs_disarm_irq() and
intel_breadcrumbs_arm_irq().

RT complains about might sleep inside interrupt disable by spin_lock, so 
switch spin_lock to spin_lock_irqsave with the shutdown interrupt at the 
same time.

--- ---
BUG: sleeping function called from invalid context at 
kernel/locking/rtmutex.c:969
  #0: 89c4c00ca970 ((wq_completion)events){+.+.}-{0:0}, at: 
process_one_work+0x1cf/0x6d0
  #1: a433c1f53e60 ((work_completion)(&engine->retire_work)){+.+.}-{0:0}, 
at: process_one_work+0x1cf 0x6d
  #2: 89c4ccb0a0a8 (kernel_context){+.+.}-{0:0}, at: 
engine_retire+0x62/0x110 [i915]
  #3: 89c4cf682300 (wakeref.mutex#3){+.+.}-{0:0}, at: 
__intel_wakeref_put_last+0x20/0x60 [i915]
  #4: 89c4ccb08398 (&b->irq_lock){+.+.}-{0:0}, at: 
intel_breadcrumbs_disarm_irq+0x20/0xd0 [i915]
 irq event stamp: 2126
 hardirqs last  enabled at (2125): [] 
cancel_delayed_work+0xa9/0xc0
 hardirqs last disabled at (2126): [] 
__intel_breadcrumbs_park+0x76/0x80 [i915]
 softirqs last  enabled at (0): [] copy_process+0x63e/0x1630
 softirqs last disabled at (0): [<>] 0x0
 CPU: 3 PID: 281 Comm: kworker/3:3 Not tainted 5.10.27-rt34-yocto-preempt-rt #1
 Hardware name: Intel(R) Client Systems NUC7i5DNKE/NUC7i5DNB, BIOS 
DNKBLi5v.86A.0064.2019.0523.1933 05/23 2019
 Workqueue: events engine_retire [i915]
 Call Trace:
  show_stack+0x52/0x58
  dump_stack+0x7d/0x9f
  ___might_sleep.cold+0xe3/0xf4
  rt_spin_lock+0x3f/0xc0
  ? intel_breadcrumbs_disarm_irq+0x20/0xd0 [i915]
  intel_breadcrumbs_disarm_irq+0x20/0xd0 [i915]
  signal_irq_work+0x241/0x660 [i915]
  ? __this_cpu_preempt_check+0x13/0x20
  ? lockdep_hardirqs_off+0x106/0x120
  __intel_breadcrumbs_park+0x3f/0x80 [i915]
  __engine_park+0xbd/0xe0 [i915]
  intel_wakeref_put_last+0x22/0x60 [i915]
  __intel_wakeref_put_last+0x50/0x60 [i915]
  intel_context_exit_engine+0x5f/0x70 [i915]
  i915_request_retire+0x139/0x2d0 [i915]
  engine_retire+0xb0/0x110 [i915]
  process_one_work+0x26d/0x6d0
  worker_thread+0x53/0x330
  kthread+0x1b0/0x1d0
  ? process_one_work+0x6d0/0x6d0
  ? __kthread_parkme+0xc0/0xc0
  ret_from_fork+0x22/0x30

Fixes: 9d5612ca165a ("drm/i915/gt: Defer enabling the breadcrumb interrupt to 
after submission")
Signed-off-by: Jun Miao 
---
 drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 38cc42783dfb..9b74d0a56bc5 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -63,13 +63,15 @@ static void __intel_breadcrumbs_arm_irq(struct 
intel_breadcrumbs *b)
 
 static void intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
 {
+   unsigned long flags;
+
if (!b->irq_engine)
return;
 
-   spin_lock(&b->irq_lock);
+   spin_lock_irqsave(&b->irq_lock, flags);
if (!b->irq_armed)
__intel_breadcrumbs_arm_irq(b);
-   spin_unlock(&b->irq_lock);
+   spin_unlock_irqrestore(&b->irq_lock, flags);
 }
 
 static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
@@ -84,10 +86,12 @@ static void __intel_breadcrumbs_disarm_irq(struct 
intel_breadcrumbs *b)
 
 static void intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
 {
-   spin_lock(&b->irq_lock);
+   unsigned long flags;
+
+   spin_lock_irqsave(&b->irq_lock, flags);
if (b->irq_armed)
__intel_breadcrumbs_disarm_irq(b);
-   spin_unlock(&b->irq_lock);
+   spin_unlock_irqrestore(&b->irq_lock, flags);
 }
 
 static void add_signaling_context(struct intel_breadcrumbs *b,
@@ -181,6 +185,7 @@ static void signal_irq_work(struct irq_work *work)
const ktime_t timestamp = ktime_get();
struct llist_node *signal, *sn;
struct intel_context *ce;
+   unsigned long flags;
 
signal = NULL;
if (unlikely(!llist_empty(&b->signaled_requests)))
@@ -259,11 +264,11 @@ static void signal_irq_work(struct irq_work *work)
llist_entry(signal, typeof(*rq), signal_node);
struct list_head cb_list;
 
-   spin_lock(&rq->lock);
+   spin_lock_irqsave(&rq->lock, flags);
list_replace(&rq->fence.cb_list, &cb_list);
__dma_fence_signal__timestamp(&rq->fence, timestamp);
__dma_fence_signal__notify(&rq->fence, &cb_list);
-   spin_unlock(&rq->lock);
+   spin_unlock_irqrestore(&rq->lock, flags);
 
i915_request_put(rq);
}
@@ -318,9 +323,7 @@ void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
/* Kick the work once more to drain the signalers, and disarm the irq */
irq_work_sync(&b->irq_work);
while (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) {

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: Fix a lockdep warning with disable interrupts

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Fix a lockdep warning with disable interrupts
URL   : https://patchwork.freedesktop.org/series/93100/
State : failure

== Summary ==

Applying: drm/i915/gt: Fix a lockdep warning with disable interrupts
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
CONFLICT (content): Merge conflict in 
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/gt: Fix a lockdep warning with disable interrupts
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] [PATCH i-g-t v2 01/11] lib/i915/gem_mman: add FIXED mmap mode

[Matthew Auld]

We need this for discrete.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 37 +
 lib/i915/gem_mman.h |  4 
 2 files changed, 41 insertions(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 4b4f2114..e2514f0c 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, 
uint64_t offset,
return ptr;
 }
 
+#define LOCAL_I915_MMAP_OFFSET_FIXED 4
+
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+  uint64_t size, unsigned prot)
+{
+   return __gem_mmap_offset(fd, handle, offset, size, prot,
+LOCAL_I915_MMAP_OFFSET_FIXED);
+}
+
+/**
+ * gem_mmap_offset__fixed: Used to mmap objects on discrete platforms
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Like __gem_mmap_offset__fixed() except we assert on failure.
+ *
+ * For discrete the caching attributes for the pages are fixed at allocation
+ * time, and can't be changed. The FIXED mode will simply use the same caching 
*
+ * mode of the allocated pages. This mode will always be coherent with GPU
+ * access.
+ *
+ * On non-discrete platforms this mode is not supported.
+ *
+ * Returns: A pointer to the created memory mapping
+ */
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+  uint64_t size, unsigned prot)
+{
+   void *ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+   igt_assert(ptr);
+   return ptr;
+}
+
 /**
  * __gem_mmap__cpu_coherent:
  * @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 5695d2ad..290c997d 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -37,6 +37,8 @@ bool gem_mmap_offset__has_wc(int fd);
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, 
unsigned prot);
 void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
  uint64_t size, unsigned prot);
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+uint64_t size, unsigned prot);
 void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
 void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
@@ -54,6 +56,8 @@ void *__gem_mmap_offset__cpu(int fd, uint32_t handle, 
uint64_t offset,
 void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, 
unsigned prot);
 void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+  uint64_t size, unsigned prot);
 void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
  uint64_t size, unsigned prot);
 void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t 
size,
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent

[Matthew Auld]

On discrete we need to fallback to this mode.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index e2514f0c..222e8896 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -383,9 +383,10 @@ void *__gem_mmap__device_coherent(int fd, uint32_t handle, 
uint64_t offset,
  I915_MMAP_OFFSET_WC);
if (!ptr)
ptr = __gem_mmap__wc(fd, handle, offset, size, prot);
-
if (!ptr)
ptr = __gem_mmap__gtt(fd, handle, size, prot);
+   if (!ptr)
+   ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
 
return ptr;
 }
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 03/11] lib/i915/gem_mman: add fixed mode to mmap__cpu_coherent

[Matthew Auld]

On discrete we only support the new fixed mode.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 222e8896..337d28fb 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -580,6 +580,8 @@ void *gem_mmap__cpu_coherent(int fd, uint32_t handle, 
uint64_t offset,
igt_assert(offset == 0);
 
ptr = __gem_mmap__cpu_coherent(fd, handle, offset, size, prot);
+   if (!ptr)
+   ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
igt_assert(ptr);
 
return ptr;
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu

[Matthew Auld]

On discrete we only support the new fixed mode.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 337d28fb..6f5e6d72 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -434,7 +434,13 @@ void *gem_mmap__device_coherent(int fd, uint32_t handle, 
uint64_t offset,
  */
 void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, 
unsigned prot)
 {
-   return __gem_mmap(fd, handle, offset, size, prot, 0);
+   void *ptr;
+
+   ptr = __gem_mmap(fd, handle, offset, size, prot, 0);
+   if (!ptr)
+   ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+   return ptr;
 }
 
 /**
-- 
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[Intel-gfx] [PATCH i-g-t v2 05/11] lib/i915/gem_mman: update mmap_offset_types with FIXED

[Matthew Auld]

We need to also iterate the fixed mode in the tests which rely on this.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 6f5e6d72..16168a32 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -617,6 +617,7 @@ const struct mmap_offset mmap_offset_types[] = {
{ "wb", I915_MMAP_OFFSET_WB, I915_GEM_DOMAIN_CPU },
{ "wc", I915_MMAP_OFFSET_WC, I915_GEM_DOMAIN_WC },
{ "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC },
+   { "fixed", LOCAL_I915_MMAP_OFFSET_FIXED, 0},
{},
 };
 
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 06/11] lib/ioctl_wrappers: update mmap_{read, write} for discrete

[Matthew Auld]

We can no longer just call get_caching or set_domain, and the mmap mode
must be FIXED. This should bring back gem_exec_basic and a few others in
CI on DG1.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/ioctl_wrappers.c | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 25c5e495..7e27a1b3 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -339,7 +339,18 @@ static void mmap_write(int fd, uint32_t handle, uint64_t 
offset,
if (!length)
return;
 
-   if (is_cache_coherent(fd, handle)) {
+   if (gem_has_lmem(fd)) {
+   /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only mmap mode supportd is FIXED.
+*/
+   map = gem_mmap_offset__fixed(fd, handle, 0,
+offset + length,
+PROT_READ | PROT_WRITE);
+   igt_assert_eq(gem_wait(fd, handle, 0), 0);
+   }
+
+   if (!map && is_cache_coherent(fd, handle)) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0, offset + length,
   PROT_READ | PROT_WRITE);
@@ -369,7 +380,17 @@ static void mmap_read(int fd, uint32_t handle, uint64_t 
offset, void *buf, uint6
if (!length)
return;
 
-   if (gem_has_llc(fd) || is_cache_coherent(fd, handle)) {
+   if (gem_has_lmem(fd)) {
+   /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only supported mmap mode is FIXED.
+*/
+   map = gem_mmap_offset__fixed(fd, handle, 0,
+offset + length, PROT_READ);
+   igt_assert_eq(gem_wait(fd, handle, 0), 0);
+   }
+
+   if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, handle))) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0,
   offset + length, PROT_READ);
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 07/11] lib/intel_bufops: update mmap_{read, write} for discrete

[Matthew Auld]

On discrete we can no longer call get_caching or set_domain, and the
mmap mode must be FIXED.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/intel_bufops.c | 25 +++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 3ce68663..faca4406 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -424,7 +424,18 @@ static void *mmap_write(int fd, struct intel_buf *buf)
 {
void *map = NULL;
 
-   if (is_cache_coherent(fd, buf->handle)) {
+   if (gem_has_lmem(fd)) {
+   /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only mmap mode supportd is FIXED.
+*/
+   map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+buf->surface[0].size,
+PROT_READ | PROT_WRITE);
+   igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+   }
+
+   if (!map && is_cache_coherent(fd, buf->handle)) {
map = __gem_mmap_offset__cpu(fd, buf->handle, 0, 
buf->surface[0].size,
 PROT_READ | PROT_WRITE);
if (!map)
@@ -455,7 +466,17 @@ static void *mmap_read(int fd, struct intel_buf *buf)
 {
void *map = NULL;
 
-   if (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle)) {
+   if (gem_has_lmem(fd)) {
+   /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only supported mmap mode is FIXED.
+*/
+   map = gem_mmap_offset__fixed(fd, buf->handle, 0,
+buf->surface[0].size, PROT_READ);
+   igt_assert_eq(gem_wait(fd, buf->handle, 0), 0);
+   }
+
+   if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, buf->handle))) {
map = __gem_mmap_offset__cpu(fd, buf->handle, 0,
 buf->surface[0].size, PROT_READ);
if (!map)
-- 
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[Intel-gfx] [PATCH i-g-t v2 08/11] lib/ioctl_wrappers: update set_domain for discrete

[Matthew Auld]

On discrete set_domain is now gone, instead we just need to add the
wait.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/ioctl_wrappers.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 7e27a1b3..09eb3ce7 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -565,7 +565,12 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t 
read, uint32_t write)
  */
 void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
 {
-   igt_assert_eq(__gem_set_domain(fd, handle, read, write), 0);
+   int ret = __gem_set_domain(fd, handle, read, write);
+
+   if (ret == -ENODEV && gem_has_lmem(fd))
+   igt_assert_eq(gem_wait(fd, handle, 0), 0);
+   else
+   igt_assert_eq(ret, 0);
 }
 
 /**
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 09/11] tests/i915/module_load: update for discrete

[Matthew Auld]

The set_caching ioctl is gone for discrete, and now just returns
-ENODEV. Update the gem_sanitycheck to account for that. After this we
should be back to just having the breakage caused by missing reloc
support for the reload testcase.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 tests/i915/i915_module_load.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 98ceb5d8..4b42fe3e 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -172,17 +172,22 @@ static void gem_sanitycheck(void)
 {
struct drm_i915_gem_caching args = {};
int i915 = __drm_open_driver(DRIVER_INTEL);
+   int expected;
int err;
 
+   expected = -ENOENT;
+   if (gem_has_lmem(i915))
+   expected = -ENODEV;
+
err = 0;
if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args))
err = -errno;
-   if (err == -ENOENT)
+   if (err == expected)
store_all(i915);
errno = 0;
 
close(i915);
-   igt_assert_eq(err, -ENOENT);
+   igt_assert_eq(err, expected);
 }
 
 static void
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 10/11] lib/i915/gem_mman: add helper query for has_device_coherent

[Matthew Auld]

Might be useful in some tests, where we are not explicitly testing WC
maps, but rather just require something that is "device coherent", which
should also play nice on discrete platforms.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 lib/i915/gem_mman.c | 43 +--
 lib/i915/gem_mman.h | 11 +++
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 16168a32..27ef97cf 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -196,6 +196,47 @@ bool gem_mmap_offset__has_wc(int fd)
return has_wc > 0;
 }
 
+#define LOCAL_I915_MMAP_OFFSET_FIXED 4
+
+bool gem_mmap__has_device_coherent(int fd)
+{
+   struct drm_i915_gem_mmap_offset arg;
+   bool supported;
+
+   if (gem_mmap__has_wc(fd))
+   return true;
+
+   /* Maybe we still have GTT mmaps? */
+   memset(&arg, 0, sizeof(arg));
+   arg.handle = gem_create(fd, 4096);
+   arg.offset = 0;
+   arg.flags = I915_MMAP_OFFSET_GTT;
+   supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+ &arg) == 0;
+   gem_close(fd, arg.handle);
+
+   errno = 0;
+
+   if (supported)
+   return true;
+
+   /*
+* Maybe this is a discrete device, which only supports fixed mmaps?
+* Such mappings should also be considered device coherent.
+*/
+   memset(&arg, 0, sizeof(arg));
+   arg.handle = gem_create(fd, 4096);
+   arg.offset = 0;
+   arg.flags = LOCAL_I915_MMAP_OFFSET_FIXED;
+   supported = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_OFFSET,
+ &arg) == 0;
+   gem_close(fd, arg.handle);
+
+   errno = 0;
+
+   return supported;
+}
+
 /**
  * __gem_mmap:
  * @fd: open i915 drm file descriptor
@@ -504,8 +545,6 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle, 
uint64_t offset,
return ptr;
 }
 
-#define LOCAL_I915_MMAP_OFFSET_FIXED 4
-
 void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
   uint64_t size, unsigned prot)
 {
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 290c997d..5966ddb5 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -41,6 +41,7 @@ void *gem_mmap_offset__fixed(int fd, uint32_t handle, 
uint64_t offset,
 uint64_t size, unsigned prot);
 void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+bool gem_mmap__has_device_coherent(int fd);
 void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
 uint64_t size, unsigned prot);
 
@@ -96,6 +97,16 @@ int gem_munmap(void *ptr, uint64_t size);
  */
 #define gem_require_mmap_offset_wc(fd) igt_require(gem_mmap_offset__has_wc(fd))
 
+/**
+ * gem_require_mmap_offset_device_coherent:
+ * @fd: open i915 drm file descriptor
+ *
+ * Feature test macro to query whether direct (i.e. cpu access path, bypassing
+ * the gtt) write-combine memory mappings are available, or fixed mapping for
+ * discrete. Automatically skips through igt_require() if not.
+ */
+#define gem_require_mmap_device_coherent(fd) 
igt_require(gem_mmap__has_device_coherent(fd))
+
 extern const struct mmap_offset {
const char *name;
unsigned int type;
-- 
2.26.3

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[Intel-gfx] [PATCH i-g-t v2 11/11] tests/i915/gem_exec_fence: use device_coherent mmap

[Matthew Auld]

We lost explicit WC mmaps on discrete, where we now only support FIXED,
however such mappings should be device coherent. In gem_exec_fence it
looks like we can just use mmap__device_coherent, which should also work
on discrete platforms, while still using an explicit WC mmap on
integrated platforms.

Signed-off-by: Matthew Auld 
Cc: Maarten Lankhorst 
Cc: Ashutosh Dixit 
Cc: Daniel Vetter 
Cc: Ramalingam C 
---
 tests/i915/gem_exec_fence.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index ef1bb0ca..620e7ac2 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -152,7 +152,7 @@ static void test_fence_busy(int fd, const intel_ctx_t *ctx,
obj.relocation_count = 1;
memset(&reloc, 0, sizeof(reloc));
 
-   batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+   batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
gem_set_domain(fd, obj.handle,
   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -244,7 +244,7 @@ static void test_fence_busy_all(int fd, const intel_ctx_t 
*ctx, unsigned flags)
obj.relocation_count = 1;
memset(&reloc, 0, sizeof(reloc));
 
-   batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+   batch = gem_mmap__device_coherent(fd, obj.handle, 0, 4096, PROT_WRITE);
gem_set_domain(fd, obj.handle,
   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -353,7 +353,7 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
uint32_t *out;
int i;
 
-   out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
+   out = gem_mmap__device_coherent(fd, scratch, 0, 4096, PROT_WRITE);
gem_set_domain(fd, scratch,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 
@@ -617,7 +617,7 @@ static void test_parallel(int i915, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e2;
const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
uint32_t scratch = gem_create(i915, 4096);
-   uint32_t *out = gem_mmap__wc(i915, scratch, 0, 4096, PROT_READ);
+   uint32_t *out = gem_mmap__device_coherent(i915, scratch, 0, 4096, 
PROT_READ);
uint32_t handle[I915_EXEC_RING_MASK];
IGT_CORK_FENCE(cork);
igt_spin_t *spin;
@@ -2813,7 +2813,7 @@ static void test_syncobj_timeline_chain_engines(int fd, 
const intel_ctx_cfg_t *c
 
gem_sync(fd, ctx.engine_counter_object.handle);
 
-   counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 
4096, PROT_READ);
+   counter_output = gem_mmap__device_coherent(fd, 
ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2879,7 +2879,7 @@ static void 
test_syncobj_stationary_timeline_chain_engines(int fd, const intel_c
 
gem_sync(fd, ctx.engine_counter_object.handle);
 
-   counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 
4096, PROT_READ);
+   counter_output = gem_mmap__device_coherent(fd, 
ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2940,7 +2940,7 @@ static void 
test_syncobj_backward_timeline_chain_engines(int fd, const intel_ctx
 
gem_sync(fd, ctx.engine_counter_object.handle);
 
-   counter_output = gem_mmap__wc(fd, ctx.engine_counter_object.handle, 0, 
4096, PROT_READ);
+   counter_output = gem_mmap__device_coherent(fd, 
ctx.engine_counter_object.handle, 0, 4096, PROT_READ);
 
for (uint32_t i = 0; i < ctx.engines.nengines; i++)
igt_debug("engine %i (%s)\t= %016"PRIx64"\n", i,
@@ -2963,7 +2963,7 @@ igt_main
i915 = drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
igt_require(gem_has_exec_fence(i915));
-   gem_require_mmap_wc(i915);
+   gem_require_mmap_device_coherent(i915);
ctx = intel_ctx_create_all_physical(i915);
 
gem_submission_print_method(i915);
-- 
2.26.3

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Re: [Intel-gfx] [Linaro-mm-sig] [PATCH v4 03/18] drm/sched: Add dependency tracking

[Daniel Vetter]

On Wed, Jul 28, 2021 at 1:29 PM Christian König
 wrote:
> Am 27.07.21 um 13:09 schrieb Daniel Vetter:
> > Adding a few more people to this bikeshed.
> >
> > On Mon, Jul 12, 2021 at 10:02 PM Daniel Vetter  
> > wrote:
> >
> >> @@ -349,6 +367,13 @@ int drm_sched_job_init(struct drm_sched_job *job,
> >> struct drm_sched_entity *entity,
> >> void *owner);
> >>   void drm_sched_job_arm(struct drm_sched_job *job);
> >> +int drm_sched_job_await_fence(struct drm_sched_job *job,
> >> + struct dma_fence *fence);
> >> +int drm_sched_job_await_implicit(struct drm_sched_job *job,
> >> +struct drm_gem_object *obj,
> >> +bool write);
> >> +
> >> +
> > I'm still waiting on the paint delivery for these two functions so I
> > can finish this shed.
>
> Well I wouldn't call that bike shedding, good names are important.
>
> Just imaging we would have called the exclusive-fence write-fence instead.

Sure naming matters, but at least to my English understanding there's
not a semantic different between telling something to await for
something else (i.e. add a dependency) or to tell something to add a
dependency (i.e. await that thing later on before you start doing your
own thing).

Exclusive vs write fence otoh is a pretty big difference in what it means.

But also if there's consensus that I'm wrong then I'm happy to pick
the more preferred of the two options I deem equivalent.

> What speaks against calling them add_dependency() and
> _add_implicit_depencencies() ?

Nothing. I just like another ack on this before I rename it all. Also
I wasnt sure what you'd want to name the implicit dependency thing.

Lucas, Boris, Melissa, any acks here?
-Daniel

> Regards,
> Christian.
>
> >
> > Thanks, Daniel
> >
> >>   void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
> >>  struct drm_gpu_scheduler **sched_list,
> >>  unsigned int num_sched_list);
> >> --
> >> 2.32.0
> >>
> >
>


-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain

[Anshuman Gupta]

DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
well. Adjusting the power domain accordingly to
POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
for audio playback.

v1: Changes since RFC
- changed power domain names. [Imre]
- Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
  power well and PW_3 power domains. [Imre]
- Fixed the order of powe wells , power domains and its
  registration. [Imre]

v2:
- Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]

Cc: Ville Syrjälä 
Cc: Kai Vehmanen 
Cc: Uma Shankar 
Cc: Imre Deak 
Signed-off-by: Anshuman Gupta 
---
 .../drm/i915/display/intel_display_power.c| 234 --
 .../drm/i915/display/intel_display_power.h|   3 +-
 2 files changed, 221 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 81efc77bada0..2675b48d707e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -106,8 +106,10 @@ intel_display_power_domain_str(enum 
intel_display_power_domain domain)
return "PORT_OTHER";
case POWER_DOMAIN_VGA:
return "VGA";
-   case POWER_DOMAIN_AUDIO:
-   return "AUDIO";
+   case POWER_DOMAIN_AUDIO_MMIO:
+   return "AUDIO_MMIO";
+   case POWER_DOMAIN_AUDIO_PLAYBACK:
+   return "AUDIO_PLAYBAK";
case POWER_DOMAIN_AUX_A:
return "AUX_A";
case POWER_DOMAIN_AUX_B:
@@ -2519,7 +2521,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
BIT_ULL(POWER_DOMAIN_VGA) | \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_AUX_B) |   \
BIT_ULL(POWER_DOMAIN_AUX_C) |   \
BIT_ULL(POWER_DOMAIN_GMBUS) |   \
@@ -2569,7 +2572,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
BIT_ULL(POWER_DOMAIN_VGA) | \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_AUX_B) |   \
BIT_ULL(POWER_DOMAIN_AUX_C) |   \
BIT_ULL(POWER_DOMAIN_AUX_D) |   \
@@ -2602,7 +2606,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
BIT_ULL(POWER_DOMAIN_VGA) | \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_INIT))
 
 #define BDW_DISPLAY_POWER_DOMAINS (\
@@ -2618,7 +2623,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
BIT_ULL(POWER_DOMAIN_VGA) | \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_INIT))
 
 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (\
@@ -2636,7 +2642,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_AUX_B) |   \
BIT_ULL(POWER_DOMAIN_AUX_C) |   \
BIT_ULL(POWER_DOMAIN_AUX_D) |   \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_INIT))
 #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
@@ -2671,7 +2678,8 @@ intel_display_power_put_mask_in_set(struct 
drm_i915_private *i915,
BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
BIT_ULL(POWER_DOMAIN_AUX_B) |   \
BIT_ULL(POWER_DOMAIN_AUX_C) |   \
-   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
+   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
+   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH v4 03/18] drm/sched: Add dependency tracking

[Christian König]

Am 27.07.21 um 13:09 schrieb Daniel Vetter:

Adding a few more people to this bikeshed.

On Mon, Jul 12, 2021 at 10:02 PM Daniel Vetter  wrote:


@@ -349,6 +367,13 @@ int drm_sched_job_init(struct drm_sched_job *job,
struct drm_sched_entity *entity,
void *owner);
  void drm_sched_job_arm(struct drm_sched_job *job);
+int drm_sched_job_await_fence(struct drm_sched_job *job,
+ struct dma_fence *fence);
+int drm_sched_job_await_implicit(struct drm_sched_job *job,
+struct drm_gem_object *obj,
+bool write);
+
+

I'm still waiting on the paint delivery for these two functions so I
can finish this shed.


Well I wouldn't call that bike shedding, good names are important.

Just imaging we would have called the exclusive-fence write-fence instead.

What speaks against calling them add_dependency() and 
_add_implicit_depencencies() ?


Regards,
Christian.



Thanks, Daniel


  void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
 struct drm_gpu_scheduler **sched_list,
 unsigned int num_sched_list);
--
2.32.0





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Re: [Intel-gfx] [PATCH v2 2/3] drm: clarify usage of drm leases

[Desmond Cheong Zhi Xi]

On 27/7/21 9:04 pm, Daniel Vetter wrote:

On Sat, Jul 24, 2021 at 07:18:23PM +0800, Desmond Cheong Zhi Xi wrote:

We make the following changes to the documentation of drm leases to
make it easier to reason about their usage. In particular, we clarify
the lifetime and locking rules of lease fields in drm_master:

1. Make it clear that &drm_device.mode_config.idr_mutex protects the
lease idr and list structures for drm_master. The lessor field itself
doesn't need to be protected as it doesn't change after it's set in
drm_lease_create.

2. Add descriptions for the lifetime of lessors and leases.

3. Add an overview DOC: section in drm-uapi.rst that defines the
terminology for drm leasing, and explains how leases work and why
they're used.

4. Clean up function documentation in drm_lease.c to use kernel-doc
formatting.

Signed-off-by: Desmond Cheong Zhi Xi 
---

Hi,

After I updated the formatting for comments in drm_lease.c, I noticed
that none of these were driver interfaces (i.e. no structs/inline
functions declared in headers, and no exported symbols in .c files).

I left the kernel-doc links inside drm-uapi.rst so that if any such
interfaces are defined in the future, they'll go to the appropriate
place. But if these should be removed, or if the formatting changes for
function comments should be removed, please let me know.



Hm indeed, so there's not really any need to either include the
drm_lease.c or drm_lease.h kerneldoc. The DOC section itself is still
useful.

For the internal pieces usually what we do is remove the comment outright
if it doesn't provide anything useful (like just repeats what the function
name says already). If there's something interesting in the comment then
we leave it that sentence in there as a normal comment, but without any of
the structured comment stuff (so no /**, nor @arguments, or the function
summary).





Best wishes,
Desmond

  Documentation/gpu/drm-uapi.rst |  15 +++
  drivers/gpu/drm/drm_lease.c| 182 -
  include/drm/drm_auth.h |  67 ++--
  3 files changed, 180 insertions(+), 84 deletions(-)

diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst
index 7e51dd40bf6e..6d7233a9fb14 100644
--- a/Documentation/gpu/drm-uapi.rst
+++ b/Documentation/gpu/drm-uapi.rst
@@ -37,6 +37,21 @@ Primary Nodes, DRM Master and Authentication
  .. kernel-doc:: include/drm/drm_auth.h
 :internal:
  
+

+.. _drm_leasing:
+
+DRM Display Resource Leasing
+
+
+.. kernel-doc:: drivers/gpu/drm/drm_lease.c
+   :doc: drm leasing
+
+.. kernel-doc:: drivers/gpu/drm/drm_lease.c
+   :export:
+
+.. kernel-doc:: include/drm/drm_lease.h
+   :internal:
+
  Open-Source Userspace Requirements
  ==
  
diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c

index 92eac73d9001..9b68617840ed 100644
--- a/drivers/gpu/drm/drm_lease.c
+++ b/drivers/gpu/drm/drm_lease.c
@@ -15,18 +15,67 @@
  #include "drm_crtc_internal.h"
  #include "drm_internal.h"
  
+/**

+ * DOC: drm leasing
+ *
+ * DRM leases provide information about whether a DRM master may control a DRM
+ * mode setting object. This enables the creation of multiple DRM masters that
+ * manage subsets of display resources.
+ *
+ * The original DRM master of a device 'owns' the available drm resources. It
+ * may create additional DRM masters and 'lease' resources which it controls
+ * to the new DRM master. This gives the new DRM master control over the
+ * leased resources until the owner revokes the lease, or the new DRM master
+ * is closed. Some helpful terminology:
+ *
+ * - An 'owner' is a &struct drm_master that is not leasing objects from
+ *   another &struct drm_master, and hence 'owns' the objects. The owner can be
+ *   identified as the &struct drm_master for which &drm_master.lessor is NULL.
+ *
+ * - A 'lessor' is a &struct drm_master which is leasing objects to one or more
+ *   other &struct drm_master. Currently, lessees are not allowed to
+ *   create sub-leases, hence the lessor is the same as the owner.
+ *
+ * - A 'lessee' is a &struct drm_master which is leasing objects from some
+ *   other &struct drm_master. Each lessee only leases resources from a single
+ *   lessor recorded in &drm_master.lessor, and holds the set of objects that
+ *   it is leasing in &drm_master.leases.
+ *
+ * - A 'lease' is a contract between the lessor and lessee that identifies
+ *   which resources may be controlled by the lessee. All of the resources
+ *   that are leased must be owned by or leased to the lessor, and lessors are
+ *   not permitted to lease the same object to multiple lessees.
+ *
+ * The set of objects any &struct drm_master 'controls' is limited to the set
+ * of objects it leases (for lessees) or all objects (for owners).
+ *
+ * Objects not controlled by a &struct drm_master cannot be modified through
+ * the various state manipulating ioctls, and any state reported back to user
+

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for lpsp with hdmi/dp outputs (rev2)

[Patchwork]

== Series Details ==

Series: lpsp with hdmi/dp outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/92108/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1900:21:expected struct 
i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1900:21:got void [noderef] 
__iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type 
in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1414:34:expected struct 
i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1414:34:got struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1414:34: warning: incorrect type 
in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct 
i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect 
type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct 
i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect 
type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1268:24: warning: Using plain 
integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context i

[Intel-gfx] [PULL] drm-misc-fixes

[Thomas Zimmermann]

Hi Dave and Daniel,

here's this week's PR for drm-misc-fixes. Besides the patches, it
contains a backmerge of drm-fixes.

Best regards
Thomas

drm-misc-fixes-2021-07-28:
Short summary of fixes pull:

 * panel: Fix bpc for ytc700tlag_05_201c
 * ttm: debugfs init fixes
The following changes since commit ff1176468d368232b684f75e82563369208bc371:

  Linux 5.14-rc3 (2021-07-25 15:35:14 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2021-07-28

for you to fetch changes up to 8ee18e769dd621104fecad584c84ec3c4c9ef3fa:

  Merge drm/drm-fixes into drm-misc-fixes (2021-07-27 14:08:29 +0200)


Short summary of fixes pull:

 * panel: Fix bpc for ytc700tlag_05_201c
 * ttm: debugfs init fixes


Jagan Teki (1):
  drm/panel: panel-simple: Fix proper bpc for ytc700tlag_05_201c

Jason Ekstrand (1):
  drm/ttm: Initialize debugfs from ttm_global_init()

Thomas Zimmermann (1):
  Merge drm/drm-fixes into drm-misc-fixes

 drivers/gpu/drm/panel/panel-simple.c |  2 +-
 drivers/gpu/drm/ttm/ttm_device.c | 12 
 drivers/gpu/drm/ttm/ttm_module.c | 16 
 3 files changed, 13 insertions(+), 17 deletions(-)

--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Maxfeldstr. 5, 90409 Nürnberg, Germany
(HRB 36809, AG Nürnberg)
Geschäftsführer: Felix Imendörffer
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[Intel-gfx] ✓ Fi.CI.BAT: success for lpsp with hdmi/dp outputs (rev2)

[Patchwork]

== Series Details ==

Series: lpsp with hdmi/dp outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/92108/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10410 -> Patchwork_20723


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/index.html

Known issues


  Here are the changes found in Patchwork_20723 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-compute:
- fi-cfl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +28 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-cfl-guc/igt@amdgpu/amd_ba...@cs-compute.html
- fi-elk-e7500:   NOTRUN -> [SKIP][2] ([fdo#109271]) +49 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-elk-e7500/igt@amdgpu/amd_ba...@cs-compute.html

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#109315]) +17 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html
- fi-skl-6700k2:  NOTRUN -> [SKIP][4] ([fdo#109271]) +33 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-skl-6700k2/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +59 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-kbl-guc/igt@amdgpu/amd_ba...@cs-sdma.html
- fi-kbl-7500u:   NOTRUN -> [SKIP][6] ([fdo#109271]) +30 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-kbl-7500u/igt@amdgpu/amd_ba...@cs-sdma.html

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-u2:  NOTRUN -> [SKIP][8] ([fdo#109315])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-u2/igt@amdgpu/amd_ba...@query-info.html
- fi-tgl-1115g4:  NOTRUN -> [SKIP][9] ([fdo#109315])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html
- fi-tgl-y:   NOTRUN -> [SKIP][10] ([fdo#109315])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-y/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
- fi-icl-y:   NOTRUN -> [SKIP][11] ([fdo#109315]) +17 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-icl-y/igt@amdgpu/amd_ba...@semaphore.html
- fi-bdw-5557u:   NOTRUN -> [SKIP][12] ([fdo#109271]) +29 similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-tgl-u2:  NOTRUN -> [SKIP][13] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-u2/igt@amdgpu/amd_cs_...@fork-compute0.html
- fi-ivb-3770:NOTRUN -> [SKIP][14] ([fdo#109271]) +31 similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-ivb-3770/igt@amdgpu/amd_cs_...@fork-compute0.html

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-tgl-y:   NOTRUN -> [SKIP][15] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-y/igt@amdgpu/amd_cs_...@fork-gfx0.html

  * igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][16] ([fdo#109271]) +35 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][17] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-x1275:   NOTRUN -> [SKIP][18] ([fdo#109271]) +28 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-kbl-x1275/igt@amdgpu/amd_pr...@amd-to-i915.html

  * igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m:   NOTRUN -> [SKIP][19] ([fdo#109271]) +37 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-snb-2520m/igt@amdgpu/amd_pr...@i915-to-amd.html

  * igt@core_hotunplug@unbind-rebind:
- fi-hsw-4770:NOTRUN -> [WARN][20] ([i915#3718])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/fi-hsw-4770/igt@core_hotunp...@unbind-rebind.html
- fi-bdw-5557u:   NOTRUN -> [WARN][21] ([i9

Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain

[Imre Deak]

On Wed, Jul 28, 2021 at 05:22:16PM +0530, Anshuman Gupta wrote:
> DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
> well. Adjusting the power domain accordingly to
> POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
> for audio playback.
> 
> v1: Changes since RFC
> - changed power domain names. [Imre]
> - Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
>   power well and PW_3 power domains. [Imre]
> - Fixed the order of powe wells , power domains and its
>   registration. [Imre]
> 
> v2:
> - Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]
> 
> Cc: Ville Syrjälä 
> Cc: Kai Vehmanen 
> Cc: Uma Shankar 
> Cc: Imre Deak 
> Signed-off-by: Anshuman Gupta 

On the patchset:
Reviewed-by: Imre Deak 

> ---
>  .../drm/i915/display/intel_display_power.c| 234 --
>  .../drm/i915/display/intel_display_power.h|   3 +-
>  2 files changed, 221 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 81efc77bada0..2675b48d707e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -106,8 +106,10 @@ intel_display_power_domain_str(enum 
> intel_display_power_domain domain)
>   return "PORT_OTHER";
>   case POWER_DOMAIN_VGA:
>   return "VGA";
> - case POWER_DOMAIN_AUDIO:
> - return "AUDIO";
> + case POWER_DOMAIN_AUDIO_MMIO:
> + return "AUDIO_MMIO";
> + case POWER_DOMAIN_AUDIO_PLAYBACK:
> + return "AUDIO_PLAYBAK";
>   case POWER_DOMAIN_AUX_A:
>   return "AUX_A";
>   case POWER_DOMAIN_AUX_B:
> @@ -2519,7 +2521,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
>   BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
>   BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
>   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
>   BIT_ULL(POWER_DOMAIN_GMBUS) |   \
> @@ -2569,7 +2572,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
>   BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
>   BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
>   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> @@ -2602,7 +2606,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
>   BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
>   BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
>   BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define BDW_DISPLAY_POWER_DOMAINS (  \
> @@ -2618,7 +2623,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
>   BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
>   BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
>   BIT_ULL(POWER_DOMAIN_INIT))
>  
>  #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (  \
> @@ -2636,7 +2642,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
>   BIT_ULL(POWER_DOMAIN_VGA) | \
>   BIT_ULL(POWER_DOMAIN_INIT))
>  #define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS (   \
> @@ -2671,7 +2678,8 @@ intel_display_power_put_mask_in_set(struct 
> drm_i915_private *i915,
>   BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
>   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
>   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> - BIT_ULL(POWER_DOMAIN_AUDIO) |   

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add workaround to disable CMTG clock gating

[Imre Deak]

On Tue, Jul 27, 2021 at 10:51:22PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
> URL   : https://patchwork.freedesktop.org/series/93067/
> State : failure

Thanks for the review pushed to -din with the checkpatch errors fixed.

The failure on TGL is unrelated.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20716_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_20716_full absolutely need to 
> be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_20716_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_20716_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_exec_schedule@independent@vcs1:
> - shard-tglb: [PASS][1] -> [FAIL][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@gem_exec_schedule@independ...@vcs1.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-tglb6/igt@gem_exec_schedule@independ...@vcs1.html
> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
> - {shard-rkl}:[SKIP][3] ([i915#1845]) -> [DMESG-WARN][4]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
> 
>   * igt@runner@aborted:
> - {shard-rkl}:([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8]) 
> ([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][9], 
> [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13]) ([i915#2029] / [i915#3002] / 
> [i915#3621] / [i915#3810] / [i915#3811])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-6/igt@run...@aborted.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@run...@aborted.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@run...@aborted.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-2/igt@run...@aborted.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-1/igt@run...@aborted.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-2/igt@run...@aborted.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_20716_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_persistence@engines-hostile-preempt:
> - shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) 
> +6 similar issues
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-snb7/igt@gem_ctx_persiste...@engines-hostile-preempt.html
> 
>   * igt@gem_eio@in-flight-suspend:
> - shard-kbl:  [PASS][15] -> [INCOMPLETE][16] ([i915#155])
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_...@in-flight-suspend.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl3/igt@gem_...@in-flight-suspend.html
> 
>   * igt@gem_exec_fair@basic-deadline:
> - shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2846])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk1/igt@gem_exec_f...@basic-deadline.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk9/igt@gem_exec_f...@basic-deadline.html
> 
>   * igt@gem_exec_fair@basic-none-vip@rcs0:
> - shard-kbl:  [PASS][19] -> [FAIL][20] ([i915#2842])
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk:  [PASS][21] -> [FAIL][22] ([i915#2842])
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs

Re: [Intel-gfx] refactor the i915 GVT support

[Wang, Zhi A]

Hi Jason:

I guess those APIs you were talking about are KVM-only. For other hypervisors, 
e.g. Xen, ARCN cannot use the APIs you mentioned. Not sure if you have already 
noticed that VFIO is KVM-only right now.

GVT-g is designed for many hypervisors not only KVM. In the design, we 
implemented an abstraction layer for different hypervisors. You can check the 
link in the previous email which has an example of how the MPT module "xengt" 
supports GVT-g running under Xen. 
For example, injecting a msi in VFIO/KVM is via playing with eventfd. But in 
Xen, we need to issue a hypercall from Dom0. So does others, like querying 
mappings between GFN and HFN. Some GPU related emulation logic might be 
implemented differently under different hypervisors because different 
hypervisors might provide not exact the APIs we want. That's the reason why 
they get a callback in the MPT (yet not perfect.)  

As you can see, to survive from this situation, we have to rely on an 
abstraction layer so that we can prevent introducing coding blocks like in the 
core logic:

If (in_hypervisor_xen)
Issue hypercalls
else if (in_hypervisor_kvm)
Play with eventfds.
Else if (in_hypervisor_other)


Thus some of the APIs have to be wrapped in the MPT module in GVT-g design.

Sadly, not all customers are motivated or allowed to get their 
hypervisor-specific modules into the kernel. We have a customer who runs GVT-g 
with their private hypervisor. In this case, they don't want to get their 
"xxxgt" MPT module into upstream since their hypervisor has been in the kernel 
yet. Also, we have customers who ported the GVT-g to QNX which is another 
widely used commercial hypervisor in the industry. They can't get the "qnxgt" 
MPT module into upstream since it's not allowed.

We do understand the situation and try to figure out a solution that can 
fulfill expectations from different people in the community and also customers. 

According to Greg KH's comments, we are collecting the requirements of MPT 
modules from other open-source hypervisors in the kernel, e.g. ACRN, to see if 
they can get another MPT module into the kernel, which will show an example 
that how the MPT abstraction can benefit. Also, we are evaluating the impact on 
our customers if we have to remove MPT abstraction in the kernel because there 
is only one MPT module. 

Thanks so much for the comments.

Thanks,
Zhi.

-Original Message-
From: Jason Gunthorpe  
Sent: Tuesday, July 27, 2021 3:12 PM
To: Gerd Hoffmann 
Cc: Wang, Zhi A ; Christoph Hellwig ; Jani 
Nikula ; Joonas Lahtinen 
; Vivi, Rodrigo ; 
Zhenyu Wang ; intel-gfx@lists.freedesktop.org; 
intel-gvt-...@lists.freedesktop.org; linux-ker...@vger.kernel.org; 
dri-de...@lists.freedesktop.org
Subject: Re: refactor the i915 GVT support

On Thu, Jul 22, 2021 at 01:26:36PM +0200, Gerd Hoffmann wrote:
>   Hi,
> 
> > https://github.com/intel/gvt-linux/blob/topic/gvt-xengt/drivers/gpu/
> > drm/i915/gvt/xengt.c
> 
> > But it's hard for some customers to contribute their own "hypervisor"
> > module to the upstream Linux kernel. I am thinking what would be a 
> > better solution here? The MPT layer in the kernel helps a lot for 
> > customers, but only one open-source "hypervisor" module is there in 
> > the kernel. That can confuse people which don't know the story.  One 
> > thing I was thinking is to put a document about the background and 
> > more description in the MPT headers. So it won't confuse more people.
> 
> Getting the xengt module linked above merged into mainline would also 
> nicely explain why there are hypervisor modules.

It would also be nice to explain why a GPU driver needs a hypervisor specific 
shim like this in the first place.

enum hypervisor_type type;
int (*host_init)(struct device *dev, void *gvt, const void *ops);
void (*host_exit)(struct device *dev, void *gvt);
int (*attach_vgpu)(void *vgpu, unsigned long *handle);
void (*detach_vgpu)(void *vgpu);

Doesn't vfio provide all this generically with notifiers?

int (*inject_msi)(unsigned long handle, u32 addr, u16 data);

Isn't this one just an eventfd?

unsigned long (*from_virt_to_mfn)(void *p);
int (*read_gpa)(unsigned long handle, unsigned long gpa, void *buf,
unsigned long len);
int (*write_gpa)(unsigned long handle, unsigned long gpa, void *buf,
 unsigned long len);
unsigned long (*gfn_to_mfn)(unsigned long handle, unsigned long gfn);

int (*dma_map_guest_page)(unsigned long handle, unsigned long gfn,
  unsigned long size, dma_addr_t *dma_addr);
void (*dma_unmap_guest_page)(unsigned long handle, dma_addr_t dma_addr);

int (*dma_pin_guest_page)(unsigned long handle, dma_addr_t dma_addr);

int (*map_gfn_to_mfn)(unsigned long handle, unsigned long gfn,
  unsigned long mfn, unsigned int nr, bool

Re: [Intel-gfx] refactor the i915 GVT support

[Greg KH]

A: http://en.wikipedia.org/wiki/Top_post
Q: Were do I find info about this thing called top-posting?
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?

A: No.
Q: Should I include quotations after my reply?

http://daringfireball.net/2007/07/on_top

On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote:
> Hi Jason:
> 
> I guess those APIs you were talking about are KVM-only. For other 
> hypervisors, e.g. Xen, ARCN cannot use the APIs you mentioned. Not sure if 
> you have already noticed that VFIO is KVM-only right now.

Please wrap your lines properly :(

> GVT-g is designed for many hypervisors not only KVM. In the design, we 
> implemented an abstraction layer for different hypervisors. You can check the 
> link in the previous email which has an example of how the MPT module "xengt" 
> supports GVT-g running under Xen. 
> For example, injecting a msi in VFIO/KVM is via playing with eventfd. But in 
> Xen, we need to issue a hypercall from Dom0. So does others, like querying 
> mappings between GFN and HFN. Some GPU related emulation logic might be 
> implemented differently under different hypervisors because different 
> hypervisors might provide not exact the APIs we want. That's the reason why 
> they get a callback in the MPT (yet not perfect.)  
> 
> As you can see, to survive from this situation, we have to rely on an 
> abstraction layer so that we can prevent introducing coding blocks like in 
> the core logic:
> 
> If (in_hypervisor_xen)
>   Issue hypercalls
> else if (in_hypervisor_kvm)
>   Play with eventfds.
> Else if (in_hypervisor_other)
>   

That's horrid, and slow, please do this properly.

> Thus some of the APIs have to be wrapped in the MPT module in GVT-g design.
> 
> Sadly, not all customers are motivated or allowed to get their 
> hypervisor-specific modules into the kernel. We have a customer who runs 
> GVT-g with their private hypervisor. In this case, they don't want to get 
> their "xxxgt" MPT module into upstream since their hypervisor has been in the 
> kernel yet. Also, we have customers who ported the GVT-g to QNX which is 
> another widely used commercial hypervisor in the industry. They can't get the 
> "qnxgt" MPT module into upstream since it's not allowed.

Why is it not allowed?

> We do understand the situation and try to figure out a solution that can 
> fulfill expectations from different people in the community and also 
> customers. 
> 
> According to Greg KH's comments, we are collecting the requirements of MPT 
> modules from other open-source hypervisors in the kernel, e.g. ACRN, to see 
> if they can get another MPT module into the kernel, which will show an 
> example that how the MPT abstraction can benefit. Also, we are evaluating the 
> impact on our customers if we have to remove MPT abstraction in the kernel 
> because there is only one MPT module. 

Until that happens, can we please just remove the unneeded layer here as
no one is using it?  Then, when you have a real user for this type of
middle-layer, you can add it back?  We have no need for it now.

thanks,

greg k-h
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain

[Gupta, Anshuman]

> -Original Message-
> From: Deak, Imre 
> Sent: Wednesday, July 28, 2021 7:02 PM
> To: Gupta, Anshuman 
> Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä 
> ;
> Kai Vehmanen ; Shankar, Uma
> 
> Subject: Re: [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain
> 
> On Wed, Jul 28, 2021 at 05:22:16PM +0530, Anshuman Gupta wrote:
> > DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well.
> > Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS
> for
> > audio detection and POWER_DOMAIN_AUDIO for audio playback.
> >
> > v1: Changes since RFC
> > - changed power domain names. [Imre]
> > - Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
> >   power well and PW_3 power domains. [Imre]
> > - Fixed the order of powe wells , power domains and its
> >   registration. [Imre]
> >
> > v2:
> > - Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]
> >
> > Cc: Ville Syrjälä 
> > Cc: Kai Vehmanen 
> > Cc: Uma Shankar 
> > Cc: Imre Deak 
> > Signed-off-by: Anshuman Gupta 
> 
> On the patchset:
> Reviewed-by: Imre Deak 
Thanks Imre for providing RB. 
Does RB on patchset means RB for all three patches in the series?
Br,
Anshuman Gupta.
 
> 
> > ---
> >  .../drm/i915/display/intel_display_power.c| 234 --
> >  .../drm/i915/display/intel_display_power.h|   3 +-
> >  2 files changed, 221 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 81efc77bada0..2675b48d707e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -106,8 +106,10 @@ intel_display_power_domain_str(enum
> intel_display_power_domain domain)
> > return "PORT_OTHER";
> > case POWER_DOMAIN_VGA:
> > return "VGA";
> > -   case POWER_DOMAIN_AUDIO:
> > -   return "AUDIO";
> > +   case POWER_DOMAIN_AUDIO_MMIO:
> > +   return "AUDIO_MMIO";
> > +   case POWER_DOMAIN_AUDIO_PLAYBACK:
> > +   return "AUDIO_PLAYBAK";
> > case POWER_DOMAIN_AUX_A:
> > return "AUX_A";
> > case POWER_DOMAIN_AUX_B:
> > @@ -2519,7 +2521,8 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > -   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > BIT_ULL(POWER_DOMAIN_GMBUS) |   \
> > @@ -2569,7 +2572,8 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > -   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> > @@ -2602,7 +2606,8 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > -   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> >  #define BDW_DISPLAY_POWER_DOMAINS (\
> > @@ -2618,7 +2623,8 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > -   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> >  #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (\
> > @@ -2636,7 +2642,8 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> > BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> > -   BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > +   BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > BIT_ULL(POWER_D

[Intel-gfx] [PATCH] drm/i915: Use Transparent Hugepages when IOMMU is enabled

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Usage of Transparent Hugepages was disabled in 9987da4b5dcf
("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
appears majority of performance regressions reported with an enabled IOMMU
can be almost eliminated by turning them on, lets do that by adding a
couple of Kconfig options.

To err on the side of safety we keep the current default in cases where
IOMMU is not active, and only when it is default to the "huge=within_size"
mode. Although there probably would be wins to enable them throughout,
more extensive testing across benchmarks and platforms would need to be
done.

With the patch and IOMMU enabled my local testing on a small Skylake part
shows OglVSTangent regression being reduced from ~14% to ~2%.

References: b901bb89324a ("drm/i915/gemfs: enable THP")
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW 
W/A")
References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
Co-developed-by: Chris Wilson 
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
Cc: Eero Tamminen 
Cc: Tvrtko Ursulin 
Signed-off-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/Kconfig.profile  | 46 +++
 drivers/gpu/drm/i915/gem/i915_gemfs.c | 11 +--
 2 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.profile 
b/drivers/gpu/drm/i915/Kconfig.profile
index 39328567c200..c64c3d39a0f9 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -119,3 +119,49 @@ config DRM_I915_TIMESLICE_DURATION
  /sys/class/drm/card?/engine/*/timeslice_duration_ms
 
  May be 0 to disable timeslicing.
+
+choice
+   prompt "Transparent Hugepage Support (native)"
+   default DRM_I915_THP_NATIVE_NEVER
+   help
+ Select the preferred method for allocating from Transparent Hugepages
+ when IOMMU is not enabled.
+
+   config DRM_I915_THP_NATIVE_NEVER
+   bool "Never"
+
+   config DRM_I915_THP_NATIVE_WITHIN
+   bool "Within"
+
+   config DRM_I915_THP_NATIVE_ALWAYS
+   bool "Always"
+endchoice
+
+config DRM_I915_THP_NATIVE
+   string
+   default "always" if DRM_I915_THP_NATIVE_ALWAYS
+   default "within_size" if DRM_I915_THP_NATIVE_WITHIN
+   default "never" if DRM_I915_THP_NATIVE_NEVER
+
+choice
+   prompt "Transparent Hugepage Support (IOMMU)"
+   default DRM_I915_THP_IOMMU_WITHIN
+   help
+ Select the preferred method for allocating from Transparent Hugepages
+ with IOMMU active.
+
+   config DRM_I915_THP_IOMMU_NEVER
+   bool "Never"
+
+   config DRM_I915_THP_IOMMU_WITHIN
+   bool "Within"
+
+   config DRM_I915_THP_IOMMU_ALWAYS
+   bool "Always"
+endchoice
+
+config DRM_I915_THP_IOMMU
+   string
+   default "always" if DRM_I915_THP_IOMMU_ALWAYS
+   default "within_size" if DRM_I915_THP_IOMMU_WITHIN
+   default "never" if DRM_I915_THP_IOMMU_NEVER
diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c 
b/drivers/gpu/drm/i915/gem/i915_gemfs.c
index 5e6e8c91ab38..b71d2b2d2ada 100644
--- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
+++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
@@ -13,8 +13,11 @@
 
 int i915_gemfs_init(struct drm_i915_private *i915)
 {
+   char thp_native[] = "huge=" CONFIG_DRM_I915_THP_NATIVE;
+   char thp_iommu[] = "huge=" CONFIG_DRM_I915_THP_IOMMU;
struct file_system_type *type;
struct vfsmount *gemfs;
+   char *opts;
 
type = get_fs_type("tmpfs");
if (!type)
@@ -26,15 +29,19 @@ int i915_gemfs_init(struct drm_i915_private *i915)
 *
 * One example, although it is probably better with a per-file
 * control, is selecting huge page allocations ("huge=within_size").
-* Currently unused due to bandwidth issues (slow reads) on Broadwell+.
+* However, we only do so to offset the overhead of iommu lookups
+* due to bandwidth issues (slow reads) on Broadwell+.
 */
+   opts = intel_vtd_active() ? thp_iommu : thp_native;
 
-   gemfs = kern_mount(type);
+   gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, opts);
if (IS_ERR(gemfs))
return PTR_ERR(gemfs);
 
i915->mm.gemfs = gemfs;
 
+   drm_info(&i915->drm, "Transparent Hugepage mode '%s'", opts);
+
return 0;
 }
 
-- 
2.30.2

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Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation

[Matthew Auld]

On Mon, 26 Jul 2021 at 17:10, Tvrtko Ursulin
 wrote:
>
>
> On 26/07/2021 16:14, Jason Ekstrand wrote:
> > On Mon, Jul 26, 2021 at 3:31 AM Maarten Lankhorst
> >  wrote:
> >>
> >> Op 23-07-2021 om 13:34 schreef Matthew Auld:
> >>> From: Chris Wilson 
> >>>
> >>> Jason Ekstrand requested a more efficient method than userptr+set-domain
> >>> to determine if the userptr object was backed by a complete set of pages
> >>> upon creation. To be more efficient than simply populating the userptr
> >>> using get_user_pages() (as done by the call to set-domain or execbuf),
> >>> we can walk the tree of vm_area_struct and check for gaps or vma not
> >>> backed by struct page (VM_PFNMAP). The question is how to handle
> >>> VM_MIXEDMAP which may be either struct page or pfn backed...
> >>>
> >>> With discrete we are going to drop support for set_domain(), so offering
> >>> a way to probe the pages, without having to resort to dummy batches has
> >>> been requested.
> >>>
> >>> v2:
> >>> - add new query param for the PROBE flag, so userspace can easily
> >>>check if the kernel supports it(Jason).
> >>> - use mmap_read_{lock, unlock}.
> >>> - add some kernel-doc.
> >>> v3:
> >>> - In the docs also mention that PROBE doesn't guarantee that the pages
> >>>will remain valid by the time they are actually used(Tvrtko).
> >>> - Add a small comment for the hole finding logic(Jason).
> >>> - Move the param next to all the other params which just return true.
> >>>
> >>> Testcase: igt/gem_userptr_blits/probe
> >>> Signed-off-by: Chris Wilson 
> >>> Signed-off-by: Matthew Auld 
> >>> Cc: Thomas Hellström 
> >>> Cc: Maarten Lankhorst 
> >>> Cc: Tvrtko Ursulin 
> >>> Cc: Jordan Justen 
> >>> Cc: Kenneth Graunke 
> >>> Cc: Jason Ekstrand 
> >>> Cc: Daniel Vetter 
> >>> Cc: Ramalingam C 
> >>> Reviewed-by: Tvrtko Ursulin 
> >>> Acked-by: Kenneth Graunke 
> >>> Reviewed-by: Jason Ekstrand 
> >>> ---
> >>>   drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> >>>   drivers/gpu/drm/i915/i915_getparam.c|  1 +
> >>>   include/uapi/drm/i915_drm.h | 20 ++
> >>>   3 files changed, 61 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c 
> >>> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> >>> index 56edfeff8c02..468a7a617fbf 100644
> >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> >>> @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops 
> >>> i915_gem_userptr_ops = {
> >>>
> >>>   #endif
> >>>
> >>> +static int
> >>> +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> >>> +{
> >>> + const unsigned long end = addr + len;
> >>> + struct vm_area_struct *vma;
> >>> + int ret = -EFAULT;
> >>> +
> >>> + mmap_read_lock(mm);
> >>> + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> >>> + /* Check for holes, note that we also update the addr below 
> >>> */
> >>> + if (vma->vm_start > addr)
> >>> + break;
> >>> +
> >>> + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> >>> + break;
> >>> +
> >>> + if (vma->vm_end >= end) {
> >>> + ret = 0;
> >>> + break;
> >>> + }
> >>> +
> >>> + addr = vma->vm_end;
> >>> + }
> >>> + mmap_read_unlock(mm);
> >>> +
> >>> + return ret;
> >>> +}
> >>> +
> >>>   /*
> >>>* Creates a new mm object that wraps some normal memory from the 
> >>> process
> >>>* context - user memory.
> >>> @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> >>>}
> >>>
> >>>if (args->flags & ~(I915_USERPTR_READ_ONLY |
> >>> - I915_USERPTR_UNSYNCHRONIZED))
> >>> + I915_USERPTR_UNSYNCHRONIZED |
> >>> + I915_USERPTR_PROBE))
> >>>return -EINVAL;
> >>>
> >>>if (i915_gem_object_size_2big(args->user_size))
> >>> @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> >>>return -ENODEV;
> >>>}
> >>>
> >>> + if (args->flags & I915_USERPTR_PROBE) {
> >>> + /*
> >>> +  * Check that the range pointed to represents real struct
> >>> +  * pages and not iomappings (at this moment in time!)
> >>> +  */
> >>> + ret = probe_range(current->mm, args->user_ptr, 
> >>> args->user_size);
> >>> + if (ret)
> >>> + return ret;
> >>> + }
> >>> +
> >>>   #ifdef CONFIG_MMU_NOTIFIER
> >>>obj = i915_gem_object_alloc();
> >>>if (obj == NULL)
> >>> diff --git a/drivers/gpu/drm/i915/i915_getparam.c 
> >>> b/drivers/gpu/drm/i915/i915_getparam.c
> >>> index 24e18219eb50..bbb7cac43eb4 100644
> >>> --- a/drivers/gpu/drm/i915/i915_getparam.c
> >>> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> >>> @@ 

Re: [Intel-gfx] [RESEND PATCH v6 03/14] drm/i915/utils: Replace dev_printk with drm helpers

[jim . cromie]

On Wed, Jul 21, 2021 at 1:55 PM Sean Paul  wrote:
>
> From: Sean Paul 
>
> Use drm logging helpers to add support for the upcoming tracefs
> implementation.
>
> Signed-off-by: Sean Paul 
> Link: 
> https://patchwork.freedesktop.org/patch/msgid/20200608210505.48519-4-s...@poorly.run
>  #v5
>
> Changes in v5:
> -Added to the set
> Changes in v6:
> -None
> ---
>  drivers/gpu/drm/i915/i915_utils.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_utils.c 
> b/drivers/gpu/drm/i915/i915_utils.c
> index f9e780dee9de..d858c92c6997 100644
> --- a/drivers/gpu/drm/i915/i915_utils.c
> +++ b/drivers/gpu/drm/i915/i915_utils.c
> @@ -30,10 +30,9 @@ __i915_printk(struct drm_i915_private *dev_priv, const 
> char *level,
> vaf.va = &args;
>
> if (is_error)
> -   dev_printk(level, kdev, "%pV", &vaf);
> +   drm_dev_printk(kdev, level, "%pV", &vaf);
> else
> -   dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
> -  __builtin_return_address(0), &vaf);
> +   drm_err(&dev_priv->drm, "%pV", &vaf);

its slightly jarring to see drm_err() in the !is_err branch.
warn or notice seems better.


>
> va_end(args);
>
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain

[Imre Deak]

On Wed, Jul 28, 2021 at 04:59:26PM +0300, Gupta, Anshuman wrote:
> 
> 
> > -Original Message-
> > From: Deak, Imre 
> > Sent: Wednesday, July 28, 2021 7:02 PM
> > To: Gupta, Anshuman 
> > Cc: intel-gfx@lists.freedesktop.org; Ville Syrjälä 
> > ;
> > Kai Vehmanen ; Shankar, Uma
> > 
> > Subject: Re: [PATCH 1/3] drm/i915/dg1: Adjust the AUDIO power domain
> > 
> > On Wed, Jul 28, 2021 at 05:22:16PM +0530, Anshuman Gupta wrote:
> > > DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power well.
> > > Adjusting the power domain accordingly to POWER_DOMAIN_AUDIO_VERBS
> > for
> > > audio detection and POWER_DOMAIN_AUDIO for audio playback.
> > >
> > > v1: Changes since RFC
> > > - changed power domain names. [Imre]
> > > - Removed TC{3,6}, AUX_USBC{3,6} and TBT from DG1
> > >   power well and PW_3 power domains. [Imre]
> > > - Fixed the order of powe wells , power domains and its
> > >   registration. [Imre]
> > >
> > > v2:
> > > - Not allowe DC states when AUDIO_MMIO domain enabled. [Imre]
> > >
> > > Cc: Ville Syrjälä 
> > > Cc: Kai Vehmanen 
> > > Cc: Uma Shankar 
> > > Cc: Imre Deak 
> > > Signed-off-by: Anshuman Gupta 
> > 
> > On the patchset:
> > Reviewed-by: Imre Deak 
> Thanks Imre for providing RB. 
> Does RB on patchset means RB for all three patches in the series?

Yes, patchset = series of 3 patches.

> Br,
> Anshuman Gupta.
>  
> > 
> > > ---
> > >  .../drm/i915/display/intel_display_power.c| 234 --
> > >  .../drm/i915/display/intel_display_power.h|   3 +-
> > >  2 files changed, 221 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 81efc77bada0..2675b48d707e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -106,8 +106,10 @@ intel_display_power_domain_str(enum
> > intel_display_power_domain domain)
> > >   return "PORT_OTHER";
> > >   case POWER_DOMAIN_VGA:
> > >   return "VGA";
> > > - case POWER_DOMAIN_AUDIO:
> > > - return "AUDIO";
> > > + case POWER_DOMAIN_AUDIO_MMIO:
> > > + return "AUDIO_MMIO";
> > > + case POWER_DOMAIN_AUDIO_PLAYBACK:
> > > + return "AUDIO_PLAYBAK";
> > >   case POWER_DOMAIN_AUX_A:
> > >   return "AUX_A";
> > >   case POWER_DOMAIN_AUX_B:
> > > @@ -2519,7 +2521,8 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >   BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
> > >   BIT_ULL(POWER_DOMAIN_PORT_CRT) |\
> > >   BIT_ULL(POWER_DOMAIN_VGA) | \
> > > - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > >   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > >   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > >   BIT_ULL(POWER_DOMAIN_GMBUS) |   \
> > > @@ -2569,7 +2572,8 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > >   BIT_ULL(POWER_DOMAIN_PORT_DSI) |\
> > >   BIT_ULL(POWER_DOMAIN_VGA) | \
> > > - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > >   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > >   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > >   BIT_ULL(POWER_DOMAIN_AUX_D) |   \
> > > @@ -2602,7 +2606,8 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > >   BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
> > >   BIT_ULL(POWER_DOMAIN_VGA) | \
> > > - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > >   BIT_ULL(POWER_DOMAIN_INIT))
> > >
> > >  #define BDW_DISPLAY_POWER_DOMAINS (  \
> > > @@ -2618,7 +2623,8 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >   BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> > >   BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */\
> > >   BIT_ULL(POWER_DOMAIN_VGA) | \
> > > - BIT_ULL(POWER_DOMAIN_AUDIO) |   \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) |  \
> > > + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) |  \
> > >   BIT_ULL(POWER_DOMAIN_INIT))
> > >
> > >  #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (  \
> > > @@ -2636,7 +2642,8 @@ intel_display_power_put_mask_in_set(struct
> > drm_i915_private *i915,
> > >   BIT_ULL(POWER_DOMAIN_AUX_B) |   \
> > >   BIT_ULL(POWER_DOMAIN_AUX_C) |   \
> > >   BIT_ULL(POWER_DOMAIN

Re: [Intel-gfx] [PATCH 07/10] drm/i915/bios: Enable parse of two DSI panels data

[Matt Atwood]

On Wed, Jul 21, 2021 at 10:43:35PM -0700, José Roberto de Souza wrote:
> Continuing the conversion from single integrated VBT data to two, now
> handling DSI data.
> 
> Cc: Ville Syrjälä 
> Cc: Jani Nikula 
> Signed-off-by: José Roberto de Souza 
Reviewed-by: Matt Atwood 
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c   |  12 +-
>  drivers/gpu/drm/i915/display/intel_bios.c| 163 ++-
>  drivers/gpu/drm/i915/display/intel_bios.h|   1 +
>  drivers/gpu/drm/i915/display/intel_dsi.c |   8 +-
>  drivers/gpu/drm/i915/display/intel_dsi_vbt.c |  58 ---
>  drivers/gpu/drm/i915/display/intel_panel.c   |   3 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c   |  14 +-
>  drivers/gpu/drm/i915/i915_drv.h  |  30 ++--
>  8 files changed, 161 insertions(+), 128 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 43ec7fcd3f5d2..0a8360d196cc7 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1846,7 +1846,8 @@ static void icl_dphy_param_init(struct intel_dsi 
> *intel_dsi)
>  {
>   struct drm_device *dev = intel_dsi->base.base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> - struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> + const struct vbt_dsi_info *vbt_dsi_info = 
> intel_bios_dsi_info(&intel_dsi->base);
> + struct mipi_config *mipi_config = vbt_dsi_info->config;
>   u32 tlpx_ns;
>   u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
>   u32 ths_prepare_ns, tclk_trail_ns;
> @@ -1977,6 +1978,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   struct intel_connector *intel_connector;
>   struct drm_connector *connector;
>   struct drm_display_mode *fixed_mode;
> + const struct vbt_dsi_info *vbt_dsi_info;
>   enum port port;
>  
>   if (!intel_bios_is_dsi_present(dev_priv, &port))
> @@ -2044,13 +2046,15 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
>   intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
>   intel_panel_setup_backlight(connector, INVALID_PIPE);
>  
> - if (dev_priv->vbt.dsi.config->dual_link)
> + vbt_dsi_info = intel_bios_dsi_info(encoder);
> +
> + if (vbt_dsi_info->config->dual_link)
>   intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
>   else
>   intel_dsi->ports = BIT(port);
>  
> - intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
> - intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
> + intel_dsi->dcs_backlight_ports = vbt_dsi_info->bl_ports;
> + intel_dsi->dcs_cabc_ports = vbt_dsi_info->cabc_ports;
>  
>   for_each_dsi_port(port, intel_dsi->ports) {
>   struct intel_dsi_host *host;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index de690e96de723..a1a1cc0c462fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1022,55 +1022,56 @@ parse_psr(struct drm_i915_private *i915, const struct 
> bdb_header *bdb,
>  }
>  
>  static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
> -   u16 version, enum port port)
> +   u16 version, enum port port,
> +   struct ddi_vbt_port_info *info)
>  {
> - if (!i915->vbt.dsi.config->dual_link || version < 197) {
> - i915->vbt.dsi.bl_ports = BIT(port);
> - if (i915->vbt.dsi.config->cabc_supported)
> - i915->vbt.dsi.cabc_ports = BIT(port);
> + if (!info->dsi.config->dual_link || version < 197) {
> + info->dsi.bl_ports = BIT(port);
> + if (info->dsi.config->cabc_supported)
> + info->dsi.cabc_ports = BIT(port);
>  
>   return;
>   }
>  
> - switch (i915->vbt.dsi.config->dl_dcs_backlight_ports) {
> + switch (info->dsi.config->dl_dcs_backlight_ports) {
>   case DL_DCS_PORT_A:
> - i915->vbt.dsi.bl_ports = BIT(PORT_A);
> + info->dsi.bl_ports = BIT(PORT_A);
>   break;
>   case DL_DCS_PORT_C:
> - i915->vbt.dsi.bl_ports = BIT(PORT_C);
> + info->dsi.bl_ports = BIT(PORT_C);
>   break;
>   default:
>   case DL_DCS_PORT_A_AND_C:
> - i915->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
> + info->dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
>   break;
>   }
>  
> - if (!i915->vbt.dsi.config->cabc_supported)
> + if (!info->dsi.config->cabc_supported)
>   return;
>  
> - switch (i915->vbt.dsi.config->dl_dcs_cabc_ports) {
> + switch (info->dsi.config->dl_dcs_cabc_ports) {
>   case DL_DCS_PORT_A:
> - i915->vbt.dsi.cabc_ports = BIT(PORT_A);
> + info->dsi.cabc_ports = BIT(PORT_A);
>   

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH v4 03/18] drm/sched: Add dependency tracking

[Melissa Wen]

On 07/28, Daniel Vetter wrote:
> On Wed, Jul 28, 2021 at 1:29 PM Christian König
>  wrote:
> > Am 27.07.21 um 13:09 schrieb Daniel Vetter:
> > > Adding a few more people to this bikeshed.
> > >
> > > On Mon, Jul 12, 2021 at 10:02 PM Daniel Vetter  
> > > wrote:
> > >
> > >> @@ -349,6 +367,13 @@ int drm_sched_job_init(struct drm_sched_job *job,
> > >> struct drm_sched_entity *entity,
> > >> void *owner);
> > >>   void drm_sched_job_arm(struct drm_sched_job *job);
> > >> +int drm_sched_job_await_fence(struct drm_sched_job *job,
> > >> + struct dma_fence *fence);
> > >> +int drm_sched_job_await_implicit(struct drm_sched_job *job,
> > >> +struct drm_gem_object *obj,
> > >> +bool write);
> > >> +
> > >> +
> > > I'm still waiting on the paint delivery for these two functions so I
> > > can finish this shed.
> >
> > Well I wouldn't call that bike shedding, good names are important.
> >
> > Just imaging we would have called the exclusive-fence write-fence instead.
> 
> Sure naming matters, but at least to my English understanding there's
> not a semantic different between telling something to await for
> something else (i.e. add a dependency) or to tell something to add a
> dependency (i.e. await that thing later on before you start doing your
> own thing).
> 
> Exclusive vs write fence otoh is a pretty big difference in what it means.
> 
> But also if there's consensus that I'm wrong then I'm happy to pick
> the more preferred of the two options I deem equivalent.
> 
> > What speaks against calling them add_dependency() and
> > _add_implicit_depencencies() ?
> 
> Nothing. I just like another ack on this before I rename it all. Also
> I wasnt sure what you'd want to name the implicit dependency thing.
> 
> Lucas, Boris, Melissa, any acks here?

so, my English is far from good; but _add_dependency sounds good to me.

Melissa

> -Daniel
> 
> > Regards,
> > Christian.
> >
> > >
> > > Thanks, Daniel
> > >
> > >>   void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
> > >>  struct drm_gpu_scheduler 
> > >> **sched_list,
> > >>  unsigned int num_sched_list);
> > >> --
> > >> 2.32.0
> > >>
> > >
> >
> 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch


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Re: [Intel-gfx] [PATCH 08/10] drm/i915/bios: Nuke panel_type

[Matt Atwood]

On Wed, Jul 21, 2021 at 10:43:36PM -0700, José Roberto de Souza wrote:
> All the users was converted now we can drop it.
> 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Signed-off-by: José Roberto de Souza 
Reviewed-by: Matt Atwood 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 36 ---
>  drivers/gpu/drm/i915/i915_drv.h   |  1 -
>  2 files changed, 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index a1a1cc0c462fd..d1ad6d625e521 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -211,41 +211,6 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
>   return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
>  }
>  
> -/*
> - * Parse and set vbt.panel_type, it will be used by the VBT blocks that are
> - * not being called from parse_integrated_panel() yet.
> - */
> -static void parse_panel_type(struct drm_i915_private *i915,
> -  const struct bdb_header *bdb)
> -{
> - const struct bdb_lvds_options *lvds_options;
> - int ret, panel_type;
> -
> - lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
> - if (!lvds_options)
> - return;
> -
> - ret = intel_opregion_get_panel_type(i915);
> - if (ret >= 0) {
> - drm_WARN_ON(&i915->drm, ret > 0xf);
> - panel_type = ret;
> - drm_dbg_kms(&i915->drm, "Panel type: %d (OpRegion)\n",
> - panel_type);
> - } else {
> - if (lvds_options->panel_type > 0xf) {
> - drm_dbg_kms(&i915->drm,
> - "Invalid VBT panel type 0x%x\n",
> - lvds_options->panel_type);
> - return;
> - }
> - panel_type = lvds_options->panel_type;
> - drm_dbg_kms(&i915->drm, "Panel type: %d (VBT)\n",
> - panel_type);
> - }
> -
> - i915->vbt.panel_type = panel_type;
> -}
> -
>  /* Parse general panel options */
>  static void
>  parse_panel_options(struct drm_i915_private *i915,
> @@ -2489,7 +2454,6 @@ void intel_bios_init(struct drm_i915_private *i915)
>   /* Grab useful general definitions */
>   parse_general_features(i915, bdb);
>   parse_general_definitions(i915, bdb);
> - parse_panel_type(i915, bdb);
>   parse_sdvo_panel_data(i915, bdb);
>   parse_driver_features(i915, bdb);
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index adcacb8cb248a..8a09f9ed881b9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -729,7 +729,6 @@ struct intel_vbt_data {
>   unsigned int int_lvds_support:1;
>   unsigned int display_clock_mode:1;
>   unsigned int fdi_rx_polarity_inverted:1;
> - unsigned int panel_type:4;
>   int lvds_ssc_freq;
>   unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
>   enum drm_panel_orientation orientation;
> -- 
> 2.32.0
> 
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Re: [Intel-gfx] [PATCH 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older

[Matt Atwood]

On Wed, Jul 21, 2021 at 10:43:37PM -0700, José Roberto de Souza wrote:
> On newer platform this opregion call always fails, also it do not
> support multiple panels so dropping it.
> 
> Cc: Ville Syrjälä 
> Cc: Jani Nikula 
> Signed-off-by: José Roberto de Souza 
Reviewed-by: Matt Atwood 
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 19 +++
>  1 file changed, 7 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index d1ad6d625e521..6c848384a2ada 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1924,7 +1924,7 @@ static void parse_integrated_panel(struct 
> drm_i915_private *i915,
>  {
>   const struct vbt_header *vbt = i915->opregion.vbt;
>   const struct bdb_header *bdb;
> - int lfp_inst = 0, panel_index, opregion_panel_index;
> + int lfp_inst = 0, panel_index;
>  
>   if (devdata->child.handle == HANDLE_LFP_1)
>   lfp_inst = 1;
> @@ -1937,17 +1937,12 @@ static void parse_integrated_panel(struct 
> drm_i915_private *i915,
>   bdb = get_bdb_header(vbt);
>   panel_index = get_lfp_panel_index(i915, bdb, lfp_inst);
>  
> - opregion_panel_index = intel_opregion_get_panel_type(i915);
> - /*
> -  * TODO: the current implementation always use the panel index from
> -  * opregion if available due to issues with old platforms.
> -  * But this do not supports two panels and in SKL or newer I never saw a
> -  * system were this call returns a valid value.
> -  * So will change this to only use opregion up to BDW in a separated
> -  * commit.
> -  */
> - if (opregion_panel_index >= 0)
> - panel_index = opregion_panel_index;
> + if (DISPLAY_VER(i915) < 9) {
> + int opregion_panel_index = intel_opregion_get_panel_type(i915);
> +
> + if (opregion_panel_index >= 0)
> + opregion_panel_index = panel_index;
> + }
>  
>   if (panel_index == -1)
>   return;
> -- 
> 2.32.0
> 
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Re: [Intel-gfx] [PATCH 10/10] drm/i915/display/tgl+: Use PPS index from vbt

[Matt Atwood]

On Wed, Jul 21, 2021 at 10:43:38PM -0700, José Roberto de Souza wrote:
> Tigerlake and newer has two instances of PPS, to support up to two
> eDP panels.
> 
> Cc: Ville Syrjälä 
> Cc: Jani Nikula 
> Signed-off-by: José Roberto de Souza 
Reveiwed-by: Matt Atwood 
> ---
>  drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c 
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index f4c15a1f31d15..ee92f416834e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -368,7 +368,8 @@ static void intel_pps_get_registers(struct intel_dp 
> *intel_dp,
>  
>   memset(regs, 0, sizeof(*regs));
>  
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ||
> + DISPLAY_VER(dev_priv) >= 12)
>   pps_idx = bxt_power_sequencer_idx(intel_dp);
>   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>   pps_idx = vlv_power_sequencer_pipe(intel_dp);
> -- 
> 2.32.0
> 
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Re: [Intel-gfx] [PATCH 13/15] drm/i915/guc/slpc: Sysfs hooks for SLPC

[Belgaumkar, Vinay]

On 7/27/2021 9:59 AM, Michal Wajdeczko wrote:



On 26.07.2021 21:07, Vinay Belgaumkar wrote:

Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether SLPC is enabled.

v2: Add wrappers for getting rp0/1/n frequencies, update
softlimits in set min/max SLPC functions. Also check for
boundary conditions before setting them.

v3: Address review comments (Michal W)

Acked-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Sujaritha Sundaresan 
---
  drivers/gpu/drm/i915/gt/intel_rps.c | 165 
  drivers/gpu/drm/i915/gt/intel_rps.h |  11 ++
  drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c |  14 ++
  drivers/gpu/drm/i915/i915_pmu.c |   2 +-
  drivers/gpu/drm/i915/i915_reg.h |   2 +
  drivers/gpu/drm/i915/i915_sysfs.c   |  77 ++---
  6 files changed, 207 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index e858eeb2c59d..48d4147165a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps 
*rps)
return rps_to_gt(rps)->uncore;
  }
  
+static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)

+{
+   struct intel_gt *gt = rps_to_gt(rps);
+
+   return >->uc.guc.slpc;
+}
+
  static bool rps_uses_slpc(struct intel_rps *rps)
  {
struct intel_gt *gt = rps_to_gt(rps);
@@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps 
*rps)
return freq;
  }
  
+u32 intel_rps_read_punit_req(struct intel_rps *rps)

+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+
+   return intel_uncore_read(uncore, GEN6_RPNSWREQ);
+}
+
+u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq)


hmm, "rps" looks to be not needed here
btw, shouldn't this function be static ?


sure.




+{
+   u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
+
+   return req;
+}
+
+u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
+{
+   u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps));
+
+   return intel_gpu_freq(rps, freq);
+}
+
+u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
+{
+   if (rps_uses_slpc(rps))
+   return intel_rps_read_punit_req_frequency(rps);
+   else
+   return intel_gpu_freq(rps, rps->cur_freq);
+}
+
+u32 intel_rps_get_max_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->max_freq_softlimit;
+   else
+   return intel_gpu_freq(rps, rps->max_freq_softlimit);
+}
+
+u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->rp0_freq;
+   else
+   return intel_gpu_freq(rps, rps->rp0_freq);
+}
+
+u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->rp1_freq;
+   else
+   return intel_gpu_freq(rps, rps->rp1_freq);
+}
+
+u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->min_freq;
+   else
+   return intel_gpu_freq(rps, rps->min_freq);
+}
+
+int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+   int ret = 0;
+
+   if (rps_uses_slpc(rps))
+   return intel_guc_slpc_set_max_freq(slpc, val);


few above functions are implemented as nice dispatcher

if (rps_uses_slpc(rps))
return ... slpc stuff;
else
return ... gpu stuff;

can we have something similar here ?
likely just putting below code into helper will do the trick


ok.




+
+   mutex_lock(&rps->lock);
+
+   val = intel_freq_opcode(rps, val);
+   if (val < rps->min_freq ||
+   val > rps->max_freq ||
+   val < rps->min_freq_softlimit) {
+   ret = -EINVAL;
+   goto unlock;
+   }
+
+   if (val > rps->rp0_freq)
+   drm_dbg(&i915->drm, "User requested overclocking to %d\n",
+ intel_gpu_freq(rps, val));
+
+   rps->max_freq_softlimit = val;
+
+   val = clamp_t(int, rps->cur_freq,
+ rps->min_freq_softlimit,
+ rps->max_freq_softlimit);
+
+   /*
+* We still need *_set_rps to process the new max_delay and
+* update the interrup

[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave and Daniel,

Here goes drm-intel-fixes-2021-07-28:

Display related fixes:
- Fix vbt port mask
- Fix around reading the right DSC disable fuse in display_ver 10
- Split display version 9 and 10 in intel_setup_outputs

Thanks,
Rodrigo.

The following changes since commit ff1176468d368232b684f75e82563369208bc371:

  Linux 5.14-rc3 (2021-07-25 15:35:14 -0700)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-07-28

for you to fetch changes up to b4bde5554f70fb04ff07989fdc1356ab84d6f482:

  drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs() 
(2021-07-26 06:16:47 -0400)


Display related fixes:
- Fix vbt port mask
- Fix around reading the right DSC disable fuse in display_ver 10
- Split display version 9 and 10 in intel_setup_outputs


Lucas De Marchi (2):
  drm/i915: fix not reading DSC disable fuse in GLK
  drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()

Rodrigo Vivi (1):
  drm/i915/bios: Fix ports mask

 drivers/gpu/drm/i915/display/intel_bios.c| 3 ++-
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++-
 drivers/gpu/drm/i915/intel_device_info.c | 9 +
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adlp: Add workaround to disable CMTG clock gating

[Patchwork]

== Series Details ==

Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
URL   : https://patchwork.freedesktop.org/series/93067/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20716_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20716_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) 
([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][5], 
[FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9]) ([i915#2029] / [i915#3002] / 
[i915#3621] / [i915#3810] / [i915#3811])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-6/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-2/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-2/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20716_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +6 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-snb7/igt@gem_ctx_persiste...@engines-hostile-preempt.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][11] -> [INCOMPLETE][12] ([i915#155])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_...@in-flight-suspend.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl3/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2846])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk1/igt@gem_exec_f...@basic-deadline.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk9/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl6/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar 
issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb7/igt@gem_exec_fair@basic-p...@bcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  NOTRUN -> [FAIL][21] ([i915#2842]) +1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl1/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_schedule@independent@vcs1:
- shard-tglb: [PASS][22] -> [FAIL][23] ([i915#3795])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@gem_exec_schedule@independ...@vcs1.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-tglb6/igt@gem_exec_schedule@independ...@vcs1.html

  * igt@gem_exec_whisper@basic-fds-all:
- shard-glk:  [PASS][24] -> [DMESG-WARN][25] ([i915#118] / 
[i915#95]) +1 similar issue
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk8/igt@gem_exec_whis...@basic-fds-all.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk3/igt@gem_exec_whis...@basic-fds-all.html

  * igt@gem_mmap_gtt@cpuset-basic-small-

[Intel-gfx] [PATCH] drm/i915/selftests: fixup igt_shrink_thp

[Matthew Auld]

Since the object might still be active here, the shrink_all will simply
ignore it, which blows up in the test, since the pages will still be
there. Currently THP is disabled which should result in the test being
skipped, but if we ever re-enable THP we might start seeing the failure.
Fix this by forcing I915_SHRINK_ACTIVE.

Signed-off-by: Matthew Auld 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c 
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index a094f3ce1a90..7a67e880b562 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1575,7 +1575,10 @@ static int igt_shrink_thp(void *arg)
 * Now that the pages are *unpinned* shrink-all should invoke
 * shmem to truncate our pages.
 */
-   i915_gem_shrink_all(i915);
+   i915_gem_shrink(NULL, i915, -1UL, NULL,
+   I915_SHRINK_BOUND |
+   I915_SHRINK_UNBOUND |
+   I915_SHRINK_ACTIVE);
if (i915_gem_object_has_pages(obj)) {
pr_err("shrink-all didn't truncate the pages\n");
err = -EINVAL;
-- 
2.26.3

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[Intel-gfx] [PATCH] drm/i915/selftests: prefer the create_user helper

[Matthew Auld]

No need to hand roll the set_placements stuff, now that that we have a
helper for this. Also no need to handle the -ENODEV case here, since
NULL mr implies missing device support, where the for_each_memory_region
helper will always skip over such regions.

Signed-off-by: Matthew Auld 
Cc: Jason Ekstrand 
---
 .../drm/i915/gem/selftests/i915_gem_mman.c| 46 ++-
 1 file changed, 4 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c 
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 0b2b73d8a364..eed1c2c64e75 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -860,24 +860,6 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum 
i915_mmap_type type)
return !no_map;
 }
 
-static void object_set_placements(struct drm_i915_gem_object *obj,
- struct intel_memory_region **placements,
- unsigned int n_placements)
-{
-   GEM_BUG_ON(!n_placements);
-
-   if (n_placements == 1) {
-   struct drm_i915_private *i915 = to_i915(obj->base.dev);
-   struct intel_memory_region *mr = placements[0];
-
-   obj->mm.placements = &i915->mm.regions[mr->id];
-   obj->mm.n_placements = 1;
-   } else {
-   obj->mm.placements = placements;
-   obj->mm.n_placements = n_placements;
-   }
-}
-
 #define expand32(x) (((x) << 0) | ((x) << 8) | ((x) << 16) | ((x) << 24))
 static int __igt_mmap(struct drm_i915_private *i915,
  struct drm_i915_gem_object *obj,
@@ -972,15 +954,10 @@ static int igt_mmap(void *arg)
struct drm_i915_gem_object *obj;
int err;
 
-   obj = i915_gem_object_create_region(mr, sizes[i], 0, 
I915_BO_ALLOC_USER);
-   if (obj == ERR_PTR(-ENODEV))
-   continue;
-
+   obj = __i915_gem_object_create_user(i915, sizes[i], 
&mr, 1);
if (IS_ERR(obj))
return PTR_ERR(obj);
 
-   object_set_placements(obj, &mr, 1);
-
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap(i915, obj, I915_MMAP_TYPE_WC);
@@ -1101,15 +1078,10 @@ static int igt_mmap_access(void *arg)
struct drm_i915_gem_object *obj;
int err;
 
-   obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0, 
I915_BO_ALLOC_USER);
-   if (obj == ERR_PTR(-ENODEV))
-   continue;
-
+   obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (IS_ERR(obj))
return PTR_ERR(obj);
 
-   object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_access(i915, obj, I915_MMAP_TYPE_WB);
@@ -1248,15 +1220,10 @@ static int igt_mmap_gpu(void *arg)
struct drm_i915_gem_object *obj;
int err;
 
-   obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0, 
I915_BO_ALLOC_USER);
-   if (obj == ERR_PTR(-ENODEV))
-   continue;
-
+   obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (IS_ERR(obj))
return PTR_ERR(obj);
 
-   object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_gpu(i915, obj, I915_MMAP_TYPE_WC);
@@ -1405,15 +1372,10 @@ static int igt_mmap_revoke(void *arg)
struct drm_i915_gem_object *obj;
int err;
 
-   obj = i915_gem_object_create_region(mr, PAGE_SIZE, 0, 
I915_BO_ALLOC_USER);
-   if (obj == ERR_PTR(-ENODEV))
-   continue;
-
+   obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &mr, 1);
if (IS_ERR(obj))
return PTR_ERR(obj);
 
-   object_set_placements(obj, &mr, 1);
-
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_GTT);
if (err == 0)
err = __igt_mmap_revoke(i915, obj, I915_MMAP_TYPE_WC);
-- 
2.26.3

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use Transparent Hugepages when IOMMU is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled
URL   : https://patchwork.freedesktop.org/series/93122/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1e72a7f59823 drm/i915: Use Transparent Hugepages when IOMMU is enabled
-:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable 
THP until we have a GPU read BW W/A")'
#6: 
Usage of Transparent Hugepages was disabled in 9987da4b5dcf

-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit b901bb89324a ("drm/i915/gemfs: 
enable THP")'
#21: 
References: b901bb89324a ("drm/i915/gemfs: enable THP")

-:22: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#22: 
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW 
W/A")

-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 9987da4b5dcf ("drm/i915: Disable 
THP until we have a GPU read BW W/A")'
#22: 
References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW 
W/A")

total: 3 errors, 1 warnings, 0 checks, 81 lines checked


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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add workaround to disable CMTG clock gating

[Vudum, Lakshminarayana]

Re-reported the series.

-Original Message-
From: Deak, Imre  
Sent: Wednesday, July 28, 2021 6:34 AM
To: intel-gfx@lists.freedesktop.org; Souza, Jose ; Vudum, 
Lakshminarayana 
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/adlp: Add workaround to disable 
CMTG clock gating

On Tue, Jul 27, 2021 at 10:51:22PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/adlp: Add workaround to disable CMTG clock gating
> URL   : https://patchwork.freedesktop.org/series/93067/
> State : failure

Thanks for the review pushed to -din with the checkpatch errors fixed.

The failure on TGL is unrelated.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_10404_full -> Patchwork_20716_full 
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_20716_full absolutely need to 
> be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_20716_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_20716_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_exec_schedule@independent@vcs1:
> - shard-tglb: [PASS][1] -> [FAIL][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-tglb1/igt@gem_exec_schedule@independ...@vcs1.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-tglb6/i
> gt@gem_exec_schedule@independ...@vcs1.html
> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
> - {shard-rkl}:[SKIP][3] ([i915#1845]) -> [DMESG-WARN][4]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/i
> gt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html
> 
>   * igt@runner@aborted:
> - {shard-rkl}:([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8]) 
> ([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][9], 
> [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13]) ([i915#2029] / [i915#3002] / 
> [i915#3621] / [i915#3810] / [i915#3811])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-6/igt@run...@aborted.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-1/igt@run...@aborted.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-5/igt@run...@aborted.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-rkl-2/igt@run...@aborted.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-1/igt@run...@aborted.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-2/igt@run...@aborted.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/igt@run...@aborted.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-rkl-6/i
> gt@run...@aborted.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_20716_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_persistence@engines-hostile-preempt:
> - shard-snb:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) 
> +6 similar issues
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-snb7/ig
> t@gem_ctx_persiste...@engines-hostile-preempt.html
> 
>   * igt@gem_eio@in-flight-suspend:
> - shard-kbl:  [PASS][15] -> [INCOMPLETE][16] ([i915#155])
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl7/igt@gem_...@in-flight-suspend.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-kbl3/ig
> t@gem_...@in-flight-suspend.html
> 
>   * igt@gem_exec_fair@basic-deadline:
> - shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2846])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-glk1/igt@gem_exec_f...@basic-deadline.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20716/shard-glk9/ig
> t@gem_exec_f...@basic-deadline.html
> 
>   * igt@gem_exec_fair@basic-none-vip@rcs0:
> - shard-kbl:  [PASS][19] -> [FAIL][20] ([i915#2842])
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10404/shard-kbl4/igt@gem_exec_fair@basic-none-...@rcs0.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/

Re: [Intel-gfx] [PATCH] drm/i915: Use Transparent Hugepages when IOMMU is enabled

[Rodrigo Vivi]

On Wed, Jul 28, 2021 at 03:12:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Usage of Transparent Hugepages was disabled in 9987da4b5dcf
> ("drm/i915: Disable THP until we have a GPU read BW W/A"), but since it
> appears majority of performance regressions reported with an enabled IOMMU
> can be almost eliminated by turning them on, lets do that by adding a
> couple of Kconfig options.
> 
> To err on the side of safety we keep the current default in cases where
> IOMMU is not active, and only when it is default to the "huge=within_size"
> mode. Although there probably would be wins to enable them throughout,
> more extensive testing across benchmarks and platforms would need to be
> done.
> 
> With the patch and IOMMU enabled my local testing on a small Skylake part
> shows OglVSTangent regression being reduced from ~14% to ~2%.
> 
> References: b901bb89324a ("drm/i915/gemfs: enable THP")
> References: 9987da4b5dcf ("drm/i915: Disable THP until we have a GPU read BW 
> W/A")
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/430
> Co-developed-by: Chris Wilson 
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
> Cc: Matthew Auld 
> Cc: Eero Tamminen 
> Cc: Tvrtko Ursulin 
> Signed-off-by: Tvrtko Ursulin 
> ---
>  drivers/gpu/drm/i915/Kconfig.profile  | 46 +++
>  drivers/gpu/drm/i915/gem/i915_gemfs.c | 11 +--
>  2 files changed, 55 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/Kconfig.profile 
> b/drivers/gpu/drm/i915/Kconfig.profile
> index 39328567c200..c64c3d39a0f9 100644
> --- a/drivers/gpu/drm/i915/Kconfig.profile
> +++ b/drivers/gpu/drm/i915/Kconfig.profile
> @@ -119,3 +119,49 @@ config DRM_I915_TIMESLICE_DURATION
> /sys/class/drm/card?/engine/*/timeslice_duration_ms
>  
> May be 0 to disable timeslicing.
> +
> +choice
> + prompt "Transparent Hugepage Support (native)"
> + default DRM_I915_THP_NATIVE_NEVER
> + help
> +   Select the preferred method for allocating from Transparent Hugepages
> +   when IOMMU is not enabled.
> +
> + config DRM_I915_THP_NATIVE_NEVER
> + bool "Never"
> +
> + config DRM_I915_THP_NATIVE_WITHIN
> + bool "Within"
> +
> + config DRM_I915_THP_NATIVE_ALWAYS
> + bool "Always"
> +endchoice
> +
> +config DRM_I915_THP_NATIVE
> + string
> + default "always" if DRM_I915_THP_NATIVE_ALWAYS
> + default "within_size" if DRM_I915_THP_NATIVE_WITHIN
> + default "never" if DRM_I915_THP_NATIVE_NEVER
> +
> +choice
> + prompt "Transparent Hugepage Support (IOMMU)"
> + default DRM_I915_THP_IOMMU_WITHIN
> + help
> +   Select the preferred method for allocating from Transparent Hugepages
> +   with IOMMU active.
> +
> + config DRM_I915_THP_IOMMU_NEVER
> + bool "Never"
> +
> + config DRM_I915_THP_IOMMU_WITHIN
> + bool "Within"
> +
> + config DRM_I915_THP_IOMMU_ALWAYS
> + bool "Always"
> +endchoice
> +
> +config DRM_I915_THP_IOMMU
> + string
> + default "always" if DRM_I915_THP_IOMMU_ALWAYS
> + default "within_size" if DRM_I915_THP_IOMMU_WITHIN
> + default "never" if DRM_I915_THP_IOMMU_NEVER
> diff --git a/drivers/gpu/drm/i915/gem/i915_gemfs.c 
> b/drivers/gpu/drm/i915/gem/i915_gemfs.c
> index 5e6e8c91ab38..b71d2b2d2ada 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gemfs.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gemfs.c
> @@ -13,8 +13,11 @@
>  
>  int i915_gemfs_init(struct drm_i915_private *i915)
>  {
> + char thp_native[] = "huge=" CONFIG_DRM_I915_THP_NATIVE;
> + char thp_iommu[] = "huge=" CONFIG_DRM_I915_THP_IOMMU;
>   struct file_system_type *type;
>   struct vfsmount *gemfs;
> + char *opts;
>  
>   type = get_fs_type("tmpfs");
>   if (!type)
> @@ -26,15 +29,19 @@ int i915_gemfs_init(struct drm_i915_private *i915)
>*
>* One example, although it is probably better with a per-file
>* control, is selecting huge page allocations ("huge=within_size").
> -  * Currently unused due to bandwidth issues (slow reads) on Broadwell+.
> +  * However, we only do so to offset the overhead of iommu lookups
> +  * due to bandwidth issues (slow reads) on Broadwell+.
>*/
> + opts = intel_vtd_active() ? thp_iommu : thp_native;

at first sight I got confused on why we where having to configs, then
very few drivers using the mount option there, so it took me a few
minutes to realize it... but I know understood the goal...

Reviewed-by: Rodrigo Vivi 

>  
> - gemfs = kern_mount(type);
> + gemfs = vfs_kern_mount(type, SB_KERNMOUNT, type->name, opts);
>   if (IS_ERR(gemfs))
>   return PTR_ERR(gemfs);
>  
>   i915->mm.gemfs = gemfs;
>  
> + drm_info(&i915->drm, "Transparent Hugepage mode '%s'", opts);
> +
>   return 0;
>  }
>  
> -- 
> 2.30.2
> 
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Re: [Intel-gfx] [PATCH 1/1] drm/i915/dmc: Bump ADLP DMC version to v2.11

[Imre Deak]

On Tue, Jul 27, 2021 at 11:55:05AM -0700, Anusha Srivatsa wrote:
> Release notes mention that this verion has:
> - Fixes for DC6v issue.
> - Flip queue enabled on pipe C and pipe D.
> 
> Cc: Imre Deak 
> Signed-off-by: Anusha Srivatsa 

I suggest merging this only once we can look at the firmware source. I
can't see this yet for v2.11.

> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 9895fd957df9..601c30b92739 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -45,8 +45,8 @@
>  
>  #define GEN12_DMC_MAX_FW_SIZEICL_DMC_MAX_FW_SIZE
>  
> -#define ADLP_DMC_PATHDMC_PATH(adlp, 2, 10)
> -#define ADLP_DMC_VERSION_REQUIREDDMC_VERSION(2, 10)
> +#define ADLP_DMC_PATHDMC_PATH(adlp, 2, 11)
> +#define ADLP_DMC_VERSION_REQUIREDDMC_VERSION(2, 11)
>  MODULE_FIRMWARE(ADLP_DMC_PATH);
>  
>  #define ADLS_DMC_PATHDMC_PATH(adls, 2, 01)
> -- 
> 2.32.0
> 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use Transparent Hugepages when IOMMU is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Use Transparent Hugepages when IOMMU is enabled
URL   : https://patchwork.freedesktop.org/series/93122/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10411 -> Patchwork_20724


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20724 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20724, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_20724:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@hugepages:
- fi-tgl-u2:  [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-tgl-u2/igt@i915_selftest@l...@hugepages.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-tgl-u2/igt@i915_selftest@l...@hugepages.html
- fi-icl-y:   [PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-icl-y/igt@i915_selftest@l...@hugepages.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-icl-y/igt@i915_selftest@l...@hugepages.html
- fi-ivb-3770:[PASS][5] -> [DMESG-FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-ivb-3770/igt@i915_selftest@l...@hugepages.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-ivb-3770/igt@i915_selftest@l...@hugepages.html
- fi-kbl-x1275:   [PASS][7] -> [DMESG-FAIL][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-kbl-x1275/igt@i915_selftest@l...@hugepages.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-kbl-x1275/igt@i915_selftest@l...@hugepages.html
- fi-tgl-1115g4:  [PASS][9] -> [DMESG-FAIL][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-tgl-1115g4/igt@i915_selftest@l...@hugepages.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-tgl-1115g4/igt@i915_selftest@l...@hugepages.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@hugepages:
- {fi-ehl-2}: [PASS][11] -> [DMESG-FAIL][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-ehl-2/igt@i915_selftest@l...@hugepages.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-ehl-2/igt@i915_selftest@l...@hugepages.html
- {fi-jsl-1}: [PASS][13] -> [DMESG-FAIL][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-jsl-1/igt@i915_selftest@l...@hugepages.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-jsl-1/igt@i915_selftest@l...@hugepages.html

  
Known issues


  Here are the changes found in Patchwork_20724 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[PASS][15] -> [DMESG-FAIL][16] ([i915#2927])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#1436])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-bsw-nick/igt@run...@aborted.html
- fi-kbl-soraka:  NOTRUN -> [FAIL][18] ([i915#1569] / [i915#192] / 
[i915#193] / [i915#194] / [i915#2426] / [i915#3363])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-kbl-soraka/igt@run...@aborted.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [FAIL][19] ([i915#1888]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20724/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/

Re: [Intel-gfx] [PATCH 1/1] drm/i915: dgfx cards need to wait on pcode's uncore init done

[Rodrigo Vivi]

On Tue, Jul 27, 2021 at 11:03:38PM +0530, badal.nila...@intel.com wrote:
> From: Badal Nilawar 
> 
> In discrete cards, the graphics driver shouldn't proceed with the probe
> or resume unless PCODE indicated everything is done, including memory
> training and gt bring up.
> 
> For this reason, the driver probe and resume paths needs to be blocked
> until PCODE indicates it is done. Also, it needs to aborted if the
> notification never arrives.
> 
> In general, the few miliseconds would be enough and the regular PCODE
> recommendation for the timeout was 10 seconds. However there are some
> rare cases where this initialization can take up to 1 minute. So,
> PCODE has increased the recommendation to 3 minutes so we don't fully
> block the device utilization when something just got delayed for
> whatever reason. To be on the safest side, let's accept this
> recommendation, since on the regular case it won't delay or block the
> driver initialization and resume flows
> 
> Cc: Rodrigo Vivi 
> Signed-off-by: Badal Nilawar 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/i915_drv.c   |  8 +++-
>  drivers/gpu/drm/i915/intel_sideband.c | 13 +
>  drivers/gpu/drm/i915/intel_sideband.h |  2 +-
>  3 files changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c43b698bf0b97..59fb4c710c8ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -620,7 +620,9 @@ static int i915_driver_hw_probe(struct drm_i915_private 
> *dev_priv)
>  
>   intel_opregion_setup(dev_priv);
>  
> - intel_pcode_init(dev_priv);
> + ret = intel_pcode_init(dev_priv);
> + if (ret)
> + goto err_msi;
>  
>   /*
>* Fill the dram structure to get the system dram info. This will be
> @@ -1231,6 +1233,10 @@ static int i915_drm_resume(struct drm_device *dev)
>  
>   disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
> + ret = intel_pcode_init(dev_priv);
> + if (ret)
> + return ret;
> +
>   sanitize_gpu(dev_priv);
>  
>   ret = i915_ggtt_enable_hw(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c 
> b/drivers/gpu/drm/i915/intel_sideband.c
> index f0a82b37bd1ac..e304bf44e1ff8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -556,17 +556,22 @@ int skl_pcode_request(struct drm_i915_private *i915, 
> u32 mbox, u32 request,
>  #undef COND
>  }
>  
> -void intel_pcode_init(struct drm_i915_private *i915)
> +int intel_pcode_init(struct drm_i915_private *i915)
>  {
> - int ret;
> + int ret = 0;
>  
>   if (!IS_DGFX(i915))
> - return;
> + return ret;
>  
>   ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
>   DG1_UNCORE_GET_INIT_STATUS,
>   DG1_UNCORE_INIT_STATUS_COMPLETE,
> - DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
> + DG1_UNCORE_INIT_STATUS_COMPLETE, 18);
> +
> + drm_dbg(&i915->drm, "PCODE init status %d\n", ret);
> +
>   if (ret)
>   drm_err(&i915->drm, "Pcode did not report uncore initialization 
> completion!\n");
> +
> + return ret;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h 
> b/drivers/gpu/drm/i915/intel_sideband.h
> index 094c7b19c5d42..d1d14bcb8f56e 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -138,6 +138,6 @@ int sandybridge_pcode_write_timeout(struct 
> drm_i915_private *i915, u32 mbox,
>  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
>  
> -void intel_pcode_init(struct drm_i915_private *i915);
> +int intel_pcode_init(struct drm_i915_private *i915);
>  
>  #endif /* _INTEL_SIDEBAND_H */
> -- 
> 2.25.1
> 
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/1] drm/i915: dgfx cards need to wait on pcode's uncore init done

[Rodrigo Vivi]

On Wed, Jul 28, 2021 at 05:10:01AM -, Patchwork wrote:
>Patch Details
> 
>Series: series starting with [1/1] drm/i915: dgfx cards need to wait on
>pcode's uncore init done
>URL: [1]https://patchwork.freedesktop.org/series/93075/
>State: failure
>Details:
>[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20720/index.html
> 
>   CI Bug Log - changes from CI_DRM_10405_full -> Patchwork_20720_full
> 
> Summary
> 
>FAILURE
> 
>Serious unknown changes coming with Patchwork_20720_full absolutely
>need to be
>verified manually.
> 
>If you think the reported changes have nothing to do with the changes
>introduced in Patchwork_20720_full, please notify your bug team to
>allow them
>to document this new failure mode, which will reduce false positives in
>CI.
> 
> Possible new issues
> 
>Here are the unknown changes that may have been introduced in
>Patchwork_20720_full:
> 
>   IGT changes
> 
> Possible regressions
> 
>  * igt@kms_selftest@all@damage_iter_no_damage:
>   + shard-apl: NOTRUN -> [3]INCOMPLETE

This is not related.
Well, I should have triggered a CI re-run, for cleaning this up, but I ended up
pushing it :/ Bad example, sorry yall.

But yeap, patch is merged. Thanks for the patch.

> 
> Suppressed
> 
>The following results come from untrusted machines, tests, or statuses.
>They do not affect the overall result.
>  * igt@kms_busy@basic-hang:
>   + {shard-rkl}: NOTRUN -> [4]SKIP +1 similar issue
>  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
>   + {shard-rkl}: [5]SKIP ([6]i915#1849) -> [7]DMESG-WARN
> 
> Known issues
> 
>Here are the changes found in Patchwork_20720_full that come from known
>issues:
> 
>   IGT changes
> 
> Issues hit
> 
>  * igt@feature_discovery@psr2:
>   + shard-iclb: [8]PASS -> [9]SKIP ([i915#658])
>  * igt@gem_ctx_isolation@preservation-s3@bcs0:
>   + shard-kbl: [10]PASS -> [11]DMESG-WARN ([12]i915#180) +2
> similar issues
>   + shard-apl: NOTRUN -> [13]DMESG-WARN ([14]i915#180) +3 similar
> issues
>  * igt@gem_ctx_persistence@process:
>   + shard-snb: NOTRUN -> [15]SKIP ([16]fdo#109271 / [17]i915#1099)
> +4 similar issues
>  * igt@gem_ctx_shared@q-in-order:
>   + shard-snb: NOTRUN -> [18]SKIP ([19]fdo#109271) +209 similar
> issues
>  * igt@gem_exec_fair@basic-none@vecs0:
>   + shard-glk: [20]PASS -> [21]FAIL ([i915#2842] / [i915#3468])
>  * igt@gem_exec_fair@basic-pace@rcs0:
>   + shard-kbl: [22]PASS -> [23]FAIL ([i915#2851])
>  * igt@gem_exec_fair@basic-pace@vcs0:
>   + shard-iclb: [24]PASS -> [25]FAIL ([i915#2842]) +1 similar
> issue
>  * igt@gem_exec_fair@basic-throttle@rcs0:
>   + shard-glk: [26]PASS -> [27]FAIL ([i915#2842]) +2 similar
> issues
>  * igt@gem_exec_whisper@basic-contexts-forked-all:
>   + shard-glk: [28]PASS -> [29]DMESG-WARN ([30]i915#118 /
> [i915#95]) +1 similar issue
>  * igt@gem_huc_copy@huc-copy:
>   + shard-apl: NOTRUN -> [31]SKIP ([32]fdo#109271 / [33]i915#2190)
>  * igt@gem_mmap_offset@clear:
>   + shard-skl: [34]PASS -> [35]FAIL ([36]i915#1888 / [i915#3160])
>  * igt@gem_pwrite@basic-exhaustion:
>   + shard-apl: NOTRUN -> [37]WARN ([i915#2658])
>  * igt@gem_userptr_blits@vma-merge:
>   + shard-snb: NOTRUN -> [38]FAIL ([i915#2724])
>  * igt@i915_pm_rpm@fences:
>   + shard-tglb: NOTRUN -> [39]SKIP ([i915#579])
>  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
>   + shard-apl: NOTRUN -> [40]SKIP ([41]fdo#109271 / [i915#3777])
> +2 similar issues
>  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
>   + shard-apl: NOTRUN -> [42]SKIP ([43]fdo#109271 /
> [44]fdo#111827) +30 similar issues
>  * igt@kms_color@pipe-a-legacy-gamma:
>   + shard-skl: [45]PASS -> [46]DMESG-WARN ([47]i915#1982)
>  * igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
>   + shard-snb: NOTRUN -> [48]SKIP ([49]fdo#109271 /
> [50]fdo#111827) +9 similar issues
>  * igt@kms_color_chamelium@pipe-invalid-gamma-lut-sizes:
>   + shard-skl: NOTRUN -> [51]SKIP ([52]fdo#109271 /
> [53]fdo#111827)
>  * igt@kms_content_protection@legacy:
>   + shard-apl: NOTRUN -> [54]TIMEOUT ([55]i915#1319)
>  * igt@kms_content_protection@uevent:
>   + shard-apl: NOTRUN -> [56]FAIL ([57]i915#2105)
>  * igt@kms_cursor_crc@pipe-d-cursor-128x128-offscreen:
>   + shard-kbl: NOTRUN -> [58]SKIP ([59]fdo#109271)
>  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
>   + shard-tglb: NOTRUN -> [60]SKIP ([61]fdo#111825)
>  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
>   + shard-skl: [62]PASS -> [63]FAIL ([i915#79])
>  

Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support

[Rodrigo Vivi]

On Wed, Jul 28, 2021 at 08:50:20AM +0200, Daniel Vetter wrote:
> On Thu, May 6, 2021 at 6:19 PM Imre Deak  wrote:
> >
> > From: Ville Syrjälä 
> >
> > Add support for DPT (display page table). DPT is a
> > slightly peculiar two level page table scheme used for
> > tiled scanout buffers (linear uses direct ggtt mapping
> > still). The plane surface address will point at a page
> > in the DPT which holds the PTEs for 512 actual pages.
> > Thus we require 1/512 of the ggttt address space
> > compared to a direct ggtt mapping.
> >
> > We create a new DPT address space for each framebuffer and
> > track two vmas (one for the DPT, another for the ggtt).
> >
> > TODO:
> > - Is the i915_address_space approaach sane?
> > - Maybe don't map the whole DPT to write the PTEs?
> > - Deal with remapping/rotation? Need to create a
> >   separate DPT for each remapped/rotated plane I
> >   guess. Or else we'd need to make the per-fb DPT
> >   large enough to support potentially several
> >   remapped/rotated vmas. How large should that be?
> 
> I know this code predates efforts to split up intel_display.c, but
> adding entirely new feature to intel_display.c like this isn't cool.
> Please move this to intel_display_pt.c or something like that and give
> it a reasonable interface. Minimal kerneldoc as bonus would be great
> too.
> 
> I'm feeling like dim should reject any patch which has a positive
> diffstat on intel_display.c until this file is in better shape. Would
> be harsh, but we seem to be stuck in one step forward, one step back
> mode.

I like this idea, although that would mean more intel-only stuff in dim
what is not good :/

> -Daniel
> 
> >
> > Signed-off-by: Ville Syrjälä 
> > Signed-off-by: Bommu Krishnaiah 
> > Cc: Wilson Chris P 
> > Cc: Tang CQ 
> > Cc: Auld Matthew 
> > Reviewed-by: Uma Shankar 
> > Reviewed-by: Wilson Chris P 
> > Signed-off-by: Imre Deak 
> > ---
> >  .../gpu/drm/i915/display/intel_atomic_plane.c |   7 +-
> >  drivers/gpu/drm/i915/display/intel_display.c  | 352 +-
> >  drivers/gpu/drm/i915/display/intel_display.h  |   1 +
> >  .../drm/i915/display/intel_display_types.h|  15 +-
> >  drivers/gpu/drm/i915/display/intel_fbc.c  |   6 +-
> >  .../drm/i915/display/skl_universal_plane.c|  19 +-
> >  drivers/gpu/drm/i915/gt/gen8_ppgtt.h  |   7 +
> >  drivers/gpu/drm/i915/gt/intel_ggtt.c  |   7 +-
> >  drivers/gpu/drm/i915/gt/intel_gtt.h   |   5 +
> >  9 files changed, 392 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 7bfb26ca0bd07..36f52a1d7552f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> >
> > __drm_atomic_helper_plane_duplicate_state(plane, 
> > &intel_state->uapi);
> >
> > -   intel_state->vma = NULL;
> > +   intel_state->ggtt_vma = NULL;
> > +   intel_state->dpt_vma = NULL;
> > intel_state->flags = 0;
> >
> > /* add reference to fb */
> > @@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
> >   struct drm_plane_state *state)
> >  {
> > struct intel_plane_state *plane_state = to_intel_plane_state(state);
> > -   drm_WARN_ON(plane->dev, plane_state->vma);
> > +
> > +   drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
> > +   drm_WARN_ON(plane->dev, plane_state->dpt_vma);
> >
> > __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> > if (plane_state->hw.fb)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5d53ee4c58f5b..99a921ea2e81b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -67,6 +67,7 @@
> >  #include "gem/i915_gem_object.h"
> >
> >  #include "gt/intel_rps.h"
> > +#include "gt/gen8_ppgtt.h"
> >
> >  #include "g4x_dp.h"
> >  #include "g4x_hdmi.h"
> > @@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct 
> > intel_crtc_state *crtc_state);
> >  static void intel_modeset_setup_hw_state(struct drm_device *dev,
> >  struct drm_modeset_acquire_ctx 
> > *ctx);
> >
> > +struct i915_dpt {
> > +   struct i915_address_space vm;
> > +
> > +   struct drm_i915_gem_object *obj;
> > +   struct i915_vma *vma;
> > +   void __iomem *iomem;
> > +};
> > +
> > +#define i915_is_dpt(vm) ((vm)->is_dpt)
> > +
> > +static inline struct i915_dpt *
> > +i915_vm_to_dpt(struct i915_address_space *vm)
> > +{
> > +   BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
> > +   GEM_BUG_ON(!i915_is_dpt(vm));
> > +   return container_of(vm, struct i915_dpt, vm);
> > +}
> > +
> > +#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
> > +
> > 

[Intel-gfx] ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

[Patchwork]

== Series Details ==

Series: lpsp with hdmi/dp outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/92108/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10410_full -> Patchwork_20723_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20723_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20723_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20723_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_selftest@all@damage_iter_no_damage:
- shard-apl:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl1/igt@kms_selftest@all@damage_iter_no_damage.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5]) 
([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][6], [FAIL][7], [FAIL][8]) 
([i915#3002] / [i915#3810])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-1/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-5/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-1/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-5/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-6/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20723_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-snb6/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][10] -> [INCOMPLETE][11] ([i915#155])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-kbl1/igt@gem_...@in-flight-suspend.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][12] ([i915#2846])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][19] ([i915#2658])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#110542])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3323])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-s

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH v4 03/18] drm/sched: Add dependency tracking

[Christian König]

Am 28.07.21 um 14:09 schrieb Daniel Vetter:

On Wed, Jul 28, 2021 at 1:29 PM Christian König
 wrote:

Am 27.07.21 um 13:09 schrieb Daniel Vetter:

Adding a few more people to this bikeshed.

On Mon, Jul 12, 2021 at 10:02 PM Daniel Vetter  wrote:


@@ -349,6 +367,13 @@ int drm_sched_job_init(struct drm_sched_job *job,
 struct drm_sched_entity *entity,
 void *owner);
   void drm_sched_job_arm(struct drm_sched_job *job);
+int drm_sched_job_await_fence(struct drm_sched_job *job,
+ struct dma_fence *fence);
+int drm_sched_job_await_implicit(struct drm_sched_job *job,
+struct drm_gem_object *obj,
+bool write);
+
+

I'm still waiting on the paint delivery for these two functions so I
can finish this shed.

Well I wouldn't call that bike shedding, good names are important.

Just imaging we would have called the exclusive-fence write-fence instead.

Sure naming matters, but at least to my English understanding there's
not a semantic different between telling something to await for
something else (i.e. add a dependency) or to tell something to add a
dependency (i.e. await that thing later on before you start doing your
own thing).


To be honest I had to google what await means when you first mentioned 
it because I didn't had that in my English vocabulary.


(But I have to note that my English education is basically non-existent. 
I speak German and a good bunch of Dutch and just interfere most of the 
words).


Regards,
Christian.


Exclusive vs write fence otoh is a pretty big difference in what it means.

But also if there's consensus that I'm wrong then I'm happy to pick
the more preferred of the two options I deem equivalent.


What speaks against calling them add_dependency() and
_add_implicit_depencencies() ?

Nothing. I just like another ack on this before I rename it all. Also
I wasnt sure what you'd want to name the implicit dependency thing.

Lucas, Boris, Melissa, any acks here?
-Daniel


Regards,
Christian.


Thanks, Daniel


   void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
  struct drm_gpu_scheduler **sched_list,
  unsigned int num_sched_list);
--
2.32.0





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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: fixup igt_shrink_thp

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: fixup igt_shrink_thp
URL   : https://patchwork.freedesktop.org/series/93128/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10411 -> Patchwork_20725


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/index.html

Known issues


  Here are the changes found in Patchwork_20725 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][1] -> [FAIL][2] ([i915#1372])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2:  [FAIL][3] ([i915#1888]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/fi-tgl-u2/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][5] ([i915#3303]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303


Participating hosts (41 -> 35)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-kbl-8809g fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_10411 -> Patchwork_20725

  CI-20190529: 20190529
  CI_DRM_10411: 2c25ff42a7175b652d93ac3555d4ae13456beb4a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6153: a5dffe7499a2f7189718ddf1ccf49060b7c1529d @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20725: 2f028f0cdb9110c4e093c1b35796181087728ee7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2f028f0cdb91 drm/i915/selftests: fixup igt_shrink_thp

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/index.html
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[Intel-gfx] i915 DMC Updates - TGL:v2.12 and RKL v2.03

[Srivatsa, Anusha]

Hi,
Kindly pull these updates from i915.

The following changes since commit 168452ee695b5edb9deb641059bc110b9c5e8fc7:

  Merge tag 'iwlwifi-fw-2021-07-19' of 
git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/linux-firmware into main 
(2021-07-19 14:35:47 -0400)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-firmware tgl_rkl_dmc_updates

for you to fetch changes up to 6c9fd94d41310443ea4ff782ce1545e49e74221c:

  i915: Add v2.03 DMC for RKL (2021-07-28 09:45:27 -0700)


Anusha Srivatsa (2):
  i915: Add v2.12 DMC for TGL
 i915: Add v2.03 DMC for RKL

WHENCE   |   6 ++
i915/rkl_dmc_ver2_03.bin | Bin 0 -> 18476 bytes
i915/tgl_dmc_ver2_12.bin | Bin 0 -> 19760 bytes
3 files changed, 6 insertions(+)
create mode 100644 i915/rkl_dmc_ver2_03.bin
create mode 100644 i915/tgl_dmc_ver2_12.bin

Thanks,
Anusha
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

[Gupta, Anshuman]

Hi Lakshmi ,
Below failures are not related to my series.


  *   igt@kms_selftest@all@damage_iter_no_damage:
 *   shard-apl: NOTRUN -> 
INCOMPLETE
Could you please raise the issue and rereport the run.
Thanks,
Anshuman Gupta.




From: Patchwork 
Sent: Wednesday, July 28, 2021 10:17 PM
To: Gupta, Anshuman 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

Patch Details
Series:

lpsp with hdmi/dp outputs (rev2)

URL:

https://patchwork.freedesktop.org/series/92108/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/index.html

CI Bug Log - changes from CI_DRM_10410_full -> Patchwork_20723_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_20723_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20723_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20723_full:

IGT changes
Possible regressions

  *   igt@kms_selftest@all@damage_iter_no_damage:

 *   shard-apl: NOTRUN -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@runner@aborted:

 *   {shard-rkl}: 
(FAIL,
 
FAIL,
 
FAIL,
 
FAIL)
 ([i915#3002] / [i915#3810] / [i915#3811]) -> 
(FAIL,
 
FAIL,
 
FAIL)
 ([i915#3002] / [i915#3810])

Known issues

Here are the changes found in Patchwork_20723_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_ctx_persistence@idempotent:

 *   shard-snb: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#1099]) +3 similar issues

  *   igt@gem_eio@in-flight-suspend:

 *   shard-kbl: 
PASS
 -> 
INCOMPLETE
 ([i915#155])

  *   igt@gem_exec_fair@basic-deadline:

 *   shard-apl: NOTRUN -> 
FAIL
 ([i915#2846])

  *   igt@gem_exec_fair@basic-none-rrul@rcs0:

 *   shard-tglb: NOTRUN -> 
FAIL
 ([i915#2842])

  *   igt@gem_exec_fair@basic-none-share@rcs0:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842])

  *   igt@gem_exec_fair@basic-pace@vcs1:

 *   shard-iclb: NOTRUN -> 
FAIL
 ([i915#2842])

  *   igt@gem_huc_copy@huc-copy:

 *   shard-kbl: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#2190])

  *   igt@gem_pread@exhaustion:

 *   shard-apl: NOTRUN -> 
WARN
 ([i915#2658])

  *   igt@gem_pwrite@basic-exhaustion:

 *   shard-kbl: NOTRUN -> 
WARN
 ([i915#2658])

  *   igt@gem_userptr_blits@coherency-sync:

 *   shard-tglb: NOTRUN -> 
SKIP
 ([fdo#110542])

  *   igt@gem_userptr_blits@dmabuf-sync:

 *   shard-apl: NOTRUN -> 
SKIP

Re: [Intel-gfx] [PATCH 1/2] drm/i915/adl_s: Update ddi buf translation tables

[Souza, Jose]

On Thu, 2021-07-22 at 22:34 -0700, Matt Roper wrote:
> The hardware team updates the translation tables on 2021-06-23.  Let's
> update the driver accordingly.

Reviewed-by: José Roberto de Souza 

> 
> Bspec: 49291
> Signed-off-by: Matt Roper 
> ---
>  .../drm/i915/display/intel_ddi_buf_trans.c| 44 +--
>  1 file changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 63b1ae830d9a..cdd0df467287 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1004,13 +1004,13 @@ static const union intel_ddi_buf_trans_entry 
> _adls_combo_phy_ddi_translations_dp
>   /* NT mV Trans mV db
> */
>   { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
> */
>   { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
> */
> - { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350   700  6.0   
> */
> - { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
> */
> + { .cnl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350   700  6.0   
> */
> + { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900  8.2   
> */
>   { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
>   { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500   700  2.9   
> */
> - { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500   900  5.1   
> */
> - { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
> */
> - { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
> */
> + { .cnl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500   900  5.1   
> */
> + { .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650   700  0.6   
> */
> + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
> */
>   { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
> */
>  };
>  
> @@ -1021,16 +1021,16 @@ static const struct intel_ddi_buf_trans 
> adls_combo_phy_ddi_translations_dp_hbr2_
>  
>  static const union intel_ddi_buf_trans_entry 
> _adls_combo_phy_ddi_translations_edp_hbr2[] = {
>   /* NT mV Trans mV db
> */
> - { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200   200  0.0   
> */
> - { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200   250  1.9   
> */
> - { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200   300  3.5   
> */
> - { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200   350  4.9   
> */
> - { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250   250  0.0   
> */
> - { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250   300  1.6   
> */
> + { .cnl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200   200  0.0   
> */
> + { .cnl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200   250  1.9   
> */
> + { .cnl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200   300  3.5   
> */
> + { .cnl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200   350  4.9   
> */
> + { .cnl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250   250  0.0   
> */
> + { .cnl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250   300  1.6   
> */
>   { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250   350  2.9   
> */
> - { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300   300  0.0   
> */
> + { .cnl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300   300  0.0   
> */
>   { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300   350  1.3   
> */
> - { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350   350  0.0   
> */
> + { .cnl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350   350  0.0   
> */
>  };
>  
>  static const struct intel_ddi_buf_trans 
> adls_combo_phy_ddi_translations_edp_hbr2 = {
> @@ -1040,15 +1040,15 @@ static const struct intel_ddi_buf_trans 
> adls_combo_phy_ddi_translations_edp_hbr2
>  
>  static const union intel_ddi_buf_trans_entry 
> _adls_combo_phy_ddi_translations_edp_hbr3[] = {
>   /* NT mV Trans mV db
> */
> - { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350   350  0.0   
> */
> - { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350   500  3.1   
> */
> - { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350   700  6.0   
> */
> - { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350   900  8.2   
> */
> - { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
> - { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
> - { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500   900  5.1 

[Intel-gfx] ✓ Fi.CI.IGT: success for lpsp with hdmi/dp outputs (rev2)

[Patchwork]

== Series Details ==

Series: lpsp with hdmi/dp outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/92108/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10410_full -> Patchwork_20723_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20723_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) 
([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][5], [FAIL][6], [FAIL][7]) 
([i915#3002] / [i915#3810])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-1/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-5/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-5/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-6/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20723_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-snb6/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][9] -> [INCOMPLETE][10] ([i915#155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-kbl1/igt@gem_...@in-flight-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][11] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#110542])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-snb:  NOTRUN -> [FAIL][21] ([i915#2724])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-snb5/igt@gem_userptr_bl...@vma-merge.html
- shard-tglb: NOTRUN -> [FAIL][22] ([i915#3318])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen7_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109289])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gen7_exec_pa...@cmd-crossing-page.html

  * i

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/adl_p: Add ddi buf translation tables for combo PHY

[Souza, Jose]

On Thu, 2021-07-22 at 22:38 -0700, Matt Roper wrote:
> ADL-P now has its own set of DDI buf translation tables (except for eDP
> which appears to be the same as TGL).  Add the new values (last updated
> in bspec 2021-07-22) to the driver.
> 
> v2:
>  - Actually hook up the new tables via encoder->get_buf_trans()
> 
> Bspec: 49291
> Signed-off-by: Matt Roper 
> ---
>  .../drm/i915/display/intel_ddi_buf_trans.c| 106 +-
>  1 file changed, 105 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index cdd0df467287..7bf80b72733d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1057,6 +1057,64 @@ static const struct intel_ddi_buf_trans 
> adls_combo_phy_ddi_translations_edp_hbr3
>   .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3),
>  };
>  
> +static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_ddi_translations_hdmi[] = {
> + /* NT mV Trans mVdb 
>   */
> + { .cnl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } }, /*  400400  0.0 
> */
> + { .cnl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } }, /*  500500  0.0 
> */
> + { .cnl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } }, /*  650650  0.0 
> ALS */
> + { .cnl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } }, /*  800800  0.0 
> */
> + { .cnl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1000   1000  0.0 
> Re-timer */
> + { .cnl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } }, /* FullRed -1.5 
> */
> + { .cnl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } }, /* FullRed -1.8 
> */
> + { .cnl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } }, /* FullRed -2.0 
> CRLS */
> + { .cnl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } }, /* FullRed -2.5 
> */
> + { .cnl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } }, /* FullRed -3.0 
> */
> +};
> +
> +static const struct intel_ddi_buf_trans adlp_combo_phy_ddi_translations_hdmi 
> = {
> + .entries = _adlp_combo_phy_ddi_translations_hdmi,
> + .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi),
> + .hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_hdmi) 
> - 1,
> +};
> +
> +static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db
> */
> + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
> */
> + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
> */
> + { .cnl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350   700  6.0   
> */
> + { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350   900  8.2   
> */
> + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
> + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
> + { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
> */
> + { .cnl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650   700  0.6   
> */
> + { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
> */
> + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
> */
> +};
> +
> +static const struct intel_ddi_buf_trans 
> adlp_combo_phy_ddi_translations_dp_hbr = {
> + .entries = _adlp_combo_phy_ddi_translations_dp_hbr,
> + .num_entries = ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr),
> +};
> +
> +static const union intel_ddi_buf_trans_entry 
> _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3[] = {
> + /* NT mV Trans mV db
> */
> + { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
> */
> + { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
> */
> + { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700  6.0   
> */
> + { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
> */
> + { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
> */
> + { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
> */
> + { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500   900  5.1   
> */
> + { .cnl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650   700  0.6   
> */
> + { .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600   900  3.5   
> */
> + { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
> */
> +};
> +
> +static const struct intel_ddi_buf_trans 
> adlp_combo_phy_ddi_translations_dp_hbr2_hbr3 = {
> + .entries = _adlp_combo_phy_ddi_translations_dp_hbr2_hbr3,
> + .num_entries = 
> ARRAY_SIZE(_adlp_combo_phy_ddi_translations_dp_hbr2_hbr3),
> +};
> +
>  static const union intel_ddi_b

[Intel-gfx] ✓ Fi.CI.IGT: success for lpsp with hdmi/dp outputs (rev2)

[Patchwork]

== Series Details ==

Series: lpsp with hdmi/dp outputs (rev2)
URL   : https://patchwork.freedesktop.org/series/92108/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10410_full -> Patchwork_20723_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20723_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) 
([i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][5], [FAIL][6], [FAIL][7]) 
([i915#3002] / [i915#3810])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-1/igt@run...@aborted.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-5/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-rkl-2/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-1/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-5/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-rkl-6/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20723_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@idempotent:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-snb6/igt@gem_ctx_persiste...@idempotent.html

  * igt@gem_eio@in-flight-suspend:
- shard-kbl:  [PASS][9] -> [INCOMPLETE][10] ([i915#155])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-kbl1/igt@gem_...@in-flight-suspend.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl4/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][11] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10410/shard-tglb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl2/igt@gem_huc_c...@huc-copy.html

  * igt@gem_pread@exhaustion:
- shard-apl:  NOTRUN -> [WARN][17] ([i915#2658])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_pr...@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][18] ([i915#2658])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-kbl6/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#110542])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-snb:  NOTRUN -> [FAIL][21] ([i915#2724])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-snb5/igt@gem_userptr_bl...@vma-merge.html
- shard-tglb: NOTRUN -> [FAIL][22] ([i915#3318])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen7_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109289])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/shard-tglb8/igt@gen7_exec_pa...@cmd-crossing-page.html

  * i

[Intel-gfx] [PATCH] drm/i915: Disable bonding on gen12+ platforms

[Matthew Brost]

Disable bonding on gen12+ platforms aside from ones already supported by
the i915 - TGL, RKL, and ADL-S.

Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c 
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 05c3ee191710..9c3672bac0e2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -446,6 +446,13 @@ set_proto_ctx_engines_bond(struct i915_user_extension 
__user *base, void *data)
u16 idx, num_bonds;
int err, n;
 
+   if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915) &&
+   !IS_ROCKETLAKE(i915) && !IS_ALDERLAKE_S(i915)) {
+   drm_dbg(&i915->drm,
+   "Bonding on gen12+ aside from TGL, RKL, and ADL_S not 
allowed\n");
+   return -ENODEV;
+   }
+
if (get_user(idx, &ext->virtual_index))
return -EFAULT;
 
-- 
2.28.0

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Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support

[Daniel Vetter]

On Wed, Jul 28, 2021 at 6:41 PM Rodrigo Vivi  wrote:
>
> On Wed, Jul 28, 2021 at 08:50:20AM +0200, Daniel Vetter wrote:
> > On Thu, May 6, 2021 at 6:19 PM Imre Deak  wrote:
> > >
> > > From: Ville Syrjälä 
> > >
> > > Add support for DPT (display page table). DPT is a
> > > slightly peculiar two level page table scheme used for
> > > tiled scanout buffers (linear uses direct ggtt mapping
> > > still). The plane surface address will point at a page
> > > in the DPT which holds the PTEs for 512 actual pages.
> > > Thus we require 1/512 of the ggttt address space
> > > compared to a direct ggtt mapping.
> > >
> > > We create a new DPT address space for each framebuffer and
> > > track two vmas (one for the DPT, another for the ggtt).
> > >
> > > TODO:
> > > - Is the i915_address_space approaach sane?
> > > - Maybe don't map the whole DPT to write the PTEs?
> > > - Deal with remapping/rotation? Need to create a
> > >   separate DPT for each remapped/rotated plane I
> > >   guess. Or else we'd need to make the per-fb DPT
> > >   large enough to support potentially several
> > >   remapped/rotated vmas. How large should that be?
> >
> > I know this code predates efforts to split up intel_display.c, but
> > adding entirely new feature to intel_display.c like this isn't cool.
> > Please move this to intel_display_pt.c or something like that and give
> > it a reasonable interface. Minimal kerneldoc as bonus would be great
> > too.
> >
> > I'm feeling like dim should reject any patch which has a positive
> > diffstat on intel_display.c until this file is in better shape. Would
> > be harsh, but we seem to be stuck in one step forward, one step back
> > mode.
>
> I like this idea, although that would mean more intel-only stuff in dim
> what is not good :/

Ok I've stumbled over this patch a 2nd time, and this time it's bad.

This wasn't properly converted over to the dma_resv_lock work from
Maarten, the intel_pin_fb_obj_dpt() function is still all copypasted
from the old style how this work. That's definitely not great at all.
Someone needs to fix this.
-Daniel

> > -Daniel
> >
> > >
> > > Signed-off-by: Ville Syrjälä 
> > > Signed-off-by: Bommu Krishnaiah 
> > > Cc: Wilson Chris P 
> > > Cc: Tang CQ 
> > > Cc: Auld Matthew 
> > > Reviewed-by: Uma Shankar 
> > > Reviewed-by: Wilson Chris P 
> > > Signed-off-by: Imre Deak 
> > > ---
> > >  .../gpu/drm/i915/display/intel_atomic_plane.c |   7 +-
> > >  drivers/gpu/drm/i915/display/intel_display.c  | 352 +-
> > >  drivers/gpu/drm/i915/display/intel_display.h  |   1 +
> > >  .../drm/i915/display/intel_display_types.h|  15 +-
> > >  drivers/gpu/drm/i915/display/intel_fbc.c  |   6 +-
> > >  .../drm/i915/display/skl_universal_plane.c|  19 +-
> > >  drivers/gpu/drm/i915/gt/gen8_ppgtt.h  |   7 +
> > >  drivers/gpu/drm/i915/gt/intel_ggtt.c  |   7 +-
> > >  drivers/gpu/drm/i915/gt/intel_gtt.h   |   5 +
> > >  9 files changed, 392 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c 
> > > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 7bfb26ca0bd07..36f52a1d7552f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> > >
> > > __drm_atomic_helper_plane_duplicate_state(plane, 
> > > &intel_state->uapi);
> > >
> > > -   intel_state->vma = NULL;
> > > +   intel_state->ggtt_vma = NULL;
> > > +   intel_state->dpt_vma = NULL;
> > > intel_state->flags = 0;
> > >
> > > /* add reference to fb */
> > > @@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
> > >   struct drm_plane_state *state)
> > >  {
> > > struct intel_plane_state *plane_state = 
> > > to_intel_plane_state(state);
> > > -   drm_WARN_ON(plane->dev, plane_state->vma);
> > > +
> > > +   drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
> > > +   drm_WARN_ON(plane->dev, plane_state->dpt_vma);
> > >
> > > __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> > > if (plane_state->hw.fb)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 5d53ee4c58f5b..99a921ea2e81b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -67,6 +67,7 @@
> > >  #include "gem/i915_gem_object.h"
> > >
> > >  #include "gt/intel_rps.h"
> > > +#include "gt/gen8_ppgtt.h"
> > >
> > >  #include "g4x_dp.h"
> > >  #include "g4x_hdmi.h"
> > > @@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct 
> > > intel_crtc_state *crtc_state);
> > >  static void intel_modeset_setup_hw_state(struct drm_device *dev,
> > >  struct drm_modeset_acquire_ctx 
> > > *ctx);
> > >
> > > 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: fixup igt_shrink_thp

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: fixup igt_shrink_thp
URL   : https://patchwork.freedesktop.org/series/93128/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10411_full -> Patchwork_20725_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20725_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_busy@extended-modeset-hang-oldfb:
- {shard-rkl}:NOTRUN -> [SKIP][1] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-rkl-1/igt@kms_b...@extended-modeset-hang-oldfb.html

  * igt@runner@aborted:
- {shard-rkl}:([FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5]) 
([i915#2029] / [i915#3002] / [i915#3810] / [i915#3811]) -> ([FAIL][6], 
[FAIL][7], [FAIL][8]) ([i915#3002] / [i915#3810])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-rkl-6/igt@run...@aborted.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-rkl-5/igt@run...@aborted.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-rkl-1/igt@run...@aborted.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-rkl-2/igt@run...@aborted.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-rkl-6/igt@run...@aborted.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-rkl-1/igt@run...@aborted.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-rkl-5/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_20725_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@process:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +1 
similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-snb7/igt@gem_ctx_persiste...@process.html

  * igt@gem_ctx_shared@q-in-order:
- shard-snb:  NOTRUN -> [SKIP][10] ([fdo#109271]) +215 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-snb7/igt@gem_ctx_sha...@q-in-order.html

  * igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][11] -> [TIMEOUT][12] ([i915#2369] / 
[i915#2481] / [i915#3070])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-iclb6/igt@gem_...@unwedge-stress.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-iclb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  NOTRUN -> [FAIL][13] ([i915#2846])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-tglb3/igt@gem_exec_fair@basic-p...@vcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-glk:  [PASS][16] -> [DMESG-WARN][17] ([i915#118] / 
[i915#95])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-glk1/igt@gem_exec_whis...@basic-contexts-forked-all.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-glk3/igt@gem_exec_whis...@basic-contexts-forked-all.html

  * igt@gem_huc_copy@huc-copy:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-kbl3/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-glk:  [PASS][19] -> [FAIL][20] ([i915#1888] / [i915#307]) 
+1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10411/shard-glk3/igt@gem_mmap_...@cpuset-big-copy-xy.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-glk9/igt@gem_mmap_...@cpuset-big-copy-xy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-kbl:  NOTRUN -> [WARN][21] ([i915#2658])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-kbl1/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl:  NOTRUN -> [SKIP][22] ([fdo#109271]) +211 similar 
issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-kbl6/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3323])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20725/shard-kbl6/igt@gem_userptr_bl...@d

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

[Vudum, Lakshminarayana]

Re-reported.

From: Gupta, Anshuman 
Sent: Wednesday, July 28, 2021 10:06 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Subject: RE: ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

Hi Lakshmi ,
Below failures are not related to my series.


  *   igt@kms_selftest@all@damage_iter_no_damage:
 *   shard-apl: NOTRUN -> 
INCOMPLETE
Could you please raise the issue and rereport the run.
Thanks,
Anshuman Gupta.




From: Patchwork 
mailto:patchw...@emeril.freedesktop.org>>
Sent: Wednesday, July 28, 2021 10:17 PM
To: Gupta, Anshuman mailto:anshuman.gu...@intel.com>>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for lpsp with hdmi/dp outputs (rev2)

Patch Details
Series:

lpsp with hdmi/dp outputs (rev2)

URL:

https://patchwork.freedesktop.org/series/92108/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20723/index.html

CI Bug Log - changes from CI_DRM_10410_full -> Patchwork_20723_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_20723_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20723_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20723_full:

IGT changes
Possible regressions

  *   igt@kms_selftest@all@damage_iter_no_damage:

 *   shard-apl: NOTRUN -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@runner@aborted:

 *   {shard-rkl}: 
(FAIL,
 
FAIL,
 
FAIL,
 
FAIL)
 ([i915#3002] / [i915#3810] / [i915#3811]) -> 
(FAIL,
 
FAIL,
 
FAIL)
 ([i915#3002] / [i915#3810])

Known issues

Here are the changes found in Patchwork_20723_full that come from known issues:

IGT changes
Issues hit

  *   igt@gem_ctx_persistence@idempotent:

 *   shard-snb: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#1099]) +3 similar issues

  *   igt@gem_eio@in-flight-suspend:

 *   shard-kbl: 
PASS
 -> 
INCOMPLETE
 ([i915#155])

  *   igt@gem_exec_fair@basic-deadline:

 *   shard-apl: NOTRUN -> 
FAIL
 ([i915#2846])

  *   igt@gem_exec_fair@basic-none-rrul@rcs0:

 *   shard-tglb: NOTRUN -> 
FAIL
 ([i915#2842])

  *   igt@gem_exec_fair@basic-none-share@rcs0:

 *   shard-tglb: 
PASS
 -> 
FAIL
 ([i915#2842])

  *   igt@gem_exec_fair@basic-pace@vcs1:

 *   shard-iclb: NOTRUN -> 
FAIL
 ([i915#2842])

  *   igt@gem_huc_copy@huc-copy:

 *   shard-kbl: NOTRUN -> 
SKIP
 ([fdo#109271] / [i915#2190])

  *   igt@gem_pread@exhaustion:

 *   shard-apl: NOTRUN -> 
WARN
 ([i915#2658])

  *   igt@gem_pwrite@basic-exhaustion:

 *   shard-kbl: NOTRUN -> 
WARN
 ([i915#2658])

  *   igt@gem_userptr_blits@coher

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: prefer the create_user helper

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: prefer the create_user helper
URL   : https://patchwork.freedesktop.org/series/93131/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
28a3c3987659 drm/i915/selftests: prefer the create_user helper
-:6: WARNING:REPEATED_WORD: Possible repeated word: 'that'
#6: 
No need to hand roll the set_placements stuff, now that that we have a

total: 0 errors, 1 warnings, 0 checks, 88 lines checked


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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: prefer the create_user helper

[Patchwork]

== Series Details ==

Series: drm/i915/selftests: prefer the create_user helper
URL   : https://patchwork.freedesktop.org/series/93131/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10413 -> Patchwork_20726


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20726 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20726, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_20726:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@mman:
- fi-kbl-8809g:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10413/fi-kbl-8809g/igt@i915_selftest@l...@mman.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/fi-kbl-8809g/igt@i915_selftest@l...@mman.html
- fi-ivb-3770:[PASS][3] -> [DMESG-FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10413/fi-ivb-3770/igt@i915_selftest@l...@mman.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/fi-ivb-3770/igt@i915_selftest@l...@mman.html

  
Known issues


  Here are the changes found in Patchwork_20726 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][5] -> [FAIL][6] ([i915#1888])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10413/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-tgl-1115g4:  [PASS][7] -> [DMESG-WARN][8] ([i915#1887])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10413/fi-tgl-1115g4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/fi-tgl-1115g4/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@runner@aborted:
- fi-tgl-1115g4:  NOTRUN -> [FAIL][9] ([i915#1602])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/fi-tgl-1115g4/igt@run...@aborted.html

  
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888


Participating hosts (42 -> 36)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10413 -> Patchwork_20726

  CI-20190529: 20190529
  CI_DRM_10413: 33ace46253ab0ea580c1ff117e8ec2c6096d3297 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6155: 4b51398dcd7559012b85776e7353d516ff1e6ce6 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20726: 28a3c39876598c0ea3a09e8fe98c100614c9b759 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

28a3c3987659 drm/i915/selftests: prefer the create_user helper

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20726/index.html
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[Intel-gfx] [PATCH v4 00/14] drm/i915/guc/slpc: Enable GuC based power management features

[Vinay Belgaumkar]

This series enables Single Loop Power Control (SLPC) feature in GuC.
GuC implements various power management algorithms as part of it's
operation. These need to be specifically enabled by KMD. They replace
the legacy host based management of these features.

With this series, we will enable two PM features - GTPerf and GuCRC. These
are the Turbo and RC6 equivalents of the host based version. GuC provides
various interfaces via host-to-guc messaging, which allows KMD to enable
these features after GuC is loaded and GuC submission is enabled. We will
specifically disable the IA/GT Balancer and Duty Cycle control features in
SLPC.

To enable GTPerf, KMD sends a specific h2g message after setting up
some shared data structures. As part of this, we will gate host RPS as 
well. GuC takes over the duties of requesting frequencies by monitoring
GPU busyness. We can influence what GuC requests by modifying the min 
and max frequencies setup by SLPC through the sysfs interfaces that have
been exposed by legacy Turbo. SLPC typically requests efficient frequency
instead of minimum frequency to optimize performance. It also does not
necessarily stick to platform max, and can request frequencies that are
much higher since pcode will ultimately grant the appropriate values.
However, we will force it to adhere to platform min and max values so as
to maintain legacy behavior. SLPC does not have the concept of waitboost,
so the boost_freq sysfs will show a '0' value for now. There is a patch
forthcoming to ensure the interface is not exposed when SLPC is enabled.

GuCRC is enabled similarly through a h2g message. We still need to enable
RC6 feature bit (GEN6_RC_CTL_RC6_ENABLE) before we send this out.
Render/Media power gating still needs to be enabled by host as before.
GuC will take care of setting up the hysterisis values for RC6, host
does not need to set this up anymore.

v2: Address review comments (Michal W)
v3: More comments, optimizations (Michal W)
v4: Address comments (Michal W, Matt Roper, Matthew Brost)

Signed-off-by: Vinay Belgaumkar 

Vinay Belgaumkar (14):
  drm/i915/guc/slpc: Initial definitions for SLPC
  drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled
  drm/i915/guc/slpc: Adding SLPC communication interfaces
  drm/i915/guc/slpc: Allocate, initialize and release SLPC
  drm/i915/guc/slpc: Enable SLPC and add related H2G events
  drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable
  drm/i915/guc/slpc: Add methods to set min/max frequency
  drm/i915/guc/slpc: Add get max/min freq hooks
  drm/i915/guc/slpc: Add debugfs for SLPC info
  drm/i915/guc/slpc: Enable ARAT timer interrupt
  drm/i915/guc/slpc: Cache platform frequency limits
  drm/i915/guc/slpc: Sysfs hooks for SLPC
  drm/i915/guc/slpc: Add SLPC selftest
  drm/i915/guc/rc: Setup and enable GuCRC feature

 drivers/gpu/drm/i915/Makefile |   2 +
 drivers/gpu/drm/i915/gt/intel_gt.c|   2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c   |  47 +-
 drivers/gpu/drm/i915/gt/intel_rps.c   | 198 ++
 drivers/gpu/drm/i915/gt/intel_rps.h   |  10 +
 drivers/gpu/drm/i915/gt/selftest_slpc.c   | 309 +
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   7 +-
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 234 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  17 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   4 +
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c|  22 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   7 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c |  80 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h |  31 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 609 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  42 ++
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |  29 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |   4 -
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  25 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.h |   4 +
 drivers/gpu/drm/i915/i915_pmu.c   |   2 +-
 drivers/gpu/drm/i915/i915_reg.h   |   5 +
 drivers/gpu/drm/i915/i915_sysfs.c |  83 +--
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 24 files changed, 1684 insertions(+), 90 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h

-- 
2.25.0

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[Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Adding SLPC communication interfaces

[Vinay Belgaumkar]

Add constants and params that are needed to configure SLPC.

v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.

v3: Add slpc H2G format in abi, other review commments (Michal W)

v4: Update status bits according to latest spec

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   1 -
 .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 234 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|   3 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   7 +
 4 files changed, 244 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index d832c8f11c11..ca538e5de940 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -135,7 +135,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
-   INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
new file mode 100644
index ..efd2487626f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _GUC_ACTIONS_SLPC_ABI_H_
+#define _GUC_ACTIONS_SLPC_ABI_H_
+
+#include 
+#include "i915_reg.h"
+
+/**
+ * DOC: SLPC SHARED DATA STRUCTURE
+ *
+ *  
++--+--+
+ *  | CL | Bytes| Description  
|
+ *  
++==+==+
+ *  | 1  | 0-3  | SHARED DATA SIZE 
|
+ *  |
+--+--+
+ *  || 4-7  | GLOBAL STATE 
|
+ *  |
+--+--+
+ *  || 8-11 | DISPLAY DATA ADDRESS 
|
+ *  |
+--+--+
+ *  || 12:63| PADDING  
|
+ *  
++--+--+
+ *  || 0:63 | PADDING(PLATFORM INFO)   
|
+ *  
++--+--+
+ *  | 3  | 0-3  | TASK STATE DATA  
|
+ *  +
+--+--+
+ *  || 4:63 | PADDING  
|
+ *  
++--+--+
+ *  |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS   
|
+ *  
++--+--+
+ *  ||  | PADDING + EXTRA RESERVED PAGE
|
+ *  
++--+--+
+ */
+
+/*
+ * SLPC exposes certain parameters for global configuration by the host.
+ * These are referred to as override parameters, because in most cases
+ * the host will not need to modify the default values used by SLPC.
+ * SLPC remembers the default values which allows the host to easily restore
+ * them by simply unsetting the override. The host can set or unset override
+ * parameters during SLPC (re-)initialization using the SLPC Reset event.
+ * The host can also set or unset override parameters on the fly using the
+ * Parameter Set and Parameter Unset events
+ */
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS   256
+#define SLPC_OVERRIDE_BITFIELD_SIZE \
+   (SLPC_MAX_OVERRIDE_PARAMETERS / 32)
+
+#define SLPC_PAGE_SIZE_BYTES   4096
+#define SLPC_CACHELINE_SIZE_BYTES  64
+#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER  SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO   
SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE  SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE  SLPC_PAGE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_MAX (2 * SLPC_PAGE_SIZE_BYTES)
+
+/*
+ * Cacheline size aligned (Total size needed for
+ * SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)
+

[Intel-gfx] [PATCH 01/14] drm/i915/guc/slpc: Initial definitions for SLPC

[Vinay Belgaumkar]

Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.

Include templates for SLPC init/fini and enable.

v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)

v3: Review comments (Michal W)

v4: Include supported/selected inside slpc struct (Michal W)

Reviewed-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
Signed-off-by: Daniele Ceraolo Spurio 

drm/i915/guc/slpc: Lay out slpc init/enable/fini

Declare init/fini and enable function templates.

v2: Rebase

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 45 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   | 33 ++
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 16 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  6 ++-
 drivers/gpu/drm/i915/gt/uc/intel_uc.h |  2 +
 8 files changed, 105 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ab7679957623..d8eac4468df9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_guc_fw.o \
  gt/uc/intel_guc_log.o \
  gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_slpc.o \
  gt/uc/intel_guc_submission.o \
  gt/uc/intel_huc.o \
  gt/uc/intel_huc_debugfs.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 979128e28372..39bc3c16057b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -7,6 +7,7 @@
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm_irq.h"
 #include "intel_guc.h"
+#include "intel_guc_slpc.h"
 #include "intel_guc_ads.h"
 #include "intel_guc_submission.h"
 #include "i915_drv.h"
@@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
intel_guc_submission_init_early(guc);
+   intel_guc_slpc_init_early(&guc->slpc);
 
mutex_init(&guc->send_mutex);
spin_lock_init(&guc->irq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a9547069ee7e..7da11a0b6059 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -15,6 +15,7 @@
 #include "intel_guc_ct.h"
 #include "intel_guc_log.h"
 #include "intel_guc_reg.h"
+#include "intel_guc_slpc_types.h"
 #include "intel_uc_fw.h"
 #include "i915_utils.h"
 #include "i915_vma.h"
@@ -30,6 +31,7 @@ struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
struct intel_guc_ct ct;
+   struct intel_guc_slpc slpc;
 
/* Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
new file mode 100644
index ..40950f1bf05c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_guc_slpc.h"
+#include "gt/intel_gt.h"
+
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+   return container_of(slpc, struct intel_guc, slpc);
+}
+
+static bool __detect_slpc_supported(struct intel_guc *guc)
+{
+   /* GuC SLPC is unavailable for pre-Gen12 */
+   return guc->submission_supported &&
+   GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
+}
+
+static bool __guc_slpc_selected(struct intel_guc *guc)
+{
+   if (!intel_guc_slpc_is_supported(guc))
+   return false;
+
+   return guc->submission_selected;
+}
+
+void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   slpc->supported = __detect_slpc_supported(guc);
+   slpc->selected = __guc_slpc_selected(guc);
+}
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
+{
+   return 0;
+}
+
+void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
+{
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
new file mode 100644
index ..bc139682ad0f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h

[Intel-gfx] [PATCH 02/14] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled

[Vinay Belgaumkar]

Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 drivers/gpu/drm/i915/gt/intel_gt.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_rps.c | 20 
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a64aa43f7cd9..04dd69bcf6cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct 
drm_i915_private *i915)
intel_gt_init_timelines(gt);
intel_gt_pm_init_early(gt);
 
-   intel_rps_init_early(>->rps);
intel_uc_init_early(>->uc);
+   intel_rps_init_early(>->rps);
 }
 
 int intel_gt_probe_lmem(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0c8e7f2b06f0..e858eeb2c59d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps 
*rps)
return rps_to_gt(rps)->uncore;
 }
 
+static bool rps_uses_slpc(struct intel_rps *rps)
+{
+   struct intel_gt *gt = rps_to_gt(rps);
+
+   return intel_uc_uses_guc_slpc(>->uc);
+}
+
 static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
 {
return mask & ~rps->pm_intrmsk_mbz;
@@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
 {
struct intel_gt *gt = rps_to_gt(rps);
 
+   GEM_BUG_ON(rps_uses_slpc(rps));
+
GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
 rps->pm_events, rps_pm_mask(rps, rps->last_freq));
 
@@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 swreq;
 
+   GEM_BUG_ON(rps_uses_slpc(rps));
+
if (GRAPHICS_VER(i915) >= 9)
swreq = GEN9_FREQUENCY(val);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps)
 {
int adj;
 
+   if (!intel_rps_is_enabled(rps))
+   return;
+
GEM_BUG_ON(atomic_read(&rps->num_waiters));
 
if (!intel_rps_clear_active(rps))
@@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps)
 {
struct drm_i915_private *i915 = rps_to_i915(rps);
 
+   if (rps_uses_slpc(rps))
+   return;
+
if (IS_CHERRYVIEW(i915))
chv_rps_init(rps);
else if (IS_VALLEYVIEW(i915))
@@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps)
 
 void intel_rps_sanitize(struct intel_rps *rps)
 {
+   if (rps_uses_slpc(rps))
+   return;
+
if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
rps_disable_interrupts(rps);
 }
-- 
2.25.0

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[Intel-gfx] [PATCH 04/14] drm/i915/guc/slpc: Allocate, initialize and release SLPC

[Vinay Belgaumkar]

Allocate data structures for SLPC and functions for
initializing on host side.

v2: Address review comments (Michal W)
v3: Remove unnecessary header includes (Michal W)
v4: Rebase

Reviewed-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c| 11 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 36 ++-
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |  2 ++
 3 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 5b0f8c541b69..13d162353b1a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -336,6 +336,12 @@ int intel_guc_init(struct intel_guc *guc)
goto err_ct;
}
 
+   if (intel_guc_slpc_is_used(guc)) {
+   ret = intel_guc_slpc_init(&guc->slpc);
+   if (ret)
+   goto err_submission;
+   }
+
/* now that everything is perma-pinned, initialize the parameters */
guc_init_params(guc);
 
@@ -346,6 +352,8 @@ int intel_guc_init(struct intel_guc *guc)
 
return 0;
 
+err_submission:
+   intel_guc_submission_fini(guc);
 err_ct:
intel_guc_ct_fini(&guc->ct);
 err_ads:
@@ -368,6 +376,9 @@ void intel_guc_fini(struct intel_guc *guc)
 
i915_ggtt_disable_guc(gt->ggtt);
 
+   if (intel_guc_slpc_is_used(guc))
+   intel_guc_slpc_fini(&guc->slpc);
+
if (intel_guc_submission_is_used(guc))
intel_guc_submission_fini(guc);
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 40950f1bf05c..6d76ea4c0ace 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -12,6 +12,16 @@ static inline struct intel_guc *slpc_to_guc(struct 
intel_guc_slpc *slpc)
return container_of(slpc, struct intel_guc, slpc);
 }
 
+static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
+{
+   return guc_to_gt(slpc_to_guc(slpc));
+}
+
+static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc 
*slpc)
+{
+   return slpc_to_gt(slpc)->i915;
+}
+
 static bool __detect_slpc_supported(struct intel_guc *guc)
 {
/* GuC SLPC is unavailable for pre-Gen12 */
@@ -35,11 +45,35 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
slpc->selected = __guc_slpc_selected(guc);
 }
 
+static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
+   int err;
+
+   err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void 
**)&slpc->vaddr);
+   if (unlikely(err)) {
+   drm_err(&i915->drm,
+   "Failed to allocate SLPC struct (err=%pe)\n",
+   ERR_PTR(err));
+   return err;
+   }
+
+   return err;
+}
+
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
 {
-   return 0;
+   GEM_BUG_ON(slpc->vma);
+
+   return slpc_shared_data_init(slpc);
 }
 
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
 {
+   if (!slpc->vma)
+   return;
+
+   i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
 }
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index 769c162305a0..8bd753167234 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -9,6 +9,8 @@
 #include 
 
 struct intel_guc_slpc {
+   struct i915_vma *vma;
+   struct slpc_shared_data *vaddr;
bool supported;
bool selected;
 };
-- 
2.25.0

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[Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events

[Vinay Belgaumkar]

Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in the shared
data structure.

v2: Address several review comments, add new helpers for
decoding the SLPC min/max frequencies. Use masks instead of hardcoded
constants. (Michal W)

v3: Split global_state_to_string function, and check for positive
non-zero return value from intel_guc_send() (Michal W)

v4: Optimize the stringify function and other comments (Michal W)

v5: Enable slpc as well before declaring GuC submission status (Michal W)

Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 226 ++
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |   2 +
 drivers/gpu/drm/i915/gt/uc/intel_uc.c |  11 +
 3 files changed, 239 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 6d76ea4c0ace..da3e1f8844a9 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
slpc->selected = __guc_slpc_selected(guc);
 }
 
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+   u32 id, u32 value)
+{
+   GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
+   /*
+* When the flag bit is set, corresponding value will be read
+* and applied by SLPC.
+*/
+   data->override_params.bits[id >> 5] |= (1 << (id % 32));
+   data->override_params.values[id] = value;
+}
+
+static void slpc_mem_set_enabled(struct slpc_shared_data *data,
+   u8 enable_id, u8 disable_id)
+{
+   /*
+* Enabling a param involves setting the enable_id
+* to 1 and disable_id to 0.
+*/
+   slpc_mem_set_param(data, enable_id, 1);
+   slpc_mem_set_param(data, disable_id, 0);
+}
+
+static void slpc_mem_set_disabled(struct slpc_shared_data *data,
+   u8 enable_id, u8 disable_id)
+{
+   /*
+* Disabling a param involves setting the enable_id
+* to 0 and disable_id to 1.
+*/
+   slpc_mem_set_param(data, disable_id, 1);
+   slpc_mem_set_param(data, enable_id, 0);
+}
+
 static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
 {
struct intel_guc *guc = slpc_to_guc(slpc);
@@ -63,6 +97,121 @@ static int slpc_shared_data_init(struct intel_guc_slpc 
*slpc)
return err;
 }
 
+static u32 slpc_get_state(struct intel_guc_slpc *slpc)
+{
+   struct slpc_shared_data *data;
+
+   GEM_BUG_ON(!slpc->vma);
+
+   drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
+   data = slpc->vaddr;
+
+   return data->header.global_state;
+}
+
+static bool slpc_is_running(struct intel_guc_slpc *slpc)
+{
+   return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
+}
+
+static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+   offset,
+   0,
+   };
+   int ret;
+
+   ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+   return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_query_task_state(struct intel_guc_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
+   int ret;
+
+   ret = guc_action_slpc_query(guc, offset);
+   if (ret)
+   drm_err(&i915->drm, "Failed to query task state (%pe)\n",
+   ERR_PTR(ret));
+
+   drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
+
+   return ret;
+}
+
+static const char *slpc_global_state_to_string(enum slpc_global_state state)
+{
+   switch (state) {
+   case SLPC_GLOBAL_STATE_NOT_RUNNING:
+   return "not running";
+   case SLPC_GLOBAL_STATE_INITIALIZING:
+   return "initializing";
+   case SLPC_GLOBAL_STATE_RESETTING:
+   return "resetting";
+   case SLPC_GLOBAL_STATE_RUNNING:
+   return "running";
+   case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+   return "shutting down";
+   case SLPC_GLOBAL_STATE_ERROR:
+   return "error";
+   default:
+   return "unknown";
+   }
+}
+
+static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
+{
+   return slpc_global_state_to_string(slpc_get_state(slpc));
+}
+
+static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
+{
+   u32 request[] = {
+  

[Intel-gfx] [PATCH 08/14] drm/i915/guc/slpc: Add get max/min freq hooks

[Vinay Belgaumkar]

Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used in a sysfs patch later
on.

v2: Address review comments (Michal W)
v3: Return err in case of query failure (Michal W)

Reviewed-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 54 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h |  2 +
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 0959cc9e104a..816c9ee301bf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -320,6 +320,33 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc 
*slpc, u32 val)
return ret;
 }
 
+/**
+ * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold max frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   /* Force GuC to update task data */
+   ret = slpc_query_task_state(slpc);
+
+   if (!ret)
+   *val = slpc_decode_max_freq(slpc);
+   }
+
+   return ret;
+}
+
 /**
  * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
  * @slpc: pointer to intel_guc_slpc.
@@ -349,6 +376,33 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc 
*slpc, u32 val)
return ret;
 }
 
+/**
+ * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold min frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the min frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   /* Force GuC to update task data */
+   ret = slpc_query_task_state(slpc);
+
+   if (!ret)
+   *val = slpc_decode_min_freq(slpc);
+   }
+
+   return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 788d87ff7b58..78a7893ce489 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -31,5 +31,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
 int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
 
 #endif
-- 
2.25.0

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[Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency

[Vinay Belgaumkar]

Add param set h2g helpers to set the min and max frequencies
for use by SLPC.

v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
v4: Print generic error in set_param (Michal W)

Signed-off-by: Sundaresan Sujaritha 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h |  2 +
 2 files changed, 91 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index da3e1f8844a9..0959cc9e104a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
 }
 
+static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+   id,
+   value,
+   };
+   int ret;
+
+   ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+   return ret > 0 ? -EPROTO : ret;
+}
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -146,6 +161,22 @@ static int slpc_query_task_state(struct intel_guc_slpc 
*slpc)
return ret;
 }
 
+static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   int ret;
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   ret = guc_action_slpc_set_param(guc, id, value);
+   if (ret)
+   drm_err(&i915->drm, "Failed to set param %d to %u (%pe)\n",
+   id, value, ERR_PTR(ret));
+
+   return ret;
+}
+
 static const char *slpc_global_state_to_string(enum slpc_global_state state)
 {
switch (state) {
@@ -260,6 +291,64 @@ static void slpc_shared_data_reset(struct slpc_shared_data 
*data)
SLPC_PARAM_TASK_DISABLE_DCC);
 }
 
+/**
+ * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   ret = slpc_set_param(slpc,
+  SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+  val);
+
+   /* Return standardized err code for sysfs calls */
+   if (ret)
+   ret = -EIO;
+   }
+
+   return ret;
+}
+
+/**
+ * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the min unslice
+ * frequency.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   intel_wakeref_t wakeref;
+   int ret;
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   ret = slpc_set_param(slpc,
+  SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+  val);
+
+   /* Return standardized err code for sysfs calls */
+   if (ret)
+   ret = -EIO;
+   }
+
+   return ret;
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index bc139682ad0f..788d87ff7b58 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
 
 #endif
-- 
2.25.0

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[Intel-gfx] [PATCH 06/14] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable

[Vinay Belgaumkar]

The assumption when it was added was that GT would not be
holding any gt_pm references. However, uc_init is called
from gt_init_hw, which holds a forcewake ref. If SLPC
enable fails, we will still be holding this ref, which will
result in the BUG_ON.

Reviewed-by: Matthew Brost 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b6338742a594..48cbd800ca54 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2523,10 +2523,6 @@ void intel_guc_submission_enable(struct intel_guc *guc)
 
 void intel_guc_submission_disable(struct intel_guc *guc)
 {
-   struct intel_gt *gt = guc_to_gt(guc);
-
-   GEM_BUG_ON(gt->awake); /* GT should be parked first */
-
/* Note: By the time we're here, GuC may have already been reset */
 }
 
-- 
2.25.0

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[Intel-gfx] [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info

[Vinay Belgaumkar]

This prints out relevant SLPC info from the SLPC shared structure.

We will send a H2G message which forces SLPC to update the
shared data structure with latest information before reading it.

v2: Address review comments (Michal W)
v3: Remove unnecessary tasks from slpc_info (Michal W)
v4: Rename function to intel_guc_slpc_print_info() (Michal W)

Reviewed-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Sundaresan Sujaritha 
---
 .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 22 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 29 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h   |  3 ++
 3 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
index 72ddfff42f7d..887c8c8f35db 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -12,6 +12,7 @@
 #include "gt/uc/intel_guc_ct.h"
 #include "gt/uc/intel_guc_ads.h"
 #include "gt/uc/intel_guc_submission.h"
+#include "gt/uc/intel_guc_slpc.h"
 
 static int guc_info_show(struct seq_file *m, void *data)
 {
@@ -50,11 +51,32 @@ static int guc_registered_contexts_show(struct seq_file *m, 
void *data)
 }
 DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts);
 
+static int guc_slpc_info_show(struct seq_file *m, void *unused)
+{
+   struct intel_guc *guc = m->private;
+   struct intel_guc_slpc *slpc = &guc->slpc;
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   if (!intel_guc_slpc_is_used(guc))
+   return -ENODEV;
+
+   return intel_guc_slpc_print_info(slpc, &p);
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_slpc_info);
+
+static bool intel_eval_slpc_support(void *data)
+{
+   struct intel_guc *guc = (struct intel_guc *)data;
+
+   return intel_guc_slpc_is_used(guc);
+}
+
 void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
 {
static const struct debugfs_gt_file files[] = {
{ "guc_info", &guc_info_fops, NULL },
{ "guc_registered_contexts", &guc_registered_contexts_fops, 
NULL },
+   { "guc_slpc_info", &guc_slpc_info_fops, 
&intel_eval_slpc_support},
};
 
if (!intel_guc_is_supported(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 816c9ee301bf..2643d207009b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -439,6 +439,35 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
return 0;
 }
 
+int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer 
*p)
+{
+   struct drm_i915_private *i915 = slpc_to_i915(slpc);
+   struct slpc_shared_data *data = slpc->vaddr;
+   struct slpc_task_state_data *slpc_tasks;
+   intel_wakeref_t wakeref;
+   int ret = 0;
+
+   GEM_BUG_ON(!slpc->vma);
+
+   with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+   ret = slpc_query_task_state(slpc);
+
+   if (!ret) {
+   slpc_tasks = &data->task_state_data;
+
+   drm_printf(p, "\tSLPC state: %s\n", 
slpc_get_state_string(slpc));
+   drm_printf(p, "\tGTPERF task active: %s\n",
+   yesno(slpc_tasks->status & 
SLPC_GTPERF_TASK_ENABLED));
+   drm_printf(p, "\tMax freq: %u MHz\n",
+   slpc_decode_max_freq(slpc));
+   drm_printf(p, "\tMin freq: %u MHz\n",
+   slpc_decode_min_freq(slpc));
+   }
+   }
+
+   return ret;
+}
+
 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
 {
if (!slpc->vma)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 78a7893ce489..3ffd4f2e3151 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,8 @@
 #include "intel_guc_submission.h"
 #include "intel_guc_slpc_types.h"
 
+struct drm_printer;
+
 static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
 {
return guc->slpc.supported;
@@ -33,5 +35,6 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, 
u32 val);
 int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
 int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
 int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
+int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer 
*p);
 
 #endif
-- 
2.25.0

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[Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits

[Vinay Belgaumkar]

Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.

Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.

v2: Address review comments (Michal W)
v3: Formatting (Michal W)
v4: Add separate function to parse rp values (Michal W)
v5: Perform range checking for set min/max (Michal W)

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c   | 115 ++
 .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h |   9 ++
 drivers/gpu/drm/i915/i915_reg.h   |   3 +
 3 files changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 742918875593..bfd5fb0751fd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
return err;
}
 
+   slpc->max_freq_softlimit = 0;
+   slpc->min_freq_softlimit = 0;
+
return err;
 }
 
@@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc 
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
 }
 
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+   u32 request[] = {
+   GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
+   SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
+   id,
+   };
+
+   return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
+
 static bool slpc_is_running(struct intel_guc_slpc *slpc)
 {
return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
@@ -177,6 +192,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8 
id, u32 value)
return ret;
 }
 
+static int slpc_unset_param(struct intel_guc_slpc *slpc,
+   u8 id)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+   return guc_action_slpc_unset_param(guc, id);
+}
+
 static const char *slpc_global_state_to_string(enum slpc_global_state state)
 {
switch (state) {
@@ -307,6 +332,11 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc 
*slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
 
+   if ((val < slpc->min_freq) ||
+   (val > slpc->rp0_freq) ||
+   (val < slpc->min_freq_softlimit))
+   return -EINVAL;
+
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
   SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
@@ -317,6 +347,8 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc 
*slpc, u32 val)
ret = -EIO;
}
 
+   slpc->max_freq_softlimit = val;
+
return ret;
 }
 
@@ -363,6 +395,11 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc 
*slpc, u32 val)
intel_wakeref_t wakeref;
int ret;
 
+   if ((val < slpc->min_freq) ||
+   (val > slpc->rp0_freq) ||
+   (val > slpc->max_freq_softlimit))
+   return -EINVAL;
+
with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
ret = slpc_set_param(slpc,
   SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
@@ -373,6 +410,8 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc 
*slpc, u32 val)
ret = -EIO;
}
 
+   slpc->min_freq_softlimit = val;
+
return ret;
 }
 
@@ -418,6 +457,71 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
   GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
 }
 
+static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
+{
+   int ret = 0;
+
+   /*
+* Softlimits are initially equivalent to platform limits
+* unless they have deviated from defaults, in which case,
+* we retain the values and set min/max accordingly.
+*/
+   if (!slpc->max_freq_softlimit)
+   slpc->max_freq_softlimit = slpc->rp0_freq;
+   else if (slpc->max_freq_softlimit != slpc->rp0_freq)
+   ret = intel_guc_slpc_set_max_freq(slpc,
+   slpc->max_freq_softlimit);
+
+   if (!slpc->min_freq_softlimit)
+   slpc->min_freq_softlimit = slpc->min_freq;
+   else if (slpc->min_freq_softlimit != slpc->min_freq)
+   ret = intel_guc_slpc_set_min_freq(slpc,
+   slpc->min_freq_softlimit);
+
+   return ret;
+}
+
+static void intel_guc_slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool 
ignore)
+{
+   /* A failure here does not affect the algorithm in a fatal way */
+   if (ignore) {
+   slpc_set_param(slpc,
+  SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
+  ignore);
+   slpc_set_param(slpc,
+  SLPC_PARAM_GL

[Intel-gfx] [PATCH 10/14] drm/i915/guc/slpc: Enable ARAT timer interrupt

[Vinay Belgaumkar]

This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.

v2: Fix comment (Matthew Brost)

Reviewed-by: Matthew Brost 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 17 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h |  2 ++
 drivers/gpu/drm/i915/gt/uc/intel_uc.c   |  8 
 3 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 2643d207009b..742918875593 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -403,6 +403,21 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc 
*slpc, u32 *val)
return ret;
 }
 
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
+{
+   u32 pm_intrmsk_mbz = 0;
+
+   /*
+* Allow GuC to receive ARAT timer expiry event.
+* This interrupt register is setup by RPS code
+* when host based Turbo is enabled.
+*/
+   pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+
+   intel_uncore_rmw(gt->uncore,
+  GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
+}
+
 /*
  * intel_guc_slpc_enable() - Start SLPC
  * @slpc: pointer to intel_guc_slpc.
@@ -436,6 +451,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
if (unlikely(ret < 0))
return ret;
 
+   intel_guc_pm_intrmsk_enable(&i915->gt);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 3ffd4f2e3151..e45054d5b9b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,7 @@
 #include "intel_guc_submission.h"
 #include "intel_guc_slpc_types.h"
 
+struct intel_gt;
 struct drm_printer;
 
 static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
@@ -36,5 +37,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, 
u32 val);
 int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
 int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
 int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer 
*p);
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
 
 #endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3e0cd1f05e3b..b104fb7607eb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -655,6 +655,7 @@ void intel_uc_suspend(struct intel_uc *uc)
 static int __uc_resume(struct intel_uc *uc, bool enable_communication)
 {
struct intel_guc *guc = &uc->guc;
+   struct intel_gt *gt = guc_to_gt(guc);
int err;
 
if (!intel_guc_is_fw_running(guc))
@@ -666,6 +667,13 @@ static int __uc_resume(struct intel_uc *uc, bool 
enable_communication)
if (enable_communication)
guc_enable_communication(guc);
 
+   /* If we are only resuming GuC communication but not reloading
+* GuC, we need to ensure the ARAT timer interrupt is enabled
+* again. In case of GuC reload, it is enabled during SLPC enable.
+*/
+   if (enable_communication && intel_uc_uses_guc_slpc(uc))
+   intel_guc_pm_intrmsk_enable(gt);
+
err = intel_guc_resume(guc);
if (err) {
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
-- 
2.25.0

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[Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC

[Vinay Belgaumkar]

Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether SLPC is enabled.

v2: Add wrappers for getting rp0/1/n frequencies, update
softlimits in set min/max SLPC functions. Also check for
boundary conditions before setting them.

v3: Address review comments (Michal W)

v4: Add helper for host part of intel_rps_set_freq helpers (Michal W)

Acked-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
Signed-off-by: Tvrtko Ursulin 
Signed-off-by: Sujaritha Sundaresan 
---
 drivers/gpu/drm/i915/gt/intel_rps.c | 177 
 drivers/gpu/drm/i915/gt/intel_rps.h |  10 ++
 drivers/gpu/drm/i915/i915_pmu.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h |   2 +
 drivers/gpu/drm/i915/i915_sysfs.c   |  83 +++--
 5 files changed, 207 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index e858eeb2c59d..49db8ed9f80d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps 
*rps)
return rps_to_gt(rps)->uncore;
 }
 
+static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)
+{
+   struct intel_gt *gt = rps_to_gt(rps);
+
+   return >->uc.guc.slpc;
+}
+
 static bool rps_uses_slpc(struct intel_rps *rps)
 {
struct intel_gt *gt = rps_to_gt(rps);
@@ -1960,6 +1967,176 @@ u32 intel_rps_read_actual_frequency(struct intel_rps 
*rps)
return freq;
 }
 
+u32 intel_rps_read_punit_req(struct intel_rps *rps)
+{
+   struct intel_uncore *uncore = rps_to_uncore(rps);
+
+   return intel_uncore_read(uncore, GEN6_RPNSWREQ);
+}
+
+static u32 intel_rps_get_req(u32 pureq)
+{
+   u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
+
+   return req;
+}
+
+u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
+{
+   u32 freq = intel_rps_get_req(intel_rps_read_punit_req(rps));
+
+   return intel_gpu_freq(rps, freq);
+}
+
+u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
+{
+   if (rps_uses_slpc(rps))
+   return intel_rps_read_punit_req_frequency(rps);
+   else
+   return intel_gpu_freq(rps, rps->cur_freq);
+}
+
+u32 intel_rps_get_max_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->max_freq_softlimit;
+   else
+   return intel_gpu_freq(rps, rps->max_freq_softlimit);
+}
+
+u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->rp0_freq;
+   else
+   return intel_gpu_freq(rps, rps->rp0_freq);
+}
+
+u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->rp1_freq;
+   else
+   return intel_gpu_freq(rps, rps->rp1_freq);
+}
+
+u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->min_freq;
+   else
+   return intel_gpu_freq(rps, rps->min_freq);
+}
+
+static int set_max_freq(struct intel_rps *rps, u32 val)
+{
+   struct drm_i915_private *i915 = rps_to_i915(rps);
+   int ret = 0;
+
+   mutex_lock(&rps->lock);
+
+   val = intel_freq_opcode(rps, val);
+   if (val < rps->min_freq ||
+   val > rps->max_freq ||
+   val < rps->min_freq_softlimit) {
+   ret = -EINVAL;
+   goto unlock;
+   }
+
+   if (val > rps->rp0_freq)
+   drm_dbg(&i915->drm, "User requested overclocking to %d\n",
+ intel_gpu_freq(rps, val));
+
+   rps->max_freq_softlimit = val;
+
+   val = clamp_t(int, rps->cur_freq,
+ rps->min_freq_softlimit,
+ rps->max_freq_softlimit);
+
+   /*
+* We still need *_set_rps to process the new max_delay and
+* update the interrupt limits and PMINTRMSK even though
+* frequency request may be unchanged.
+*/
+   intel_rps_set(rps, val);
+
+unlock:
+   mutex_unlock(&rps->lock);
+
+   return ret;
+}
+
+int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return intel_guc_slpc_set_max_freq(slpc, val);
+   else
+   return set_max_freq(rps, val);
+}
+
+u32 intel_rps_get_min_frequency(struct intel_rps *rps)
+{
+   struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+   if (rps_uses_slpc(rps))
+   return slpc->min_freq_softlimit;
+  

[Intel-gfx] [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest

[Vinay Belgaumkar]

Tests that exercise the SLPC get/set frequency interfaces.

Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.

Clamp_min will set min frequency to different levels and check
if SLPC requests are higher or equal to those levels.

v2: Address review comments (Michal W)
v3: Checkpatch() corrections
v4: Remove unnecessary header file (Matthew Brost)

Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/gt/intel_rps.c   |   1 +
 drivers/gpu/drm/i915/gt/selftest_slpc.c   | 309 ++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 3 files changed, 311 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c 
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 49db8ed9f80d..7a2aa0031cf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2330,4 +2330,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_rps.c"
+#include "selftest_slpc.c"
 #endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c 
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
new file mode 100644
index ..119d012d1e1e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#define NUM_STEPS 5
+#define H2G_DELAY 5
+#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 1)
+
+static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+   int ret;
+
+   ret = intel_guc_slpc_set_min_freq(slpc, freq);
+   if (ret)
+   pr_err("Could not set min frequency to [%u]\n", freq);
+   else /* Delay to ensure h2g completes */
+   delay_for_h2g();
+
+   return ret;
+}
+
+static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+   int ret;
+
+   ret = intel_guc_slpc_set_max_freq(slpc, freq);
+   if (ret)
+   pr_err("Could not set maximum frequency [%u]\n",
+   freq);
+   else /* Delay to ensure h2g completes */
+   delay_for_h2g();
+
+   return ret;
+}
+
+int live_slpc_clamp_min(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_gt *gt = &i915->gt;
+   struct intel_guc_slpc *slpc = >->uc.guc.slpc;
+   struct intel_rps *rps = >->rps;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   struct igt_spinner spin;
+   u32 slpc_min_freq, slpc_max_freq;
+   int err = 0;
+
+   if (!intel_uc_uses_guc_slpc(>->uc))
+   return 0;
+
+   if (igt_spinner_init(&spin, gt))
+   return -ENOMEM;
+
+   if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
+   pr_err("Could not get SLPC max freq\n");
+   return -EIO;
+   }
+
+   if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
+   pr_err("Could not get SLPC min freq\n");
+   return -EIO;
+   }
+
+   if (slpc_min_freq == slpc_max_freq) {
+   pr_err("Min/Max are fused to the same value\n");
+   return -EINVAL;
+   }
+
+   intel_gt_pm_wait_for_idle(gt);
+   intel_gt_pm_get(gt);
+   for_each_engine(engine, gt, id) {
+   struct i915_request *rq;
+   u32 step, min_freq, req_freq;
+   u32 act_freq, max_act_freq;
+
+   if (!intel_engine_can_store_dword(engine))
+   continue;
+
+   /* Go from min to max in 5 steps */
+   step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
+   max_act_freq = slpc_min_freq;
+   for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
+   min_freq += step) {
+   err = slpc_set_min_freq(slpc, min_freq);
+   if (err)
+   break;
+
+   st_engine_heartbeat_disable(engine);
+
+   rq = igt_spinner_create_request(&spin,
+   engine->kernel_context,
+   MI_NOOP);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   st_engine_heartbeat_enable(engine);
+   break;
+   }
+
+   i915_request_add(rq);
+
+   if (!igt_wait_for_spinner(&spin, rq)) {
+   pr_err("%s: Spinner did not start\n",
+   engine->name);
+   igt_spinner_end(&spin);
+   st_engine_heartbeat_enable(engine);
+   intel_gt_set_wedged(engine->gt);
+   err = -EIO;
+   

[Intel-gfx] [PATCH 14/14] drm/i915/guc/rc: Setup and enable GuCRC feature

[Vinay Belgaumkar]

This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.

GuCRC needs GuC submission to be enabled, and only
supported on Gen12+ for now.

When GuCRC is enabled, do not set HW RC6. Use a H2G message
to tell GuC to enable GuCRC. When disabling RC6, tell GuC to
revert RC6 control back to KMD. KMD is still responsible for
enabling everything related to Coarse Power Gating though.

v2: Address comments (Michal W)
v3: Don't set hysterisis values when GuCRC is used (Matt Roper)

Reviewed-by: Michal Wajdeczko 
Signed-off-by: Vinay Belgaumkar 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/gt/intel_rc6.c   | 47 +++
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |  6 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  2 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++
 drivers/gpu/drm/i915/gt/uc/intel_uc.h |  2 +
 8 files changed, 155 insertions(+), 15 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d8eac4468df9..3fc17f20d88e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_guc_fw.o \
  gt/uc/intel_guc_log.o \
  gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_rc.o \
  gt/uc/intel_guc_slpc.o \
  gt/uc/intel_guc_submission.o \
  gt/uc/intel_huc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c 
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 259d7eb4e165..f6b914438a0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -62,20 +62,25 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
u32 pg_enable;
int i;
 
-   /* 2b: Program RC6 thresholds.*/
-   set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
-   set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+   /*
+* With GuCRC, these parameters are set by GuC
+*/
+   if (!intel_uc_uses_guc_rc(>->uc)) {
+   /* 2b: Program RC6 thresholds.*/
+   set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+   set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
 
-   set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
-   set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-   for_each_engine(engine, rc6_to_gt(rc6), id)
-   set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+   set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 
1280ns */
+   set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+   for_each_engine(engine, rc6_to_gt(rc6), id)
+   set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
-   set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
+   set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
 
-   set(uncore, GEN6_RC_SLEEP, 0);
+   set(uncore, GEN6_RC_SLEEP, 0);
 
-   set(uncore, GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+   set(uncore, GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
+   }
 
/*
 * 2c: Program Coarse Power Gating Policies.
@@ -98,11 +103,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
 
-   /* 3a: Enable RC6 */
-   rc6->ctl_enable =
-   GEN6_RC_CTL_HW_ENABLE |
-   GEN6_RC_CTL_RC6_ENABLE |
-   GEN6_RC_CTL_EI_MODE(1);
+   /* 3a: Enable RC6
+*
+* With GuCRC, we do not enable bit 31 of RC_CTL,
+* thus allowing GuC to control RC6 entry/exit fully instead.
+* We will not set the HW ENABLE and EI bits
+*/
+   if (!intel_guc_rc_enable(>->uc.guc))
+   rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
+   else
+   rc6->ctl_enable =
+   GEN6_RC_CTL_HW_ENABLE |
+   GEN6_RC_CTL_RC6_ENABLE |
+   GEN6_RC_CTL_EI_MODE(1);
 
pg_enable =
GEN9_RENDER_PG_ENABLE |
@@ -513,6 +526,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
 {
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
+   struct intel_gt *gt = rc6_to_gt(rc6);
+
+   /* Take control of RC6 back from GuC */
+   intel_guc_rc_disable(>->uc.guc);
 
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
if (GRAPHICS_VER(i915) >= 9)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi

Re: [Intel-gfx] [PATCH v3 3/5] drm/print: RFC add choice to use dynamic debug in drm-debug

[jim . cromie]

On Tue, Jul 27, 2021 at 10:03 AM Sean Paul  wrote:
>
> On Thu, Jul 22, 2021 at 11:20 AM Sean Paul  wrote:
> >
>
> Reply-all fail. Adding everyone else back to my response.
>
> > On Tue, Jul 20, 2021 at 03:29:34PM +0200, Daniel Vetter wrote:
> > > On Wed, Jul 14, 2021 at 11:51:36AM -0600, Jim Cromie wrote:
> > > > drm's debug system uses distinct categories of debug messages, encoded
> > > > in an enum (DRM_UT_), which are mapped to bits in drm.debug.
> > > > drm_debug_enabled() does a lot of unlikely bit-mask checks on
> > > > drm.debug; we can use dynamic debug instead, and get all that
> > > > static_key/jump_label goodness.
> >
> > Hi Jim,
> > Thanks for your patches! Daniel pointed me at them in response to my 
> > drm_trace
> > patchset (https://patchwork.freedesktop.org/series/78133/). I'd love to get 
> > your
> > input on it. I think the 2 sets are mostly compatible, we'd just need to 
> > keep
> > drm_dev_dbg and do the CONFIG check in the function beside the trace_enabled
> > checks.
> >
> > > >
> > > > Dynamic debug has no concept of category, but we can map the DRM_UT_*
> > > > to a set of distinct prefixes; "drm:core:", "drm:kms:" etc, and
> > > > prepend them to the given formats.
> > > >
> > > > Then we can use:
> > > >   `echo module drm format ^drm:core: +p > control`
> > > >
> > > > to enable every such "prefixed" pr_debug with one query.  This new
> > > > prefix changes pr_debug's output, so is user visible, but it seems
> > > > unlikely to cause trouble for log watchers; they're not relying on the
> > > > absence of class prefix strings.
> > > >
> > > > This conversion yields ~2100 new callsites on my i7/i915 laptop:
> > > >
> > > >   dyndbg: 195 debug prints in module drm_kms_helper
> > > >   dyndbg: 298 debug prints in module drm
> > > >   dyndbg: 1630 debug prints in module i915
> > > >
> > > > CONFIG_DRM_USE_DYNAMIC_DEBUG enables this, and is available if
> > > > CONFIG_DYNAMIC_DEBUG or CONFIG_DYNAMIC_DEBUG_CORE is chosen, and if
> > > > CONFIG_JUMP_LABEL is enabled; this because its required to get the
> > > > promised optimizations.
> > > >
> > > > The indirection/switchover is layered into the macro scheme:
> > > >
> > > > 0. A new callback on drm.debug which calls dynamic_debug_exec_queries
> > > >to map those bits to specific query/commands
> > > >dynamic_debug_exec_queries("format ^drm:kms: +p", "drm*");
> > > >here for POC, this should be in dynamic_debug.c
> > > >with a MODULE_PARAM_DEBUG_BITMAP(__drm_debug, { "prefix-1", "desc-1" 
> > > > }+)
> > >
> > > This is really awesome.
> >
> >
> > Agreed, this is a very clever way of merging the 2 worlds!
> >
> >
> > > For merging I think we need to discuss with dyn
> > > debug folks whether they're all ok with this, but it's exported already
> > > should should be fine.
> >
> > I wonder if this is a good time to reconsider our drm categories. IMO 
> > they're
> > overly broad and it's hard to get the right information without subscribing 
> > to
> > the firehose. It seems like dyndbg might be a good opportunity to unlock
> > subcategories of log messages.
> >
> > More concretely, on CrOS we can't subscribe to atomic or state categories 
> > since
> > they're too noisy. However if there was a "fail" subcategory which dumped
> > state/atomic logs on check failures, that would be really compelling. 
> > Something
> > like:
> >
> > drm:atomic:fail vs. drm:atomic
> >

YES

> > Both would be picked up if (drm.debug & DRM_DBG_ATOMIC), however it would 
> > allow
> > dyndbg-aware clients to get better logs without having a huge table of
> > individual log signatures.
> >
> > I'm not sure how tightly we'd want to control the subcategories. It could be
> > strict like the categories spelled out in drm_print.h, or an open prefix 
> > arg to
> > drm_dev_dbg. I suspect we'd want the former, but would want to be careful to
> > provide enough flexibility to properly

formalizing categories and subcategories is where the
practical selectivity of format ^prefix is determined.

While endless bikeshedding is a possible downside,
there are a few subtleties to note,  so we can pick a harmonious 3-color scheme:

"drm:kms: " and "drm:kms:" are different  (2nd, w/o trailing space,
allows subcats)
"drm:kms"  is also different  (includes "drm:kmsmart", whatever that would be)
"drm.kms"  again.   dot names anyone ?

ASIDE(s):

"drm:kms"  and  "drm:kms*" are different,
the latter does not work as you might reasonably expect.
This is because

commit 578b1e0701af34f9ef69daabda4431f1e8501109
Author: Changbin Du 
Date:   Thu Jan 23 15:54:14 2014 -0800

dynamic_debug: add wildcard support to filter files/functions/modules

Add wildcard '*'(matches zero or more characters) and '?' (matches one
character) support when qurying debug flags.

specifically left format out of the wildcarded query terms.
And that was rational since the format search was already special
(floating substring, not exact match or basename match)
and format 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disable bonding on gen12+ platforms

[Patchwork]

== Series Details ==

Series: drm/i915: Disable bonding on gen12+ platforms
URL   : https://patchwork.freedesktop.org/series/93135/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10413 -> Patchwork_20727


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/index.html

Known issues


  Here are the changes found in Patchwork_20727 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@semaphore:
- fi-bdw-5557u:   NOTRUN -> [SKIP][1] ([fdo#109271]) +29 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html

  * igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u:   NOTRUN -> [WARN][2] ([i915#3718])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/fi-bdw-5557u/igt@core_hotunp...@unbind-rebind.html

  * igt@i915_pm_rpm@basic-rte:
- fi-bdw-5557u:   NOTRUN -> [FAIL][3] ([i915#579])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/fi-bdw-5557u/igt@i915_pm_...@basic-rte.html

  * igt@i915_selftest@live@execlists:
- fi-icl-y:   [PASS][4] -> [DMESG-FAIL][5] ([i915#1993])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10413/fi-icl-y/igt@i915_selftest@l...@execlists.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/fi-icl-y/igt@i915_selftest@l...@execlists.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u:   NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993
  [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (42 -> 36)
--

  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 
fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10413 -> Patchwork_20727

  CI-20190529: 20190529
  CI_DRM_10413: 33ace46253ab0ea580c1ff117e8ec2c6096d3297 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6155: 4b51398dcd7559012b85776e7353d516ff1e6ce6 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20727: 8f19ec8cfad8387f3326ef903d6aa397a122c3f3 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8f19ec8cfad8 drm/i915: Disable bonding on gen12+ platforms

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20727/index.html
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Re: [Intel-gfx] refactor the i915 GVT support

[Jason Gunthorpe]

On Wed, Jul 28, 2021 at 01:38:58PM +, Wang, Zhi A wrote:

> I guess those APIs you were talking about are KVM-only. For other
> hypervisors, e.g. Xen, ARCN cannot use the APIs you mentioned. Not
> sure if you have already noticed that VFIO is KVM-only right now.

There is very little hard connection between VFIO and KVM, so no, I
don't think that is completely true.

In an event, an in-tree version of other hypervisor support for GVT
needs to go through enabling VFIO support so that the existing API
multiplexers we have can be used properly, not adding a shim layer
trying to recreate VFIO inside a GPU driver.

> GVT-g is designed for many hypervisors not only KVM. In the design,
> we implemented an abstraction layer for different hypervisors. You
> can check the link in the previous email which has an example of how
> the MPT module "xengt" supports GVT-g running under Xen.  For
> example, injecting a msi in VFIO/KVM is via playing with
> eventfd. But in Xen, we need to issue a hypercall from Dom0. 

This is obviously bad design, Xen should plug into the standardized
eventfd scheme as well and trigger its hypercall this way. Then it can
integrate with the existing VFIO interrupt abstraction infrastructure.

> others, like querying mappings between GFN and HFN. 

This should be done through VFIO containers, there is nothing KVM
specific there.

> As you can see, to survive from this situation, we have to rely on
> an abstraction layer so that we can prevent introducing coding
> blocks like in the core logic:

No, you have to fix the abstractions we already have to support the
matrix of things you care about. If this can't be done then maybe we
can add new abstractions, but abstractions like this absoultely should
not be done inside drivers.

Jason
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[Intel-gfx] [PATCH 05/25] drm/i915/display: remove explicit CNL handling from intel_crtc.c

[Lucas De Marchi]

No need for special CNL handling as there is no real platform with that
configuration.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c 
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 448c4d99ac35..254e67141a77 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -335,7 +335,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum 
pipe pipe)
dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc;
}
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+   if (DISPLAY_VER(dev_priv) >= 11)
drm_crtc_create_scaling_filter_property(&crtc->base,
BIT(DRM_SCALING_FILTER_DEFAULT) 
|

BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
-- 
2.31.1

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[Intel-gfx] [PATCH 01/25] drm/i915/display: remove PORT_F workaround for CNL

[Lucas De Marchi]

Explicit support for CNL is being removed from the driver as it's not
expected to work. Remove the workaround for PORT_F from
display/intel_bios.c so we can also remove the generic DISPLAY_VER == 10
calls to intel_ddi_init(): the only platform with that display version
is already handled separately (GLK).

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_bios.c| 6 +++---
 drivers/gpu/drm/i915/display/intel_display.c | 7 ---
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index aa667fa71158..4172c8ee6aa6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1871,12 +1871,12 @@ intel_bios_encoder_supports_edp(const struct 
intel_bios_encoder_data *devdata)
 static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 {
/*
-* On some ICL/CNL SKUs port F is not present, but broken VBTs mark
+* On some ICL SKUs port F is not present, but broken VBTs mark
 * the port as present. Only try to initialize port F for the
 * SKUs that may actually have it.
 */
-   if (port == PORT_F && (IS_ICELAKE(i915) || IS_CANNONLAKE(i915)))
-   return IS_ICL_WITH_PORT_F(i915) || IS_CNL_WITH_PORT_F(i915);
+   if (port == PORT_F && IS_ICELAKE(i915))
+   return IS_ICL_WITH_PORT_F(i915);
 
return true;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 4833eaeb8f0b..8597194bea88 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11452,13 +11452,6 @@ static void intel_setup_outputs(struct 
drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
vlv_dsi_init(dev_priv);
-   } else if (DISPLAY_VER(dev_priv) == 10) {
-   intel_ddi_init(dev_priv, PORT_A);
-   intel_ddi_init(dev_priv, PORT_B);
-   intel_ddi_init(dev_priv, PORT_C);
-   intel_ddi_init(dev_priv, PORT_D);
-   intel_ddi_init(dev_priv, PORT_E);
-   intel_ddi_init(dev_priv, PORT_F);
} else if (DISPLAY_VER(dev_priv) >= 9) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
-- 
2.31.1

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[Intel-gfx] [PATCH 02/25] drm/i915/display: remove explicit CNL handling from intel_cdclk.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. Remove code and rename
functions/macros accordingly.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 72 +-
 drivers/gpu/drm/i915/i915_reg.h|  4 +-
 2 files changed, 18 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ff35c29508d5..34fa4130d5c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1195,17 +1195,6 @@ static const struct intel_cdclk_vals glk_cdclk_table[] = 
{
{}
 };
 
-static const struct intel_cdclk_vals cnl_cdclk_table[] = {
-   { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
-   { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 },
-   { .refclk = 19200, .cdclk = 528000, .divider = 2, .ratio = 55 },
-
-   { .refclk = 24000, .cdclk = 168000, .divider = 4, .ratio = 28 },
-   { .refclk = 24000, .cdclk = 336000, .divider = 2, .ratio = 28 },
-   { .refclk = 24000, .cdclk = 528000, .divider = 2, .ratio = 44 },
-   {}
-};
-
 static const struct intel_cdclk_vals icl_cdclk_table[] = {
{ .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -1339,16 +1328,6 @@ static u8 bxt_calc_voltage_level(int cdclk)
return DIV_ROUND_UP(cdclk, 25000);
 }
 
-static u8 cnl_calc_voltage_level(int cdclk)
-{
-   if (cdclk > 336000)
-   return 2;
-   else if (cdclk > 168000)
-   return 1;
-   else
-   return 0;
-}
-
 static u8 icl_calc_voltage_level(int cdclk)
 {
if (cdclk > 556800)
@@ -1383,15 +1362,6 @@ static u8 tgl_calc_voltage_level(int cdclk)
return 0;
 }
 
-static void cnl_readout_refclk(struct drm_i915_private *dev_priv,
-  struct intel_cdclk_config *cdclk_config)
-{
-   if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
-   cdclk_config->ref = 24000;
-   else
-   cdclk_config->ref = 19200;
-}
-
 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
   struct intel_cdclk_config *cdclk_config)
 {
@@ -1422,8 +1392,6 @@ static void bxt_de_pll_readout(struct drm_i915_private 
*dev_priv,
cdclk_config->ref = 38400;
else if (DISPLAY_VER(dev_priv) >= 11)
icl_readout_refclk(dev_priv, cdclk_config);
-   else if (IS_CANNONLAKE(dev_priv))
-   cnl_readout_refclk(dev_priv, cdclk_config);
else
cdclk_config->ref = 19200;
 
@@ -1439,11 +1407,11 @@ static void bxt_de_pll_readout(struct drm_i915_private 
*dev_priv,
}
 
/*
-* CNL+ have the ratio directly in the PLL enable register, gen9lp had
-* it in a separate PLL control register.
+* DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
+* gen9lp had it in a separate PLL control register.
 */
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
-   ratio = val & CNL_CDCLK_PLL_RATIO_MASK;
+   if (DISPLAY_VER(dev_priv) >= 11)
+   ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
else
ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & 
BXT_DE_PLL_RATIO_MASK;
 
@@ -1530,7 +1498,7 @@ static void bxt_de_pll_enable(struct drm_i915_private 
*dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
 }
 
-static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
+static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
 {
intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
 BXT_DE_PLL_PLL_ENABLE, 0);
@@ -1542,12 +1510,12 @@ static void cnl_cdclk_pll_disable(struct 
drm_i915_private *dev_priv)
dev_priv->cdclk.hw.vco = 0;
 }
 
-static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
+static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
 {
int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
u32 val;
 
-   val = CNL_CDCLK_PLL_RATIO(ratio);
+   val = ICL_CDCLK_PLL_RATIO(ratio);
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
 
val |= BXT_DE_PLL_PLL_ENABLE;
@@ -1566,7 +1534,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private 
*dev_priv, int vco)
u32 val;
 
/* Write PLL ratio without disabling */
-   val = CNL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
+   val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
 
/* Submit freq change request */
@@ -1635,7 +1603,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
int ret;
 
  

[Intel-gfx] [PATCH 10/25] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.

A lot of special code for CNL can be removed. There were some
__cnl.*() functions that were created to share the implementation
between ICL and CNL. Those are now embedded in the only caller, in ICL.

Remove code and rename functions/macros accordingly to use ICL prefix
for those that are still needed.

Verified with:

make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++---
 drivers/gpu/drm/i915/i915_reg.h   |   4 +-
 2 files changed, 96 insertions(+), 494 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d180aec4e530..a379649d3e9e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
return MG_PLL_ENABLE(0);
 
-   return CNL_DPLL_ENABLE(pll->info->id);
+   return ICL_DPLL_ENABLE(pll->info->id);
 }
 
 static i915_reg_t
@@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
.dump_hw_state = bxt_dump_hw_state,
 };
 
-static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
-  struct intel_shared_dpll *pll)
-{
-   const enum intel_dpll_id id = pll->info->id;
-   u32 val;
-
-   /* 1. Enable DPLL power in DPLL_ENABLE. */
-   val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-   val |= PLL_POWER_ENABLE;
-   intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-   /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
-   if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
- PLL_POWER_STATE, 5))
-   drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
-
-   /*
-* 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
-* select DP mode, and set DP link rate.
-*/
-   val = pll->state.hw_state.cfgcr0;
-   intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
-
-   /* 4. Reab back to ensure writes completed */
-   intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
-
-   /* 3. Configure DPLL_CFGCR0 */
-   /* Avoid touch CFGCR1 if HDMI mode is not enabled */
-   if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
-   val = pll->state.hw_state.cfgcr1;
-   intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
-   /* 4. Reab back to ensure writes completed */
-   intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
-   }
-
-   /*
-* 5. If the frequency will result in a change to the voltage
-* requirement, follow the Display Voltage Frequency Switching
-* Sequence Before Frequency Change
-*
-* Note: DVFS is actually handled via the cdclk code paths,
-* hence we do nothing here.
-*/
-
-   /* 6. Enable DPLL in DPLL_ENABLE. */
-   val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-   val |= PLL_ENABLE;
-   intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-   /* 7. Wait for PLL lock status in DPLL_ENABLE. */
-   if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
-   drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
-
-   /*
-* 8. If the frequency will result in a change to the voltage
-* requirement, follow the Display Voltage Frequency Switching
-* Sequence After Frequency Change
-*
-* Note: DVFS is actually handled via the cdclk code paths,
-* hence we do nothing here.
-*/
-
-   /*
-* 9. turn on the clock for the DDI and map the DPLL to the DDI
-* Done at intel_ddi_clk_select
-*/
-}
-
-static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
-   struct intel_shared_dpll *pll)
-{
-   const enum intel_dpll_id id = pll->info->id;
-   u32 val;
-
-   /*
-* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
-* Done at intel_ddi_post_disable
-*/
-
-   /*
-* 2. If the frequency will result in a change to the voltage
-* requirement, follow the Display Voltage Frequency Switching
-* Sequence Before Frequency Change
-*
-* Note: DVFS is actually handled via the cdclk code paths,
-* hence we do nothing here.
-*/
-
-   /* 3. Disable DPLL through DPLL_ENABLE. */
-   val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
-   val &= ~PLL_ENABLE;
-   intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
-
-   /* 4. Wait for PLL

[Intel-gfx] [PATCH 15/25] drm/i915/display: rename CNL references in skl_scaler.c

[Lucas De Marchi]

With the removal of CNL, let's consider GLK as the first platform using
those constants since GLK has DISPLAY_VER == 10.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/skl_scaler.c | 10 +-
 drivers/gpu/drm/i915/i915_reg.h   |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c 
b/drivers/gpu/drm/i915/display/skl_scaler.c
index 911a113ee006..ebdd3115de16 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -341,12 +341,12 @@ static u16 cnl_nearest_filter_coef(int t)
  *
  */
 
-static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
+static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
 enum pipe pipe, int id, int set)
 {
int i;
 
-   intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
+   intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
  PS_COEE_INDEX_AUTO_INC);
 
for (i = 0; i < 17 * 7; i += 2) {
@@ -359,11 +359,11 @@ static void cnl_program_nearest_filter_coefs(struct 
drm_i915_private *dev_priv,
t = cnl_coef_tap(i + 1);
tmp |= cnl_nearest_filter_coef(t) << 16;
 
-   intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
+   intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
  tmp);
}
 
-   intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
+   intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
 }
 
 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int 
set)
@@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct drm_i915_private 
*dev_priv, enum pipe
case DRM_SCALING_FILTER_DEFAULT:
break;
case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
-   cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
+   glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
break;
default:
MISSING_CASE(filter);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0086b165f03a..bf1d0cadc208 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7720,11 +7720,11 @@ enum {
 #define SKL_PS_ECC_STAT(pipe, id)  _MMIO_PIPE(pipe, \
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
-#define CNL_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,\
+#define GLK_PS_COEF_INDEX_SET(pipe, id, set)  _MMIO_PIPE(pipe,\
_ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) 
+ (set) * 8, \
_ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) 
+ (set) * 8)
 
-#define CNL_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe, \
+#define GLK_PS_COEF_DATA_SET(pipe, id, set)  _MMIO_PIPE(pipe, \
_ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + 
(set) * 8, \
_ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + 
(set) * 8)
 /* legacy palette */
-- 
2.31.1

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[Intel-gfx] [PATCH 08/25] drm/i915/display: remove explicit CNL handling from intel_dmc.c

[Lucas De Marchi]

Remove DMC firmware for CNL.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 9895fd957df9..3c3c6cb5c0df 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
 #define ICL_DMC_MAX_FW_SIZE0x6000
 MODULE_FIRMWARE(ICL_DMC_PATH);
 
-#define CNL_DMC_PATH   DMC_PATH(cnl, 1, 07)
-#define CNL_DMC_VERSION_REQUIRED   DMC_VERSION(1, 7)
-#define CNL_DMC_MAX_FW_SIZEGLK_DMC_MAX_FW_SIZE
-MODULE_FIRMWARE(CNL_DMC_PATH);
-
 #define GLK_DMC_PATH   DMC_PATH(glk, 1, 04)
 #define GLK_DMC_VERSION_REQUIRED   DMC_VERSION(1, 4)
 #define GLK_DMC_MAX_FW_SIZE0x4000
@@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private 
*dev_priv)
dmc->fw_path = ICL_DMC_PATH;
dmc->required_version = ICL_DMC_VERSION_REQUIRED;
dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
-   } else if (IS_CANNONLAKE(dev_priv)) {
-   dmc->fw_path = CNL_DMC_PATH;
-   dmc->required_version = CNL_DMC_VERSION_REQUIRED;
-   dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
} else if (IS_GEMINILAKE(dev_priv)) {
dmc->fw_path = GLK_DMC_PATH;
dmc->required_version = GLK_DMC_VERSION_REQUIRED;
-- 
2.31.1

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[Intel-gfx] [PATCH 07/25] drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c

[Lucas De Marchi]

Only one reference to CNL that is not needed, but code is the same for
DISPLAY_VER >= 11, so leave the code around and just remove the special
case for CNL.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2cf742a0b957..8fdacb252bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2500,7 +2500,7 @@ int intel_connector_debugfs_add(struct drm_connector 
*connector)
connector, &i915_hdcp_sink_capability_fops);
}
 
-   if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&
+   if (DISPLAY_VER(dev_priv) >= 11 &&
((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
!to_intel_connector(connector)->mst_port) ||
connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
-- 
2.31.1

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[Intel-gfx] [PATCH 04/25] drm/i915/display: remove explicit CNL handling from intel_combo_phy.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, that doesn't have
combo phys. We don't need to handle CNL explicitly in
intel_combo_phy.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 .../gpu/drm/i915/display/intel_combo_phy.c| 106 --
 1 file changed, 20 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 487c54cd5982..bacdf8a16bcb 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -23,9 +23,9 @@ enum {
PROCMON_1_05V_DOT_1,
 };
 
-static const struct cnl_procmon {
+static const struct icl_procmon {
u32 dw1, dw9, dw10;
-} cnl_procmon_values[] = {
+} icl_procmon_values[] = {
[PROCMON_0_85V_DOT_0] =
{ .dw1 = 0x, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, },
[PROCMON_0_95V_DOT_0] =
@@ -38,15 +38,10 @@ static const struct cnl_procmon {
{ .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
 };
 
-/*
- * CNL has just one set of registers, while gen11 has a set for each combo PHY.
- * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
- * call the ICL macros even though the function has CNL on its name.
- */
-static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
+static const struct icl_procmon *
+icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 {
-   const struct cnl_procmon *procmon;
+   const struct icl_procmon *procmon;
u32 val;
 
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
@@ -55,32 +50,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private 
*dev_priv, enum phy phy)
MISSING_CASE(val);
fallthrough;
case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
-   procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
+   procmon = &icl_procmon_values[PROCMON_0_85V_DOT_0];
break;
case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
-   procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0];
+   procmon = &icl_procmon_values[PROCMON_0_95V_DOT_0];
break;
case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
-   procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1];
+   procmon = &icl_procmon_values[PROCMON_0_95V_DOT_1];
break;
case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
-   procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0];
+   procmon = &icl_procmon_values[PROCMON_1_05V_DOT_0];
break;
case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
-   procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1];
+   procmon = &icl_procmon_values[PROCMON_1_05V_DOT_1];
break;
}
 
return procmon;
 }
 
-static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
+static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
   enum phy phy)
 {
-   const struct cnl_procmon *procmon;
+   const struct icl_procmon *procmon;
u32 val;
 
-   procmon = cnl_get_procmon_ref_values(dev_priv, phy);
+   procmon = icl_get_procmon_ref_values(dev_priv, phy);
 
val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
val &= ~((0xff << 16) | 0xff);
@@ -109,13 +104,13 @@ static bool check_phy_reg(struct drm_i915_private 
*dev_priv,
return true;
 }
 
-static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
+static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
  enum phy phy)
 {
-   const struct cnl_procmon *procmon;
+   const struct icl_procmon *procmon;
bool ret;
 
-   procmon = cnl_get_procmon_ref_values(dev_priv, phy);
+   procmon = icl_get_procmon_ref_values(dev_priv, phy);
 
ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
(0xff << 16) | 0xff, procmon->dw1);
@@ -127,61 +122,6 @@ static bool cnl_verify_procmon_ref_values(struct 
drm_i915_private *dev_priv,
return ret;
 }
 
-static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
-{
-   return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
-   (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT);
-}
-
-static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
-{
-   enum phy phy = PHY_A;
-   bool ret;
-
-   if (!cnl_combo_phy_enabled(dev_priv))
-   return false;
-
-   ret = cnl_verify_procmon_ref_values(dev_priv, phy);
-
-   ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
-

[Intel-gfx] [PATCH 12/25] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in skl_universal_plane.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 3ad04bf2a0fd..0f40f8b07724 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
return 0;
 }
 
-static u32 cnl_plane_ctl_flip(unsigned int reflect)
+static u32 icl_plane_ctl_flip(unsigned int reflect)
 {
switch (reflect) {
case 0:
@@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
-   plane_ctl |= cnl_plane_ctl_flip(rotation &
+   if (DISPLAY_VER(dev_priv) >= 11)
+   plane_ctl |= icl_plane_ctl_flip(rotation &
DRM_MODE_REFLECT_MASK);
 
if (key->flags & I915_SET_COLORKEY_DESTINATION)
@@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private 
*dev_priv,
if (plane_id == PLANE_CURSOR)
return false;
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+   if (DISPLAY_VER(dev_priv) >= 11)
return true;
 
if (IS_GEMINILAKE(dev_priv))
@@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private 
*dev_priv,
DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+   if (DISPLAY_VER(dev_priv) >= 11)
supported_rotations |= DRM_MODE_REFLECT_X;
 
drm_plane_create_rotation_property(&plane->base,
@@ -2174,7 +2174,7 @@ skl_universal_plane_create(struct drm_i915_private 
*dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
drm_plane_enable_fb_damage_clips(&plane->base);
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
+   if (DISPLAY_VER(dev_priv) >= 11)
drm_plane_create_scaling_filter_property(&plane->base,
BIT(DRM_SCALING_FILTER_DEFAULT) 
|

BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
@@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
break;
}
 
-   if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val & 
PLANE_CTL_FLIP_HORIZONTAL)
+   if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
plane_config->rotation |= DRM_MODE_REFLECT_X;
 
/* 90/270 degree rotation would require extra work */
-- 
2.31.1

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[Intel-gfx] [PATCH 20/25] drm/i915: rename CNL references in intel_dram.c

[Lucas De Marchi]

With the removal of CNL, let's consider ICL as the first platform using
those constants.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h   | 24 +++
 drivers/gpu/drm/i915/intel_dram.c | 32 +++
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d98c0c97c134..1be6a8c76478 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11085,18 +11085,18 @@ enum skl_power_gate {
 #define  SKL_DRAM_RANK_1   (0x0 << 10)
 #define  SKL_DRAM_RANK_2   (0x1 << 10)
 #define  SKL_DRAM_RANK_MASK(0x1 << 10)
-#define  CNL_DRAM_SIZE_MASK0x7F
-#define  CNL_DRAM_WIDTH_MASK   (0x3 << 7)
-#define  CNL_DRAM_WIDTH_SHIFT  7
-#define  CNL_DRAM_WIDTH_X8 (0x0 << 7)
-#define  CNL_DRAM_WIDTH_X16(0x1 << 7)
-#define  CNL_DRAM_WIDTH_X32(0x2 << 7)
-#define  CNL_DRAM_RANK_MASK(0x3 << 9)
-#define  CNL_DRAM_RANK_SHIFT   9
-#define  CNL_DRAM_RANK_1   (0x0 << 9)
-#define  CNL_DRAM_RANK_2   (0x1 << 9)
-#define  CNL_DRAM_RANK_3   (0x2 << 9)
-#define  CNL_DRAM_RANK_4   (0x3 << 9)
+#define  ICL_DRAM_SIZE_MASK0x7F
+#define  ICL_DRAM_WIDTH_MASK   (0x3 << 7)
+#define  ICL_DRAM_WIDTH_SHIFT  7
+#define  ICL_DRAM_WIDTH_X8 (0x0 << 7)
+#define  ICL_DRAM_WIDTH_X16(0x1 << 7)
+#define  ICL_DRAM_WIDTH_X32(0x2 << 7)
+#define  ICL_DRAM_RANK_MASK(0x3 << 9)
+#define  ICL_DRAM_RANK_SHIFT   9
+#define  ICL_DRAM_RANK_1   (0x0 << 9)
+#define  ICL_DRAM_RANK_2   (0x1 << 9)
+#define  ICL_DRAM_RANK_3   (0x2 << 9)
+#define  ICL_DRAM_RANK_4   (0x3 << 9)
 
 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 
0x5918)
 #define  DG1_QCLK_RATIO_MASK   REG_GENMASK(9, 2)
diff --git a/drivers/gpu/drm/i915/intel_dram.c 
b/drivers/gpu/drm/i915/intel_dram.c
index 83924732183d..91866520c173 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
 }
 
 /* Returns total Gb for the whole DIMM */
-static int cnl_get_dimm_size(u16 val)
+static int icl_get_dimm_size(u16 val)
 {
-   return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
+   return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
 }
 
-static int cnl_get_dimm_width(u16 val)
+static int icl_get_dimm_width(u16 val)
 {
-   if (cnl_get_dimm_size(val) == 0)
+   if (icl_get_dimm_size(val) == 0)
return 0;
 
-   switch (val & CNL_DRAM_WIDTH_MASK) {
-   case CNL_DRAM_WIDTH_X8:
-   case CNL_DRAM_WIDTH_X16:
-   case CNL_DRAM_WIDTH_X32:
-   val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
+   switch (val & ICL_DRAM_WIDTH_MASK) {
+   case ICL_DRAM_WIDTH_X8:
+   case ICL_DRAM_WIDTH_X16:
+   case ICL_DRAM_WIDTH_X32:
+   val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
return 8 << val;
default:
MISSING_CASE(val);
@@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
}
 }
 
-static int cnl_get_dimm_ranks(u16 val)
+static int icl_get_dimm_ranks(u16 val)
 {
-   if (cnl_get_dimm_size(val) == 0)
+   if (icl_get_dimm_size(val) == 0)
return 0;
 
-   val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
+   val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
 
return val + 1;
 }
@@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
   struct dram_dimm_info *dimm,
   int channel, char dimm_name, u16 val)
 {
-   if (GRAPHICS_VER(i915) >= 10) {
-   dimm->size = cnl_get_dimm_size(val);
-   dimm->width = cnl_get_dimm_width(val);
-   dimm->ranks = cnl_get_dimm_ranks(val);
+   if (GRAPHICS_VER(i915) >= 11) {
+   dimm->size = icl_get_dimm_size(val);
+   dimm->width = icl_get_dimm_width(val);
+   dimm->ranks = icl_get_dimm_ranks(val);
} else {
dimm->size = skl_get_dimm_size(val);
dimm->width = skl_get_dimm_width(val);
-- 
2.31.1

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[Intel-gfx] [PATCH 23/25] drm/i915: remove GRAPHICS_VER == 10

[Lucas De Marchi]

Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
{==,>=} 11. With the removal of CNL, there is no platform with graphics
version equals 10.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c |  1 -
 drivers/gpu/drm/i915/gvt/gtt.c |  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c|  6 +++---
 drivers/gpu/drm/i915/i915_drv.h|  2 +-
 drivers/gpu/drm/i915/i915_perf.c   | 21 -
 5 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index b0c3a7dc60d1..34070d0ea325 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region 
*mem)
break;
case 8:
case 9:
-   case 10:
if (IS_LP(i915))
chv_get_stolen_reserved(i915, uncore,
&reserved_base, &reserved_size);
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index cc2c05e18206..e5c2fdfc20e3 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
 {
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 
-   if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
+   if (GRAPHICS_VER(dev_priv) == 9) {
u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
GAMW_ECO_ENABLE_64K_IPS_FIELD;
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0529576f069c..44969f5dde50 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_GEN9_BC(dev_priv) ||
-GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 
1);
+GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 
1);
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
   intel_gpu_freq(rps, max_freq));
 
max_freq = (rp_state_cap & 0xff00) >> 8;
max_freq *= (IS_GEN9_BC(dev_priv) ||
-GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 
1);
+GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 
1);
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
   intel_gpu_freq(rps, max_freq));
 
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_GEN9_BC(dev_priv) ||
-GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 
1);
+GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 
1);
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
   intel_gpu_freq(rps, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4bb42246904..5d5cf5ad0513 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1597,7 +1597,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
+#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
IS_GEMINILAKE(dev_priv) || \
IS_KABYLAKE(dev_priv))
 
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9f94914958c3..05e941cd1065 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream 
*stream)
 
case 8:
case 9:
-   case 10:
if (intel_engine_uses_guc(ce->engine)) {
/*
 * When using GuC, the context descriptor we write in
@@ -2580,7 +2579,7 @@ static void gen8_disable_metric_set(struct 
i915_perf_stream *stream)
intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
 }
 
-static void gen10_disable_metric_set(struct i915_perf_stream *stream)
+static void gen11_disable_metric_set(struct i915_perf_stream *stream)
 {
struct intel_uncore *uncore = stream->uncore;
 
@@ -3887,7 +3886,7 @@ static bool gen8_i

[Intel-gfx] [PATCH 21/25] drm/i915: replace random CNL comments

[Lucas De Marchi]

Cleanup remaining cases that we find CNL in the codebase.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux.c   | 1 -
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 -
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h  | 2 +-
 6 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4172c8ee6aa6..e86e6ed2d3bf 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
"Port %c VBT HDMI boost level: %d\n",
port_name(port), hdmi_boost_level);
 
-   /* DP max link rate for CNL+ */
+   /* DP max link rate for GLK+ */
if (i915->vbt.version >= 216) {
if (i915->vbt.version >= 230)
info->dp_max_link_rate = 
parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8597194bea88..f76233cf36cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9819,7 +9819,7 @@ static int intel_atomic_check_async(struct 
intel_atomic_state *state)
 
/*
 * FIXME: This check is kept generic for all platforms.
-* Need to verify this for all gen9 and gen10 platforms to 
enable
+* Need to verify this for all gen9 platforms to enable
 * this selectively if required.
 */
switch (new_plane_state->hw.fb->modifier) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c 
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 7c048d2ecf43..f483f479dd0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
/*
 * Max timeout values:
 * SKL-GLK: 1.6ms
-* CNL: 3.2ms
 * ICL+: 4ms
 */
ret = DP_AUX_CH_CTL_SEND_BUSY |
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 7fd031a70cfd..6b19f74efd61 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -206,7 +206,6 @@ struct intel_dpll_hw_state {
 
/* cnl */
u32 cfgcr0;
-   /* CNL also uses cfgcr1 */
 
/* bxt */
u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, 
pcsdw12;
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h 
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index dbe24d7e7375..330077c2e588 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -456,7 +456,7 @@ struct child_device_config {
u16 dp_gpio_pin_num;/* 195 */
u8 dp_iboost_level:4;   /* 196 */
u8 hdmi_iboost_level:4; /* 196 */
-   u8 dp_max_link_rate:3;  /* 216/230 CNL+ 
*/
+   u8 dp_max_link_rate:3;  /* 216/230 GLK+ 
*/
u8 dp_max_link_rate_reserved:5; /* 216/230 */
 } __packed;
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 616ccec41d76..316edad22eb0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -105,7 +105,7 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_ULT  (0)
 #define INTEL_SUBPLATFORM_ULX  (1)
 
-/* CNL/ICL */
+/* ICL */
 #define INTEL_SUBPLATFORM_PORTF(0)
 
 /* DG2 */
-- 
2.31.1

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[Intel-gfx] [PATCH 03/25] drm/i915/display: remove explicit CNL handling from intel_color.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK, so we don't need
any checks and supporting code for CNL. For DISPLAY_VER >= 11,
ilk_load_csc_matrix() is not used, so make it handle GLK only.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_color.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c 
b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..afcb4bf3826c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -305,13 +305,12 @@ static void ilk_load_csc_matrix(const struct 
intel_crtc_state *crtc_state)
ilk_csc_postoff_limited_range);
} else if (crtc_state->csc_enable) {
/*
-* On GLK+ both pipe CSC and degamma LUT are controlled
+* On GLK both pipe CSC and degamma LUT are controlled
 * by csc_enable. Hence for the cases where the degama
 * LUT is needed but CSC is not we need to load an
 * identity matrix.
 */
-   drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) &&
-   !IS_GEMINILAKE(dev_priv));
+   drm_WARN_ON(&dev_priv->drm, !IS_GEMINILAKE(dev_priv));
 
ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
ilk_csc_coeff_identity,
-- 
2.31.1

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[Intel-gfx] [PATCH 25/25] drm/i915: finish removal of CNL

[Lucas De Marchi]

With all the users removed, finish removing the CNL platform definitions.
We will leave the PCI IDs around as those are exposed to userspace.
Even if mesa doesn't support CNL anymore, let's avoid build breakages
due to changing the headers.

Also, due to drm/i915/gt still using IS_CANNONLAKE() let's just redefine
it instead of removing.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_drv.h  |  8 ++--
 drivers/gpu/drm/i915/i915_pci.c  | 23 +--
 drivers/gpu/drm/i915/i915_perf.c |  1 -
 drivers/gpu/drm/i915/intel_device_info.c |  2 --
 drivers/gpu/drm/i915/intel_device_info.h |  2 --
 5 files changed, 7 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5d5cf5ad0513..6ac90ccbee0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1380,7 +1380,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 #define IS_COFFEELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
-#define IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_CANNONLAKE(dev_priv)0
 #define IS_ICELAKE(dev_priv)   IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_JSL_EHL(dev_priv)   (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
@@ -1446,8 +1446,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_CML_GT2(dev_priv)   (IS_COMETLAKE(dev_priv) && \
 INTEL_INFO(dev_priv)->gt == 2)
 
-#define IS_CNL_WITH_PORT_F(dev_priv) \
-   IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
 #define IS_ICL_WITH_PORT_F(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
 
@@ -1592,9 +1590,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)   \
-   (IS_CANNONLAKE(dev_priv) || \
-IS_SKL_GT3(dev_priv) ||\
-IS_SKL_GT4(dev_priv))
+   (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ec80cd1cd00c..cb4a46174513 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = {
.gt = 2,
 };
 
-#define GEN10_FEATURES \
-   GEN9_FEATURES, \
-   GEN(10), \
-   .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
-   .display.has_dsc = 1, \
-   .has_coherent_ggtt = false, \
-   GLK_COLORS
-
-static const struct intel_device_info cnl_info = {
-   GEN10_FEATURES,
-   PLATFORM(INTEL_CANNONLAKE),
-   .gt = 2,
-};
-
 #define GEN11_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
  I915_GTT_PAGE_SIZE_64K | \
  I915_GTT_PAGE_SIZE_2M
 
 #define GEN11_FEATURES \
-   GEN10_FEATURES, \
+   GEN9_FEATURES, \
GEN11_DEFAULT_PAGE_SIZES, \
.abox_mask = BIT(0), \
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
@@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
GEN(11), \
+   .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
.dbuf.size = 2048, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
-   .has_logical_ring_elsq = 1, \
-   .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
+   .display.has_dsc = 1, \
+   .has_coherent_ggtt = false, \
+   .has_logical_ring_elsq = 1
 
 static const struct intel_device_info icl_info = {
GEN11_FEATURES,
@@ -1123,7 +,6 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CML_GT2_IDS(&cml_gt2_info),
INTEL_CML_U_GT1_IDS(&cml_gt1_info),
INTEL_CML_U_GT2_IDS(&cml_gt2_info),
-   INTEL_CNL_IDS(&cnl_info),
INTEL_ICL_11_IDS(&icl_info),
INTEL_EHL_IDS(&ehl_info),
INTEL_JSL_IDS(&jsl_info),
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 05e941cd1065..efef89e53440 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4309,7 +4309,6 @@ static void oa_init_supported_formats(struct i915_perf 
*perf)
case INTEL_GEMINILAKE:
case INTEL_COFFEELAKE:
case INTEL_COMETLAKE:
-   case INTEL_CANNONLA

[Intel-gfx] [PATCH 09/25] drm/i915/display: remove explicit CNL handling from intel_dp.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_dp.c.

Remove code and rename functions/macros accordingly to use ICL prefix.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 35 -
 1 file changed, 5 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index c386ef8eb200..db701ec5a221 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 encoder->port != PORT_A);
 }
 
-static int cnl_max_source_rate(struct intel_dp *intel_dp)
-{
-   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-   enum port port = dig_port->base.port;
-
-   u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & 
VOLTAGE_INFO_MASK;
-
-   /* Low voltage SKUs are limited to max of 5.4G */
-   if (voltage == VOLTAGE_INFO_0_85V)
-   return 54;
-
-   /* For this SKU 8.1G is supported in all ports */
-   if (IS_CNL_WITH_PORT_F(dev_priv))
-   return 81;
-
-   /* For other SKUs, max rate on ports A and D is 5.4G */
-   if (port == PORT_A || port == PORT_D)
-   return 54;
-
-   return 81;
-}
-
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -270,7 +247,7 @@ static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
/* The values must be in increasing order */
-   static const int cnl_rates[] = {
+   static const int icl_rates[] = {
162000, 216000, 27, 324000, 432000, 54, 648000, 81
};
static const int bxt_rates[] = {
@@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
 
-   if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
-   source_rates = cnl_rates;
-   size = ARRAY_SIZE(cnl_rates);
-   if (DISPLAY_VER(dev_priv) == 10)
-   max_rate = cnl_max_source_rate(intel_dp);
-   else if (IS_JSL_EHL(dev_priv))
+   if (DISPLAY_VER(dev_priv) >= 11) {
+   source_rates = icl_rates;
+   size = ARRAY_SIZE(icl_rates);
+   if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
-- 
2.31.1

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[Intel-gfx] [PATCH 14/25] drm/i915/display: remove CNL ddi buf translation tables

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  12 +-
 .../drm/i915/display/intel_ddi_buf_trans.c| 616 +-
 .../drm/i915/display/intel_ddi_buf_trans.h|   4 +-
 3 files changed, 184 insertions(+), 448 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6e6d37b97c51..a989a56fc9ff 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1055,8 +1055,8 @@ static void icl_ddi_combo_vswing_program(struct 
intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 RCOMP_SCALAR_MASK);
-   val |= 
SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-   val |= 
SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
+   val |= 
SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
+   val |= 
SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
val |= RCOMP_SCALAR(0x98);
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
@@ -1067,16 +1067,16 @@ static void icl_ddi_combo_vswing_program(struct 
intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 CURSOR_COEFF_MASK);
-   val |= 
POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
-   val |= 
POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
-   val |= 
CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
+   val |= 
POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
+   val |= 
POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
+   val |= 
CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
}
 
/* Program PORT_TX_DW7 */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
val &= ~N_SCALAR_MASK;
-   val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
+   val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 63b1ae830d9a..9ab95bcd0c86 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans 
bxt_ddi_translations_hdmi = {
.hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
 };
 
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] 
= {
-   /* NT mV Trans mV db
*/
-   { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
*/
-   { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350   500  3.1   
*/
-   { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350   700  6.0   
*/
-   { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350   900  8.2   
*/
-   { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
-   { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500   700  2.9   
*/
-   { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500   900  5.1   
*/
-   { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650   725  0.9   
*/
-   { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600   900  3.5   
*/
-   { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
*/
-};
-
-static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
-   .entries = _cnl_ddi_translations_dp_0_85V,
-   .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for HDMI */
-static const union intel_ddi_buf_trans_entry 
_cnl_ddi_translations_hdmi_0_85V[] = {
-   /* NT mV Trans mV db
*/
-   { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450   450  0.0   
*/
-   { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450   650  3.2   
*/
-   { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450   850  5.5   
*/
-   { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650   650  0.0   
*/
-   { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0

[Intel-gfx] [PATCH 06/25] drm/i915/display: remove explicit CNL handling from intel_ddi.c

[Lucas De Marchi]

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly in intel_ddi.c.

Remove code and rename functions/macros accordingly to use ICL prefix.
There's one leftover reference to cnl that comes from the struct
intel_ddi_buf_trans. This will be renamed later when we get rid of the
additional CNL tables.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 254 ++-
 1 file changed, 20 insertions(+), 234 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 061a663f43b8..6e6d37b97c51 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -822,7 +822,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 static enum intel_display_power_domain
 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 {
-   /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
+   /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 * DC states enabled at the same time, while for driver initiated AUX
 * transfers we need the same AUX IOs to be powered but with DC states
 * disabled. Accordingly use the AUX power domain here which leaves DC
@@ -1017,126 +1017,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp 
*intel_dp)
return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
-static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
-  const struct intel_crtc_state *crtc_state,
-  int level)
-{
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   const struct intel_ddi_buf_trans *ddi_translations;
-   enum port port = encoder->port;
-   int n_entries, ln;
-   u32 val;
-
-   ddi_translations = encoder->get_buf_trans(encoder, crtc_state, 
&n_entries);
-   if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
-   return;
-   if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
-   level = n_entries - 1;
-
-   /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
-   val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-   val &= ~SCALING_MODE_SEL_MASK;
-   val |= SCALING_MODE_SEL(2);
-   intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-
-   /* Program PORT_TX_DW2 */
-   val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
-   val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
-RCOMP_SCALAR_MASK);
-   val |= 
SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-   val |= 
SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
-   /* Rcomp scalar is fixed as 0x98 for every table entry */
-   val |= RCOMP_SCALAR(0x98);
-   intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
-
-   /* Program PORT_TX_DW4 */
-   /* We cannot write to GRP. It would overrite individual loadgen */
-   for (ln = 0; ln < 4; ln++) {
-   val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
-   val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
-CURSOR_COEFF_MASK);
-   val |= 
POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
-   val |= 
POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
-   val |= 
CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
-   intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
-   }
-
-   /* Program PORT_TX_DW5 */
-   /* All DW5 values are fixed for every table entry */
-   val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
-   val &= ~RTERM_SELECT_MASK;
-   val |= RTERM_SELECT(6);
-   val |= TAP3_DISABLE;
-   intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
-
-   /* Program PORT_TX_DW7 */
-   val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
-   val &= ~N_SCALAR_MASK;
-   val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
-   intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
-}
-
-static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
-   const struct intel_crtc_state *crtc_state,
-   int level)
-{
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   enum port port = encoder->port;
-   int width, rate, ln;
-   u32 val;
-
-   width = crtc_state->lane_count;
-   rate = crtc_state->port_clock;
-
-   /*
-* 1. If port type is eDP or DP,
-* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
-* else clear to 0b.
-*/
-   val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
-   if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDM

[Intel-gfx] [PATCH 16/25] drm/i915: remove explicit CNL handling from i915_irq.c

[Lucas De Marchi]

Remove special handling of PORT_F in i915_irq.c and only do it for
DISPLAY_VER == 11.

Signed-off-by: Lucas De Marchi 
Reviewed-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_irq.c | 7 +++
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e1774e48499..1b9ee92b6ee7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct 
drm_i915_private *dev_priv)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
 
-   if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
-   mask |= CNL_AUX_CHANNEL_F;
-
-   if (DISPLAY_VER(dev_priv) == 11)
+   if (DISPLAY_VER(dev_priv) == 11) {
+   mask |= ICL_AUX_CHANNEL_F;
mask |= ICL_AUX_CHANNEL_E;
+   }
 
return mask;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf1d0cadc208..02d645c573f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7939,7 +7939,7 @@ enum {
 #define  DSI1_NON_TE   (1 << 31)
 #define  DSI0_NON_TE   (1 << 30)
 #define  ICL_AUX_CHANNEL_E (1 << 29)
-#define  CNL_AUX_CHANNEL_F (1 << 28)
+#define  ICL_AUX_CHANNEL_F (1 << 28)
 #define  GEN9_AUX_CHANNEL_D(1 << 27)
 #define  GEN9_AUX_CHANNEL_C(1 << 26)
 #define  GEN9_AUX_CHANNEL_B(1 << 25)
-- 
2.31.1

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