[Intel-gfx] ✓ Fi.CI.BAT: success for MIPI DSI driver enhancements (rev4)
== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10392 -> Patchwork_20703
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/index.html
Known issues
Here are the changes found in Patchwork_20703 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-apl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][2] ([i915#1610])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@i915_hang...@error-state-basic.html
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][3] ([i915#2426] / [i915#3363])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-apl-guc/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gtt:
- {fi-tgl-dsi}: [DMESG-FAIL][4] ([i915#2927]) -> [PASS][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/fi-tgl-dsi/igt@i915_selftest@l...@gtt.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-tgl-dsi/igt@i915_selftest@l...@gtt.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-FAIL][6] ([i915#165]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 35)
--
Additional (1): fi-apl-guc
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adls-4 bat-adls-3
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10392 -> Patchwork_20703
CI-20190529: 20190529
CI_DRM_10392: 5ed997f5d0de6cbd2379499e7c132410df93922d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20703: 4956eeca561c8f9feffd3ed5bd56d4037e4ab432 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4956eeca561c drm/i915/dsi: Send proper brightness value via MIPI DCS command
b62bfc065334 drm/i915/dsi: Retrieve max brightness level from VBT.
fef2d31a1c41 drm/i915: Get proper min cdclk if vDSC enabled
cb2493d12c0d drm/i915/dsi: refine send MIPI DCS command sequence
4a2d5040a99d drm/i915/dsi: wait for header and payload credit available
1994193a9893 drm/i915/jsl: program DSI panel GPIOs
77529e9e348e drm/i915/dsi: send correct gpio_number on gen11 platform
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
On Fri, 23 Jul 2021 at 18:49, Jason Ekstrand wrote:
>
> Are there IGTs for this anywhere?
https://patchwork.freedesktop.org/series/92580/
>
> On Fri, Jul 23, 2021 at 12:47 PM Jason Ekstrand wrote:
> >
> > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044
> >
> > On Fri, Jul 23, 2021 at 6:35 AM Matthew Auld wrote:
> > >
> > > From: Chris Wilson
> > >
> > > Jason Ekstrand requested a more efficient method than userptr+set-domain
> > > to determine if the userptr object was backed by a complete set of pages
> > > upon creation. To be more efficient than simply populating the userptr
> > > using get_user_pages() (as done by the call to set-domain or execbuf),
> > > we can walk the tree of vm_area_struct and check for gaps or vma not
> > > backed by struct page (VM_PFNMAP). The question is how to handle
> > > VM_MIXEDMAP which may be either struct page or pfn backed...
> > >
> > > With discrete we are going to drop support for set_domain(), so offering
> > > a way to probe the pages, without having to resort to dummy batches has
> > > been requested.
> > >
> > > v2:
> > > - add new query param for the PROBE flag, so userspace can easily
> > > check if the kernel supports it(Jason).
> > > - use mmap_read_{lock, unlock}.
> > > - add some kernel-doc.
> > > v3:
> > > - In the docs also mention that PROBE doesn't guarantee that the pages
> > > will remain valid by the time they are actually used(Tvrtko).
> > > - Add a small comment for the hole finding logic(Jason).
> > > - Move the param next to all the other params which just return true.
> > >
> > > Testcase: igt/gem_userptr_blits/probe
> > > Signed-off-by: Chris Wilson
> > > Signed-off-by: Matthew Auld
> > > Cc: Thomas Hellström
> > > Cc: Maarten Lankhorst
> > > Cc: Tvrtko Ursulin
> > > Cc: Jordan Justen
> > > Cc: Kenneth Graunke
> > > Cc: Jason Ekstrand
> > > Cc: Daniel Vetter
> > > Cc: Ramalingam C
> > > Reviewed-by: Tvrtko Ursulin
> > > Acked-by: Kenneth Graunke
> > > Reviewed-by: Jason Ekstrand
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> > > drivers/gpu/drm/i915/i915_getparam.c| 1 +
> > > include/uapi/drm/i915_drm.h | 20 ++
> > > 3 files changed, 61 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > index 56edfeff8c02..468a7a617fbf 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
> > > i915_gem_userptr_ops = {
> > >
> > > #endif
> > >
> > > +static int
> > > +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> > > +{
> > > + const unsigned long end = addr + len;
> > > + struct vm_area_struct *vma;
> > > + int ret = -EFAULT;
> > > +
> > > + mmap_read_lock(mm);
> > > + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> > > + /* Check for holes, note that we also update the addr
> > > below */
> > > + if (vma->vm_start > addr)
> > > + break;
> > > +
> > > + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> > > + break;
> > > +
> > > + if (vma->vm_end >= end) {
> > > + ret = 0;
> > > + break;
> > > + }
> > > +
> > > + addr = vma->vm_end;
> > > + }
> > > + mmap_read_unlock(mm);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > /*
> > > * Creates a new mm object that wraps some normal memory from the process
> > > * context - user memory.
> > > @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > > }
> > >
> > > if (args->flags & ~(I915_USERPTR_READ_ONLY |
> > > - I915_USERPTR_UNSYNCHRONIZED))
> > > + I915_USERPTR_UNSYNCHRONIZED |
> > > + I915_USERPTR_PROBE))
> > > return -EINVAL;
> > >
> > > if (i915_gem_object_size_2big(args->user_size))
> > > @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > > return -ENODEV;
> > > }
> > >
> > > + if (args->flags & I915_USERPTR_PROBE) {
> > > + /*
> > > +* Check that the range pointed to represents real struct
> > > +* pages and not iomappings (at this moment in time!)
> > > +*/
> > > + ret = probe_range(current->mm, args->user_ptr,
> > > args->user_size);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > #ifdef CONFIG_MMU_NOTIFIER
> > > obj = i915_gem_object_alloc();
> > > if (obj == NULL)
> > > diff --git a/drivers/gpu/drm/i915/i915_getparam.c
> > > b/drivers/gpu/drm/i915/i9
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
On Fri, 23 Jul 2021 at 18:48, Jason Ekstrand wrote:
>
> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044
Cool, is that ready to go? i.e can we start merging the kernel + IGT side.
>
> On Fri, Jul 23, 2021 at 6:35 AM Matthew Auld wrote:
> >
> > From: Chris Wilson
> >
> > Jason Ekstrand requested a more efficient method than userptr+set-domain
> > to determine if the userptr object was backed by a complete set of pages
> > upon creation. To be more efficient than simply populating the userptr
> > using get_user_pages() (as done by the call to set-domain or execbuf),
> > we can walk the tree of vm_area_struct and check for gaps or vma not
> > backed by struct page (VM_PFNMAP). The question is how to handle
> > VM_MIXEDMAP which may be either struct page or pfn backed...
> >
> > With discrete we are going to drop support for set_domain(), so offering
> > a way to probe the pages, without having to resort to dummy batches has
> > been requested.
> >
> > v2:
> > - add new query param for the PROBE flag, so userspace can easily
> > check if the kernel supports it(Jason).
> > - use mmap_read_{lock, unlock}.
> > - add some kernel-doc.
> > v3:
> > - In the docs also mention that PROBE doesn't guarantee that the pages
> > will remain valid by the time they are actually used(Tvrtko).
> > - Add a small comment for the hole finding logic(Jason).
> > - Move the param next to all the other params which just return true.
> >
> > Testcase: igt/gem_userptr_blits/probe
> > Signed-off-by: Chris Wilson
> > Signed-off-by: Matthew Auld
> > Cc: Thomas Hellström
> > Cc: Maarten Lankhorst
> > Cc: Tvrtko Ursulin
> > Cc: Jordan Justen
> > Cc: Kenneth Graunke
> > Cc: Jason Ekstrand
> > Cc: Daniel Vetter
> > Cc: Ramalingam C
> > Reviewed-by: Tvrtko Ursulin
> > Acked-by: Kenneth Graunke
> > Reviewed-by: Jason Ekstrand
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> > drivers/gpu/drm/i915/i915_getparam.c| 1 +
> > include/uapi/drm/i915_drm.h | 20 ++
> > 3 files changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > index 56edfeff8c02..468a7a617fbf 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
> > i915_gem_userptr_ops = {
> >
> > #endif
> >
> > +static int
> > +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> > +{
> > + const unsigned long end = addr + len;
> > + struct vm_area_struct *vma;
> > + int ret = -EFAULT;
> > +
> > + mmap_read_lock(mm);
> > + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> > + /* Check for holes, note that we also update the addr below
> > */
> > + if (vma->vm_start > addr)
> > + break;
> > +
> > + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> > + break;
> > +
> > + if (vma->vm_end >= end) {
> > + ret = 0;
> > + break;
> > + }
> > +
> > + addr = vma->vm_end;
> > + }
> > + mmap_read_unlock(mm);
> > +
> > + return ret;
> > +}
> > +
> > /*
> > * Creates a new mm object that wraps some normal memory from the process
> > * context - user memory.
> > @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > }
> >
> > if (args->flags & ~(I915_USERPTR_READ_ONLY |
> > - I915_USERPTR_UNSYNCHRONIZED))
> > + I915_USERPTR_UNSYNCHRONIZED |
> > + I915_USERPTR_PROBE))
> > return -EINVAL;
> >
> > if (i915_gem_object_size_2big(args->user_size))
> > @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > return -ENODEV;
> > }
> >
> > + if (args->flags & I915_USERPTR_PROBE) {
> > + /*
> > +* Check that the range pointed to represents real struct
> > +* pages and not iomappings (at this moment in time!)
> > +*/
> > + ret = probe_range(current->mm, args->user_ptr,
> > args->user_size);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > #ifdef CONFIG_MMU_NOTIFIER
> > obj = i915_gem_object_alloc();
> > if (obj == NULL)
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c
> > b/drivers/gpu/drm/i915/i915_getparam.c
> > index 24e18219eb50..bbb7cac43eb4 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -134,6 +134,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
> > *data,
> > case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
> > case I915_PA
Re: [Intel-gfx] [PATCH 5/8] drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed
On Fri, 23 Jul 2021 at 18:22, Jason Ekstrand wrote: > > __i915_ttm_get_pages does two things. First, it calls ttm_bo_validate() > to check the given placement and migrate the BO if needed. Then, it > updates the GEM object to match, in case the object was migrated. If > no migration occured, however, we might still have pages on the GEM > object in which case we don't need to fetch them from TTM and call > __i915_gem_object_set_pages. This hasn't been a problem before because > the primary user of __i915_ttm_get_pages is __i915_gem_object_get_pages > which only calls it if the GEM object doesn't have pages. > > However, i915_ttm_migrate also uses __i915_ttm_get_pages to do the > migration so this meant it was unsafe to call on an already populated > object. This patch checks i915_gem_object_has_pages() before trying to > __i915_gem_object_set_pages so i915_ttm_migrate is safe to call, even on > populated objects. > > Signed-off-by: Jason Ekstrand Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/8] drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails
On Fri, 23 Jul 2021 at 18:22, Jason Ekstrand wrote:
>
> Without TTM, we have no such hook so we exit early but this is fine
> because we use TTM on all LMEM platforms and, on integrated platforms,
> there is no real migration. If we do have the hook, it's better to just
> let TTM handle the migration because it knows where things are actually
> placed.
>
> This fixes a bug where i915_gem_object_migrate fails to migrate newly
> created LMEM objects. In that scenario, the object has obj->mm.region
> set to LMEM but TTM has it in SMEM because that's where all new objects
> are placed there prior to getting actual pages. When we invoke
> i915_gem_object_migrate, it exits early because, from the point of view
> of the GEM object, it's already in LMEM and no migration is needed.
> Then, when we try to pin the pages, __i915_ttm_get_pages is called
> which, unaware of our failed attempt at a migration, places the object
> in SMEM. This only happens on newly created objects because they have
> this weird state where TTM thinks they're in SMEM, GEM thinks they're in
> LMEM, and the reality is that they don't exist at all.
>
> It's better if GEM just always calls into TTM and let's TTM handle
> things. That way the lies stay better contained. Once the migration is
> complete, the object will have pages, obj->mm.region will be correct,
> and we're done lying.
>
> Signed-off-by: Jason Ekstrand
Thanks for fixing this,
Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index d09bd9bdb38ac..9d3497e1235a0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -607,12 +607,15 @@ int i915_gem_object_migrate(struct drm_i915_gem_object
> *obj,
> mr = i915->mm.regions[id];
> GEM_BUG_ON(!mr);
>
> - if (obj->mm.region == mr)
> - return 0;
> -
> if (!i915_gem_object_can_migrate(obj, id))
> return -EINVAL;
>
> + if (!obj->ops->migrate) {
> + if (GEM_WARN_ON(obj->mm.region != mr))
> + return -EINVAL;
> + return 0;
> + }
> +
> return obj->ops->migrate(obj, mr);
> }
>
> --
> 2.31.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] [PATCH 0/8] drm/i915: Migrate memory to SMEM when imported cross-device (v8)
On Fri, 23 Jul 2021 at 18:21, Jason Ekstrand wrote: > > This patch series fixes an issue with discrete graphics on Intel where we > allowed dma-buf import while leaving the object in local memory. This > breaks down pretty badly if the import happened on a different physical > device. > > v7: > - Drop "drm/i915/gem/ttm: Place new BOs in the requested region" > - Add a new "drm/i915/gem: Call i915_gem_flush_free_objects() in > i915_gem_dumb_create()" > - Misc. review feedback from Matthew Auld > v8: > - Misc. review feedback from Matthew Auld > v9: > - Replace the i915/ttm patch with two that are hopefully more correct > > Jason Ekstrand (6): > drm/i915/gem: Check object_can_migrate from object_migrate > drm/i915/gem: Refactor placement setup for i915_gem_object_create* > (v2) > drm/i915/gem: Call i915_gem_flush_free_objects() in > i915_gem_dumb_create() > drm/i915/gem: Unify user object creation (v3) > drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed > drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails > > Thomas Hellström (2): > drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8) > drm/i915/gem: Migrate to system at dma-buf attach time (v7) Should I push the series? > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 177 > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 58 -- > drivers/gpu/drm/i915/gem/i915_gem_object.c| 20 +- > drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 + > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 +- > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 190 +- > .../drm/i915/gem/selftests/i915_gem_migrate.c | 15 -- > 7 files changed, 341 insertions(+), 136 deletions(-) > > -- > 2.31.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
Op 23-07-2021 om 13:34 schreef Matthew Auld:
> From: Chris Wilson
>
> Jason Ekstrand requested a more efficient method than userptr+set-domain
> to determine if the userptr object was backed by a complete set of pages
> upon creation. To be more efficient than simply populating the userptr
> using get_user_pages() (as done by the call to set-domain or execbuf),
> we can walk the tree of vm_area_struct and check for gaps or vma not
> backed by struct page (VM_PFNMAP). The question is how to handle
> VM_MIXEDMAP which may be either struct page or pfn backed...
>
> With discrete we are going to drop support for set_domain(), so offering
> a way to probe the pages, without having to resort to dummy batches has
> been requested.
>
> v2:
> - add new query param for the PROBE flag, so userspace can easily
> check if the kernel supports it(Jason).
> - use mmap_read_{lock, unlock}.
> - add some kernel-doc.
> v3:
> - In the docs also mention that PROBE doesn't guarantee that the pages
> will remain valid by the time they are actually used(Tvrtko).
> - Add a small comment for the hole finding logic(Jason).
> - Move the param next to all the other params which just return true.
>
> Testcase: igt/gem_userptr_blits/probe
> Signed-off-by: Chris Wilson
> Signed-off-by: Matthew Auld
> Cc: Thomas Hellström
> Cc: Maarten Lankhorst
> Cc: Tvrtko Ursulin
> Cc: Jordan Justen
> Cc: Kenneth Graunke
> Cc: Jason Ekstrand
> Cc: Daniel Vetter
> Cc: Ramalingam C
> Reviewed-by: Tvrtko Ursulin
> Acked-by: Kenneth Graunke
> Reviewed-by: Jason Ekstrand
> ---
> drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> drivers/gpu/drm/i915/i915_getparam.c| 1 +
> include/uapi/drm/i915_drm.h | 20 ++
> 3 files changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 56edfeff8c02..468a7a617fbf 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
> i915_gem_userptr_ops = {
>
> #endif
>
> +static int
> +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> +{
> + const unsigned long end = addr + len;
> + struct vm_area_struct *vma;
> + int ret = -EFAULT;
> +
> + mmap_read_lock(mm);
> + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> + /* Check for holes, note that we also update the addr below */
> + if (vma->vm_start > addr)
> + break;
> +
> + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> + break;
> +
> + if (vma->vm_end >= end) {
> + ret = 0;
> + break;
> + }
> +
> + addr = vma->vm_end;
> + }
> + mmap_read_unlock(mm);
> +
> + return ret;
> +}
> +
> /*
> * Creates a new mm object that wraps some normal memory from the process
> * context - user memory.
> @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> }
>
> if (args->flags & ~(I915_USERPTR_READ_ONLY |
> - I915_USERPTR_UNSYNCHRONIZED))
> + I915_USERPTR_UNSYNCHRONIZED |
> + I915_USERPTR_PROBE))
> return -EINVAL;
>
> if (i915_gem_object_size_2big(args->user_size))
> @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> return -ENODEV;
> }
>
> + if (args->flags & I915_USERPTR_PROBE) {
> + /*
> + * Check that the range pointed to represents real struct
> + * pages and not iomappings (at this moment in time!)
> + */
> + ret = probe_range(current->mm, args->user_ptr, args->user_size);
> + if (ret)
> + return ret;
> + }
> +
> #ifdef CONFIG_MMU_NOTIFIER
> obj = i915_gem_object_alloc();
> if (obj == NULL)
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c
> b/drivers/gpu/drm/i915/i915_getparam.c
> index 24e18219eb50..bbb7cac43eb4 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -134,6 +134,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
> *data,
> case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
> case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
> case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
> + case I915_PARAM_HAS_USERPTR_PROBE:
> /* For the time being all of these are always true;
>* if some supported hardware does not have one of these
>* features this value needs to be provided from
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 975087553ea0..0d290535a6e5 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -674,6 +674,9 @@ typ
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On 23/07/2021 20:29, Daniel Vetter wrote:
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_ce to just a
slab_ce.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/gt/intel_context.c | 25 -
drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
drivers/gpu/drm/i915/i915_globals.c | 2 --
drivers/gpu/drm/i915/i915_globals.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 2 ++
5 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index baa05fddd690..283382549a6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -7,7 +7,6 @@
#include "gem/i915_gem_pm.h"
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_context.h"
@@ -15,14 +14,11 @@
#include "intel_engine_pm.h"
#include "intel_ring.h"
-static struct i915_global_context {
- struct i915_global base;
- struct kmem_cache *slab_ce;
-} global;
+struct kmem_cache *slab_ce;
static struct intel_context *intel_context_alloc(void)
{
- return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
+ return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
}
static void rcu_context_free(struct rcu_head *rcu)
@@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
trace_intel_context_free(ce);
- kmem_cache_free(global.slab_ce, ce);
+ kmem_cache_free(slab_ce, ce);
}
void intel_context_free(struct intel_context *ce)
@@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
i915_active_fini(&ce->active);
}
-static void i915_global_context_exit(void)
+void i915_context_module_exit(void)
{
- kmem_cache_destroy(global.slab_ce);
+ kmem_cache_destroy(slab_ce);
}
-static struct i915_global_context global = { {
- .exit = i915_global_context_exit,
-} };
-
-int __init i915_global_context_init(void)
+int __init i915_context_module_init(void)
{
- global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
- if (!global.slab_ce)
+ slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
+ if (!slab_ce)
return -ENOMEM;
- i915_global_register(&global.base);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index 974ef85320c2..a0ca82e3c40d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
struct intel_engine_cs *engine);
void intel_context_fini(struct intel_context *ce);
+void i915_context_module_exit(void);
+int i915_context_module_init(void);
+
struct intel_context *
intel_context_create(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_globals.c b/drivers/gpu/drm/i915/i915_globals.c
index 3de7cf22ec76..d36eb7dc40aa 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -7,7 +7,6 @@
#include
#include
-#include "gem/i915_gem_context.h"
#include "gem/i915_gem_object.h"
#include "i915_globals.h"
#include "i915_request.h"
@@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_context_init,
i915_global_gem_context_init,
i915_global_objects_init,
i915_global_request_init,
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index d80901ba75e3..60daa738a188 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -23,7 +23,6 @@ int i915_globals_init(void);
void i915_globals_exit(void);
/* constructors */
-int i915_global_context_init(void);
int i915_global_gem_context_init(void);
int i915_global_objects_init(void);
int i915_global_request_init(void);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9527269e30a..266618157775 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -33,6 +33,7 @@
#include "i915_active.h"
#include "i915_buddy.h"
#include "i915_drv.h"
+#include "gem/i915_gem_context.h"
It's a bit ugly to go to a design where i915_pci.c has to include so
many random parts of i915. IMO for a complex driver like i915,
compartmentalizing so much knowledge about the internals was better
inside the globals layer.
Maybe add a cover letter to explain the perceived pros and cons and
thinking in general?
Regards,
Tvrtko
#include "i915_perf.h"
Re: [Intel-gfx] [RFC 6/8] drm: Document fdinfo format specification
On 23/07/2021 17:43, Daniel Stone wrote: Hi Tvrtko, Thanks for typing this up! On Thu, 15 Jul 2021 at 10:18, Tvrtko Ursulin wrote: +Mandatory fully standardised keys +- + +- drm-driver: + +String shall contain a fixed string uniquely identified the driver handling +the device in question. For example name of the respective kernel module. I think let's be more prescriptive and just say that it is the module name. I liked the drm_driver.name the other Daniel made so I'll go with that. +Optional fully standardised keys + + +- drm-pdev: + +For PCI devices this should contain the PCI slot address of the device in +question. How about just major:minor of the DRM render node device it's attached to? I don't have a strong opinion on this one. I can add it, but might keep the drm-dev tag under the optional list because it is handy for intel_gpu_top multi-device support. Or maybe the lookup to pci device is easier than I think now so okay, on my todo list to check. +- drm-client-id: + +Unique value relating to the open DRM file descriptor used to distinguish +duplicated and shared file descriptors. Conceptually the value should map 1:1 +to the in kernel representation of `struct drm_file` instances. + +Uniqueness of the value shall be either globally unique, or unique within the +scope of each device, in which case `drm-pdev` shall be present as well. + +Userspace should make sure to not double account any usage statistics by using +the above described criteria in order to associate data to individual clients. + +- drm-engine-: ns + +GPUs usually contain multiple execution engines. Each shall be given a stable +and unique name (str), with possible values documented in the driver specific +documentation. + +Value shall be in specified time units which the respective GPU engine spent +busy executing workloads belonging to this client. + +Values are not required to be constantly monotonic if it makes the driver +implementation easier, but are required to catch up with the previously reported +larger value within a reasonable period. Upon observing a value lower than what +was previously read, userspace is expected to stay with that larger previous +value until a monotonic update is seen. Yeah, that would work well for Mali/Panfrost. We can queue multiple jobs in the hardware, which can either be striped across multiple cores with an affinity mask (e.g. 3 cores for your client and 1 for your compositor), or picked according to priority, or ... The fine-grained performance counters (e.g. time spent waiting for sampler) are only GPU-global. So if you have two jobs running simultaneously, you have no idea who's responsible for what. But it does give us coarse-grained counters which are accounted per-job-slot, including exactly this metric: amount of 'GPU time' (whatever that means) occupied by that job slot during the sampling period. So we could support that nicely if we fenced job-slot updates with register reads/writes. Something I'm missing though is how we enable this information. Seems like it would be best to either only do it whilst fdinfo is open (and re-read it whenever you need an update), or on a per-driver sysfs toggle, or ... ? Presumably there is non-trivial cost for querying this data on your driver? Would it be workable to enable tracking on first use and stop some time after last? Just a thought which may have significant downsides from driver to driver. +- drm-memory-: [KiB|MiB] + +Each possible memory type which can be used to store buffer objects by the +GPU in question shall be given a stable and unique name to be returned as the +string here. + +Value shall reflect the amount of storage currently consumed by the buffer +object belong to this client, in the respective memory region. + +Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB' +indicating kibi- or mebi-bytes. I'm a bit wary of the accounting here. Is it buffer allocations originating from the client, in which case it conceptually clashes with gralloc? Is it the client which last wrote to the buffer? The client with the oldest open handle to the buffer? Other? Haven't looked into AMD code here so know what they export. Gralloc allocates buffer from it's own drm client and shares them or it is just a library which runs from a client context? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/3] drm: use the lookup lock in drm_is_current_master
Inside drm_is_current_master, using the outer drm_device.master_mutex
to protect reads of drm_file.master makes the function prone to creating
lock hierarchy inversions. Instead, we can use the
drm_file.master_lookup_lock that sits at the bottom of the lock
hierarchy.
Reported-by: Daniel Vetter
Signed-off-by: Desmond Cheong Zhi Xi
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_auth.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c
index f00354bec3fb..9c24b8cc8e36 100644
--- a/drivers/gpu/drm/drm_auth.c
+++ b/drivers/gpu/drm/drm_auth.c
@@ -63,8 +63,9 @@
static bool drm_is_current_master_locked(struct drm_file *fpriv)
{
- lockdep_assert_held_once(&fpriv->minor->dev->master_mutex);
-
+ /* Either drm_device.master_mutex or drm_file.master_lookup_lock
+* should be held here.
+*/
return fpriv->is_master && drm_lease_owner(fpriv->master) ==
fpriv->minor->dev->master;
}
@@ -82,9 +83,9 @@ bool drm_is_current_master(struct drm_file *fpriv)
{
bool ret;
- mutex_lock(&fpriv->minor->dev->master_mutex);
+ spin_lock(&fpriv->master_lookup_lock);
ret = drm_is_current_master_locked(fpriv);
- mutex_unlock(&fpriv->minor->dev->master_mutex);
+ spin_unlock(&fpriv->master_lookup_lock);
return ret;
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/vmwgfx: fix potential UAF in vmwgfx_surface.c
drm_file.master should be protected by either drm_device.master_mutex or drm_file.master_lookup_lock when being dereferenced. However, drm_master_get is called on unprotected file_priv->master pointers in vmw_surface_define_ioctl and vmw_gb_surface_define_internal. This is fixed by replacing drm_master_get with drm_file_get_master. Signed-off-by: Desmond Cheong Zhi Xi Reviewed-by: Daniel Vetter Reviewed-by: Zack Rusin --- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c index 0eba47762bed..5d53a5f9d123 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c @@ -865,7 +865,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data, user_srf->prime.base.shareable = false; user_srf->prime.base.tfile = NULL; if (drm_is_primary_client(file_priv)) - user_srf->master = drm_master_get(file_priv->master); + user_srf->master = drm_file_get_master(file_priv); /** * From this point, the generic resource management functions @@ -1534,7 +1534,7 @@ vmw_gb_surface_define_internal(struct drm_device *dev, user_srf = container_of(srf, struct vmw_user_surface, srf); if (drm_is_primary_client(file_priv)) - user_srf->master = drm_master_get(file_priv->master); + user_srf->master = drm_file_get_master(file_priv); res = &user_srf->srf.res; -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm: clarify usage of drm leases
We make the following changes to the documentation of drm leases to make it easier to reason about their usage. In particular, we clarify the lifetime and locking rules of lease fields in drm_master: 1. Make it clear that &drm_device.mode_config.idr_mutex protects the lease idr and list structures for drm_master. The lessor field itself doesn't need to be protected as it doesn't change after it's set in drm_lease_create. 2. Add descriptions for the lifetime of lessors and leases. 3. Add an overview DOC: section in drm-uapi.rst that defines the terminology for drm leasing, and explains how leases work and why they're used. 4. Clean up function documentation in drm_lease.c to use kernel-doc formatting. Signed-off-by: Desmond Cheong Zhi Xi --- Hi, After I updated the formatting for comments in drm_lease.c, I noticed that none of these were driver interfaces (i.e. no structs/inline functions declared in headers, and no exported symbols in .c files). I left the kernel-doc links inside drm-uapi.rst so that if any such interfaces are defined in the future, they'll go to the appropriate place. But if these should be removed, or if the formatting changes for function comments should be removed, please let me know. Best wishes, Desmond Documentation/gpu/drm-uapi.rst | 15 +++ drivers/gpu/drm/drm_lease.c| 182 - include/drm/drm_auth.h | 67 ++-- 3 files changed, 180 insertions(+), 84 deletions(-) diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 7e51dd40bf6e..6d7233a9fb14 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -37,6 +37,21 @@ Primary Nodes, DRM Master and Authentication .. kernel-doc:: include/drm/drm_auth.h :internal: + +.. _drm_leasing: + +DRM Display Resource Leasing + + +.. kernel-doc:: drivers/gpu/drm/drm_lease.c + :doc: drm leasing + +.. kernel-doc:: drivers/gpu/drm/drm_lease.c + :export: + +.. kernel-doc:: include/drm/drm_lease.h + :internal: + Open-Source Userspace Requirements == diff --git a/drivers/gpu/drm/drm_lease.c b/drivers/gpu/drm/drm_lease.c index 92eac73d9001..9b68617840ed 100644 --- a/drivers/gpu/drm/drm_lease.c +++ b/drivers/gpu/drm/drm_lease.c @@ -15,18 +15,67 @@ #include "drm_crtc_internal.h" #include "drm_internal.h" +/** + * DOC: drm leasing + * + * DRM leases provide information about whether a DRM master may control a DRM + * mode setting object. This enables the creation of multiple DRM masters that + * manage subsets of display resources. + * + * The original DRM master of a device 'owns' the available drm resources. It + * may create additional DRM masters and 'lease' resources which it controls + * to the new DRM master. This gives the new DRM master control over the + * leased resources until the owner revokes the lease, or the new DRM master + * is closed. Some helpful terminology: + * + * - An 'owner' is a &struct drm_master that is not leasing objects from + * another &struct drm_master, and hence 'owns' the objects. The owner can be + * identified as the &struct drm_master for which &drm_master.lessor is NULL. + * + * - A 'lessor' is a &struct drm_master which is leasing objects to one or more + * other &struct drm_master. Currently, lessees are not allowed to + * create sub-leases, hence the lessor is the same as the owner. + * + * - A 'lessee' is a &struct drm_master which is leasing objects from some + * other &struct drm_master. Each lessee only leases resources from a single + * lessor recorded in &drm_master.lessor, and holds the set of objects that + * it is leasing in &drm_master.leases. + * + * - A 'lease' is a contract between the lessor and lessee that identifies + * which resources may be controlled by the lessee. All of the resources + * that are leased must be owned by or leased to the lessor, and lessors are + * not permitted to lease the same object to multiple lessees. + * + * The set of objects any &struct drm_master 'controls' is limited to the set + * of objects it leases (for lessees) or all objects (for owners). + * + * Objects not controlled by a &struct drm_master cannot be modified through + * the various state manipulating ioctls, and any state reported back to user + * space will be edited to make them appear idle and/or unusable. For + * instance, connectors always report 'disconnected', while encoders + * report no possible crtcs or clones. + * + * Since each lessee may lease objects from a single lessor, display resource + * leases form a tree of &struct drm_master. As lessees are currently not + * allowed to create sub-leases, the tree depth is limited to 1. All of + * these get activated simultaneously, so &drm_device.master points to the + * owner at the top of the lease tree (i.e. the &struct drm_master for which + * &drm_master.lessor is NULL). The full list of lessees that are leasing + * objects from the
Re: [Intel-gfx] [RFC 6/8] drm: Document fdinfo format specification
On 23/07/2021 18:45, Nieto, David M wrote: [AMD Official Use Only] I just want to make a comment that with this approach (the ns) calculating the percentage will take at least two reads of the fdinfo per pid over some time. Some engines may be able to provide a single shot percentage usage over an internal integration period. That is, for example, what we currently have implemented for that exact reason. I'd like to propose that we add an optional set of fields for this. Yes it is already like that in the text I've sent out. Because I was unclear how the amdgpu accounting works I called out for you guys to fill in the blanks in the last patch: """ Opens: * Does it work for AMD? * What are the semantics of AMD engine utilisation reported in percents? Can it align with what i915 does or needs to document the alternative in the specification document? """ """ -- drm-engine-: ns +- drm-engine-: [ns|%] ... +Where time unit is given as a percentage...[AMD folks to fill the semantics +and interpretation of that]... """ So if cumulative nanoseconds definitely do not work for you, could you please fill in those blanks? Also, I may have missed a message, but why did we remove the timstamp? It is needed for accurate measurements of engine usage. Hm I did not remove anything - I only renamed some of the fields output from amdgpu fdinfo. Regards, Tvrtko David *From:* Daniel Vetter *Sent:* Friday, July 23, 2021 9:47 AM *To:* Daniel Stone *Cc:* Tvrtko Ursulin ; intel-gfx ; Tvrtko Ursulin ; Koenig, Christian ; dri-devel ; Nieto, David M *Subject:* Re: [RFC 6/8] drm: Document fdinfo format specification On Fri, Jul 23, 2021 at 05:43:01PM +0100, Daniel Stone wrote: Hi Tvrtko, Thanks for typing this up! On Thu, 15 Jul 2021 at 10:18, Tvrtko Ursulin wrote: > +Mandatory fully standardised keys > +- > + > +- drm-driver: > + > +String shall contain a fixed string uniquely identified the driver handling > +the device in question. For example name of the respective kernel module. I think let's be more prescriptive and just say that it is the module name. Just a quick comment on this one. drm_driver.name is already uapi, so let's please not invent a new one. The shared code should probably make sure drivers don't get this wrong. Maybe good if we document the getverion ioctl, which also exposes this, and then link between the two. -Daniel > +Optional fully standardised keys > + > + > +- drm-pdev: > + > +For PCI devices this should contain the PCI slot address of the device in > +question. How about just major:minor of the DRM render node device it's attached to? > +- drm-client-id: > + > +Unique value relating to the open DRM file descriptor used to distinguish > +duplicated and shared file descriptors. Conceptually the value should map 1:1 > +to the in kernel representation of `struct drm_file` instances. > + > +Uniqueness of the value shall be either globally unique, or unique within the > +scope of each device, in which case `drm-pdev` shall be present as well. > + > +Userspace should make sure to not double account any usage statistics by using > +the above described criteria in order to associate data to individual clients. > + > +- drm-engine-: ns > + > +GPUs usually contain multiple execution engines. Each shall be given a stable > +and unique name (str), with possible values documented in the driver specific > +documentation. > + > +Value shall be in specified time units which the respective GPU engine spent > +busy executing workloads belonging to this client. > + > +Values are not required to be constantly monotonic if it makes the driver > +implementation easier, but are required to catch up with the previously reported > +larger value within a reasonable period. Upon observing a value lower than what > +was previously read, userspace is expected to stay with that larger previous > +value until a monotonic update is seen. Yeah, that would work well for Mali/Panfrost. We can queue multiple jobs in the hardware, which can either be striped across multiple cores with an affinity mask (e.g. 3 cores for your client and 1 for your compositor), or picked according to priority, or ... The fine-grained performance counters (e.g. time spent waiting for sampler) are only GPU-global. So if you have two jobs running simultaneously, you have no idea who's responsible for what. But it does give us coarse-grained counters which are accounted per-job-slot, including exactly this metric: amount of 'GPU time' (whatever that means) occupied by that job slot during the sampling period. So we could support that nicely if we fenced job-slot updates with register reads/writes. Something I'm missing though is how we enable this information. Seems like it would be best to either only do it whilst fdinfo is open (and re-read it whenever you n
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/3] drm: use the lookup lock in drm_is_current_master
== Series Details == Series: series starting with [v2,1/3] drm: use the lookup lock in drm_is_current_master URL : https://patchwork.freedesktop.org/series/93005/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/drm_drv.c:425:6: warning: context imbalance in 'drm_dev_enter' - different lock contexts for basic block +drivers/gpu/drm/i915/display/intel_display.c:1900:21:expected struct i915_vma *[assigned] vma +drivers/gpu/drm/i915/display/intel_display.c:1900:21:got void [noderef] __iomem *[assigned] iomem +drivers/gpu/drm/i915/display/intel_display.c:1900:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/i915_gem_context.c:1413:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct i915_address_space * +drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct i915_address_space *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct i915_address_space [noderef] __rcu *vm +drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1402:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/i915_perf.c:1443:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1497:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock
[Intel-gfx] ✗ Fi.CI.IGT: failure for MIPI DSI driver enhancements (rev4)
== Series Details ==
Series: MIPI DSI driver enhancements (rev4)
URL : https://patchwork.freedesktop.org/series/92695/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10392_full -> Patchwork_20703_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20703_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20703_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20703_full:
### IGT changes ###
Possible regressions
* igt@perf_pmu@multi-client@vcs0:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-skl9/igt@perf_pmu@multi-cli...@vcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl3/igt@perf_pmu@multi-cli...@vcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
- {shard-rkl}:[SKIP][3] ([i915#3558]) -> [DMESG-WARN][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-5/igt@kms_plane@pixel-format-source-clamp...@pipe-a-planes.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@kms_plane@pixel-format-source-clamp...@pipe-a-planes.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8])
([i915#3002] / [i915#3728] / [i915#3811]) -> ([FAIL][9], [FAIL][10],
[FAIL][11], [FAIL][12]) ([i915#3002] / [i915#3811])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-1/igt@run...@aborted.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-2/igt@run...@aborted.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-2/igt@run...@aborted.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-rkl-6/igt@run...@aborted.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-6/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-2/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-2/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-rkl-5/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20703_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +2
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-snb2/igt@gem_ctx_persiste...@engines-hostile-preempt.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2846])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk5/igt@gem_exec_f...@basic-deadline.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk6/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar
issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb2/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-glk5/igt@gem_exec_fair@basic-none-s...@rcs0.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-glk3/igt@gem_exec_fair@basic-none-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][21] -> [SKIP][22] ([i915#2190])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10392/shard-tglb2/igt@gem_huc_c...@huc-copy.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-tglb6/igt@gem_huc_c...@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][23] ([i915#2658])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20703/shard-skl10/igt@gem_pr...@exhaustion.html
* igt@gem_render_copy@linear-to-ve
Re: [Intel-gfx] [PATCH i-g-t 1/3] lib/intel_memory_region: verify item.length
On 2021-07-08 at 13:25:52 +0100, Matthew Auld wrote: > If the regions query fails then the error will be encoded in the > item.length, while the ioctl will still return success. > > Reported-by: Ville Syrjala > Signed-off-by: Matthew Auld > --- > lib/i915/intel_memory_region.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c > index 144ae12c..e1e210f2 100644 > --- a/lib/i915/intel_memory_region.c > +++ b/lib/i915/intel_memory_region.c > @@ -119,6 +119,13 @@ struct drm_i915_query_memory_regions > *gem_get_query_memory_regions(int fd) > memset(&item, 0, sizeof(item)); > item.query_id = DRM_I915_QUERY_MEMORY_REGIONS; > i915_query_items(fd, &item, 1); > + /* > + * Any DRM_I915_QUERY_MEMORY_REGIONS specific errors are encoded in the > + * item.length, even though the ioctl might still return success. > + */ > + igt_assert_f(item.length > 0, > + "DRM_I915_QUERY_MEMORY_REGIONS failed with %d\n", > + item.length); LGTM. Reviewed-by: Ramalingam C > > query_info = calloc(1, item.length); > > -- > 2.26.3 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm: use the lookup lock in drm_is_current_master
== Series Details ==
Series: series starting with [v2,1/3] drm: use the lookup lock in
drm_is_current_master
URL : https://patchwork.freedesktop.org/series/93005/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10393 -> Patchwork_20704
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/index.html
Known issues
Here are the changes found in Patchwork_20704 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/fi-kbl-soraka/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/fi-kbl-soraka/igt@i915_module_l...@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Participating hosts (42 -> 35)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 bat-adls-4
bat-adls-3 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_10393 -> Patchwork_20704
CI-20190529: 20190529
CI_DRM_10393: c251a707c5b679d62cff229e0e8ee9cf543d3d33 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6149: 34ff2cf2bc352dce691593db803389fe0eb2be03 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20704: 711a8c303ff6edbb76037ea69bc5af68217e5bce @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
711a8c303ff6 drm/vmwgfx: fix potential UAF in vmwgfx_surface.c
3986804d3cd7 drm: clarify usage of drm leases
6397fa00eb03 drm: use the lookup lock in drm_is_current_master
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 28/30] drm/i915: rename/remove CNL registers
On Fri, Jul 23, 2021 at 05:11:12PM -0700, Lucas De Marchi wrote: > Remove registers that are not used anymore due to CNL removal and rename > those that are. > > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/i915_reg.h | 192 ++- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > 2 files changed, 48 insertions(+), 146 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8782d1723254..925cbdb53712 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1877,7 +1877,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) > > /* > - * CNL/ICL Port/COMBO-PHY Registers > + * ICL Port/COMBO-PHY Registers > */ > #define _ICL_COMBOPHY_A 0x162000 > #define _ICL_COMBOPHY_B 0x6C000 > @@ -1891,11 +1891,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > _RKL_COMBOPHY_D, \ > _ADL_COMBOPHY_E) > > -/* CNL/ICL Port CL_DW registers */ > +/* ICL Port CL_DW registers */ > #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ >4 * (dw)) > > -#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) > #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) > #define CL_POWER_DOWN_ENABLE (1 << 4) > #define SUS_CLOCK_CONFIG (3 << 0) > @@ -1920,19 +1919,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define ICL_PORT_CL_DW12(phy)_MMIO(_ICL_PORT_CL_DW(12, phy)) > #define ICL_LANE_ENABLE_AUX(1 << 0) > > -/* CNL/ICL Port COMP_DW registers */ > +/* ICL Port COMP_DW registers */ > #define _ICL_PORT_COMP 0x100 > #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ >_ICL_PORT_COMP + 4 * (dw)) > > -#define CNL_PORT_COMP_DW0_MMIO(0x162100) > #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) > #define COMP_INIT (1 << 31) > > -#define CNL_PORT_COMP_DW1_MMIO(0x162104) > #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) > > -#define CNL_PORT_COMP_DW3_MMIO(0x16210c) > #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) > #define PROCESS_INFO_DOT_0 (0 << 26) > #define PROCESS_INFO_DOT_1 (1 << 26) > @@ -1948,38 +1944,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) > #define IREFGEN(1 << 24) > > -#define CNL_PORT_COMP_DW9_MMIO(0x162124) > #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) > > -#define CNL_PORT_COMP_DW10 _MMIO(0x162128) > #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, > phy)) > > -/* CNL/ICL Port PCS registers */ > -#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 > -#define _CNL_PORT_PCS_DW1_GRP_B 0x162384 > -#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 > -#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 > -#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 > -#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 > -#define _CNL_PORT_PCS_DW1_LN0_B 0x162604 > -#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 > -#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 > -#define _CNL_PORT_PCS_DW1_LN0_F 0x162804 > -#define CNL_PORT_PCS_DW1_GRP(phy)_MMIO(_PICK(phy, \ > - _CNL_PORT_PCS_DW1_GRP_AE, \ > - _CNL_PORT_PCS_DW1_GRP_B, \ > - _CNL_PORT_PCS_DW1_GRP_C, \ > - _CNL_PORT_PCS_DW1_GRP_D, \ > - _CNL_PORT_PCS_DW1_GRP_AE, \ > - _CNL_PORT_PCS_DW1_GRP_F)) > -#define CNL_PORT_PCS_DW1_LN0(phy)_MMIO(_PICK(phy, \ > - _CNL_PORT_PCS_DW1_LN0_AE, \ > - _CNL_PORT_PCS_DW1_LN0_B, \ > - _CNL_PORT_PCS_DW1_LN0_C, \ > - _CNL_PORT_PCS_DW1_LN0_D, \ > - _CNL_PORT_PCS_DW1_LN0_AE, \ > - _CNL_PORT_PCS_DW1_LN0_F)) > - > +/* ICL Port PCS registers */ > #define _ICL_PORT_PCS_AUX0x300 > #define _ICL_PORT_PCS_GRP0x600 > #define _ICL_PORT_PCS_LN(ln)
Re: [Intel-gfx] [PATCH 27/30] drm/i915: remove GRAPHICS_VER == 10
On Fri, Jul 23, 2021 at 05:11:11PM -0700, Lucas De Marchi wrote:
> Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with
> {==,>=} 11. With the removal of CNL, there is no platform with graphics
> version equals 10.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 1 -
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 10 ++---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 --
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 10 ++---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 6 +--
> drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +--
> drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +--
> drivers/gpu/drm/i915/gvt/gtt.c| 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 21 --
> drivers/gpu/drm/i915/intel_device_info.c | 4 +-
> 15 files changed, 37 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 90708de27684..ddd37ccb1362 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct
> intel_memory_region *mem)
> break;
> case 8:
> case 9:
> - case 10:
> if (IS_LP(i915))
> chv_get_stolen_reserved(i915, uncore,
> &reserved_base, &reserved_size);
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index 4270b5a34a83..d6f5836396f8 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void
> *unused)
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 11 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
> seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
> intel_gpu_freq(rps,
> (gpu_freq *
> (IS_GEN9_BC(i915) ||
> - GRAPHICS_VER(i915) >= 10 ?
> + GRAPHICS_VER(i915) >= 11 ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 4168b9fc59e1..152b5493a455 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -35,7 +35,6 @@
> #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
> #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> -#define GE
Re: [Intel-gfx] [PATCH 29/30] drm/i915: replace random CNL comments
On Fri, Jul 23, 2021 at 05:11:13PM -0700, Lucas De Marchi wrote:
> Cleanup remaining cases that we find CNL in the codebase.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 1 -
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 -
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.h | 2 +-
> 6 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 4172c8ee6aa6..e86e6ed2d3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1998,7 +1998,7 @@ static void parse_ddi_port(struct drm_i915_private
> *i915,
> "Port %c VBT HDMI boost level: %d\n",
> port_name(port), hdmi_boost_level);
>
> - /* DP max link rate for CNL+ */
> + /* DP max link rate for GLK+ */
> if (i915->vbt.version >= 216) {
> if (i915->vbt.version >= 230)
> info->dp_max_link_rate =
> parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ee6d5f8de24b..b49bf380baab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9778,7 +9778,7 @@ static int intel_atomic_check_async(struct
> intel_atomic_state *state)
>
> /*
>* FIXME: This check is kept generic for all platforms.
> - * Need to verify this for all gen9 and gen10 platforms to
> enable
> + * Need to verify this for all gen9 platforms to enable
>* this selectively if required.
>*/
> switch (new_plane_state->hw.fb->modifier) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 7c048d2ecf43..f483f479dd0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -158,7 +158,6 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
> /*
>* Max timeout values:
>* SKL-GLK: 1.6ms
> - * CNL: 3.2ms
>* ICL+: 4ms
>*/
> ret = DP_AUX_CH_CTL_SEND_BUSY |
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 7fd031a70cfd..6b19f74efd61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -206,7 +206,6 @@ struct intel_dpll_hw_state {
>
> /* cnl */
> u32 cfgcr0;
> - /* CNL also uses cfgcr1 */
>
> /* bxt */
> u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
> pcsdw12;
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index dbe24d7e7375..330077c2e588 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -456,7 +456,7 @@ struct child_device_config {
> u16 dp_gpio_pin_num;/* 195 */
> u8 dp_iboost_level:4; /* 196 */
> u8 hdmi_iboost_level:4; /* 196 */
> - u8 dp_max_link_rate:3; /* 216/230 CNL+
> */
> + u8 dp_max_link_rate:3; /* 216/230 GLK+
> */
> u8 dp_max_link_rate_reserved:5; /* 216/230 */
> } __packed;
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 057c9aa6f9c6..ef1eecd259e0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -103,7 +103,7 @@ enum intel_platform {
> #define INTEL_SUBPLATFORM_ULT(0)
> #define INTEL_SUBPLATFORM_ULX(1)
>
> -/* CNL/ICL */
> +/* ICL */
> #define INTEL_SUBPLATFORM_PORTF (0)
>
> /* DG2 */
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 17/30] drm/i915/display: rename CNL references in skl_scaler.c
On Fri, Jul 23, 2021 at 05:11:01PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider GLK as the first platform using
> those constants since GLK has DISPLAY_VER == 10.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 10 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 911a113ee006..ebdd3115de16 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -341,12 +341,12 @@ static u16 cnl_nearest_filter_coef(int t)
> *
> */
>
> -static void cnl_program_nearest_filter_coefs(struct drm_i915_private
> *dev_priv,
> +static void glk_program_nearest_filter_coefs(struct drm_i915_private
> *dev_priv,
>enum pipe pipe, int id, int set)
> {
> int i;
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
> PS_COEE_INDEX_AUTO_INC);
>
> for (i = 0; i < 17 * 7; i += 2) {
> @@ -359,11 +359,11 @@ static void cnl_program_nearest_filter_coefs(struct
> drm_i915_private *dev_priv,
> t = cnl_coef_tap(i + 1);
> tmp |= cnl_nearest_filter_coef(t) << 16;
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
> tmp);
> }
>
> - intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
> + intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
> }
>
> static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int
> set)
> @@ -386,7 +386,7 @@ static void skl_scaler_setup_filter(struct
> drm_i915_private *dev_priv, enum pipe
> case DRM_SCALING_FILTER_DEFAULT:
> break;
> case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
> - cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
> + glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
> break;
> default:
> MISSING_CASE(filter);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91e93f3e9649..d198b1a2d4b5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7726,11 +7726,11 @@ enum {
> #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> -#define CNL_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\
> +#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe,\
> _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A)
> + (set) * 8, \
> _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B)
> + (set) * 8)
>
> -#define CNL_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> +#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
> _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) +
> (set) * 8, \
> _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) +
> (set) * 8)
> /* legacy palette */
> --
> 2.31.1
>
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/3] tests/i915_query: extract query_garbage_items
On 2021-07-08 at 13:25:53 +0100, Matthew Auld wrote:
> We should be able to re-use this for other queries.
LGTM
Reviewed-by: Ramalingam C
>
> Signed-off-by: Matthew Auld
> Cc: Ville Syrjala
> ---
> tests/i915/i915_query.c | 46 -
> 1 file changed, 27 insertions(+), 19 deletions(-)
>
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 29b938e9..34965841 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -92,7 +92,8 @@ static void test_query_garbage(int fd)
> i915_query_items_err(fd, &item, 1, EINVAL);
> }
>
> -static void test_query_garbage_items(int fd)
> +static void test_query_garbage_items(int fd, int query_id, int min_item_size,
> + int sizeof_query_item)
> {
> struct drm_i915_query_item items[2];
> struct drm_i915_query_item *items_ptr;
> @@ -103,7 +104,7 @@ static void test_query_garbage_items(int fd)
>* Subject to change in the future.
>*/
> memset(items, 0, sizeof(items));
> - items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items[0].query_id = query_id;
> items[0].flags = 42;
> i915_query_items(fd, items, 1);
> igt_assert_eq(items[0].length, -EINVAL);
> @@ -113,10 +114,10 @@ static void test_query_garbage_items(int fd)
>* one is properly processed.
>*/
> memset(items, 0, sizeof(items));
> - items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items[0].query_id = query_id;
> items[1].query_id = ULONG_MAX;
> i915_query_items(fd, items, 2);
> - igt_assert_lte(MIN_TOPOLOGY_ITEM_SIZE, items[0].length);
> + igt_assert_lte(min_item_size, items[0].length);
> igt_assert_eq(items[1].length, -EINVAL);
>
> /*
> @@ -126,16 +127,16 @@ static void test_query_garbage_items(int fd)
>*/
> memset(items, 0, sizeof(items));
> items[0].query_id = ULONG_MAX;
> - items[1].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items[1].query_id = query_id;
> i915_query_items(fd, items, 2);
> igt_assert_eq(items[0].length, -EINVAL);
> - igt_assert_lte(MIN_TOPOLOGY_ITEM_SIZE, items[1].length);
> + igt_assert_lte(min_item_size, items[1].length);
>
> /* Test a couple of invalid data pointer in query item. */
> memset(items, 0, sizeof(items));
> - items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items[0].query_id = query_id;
> i915_query_items(fd, items, 1);
> - igt_assert_lte(MIN_TOPOLOGY_ITEM_SIZE, items[0].length);
> + igt_assert_lte(min_item_size, items[0].length);
>
> items[0].data_ptr = 0;
> i915_query_items(fd, items, 1);
> @@ -145,14 +146,13 @@ static void test_query_garbage_items(int fd)
> i915_query_items(fd, items, 1);
> igt_assert_eq(items[0].length, -EFAULT);
>
> -
> /* Test an invalid query item length. */
> memset(items, 0, sizeof(items));
> - items[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> - items[1].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> - items[1].length = sizeof(struct drm_i915_query_topology_info) - 1;
> + items[0].query_id = query_id;
> + items[1].query_id = query_id;
> + items[1].length = sizeof_query_item - 1;
> i915_query_items(fd, items, 2);
> - igt_assert_lte(MIN_TOPOLOGY_ITEM_SIZE, items[0].length);
> + igt_assert_lte(min_item_size, items[0].length);
> igt_assert_eq(items[1].length, -EINVAL);
>
> /*
> @@ -162,9 +162,9 @@ static void test_query_garbage_items(int fd)
>* has been removed from our address space.
>*/
> items_ptr = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
> - items_ptr[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items_ptr[0].query_id = query_id;
> i915_query_items(fd, items_ptr, 1);
> - igt_assert_lte(MIN_TOPOLOGY_ITEM_SIZE, items_ptr[0].length);
> + igt_assert_lte(min_item_size, items_ptr[0].length);
> munmap(items_ptr, 4096);
> i915_query_items_err(fd, items_ptr, 1, EFAULT);
>
> @@ -173,7 +173,7 @@ static void test_query_garbage_items(int fd)
>* the kernel errors out with EFAULT.
>*/
> items_ptr = mmap(0, 4096, PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
> - items_ptr[0].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items_ptr[0].query_id = query_id;
> igt_assert_eq(0, mprotect(items_ptr, 4096, PROT_READ));
> i915_query_items_err(fd, items_ptr, 1, EFAULT);
> munmap(items_ptr, 4096);
> @@ -186,12 +186,20 @@ static void test_query_garbage_items(int fd)
> memset(items_ptr, 0, 8192);
> n_items = 8192 / sizeof(struct drm_i915_query_item);
> for (i = 0; i < n_items; i++)
> - items_ptr[i].query_id = DRM_I915_QUERY_TOPOLOGY_INFO;
> + items_ptr[i].query_id = query_id;
> mprotect(((uint8_t *)items_ptr) + 4096, 4096, PROT_READ);
> i915_query_items_err(fd, items_ptr, n_items, EFAULT);
>
Re: [Intel-gfx] [PATCH 30/30] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
On Fri, Jul 23, 2021 at 05:11:14PM -0700, Lucas De Marchi wrote:
> The numbers of scalers and sprites depend on the display version, so use
> it instead of GRAPHICS_VER. We were mixing both, which let me confused
> while removing CNL and GRAPHICS_VER == 10.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index ffe3b5d89a63..7023d36a9a28 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -265,10 +265,10 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
> for_each_pipe(dev_priv, pipe)
> runtime->num_scalers[pipe] = 0;
> - else if (GRAPHICS_VER(dev_priv) >= 11) {
> + else if (DISPLAY_VER(dev_priv) >= 11) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_scalers[pipe] = 2;
> - } else if (GRAPHICS_VER(dev_priv) == 9) {
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> runtime->num_scalers[PIPE_A] = 2;
> runtime->num_scalers[PIPE_B] = 2;
> runtime->num_scalers[PIPE_C] = 1;
> @@ -279,7 +279,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 4;
> - else if (GRAPHICS_VER(dev_priv) >= 11)
> + else if (DISPLAY_VER(dev_priv) >= 11)
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 6;
> else if (IS_GEMINILAKE(dev_priv))
while at it we could probably change this to DISPLAY_VER == 10?!
but anyway:
Reviewed-by: Rodrigo Vivi
> @@ -301,7 +301,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 2;
> - } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> + } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 1;
> }
> --
> 2.31.1
>
> ___
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Re: [Intel-gfx] [PATCH 21/30] drm/i915: remove explicit CNL handling from intel_pch.c
On Fri, Jul 23, 2021 at 05:11:05PM -0700, Lucas De Marchi wrote: > Remove references for CNL from pch detection. for a moment I almost thought you were removing the CNP support... > > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/intel_pch.c | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pch.c > b/drivers/gpu/drm/i915/intel_pch.c > index cc44164e242b..d1d4b97b86f5 100644 > --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -81,7 +81,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, > unsigned short id) > case INTEL_PCH_CNP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_CANNONLAKE(dev_priv) && > !IS_COFFEELAKE(dev_priv) && > !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > @@ -89,7 +88,6 @@ intel_pch_type(const struct drm_i915_private *dev_priv, > unsigned short id) > drm_dbg_kms(&dev_priv->drm, > "Found Cannon Lake LP PCH (CNP-LP)\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_CANNONLAKE(dev_priv) && > !IS_COFFEELAKE(dev_priv) && > !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > @@ -171,8 +169,7 @@ intel_virt_detect_pch(const struct drm_i915_private > *dev_priv, > id = INTEL_PCH_MCC_DEVICE_ID_TYPE; > else if (IS_ICELAKE(dev_priv)) > id = INTEL_PCH_ICP_DEVICE_ID_TYPE; > - else if (IS_CANNONLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv) || > + else if (IS_COFFEELAKE(dev_priv) || >IS_COMETLAKE(dev_priv)) > id = INTEL_PCH_CNP_DEVICE_ID_TYPE; > else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) > -- > 2.31.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
On Sat, Jul 24, 2021 at 10:02:15PM -0700, Lucas De Marchi wrote: > On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote: > > Still tests fine: > > > > Tested-by: Christoph Hellwig > > I just pushed this to drm-intel-next as part of another series and > added your Tested-by. > > Rodrigo, can you pick this up for -fixes? This should go with your other > patch to fix the port mask, too. done. But while doing this and reviewing this series at the same time I got myself wondering if we shouldn't remove the PORT_F support entirely... > > Thanks for the bug report and test. > > Lucas De Marchi > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 26/30] drm/i915: finish removal of CNL
On Fri, Jul 23, 2021 at 05:11:10PM -0700, Lucas De Marchi wrote:
> With all the users removed, finish removing the CNL platform definitions.
> We will leave the PCI IDs around as those are exposed to userspace.
> Even if mesa doesn't support CNL anymore, let's avoid build breakages
> due to changing the headers.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 +--
> drivers/gpu/drm/i915/i915_pci.c | 23 +--
> drivers/gpu/drm/i915/i915_perf.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.c | 2 --
> drivers/gpu/drm/i915/intel_device_info.h | 2 --
> 5 files changed, 6 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd2d196050d4..e3c8283d770c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1437,7 +1437,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
> #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> -#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
> IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> @@ -1503,8 +1502,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
>INTEL_INFO(dev_priv)->gt == 2)
>
> -#define IS_CNL_WITH_PORT_F(dev_priv) \
> - IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
> #define IS_ICL_WITH_PORT_F(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
>
> @@ -1649,9 +1646,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> /* WaRsDisableCoarsePowerGating:skl,cnl */
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> - (IS_CANNONLAKE(dev_priv) || \
> - IS_SKL_GT3(dev_priv) ||\
> - IS_SKL_GT4(dev_priv))
> + (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 48ea23dd3b5b..aea2c2d82fbf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -787,27 +787,13 @@ static const struct intel_device_info cml_gt2_info = {
> .gt = 2,
> };
>
> -#define GEN10_FEATURES \
> - GEN9_FEATURES, \
> - GEN(10), \
> - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
> - .display.has_dsc = 1, \
> - .has_coherent_ggtt = false, \
> - GLK_COLORS
> -
> -static const struct intel_device_info cnl_info = {
> - GEN10_FEATURES,
> - PLATFORM(INTEL_CANNONLAKE),
> - .gt = 2,
> -};
> -
> #define GEN11_DEFAULT_PAGE_SIZES \
> .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> I915_GTT_PAGE_SIZE_64K | \
> I915_GTT_PAGE_SIZE_2M
>
> #define GEN11_FEATURES \
> - GEN10_FEATURES, \
> + GEN9_FEATURES, \
> GEN11_DEFAULT_PAGE_SIZES, \
> .abox_mask = BIT(0), \
> .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> @@ -830,10 +816,12 @@ static const struct intel_device_info cnl_info = {
> [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
> }, \
> GEN(11), \
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
> .dbuf.size = 2048, \
> .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
> - .has_logical_ring_elsq = 1, \
> - .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
> + .display.has_dsc = 1, \
> + .has_coherent_ggtt = false, \
> + .has_logical_ring_elsq = 1
>
> static const struct intel_device_info icl_info = {
> GEN11_FEATURES,
> @@ -1123,7 +,6 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CML_GT2_IDS(&cml_gt2_info),
> INTEL_CML_U_GT1_IDS(&cml_gt1_info),
> INTEL_CML_U_GT2_IDS(&cml_gt2_info),
> - INTEL_CNL_IDS(&cnl_info),
> INTEL_ICL_11_IDS(&icl_info),
> INTEL_EHL_IDS(&ehl_info),
> INTEL_JSL_IDS(&jsl_info),
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 838cc14c2f24..108774d651d9 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4319,7 +4319,6 @@ static void oa_init_supported_formats(struct i915_perf
> *perf)
> case INTEL_GEMINILAKE:
> case INTEL_COFFEELAKE:
> ca
Re: [Intel-gfx] [PATCH 20/30] drm/i915: remove explicit CNL handling from intel_mocs.c
On Fri, Jul 23, 2021 at 05:11:04PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> GEN9_BC, so leave the code around and just remove the special
> case for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 17848807f111..582c4423b95d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -352,7 +352,7 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> table->size = ARRAY_SIZE(icl_mocs_table);
> table->table = icl_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> + } else if (IS_GEN9_BC(i915)) {
> table->size = ARRAY_SIZE(skl_mocs_table);
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> table->table = skl_mocs_table;
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 14/30] drm/i915/display: remove explicit CNL handling from skl_universal_plane.c
On Fri, Jul 23, 2021 at 05:10:58PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in skl_universal_plane.c.
>
> Remove code and rename functions/macros accordingly to use ICL prefix.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 3ad04bf2a0fd..0f40f8b07724 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -835,7 +835,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate)
> return 0;
> }
>
> -static u32 cnl_plane_ctl_flip(unsigned int reflect)
> +static u32 icl_plane_ctl_flip(unsigned int reflect)
> {
> switch (reflect) {
> case 0:
> @@ -917,8 +917,8 @@ static u32 skl_plane_ctl(const struct intel_crtc_state
> *crtc_state,
> plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
> plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> - plane_ctl |= cnl_plane_ctl_flip(rotation &
> + if (DISPLAY_VER(dev_priv) >= 11)
> + plane_ctl |= icl_plane_ctl_flip(rotation &
> DRM_MODE_REFLECT_MASK);
>
> if (key->flags & I915_SET_COLORKEY_DESTINATION)
> @@ -1828,7 +1828,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private
> *dev_priv,
> if (plane_id == PLANE_CURSOR)
> return false;
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> return true;
>
> if (IS_GEMINILAKE(dev_priv))
> @@ -2144,7 +2144,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> supported_rotations |= DRM_MODE_REFLECT_X;
>
> drm_plane_create_rotation_property(&plane->base,
> @@ -2174,7 +2174,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> if (DISPLAY_VER(dev_priv) >= 12)
> drm_plane_enable_fb_damage_clips(&plane->base);
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11)
> drm_plane_create_scaling_filter_property(&plane->base,
> BIT(DRM_SCALING_FILTER_DEFAULT)
> |
>
> BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
> @@ -2295,7 +2295,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> break;
> }
>
> - if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) && val &
> PLANE_CTL_FLIP_HORIZONTAL)
> + if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
> plane_config->rotation |= DRM_MODE_REFLECT_X;
>
> /* 90/270 degree rotation would require extra work */
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 24/30] drm/i915: rename CNL references in intel_dram.c
On Fri, Jul 23, 2021 at 05:11:08PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider ICL as the first platform using
> those constants.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 24 +++
> drivers/gpu/drm/i915/intel_dram.c | 32 +++
> 2 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f032a4c8b26d..8782d1723254 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11082,18 +11082,18 @@ enum skl_power_gate {
> #define SKL_DRAM_RANK_1 (0x0 << 10)
> #define SKL_DRAM_RANK_2 (0x1 << 10)
> #define SKL_DRAM_RANK_MASK (0x1 << 10)
> -#define CNL_DRAM_SIZE_MASK 0x7F
> -#define CNL_DRAM_WIDTH_MASK (0x3 << 7)
> -#define CNL_DRAM_WIDTH_SHIFT7
> -#define CNL_DRAM_WIDTH_X8 (0x0 << 7)
> -#define CNL_DRAM_WIDTH_X16 (0x1 << 7)
> -#define CNL_DRAM_WIDTH_X32 (0x2 << 7)
> -#define CNL_DRAM_RANK_MASK (0x3 << 9)
> -#define CNL_DRAM_RANK_SHIFT 9
> -#define CNL_DRAM_RANK_1 (0x0 << 9)
> -#define CNL_DRAM_RANK_2 (0x1 << 9)
> -#define CNL_DRAM_RANK_3 (0x2 << 9)
> -#define CNL_DRAM_RANK_4 (0x3 << 9)
> +#define ICL_DRAM_SIZE_MASK 0x7F
> +#define ICL_DRAM_WIDTH_MASK (0x3 << 7)
> +#define ICL_DRAM_WIDTH_SHIFT7
> +#define ICL_DRAM_WIDTH_X8 (0x0 << 7)
> +#define ICL_DRAM_WIDTH_X16 (0x1 << 7)
> +#define ICL_DRAM_WIDTH_X32 (0x2 << 7)
> +#define ICL_DRAM_RANK_MASK (0x3 << 9)
> +#define ICL_DRAM_RANK_SHIFT 9
> +#define ICL_DRAM_RANK_1 (0x0 << 9)
> +#define ICL_DRAM_RANK_2 (0x1 << 9)
> +#define ICL_DRAM_RANK_3 (0x2 << 9)
> +#define ICL_DRAM_RANK_4 (0x3 << 9)
>
> #define SA_PERF_STATUS_0_0_0_MCHBAR_PC
> _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 9675bb94b70b..34d6cf440352 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -77,21 +77,21 @@ static int skl_get_dimm_ranks(u16 val)
> }
>
> /* Returns total Gb for the whole DIMM */
> -static int cnl_get_dimm_size(u16 val)
> +static int icl_get_dimm_size(u16 val)
> {
> - return (val & CNL_DRAM_SIZE_MASK) * 8 / 2;
> + return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
> }
>
> -static int cnl_get_dimm_width(u16 val)
> +static int icl_get_dimm_width(u16 val)
> {
> - if (cnl_get_dimm_size(val) == 0)
> + if (icl_get_dimm_size(val) == 0)
> return 0;
>
> - switch (val & CNL_DRAM_WIDTH_MASK) {
> - case CNL_DRAM_WIDTH_X8:
> - case CNL_DRAM_WIDTH_X16:
> - case CNL_DRAM_WIDTH_X32:
> - val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
> + switch (val & ICL_DRAM_WIDTH_MASK) {
> + case ICL_DRAM_WIDTH_X8:
> + case ICL_DRAM_WIDTH_X16:
> + case ICL_DRAM_WIDTH_X32:
> + val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
> return 8 << val;
> default:
> MISSING_CASE(val);
> @@ -99,12 +99,12 @@ static int cnl_get_dimm_width(u16 val)
> }
> }
>
> -static int cnl_get_dimm_ranks(u16 val)
> +static int icl_get_dimm_ranks(u16 val)
> {
> - if (cnl_get_dimm_size(val) == 0)
> + if (icl_get_dimm_size(val) == 0)
> return 0;
>
> - val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
> + val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
>
> return val + 1;
> }
> @@ -121,10 +121,10 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
> struct dram_dimm_info *dimm,
> int channel, char dimm_name, u16 val)
> {
> - if (GRAPHICS_VER(i915) >= 10) {
> - dimm->size = cnl_get_dimm_size(val);
> - dimm->width = cnl_get_dimm_width(val);
> - dimm->ranks = cnl_get_dimm_ranks(val);
> + if (GRAPHICS_VER(i915) >= 11) {
> + dimm->size = icl_get_dimm_size(val);
> + dimm->width = icl_get_dimm_width(val);
> + dimm->ranks = icl_get_dimm_ranks(val);
> } else {
> dimm->size = skl_get_dimm_size(val);
> dimm->width = skl_get_dimm_width(val);
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 15/30] drm/i915/display: remove explicit CNL handling from intel_display_power.c
On Fri, Jul 23, 2021 at 05:10:59PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_display_power.c.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> .../drm/i915/display/intel_display_power.c| 289 --
> .../drm/i915/display/intel_display_power.h| 2 -
> drivers/gpu/drm/i915/i915_reg.h | 13 -
> 3 files changed, 304 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 81efc77bada0..44aef0c44ab7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -447,17 +447,6 @@ static void hsw_power_well_enable(struct
> drm_i915_private *dev_priv,
>
> hsw_wait_for_power_well_enable(dev_priv, power_well, false);
>
> - /* Display WA #1178: cnl */
> - if (IS_CANNONLAKE(dev_priv) &&
> - pw_idx >= GLK_PW_CTL_IDX_AUX_B &&
> - pw_idx <= CNL_PW_CTL_IDX_AUX_F) {
> - u32 val;
> -
> - val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx));
> - val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> - intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val);
> - }
> -
> if (power_well->desc->hsw.has_fuses) {
> enum skl_power_gate pg;
>
> @@ -2743,63 +2732,6 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_GMBUS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
> -#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) |\
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_A_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) |\
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_B_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_C_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_D_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_AUX_F_POWER_DOMAINS (\
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DDI_F_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> /*
> * ICL PW_0/PG_0 domains (HW/DMC control):
> * - PCI
> @@ -3706,148 +3638,6 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> },
> };
>
> -static const struct i915_power_well_desc cnl_power_wells[] = {
> - {
> - .name = "alway
Re: [Intel-gfx] [PATCH 12/30] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
On Fri, Jul 23, 2021 at 05:10:56PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_ddi.c.
>
> A lot of special code for CNL can be removed. There were some
> __cnl.*() functions that were created to share the implementation
> between ICL and CNL. Those are now embedded in the only caller, in ICL.
>
> Remove code and rename functions/macros accordingly to use ICL prefix
> for those that are still needed.
>
> Verified with:
>
> make EXTRA_CFLAGS=-Wunused drivers/gpu/drm/i915/display/intel_dpll_mgr.o
good idea...
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 586 +++---
> drivers/gpu/drm/i915/i915_reg.h | 4 +-
> 2 files changed, 96 insertions(+), 494 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8e2bd8fa090a..0d72917e5670 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -168,7 +168,7 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
> else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
> return MG_PLL_ENABLE(0);
>
> - return CNL_DPLL_ENABLE(pll->info->id);
> + return ICL_DPLL_ENABLE(pll->info->id);
> }
>
> static i915_reg_t
> @@ -2346,160 +2346,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
> .dump_hw_state = bxt_dump_hw_state,
> };
>
> -static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
> -struct intel_shared_dpll *pll)
> -{
> - const enum intel_dpll_id id = pll->info->id;
> - u32 val;
> -
> - /* 1. Enable DPLL power in DPLL_ENABLE. */
> - val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> - val |= PLL_POWER_ENABLE;
> - intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> - /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
> - if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
> - PLL_POWER_STATE, 5))
> - drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);
> -
> - /*
> - * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
> - * select DP mode, and set DP link rate.
> - */
> - val = pll->state.hw_state.cfgcr0;
> - intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val);
> -
> - /* 4. Reab back to ensure writes completed */
> - intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id));
> -
> - /* 3. Configure DPLL_CFGCR0 */
> - /* Avoid touch CFGCR1 if HDMI mode is not enabled */
> - if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
> - val = pll->state.hw_state.cfgcr1;
> - intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val);
> - /* 4. Reab back to ensure writes completed */
> - intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id));
> - }
> -
> - /*
> - * 5. If the frequency will result in a change to the voltage
> - * requirement, follow the Display Voltage Frequency Switching
> - * Sequence Before Frequency Change
> - *
> - * Note: DVFS is actually handled via the cdclk code paths,
> - * hence we do nothing here.
> - */
> -
> - /* 6. Enable DPLL in DPLL_ENABLE. */
> - val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id));
> - val |= PLL_ENABLE;
> - intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val);
> -
> - /* 7. Wait for PLL lock status in DPLL_ENABLE. */
> - if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
> - drm_err(&dev_priv->drm, "PLL %d not locked\n", id);
> -
> - /*
> - * 8. If the frequency will result in a change to the voltage
> - * requirement, follow the Display Voltage Frequency Switching
> - * Sequence After Frequency Change
> - *
> - * Note: DVFS is actually handled via the cdclk code paths,
> - * hence we do nothing here.
> - */
> -
> - /*
> - * 9. turn on the clock for the DDI and map the DPLL to the DDI
> - * Done at intel_ddi_clk_select
> - */
> -}
> -
> -static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll *pll)
> -{
> - const enum intel_dpll_id id = pll->info->id;
> - u32 val;
> -
> - /*
> - * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
> - * Done at intel_ddi_post_disable
> - */
> -
> - /*
> - * 2. If the frequency will result in a change to the voltage
> - * requirement, follow the Display Voltage Frequency Switching
> - * Sequence Before Frequency Change
> - *
> - * Note: DVFS is actually handled via the cdclk code paths,
> - * hence we do nothing here.
> - */
> -
> - /* 3. Disable DPLL through DPLL_ENA
Re: [Intel-gfx] [PATCH 25/30] drm/i915/gt: rename CNL references in intel_engine.h
On Fri, Jul 23, 2021 at 05:11:09PM -0700, Lucas De Marchi wrote:
> With the removal of CNL, let's consider ICL as the first platform using
> that index.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
(
I got myself thinking that some patches like this could be squashed into others,
and a few of them made with coccinele, but in the end I like the approach you
took. It's been very easy to review this series...
)
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
> drivers/gpu/drm/i915/i915_drv.h| 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index f911c1224ab2..dfb400766db5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -179,7 +179,7 @@ intel_write_status_page(struct intel_engine_cs *engine,
> int reg, u32 value)
>
> #define I915_HWS_CSB_BUF0_INDEX 0x10
> #define I915_HWS_CSB_WRITE_INDEX 0x1f
> -#define CNL_HWS_CSB_WRITE_INDEX 0x2f
> +#define ICL_HWS_CSB_WRITE_INDEX 0x2f
>
> void intel_engine_stop(struct intel_engine_cs *engine);
> void intel_engine_cleanup(struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d118834a4ed9..dd2d196050d4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1959,8 +1959,8 @@ int remap_io_sg(struct vm_area_struct *vma,
>
> static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
> {
> - if (GRAPHICS_VER(i915) >= 10)
> - return CNL_HWS_CSB_WRITE_INDEX;
> + if (GRAPHICS_VER(i915) >= 11)
> + return ICL_HWS_CSB_WRITE_INDEX;
> else
> return I915_HWS_CSB_WRITE_INDEX;
> }
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 11/30] drm/i915/display: remove explicit CNL handling from intel_dp.c
On Fri, Jul 23, 2021 at 05:10:55PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_dp.c.
>
> Remove code and rename functions/macros accordingly to use ICL prefix.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 35 -
> 1 file changed, 5 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c386ef8eb200..db701ec5a221 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -222,29 +222,6 @@ bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
>encoder->port != PORT_A);
> }
>
> -static int cnl_max_source_rate(struct intel_dp *intel_dp)
> -{
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum port port = dig_port->base.port;
> -
> - u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) &
> VOLTAGE_INFO_MASK;
> -
> - /* Low voltage SKUs are limited to max of 5.4G */
> - if (voltage == VOLTAGE_INFO_0_85V)
> - return 54;
> -
> - /* For this SKU 8.1G is supported in all ports */
> - if (IS_CNL_WITH_PORT_F(dev_priv))
> - return 81;
> -
> - /* For other SKUs, max rate on ports A and D is 5.4G */
> - if (port == PORT_A || port == PORT_D)
> - return 54;
> -
> - return 81;
> -}
> -
> static int icl_max_source_rate(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -270,7 +247,7 @@ static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> /* The values must be in increasing order */
> - static const int cnl_rates[] = {
> + static const int icl_rates[] = {
> 162000, 216000, 27, 324000, 432000, 54, 648000, 81
> };
> static const int bxt_rates[] = {
> @@ -295,12 +272,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> drm_WARN_ON(&dev_priv->drm,
> intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> - source_rates = cnl_rates;
> - size = ARRAY_SIZE(cnl_rates);
> - if (DISPLAY_VER(dev_priv) == 10)
> - max_rate = cnl_max_source_rate(intel_dp);
> - else if (IS_JSL_EHL(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 11) {
> + source_rates = icl_rates;
> + size = ARRAY_SIZE(icl_rates);
> + if (IS_JSL_EHL(dev_priv))
> max_rate = ehl_max_source_rate(intel_dp);
> else
> max_rate = icl_max_source_rate(intel_dp);
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 16/30] drm/i915/display: remove CNL ddi buf translation tables
On Fri, Jul 23, 2021 at 05:11:00PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 12 +-
> .../drm/i915/display/intel_ddi_buf_trans.c| 616 +-
> .../drm/i915/display/intel_ddi_buf_trans.h| 4 +-
> 3 files changed, 184 insertions(+), 448 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8367462842fa..e5cfb606dd30 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1055,8 +1055,8 @@ static void icl_ddi_combo_vswing_program(struct
> intel_encoder *encoder,
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>RCOMP_SCALAR_MASK);
> - val |=
> SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> - val |=
> SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> + val |=
> SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
> + val |=
> SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> val |= RCOMP_SCALAR(0x98);
> intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
> @@ -1067,16 +1067,16 @@ static void icl_ddi_combo_vswing_program(struct
> intel_encoder *encoder,
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>CURSOR_COEFF_MASK);
> - val |=
> POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
> - val |=
> POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
> - val |=
> CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
> + val |=
> POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
> + val |=
> POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
> + val |=
> CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
> intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
> }
>
> /* Program PORT_TX_DW7 */
> val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
> val &= ~N_SCALAR_MASK;
> - val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
> + val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
> intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 63b1ae830d9a..9ab95bcd0c86 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -417,199 +417,19 @@ static const struct intel_ddi_buf_trans
> bxt_ddi_translations_hdmi = {
> .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1,
> };
>
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const union intel_ddi_buf_trans_entry
> _cnl_ddi_translations_dp_0_85V[] = {
> - /* NT mV Trans mV db
> */
> - { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0
> */
> - { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1
> */
> - { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0
> */
> - { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2
> */
> - { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0
> */
> - { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9
> */
> - { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1
> */
> - { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9
> */
> - { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5
> */
> - { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0
> */
> -};
> -
> -static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = {
> - .entries = _cnl_ddi_translations_dp_0_85V,
> - .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V),
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for HDMI */
> -static const union intel_ddi_buf_trans_entry
> _cnl_ddi_translations_hdmi_0_85V[] = {
> - /* NT mV Trans mV db
> */
> - { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0
> */
> - { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2
> */
> - { .c
Re: [Intel-gfx] [PATCH 22/30] drm/i915: remove explicit CNL handling from intel_wopcm.c
On Fri, Jul 23, 2021 at 05:11:06PM -0700, Lucas De Marchi wrote:
> Consider the new WOPCM size as starting in ICL rather than CNL since the
> latter is being removed from the driver.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_wopcm.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index 8309455f13ea..5e511bb891f9 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -56,8 +56,8 @@
>
> /* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
> #define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K)
> -/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
> -#define CNL_WOPCM_HW_CTX_RESERVED(SZ_32K + SZ_4K)
> +/* 36KB WOPCM reserved at the end of WOPCM on ICL. */
> +#define ICL_WOPCM_HW_CTX_RESERVED(SZ_32K + SZ_4K)
>
> /* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
> #define GEN9_GUC_FW_RESERVED SZ_128K
> @@ -93,8 +93,8 @@ static u32 context_reserved_size(struct drm_i915_private
> *i915)
> {
> if (IS_GEN9_LP(i915))
> return BXT_WOPCM_RC6_CTX_RESERVED;
> - else if (GRAPHICS_VER(i915) >= 10)
> - return CNL_WOPCM_HW_CTX_RESERVED;
> + else if (GRAPHICS_VER(i915) >= 11)
> + return ICL_WOPCM_HW_CTX_RESERVED;
> else
> return 0;
> }
> @@ -126,7 +126,7 @@ static bool gen9_check_huc_fw_fits(struct
> drm_i915_private *i915,
> u32 guc_wopcm_size, u32 huc_fw_size)
> {
> /*
> - * On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
> + * On Gen9, hardware requires the total available GuC WOPCM
>* size to be larger than or equal to HuC firmware size. Otherwise,
>* firmware uploading would fail.
>*/
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 18/30] drm/i915: remove explicit CNL handling from i915_irq.c
On Fri, Jul 23, 2021 at 05:11:02PM -0700, Lucas De Marchi wrote:
> Remove special handling of PORT_F in i915_irq.c and only do it for
> DISPLAY_VER == 11.
oh! ignore my previous thought about removing the port F...
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 +++
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2171bd2820e..17d336218b67 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
> GEN9_AUX_CHANNEL_C |
> GEN9_AUX_CHANNEL_D;
>
> - if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
> - mask |= CNL_AUX_CHANNEL_F;
> -
> - if (DISPLAY_VER(dev_priv) == 11)
> + if (DISPLAY_VER(dev_priv) == 11) {
> + mask |= ICL_AUX_CHANNEL_F;
> mask |= ICL_AUX_CHANNEL_E;
> + }
>
> return mask;
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d198b1a2d4b5..fdc8fd424d36 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7945,7 +7945,7 @@ enum {
> #define DSI1_NON_TE (1 << 31)
> #define DSI0_NON_TE (1 << 30)
> #define ICL_AUX_CHANNEL_E (1 << 29)
> -#define CNL_AUX_CHANNEL_F (1 << 28)
> +#define ICL_AUX_CHANNEL_F (1 << 28)
> #define GEN9_AUX_CHANNEL_D (1 << 27)
> #define GEN9_AUX_CHANNEL_C (1 << 26)
> #define GEN9_AUX_CHANNEL_B (1 << 25)
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 08/30] drm/i915/display: remove explicit CNL handling from intel_ddi.c
On Fri, Jul 23, 2021 at 05:10:52PM -0700, Lucas De Marchi wrote:
> The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
> handle CNL explicitly in intel_ddi.c.
>
> Remove code and rename functions/macros accordingly to use ICL prefix.
> There's one leftover reference to cnl that comes from the struct
> intel_ddi_buf_trans. This will be renamed later when we get rid of the
> additional CNL tables.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 254 ++-
> 1 file changed, 20 insertions(+), 234 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 26a3aa73fcc4..8367462842fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -822,7 +822,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
> static enum intel_display_power_domain
> intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
> {
> - /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
> + /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
>* DC states enabled at the same time, while for driver initiated AUX
>* transfers we need the same AUX IOs to be powered but with DC states
>* disabled. Accordingly use the AUX power domain here which leaves DC
> @@ -1017,126 +1017,6 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp
> *intel_dp)
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> }
>
> -static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
> -const struct intel_crtc_state *crtc_state,
> -int level)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - const struct intel_ddi_buf_trans *ddi_translations;
> - enum port port = encoder->port;
> - int n_entries, ln;
> - u32 val;
> -
> - ddi_translations = encoder->get_buf_trans(encoder, crtc_state,
> &n_entries);
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
> - return;
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
> - level = n_entries - 1;
> -
> - /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
> - val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> - val &= ~SCALING_MODE_SEL_MASK;
> - val |= SCALING_MODE_SEL(2);
> - intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW2 */
> - val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
> - val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> - RCOMP_SCALAR_MASK);
> - val |=
> SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> - val |=
> SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
> - /* Rcomp scalar is fixed as 0x98 for every table entry */
> - val |= RCOMP_SCALAR(0x98);
> - intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
> -
> - /* Program PORT_TX_DW4 */
> - /* We cannot write to GRP. It would overrite individual loadgen */
> - for (ln = 0; ln < 4; ln++) {
> - val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
> - val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> - CURSOR_COEFF_MASK);
> - val |=
> POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
> - val |=
> POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
> - val |=
> CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
> - intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
> - }
> -
> - /* Program PORT_TX_DW5 */
> - /* All DW5 values are fixed for every table entry */
> - val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
> - val &= ~RTERM_SELECT_MASK;
> - val |= RTERM_SELECT(6);
> - val |= TAP3_DISABLE;
> - intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW7 */
> - val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
> - val &= ~N_SCALAR_MASK;
> - val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
> - intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
> -}
> -
> -static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> - const struct intel_crtc_state *crtc_state,
> - int level)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> - int width, rate, ln;
> - u32 val;
> -
> - width = crtc_state->lane_count;
> - rate = crtc_state->port_clock;
> -
> - /*
> - * 1. If port type is eDP or DP,
> - * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> -
Re: [Intel-gfx] [PATCH 13/30] drm/i915/display: remove explicit CNL handling from intel_vdsc.c
On Fri, Jul 23, 2021 at 05:10:57PM -0700, Lucas De Marchi wrote: > Only one reference to CNL that is not needed, but code is the same for > DISPLAY_VER >= 11, so leave the code around and just remove the special > case for CNL. > > Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 85749370508c..df3286aa6999 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -348,7 +348,10 @@ bool intel_dsc_source_support(const struct > intel_crtc_state *crtc_state) > if (DISPLAY_VER(i915) >= 12) > return true; > > - if ((DISPLAY_VER(i915) >= 11 || IS_CANNONLAKE(i915)) && (pipe != PIPE_A > || (cpu_transcoder == TRANSCODER_EDP || cpu_transcoder == TRANSCODER_DSI_0 || > cpu_transcoder == TRANSCODER_DSI_1))) > + if (DISPLAY_VER(i915) >= 11 && > + (pipe != PIPE_A || cpu_transcoder == TRANSCODER_EDP || > + cpu_transcoder == TRANSCODER_DSI_0 || > + cpu_transcoder == TRANSCODER_DSI_1)) > return true; > > return false; > -- > 2.31.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/30] drm/i915/display: remove explicit CNL handling from intel_dmc.c
On Fri, Jul 23, 2021 at 05:10:54PM -0700, Lucas De Marchi wrote:
> Remove DMC firmware for CNL.
>
> Signed-off-by: Lucas De Marchi
Cc: Anusha Srivatsa
We need to remove the binary from linux-firmware.git as well
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 9895fd957df9..3c3c6cb5c0df 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -70,11 +70,6 @@ MODULE_FIRMWARE(TGL_DMC_PATH);
> #define ICL_DMC_MAX_FW_SIZE 0x6000
> MODULE_FIRMWARE(ICL_DMC_PATH);
>
> -#define CNL_DMC_PATH DMC_PATH(cnl, 1, 07)
> -#define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7)
> -#define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE
> -MODULE_FIRMWARE(CNL_DMC_PATH);
> -
> #define GLK_DMC_PATH DMC_PATH(glk, 1, 04)
> #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4)
> #define GLK_DMC_MAX_FW_SIZE 0x4000
> @@ -718,10 +713,6 @@ void intel_dmc_ucode_init(struct drm_i915_private
> *dev_priv)
> dmc->fw_path = ICL_DMC_PATH;
> dmc->required_version = ICL_DMC_VERSION_REQUIRED;
> dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE;
> - } else if (IS_CANNONLAKE(dev_priv)) {
> - dmc->fw_path = CNL_DMC_PATH;
> - dmc->required_version = CNL_DMC_VERSION_REQUIRED;
> - dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE;
> } else if (IS_GEMINILAKE(dev_priv)) {
> dmc->fw_path = GLK_DMC_PATH;
> dmc->required_version = GLK_DMC_VERSION_REQUIRED;
> --
> 2.31.1
>
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Re: [Intel-gfx] [PATCH 09/30] drm/i915/display: remove explicit CNL handling from intel_display_debugfs.c
On Fri, Jul 23, 2021 at 05:10:53PM -0700, Lucas De Marchi wrote:
> Only one reference to CNL that is not needed, but code is the same for
> DISPLAY_VER >= 11, so leave the code around and just remove the special
> case for CNL.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 2cf742a0b957..8fdacb252bb1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2500,7 +2500,7 @@ int intel_connector_debugfs_add(struct drm_connector
> *connector)
> connector, &i915_hdcp_sink_capability_fops);
> }
>
> - if ((DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) &&
> + if (DISPLAY_VER(dev_priv) >= 11 &&
> ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
> !to_intel_connector(connector)->mst_port) ||
> connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
> --
> 2.31.1
>
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove CNL support
On Sat, Jul 24, 2021 at 12:37:18PM -, Patchwork wrote: >Patch Details > >Series: Remove CNL support >URL: [1]https://patchwork.freedesktop.org/series/92969/ >State: failure >Details: >[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html > > CI Bug Log - changes from CI_DRM_10383_full -> Patchwork_20701_full > > Summary > >FAILURE > >Serious unknown changes coming with Patchwork_20701_full absolutely >need to be >verified manually. > >If you think the reported changes have nothing to do with the changes >introduced in Patchwork_20701_full, please notify your bug team to >allow them >to document this new failure mode, which will reduce false positives in >CI. > > Possible new issues > >Here are the unknown changes that may have been introduced in >Patchwork_20701_full: > > IGT changes > > Possible regressions > > * igt@kms_universal_plane@universal-plane-pipe-b-sanity: > + shard-glk: [3]PASS -> [4]FAIL +23 similar issues I got to the end of the display related ones and I couldn't spot where this bug is :( > > Known issues > >Here are the changes found in Patchwork_20701_full that come from known >issues: > > IGT changes > > Issues hit > > * igt@feature_discovery@psr2: > + shard-iclb: [5]PASS -> [6]SKIP ([i915#658]) > * igt@gem_ctx_persistence@engines-queued: > + shard-snb: NOTRUN -> [7]SKIP ([fdo#109271] / [i915#1099]) > * igt@gem_eio@in-flight-suspend: > + shard-apl: [8]PASS -> [9]DMESG-WARN ([i915#180]) +2 similar > issues > * igt@gem_exec_fair@basic-deadline: > + shard-glk: [10]PASS -> [11]FAIL ([i915#2846]) > * igt@gem_exec_fair@basic-none-rrul@rcs0: > + shard-glk: [12]PASS -> [13]FAIL ([i915#2842]) +2 similar > issues > * igt@gem_exec_fair@basic-none@vcs1: > + shard-kbl: [14]PASS -> [15]FAIL ([i915#2842]) +1 similar issue > * igt@gem_exec_fair@basic-pace@rcs0: > + shard-tglb: [16]PASS -> [17]FAIL ([i915#2851]) > * igt@gem_exec_fair@basic-pace@vecs0: > + shard-kbl: NOTRUN -> [18]FAIL ([i915#2842]) +1 similar issue > * igt@gem_exec_schedule@pi-ringfull@vecs0: > + shard-skl: [19]PASS -> [20]FAIL ([i915#3397]) > * igt@gem_userptr_blits@dmabuf-sync: > + shard-apl: NOTRUN -> [21]SKIP ([fdo#109271] / [i915#3323]) > * igt@gem_userptr_blits@input-checking: > + shard-snb: NOTRUN -> [22]DMESG-WARN ([i915#3002]) > * igt@i915_pm_rpm@drm-resources-equal: > + shard-tglb: NOTRUN -> [23]SKIP ([i915#579]) > * igt@kms_async_flips@alternate-sync-async-flip: > + shard-skl: [24]PASS -> [25]FAIL ([i915#2521]) > * igt@kms_big_fb@x-tiled-32bpp-rotate-0: > + shard-glk: [26]PASS -> [27]DMESG-WARN ([i915#118] / [i915#95]) > * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: > + shard-apl: NOTRUN -> [28]SKIP ([fdo#109271] / [i915#3777]) +1 > similar issue > * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: > + shard-skl: NOTRUN -> [29]SKIP ([fdo#109271] / [i915#3777]) > * igt@kms_big_fb@yf-tiled-64bpp-rotate-180: > + shard-tglb: NOTRUN -> [30]SKIP ([fdo#111615]) > * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs: > + shard-tglb: NOTRUN -> [31]SKIP ([i915#3689]) > * igt@kms_chamelium@dp-mode-timings: > + shard-apl: NOTRUN -> [32]SKIP ([fdo#109271] / [fdo#111827]) > +21 similar issues > * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: > + shard-snb: NOTRUN -> [33]SKIP ([fdo#109271] / [fdo#111827]) > +13 similar issues > * igt@kms_color_chamelium@pipe-a-ctm-0-25: > + shard-skl: NOTRUN -> [34]SKIP ([fdo#109271] / [fdo#111827]) +1 > similar issue > * igt@kms_color_chamelium@pipe-a-ctm-0-75: > + shard-kbl: NOTRUN -> [35]SKIP ([fdo#109271] / [fdo#111827]) +4 > similar issues > * igt@kms_content_protection@atomic-dpms: > + shard-apl: NOTRUN -> [36]TIMEOUT ([i915#1319]) > * igt@kms_cursor_legacy@pipe-d-single-bo: > + shard-kbl: NOTRUN -> [37]SKIP ([fdo#109271] / [i915#533]) +1 > similar issue > * igt@kms_cursor_legacy@pipe-d-torture-bo: > + shard-iclb: NOTRUN -> [38]SKIP ([fdo#109278]) +3 similar > issues > * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1: > + shard-glk: [39]PASS -> [40]FAIL ([i915#2122]) > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: > + shard-skl: [41]PASS -> [42]FAIL ([i915#79]) > * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2: > + shard-glk: [43]PASS -> [44]FAIL ([i915#79]) > * igt@kms_flip@flip-vs-expired-vblank@a-edp1: > + shard-skl: [45]PASS -> [46]FAIL ([i91
Re: [Intel-gfx] [PATCH 19/30] drm/i915: remove explicit CNL handling from intel_pm.c
On Fri, Jul 23, 2021 at 05:11:03PM -0700, Lucas De Marchi wrote:
> Remove support for CNL as it's highly untested, probably broken, and
> there is no real platform that requires this code. This is part of CNL
> removal from i915.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 41 +
> 2 files changed, 2 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fdc8fd424d36..f032a4c8b26d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8239,7 +8239,7 @@ enum {
>
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
> -#define CNL_DELAY_PMRSP(1 << 22)
> +#define ICL_DELAY_PMRSP(1 << 22)
> #define MASK_WAKEMEM (1 << 13)
> #define CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index aa64b2ef2efb..65bc3709f54c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7465,7 +7465,7 @@ static void icl_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> /*Wa_14010594013:icl, ehl */
> intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> - 0, CNL_DELAY_PMRSP);
> + 0, ICL_DELAY_PMRSP);
> }
>
> static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -7515,43 +7515,6 @@ static void cnp_init_clock_gating(struct
> drm_i915_private *dev_priv)
> CNP_PWM_CGE_GATING_DISABLE);
> }
>
> -static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> - cnp_init_clock_gating(dev_priv);
> -
> - /* This is not an Wa. Enable for better image quality */
> - intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
> -_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> -
> - /* WaEnableChickenDCPR:cnl */
> - intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> -intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) |
> MASK_WAKEMEM);
> -
> - /*
> - * WaFbcWakeMemOn:cnl
> - * Display WA #0859: cnl
> - */
> - intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
> intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> -DISP_FBC_MEMORY_WAKE);
> -
> - val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
> - /* ReadHitWriteOnlyDisable:cnl */
> - val |= RCCUNIT_CLKGATE_DIS;
> - intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
> -
> - /* Wa_2201832410:cnl */
> - val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
> - val |= GWUNIT_CLKGATE_DIS;
> - intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
> -
> - /* WaDisableVFclkgate:cnl */
> - /* WaVFUnitClockGatingDisable:cnl */
> - val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
> - val |= VFUNIT_CLKGATE_DIS;
> - intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
> -}
> -
> static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> cnp_init_clock_gating(dev_priv);
> @@ -7980,8 +7943,6 @@ void intel_init_clock_gating_hooks(struct
> drm_i915_private *dev_priv)
> dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
> else if (GRAPHICS_VER(dev_priv) == 11)
> dev_priv->display.init_clock_gating = icl_init_clock_gating;
> - else if (IS_CANNONLAKE(dev_priv))
> - dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> else if (IS_SKYLAKE(dev_priv))
> --
> 2.31.1
>
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 3/3] tests/i915_query: add some sanity checking around regions query
On 2021-07-08 at 13:25:54 +0100, Matthew Auld wrote:
> Ensure if we feed garbage into DRM_I915_QUERY_MEMORY_REGIONS it does
> indeed fail as expected. Also add some asserts for the invariants with
> the probed regions, for example we should always have at least system
> memory.
LGTM.
Reviewed-by: Ramalingam C
>
> Signed-off-by: Matthew Auld
> Cc: Ville Syrjala
> ---
> tests/i915/i915_query.c | 127
> 1 file changed, 127 insertions(+)
>
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 34965841..78bd4a2b 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -33,6 +33,10 @@ IGT_TEST_DESCRIPTION("Testing the i915 query uAPI.");
> */
> #define MIN_TOPOLOGY_ITEM_SIZE (sizeof(struct drm_i915_query_topology_info)
> + 3)
>
> +/* All devices should have at least one region. */
> +#define MIN_REGIONS_ITEM_SIZE (sizeof(struct drm_i915_query_memory_regions)
> + \
> +sizeof(struct drm_i915_memory_region_info))
> +
> static int
> __i915_query(int fd, struct drm_i915_query *q)
> {
> @@ -491,6 +495,119 @@ test_query_topology_known_pci_ids(int fd, int devid)
> free(topo_info);
> }
>
> +static bool query_regions_supported(int fd)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_MEMORY_REGIONS,
> + };
> +
> + return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
> +}
> +
> +static void test_query_regions_garbage_items(int fd)
> +{
> + struct drm_i915_query_memory_regions *regions;
> + struct drm_i915_query_item item;
> + int i;
> +
> + test_query_garbage_items(fd,
> + DRM_I915_QUERY_MEMORY_REGIONS,
> + MIN_REGIONS_ITEM_SIZE,
> + sizeof(struct drm_i915_query_memory_regions));
> +
> + memset(&item, 0, sizeof(item));
> + item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
> + i915_query_items(fd, &item, 1);
> + igt_assert(item.length > 0);
> +
> + regions = calloc(1, item.length);
> + item.data_ptr = to_user_pointer(regions);
> +
> + /* Bogus; in-MBZ */
> + for (i = 0; i < ARRAY_SIZE(regions->rsvd); i++) {
> + regions->rsvd[i] = 0xdeadbeaf;
> + i915_query_items(fd, &item, 1);
> + igt_assert_eq(item.length, -EINVAL);
> + regions->rsvd[i] = 0;
> + }
> +
> + i915_query_items(fd, &item, 1);
> + igt_assert(regions->num_regions);
> + igt_assert(item.length > 0);
> +
> + /* Bogus; out-MBZ */
> + for (i = 0; i < regions->num_regions; i++) {
> + struct drm_i915_memory_region_info info = regions->regions[i];
> + int j;
> +
> + igt_assert_eq_u32(info.rsvd0, 0);
> +
> + for (j = 0; j < ARRAY_SIZE(info.rsvd1); j++)
> + igt_assert_eq_u32(info.rsvd1[j], 0);
> + }
> +
> + /* Bogus; kernel is meant to set this */
> + regions->num_regions = 1;
> + i915_query_items(fd, &item, 1);
> + igt_assert_eq(item.length, -EINVAL);
> + regions->num_regions = 0;
> +
> + free(regions);
> +}
> +
> +static void test_query_regions_sanity_check(int fd)
> +{
> + struct drm_i915_query_memory_regions *regions;
> + struct drm_i915_query_item item;
> + bool found_system;
> + int i;
> +
> + memset(&item, 0, sizeof(item));
> + item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
> + i915_query_items(fd, &item, 1);
> + igt_assert(item.length > 0);
> +
> + regions = calloc(1, item.length);
> +
> + item.data_ptr = to_user_pointer(regions);
> + i915_query_items(fd, &item, 1);
> +
> + /* We should always have at least one region */
> + igt_assert(regions->num_regions);
> +
> + found_system = false;
> + for (i = 0; i < regions->num_regions; i++) {
> + struct drm_i915_gem_memory_class_instance r1 =
> + regions->regions[i].region;
> + int j;
> +
> + if (r1.memory_class == I915_MEMORY_CLASS_SYSTEM) {
> + igt_assert_eq(r1.memory_instance, 0);
> + found_system = true;
> + }
> +
> + igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
> +r1.memory_class == I915_MEMORY_CLASS_DEVICE);
> +
> + for (j = 0; j < regions->num_regions; j++) {
> + struct drm_i915_gem_memory_class_instance r2 =
> + regions->regions[j].region;
> +
> + if (i == j)
> + continue;
> +
> + /* All probed class:instance pairs must be unique */
> + igt_assert(!(r1.memory_class == r2.memory_class &&
> + r1.memory_instance == r2.memory_instance));
> + }
> + }
> +
> + /* All devices should at least have system memory */
> + igt_as
[Intel-gfx] [PATCH i-g-t 1/7] lib/i915/gem_mman: add FIXED mmap mode
We need this for discrete.
Signed-off-by: Matthew Auld
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Ramalingam C
---
lib/i915/gem_mman.c | 37 +
lib/i915/gem_mman.h | 4
2 files changed, 41 insertions(+)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 4b4f2114..e2514f0c 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -497,6 +497,43 @@ void *gem_mmap_offset__cpu(int fd, uint32_t handle,
uint64_t offset,
return ptr;
}
+#define LOCAL_I915_MMAP_OFFSET_FIXED 4
+
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot)
+{
+ return __gem_mmap_offset(fd, handle, offset, size, prot,
+LOCAL_I915_MMAP_OFFSET_FIXED);
+}
+
+/**
+ * gem_mmap_offset__fixed: Used to mmap objects on discrete platforms
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Like __gem_mmap_offset__fixed() except we assert on failure.
+ *
+ * For discrete the caching attributes for the pages are fixed at allocation
+ * time, and can't be changed. The FIXED mode will simply use the same caching
*
+ * mode of the allocated pages. This mode will always be coherent with GPU
+ * access.
+ *
+ * On non-discrete platforms this mode is not supported.
+ *
+ * Returns: A pointer to the created memory mapping
+ */
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot)
+{
+ void *ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot);
+
+ igt_assert(ptr);
+ return ptr;
+}
+
/**
* __gem_mmap__cpu_coherent:
* @fd: open i915 drm file descriptor
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index 5695d2ad..290c997d 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -37,6 +37,8 @@ bool gem_mmap_offset__has_wc(int fd);
void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size,
unsigned prot);
void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+void *gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+uint64_t size, unsigned prot);
void *gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset,
@@ -54,6 +56,8 @@ void *__gem_mmap_offset__cpu(int fd, uint32_t handle,
uint64_t offset,
void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size,
unsigned prot);
void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
+void *__gem_mmap_offset__fixed(int fd, uint32_t handle, uint64_t offset,
+ uint64_t size, unsigned prot);
void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset,
uint64_t size, unsigned prot);
void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t
size,
--
2.26.3
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[Intel-gfx] [PATCH i-g-t 2/7] lib/i915/gem_mman: add fixed mode to mmap__device_coherent
On discrete we need to fallback to this mode. Signed-off-by: Matthew Auld Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Ramalingam C --- lib/i915/gem_mman.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c index e2514f0c..222e8896 100644 --- a/lib/i915/gem_mman.c +++ b/lib/i915/gem_mman.c @@ -383,9 +383,10 @@ void *__gem_mmap__device_coherent(int fd, uint32_t handle, uint64_t offset, I915_MMAP_OFFSET_WC); if (!ptr) ptr = __gem_mmap__wc(fd, handle, offset, size, prot); - if (!ptr) ptr = __gem_mmap__gtt(fd, handle, size, prot); + if (!ptr) + ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot); return ptr; } -- 2.26.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 3/7] lib/i915/gem_mman: add fixed mode to mmap__cpu_coherent
On discrete we only support the new fixed mode. Signed-off-by: Matthew Auld Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Ramalingam C --- lib/i915/gem_mman.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c index 222e8896..337d28fb 100644 --- a/lib/i915/gem_mman.c +++ b/lib/i915/gem_mman.c @@ -580,6 +580,8 @@ void *gem_mmap__cpu_coherent(int fd, uint32_t handle, uint64_t offset, igt_assert(offset == 0); ptr = __gem_mmap__cpu_coherent(fd, handle, offset, size, prot); + if (!ptr) + ptr = __gem_mmap_offset__fixed(fd, handle, offset, size, prot); igt_assert(ptr); return ptr; -- 2.26.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 5/7] lib/ioctl_wrappers: update mmap_{read, write} for discrete
We can no longer just call get_caching or set_domain, and the mmap mode
must be FIXED. This should bring back gem_exec_basic and a few others in
CI on DG1.
Signed-off-by: Matthew Auld
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Ramalingam C
---
lib/ioctl_wrappers.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 25c5e495..7e27a1b3 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -339,7 +339,18 @@ static void mmap_write(int fd, uint32_t handle, uint64_t
offset,
if (!length)
return;
- if (is_cache_coherent(fd, handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only mmap mode supportd is FIXED.
+*/
+ map = gem_mmap_offset__fixed(fd, handle, 0,
+offset + length,
+PROT_READ | PROT_WRITE);
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ }
+
+ if (!map && is_cache_coherent(fd, handle)) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0, offset + length,
PROT_READ | PROT_WRITE);
@@ -369,7 +380,17 @@ static void mmap_read(int fd, uint32_t handle, uint64_t
offset, void *buf, uint6
if (!length)
return;
- if (gem_has_llc(fd) || is_cache_coherent(fd, handle)) {
+ if (gem_has_lmem(fd)) {
+ /*
+* set/get_caching and set_domain are no longer supported on
+* discrete, also the only supported mmap mode is FIXED.
+*/
+ map = gem_mmap_offset__fixed(fd, handle, 0,
+offset + length, PROT_READ);
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ }
+
+ if (!map && (gem_has_llc(fd) || is_cache_coherent(fd, handle))) {
/* offset arg for mmap functions must be 0 */
map = __gem_mmap__cpu_coherent(fd, handle, 0,
offset + length, PROT_READ);
--
2.26.3
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[Intel-gfx] [PATCH i-g-t 4/7] lib/i915/gem_mman: update mmap_offset_types with FIXED
We need to also iterate the fixed mode in the tests which rely on this.
Signed-off-by: Matthew Auld
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Ramalingam C
---
lib/i915/gem_mman.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 337d28fb..fe4963f0 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -611,6 +611,7 @@ const struct mmap_offset mmap_offset_types[] = {
{ "wb", I915_MMAP_OFFSET_WB, I915_GEM_DOMAIN_CPU },
{ "wc", I915_MMAP_OFFSET_WC, I915_GEM_DOMAIN_WC },
{ "uc", I915_MMAP_OFFSET_UC, I915_GEM_DOMAIN_WC },
+ { "fixed", LOCAL_I915_MMAP_OFFSET_FIXED, 0},
{},
};
--
2.26.3
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[Intel-gfx] [PATCH i-g-t 6/7] lib/ioctl_wrappers: update set_domain for discrete
On discrete set_domain is now gone, instead we just need to add the
wait.
Signed-off-by: Matthew Auld
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Ramalingam C
---
lib/ioctl_wrappers.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 7e27a1b3..09eb3ce7 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -565,7 +565,12 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t
read, uint32_t write)
*/
void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write)
{
- igt_assert_eq(__gem_set_domain(fd, handle, read, write), 0);
+ int ret = __gem_set_domain(fd, handle, read, write);
+
+ if (ret == -ENODEV && gem_has_lmem(fd))
+ igt_assert_eq(gem_wait(fd, handle, 0), 0);
+ else
+ igt_assert_eq(ret, 0);
}
/**
--
2.26.3
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[Intel-gfx] [PATCH i-g-t 7/7] tests/i915/module_load: update for discrete
The set_caching ioctl is gone for discrete, and now just returns
-ENODEV. Update the gem_sanitycheck to account for that. After this we
should be back to just having the breakage caused by missing reloc
support for the reload testcase.
Signed-off-by: Matthew Auld
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Ramalingam C
---
tests/i915/i915_module_load.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 98ceb5d8..4b42fe3e 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -172,17 +172,22 @@ static void gem_sanitycheck(void)
{
struct drm_i915_gem_caching args = {};
int i915 = __drm_open_driver(DRIVER_INTEL);
+ int expected;
int err;
+ expected = -ENOENT;
+ if (gem_has_lmem(i915))
+ expected = -ENODEV;
+
err = 0;
if (ioctl(i915, DRM_IOCTL_I915_GEM_SET_CACHING, &args))
err = -errno;
- if (err == -ENOENT)
+ if (err == expected)
store_all(i915);
errno = 0;
close(i915);
- igt_assert_eq(err, -ENOENT);
+ igt_assert_eq(err, expected);
}
static void
--
2.26.3
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm: use the lookup lock in drm_is_current_master
== Series Details ==
Series: series starting with [v2,1/3] drm: use the lookup lock in
drm_is_current_master
URL : https://patchwork.freedesktop.org/series/93005/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10393_full -> Patchwork_20704_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_20704_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20704_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_20704_full:
### IGT changes ###
Possible regressions
* igt@i915_selftest@mock@requests:
- shard-glk: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-glk9/igt@i915_selftest@m...@requests.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-glk2/igt@i915_selftest@m...@requests.html
* igt@perf_pmu@multi-client@bcs0:
- shard-skl: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-skl5/igt@perf_pmu@multi-cli...@bcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-skl10/igt@perf_pmu@multi-cli...@bcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@suspend:
- {shard-rkl}:[SKIP][5] ([i915#1072]) -> [DMESG-WARN][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-2/igt@kms_...@suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-6/igt@kms_...@suspend.html
* igt@prime_vgem@sync@bcs0:
- {shard-rkl}:[PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-5/igt@prime_vgem@s...@bcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-1/igt@prime_vgem@s...@bcs0.html
* igt@runner@aborted:
- {shard-rkl}:([FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12])
([i915#3002] / [i915#3728] / [i915#3811]) -> ([FAIL][13], [FAIL][14],
[FAIL][15], [FAIL][16]) ([i915#3002] / [i915#3811])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-6/igt@run...@aborted.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-5/igt@run...@aborted.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-1/igt@run...@aborted.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-rkl-1/igt@run...@aborted.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-1/igt@run...@aborted.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-1/igt@run...@aborted.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-5/igt@run...@aborted.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-rkl-5/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_20704_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#111827])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-iclb3/igt@feature_discov...@chamelium.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099]) +5
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-snb6/igt@gem_ctx_persiste...@idempotent.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2846])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-glk6/igt@gem_exec_f...@basic-deadline.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-glk7/igt@gem_exec_f...@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-iclb5/igt@gem_exec_fair@basic-none-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][23] ([i915#2842])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20704/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][24] -> [SKIP][25] ([fdo#109271])
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10393/shard-kbl
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Remove CNL support
On Mon, Jul 26, 2021 at 07:07:49AM -0400, Rodrigo Vivi wrote: On Sat, Jul 24, 2021 at 12:37:18PM -, Patchwork wrote: Patch Details Series: Remove CNL support URL: [1]https://patchwork.freedesktop.org/series/92969/ State: failure Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20701/index.html CI Bug Log - changes from CI_DRM_10383_full -> Patchwork_20701_full Summary FAILURE Serious unknown changes coming with Patchwork_20701_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_20701_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues Here are the unknown changes that may have been introduced in Patchwork_20701_full: IGT changes Possible regressions * igt@kms_universal_plane@universal-plane-pipe-b-sanity: + shard-glk: [3]PASS -> [4]FAIL +23 similar issues I got to the end of the display related ones and I couldn't spot where this bug is :( although since this is GLK, it's very suspicious. I will take another look and maybe try to split the patches to check what CI thinks. Thanks! Lucas De Marchi Known issues Here are the changes found in Patchwork_20701_full that come from known issues: IGT changes Issues hit * igt@feature_discovery@psr2: + shard-iclb: [5]PASS -> [6]SKIP ([i915#658]) * igt@gem_ctx_persistence@engines-queued: + shard-snb: NOTRUN -> [7]SKIP ([fdo#109271] / [i915#1099]) * igt@gem_eio@in-flight-suspend: + shard-apl: [8]PASS -> [9]DMESG-WARN ([i915#180]) +2 similar issues * igt@gem_exec_fair@basic-deadline: + shard-glk: [10]PASS -> [11]FAIL ([i915#2846]) * igt@gem_exec_fair@basic-none-rrul@rcs0: + shard-glk: [12]PASS -> [13]FAIL ([i915#2842]) +2 similar issues * igt@gem_exec_fair@basic-none@vcs1: + shard-kbl: [14]PASS -> [15]FAIL ([i915#2842]) +1 similar issue * igt@gem_exec_fair@basic-pace@rcs0: + shard-tglb: [16]PASS -> [17]FAIL ([i915#2851]) * igt@gem_exec_fair@basic-pace@vecs0: + shard-kbl: NOTRUN -> [18]FAIL ([i915#2842]) +1 similar issue * igt@gem_exec_schedule@pi-ringfull@vecs0: + shard-skl: [19]PASS -> [20]FAIL ([i915#3397]) * igt@gem_userptr_blits@dmabuf-sync: + shard-apl: NOTRUN -> [21]SKIP ([fdo#109271] / [i915#3323]) * igt@gem_userptr_blits@input-checking: + shard-snb: NOTRUN -> [22]DMESG-WARN ([i915#3002]) * igt@i915_pm_rpm@drm-resources-equal: + shard-tglb: NOTRUN -> [23]SKIP ([i915#579]) * igt@kms_async_flips@alternate-sync-async-flip: + shard-skl: [24]PASS -> [25]FAIL ([i915#2521]) * igt@kms_big_fb@x-tiled-32bpp-rotate-0: + shard-glk: [26]PASS -> [27]DMESG-WARN ([i915#118] / [i915#95]) * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: + shard-apl: NOTRUN -> [28]SKIP ([fdo#109271] / [i915#3777]) +1 similar issue * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip: + shard-skl: NOTRUN -> [29]SKIP ([fdo#109271] / [i915#3777]) * igt@kms_big_fb@yf-tiled-64bpp-rotate-180: + shard-tglb: NOTRUN -> [30]SKIP ([fdo#111615]) * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_ccs: + shard-tglb: NOTRUN -> [31]SKIP ([i915#3689]) * igt@kms_chamelium@dp-mode-timings: + shard-apl: NOTRUN -> [32]SKIP ([fdo#109271] / [fdo#111827]) +21 similar issues * igt@kms_chamelium@hdmi-hpd-enable-disable-mode: + shard-snb: NOTRUN -> [33]SKIP ([fdo#109271] / [fdo#111827]) +13 similar issues * igt@kms_color_chamelium@pipe-a-ctm-0-25: + shard-skl: NOTRUN -> [34]SKIP ([fdo#109271] / [fdo#111827]) +1 similar issue * igt@kms_color_chamelium@pipe-a-ctm-0-75: + shard-kbl: NOTRUN -> [35]SKIP ([fdo#109271] / [fdo#111827]) +4 similar issues * igt@kms_content_protection@atomic-dpms: + shard-apl: NOTRUN -> [36]TIMEOUT ([i915#1319]) * igt@kms_cursor_legacy@pipe-d-single-bo: + shard-kbl: NOTRUN -> [37]SKIP ([fdo#109271] / [i915#533]) +1 similar issue * igt@kms_cursor_legacy@pipe-d-torture-bo: + shard-iclb: NOTRUN -> [38]SKIP ([fdo#109278]) +3 similar issues * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1: + shard-glk: [39]PASS -> [40]FAIL ([i915#2122]) * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: + shard-skl: [41]PASS -> [42]FAIL ([i915#79]) * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2: + shard-glk: [43]PASS -> [44]FAIL ([i915#79]) * igt@kms_flip@flip-vs-expired-vblank@a-edp1: + shard-skl: [45]PASS -> [46]FAI
Re: [Intel-gfx] [PATCH 02/30] drm/i915/display: split DISPLAY_VER 9 and 10 in intel_setup_outputs()
On Mon, Jul 26, 2021 at 06:20:03AM -0400, Rodrigo Vivi wrote: On Sat, Jul 24, 2021 at 10:02:15PM -0700, Lucas De Marchi wrote: On Sat, Jul 24, 2021 at 06:41:21PM +0100, Christoph Hellwig wrote: > Still tests fine: > > Tested-by: Christoph Hellwig I just pushed this to drm-intel-next as part of another series and added your Tested-by. Rodrigo, can you pick this up for -fixes? This should go with your other patch to fix the port mask, too. done. But while doing this and reviewing this series at the same time I got myself wondering if we shouldn't remove the PORT_F support entirely... well, there is still ICL with some skus having it. I'm not sure we actually have that sku out in the wild, but if we do, we wouldn't be able to remove it. Lucas De Marchi Thanks for the bug report and test. Lucas De Marchi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/30] drm/i915: remove explicit CNL handling from i915_irq.c
On Mon, Jul 26, 2021 at 06:59:35AM -0400, Rodrigo Vivi wrote:
On Fri, Jul 23, 2021 at 05:11:02PM -0700, Lucas De Marchi wrote:
Remove special handling of PORT_F in i915_irq.c and only do it for
DISPLAY_VER == 11.
oh! ignore my previous thought about removing the port F...
of course I only saw this after replying to your comment :)
thanks
Lucas De Marchi
Signed-off-by: Lucas De Marchi
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_irq.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e2171bd2820e..17d336218b67 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2297,11 +2297,10 @@ static u32 gen8_de_port_aux_mask(struct
drm_i915_private *dev_priv)
GEN9_AUX_CHANNEL_C |
GEN9_AUX_CHANNEL_D;
- if (IS_CNL_WITH_PORT_F(dev_priv) || DISPLAY_VER(dev_priv) == 11)
- mask |= CNL_AUX_CHANNEL_F;
-
- if (DISPLAY_VER(dev_priv) == 11)
+ if (DISPLAY_VER(dev_priv) == 11) {
+ mask |= ICL_AUX_CHANNEL_F;
mask |= ICL_AUX_CHANNEL_E;
+ }
return mask;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d198b1a2d4b5..fdc8fd424d36 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7945,7 +7945,7 @@ enum {
#define DSI1_NON_TE (1 << 31)
#define DSI0_NON_TE (1 << 30)
#define ICL_AUX_CHANNEL_E (1 << 29)
-#define CNL_AUX_CHANNEL_F (1 << 28)
+#define ICL_AUX_CHANNEL_F (1 << 28)
#define GEN9_AUX_CHANNEL_D(1 << 27)
#define GEN9_AUX_CHANNEL_C(1 << 26)
#define GEN9_AUX_CHANNEL_B(1 << 25)
--
2.31.1
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Re: [Intel-gfx] [PATCH 0/8] drm/i915: Migrate memory to SMEM when imported cross-device (v8)
On Mon, Jul 26, 2021 at 3:12 AM Matthew Auld wrote: > > On Fri, 23 Jul 2021 at 18:21, Jason Ekstrand wrote: > > > > This patch series fixes an issue with discrete graphics on Intel where we > > allowed dma-buf import while leaving the object in local memory. This > > breaks down pretty badly if the import happened on a different physical > > device. > > > > v7: > > - Drop "drm/i915/gem/ttm: Place new BOs in the requested region" > > - Add a new "drm/i915/gem: Call i915_gem_flush_free_objects() in > > i915_gem_dumb_create()" > > - Misc. review feedback from Matthew Auld > > v8: > > - Misc. review feedback from Matthew Auld > > v9: > > - Replace the i915/ttm patch with two that are hopefully more correct > > > > Jason Ekstrand (6): > > drm/i915/gem: Check object_can_migrate from object_migrate > > drm/i915/gem: Refactor placement setup for i915_gem_object_create* > > (v2) > > drm/i915/gem: Call i915_gem_flush_free_objects() in > > i915_gem_dumb_create() > > drm/i915/gem: Unify user object creation (v3) > > drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed > > drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails > > > > Thomas Hellström (2): > > drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8) > > drm/i915/gem: Migrate to system at dma-buf attach time (v7) > > Should I push the series? Yes, please. Do we have a solid testing plan for things like this that touch discrete? I tested with mesa+glxgears on my DG1 but haven't run anything more stressful. --Jason > > > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 177 > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 58 -- > > drivers/gpu/drm/i915/gem/i915_gem_object.c| 20 +- > > drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 + > > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 +- > > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 190 +- > > .../drm/i915/gem/selftests/i915_gem_migrate.c | 15 -- > > 7 files changed, 341 insertions(+), 136 deletions(-) > > > > -- > > 2.31.1 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
On Mon, Jul 26, 2021 at 3:06 AM Matthew Auld
wrote:
>
> On Fri, 23 Jul 2021 at 18:48, Jason Ekstrand wrote:
> >
> > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12044
>
> Cool, is that ready to go? i.e can we start merging the kernel + IGT side.
Yes, it's all reviewed. Though, it sounds like Maarten had a comment
so we should settle on that before landing.
> >
> > On Fri, Jul 23, 2021 at 6:35 AM Matthew Auld wrote:
> > >
> > > From: Chris Wilson
> > >
> > > Jason Ekstrand requested a more efficient method than userptr+set-domain
> > > to determine if the userptr object was backed by a complete set of pages
> > > upon creation. To be more efficient than simply populating the userptr
> > > using get_user_pages() (as done by the call to set-domain or execbuf),
> > > we can walk the tree of vm_area_struct and check for gaps or vma not
> > > backed by struct page (VM_PFNMAP). The question is how to handle
> > > VM_MIXEDMAP which may be either struct page or pfn backed...
> > >
> > > With discrete we are going to drop support for set_domain(), so offering
> > > a way to probe the pages, without having to resort to dummy batches has
> > > been requested.
> > >
> > > v2:
> > > - add new query param for the PROBE flag, so userspace can easily
> > > check if the kernel supports it(Jason).
> > > - use mmap_read_{lock, unlock}.
> > > - add some kernel-doc.
> > > v3:
> > > - In the docs also mention that PROBE doesn't guarantee that the pages
> > > will remain valid by the time they are actually used(Tvrtko).
> > > - Add a small comment for the hole finding logic(Jason).
> > > - Move the param next to all the other params which just return true.
> > >
> > > Testcase: igt/gem_userptr_blits/probe
> > > Signed-off-by: Chris Wilson
> > > Signed-off-by: Matthew Auld
> > > Cc: Thomas Hellström
> > > Cc: Maarten Lankhorst
> > > Cc: Tvrtko Ursulin
> > > Cc: Jordan Justen
> > > Cc: Kenneth Graunke
> > > Cc: Jason Ekstrand
> > > Cc: Daniel Vetter
> > > Cc: Ramalingam C
> > > Reviewed-by: Tvrtko Ursulin
> > > Acked-by: Kenneth Graunke
> > > Reviewed-by: Jason Ekstrand
> > > ---
> > > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> > > drivers/gpu/drm/i915/i915_getparam.c| 1 +
> > > include/uapi/drm/i915_drm.h | 20 ++
> > > 3 files changed, 61 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > index 56edfeff8c02..468a7a617fbf 100644
> > > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > > @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
> > > i915_gem_userptr_ops = {
> > >
> > > #endif
> > >
> > > +static int
> > > +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> > > +{
> > > + const unsigned long end = addr + len;
> > > + struct vm_area_struct *vma;
> > > + int ret = -EFAULT;
> > > +
> > > + mmap_read_lock(mm);
> > > + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> > > + /* Check for holes, note that we also update the addr
> > > below */
> > > + if (vma->vm_start > addr)
> > > + break;
> > > +
> > > + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> > > + break;
> > > +
> > > + if (vma->vm_end >= end) {
> > > + ret = 0;
> > > + break;
> > > + }
> > > +
> > > + addr = vma->vm_end;
> > > + }
> > > + mmap_read_unlock(mm);
> > > +
> > > + return ret;
> > > +}
> > > +
> > > /*
> > > * Creates a new mm object that wraps some normal memory from the process
> > > * context - user memory.
> > > @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > > }
> > >
> > > if (args->flags & ~(I915_USERPTR_READ_ONLY |
> > > - I915_USERPTR_UNSYNCHRONIZED))
> > > + I915_USERPTR_UNSYNCHRONIZED |
> > > + I915_USERPTR_PROBE))
> > > return -EINVAL;
> > >
> > > if (i915_gem_object_size_2big(args->user_size))
> > > @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > > return -ENODEV;
> > > }
> > >
> > > + if (args->flags & I915_USERPTR_PROBE) {
> > > + /*
> > > +* Check that the range pointed to represents real struct
> > > +* pages and not iomappings (at this moment in time!)
> > > +*/
> > > + ret = probe_range(current->mm, args->user_ptr,
> > > args->user_size);
> > > + if (ret)
> > > + return ret;
> > > + }
> > > +
> > > #ifdef CONFIG_MMU_NOTIFIER
> > > obj = i915_gem_object_alloc();
> > > i
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
On Mon, Jul 26, 2021 at 3:31 AM Maarten Lankhorst
wrote:
>
> Op 23-07-2021 om 13:34 schreef Matthew Auld:
> > From: Chris Wilson
> >
> > Jason Ekstrand requested a more efficient method than userptr+set-domain
> > to determine if the userptr object was backed by a complete set of pages
> > upon creation. To be more efficient than simply populating the userptr
> > using get_user_pages() (as done by the call to set-domain or execbuf),
> > we can walk the tree of vm_area_struct and check for gaps or vma not
> > backed by struct page (VM_PFNMAP). The question is how to handle
> > VM_MIXEDMAP which may be either struct page or pfn backed...
> >
> > With discrete we are going to drop support for set_domain(), so offering
> > a way to probe the pages, without having to resort to dummy batches has
> > been requested.
> >
> > v2:
> > - add new query param for the PROBE flag, so userspace can easily
> > check if the kernel supports it(Jason).
> > - use mmap_read_{lock, unlock}.
> > - add some kernel-doc.
> > v3:
> > - In the docs also mention that PROBE doesn't guarantee that the pages
> > will remain valid by the time they are actually used(Tvrtko).
> > - Add a small comment for the hole finding logic(Jason).
> > - Move the param next to all the other params which just return true.
> >
> > Testcase: igt/gem_userptr_blits/probe
> > Signed-off-by: Chris Wilson
> > Signed-off-by: Matthew Auld
> > Cc: Thomas Hellström
> > Cc: Maarten Lankhorst
> > Cc: Tvrtko Ursulin
> > Cc: Jordan Justen
> > Cc: Kenneth Graunke
> > Cc: Jason Ekstrand
> > Cc: Daniel Vetter
> > Cc: Ramalingam C
> > Reviewed-by: Tvrtko Ursulin
> > Acked-by: Kenneth Graunke
> > Reviewed-by: Jason Ekstrand
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
> > drivers/gpu/drm/i915/i915_getparam.c| 1 +
> > include/uapi/drm/i915_drm.h | 20 ++
> > 3 files changed, 61 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > index 56edfeff8c02..468a7a617fbf 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> > @@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
> > i915_gem_userptr_ops = {
> >
> > #endif
> >
> > +static int
> > +probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
> > +{
> > + const unsigned long end = addr + len;
> > + struct vm_area_struct *vma;
> > + int ret = -EFAULT;
> > +
> > + mmap_read_lock(mm);
> > + for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
> > + /* Check for holes, note that we also update the addr below */
> > + if (vma->vm_start > addr)
> > + break;
> > +
> > + if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> > + break;
> > +
> > + if (vma->vm_end >= end) {
> > + ret = 0;
> > + break;
> > + }
> > +
> > + addr = vma->vm_end;
> > + }
> > + mmap_read_unlock(mm);
> > +
> > + return ret;
> > +}
> > +
> > /*
> > * Creates a new mm object that wraps some normal memory from the process
> > * context - user memory.
> > @@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > }
> >
> > if (args->flags & ~(I915_USERPTR_READ_ONLY |
> > - I915_USERPTR_UNSYNCHRONIZED))
> > + I915_USERPTR_UNSYNCHRONIZED |
> > + I915_USERPTR_PROBE))
> > return -EINVAL;
> >
> > if (i915_gem_object_size_2big(args->user_size))
> > @@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
> > return -ENODEV;
> > }
> >
> > + if (args->flags & I915_USERPTR_PROBE) {
> > + /*
> > + * Check that the range pointed to represents real struct
> > + * pages and not iomappings (at this moment in time!)
> > + */
> > + ret = probe_range(current->mm, args->user_ptr,
> > args->user_size);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > #ifdef CONFIG_MMU_NOTIFIER
> > obj = i915_gem_object_alloc();
> > if (obj == NULL)
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c
> > b/drivers/gpu/drm/i915/i915_getparam.c
> > index 24e18219eb50..bbb7cac43eb4 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -134,6 +134,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
> > *data,
> > case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
> > case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
> > case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
> > + case I915_PARAM_HAS_USERPTR_PROBE:
> > /* For the time being all of these are always true;
> >* if some supported hard
Re: [Intel-gfx] [PATCH 01/10] drm/i915: Check for nomodeset in i915_init() first
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> When modesetting (aka the full pci driver, which has nothing to do
> with disable_display option, which just gives you the full pci driver
> without the display driver) is disabled, we load nothing and do
> nothing.
>
> So move that check first, for a bit of orderliness. With Jason's
> module init/exit table this now becomes trivial.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
Reviewed-by: Jason Ekstrand
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 48ea23dd3b5b..0deaeeba2347 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1292,9 +1292,9 @@ static const struct {
> int (*init)(void);
> void (*exit)(void);
> } init_funcs[] = {
> + { i915_check_nomodeset, NULL },
> { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> - { i915_check_nomodeset, NULL },
> { i915_pmu_init, i915_pmu_exit },
> { i915_register_pci_driver, i915_unregister_pci_driver },
> { i915_perf_sysctl_register, i915_perf_sysctl_unregister },
> --
> 2.32.0
>
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Re: [Intel-gfx] [PATCH 02/10] drm/i915: move i915_active slab to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_cache to just a slab_cache.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_active.c | 31 ++---
> drivers/gpu/drm/i915/i915_active.h | 3 +++
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_globals.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> 5 files changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_active.c
> b/drivers/gpu/drm/i915/i915_active.c
> index 91723123ae9f..9ffeb77eb5bb 100644
> --- a/drivers/gpu/drm/i915/i915_active.c
> +++ b/drivers/gpu/drm/i915/i915_active.c
> @@ -13,7 +13,6 @@
>
> #include "i915_drv.h"
> #include "i915_active.h"
> -#include "i915_globals.h"
>
> /*
> * Active refs memory management
> @@ -22,10 +21,7 @@
> * they idle (when we know the active requests are inactive) and allocate the
> * nodes from a local slab cache to hopefully reduce the fragmentation.
> */
> -static struct i915_global_active {
> - struct i915_global base;
> - struct kmem_cache *slab_cache;
> -} global;
> +struct kmem_cache *slab_cache;
static? Or were you planning to expose it somehow? With that fixed,
Reviewed-by: Jason Ekstrand
>
> struct active_node {
> struct rb_node node;
> @@ -174,7 +170,7 @@ __active_retire(struct i915_active *ref)
> /* Finally free the discarded timeline tree */
> rbtree_postorder_for_each_entry_safe(it, n, &root, node) {
> GEM_BUG_ON(i915_active_fence_isset(&it->base));
> - kmem_cache_free(global.slab_cache, it);
> + kmem_cache_free(slab_cache, it);
> }
> }
>
> @@ -322,7 +318,7 @@ active_instance(struct i915_active *ref, u64 idx)
> * XXX: We should preallocate this before i915_active_ref() is ever
> * called, but we cannot call into fs_reclaim() anyway, so use
> GFP_ATOMIC.
> */
> - node = kmem_cache_alloc(global.slab_cache, GFP_ATOMIC);
> + node = kmem_cache_alloc(slab_cache, GFP_ATOMIC);
> if (!node)
> goto out;
>
> @@ -788,7 +784,7 @@ void i915_active_fini(struct i915_active *ref)
> mutex_destroy(&ref->mutex);
>
> if (ref->cache)
> - kmem_cache_free(global.slab_cache, ref->cache);
> + kmem_cache_free(slab_cache, ref->cache);
> }
>
> static inline bool is_idle_barrier(struct active_node *node, u64 idx)
> @@ -908,7 +904,7 @@ int i915_active_acquire_preallocate_barrier(struct
> i915_active *ref,
> node = reuse_idle_barrier(ref, idx);
> rcu_read_unlock();
> if (!node) {
> - node = kmem_cache_alloc(global.slab_cache,
> GFP_KERNEL);
> + node = kmem_cache_alloc(slab_cache, GFP_KERNEL);
> if (!node)
> goto unwind;
>
> @@ -956,7 +952,7 @@ int i915_active_acquire_preallocate_barrier(struct
> i915_active *ref,
> atomic_dec(&ref->count);
> intel_engine_pm_put(barrier_to_engine(node));
>
> - kmem_cache_free(global.slab_cache, node);
> + kmem_cache_free(slab_cache, node);
> }
> return -ENOMEM;
> }
> @@ -1176,21 +1172,16 @@ struct i915_active *i915_active_create(void)
> #include "selftests/i915_active.c"
> #endif
>
> -static void i915_global_active_exit(void)
> +void i915_active_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_cache);
> + kmem_cache_destroy(slab_cache);
> }
>
> -static struct i915_global_active global = { {
> - .exit = i915_global_active_exit,
> -} };
> -
> -int __init i915_global_active_init(void)
> +int __init i915_active_module_init(void)
> {
> - global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
> - if (!global.slab_cache)
> + slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
> + if (!slab_cache)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_active.h
> b/drivers/gpu/drm/i915/i915_active.h
> index d0feda68b874..5fcdb0e2bc9e 100644
> --- a/drivers/gpu/drm/i915/i915_active.h
> +++ b/drivers/gpu/drm/i915/i915_active.h
> @@ -247,4 +247,7 @@ static inline int __i915_request_await_exclusive(struct
> i915_request *rq,
> return err;
> }
>
> +void i915_active_module_exit(void);
> +int i915_active_module_init(void);
> +
> #endif /* _I915_ACTIVE_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index 91198f5b0a06..a53135ee831d 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++
Re: [Intel-gfx] [PATCH 03/10] drm/i915: move i915_buddy slab to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_blocks to just a
> slab_blocks.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_buddy.c | 25 -
> drivers/gpu/drm/i915/i915_buddy.h | 3 ++-
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> 4 files changed, 12 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_buddy.c
> b/drivers/gpu/drm/i915/i915_buddy.c
> index caabcaea3be7..045d00c43b4c 100644
> --- a/drivers/gpu/drm/i915/i915_buddy.c
> +++ b/drivers/gpu/drm/i915/i915_buddy.c
> @@ -8,13 +8,9 @@
> #include "i915_buddy.h"
>
> #include "i915_gem.h"
> -#include "i915_globals.h"
> #include "i915_utils.h"
>
> -static struct i915_global_buddy {
> - struct i915_global base;
> - struct kmem_cache *slab_blocks;
> -} global;
> +struct kmem_cache *slab_blocks;
static? With that fixed,
Reviewed-by: Jason Ekstrand
>
> static struct i915_buddy_block *i915_block_alloc(struct i915_buddy_mm *mm,
> struct i915_buddy_block
> *parent,
> @@ -25,7 +21,7 @@ static struct i915_buddy_block *i915_block_alloc(struct
> i915_buddy_mm *mm,
>
> GEM_BUG_ON(order > I915_BUDDY_MAX_ORDER);
>
> - block = kmem_cache_zalloc(global.slab_blocks, GFP_KERNEL);
> + block = kmem_cache_zalloc(slab_blocks, GFP_KERNEL);
> if (!block)
> return NULL;
>
> @@ -40,7 +36,7 @@ static struct i915_buddy_block *i915_block_alloc(struct
> i915_buddy_mm *mm,
> static void i915_block_free(struct i915_buddy_mm *mm,
> struct i915_buddy_block *block)
> {
> - kmem_cache_free(global.slab_blocks, block);
> + kmem_cache_free(slab_blocks, block);
> }
>
> static void mark_allocated(struct i915_buddy_block *block)
> @@ -410,21 +406,16 @@ int i915_buddy_alloc_range(struct i915_buddy_mm *mm,
> #include "selftests/i915_buddy.c"
> #endif
>
> -static void i915_global_buddy_exit(void)
> +void i915_buddy_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_blocks);
> + kmem_cache_destroy(slab_blocks);
> }
>
> -static struct i915_global_buddy global = { {
> - .exit = i915_global_buddy_exit,
> -} };
> -
> -int __init i915_global_buddy_init(void)
> +int __init i915_buddy_module_init(void)
> {
> - global.slab_blocks = KMEM_CACHE(i915_buddy_block, 0);
> - if (!global.slab_blocks)
> + slab_blocks = KMEM_CACHE(i915_buddy_block, 0);
> + if (!slab_blocks)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_buddy.h
> b/drivers/gpu/drm/i915/i915_buddy.h
> index d8f26706de52..3940d632f208 100644
> --- a/drivers/gpu/drm/i915/i915_buddy.h
> +++ b/drivers/gpu/drm/i915/i915_buddy.h
> @@ -129,6 +129,7 @@ void i915_buddy_free(struct i915_buddy_mm *mm, struct
> i915_buddy_block *block);
>
> void i915_buddy_free_list(struct i915_buddy_mm *mm, struct list_head
> *objects);
>
> -int i915_global_buddy_init(void);
> +void i915_buddy_module_exit(void);
> +int i915_buddy_module_init(void);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index a53135ee831d..3de7cf22ec76 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -7,7 +7,6 @@
> #include
> #include
>
> -#include "i915_buddy.h"
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_object.h"
> #include "i915_globals.h"
> @@ -33,7 +32,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_buddy_init,
> i915_global_context_init,
> i915_global_gem_context_init,
> i915_global_objects_init,
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6ee77a8f43d6..f9527269e30a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -31,6 +31,7 @@
> #include "display/intel_fbdev.h"
>
> #include "i915_active.h"
> +#include "i915_buddy.h"
> #include "i915_drv.h"
> #include "i915_perf.h"
> #include "i915_globals.h"
> @@ -1295,6 +1296,7 @@ static const struct {
> } init_funcs[] = {
> { i915_check_nomodeset, NULL },
> { i915_active_module_init, i915_active_module_exit },
> + { i915_buddy_module_init, i915_buddy_module_exit },
> { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> { i915_pmu_init, i915_pmu_exit },
> --
> 2.32.0
>
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ht
Re: [Intel-gfx] [PATCH 0/8] drm/i915: Migrate memory to SMEM when imported cross-device (v8)
On Mon, 26 Jul 2021 at 16:11, Jason Ekstrand wrote: > > On Mon, Jul 26, 2021 at 3:12 AM Matthew Auld > wrote: > > > > On Fri, 23 Jul 2021 at 18:21, Jason Ekstrand wrote: > > > > > > This patch series fixes an issue with discrete graphics on Intel where we > > > allowed dma-buf import while leaving the object in local memory. This > > > breaks down pretty badly if the import happened on a different physical > > > device. > > > > > > v7: > > > - Drop "drm/i915/gem/ttm: Place new BOs in the requested region" > > > - Add a new "drm/i915/gem: Call i915_gem_flush_free_objects() in > > > i915_gem_dumb_create()" > > > - Misc. review feedback from Matthew Auld > > > v8: > > > - Misc. review feedback from Matthew Auld > > > v9: > > > - Replace the i915/ttm patch with two that are hopefully more correct > > > > > > Jason Ekstrand (6): > > > drm/i915/gem: Check object_can_migrate from object_migrate > > > drm/i915/gem: Refactor placement setup for i915_gem_object_create* > > > (v2) > > > drm/i915/gem: Call i915_gem_flush_free_objects() in > > > i915_gem_dumb_create() > > > drm/i915/gem: Unify user object creation (v3) > > > drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed > > > drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails > > > > > > Thomas Hellström (2): > > > drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8) > > > drm/i915/gem: Migrate to system at dma-buf attach time (v7) > > > > Should I push the series? > > Yes, please. Do we have a solid testing plan for things like this > that touch discrete? I tested with mesa+glxgears on my DG1 but > haven't run anything more stressful. I think all we really have are the migration related selftests, and CI is not even running them on DG1 due to other breakage. Assuming you ran these locally, I think we just merge the series? > > --Jason > > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 177 > > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 58 -- > > > drivers/gpu/drm/i915/gem/i915_gem_object.c| 20 +- > > > drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 + > > > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 +- > > > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 190 +- > > > .../drm/i915/gem/selftests/i915_gem_migrate.c | 15 -- > > > 7 files changed, 341 insertions(+), 136 deletions(-) > > > > > > -- > > > 2.31.1 > > > > > > ___ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
wrote:
>
>
> On 23/07/2021 20:29, Daniel Vetter wrote:
> > With the global kmem_cache shrink infrastructure gone there's nothing
> > special and we can convert them over.
> >
> > I'm doing this split up into each patch because there's quite a bit of
> > noise with removing the static global.slab_ce to just a
> > slab_ce.
> >
> > Cc: Jason Ekstrand
> > Signed-off-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 25 -
> > drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
> > drivers/gpu/drm/i915/i915_globals.c | 2 --
> > drivers/gpu/drm/i915/i915_globals.h | 1 -
> > drivers/gpu/drm/i915/i915_pci.c | 2 ++
> > 5 files changed, 13 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index baa05fddd690..283382549a6f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -7,7 +7,6 @@
> > #include "gem/i915_gem_pm.h"
> >
> > #include "i915_drv.h"
> > -#include "i915_globals.h"
> > #include "i915_trace.h"
> >
> > #include "intel_context.h"
> > @@ -15,14 +14,11 @@
> > #include "intel_engine_pm.h"
> > #include "intel_ring.h"
> >
> > -static struct i915_global_context {
> > - struct i915_global base;
> > - struct kmem_cache *slab_ce;
> > -} global;
> > +struct kmem_cache *slab_ce;
Static? With that,
Reviewed-by: Jason Ekstrand
> >
> > static struct intel_context *intel_context_alloc(void)
> > {
> > - return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
> > + return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
> > }
> >
> > static void rcu_context_free(struct rcu_head *rcu)
> > @@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
> > struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
> >
> > trace_intel_context_free(ce);
> > - kmem_cache_free(global.slab_ce, ce);
> > + kmem_cache_free(slab_ce, ce);
> > }
> >
> > void intel_context_free(struct intel_context *ce)
> > @@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
> > i915_active_fini(&ce->active);
> > }
> >
> > -static void i915_global_context_exit(void)
> > +void i915_context_module_exit(void)
> > {
> > - kmem_cache_destroy(global.slab_ce);
> > + kmem_cache_destroy(slab_ce);
> > }
> >
> > -static struct i915_global_context global = { {
> > - .exit = i915_global_context_exit,
> > -} };
> > -
> > -int __init i915_global_context_init(void)
> > +int __init i915_context_module_init(void)
> > {
> > - global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> > - if (!global.slab_ce)
> > + slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> > + if (!slab_ce)
> > return -ENOMEM;
> >
> > - i915_global_register(&global.base);
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > b/drivers/gpu/drm/i915/gt/intel_context.h
> > index 974ef85320c2..a0ca82e3c40d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > @@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
> > struct intel_engine_cs *engine);
> > void intel_context_fini(struct intel_context *ce);
> >
> > +void i915_context_module_exit(void);
> > +int i915_context_module_init(void);
> > +
> > struct intel_context *
> > intel_context_create(struct intel_engine_cs *engine);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_globals.c
> > b/drivers/gpu/drm/i915/i915_globals.c
> > index 3de7cf22ec76..d36eb7dc40aa 100644
> > --- a/drivers/gpu/drm/i915/i915_globals.c
> > +++ b/drivers/gpu/drm/i915/i915_globals.c
> > @@ -7,7 +7,6 @@
> > #include
> > #include
> >
> > -#include "gem/i915_gem_context.h"
> > #include "gem/i915_gem_object.h"
> > #include "i915_globals.h"
> > #include "i915_request.h"
> > @@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
> > }
> >
> > static __initconst int (* const initfn[])(void) = {
> > - i915_global_context_init,
> > i915_global_gem_context_init,
> > i915_global_objects_init,
> > i915_global_request_init,
> > diff --git a/drivers/gpu/drm/i915/i915_globals.h
> > b/drivers/gpu/drm/i915/i915_globals.h
> > index d80901ba75e3..60daa738a188 100644
> > --- a/drivers/gpu/drm/i915/i915_globals.h
> > +++ b/drivers/gpu/drm/i915/i915_globals.h
> > @@ -23,7 +23,6 @@ int i915_globals_init(void);
> > void i915_globals_exit(void);
> >
> > /* constructors */
> > -int i915_global_context_init(void);
> > int i915_global_gem_context_init(void);
> > int i915_global_objects_init(void);
> > int i915_global_request_init(void);
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index f9527269e30a..266618157775 100644
> > --- a/drivers/gpu/
Re: [Intel-gfx] [PATCH 0/8] drm/i915: Migrate memory to SMEM when imported cross-device (v8)
On Mon, Jul 26, 2021 at 10:29 AM Matthew Auld wrote: > > On Mon, 26 Jul 2021 at 16:11, Jason Ekstrand wrote: > > > > On Mon, Jul 26, 2021 at 3:12 AM Matthew Auld > > wrote: > > > > > > On Fri, 23 Jul 2021 at 18:21, Jason Ekstrand wrote: > > > > > > > > This patch series fixes an issue with discrete graphics on Intel where > > > > we > > > > allowed dma-buf import while leaving the object in local memory. This > > > > breaks down pretty badly if the import happened on a different physical > > > > device. > > > > > > > > v7: > > > > - Drop "drm/i915/gem/ttm: Place new BOs in the requested region" > > > > - Add a new "drm/i915/gem: Call i915_gem_flush_free_objects() in > > > > i915_gem_dumb_create()" > > > > - Misc. review feedback from Matthew Auld > > > > v8: > > > > - Misc. review feedback from Matthew Auld > > > > v9: > > > > - Replace the i915/ttm patch with two that are hopefully more correct > > > > > > > > Jason Ekstrand (6): > > > > drm/i915/gem: Check object_can_migrate from object_migrate > > > > drm/i915/gem: Refactor placement setup for i915_gem_object_create* > > > > (v2) > > > > drm/i915/gem: Call i915_gem_flush_free_objects() in > > > > i915_gem_dumb_create() > > > > drm/i915/gem: Unify user object creation (v3) > > > > drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed > > > > drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails > > > > > > > > Thomas Hellström (2): > > > > drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8) > > > > drm/i915/gem: Migrate to system at dma-buf attach time (v7) > > > > > > Should I push the series? > > > > Yes, please. Do we have a solid testing plan for things like this > > that touch discrete? I tested with mesa+glxgears on my DG1 but > > haven't run anything more stressful. > > I think all we really have are the migration related selftests, and CI > is not even running them on DG1 due to other breakage. Assuming you > ran these locally, I think we just merge the series? Works for me. Yes, I ran them on my TGL+DG1 box. I've also tested both GL and Vulkan PRIME support with the client running on DG1 and the compositor running on TGL with this series and everything works smooth. --Jason > > > > --Jason > > > > > > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 177 > > > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 58 -- > > > > drivers/gpu/drm/i915/gem/i915_gem_object.c| 20 +- > > > > drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 + > > > > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 +- > > > > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 190 +- > > > > .../drm/i915/gem/selftests/i915_gem_migrate.c | 15 -- > > > > 7 files changed, 341 insertions(+), 136 deletions(-) > > > > > > > > -- > > > > 2.31.1 > > > > > > > > ___ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 05/10] drm/i915: move gem_context slab to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_luts to just a
> slab_luts.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 25 +++--
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 3 +++
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_globals.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> 5 files changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 89ca401bf9ae..c17c28af1e57 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -79,25 +79,21 @@
> #include "gt/intel_ring.h"
>
> #include "i915_gem_context.h"
> -#include "i915_globals.h"
> #include "i915_trace.h"
> #include "i915_user_extensions.h"
>
> #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
>
> -static struct i915_global_gem_context {
> - struct i915_global base;
> - struct kmem_cache *slab_luts;
> -} global;
> +struct kmem_cache *slab_luts;
static.
With that,
Reviewed-by: Jason Ekstrand
> struct i915_lut_handle *i915_lut_handle_alloc(void)
> {
> - return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
> + return kmem_cache_alloc(slab_luts, GFP_KERNEL);
> }
>
> void i915_lut_handle_free(struct i915_lut_handle *lut)
> {
> - return kmem_cache_free(global.slab_luts, lut);
> + return kmem_cache_free(slab_luts, lut);
> }
>
> static void lut_close(struct i915_gem_context *ctx)
> @@ -2282,21 +2278,16 @@ i915_gem_engines_iter_next(struct
> i915_gem_engines_iter *it)
> #include "selftests/i915_gem_context.c"
> #endif
>
> -static void i915_global_gem_context_exit(void)
> +void i915_gem_context_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_luts);
> + kmem_cache_destroy(slab_luts);
> }
>
> -static struct i915_global_gem_context global = { {
> - .exit = i915_global_gem_context_exit,
> -} };
> -
> -int __init i915_global_gem_context_init(void)
> +int __init i915_gem_context_module_init(void)
> {
> - global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
> - if (!global.slab_luts)
> + slab_luts = KMEM_CACHE(i915_lut_handle, 0);
> + if (!slab_luts)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 20411db84914..18060536b0c2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -224,6 +224,9 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter
> *it);
> for (i915_gem_engines_iter_init(&(it), (engines)); \
> ((ce) = i915_gem_engines_iter_next(&(it)));)
>
> +void i915_gem_context_module_exit(void);
> +int i915_gem_context_module_init(void);
> +
> struct i915_lut_handle *i915_lut_handle_alloc(void);
> void i915_lut_handle_free(struct i915_lut_handle *lut);
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index d36eb7dc40aa..dbb3d81eeea7 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -7,7 +7,6 @@
> #include
> #include
>
> -#include "gem/i915_gem_object.h"
> #include "i915_globals.h"
> #include "i915_request.h"
> #include "i915_scheduler.h"
> @@ -31,7 +30,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_gem_context_init,
> i915_global_objects_init,
> i915_global_request_init,
> i915_global_scheduler_init,
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
> b/drivers/gpu/drm/i915/i915_globals.h
> index 60daa738a188..f16752dbbdbf 100644
> --- a/drivers/gpu/drm/i915/i915_globals.h
> +++ b/drivers/gpu/drm/i915/i915_globals.h
> @@ -23,7 +23,6 @@ int i915_globals_init(void);
> void i915_globals_exit(void);
>
> /* constructors */
> -int i915_global_gem_context_init(void);
> int i915_global_objects_init(void);
> int i915_global_request_init(void);
> int i915_global_scheduler_init(void);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 266618157775..2b56e664d043 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -34,6 +34,7 @@
> #include "i915_buddy.h"
> #include "i915_drv.h"
> #include "gem/i915_gem_context.h"
> +#include "gem/i915_gem_object.h"
> #include "i915_perf.h"
> #include "i915_globals.h"
> #include "i915_selftest.h"
> @@ -1299,6 +1300,7 @@ static cons
Re: [Intel-gfx] [PATCH 06/10] drm/i915: move gem_objects slab to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_objects to just a
> slab_objects.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 26 +++---
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 3 +++
> drivers/gpu/drm/i915/i915_globals.c| 1 -
> drivers/gpu/drm/i915/i915_globals.h| 1 -
> drivers/gpu/drm/i915/i915_pci.c| 1 +
> 5 files changed, 12 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 5c21cff33199..53156250d283 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -30,14 +30,10 @@
> #include "i915_gem_context.h"
> #include "i915_gem_mman.h"
> #include "i915_gem_object.h"
> -#include "i915_globals.h"
> #include "i915_memcpy.h"
> #include "i915_trace.h"
>
> -static struct i915_global_object {
> - struct i915_global base;
> - struct kmem_cache *slab_objects;
> -} global;
> +struct kmem_cache *slab_objects;
static
With that,
Reviewed-by: Jason Ekstrand
> static const struct drm_gem_object_funcs i915_gem_object_funcs;
>
> @@ -45,7 +41,7 @@ struct drm_i915_gem_object *i915_gem_object_alloc(void)
> {
> struct drm_i915_gem_object *obj;
>
> - obj = kmem_cache_zalloc(global.slab_objects, GFP_KERNEL);
> + obj = kmem_cache_zalloc(slab_objects, GFP_KERNEL);
> if (!obj)
> return NULL;
> obj->base.funcs = &i915_gem_object_funcs;
> @@ -55,7 +51,7 @@ struct drm_i915_gem_object *i915_gem_object_alloc(void)
>
> void i915_gem_object_free(struct drm_i915_gem_object *obj)
> {
> - return kmem_cache_free(global.slab_objects, obj);
> + return kmem_cache_free(slab_objects, obj);
> }
>
> void i915_gem_object_init(struct drm_i915_gem_object *obj,
> @@ -664,23 +660,17 @@ void i915_gem_init__objects(struct drm_i915_private
> *i915)
> INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
> }
>
> -static void i915_global_objects_exit(void)
> +void i915_objects_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_objects);
> + kmem_cache_destroy(slab_objects);
> }
>
> -static struct i915_global_object global = { {
> - .exit = i915_global_objects_exit,
> -} };
> -
> -int __init i915_global_objects_init(void)
> +int __init i915_objects_module_init(void)
> {
> - global.slab_objects =
> - KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
> - if (!global.slab_objects)
> + slab_objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
> + if (!slab_objects)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index f3ede43282dc..6d8ea62a372f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> @@ -48,6 +48,9 @@ static inline bool i915_gem_object_size_2big(u64 size)
>
> void i915_gem_init__objects(struct drm_i915_private *i915);
>
> +void i915_objects_module_exit(void);
> +int i915_objects_module_init(void);
> +
> struct drm_i915_gem_object *i915_gem_object_alloc(void);
> void i915_gem_object_free(struct drm_i915_gem_object *obj);
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index dbb3d81eeea7..40a592fbc3e0 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -30,7 +30,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_objects_init,
> i915_global_request_init,
> i915_global_scheduler_init,
> i915_global_vma_init,
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
> b/drivers/gpu/drm/i915/i915_globals.h
> index f16752dbbdbf..9734740708f4 100644
> --- a/drivers/gpu/drm/i915/i915_globals.h
> +++ b/drivers/gpu/drm/i915/i915_globals.h
> @@ -23,7 +23,6 @@ int i915_globals_init(void);
> void i915_globals_exit(void);
>
> /* constructors */
> -int i915_global_objects_init(void);
> int i915_global_request_init(void);
> int i915_global_scheduler_init(void);
> int i915_global_vma_init(void);
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2b56e664d043..2334eb3e9abb 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1301,6 +1301,7 @@ static const struct {
> { i915_buddy_module_init, i915_buddy_module_exit },
> { i915_context_module_init, i915_context_module_exit }
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On Mon, Jul 26, 2021 at 10:30 AM Jason Ekstrand wrote:
>
> On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
> wrote:
> >
> >
> > On 23/07/2021 20:29, Daniel Vetter wrote:
> > > With the global kmem_cache shrink infrastructure gone there's nothing
> > > special and we can convert them over.
> > >
> > > I'm doing this split up into each patch because there's quite a bit of
> > > noise with removing the static global.slab_ce to just a
> > > slab_ce.
> > >
> > > Cc: Jason Ekstrand
> > > Signed-off-by: Daniel Vetter
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_context.c | 25 -
> > > drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
> > > drivers/gpu/drm/i915/i915_globals.c | 2 --
> > > drivers/gpu/drm/i915/i915_globals.h | 1 -
> > > drivers/gpu/drm/i915/i915_pci.c | 2 ++
> > > 5 files changed, 13 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > > b/drivers/gpu/drm/i915/gt/intel_context.c
> > > index baa05fddd690..283382549a6f 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > > @@ -7,7 +7,6 @@
> > > #include "gem/i915_gem_pm.h"
> > >
> > > #include "i915_drv.h"
> > > -#include "i915_globals.h"
> > > #include "i915_trace.h"
> > >
> > > #include "intel_context.h"
> > > @@ -15,14 +14,11 @@
> > > #include "intel_engine_pm.h"
> > > #include "intel_ring.h"
> > >
> > > -static struct i915_global_context {
> > > - struct i915_global base;
> > > - struct kmem_cache *slab_ce;
> > > -} global;
> > > +struct kmem_cache *slab_ce;
>
> Static? With that,
>
> Reviewed-by: Jason Ekstrand
>
> > >
> > > static struct intel_context *intel_context_alloc(void)
> > > {
> > > - return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
> > > + return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
> > > }
> > >
> > > static void rcu_context_free(struct rcu_head *rcu)
> > > @@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
> > > struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
> > >
> > > trace_intel_context_free(ce);
> > > - kmem_cache_free(global.slab_ce, ce);
> > > + kmem_cache_free(slab_ce, ce);
> > > }
> > >
> > > void intel_context_free(struct intel_context *ce)
> > > @@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
> > > i915_active_fini(&ce->active);
> > > }
> > >
> > > -static void i915_global_context_exit(void)
> > > +void i915_context_module_exit(void)
> > > {
> > > - kmem_cache_destroy(global.slab_ce);
> > > + kmem_cache_destroy(slab_ce);
> > > }
> > >
> > > -static struct i915_global_context global = { {
> > > - .exit = i915_global_context_exit,
> > > -} };
> > > -
> > > -int __init i915_global_context_init(void)
> > > +int __init i915_context_module_init(void)
> > > {
> > > - global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> > > - if (!global.slab_ce)
> > > + slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> > > + if (!slab_ce)
> > > return -ENOMEM;
> > >
> > > - i915_global_register(&global.base);
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > > b/drivers/gpu/drm/i915/gt/intel_context.h
> > > index 974ef85320c2..a0ca82e3c40d 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > > @@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
> > > struct intel_engine_cs *engine);
> > > void intel_context_fini(struct intel_context *ce);
> > >
> > > +void i915_context_module_exit(void);
> > > +int i915_context_module_init(void);
> > > +
> > > struct intel_context *
> > > intel_context_create(struct intel_engine_cs *engine);
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_globals.c
> > > b/drivers/gpu/drm/i915/i915_globals.c
> > > index 3de7cf22ec76..d36eb7dc40aa 100644
> > > --- a/drivers/gpu/drm/i915/i915_globals.c
> > > +++ b/drivers/gpu/drm/i915/i915_globals.c
> > > @@ -7,7 +7,6 @@
> > > #include
> > > #include
> > >
> > > -#include "gem/i915_gem_context.h"
> > > #include "gem/i915_gem_object.h"
> > > #include "i915_globals.h"
> > > #include "i915_request.h"
> > > @@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
> > > }
> > >
> > > static __initconst int (* const initfn[])(void) = {
> > > - i915_global_context_init,
> > > i915_global_gem_context_init,
> > > i915_global_objects_init,
> > > i915_global_request_init,
> > > diff --git a/drivers/gpu/drm/i915/i915_globals.h
> > > b/drivers/gpu/drm/i915/i915_globals.h
> > > index d80901ba75e3..60daa738a188 100644
> > > --- a/drivers/gpu/drm/i915/i915_globals.h
> > > +++ b/drivers/gpu/drm/i915/i915_globals.h
> > > @@ -23,7 +23,6 @@ int i915_globals_init(void);
> > > void i915_globals_exit(void);
> > >
> > > /* construc
Re: [Intel-gfx] [PATCH 07/10] drm/i915: move request slabs to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_requests|execute_cbs to just a
> slab_requests|execute_cbs.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_request.c | 47 -
> drivers/gpu/drm/i915/i915_request.h | 3 ++
> 4 files changed, 24 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index 40a592fbc3e0..8fffa8d93bc5 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -8,7 +8,6 @@
> #include
>
> #include "i915_globals.h"
> -#include "i915_request.h"
> #include "i915_scheduler.h"
> #include "i915_vma.h"
>
> @@ -30,7 +29,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_request_init,
> i915_global_scheduler_init,
> i915_global_vma_init,
> };
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 2334eb3e9abb..bb2bd12fb8c2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -35,6 +35,7 @@
> #include "i915_drv.h"
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_object.h"
> +#include "i915_request.h"
> #include "i915_perf.h"
> #include "i915_globals.h"
> #include "i915_selftest.h"
> @@ -1302,6 +1303,7 @@ static const struct {
> { i915_context_module_init, i915_context_module_exit },
> { i915_gem_context_module_init, i915_gem_context_module_exit },
> { i915_objects_module_init, i915_objects_module_exit },
> + { i915_request_module_init, i915_request_module_exit },
> { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> { i915_pmu_init, i915_pmu_exit },
> diff --git a/drivers/gpu/drm/i915/i915_request.c
> b/drivers/gpu/drm/i915/i915_request.c
> index 6594cb2f8ebd..69152369ea00 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -42,7 +42,6 @@
>
> #include "i915_active.h"
> #include "i915_drv.h"
> -#include "i915_globals.h"
> #include "i915_trace.h"
> #include "intel_pm.h"
>
> @@ -52,11 +51,8 @@ struct execute_cb {
> struct i915_request *signal;
> };
>
> -static struct i915_global_request {
> - struct i915_global base;
> - struct kmem_cache *slab_requests;
> - struct kmem_cache *slab_execute_cbs;
> -} global;
> +struct kmem_cache *slab_requests;
static
> +struct kmem_cache *slab_execute_cbs;
static
Am I tired of typing this? Yes, I am! Will I keep typing it? Probably. :-P
>
> static const char *i915_fence_get_driver_name(struct dma_fence *fence)
> {
> @@ -107,7 +103,7 @@ static signed long i915_fence_wait(struct dma_fence
> *fence,
>
> struct kmem_cache *i915_request_slab_cache(void)
> {
> - return global.slab_requests;
> + return slab_requests;
> }
>
> static void i915_fence_release(struct dma_fence *fence)
> @@ -159,7 +155,7 @@ static void i915_fence_release(struct dma_fence *fence)
> !cmpxchg(&rq->engine->request_pool, NULL, rq))
> return;
>
> - kmem_cache_free(global.slab_requests, rq);
> + kmem_cache_free(slab_requests, rq);
> }
>
> const struct dma_fence_ops i915_fence_ops = {
> @@ -176,7 +172,7 @@ static void irq_execute_cb(struct irq_work *wrk)
> struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
>
> i915_sw_fence_complete(cb->fence);
> - kmem_cache_free(global.slab_execute_cbs, cb);
> + kmem_cache_free(slab_execute_cbs, cb);
> }
>
> static __always_inline void
> @@ -514,7 +510,7 @@ __await_execution(struct i915_request *rq,
> if (i915_request_is_active(signal))
> return 0;
>
> - cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
> + cb = kmem_cache_alloc(slab_execute_cbs, gfp);
> if (!cb)
> return -ENOMEM;
>
> @@ -868,7 +864,7 @@ request_alloc_slow(struct intel_timeline *tl,
> rq = list_first_entry(&tl->requests, typeof(*rq), link);
> i915_request_retire(rq);
>
> - rq = kmem_cache_alloc(global.slab_requests,
> + rq = kmem_cache_alloc(slab_requests,
> gfp | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
> if (rq)
> return rq;
> @@ -881,7 +877,7 @@ request_alloc_slow(struct intel_timeline *tl,
> retire_requests(tl);
>
> out:
> - return kmem_cache_alloc(global.slab_requests, gfp);
> + return kmem_cache_alloc(slab_requests, gfp);
> }
>
> static void __i915_request_ctor(void *a
Re: [Intel-gfx] [PATCH 08/10] drm/i915: move scheduler slabs to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_dependencies|priorities to just a
> slab_dependencies|priorities.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_globals.h | 2 --
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_scheduler.c | 39 +++
> drivers/gpu/drm/i915/i915_scheduler.h | 3 +++
> 5 files changed, 20 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index 8fffa8d93bc5..8923589057ab 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -8,7 +8,6 @@
> #include
>
> #include "i915_globals.h"
> -#include "i915_scheduler.h"
> #include "i915_vma.h"
>
> static LIST_HEAD(globals);
> @@ -29,7 +28,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_scheduler_init,
> i915_global_vma_init,
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
> b/drivers/gpu/drm/i915/i915_globals.h
> index 9734740708f4..7a57bce1da05 100644
> --- a/drivers/gpu/drm/i915/i915_globals.h
> +++ b/drivers/gpu/drm/i915/i915_globals.h
> @@ -23,8 +23,6 @@ int i915_globals_init(void);
> void i915_globals_exit(void);
>
> /* constructors */
> -int i915_global_request_init(void);
> -int i915_global_scheduler_init(void);
> int i915_global_vma_init(void);
>
> #endif /* _I915_GLOBALS_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bb2bd12fb8c2..a44318519977 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -39,6 +39,7 @@
> #include "i915_perf.h"
> #include "i915_globals.h"
> #include "i915_selftest.h"
> +#include "i915_scheduler.h"
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> @@ -1304,6 +1305,7 @@ static const struct {
> { i915_gem_context_module_init, i915_gem_context_module_exit },
> { i915_objects_module_init, i915_objects_module_exit },
> { i915_request_module_init, i915_request_module_exit },
> + { i915_scheduler_module_init, i915_scheduler_module_exit },
> { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> { i915_pmu_init, i915_pmu_exit },
> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
> b/drivers/gpu/drm/i915/i915_scheduler.c
> index 561c649e59f7..02d90d239ff5 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler.c
> +++ b/drivers/gpu/drm/i915/i915_scheduler.c
> @@ -7,15 +7,11 @@
> #include
>
> #include "i915_drv.h"
> -#include "i915_globals.h"
> #include "i915_request.h"
> #include "i915_scheduler.h"
>
> -static struct i915_global_scheduler {
> - struct i915_global base;
> - struct kmem_cache *slab_dependencies;
> - struct kmem_cache *slab_priorities;
> -} global;
> +struct kmem_cache *slab_dependencies;
static
> +struct kmem_cache *slab_priorities;
static
>
> static DEFINE_SPINLOCK(schedule_lock);
>
> @@ -93,7 +89,7 @@ i915_sched_lookup_priolist(struct i915_sched_engine
> *sched_engine, int prio)
> if (prio == I915_PRIORITY_NORMAL) {
> p = &sched_engine->default_priolist;
> } else {
> - p = kmem_cache_alloc(global.slab_priorities, GFP_ATOMIC);
> + p = kmem_cache_alloc(slab_priorities, GFP_ATOMIC);
> /* Convert an allocation failure to a priority bump */
> if (unlikely(!p)) {
> prio = I915_PRIORITY_NORMAL; /* recurses just once */
> @@ -122,7 +118,7 @@ i915_sched_lookup_priolist(struct i915_sched_engine
> *sched_engine, int prio)
>
> void __i915_priolist_free(struct i915_priolist *p)
> {
> - kmem_cache_free(global.slab_priorities, p);
> + kmem_cache_free(slab_priorities, p);
> }
>
> struct sched_cache {
> @@ -313,13 +309,13 @@ void i915_sched_node_reinit(struct i915_sched_node
> *node)
> static struct i915_dependency *
> i915_dependency_alloc(void)
> {
> - return kmem_cache_alloc(global.slab_dependencies, GFP_KERNEL);
> + return kmem_cache_alloc(slab_dependencies, GFP_KERNEL);
> }
>
> static void
> i915_dependency_free(struct i915_dependency *dep)
> {
> - kmem_cache_free(global.slab_dependencies, dep);
> + kmem_cache_free(slab_dependencies, dep);
> }
>
> bool __i915_sched_node_add_dependency(struct i915_sched_node *node,
> @@ -475,32 +471,27 @@ i915_sched_engine_create(unsigned int subclass)
> return sched_engine;
> }
>
> -static void i915_global_scheduler_exit(void)
> +void i915_scheduler_module_exit(void)
> {
> - kmem_cache_
Re: [Intel-gfx] [PATCH 09/10] drm/i915: move vma slab to direct module init/exit
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_vmas to just a
> slab_vmas.
>
> We have to keep i915_drv.h include in i915_globals otherwise there's
> nothing anymore that pulls in GEM_BUG_ON.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/i915_globals.c | 3 +--
> drivers/gpu/drm/i915/i915_globals.h | 3 ---
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/i915_vma.c | 25 -
> drivers/gpu/drm/i915/i915_vma.h | 3 +++
> 5 files changed, 14 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index 8923589057ab..04979789e7be 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -8,7 +8,7 @@
> #include
>
> #include "i915_globals.h"
> -#include "i915_vma.h"
> +#include "i915_drv.h"
>
> static LIST_HEAD(globals);
>
> @@ -28,7 +28,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_vma_init,
> };
>
> int __init i915_globals_init(void)
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
> b/drivers/gpu/drm/i915/i915_globals.h
> index 7a57bce1da05..57d2998bba45 100644
> --- a/drivers/gpu/drm/i915/i915_globals.h
> +++ b/drivers/gpu/drm/i915/i915_globals.h
> @@ -22,7 +22,4 @@ void i915_global_register(struct i915_global *global);
> int i915_globals_init(void);
> void i915_globals_exit(void);
>
> -/* constructors */
> -int i915_global_vma_init(void);
> -
> #endif /* _I915_GLOBALS_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a44318519977..0affcf33a211 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -40,6 +40,7 @@
> #include "i915_globals.h"
> #include "i915_selftest.h"
> #include "i915_scheduler.h"
> +#include "i915_vma.h"
>
> #define PLATFORM(x) .platform = (x)
> #define GEN(x) \
> @@ -1306,6 +1307,7 @@ static const struct {
> { i915_objects_module_init, i915_objects_module_exit },
> { i915_request_module_init, i915_request_module_exit },
> { i915_scheduler_module_init, i915_scheduler_module_exit },
> + { i915_vma_module_init, i915_vma_module_exit },
> { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> { i915_pmu_init, i915_pmu_exit },
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 09a7c47926f7..d094e2016b93 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -34,24 +34,20 @@
> #include "gt/intel_gt_requests.h"
>
> #include "i915_drv.h"
> -#include "i915_globals.h"
> #include "i915_sw_fence_work.h"
> #include "i915_trace.h"
> #include "i915_vma.h"
>
> -static struct i915_global_vma {
> - struct i915_global base;
> - struct kmem_cache *slab_vmas;
> -} global;
> +struct kmem_cache *slab_vmas;
static. With that,
Reviewed-by: Jason Ekstrand
>
> struct i915_vma *i915_vma_alloc(void)
> {
> - return kmem_cache_zalloc(global.slab_vmas, GFP_KERNEL);
> + return kmem_cache_zalloc(slab_vmas, GFP_KERNEL);
> }
>
> void i915_vma_free(struct i915_vma *vma)
> {
> - return kmem_cache_free(global.slab_vmas, vma);
> + return kmem_cache_free(slab_vmas, vma);
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_ERRLOG_GEM) && IS_ENABLED(CONFIG_DRM_DEBUG_MM)
> @@ -1414,21 +1410,16 @@ void i915_vma_make_purgeable(struct i915_vma *vma)
> #include "selftests/i915_vma.c"
> #endif
>
> -static void i915_global_vma_exit(void)
> +void i915_vma_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_vmas);
> + kmem_cache_destroy(slab_vmas);
> }
>
> -static struct i915_global_vma global = { {
> - .exit = i915_global_vma_exit,
> -} };
> -
> -int __init i915_global_vma_init(void)
> +int __init i915_vma_module_init(void)
> {
> - global.slab_vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
> - if (!global.slab_vmas)
> + slab_vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
> + if (!slab_vmas)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index eca452a9851f..ed69f66c7ab0 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -426,4 +426,7 @@ static inline int i915_vma_sync(struct i915_vma *vma)
> return i915_active_wait(&vma->active);
> }
>
> +void i915_vma_module_exit(void);
> +int i915_vma_module_init(void);
> +
> #endif
> --
> 2.32.0
>
___
Intel-g
Re: [Intel-gfx] [PATCH 10/10] drm/i915: Remove i915_globals
On Fri, Jul 23, 2021 at 2:29 PM Daniel Vetter wrote:
>
> No longer used.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
Reviewed-by: Jason Ekstrand
But, also, tvrtko is right that dumping all that stuff in i915_pci.c
isn't great. Mind typing a quick follow-on that moves i915_init/exit
to i915_drv.c?
--Jason
> ---
> drivers/gpu/drm/i915/Makefile | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
> drivers/gpu/drm/i915/i915_globals.c | 53 ---
> drivers/gpu/drm/i915/i915_globals.h | 25 -
> drivers/gpu/drm/i915/i915_pci.c | 2 -
> 5 files changed, 82 deletions(-)
> delete mode 100644 drivers/gpu/drm/i915/i915_globals.c
> delete mode 100644 drivers/gpu/drm/i915/i915_globals.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 10b3bb6207ba..9022dc638ed6 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -166,7 +166,6 @@ i915-y += \
> i915_gem_gtt.o \
> i915_gem_ww.o \
> i915_gem.o \
> - i915_globals.o \
> i915_query.o \
> i915_request.o \
> i915_scheduler.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index d86825437516..943c1d416ec0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -6,7 +6,6 @@
> #include
>
> #include "i915_drv.h"
> -#include "i915_globals.h"
> #include "i915_params.h"
> #include "intel_context.h"
> #include "intel_engine_pm.h"
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> deleted file mode 100644
> index 04979789e7be..
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -/*
> - * SPDX-License-Identifier: MIT
> - *
> - * Copyright © 2019 Intel Corporation
> - */
> -
> -#include
> -#include
> -
> -#include "i915_globals.h"
> -#include "i915_drv.h"
> -
> -static LIST_HEAD(globals);
> -
> -void __init i915_global_register(struct i915_global *global)
> -{
> - GEM_BUG_ON(!global->exit);
> -
> - list_add_tail(&global->link, &globals);
> -}
> -
> -static void __i915_globals_cleanup(void)
> -{
> - struct i915_global *global, *next;
> -
> - list_for_each_entry_safe_reverse(global, next, &globals, link)
> - global->exit();
> -}
> -
> -static __initconst int (* const initfn[])(void) = {
> -};
> -
> -int __init i915_globals_init(void)
> -{
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(initfn); i++) {
> - int err;
> -
> - err = initfn[i]();
> - if (err) {
> - __i915_globals_cleanup();
> - return err;
> - }
> - }
> -
> - return 0;
> -}
> -
> -void i915_globals_exit(void)
> -{
> - __i915_globals_cleanup();
> -}
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
> b/drivers/gpu/drm/i915/i915_globals.h
> deleted file mode 100644
> index 57d2998bba45..
> --- a/drivers/gpu/drm/i915/i915_globals.h
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -/*
> - * SPDX-License-Identifier: MIT
> - *
> - * Copyright © 2019 Intel Corporation
> - */
> -
> -#ifndef _I915_GLOBALS_H_
> -#define _I915_GLOBALS_H_
> -
> -#include
> -
> -typedef void (*i915_global_func_t)(void);
> -
> -struct i915_global {
> - struct list_head link;
> -
> - i915_global_func_t exit;
> -};
> -
> -void i915_global_register(struct i915_global *global);
> -
> -int i915_globals_init(void);
> -void i915_globals_exit(void);
> -
> -#endif /* _I915_GLOBALS_H_ */
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0affcf33a211..ed72bcb58331 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -37,7 +37,6 @@
> #include "gem/i915_gem_object.h"
> #include "i915_request.h"
> #include "i915_perf.h"
> -#include "i915_globals.h"
> #include "i915_selftest.h"
> #include "i915_scheduler.h"
> #include "i915_vma.h"
> @@ -1308,7 +1307,6 @@ static const struct {
> { i915_request_module_init, i915_request_module_exit },
> { i915_scheduler_module_init, i915_scheduler_module_exit },
> { i915_vma_module_init, i915_vma_module_exit },
> - { i915_globals_init, i915_globals_exit },
> { i915_mock_selftests, NULL },
> { i915_pmu_init, i915_pmu_exit },
> { i915_register_pci_driver, i915_unregister_pci_driver },
> --
> 2.32.0
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/8] drm/i915: Migrate memory to SMEM when imported cross-device (v8)
On Mon, 26 Jul 2021 at 16:32, Jason Ekstrand wrote: > > On Mon, Jul 26, 2021 at 10:29 AM Matthew Auld > wrote: > > > > On Mon, 26 Jul 2021 at 16:11, Jason Ekstrand wrote: > > > > > > On Mon, Jul 26, 2021 at 3:12 AM Matthew Auld > > > wrote: > > > > > > > > On Fri, 23 Jul 2021 at 18:21, Jason Ekstrand > > > > wrote: > > > > > > > > > > This patch series fixes an issue with discrete graphics on Intel > > > > > where we > > > > > allowed dma-buf import while leaving the object in local memory. This > > > > > breaks down pretty badly if the import happened on a different > > > > > physical > > > > > device. > > > > > > > > > > v7: > > > > > - Drop "drm/i915/gem/ttm: Place new BOs in the requested region" > > > > > - Add a new "drm/i915/gem: Call i915_gem_flush_free_objects() in > > > > > i915_gem_dumb_create()" > > > > > - Misc. review feedback from Matthew Auld > > > > > v8: > > > > > - Misc. review feedback from Matthew Auld > > > > > v9: > > > > > - Replace the i915/ttm patch with two that are hopefully more correct > > > > > > > > > > Jason Ekstrand (6): > > > > > drm/i915/gem: Check object_can_migrate from object_migrate > > > > > drm/i915/gem: Refactor placement setup for i915_gem_object_create* > > > > > (v2) > > > > > drm/i915/gem: Call i915_gem_flush_free_objects() in > > > > > i915_gem_dumb_create() > > > > > drm/i915/gem: Unify user object creation (v3) > > > > > drm/i915/gem/ttm: Only call __i915_gem_object_set_pages if needed > > > > > drm/i915/gem: Always call obj->ops->migrate unless can_migrate fails > > > > > > > > > > Thomas Hellström (2): > > > > > drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8) > > > > > drm/i915/gem: Migrate to system at dma-buf attach time (v7) > > > > > > > > Should I push the series? > > > > > > Yes, please. Do we have a solid testing plan for things like this > > > that touch discrete? I tested with mesa+glxgears on my DG1 but > > > haven't run anything more stressful. > > > > I think all we really have are the migration related selftests, and CI > > is not even running them on DG1 due to other breakage. Assuming you > > ran these locally, I think we just merge the series? > > Works for me. Yes, I ran them on my TGL+DG1 box. I've also tested > both GL and Vulkan PRIME support with the client running on DG1 and > the compositor running on TGL with this series and everything works > smooth. And pushed to drm-intel-gt-next. > > --Jason > > > > > > > > --Jason > > > > > > > > > > > > > > > > drivers/gpu/drm/i915/gem/i915_gem_create.c| 177 > > > > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 58 -- > > > > > drivers/gpu/drm/i915/gem/i915_gem_object.c| 20 +- > > > > > drivers/gpu/drm/i915/gem/i915_gem_object.h| 4 + > > > > > drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 +- > > > > > .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 190 > > > > > +- > > > > > .../drm/i915/gem/selftests/i915_gem_migrate.c | 15 -- > > > > > 7 files changed, 341 insertions(+), 136 deletions(-) > > > > > > > > > > -- > > > > > 2.31.1 > > > > > > > > > > ___ > > > > > Intel-gfx mailing list > > > > > Intel-gfx@lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/33] drm/i915/guc: GuC virtual engines
On 7/24/2021 4:13 PM, Matthew Brost wrote:
On Fri, Jul 23, 2021 at 05:47:45PM -0700, Daniele Ceraolo Spurio wrote:
On 7/22/2021 4:53 PM, Matthew Brost wrote:
Implement GuC virtual engines. Rather simple implementation, basically
just allocate an engine, setup context enter / exit function to virtual
engine specific functions, set all other variables / functions to guc
versions, and set the engine mask to that of all the siblings.
v2: Update to work with proto-ctx
v3:
(Daniele)
- Drop include, add comment to intel_virtual_engine_has_heartbeat
Cc: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 8 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 6 +
drivers/gpu/drm/i915/gt/intel_engine.h| 30 ++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 +
.../drm/i915/gt/intel_execlists_submission.c | 29 ++-
.../drm/i915/gt/intel_execlists_submission.h | 4 -
drivers/gpu/drm/i915/gt/selftest_execlists.c | 12 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 244 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 2 +
9 files changed, 313 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 89ca401bf9ae..bc52eeed782a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -74,7 +74,6 @@
#include "gt/intel_context_param.h"
#include "gt/intel_engine_heartbeat.h"
#include "gt/intel_engine_user.h"
-#include "gt/intel_execlists_submission.h" /* virtual_engine */
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
@@ -363,9 +362,6 @@ set_proto_ctx_engines_balance(struct i915_user_extension
__user *base,
if (!HAS_EXECLISTS(i915))
return -ENODEV;
- if (intel_uc_uses_guc_submission(&i915->gt.uc))
- return -ENODEV; /* not implement yet */
-
if (get_user(idx, &ext->engine_index))
return -EFAULT;
@@ -950,8 +946,8 @@ static struct i915_gem_engines *user_engines(struct
i915_gem_context *ctx,
break;
case I915_GEM_ENGINE_TYPE_BALANCED:
- ce = intel_execlists_create_virtual(pe[n].siblings,
- pe[n].num_siblings);
+ ce = intel_engine_create_virtual(pe[n].siblings,
+pe[n].num_siblings);
break;
case I915_GEM_ENGINE_TYPE_INVALID:
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 4a5518d295c2..542c98418771 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -47,6 +47,12 @@ struct intel_context_ops {
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
+
+ /* virtual engine/context interface */
+ struct intel_context *(*create_virtual)(struct intel_engine_cs **engine,
+ unsigned int count);
+ struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine,
+ unsigned int sibling);
};
struct intel_context {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index f911c1224ab2..13bfb7ec33b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -273,13 +273,41 @@ intel_engine_has_preempt_reset(const struct
intel_engine_cs *engine)
return intel_engine_has_preemption(engine);
}
+struct intel_context *
+intel_engine_create_virtual(struct intel_engine_cs **siblings,
+ unsigned int count);
looks like I missed this earlier, but this forward decl seems unneeded.
Not a forward decl, this is a header file which defines a function
implmented in gt/intel_engine_cs.c and used in gem/i915_gem_contexts.c.
It is absolutely needed.
D'oh! My mistake, my mind read this as a .c file because the functions
below are implemented in here. Now I get why it didn't bother me the
first time I reviewed this...
The r-b obviously stands.
Daniele
+
+static inline bool
+intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine)
+{
+ /*
+* For non-GuC submission we expect the back-end to look at the
+* heartbeat status of the actual physical engine that the work
+* has been (or is being) scheduled on, so we should only reach
+* here with GuC submission enabled.
+*/
+ GEM_BUG_ON(!intel_engine_uses_guc(engine));
+
+ return intel_guc_virtual_engine_has_heartbeat(engine);
+}
+
static inline bool
intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
{
if
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On 26/07/2021 16:42, Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 10:30 AM Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
wrote:
On 23/07/2021 20:29, Daniel Vetter wrote:
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_ce to just a
slab_ce.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/gt/intel_context.c | 25 -
drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
drivers/gpu/drm/i915/i915_globals.c | 2 --
drivers/gpu/drm/i915/i915_globals.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 2 ++
5 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index baa05fddd690..283382549a6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -7,7 +7,6 @@
#include "gem/i915_gem_pm.h"
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_context.h"
@@ -15,14 +14,11 @@
#include "intel_engine_pm.h"
#include "intel_ring.h"
-static struct i915_global_context {
- struct i915_global base;
- struct kmem_cache *slab_ce;
-} global;
+struct kmem_cache *slab_ce;
Static? With that,
Reviewed-by: Jason Ekstrand
static struct intel_context *intel_context_alloc(void)
{
- return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
+ return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
}
static void rcu_context_free(struct rcu_head *rcu)
@@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
trace_intel_context_free(ce);
- kmem_cache_free(global.slab_ce, ce);
+ kmem_cache_free(slab_ce, ce);
}
void intel_context_free(struct intel_context *ce)
@@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
i915_active_fini(&ce->active);
}
-static void i915_global_context_exit(void)
+void i915_context_module_exit(void)
{
- kmem_cache_destroy(global.slab_ce);
+ kmem_cache_destroy(slab_ce);
}
-static struct i915_global_context global = { {
- .exit = i915_global_context_exit,
-} };
-
-int __init i915_global_context_init(void)
+int __init i915_context_module_init(void)
{
- global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
- if (!global.slab_ce)
+ slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
+ if (!slab_ce)
return -ENOMEM;
- i915_global_register(&global.base);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 974ef85320c2..a0ca82e3c40d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
struct intel_engine_cs *engine);
void intel_context_fini(struct intel_context *ce);
+void i915_context_module_exit(void);
+int i915_context_module_init(void);
+
struct intel_context *
intel_context_create(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index 3de7cf22ec76..d36eb7dc40aa 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -7,7 +7,6 @@
#include
#include
-#include "gem/i915_gem_context.h"
#include "gem/i915_gem_object.h"
#include "i915_globals.h"
#include "i915_request.h"
@@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_context_init,
i915_global_gem_context_init,
i915_global_objects_init,
i915_global_request_init,
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index d80901ba75e3..60daa738a188 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -23,7 +23,6 @@ int i915_globals_init(void);
void i915_globals_exit(void);
/* constructors */
-int i915_global_context_init(void);
int i915_global_gem_context_init(void);
int i915_global_objects_init(void);
int i915_global_request_init(void);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9527269e30a..266618157775 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -33,6 +33,7 @@
#include "i915_active.h"
#include "i915_buddy.h"
#include "i915_drv.h"
+#include "gem/i915_gem_context.h"
It's a bit ugly to go to a design where i915_pci.c has to include so
many random parts of i915. IMO for a complex driver like i915,
compartmentalizing so much knowledge about the intern
Re: [Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
On 26/07/2021 16:14, Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 3:31 AM Maarten Lankhorst
wrote:
Op 23-07-2021 om 13:34 schreef Matthew Auld:
From: Chris Wilson
Jason Ekstrand requested a more efficient method than userptr+set-domain
to determine if the userptr object was backed by a complete set of pages
upon creation. To be more efficient than simply populating the userptr
using get_user_pages() (as done by the call to set-domain or execbuf),
we can walk the tree of vm_area_struct and check for gaps or vma not
backed by struct page (VM_PFNMAP). The question is how to handle
VM_MIXEDMAP which may be either struct page or pfn backed...
With discrete we are going to drop support for set_domain(), so offering
a way to probe the pages, without having to resort to dummy batches has
been requested.
v2:
- add new query param for the PROBE flag, so userspace can easily
check if the kernel supports it(Jason).
- use mmap_read_{lock, unlock}.
- add some kernel-doc.
v3:
- In the docs also mention that PROBE doesn't guarantee that the pages
will remain valid by the time they are actually used(Tvrtko).
- Add a small comment for the hole finding logic(Jason).
- Move the param next to all the other params which just return true.
Testcase: igt/gem_userptr_blits/probe
Signed-off-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Cc: Daniel Vetter
Cc: Ramalingam C
Reviewed-by: Tvrtko Ursulin
Acked-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 41 -
drivers/gpu/drm/i915/i915_getparam.c| 1 +
include/uapi/drm/i915_drm.h | 20 ++
3 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 56edfeff8c02..468a7a617fbf 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -422,6 +422,34 @@ static const struct drm_i915_gem_object_ops
i915_gem_userptr_ops = {
#endif
+static int
+probe_range(struct mm_struct *mm, unsigned long addr, unsigned long len)
+{
+ const unsigned long end = addr + len;
+ struct vm_area_struct *vma;
+ int ret = -EFAULT;
+
+ mmap_read_lock(mm);
+ for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
+ /* Check for holes, note that we also update the addr below */
+ if (vma->vm_start > addr)
+ break;
+
+ if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
+ break;
+
+ if (vma->vm_end >= end) {
+ ret = 0;
+ break;
+ }
+
+ addr = vma->vm_end;
+ }
+ mmap_read_unlock(mm);
+
+ return ret;
+}
+
/*
* Creates a new mm object that wraps some normal memory from the process
* context - user memory.
@@ -477,7 +505,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
}
if (args->flags & ~(I915_USERPTR_READ_ONLY |
- I915_USERPTR_UNSYNCHRONIZED))
+ I915_USERPTR_UNSYNCHRONIZED |
+ I915_USERPTR_PROBE))
return -EINVAL;
if (i915_gem_object_size_2big(args->user_size))
@@ -504,6 +533,16 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
return -ENODEV;
}
+ if (args->flags & I915_USERPTR_PROBE) {
+ /*
+ * Check that the range pointed to represents real struct
+ * pages and not iomappings (at this moment in time!)
+ */
+ ret = probe_range(current->mm, args->user_ptr, args->user_size);
+ if (ret)
+ return ret;
+ }
+
#ifdef CONFIG_MMU_NOTIFIER
obj = i915_gem_object_alloc();
if (obj == NULL)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c
b/drivers/gpu/drm/i915/i915_getparam.c
index 24e18219eb50..bbb7cac43eb4 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -134,6 +134,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
+ case I915_PARAM_HAS_USERPTR_PROBE:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 975087553ea0..0d290535a6e5 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -674,6 +674,9 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+/* Query if the kernel supports the I915_USE
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On Mon, Jul 26, 2021 at 11:08 AM Tvrtko Ursulin
wrote:
> On 26/07/2021 16:42, Jason Ekstrand wrote:
> > On Mon, Jul 26, 2021 at 10:30 AM Jason Ekstrand
> > wrote:
> >>
> >> On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
> >> wrote:
> >>>
> >>>
> >>> On 23/07/2021 20:29, Daniel Vetter wrote:
> With the global kmem_cache shrink infrastructure gone there's nothing
> special and we can convert them over.
>
> I'm doing this split up into each patch because there's quite a bit of
> noise with removing the static global.slab_ce to just a
> slab_ce.
>
> Cc: Jason Ekstrand
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/i915/gt/intel_context.c | 25 -
> drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
> drivers/gpu/drm/i915/i915_globals.c | 2 --
> drivers/gpu/drm/i915/i915_globals.h | 1 -
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> 5 files changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> b/drivers/gpu/drm/i915/gt/intel_context.c
> index baa05fddd690..283382549a6f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -7,7 +7,6 @@
> #include "gem/i915_gem_pm.h"
>
> #include "i915_drv.h"
> -#include "i915_globals.h"
> #include "i915_trace.h"
>
> #include "intel_context.h"
> @@ -15,14 +14,11 @@
> #include "intel_engine_pm.h"
> #include "intel_ring.h"
>
> -static struct i915_global_context {
> - struct i915_global base;
> - struct kmem_cache *slab_ce;
> -} global;
> +struct kmem_cache *slab_ce;
> >>
> >> Static? With that,
> >>
> >> Reviewed-by: Jason Ekstrand
> >>
>
> static struct intel_context *intel_context_alloc(void)
> {
> - return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
> + return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
> }
>
> static void rcu_context_free(struct rcu_head *rcu)
> @@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
> struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
>
> trace_intel_context_free(ce);
> - kmem_cache_free(global.slab_ce, ce);
> + kmem_cache_free(slab_ce, ce);
> }
>
> void intel_context_free(struct intel_context *ce)
> @@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
> i915_active_fini(&ce->active);
> }
>
> -static void i915_global_context_exit(void)
> +void i915_context_module_exit(void)
> {
> - kmem_cache_destroy(global.slab_ce);
> + kmem_cache_destroy(slab_ce);
> }
>
> -static struct i915_global_context global = { {
> - .exit = i915_global_context_exit,
> -} };
> -
> -int __init i915_global_context_init(void)
> +int __init i915_context_module_init(void)
> {
> - global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> - if (!global.slab_ce)
> + slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> + if (!slab_ce)
> return -ENOMEM;
>
> - i915_global_register(&global.base);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> b/drivers/gpu/drm/i915/gt/intel_context.h
> index 974ef85320c2..a0ca82e3c40d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> @@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
> struct intel_engine_cs *engine);
> void intel_context_fini(struct intel_context *ce);
>
> +void i915_context_module_exit(void);
> +int i915_context_module_init(void);
> +
> struct intel_context *
> intel_context_create(struct intel_engine_cs *engine);
>
> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> b/drivers/gpu/drm/i915/i915_globals.c
> index 3de7cf22ec76..d36eb7dc40aa 100644
> --- a/drivers/gpu/drm/i915/i915_globals.c
> +++ b/drivers/gpu/drm/i915/i915_globals.c
> @@ -7,7 +7,6 @@
> #include
> #include
>
> -#include "gem/i915_gem_context.h"
> #include "gem/i915_gem_object.h"
> #include "i915_globals.h"
> #include "i915_request.h"
> @@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
> }
>
> static __initconst int (* const initfn[])(void) = {
> - i915_global_context_init,
> i915_global_gem_context_init,
> i915_global_objects_init,
> i915_global_request_init,
> diff --git a/drivers/gpu/drm/i915/i915_globals.h
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On 26/07/2021 17:20, Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 11:08 AM Tvrtko Ursulin
wrote:
On 26/07/2021 16:42, Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 10:30 AM Jason Ekstrand wrote:
On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
wrote:
On 23/07/2021 20:29, Daniel Vetter wrote:
With the global kmem_cache shrink infrastructure gone there's nothing
special and we can convert them over.
I'm doing this split up into each patch because there's quite a bit of
noise with removing the static global.slab_ce to just a
slab_ce.
Cc: Jason Ekstrand
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/i915/gt/intel_context.c | 25 -
drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
drivers/gpu/drm/i915/i915_globals.c | 2 --
drivers/gpu/drm/i915/i915_globals.h | 1 -
drivers/gpu/drm/i915/i915_pci.c | 2 ++
5 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index baa05fddd690..283382549a6f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -7,7 +7,6 @@
#include "gem/i915_gem_pm.h"
#include "i915_drv.h"
-#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_context.h"
@@ -15,14 +14,11 @@
#include "intel_engine_pm.h"
#include "intel_ring.h"
-static struct i915_global_context {
- struct i915_global base;
- struct kmem_cache *slab_ce;
-} global;
+struct kmem_cache *slab_ce;
Static? With that,
Reviewed-by: Jason Ekstrand
static struct intel_context *intel_context_alloc(void)
{
- return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
+ return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
}
static void rcu_context_free(struct rcu_head *rcu)
@@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
trace_intel_context_free(ce);
- kmem_cache_free(global.slab_ce, ce);
+ kmem_cache_free(slab_ce, ce);
}
void intel_context_free(struct intel_context *ce)
@@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
i915_active_fini(&ce->active);
}
-static void i915_global_context_exit(void)
+void i915_context_module_exit(void)
{
- kmem_cache_destroy(global.slab_ce);
+ kmem_cache_destroy(slab_ce);
}
-static struct i915_global_context global = { {
- .exit = i915_global_context_exit,
-} };
-
-int __init i915_global_context_init(void)
+int __init i915_context_module_init(void)
{
- global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
- if (!global.slab_ce)
+ slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
+ if (!slab_ce)
return -ENOMEM;
- i915_global_register(&global.base);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 974ef85320c2..a0ca82e3c40d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
struct intel_engine_cs *engine);
void intel_context_fini(struct intel_context *ce);
+void i915_context_module_exit(void);
+int i915_context_module_init(void);
+
struct intel_context *
intel_context_create(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/i915_globals.c
b/drivers/gpu/drm/i915/i915_globals.c
index 3de7cf22ec76..d36eb7dc40aa 100644
--- a/drivers/gpu/drm/i915/i915_globals.c
+++ b/drivers/gpu/drm/i915/i915_globals.c
@@ -7,7 +7,6 @@
#include
#include
-#include "gem/i915_gem_context.h"
#include "gem/i915_gem_object.h"
#include "i915_globals.h"
#include "i915_request.h"
@@ -32,7 +31,6 @@ static void __i915_globals_cleanup(void)
}
static __initconst int (* const initfn[])(void) = {
- i915_global_context_init,
i915_global_gem_context_init,
i915_global_objects_init,
i915_global_request_init,
diff --git a/drivers/gpu/drm/i915/i915_globals.h
b/drivers/gpu/drm/i915/i915_globals.h
index d80901ba75e3..60daa738a188 100644
--- a/drivers/gpu/drm/i915/i915_globals.h
+++ b/drivers/gpu/drm/i915/i915_globals.h
@@ -23,7 +23,6 @@ int i915_globals_init(void);
void i915_globals_exit(void);
/* constructors */
-int i915_global_context_init(void);
int i915_global_gem_context_init(void);
int i915_global_objects_init(void);
int i915_global_request_init(void);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f9527269e30a..266618157775 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -33,6 +33,7 @@
#include "i915_active.h"
#include "i915_buddy.h"
#include "i915_drv.h"
+#include "gem/i915_gem_context.h"
It's a bit ugly to go to a design
Re: [Intel-gfx] [PATCH 25/33] drm/i915/guc: Support request cancellation
On 7/22/2021 4:54 PM, Matthew Brost wrote:
This adds GuC backend support for i915_request_cancel(), which in turn
makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
This implemenation makes use of fence while there is likely simplier
options. A fence was choosen because of another feature coming soon
which requires a user to block on a context until scheduling is
disabled. In that case we return the fence to the user and the user can
wait on that fence.
v2:
(Daniele)
- A comment about locking the blocked incr / decr
- A comments about the use of the fence
- Update commit message explaining why fence
- Delete redundant check blocked count in unblock function
- Ring buffer implementation
- Comment about blocked in submission path
- Shorter rpm path
Signed-off-by: Matthew Brost
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 13 ++
drivers/gpu/drm/i915/gt/intel_context.h | 7 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +
.../drm/i915/gt/intel_execlists_submission.c | 18 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 16 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 175 ++
drivers/gpu/drm/i915/i915_request.c | 14 +-
7 files changed, 237 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 237b70e98744..477c42d7d693 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -366,6 +366,12 @@ static int __intel_context_active(struct i915_active
*active)
return 0;
}
+static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
+enum i915_sw_fence_notify state)
+{
+ return NOTIFY_DONE;
+}
+
void
intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
{
@@ -399,6 +405,13 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
ce->guc_id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(&ce->guc_id_link);
+ /*
+* Initialize fence to be complete as this is expected to be complete
+* unless there is a pending schedule disable outstanding.
+*/
+ i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
+ i915_sw_fence_commit(&ce->guc_blocked);
+
i915_active_init(&ce->active,
__intel_context_active, __intel_context_retire, 0);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 814d9277096a..876bdb08303c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -70,6 +70,13 @@ intel_context_is_pinned(struct intel_context *ce)
return atomic_read(&ce->pin_count);
}
+static inline void intel_context_cancel_request(struct intel_context *ce,
+ struct i915_request *rq)
+{
+ GEM_BUG_ON(!ce->ops->cancel_request);
+ return ce->ops->cancel_request(ce, rq);
+}
+
/**
* intel_context_unlock_pinned - Releases the earlier locking of 'pinned'
status
* @ce - the context
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 57c19ee3e313..005a64f2afa7 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -13,6 +13,7 @@
#include
#include "i915_active_types.h"
+#include "i915_sw_fence.h"
#include "i915_utils.h"
#include "intel_engine_types.h"
#include "intel_sseu.h"
@@ -42,6 +43,9 @@ struct intel_context_ops {
void (*unpin)(struct intel_context *ce);
void (*post_unpin)(struct intel_context *ce);
+ void (*cancel_request)(struct intel_context *ce,
+ struct i915_request *rq);
+
void (*enter)(struct intel_context *ce);
void (*exit)(struct intel_context *ce);
@@ -184,6 +188,9 @@ struct intel_context {
* GuC ID link - in list when unpinned but guc_id still valid in GuC
*/
struct list_head guc_id_link;
+
+ /* GuC context blocked fence */
+ struct i915_sw_fence guc_blocked;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 60427b106bad..e7b4b71d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -114,6 +114,7 @@
#include "gen8_engine_cs.h"
#include "intel_breadcrumbs.h"
#include "intel_context.h"
+#include "intel_engine_heartbeat.h"
#include "intel_engine_pm.h"
#include "intel_engine_stats.h"
#include "intel_execlists_submission.h"
@@ -2587,11 +2588,26 @@ static int execlists_context_alloc(struct intel_context
*ce)
return lrc_alloc(ce, ce->engine);
}
+static void execlists_context_cancel_r
Re: [Intel-gfx] [PATCH 25/33] drm/i915/guc: Support request cancellation
On Mon, Jul 26, 2021 at 10:49:37AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/22/2021 4:54 PM, Matthew Brost wrote:
> > This adds GuC backend support for i915_request_cancel(), which in turn
> > makes CONFIG_DRM_I915_REQUEST_TIMEOUT work.
> >
> > This implemenation makes use of fence while there is likely simplier
> > options. A fence was choosen because of another feature coming soon
> > which requires a user to block on a context until scheduling is
> > disabled. In that case we return the fence to the user and the user can
> > wait on that fence.
> >
> > v2:
> > (Daniele)
> >- A comment about locking the blocked incr / decr
> >- A comments about the use of the fence
> >- Update commit message explaining why fence
> >- Delete redundant check blocked count in unblock function
> >- Ring buffer implementation
> >- Comment about blocked in submission path
> >- Shorter rpm path
> >
> > Signed-off-by: Matthew Brost
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gt/intel_context.c | 13 ++
> > drivers/gpu/drm/i915/gt/intel_context.h | 7 +
> > drivers/gpu/drm/i915/gt/intel_context_types.h | 7 +
> > .../drm/i915/gt/intel_execlists_submission.c | 18 ++
> > .../gpu/drm/i915/gt/intel_ring_submission.c | 16 ++
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 175 ++
> > drivers/gpu/drm/i915/i915_request.c | 14 +-
> > 7 files changed, 237 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> > b/drivers/gpu/drm/i915/gt/intel_context.c
> > index 237b70e98744..477c42d7d693 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> > @@ -366,6 +366,12 @@ static int __intel_context_active(struct i915_active
> > *active)
> > return 0;
> > }
> > +static int sw_fence_dummy_notify(struct i915_sw_fence *sf,
> > +enum i915_sw_fence_notify state)
> > +{
> > + return NOTIFY_DONE;
> > +}
> > +
> > void
> > intel_context_init(struct intel_context *ce, struct intel_engine_cs
> > *engine)
> > {
> > @@ -399,6 +405,13 @@ intel_context_init(struct intel_context *ce, struct
> > intel_engine_cs *engine)
> > ce->guc_id = GUC_INVALID_LRC_ID;
> > INIT_LIST_HEAD(&ce->guc_id_link);
> > + /*
> > +* Initialize fence to be complete as this is expected to be complete
> > +* unless there is a pending schedule disable outstanding.
> > +*/
> > + i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
> > + i915_sw_fence_commit(&ce->guc_blocked);
> > +
> > i915_active_init(&ce->active,
> > __intel_context_active, __intel_context_retire, 0);
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> > b/drivers/gpu/drm/i915/gt/intel_context.h
> > index 814d9277096a..876bdb08303c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> > @@ -70,6 +70,13 @@ intel_context_is_pinned(struct intel_context *ce)
> > return atomic_read(&ce->pin_count);
> > }
> > +static inline void intel_context_cancel_request(struct intel_context *ce,
> > + struct i915_request *rq)
> > +{
> > + GEM_BUG_ON(!ce->ops->cancel_request);
> > + return ce->ops->cancel_request(ce, rq);
> > +}
> > +
> > /**
> >* intel_context_unlock_pinned - Releases the earlier locking of 'pinned'
> > status
> >* @ce - the context
> > diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > index 57c19ee3e313..005a64f2afa7 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> > @@ -13,6 +13,7 @@
> > #include
> > #include "i915_active_types.h"
> > +#include "i915_sw_fence.h"
> > #include "i915_utils.h"
> > #include "intel_engine_types.h"
> > #include "intel_sseu.h"
> > @@ -42,6 +43,9 @@ struct intel_context_ops {
> > void (*unpin)(struct intel_context *ce);
> > void (*post_unpin)(struct intel_context *ce);
> > + void (*cancel_request)(struct intel_context *ce,
> > + struct i915_request *rq);
> > +
> > void (*enter)(struct intel_context *ce);
> > void (*exit)(struct intel_context *ce);
> > @@ -184,6 +188,9 @@ struct intel_context {
> > * GuC ID link - in list when unpinned but guc_id still valid in GuC
> > */
> > struct list_head guc_id_link;
> > +
> > + /* GuC context blocked fence */
> > + struct i915_sw_fence guc_blocked;
> > };
> > #endif /* __INTEL_CONTEXT_TYPES__ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > index 60427b106bad..e7b4b71d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > @@ -114,6
[Intel-gfx] [PATCH] drm/i915/display: Disable audio, DRRS and PSR before planes
HDMI and DisplayPort sequences states that audio and PSR should be
disabled before planes are disabled.
Not following it did not caused any problems up to Alderlake-P but
for this platform it causes underruns during the PSR2 disable
sequence.
Specification don't mention that DRRS should be disabled before planes
but it looks safer to switch back to the default refresh rate before
following with the rest of the pipe disable sequence.
BSpec: 49191
BSpec: 49190
Cc: Ville Syrjälä
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 30 ---
drivers/gpu/drm/i915/display/intel_display.c | 24 +++
.../drm/i915/display/intel_display_types.h| 4 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++--
4 files changed, 59 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 26a3aa73fcc43..061a663f43b84 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3204,12 +3204,6 @@ static void intel_disable_ddi_dp(struct
intel_atomic_state *state,
intel_dp->link_trained = false;
- if (old_crtc_state->has_audio)
- intel_audio_codec_disable(encoder,
- old_crtc_state, old_conn_state);
-
- intel_edp_drrs_disable(intel_dp, old_crtc_state);
- intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
/* Disable the decompression in DP Sink */
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
@@ -3227,10 +3221,6 @@ static void intel_disable_ddi_hdmi(struct
intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct drm_connector *connector = old_conn_state->connector;
- if (old_crtc_state->has_audio)
- intel_audio_codec_disable(encoder,
- old_crtc_state, old_conn_state);
-
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
false, false))
drm_dbg_kms(&i915->drm,
@@ -3238,6 +3228,25 @@ static void intel_disable_ddi_hdmi(struct
intel_atomic_state *state,
connector->base.id, connector->name);
}
+static void intel_pre_disable_ddi(struct intel_atomic_state *state,
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state
*old_conn_state)
+{
+ struct intel_dp *intel_dp;
+
+ if (old_crtc_state->has_audio)
+ intel_audio_codec_disable(encoder, old_crtc_state,
+ old_conn_state);
+
+ if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
+ return;
+
+ intel_dp = enc_to_intel_dp(encoder);
+ intel_edp_drrs_disable(intel_dp, old_crtc_state);
+ intel_psr_disable(intel_dp, old_crtc_state);
+}
+
static void intel_disable_ddi(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -4590,6 +4599,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->enable = intel_enable_ddi;
encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
encoder->pre_enable = intel_ddi_pre_enable;
+ encoder->pre_disable = intel_pre_disable_ddi;
encoder->disable = intel_disable_ddi;
encoder->post_disable = intel_ddi_post_disable;
encoder->update_pipe = intel_ddi_update_pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bb0aebcc3ecd3..cf58df9132748 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3195,6 +3195,28 @@ static void intel_encoders_enable(struct
intel_atomic_state *state,
}
}
+static void intel_encoders_pre_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
+ struct drm_connector *conn;
+ int i;
+
+ for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
+ struct intel_encoder *encoder =
+ to_intel_encoder(old_conn_state->best_encoder);
+
+ if (old_conn_state->crtc != &crtc->base)
+ continue;
+
+ if (encoder->pre_disable)
+ encoder->pre_disable(state, encoder, old_crtc_state,
+
Re: [Intel-gfx] [PATCH 04/10] drm/i915: move intel_context slab to direct module init/exit
On Mon, Jul 26, 2021 at 11:31 AM Tvrtko Ursulin
wrote:
>
>
> On 26/07/2021 17:20, Jason Ekstrand wrote:
> > On Mon, Jul 26, 2021 at 11:08 AM Tvrtko Ursulin
> > wrote:
> >> On 26/07/2021 16:42, Jason Ekstrand wrote:
> >>> On Mon, Jul 26, 2021 at 10:30 AM Jason Ekstrand
> >>> wrote:
>
> On Mon, Jul 26, 2021 at 3:35 AM Tvrtko Ursulin
> wrote:
> >
> >
> > On 23/07/2021 20:29, Daniel Vetter wrote:
> >> With the global kmem_cache shrink infrastructure gone there's nothing
> >> special and we can convert them over.
> >>
> >> I'm doing this split up into each patch because there's quite a bit of
> >> noise with removing the static global.slab_ce to just a
> >> slab_ce.
> >>
> >> Cc: Jason Ekstrand
> >> Signed-off-by: Daniel Vetter
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_context.c | 25
> >> -
> >> drivers/gpu/drm/i915/gt/intel_context.h | 3 +++
> >> drivers/gpu/drm/i915/i915_globals.c | 2 --
> >> drivers/gpu/drm/i915/i915_globals.h | 1 -
> >> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> >> 5 files changed, 13 insertions(+), 20 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
> >> b/drivers/gpu/drm/i915/gt/intel_context.c
> >> index baa05fddd690..283382549a6f 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> >> @@ -7,7 +7,6 @@
> >> #include "gem/i915_gem_pm.h"
> >>
> >> #include "i915_drv.h"
> >> -#include "i915_globals.h"
> >> #include "i915_trace.h"
> >>
> >> #include "intel_context.h"
> >> @@ -15,14 +14,11 @@
> >> #include "intel_engine_pm.h"
> >> #include "intel_ring.h"
> >>
> >> -static struct i915_global_context {
> >> - struct i915_global base;
> >> - struct kmem_cache *slab_ce;
> >> -} global;
> >> +struct kmem_cache *slab_ce;
>
> Static? With that,
>
> Reviewed-by: Jason Ekstrand
>
> >>
> >> static struct intel_context *intel_context_alloc(void)
> >> {
> >> - return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
> >> + return kmem_cache_zalloc(slab_ce, GFP_KERNEL);
> >> }
> >>
> >> static void rcu_context_free(struct rcu_head *rcu)
> >> @@ -30,7 +26,7 @@ static void rcu_context_free(struct rcu_head *rcu)
> >> struct intel_context *ce = container_of(rcu, typeof(*ce), rcu);
> >>
> >> trace_intel_context_free(ce);
> >> - kmem_cache_free(global.slab_ce, ce);
> >> + kmem_cache_free(slab_ce, ce);
> >> }
> >>
> >> void intel_context_free(struct intel_context *ce)
> >> @@ -410,22 +406,17 @@ void intel_context_fini(struct intel_context *ce)
> >> i915_active_fini(&ce->active);
> >> }
> >>
> >> -static void i915_global_context_exit(void)
> >> +void i915_context_module_exit(void)
> >> {
> >> - kmem_cache_destroy(global.slab_ce);
> >> + kmem_cache_destroy(slab_ce);
> >> }
> >>
> >> -static struct i915_global_context global = { {
> >> - .exit = i915_global_context_exit,
> >> -} };
> >> -
> >> -int __init i915_global_context_init(void)
> >> +int __init i915_context_module_init(void)
> >> {
> >> - global.slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> >> - if (!global.slab_ce)
> >> + slab_ce = KMEM_CACHE(intel_context, SLAB_HWCACHE_ALIGN);
> >> + if (!slab_ce)
> >> return -ENOMEM;
> >>
> >> - i915_global_register(&global.base);
> >> return 0;
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
> >> b/drivers/gpu/drm/i915/gt/intel_context.h
> >> index 974ef85320c2..a0ca82e3c40d 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> >> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> >> @@ -30,6 +30,9 @@ void intel_context_init(struct intel_context *ce,
> >> struct intel_engine_cs *engine);
> >> void intel_context_fini(struct intel_context *ce);
> >>
> >> +void i915_context_module_exit(void);
> >> +int i915_context_module_init(void);
> >> +
> >> struct intel_context *
> >> intel_context_create(struct intel_engine_cs *engine);
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_globals.c
> >> b/drivers/gpu/drm/i915/i915_globals.c
> >> index 3de7cf22ec76..d36eb7dc40aa 100644
> >> --- a/drivers/gpu/drm/i915/i915_globals.c
> >> +++ b/drivers/gpu/drm/i915/i915_globals.c
> >> @@ -7,7 +7,6 @@
> >> #include
> >> #include
> >>
> >> -#include "gem/i915_gem_context.h"
> >> #include "gem/i915_gem_object.h"
> >> #include "i915_glo
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Disable audio, DRRS and PSR before planes
== Series Details == Series: drm/i915/display: Disable audio, DRRS and PSR before planes URL : https://patchwork.freedesktop.org/series/93024/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4b987bbf5ee8 drm/i915/display: Disable audio, DRRS and PSR before planes -:137: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_atomic_state *' should also have an identifier name #137: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:199: + void (*pre_disable)(struct intel_atomic_state *, -:137: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_encoder *' should also have an identifier name #137: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:199: + void (*pre_disable)(struct intel_atomic_state *, -:137: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct intel_crtc_state *' should also have an identifier name #137: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:199: + void (*pre_disable)(struct intel_atomic_state *, -:137: WARNING:FUNCTION_ARGUMENTS: function definition argument 'const struct drm_connector_state *' should also have an identifier name #137: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:199: + void (*pre_disable)(struct intel_atomic_state *, total: 0 errors, 4 warnings, 0 checks, 132 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/display: Drop redundant debug print
drm_dp_dpcd_read/write already has debug error message.
Drop redundant error messages which gives false
status even if correct value is read in drm_dp_dpcd_read().
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index c386ef8eb200..5c84f51ad41d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3871,16 +3871,12 @@ static void intel_dp_check_link_service_irq(struct
intel_dp *intel_dp)
return;
if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 ||
!val) {
- drm_dbg_kms(&i915->drm, "Error in reading link service irq
vector\n");
+ DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 ||
!val)
return;
- }
if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) {
- drm_dbg_kms(&i915->drm, "Error in writing link service irq
vector\n");
+ DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
return;
- }
if (val & HDMI_LINK_STATUS_CHANGED)
intel_dp_handle_hdmi_link_status_change(intel_dp);
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display: Drop redundant debug print
== Series Details == Series: drm/i915/display: Drop redundant debug print URL : https://patchwork.freedesktop.org/series/93025/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/display/intel_dp.o drivers/gpu/drm/i915/display/intel_dp.c: In function ‘intel_dp_check_link_service_irq’: drivers/gpu/drm/i915/display/intel_dp.c:3867:27: error: unused variable ‘i915’ [-Werror=unused-variable] struct drm_i915_private *i915 = dp_to_i915(intel_dp); ^~~~ cc1: all warnings being treated as errors scripts/Makefile.build:271: recipe for target 'drivers/gpu/drm/i915/display/intel_dp.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_dp.o] Error 1 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:514: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1842: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Disable audio, DRRS and PSR before planes
== Series Details == Series: drm/i915/display: Disable audio, DRRS and PSR before planes URL : https://patchwork.freedesktop.org/series/93024/ State : success == Summary == CI Bug Log - changes from CI_DRM_10396 -> Patchwork_20705 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20705/index.html Known issues Here are the changes found in Patchwork_20705 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#1372]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10396/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20705/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [DMESG-FAIL][3] ([i915#165]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10396/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20705/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 Participating hosts (39 -> 35) -- Missing(4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Build changes - * Linux: CI_DRM_10396 -> Patchwork_20705 CI-20190529: 20190529 CI_DRM_10396: a119adff94c9db72f198ddde3dbb0a3e51c56618 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6151: c3170c2d3744521b8351a4b9c579792bc9a5f835 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_20705: 4b987bbf5ee886fe98a743f73849a03ec30de6db @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4b987bbf5ee8 drm/i915/display: Disable audio, DRRS and PSR before planes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20705/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 00/15] drm/i915/guc/slpc: Enable GuC based power management features
This series enables Single Loop Power Control (SLPC) feature in GuC. GuC implements various power management algorithms as part of it's operation. These need to be specifically enabled by KMD. They replace the legacy host based management of these features. With this series, we will enable two PM features - GTPerf and GuCRC. These are the Turbo and RC6 equivalents of the host based version. GuC provides various interfaces via host-to-guc messaging, which allows KMD to enable these features after GuC is loaded and GuC submission is enabled. We will specifically disable the IA/GT Balancer and Duty Cycle control features in SLPC. To enable GTPerf, KMD sends a specific h2g message after setting up some shared data structures. As part of this, we will gate host RPS as well. GuC takes over the duties of requesting frequencies by monitoring GPU busyness. We can influence what GuC requests by modifying the min and max frequencies setup by SLPC through the sysfs interfaces that have been exposed by legacy Turbo. SLPC typically requests efficient frequency instead of minimum frequency to optimize performance. It also does not necessarily stick to platform max, and can request frequencies that are much higher since pcode will ultimately grant the appropriate values. However, we will force it to adhere to platform min and max values so as to maintain legacy behavior. SLPC does not have the concept of waitboost, so the boost_freq sysfs will show a '0' value for now. There is a patch forthcoming to ensure the interface is not exposed when SLPC is enabled. GuCRC is enabled similarly through a h2g message. We still need to enable RC6 feature bit (GEN6_RC_CTL_RC6_ENABLE) before we send this out. Render/Media power gating still needs to be enabled by host as before. GuC will take care of setting up the hysterisis values for RC6, host does not need to set this up anymore. v2: Address review comments (Michal W) v3: More comments, optimizations (Michal W) Signed-off-by: Vinay Belgaumkar Matthew Brost (1): drm/i915/guc: SQUASHED PATCH - DO NOT REVIEW Vinay Belgaumkar (14): drm/i915/guc/slpc: Initial definitions for SLPC drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled drm/i915/guc/slpc: Adding SLPC communication interfaces drm/i915/guc/slpc: Allocate, initialize and release SLPC drm/i915/guc/slpc: Enable SLPC and add related H2G events drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable drm/i915/guc/slpc: Add methods to set min/max frequency drm/i915/guc/slpc: Add get max/min freq hooks drm/i915/guc/slpc: Add debugfs for SLPC info drm/i915/guc/slpc: Enable ARAT timer interrupt drm/i915/guc/slpc: Cache platform frequency limits drm/i915/guc/slpc: Sysfs hooks for SLPC drm/i915/guc/slpc: Add SLPC selftest drm/i915/guc/rc: Setup and enable GUCRC feature drivers/gpu/drm/i915/Makefile |3 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 44 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.h | 16 +- .../gpu/drm/i915/gt/intel_breadcrumbs_types.h |7 + drivers/gpu/drm/i915/gt/intel_context.c | 36 + drivers/gpu/drm/i915/gt/intel_context.h | 23 + drivers/gpu/drm/i915/gt/intel_context_types.h | 31 +- drivers/gpu/drm/i915/gt/intel_engine.h| 57 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 183 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 70 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.h |4 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +- drivers/gpu/drm/i915/gt/intel_engine_user.c |4 + .../drm/i915/gt/intel_execlists_submission.c | 89 +- .../drm/i915/gt/intel_execlists_submission.h |4 - drivers/gpu/drm/i915/gt/intel_gt.c|4 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c |6 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +- drivers/gpu/drm/i915/gt/intel_reset.c | 50 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 58 + drivers/gpu/drm/i915/gt/intel_rps.c | 190 ++ drivers/gpu/drm/i915/gt/intel_rps.h | 11 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 +- .../gpu/drm/i915/gt/intel_workarounds_types.h |1 + drivers/gpu/drm/i915/gt/mock_engine.c | 34 +- .../drm/i915/gt/selftest_engine_heartbeat.c | 22 + .../drm/i915/gt/selftest_engine_heartbeat.h |2 + drivers/gpu/drm/i915/gt/selftest_execlists.c | 12 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 322 +++- drivers/gpu/drm/i915/gt/selftest_mocs.c | 50 +- drivers/gpu/drm/i915/gt/selftest_slpc.c | 311 drivers/gpu/drm/i915/gt/selftest_slpc.h | 12 + .../gpu/drm/i915/gt/selftest_workarounds.c| 132 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h |8 +- .../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 +++ drivers/gpu/drm/i915/gt/uc/intel_guc.c| 99 +- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 44 +- drivers/g
[Intel-gfx] [PATCH 02/15] drm/i915/guc/slpc: Initial definitions for SLPC
Add macros to check for SLPC support. This feature is currently supported
for Gen12+ and enabled whenever GuC submission is enabled/selected.
Include templates for SLPC init/fini and enable.
v2: Move SLPC helper functions to intel_guc_slpc.c/.h. Define basic
template for SLPC structure in intel_guc_slpc_types.h. Fix copyright (Michal W)
v3: Review comments (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Daniele Ceraolo Spurio
drm/i915/guc/slpc: Lay out slpc init/enable/fini
Declare init/fini and enable function templates.
v2: Rebase
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 45 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 33 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 12 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
8 files changed, 103 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ab7679957623..d8eac4468df9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
gt/uc/intel_huc_debugfs.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 979128e28372..39bc3c16057b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -7,6 +7,7 @@
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm_irq.h"
#include "intel_guc.h"
+#include "intel_guc_slpc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
@@ -157,6 +158,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
intel_guc_submission_init_early(guc);
+ intel_guc_slpc_init_early(&guc->slpc);
mutex_init(&guc->send_mutex);
spin_lock_init(&guc->irq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index a9547069ee7e..15ad2eaee473 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -15,6 +15,7 @@
#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
+#include "intel_guc_slpc_types.h"
#include "intel_uc_fw.h"
#include "i915_utils.h"
#include "i915_vma.h"
@@ -30,6 +31,7 @@ struct intel_guc {
struct intel_uc_fw fw;
struct intel_guc_log log;
struct intel_guc_ct ct;
+ struct intel_guc_slpc slpc;
/* Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
@@ -57,6 +59,8 @@ struct intel_guc {
bool submission_supported;
bool submission_selected;
+ bool slpc_supported;
+ bool slpc_selected;
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
new file mode 100644
index ..7275100ef8f8
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_guc_slpc.h"
+#include "gt/intel_gt.h"
+
+static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
+{
+ return container_of(slpc, struct intel_guc, slpc);
+}
+
+static bool __detect_slpc_supported(struct intel_guc *guc)
+{
+ /* GuC SLPC is unavailable for pre-Gen12 */
+ return guc->submission_supported &&
+ GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
+}
+
+static bool __guc_slpc_selected(struct intel_guc *guc)
+{
+ if (!intel_guc_slpc_is_supported(guc))
+ return false;
+
+ return guc->submission_selected;
+}
+
+void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ guc->slpc_supported = __detect_slpc_supported(guc);
+ guc->slpc_selected = __guc_slpc_selected(guc);
+}
+
+int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
+{
+ return 0;
+}
+
+void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
+{
+}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drive
[Intel-gfx] [PATCH 03/15] drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled
Also ensure uc_init is called before we initialize RPS so that we
can check for SLPC support. We do not need to enable up/down
interrupts when SLPC is enabled. However, we still need the ARAT
interrupt, which will be enabled separately later.
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 20
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a64aa43f7cd9..04dd69bcf6cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -41,8 +41,8 @@ void intel_gt_init_early(struct intel_gt *gt, struct
drm_i915_private *i915)
intel_gt_init_timelines(gt);
intel_gt_pm_init_early(gt);
- intel_rps_init_early(>->rps);
intel_uc_init_early(>->uc);
+ intel_rps_init_early(>->rps);
}
int intel_gt_probe_lmem(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 0c8e7f2b06f0..e858eeb2c59d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
*rps)
return rps_to_gt(rps)->uncore;
}
+static bool rps_uses_slpc(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+
+ return intel_uc_uses_guc_slpc(>->uc);
+}
+
static u32 rps_pm_sanitize_mask(struct intel_rps *rps, u32 mask)
{
return mask & ~rps->pm_intrmsk_mbz;
@@ -167,6 +174,8 @@ static void rps_enable_interrupts(struct intel_rps *rps)
{
struct intel_gt *gt = rps_to_gt(rps);
+ GEM_BUG_ON(rps_uses_slpc(rps));
+
GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
rps->pm_events, rps_pm_mask(rps, rps->last_freq));
@@ -771,6 +780,8 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 swreq;
+ GEM_BUG_ON(rps_uses_slpc(rps));
+
if (GRAPHICS_VER(i915) >= 9)
swreq = GEN9_FREQUENCY(val);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -861,6 +872,9 @@ void intel_rps_park(struct intel_rps *rps)
{
int adj;
+ if (!intel_rps_is_enabled(rps))
+ return;
+
GEM_BUG_ON(atomic_read(&rps->num_waiters));
if (!intel_rps_clear_active(rps))
@@ -1829,6 +1843,9 @@ void intel_rps_init(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
+ if (rps_uses_slpc(rps))
+ return;
+
if (IS_CHERRYVIEW(i915))
chv_rps_init(rps);
else if (IS_VALLEYVIEW(i915))
@@ -1885,6 +1902,9 @@ void intel_rps_init(struct intel_rps *rps)
void intel_rps_sanitize(struct intel_rps *rps)
{
+ if (rps_uses_slpc(rps))
+ return;
+
if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
rps_disable_interrupts(rps);
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/15] drm/i915/guc/slpc: Adding SLPC communication interfaces
Add constants and params that are needed to configure SLPC.
v2: Add a new abi header for SLPC. Replace bitfields with
genmasks. Address other comments from Michal W.
v3: Add slpc H2G format in abi, other review commments (Michal W)
v4: Update status bits according to latest spec
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 1 -
.../drm/i915/gt/uc/abi/guc_actions_slpc_abi.h | 235 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 3 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 7 +
4 files changed, 245 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index d832c8f11c11..ca538e5de940 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -135,7 +135,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
- INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
new file mode 100644
index ..70b300d4a536
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
@@ -0,0 +1,235 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _GUC_ACTIONS_SLPC_ABI_H_
+#define _GUC_ACTIONS_SLPC_ABI_H_
+
+#include
+
+/**
+ * DOC: SLPC SHARED DATA STRUCTURE
+ *
+ *
++--+--+
+ * | CL | Bytes| Description
|
+ *
++==+==+
+ * | 1 | 0-3 | SHARED DATA SIZE
|
+ * |
+--+--+
+ * || 4-7 | GLOBAL STATE
|
+ * |
+--+--+
+ * || 8-11 | DISPLAY DATA ADDRESS
|
+ * |
+--+--+
+ * || 12:63| PADDING
|
+ *
++--+--+
+ * || 0:63 | PADDING(PLATFORM INFO)
|
+ *
++--+--+
+ * | 3 | 0-3 | TASK STATE DATA
|
+ * +
+--+--+
+ * || 4:63 | PADDING
|
+ *
++--+--+
+ * |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS
|
+ *
++--+--+
+ * || | PADDING + EXTRA RESERVED PAGE
|
+ *
++--+--+
+ */
+
+/*
+ * SLPC exposes certain parameters for global configuration by the host.
+ * These are referred to as override parameters, because in most cases
+ * the host will not need to modify the default values used by SLPC.
+ * SLPC remembers the default values which allows the host to easily restore
+ * them by simply unsetting the override. The host can set or unset override
+ * parameters during SLPC (re-)initialization using the SLPC Reset event.
+ * The host can also set or unset override parameters on the fly using the
+ * Parameter Set and Parameter Unset events
+ */
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 256
+#define SLPC_OVERRIDE_BITFIELD_SIZE \
+ (SLPC_MAX_OVERRIDE_PARAMETERS / 32)
+
+#define SLPC_PAGE_SIZE_BYTES 4096
+#define SLPC_CACHELINE_SIZE_BYTES 64
+#define SLPC_SHARED_DATA_SIZE_BYTE_HEADER SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO
SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE SLPC_CACHELINE_SIZE_BYTES
+#define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE SLPC_PAGE_SIZE_BYTES
+#define SLPC_SHARED_DATA_SIZE_BYTE_MAX (2 * SLPC_PAGE_SIZE_BYTES)
+
+/*
+ * Cacheline size aligned (Total size needed for
+ * SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)
+ */
+#define SLPC_OVERR
[Intel-gfx] [PATCH 05/15] drm/i915/guc/slpc: Allocate, initialize and release SLPC
Allocate data structures for SLPC and functions for
initializing on host side.
v2: Address review comments (Michal W)
v3: Remove unnecessary header includes (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 11 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 36 ++-
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 ++
3 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 5b0f8c541b69..13d162353b1a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -336,6 +336,12 @@ int intel_guc_init(struct intel_guc *guc)
goto err_ct;
}
+ if (intel_guc_slpc_is_used(guc)) {
+ ret = intel_guc_slpc_init(&guc->slpc);
+ if (ret)
+ goto err_submission;
+ }
+
/* now that everything is perma-pinned, initialize the parameters */
guc_init_params(guc);
@@ -346,6 +352,8 @@ int intel_guc_init(struct intel_guc *guc)
return 0;
+err_submission:
+ intel_guc_submission_fini(guc);
err_ct:
intel_guc_ct_fini(&guc->ct);
err_ads:
@@ -368,6 +376,9 @@ void intel_guc_fini(struct intel_guc *guc)
i915_ggtt_disable_guc(gt->ggtt);
+ if (intel_guc_slpc_is_used(guc))
+ intel_guc_slpc_fini(&guc->slpc);
+
if (intel_guc_submission_is_used(guc))
intel_guc_submission_fini(guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 7275100ef8f8..bae4e33db0f8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -12,6 +12,16 @@ static inline struct intel_guc *slpc_to_guc(struct
intel_guc_slpc *slpc)
return container_of(slpc, struct intel_guc, slpc);
}
+static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
+{
+ return guc_to_gt(slpc_to_guc(slpc));
+}
+
+static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc
*slpc)
+{
+ return slpc_to_gt(slpc)->i915;
+}
+
static bool __detect_slpc_supported(struct intel_guc *guc)
{
/* GuC SLPC is unavailable for pre-Gen12 */
@@ -35,11 +45,35 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
guc->slpc_selected = __guc_slpc_selected(guc);
}
+static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
+ int err;
+
+ err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void
**)&slpc->vaddr);
+ if (unlikely(err)) {
+ drm_err(&i915->drm,
+ "Failed to allocate SLPC struct (err=%pe)\n",
+ ERR_PTR(err));
+ return err;
+ }
+
+ return err;
+}
+
int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
{
- return 0;
+ GEM_BUG_ON(slpc->vma);
+
+ return slpc_shared_data_init(slpc);
}
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
{
+ if (!slpc->vma)
+ return;
+
+ i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index bfe4a7f9ce15..edcf4c05bd9f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -7,6 +7,8 @@
#define _INTEL_GUC_SLPC_TYPES_H_
struct intel_guc_slpc {
+ struct i915_vma *vma;
+ struct slpc_shared_data *vaddr;
};
#endif
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/15] drm/i915/guc/slpc: Enable SLPC and add related H2G events
Add methods for interacting with GuC for enabling SLPC. Enable
SLPC after GuC submission has been established. GuC load will
fail if SLPC cannot be successfully initialized. Add various
helper methods to set/unset the parameters for SLPC. They can
be set using H2G calls or directly setting bits in the shared
data structure.
v2: Address several review comments, add new helpers for
decoding the SLPC min/max frequencies. Use masks instead of hardcoded
constants. (Michal W)
v3: Split global_state_to_string function, and check for positive
non-zero return value from intel_guc_send() (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 237 ++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 2 +
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8 +
3 files changed, 247 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index bae4e33db0f8..f5808d2acbca 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -45,6 +45,40 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
guc->slpc_selected = __guc_slpc_selected(guc);
}
+static void slpc_mem_set_param(struct slpc_shared_data *data,
+ u32 id, u32 value)
+{
+ GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
+ /*
+* When the flag bit is set, corresponding value will be read
+* and applied by slpc.
+*/
+ data->override_params.bits[id >> 5] |= (1 << (id % 32));
+ data->override_params.values[id] = value;
+}
+
+static void slpc_mem_set_enabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+* Enabling a param involves setting the enable_id
+* to 1 and disable_id to 0.
+*/
+ slpc_mem_set_param(data, enable_id, 1);
+ slpc_mem_set_param(data, disable_id, 0);
+}
+
+static void slpc_mem_set_disabled(struct slpc_shared_data *data,
+ u8 enable_id, u8 disable_id)
+{
+ /*
+* Disabling a param involves setting the enable_id
+* to 0 and disable_id to 1.
+*/
+ slpc_mem_set_param(data, disable_id, 1);
+ slpc_mem_set_param(data, enable_id, 0);
+}
+
static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
@@ -63,6 +97,129 @@ static int slpc_shared_data_init(struct intel_guc_slpc
*slpc)
return err;
}
+static u32 slpc_get_state(struct intel_guc_slpc *slpc)
+{
+ struct slpc_shared_data *data;
+
+ GEM_BUG_ON(!slpc->vma);
+
+ drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
+ data = slpc->vaddr;
+
+ return data->header.global_state;
+}
+
+static bool slpc_is_running(struct intel_guc_slpc *slpc)
+{
+ return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
+}
+
+static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ offset,
+ 0,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
+static int slpc_query_task_state(struct intel_guc_slpc *slpc)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ u32 shared_data_gtt_offset = intel_guc_ggtt_offset(guc, slpc->vma);
+ int ret;
+
+ ret = guc_action_slpc_query(guc, shared_data_gtt_offset);
+ if (ret)
+ drm_err(&i915->drm, "Query task state data returned (%pe)\n",
+ ERR_PTR(ret));
+
+ drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
+
+ return ret;
+}
+
+static const char *slpc_global_state_to_string(enum slpc_global_state state)
+{
+ const char *str = NULL;
+
+ switch (state) {
+ case SLPC_GLOBAL_STATE_NOT_RUNNING:
+ str = "not running";
+ break;
+ case SLPC_GLOBAL_STATE_INITIALIZING:
+ str = "initializing";
+ break;
+ case SLPC_GLOBAL_STATE_RESETTING:
+ str = "resetting";
+ break;
+ case SLPC_GLOBAL_STATE_RUNNING:
+ str = "running";
+ break;
+ case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
+ str = "shutting down";
+ break;
+ case SLPC_GLOBAL_STATE_ERROR:
+ str = "error";
+ break;
+ default:
+ str = "unknown";
+ break;
+ }
+
+ return str;
+}
+
+static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
+{
+ return slpc_global_state_to_string(slpc_get_state(slpc));
+}
+
+static i
[Intel-gfx] [PATCH 08/15] drm/i915/guc/slpc: Add methods to set min/max frequency
Add param set h2g helpers to set the min and max frequencies
for use by SLPC.
v2: Address review comments (Michal W)
v3: Check for positive error code (Michal W)
Signed-off-by: Sundaresan Sujaritha
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 89 -
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index f5808d2acbca..63656640189c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -109,6 +109,21 @@ static u32 slpc_get_state(struct intel_guc_slpc *slpc)
return data->header.global_state;
}
+static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
+ id,
+ value,
+ };
+ int ret;
+
+ ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
+
+ return ret > 0 ? -EPROTO : ret;
+}
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
@@ -118,7 +133,7 @@ static int guc_action_slpc_query(struct intel_guc *guc, u32
offset)
{
u32 request[] = {
INTEL_GUC_ACTION_SLPC_REQUEST,
- SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
+ SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
offset,
0,
};
@@ -146,6 +161,15 @@ static int slpc_query_task_state(struct intel_guc_slpc
*slpc)
return ret;
}
+static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_set_param(guc, id, value);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
const char *str = NULL;
@@ -251,6 +275,69 @@ static u32 slpc_decode_max_freq(struct intel_guc_slpc
*slpc)
GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
}
+/**
+ * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(&i915->drm,
+ "Set max frequency unslice returned (%pe)\n",
ERR_PTR(ret));
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to update the min unslice
+ * frequency.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
+{
+ int ret;
+ struct intel_guc *guc = slpc_to_guc(slpc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ ret = slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ val);
+ if (ret) {
+ drm_err(&i915->drm,
+ "Set min frequency for unslice returned
(%pe)\n", ERR_PTR(ret));
+ /* Return standardized err code for sysfs */
+ ret = -EIO;
+ }
+ }
+
+ return ret;
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index c3b0ad7f0f93..e594510497ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -29,5 +29,7 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
+int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc,
[Intel-gfx] [PATCH 07/15] drm/i915/guc/slpc: Remove BUG_ON in guc_submission_disable
The assumption when it was added was there would be no wakerefs
held. However, if we fail to enable SLPC, we will still be
holding a wakeref.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b6338742a594..48cbd800ca54 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2523,10 +2523,6 @@ void intel_guc_submission_enable(struct intel_guc *guc)
void intel_guc_submission_disable(struct intel_guc *guc)
{
- struct intel_gt *gt = guc_to_gt(guc);
-
- GEM_BUG_ON(gt->awake); /* GT should be parked first */
-
/* Note: By the time we're here, GuC may have already been reset */
}
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/15] drm/i915/guc/slpc: Add get max/min freq hooks
Add helpers to read the min/max frequency being used
by SLPC. This is done by send a H2G command which forces
SLPC to update the shared data struct which can then be
read. These helpers will be used in a sysfs patch later
on.
v2: Address review comments (Michal W)
v3: Return err in case of query failure (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 54 +
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 +
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 63656640189c..c653bba3b5eb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -306,6 +306,33 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc
*slpc, u32 val)
return ret;
}
+/**
+ * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold max frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the max frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+ struct drm_i915_private *i915 = slpc_to_i915(slpc);
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ /* Force GuC to update task data */
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret)
+ *val = slpc_decode_max_freq(slpc);
+ }
+
+ return ret;
+}
+
/**
* intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
* @slpc: pointer to intel_guc_slpc.
@@ -338,6 +365,33 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc
*slpc, u32 val)
return ret;
}
+/**
+ * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
+ * @slpc: pointer to intel_guc_slpc.
+ * @val: pointer to val which will hold min frequency (MHz)
+ *
+ * This function will invoke GuC SLPC action to read the min frequency
+ * limit for unslice.
+ *
+ * Return: 0 on success, non-zero error code on failure.
+ */
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
+{
+ intel_wakeref_t wakeref;
+ struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
+ int ret = 0;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ /* Force GuC to update task data */
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret)
+ *val = slpc_decode_min_freq(slpc);
+ }
+
+ return ret;
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index e594510497ec..92d7afd44f07 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -31,5 +31,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val);
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
+int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
+int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
#endif
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/15] drm/i915/guc/slpc: Add debugfs for SLPC info
This prints out relevant SLPC info from the SLPC shared structure.
We will send a h2g message which forces SLPC to update the
shared data structure with latest information before reading it.
v2: Address review comments (Michal W)
v3: Remove unnecessary tasks from slpc_info (Michal W)
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Sundaresan Sujaritha
---
.../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 22 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 4 ++-
3 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
index 72ddfff42f7d..3244e54b1337 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c
@@ -12,6 +12,7 @@
#include "gt/uc/intel_guc_ct.h"
#include "gt/uc/intel_guc_ads.h"
#include "gt/uc/intel_guc_submission.h"
+#include "gt/uc/intel_guc_slpc.h"
static int guc_info_show(struct seq_file *m, void *data)
{
@@ -50,11 +51,32 @@ static int guc_registered_contexts_show(struct seq_file *m,
void *data)
}
DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts);
+static int guc_slpc_info_show(struct seq_file *m, void *unused)
+{
+ struct intel_guc *guc = m->private;
+ struct intel_guc_slpc *slpc = &guc->slpc;
+ struct drm_printer p = drm_seq_file_printer(m);
+
+ if (!intel_guc_slpc_is_used(guc))
+ return -ENODEV;
+
+ return intel_guc_slpc_info(slpc, &p);
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_slpc_info);
+
+static bool intel_eval_slpc_support(void *data)
+{
+ struct intel_guc *guc = (struct intel_guc *)data;
+
+ return intel_guc_slpc_is_used(guc);
+}
+
void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root)
{
static const struct debugfs_gt_file files[] = {
{ "guc_info", &guc_info_fops, NULL },
{ "guc_registered_contexts", &guc_registered_contexts_fops,
NULL },
+ { "guc_slpc_info", &guc_slpc_info_fops,
&intel_eval_slpc_support},
};
if (!intel_guc_is_supported(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index c653bba3b5eb..995d3d4807a3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -448,6 +448,35 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
return 0;
}
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
+{
+ struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915;
+ struct slpc_shared_data *data = slpc->vaddr;
+ struct slpc_task_state_data *slpc_tasks;
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ GEM_BUG_ON(!slpc->vma);
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ ret = slpc_query_task_state(slpc);
+
+ if (!ret) {
+ slpc_tasks = &data->task_state_data;
+
+ drm_printf(p, "\tSLPC state: %s\n",
slpc_get_state_string(slpc));
+ drm_printf(p, "\tGTPERF task active: %s\n",
+ yesno(slpc_tasks->status &
SLPC_GTPERF_TASK_ENABLED));
+ drm_printf(p, "\tMax freq: %u MHz\n",
+ slpc_decode_max_freq(slpc));
+ drm_printf(p, "\tMin freq: %u MHz\n",
+ slpc_decode_min_freq(slpc));
+ }
+ }
+
+ return ret;
+}
+
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
{
if (!slpc->vma)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index 92d7afd44f07..d133c8020c16 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,8 @@
#include "intel_guc_submission.h"
#include "intel_guc_slpc_types.h"
+struct drm_printer;
+
static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
{
return guc->slpc_supported;
@@ -25,7 +27,6 @@ static inline bool intel_guc_slpc_is_used(struct intel_guc
*guc)
}
void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc);
-
int intel_guc_slpc_init(struct intel_guc_slpc *slpc);
int intel_guc_slpc_enable(struct intel_guc_slpc *slpc);
void intel_guc_slpc_fini(struct intel_guc_slpc *slpc);
@@ -33,5 +34,6 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc,
u32 val);
int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val);
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
+int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
#endif
--
2.25.0
___
Intel-gf
[Intel-gfx] [PATCH 11/15] drm/i915/guc/slpc: Enable ARAT timer interrupt
This interrupt is enabled during RPS initialization, and
now needs to be done by SLPC code. It allows ARAT timer
expiry interrupts to get forwarded to GuC.
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 16
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 8
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 995d3d4807a3..c79dba60b2e6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -392,6 +392,20 @@ int intel_guc_slpc_get_min_freq(struct intel_guc_slpc
*slpc, u32 *val)
return ret;
}
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
+{
+ u32 pm_intrmsk_mbz = 0;
+
+ /* Allow GuC to receive ARAT timer expiry event.
+* This interrupt register is setup by RPS code
+* when host based Turbo is enabled.
+*/
+ pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+
+ intel_uncore_rmw(gt->uncore,
+ GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
@@ -439,6 +453,8 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
slpc_query_task_state(slpc);
+ intel_guc_pm_intrmsk_enable(&i915->gt);
+
/* min and max frequency limits being used by SLPC */
drm_info(&i915->drm, "SLPC min freq: %u Mhz, max is %u Mhz\n",
slpc_decode_min_freq(slpc),
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
index d133c8020c16..f128143cc1d8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
@@ -9,6 +9,7 @@
#include "intel_guc_submission.h"
#include "intel_guc_slpc_types.h"
+struct intel_gt;
struct drm_printer;
static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc)
@@ -35,5 +36,6 @@ int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc,
u32 val);
int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val);
int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val);
int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p);
+void intel_guc_pm_intrmsk_enable(struct intel_gt *gt);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index b98c14f8c229..9238bc076605 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -652,6 +652,7 @@ void intel_uc_suspend(struct intel_uc *uc)
static int __uc_resume(struct intel_uc *uc, bool enable_communication)
{
struct intel_guc *guc = &uc->guc;
+ struct intel_gt *gt = guc_to_gt(guc);
int err;
if (!intel_guc_is_fw_running(guc))
@@ -663,6 +664,13 @@ static int __uc_resume(struct intel_uc *uc, bool
enable_communication)
if (enable_communication)
guc_enable_communication(guc);
+ /* If we are only resuming GuC communication but not reloading
+* GuC, we need to ensure the ARAT timer interrupt is enabled
+* again. In case of GuC reload, it is enabled during SLPC enable.
+*/
+ if (enable_communication && intel_uc_uses_guc_slpc(uc))
+ intel_guc_pm_intrmsk_enable(gt);
+
err = intel_guc_resume(guc);
if (err) {
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
--
2.25.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/15] drm/i915/guc/slpc: Add SLPC selftest
Tests that exercise the SLPC get/set frequency interfaces.
Clamp_max will set max frequency to multiple levels and check
that SLPC requests frequency lower than or equal to it.
Clamp_min will set min frequency to different levels and check
if SLPC requests are higher or equal to those levels.
v2: Address review comments (Michal W)
v3: Checkpatch() corrections
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/intel_rps.c | 1 +
drivers/gpu/drm/i915/gt/selftest_slpc.c | 311 ++
drivers/gpu/drm/i915/gt/selftest_slpc.h | 12 +
.../drm/i915/selftests/i915_live_selftests.h | 1 +
4 files changed, 325 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.c
create mode 100644 drivers/gpu/drm/i915/gt/selftest_slpc.h
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 48d4147165a9..6237332835fe 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2318,4 +2318,5 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_rps.c"
+#include "selftest_slpc.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
b/drivers/gpu/drm/i915/gt/selftest_slpc.c
new file mode 100644
index ..5018f686686f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "selftest_slpc.h"
+
+#define NUM_STEPS 5
+#define H2G_DELAY 5
+#define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 1)
+
+static int set_min_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+ int ret;
+
+ ret = intel_guc_slpc_set_min_freq(slpc, freq);
+ if (ret)
+ pr_err("Could not set min frequency to [%u]\n", freq);
+ else /* Delay to ensure h2g completes */
+ delay_for_h2g();
+
+ return ret;
+}
+
+static int set_max_freq(struct intel_guc_slpc *slpc, u32 freq)
+{
+ int ret;
+
+ ret = intel_guc_slpc_set_max_freq(slpc, freq);
+ if (ret)
+ pr_err("Could not set maximum frequency [%u]\n",
+ freq);
+ else /* Delay to ensure h2g completes */
+ delay_for_h2g();
+
+ return ret;
+}
+
+int live_slpc_clamp_min(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_gt *gt = &i915->gt;
+ struct intel_guc_slpc *slpc = >->uc.guc.slpc;
+ struct intel_rps *rps = >->rps;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ u32 slpc_min_freq, slpc_max_freq;
+ int err = 0;
+
+ if (!intel_uc_uses_guc_slpc(>->uc))
+ return 0;
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) {
+ pr_err("Could not get SLPC max freq\n");
+ return -EIO;
+ }
+
+ if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) {
+ pr_err("Could not get SLPC min freq\n");
+ return -EIO;
+ }
+
+ if (slpc_min_freq == slpc_max_freq) {
+ pr_err("Min/Max are fused to the same value\n");
+ return -EINVAL;
+ }
+
+ intel_gt_pm_wait_for_idle(gt);
+ intel_gt_pm_get(gt);
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ u32 step, min_freq, req_freq;
+ u32 act_freq, max_act_freq;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ /* Go from min to max in 5 steps */
+ step = (slpc_max_freq - slpc_min_freq) / NUM_STEPS;
+ max_act_freq = slpc_min_freq;
+ for (min_freq = slpc_min_freq; min_freq < slpc_max_freq;
+ min_freq += step) {
+ err = set_min_freq(slpc, min_freq);
+ if (err)
+ break;
+
+ st_engine_heartbeat_disable(engine);
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ st_engine_heartbeat_enable(engine);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ pr_err("%s: Spinner did not start\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ st_engine_heartbeat_enable(engine);
+ intel_gt_s
[Intel-gfx] [PATCH 12/15] drm/i915/guc/slpc: Cache platform frequency limits
Cache rp0, rp1 and rpn platform limits into SLPC structure
for range checking while setting min/max frequencies.
Also add "soft" limits which keep track of frequency changes
made from userland. These are initially set to platform min
and max.
v2: Address review comments (Michal W)
v3: Formatting (Michal W)
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 97 +++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 11 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +
3 files changed, 111 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index c79dba60b2e6..a98cbf274862 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -94,6 +94,9 @@ static int slpc_shared_data_init(struct intel_guc_slpc *slpc)
return err;
}
+ slpc->max_freq_softlimit = 0;
+ slpc->min_freq_softlimit = 0;
+
return err;
}
@@ -124,6 +127,18 @@ static int guc_action_slpc_set_param(struct intel_guc
*guc, u8 id, u32 value)
return ret > 0 ? -EPROTO : ret;
}
+static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
+{
+ u32 request[] = {
+ INTEL_GUC_ACTION_SLPC_REQUEST,
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
+ id,
+ };
+
+ return intel_guc_send(guc, request, ARRAY_SIZE(request));
+}
+
+
static bool slpc_is_running(struct intel_guc_slpc *slpc)
{
return (slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING);
@@ -170,6 +185,16 @@ static int slpc_set_param(struct intel_guc_slpc *slpc, u8
id, u32 value)
return guc_action_slpc_set_param(guc, id, value);
}
+static int slpc_unset_param(struct intel_guc_slpc *slpc,
+ u8 id)
+{
+ struct intel_guc *guc = slpc_to_guc(slpc);
+
+ GEM_BUG_ON(id >= SLPC_MAX_PARAM);
+
+ return guc_action_slpc_unset_param(guc, id);
+}
+
static const char *slpc_global_state_to_string(enum slpc_global_state state)
{
const char *str = NULL;
@@ -406,6 +431,55 @@ void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
}
+static int intel_guc_slpc_set_softlimits(struct intel_guc_slpc *slpc)
+{
+ int ret = 0;
+
+ /* Softlimits are initially equivalent to platform limits
+* unless they have deviated from defaults, in which case,
+* we retain the values and set min/max accordingly.
+*/
+ if (!slpc->max_freq_softlimit)
+ slpc->max_freq_softlimit = slpc->rp0_freq;
+ else if (slpc->max_freq_softlimit != slpc->rp0_freq)
+ ret = intel_guc_slpc_set_max_freq(slpc,
+ slpc->max_freq_softlimit);
+
+ if (!slpc->min_freq_softlimit)
+ slpc->min_freq_softlimit = slpc->min_freq;
+ else if (slpc->min_freq_softlimit != slpc->min_freq)
+ ret = intel_guc_slpc_set_min_freq(slpc,
+ slpc->min_freq_softlimit);
+
+ return ret;
+}
+
+static void intel_guc_slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool
ignore)
+{
+ if (ignore) {
+ /* A failure here does not affect the algorithm in a fatal way
*/
+ slpc_set_param(slpc,
+ SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
+ ignore);
+ slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ slpc->min_freq);
+ } else {
+ slpc_unset_param(slpc,
+ SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
+ slpc_unset_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
+ }
+}
+
+static void intel_guc_slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
+{
+ /* Force slpc to used platform rp0 */
+ slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ slpc->rp0_freq);
+}
+
/*
* intel_guc_slpc_enable() - Start SLPC
* @slpc: pointer to intel_guc_slpc.
@@ -423,6 +497,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
struct slpc_shared_data *data;
+ u32 rp_state_cap;
int ret;
GEM_BUG_ON(!slpc->vma);
@@ -460,6 +535,28 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
slpc_decode_min_freq(slpc),
slpc_decode_max_freq(slpc));
+ rp_state_cap = intel_uncore_read(i915->gt.uncore, GEN6_RP_STATE_CAP);
+
+ slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) *
+ GT_FREQUENCY_MULTIPLIER;
+ slpc->rp1_freq = REG_FIELD_GET(RP1_CAP_MASK, rp_state_cap) *
+ GT_FREQUENCY_MULTIPLIER;
+ slpc->min_freq = R
[Intel-gfx] [PATCH 13/15] drm/i915/guc/slpc: Sysfs hooks for SLPC
Update the get/set min/max freq hooks to work for
SLPC case as well. Consolidate helpers for requested/min/max
frequency get/set to intel_rps where the proper action can
be taken depending on whether SLPC is enabled.
v2: Add wrappers for getting rp0/1/n frequencies, update
softlimits in set min/max SLPC functions. Also check for
boundary conditions before setting them.
v3: Address review comments (Michal W)
Acked-by: Michal Wajdeczko
Signed-off-by: Vinay Belgaumkar
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/gt/intel_rps.c | 165
drivers/gpu/drm/i915/gt/intel_rps.h | 11 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 14 ++
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/i915_sysfs.c | 77 ++---
6 files changed, 207 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index e858eeb2c59d..48d4147165a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -37,6 +37,13 @@ static struct intel_uncore *rps_to_uncore(struct intel_rps
*rps)
return rps_to_gt(rps)->uncore;
}
+static struct intel_guc_slpc *rps_to_slpc(struct intel_rps *rps)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+
+ return >->uc.guc.slpc;
+}
+
static bool rps_uses_slpc(struct intel_rps *rps)
{
struct intel_gt *gt = rps_to_gt(rps);
@@ -1960,6 +1967,164 @@ u32 intel_rps_read_actual_frequency(struct intel_rps
*rps)
return freq;
}
+u32 intel_rps_read_punit_req(struct intel_rps *rps)
+{
+ struct intel_uncore *uncore = rps_to_uncore(rps);
+
+ return intel_uncore_read(uncore, GEN6_RPNSWREQ);
+}
+
+u32 intel_rps_get_req(struct intel_rps *rps, u32 pureq)
+{
+ u32 req = pureq >> GEN9_SW_REQ_UNSLICE_RATIO_SHIFT;
+
+ return req;
+}
+
+u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps)
+{
+ u32 freq = intel_rps_get_req(rps, intel_rps_read_punit_req(rps));
+
+ return intel_gpu_freq(rps, freq);
+}
+
+u32 intel_rps_get_requested_frequency(struct intel_rps *rps)
+{
+ if (rps_uses_slpc(rps))
+ return intel_rps_read_punit_req_frequency(rps);
+ else
+ return intel_gpu_freq(rps, rps->cur_freq);
+}
+
+u32 intel_rps_get_max_frequency(struct intel_rps *rps)
+{
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+ if (rps_uses_slpc(rps))
+ return slpc->max_freq_softlimit;
+ else
+ return intel_gpu_freq(rps, rps->max_freq_softlimit);
+}
+
+u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
+{
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+ if (rps_uses_slpc(rps))
+ return slpc->rp0_freq;
+ else
+ return intel_gpu_freq(rps, rps->rp0_freq);
+}
+
+u32 intel_rps_get_rp1_frequency(struct intel_rps *rps)
+{
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+ if (rps_uses_slpc(rps))
+ return slpc->rp1_freq;
+ else
+ return intel_gpu_freq(rps, rps->rp1_freq);
+}
+
+u32 intel_rps_get_rpn_frequency(struct intel_rps *rps)
+{
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+ if (rps_uses_slpc(rps))
+ return slpc->min_freq;
+ else
+ return intel_gpu_freq(rps, rps->min_freq);
+}
+
+int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+ int ret = 0;
+
+ if (rps_uses_slpc(rps))
+ return intel_guc_slpc_set_max_freq(slpc, val);
+
+ mutex_lock(&rps->lock);
+
+ val = intel_freq_opcode(rps, val);
+ if (val < rps->min_freq ||
+ val > rps->max_freq ||
+ val < rps->min_freq_softlimit) {
+ ret = -EINVAL;
+ goto unlock;
+ }
+
+ if (val > rps->rp0_freq)
+ drm_dbg(&i915->drm, "User requested overclocking to %d\n",
+ intel_gpu_freq(rps, val));
+
+ rps->max_freq_softlimit = val;
+
+ val = clamp_t(int, rps->cur_freq,
+ rps->min_freq_softlimit,
+ rps->max_freq_softlimit);
+
+ /*
+* We still need *_set_rps to process the new max_delay and
+* update the interrupt limits and PMINTRMSK even though
+* frequency request may be unchanged.
+*/
+ intel_rps_set(rps, val);
+
+unlock:
+ mutex_unlock(&rps->lock);
+
+ return ret;
+}
+
+u32 intel_rps_get_min_frequency(struct intel_rps *rps)
+{
+ struct intel_guc_slpc *slpc = rps_to_slpc(rps);
+
+ if (rps_uses_slpc(rps))
+ return slpc->min_freq_softlimit;
+ else
+ return intel_gpu_freq(rps, rps->min_freq_softlimit);
+}
+
+int intel_rp
[Intel-gfx] [PATCH 15/15] drm/i915/guc/rc: Setup and enable GUCRC feature
This feature hands over the control of HW RC6 to the GuC.
GuC decides when to put HW into RC6 based on it's internal
busyness algorithms.
GUCRC needs GuC submission to be enabled, and only
supported on Gen12+ for now.
When GUCRC is enabled, do not set HW RC6. Use a H2G message
to tell GuC to enable GUCRC. When disabling RC6, tell GuC to
revert RC6 control back to KMD.
v2: Address comments (Michal W)
Reviewed-by: Michal Wajdeczko
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 22 +++--
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 6 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c | 80 +++
drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h | 31 +++
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 2 +
8 files changed, 140 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d8eac4468df9..3fc17f20d88e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -186,6 +186,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
+ gt/uc/intel_guc_rc.o \
gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 259d7eb4e165..299fcf10b04b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -98,11 +98,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
- /* 3a: Enable RC6 */
- rc6->ctl_enable =
- GEN6_RC_CTL_HW_ENABLE |
- GEN6_RC_CTL_RC6_ENABLE |
- GEN6_RC_CTL_EI_MODE(1);
+ /* 3a: Enable RC6
+*
+* With GUCRC, we do not enable bit 31 of RC_CTL,
+* thus allowing GuC to control RC6 entry/exit fully instead.
+* We will not set the HW ENABLE and EI bits
+*/
+ if (!intel_guc_rc_enable(>->uc.guc))
+ rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
+ else
+ rc6->ctl_enable =
+ GEN6_RC_CTL_HW_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE |
+ GEN6_RC_CTL_EI_MODE(1);
pg_enable =
GEN9_RENDER_PG_ENABLE |
@@ -513,6 +521,10 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ struct intel_gt *gt = rc6_to_gt(rc6);
+
+ /* Take control of RC6 back from GuC */
+ intel_guc_rc_disable(>->uc.guc);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
if (GRAPHICS_VER(i915) >= 9)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index ca538e5de940..8ff58aff 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -135,6 +135,7 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
+ INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
@@ -145,6 +146,11 @@ enum intel_guc_action {
INTEL_GUC_ACTION_LIMIT
};
+enum intel_guc_rc_options {
+ INTEL_GUCRC_HOST_CONTROL,
+ INTEL_GUCRC_FIRMWARE_CONTROL,
+};
+
enum intel_guc_preempt_options {
INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 13d162353b1a..fbfcae727d7f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -159,6 +159,7 @@ void intel_guc_init_early(struct intel_guc *guc)
intel_guc_log_init_early(&guc->log);
intel_guc_submission_init_early(guc);
intel_guc_slpc_init_early(&guc->slpc);
+ intel_guc_rc_init_early(guc);
mutex_init(&guc->send_mutex);
spin_lock_init(&guc->irq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 15ad2eaee473..08919d1b35dc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Enable GuC based power management features
== Series Details == Series: drm/i915/guc/slpc: Enable GuC based power management features URL : https://patchwork.freedesktop.org/series/93026/ State : warning == Summary == $ dim checkpatch origin/drm-tip e739b51dc573 drm/i915/guc: SQUASHED PATCH - DO NOT REVIEW -:54: WARNING:BAD_SIGN_OFF: Duplicate signature #54: Signed-off-by: Matthew Brost -:74: WARNING:BAD_SIGN_OFF: Duplicate signature #74: Signed-off-by: Matthew Brost -:83: WARNING:BAD_SIGN_OFF: Duplicate signature #83: Signed-off-by: Matthew Brost -:84: WARNING:BAD_SIGN_OFF: Duplicate signature #84: Reviewed-by: John Harrison -:99: WARNING:BAD_SIGN_OFF: Duplicate signature #99: Signed-off-by: Matthew Brost -:101: WARNING:BAD_SIGN_OFF: Duplicate signature #101: Reviewed-by: John Harrison -:111: WARNING:BAD_SIGN_OFF: Duplicate signature #111: Signed-off-by: Matthew Brost -:112: WARNING:BAD_SIGN_OFF: Duplicate signature #112: Reviewed-by: John Harrison -:121: WARNING:BAD_SIGN_OFF: Duplicate signature #121: Signed-off-by: Matthew Brost -:122: WARNING:BAD_SIGN_OFF: Duplicate signature #122: Reviewed-by: John Harrison -:150: WARNING:BAD_SIGN_OFF: Duplicate signature #150: Cc: John Harrison -:151: WARNING:BAD_SIGN_OFF: Duplicate signature #151: Signed-off-by: Matthew Brost -:159: WARNING:BAD_SIGN_OFF: Duplicate signature #159: Signed-off-by: Matthew Brost -:160: WARNING:BAD_SIGN_OFF: Duplicate signature #160: Reviewed-by: John Harrison -:168: WARNING:BAD_SIGN_OFF: Duplicate signature #168: Signed-off-by: Matthew Brost -:169: WARNING:BAD_SIGN_OFF: Duplicate signature #169: Cc: Daniele Ceraolo Spurio -:170: WARNING:BAD_SIGN_OFF: Duplicate signature #170: Reviewed-by: John Harrison -:191: WARNING:BAD_SIGN_OFF: Duplicate signature #191: Cc: John Harrison -:192: WARNING:BAD_SIGN_OFF: Duplicate signature #192: Signed-off-by: Matthew Brost -:194: WARNING:BAD_SIGN_OFF: Duplicate signature #194: Reviewed-by: John Harrison -:211: WARNING:BAD_SIGN_OFF: Duplicate signature #211: Cc: John Harrison -:212: WARNING:BAD_SIGN_OFF: Duplicate signature #212: Signed-off-by: Matthew Brost -:213: WARNING:BAD_SIGN_OFF: Duplicate signature #213: Reviewed-by: John Harrison -:225: WARNING:BAD_SIGN_OFF: Duplicate signature #225: Signed-off-by: Matthew Brost -:227: WARNING:BAD_SIGN_OFF: Duplicate signature #227: Reviewed-by: John Harrison -:234: WARNING:BAD_SIGN_OFF: Duplicate signature #234: Signed-off-by: Matthew Brost -:235: WARNING:BAD_SIGN_OFF: Duplicate signature #235: CC: John Harrison -:236: WARNING:BAD_SIGN_OFF: Duplicate signature #236: Reviewed-by: John Harrison -:250: WARNING:BAD_SIGN_OFF: Duplicate signature #250: Signed-off-by: John Harrison -:251: WARNING:BAD_SIGN_OFF: Duplicate signature #251: Signed-off-by: Fernando Pacheco -:252: WARNING:BAD_SIGN_OFF: Duplicate signature #252: Signed-off-by: Matthew Brost -:253: WARNING:BAD_SIGN_OFF: Duplicate signature #253: Cc: Daniele Ceraolo Spurio -:255: WARNING:BAD_SIGN_OFF: Duplicate signature #255: Reviewed-by: Matthew Brost -:265: WARNING:BAD_SIGN_OFF: Duplicate signature #265: Signed-off-by: John Harrison -:266: WARNING:BAD_SIGN_OFF: Duplicate signature #266: Signed-off-by: Matthew Brost -:267: WARNING:BAD_SIGN_OFF: Duplicate signature #267: Reviewed-by: Matthew Brost -:274: WARNING:BAD_SIGN_OFF: Duplicate signature #274: Signed-off-by: John Harrison -:275: WARNING:BAD_SIGN_OFF: Duplicate signature #275: Signed-off-by: Matthew Brost -:276: WARNING:BAD_SIGN_OFF: Duplicate signature #276: Reviewed-by: Matthew Brost -:290: WARNING:BAD_SIGN_OFF: Duplicate signature #290: Signed-off-by: Matthew Brost -:291: WARNING:BAD_SIGN_OFF: Duplicate signature #291: Reviewed-by: John Harrison -:308: WARNING:BAD_SIGN_OFF: Duplicate signature #308: Signed-off-by: John Harrison -:309: WARNING:BAD_SIGN_OFF: Duplicate signature #309: Signed-off-by: Matthew Brost -:310: WARNING:BAD_SIGN_OFF: Duplicate signature #310: Reviewed-by: Matthew Brost -:321: WARNING:BAD_SIGN_OFF: Duplicate signature #321: Signed-off-by: John Harrison -:322: WARNING:BAD_SIGN_OFF: Duplicate signature #322: Signed-off-by: Matthew Brost -:323: WARNING:BAD_SIGN_OFF: Duplicate signature #323: Reviewed-by: Matthew Brost -:341: WARNING:BAD_SIGN_OFF: Duplicate signature #341: Signed-off-by: John Harrison -:342: WARNING:BAD_SIGN_OFF: Duplicate signature #342: Signed-off-by: Matthew Brost -:343: WARNING:BAD_SIGN_OFF: Duplicate signature #343: Reviewed-by: Matthew Brost -:350: WARNING:BAD_SIGN_OFF: Duplicate signature #350: Signed-off-by: John Harrison -:351: WARNING:BAD_SIGN_OFF: Duplicate signature #351: Signed-off-by: Matthew Brost -:352: WARNING:BAD_SIGN_OFF: Duplicate signature #352: Reviewed-by: Matthew Brost -:366: WARNING:BAD_SIGN_OFF: Duplicate signature #366: Signed-off-by: John Harrison -:367: WARNING:BAD_SIGN_OFF: Duplicate signature #367: Signed-off-by: Matthew Brost -:368: WARNING:BAD_SIGN_OFF: Duplic
