Re: [Intel-gfx] [PATCH] drm/i915: Implement display WA #1142:kbl, cfl, cml
On Fri, Sept. 25, 2020, 11 a.m., Ville Syrjälä wrote:
>On Thu, Sep 24, 2020 at 08:43:33PM +, Souza, Jose wrote:
>> On Thu, 2020-09-24 at 22:48 +0300, Ville Syrjala wrote:
>> > From: Ville Syrjälä <
>> > ville.syrj...@linux.intel.com
>> > >
>> >
>> > Implement display w/a #1142. This supposedly fixes some underruns
>> > with FBC+VTd. Bspec says we should use the same programming regardless
>> > of circumstances. Apparently we should flip the magic bits before
>> > turning on any planes so let's put this into the early w/as.
>> >
>> > Cc: Lee Shawn C <
>> > shawn.c@intel.com
>> > >
>> > Signed-off-by: Ville Syrjälä <
>> > ville.syrj...@linux.intel.com
>> > >
>> > ---
>> > drivers/gpu/drm/i915/display/intel_display.c | 9 +
>> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> > 2 files changed, 12 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index 5a9d933e425a..9d64187cfd56 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -18677,6 +18677,15 @@ static void intel_early_display_was(struct
>> > drm_i915_private *dev_priv)
>> >intel_de_write(dev_priv, CHICKEN_PAR1_1,
>> > intel_de_read(dev_priv, CHICKEN_PAR1_1) |
>> > FORCE_ARB_IDLE_PLANES);
>> >}
>> > +
>> > + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
>> > IS_COMETLAKE(dev_priv)) {
>>
>> WA mentions that it is required only for KBL, but if Lee says that this
>> helps with his CML issues.
>
>I think there's a note somewhere that says cfl+ are derived from the
>last kbl, and I don't think there's are specific cfl/cml tags for w/as.
>
>>
>> Reviewed-by: José Roberto de Souza
>
>Ta.
>
Thanks for the patch. We already shared this patch for external customer test.
According to customer's reply, the reproduce rate of flicker issue is lower
than before.
Unfortunately, they still can see panel flicker happen very randomly.
Best regards,
Shawn
>>
>> > + /* Display WA #1142:kbl,cfl,cml */
>> > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
>> > + KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
>> > + intel_de_rmw(dev_priv, CHICKEN_MISC_2,
>> > + KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
>> > + KBL_ARB_FILL_SPARE_14);
>> > + }
>> > }
>> >
>> > static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv,
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h
>> > index d805d4da6181..3f97cc0fcbf1 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -7865,6 +7865,7 @@ enum {
>> > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
>> >
>> > #define CHICKEN_PAR1_1_MMIO(0x42080)
>> > +#define KBL_ARB_FILL_SPARE_22REG_BIT(22)
>> > #define DIS_RAM_BYPASS_PSR2_MAN_TRACK(1 << 16)
>> > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
>> > #define DPA_MASK_VBLANK_SRD (1 << 15)
>> > @@ -7877,6 +7878,8 @@ enum {
>> >
>> > #define CHICKEN_MISC_2_MMIO(0x42084)
>> > #define CNL_COMP_PWR_DOWN(1 << 23)
>> > +#define KBL_ARB_FILL_SPARE_14REG_BIT(14)
>> > +#define KBL_ARB_FILL_SPARE_13REG_BIT(13)
>> > #define GLK_CL2_PWR_DOWN (1 << 12)
>> > #define GLK_CL1_PWR_DOWN (1 << 11)
>> > #define GLK_CL0_PWR_DOWN (1 << 10)
>> >
___
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[Intel-gfx] [RFC] drm/i915/gt: reduce context clear batch size to avoid gpu hang
Hello,
For several months, I've been experiencing GPU hangs when starting
Cinnamon on an HP Pavilion Mini 300-020 if I try to run an upstream
kernel. I reported this recently in
https://gitlab.freedesktop.org/drm/intel/-/issues/2413 where I have
attached the requested evidence including the state collected from
/sys/class/drm/card0/error and debug output from dmesg.
I got around to running a bisect to find the problem, which indicates:
[47f8253d2b8947d79fd3196bf96c1959c0f25f20] drm/i915/gen7: Clear all EU/L3
residual contexts
While I'm experienced in several areas of the Linux kernel, I'm really
nothing but an end user of the graphics drivers. But the nature of that
troublesome commit suggested to me that reducing the batch size used in
the context clear operation might help this relatively low-powered
system to avoid the hang and it did! I simply forced this system to
take the smaller batch length that is already used for non-Haswell
systems.
I'm calling this patch an RFC because this version is quick-and-dirty,
affecting only one file. If this makes sense, I have a cleaner version
that keys off of a proper quirk, but let's discuss the idea first before
looking at that. Maybe it doesn't need a new quirk? Maybe
there is already something distinctive on which the decision
could be made?
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index d93d85cd3027..6d24e266cda2 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -49,7 +49,11 @@ struct batch_vals {
static void
batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
{
- if (IS_HASWELL(i915)) {
+struct pci_dev *d = i915->drm.pdev;
+int force_reduced = (d->subsystem_vendor == PCI_VENDOR_ID_HP
+ && d->subsystem_device == 0x2b38);
+
+ if (IS_HASWELL(i915) && !force_reduced) {
bv->max_primitives = 280;
bv->max_urb_entries = MAX_URB_ENTRIES;
bv->surface_height = 16 * 16;
--
--
Randy WrightUsmail: Hewlett Packard Enterprise
Email: rwri...@hpe.com Servers Linux Enablement
Phone: (970) 898-0998 3404 E. Harmony Rd, Mailstop 36
Fort Collins, CO 80528-9599
___
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/gt: reduce context clear batch size to avoid gpu hang
== Series Details == Series: drm/i915/gt: reduce context clear batch size to avoid gpu hang URL : https://patchwork.freedesktop.org/series/82377/ State : failure == Summary == Applying: drm/i915/gt: reduce context clear batch size to avoid gpu hang error: patch failed: drivers/gpu/drm/i915/gt/gen7_renderclear.c:49 error: drivers/gpu/drm/i915/gt/gen7_renderclear.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... Patch failed at 0001 drm/i915/gt: reduce context clear batch size to avoid gpu hang When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
JSL has update in vswing table for eDP.
BSpec: 21257
Changes since V3 :
- Changed IS_EHL_JSL to IS_JSL_EH
- Reverted removal of IS_ELKHARTLAKE and also
added IS_JASPERLAKE
- Corrected mistake of using IS_ELKHARTLAKE twice and
missing IS_JASPERLAKE
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
- Changes rebased as per new drm top commit
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++--
1 file changed, 88 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..7589508ff7e2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x36, 0x00, 0x09 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x35, 0x00, 0x0A },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x3D, 0x00, 0x02 },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x3A, 0x00, 0x05 },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1167,6 +1195,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
return ehl_get_combo_buf_trans_dp(encoder, crtc_state,
n_entries);
}
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+ return icl_combo_phy_ddi_translations_dp_hbr2;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (dev_priv->vbt.edp.low_vswing) {
+ if (crtc_state->port_clock > 27) {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+ return jsl_combo_phy_ddi_translations_edp_hbr;
+ }
+ }
+
+ return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder,
+
[Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.
Changes since V3 :
- Changed IS_EHL_JSL to IS_JSL_EHL
- Renamed IS_EHL_REVID to IS_JSL_EHL_REVID
- Reverted removal of IS_ELKHARTLAKE and also
added IS_JASPERLAKE
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display.c | 8
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 9 ++---
drivers/gpu/drm/i915/i915_pci.c| 9 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pch.c | 2 +-
include/drm/i915_pciids.h | 9 ++---
14 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..f7c3731f5a4b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+ if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
tmp = intel_de_read(dev_priv,
ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
@@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys) {
tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb93f6cf6d37..c6e87569b3d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 552000;
else
@@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
- } else if (IS_ELKHARTLAKE(dev_priv)) {
+ } else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 157d8c8c605a..d59ceaa2916a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915,
enum phy phy)
* PHY-B and may not even have instances of the register for the
* other combo PHY's.
*/
- if (IS_ELKHARTLAKE(i915) ||
+ if (IS_JSL_EHL(i915) ||
IS_ROCKETLAKE(i915))
return phy < PHY_C;
@@ -282,7 +282,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
@@
[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table
Patch series covers following thigns: 1. Split and differentiate between EHL and JSL platfrom 2. Update voltage swing table for eDP on JSL platform Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE - Corrected mistake of using IS_ELKHARTLAKE twice and missing IS_JASPERLAKE in intel_ddi Changes since V2 : - Added IS_EHL_JSL to replace IS_ELKHARTLAKE - EHL/JSL PCI ids split added - Rebased to drm master commit Changes since V1 : - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively - Reverted EHL/JSL PCI ids split change Tejas Upadhyay (2): drm/i915/jsl: Split EHL/JSL platform info and PCI ids drm/i915/edp/jsl: Update vswing table for HBR and HBR2 drivers/gpu/drm/i915/display/icl_dsi.c| 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- .../gpu/drm/i915/display/intel_combo_phy.c| 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++- drivers/gpu/drm/i915/display/intel_display.c | 8 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++-- drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_pci.c | 9 ++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pch.c | 2 +- include/drm/i915_pciids.h | 9 +- 15 files changed, 135 insertions(+), 35 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 0/2] drm/i915/jsl: Update JSL Voltage swing table
Patch series covers following thigns: 1. Split and differentiate between EHL and JSL platfrom 2. Update voltage swing table for eDP on JSL platform Changes since V3 : - Changed IS_EHL_JSL to IS_JSL_EHL - Renamed IS_EHL_REVID to IS_JSL_EHL_REVID - Reverted removal of IS_ELKHARTLAKE and also added IS_JASPERLAKE - Corrected mistake of using IS_ELKHARTLAKE twice and missing IS_JASPERLAKE in intel_ddi Changes since V2 : - Added IS_EHL_JSL to replace IS_ELKHARTLAKE - EHL/JSL PCI ids split added - Rebased to drm master commit Changes since V1 : - IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively - Reverted EHL/JSL PCI ids split change Tejas Upadhyay (2): drm/i915/jsl: Split EHL/JSL platform info and PCI ids drm/i915/edp/jsl: Update vswing table for HBR and HBR2 drivers/gpu/drm/i915/display/icl_dsi.c| 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- .../gpu/drm/i915/display/intel_combo_phy.c| 6 +- drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++- drivers/gpu/drm/i915/display/intel_display.c | 8 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16 ++-- drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +- drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_pci.c | 9 ++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_pch.c | 2 +- include/drm/i915_pciids.h | 9 +- 15 files changed, 135 insertions(+), 35 deletions(-) -- 2.28.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
JSL has update in vswing table for eDP.
BSpec: 21257
Changes since V3 :
- Changed IS_EHL_JSL to IS_JSL_EH
- Reverted removal of IS_ELKHARTLAKE and also
added IS_JASPERLAKE
- Corrected mistake of using IS_ELKHARTLAKE twice and
missing IS_JASPERLAKE
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
- Changes rebased as per new drm top commit
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/intel_ddi.c | 93 ++--
1 file changed, 88 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..7589508ff7e2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
ehl_combo_phy_ddi_translations_dp[] = {
{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900 900 0.0 */
};
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[]
= {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x36, 0x00, 0x09 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x35, 0x00, 0x0A },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
+static const struct cnl_ddi_buf_trans
jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db*/
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 200 0.0 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200 250 1.9 */
+ { 0x1, 0x7F, 0x3D, 0x00, 0x02 },/* 200 300 3.5 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250 250 0.0 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 250 300 1.6 */
+ { 0xA, 0x35, 0x3A, 0x00, 0x05 },/* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300 300 0.0 */
+ { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300 350 1.3 */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350 350 0.0 */
+};
+
struct icl_mg_phy_ddi_buf_trans {
u32 cri_txdeemph_override_11_6;
u32 cri_txdeemph_override_5_0;
@@ -1167,6 +1195,57 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder,
return ehl_get_combo_buf_trans_dp(encoder, crtc_state,
n_entries);
}
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+ return icl_combo_phy_ddi_translations_dp_hbr2;
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (dev_priv->vbt.edp.low_vswing) {
+ if (crtc_state->port_clock > 27) {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
+ *n_entries =
ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+ return jsl_combo_phy_ddi_translations_edp_hbr;
+ }
+ }
+
+ return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder,
+
[Intel-gfx] [PATCH v4 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.
Changes since V3 :
- Changed IS_EHL_JSL to IS_JSL_EHL
- Renamed IS_EHL_REVID to IS_JSL_EHL_REVID
- Reverted removal of IS_ELKHARTLAKE and also
added IS_JASPERLAKE
Changes since V2 :
- Added IS_EHL_JSL to replace IS_ELKHARTLAKE
- EHL/JSL PCI ids split added
Changes since V1 :
- IS_ELKHARTLAKE and IS_JASPERLAKE is replaced with
HAS_PCH_MCC(EHL) and HAS_PCH_JSP(JSL) respectively
- Reverted EHL/JSL PCI ids split change
Signed-off-by: Tejas Upadhyay
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 +++---
drivers/gpu/drm/i915/display/intel_display.c | 8
drivers/gpu/drm/i915/display/intel_dp.c| 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 16
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c| 4 ++--
drivers/gpu/drm/i915/i915_drv.h| 9 ++---
drivers/gpu/drm/i915/i915_pci.c| 9 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pch.c | 2 +-
include/drm/i915_pciids.h | 9 ++---
14 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..f7c3731f5a4b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct
intel_encoder *encoder)
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
- if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
+ if (IS_JSL_EHL(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) {
tmp = intel_de_read(dev_priv,
ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
@@ -612,7 +612,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
}
}
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys) {
tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy));
tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index cb93f6cf6d37..c6e87569b3d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2588,7 +2588,7 @@ static int intel_compute_max_dotclk(struct
drm_i915_private *dev_priv)
*/
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
if (dev_priv->cdclk.hw.ref == 24000)
dev_priv->max_cdclk_freq = 552000;
else
@@ -2815,7 +2815,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
dev_priv->cdclk.table = icl_cdclk_table;
- } else if (IS_ELKHARTLAKE(dev_priv)) {
+ } else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display.set_cdclk = bxt_set_cdclk;
dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 157d8c8c605a..d59ceaa2916a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -188,7 +188,7 @@ static bool has_phy_misc(struct drm_i915_private *i915,
enum phy phy)
* PHY-B and may not even have instances of the register for the
* other combo PHY's.
*/
- if (IS_ELKHARTLAKE(i915) ||
+ if (IS_JSL_EHL(i915) ||
IS_ROCKETLAKE(i915))
return phy < PHY_C;
@@ -282,7 +282,7 @@ static bool icl_combo_phy_verify_state(struct
drm_i915_private *dev_priv,
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
- if (IS_ELKHARTLAKE(dev_priv)) {
+ if (IS_JSL_EHL(dev_priv)) {
if (ehl_vbt_ddi_d_present(dev_priv))
expected_val = ICL_PHY_MISC_MUX_DDID;
@@
[Intel-gfx] [PATCH CI] drm/i915/display/ehl: Limit eDP to HBR2
Recent update in documentation defeatured eDP HBR3 for EHL and JSL.
v2:
- Remove dead code in ehl_get_combo_buf_trans()
v3:
- Rebase
BSpec: 32247
Cc: Matt Roper
Cc: Vidya Srinivas
Reviewed-by: Matt Roper
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++---
drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..2c85d4202846 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1142,13 +1142,8 @@ ehl_get_combo_buf_trans_edp(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (dev_priv->vbt.edp.low_vswing) {
- if (crtc_state->port_clock > 54) {
- *n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
- return icl_combo_phy_ddi_translations_edp_hbr3;
- } else {
- *n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
- return icl_combo_phy_ddi_translations_edp_hbr2;
- }
+ *n_entries =
ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
}
return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7429597b57be..4ae79e39c70c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -277,13 +277,20 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
if (intel_phy_is_combo(dev_priv, phy) &&
- !IS_ELKHARTLAKE(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return 54;
return 81;
}
+static int ehl_max_source_rate(struct intel_dp *intel_dp)
+{
+ if (intel_dp_is_edp(intel_dp))
+ return 54;
+
+ return 81;
+}
+
static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
@@ -318,6 +325,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(cnl_rates);
if (IS_GEN(dev_priv, 10))
max_rate = cnl_max_source_rate(intel_dp);
+ else if (IS_ELKHARTLAKE(dev_priv))
+ max_rate = ehl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
} else if (IS_GEN9_LP(dev_priv)) {
--
2.28.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Rename i915_{save,restore}_state()
From: Ville Syrjälä
i915_{save,restore}_state() are actually all about the display.
Currently they are split into display part + SWF part. But since
the SWF part is also related to the display let's just move that
part into its own thing and flip the roles around so that the
current display part is the main function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 116 ++--
drivers/gpu/drm/i915/i915_suspend.h | 4 +-
3 files changed, 60 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 45e719c79183..1c1f5dbb467c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1089,7 +1089,7 @@ static int i915_drm_suspend(struct drm_device *dev)
i915_ggtt_suspend(&dev_priv->ggtt);
- i915_save_state(dev_priv);
+ i915_save_display(dev_priv);
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
intel_opregion_suspend(dev_priv, opregion_target_state);
@@ -1202,7 +1202,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_csr_ucode_resume(dev_priv);
- i915_restore_state(dev_priv);
+ i915_restore_display(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
intel_init_pch_refclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c
b/drivers/gpu/drm/i915/i915_suspend.c
index 7b64e7137270..db2111fc809e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,7 +32,57 @@
#include "i915_reg.h"
#include "i915_suspend.h"
-static void i915_save_display(struct drm_i915_private *dev_priv)
+static void intel_save_swf(struct drm_i915_private *dev_priv)
+{
+ int i;
+
+ /* Scratch space */
+ if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
+ for (i = 0; i < 7; i++) {
+ dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+ dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+ }
+ for (i = 0; i < 3; i++)
+ dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+ } else if (IS_GEN(dev_priv, 2)) {
+ for (i = 0; i < 7; i++)
+ dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+ } else if (HAS_GMCH(dev_priv)) {
+ for (i = 0; i < 16; i++) {
+ dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
+ dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
+ }
+ for (i = 0; i < 3; i++)
+ dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
+ }
+}
+
+static void intel_restore_swf(struct drm_i915_private *dev_priv)
+{
+ int i;
+
+ /* Scratch space */
+ if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
+ for (i = 0; i < 7; i++) {
+ I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
+ I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+ }
+ for (i = 0; i < 3; i++)
+ I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
+ } else if (IS_GEN(dev_priv, 2)) {
+ for (i = 0; i < 7; i++)
+ I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+ } else if (HAS_GMCH(dev_priv)) {
+ for (i = 0; i < 16; i++) {
+ I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
+ I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
+ }
+ for (i = 0; i < 3; i++)
+ I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
+ }
+}
+
+void i915_save_display(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
@@ -43,12 +93,16 @@ static void i915_save_display(struct drm_i915_private
*dev_priv)
if (IS_GEN(dev_priv, 4))
pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS);
+
+ intel_save_swf(dev_priv);
}
-static void i915_restore_display(struct drm_i915_private *dev_priv)
+void i915_restore_display(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
+ intel_restore_swf(dev_priv);
+
if (IS_GEN(dev_priv, 4))
pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS);
@@ -64,61 +118,3 @@ static void i915_restore_display(struct drm_i915_private
*dev_priv)
intel_gmbus_reset(dev_priv);
}
-
-int i915_save_state(struct drm_i915_private *dev_priv)
-{
- int i;
-
- i915_save_display(dev_priv);
-
- /* Scratch space */
- if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
- for (i = 0; i < 7; i++) {
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JSL Voltage swing table
== Series Details ==
Series: drm/i915/jsl: Update JSL Voltage swing table
URL : https://patchwork.freedesktop.org/series/82383/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18624
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/index.html
Known issues
Here are the changes found in Patchwork_18624 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html
Possible fixes
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#1982] / [k.org#205379]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@i915_module_l...@reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-tgl-dsi/igt@i915_module_l...@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
* igt@kms_force_connector_basic@force-connector-state:
- {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][11] ([i915#2203]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-skl-guc/igt@vgem_ba...@unload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-skl-guc/igt@vgem_ba...@unload.html
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@vgem_ba...@unload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@i915_module_load@reload:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@i915_module_l...@reload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-kbl-x1275/igt@i915_module_l...@reload.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) ->
[DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9097 -> Patchwork_18624
CI-20190529: 20190529
CI_DRM_9097: 5f854df6a9500c064bb0be25995ccb696e41 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18624: b4ae1a2562dd58147165df6a51ec4
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2)
== Series Details ==
Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
(rev2)
URL : https://patchwork.freedesktop.org/series/82351/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18625
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/index.html
Known issues
Here are the changes found in Patchwork_18625 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +3 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
Possible fixes
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982] / [k.org#205379]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@i915_module_l...@reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-tgl-dsi/igt@i915_module_l...@reload.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
* igt@kms_force_connector_basic@force-connector-state:
- {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][11] ([i915#2203]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-skl-guc/igt@vgem_ba...@unload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-skl-guc/igt@vgem_ba...@unload.html
Warnings
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) ->
[DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_force_connector_ba...@prune-stale-modes.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-kbl-x1275/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/fi-kbl-x1275/igt@prime_v...@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9097 -> Patchwork_18625
CI-20190529: 20190529
CI_DRM_9097: 5f854df6a9500c064bb0be25995ccb696e41 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18625: 68870e5d103dec6a4a8c09849a771dee2dbd4ecb @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
68870e5d103d drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
==
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JSL Voltage swing table
== Series Details ==
Series: drm/i915/jsl: Update JSL Voltage swing table
URL : https://patchwork.freedesktop.org/series/82386/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0d2e2bc8cea7 drm/i915/jsl: Split EHL/JSL platform info and PCI ids
-:163: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around
'pll->info->id == DPLL_ID_EHL_DPLL4'
#163: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:155:
+ if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
-:276: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible
side-effects?
#276: FILE: drivers/gpu/drm/i915/i915_drv.h:1422:
+#define IS_JSL_EHL(dev_priv) (IS_JASPERLAKE(dev_priv) || \
+ IS_ELKHARTLAKE(dev_priv))
-:287: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#287: FILE: drivers/gpu/drm/i915/i915_drv.h:1564:
+#define IS_JSL_EHL_REVID(p, since, until) \
+ (IS_JSL_EHL(p) && IS_REVID(p, since, until))
-:377: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#377: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E57, info), \
INTEL_VGA_DEVICE(0x4E55, info), \
-:377: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible
side-effects?
#377: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+ INTEL_VGA_DEVICE(0x4E71, info), \
INTEL_VGA_DEVICE(0x4E61, info), \
INTEL_VGA_DEVICE(0x4E57, info), \
INTEL_VGA_DEVICE(0x4E55, info), \
total: 1 errors, 0 warnings, 4 checks, 269 lines checked
fc458df5554c drm/i915/edp/jsl: Update vswing table for HBR and HBR2
-:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or
return
#101: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1227:
+ return jsl_combo_phy_ddi_translations_edp_hbr2;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 141 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/jsl: Update JSL Voltage swing table
== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> bit#0 incorrectly set.
>
> This happens with the
>
> "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
>
> HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
>
> ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
>
> WRPLL parameters (assuming PDIV=7 was the intended setting). This
> corresponds to 262749 PLL frequency/port clock.
>
> Later the driver sets the same mode for which it calculates the same
> dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
>
> Based on the above, let's assume that PDIV=7 was intended and the HW
> just ignores bit#0 in the PDIV register field for this setting, treating
> 100b and 101b encodings the same way.
>
> While at it add the MISSING_CASE() for the p0,p2 divider decodings.
>
> v2: (Ville)
> - Add a define for the incorrect divider value.
> - Emit only a debug message when detecting the incorrect divider value.
> - Use fallthrough from the incorrect divider value case.
> - Add the MISSING_CASE()s.
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index e08684e34078..61cb558c60d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct
> drm_i915_private *i915,
> case DPLL_CFGCR2_PDIV_3:
> p0 = 3;
> break;
> + default:
> + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
> + /*
> + * Incorrect ASUS-Z170M BIOS setting, the HW seems to
> ignore bit#0,
> + * handling it the same way as PDIV_7.
> + */
> + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider
> value, fixing it.\n");
> + else
> + MISSING_CASE(p0);
> +
> + fallthrough;
> case DPLL_CFGCR2_PDIV_7:
> p0 = 7;
> break;
> }
>
> switch (p2) {
> + default:
> + MISSING_CASE(p2);
> + fallthrough;
Is there a specific reason we fall through to the 5 and 7 cases for
bogus values?
> case DPLL_CFGCR2_KDIV_5:
> p2 = 5;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88c215cf97d4..d911583526db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
>
> #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
> _DPLL2_CFGCR1)
> --
> 2.25.1
--
Ville Syrjälä
Intel
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JSL Voltage swing table
== Series Details ==
Series: drm/i915/jsl: Update JSL Voltage swing table
URL : https://patchwork.freedesktop.org/series/82386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18626
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/index.html
Known issues
Here are the changes found in Patchwork_18626 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-y/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-icl-y/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-byt-j1900/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-byt-j1900/igt@i915_pm_...@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982] / [k.org#205379]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-tgl-dsi/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-connector-state:
- {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][19] ([i915#2203]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-skl-guc/igt@vgem_ba...@unload.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-skl-guc/igt@vgem_ba...@unload.html
Warnings
* igt@i915_module_load@reload:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][22] ([i915#62] / [i915#92])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@i915_module_l...@reload.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-kbl-x1275/igt@i915_module_l...@reload.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [DMESG-FAIL][23] ([i915#62]) -> [DMESG-FAIL][24]
([i915#62] / [i915#95])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/fi-kbl-x1275/igt@i915_pm_...@module-reload.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275:
Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote:
> Move the checks to decide whether a fastset is possible during the
> initial commit to an encoder hook. This check is really encoder specific
> and the next patch will also require this adding a DP encoder specific
> check.
>
> v2: Fix negated condition in gen11_dsi_initial_fastset_check().
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 14 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
> drivers/gpu/drm/i915/display/intel_display.c | 29 +--
> .../drm/i915/display/intel_display_types.h| 8 +
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++
> 7 files changed, 80 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index fe946a2e2082..4400e83f783f 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct
> intel_encoder *encoder,
> return ret;
> }
>
> +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->dsc.compression_enable) {
> + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC
> being enabled\n");
> + crtc_state->uapi.mode_changed = true;
> +
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> intel_encoder_destroy(encoder);
> @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->update_pipe = intel_panel_update_backlight;
> encoder->compute_config = gen11_dsi_compute_config;
> encoder->get_hw_state = gen11_dsi_get_hw_state;
> + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b4c520348b3b..4e54c55ec99f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + return intel_dp_initial_fastset_check(encoder, crtc_state);
> +
> + return true;
> +}
> +
> static enum intel_output_type
> intel_ddi_compute_output_type(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 753f202ef6a0..31be63225b10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device
> *dev)
> }
>
> if (crtc_state->hw.active) {
> + struct intel_encoder *encoder;
> +
> /*
>* We've not yet detected sink capabilities
>* (audio,infoframes,etc.) and thus we don't want to
> @@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device
> *dev)
>*/
> crtc_state->uapi.color_mgmt_changed = true;
>
> - /*
> - * FIXME hack to force full modeset when DSC is being
> - * used.
> - *
> - * As long as we do not have full state readout and
> - * config comparison of crtc_state->dsc, we have no way
> - * to ensure reliable fastset. Remove once we have
> - * readout for DSC.
> - */
> - if (crtc_state->dsc.compression_enable) {
> -
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h| 7 +
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
I think we usually use 'sanitize' to mean "hw state is garbage -> must
take steps to sanitize it". This one is just filling in our intel_dp
sidechannel state. So the name isn't super consistnet with existing
practies.
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
I wonder if we should even bother calling it in this case.
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> +const struct intel_crtc_state *crtc_state);
> +
> /*
>* Optional hook, returning true if this encoder allows a fastset
>* during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder
>
Re: [Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
On Mon, Oct 05, 2020 at 11:24:56PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 04:07:08AM +0300, Imre Deak wrote:
> > Move the checks to decide whether a fastset is possible during the
> > initial commit to an encoder hook. This check is really encoder specific
> > and the next patch will also require this adding a DP encoder specific
> > check.
> >
> > v2: Fix negated condition in gen11_dsi_initial_fastset_check().
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c| 14 +
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
> > drivers/gpu/drm/i915/display/intel_display.c | 29 +--
> > .../drm/i915/display/intel_display_types.h| 8 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 22 ++
> > drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++
> > 7 files changed, 80 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index fe946a2e2082..4400e83f783f 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct
> > intel_encoder *encoder,
> > return ret;
> > }
> >
> > +static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state->dsc.compression_enable) {
> > + drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC
> > being enabled\n");
> > + crtc_state->uapi.mode_changed = true;
> > +
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> > {
> > intel_encoder_destroy(encoder);
> > @@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> > encoder->update_pipe = intel_panel_update_backlight;
> > encoder->compute_config = gen11_dsi_compute_config;
> > encoder->get_hw_state = gen11_dsi_get_hw_state;
> > + encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
> > encoder->type = INTEL_OUTPUT_DSI;
> > encoder->cloneable = 0;
> > encoder->pipe_mask = ~0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index b4c520348b3b..4e54c55ec99f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state))
> > + return intel_dp_initial_fastset_check(encoder, crtc_state);
> > +
> > + return true;
> > +}
> > +
> > static enum intel_output_type
> > intel_ddi_compute_output_type(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state,
> > @@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 753f202ef6a0..31be63225b10 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device
> > *dev)
> > }
> >
> > if (crtc_state->hw.active) {
> > + struct intel_encoder *encoder;
> > +
> > /*
> > * We've not yet detected sink capabilities
> > * (audio,infoframes,etc.) and thus we don't want to
> > @@ -17972,22 +17974,17 @@ static int intel_initial_commit(struct drm_device
> > *dev)
> > */
> > crtc_state->uapi.color_mgmt_changed = true;
> >
> > - /*
> > -* FIXME hack to force full modeset when DSC is being
> > -* used.
> > -*
> > -* As long as we do not have full state readout and
> > -* config comparison of crtc_state->dsc, we have no way
> > -* to en
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/jsl: Update JSL Voltage swing table
== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82383/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18624_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_18624_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#198]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl5/igt@gem_...@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-skl6/igt@gem_...@in-flight-suspend.html * igt@gem_eio@kms: - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-snb2/igt@gem_...@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-snb6/igt@gem_...@kms.html * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk9/igt@gem_exec_whis...@basic-fds-priority.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-glk6/igt@gem_exec_whis...@basic-fds-priority.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#2424]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl7/igt@gem_userptr_bl...@unsync-unmap-cycles.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-skl3/igt@gem_userptr_bl...@unsync-unmap-cycles.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#2346]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vbl...@bc-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#1635] / [i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-apl7/igt@kms_flip@flip-vs-expired-vblank-interrupti...@c-dp1.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-skl1/igt@kms_plane_alpha_bl...@pipe-b-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +9 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_vbl...@pipe-a-ts-continuation-dpms-rpm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-skl10/igt@kms_vbl...@pipe-a-ts-continuation-dpms-rpm.html * igt@kms_vblank@pipe-b-wait-forked-busy: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1635] / [i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl8/igt@kms_vbl...@pipe-b-wait-forked-busy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18624/shard-apl8/igt@kms_vbl...@pipe-b-wait-forked-busy.html Possible fixes * igt@gem_exec_reloc@basic
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4)
== Series Details ==
Series: drm/i915/display/ehl: Limit eDP to HBR2 (rev4)
URL : https://patchwork.freedesktop.org/series/82162/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18627
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/index.html
Known issues
Here are the changes found in Patchwork_18627 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
Possible fixes
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@c-edp1.html
* igt@kms_force_connector_basic@force-connector-state:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar
issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@vgem_ba...@unload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@i915_module_load@reload:
- fi-icl-u2: [DMESG-WARN][11] ([i915#289]) -> [DMESG-WARN][12]
([i915#1982] / [i915#289])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@i915_module_l...@reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-icl-u2/igt@i915_module_l...@reload.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) ->
[DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@prime_v...@basic-fence-flip.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-kbl-x1275/igt@prime_v...@basic-fence-flip.html
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][17] ([i915#2029]) -> [FAIL][18] ([i915#2029] /
[i915#2439])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-bdw-5557u/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/fi-bdw-5557u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9097 -> Patchwork_18627
CI-20190529: 20190529
CI_DRM_9097: 5f854df6a950
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Rename i915_{save,restore}_state()
== Series Details ==
Series: drm/i915: Rename i915_{save,restore}_state()
URL : https://patchwork.freedesktop.org/series/82388/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4c7a7c4e0a80 drm/i915: Rename i915_{save,restore}_state()
-:120: CHECK:CAMELCASE: Avoid CamelCase:
#120: FILE: drivers/gpu/drm/i915/i915_suspend.c:91:
+ dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
-:125: CHECK:CAMELCASE: Avoid CamelCase:
#125: FILE: drivers/gpu/drm/i915/i915_suspend.c:95:
+&dev_priv->regfile.saveGCDGMBUS);
total: 0 errors, 0 warnings, 2 checks, 130 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit
On Sat, Oct 03, 2020 at 03:18:44AM +0300, Imre Deak wrote:
> Some BIOSes set an unsupported/imprecise DP link rate (for instance on
> TGL A stepping). Make sure that we do an encoder recompute and a modeset
> in this case.
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d33a3d9fdc3a..df5277c2b9ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3707,6 +3707,18 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + /*
> + * If BIOS has set an unsupported or non-standard link rate for some
> + * reason force an encoder recompute and full modeset.
> + */
> + if (intel_dp_rate_index(intel_dp->source_rates,
> intel_dp->num_source_rates,
> + crtc_state->port_clock) < 0) {
> + drm_dbg_kms(&i915->drm, "Forcing full modeset due to
> unsupported link rate\n");
> + crtc_state->uapi.connectors_changed = true;
> + return false;
> + }
>
> /*
>* FIXME hack to force full modeset when DSC is being used.
> --
> 2.25.1
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h| 7 +
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> +const struct intel_crtc_state *crtc_state);
> +
> /*
>* Optional hook, returning true if this encoder allows a fastset
>* during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> + * @encoder: intel encoder to sanitize
> + * @crtc_state: state for the CRTC connected to the e
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Rename i915_{save,restore}_state()
== Series Details ==
Series: drm/i915: Rename i915_{save,restore}_state()
URL : https://patchwork.freedesktop.org/series/82388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097 -> Patchwork_18628
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/index.html
Known issues
Here are the changes found in Patchwork_18628 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload:
- fi-icl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-y/igt@i915_module_l...@reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-icl-y/igt@i915_module_l...@reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
Possible fixes
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1
similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-connector-state:
- {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-tgl-dsi/igt@kms_force_connector_ba...@force-connector-state.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-skl-guc/igt@vgem_ba...@unload.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-skl-guc/igt@vgem_ba...@unload.html
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@vgem_ba...@unload.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][18] ([i915#62] / [i915#92]) +1 similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) ->
[DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/fi-kbl-x1275/igt@kms_force_connector_ba...@prune-stale-modes.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/fi-kbl-x1275/igt@kms_force_connector_ba...@prune-stale-modes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 38)
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2)
== Series Details == Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications (rev2) URL : https://patchwork.freedesktop.org/series/82351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18625_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18625_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18625_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18625_full: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@all-pipes-forked-move: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-tglb8/igt@kms_cursor_leg...@all-pipes-forked-move.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-tglb8/igt@kms_cursor_leg...@all-pipes-forked-move.html * igt@kms_psr2_su@frontbuffer: - shard-tglb: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-tglb2/igt@kms_psr2...@frontbuffer.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-tglb7/igt@kms_psr2...@frontbuffer.html Known issues Here are the changes found in Patchwork_18625_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#2389]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-hsw6/igt@gem_exec_reloc@basic-many-act...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-hsw4/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][7] -> [WARN][8] ([i915#1519]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-hsw2/igt@i915_pm_rc6_reside...@rc6-fence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-hsw1/igt@i915_pm_rc6_reside...@rc6-fence.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk5/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-glk4/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2346]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-tglb2/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-tglb7/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@pipe-c-torture-bo: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#128]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-tglb5/igt@kms_cursor_leg...@pipe-c-torture-bo.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-tglb8/igt@kms_cursor_leg...@pipe-c-torture-bo.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl3/igt@kms_...@bpc-switch-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-skl10/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +9 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl3/igt@kms_pl...@plane-panning-bottom-right-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shard-skl5/igt@kms_pl...@plane-panning-bottom-right-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#648]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl5/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18625/shar
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> .../drm/i915/display/intel_display_types.h| 7 +
> drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> 6 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..a0805260b224 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sanitize_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sanitize_state = intel_ddi_sanitize_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 31be63225b10..e61311ee8b8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> + if (encoder->sanitize_state)
> + encoder->sanitize_state(encoder, NULL);
> }
>
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..b2b458144f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sanitize any state
> + * stored in the encoder (eg. DP link parameters).
> + */
> + void (*sanitize_state)(struct intel_encoder *encoder,
> +const struct intel_crtc_state *crtc_state);
> +
> /*
>* Optional hook, returning true if this encoder allows a fastset
>* during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..9b6fe3b3b5b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sanitize_state - sanitize the encoder state during init/resume
> + * @encoder: intel encoder to sanitize
> + * @crtc_state: state for the CRTC connected to the e
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/jsl: Update JSL Voltage swing table
== Series Details == Series: drm/i915/jsl: Update JSL Voltage swing table URL : https://patchwork.freedesktop.org/series/82386/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18626_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_18626_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@rcs0: - shard-hsw: [PASS][1] -> [FAIL][2] ([i915#2389]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-hsw6/igt@gem_exec_reloc@basic-many-act...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-hsw2/igt@gem_exec_reloc@basic-many-act...@rcs0.html * igt@gem_mmap_offset@blt-coherency: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#1635]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl1/igt@gem_mmap_off...@blt-coherency.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-apl8/igt@gem_mmap_off...@blt-coherency.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb4/igt@i915_pm...@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][7] -> [FAIL][8] ([i915#96]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_flip@2x-flip-vs-fences-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk7/igt@kms_flip@2x-flip-vs-fences-interrupti...@ab-hdmi-a1-hdmi-a2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-glk8/igt@kms_flip@2x-flip-vs-fences-interrupti...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#79]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl3/igt@kms_...@bpc-switch-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-skl4/igt@kms_...@bpc-switch-dpms.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-kbl1/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-kbl4/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-skl3/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +11 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_vbl...@pipe-a-ts-continuation-dpms-rpm.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-skl8/igt@kms_vbl...@pipe-a-ts-continuation-dpms-rpm.html * igt@kms_vblank@pipe-b-wait-forked-busy: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1635] / [i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl8/igt@kms_vbl...@pipe-b-wait-forked-busy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18626/shard-apl2/igt@kms_vbl...@pipe-b-wait-forked-busy.html * igt@sysfs_timeslice_duration@timeout@vecs0: - shard-iclb: [PASS][25] -> [FA
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev4)
== Series Details == Series: drm/i915/display/ehl: Limit eDP to HBR2 (rev4) URL : https://patchwork.freedesktop.org/series/82162/ State : success == Summary == CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18627_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_18627_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-glk9/igt@gem_exec_whis...@basic-fds-priority.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-glk3/igt@gem_exec_whis...@basic-fds-priority.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#2424]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl7/igt@gem_userptr_bl...@unsync-unmap-cycles.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl6/igt@gem_userptr_bl...@unsync-unmap-cycles.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl8/igt@kms_big...@yf-tiled-32bpp-rotate-270.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-apl8/igt@kms_big...@yf-tiled-32bpp-rotate-270.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#300]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl6/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +11 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl5/igt@kms_cursor_leg...@cursora-vs-flipa-varying-size.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interrupti...@b-edp1.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl3/igt@kms_...@bpc-switch-dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl2/igt@kms_...@bpc-switch-dpms.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl6/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html * igt@perf@polling: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1542]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl3/igt@p...@polling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-skl2/igt@p...@polling.html Possible fixes * igt@feature_discovery@psr2: - shard-iclb: [SKIP][23] ([i915#658]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb8/igt@feature_discov...@psr2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18627/shard-iclb2/igt@feature_discov...@psr2.html * igt@gem_exec_reloc@basic-many-active@vecs0: - shard-glk: [FAIL][25] ([i915#2389]) -> [PASS][26] +2 similar issues [25]
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Mon, Oct 05, 2020 at 11:40:44PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h| 7 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > +const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> > drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> >struct intel_crtc_state *pipe_config);
> >
> > +/*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Optional hook, returning true if this encoder allows a fastset
> > * during the initial commit, false otherwise.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder
> > *encoder,
> > }
> > }
> >
> > +static bool
> > +intel_dp_get_dpcd(struct int
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h| 7 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > +const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
>
> I think we usually use 'sanitize' to mean "hw state is garbage -> must
> take steps to sanitize it". This one is just filling in our intel_dp
> sidechannel state. So the name isn't super consistnet with existing
> practies.
It is called during init/resume time when encoders are sanitized as
well, but yea it's a separate step from HW readout. So I can rename it
for instance (back) to sync_state, or any better idea?
>
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> > drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
>
> I wonder if we should even bother calling it in this case.
Yes, it would be just a nop atm, and can't think what state would need
to be updated, so will remove it.
>
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> >struct intel_crtc_state *pipe_config);
> >
> > +/*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + cons
Re: [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:53 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 07/11] drm/i915/display: Implement DRM infoframe read for
> LSPCON
>
> On Tue, Sep 15, 2020 at 02:30:43AM +0530, Uma Shankar wrote:
> > Implement Read back of HDR metadata infoframes i.e Dynamic Range and
> > Mastering Infoframe for LSPCON devices.
> >
> > v2: Added proper bitmask of enabled infoframes as per Ville's
> > recommendation.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +-
> > drivers/gpu/drm/i915/display/intel_lspcon.h | 4
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 1e40ed473fb9..02b0b5921bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct
> intel_encoder *encoder,
> > hsw_write_infoframe(encoder, crtc_state, type, frame, len); }
> >
> > +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len)
> > +{
> > + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n");
> > + /* It uses the legacy hsw implementation for the same */
> > + hsw_read_infoframe(encoder, crtc_state, type, frame, len); }
>
> Another pointless wrapper.
Sure, will drop this.
> > +
> > static const u8 infoframe_type_to_idx[] = {
> > HDMI_PACKET_TYPE_GENERAL_CONTROL,
> > HDMI_PACKET_TYPE_GAMUT_METADATA,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 565913b8e656..ee77a5381cb5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder
> *encoder,
> >unsigned int type,
> >void *frame, ssize_t len)
> > {
> > - /* FIXME implement this */
> > + /* FIXME implement for AVI Infoframe as well */
> > + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
> > + lspcon_drm_read_infoframe(encoder, crtc_state,
> > +
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> > + frame, VIDEO_DIP_DATA_SIZE);
>
> Again I'd just pass the params through.
Will do the same.
> > }
> >
> > /* HDMI HDR Colorspace Spec Definitions */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > index 3fac05535731..1b9fb531128e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h
> > @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder
> *encoder,
> > const struct intel_crtc_state *crtc_state,
> > unsigned int type,
> > const void *frame, ssize_t len);
> > +void lspcon_drm_read_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + void *frame, ssize_t len);
> > #endif /* __INTEL_LSPCON_H__ */
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:48 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON
> devices
>
> On Tue, Sep 15, 2020 at 02:30:40AM +0530, Uma Shankar wrote:
> > Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry
> > data for HDR using AVI infoframe. LSPCON firmware expects this and
> > though SOC drives DP, for HDMI panel AVI infoframe is sent to the
> > LSPCON device which transfers the same to HDMI sink.
> >
> > v2: Dropped state managed in drm core as per Jani Nikula's suggestion.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index fd05210f4405..b0ca494f1110 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder
> *encoder,
> > /* FIXME implement this */
> > }
> >
> > +/* HDMI HDR Colorspace Spec Definitions */
> > +#define NORMAL_COLORIMETRY_MASK0x3
> > +#define EXTENDED_COLORIMETRY_MASK 0x7
> > +#define HDMI_COLORIMETRY_BT2020_YCC((3 << 0) | (6 << 2) | (0 << 5))
> > +
> > void lspcon_set_infoframes(struct intel_encoder *encoder,
> >bool enable,
> >const struct intel_crtc_state *crtc_state, @@ -551,6
> +556,19 @@
> > void lspcon_set_infoframes(struct intel_encoder *encoder,
> >HDMI_QUANTIZATION_RANGE_LIMITED
> :
> >HDMI_QUANTIZATION_RANGE_FULL);
> >
> > + /*
> > +* Set BT2020 colorspace if driving HDR data
> > +* ToDo: Make this generic and expose all colorspaces for lspcon
> > +*/
> > + if (lspcon->active && lspcon->hdr_supported) {
> > + frame.avi.colorimetry =
> > + HDMI_COLORIMETRY_BT2020_YCC &
> > + NORMAL_COLORIMETRY_MASK;
> > + frame.avi.extended_colorimetry =
> > + (HDMI_COLORIMETRY_BT2020_YCC >> 2) &
> > +EXTENDED_COLORIMETRY_MASK;
> > + }
>
> drm_hdmi_avi_infoframe_colorspace().
>
> Also pls try to match intel_hdmi_compute_avi_infoframe() as closesly as
> possible
> if we can't just outright reuse it. That will make it easier to spot
> differences
> between the two.
Sure, will rectify it.
> > +
> > ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
> > if (ret < 0) {
> > DRM_ERROR("Failed to pack AVI IF\n");
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH v3 2/5] drm/i915: Move the initial fastset commit check to encoder hooks
Move the checks to decide whether a fastset is possible during the
initial commit to an encoder hook. This check is really encoder specific
and the next patch will also require this adding a DP encoder specific
check.
v2: Fix negated condition in gen11_dsi_initial_fastset_check().
v3: Make sure to call the hook for all encoders on the crtc. (Ville)
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/icl_dsi.c| 14 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++
drivers/gpu/drm/i915/display/intel_display.c | 27 ---
.../drm/i915/display/intel_display_types.h| 8 ++
drivers/gpu/drm/i915/display/intel_dp.c | 22 +++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 +++
7 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index fe946a2e2082..4400e83f783f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1668,6 +1668,19 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder
*encoder,
return ret;
}
+static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (crtc_state->dsc.compression_enable) {
+ drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC
being enabled\n");
+ crtc_state->uapi.mode_changed = true;
+
+ return false;
+ }
+
+ return true;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1923,6 +1936,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->update_pipe = intel_panel_update_backlight;
encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
+ encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index b4c520348b3b..4e54c55ec99f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,15 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ return intel_dp_initial_fastset_check(encoder, crtc_state);
+
+ return true;
+}
+
static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -5173,6 +5182,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 753f202ef6a0..755b83d47f9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17951,6 +17951,8 @@ static int intel_initial_commit(struct drm_device *dev)
}
if (crtc_state->hw.active) {
+ struct intel_encoder *encoder;
+
/*
* We've not yet detected sink capabilities
* (audio,infoframes,etc.) and thus we don't want to
@@ -17972,22 +17974,15 @@ static int intel_initial_commit(struct drm_device
*dev)
*/
crtc_state->uapi.color_mgmt_changed = true;
- /*
-* FIXME hack to force full modeset when DSC is being
-* used.
-*
-* As long as we do not have full state readout and
-* config comparison of crtc_state->dsc, we have no way
-* to ensure reliable fastset. Remove once we have
-* readout for DSC.
-*/
- if (crtc_state->dsc.compression_enable) {
- ret = drm_atomic_add_affected_connectors(state,
-
[Intel-gfx] [PATCH v2 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
Atm, if a full modeset is performed during the initial modeset the link
training will happen with uninitialized max DP rate and lane count. Make
sure the corresponding encoder state is initialized by adding an encoder
hook called during driver init and system resume.
A better alternative would be to store all states in the CRTC state and
make this state available for the link re-training code. Also instead of
the DPCD read in the hook there should be really a proper sink HW
readout in place. Both of these require a bigger rework, so for now opting
for this minimal fix to make at least full initial modesets work.
The patch is based on
https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
v2: (Ville)
- s/sanitize_state/sync_state/
- No point in calling the hook when CRTC is disabled, remove the call.
- No point in calling the hook for MST, remove it.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h| 7 +
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
5 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e54c55ec99f..6f7bd67732f2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static void intel_ddi_sync_state(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_sync_state(encoder, crtc_state);
+}
+
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 755b83d47f9c..907e1d155443 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
encoder->base.crtc = &crtc->base;
encoder->get_config(encoder, crtc_state);
+ if (encoder->sync_state)
+ encoder->sync_state(encoder, crtc_state);
} else {
encoder->base.crtc = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5297b2f08ff9..65ae2070576f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -188,6 +188,13 @@ struct intel_encoder {
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+ /*
+* Optional hook called during init/resume to sync any state
+* stored in the encoder (eg. DP link parameters) wrt. the HW state.
+*/
+ void (*sync_state)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
/*
* Optional hook, returning true if this encoder allows a fastset
* during the initial commit, false otherwise.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index df5277c2b9ba..54328eba473c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
}
}
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sync_state - sync the encoder state during init/resume
+ * @encoder: intel encoder to sync
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sync any state stored in the encoder wrt. HW state during driver init
+ * and system resume.
+ */
+void intel_dp_sync_state(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ /*
+*
[Intel-gfx] [PATCH v3 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
Atm, if a full modeset is performed during the initial modeset the link
training will happen with uninitialized max DP rate and lane count. Make
sure the corresponding encoder state is initialized by adding an encoder
hook called during driver init and system resume.
A better alternative would be to store all states in the CRTC state and
make this state available for the link re-training code. Also instead of
the DPCD read in the hook there should be really a proper sink HW
readout in place. Both of these require a bigger rework, so for now opting
for this minimal fix to make at least full initial modesets work.
The patch is based on
https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
v2: (Ville)
- s/sanitize_state/sync_state/
- No point in calling the hook when CRTC is disabled, remove the call.
- No point in calling the hook for MST, remove it.
v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h| 7 +
drivers/gpu/drm/i915/display/intel_dp.c | 28 +++
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
5 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4e54c55ec99f..6f7bd67732f2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
}
+static void intel_ddi_sync_state(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_sync_state(encoder, crtc_state);
+}
+
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
enum port port)
encoder->update_pipe = intel_ddi_update_pipe;
encoder->get_hw_state = intel_ddi_get_hw_state;
encoder->get_config = intel_ddi_get_config;
+ encoder->sync_state = intel_ddi_sync_state;
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
encoder->suspend = intel_dp_encoder_suspend;
encoder->get_power_domains = intel_ddi_get_power_domains;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 755b83d47f9c..907e1d155443 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
encoder->base.crtc = &crtc->base;
encoder->get_config(encoder, crtc_state);
+ if (encoder->sync_state)
+ encoder->sync_state(encoder, crtc_state);
} else {
encoder->base.crtc = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5297b2f08ff9..65ae2070576f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -188,6 +188,13 @@ struct intel_encoder {
void (*get_config)(struct intel_encoder *,
struct intel_crtc_state *pipe_config);
+ /*
+* Optional hook called during init/resume to sync any state
+* stored in the encoder (eg. DP link parameters) wrt. the HW state.
+*/
+ void (*sync_state)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+
/*
* Optional hook, returning true if this encoder allows a fastset
* during the initial commit, false otherwise.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index df5277c2b9ba..239016dcd544 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
}
}
+static bool
+intel_dp_get_dpcd(struct intel_dp *intel_dp);
+
+/**
+ * intel_dp_sync_state - sync the encoder state during init/resume
+ * @encoder: intel encoder to sync
+ * @crtc_state: state for the CRTC connected to the encoder
+ *
+ * Sync any state stored in the encoder wrt. HW state during driver init
+ * and system resume.
+ */
+void intel_dp_sync_state(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state)
+{
+ struct in
Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > bit#0 incorrectly set.
> >
> > This happens with the
> >
> > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> >
> > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> >
> > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
> >
> > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > corresponds to 262749 PLL frequency/port clock.
> >
> > Later the driver sets the same mode for which it calculates the same
> > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> >
> > Based on the above, let's assume that PDIV=7 was intended and the HW
> > just ignores bit#0 in the PDIV register field for this setting, treating
> > 100b and 101b encodings the same way.
> >
> > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> >
> > v2: (Ville)
> > - Add a define for the incorrect divider value.
> > - Emit only a debug message when detecting the incorrect divider value.
> > - Use fallthrough from the incorrect divider value case.
> > - Add the MISSING_CASE()s.
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index e08684e34078..61cb558c60d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct
> > drm_i915_private *i915,
> > case DPLL_CFGCR2_PDIV_3:
> > p0 = 3;
> > break;
> > + default:
> > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
>
> Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
So we can use fallthrough for both this one and the default case.
>
> > + /*
> > +* Incorrect ASUS-Z170M BIOS setting, the HW seems to
> > ignore bit#0,
> > +* handling it the same way as PDIV_7.
> > +*/
> > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider
> > value, fixing it.\n");
> > + else
> > + MISSING_CASE(p0);
> > +
> > + fallthrough;
> > case DPLL_CFGCR2_PDIV_7:
> > p0 = 7;
> > break;
> > }
> >
> > switch (p2) {
> > + default:
> > + MISSING_CASE(p2);
> > + fallthrough;
>
> Is there a specific reason we fall through to the 5 and 7 cases for
> bogus values?
Just to default to dividers that result in the minimum PLL freq.
>
> > case DPLL_CFGCR2_KDIV_5:
> > p2 = 5;
> > break;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 88c215cf97d4..d911583526db 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > +#define DPLL_CFGCR2_PDIV_7_INVALID(5 << 2)
> > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> >
> > #define DPLL_CFGCR1(id)_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
> > _DPLL2_CFGCR1)
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Mon, Oct 05, 2020 at 11:51:02PM +0300, Ville Syrjälä wrote:
> On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > Atm, if a full modeset is performed during the initial modeset the link
> > training will happen with uninitialized max DP rate and lane count. Make
> > sure the corresponding encoder state is initialized by adding an encoder
> > hook called during driver init and system resume.
> >
> > A better alternative would be to store all states in the CRTC state and
> > make this state available for the link re-training code. Also instead of
> > the DPCD read in the hook there should be really a proper sink HW
> > readout in place. Both of these require a bigger rework, so for now opting
> > for this minimal fix to make at least full initial modesets work.
> >
> > The patch is based on
> > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> >
> > Cc: Ville Syrjälä
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > .../drm/i915/display/intel_display_types.h| 7 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> > 6 files changed, 62 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4e54c55ec99f..a0805260b224 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> > *encoder,
> > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > }
> >
> > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > +const struct intel_crtc_state *crtc_state)
> > +{
> > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > + intel_dp_sanitize_state(encoder, crtc_state);
> > +}
> > +
> > static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > encoder->update_pipe = intel_ddi_update_pipe;
> > encoder->get_hw_state = intel_ddi_get_hw_state;
> > encoder->get_config = intel_ddi_get_config;
> > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > encoder->suspend = intel_dp_encoder_suspend;
> > encoder->get_power_domains = intel_ddi_get_power_domains;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 31be63225b10..e61311ee8b8c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(struct
> > drm_device *dev)
> >
> > encoder->base.crtc = &crtc->base;
> > encoder->get_config(encoder, crtc_state);
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, crtc_state);
> > } else {
> > encoder->base.crtc = NULL;
> > + if (encoder->sanitize_state)
> > + encoder->sanitize_state(encoder, NULL);
> > }
> >
> > drm_dbg_kms(&dev_priv->drm,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5297b2f08ff9..b2b458144f5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -188,6 +188,13 @@ struct intel_encoder {
> > void (*get_config)(struct intel_encoder *,
> >struct intel_crtc_state *pipe_config);
> >
> > +/*
> > + * Optional hook called during init/resume to sanitize any state
> > + * stored in the encoder (eg. DP link parameters).
> > + */
> > + void (*sanitize_state)(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +
> > /*
> > * Optional hook, returning true if this encoder allows a fastset
> > * during the initial commit, false otherwise.
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index df5277c2b9ba..9b6fe3b3b5b2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_encoder
> > *encoder,
> > }
> > }
> >
> > +static bool
> > +intel_dp_get_dpcd(struct int
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Rename i915_{save,restore}_state()
== Series Details ==
Series: drm/i915: Rename i915_{save,restore}_state()
URL : https://patchwork.freedesktop.org/series/82388/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9097_full -> Patchwork_18628_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_18628_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][1] -> [WARN][2] ([i915#1519])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-hsw2/igt@i915_pm_rc6_reside...@rc6-idle.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-hsw4/igt@i915_pm_rc6_reside...@rc6-idle.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] /
[i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-apl8/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-apl8/igt@kms_big...@yf-tiled-32bpp-rotate-270.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#300])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#2346]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl4/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl8/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#79])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl1/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl10/igt@kms_flip@flip-vs-expired-vbl...@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#2122])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-edp1.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interrupti...@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-render.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-tglb7/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +8
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-kbl1/igt@kms_...@bpc-switch-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-kbl4/igt@kms_...@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
+2 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +13
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl5/igt@kms_plane_cur...@pipe-a-viewport-size-128.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl7/igt@kms_plane_cur...@pipe-a-viewport-size-128.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar
issues
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@sysfs_preempt_timeout@timeout@bcs0:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#2060])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9097/shard-skl5/igt@sysfs_preempt_timeout@time...@bcs0.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18628/shard-skl2/igt@sysfs_preempt_timeout@time...@bcs0.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Update gen12 forcewake table
On Fri, 2020-10-02 at 20:29 -0700, Matt Roper wrote:
> The bspec's forcewake page was very stale and out of date for recent
> platforms. The hardware team finally provided us with an updated gen12
> table (which applies to TGL, RKL, and DG1) and there are a lot of
> changes.
>
> Bspec: 66696
> Cc: Caz Yokoyama <
> caz.yokoy...@intel.com
> >
> Cc: Daniele Ceraolo Spurio <
> daniele.ceraolospu...@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.ro...@intel.com
> >
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 66 +
> 1 file changed, 40 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 263ffcb832b7..e14dbc1c7e22 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1124,44 +1124,58 @@ static const struct intel_forcewake_range
> __gen11_fw_ranges[] = {
> GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
> };
>
> -/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
> +/*
> + * *Must* be sorted by offset ranges! See intel_fw_table_check().
> + *
> + * Note that the spec lists several reserved/unused ranges that don't
> + * actually contain any registers. In the table below we'll combine those
> + * reserved ranges with either the preceding or following range to keep the
> + * table small and lookups fast.
What about add those reserved/unused ranges but leave those commented?
That would make easier to match the table with spec.
> + */
> static const struct intel_forcewake_range __gen12_fw_ranges[] = {
> - GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
> + GEN_FW_RANGE(0x0, 0x1fff, 0),
> GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_BLITTER),
> GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
> GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
> GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
> GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0x8180, 0x81ff, 0),
> + GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_BLITTER),
> GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
> + GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0x9560, 0x97ff, 0),
> GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0xe900, 0x147ff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x14800, 0x148ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x14900, 0x19fff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x1a000, 0x1a7ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x1a800, 0x1afff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x1b000, 0x1bfff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x1c000, 0x243ff, FORCEWAKE_BLITTER),
> - GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
> - GEN_FW_RANGE(0x24800, 0x3, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0xd000, 0xd7ff, 0),
> + GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x14800, 0x1, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0x2, 0x20fff, FORCEWAKE_MEDIA_VDBOX0),
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2),
> + GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x24000, 0x2417f, 0),
> + GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER),
> + GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_BLITTER),
> + GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0),
> + GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2),
> + GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0),
> + GEN_FW_RANGE(0x25a80, 0x2, FORCEWAKE_MEDIA_VDBOX2),
> + GEN_FW_RANGE(0x3, 0x3, FORCEWAKE_BLITTER),
> GEN_FW_RANGE(0x4, 0x1b, 0),
> GEN_FW_RANGE(0x1c, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
> - GEN_FW
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock (rev6)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9098 -> Patchwork_18629
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/index.html
Known issues
Here are the changes found in Patchwork_18629 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-bsw-kefka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-before-cursor-atomic.html
Possible fixes
* {igt@core_hotunplug@unbind-rebind}:
- {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-tgl-dsi/igt@core_hotunp...@unbind-rebind.html
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982] / [k.org#205379]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-tgl-dsi/igt@i915_module_l...@reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-tgl-dsi/igt@i915_module_l...@reload.html
- fi-apl-guc: [DMESG-WARN][9] ([i915#1635] / [i915#1982]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-apl-guc/igt@i915_module_l...@reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-apl-guc/igt@i915_module_l...@reload.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@vgem_ba...@unload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@debugfs_test@read_all_entries:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@debugfs_test@read_all_entries.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) ->
[DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-kbl-x1275/igt@kms_force_connector_ba...@force-connector-state.html
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][17] ([i915#2029] / [i915#2439]) -> [FAIL][18]
([i915#2029])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/fi-bdw-5557u/igt@run...@aborted.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/fi-bdw-5557u/igt@run...@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9098 -> Patchwork_18629
CI-20190529: 20190529
C
Re: [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:51 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 06/11] drm/i915/display: Implement infoframes readback for
> LSPCON
>
> On Tue, Sep 15, 2020 at 02:30:42AM +0530, Uma Shankar wrote:
> > Implemented Infoframes enabled readback for LSPCON devices.
> > This will help align the implementation with state readback
> > infrastructure.
> >
> > v2: Added proper bitmask of enabled infoframes as per Ville's
> > recommendation.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 57
> > -
> > 1 file changed, 55 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 60863b825cc5..565913b8e656 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder
> *encoder,
> > buf, ret);
> > }
> >
> > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux
> > +*aux) {
> > + int ret;
> > + u32 val = 0;
> > + u16 reg = LSPCON_MCA_AVI_IF_CTRL;
> > +
> > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > + if (ret < 0) {
> > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > + return false;
> > + }
> > +
> > + return val & LSPCON_MCA_AVI_IF_KICKOFF; }
> > +
> > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct
> > +drm_dp_aux *aux) {
> > + int ret;
> > + u32 val = 0;
> > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
> > +
> > + ret = drm_dp_dpcd_read(aux, reg, &val, 1);
> > + if (ret < 0) {
> > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg);
> > + return false;
> > + }
> > +
> > + return val & LSPCON_PARADE_AVI_IF_KICKOFF; }
> > +
> > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
> > const struct intel_crtc_state *pipe_config) {
> > - /* FIXME actually read this from the hw */
> > - return 0;
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + bool infoframes_enabled;
> > + u32 val = 0;
> > + u32 mask, tmp;
> > +
> > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > + infoframes_enabled =
> _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
> > + else
> > + infoframes_enabled =
> > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
> > +
> > + if (infoframes_enabled)
> > + val |= VIDEO_DIP_ENABLE_AVI_HSW;
>
> Still not a fan of abusing the HSW specific reg values here.
I just kept it so that rest of the infrastructure can be re-used easily. So the
AVI and GMP
bit fields will get re-used and will not require any separate handling.
> > +
> > + if (lspcon->hdr_supported) {
> > + tmp = intel_de_read(dev_priv,
> > + HSW_TVIDEO_DIP_CTL(pipe_config-
> >cpu_transcoder));
> > + mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > +
> > + if (tmp & mask)
> > + val |= mask;
> > + }
> > +
> > + return val;
> > }
> >
> > void lspcon_resume(struct intel_lspcon *lspcon)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:44 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9
> devices
>
> On Tue, Sep 15, 2020 at 02:30:39AM +0530, Uma Shankar wrote:
> > Attach HDR property for Gen9 devices with MCA LSPCON chips.
> >
> > v2: Cleaned HDR property attachment logic based on capability as per
> > Jani Nikula's suggestion.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 5e2d7ca1d20f..fd05210f4405 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port
> > *dig_port)
> >
> > lspcon_detect_hdr_capability(lspcon);
> >
> > + if (lspcon->hdr_supported)
> > + drm_object_attach_property(&connector->base,
> > + connector->dev-
> >mode_config.hdr_output_metadata_property,
> > + 0);
>
> Hmm. This hdr capability detection is going to cause us extra grief when
> looking
> at Kai-Heng's patch to defer lspcon detection until hotplug time. Not quite
> sure
> what to do about that though.
Yeah Ville, saw your comments and with Kai's change merge, I am thinking how to
attach
this dynamically.
Can we just assume that Lspcon will support HDR as is the case in Gen9. We can
just attach this
unconditionally at init if Lspcon is exposed from VBT. Will this be acceptable
or Any better ideas ?
> > +
> > connector->ycbcr_420_allowed = true;
> > lspcon->active = true;
> > DRM_DEBUG_KMS("Success: LSPCON init\n");
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:49 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org; Anand, Vipin
> Subject: Re: [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
>
> On Tue, Sep 15, 2020 at 02:30:41AM +0530, Uma Shankar wrote:
> > Enable HDR for LSPCON based on Parade along with MCA.
> >
> > Signed-off-by: Uma Shankar
> > Signed-off-by: Vipin Anand
> > ---
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ---
> > 1 file changed, 8 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index b0ca494f1110..60863b825cc5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -36,6 +36,7 @@
> > #define LSPCON_VENDOR_MCA_OUI 0x0060AD
> >
> > #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
> > +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
> >
> > /* AUX addresses to write MCA AVI IF */ #define
> > LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 @@ -112,16 +113,20 @@ static
> void
> > lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
> > container_of(lspcon, struct intel_digital_port, lspcon);
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
> > + u32 lspcon_hdr_status_reg;
> > u8 hdr_caps;
> > int ret;
> >
> > - /* Enable HDR for MCA based LSPCON devices */
> > if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > - ret = drm_dp_dpcd_read(&dp->aux,
> DPCD_MCA_LSPCON_HDR_STATUS,
> > - &hdr_caps, 1);
> > + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS;
> > + else if (lspcon->vendor == LSPCON_VENDOR_PARADE)
> > + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS;
> > else
> > return;
>
> That could be small helper function.
Ok, will add the same.
> >
> > + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg,
> > + &hdr_caps, 1);
> > +
> > if (ret < 0) {
> > drm_dbg_kms(dev, "hdr capability detection failed\n");
> > lspcon->hdr_supported = false;
> > @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder
> *encoder,
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> >
> > - /*
> > -* Supporting HDR on MCA LSPCON
> > -* Todo: Add support for Parade later
> > -*/
> > - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> > - lspcon->vendor != LSPCON_VENDOR_MCA)
> > - return;
> > -
> > switch (type) {
> > case HDMI_INFOFRAME_TYPE_AVI:
> > if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > --
> > 2.26.2
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume
On Mon, Oct 05, 2020 at 11:46:17PM +0300, Imre Deak wrote:
> On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrjälä wrote:
> > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote:
> > > Atm, if a full modeset is performed during the initial modeset the link
> > > training will happen with uninitialized max DP rate and lane count. Make
> > > sure the corresponding encoder state is initialized by adding an encoder
> > > hook called during driver init and system resume.
> > >
> > > A better alternative would be to store all states in the CRTC state and
> > > make this state available for the link re-training code. Also instead of
> > > the DPCD read in the hook there should be really a proper sink HW
> > > readout in place. Both of these require a bigger rework, so for now opting
> > > for this minimal fix to make at least full initial modesets work.
> > >
> > > The patch is based on
> > > https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
> > >
> > > Cc: Ville Syrjälä
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +
> > > drivers/gpu/drm/i915/display/intel_display.c | 4 +++
> > > .../drm/i915/display/intel_display_types.h| 7 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++
> > > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++
> > > 6 files changed, 62 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 4e54c55ec99f..a0805260b224 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> > > *encoder,
> > > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> > > }
> > >
> > > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder,
> > > + const struct intel_crtc_state *crtc_state)
> > > +{
> > > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
> > > + intel_dp_sanitize_state(encoder, crtc_state);
> > > +}
> >
> > I think we usually use 'sanitize' to mean "hw state is garbage -> must
> > take steps to sanitize it". This one is just filling in our intel_dp
> > sidechannel state. So the name isn't super consistnet with existing
> > practies.
>
> It is called during init/resume time when encoders are sanitized as
> well, but yea it's a separate step from HW readout. So I can rename it
> for instance (back) to sync_state, or any better idea?
All I know is that I suck at naming things.
>
> >
> > > +
> > > static bool intel_ddi_initial_fastset_check(struct intel_encoder
> > > *encoder,
> > > struct intel_crtc_state *crtc_state)
> > > {
> > > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private
> > > *dev_priv, enum port port)
> > > encoder->update_pipe = intel_ddi_update_pipe;
> > > encoder->get_hw_state = intel_ddi_get_hw_state;
> > > encoder->get_config = intel_ddi_get_config;
> > > + encoder->sanitize_state = intel_ddi_sanitize_state;
> > > encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> > > encoder->suspend = intel_dp_encoder_suspend;
> > > encoder->get_power_domains = intel_ddi_get_power_domains;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 31be63225b10..e61311ee8b8c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -18725,8 +18725,12 @@ static void
> > > intel_modeset_readout_hw_state(struct drm_device *dev)
> > >
> > > encoder->base.crtc = &crtc->base;
> > > encoder->get_config(encoder, crtc_state);
> > > + if (encoder->sanitize_state)
> > > + encoder->sanitize_state(encoder, crtc_state);
> > > } else {
> > > encoder->base.crtc = NULL;
> > > + if (encoder->sanitize_state)
> > > + encoder->sanitize_state(encoder, NULL);
> >
> > I wonder if we should even bother calling it in this case.
>
> Yes, it would be just a nop atm, and can't think what state would need
> to be updated, so will remove it.
>
> >
> > > }
> > >
> > > drm_dbg_kms(&dev_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5297b2f08ff9..b2b458144f5a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -188,6 +188,13 @@ struct intel_encoder {
> > > void (*get_config)(struct intel_encoder *,
> > > struct intel_crtc_state *pipe_confi
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with fake lmem
On Thu, Oct 01, 2020 at 08:39:43AM +, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: don't conflate is_dgfx with
fake lmem
URL : https://patchwork.freedesktop.org/series/82283/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9085_full -> Patchwork_18604_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18604_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18604_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18604_full:
### IGT changes ###
Possible regressions
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-skl: NOTRUN -> [INCOMPLETE][1]
it would be suspicious if it was on the skl with fake lmem. Nothing
related here though.
Lucas De Marchi
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl4/igt@kms_color_chamel...@pipe-a-ctm-0-75.html
Known issues
Here are the changes found in Patchwork_18604_full that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#118] / [i915#95])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-glk8/igt@gem_exec_whis...@basic-contexts-priority.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-glk2/igt@gem_exec_whis...@basic-contexts-priority.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#151])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl7/igt@i915_pm_...@system-suspend.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl10/igt@i915_pm_...@system-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-right-edge:
- shard-skl: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +10 similar
issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl5/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl5/igt@kms_cursor_edge_w...@pipe-b-64x64-right-edge.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-kbl4/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-kbl7/igt@kms_flip@flip-vs-suspend-interrupti...@b-dp1.html
* igt@kms_flip_tiling@flip-y-tiled:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#1635] /
[i915#1982])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-apl7/igt@kms_flip_til...@flip-y-tiled.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-apl7/igt@kms_flip_til...@flip-y-tiled.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1
similar issue
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-tglb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][14] -> [FAIL][15] ([fdo#108145] / [i915#265])
+1 similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][18] -> [FAIL][19] ([i915#1635] / [i915#31])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-apl4/igt@kms_setm...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18604/shard-apl8/igt@kms_setm...@basic.html
Possible fixes
* {igt@core_hotunplug@unbind-rebind}:
- shard-skl: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21] +3
similar issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9085/shard-skl2/igt@core_hotunp...@unbind-rebind
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications
On Sat, 2020-10-03 at 01:26 +, Patchwork wrote:
> Patch Details
> Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer
> modifications
> URL: https://patchwork.freedesktop.org/series/82351/
> State:failure
> Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18617/index.html
> CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18617_full
> Summary
> FAILURE
>
> Serious unknown changes coming with Patchwork_18617_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18617_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> Possible new issues
> Here are the unknown changes that may have been introduced in
> Patchwork_18617_full:
>
> IGT changes
> Possible regressions
> igt@gem_userptr_blits@unsync-unmap-cycles:
>
> shard-skl: PASS -> TIMEOUT
> igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge:
>
> shard-hsw: PASS -> INCOMPLETE
The two above don't are not related as this change only affects TGL.
> igt@kms_cursor_legacy@all-pipes-forked-bo:
>
> shard-tglb: PASS -> INCOMPLETE
Something went pretty wrong in this test executing by the logs but don't look
related.
> igt@kms_psr2_su@frontbuffer:
>
> shard-tglb: PASS -> FAIL +1 similar issue
This failure is expected with this change.
> Suppressed
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> {igt@kms_async_flips@test-time-stamp}:
> shard-tglb: PASS -> FAIL
> Known issues
> Here are the changes found in Patchwork_18617_full that come from known
> issues:
>
> IGT changes
> Issues hit
> igt@gem_exec_create@madvise:
>
> shard-glk: PASS -> DMESG-WARN (i915#118 / i915#95)
> igt@i915_pm_rc6_residency@rc6-idle:
>
> shard-hsw: PASS -> FAIL (i915#1860)
> igt@kms_cursor_crc@pipe-b-cursor-suspend:
>
> shard-skl: PASS -> INCOMPLETE (i915#300)
> igt@kms_cursor_legacy@flip-vs-cursor-atomic:
>
> shard-tglb: PASS -> FAIL (i915#2346) +3 similar issues
> igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
>
> shard-kbl: PASS -> DMESG-WARN (i915#1982)
> igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
>
> shard-apl: PASS -> DMESG-WARN (i915#1635 / i915#1982)
> igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
>
> shard-skl: PASS -> DMESG-WARN (i915#1982) +9 similar issues
> igt@kms_flip@flip-vs-expired-vblank@c-edp1:
>
> shard-skl: PASS -> FAIL (i915#79)
> igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>
> shard-kbl: PASS -> DMESG-WARN (i915#180) +3 similar issues
> igt@kms_flip_tiling@flip-changes-tiling:
>
> shard-skl: PASS -> FAIL (i915#699)
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
>
> shard-skl: PASS -> FAIL (i915#49) +1 similar issue
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
>
> shard-tglb: PASS -> DMESG-WARN (i915#1982) +1 similar issue
> igt@kms_hdr@bpc-switch-dpms:
>
> shard-skl: PASS -> FAIL (i915#1188)
> igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
>
> shard-iclb: PASS -> INCOMPLETE (i915#1185 / i915#250)
> igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>
> shard-skl: PASS -> FAIL (fdo#108145 / i915#265) +1 similar issue
> igt@kms_psr@psr2_sprite_mmap_gtt:
>
> shard-iclb: PASS -> SKIP (fdo#109441)
> Possible fixes
> igt@gem_exec_reloc@basic-cpu-gtt-active:
>
> shard-skl: DMESG-WARN (i915#1982) -> PASS +3 similar issues
> igt@gem_exec_reloc@basic-many-active@vecs0:
>
> shard-glk: FAIL (i915#2389) -> PASS
> {igt@kms_async_flips@async-flip-with-page-flip-events}:
>
> shard-kbl: FAIL (i915#2521) -> PASS
> igt@kms_big_fb@linear-8bpp-rotate-0:
>
> shard-apl: DMESG-WARN (i915#1635 / i915#1982) -> PASS
> igt@kms_flip@plain-flip-fb-recreate@b-edp1:
>
> shard-skl: FAIL (i915#2122) -> PASS
> igt@kms_flip_tiling@flip-changes-tiling-yf:
>
> shard-kbl: DMESG-WARN (i915#1982) -> PASS
> igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
>
> shard-tglb: DMESG-WARN (i915#1982) -> PASS
> igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>
> shard-skl: FAIL (fdo#108145 / i915#265) -> PASS
> igt@kms_psr@psr2_cursor_mmap_cpu:
>
> shard-iclb: SKIP (fdo#109441) -> PASS +1 similar issue
> igt@kms_setmode@basic:
>
> shard-glk: FAIL (i915#31) -> PASS
> igt@kms_vblank@pipe-b-ts-continuation-suspend:
>
> shard-kbl: DMESG-WARN (i915#180) -> PASS
> Warnings
> igt@i915_pm_rc6_residency@rc6-idle:
>
> shard-iclb: FAIL (i915#1515) -> WARN (i915#1515)
> igt@kms_cursor_legacy@flip-vs-cursor-atomic:
>
> shard-skl: DMESG-FAIL (i915#1982) -> DMESG-WARN (i915#1982)
> igt@kms_vblank@pipe-a-ts-continuation-suspend:
>
> shard-skl: INCOMPLETE (i915#198) -> DMESG-WARN (i915#1982)
> igt@runner@aborted:
>
> shard-skl: FAIL (i915#1436) -> FAIL (i915#1611 / i915#2029)
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (
Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote:
> On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > > bit#0 incorrectly set.
> > >
> > > This happens with the
> > >
> > > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> > >
> > > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> > >
> > > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1,
> > > kdiv=1
> > >
> > > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > > corresponds to 262749 PLL frequency/port clock.
> > >
> > > Later the driver sets the same mode for which it calculates the same
> > > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
> > >
> > > Based on the above, let's assume that PDIV=7 was intended and the HW
> > > just ignores bit#0 in the PDIV register field for this setting, treating
> > > 100b and 101b encodings the same way.
> > >
> > > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> > >
> > > v2: (Ville)
> > > - Add a define for the incorrect divider value.
> > > - Emit only a debug message when detecting the incorrect divider value.
> > > - Use fallthrough from the incorrect divider value case.
> > > - Add the MISSING_CASE()s.
> > >
> > > Cc: Ville Syrjälä
> > > Signed-off-by: Imre Deak
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > 2 files changed, 15 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > index e08684e34078..61cb558c60d1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct
> > > drm_i915_private *i915,
> > > case DPLL_CFGCR2_PDIV_3:
> > > p0 = 3;
> > > break;
> > > + default:
> > > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
> >
> > Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
>
> So we can use fallthrough for both this one and the default case.
IMO trying to be fancy just makes the code harder to read.
>
> >
> > > + /*
> > > + * Incorrect ASUS-Z170M BIOS setting, the HW seems to
> > > ignore bit#0,
> > > + * handling it the same way as PDIV_7.
> > > + */
> > > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider
> > > value, fixing it.\n");
> > > + else
> > > + MISSING_CASE(p0);
> > > +
> > > + fallthrough;
> > > case DPLL_CFGCR2_PDIV_7:
> > > p0 = 7;
> > > break;
> > > }
> > >
> > > switch (p2) {
> > > + default:
> > > + MISSING_CASE(p2);
> > > + fallthrough;
> >
> > Is there a specific reason we fall through to the 5 and 7 cases for
> > bogus values?
>
> Just to default to dividers that result in the minimum PLL freq.
I'd probably just set them to zero if they're bogus. Looks like
that should already give us warn and just return zero as the freq.
>
> >
> > > case DPLL_CFGCR2_KDIV_5:
> > > p2 = 5;
> > > break;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 88c215cf97d4..d911583526db 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > > +#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
> > > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> > >
> > > #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
> > > _DPLL2_CFGCR1)
> > > --
> > > 2.25.1
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
On Tue, Oct 06, 2020 at 02:37:58AM +0300, Ville Syrjälä wrote:
> On Mon, Oct 05, 2020 at 11:26:05PM +0300, Imre Deak wrote:
> > On Mon, Oct 05, 2020 at 11:08:19PM +0300, Ville Syrjälä wrote:
> > > On Sat, Oct 03, 2020 at 03:18:42AM +0300, Imre Deak wrote:
> > > > The BIOS of at least one ASUS-Z170M system with an SKL I have programs
> > > > the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
> > > > bit#0 incorrectly set.
> > > >
> > > > This happens with the
> > > >
> > > > "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
> > > >
> > > > HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
> > > >
> > > > ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1,
> > > > kdiv=1
> > > >
> > > > WRPLL parameters (assuming PDIV=7 was the intended setting). This
> > > > corresponds to 262749 PLL frequency/port clock.
> > > >
> > > > Later the driver sets the same mode for which it calculates the same
> > > > dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7
> > > > encoding).
> > > >
> > > > Based on the above, let's assume that PDIV=7 was intended and the HW
> > > > just ignores bit#0 in the PDIV register field for this setting, treating
> > > > 100b and 101b encodings the same way.
> > > >
> > > > While at it add the MISSING_CASE() for the p0,p2 divider decodings.
> > > >
> > > > v2: (Ville)
> > > > - Add a define for the incorrect divider value.
> > > > - Emit only a debug message when detecting the incorrect divider value.
> > > > - Use fallthrough from the incorrect divider value case.
> > > > - Add the MISSING_CASE()s.
> > > >
> > > > Cc: Ville Syrjälä
> > > > Signed-off-by: Imre Deak
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 14 ++
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > 2 files changed, 15 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > index e08684e34078..61cb558c60d1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > > > @@ -1602,12 +1602,26 @@ static int skl_ddi_wrpll_get_freq(struct
> > > > drm_i915_private *i915,
> > > > case DPLL_CFGCR2_PDIV_3:
> > > > p0 = 3;
> > > > break;
> > > > + default:
> > > > + if (p0 == DPLL_CFGCR2_PDIV_7_INVALID)
> > >
> > > Why not just 'case DPLL_CFGCR2_PDIV_7_INVALID:' ?
> >
> > So we can use fallthrough for both this one and the default case.
>
> IMO trying to be fancy just makes the code harder to read.
>
> > > > + /*
> > > > +* Incorrect ASUS-Z170M BIOS setting, the HW
> > > > seems to ignore bit#0,
> > > > +* handling it the same way as PDIV_7.
> > > > +*/
> > > > + drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV
> > > > divider value, fixing it.\n");
> > > > + else
> > > > + MISSING_CASE(p0);
> > > > +
> > > > + fallthrough;
> > > > case DPLL_CFGCR2_PDIV_7:
> > > > p0 = 7;
> > > > break;
> > > > }
> > > >
> > > > switch (p2) {
> > > > + default:
> > > > + MISSING_CASE(p2);
> > > > + fallthrough;
> > >
> > > Is there a specific reason we fall through to the 5 and 7 cases for
> > > bogus values?
> >
> > Just to default to dividers that result in the minimum PLL freq.
>
> I'd probably just set them to zero if they're bogus. Looks like
> that should already give us warn and just return zero as the freq.
Ok.
> > > > case DPLL_CFGCR2_KDIV_5:
> > > > p2 = 5;
> > > > break;
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 88c215cf97d4..d911583526db 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -10261,6 +10261,7 @@ enum skl_power_gate {
> > > > #define DPLL_CFGCR2_PDIV_2 (1 << 2)
> > > > #define DPLL_CFGCR2_PDIV_3 (2 << 2)
> > > > #define DPLL_CFGCR2_PDIV_7 (4 << 2)
> > > > +#define DPLL_CFGCR2_PDIV_7_INVALID(5 << 2)
> > > > #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
> > > >
> > > > #define DPLL_CFGCR1(id)_MMIO_PIPE((id) - SKL_DPLL1,
> > > > _DPLL1_CFGCR1, _DPLL2_CFGCR1)
> > > > --
> > > > 2.25.1
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
___
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[Intel-gfx] [PATCH v3 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
The BIOS of at least one ASUS-Z170M system with an SKL I have programs
the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with
bit#0 incorrectly set.
This happens with the
"3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9
HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the
ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1
WRPLL parameters (assuming PDIV=7 was the intended setting). This
corresponds to 262749 PLL frequency/port clock.
Later the driver sets the same mode for which it calculates the same
dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding).
Based on the above, let's assume that PDIV=7 was intended and the HW
just ignores bit#0 in the PDIV register field for this setting, treating
100b and 101b encodings the same way.
While at it add the MISSING_CASE() for the p0,p2 divider decodings.
v2: (Ville)
- Add a define for the incorrect divider value.
- Emit only a debug message when detecting the incorrect divider value.
- Use fallthrough from the incorrect divider value case.
- Add the MISSING_CASE()s.
v3: Return 0 freq for incorrect divider values. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e08684e34078..fff4e154b391 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1602,9 +1602,19 @@ static int skl_ddi_wrpll_get_freq(struct
drm_i915_private *i915,
case DPLL_CFGCR2_PDIV_3:
p0 = 3;
break;
+ case DPLL_CFGCR2_PDIV_7_INVALID:
+ /*
+* Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore
bit#0,
+* handling it the same way as PDIV_7.
+*/
+ drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value,
fixing it.\n");
+ fallthrough;
case DPLL_CFGCR2_PDIV_7:
p0 = 7;
break;
+ default:
+ MISSING_CASE(p0);
+ return 0;
}
switch (p2) {
@@ -1620,6 +1630,9 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private
*i915,
case DPLL_CFGCR2_KDIV_1:
p2 = 1;
break;
+ default:
+ MISSING_CASE(p2);
+ return 0;
}
dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88c215cf97d4..d911583526db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10261,6 +10261,7 @@ enum skl_power_gate {
#define DPLL_CFGCR2_PDIV_2 (1 << 2)
#define DPLL_CFGCR2_PDIV_3 (2 << 2)
#define DPLL_CFGCR2_PDIV_7 (4 << 2)
+#define DPLL_CFGCR2_PDIV_7_INVALID(5 << 2)
#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
#define DPLL_CFGCR1(id)_MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1,
_DPLL2_CFGCR1)
--
2.25.1
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31 +./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31 +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
> -Original Message-
> From: Ville Syrjälä
> Sent: Tuesday, September 29, 2020 9:42 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA
> Lspcon
>
> On Tue, Sep 15, 2020 at 02:30:38AM +0530, Uma Shankar wrote:
> > Gen9 hardware supports HDMI2.0 through LSPCON chips.
> > Extending HDR support for MCA LSPCON based GEN9 devices.
> >
> > SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP
> > packets. LSPCON will be set to operate in PCON mode, will receive the
> > metadata and create Dynamic Range and Mastering Infoframe (DRM
> > packets) and send it to HDR capable HDMI sink devices.
> >
> > v2: Re-used hsw infoframe write implementation for HDR metadata for
> > LSPCON as per Ville's suggestion.
> >
> > v3: Addressed Jani Nikula's review comments.
> >
> > Signed-off-by: Uma Shankar
> > ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++
> > drivers/gpu/drm/i915/display/intel_lspcon.c | 37
> > +++-- drivers/gpu/drm/i915/display/intel_lspcon.h |
> > 5 ++-
> > 3 files changed, 40 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0978b0d8f4c6..1e40ed473fb9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct
> intel_encoder *encoder,
> > return val & mask;
> > }
> >
> > +void lspcon_drm_write_infoframe(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state,
> > + unsigned int type,
> > + const void *frame, ssize_t len)
> > +{
> > + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n");
> > + /* It uses the legacy hsw implementation for the same */
> > + hsw_write_infoframe(encoder, crtc_state, type, frame, len); }
>
> This wrapper seems quite pointless.
Hmm yeah, will drop this.
> > +
> > static const u8 infoframe_type_to_idx[] = {
> > HDMI_PACKET_TYPE_GENERAL_CONTROL,
> > HDMI_PACKET_TYPE_GAMUT_METADATA,
> > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 8e8c7a02ab51..5e2d7ca1d20f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder
> *encoder,
> > unsigned int type,
> > const void *frame, ssize_t len) {
> > - bool ret;
> > + bool ret = true;
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
> >
> > - /* LSPCON only needs AVI IF */
> > - if (type != HDMI_INFOFRAME_TYPE_AVI)
> > + /*
> > +* Supporting HDR on MCA LSPCON
> > +* Todo: Add support for Parade later
> > +*/
> > + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA &&
> > + lspcon->vendor != LSPCON_VENDOR_MCA)
> > return;
>
> We shouldn't have the infoframe flagged as enabled if we don't support it. So
> this check seems pointless, or there's a bug somewhere else.
Sure, will drop this check. It's not required.
> >
> > - if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> > - frame, len);
> > - else
> > - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
> > -frame, len);
> > + switch (type) {
> > + case HDMI_INFOFRAME_TYPE_AVI:
> > + if (lspcon->vendor == LSPCON_VENDOR_MCA)
> > + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
> > + frame, len);
> > + else
> > + ret = _lspcon_write_avi_infoframe_parade(&intel_dp-
> >aux,
> > +frame, len);
> > + break;
> > + case HDMI_PACKET_TYPE_GAMUT_METADATA:
> > + lspcon_drm_write_infoframe(encoder, crtc_state,
> > +
> HDMI_PACKET_TYPE_GAMUT_METADATA,
> > + frame, VIDEO_DIP_DATA_SIZE);
>
> Why are we hardocoding the parameters here? Just pass them through?
Ok, will rectify this.
> > + break;
> > + default:
> > + return;
> > + }
> >
> > if (!ret) {
> > - DRM_ERROR("Failed to write AVI infoframes\n");
> > + DRM_ERROR("Failed to write infoframes\n");
> > return;
> > }
> >
> > - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n");
> > + DRM_DEBUG_DRIVER("Infoframes updated successfully\n");
>
> That pointless debug should probably be just nuked.
Ok, will dro
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock (rev7)
URL : https://patchwork.freedesktop.org/series/82173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9100 -> Patchwork_18630
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html
Known issues
Here are the changes found in Patchwork_18630 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] /
[i915#95])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_busy@ba...@flip.html
Possible fixes
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-tgl-dsi/igt@kms_busy@ba...@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-bsw-n3050/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
- fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95])
-> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@vgem_ba...@unload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@vgem_ba...@unload.html
Warnings
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) ->
[DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_cursor_leg...@basic-flip-after-cursor-varying-size.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95])
-> [DMESG-WARN][14] ([i915#62] / [i915#92]) +5 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/fi-kbl-x1275/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (44 -> 38)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_9100 -> Patchwork_18630
CI-20190529: 20190529
CI_DRM_9100: 62e000a556587d80f5c23b863195a30c073c7741 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5800: 982ca4122fd4f04ad3dfa80c6246f190b36e0c72 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18630: c9218b4e5fb4b047c75911a798897ab663fe158f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c9218b4e5fb4 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz
ref clock
c2ee2fe22455 drm/i915: Add an encoder hook to sanitize its state during
init/resume
cf94f1fd7110 drm/i915: Check for unsupported DP link rates during initial commit
76cfbbbf6aa9 drm/i915: Move the initial fastset commit check to encoder hooks
479da4d9f49e drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/index.html
_
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6)
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev6) URL : https://patchwork.freedesktop.org/series/82173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9098_full -> Patchwork_18629_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_18629_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18629_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_18629_full: ### IGT changes ### Possible regressions * igt@gem_softpin@softpin: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-iclb6/igt@gem_soft...@softpin.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-iclb1/igt@gem_soft...@softpin.html Known issues Here are the changes found in Patchwork_18629_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-many-active@vecs0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk4/igt@gem_exec_reloc@basic-many-act...@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk6/igt@gem_exec_reloc@basic-many-act...@vecs0.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#128]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb3/igt@kms_cursor_leg...@all-pipes-torture-bo.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb7/igt@kms_cursor_leg...@all-pipes-torture-bo.html * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#79]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vbl...@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-kbl6/igt@kms_flip@flip-vs-susp...@c-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-kbl4/igt@kms_flip@flip-vs-susp...@c-dp1.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-tglb1/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-rgb101010-draw-render.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl10/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl1/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#198]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl9/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-skl1/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18629/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9098/shard-
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev7)
== Series Details ==
Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref
clock (rev7)
URL : https://patchwork.freedesktop.org/series/82173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9100_full -> Patchwork_18630_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_18630_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18630_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_18630_full:
### Piglit changes ###
Possible regressions
* spec@!opengl 1.3@gl-1.3-texture-env:
- pig-snb-2600: NOTRUN -> [INCOMPLETE][1] +7 similar issues
[1]: None
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][2] +7 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/pig-icl-1065g7/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2.html
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3
(NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][3] +1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/pig-icl-1065g7/spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3.html
New tests
-
New tests have been introduced between CI_DRM_9100_full and
Patchwork_18630_full:
### New Piglit tests (11) ###
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-double_dmat4x2-float_float_array3-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-float_mat2x3_array3-position-double_dvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-double_dvec4-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-int_ivec3_array3-position-double_dvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4-double_dmat4x2_array2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4-double_dvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-float_mat3:
- Statuses : 1 crash(s)
- Exec time: [0.75] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-double_dmat4x3-int_ivec2_array3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-position-float_vec3_array3-double_dmat4x2:
- Statuses : 1 crash(s)
- Exec time: [1.14] s
*
spec@arb_vertex_attrib_64bit@execution@vs_in@vs-input-ubyte_uvec2-short_ivec3-double_dmat3x2-position:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@nv_vertex_program2_option@vp-clipdistance-01:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18630_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +7 similar
issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-kbl6/igt@gem_ctx_isolation@preservation...@vecs0.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-kbl7/igt@gem_ctx_isolation@preservation...@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][6] -> [SKIP][7] ([i915#2190])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-tglb8/igt@gem_huc_c...@huc-copy.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-tglb6/igt@gem_huc_c...@huc-copy.html
* igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge:
- shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/shard-glk6/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18630/shard-glk4/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- shard-skl: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9100/sha
