[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Avoid uninitialized use of rpcurupei in frequency_show
== Series Details ==
Series: drm/i915/gt: Avoid uninitialized use of rpcurupei in frequency_show
URL : https://patchwork.freedesktop.org/series/76691/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8389_full -> Patchwork_17503_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17503_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar
issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +7 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#52] / [i915#54])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-glk8/igt@kms_draw_...@draw-method-rgb565-blt-xtiled.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-glk1/igt@kms_draw_...@draw-method-rgb565-blt-xtiled.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#49])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265])
+2 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl4/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-iclb7/igt@kms_psr@psr2_primary_blt.html
Possible fixes
* igt@gem_eio@kms:
- shard-glk: [TIMEOUT][13] ([i915#1383]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-glk6/igt@gem_...@kms.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-glk4/igt@gem_...@kms.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +9
similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-apl1/igt@gem_workarou...@suspend-resume-context.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-apl7/igt@gem_workarou...@suspend-resume-context.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-glk: [FAIL][17] ([i915#177] / [i915#52] / [i915#54]) ->
[PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-glk8/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-glk1/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
* {igt@kms_flip@flip-vs-suspend-interruptible@a-dp1}:
- shard-kbl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-kbl1/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-kbl2/igt@kms_flip@flip-vs-suspend-interrupti...@a-dp1.html
* {igt@kms_flip@plain-flip-ts-check@a-edp1}:
- shard-skl: [FAIL][21] ([i915#34]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl10/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-skl1/igt@kms_flip@plain-flip-ts-ch...@a-edp1.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-kbl: [FAIL][23] ([i915#699] / [i915#93] / [i915#95]) ->
[PASS][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-kbl6/igt@kms_flip_til...@flip-changes-tiling-y.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17503/shard-kbl7/igt@kms_flip
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
Hi Stephen,
On 4/29/20 12:33 AM, Stephen Rothwell wrote:
> Hi all,
>
> On Mon, 20 Apr 2020 13:01:18 +1000 Stephen Rothwell
> wrote:
>>
>> After merging the drm-misc tree, today's linux-next build (powerpc
>> allyesconfig) failed like this:
>>
>> drivers/video/fbdev/controlfb.c: In function 'controlfb_mmap':
>> drivers/video/fbdev/controlfb.c:756:23: error: implicit declaration of
>> function 'pgprot_cached_wthru'; did you mean 'pgprot_cached'?
>> [-Werror=implicit-function-declaration]
>> 756 | vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
>> | ^~~
>> | pgprot_cached
>> drivers/video/fbdev/controlfb.c:756:23: error: incompatible types when
>> assigning to type 'pgprot_t' {aka 'struct '} from type 'int'
>>
>> Presumably exposed by commit
>>
>> a07a63b0e24d ("video: fbdev: controlfb: add COMPILE_TEST support")
>>
>> I just turned off COMPILE_TEST again for today. Please let me know when
>> this is fixed.
>
> This still appears to have not been addressed.
Sorry for the delay, I've just posted a patch (also included below):
"[PATCH] video: fbdev: controlfb: fix build for COMPILE_TEST=y && PPC_PMAC=y &&
PPC32=n"
which should fix it.
Please verify it, thank you!
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
From: Bartlomiej Zolnierkiewicz
Subject: [PATCH] video: fbdev: controlfb: fix build for COMPILE_TEST=y &&
PPC_PMAC=y && PPC32=n
powerpc allyesconfig fails like this:
drivers/video/fbdev/controlfb.c: In function 'controlfb_mmap':
drivers/video/fbdev/controlfb.c:756:23: error: implicit declaration of function
'pgprot_cached_wthru'; did you mean 'pgprot_cached'?
[-Werror=implicit-function-declaration]
756 | vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
| ^~~
| pgprot_cached
drivers/video/fbdev/controlfb.c:756:23: error: incompatible types when
assigning to type 'pgprot_t' {aka 'struct '} from type 'int'
Fix it by adding missing PPC32 dependency.
Fixes: a07a63b0e24d ("video: fbdev: controlfb: add COMPILE_TEST support")
Reported-by: Stephen Rothwell
Reported-by: kbuild test robot
Cc: Sam Ravnborg
Cc: Daniel Vetter
Signed-off-by: Bartlomiej Zolnierkiewicz
---
drivers/video/fbdev/controlfb.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: b/drivers/video/fbdev/controlfb.c
===
--- a/drivers/video/fbdev/controlfb.c
+++ b/drivers/video/fbdev/controlfb.c
@@ -47,7 +47,7 @@
#include
#include
#include
-#ifdef CONFIG_PPC_PMAC
+#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
#include
#include
#endif
@@ -55,7 +55,7 @@
#include "macmodes.h"
#include "controlfb.h"
-#ifndef CONFIG_PPC_PMAC
+#if !defined(CONFIG_PPC_PMAC) || !defined(CONFIG_PPC32)
#define invalid_vram_cache(addr)
#undef in_8
#undef out_8
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Re: [Intel-gfx] [patch] drm/i915: Update Slylake PCI IDs
On Wed, 29 Apr 2020, Ville Syrjälä wrote: > On Tue, Apr 28, 2020 at 11:27:50PM -0400, Alexei Podtelezhnikov wrote: >> Add three new devices 0x1513, 0x1515, and 0x1517 also known as > > typo 0x15 vs. 0x19 > >> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927, >> and 0x192A according to specifications. > > I'd make this three separate patches, just in case we have to revert > some of these in the future. Most worried about the 0x192a case since > the evidence is rather poor. +1 > > Otherwise lgtm. > >> >> Signed-off-by: Alexei Podtelezhnikov >> --- >> include/drm/i915_pciids.h | 19 +++ >> 1 file changed, 11 insertions(+), 8 deletions(-) >> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h >> index 1d2c1221..c12bce9e 100644 >> --- a/include/drm/i915_pciids.h >> +++ b/include/drm/i915_pciids.h >> @@ -331,15 +331,18 @@ >> INTEL_VGA_DEVICE(0x22b3, info) >> >> #define INTEL_SKL_ULT_GT1_IDS(info) \ >> -INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */ >> +INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ >> +INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */ >> >> #define INTEL_SKL_ULX_GT1_IDS(info) \ >> -INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */ >> +INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ >> +INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */ >> >> #define INTEL_SKL_GT1_IDS(info) \ >> INTEL_SKL_ULT_GT1_IDS(info), \ >> INTEL_SKL_ULX_GT1_IDS(info), \ >> INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ >> +INTEL_VGA_DEVICE(0x1917, info), /* DT GT1.5 */ \ >> INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ >> INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ >> >> @@ -359,21 +362,21 @@ >> INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ >> >> #define INTEL_SKL_ULT_GT3_IDS(info) \ >> -INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */ >> +INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ >> +INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 28W */ \ >> +INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3e */ >> >> #define INTEL_SKL_GT3_IDS(info) \ >> INTEL_SKL_ULT_GT3_IDS(info), \ >> -INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ >> -INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ >> +INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ >> INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ >> -INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ >> +INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */ >> >> #define INTEL_SKL_GT4_IDS(info) \ >> INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ >> INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ >> INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ >> -INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ >> -INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ >> +INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */ >> >> #define INTEL_SKL_IDS(info) \ >> INTEL_SKL_GT1_IDS(info), \ >> -- >> 2.26.2 -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Replace drm_modeset_lock/unlock_all with DRM_MODESET_LOCK_ALL_* helpers
On Tue, 28 Apr 2020, Michal Orzel wrote:
> As suggested by the TODO list for the kernel DRM subsystem, replace
> the deprecated functions that take/drop modeset locks with new helpers.
>
> Signed-off-by: Michal Orzel
> ---
> drivers/gpu/drm/drm_mode_object.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_mode_object.c
> b/drivers/gpu/drm/drm_mode_object.c
> index 35c2719..901b078 100644
> --- a/drivers/gpu/drm/drm_mode_object.c
> +++ b/drivers/gpu/drm/drm_mode_object.c
> @@ -402,12 +402,13 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device
> *dev, void *data,
> {
> struct drm_mode_obj_get_properties *arg = data;
> struct drm_mode_object *obj;
> + struct drm_modeset_acquire_ctx ctx;
> int ret = 0;
>
> if (!drm_core_check_feature(dev, DRIVER_MODESET))
> return -EOPNOTSUPP;
>
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
I cry a little every time I look at the DRM_MODESET_LOCK_ALL_BEGIN and
DRM_MODESET_LOCK_ALL_END macros. :(
Currently only six users... but there are ~60 calls to
drm_modeset_lock_all{,_ctx} that I presume are to be replaced. I wonder
if this will come back and haunt us.
BR,
Jani.
>
> obj = drm_mode_object_find(dev, file_priv, arg->obj_id, arg->obj_type);
> if (!obj) {
> @@ -427,7 +428,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device
> *dev, void *data,
> out_unref:
> drm_mode_object_put(obj);
> out:
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(ctx, ret);
> return ret;
> }
>
> @@ -449,12 +450,13 @@ static int set_property_legacy(struct drm_mode_object
> *obj,
> {
> struct drm_device *dev = prop->dev;
> struct drm_mode_object *ref;
> + struct drm_modeset_acquire_ctx ctx;
> int ret = -EINVAL;
>
> if (!drm_property_change_valid_get(prop, prop_value, &ref))
> return -EINVAL;
>
> - drm_modeset_lock_all(dev);
> + DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret);
> switch (obj->type) {
> case DRM_MODE_OBJECT_CONNECTOR:
> ret = drm_connector_set_obj_prop(obj, prop, prop_value);
> @@ -468,7 +470,7 @@ static int set_property_legacy(struct drm_mode_object
> *obj,
> break;
> }
> drm_property_change_valid_put(prop, ref);
> - drm_modeset_unlock_all(dev);
> + DRM_MODESET_LOCK_ALL_END(ctx, ret);
>
> return ret;
> }
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH v9 2/4] drm/i915/perf: stop using the kernel context
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 153 +
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files changed, 113 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 6d8a1e624bc3..f71f45b68265 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1356,9 +1356,31 @@ free_noa_wait(struct i915_perf_stream *stream)
i915_vma_unpin_and_release(&stream->noa_wait, 0);
}
+static int i915_perf_stream_sync(struct i915_perf_stream *stream,
+bool enable)
+{
+ struct i915_active *active;
+ int err = 0;
+
+ active = i915_active_create();
+ if (!active)
+ return -ENOMEM;
+
+ if (enable)
+ err = stream->perf->ops.enable_metric_set(stream, active);
+ else
+ stream->perf->ops.disable_metric_set(stream, active);
+ if (err == 0)
+ __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
+
+ i915_active_put(active);
+ return err;
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
+ int err;
BUG_ON(stream != perf->exclusive_stream);
@@ -1369,7 +1391,14 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
* See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
WRITE_ONCE(perf->exclusive_stream, NULL);
- perf->ops.disable_metric_set(stream);
+ err = i915_perf_stream_sync(stream, false /* enable */);
+ if (err) {
+ drm_err(&perf->i915->drm,
+ "Error while disabling OA stream\n");
+ }
+
+ intel_context_unpin(stream->config_context);
+ intel_context_put(stream->config_context);
free_oa_buffer(stream);
@@ -2013,11 +2042,6 @@ emit_oa_config(struct i915_perf_stream *stream,
return err;
}
-static struct intel_context *oa_context(struct i915_perf_stream *stream)
-{
- return stream->pinned_ctx ?: stream->engine->kernel_context;
-}
-
static int
hsw_enable_metric_set(struct i915_perf_stream *stream,
struct i915_active *active)
@@ -2040,13 +2064,14 @@ hsw_enable_metric_set(struct i915_perf_stream *stream,
0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
return emit_oa_config(stream, stream->oa_config,
- oa_context(stream),
+ stream->config_context,
active,
BIT(I915_OA_CONFIG_PART_GLOBAL) |
BIT(I915_OA_CONFIG_PART_PER_CONTEXT));
}
-static void hsw_disable_metric_set(struct i915_perf_stream *stream)
+static void hsw_disable_metric_set(struct i915_perf_stream *stream,
+ struct i915_active *active)
{
struct intel_uncore *uncore = stream->uncore;
@@ -2171,13 +2196,14 @@ gen8_load_flex(struct i915_request *rq,
return 0;
}
-static int gen8_modify_context(struct intel_context *ce,
+static int gen8_modify_context(struct i915_perf_stream *stream,
+ struct intel_context *ce,
const struct flex *flex, unsigned int count)
{
struct i915_request *rq;
int err;
- rq = intel_engine_create_kernel_request(ce->engine);
+ rq = intel_context_create_request(stream->config_context);
if (IS_ERR(rq))
return PTR_ERR(rq);
@@ -2219,7 +2245,8 @@ gen8_modify_self(struct intel_context *ce,
return err;
}
-static int gen8_configure_context(struct i915_gem_context *ctx,
+static int gen8_configure_context(struct i915_perf_stream *stream,
+ struct i915_gem_context *ctx,
struct flex *flex, unsigned int count)
{
struct i915_gem_engines_iter it;
@@ -2237,7 +2264,7 @@ static int gen8_configure_context(struct i915_gem_context
*ctx,
continue;
flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
- err = gen8_modify_context(ce, flex, count);
+ err = gen8_modify_context(stream, ce, flex, count);
intel_context_unpin(ce);
if (err)
@@ -2287,7 +2314,7 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream,
if (err)
return err;
- err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
+ err = gen8_modify_context(stream, ce, regs_context,
ARRAY_SIZE(regs_context));
intel_context_unlock_pinned(ce);
if (err)
return err;
@@ -2330,6 +2357,7 @@ oa_configure_all_c
[Intel-gfx] [PATCH v9 1/4] drm/i915/perf: break OA config buffer object in 2
We want to enable performance monitoring on multiple contexts to cover
the Iris use case of using 2 GEM contexts (3D & compute).
So start by breaking the OA configuration BO which contains global &
per context register writes.
NOA muxes & OA configurations are global, while FLEXEU register
configurations are per context.
v2: Use an offset into the same VMA (Chris)
v3: Use a bitfield to select config parts to emit (Umesh)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 177 ---
1 file changed, 114 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index dec1b33e4da8..6d8a1e624bc3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -367,11 +367,18 @@ struct perf_open_properties {
u64 poll_oa_period;
};
+enum i915_oa_config_part {
+ I915_OA_CONFIG_PART_PER_CONTEXT,
+ I915_OA_CONFIG_PART_GLOBAL,
+ I915_OA_CONFIG_PART_MAX,
+};
+
struct i915_oa_config_bo {
struct llist_node node;
struct i915_oa_config *oa_config;
struct i915_vma *vma;
+ u32 per_context_offset;
};
static struct ctl_table_header *sysctl_header;
@@ -1826,37 +1833,43 @@ static struct i915_oa_config_bo *
alloc_oa_config_buffer(struct i915_perf_stream *stream,
struct i915_oa_config *oa_config)
{
- struct drm_i915_gem_object *obj;
struct i915_oa_config_bo *oa_bo;
+ struct drm_i915_gem_object *obj;
size_t config_length = 0;
- u32 *cs;
+ u32 *cs_start, *cs;
int err;
oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
if (!oa_bo)
return ERR_PTR(-ENOMEM);
+ /*
+* Global configuration requires a jump into the NOA wait BO for it to
+* apply.
+*/
config_length += num_lri_dwords(oa_config->mux_regs_len);
config_length += num_lri_dwords(oa_config->b_counter_regs_len);
- config_length += num_lri_dwords(oa_config->flex_regs_len);
config_length += 3; /* MI_BATCH_BUFFER_START */
+
+ config_length += num_lri_dwords(oa_config->flex_regs_len);
+ config_length += 1 /* MI_BATCH_BUFFER_END */;
+
config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
- obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
+ obj = i915_gem_object_create_shmem(stream->perf->i915,
+ config_length);
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
goto err_free;
}
- cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
- if (IS_ERR(cs)) {
- err = PTR_ERR(cs);
- goto err_oa_bo;
+ cs_start = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cs_start)) {
+ err = PTR_ERR(cs_start);
+ goto err_bo;
}
- cs = write_cs_mi_lri(cs,
-oa_config->mux_regs,
-oa_config->mux_regs_len);
+ cs = cs_start;
cs = write_cs_mi_lri(cs,
oa_config->b_counter_regs,
oa_config->b_counter_regs_len);
@@ -1871,6 +1884,14 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
*cs++ = i915_ggtt_offset(stream->noa_wait);
*cs++ = 0;
+ oa_bo->per_context_offset = 4 * (cs - cs_start);
+
+ cs = write_cs_mi_lri(cs,
+oa_config->mux_regs,
+oa_config->mux_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
i915_gem_object_flush_map(obj);
i915_gem_object_unpin_map(obj);
@@ -1879,7 +1900,7 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
NULL);
if (IS_ERR(oa_bo->vma)) {
err = PTR_ERR(oa_bo->vma);
- goto err_oa_bo;
+ goto err_bo;
}
oa_bo->oa_config = i915_oa_config_get(oa_config);
@@ -1887,15 +1908,15 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
return oa_bo;
-err_oa_bo:
+err_bo:
i915_gem_object_put(obj);
err_free:
kfree(oa_bo);
return ERR_PTR(err);
}
-static struct i915_vma *
-get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
+static struct i915_oa_config_bo *
+get_oa_bo(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
{
struct i915_oa_config_bo *oa_bo;
@@ -1908,34 +1929,31 @@ get_oa_vma(struct i915_perf_stream *stream, struct
i915_oa_config *oa_config)
memcmp(oa_bo->oa_config->uuid,
oa_config->uuid,
sizeof(oa_config->uuid)) == 0)
- goto out;
+ return oa_bo;
}
- oa_bo = alloc_oa_config_buffer(stream, oa_config);
- if (IS_ERR(
[Intel-gfx] [PATCH v9 0/4] drm/i915/perf: Add support for multi context perf queries
Hi all, Just a small change on the key passed to bsearch(). Cheers, Lionel Landwerlin (4): drm/i915/perf: break OA config buffer object in 2 drm/i915/perf: stop using the kernel context drm/i915/perf: prepare driver to receive multiple ctx handles drm/i915/perf: enable filtering on multiple contexts drivers/gpu/drm/i915/i915_perf.c | 930 - drivers/gpu/drm/i915/i915_perf_types.h | 47 +- include/uapi/drm/i915_drm.h| 21 + 3 files changed, 661 insertions(+), 337 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 3/4] drm/i915/perf: prepare driver to receive multiple ctx handles
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
v4: Let the intel_context create its own timeline (Chris)
Only pin configuration context when needed (Chris)
v5: Pass filtering context ID by argument (Chris)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 594 +++--
drivers/gpu/drm/i915/i915_perf_types.h | 37 +-
2 files changed, 384 insertions(+), 247 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f71f45b68265..eb9aa3e3f804 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -192,6 +192,7 @@
*/
#include
+#include
#include
#include
@@ -329,7 +330,8 @@ static const struct i915_oa_format
gen12_oa_formats[I915_OA_FORMAT_MAX] = {
* @single_context: Whether a single or all gpu contexts should be monitored
* @hold_preemption: Whether the preemption is disabled for the filtered
* context
- * @ctx_handle: A gem ctx handle for use with @single_context
+ * @n_ctx_handles: Length of @ctx_handles
+ * @ctx_handles: An array of gem context handles
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
@@ -349,9 +351,10 @@ static const struct i915_oa_format
gen12_oa_formats[I915_OA_FORMAT_MAX] = {
struct perf_open_properties {
u32 sample_flags;
- u64 single_context:1;
u64 hold_preemption:1;
- u64 ctx_handle;
+
+ u32 n_ctx_handles;
+ u32 *ctx_handles;
/* OA sampling state */
int metrics_set;
@@ -631,6 +634,23 @@ static int append_oa_sample(struct i915_perf_stream
*stream,
return 0;
}
+static int ctx_id_equal(const void *key, const void *elem)
+{
+ const struct i915_perf_context_detail *details = elem;
+
+ return ((int)details->id) - (uintptr_t)key;
+}
+
+static inline bool ctx_id_match(struct i915_perf_stream *stream,
+ u32 masked_ctx_id)
+{
+ return bsearch((void *)(uintptr_t)masked_ctx_id,
+ stream->pinned_ctxs,
+ stream->n_pinned_ctxs,
+ sizeof(*stream->pinned_ctxs),
+ ctx_id_equal) != NULL;
+}
+
/**
* Copies all buffered OA reports into userspace read() buffer.
* @stream: An i915-perf stream opened for OA metrics
@@ -742,7 +762,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
continue;
}
- ctx_id = report32[2] & stream->specific_ctx_id_mask;
+ ctx_id = report32[2] & stream->ctx_id_mask;
/*
* Squash whatever is in the CTX_ID field if it's marked as
@@ -787,26 +807,32 @@ static int gen8_append_oa_reports(struct i915_perf_stream
*stream,
* switches since it's not-uncommon for periodic samples to
* identify a switch before any 'context switch' report.
*/
- if (!stream->perf->exclusive_stream->ctx ||
- stream->specific_ctx_id == ctx_id ||
- stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
- reason & OAREPORT_REASON_CTX_SWITCH) {
-
- /*
-* While filtering for a single context we avoid
-* leaking the IDs of other contexts.
-*/
- if (stream->perf->exclusive_stream->ctx &&
- stream->specific_ctx_id != ctx_id) {
- report32[2] = INVALID_CTX_ID;
- }
-
+ if (!stream->perf->exclusive_stream->n_ctxs) {
ret = append_oa_sample(stream, buf, count, offset,
report);
if (ret)
break;
+ } else {
+ bool ctx_match = ctx_id != INVALID_CTX_ID &&
+ ctx_id_match(stream, ctx_id);
+
+ if (ctx_match ||
+ stream->oa_buffer.last_ctx_match ||
+ reason & OAREPORT_REASON_CTX_SWITCH) {
+ /*
+* While filtering for a single context we avoid
+* leaking the IDs of other contexts.
+*/
+ if (!ctx_match)
+ report32[2] = INVALID_CTX_ID;
+
+ ret = append_oa_sample(stream, buf, count,
offset,
+ report);
+
[Intel-gfx] [PATCH v9 4/4] drm/i915/perf: enable filtering on multiple contexts
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 58 ++--
include/uapi/drm/i915_drm.h | 21
2 files changed, 76 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index eb9aa3e3f804..c1dcb7a4b7aa 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3711,7 +3711,8 @@ static int read_properties_unlocked(struct i915_perf
*perf,
struct perf_open_properties *props)
{
u64 __user *uprop = uprops;
- u32 i;
+ u32 __user *uctx_handles = NULL;
+ u32 i, n_uctx_handles = 0;
int err;
memset(props, 0, sizeof(struct perf_open_properties));
@@ -3762,7 +3763,7 @@ static int read_properties_unlocked(struct i915_perf
*perf,
switch ((enum drm_i915_perf_property_id)id) {
case DRM_I915_PERF_PROP_CTX_HANDLE:
- if (props->n_ctx_handles > 0) {
+ if (props->n_ctx_handles > 0 || n_uctx_handles > 0) {
DRM_DEBUG("Context handle specified multiple
times\n");
err = -EINVAL;
goto error;
@@ -3876,6 +3877,38 @@ static int read_properties_unlocked(struct i915_perf
*perf,
}
props->poll_oa_period = value;
break;
+ case DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY:
+ /* HSW can only filter in HW and only on a single
+* context.
+*/
+ if (IS_HASWELL(perf->i915)) {
+ DRM_DEBUG("Multi context filter not supported
on HSW\n");
+ err = -ENODEV;
+ goto error;
+ }
+ uctx_handles = u64_to_user_ptr(value);
+ break;
+ case DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY_LENGTH:
+ if (IS_HASWELL(perf->i915)) {
+ DRM_DEBUG("Multi context filter not supported
on HSW\n");
+ err = -ENODEV;
+ goto error;
+ }
+ if (props->n_ctx_handles > 0 || n_uctx_handles > 0) {
+ DRM_DEBUG("Context handle specified multiple
times\n");
+ err = -EINVAL;
+ goto error;
+ }
+ props->ctx_handles =
+ kmalloc_array(value,
+ sizeof(*props->ctx_handles),
+ GFP_KERNEL);
+ if (!props->ctx_handles) {
+ err = -ENOMEM;
+ goto error;
+ }
+ n_uctx_handles = value;
+ break;
case DRM_I915_PERF_PROP_MAX:
MISSING_CASE(id);
err = -EINVAL;
@@ -3885,6 +3918,21 @@ static int read_properties_unlocked(struct i915_perf
*perf,
uprop += 2;
}
+ if (n_uctx_handles > 0 && props->n_ctx_handles > 0) {
+ DRM_DEBUG("Context handle specified multiple times\n");
+ err = -EINVAL;
+ goto error;
+ }
+
+ for (i = 0; i < n_uctx_handles; i++) {
+ err = get_user(props->ctx_handles[i], uctx_handles);
+ if (err)
+ goto error;
+
+ uctx_handles++;
+ props->n_ctx_handles++;
+ }
+
return 0;
error:
@@ -4668,8 +4716,12 @@ int i915_perf_ioctl_version(void)
*
* 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
*interval for the hrtimer used to check for OA data.
+*
+* 6: Add DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY &
+*DRM_I915_PERF_PROP_CTX_HANDLE_ARRAY_LENGTH to allow an
+*application monitor/pin multiple contexts.
*/
- return 5;
+ return 6;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 14b67cd6b54b..f80e7932d728 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1993,6 +1993,27 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_POLL_OA_PERIOD,
+ /**
+* Specifies an array of u32 GEM context handles to filter reports
+* with.
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add PCI IDs for Skylake GT1.5 (rev2)
== Series Details == Series: drm/i915: Add PCI IDs for Skylake GT1.5 (rev2) URL : https://patchwork.freedesktop.org/series/76577/ State : success == Summary == CI Bug Log - changes from CI_DRM_8389_full -> Patchwork_17504_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_17504_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@suspend: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1185]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-iclb1/igt@gem_...@suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-iclb3/igt@gem_...@suspend.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#454]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-iclb7/igt@i915_pm...@dc6-psr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([i915#189]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-iclb1/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-iclb7/igt@i915_pm_...@i2c.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#49]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-apl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-apl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-skl2/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-skl7/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_primary_blt: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-iclb2/igt@kms_psr@psr2_primary_blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-iclb6/igt@kms_psr@psr2_primary_blt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +9 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-kbl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-kbl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gem_eio@kms: - shard-glk: [TIMEOUT][19] ([i915#1383]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-glk6/igt@gem_...@kms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-glk5/igt@gem_...@kms.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +10 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-apl1/igt@gem_workarou...@suspend-resume-context.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: - shard-glk: [FAIL][23] ([i915#177] / [i915#52] / [i915#54]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8389/shard-glk8/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17504/shard-glk7/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][25] ([i9
[Intel-gfx] [PATCH 09/12] drm/i915/fbc: Store the fbc1 compression interval in the params
From: Ville Syrjälä
Avoid the FBC_CONTROL rmw and just store the fbc compression
interval in the params/
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index dbef58af4b94..b1eb6a2ecc43 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -132,8 +132,7 @@ static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv)
}
/* enable it... */
- fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
- fbc_ctl &= FBC_CTL_INTERVAL(0x3fff);
+ fbc_ctl = FBC_CTL_INTERVAL(params->interval);
fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
if (IS_I945GM(dev_priv))
fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
@@ -728,6 +727,9 @@ static void intel_fbc_update_state_cache(struct intel_crtc
*crtc,
cache->fb.modifier = fb->modifier;
cache->fb.stride = plane_state->color_plane[0].stride;
+ /* This value was pulled out of someone's hat */
+ cache->interval = 500;
+
cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
@@ -902,6 +904,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc
*crtc,
params->fence_id = cache->fence_id;
params->fence_y_offset = cache->fence_y_offset;
+ params->interval = cache->interval;
+
params->crtc.pipe = crtc->pipe;
params->crtc.i9xx_plane =
to_intel_plane(crtc->base.primary)->i9xx_plane;
@@ -1449,11 +1453,6 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
return;
}
- /* This value was pulled out of someone's hat */
- if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
- intel_de_write(dev_priv, FBC_CONTROL,
- FBC_CTL_INTERVAL(500));
-
/* We still don't have any sort of hardware state readout for FBC, so
* deactivate it in case the BIOS activated it to make sure software
* matches the hardware state. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a634fd2330c3..bc66a7cb886b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -419,6 +419,7 @@ struct intel_fbc {
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
+ u16 interval;
s8 fence_id;
} state_cache;
@@ -443,6 +444,7 @@ struct intel_fbc {
int cfb_size;
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
+ u16 interval;
s8 fence_id;
bool plane_visible;
} params;
--
2.24.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] drm/i915/fbc: Parametrize FBC_CONTROL
From: Ville Syrjälä Parametrize the FBC_CONTROL bits for neater code. Also add the one missing bit: "stop compression on modification". Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 8 drivers/gpu/drm/i915/i915_reg.h | 18 +++--- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 56eeafa645de..dbef58af4b94 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -133,13 +133,13 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) /* enable it... */ fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); - fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; + fbc_ctl &= FBC_CTL_INTERVAL(0x3fff); fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; if (IS_I945GM(dev_priv)) fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ - fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; + fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff); if (params->fence_id >= 0) - fbc_ctl |= params->fence_id; + fbc_ctl |= FBC_CTL_FENCENO(params->fence_id); intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); } @@ -1452,7 +1452,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) /* This value was pulled out of someone's hat */ if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) intel_de_write(dev_priv, FBC_CONTROL, - 500 << FBC_CTL_INTERVAL_SHIFT); + FBC_CTL_INTERVAL(500)); /* We still don't have any sort of hardware state readout for FBC, so * deactivate it in case the BIOS activated it to make sure software diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 088215025661..e9fb64e8f28f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3194,13 +3194,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ #define FBC_LL_BASE_MMIO(0x3204) /* 4k page aligned */ #define FBC_CONTROL_MMIO(0x3208) -#define FBC_CTL_EN (1 << 31) -#define FBC_CTL_PERIODIC (1 << 30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1 << 14) -#define FBC_CTL_C3_IDLE (1 << 13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO_SHIFT(0) +#define FBC_CTL_EN REG_BIT(31) +#define FBC_CTL_PERIODIC REG_BIT(30) +#define FBC_CTL_INTERVAL_MASKREG_GENMASK(29, 16) +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) +#define FBC_CTL_STRIDE(x)REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) #define FBC_COMMAND_MMIO(0x320c) #define FBC_CMD_COMPRESS (1 << 0) #define FBC_STATUS _MMIO(0x3210) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/12] drm/i915/fbc: Don't clear busy_bits for origin==GTT
From: Ville Syrjälä The hardware host tracking won't nuke the entire cfb (unless the entire fb is written through the gtt) so don't clear the busy_bits for gtt tracking. Not that it really matters anymore since we've lost ORIGIN_GTT usage everywhere. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 983224e07eaf..56eeafa645de 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1107,11 +1107,19 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, if (!HAS_FBC(dev_priv)) return; + /* +* GTT tracking does not nuke the entire cfb +* so don't clear busy_bits set for some other +* reason. +*/ + if (origin == ORIGIN_GTT) + return; + mutex_lock(&fbc->lock); fbc->busy_bits &= ~frontbuffer_bits; - if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) + if (origin == ORIGIN_FLIP) goto out; if (!fbc->busy_bits && fbc->crtc && -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/12] drm/i915/fbc: Fix fence_y_offset handling
From: Ville Syrjälä
The current fence_y_offset calculation is broken. I think it more or
less used to do the right thing, but then I changed the plane code
to put the final x/y source offsets back into the src rectangle so
now it's just subtraacting the same value from itself. The code would
never have worked if we allowed the framebuffer to have a non-zero
offset.
Let's do this in a better way by just calculating the fence_y_offset
from the final plane surface offset. Note that we don't align the
plane surface address to fence rows so with horizontal panning there's
often a horizontal offset from the fence start to the surface address
as well. We have no way to tell the hardware about that so we just
ignore it. Based on some quick tests the invlidation still happens
correctly. I presume due to the invalidation nuking at least the full
line (or a segment of multiple lines).
Fixes: 54d4d719fa11 ("drm/i915: Overcome display engine stride limits via GTT
remapping")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++
drivers/gpu/drm/i915/display/intel_display.h | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 32 ++--
drivers/gpu/drm/i915/i915_drv.h | 6 ++--
4 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6bb87965801e..e5fa49337883 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3822,6 +3822,17 @@ skl_check_main_ccs_coordinates(struct intel_plane_state
*plane_state,
return true;
}
+unsigned int
+intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
+{
+ int x = 0, y = 0;
+
+ intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
+ plane_state->color_plane[0].offset,
0);
+
+ return y;
+}
+
static int skl_check_main_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->uapi.plane->dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index efb4da205ea2..3a06f72c9859 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -608,6 +608,7 @@ unsigned int i9xx_plane_max_stride(struct intel_plane
*plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
+unsigned int intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state);
struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 192c5ff142ee..613ab499d42e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -47,19 +47,6 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
-/*
- * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
- * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
- * origin so the x and y offsets can actually fit the registers. As a
- * consequence, the fence doesn't really start exactly at the display plane
- * address we program because it starts at the real start of the buffer, so we
- * have to take this into consideration here.
- */
-static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
-{
- return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
-}
-
/*
* For SKL+, the plane source size used by the hardware is based on the value
we
* write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
@@ -141,7 +128,7 @@ static void i8xx_fbc_activate(struct drm_i915_private
*dev_priv)
fbc_ctl2 |= FBC_CTL_CPU_FENCE;
intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
intel_de_write(dev_priv, FBC_FENCE_OFF,
- params->crtc.fence_y_offset);
+ params->fence_y_offset);
}
/* enable it... */
@@ -175,7 +162,7 @@ static void g4x_fbc_activate(struct drm_i915_private
*dev_priv)
if (params->fence_id >= 0) {
dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
intel_de_write(dev_priv, DPFC_FENCE_YOFF,
- params->crtc.fence_y_offset);
+ params->fence_y_offset);
} else {
intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
}
@@ -243,7 +230,7 @@ static void ilk_fbc_activate(struct drm_i915_private
*dev_priv)
intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | params->fe
[Intel-gfx] [PATCH 04/12] drm/i915/fbc: Fix nuke for pre-snb platforms
From: Ville Syrjälä
The MSG_FBC_REND_STATE register only exists on snb+. For older
platforms (would also work for snb+) we can simply rewite DSPSURF
to trigger a flip nuke.
While generally RMW is considered harmful we'll use it here for
simplicity. And since FBC doesn't exist in i830 we don't have to
worry about the DSPSURF double buffering hardware fails present
on that platform.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 34 +++-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 613ab499d42e..983224e07eaf 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -188,8 +188,30 @@ static bool g4x_fbc_is_active(struct drm_i915_private
*dev_priv)
return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
}
+static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+ spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
+static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+ struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
+
+ spin_lock_irq(&dev_priv->uncore.lock);
+ intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
+ spin_unlock_irq(&dev_priv->uncore.lock);
+}
+
/* This function forces a CFB recompression through the nuke operation. */
-static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
+static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
@@ -199,6 +221,16 @@ static void intel_fbc_recompress(struct drm_i915_private
*dev_priv)
intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
}
+static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) >= 6)
+ snb_fbc_recompress(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 4)
+ i965_fbc_recompress(dev_priv);
+ else
+ i8xx_fbc_recompress(dev_priv);
+}
+
static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
{
struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
--
2.24.1
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[Intel-gfx] [PATCH 12/12] drm/i915: Suppress spurious underruns on gen2
From: Ville Syrjälä Often we seem to detect an underrun right after modeset on gen2. It seems to be a spurious detection (potentially the pipe is still in a wonky state when we enable the planes). An extra vblank wait seems to cure it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a0d1057d75ee..f330054e64c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7517,6 +7517,10 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, intel_crtc_vblank_on(new_crtc_state); intel_encoders_enable(state, crtc); + + /* prevents spurious underruns */ + if (IS_GEN(dev_priv, 2)) + intel_wait_for_vblank(dev_priv, pipe); } static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/12] drm/i915/fbc: Use the correct plane stride
From: Ville Syrjälä
Consult the actual plane stride instead of the fb stride. The two
will disagree when we remap the gtt. The plane stride is what the
hw will be fed so that's what we should look at for the FBC
retrictions/cfb allocation.
Since we no longer require a fence we are going to attempt using
FBC with remapping, and so we should look at correct stride.
Cc: José Roberto de Souza
Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for
GEN9+")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7194f9bc62c5..192c5ff142ee 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -707,8 +707,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc
*crtc,
cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
cache->fb.format = fb->format;
- cache->fb.stride = fb->pitches[0];
cache->fb.modifier = fb->modifier;
+ cache->fb.stride = plane_state->color_plane[0].stride;
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
!plane_state->vma->fence);
--
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[Intel-gfx] [PATCH 10/12] drm/i915/fbc: Reduce fbc1 compression interval to 1 second
From: Ville Syrjälä The default fbc1 compression interval we use is 500 frames. That translates to over 8 seconds typically. That's rather excessive so let's drop it to 1 second. The hardware will not attempt recompression unless at least one line has been modified, so a shorter compression interval should not cause extra bandwidth use in the purely idle scenario. Of course in the mostly idle case we are possibly going to recompress a bit more. Should really try to find some kind of sweet spot to minimize the energy usage... Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index b1eb6a2ecc43..6ee45d634cf6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -727,8 +727,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fb.modifier = fb->modifier; cache->fb.stride = plane_state->color_plane[0].stride; - /* This value was pulled out of someone's hat */ - cache->interval = 500; + /* FBC1 compression interval: arbitrary choice of 1 second */ + cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/12] drm/i915: Fix g4x fbc watermark enable
From: Ville Syrjälä
'level' here means the highest level we can't use, so when checking
the fbc watermarks we need a -1 to get at the last enabled level.
While at if refactor the code a bit to declutter
g4x_compute_pipe_wm().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1e99b35f007e..1c92ebf64a34 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1344,6 +1344,23 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
}
}
+static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
+ int level)
+{
+ if (level < G4X_WM_LEVEL_SR)
+ return false;
+
+ if (level >= G4X_WM_LEVEL_SR &&
+ wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
+ return false;
+
+ if (level >= G4X_WM_LEVEL_HPLL &&
+ wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
+ return false;
+
+ return true;
+}
+
static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1383,7 +1400,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state)
wm_state->wm.plane[plane_id] = raw->plane[plane_id];
level = G4X_WM_LEVEL_SR;
-
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
goto out;
@@ -1395,7 +1411,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state)
wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
level = G4X_WM_LEVEL_HPLL;
-
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
goto out;
@@ -1418,17 +1433,11 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state
*crtc_state)
/*
* Determine if the FBC watermark(s) can be used. IF
* this isn't the case we prefer to disable the FBC
-( watermark(s) rather than disable the SR/HPLL
-* level(s) entirely.
+* watermark(s) rather than disable the SR/HPLL
+* level(s) entirely. 'level-1' is the highest valid
+* level here.
*/
- wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
-
- if (level >= G4X_WM_LEVEL_SR &&
- wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
- wm_state->fbc_en = false;
- else if (level >= G4X_WM_LEVEL_HPLL &&
-wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
- wm_state->fbc_en = false;
+ wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
return 0;
}
--
2.24.1
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[Intel-gfx] [PATCH 00/12] drm/i915: FBC fixes
From: Ville Syrjälä A bunch of FBC fixes. The most important thing is fixing glk+linear, but included a pile of stuff I had lying about for older platforms as well. Ville Syrjälä (12): drm/i915/fbc: Require linear fb stride to be multiple of 512 bytes on gen9/glk drm/i915/fbc: Use the correct plane stride drm/i915/fbc: Fix fence_y_offset handling drm/i915/fbc: Fix nuke for pre-snb platforms drm/i915/fbc: Enable fbc on i865 drm/i915/fbc: Don't clear busy_bits for origin==GTT drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865 drm/i915/fbc: Parametrize FBC_CONTROL drm/i915/fbc: Store the fbc1 compression interval in the params drm/i915/fbc: Reduce fbc1 compression interval to 1 second drm/i915: Fix g4x fbc watermark enable drm/i915: Suppress spurious underruns on gen2 drivers/gpu/drm/i915/display/intel_display.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.h | 1 + drivers/gpu/drm/i915/display/intel_fbc.c | 104 --- drivers/gpu/drm/i915/i915_drv.h | 8 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 19 ++-- drivers/gpu/drm/i915/intel_pm.c | 43 +--- 7 files changed, 135 insertions(+), 59 deletions(-) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/12] drm/i915/fbc: Require linear fb stride to be multiple of 512 bytes on gen9/glk
From: Ville Syrjälä
Display WA #1105 says that FBC requires PLANE_STRIDE to be a multiple
of 512 bytes on gen9 and glk.
This is definitely true for glk as certain tests (such as
igt/kms_big_fb/linear-16bpp-rotate-0) are now failing when the
display resolution results in a plane stride which is not a
multiple of 512 bytes.
Curiously I was not able to reproduce this on a KBL. First I
suspected that our use of the FBC override stride explain this,
but after trying to use the override stride on glk the test
still failed. I did try both the old CHICKEN_MISC_4 way and
the new FBC_CHICKEN way, neither had any effect on the result.
Anyways, we need this at least on glk. But let's trust the spec
and apply the w/a for all gen9 as well, despite being unable to
reproduce the problem.
Cc: José Roberto de Souza
Fixes: 691f7ba58d52 ("drm/i915/display/fbc: Make fences a nice-to-have for
GEN9+")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index c6afa10e814c..7194f9bc62c5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -564,7 +564,7 @@ void intel_fbc_cleanup_cfb(struct drm_i915_private
*dev_priv)
}
static bool stride_is_valid(struct drm_i915_private *dev_priv,
- unsigned int stride)
+ u64 modifier, unsigned int stride)
{
/* This should have been caught earlier. */
if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
@@ -580,6 +580,11 @@ static bool stride_is_valid(struct drm_i915_private
*dev_priv,
if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
return false;
+ /* Display WA #1105: skl,bxt,kbl,cfl,glk */
+ if (IS_GEN(dev_priv, 9) &&
+ modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
+ return false;
+
if (stride > 16384)
return false;
@@ -810,7 +815,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
- if (!stride_is_valid(dev_priv, cache->fb.stride)) {
+ if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
fbc->no_fbc_reason = "framebuffer stride not supported";
return false;
}
--
2.24.1
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[Intel-gfx] [PATCH 05/12] drm/i915/fbc: Enable fbc on i865
From: Ville Syrjälä
Unlike all the other pre-snb desktop platforms i865 actually
supports FBC. Let's enable it.
Quote from the spec:
"DevSDG provides the same Run-Length Encoded Frame Buffer
Compression (RLEFBC) function as exists in DevMGM."
As i865 only has the one pipe we want to skip massaging the
plane<->pipe assignment aimed at getting FBC+LVDS working on
the mobile platforms.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
drivers/gpu/drm/i915/i915_pci.c | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e5fa49337883..a0d1057d75ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16186,7 +16186,8 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
* On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
* port is hooked to pipe B. Hence we want plane A feeding pipe B.
*/
- if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
+ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4 &&
+ INTEL_NUM_PIPES(dev_priv) == 2)
plane->i9xx_plane = (enum i9xx_plane_id) !pipe;
else
plane->i9xx_plane = (enum i9xx_plane_id) pipe;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1faf9d6ec0a4..71afe7bc3d2d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -217,6 +217,7 @@ static const struct intel_device_info i85x_info = {
static const struct intel_device_info i865g_info = {
I845_FEATURES,
PLATFORM(INTEL_I865G),
+ .display.has_fbc = 1,
};
#define GEN3_FEATURES \
--
2.24.1
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[Intel-gfx] [PATCH 07/12] drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865
From: Ville Syrjälä Normally i85x/i865 3D activity will block FBC until a 2D blit occurs. I suppose this was meant to avoid recompression while 3D activity is still going on but the frame hasn't yet been presented. Unfortunately that also means that a page flipped 3D workload will permanently block FBC even if it only renders a single frame and then does nothing. Since we are using software render tracking anyway we might as well flip the chicken bit so that 3D does not block FBC. This will avoid the permament FBC blockage in the aforemention use case, but thanks to the software tracking the compressor will not disturb 3D rendering activity. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 96d9f8853343..088215025661 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2815,6 +2815,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VLV_GU_CTL0_MMIO(VLV_DISPLAY_BASE + 0x2030) #define VLV_GU_CTL1_MMIO(VLV_DISPLAY_BASE + 0x2034) #define SCPD0 _MMIO(0x209c) /* 915+ only */ +#define SCPD_FBC_IGNORE_3D(1 << 6) #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) #define GEN2_IER _MMIO(0x20a0) #define GEN2_IIR _MMIO(0x20a4) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bfb180fe8047..1e99b35f007e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7369,6 +7369,16 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(MEM_MODE, _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); + + /* +* Have FBC ignore 3D activity since we use software +* render tracking, and otherwise a pure 3D workload +* (even if it just renders a single frame and then does +* abosultely nothing) would not allow FBC to recompress +* until a 2D blit occurs. +*/ + I915_WRITE(SCPD0, + _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D)); } static void i830_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for linux-next: build failure after merge of the drm-misc tree
== Series Details ==
Series: linux-next: build failure after merge of the drm-misc tree
URL : https://patchwork.freedesktop.org/series/76709/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4cb00cc7b2f7 linux-next: build failure after merge of the drm-misc tree
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#11:
> On Mon, 20 Apr 2020 13:01:18 +1000 Stephen Rothwell
> wrote:
-:25: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit a07a63b0e24d ("video: fbdev:
controlfb: add COMPILE_TEST support")'
#25:
>> a07a63b0e24d ("video: fbdev: controlfb: add COMPILE_TEST support")
-:63: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
total: 2 errors, 1 warnings, 0 checks, 16 lines checked
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/perf: Add support for multi context perf queries (rev3)
== Series Details == Series: drm/i915/perf: Add support for multi context perf queries (rev3) URL : https://patchwork.freedesktop.org/series/76588/ State : failure == Summary == Applying: drm/i915/perf: break OA config buffer object in 2 Applying: drm/i915/perf: stop using the kernel context Applying: drm/i915/perf: prepare driver to receive multiple ctx handles Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_perf.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_perf.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_perf.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/i915/perf: prepare driver to receive multiple ctx handles When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 4/6] drm/i915/gt: Switch to manual evaluation of RPS
As with the realisation for soft-rc6, we respond to idling the engines
within microseconds, far faster than the response times for HW RC6 and
RPS. Furthermore, our fast parking upon idle, prevents HW RPS from
running for many desktop workloads, as the RPS evaluation intervals are
on the order of tens of milliseconds, but the typical workload is just a
couple of milliseconds, but yet we still need to determine the best
frequency for user latency versus power.
Recognising that the HW evaluation intervals are a poor fit, and that
they were deprecated [in bspec at least] from gen10, start to wean
ourselves off them and replace the EI with a timer and our accurate
busy-stats. The principle benefit of manually evaluating RPS intervals
is that we can be more responsive for better performance and powersaving
for both spiky workloads and steady-state.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1698
Fixes: 98479ada421a ("drm/i915/gt: Treat idling as a RPS downclock event")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Andi Shyti
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 5 +
drivers/gpu/drm/i915/gt/intel_rps.c | 121 ++-
drivers/gpu/drm/i915/gt/intel_rps.h | 15 +++
drivers/gpu/drm/i915/gt/intel_rps_types.h| 5 +
4 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index c943ab0981f0..601be7d4ba79 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -555,6 +555,11 @@ struct intel_engine_cs {
* Idle is defined as active == 0, active is active > 0.
*/
ktime_t start;
+
+ /**
+* @rps: Utilisation at last RPS sampling.
+*/
+ ktime_t rps;
} stats;
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 52151001d7ab..f723a9cdd24e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -15,6 +15,10 @@
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
+#define BUSY_UP95 /* % utilisation */
+#define BUSY_DOWN 85 /* % utilisation */
+#define BUSY_MAX_EI20u /* ms */
+
/*
* Lock protecting IPS related data structures
*/
@@ -45,6 +49,99 @@ static inline void set(struct intel_uncore *uncore,
i915_reg_t reg, u32 val)
intel_uncore_write_fw(uncore, reg, val);
}
+static void rps_timer(struct timer_list *t)
+{
+ struct intel_rps *rps = from_timer(rps, t, timer);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ s64 max_busy[3] = {};
+ ktime_t dt, last;
+
+ for_each_engine(engine, rps_to_gt(rps), id) {
+ s64 busy;
+ int i;
+
+ dt = intel_engine_get_busy_time(engine);
+ last = engine->stats.rps;
+ engine->stats.rps = dt;
+
+ busy = ktime_to_ns(ktime_sub(dt, last));
+ for (i = 0; i < ARRAY_SIZE(max_busy); i++) {
+ if (busy > max_busy[i])
+ swap(busy, max_busy[i]);
+ }
+ }
+
+ dt = ktime_get();
+ last = rps->pm_timestamp;
+ rps->pm_timestamp = dt;
+
+ if (intel_rps_is_active(rps)) {
+ s64 busy;
+ int i;
+
+ dt = ktime_sub(dt, last);
+
+ /*
+* Our goal is to evaluate each engine independently, so we run
+* at the lowest clocks required to sustain the heaviest
+* workload. However, a task may be split into sequential
+* dependent operations across a set of engines, such that
+* the independent contributions do not account for high load,
+* but overall the task is GPU bound. For example, consider
+* video decode on vcs followed by colour post-processing
+* on vecs, followed by general post-processing on rcs.
+* Since multi-engines being active does imply a single
+* continuous workload across all engines, we hedge our
+* bets by only contributing a factor of the distributed
+* load into our busyness calculation.
+*/
+ busy = max_busy[0];
+ for (i = 1; i < ARRAY_SIZE(max_busy); i++) {
+ if (!max_busy[i])
+ break;
+
+ busy += div_u64(max_busy[i], 1 << i);
+ }
+ GT_TRACE(rps_to_gt(rps),
+"busy:%lld [%d%%], max:[%lld, %lld, %lld]\n",
+busy, (int)div64_u64(100 * busy, dt),
+max_busy[0], max_busy[1], max_busy[2]);
+
[Intel-gfx] [CI 5/6] drm/i915/gt: Apply the aggressive downclocking to parking
We treat parking as a manual RPS timeout event, and downclock the GPU
for the next unpark and batch execution. However, having restored the
aggressive downclocking and observed that we have very light workloads
whose only interaction is through the manual parking events, carry over
the aggressive downclocking to the fake RPS events.
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rps.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index f723a9cdd24e..a2ff98706fef 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -835,8 +835,6 @@ void intel_rps_unpark(struct intel_rps *rps)
rps->min_freq_softlimit,
rps->max_freq_softlimit));
- rps->last_adj = 0;
-
mutex_unlock(&rps->lock);
rps->pm_iir = 0;
@@ -851,6 +849,8 @@ void intel_rps_unpark(struct intel_rps *rps)
void intel_rps_park(struct intel_rps *rps)
{
+ int adj;
+
if (!intel_rps_clear_active(rps))
return;
@@ -889,8 +889,13 @@ void intel_rps_park(struct intel_rps *rps)
* (Note we accommodate Cherryview's limitation of only using an
* even bin by applying it to all.)
*/
- rps->cur_freq =
- max_t(int, round_down(rps->cur_freq - 1, 2), rps->min_freq);
+ adj = rps->last_adj;
+ if (adj < 0)
+ adj *= 2;
+ else /* CHV needs even encode values */
+ adj = -2;
+ rps->last_adj = adj;
+ rps->cur_freq = max_t(int, rps->cur_freq + adj, rps->min_freq);
GT_TRACE(rps_to_gt(rps), "park:%x\n", rps->cur_freq);
}
--
2.20.1
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[Intel-gfx] [CI 2/6] drm/i915/gt: Move rps.enabled/active to flags
Pull the boolean intel_rps.enabled and intel_rps.active into a single
flags field, in preparation for more.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 5 +--
drivers/gpu/drm/i915/gt/intel_rps.c | 43 ++-
drivers/gpu/drm/i915/gt/intel_rps.h | 30
drivers/gpu/drm/i915/gt/intel_rps_types.h | 8 +++--
drivers/gpu/drm/i915/gt/selftest_rps.c| 22 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 5 +--
6 files changed, 79 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index f6ba66206273..174a24553322 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -556,7 +556,8 @@ static int rps_boost_show(struct seq_file *m, void *data)
struct drm_i915_private *i915 = gt->i915;
struct intel_rps *rps = >->rps;
- seq_printf(m, "RPS enabled? %d\n", rps->enabled);
+ seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
+ seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
seq_printf(m, "GPU busy? %s\n", yesno(gt->awake));
seq_printf(m, "Boosts outstanding? %d\n",
atomic_read(&rps->num_waiters));
@@ -576,7 +577,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
- if (INTEL_GEN(i915) >= 6 && rps->enabled && gt->awake) {
+ if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
struct intel_uncore *uncore = gt->uncore;
u32 rpup, rpupei;
u32 rpdown, rpdownei;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 2ce006e58b4a..a27e989a08eb 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -648,7 +648,7 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool
interactive)
mutex_lock(&rps->power.mutex);
if (interactive) {
- if (!rps->power.interactive++ && READ_ONCE(rps->active))
+ if (!rps->power.interactive++ && intel_rps_is_active(rps))
rps_set_power(rps, HIGH_POWER);
} else {
GEM_BUG_ON(!rps->power.interactive);
@@ -721,7 +721,7 @@ static int rps_set(struct intel_rps *rps, u8 val, bool
update)
void intel_rps_unpark(struct intel_rps *rps)
{
- if (!rps->enabled)
+ if (!intel_rps_is_enabled(rps))
return;
GT_TRACE(rps_to_gt(rps), "unpark:%x\n", rps->cur_freq);
@@ -732,8 +732,7 @@ void intel_rps_unpark(struct intel_rps *rps)
*/
mutex_lock(&rps->lock);
- WRITE_ONCE(rps->active, true);
-
+ intel_rps_set_active(rps);
intel_rps_set(rps,
clamp(rps->cur_freq,
rps->min_freq_softlimit,
@@ -754,13 +753,12 @@ void intel_rps_park(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (!rps->enabled)
+ if (!intel_rps_clear_active(rps))
return;
if (INTEL_GEN(i915) >= 6)
rps_disable_interrupts(rps);
- WRITE_ONCE(rps->active, false);
if (rps->last_freq <= rps->idle_freq)
return;
@@ -802,7 +800,7 @@ void intel_rps_boost(struct i915_request *rq)
struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
unsigned long flags;
- if (i915_request_signaled(rq) || !READ_ONCE(rps->active))
+ if (i915_request_signaled(rq) || !intel_rps_is_active(rps))
return;
/* Serializes with i915_request_retire() */
@@ -831,7 +829,7 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
GEM_BUG_ON(val > rps->max_freq);
GEM_BUG_ON(val < rps->min_freq);
- if (rps->active) {
+ if (intel_rps_is_active(rps)) {
err = rps_set(rps, val, true);
if (err)
return err;
@@ -1219,6 +1217,7 @@ void intel_rps_enable(struct intel_rps *rps)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
+ bool enabled = false;
if (!HAS_RPS(i915))
return;
@@ -1226,20 +1225,24 @@ void intel_rps_enable(struct intel_rps *rps)
intel_gt_check_clock_frequency(rps_to_gt(rps));
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- if (IS_CHERRYVIEW(i915))
- rps->enabled = chv_rps_enable(rps);
+ if (rps->max_freq <= rps->min_freq)
+ /* leave disabled, no room for dynamic reclocking */;
+ else if (IS_CHERRYVIEW(i915))
+ enabled = chv_rps_enable(rps);
else if (IS_VALLEYVIEW(i915))
- rps->enabled = vlv_rps_enable(rps);
+ enabled = vlv_rps_enable(r
[Intel-gfx] [CI 3/6] drm/i915/gt: Track use of RPS interrupts in flags
Use the new intel_rps.flags field to store whether or not interrupts are
being used with RPS.
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rps.c | 17 -
drivers/gpu/drm/i915/gt/intel_rps.h | 15 +++
drivers/gpu/drm/i915/gt/intel_rps_types.h | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c| 2 +-
4 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index a27e989a08eb..52151001d7ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -742,7 +742,7 @@ void intel_rps_unpark(struct intel_rps *rps)
mutex_unlock(&rps->lock);
- if (INTEL_GEN(rps_to_i915(rps)) >= 6)
+ if (intel_rps_has_interrupts(rps))
rps_enable_interrupts(rps);
if (IS_GEN(rps_to_i915(rps), 5))
@@ -751,12 +751,10 @@ void intel_rps_unpark(struct intel_rps *rps)
void intel_rps_park(struct intel_rps *rps)
{
- struct drm_i915_private *i915 = rps_to_i915(rps);
-
if (!intel_rps_clear_active(rps))
return;
- if (INTEL_GEN(i915) >= 6)
+ if (intel_rps_has_interrupts(rps))
rps_disable_interrupts(rps);
if (rps->last_freq <= rps->idle_freq)
@@ -838,7 +836,7 @@ int intel_rps_set(struct intel_rps *rps, u8 val)
* Make sure we continue to get interrupts
* until we hit the minimum or maximum frequencies.
*/
- if (INTEL_GEN(rps_to_i915(rps)) >= 6) {
+ if (intel_rps_has_interrupts(rps)) {
struct intel_uncore *uncore = rps_to_uncore(rps);
set(uncore,
@@ -1257,6 +1255,11 @@ void intel_rps_enable(struct intel_rps *rps)
GEM_BUG_ON(rps->efficient_freq < rps->min_freq);
GEM_BUG_ON(rps->efficient_freq > rps->max_freq);
+ if (INTEL_GEN(i915) >= 6)
+ intel_rps_set_interrupts(rps);
+ else
+ /* Ironlake currently uses intel_ips.ko */ {}
+
intel_rps_set_enabled(rps);
}
@@ -1270,6 +1273,7 @@ void intel_rps_disable(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
intel_rps_clear_enabled(rps);
+ intel_rps_clear_interrupts(rps);
if (INTEL_GEN(i915) >= 6)
gen6_rps_disable(rps);
@@ -1741,6 +1745,9 @@ void intel_rps_init(struct intel_rps *rps)
if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+
+ if (INTEL_GEN(i915) >= 6)
+ rps_disable_interrupts(rps);
}
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
b/drivers/gpu/drm/i915/gt/intel_rps.h
index a01decf70f31..0ce6a0e492ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -66,4 +66,19 @@ static inline bool intel_rps_clear_active(struct intel_rps
*rps)
return test_and_clear_bit(INTEL_RPS_ACTIVE, &rps->flags);
}
+static inline bool intel_rps_has_interrupts(const struct intel_rps *rps)
+{
+ return test_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
+}
+
+static inline void intel_rps_set_interrupts(struct intel_rps *rps)
+{
+ set_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
+}
+
+static inline void intel_rps_clear_interrupts(struct intel_rps *rps)
+{
+ clear_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
+}
+
#endif /* INTEL_RPS_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h
b/drivers/gpu/drm/i915/gt/intel_rps_types.h
index 1ec44f994bc5..624e93108da4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h
@@ -34,6 +34,7 @@ struct intel_rps_ei {
enum {
INTEL_RPS_ENABLED = 0,
INTEL_RPS_ACTIVE,
+ INTEL_RPS_INTERRUPTS,
};
struct intel_rps {
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i915/gt/selftest_rps.c
index e4cc1c84d206..b89a7d7611f6 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -1017,7 +1017,7 @@ int live_rps_interrupt(void *arg)
* First, let's check whether or not we are receiving interrupts.
*/
- if (!intel_rps_is_enabled(rps))
+ if (!intel_rps_has_interrupts(rps))
return 0;
intel_gt_pm_get(gt);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 6/6] drm/i915/gt: Restore aggressive post-boost downclocking
We reduced the clocks slowly after a boost event based on the
observation that the smoothness of animations suffered. However, since
reducing the evalution intervals, we should be able to respond to the
rapidly fluctuating workload of a simple desktop animation and so
restore the more aggressive downclocking.
References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock")
Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_rps.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index a2ff98706fef..0db543b2ac28 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1693,30 +1693,18 @@ static void rps_work(struct work_struct *work)
adj = 0;
}
- rps->last_adj = adj;
-
/*
-* Limit deboosting and boosting to keep ourselves at the extremes
-* when in the respective power modes (i.e. slowly decrease frequencies
-* while in the HIGH_POWER zone and slowly increase frequencies while
-* in the LOW_POWER zone). On idle, we will hit the timeout and drop
-* to the next level quickly, and conversely if busy we expect to
-* hit a waitboost and rapidly switch into max power.
-*/
- if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
- (adj > 0 && rps->power.mode == LOW_POWER))
- rps->last_adj = 0;
-
- /* sysfs frequency interfaces may have snuck in while servicing the
-* interrupt
+* sysfs frequency limits may have snuck in while
+* servicing the interrupt
*/
new_freq += adj;
new_freq = clamp_t(int, new_freq, min, max);
if (intel_rps_set(rps, new_freq)) {
drm_dbg(&i915->drm, "Failed to set new GPU frequency\n");
- rps->last_adj = 0;
+ adj = 0;
}
+ rps->last_adj = adj;
mutex_unlock(&rps->lock);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/6] drm/i915/gt: Always enable busy-stats for execlists
In the near future, we will utilize the busy-stats on each engine to
approximate the C0 cycles of each, and use that as an input to a manual
RPS mechanism. That entails having busy-stats always enabled and so we
can remove the enable/disable routines and simplify the pmu setup. As a
consequence of always having the stats enabled, we can also show the
current active time via sysfs/engine/xcs/active_time_ns.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 76 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 44 +++
drivers/gpu/drm/i915/i915_pmu.c | 32 +---
drivers/gpu/drm/i915/selftests/i915_request.c | 16 +---
6 files changed, 29 insertions(+), 171 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index d9ee64e2ef79..d10e52ff059f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -310,9 +310,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
struct drm_printer *m,
const char *header, ...);
-int intel_enable_engine_stats(struct intel_engine_cs *engine);
-void intel_disable_engine_stats(struct intel_engine_cs *engine);
-
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
struct i915_request *
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 7c3cb5aedfdf..bbc6ad018134 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1589,58 +1589,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
intel_engine_print_breadcrumbs(engine, m);
}
-/**
- * intel_enable_engine_stats() - Enable engine busy tracking on engine
- * @engine: engine to enable stats collection
- *
- * Start collecting the engine busyness data for @engine.
- *
- * Returns 0 on success or a negative error code.
- */
-int intel_enable_engine_stats(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists *execlists = &engine->execlists;
- unsigned long flags;
- int err = 0;
-
- if (!intel_engine_supports_stats(engine))
- return -ENODEV;
-
- execlists_active_lock_bh(execlists);
- write_seqlock_irqsave(&engine->stats.lock, flags);
-
- if (unlikely(engine->stats.enabled == ~0)) {
- err = -EBUSY;
- goto unlock;
- }
-
- if (engine->stats.enabled++ == 0) {
- struct i915_request * const *port;
- struct i915_request *rq;
-
- engine->stats.enabled_at = ktime_get();
-
- /* XXX submission method oblivious? */
- for (port = execlists->active; (rq = *port); port++)
- engine->stats.active++;
-
- for (port = execlists->pending; (rq = *port); port++) {
- /* Exclude any contexts already counted in active */
- if (!intel_context_inflight_count(rq->context))
- engine->stats.active++;
- }
-
- if (engine->stats.active)
- engine->stats.start = engine->stats.enabled_at;
- }
-
-unlock:
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
- execlists_active_unlock_bh(execlists);
-
- return err;
-}
-
static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
{
ktime_t total = engine->stats.total;
@@ -1649,7 +1597,7 @@ static ktime_t __intel_engine_get_busy_time(struct
intel_engine_cs *engine)
* If the engine is executing something at the moment
* add it to the total.
*/
- if (engine->stats.active)
+ if (atomic_read(&engine->stats.active))
total = ktime_add(total,
ktime_sub(ktime_get(), engine->stats.start));
@@ -1675,28 +1623,6 @@ ktime_t intel_engine_get_busy_time(struct
intel_engine_cs *engine)
return total;
}
-/**
- * intel_disable_engine_stats() - Disable engine busy tracking on engine
- * @engine: engine to disable stats collection
- *
- * Stops collecting the engine busyness data for @engine.
- */
-void intel_disable_engine_stats(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (!intel_engine_supports_stats(engine))
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
- WARN_ON_ONCE(engine->stats.enabled == 0);
- if (--engine->stats.enabled == 0) {
- engine->stats.total = __intel_engine_get_busy_time(engine);
- engine->stats.active = 0;
- }
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
static bool match_ring(struc
[Intel-gfx] ✓ Fi.CI.BAT: success for linux-next: build failure after merge of the drm-misc tree
== Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/76709/ State : success == Summary == CI Bug Log - changes from CI_DRM_8390 -> Patchwork_17505 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/index.html Known issues Here are the changes found in Patchwork_17505 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@hangcheck: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#1580]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/fi-icl-y/igt@i915_selftest@l...@hangcheck.html [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580 Participating hosts (48 -> 42) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8390 -> Patchwork_17505 CI-20190529: 20190529 CI_DRM_8390: 89473e10666c78c4df9e92c9caf03d7311c291cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17505: 4cb00cc7b2f7e895d430b9bf376db1a803fddd6a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4cb00cc7b2f7 linux-next: build failure after merge of the drm-misc tree == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 12/16] drm/i915: Stop using mode->private_flags
From: Ville Syrjälä
Replace the use of mode->private_flags with a truly private bitmaks
in our own crtc state. We also need a copy in the crtc itself so the
vblank code can get at it. We already have scanline_offset in there
for a similar reason, as well as the vblank->hwmode which is assigned
via drm_calc_timestamping_constants(). Fortunately we now have a
nice place for doing the crtc_state->crtc copy in
intel_crtc_update_active_timings() which gets called both for
modesets and init/resume readout.
The one slightly iffy spot is the INHERITED flag which we want to
preserve until userspace/fb_helper does the first proper commit after
actually calling .detecti() on the connectors. Otherwise we don't have
the full sink capabilities (audio,infoframes,etc.) when .compute_config()
gets called and thus we will fail to enable those features when the
first userspace commit happens. The only internal commit we do prior to
that should be from intel_initial_commit() and there we can simply
preserve the INHERITED flag from the readout.
v2: Deal with INHERITED in sanitize_watermarks() as well
CC: Sam Ravnborg
Cc: Daniel Vetter
Cc: Emil Velikov
Reviewed-by: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 13 ++
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 40 ++-
.../drm/i915/display/intel_display_types.h| 9 -
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 6 +--
drivers/gpu/drm/i915/i915_irq.c | 4 +-
7 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 4fec5bd64920..25200f289e6e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1469,8 +1469,7 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
- pipe_config->hw.adjusted_mode.private_flags |=
- I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
+ pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
}
static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
@@ -1558,10 +1557,6 @@ static int gen11_dsi_compute_config(struct intel_encoder
*encoder,
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
- /* We would not operate in periodic command mode */
- pipe_config->hw.adjusted_mode.private_flags &=
- ~I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
-
/*
* In case of TE GATE cmd mode, we
* receive TE from the slave if
@@ -1569,14 +1564,14 @@ static int gen11_dsi_compute_config(struct
intel_encoder *encoder,
*/
if (is_cmd_mode(intel_dsi)) {
if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
- pipe_config->hw.adjusted_mode.private_flags |=
+ pipe_config->mode_flags |=
I915_MODE_FLAG_DSI_USE_TE1 |
I915_MODE_FLAG_DSI_USE_TE0;
else if (intel_dsi->ports == BIT(PORT_B))
- pipe_config->hw.adjusted_mode.private_flags |=
+ pipe_config->mode_flags |=
I915_MODE_FLAG_DSI_USE_TE1;
else
- pipe_config->hw.adjusted_mode.private_flags |=
+ pipe_config->mode_flags |=
I915_MODE_FLAG_DSI_USE_TE0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index d043057d2fa0..5863e339a426 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -252,6 +252,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->wm.need_postvbl_update = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
+ crtc_state->mode_flags &= ~I915_MODE_FLAG_INHERITED;
return &crtc_state->uapi;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9f465edf4063..8a2c0686eeb2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6425,7 +6425,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
* forcibly enable IPS on the first fastset.
*/
if (new_crtc_state->update_pipe &&
- old_crtc_state->hw.adjusted_mode.private_flags &
I915_MODE_FLAG_INHERITED)
+ old_crtc_state->mode_flags & I915_MODE_FLAG_INHERITED)
[Intel-gfx] [PATCH v4 13/16] drm/i915: Replace I915_MODE_FLAG_INHERITED with a boolean
From: Ville Syrjälä
There's no reason for I915_MODE_FLAG_INHERITED to exist as a flag
anymore. Just make it a boolean.
v2: Deal with sanitize_watermarks()
CC: Sam Ravnborg
Cc: Daniel Vetter
Cc: Emil Velikov
Reviewed-by: Daniel Vetter
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c| 17 +++--
.../gpu/drm/i915/display/intel_display_types.h | 2 +-
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 5863e339a426..2deafaa9ec74 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -249,10 +249,10 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->update_wm_post = false;
crtc_state->fifo_changed = false;
crtc_state->preload_luts = false;
+ crtc_state->inherited = false;
crtc_state->wm.need_postvbl_update = false;
crtc_state->fb_bits = 0;
crtc_state->update_planes = 0;
- crtc_state->mode_flags &= ~I915_MODE_FLAG_INHERITED;
return &crtc_state->uapi;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8a2c0686eeb2..d126c6ca1d13 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6424,8 +6424,7 @@ static bool hsw_post_update_enable_ips(const struct
intel_crtc_state *old_crtc_s
* We can't read out IPS on broadwell, assume the worst and
* forcibly enable IPS on the first fastset.
*/
- if (new_crtc_state->update_pipe &&
- old_crtc_state->mode_flags & I915_MODE_FLAG_INHERITED)
+ if (new_crtc_state->update_pipe && old_crtc_state->inherited)
return true;
return !old_crtc_state->ips_enabled;
@@ -13544,8 +13543,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bool ret = true;
u32 bp_gamma = 0;
bool fixup_inherited = fastset &&
- (current_config->mode_flags & I915_MODE_FLAG_INHERITED) &&
- !(pipe_config->mode_flags & I915_MODE_FLAG_INHERITED);
+ current_config->inherited && !pipe_config->inherited;
if (fixup_inherited && !fastboot_enabled(dev_priv)) {
drm_dbg_kms(&dev_priv->drm,
@@ -14697,10 +14695,9 @@ static int intel_atomic_check(struct drm_device *dev,
int ret, i;
bool any_ms = false;
- /* Catch I915_MODE_FLAG_INHERITED */
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- if (new_crtc_state->mode_flags != old_crtc_state->mode_flags)
+ if (new_crtc_state->inherited != old_crtc_state->inherited)
new_crtc_state->uapi.mode_changed = true;
}
@@ -15046,7 +15043,7 @@ static void intel_update_crtc(struct intel_atomic_state
*state,
* of enabling them on the CRTC's first fastset.
*/
if (new_crtc_state->update_pipe && !modeset &&
- old_crtc_state->mode_flags & I915_MODE_FLAG_INHERITED)
+ old_crtc_state->inherited)
intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
@@ -17377,7 +17374,7 @@ static int sanitize_watermarks_add_affected(struct
drm_atomic_state *state)
* Preserve the inherited flag to avoid
* taking the full modeset path.
*/
- crtc_state->mode_flags |= I915_MODE_FLAG_INHERITED;
+ crtc_state->inherited = true;
}
}
@@ -17527,7 +17524,7 @@ static int intel_initial_commit(struct drm_device *dev)
* happen only for the first real commit from userspace.
* So preserve the inherited flag for the time being.
*/
- crtc_state->mode_flags |= I915_MODE_FLAG_INHERITED;
+ crtc_state->inherited = true;
ret = drm_atomic_add_affected_planes(state,
&crtc->base);
if (ret)
@@ -18299,7 +18296,7 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
* set a flag to indicate that a full recalculation is
* needed on the next commit.
*/
- crtc_state->mode_flags |= I915_MODE_FLAG_INHERITED;
+ crtc_state->inherited = true;
intel_crtc_compute_pixel_rate(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40c65274210b..36ef9e144bae 100644
--- a/drivers/gpu/drm/i915/display/intel_display
Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree
On 4/29/20 10:09 AM, Bartlomiej Zolnierkiewicz wrote:
>
> Hi Stephen,
>
> On 4/29/20 12:33 AM, Stephen Rothwell wrote:
>> Hi all,
>>
>> On Mon, 20 Apr 2020 13:01:18 +1000 Stephen Rothwell
>> wrote:
>>>
>>> After merging the drm-misc tree, today's linux-next build (powerpc
>>> allyesconfig) failed like this:
>>>
>>> drivers/video/fbdev/controlfb.c: In function 'controlfb_mmap':
>>> drivers/video/fbdev/controlfb.c:756:23: error: implicit declaration of
>>> function 'pgprot_cached_wthru'; did you mean 'pgprot_cached'?
>>> [-Werror=implicit-function-declaration]
>>> 756 | vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
>>> | ^~~
>>> | pgprot_cached
>>> drivers/video/fbdev/controlfb.c:756:23: error: incompatible types when
>>> assigning to type 'pgprot_t' {aka 'struct '} from type 'int'
>>>
>>> Presumably exposed by commit
>>>
>>> a07a63b0e24d ("video: fbdev: controlfb: add COMPILE_TEST support")
>>>
>>> I just turned off COMPILE_TEST again for today. Please let me know when
>>> this is fixed.
>>
>> This still appears to have not been addressed.
>
> Sorry for the delay, I've just posted a patch (also included below):
>
> "[PATCH] video: fbdev: controlfb: fix build for COMPILE_TEST=y && PPC_PMAC=y
> && PPC32=n"
>
> which should fix it.
>
> Please verify it, thank you!
I have tested it with powerpc allyesconfig now and it adds one dependency too
much,
fixed in v2:
https://lore.kernel.org/lkml/fe520316-3863-e6c4-9581-5d709f49e...@samsung.com/
Sam, could you please review / merge it to drm-misc-next?
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: FBC fixes
== Series Details == Series: drm/i915: FBC fixes URL : https://patchwork.freedesktop.org/series/76714/ State : success == Summary == CI Bug Log - changes from CI_DRM_8390 -> Patchwork_17507 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/index.html Changes --- No changes found Participating hosts (48 -> 41) -- Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8390 -> Patchwork_17507 CI-20190529: 20190529 CI_DRM_8390: 89473e10666c78c4df9e92c9caf03d7311c291cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17507: e3315c131c6d7813355fbd64c818dcd7eefba6ea @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e3315c131c6d drm/i915: Suppress spurious underruns on gen2 04289a752655 drm/i915: Fix g4x fbc watermark enable 46ddb82a1501 drm/i915/fbc: Reduce fbc1 compression interval to 1 second 04304c504db1 drm/i915/fbc: Store the fbc1 compression interval in the params d39ccd00f107 drm/i915/fbc: Parametrize FBC_CONTROL f5b2ff08e428 drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865 db225e51ab61 drm/i915/fbc: Don't clear busy_bits for origin==GTT 873203fee92b drm/i915/fbc: Enable fbc on i865 184da4f02cce drm/i915/fbc: Fix nuke for pre-snb platforms b91927c97ffd drm/i915/fbc: Fix fence_y_offset handling db723f635b7f drm/i915/fbc: Use the correct plane stride 1c91198476c8 drm/i915/fbc: Require linear fb stride to be multiple of 512 bytes on gen9/glk == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for
execlists
URL : https://patchwork.freedesktop.org/series/76715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
081418e7ad56 drm/i915/gt: Always enable busy-stats for execlists
1a3beaa34731 drm/i915/gt: Move rps.enabled/active to flags
-:114: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional
statements (8, 68)
#114: FILE: drivers/gpu/drm/i915/gt/intel_rps.c:1228:
+ if (rps->max_freq <= rps->min_freq)
+ /* leave disabled, no room for dynamic reclocking */;
total: 0 errors, 1 warnings, 0 checks, 296 lines checked
f24bbcfa0789 drm/i915/gt: Track use of RPS interrupts in flags
d663447ef62f drm/i915/gt: Switch to manual evaluation of RPS
c45bc814fafd drm/i915/gt: Apply the aggressive downclocking to parking
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 21abf0bf168d ("drm/i915/gt:
Treat idling as a RPS downclock event")'
#12:
References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event")
total: 1 errors, 1 warnings, 0 checks, 31 lines checked
f62efbcbf8a7 drm/i915/gt: Restore aggressive post-boost downclocking
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 2a8862d2f3da ("drm/i915: Reduce
the RPS shock")'
#12:
References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock")
total: 1 errors, 0 warnings, 0 checks, 34 lines checked
___
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[Intel-gfx] [CI 2/2] drm/i915/gt: Stop keeping the pinned_default_state
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 14 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 ++--
drivers/gpu/drm/i915/gt/selftest_context.c | 11 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 53 +++-
5 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 446e35ac0224..cf46076c59b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -22,18 +22,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
struct intel_context *ce;
- void *map;
ENGINE_TRACE(engine, "\n");
intel_gt_pm_get(engine->gt);
- /* Pin the default state for fast resets from atomic context. */
- map = NULL;
- if (engine->default_state)
- map = shmem_pin_map(engine->default_state);
- engine->pinned_default_state = map;
-
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
@@ -43,6 +36,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
struct drm_i915_gem_object *obj = ce->state->obj;
int type = i915_coherent_map_type(engine->i915);
+ void *map;
map = i915_gem_object_pin_map(obj, type);
if (!IS_ERR(map)) {
@@ -262,12 +256,6 @@ static int __engine_park(struct intel_wakeref *wf)
if (engine->park)
engine->park(engine);
- if (engine->pinned_default_state) {
- shmem_unpin_map(engine->default_state,
- engine->pinned_default_state);
- engine->pinned_default_state = NULL;
- }
-
engine->execlists.no_priolist = false;
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 483d8ff39a0d..1041c3e6eefb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -340,7 +340,6 @@ struct intel_engine_cs {
unsigned long wakeref_serial;
struct intel_wakeref wakeref;
struct file *default_state;
- void *pinned_default_state;
struct {
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7fc4081c34fe..66d1f9d965e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1293,14 +1293,11 @@ execlists_check_context(const struct intel_context *ce,
static void restore_default_state(struct intel_context *ce,
struct intel_engine_cs *engine)
{
- u32 *regs = ce->lrc_reg_state;
-
- if (engine->pinned_default_state)
- memcpy(regs, /* skip restoring the vanilla PPHWSP */
- engine->pinned_default_state + LRC_STATE_OFFSET,
- engine->context_size - PAGE_SIZE);
+ u32 *regs;
+ regs = memset(ce->lrc_reg_state, 0, engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+
ce->runtime.last = intel_context_get_runtime(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index b8ed3cbe1277..a56dff3b157a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -154,10 +154,7 @@ static int live_context_size(void *arg)
*/
for_each_engine(engine, gt, id) {
- struct {
- struct file *state;
- void *pinned;
- } saved;
+ struct file *saved;
if (!engine->context_size)
continue;
@@ -171,8 +168,7 @@ static int live_context_size(void *arg)
* active state is sufficient, we are only checking that we
* don't use more than we planned.
*/
- saved.state = fetch_and_zero(&engine->default_state);
- saved.pinned = fetch_and_zero(&engine->pinned_default_state);
+ saved = fetch_and_zero(&engine->default_state);
/* Overlaps with the execlists redzone */
engine->context_siz
[Intel-gfx] [CI 1/2] drm/i915/gt: Keep a no-frills swappable copy of the default context state
We need to keep the default context state around to instantiate new
contexts (aka golden rendercontext), and we also keep it pinned while
the engine is active so that we can quickly reset a hanging context.
However, the default contexts are large enough to merit keeping in
swappable memory as opposed to kernel memory, so we store them inside
shmemfs. Currently, we use the normal GEM objects to create the default
context image, but we can throw away all but the shmemfs file.
This greatly simplifies the tricky power management code which wants to
run underneath the normal GT locking, and we definitely do not want to
use any high level objects that may appear to recurse back into the GT.
Though perhaps the primary advantage of the complex GEM object is that
we aggressively cache the mapping, but here we are recreating the
vm_area everytime time we unpark. At the worst, we add a lightweight
cache, but first find a microbenchmark that is impacted.
Having started to create some utility functions to make working with
shmemfs objects easier, we can start putting them to wider use, where
GEM objects are overkill, such as storing persistent error state.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Ramalingam C
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 10 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +--
.../gpu/drm/i915/gt/intel_ring_submission.c | 16 +-
drivers/gpu/drm/i915/gt/selftest_context.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 10 +-
drivers/gpu/drm/i915/gt/shmem_utils.c | 176 ++
drivers/gpu/drm/i915/gt/shmem_utils.h | 22 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 26 ---
12 files changed, 224 insertions(+), 72 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/shmem_utils.c
create mode 100644 drivers/gpu/drm/i915/gt/shmem_utils.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 21bb2fb5a6b8..caf00d92ea9d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -111,6 +111,7 @@ gt-y += \
gt/intel_sseu.o \
gt/intel_timeline.o \
gt/intel_workarounds.o \
+ gt/shmem_utils.o \
gt/sysfs_engines.o
# autogenerated null render state
gt-y += \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 7c3cb5aedfdf..80bf71636c0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -834,7 +834,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
intel_engine_cleanup_cmd_parser(engine);
if (engine->default_state)
- i915_gem_object_put(engine->default_state);
+ fput(engine->default_state);
if (engine->kernel_context) {
intel_context_unpin(engine->kernel_context);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 3be679741d22..446e35ac0224 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -15,6 +15,7 @@
#include "intel_gt_pm.h"
#include "intel_rc6.h"
#include "intel_ring.h"
+#include "shmem_utils.h"
static int __engine_unpark(struct intel_wakeref *wf)
{
@@ -30,10 +31,8 @@ static int __engine_unpark(struct intel_wakeref *wf)
/* Pin the default state for fast resets from atomic context. */
map = NULL;
if (engine->default_state)
- map = i915_gem_object_pin_map(engine->default_state,
- I915_MAP_WB);
- if (!IS_ERR_OR_NULL(map))
- engine->pinned_default_state = map;
+ map = shmem_pin_map(engine->default_state);
+ engine->pinned_default_state = map;
/* Discard stale context state from across idling */
ce = engine->kernel_context;
@@ -264,7 +263,8 @@ static int __engine_park(struct intel_wakeref *wf)
engine->park(engine);
if (engine->pinned_default_state) {
- i915_gem_object_unpin_map(engine->default_state);
+ shmem_unpin_map(engine->default_state,
+ engine->pinned_default_state);
engine->pinned_default_state = NULL;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index cfe4feaee982..483d8ff39a0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -339,7 +339,7 @@ struct intel_engine_cs {
unsigned long wakeref_serial;
struct intel_wakeref wakeref;
- struct drm_i915_gem_object *default_state;
+
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details == Series: series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for execlists URL : https://patchwork.freedesktop.org/series/76715/ State : success == Summary == CI Bug Log - changes from CI_DRM_8390 -> Patchwork_17508 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/index.html Known issues Here are the changes found in Patchwork_17508 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@active: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] ([i915#666]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/fi-kbl-x1275/igt@i915_selftest@l...@active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/fi-kbl-x1275/igt@i915_selftest@l...@active.html [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 Participating hosts (48 -> 41) -- Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8390 -> Patchwork_17508 CI-20190529: 20190529 CI_DRM_8390: 89473e10666c78c4df9e92c9caf03d7311c291cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17508: f62efbcbf8a78af6c2ab2a74a9d0baa598358a3f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f62efbcbf8a7 drm/i915/gt: Restore aggressive post-boost downclocking c45bc814fafd drm/i915/gt: Apply the aggressive downclocking to parking d663447ef62f drm/i915/gt: Switch to manual evaluation of RPS f24bbcfa0789 drm/i915/gt: Track use of RPS interrupts in flags 1a3beaa34731 drm/i915/gt: Move rps.enabled/active to flags 081418e7ad56 drm/i915/gt: Always enable busy-stats for execlists == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Stop keeping the pinned_default_state
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 14 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 ++--
drivers/gpu/drm/i915/gt/selftest_context.c| 11 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 53 ++-
.../gpu/drm/i915/gt/selftest_workarounds.c| 4 ++
6 files changed, 51 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 446e35ac0224..cf46076c59b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -22,18 +22,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
struct intel_context *ce;
- void *map;
ENGINE_TRACE(engine, "\n");
intel_gt_pm_get(engine->gt);
- /* Pin the default state for fast resets from atomic context. */
- map = NULL;
- if (engine->default_state)
- map = shmem_pin_map(engine->default_state);
- engine->pinned_default_state = map;
-
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
@@ -43,6 +36,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
struct drm_i915_gem_object *obj = ce->state->obj;
int type = i915_coherent_map_type(engine->i915);
+ void *map;
map = i915_gem_object_pin_map(obj, type);
if (!IS_ERR(map)) {
@@ -262,12 +256,6 @@ static int __engine_park(struct intel_wakeref *wf)
if (engine->park)
engine->park(engine);
- if (engine->pinned_default_state) {
- shmem_unpin_map(engine->default_state,
- engine->pinned_default_state);
- engine->pinned_default_state = NULL;
- }
-
engine->execlists.no_priolist = false;
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 483d8ff39a0d..1041c3e6eefb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -340,7 +340,6 @@ struct intel_engine_cs {
unsigned long wakeref_serial;
struct intel_wakeref wakeref;
struct file *default_state;
- void *pinned_default_state;
struct {
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7fc4081c34fe..66d1f9d965e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1293,14 +1293,11 @@ execlists_check_context(const struct intel_context *ce,
static void restore_default_state(struct intel_context *ce,
struct intel_engine_cs *engine)
{
- u32 *regs = ce->lrc_reg_state;
-
- if (engine->pinned_default_state)
- memcpy(regs, /* skip restoring the vanilla PPHWSP */
- engine->pinned_default_state + LRC_STATE_OFFSET,
- engine->context_size - PAGE_SIZE);
+ u32 *regs;
+ regs = memset(ce->lrc_reg_state, 0, engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+
ce->runtime.last = intel_context_get_runtime(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index b8ed3cbe1277..a56dff3b157a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -154,10 +154,7 @@ static int live_context_size(void *arg)
*/
for_each_engine(engine, gt, id) {
- struct {
- struct file *state;
- void *pinned;
- } saved;
+ struct file *saved;
if (!engine->context_size)
continue;
@@ -171,8 +168,7 @@ static int live_context_size(void *arg)
* active state is sufficient, we are only checking that we
* don't use more than we planned.
*/
- saved.state = fetch_and_zero(&engine->default_state);
- saved.pinned = fetch_and_zero(&engine->pinned_default_state);
+ saved = fetch_and_zero(&engine->default_state);
/* Overlaps with th
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Put drm_display_mode on diet (rev6)
== Series Details ==
Series: drm: Put drm_display_mode on diet (rev6)
URL : https://patchwork.freedesktop.org/series/73674/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
12add0e7c35a drm: Nuke mode->hsync
be723dfd05d8 drm/i915: Introduce some local intel_dp variables
fb85f7555a02 drm: Nuke mode->vrefresh
-:1445: WARNING:LONG_LINE: line over 100 characters
#1445: FILE: drivers/gpu/drm/i915/display/intel_dp.c:8031:
+
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
-:1454: WARNING:LONG_LINE: line over 100 characters
#1454: FILE: drivers/gpu/drm/i915/display/intel_dp.c:8077:
+
drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
total: 0 errors, 2 warnings, 0 checks, 2641 lines checked
37cc5204d554 drm/msm/dpu: Stop copying around mode->private_flags
-:85: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#85: FILE: drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h:330:
+ TP_PROTO(uint32_t drm_id, unsigned int flags),
total: 0 errors, 0 warnings, 1 checks, 71 lines checked
191e00221dec drm: Shrink {width,height}_mm to u16
85fc97e7e8bd drm: Shrink mode->type to u8
9b86ee3bbf40 drm: Make mode->flags u32
1c06ebb25df5 drm: Shrink drm_display_mode timings
1b1cbd21b272 drm: Flatten drm_mode_vrefresh()
1bd439876388 drm: pahole struct drm_display_mode
cf2c5f9cc994 drm/mcde: Use mode->clock instead of reverse calculating it from
the vrefresh
d2feee34d331 drm/i915: Stop using mode->private_flags
32edf0d94942 drm/i915: Replace I915_MODE_FLAG_INHERITED with a boolean
7ef686ec8216 drm/gma500: Stop using mode->private_flags
d4b55166f89f drm: Nuke mode->private_flags
db0286c4611d drm: Replace mode->export_head with a boolean
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [patch] drm/i915: Update Slylake PCI IDs
Add three new devices 0x1913, 0x1915, and 0x1917 also known as iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927, and 0x192A according to specifications. Of note, the second to last digit seems to correspond to GT#. Signed-off-by: Alexei Podtelezhnikov --- include/drm/i915_pciids.h | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 1d2c1221..c12bce9e 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -331,15 +331,18 @@ INTEL_VGA_DEVICE(0x22b3, info) #define INTEL_SKL_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x1906, info) /* ULT GT1 */ + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ + INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */ #define INTEL_SKL_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x190E, info) /* ULX GT1 */ + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ + INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */ #define INTEL_SKL_GT1_IDS(info)\ INTEL_SKL_ULT_GT1_IDS(info), \ INTEL_SKL_ULX_GT1_IDS(info), \ INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ + INTEL_VGA_DEVICE(0x1917, info), /* DT GT1.5 */ \ INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ @@ -359,21 +362,21 @@ INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ #define INTEL_SKL_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3 */ + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 28W */ \ + INTEL_VGA_DEVICE(0x1926, info) /* ULT GT3e */ #define INTEL_SKL_GT3_IDS(info) \ INTEL_SKL_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ + INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ + INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */ #define INTEL_SKL_GT4_IDS(info) \ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */ #define INTEL_SKL_IDS(info) \ INTEL_SKL_GT1_IDS(info), \ -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gt: Stop keeping the pinned_default_state
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_pm.c| 14 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++---
drivers/gpu/drm/i915/gt/selftest_context.c | 11 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 53 +++-
5 files changed, 49 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 446e35ac0224..cf46076c59b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -22,18 +22,11 @@ static int __engine_unpark(struct intel_wakeref *wf)
struct intel_engine_cs *engine =
container_of(wf, typeof(*engine), wakeref);
struct intel_context *ce;
- void *map;
ENGINE_TRACE(engine, "\n");
intel_gt_pm_get(engine->gt);
- /* Pin the default state for fast resets from atomic context. */
- map = NULL;
- if (engine->default_state)
- map = shmem_pin_map(engine->default_state);
- engine->pinned_default_state = map;
-
/* Discard stale context state from across idling */
ce = engine->kernel_context;
if (ce) {
@@ -43,6 +36,7 @@ static int __engine_unpark(struct intel_wakeref *wf)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && ce->state) {
struct drm_i915_gem_object *obj = ce->state->obj;
int type = i915_coherent_map_type(engine->i915);
+ void *map;
map = i915_gem_object_pin_map(obj, type);
if (!IS_ERR(map)) {
@@ -262,12 +256,6 @@ static int __engine_park(struct intel_wakeref *wf)
if (engine->park)
engine->park(engine);
- if (engine->pinned_default_state) {
- shmem_unpin_map(engine->default_state,
- engine->pinned_default_state);
- engine->pinned_default_state = NULL;
- }
-
engine->execlists.no_priolist = false;
/* While gt calls i915_vma_parked(), we have to break the lock cycle */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 483d8ff39a0d..1041c3e6eefb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -340,7 +340,6 @@ struct intel_engine_cs {
unsigned long wakeref_serial;
struct intel_wakeref wakeref;
struct file *default_state;
- void *pinned_default_state;
struct {
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7fc4081c34fe..be796c3554d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1293,14 +1293,11 @@ execlists_check_context(const struct intel_context *ce,
static void restore_default_state(struct intel_context *ce,
struct intel_engine_cs *engine)
{
- u32 *regs = ce->lrc_reg_state;
-
- if (engine->pinned_default_state)
- memcpy(regs, /* skip restoring the vanilla PPHWSP */
- engine->pinned_default_state + LRC_STATE_OFFSET,
- engine->context_size - PAGE_SIZE);
+ u32 *regs;
+ regs = memset(ce->lrc_reg_state, 0, engine->context_size - PAGE_SIZE);
execlists_init_reg_state(regs, ce, engine, ce->ring, false);
+
ce->runtime.last = intel_context_get_runtime(ce);
}
@@ -4200,7 +4197,8 @@ static void __execlists_reset(struct intel_engine_cs
*engine, bool stalled)
* to recreate its own state.
*/
GEM_BUG_ON(!intel_context_is_pinned(ce));
- restore_default_state(ce, engine);
+ execlists_init_reg_state(ce->lrc_reg_state,
+ce, engine, ce->ring, false);
out_replay:
ENGINE_TRACE(engine, "replay {head:%04x, tail:%04x}\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c
b/drivers/gpu/drm/i915/gt/selftest_context.c
index b8ed3cbe1277..a56dff3b157a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -154,10 +154,7 @@ static int live_context_size(void *arg)
*/
for_each_engine(engine, gt, id) {
- struct {
- struct file *state;
- void *pinned;
- } saved;
+ struct file *saved;
if (!engine->context_size)
continue;
@@ -171,8 +168,7 @@ static int live_context_size(void *arg)
Re: [Intel-gfx] [patch] drm/i915: Update Slylake PCI IDs
On Wed, 29 Apr 2020, Ville Syrjälä wrote: > On Tue, Apr 28, 2020 at 11:27:50PM -0400, Alexei Podtelezhnikov wrote: >> Add three new devices 0x1513, 0x1515, and 0x1517 also known as > > typo 0x15 vs. 0x19 > >> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927, >> and 0x192A according to specifications. > > I'd make this three separate patches, just in case we have to revert > some of these in the future. Most worried about the 0x192a case since > the evidence is rather poor. I fixed the typo. The absence of 0x192a from the most recent Windows drivers indicates that it was never printed. The absence of evidence is the evidence of absence. The second to last digit indicates that it was planned as GT3. Lastly, making 3 patches for something non-existent is such an overkill. These are trivial to revert line-by-line too. Please be considerate to occasional helpers and do not ask to much of them. Regards, Alexei ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Put drm_display_mode on diet (rev6)
== Series Details ==
Series: drm: Put drm_display_mode on diet (rev6)
URL : https://patchwork.freedesktop.org/series/73674/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8390 -> Patchwork_17509
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17509/index.html
Known issues
Here are the changes found in Patchwork_17509 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([i915#1580])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17509/fi-icl-u2/igt@i915_selftest@l...@hangcheck.html
[i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
Participating hosts (48 -> 42)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u
fi-ctg-p8600 fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8390 -> Patchwork_17509
CI-20190529: 20190529
CI_DRM_8390: 89473e10666c78c4df9e92c9caf03d7311c291cb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17509: db0286c4611d0fd85cb14c8d4d8be259f1b8abb5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db0286c4611d drm: Replace mode->export_head with a boolean
d4b55166f89f drm: Nuke mode->private_flags
7ef686ec8216 drm/gma500: Stop using mode->private_flags
32edf0d94942 drm/i915: Replace I915_MODE_FLAG_INHERITED with a boolean
d2feee34d331 drm/i915: Stop using mode->private_flags
cf2c5f9cc994 drm/mcde: Use mode->clock instead of reverse calculating it from
the vrefresh
1bd439876388 drm: pahole struct drm_display_mode
1b1cbd21b272 drm: Flatten drm_mode_vrefresh()
1c06ebb25df5 drm: Shrink drm_display_mode timings
9b86ee3bbf40 drm: Make mode->flags u32
85fc97e7e8bd drm: Shrink mode->type to u8
191e00221dec drm: Shrink {width,height}_mm to u16
37cc5204d554 drm/msm/dpu: Stop copying around mode->private_flags
fb85f7555a02 drm: Nuke mode->vrefresh
be723dfd05d8 drm/i915: Introduce some local intel_dp variables
12add0e7c35a drm: Nuke mode->hsync
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17509/index.html
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Allow some leniency in PCU reads
Extend the timeout for pcode reads to 10ms as they should not be performed along critical paths, and succeeding after a short delay is better than failing entirely. References: https://gitlab.freedesktop.org/drm/intel/-/issues/1800 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_sideband.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 14daf6af6854..d5129c1dd452 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -429,7 +429,7 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, mutex_lock(&i915->sb_lock); err = __sandybridge_pcode_rw(i915, mbox, val, val1, -500, 0, +500, 20, true); mutex_unlock(&i915->sb_lock); -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/25] perf/core: Only copy-to-user after completely unlocking all locks, v3.
We inadvertently create a dependency on mmap_sem with a whole chain.
This breaks any user who wants to take a lock and call rcu_barrier(),
while also taking that lock inside mmap_sem:
<4> [604.892532] ==
<4> [604.892534] WARNING: possible circular locking dependency detected
<4> [604.892536] 5.6.0-rc7-CI-Patchwork_17096+ #1 Tainted: G U
<4> [604.892537] --
<4> [604.892538] kms_frontbuffer/2595 is trying to acquire lock:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
<4> [604.892547]
but task is already holding lock:
<4> [604.892547] 888484716050 (reservation_ww_class_mutex){+.+.}, at:
i915_gem_object_pin_to_display_plane+0x89/0x270 [i915]
<4> [604.892592]
which lock already depends on the new lock.
<4> [604.892593]
the existing dependency chain (in reverse order) is:
<4> [604.892594]
-> #6 (reservation_ww_class_mutex){+.+.}:
<4> [604.892597]__ww_mutex_lock.constprop.15+0xc3/0x1090
<4> [604.892598]ww_mutex_lock+0x39/0x70
<4> [604.892600]dma_resv_lockdep+0x10e/0x1f5
<4> [604.892602]do_one_initcall+0x58/0x300
<4> [604.892604]kernel_init_freeable+0x17b/0x1dc
<4> [604.892605]kernel_init+0x5/0x100
<4> [604.892606]ret_from_fork+0x24/0x50
<4> [604.892607]
-> #5 (reservation_ww_class_acquire){+.+.}:
<4> [604.892609]dma_resv_lockdep+0xec/0x1f5
<4> [604.892610]do_one_initcall+0x58/0x300
<4> [604.892610]kernel_init_freeable+0x17b/0x1dc
<4> [604.892611]kernel_init+0x5/0x100
<4> [604.892612]ret_from_fork+0x24/0x50
<4> [604.892613]
-> #4 (&mm->mmap_sem#2){}:
<4> [604.892615]__might_fault+0x63/0x90
<4> [604.892617]_copy_to_user+0x1e/0x80
<4> [604.892619]perf_read+0x200/0x2b0
<4> [604.892621]vfs_read+0x96/0x160
<4> [604.892622]ksys_read+0x9f/0xe0
<4> [604.892623]do_syscall_64+0x4f/0x220
<4> [604.892624]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892625]
-> #3 (&cpuctx_mutex){+.+.}:
<4> [604.892626]__mutex_lock+0x9a/0x9c0
<4> [604.892627]perf_event_init_cpu+0xa4/0x140
<4> [604.892629]perf_event_init+0x19d/0x1cd
<4> [604.892630]start_kernel+0x362/0x4e4
<4> [604.892631]secondary_startup_64+0xa4/0xb0
<4> [604.892631]
-> #2 (pmus_lock){+.+.}:
<4> [604.892633]__mutex_lock+0x9a/0x9c0
<4> [604.892633]perf_event_init_cpu+0x6b/0x140
<4> [604.892635]cpuhp_invoke_callback+0x9b/0x9d0
<4> [604.892636]_cpu_up+0xa2/0x140
<4> [604.892637]do_cpu_up+0x61/0xa0
<4> [604.892639]smp_init+0x57/0x96
<4> [604.892639]kernel_init_freeable+0x87/0x1dc
<4> [604.892640]kernel_init+0x5/0x100
<4> [604.892642]ret_from_fork+0x24/0x50
<4> [604.892642]
-> #1 (cpu_hotplug_lock.rw_sem){}:
<4> [604.892643]cpus_read_lock+0x34/0xd0
<4> [604.892644]rcu_barrier+0xaa/0x190
<4> [604.892645]kernel_init+0x21/0x100
<4> [604.892647]ret_from_fork+0x24/0x50
<4> [604.892647]
-> #0 (rcu_state.barrier_mutex){+.+.}:
<4> [604.892649]__lock_acquire+0x1328/0x15d0
<4> [604.892650]lock_acquire+0xa7/0x1c0
<4> [604.892651]__mutex_lock+0x9a/0x9c0
<4> [604.892652]rcu_barrier+0x23/0x190
<4> [604.892680]i915_gem_object_unbind+0x29d/0x3f0 [i915]
<4> [604.892707]i915_gem_object_pin_to_display_plane+0x141/0x270 [i915]
<4> [604.892737]intel_pin_and_fence_fb_obj+0xec/0x1f0 [i915]
<4> [604.892767]intel_plane_pin_fb+0x3f/0xd0 [i915]
<4> [604.892797]intel_prepare_plane_fb+0x13b/0x5c0 [i915]
<4> [604.892798]drm_atomic_helper_prepare_planes+0x85/0x110
<4> [604.892827]intel_atomic_commit+0xda/0x390 [i915]
<4> [604.892828]drm_atomic_helper_set_config+0x57/0xa0
<4> [604.892830]drm_mode_setcrtc+0x1c4/0x720
<4> [604.892830]drm_ioctl_kernel+0xb0/0xf0
<4> [604.892831]drm_ioctl+0x2e1/0x390
<4> [604.892833]ksys_ioctl+0x7b/0x90
<4> [604.892835]__x64_sys_ioctl+0x11/0x20
<4> [604.892835]do_syscall_64+0x4f/0x220
<4> [604.892836]entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [604.892837]
Changes since v1:
- Use (*values)[n++] in perf_read_one().
Changes since v2:
- Centrally allocate values.
Signed-off-by: Maarten Lankhorst
fixup perf patch
Signed-off-by: Maarten Lankhorst
---
kernel/events/core.c | 45 +---
1 file changed, 21 insertions(+), 24 deletions(-)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index c8f65daee1f9..b33b99fceecb 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -5102,20 +5102,16 @@ static int __perf_read_group_add(struct perf_event
*leader,
}
static int perf_read_group(struct perf_event *event,
- u64 read_format, char __user *buf)
+ u64 r
[Intel-gfx] [PATCH 02/25] drm/i915/gt: Move the batch buffer pool from the engine to the gt
From: Chris Wilson
Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want to have an effective cache of
recently allocated buffers available for reuse, we need to decouple that
cache from the engine powermanagement and make it timer based. As there
is no reason then to keep it within the engine (where it once made
retirement order easier to track), we can move it up the hierarchy to the
owner of the memory allocations.
v2: Hook up to debugfs/drop_caches to clear the cache on demand.
Signed-off-by: Chris Wilson
Cc: Maarten Lankhorst
Cc: Tvrtko Ursulin
Signed-off-by: Maarten Lankhorst
Link:
https://patchwork.freedesktop.org/patch/msgid/20200416071804.30187-1-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/Makefile | 2 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 1 -
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 20 ++--
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 18 +--
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 1 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 -
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 -
drivers/gpu/drm/i915/gt/intel_engine_pool.h | 34 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 --
drivers/gpu/drm/i915/gt/intel_gt.c| 3 +
...l_engine_pool.c => intel_gt_buffer_pool.c} | 111 --
.../gpu/drm/i915/gt/intel_gt_buffer_pool.h| 38 ++
...l_types.h => intel_gt_buffer_pool_types.h} | 15 ++-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 ++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 -
drivers/gpu/drm/i915/i915_debugfs.c | 4 +
16 files changed, 160 insertions(+), 114 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/gt/intel_engine_pool.h
rename drivers/gpu/drm/i915/gt/{intel_engine_pool.c => intel_gt_buffer_pool.c}
(53%)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h
rename drivers/gpu/drm/i915/gt/{intel_engine_pool_types.h =>
intel_gt_buffer_pool_types.h} (54%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 21bb2fb5a6b8..dedd260ae920 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -87,11 +87,11 @@ gt-y += \
gt/intel_engine_cs.o \
gt/intel_engine_heartbeat.o \
gt/intel_engine_pm.o \
- gt/intel_engine_pool.o \
gt/intel_engine_user.o \
gt/intel_ggtt.o \
gt/intel_ggtt_fencing.o \
gt/intel_gt.o \
+ gt/intel_gt_buffer_pool.o \
gt/intel_gt_clock_utils.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 0598e5382a1d..3a146aa2593b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -6,7 +6,6 @@
#include "i915_drv.h"
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-#include "gt/intel_engine_pool.h"
#include "i915_gem_client_blt.h"
#include "i915_gem_object_blt.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 964f73f062c1..414859fa2673 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -15,8 +15,8 @@
#include "gem/i915_gem_ioctls.h"
#include "gt/intel_context.h"
-#include "gt/intel_engine_pool.h"
#include "gt/intel_gt.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
@@ -1194,13 +1194,13 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
unsigned int len)
{
struct reloc_cache *cache = &eb->reloc_cache;
- struct intel_engine_pool_node *pool;
+ struct intel_gt_buffer_pool_node *pool;
struct i915_request *rq;
struct i915_vma *batch;
u32 *cmd;
int err;
- pool = intel_engine_get_pool(eb->engine, PAGE_SIZE);
+ pool = intel_gt_get_buffer_pool(eb->engine->gt, PAGE_SIZE);
if (IS_ERR(pool))
return PTR_ERR(pool);
@@ -1229,7 +1229,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
goto err_unpin;
}
- err = intel_engine_pool_mark_active(pool, rq);
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
if (err)
goto err_request;
@@ -1270,7 +1270,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
err_unmap:
i915_gem_object_unpin_map(pool->obj);
out_pool:
- intel_engine_pool_put(pool);
+ intel_gt_buffer_pool_put(pool);
return err;
}
@@ -1887,7 +1887,7 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb,
static int eb_parse(struct i915_execbuffer *eb)
{
[Intel-gfx] [PATCH 17/25] drm/i915: Kill last user of intel_context_create_request outside of selftests
Instead of using intel_context_create_request(), use intel_context_pin()
and i915_create_request directly.
Now all those calls are gone outside of selftests. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index adddc5c93b48..51a0e114c367 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1746,6 +1746,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
const struct i915_wa *wa;
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
unsigned int i;
u32 *results;
int err;
@@ -1758,29 +1759,34 @@ static int engine_wa_list_verify(struct intel_context
*ce,
return PTR_ERR(vma);
intel_engine_pm_get(ce->engine);
- rq = intel_context_create_request(ce);
- intel_engine_pm_put(ce->engine);
+ i915_gem_ww_ctx_init(&ww, false);
+retry:
+ err = i915_gem_object_lock(vma->obj, &ww);
+ if (err == 0)
+ err = intel_context_pin_ww(ce, &ww);
+ if (err)
+ goto err_pm;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- goto err_vma;
+ goto err_unpin;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
- if (err) {
- i915_request_add(rq);
- goto err_vma;
- }
-
- err = wa_list_srm(rq, wal, vma);
- if (err)
- goto err_vma;
+ if (err == 0)
+ err = wa_list_srm(rq, wal, vma);
i915_request_get(rq);
+ if (err)
+ i915_request_set_error_once(rq, err);
i915_request_add(rq);
+
+ if (err)
+ goto err_rq;
+
if (i915_request_wait(rq, 0, HZ / 5) < 0) {
err = -ETIME;
goto err_rq;
@@ -1805,7 +1811,16 @@ static int engine_wa_list_verify(struct intel_context
*ce,
err_rq:
i915_request_put(rq);
-err_vma:
+err_unpin:
+ intel_context_unpin(ce);
+err_pm:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+ intel_engine_pm_put(ce->engine);
i915_vma_unpin(vma);
i915_vma_put(vma);
return err;
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/25] drm/i915: Use ww locking in intel_renderstate.
We want to start using ww locking in intel_context_pin, for this
we need to lock multiple objects, and the single i915_gem_object_lock
is not enough.
Convert to using ww-waiting, and make sure we always pin intel_context_state,
even if we don't have a renderstate object.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_gt.c | 21 +++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 78 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 ++-
3 files changed, 72 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 20aa6789e693..25137a840804 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -409,21 +409,20 @@ static int __engines_record_defaults(struct intel_gt *gt)
/* We must be able to switch to something! */
GEM_BUG_ON(!engine->kernel_context);
- err = intel_renderstate_init(&so, engine);
- if (err)
- goto out;
-
ce = intel_context_create(engine);
if (IS_ERR(ce)) {
err = PTR_ERR(ce);
goto out;
}
- rq = intel_context_create_request(ce);
+ err = intel_renderstate_init(&so, ce);
+ if (err)
+ goto err;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- intel_context_put(ce);
- goto out;
+ goto err_fini;
}
err = intel_engine_emit_ctx_wa(rq);
@@ -437,9 +436,13 @@ static int __engines_record_defaults(struct intel_gt *gt)
err_rq:
requests[id] = i915_request_get(rq);
i915_request_add(rq);
- intel_renderstate_fini(&so);
- if (err)
+err_fini:
+ intel_renderstate_fini(&so, ce);
+err:
+ if (err) {
+ intel_context_put(ce);
goto out;
+ }
}
/* Flush the default context image to memory, and enable powersaving. */
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index ee5ca48d6953..d2cfa521fe89 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -27,6 +27,7 @@
#include "i915_drv.h"
#include "intel_renderstate.h"
+#include "gt/intel_context.h"
#include "intel_ring.h"
static const struct intel_renderstate_rodata *
@@ -74,10 +75,9 @@ static int render_state_setup(struct intel_renderstate *so,
u32 *d;
int ret;
- i915_gem_object_lock(so->vma->obj, NULL);
ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush);
if (ret)
- goto out_unlock;
+ return ret;
d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0));
@@ -158,8 +158,6 @@ static int render_state_setup(struct intel_renderstate *so,
ret = 0;
out:
i915_gem_object_finish_access(so->vma->obj);
-out_unlock:
- i915_gem_object_unlock(so->vma->obj);
return ret;
err:
@@ -171,33 +169,47 @@ static int render_state_setup(struct intel_renderstate
*so,
#undef OUT_BATCH
int intel_renderstate_init(struct intel_renderstate *so,
- struct intel_engine_cs *engine)
+ struct intel_context *ce)
{
- struct drm_i915_gem_object *obj;
+ struct intel_engine_cs *engine = ce->engine;
+ struct drm_i915_gem_object *obj = NULL;
int err;
memset(so, 0, sizeof(*so));
so->rodata = render_state_get_rodata(engine);
- if (!so->rodata)
- return 0;
+ if (so->rodata) {
+ if (so->rodata->batch_items * 4 > PAGE_SIZE)
+ return -EINVAL;
+
+ obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
+ if (IS_ERR(so->vma)) {
+ err = PTR_ERR(so->vma);
+ goto err_obj;
+ }
+ }
- if (so->rodata->batch_items * 4 > PAGE_SIZE)
- return -EINVAL;
+ i915_gem_ww_ctx_init(&so->ww, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err_fini;
- obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
+ /* return early if there's nothing to setup */
+ if (!err && !so->rodata)
+ return 0;
- so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
- if (
[Intel-gfx] [PATCH 23/25] drm/i915: Add ww locking to vm_fault_gtt
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++-
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index b39c24dae64e..e35e8d0b6938 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -283,37 +283,46 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
struct intel_runtime_pm *rpm = &i915->runtime_pm;
struct i915_ggtt *ggtt = &i915->ggtt;
bool write = area->vm_flags & VM_WRITE;
+ struct i915_gem_ww_ctx ww;
intel_wakeref_t wakeref;
struct i915_vma *vma;
pgoff_t page_offset;
int srcu;
int ret;
- /* Sanity check that we allow writing into this object */
- if (i915_gem_object_is_readonly(obj) && write)
- return VM_FAULT_SIGBUS;
-
/* We don't use vmf->pgoff since that has the fake offset */
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
trace_i915_gem_object_fault(obj, page_offset, true, write);
- ret = i915_gem_object_pin_pages(obj);
+ wakeref = intel_runtime_pm_get(rpm);
+
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ ret = i915_gem_object_lock(obj, &ww);
if (ret)
- goto err;
+ goto err_rpm;
- wakeref = intel_runtime_pm_get(rpm);
+ /* Sanity check that we allow writing into this object */
+ if (i915_gem_object_is_readonly(obj) && write) {
+ ret = -EFAULT;
+ goto err_rpm;
+ }
- ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu);
+ ret = i915_gem_object_pin_pages(obj);
if (ret)
goto err_rpm;
+ ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu);
+ if (ret)
+ goto err_pages;
+
/* Now pin it into the GTT as needed */
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
- PIN_MAPPABLE |
- PIN_NONBLOCK /* NOWARN */ |
- PIN_NOEVICT);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
+ PIN_MAPPABLE |
+ PIN_NONBLOCK /* NOWARN */ |
+ PIN_NOEVICT);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
/* Use a partial view if it is bigger than available space */
struct i915_ggtt_view view =
compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
@@ -328,11 +337,11 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
* all hope that the hardware is able to track future writes.
*/
- vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
- if (IS_ERR(vma)) {
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) {
flags = PIN_MAPPABLE;
view.type = I915_GGTT_VIEW_PARTIAL;
- vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0,
0, flags);
}
/* The entire mappable GGTT is pinned? Unexpected! */
@@ -389,10 +398,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
__i915_vma_unpin(vma);
err_reset:
intel_gt_reset_unlock(ggtt->vm.gt, srcu);
+err_pages:
+ i915_gem_object_unpin_pages(obj);
err_rpm:
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff(&ww);
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
intel_runtime_pm_put(rpm, wakeref);
- i915_gem_object_unpin_pages(obj);
-err:
return i915_error_to_vmf_fault(ret);
}
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/25] Revert "drm/i915/gem: Drop relocation slowpath"
This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
slowpath"). We need the slowpath relocation for taking ww-mutex
inside the page fault handler, and we will take this mutex when
pinning all objects.
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 239 +-
1 file changed, 235 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 414859fa2673..73dfcbf07886 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1531,7 +1531,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
* we would try to acquire the struct mutex again. Obviously
* this is bad and so lockdep complains vehemently.
*/
- copied = __copy_from_user(r, urelocs, count * sizeof(r[0]));
+ pagefault_disable();
+ copied = __copy_from_user_inatomic(r, urelocs, count *
sizeof(r[0]));
+ pagefault_enable();
if (unlikely(copied)) {
remain = -EFAULT;
goto out;
@@ -1579,6 +1581,236 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
return remain;
}
+static int
+eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
+{
+ const struct drm_i915_gem_exec_object2 *entry = ev->exec;
+ struct drm_i915_gem_relocation_entry *relocs =
+ u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < entry->relocation_count; i++) {
+ u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
+
+ if ((s64)offset < 0) {
+ err = (int)offset;
+ goto err;
+ }
+ }
+ err = 0;
+err:
+ reloc_cache_reset(&eb->reloc_cache);
+ return err;
+}
+
+static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
+{
+ const char __user *addr, *end;
+ unsigned long size;
+ char __maybe_unused c;
+
+ size = entry->relocation_count;
+ if (size == 0)
+ return 0;
+
+ if (size > N_RELOC(ULONG_MAX))
+ return -EINVAL;
+
+ addr = u64_to_user_ptr(entry->relocs_ptr);
+ size *= sizeof(struct drm_i915_gem_relocation_entry);
+ if (!access_ok(addr, size))
+ return -EFAULT;
+
+ end = addr + size;
+ for (; addr < end; addr += PAGE_SIZE) {
+ int err = __get_user(c, addr);
+ if (err)
+ return err;
+ }
+ return __get_user(c, end - 1);
+}
+
+static int eb_copy_relocations(const struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_relocation_entry *relocs;
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ const unsigned int nreloc = eb->exec[i].relocation_count;
+ struct drm_i915_gem_relocation_entry __user *urelocs;
+ unsigned long size;
+ unsigned long copied;
+
+ if (nreloc == 0)
+ continue;
+
+ err = check_relocations(&eb->exec[i]);
+ if (err)
+ goto err;
+
+ urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
+ size = nreloc * sizeof(*relocs);
+
+ relocs = kvmalloc_array(size, 1, GFP_KERNEL);
+ if (!relocs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ /* copy_from_user is limited to < 4GiB */
+ copied = 0;
+ do {
+ unsigned int len =
+ min_t(u64, BIT_ULL(31), size - copied);
+
+ if (__copy_from_user((char *)relocs + copied,
+(char __user *)urelocs + copied,
+len))
+ goto end;
+
+ copied += len;
+ } while (copied < size);
+
+ /*
+* As we do not update the known relocation offsets after
+* relocating (due to the complexities in lock handling),
+* we need to mark them as invalid now so that we force the
+* relocation processing next time. Just in case the target
+* object is evicted and then rebound into its old
+* presumed_offset before the next execbuffer - if that
+* happened we would make the mistake of assuming that the
+* relocations were valid.
+*/
+ if (!user_access_begin
[Intel-gfx] [PATCH 08/25] drm/i915/gem: Make eb_add_lut interruptible wait on object lock.
The lock here should be interruptible, so we can backoff if needed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 9922dc68311f..5b4f6fb1428c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -774,7 +774,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb,
if (err == 0) { /* And nor has this handle */
struct drm_i915_gem_object *obj = vma->obj;
- i915_gem_object_lock(obj, NULL);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
+ if (err) {
+ radix_tree_delete(&ctx->handles_vma, handle);
+ goto unlock;
+ }
+
if (idr_find(&eb->file->object_idr, handle) == obj) {
list_add(&lut->obj_link, &obj->lut_list);
} else {
@@ -783,6 +788,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb,
}
i915_gem_object_unlock(obj);
}
+unlock:
mutex_unlock(&ctx->mutex);
}
if (unlikely(err))
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 04/25] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory
eviction. We don't use it yet, but lets start adding the definition
first.
To use it, we have to pass a non-NULL ww to gem_object_lock, and don't
unlock directly. It is done in i915_gem_ww_ctx_fini.
Changes since v1:
- Change ww_ctx and obj order in locking functions (Jonas Lahtinen)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 10 ++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_object.h| 38 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c| 2 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
.../i915/gem/selftests/i915_gem_client_blt.c | 2 +-
.../i915/gem/selftests/i915_gem_coherency.c | 10 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c| 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
.../gpu/drm/i915/gt/selftest_workarounds.c| 2 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 52 +--
drivers/gpu/drm/i915/i915_gem.h | 11
drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++
drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +-
.../drm/i915/selftests/intel_memory_region.c | 2 +-
26 files changed, 175 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6bb87965801e..54047f8454ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
- i915_gem_object_lock(vma->obj);
+ i915_gem_object_lock(vma->obj, NULL);
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
i915_gem_object_unpin_from_display_plane(vma);
@@ -16972,7 +16972,7 @@ static int intel_framebuffer_init(struct
intel_framebuffer *intel_fb,
if (!intel_fb->frontbuffer)
return -ENOMEM;
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
tiling = i915_gem_object_get_tiling(obj);
stride = i915_gem_object_get_stride(obj);
i915_gem_object_unlock(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 3a146aa2593b..2f1d8150256b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0);
i915_sw_fence_init(&work->wait, clear_pages_work_notify);
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
err = i915_sw_fence_await_reservation(&work->wait,
obj->base.resv, NULL,
true, I915_FENCE_TIMEOUT,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 900ea8b7fc8f..7abb2deb1327 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx)
continue;
rcu_read_unlock();
- i915_gem_object_lock(obj);
+ i915_gem_object_lock(obj, NULL);
list_for_each_entry(lut, &obj->lut_list, obj_link) {
if (lut->ctx != ctx)
continue;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
index 7db5a793739d..cfadccfc2990 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
@@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf
*dma_buf, enum dma_data_dire
if (err)
return err;
- err = i915_gem_object_lock_interruptible(obj);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
goto out;
@@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf,
enum dma_data_direct
if (err)
[Intel-gfx] [PATCH 24/25] drm/i915: Add ww locking to pin_to_display_plane
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 --
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
2 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 8ebceebd11b0..c0d153284984 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -37,6 +37,12 @@ void i915_gem_object_flush_if_display(struct
drm_i915_gem_object *obj)
i915_gem_object_unlock(obj);
}
+void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj)
+{
+ if (i915_gem_object_is_framebuffer(obj))
+ __i915_gem_object_flush_for_display(obj);
+}
+
/**
* Moves a single object to the WC read, and possibly write domain.
* @obj: object to act on
@@ -197,18 +203,12 @@ int i915_gem_object_set_cache_level(struct
drm_i915_gem_object *obj,
if (ret)
return ret;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
-
/* Always invalidate stale cachelines */
if (obj->cache_level != cache_level) {
i915_gem_object_set_cache_coherency(obj, cache_level);
obj->cache_dirty = true;
}
- i915_gem_object_unlock(obj);
-
/* The cache-level will be applied when each vma is rebound. */
return i915_gem_object_unbind(obj,
I915_GEM_OBJECT_UNBIND_ACTIVE |
@@ -255,6 +255,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void
*data,
struct drm_i915_gem_caching *args = data;
struct drm_i915_gem_object *obj;
enum i915_cache_level level;
+ struct i915_gem_ww_ctx ww;
int ret = 0;
switch (args->caching) {
@@ -293,7 +294,18 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev,
void *data,
goto out;
}
- ret = i915_gem_object_set_cache_level(obj, level);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ ret = i915_gem_object_lock(obj, &ww);
+ if (!ret)
+ ret = i915_gem_object_set_cache_level(obj, level);
+
+ if (ret == -EDEADLK) {
+ ret = i915_gem_ww_ctx_backoff(&ww);
+ if (!ret)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
out:
i915_gem_object_put(obj);
@@ -313,6 +325,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
unsigned int flags)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct i915_gem_ww_ctx ww;
struct i915_vma *vma;
int ret;
@@ -320,6 +333,11 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj))
return ERR_PTR(-EINVAL);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ ret = i915_gem_object_lock(obj, &ww);
+ if (ret)
+ goto err;
/*
* The display engine is not coherent with the LLC cache on gen6. As
* a result, we make sure that the pinning that is about to occur is
@@ -334,7 +352,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
HAS_WT(i915) ?
I915_CACHE_WT : I915_CACHE_NONE);
if (ret)
- return ERR_PTR(ret);
+ goto err;
/*
* As the user may map the buffer once pinned in the display plane
@@ -347,18 +365,31 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
vma = ERR_PTR(-ENOSPC);
if ((flags & PIN_MAPPABLE) == 0 &&
(!view || view->type == I915_GGTT_VIEW_NORMAL))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
- flags |
- PIN_MAPPABLE |
- PIN_NONBLOCK);
- if (IS_ERR(vma))
- vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
- if (IS_ERR(vma))
- return vma;
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, alignment,
+ flags | PIN_MAPPABLE |
+ PIN_NONBLOCK);
+ if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK))
+ vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0,
+ alignment, flags);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err;
+ }
vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
- i915_gem_object_flush_if_display(obj);
+ i915_gem_object_flush_if_display_loc
[Intel-gfx] [PATCH 19/25] drm/i915: Dirty hack to fix selftests locking inversion
Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 64948386630f..fe9fff5a63b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -459,6 +459,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* +* timeline->mutex should be the inner lock, but is used as outer lock. +* Hack around this to shut up lockdep in selftests.. +*/ + lockdep_unpin_lock(&ce->timeline->mutex, rq->cookie); + mutex_release(&ce->timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(&ce->timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(&ce->timeline->mutex); + return rq; } -- 2.26.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/25] drm/i915: Use per object locking in execbuf, v9.
Now that we changed execbuf submission slightly to allow us to do all
pinning in one place, we can now simply add ww versions on top of
struct_mutex. All we have to do is a separate path for -EDEADLK
handling, which needs to unpin all gem bo's before dropping the lock,
then starting over.
This finally allows us to do parallel submission, but because not
all of the pinning code uses the ww ctx yet, we cannot completely
drop struct_mutex yet.
Changes since v1:
- Keep struct_mutex for now. :(
Changes since v2:
- Make sure we always lock the ww context in slowpath.
Changes since v3:
- Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be
done on normal unlock path.
- Unconditionally release vmas and context.
Changes since v4:
- Rebased on top of struct_mutex reduction.
Changes since v5:
- Remove training wheels.
Changes since v6:
- Fix accidentally broken -ENOSPC handling.
Changes since v7:
- Handle gt buffer pool better.
Changes since v8:
- Properly clear variables, to make -EDEADLK handling not BUG.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 350 ++
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/i915_gem.h | 1 +
3 files changed, 207 insertions(+), 150 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 5b4f6fb1428c..96b172f9b9f7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -249,6 +249,8 @@ struct i915_execbuffer {
/** list of vma that have execobj.relocation_count */
struct list_head relocs;
+ struct i915_gem_ww_ctx ww;
+
/**
* Track the most recently used object for relocations, as we
* frequently have to perform multiple relocations within the same
@@ -267,14 +269,18 @@ struct i915_execbuffer {
struct i915_request *rq;
u32 *rq_cmd;
unsigned int rq_size;
+ struct intel_gt_buffer_pool_node *pool;
} reloc_cache;
+ struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for
-EDEADLK handling */
+
u64 invalid_flags; /** Set of execobj.flags that are invalid */
u32 context_flags; /** Set of execobj.flags to insert from the ctx */
u32 batch_start_offset; /** Location within object of batch */
u32 batch_len; /** Length of batch within object */
u32 batch_flags; /** Flags composed for emit_bb_start() */
+ struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch
buffer */
/**
* Indicate either the size of the hastable used to resolve
@@ -441,24 +447,18 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
-static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
-{
- GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
-
- if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- __i915_vma_unpin(vma);
-}
-
static inline void
eb_unreserve_vma(struct eb_vma *ev)
{
if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
return;
- __eb_unreserve_vma(ev->vma, ev->flags);
ev->flags &= ~__EXEC_OBJECT_RESERVED;
+
+ if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(ev->vma);
+
+ __i915_vma_unpin(ev->vma);
}
static int
@@ -552,16 +552,6 @@ eb_add_vma(struct i915_execbuffer *eb,
eb->batch = ev;
}
-
- if (eb_pin_vma(eb, entry, ev)) {
- if (entry->offset != vma->node.start) {
- entry->offset = vma->node.start | UPDATE;
- eb->args->flags |= __EXEC_HAS_RELOC;
- }
- } else {
- eb_unreserve_vma(ev);
- list_add_tail(&ev->bind_link, &eb->unbound);
- }
}
static inline int use_cpu_reloc(const struct reloc_cache *cache,
@@ -646,10 +636,6 @@ static int eb_reserve(struct i915_execbuffer *eb)
* This avoid unnecessary unbinding of later objects in order to make
* room for the earlier objects *unless* we need to defragment.
*/
-
- if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex))
- return -EINTR;
-
pass = 0;
do {
list_for_each_entry(ev, &eb->unbound, bind_link) {
@@ -657,8 +643,8 @@ static int eb_reserve(struct i915_execbuffer *eb)
if (err)
break;
}
- if (!(err == -ENOSPC || err == -EAGAIN))
- break;
+ if (err != -ENOSPC)
+ return err;
/* Resort *all* the objects into priority order */
INIT_LIST_HEAD(&eb->unbound);
@@ -688,13 +674,6 @@ static int eb_r
[Intel-gfx] [PATCH 25/25] drm/i915: Ensure we hold the pin mutex
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
drivers/gpu/drm/i915/i915_vma.h | 1 +
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c
b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index e35e17810ac8..2f8bb8c44f90 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -207,7 +207,7 @@ int intel_renderstate_init(struct intel_renderstate *so,
if (err)
goto err_context;
- err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
goto err_context;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 164e23e0fc11..837706d28cc5 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -869,6 +869,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
#ifdef CONFIG_PROVE_LOCKING
if (debug_locks && lockdep_is_held(&vma->vm->i915->drm.struct_mutex))
WARN_ON(!ww);
+ if (debug_locks && ww && vma->resv)
+ assert_vma_held(vma);
#endif
BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND);
@@ -1009,8 +1011,13 @@ int i915_ggtt_pin(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
+ WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv));
+
do {
- err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL);
+ if (ww)
+ err = i915_vma_pin_ww(vma, ww, 0, align, flags |
PIN_GLOBAL);
+ else
+ err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL);
if (err != -ENOSPC) {
if (!err) {
err = i915_vma_wait_for_bind(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2e3779a8a437..d937ce950481 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -242,6 +242,7 @@ i915_vma_pin_ww(struct i915_vma *vma, struct
i915_gem_ww_ctx *ww,
static inline int __must_check
i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
{
+ WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv));
return i915_vma_pin_ww(vma, NULL, size, alignment, flags);
}
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/25] Revert "drm/i915/gem: Split eb_vma into its own allocation"
This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974.
This conflicts with the ww mutex handling, which needs to drop
the references after gpu submission anyway, because otherwise we
may risk unlocking a BO after first freeing it.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 131 --
1 file changed, 58 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 057e0ba14b47..9922dc68311f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -40,11 +40,6 @@ struct eb_vma {
u32 handle;
};
-struct eb_vma_array {
- struct kref kref;
- struct eb_vma vma[];
-};
-
enum {
FORCE_CPU_RELOC = 1,
FORCE_GTT_RELOC,
@@ -57,6 +52,7 @@ enum {
#define __EXEC_OBJECT_NEEDS_MAPBIT(29)
#define __EXEC_OBJECT_NEEDS_BIAS BIT(28)
#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */
+#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN |
__EXEC_OBJECT_HAS_FENCE)
#define __EXEC_HAS_RELOC BIT(31)
#define __EXEC_INTERNAL_FLAGS (~0u << 31)
@@ -287,7 +283,6 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
- struct eb_vma_array *array;
};
static int eb_parse(struct i915_execbuffer *eb);
@@ -299,62 +294,8 @@ static inline bool eb_use_cmdparser(const struct
i915_execbuffer *eb)
eb->args->batch_len);
}
-static struct eb_vma_array *eb_vma_array_create(unsigned int count)
-{
- struct eb_vma_array *arr;
-
- arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN);
- if (!arr)
- return NULL;
-
- kref_init(&arr->kref);
- arr->vma[0].vma = NULL;
-
- return arr;
-}
-
-static inline void eb_unreserve_vma(struct eb_vma *ev)
-{
- struct i915_vma *vma = ev->vma;
-
- if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE))
- __i915_vma_unpin_fence(vma);
-
- if (ev->flags & __EXEC_OBJECT_HAS_PIN)
- __i915_vma_unpin(vma);
-
- ev->flags &= ~(__EXEC_OBJECT_HAS_PIN |
- __EXEC_OBJECT_HAS_FENCE);
-}
-
-static void eb_vma_array_destroy(struct kref *kref)
-{
- struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref);
- struct eb_vma *ev = arr->vma;
-
- while (ev->vma) {
- eb_unreserve_vma(ev);
- i915_vma_put(ev->vma);
- ev++;
- }
-
- kvfree(arr);
-}
-
-static void eb_vma_array_put(struct eb_vma_array *arr)
-{
- kref_put(&arr->kref, eb_vma_array_destroy);
-}
-
static int eb_create(struct i915_execbuffer *eb)
{
- /* Allocate an extra slot for use by the command parser + sentinel */
- eb->array = eb_vma_array_create(eb->buffer_count + 2);
- if (!eb->array)
- return -ENOMEM;
-
- eb->vma = eb->array->vma;
-
if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) {
unsigned int size = 1 + ilog2(eb->buffer_count);
@@ -388,10 +329,8 @@ static int eb_create(struct i915_execbuffer *eb)
break;
} while (--size);
- if (unlikely(!size)) {
- eb_vma_array_put(eb->array);
+ if (unlikely(!size))
return -ENOMEM;
- }
eb->lut_size = size;
} else {
@@ -502,6 +441,26 @@ eb_pin_vma(struct i915_execbuffer *eb,
return !eb_vma_misplaced(entry, vma, ev->flags);
}
+static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags)
+{
+ GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN));
+
+ if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE))
+ __i915_vma_unpin_fence(vma);
+
+ __i915_vma_unpin(vma);
+}
+
+static inline void
+eb_unreserve_vma(struct eb_vma *ev)
+{
+ if (!(ev->flags & __EXEC_OBJECT_HAS_PIN))
+ return;
+
+ __eb_unreserve_vma(ev->vma, ev->flags);
+ ev->flags &= ~__EXEC_OBJECT_RESERVED;
+}
+
static int
eb_validate_vma(struct i915_execbuffer *eb,
struct drm_i915_gem_exec_object2 *entry,
@@ -944,13 +903,31 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned
long handle)
}
}
+static void eb_release_vmas(const struct i915_execbuffer *eb)
+{
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+
+ for (i = 0; i < count; i++) {
+ struct eb_vma *ev = &eb->vma[i];
+ struct i915_vma *vma = ev->vma;
+
+ if (!vma)
+ break;
+
+ eb->vma[i].vma = NULL;
+
+ if (ev->flags & __EXEC_OBJECT_HAS_PIN)
+ __eb_unreserve_vma(vma, ev->flags);
+
+ i915_vma_put(vma);
+ }
+}
+
static v
[Intel-gfx] [PATCH 12/25] drm/i915: Nuke arguments to eb_pin_engine
Those arguments are already set as eb.file and eb.args, so kill off
the extra arguments. This will allow us to move eb_pin_engine() to
after we reserved all BO's.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 96b172f9b9f7..ffe6853119bb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2468,11 +2468,10 @@ static void eb_unpin_engine(struct i915_execbuffer *eb)
}
static unsigned int
-eb_select_legacy_ring(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_select_legacy_ring(struct i915_execbuffer *eb)
{
struct drm_i915_private *i915 = eb->i915;
+ struct drm_i915_gem_execbuffer2 *args = eb->args;
unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
if (user_ring_id != I915_EXEC_BSD &&
@@ -2487,7 +2486,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
- bsd_idx = gen8_dispatch_bsd_engine(i915, file);
+ bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file);
} else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
bsd_idx <= I915_EXEC_BSD_RING2) {
bsd_idx >>= I915_EXEC_BSD_SHIFT;
@@ -2512,18 +2511,16 @@ eb_select_legacy_ring(struct i915_execbuffer *eb,
}
static int
-eb_pin_engine(struct i915_execbuffer *eb,
- struct drm_file *file,
- struct drm_i915_gem_execbuffer2 *args)
+eb_pin_engine(struct i915_execbuffer *eb)
{
struct intel_context *ce;
unsigned int idx;
int err;
if (i915_gem_context_user_engines(eb->gem_context))
- idx = args->flags & I915_EXEC_RING_MASK;
+ idx = eb->args->flags & I915_EXEC_RING_MASK;
else
- idx = eb_select_legacy_ring(eb, file, args);
+ idx = eb_select_legacy_ring(eb);
ce = i915_gem_context_get_engine(eb->gem_context, idx);
if (IS_ERR(ce))
@@ -2822,7 +2819,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
- err = eb_pin_engine(&eb, file, args);
+ err = eb_pin_engine(&eb);
if (unlikely(err))
goto err_context;
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/25] drm/i915: Add ww context handling to context_barrier_task
This is required if we want to pass a ww context in intel_context_pin
and gen6_ppgtt_pin().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++-
.../drm/i915/gem/selftests/i915_gem_context.c | 22 +++-
2 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 7abb2deb1327..c640f70f29f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1094,6 +1094,7 @@ I915_SELFTEST_DECLARE(static intel_engine_mask_t
context_barrier_inject_fault);
static int context_barrier_task(struct i915_gem_context *ctx,
intel_engine_mask_t engines,
bool (*skip)(struct intel_context *ce, void
*data),
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
int (*emit)(struct i915_request *rq, void
*data),
void (*task)(void *data),
void *data)
@@ -1101,6 +1102,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
struct context_barrier_task *cb;
struct i915_gem_engines_iter it;
struct i915_gem_engines *e;
+ struct i915_gem_ww_ctx ww;
struct intel_context *ce;
int err = 0;
@@ -1138,10 +1140,21 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
if (skip && skip(ce, data))
continue;
- rq = intel_context_create_request(ce);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ err = intel_context_pin(ce);
+ if (err)
+ goto err;
+
+ if (pin)
+ err = pin(ce, &ww, data);
+ if (err)
+ goto err_unpin;
+
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
- break;
+ goto err_unpin;
}
err = 0;
@@ -1151,6 +1164,16 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
err = i915_active_add_request(&cb->base, rq);
i915_request_add(rq);
+err_unpin:
+ intel_context_unpin(ce);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+
if (err)
break;
}
@@ -1206,6 +1229,17 @@ static void set_ppgtt_barrier(void *data)
i915_vm_close(old);
}
+static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx
*ww, void *data)
+{
+ struct i915_address_space *vm = ce->vm;
+
+ if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
+ /* ppGTT is not part of the legacy context image */
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+
+ return 0;
+}
+
static int emit_ppgtt_update(struct i915_request *rq, void *data)
{
struct i915_address_space *vm = rq->context->vm;
@@ -1262,20 +1296,10 @@ static int emit_ppgtt_update(struct i915_request *rq,
void *data)
static bool skip_ppgtt_update(struct intel_context *ce, void *data)
{
- if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))
- return true;
-
if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915))
- return false;
-
- if (!atomic_read(&ce->pin_count))
- return true;
-
- /* ppGTT is not part of the legacy context image */
- if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm)))
- return true;
-
- return false;
+ return !ce->state;
+ else
+ return !atomic_read(&ce->pin_count);
}
static int set_ppgtt(struct drm_i915_file_private *file_priv,
@@ -1326,6 +1350,7 @@ static int set_ppgtt(struct drm_i915_file_private
*file_priv,
*/
err = context_barrier_task(ctx, ALL_ENGINES,
skip_ppgtt_update,
+ pin_ppgtt_update,
emit_ppgtt_update,
set_ppgtt_barrier,
old);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index bcfe0f230cef..be9d4b45b289 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1902,8 +1902,8 @@ static int mock_context_barrier(void *arg)
return -ENOMEM;
counter = 0;
- err = context_barrier_task(ctx, 0,
-
[Intel-gfx] [PATCH 22/25] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2.
Make sure vma_lock is not used as inner lock when kernel context is used,
and add ww handling where appropriate.
Signed-off-by: Maarten Lankhorst
---
.../i915/gem/selftests/i915_gem_coherency.c | 26 ++--
.../drm/i915/gem/selftests/i915_gem_mman.c| 41 ++-
drivers/gpu/drm/i915/gt/selftest_rps.c| 30 --
drivers/gpu/drm/i915/selftests/i915_request.c | 18 +---
4 files changed, 75 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 99f8466a108a..d93b7d9ad174 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -199,25 +199,25 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
i915_gem_object_lock(ctx->obj, NULL);
err = i915_gem_object_set_to_gtt_domain(ctx->obj, true);
- i915_gem_object_unlock(ctx->obj);
if (err)
- return err;
+ goto out_unlock;
vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_unlock;
+ }
rq = intel_engine_create_kernel_request(ctx->engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto out_unpin;
}
cs = intel_ring_begin(rq, 4);
if (IS_ERR(cs)) {
- i915_request_add(rq);
- i915_vma_unpin(vma);
- return PTR_ERR(cs);
+ err = PTR_ERR(cs);
+ goto out_rq;
}
if (INTEL_GEN(ctx->engine->i915) >= 8) {
@@ -238,14 +238,16 @@ static int gpu_set(struct context *ctx, unsigned long
offset, u32 v)
}
intel_ring_advance(rq, cs);
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
- i915_vma_unpin(vma);
+out_rq:
i915_request_add(rq);
+out_unpin:
+ i915_vma_unpin(vma);
+out_unlock:
+ i915_gem_object_unlock(ctx->obj);
return err;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index eec58da734bd..c8b9343cc88c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -528,31 +528,42 @@ static int make_obj_busy(struct drm_i915_gem_object *obj)
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
int err;
vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ i915_gem_ww_ctx_init(&ww, false);
+retry:
+ err = i915_gem_object_lock(obj, &ww);
+ if (!err)
+ err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
if (err)
- return err;
+ goto err;
rq = intel_engine_create_kernel_request(engine);
if (IS_ERR(rq)) {
- i915_vma_unpin(vma);
- return PTR_ERR(rq);
+ err = PTR_ERR(rq);
+ goto err_unpin;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, true);
if (err == 0)
err = i915_vma_move_to_active(vma, rq,
EXEC_OBJECT_WRITE);
- i915_vma_unlock(vma);
i915_request_add(rq);
+err_unpin:
i915_vma_unpin(vma);
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
if (err)
return err;
}
@@ -1000,6 +1011,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
for_each_uabi_engine(engine, i915) {
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL);
if (IS_ERR(vma)) {
@@ -1007,9 +1019,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915,
goto out_unmap;
}
-
[Intel-gfx] [PATCH 18/25] drm/i915: Convert i915_perf to ww locking as well
We have the ordering of timeline->mutex vs resv_lock wrong,
convert the i915_pin_vma and intel_context_pin as well to
future-proof this.
We may need to do future changes to do this more transaction-like,
and only get down to a single i915_gem_ww_ctx, but for now this
should work.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_perf.c | 57 +++-
1 file changed, 42 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index c533f569dd42..c675e6cd5967 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1195,24 +1195,39 @@ static struct intel_context *oa_pin_context(struct
i915_perf_stream *stream)
struct i915_gem_engines_iter it;
struct i915_gem_context *ctx = stream->ctx;
struct intel_context *ce;
- int err;
+ struct i915_gem_ww_ctx ww;
+ int err = -ENODEV;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
if (ce->engine != stream->engine) /* first match! */
continue;
- /*
-* As the ID is the gtt offset of the context's vma we
-* pin the vma to ensure the ID remains fixed.
-*/
- err = intel_context_pin(ce);
- if (err == 0) {
- stream->pinned_ctx = ce;
- break;
- }
+ err = 0;
+ break;
}
i915_gem_context_unlock_engines(ctx);
+ if (err)
+ return ERR_PTR(err);
+
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ /*
+* As the ID is the gtt offset of the context's vma we
+* pin the vma to ensure the ID remains fixed.
+*/
+ err = intel_context_pin_ww(ce, &ww);
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+
+ if (err)
+ return ERR_PTR(err);
+
+ stream->pinned_ctx = ce;
return stream->pinned_ctx;
}
@@ -1925,15 +1940,22 @@ emit_oa_config(struct i915_perf_stream *stream,
{
struct i915_request *rq;
struct i915_vma *vma;
+ struct i915_gem_ww_ctx ww;
int err;
vma = get_oa_vma(stream, oa_config);
if (IS_ERR(vma))
return PTR_ERR(vma);
- err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ err = i915_gem_object_lock(vma->obj, &ww);
+ if (err)
+ goto err;
+
+ err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
if (err)
- goto err_vma_put;
+ goto err;
intel_engine_pm_get(ce->engine);
rq = i915_request_create(ce);
@@ -1955,11 +1977,9 @@ emit_oa_config(struct i915_perf_stream *stream,
goto err_add_request;
}
- i915_vma_lock(vma);
err = i915_request_await_object(rq, vma->obj, 0);
if (!err)
err = i915_vma_move_to_active(vma, rq, 0);
- i915_vma_unlock(vma);
if (err)
goto err_add_request;
@@ -1973,7 +1993,14 @@ emit_oa_config(struct i915_perf_stream *stream,
i915_request_add(rq);
err_vma_unpin:
i915_vma_unpin(vma);
-err_vma_put:
+err:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+
+ i915_gem_ww_ctx_fini(&ww);
i915_vma_put(vma);
return err;
}
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/25] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.
This is the last part outside of selftests that still don't use the
correct lock ordering of timeline->mutex vs resv_lock.
With gem fixed, there are a few places that still get locking wrong:
- gvt/scheduler.c
- i915_perf.c
- Most if not all selftests.
Changes since v1:
- Add intel_engine_pm_get/put() calls to fix use-after-free when using
intel_engine_get_pool().
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 80 +++--
.../gpu/drm/i915/gem/i915_gem_object_blt.c| 156 +++---
.../gpu/drm/i915/gem/i915_gem_object_blt.h| 3 +
3 files changed, 165 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
index 2f1d8150256b..6d2f6ac500dc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
@@ -156,6 +156,7 @@ static void clear_pages_worker(struct work_struct *work)
struct clear_pages_work *w = container_of(work, typeof(*w), work);
struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
struct i915_vma *batch;
int err = w->dma.error;
@@ -171,17 +172,20 @@ static void clear_pages_worker(struct work_struct *work)
obj->read_domains = I915_GEM_GPU_DOMAINS;
obj->write_domain = 0;
- err = i915_vma_pin(vma, 0, 0, PIN_USER);
- if (unlikely(err))
+ i915_gem_ww_ctx_init(&ww, false);
+ intel_engine_pm_get(w->ce->engine);
+retry:
+ err = intel_context_pin_ww(w->ce, &ww);
+ if (err)
goto out_signal;
- batch = intel_emit_vma_fill_blt(w->ce, vma, w->value);
+ batch = intel_emit_vma_fill_blt(w->ce, vma, &ww, w->value);
if (IS_ERR(batch)) {
err = PTR_ERR(batch);
- goto out_unpin;
+ goto out_ctx;
}
- rq = intel_context_create_request(w->ce);
+ rq = i915_request_create(w->ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto out_batch;
@@ -223,9 +227,19 @@ static void clear_pages_worker(struct work_struct *work)
i915_request_add(rq);
out_batch:
intel_emit_vma_release(w->ce, batch);
-out_unpin:
- i915_vma_unpin(vma);
+out_ctx:
+ intel_context_unpin(w->ce);
out_signal:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+
+ i915_vma_unpin(w->sleeve->vma);
+ intel_engine_pm_put(w->ce->engine);
+
if (unlikely(err)) {
dma_fence_set_error(&w->dma, err);
dma_fence_signal(&w->dma);
@@ -233,6 +247,45 @@ static void clear_pages_worker(struct work_struct *work)
}
}
+static int pin_wait_clear_pages_work(struct clear_pages_work *w,
+struct intel_context *ce)
+{
+ struct i915_vma *vma = w->sleeve->vma;
+ struct i915_gem_ww_ctx ww;
+ int err;
+
+ i915_gem_ww_ctx_init(&ww, false);
+retry:
+ err = i915_gem_object_lock(vma->obj, &ww);
+ if (err)
+ goto out;
+
+ err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out;
+
+ err = i915_sw_fence_await_reservation(&w->wait,
+ vma->obj->base.resv, NULL,
+ true, I915_FENCE_TIMEOUT,
+ I915_FENCE_GFP);
+ if (err)
+ goto err_unpin_vma;
+
+ dma_resv_add_excl_fence(vma->obj->base.resv, &w->dma);
+
+err_unpin_vma:
+ if (err)
+ i915_vma_unpin(vma);
+out:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
+ return err;
+}
+
static int __i915_sw_fence_call
clear_pages_work_notify(struct i915_sw_fence *fence,
enum i915_sw_fence_notify state)
@@ -286,18 +339,9 @@ int i915_gem_schedule_fill_pages_blt(struct
drm_i915_gem_object *obj,
dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0);
i915_sw_fence_init(&work->wait, clear_pages_work_notify);
- i915_gem_object_lock(obj, NULL);
- err = i915_sw_fence_await_reservation(&work->wait,
- obj->base.resv, NULL,
- true, I915_FENCE_TIMEOUT,
- I915_FENCE_GFP);
- if (err < 0) {
+ err = pin_wait_clear_pages_work(work, ce);
+ if (err < 0)
dma_fence_set_error(&work->dma, err);
- } else {
- dma_resv_add_e
[Intel-gfx] [PATCH 20/25] drm/i915/selftests: Fix locking inversion in lrc selftest.
This function does not use intel_context_create_request, so it has
to use the same locking order as normal code. This is required to
shut up lockdep in selftests.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 22a26482a33c..28ad06b13643 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4663,6 +4663,7 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
{
struct intel_context *ce;
struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
enum {
RING_START_IDX = 0,
RING_TAIL_IDX,
@@ -4677,7 +4678,11 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
if (IS_ERR(ce))
return PTR_ERR(ce);
- err = intel_context_pin(ce);
+ i915_gem_ww_ctx_init(&ww, false);
+retry:
+ err = i915_gem_object_lock(scratch->obj, &ww);
+ if (!err)
+ err = intel_context_pin_ww(ce, &ww);
if (err)
goto err_put;
@@ -4706,11 +4711,9 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
*cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32);
*cs++ = 0;
- i915_vma_lock(scratch);
err = i915_request_await_object(rq, scratch->obj, true);
if (!err)
err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE);
- i915_vma_unlock(scratch);
i915_request_get(rq);
i915_request_add(rq);
@@ -4747,6 +4750,12 @@ static int __live_lrc_state(struct intel_engine_cs
*engine,
err_unpin:
intel_context_unpin(ce);
err_put:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ }
+ i915_gem_ww_ctx_fini(&ww);
intel_context_put(ce);
return err;
}
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/25] drm/i915: Remove locking from i915_gem_object_prepare_read/write
Execbuffer submission will perform its own WW locking, and we
cannot rely on the implicit lock there.
This also makes it clear that the GVT code will get a lockdep splat when
multiple batchbuffer shadows need to be performed in the same instance,
fix that up.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 20 ++-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 13 ++--
drivers/gpu/drm/i915/gem/i915_gem_object.h| 1 -
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 -
.../i915/gem/selftests/i915_gem_coherency.c | 14 +
.../drm/i915/gem/selftests/i915_gem_context.c | 12 ---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 5 -
drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 -
drivers/gpu/drm/i915/i915_gem.c | 20 +--
9 files changed, 70 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index c0acfc97fae3..8ebceebd11b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -576,19 +576,17 @@ int i915_gem_object_prepare_read(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -616,8 +614,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object
*obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
@@ -630,20 +626,18 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
if (!i915_gem_object_has_struct_page(obj))
return -ENODEV;
- ret = i915_gem_object_lock_interruptible(obj, NULL);
- if (ret)
- return ret;
+ assert_object_held(obj);
ret = i915_gem_object_wait(obj,
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_ALL,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- goto err_unlock;
+ return ret;
ret = i915_gem_object_pin_pages(obj);
if (ret)
- goto err_unlock;
+ return ret;
if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE ||
!static_cpu_has(X86_FEATURE_CLFLUSH)) {
@@ -680,7 +674,5 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
err_unpin:
i915_gem_object_unpin_pages(obj);
-err_unlock:
- i915_gem_object_unlock(obj);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 4ced8865d8eb..0d1d64bcd964 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1003,11 +1003,14 @@ static void reloc_cache_reset(struct reloc_cache *cache)
vaddr = unmask_page(cache->vaddr);
if (cache->vaddr & KMAP) {
+ struct drm_i915_gem_object *obj =
+ (struct drm_i915_gem_object *)cache->node.mm;
if (cache->vaddr & CLFLUSH_AFTER)
mb();
kunmap_atomic(vaddr);
- i915_gem_object_finish_access((struct drm_i915_gem_object
*)cache->node.mm);
+ i915_gem_object_finish_access(obj);
+ i915_gem_object_unlock(obj);
} else {
struct i915_ggtt *ggtt = cache_to_ggtt(cache);
@@ -1042,10 +1045,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj,
unsigned int flushes;
int err;
- err = i915_gem_object_prepare_write(obj, &flushes);
+ err = i915_gem_object_lock_interruptible(obj, NULL);
if (err)
return ERR_PTR(err);
+ err = i915_gem_object_prepare_write(obj, &flushes);
+ if (err) {
+ i915_gem_object_unlock(obj);
+ return ERR_PTR(err);
+ }
+
BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS);
BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 5103067269b0..11b8e27
[Intel-gfx] [PATCH 13/25] drm/i915: Pin engine before pinning all objects, v3.
We want to lock all gem objects, including the engine context objects,
rework the throttling to ensure that we can do this. Now we only throttle
once, but can take eb_pin_engine while acquiring objects. This means we
will have to drop the lock to wait. If we don't have to throttle we can
still take the fastpath, if not we will take the slowpath and wait for
the throttle request while unlocked.
The engine has to be pinned as first step, otherwise gpu relocations
won't work.
Changes since v1:
- Only need to get a throttled request in the fastpath, no need for
a global flag any more.
- Always free the waited request correctly.
Changes since v2:
- Use intel_engine_pm_get()/put() to keeep engine pool alive during
EDEADLK handling.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 183 --
1 file changed, 127 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ffe6853119bb..b3cc08f42fac 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -55,7 +55,8 @@ enum {
#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN |
__EXEC_OBJECT_HAS_FENCE)
#define __EXEC_HAS_RELOC BIT(31)
-#define __EXEC_INTERNAL_FLAGS (~0u << 31)
+#define __EXEC_ENGINE_PINNED BIT(30)
+#define __EXEC_INTERNAL_FLAGS (~0u << 30)
#define UPDATE PIN_OFFSET_FIXED
#define BATCH_OFFSET_BIAS (256*1024)
@@ -292,6 +293,9 @@ struct i915_execbuffer {
};
static int eb_parse(struct i915_execbuffer *eb);
+static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb,
+ bool throttle);
+static void eb_unpin_engine(struct i915_execbuffer *eb);
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
{
@@ -924,7 +928,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long
handle)
}
}
-static void eb_release_vmas(const struct i915_execbuffer *eb, bool final)
+static void eb_release_vmas(struct i915_execbuffer *eb, bool final)
{
const unsigned int count = eb->buffer_count;
unsigned int i;
@@ -941,6 +945,8 @@ static void eb_release_vmas(const struct i915_execbuffer
*eb, bool final)
if (final)
i915_vma_put(vma);
}
+
+ eb_unpin_engine(eb);
}
static void eb_destroy(const struct i915_execbuffer *eb)
@@ -1768,7 +1774,8 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
return 0;
}
-static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
+static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb,
+ struct i915_request *rq)
{
bool have_copy = false;
struct eb_vma *ev;
@@ -1784,6 +1791,21 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
eb_release_vmas(eb, false);
i915_gem_ww_ctx_fini(&eb->ww);
+ if (rq) {
+ /* nonblocking is always false */
+ if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT) < 0) {
+ i915_request_put(rq);
+ rq = NULL;
+
+ err = -EINTR;
+ goto err_relock;
+ }
+
+ i915_request_put(rq);
+ rq = NULL;
+ }
+
/*
* We take 3 passes through the slowpatch.
*
@@ -1807,14 +1829,25 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
err = 0;
}
- flush_workqueue(eb->i915->mm.userptr_wq);
+ if (!err)
+ flush_workqueue(eb->i915->mm.userptr_wq);
+err_relock:
i915_gem_ww_ctx_init(&eb->ww, true);
if (err)
goto out;
/* reacquire the objects */
repeat_validate:
+ rq = eb_pin_engine(eb, false);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err;
+ }
+
+ /* We didn't throttle, should be NULL */
+ GEM_WARN_ON(rq);
+
err = eb_validate_vmas(eb);
if (err)
goto err;
@@ -1878,14 +1911,47 @@ static noinline int eb_relocate_parse_slow(struct
i915_execbuffer *eb)
}
}
+ if (rq)
+ i915_request_put(rq);
+
return err;
}
static int eb_relocate_parse(struct i915_execbuffer *eb)
{
int err;
+ struct i915_request *rq = NULL;
+ bool throttle = true;
retry:
+ rq = eb_pin_engine(eb, throttle);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ rq = NULL;
+ if (err != -EDEADLK)
+ return err;
+
+ goto err;
+ }
+
+ if (rq) {
+ bool nonblock = eb->file->filp->f_flags & O_NONBLOCK;
+
+
[Intel-gfx] [PATCH 14/25] drm/i915: Rework intel_context pinning to do everything outside of pin_mutex
Instead of doing everything inside of pin_mutex, we move all pinning
outside. Because i915_active has its own reference counting and
pinning is also having the same issues vs mutexes, we make sure
everything is pinned first, so the pinning in i915_active only needs
to bump refcounts. This allows us to take pin refcounts correctly
all the time.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 232 +++---
drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 34 ++-
.../gpu/drm/i915/gt/intel_ring_submission.c | 13 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 13 +-
5 files changed, 190 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index e4aece20bc80..c039e87a46c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -93,79 +93,6 @@ static void intel_context_active_release(struct
intel_context *ce)
i915_active_release(&ce->active);
}
-int __intel_context_do_pin(struct intel_context *ce)
-{
- int err;
-
- if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) {
- err = intel_context_alloc_state(ce);
- if (err)
- return err;
- }
-
- err = i915_active_acquire(&ce->active);
- if (err)
- return err;
-
- if (mutex_lock_interruptible(&ce->pin_mutex)) {
- err = -EINTR;
- goto out_release;
- }
-
- if (unlikely(intel_context_is_closed(ce))) {
- err = -ENOENT;
- goto out_unlock;
- }
-
- if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) {
- err = intel_context_active_acquire(ce);
- if (unlikely(err))
- goto out_unlock;
-
- err = ce->ops->pin(ce);
- if (unlikely(err))
- goto err_active;
-
- CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n",
-i915_ggtt_offset(ce->ring->vma),
-ce->ring->head, ce->ring->tail);
-
- smp_mb__before_atomic(); /* flush pin before it is visible */
- atomic_inc(&ce->pin_count);
- }
-
- GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
- GEM_BUG_ON(i915_active_is_idle(&ce->active));
- goto out_unlock;
-
-err_active:
- intel_context_active_release(ce);
-out_unlock:
- mutex_unlock(&ce->pin_mutex);
-out_release:
- i915_active_release(&ce->active);
- return err;
-}
-
-void intel_context_unpin(struct intel_context *ce)
-{
- if (!atomic_dec_and_test(&ce->pin_count))
- return;
-
- CE_TRACE(ce, "unpin\n");
- ce->ops->unpin(ce);
-
- /*
-* Once released, we may asynchronously drop the active reference.
-* As that may be the only reference keeping the context alive,
-* take an extra now so that it is not freed before we finish
-* dereferencing it.
-*/
- intel_context_get(ce);
- intel_context_active_release(ce);
- intel_context_put(ce);
-}
-
static int __context_pin_state(struct i915_vma *vma)
{
unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS;
@@ -225,6 +152,138 @@ static void __ring_retire(struct intel_ring *ring)
i915_active_release(&ring->vma->active);
}
+static int intel_context_pre_pin(struct intel_context *ce)
+{
+ int err;
+
+ CE_TRACE(ce, "active\n");
+
+ err = __ring_active(ce->ring);
+ if (err)
+ return err;
+
+ err = intel_timeline_pin(ce->timeline);
+ if (err)
+ goto err_ring;
+
+ if (!ce->state)
+ return 0;
+
+ err = __context_pin_state(ce->state);
+ if (err)
+ goto err_timeline;
+
+
+ return 0;
+
+err_timeline:
+ intel_timeline_unpin(ce->timeline);
+err_ring:
+ __ring_retire(ce->ring);
+ return err;
+}
+
+static void intel_context_post_unpin(struct intel_context *ce)
+{
+ if (ce->state)
+ __context_unpin_state(ce->state);
+
+ intel_timeline_unpin(ce->timeline);
+ __ring_retire(ce->ring);
+}
+
+int __intel_context_do_pin(struct intel_context *ce)
+{
+ bool handoff = false;
+ void *vaddr;
+ int err = 0;
+
+ if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) {
+ err = intel_context_alloc_state(ce);
+ if (err)
+ return err;
+ }
+
+ /*
+* We always pin the context/ring/timeline here, to ensure a pin
+* refcount for __intel_context_active(), which prevent a lock
+* inversion of ce->pin_mutex vs dma_resv_lock().
+*/
+ err = intel_context_pre_pin(ce);
+ if (err)
+ return err;
+
+
[Intel-gfx] [PATCH 21/25] drm/i915: Use ww pinning for intel_context_create_request()
We want to get rid of intel_context_pin(), convert
intel_context_create_request() first. :)
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/gt/intel_context.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index fe9fff5a63b1..e148e2d69ae1 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -449,15 +449,25 @@ int intel_context_prepare_remote_request(struct
intel_context *ce,
struct i915_request *intel_context_create_request(struct intel_context *ce)
{
+ struct i915_gem_ww_ctx ww;
struct i915_request *rq;
int err;
- err = intel_context_pin(ce);
- if (unlikely(err))
- return ERR_PTR(err);
+ i915_gem_ww_ctx_init(&ww, true);
+retry:
+ err = intel_context_pin_ww(ce, &ww);
+ if (!err) {
+ rq = i915_request_create(ce);
+ intel_context_unpin(ce);
+ } else if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(&ww);
+ if (!err)
+ goto retry;
+ } else {
+ rq = ERR_PTR(err);
+ }
- rq = i915_request_create(ce);
- intel_context_unpin(ce);
+ i915_gem_ww_ctx_fini(&ww);
if (IS_ERR(rq))
return rq;
--
2.26.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/25] drm/i915: Parse command buffer earlier in eb_relocate(slow)
We want to introduce backoff logic, but we need to lock the
pool object as well for command parsing. Because of this, we
will need backoff logic for the engine pool obj, move the batch
validation up slightly to eb_lookup_vmas, and the actual command
parsing in a separate function which can get called from execbuf
relocation fast and slowpath.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 68 ++-
1 file changed, 37 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 0d1d64bcd964..057e0ba14b47 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -290,6 +290,8 @@ struct i915_execbuffer {
struct eb_vma_array *array;
};
+static int eb_parse(struct i915_execbuffer *eb);
+
static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb)
{
return intel_engine_requires_cmd_parser(eb->engine) ||
@@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct
i915_execbuffer *eb, u32 handle)
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
+ struct drm_i915_private *i915 = eb->i915;
unsigned int batch = eb_batch_index(eb);
unsigned int i;
int err = 0;
@@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
vma = eb_lookup_vma(eb, eb->exec[i].handle);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
- break;
+ goto err;
}
err = eb_validate_vma(eb, &eb->exec[i], vma);
if (unlikely(err)) {
i915_vma_put(vma);
- break;
+ goto err;
}
eb_add_vma(eb, i, batch, vma);
}
+ if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) {
+ drm_dbg(&i915->drm,
+ "Attempting to use self-modifying batch buffer\n");
+ return -EINVAL;
+ }
+
+ if (range_overflows_t(u64,
+ eb->batch_start_offset, eb->batch_len,
+ eb->batch->vma->size)) {
+ drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
+ return -EINVAL;
+ }
+
+ if (eb->batch_len == 0)
+ eb->batch_len = eb->batch->vma->size - eb->batch_start_offset;
+
+ return 0;
+
+err:
eb->vma[i].vma = NULL;
return err;
}
@@ -1737,7 +1759,7 @@ static int eb_prefault_relocations(const struct
i915_execbuffer *eb)
return 0;
}
-static noinline int eb_relocate_slow(struct i915_execbuffer *eb)
+static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb)
{
bool have_copy = false;
struct eb_vma *ev;
@@ -1788,6 +1810,11 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
}
}
+ /* as last step, parse the command buffer */
+ err = eb_parse(eb);
+ if (err)
+ goto err;
+
/*
* Leave the user relocations as are, this is the painfully slow path,
* and we want to avoid the complication of dropping the lock whilst
@@ -1820,7 +1847,7 @@ static noinline int eb_relocate_slow(struct
i915_execbuffer *eb)
return err;
}
-static int eb_relocate(struct i915_execbuffer *eb)
+static int eb_relocate_parse(struct i915_execbuffer *eb)
{
int err;
@@ -1840,11 +1867,11 @@ static int eb_relocate(struct i915_execbuffer *eb)
list_for_each_entry(ev, &eb->relocs, reloc_link) {
if (eb_relocate_vma(eb, ev))
- return eb_relocate_slow(eb);
+ return eb_relocate_parse_slow(eb);
}
}
- return 0;
+ return eb_parse(eb);
}
static int eb_move_to_gpu(struct i915_execbuffer *eb)
@@ -2775,7 +2802,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_context;
- err = eb_relocate(&eb);
+ err = eb_relocate_parse(&eb);
if (err) {
/*
* If the user expects the execobject.offset and
@@ -2788,33 +2815,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_vma;
}
- if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) {
- drm_dbg(&i915->drm,
- "Attempting to use self-modifying batch buffer\n");
- err = -EINVAL;
- goto err_vma;
- }
-
- if (range_overflows_t(u64,
- eb.batch_start_offset, eb.batch_len,
- eb.batch->vma->size)) {
- drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n");
- err = -EINVAL;
-
[Intel-gfx] [PATCH 15/25] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin.
As a preparation step for full object locking and wait/wound handling
during pin and object mapping, ensure that we always pass the ww context
in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this
happens.
This also requires changing the order of eb_parse slightly, to ensure
we pass ww at a point where we could still handle -EDEADLK safely.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 137 ++
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context.c | 65 ++---
drivers/gpu/drm/i915/gt/intel_context.h | 13 ++
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 10 +-
drivers/gpu/drm/i915/gt/intel_ring.h | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 15 +-
drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +-
drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c| 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
drivers/gpu/drm/i915/i915_drv.h | 13 +-
drivers/gpu/drm/i915/i915_gem.c | 11 +-
drivers/gpu/drm/i915/i915_vma.c | 13 +-
drivers/gpu/drm/i915/i915_vma.h | 13 +-
25 files changed, 214 insertions(+), 133 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 54047f8454ae..3e8580618dda 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3449,7 +3449,7 @@ initial_plane_vma(struct drm_i915_private *i915,
if (IS_ERR(vma))
goto err_obj;
- if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
+ if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
goto err_obj;
if (i915_gem_object_is_tiled(obj) &&
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c640f70f29f1..aaea0e51fd91 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1142,7 +1142,7 @@ static int context_barrier_task(struct i915_gem_context
*ctx,
i915_gem_ww_ctx_init(&ww, true);
retry:
- err = intel_context_pin(ce);
+ err = intel_context_pin_ww(ce, &ww);
if (err)
goto err;
@@ -1235,7 +1235,7 @@ static int pin_ppgtt_update(struct intel_context *ce,
struct i915_gem_ww_ctx *ww
if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915))
/* ppGTT is not part of the legacy context image */
- return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm));
+ return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index b3cc08f42fac..719a6668fc0a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -424,16 +424,17 @@ eb_pin_vma(struct i915_execbuffer *eb,
pin_flags |= PIN_GLOBAL;
/* Attempt to reuse the current location if available */
- if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) {
+ /* TODO: Add -EDEADLK handling here */
+ if (unlikely(i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags))) {
if (entry->flags & EXEC_OBJECT_PINNED)
return false;
/* Failing that pick any _free_ space if suitable */
- if (unlikely(i915_vma_pin(vma,
- entry->pad_to_size,
- entry->alignment,
- eb_pin_flags(entry, ev->flags) |
- PIN_USER | PIN_NOEVICT)))
+ if (unlikely(i915_vma_pin_ww(vma, &eb->ww,
+entry->pad_to_size,
+entry->alignment,
+eb_pin_flags(entry, ev->flags) |
+PIN_USER | PIN_NOEVICT)))
return false;
}
@@ -575,7 +576,7 @@ static inline int use_cpu_reloc(const struct reloc_cache
*cache,
obj->cache_level != I915_
[Intel-gfx] ✓ Fi.CI.IGT: success for linux-next: build failure after merge of the drm-misc tree
== Series Details ==
Series: linux-next: build failure after merge of the drm-misc tree
URL : https://patchwork.freedesktop.org/series/76709/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8390_full -> Patchwork_17505_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_17505_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@suspend:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1185])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb7/igt@gem_...@suspend.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-iclb3/igt@gem_...@suspend.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl1/igt@gem_workarou...@suspend-resume-fd.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-apl4/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_pm_rps@waitboost:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#39])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl10/igt@i915_pm_...@waitboost.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-skl7/igt@i915_pm_...@waitboost.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl2/igt@kms_cursor_...@pipe-a-cursor-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#177] / [i915#52] /
[i915#54])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-glk2/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-glk6/igt@kms_draw_...@draw-method-rgb565-pwrite-untiled.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-skl10/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
Possible fixes
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][17] ([i915#180]) -> [PASS][18] +4
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-kbl1/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][19] ([IGT#5] / [i915#697]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl9/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-skl5/igt@kms_cursor_leg...@flip-vs-cursor-atomic-transitions.html
* {igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2}:
- shard-glk: [FAIL][21] ([i915#79]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interrupti...@a-hdmi-a2.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +3
similar issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl8/igt@kms_flip@flip-vs-suspend-interrupti...@c-dp1.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17505/shard-apl3
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Update Slylake PCI IDs
== Series Details ==
Series: drm/i915: Update Slylake PCI IDs
URL : https://patchwork.freedesktop.org/series/76720/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17510
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17510/index.html
Known issues
Here are the changes found in Patchwork_17510 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-skl-guc: [INCOMPLETE][1] ([i915#151]) -> [PASS][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-guc/igt@i915_pm_...@module-reload.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17510/fi-skl-guc/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666
Participating hosts (48 -> 42)
--
Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u
fi-ctg-p8600 fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8391 -> Patchwork_17510
CI-20190529: 20190529
CI_DRM_8391: 9cada6f702d618458eb6dda220f5cfefe655f475 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17510: 9426c725b9440eff09861eeb0c86b969def98465 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9426c725b944 drm/i915: Update Slylake PCI IDs
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17510/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [patch] drm/i915: Update Slylake PCI IDs
Quoting Alexei Podtelezhnikov (2020-04-29 12:54:20) > On Wed, 29 Apr 2020, Ville Syrjälä wrote: > > On Tue, Apr 28, 2020 at 11:27:50PM -0400, Alexei Podtelezhnikov wrote: > >> Add three new devices 0x1513, 0x1515, and 0x1517 also known as > > > > typo 0x15 vs. 0x19 > > > >> iSKLULTGT15, iSKLULXGT15, and iSKLDTGT15. Reclassify 0x1923, 0x1927, > >> and 0x192A according to specifications. > > > > I'd make this three separate patches, just in case we have to revert > > some of these in the future. Most worried about the 0x192a case since > > the evidence is rather poor. > > I fixed the typo. And slyly hide another. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable copy of the default context state (rev3)
== Series Details == Series: series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable copy of the default context state (rev3) URL : https://patchwork.freedesktop.org/series/76719/ State : warning == Summary == $ dim checkpatch origin/drm-tip 26b4faff2de3 drm/i915/gt: Keep a no-frills swappable copy of the default context state -:291: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #291: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 438 lines checked 7bc58c8c0657 drm/i915/gt: Stop keeping the pinned_default_state ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [bug report] drm/i915/gt: Use the RPM config register to determine clk frequencies
Hello Chris Wilson,
The patch 9c878557b1eb: "drm/i915/gt: Use the RPM config register to
determine clk frequencies" from Apr 24, 2020, leads to the following
static checker warning:
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c:407 frequency_show()
error: uninitialized symbol 'rpcurupei'.
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
298 } else if (INTEL_GEN(i915) >= 6) {
299 u32 rp_state_limits;
300 u32 gt_perf_status;
301 u32 rp_state_cap;
302 u32 rpmodectl, rpinclimit, rpdeclimit;
303 u32 rpstat, cagf, reqf;
304 u32 rpcurupei, rpcurup, rpprevup;
^
305 u32 rpcurdownei, rpcurdown, rpprevdown;
306 u32 rpupei, rpupt, rpdownei, rpdownt;
307 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
308 int max_freq;
309
310 rp_state_limits = intel_uncore_read(uncore,
GEN6_RP_STATE_LIMITS);
311 if (IS_GEN9_LP(i915)) {
312 rp_state_cap = intel_uncore_read(uncore,
BXT_RP_STATE_CAP);
313 gt_perf_status = intel_uncore_read(uncore,
BXT_GT_PERF_STATUS);
314 } else {
315 rp_state_cap = intel_uncore_read(uncore,
GEN6_RP_STATE_CAP);
316 gt_perf_status = intel_uncore_read(uncore,
GEN6_GT_PERF_STATUS);
317 }
318
319 /* RPSTAT1 is in the GT power well */
320 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
321
322 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
323 if (INTEL_GEN(i915) >= 9) {
324 reqf >>= 23;
325 } else {
326 reqf &= ~GEN6_TURBO_DISABLE;
327 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
328 reqf >>= 24;
329 else
330 reqf >>= 25;
331 }
332 reqf = intel_gpu_freq(rps, reqf);
333
334 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
335 rpinclimit = intel_uncore_read(uncore,
GEN6_RP_UP_THRESHOLD);
336 rpdeclimit = intel_uncore_read(uncore,
GEN6_RP_DOWN_THRESHOLD);
337
338 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
339 rpupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) &
GEN6_CURICONT_MASK;
340 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) &
GEN6_CURBSYTAVG_MASK;
341 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) &
GEN6_CURBSYTAVG_MASK;
342 rpcurdownei = intel_uncore_read(uncore,
GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
343 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN)
& GEN6_CURBSYTAVG_MASK;
344 rpprevdown = intel_uncore_read(uncore,
GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
345
346 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
347 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
348
349 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
350 rpdownt = intel_uncore_read(uncore,
GEN6_RP_DOWN_THRESHOLD);
351
352 cagf = intel_rps_read_actual_frequency(rps);
353
354 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
355
356 if (INTEL_GEN(i915) >= 11) {
357 pm_ier = intel_uncore_read(uncore,
GEN11_GPM_WGBOXPERF_INTR_ENABLE);
358 pm_imr = intel_uncore_read(uncore,
GEN11_GPM_WGBOXPERF_INTR_MASK);
359 /*
360 * The equivalent to the PM ISR & IIR cannot be
read
361 * without affecting the current state of the
system
362 */
363 pm_isr = 0;
364 pm_iir = 0;
365 } else if (INTEL_GEN(i915) >= 8) {
366 pm_ier = intel_uncore_read(uncore,
GEN8_GT_IER(2));
367 pm_imr = intel_uncore_read(uncore,
GEN8_GT_IMR(2));
368 pm_isr = intel_uncore_read(uncore,
GEN8_GT_ISR(2));
369 pm_iir = intel_uncore_read(uncore,
GEN8_GT_IIR(2));
370 } else {
371 pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
372 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
373 pm_isr = intel_uncore_read(un
[Intel-gfx] [PATCH] drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb()
If intel_context_create() fails then it leads to an error pointer
dereference. I shuffled things around to make error handling easier.
Fixes: 1dd47b54baea ("drm/i915: Add live selftests for indirect ctx
batchbuffers")
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 30 +++---
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d3fa91aed7dee..c4bfad5c49dea 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -5795,26 +5795,29 @@ static int indirect_ctx_bb_check(struct intel_context
*ce)
static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
{
struct intel_context *a, *b;
- int err = 0;
+ int err;
a = intel_context_create(engine);
- b = intel_context_create(engine);
-
+ if (IS_ERR(a))
+ return PTR_ERR(a);
err = intel_context_pin(a);
if (err)
- return err;
+ goto put_a;
- err = intel_context_pin(b);
- if (err) {
- intel_context_put(a);
- return err;
+ b = intel_context_create(engine);
+ if (IS_ERR(b)) {
+ err = PTR_ERR(b);
+ goto unpin_a;
}
+ err = intel_context_pin(b);
+ if (err)
+ goto put_b;
/* We use the already reserved extra page in context state */
if (!a->wa_bb_page) {
GEM_BUG_ON(b->wa_bb_page);
GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
- goto out;
+ goto unpin_b;
}
/*
@@ -5829,14 +5832,17 @@ static int __live_lrc_indirect_ctx_bb(struct
intel_engine_cs *engine)
err = indirect_ctx_bb_check(a);
if (err)
- goto out;
+ goto unpin_b;
err = indirect_ctx_bb_check(b);
-out:
+
+unpin_b:
intel_context_unpin(b);
+put_b:
intel_context_put(b);
-
+unpin_a:
intel_context_unpin(a);
+put_a:
intel_context_put(a);
return err;
--
2.26.2
___
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Re: [Intel-gfx] [bug report] drm/i915/gt: Use the RPM config register to determine clk frequencies
Quoting Dan Carpenter (2020-04-29 14:23:45)
> Hello Chris Wilson,
>
> The patch 9c878557b1eb: "drm/i915/gt: Use the RPM config register to
> determine clk frequencies" from Apr 24, 2020, leads to the following
> static checker warning:
>
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c:407 frequency_show()
> error: uninitialized symbol 'rpcurupei'.
>
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>298 } else if (INTEL_GEN(i915) >= 6) {
>299 u32 rp_state_limits;
>300 u32 gt_perf_status;
>301 u32 rp_state_cap;
>302 u32 rpmodectl, rpinclimit, rpdeclimit;
>303 u32 rpstat, cagf, reqf;
>304 u32 rpcurupei, rpcurup, rpprevup;
> ^
>
>305 u32 rpcurdownei, rpcurdown, rpprevdown;
>306 u32 rpupei, rpupt, rpdownei, rpdownt;
>307 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
>308 int max_freq;
>309
>310 rp_state_limits = intel_uncore_read(uncore,
> GEN6_RP_STATE_LIMITS);
>311 if (IS_GEN9_LP(i915)) {
>312 rp_state_cap = intel_uncore_read(uncore,
> BXT_RP_STATE_CAP);
>313 gt_perf_status = intel_uncore_read(uncore,
> BXT_GT_PERF_STATUS);
>314 } else {
>315 rp_state_cap = intel_uncore_read(uncore,
> GEN6_RP_STATE_CAP);
>316 gt_perf_status = intel_uncore_read(uncore,
> GEN6_GT_PERF_STATUS);
>317 }
>318
>319 /* RPSTAT1 is in the GT power well */
>320 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>321
>322 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
>323 if (INTEL_GEN(i915) >= 9) {
>324 reqf >>= 23;
>325 } else {
>326 reqf &= ~GEN6_TURBO_DISABLE;
>327 if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>328 reqf >>= 24;
>329 else
>330 reqf >>= 25;
>331 }
>332 reqf = intel_gpu_freq(rps, reqf);
>333
>334 rpmodectl = intel_uncore_read(uncore,
> GEN6_RP_CONTROL);
>335 rpinclimit = intel_uncore_read(uncore,
> GEN6_RP_UP_THRESHOLD);
>336 rpdeclimit = intel_uncore_read(uncore,
> GEN6_RP_DOWN_THRESHOLD);
>337
>338 rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
>339 rpupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI)
> & GEN6_CURICONT_MASK;
>340 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) &
> GEN6_CURBSYTAVG_MASK;
>341 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP)
> & GEN6_CURBSYTAVG_MASK;
>342 rpcurdownei = intel_uncore_read(uncore,
> GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
>343 rpcurdown = intel_uncore_read(uncore,
> GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
>344 rpprevdown = intel_uncore_read(uncore,
> GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
>345
>346 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
>347 rpupt = intel_uncore_read(uncore,
> GEN6_RP_UP_THRESHOLD);
>348
>349 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
>350 rpdownt = intel_uncore_read(uncore,
> GEN6_RP_DOWN_THRESHOLD);
>351
>352 cagf = intel_rps_read_actual_frequency(rps);
>353
>354 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>355
>356 if (INTEL_GEN(i915) >= 11) {
>357 pm_ier = intel_uncore_read(uncore,
> GEN11_GPM_WGBOXPERF_INTR_ENABLE);
>358 pm_imr = intel_uncore_read(uncore,
> GEN11_GPM_WGBOXPERF_INTR_MASK);
>359 /*
>360 * The equivalent to the PM ISR & IIR cannot
> be read
>361 * without affecting the current state of the
> system
>362 */
>363 pm_isr = 0;
>364 pm_iir = 0;
>365 } else if (INTEL_GEN(i915) >= 8) {
>366 pm_ier = intel_uncore_read(uncore,
> GEN8_GT_IER(2));
>367 pm_imr = intel_uncore_read(uncore,
> GEN8_GT_IMR(2));
>368 pm_isr = intel_uncore_read(uncore,
> GEN8_GT_ISR(2));
>369 pm_iir = intel_uncore_read(uncore,
> GEN8_GT_I
Re: [Intel-gfx] [PATCH] drm/i915: Avoid dereferencing a dead context
On 28/04/2020 10:02, Chris Wilson wrote:
Once the intel_context is closed, the GEM context may be freed and so
the link from intel_context.gem_context is invalid.
<3>[ 219.782944] BUG: KASAN: use-after-free in
intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<3>[ 219.782996] Read of size 8 at addr 8881d7dff0b8 by task kworker/0:1/12
<4>[ 219.783052] CPU: 0 PID: 12 Comm: kworker/0:1 Tainted: G U
5.7.0-rc2-g1f3ffd7683d54-kasan_118+ #1
<4>[ 219.783055] Hardware name: System manufacturer System Product Name/Z170
PRO GAMING, BIOS 3402 04/26/2017
<4>[ 219.783105] Workqueue: events heartbeat [i915]
<4>[ 219.783109] Call Trace:
<4>[ 219.783113]
<4>[ 219.783119] dump_stack+0x96/0xdb
<4>[ 219.783177] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<4>[ 219.783182] print_address_description.constprop.6+0x16/0x310
<4>[ 219.783239] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<4>[ 219.783295] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<4>[ 219.783300] __kasan_report+0x137/0x190
<4>[ 219.783359] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<4>[ 219.783366] kasan_report+0x32/0x50
<4>[ 219.783426] intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
<4>[ 219.783481] execlists_reset+0x39c/0x13d0 [i915]
<4>[ 219.783494] ? mark_held_locks+0x9e/0xe0
<4>[ 219.783546] ? execlists_hold+0xfc0/0xfc0 [i915]
<4>[ 219.783551] ? lockdep_hardirqs_on+0x348/0x5f0
<4>[ 219.783557] ? _raw_spin_unlock_irqrestore+0x34/0x60
<4>[ 219.783606] ? execlists_submission_tasklet+0x118/0x3a0 [i915]
<4>[ 219.783615] tasklet_action_common.isra.14+0x13b/0x410
<4>[ 219.783623] ? __do_softirq+0x1e4/0x9a7
<4>[ 219.783630] __do_softirq+0x226/0x9a7
<4>[ 219.783643] do_softirq_own_stack+0x2a/0x40
<4>[ 219.783647]
<4>[ 219.783692] ? heartbeat+0x3e2/0x10f0 [i915]
<4>[ 219.783696] do_softirq.part.13+0x49/0x50
<4>[ 219.783700] __local_bh_enable_ip+0x1a2/0x1e0
<4>[ 219.783748] heartbeat+0x409/0x10f0 [i915]
<4>[ 219.783801] ? __live_idle_pulse+0x9f0/0x9f0 [i915]
<4>[ 219.783806] ? lock_acquire+0x1ac/0x8a0
<4>[ 219.783811] ? process_one_work+0x811/0x1870
<4>[ 219.783827] ? rcu_read_lock_sched_held+0x9c/0xd0
<4>[ 219.783832] ? rcu_read_lock_bh_held+0xb0/0xb0
<4>[ 219.783836] ? _raw_spin_unlock_irq+0x1f/0x40
<4>[ 219.783845] process_one_work+0x8ca/0x1870
<4>[ 219.783848] ? lock_acquire+0x1ac/0x8a0
<4>[ 219.783852] ? worker_thread+0x1d0/0xb80
<4>[ 219.783864] ? pwq_dec_nr_in_flight+0x2c0/0x2c0
<4>[ 219.783870] ? do_raw_spin_lock+0x129/0x290
<4>[ 219.783886] worker_thread+0x82/0xb80
<4>[ 219.783895] ? __kthread_parkme+0xaf/0x1b0
<4>[ 219.783902] ? process_one_work+0x1870/0x1870
<4>[ 219.783906] kthread+0x34e/0x420
<4>[ 219.783911] ? kthread_create_on_node+0xc0/0xc0
<4>[ 219.783918] ret_from_fork+0x3a/0x50
<3>[ 219.783950] Allocated by task 1264:
<4>[ 219.783975] save_stack+0x19/0x40
<4>[ 219.783978] __kasan_kmalloc.constprop.3+0xa0/0xd0
<4>[ 219.784029] i915_gem_create_context+0xa2/0xab8 [i915]
<4>[ 219.784081] i915_gem_context_create_ioctl+0x1fa/0x450 [i915]
<4>[ 219.784085] drm_ioctl_kernel+0x1d8/0x270
<4>[ 219.784088] drm_ioctl+0x676/0x930
<4>[ 219.784092] ksys_ioctl+0xb7/0xe0
<4>[ 219.784096] __x64_sys_ioctl+0x6a/0xb0
<4>[ 219.784100] do_syscall_64+0x94/0x530
<4>[ 219.784103] entry_SYSCALL_64_after_hwframe+0x49/0xb3
<3>[ 219.784120] Freed by task 12:
<4>[ 219.784141] save_stack+0x19/0x40
<4>[ 219.784145] __kasan_slab_free+0x130/0x180
<4>[ 219.784148] kmem_cache_free_bulk+0x1bd/0x500
<4>[ 219.784152] kfree_rcu_work+0x1d8/0x890
<4>[ 219.784155] process_one_work+0x8ca/0x1870
<4>[ 219.784158] worker_thread+0x82/0xb80
<4>[ 219.784162] kthread+0x34e/0x420
<4>[ 219.784165] ret_from_fork+0x3a/0x50
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4d54dba35302..a976cd67b3b3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1207,8 +1207,6 @@ static void engine_record_registers(struct
intel_engine_coredump *ee)
static void record_request(const struct i915_request *request,
struct i915_request_coredump *erq)
{
- const struct i915_gem_context *ctx;
-
erq->flags = request->fence.flags;
erq->context = request->fence.context;
erq->seqno = request->fence.seqno;
@@ -1218,9 +1216,13 @@ static void record_request(const struct i915_request
*request,
erq->pid = 0;
rcu_read_lock();
- ctx = rcu_dereference(request->context->gem_context);
- if (ctx)
- erq->pid = pid_nr(ctx->pid);
+ if (!intel_context_is_closed(request->context)) {
+ const struct i915_gem_context *ctx;
+
+ ctx = rcu_dereference(request->context->gem_context);
+ if (
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: FBC fixes
== Series Details == Series: drm/i915: FBC fixes URL : https://patchwork.freedesktop.org/series/76714/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8390_full -> Patchwork_17507_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17507_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17507_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17507_full: ### IGT changes ### Possible regressions * igt@kms_big_fb@y-tiled-32bpp-rotate-270: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-tglb1/igt@kms_big...@y-tiled-32bpp-rotate-270.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-tglb6/igt@kms_big...@y-tiled-32bpp-rotate-270.html - shard-iclb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb6/igt@kms_big...@y-tiled-32bpp-rotate-270.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-iclb5/igt@kms_big...@y-tiled-32bpp-rotate-270.html * igt@kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-kbl: [PASS][5] -> [INCOMPLETE][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl7/igt@kms_plane_scal...@pipe-a-scaler-with-rotation.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-kbl3/igt@kms_plane_scal...@pipe-a-scaler-with-rotation.html - shard-apl: [PASS][7] -> [INCOMPLETE][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl1/igt@kms_plane_scal...@pipe-a-scaler-with-rotation.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-apl4/igt@kms_plane_scal...@pipe-a-scaler-with-rotation.html * igt@runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][9], [FAIL][10]) ([i915#1611] / [i915#602]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-kbl3/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-kbl4/igt@run...@aborted.html - shard-iclb: NOTRUN -> ([FAIL][11], [FAIL][12]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-iclb5/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-iclb2/igt@run...@aborted.html - shard-tglb: NOTRUN -> ([FAIL][13], [FAIL][14]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-tglb6/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-tglb6/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_17507_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1528]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#716]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl10/igt@gen9_exec_pa...@allowed-single.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-skl1/igt@gen9_exec_pa...@allowed-single.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][19] -> [FAIL][20] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb3/igt@i915_pm...@dc6-psr.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rps@waitboost: - shard-apl: [PASS][21] -> [FAIL][22] ([i915#39]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl1/igt@i915_pm_...@waitboost.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-apl4/igt@i915_pm_...@waitboost.html * igt@i915_suspend@sysfs-reader: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl4/igt@i915_susp...@sysfs-reader.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17507/shard-apl7/igt@i915_susp...@sysfs-reader.html * igt@kms_big_fb@y-tiled-32bpp-rotate-270: - shard-glk: [PASS][25] -> [INC
[Intel-gfx] [PATCH] drm/i915/hdcp: Fix the return handling of drm_hdcp_check_ksvs_revoked
drm_hdcp_check_ksvs_revoked() returns the number of revoked keys and
error codes when the SRM parsing is failed.
Errors in SRM parsing can't affect the HDCP auth, hence with this patch,
I915 will look out for revoked key count alone.
Signed-off-by: Ramalingam C
cc: Sean Paul
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2cbc4619b4ce..96bf6def9830 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -576,7 +576,7 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
goto err;
if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo,
- num_downstream)) {
+ num_downstream) > 0) {
drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
ret = -EPERM;
goto err;
@@ -682,7 +682,7 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (ret < 0)
return ret;
- if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1)) {
+ if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1) > 0) {
drm_err(&dev_priv->drm, "BKSV is revoked\n");
return -EPERM;
}
@@ -1283,7 +1283,7 @@ static int hdcp2_authentication_key_exchange(struct
intel_connector *connector)
if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
msgs.send_cert.cert_rx.receiver_id,
- 1)) {
+ 1) > 0) {
drm_err(&dev_priv->drm, "Receiver ID is revoked\n");
return -EPERM;
}
@@ -1484,7 +1484,7 @@ int hdcp2_authenticate_repeater_topology(struct
intel_connector *connector)
HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
msgs.recvid_list.receiver_ids,
- device_cnt)) {
+ device_cnt) > 0) {
drm_err(&dev_priv->drm, "Revoked receiver ID(s) is in list\n");
return -EPERM;
}
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable copy of the default context state (rev3)
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable
copy of the default context state (rev3)
URL : https://patchwork.freedesktop.org/series/76719/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17511
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_17511 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17511, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_17511:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-u2/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-u2/igt@i915_selftest@l...@execlists.html
- fi-tgl-y: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-tgl-y/igt@i915_selftest@l...@execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-tgl-y/igt@i915_selftest@l...@execlists.html
- fi-icl-y: [PASS][5] -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-y/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-y/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- fi-cml-u2: [PASS][7] -> [INCOMPLETE][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cml-u2/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-cml-u2/igt@i915_selftest@l...@hangcheck.html
- fi-icl-guc: [PASS][9] -> [INCOMPLETE][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html
- fi-cfl-8700k: [PASS][11] -> [INCOMPLETE][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cfl-8700k/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-cfl-8700k/igt@i915_selftest@l...@hangcheck.html
- fi-whl-u: [PASS][13] -> [INCOMPLETE][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-whl-u/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-whl-u/igt@i915_selftest@l...@hangcheck.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-tgl-u}: [PASS][15] -> [INCOMPLETE][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-tgl-u/igt@i915_selftest@l...@execlists.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-tgl-u/igt@i915_selftest@l...@execlists.html
- {fi-tgl-dsi}: [PASS][17] -> [INCOMPLETE][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-tgl-dsi/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-1}: [PASS][19] -> [INCOMPLETE][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-ehl-1/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-ehl-1/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_17511 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-skl-6700k2: [PASS][21] -> [INCOMPLETE][22] ([fdo#108744])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-6700k2/igt@i915_selftest@l...@hangcheck.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-skl-6700k2/igt@i915_selftest@l...@hangcheck.html
- fi-skl-6600u: [PASS][23] -> [INCOMPLETE][24] ([fdo#108744])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html
- fi-cfl-8109u: [PASS][25] -> [INCOMPLETE][26] ([fdo#106070])
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_
Re: [Intel-gfx] [PATCH v2] drm: Fix HDCP failures when SRM fw is missing
On 2020-04-14 at 15:02:55 -0400, Sean Paul wrote:
> From: Sean Paul
>
> The SRM cleanup in 79643fddd6eb2 ("drm/hdcp: optimizing the srm
> handling") inadvertently altered the behavior of HDCP auth when
> the SRM firmware is missing. Before that patch, missing SRM was
> interpreted as the device having no revoked keys. With that patch,
> if the SRM fw file is missing we reject _all_ keys.
>
> This patch fixes that regression by returning success if the file
> cannot be found. It also checks the return value from request_srm such
> that we won't end up trying to parse the ksv list if there is an error
> fetching it.
>
> Fixes: 79643fddd6eb ("drm/hdcp: optimizing the srm handling")
> Cc: sta...@vger.kernel.org
> Cc: Ramalingam C
> Cc: Sean Paul
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Thomas Zimmermann
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: dri-de...@lists.freedesktop.org
> Signed-off-by: Sean Paul
>
> Changes in v2:
> -Noticed a couple other things to clean up
> ---
>
> Sorry for the quick rev, noticed a couple other loose ends that should
> be cleaned up.
>
> drivers/gpu/drm/drm_hdcp.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> index 7f386adcf872..910108ccaae1 100644
> --- a/drivers/gpu/drm/drm_hdcp.c
> +++ b/drivers/gpu/drm/drm_hdcp.c
> @@ -241,8 +241,12 @@ static int drm_hdcp_request_srm(struct drm_device
> *drm_dev,
>
> ret = request_firmware_direct(&fw, (const char *)fw_name,
> drm_dev->dev);
> - if (ret < 0)
> + if (ret < 0) {
> + *revoked_ksv_cnt = 0;
> + *revoked_ksv_list = NULL;
These two variables are already initialized by the caller.
> + ret = 0;
Missing of this should have been caught by CI. May be CI system always
having the SRM file from previous execution. Never been removed. IGT
need a fix to clean the prior SRM files before execution.
CI fix shouldn't block this fix.
> goto exit;
> + }
>
> if (fw->size && fw->data)
> ret = drm_hdcp_srm_update(fw->data, fw->size, revoked_ksv_list,
> @@ -287,6 +291,8 @@ int drm_hdcp_check_ksvs_revoked(struct drm_device
> *drm_dev, u8 *ksvs,
>
> ret = drm_hdcp_request_srm(drm_dev, &revoked_ksv_list,
> &revoked_ksv_cnt);
> + if (ret)
> + return ret;
This error code also shouldn't effect the caller(i915) hence pushed a
change https://patchwork.freedesktop.org/series/76730/
With these addresed.
LGTM.
Reviewed-by: Ramalingam C
>
> /* revoked_ksv_cnt will be zero when above function failed */
> for (i = 0; i < revoked_ksv_cnt; i++)
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable copy of the default context state (rev3)
Quoting Patchwork (2020-04-29 14:46:49) > == Series Details == > > Series: series starting with [CI,1/2] drm/i915/gt: Keep a no-frills swappable > copy of the default context state (rev3) > URL : https://patchwork.freedesktop.org/series/76719/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17511 > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17511 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17511, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/index.html > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_17511: > > ### IGT changes ### > > Possible regressions > > * igt@i915_selftest@live@execlists: > - fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-u2/igt@i915_selftest@l...@execlists.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-u2/igt@i915_selftest@l...@execlists.html > - fi-tgl-y: [PASS][3] -> [INCOMPLETE][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-tgl-y/igt@i915_selftest@l...@execlists.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-tgl-y/igt@i915_selftest@l...@execlists.html > - fi-icl-y: [PASS][5] -> [INCOMPLETE][6] >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-y/igt@i915_selftest@l...@execlists.html >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-y/igt@i915_selftest@l...@execlists.html > > * igt@i915_selftest@live@hangcheck: > - fi-cml-u2: [PASS][7] -> [INCOMPLETE][8] >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cml-u2/igt@i915_selftest@l...@hangcheck.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-cml-u2/igt@i915_selftest@l...@hangcheck.html > - fi-icl-guc: [PASS][9] -> [INCOMPLETE][10] >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-icl-guc/igt@i915_selftest@l...@hangcheck.html > - fi-cfl-8700k: [PASS][11] -> [INCOMPLETE][12] >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cfl-8700k/igt@i915_selftest@l...@hangcheck.html >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-cfl-8700k/igt@i915_selftest@l...@hangcheck.html > - fi-whl-u: [PASS][13] -> [INCOMPLETE][14] >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-whl-u/igt@i915_selftest@l...@hangcheck.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17511/fi-whl-u/igt@i915_selftest@l...@hangcheck.html I hope this means that our minimal context is not adequate as a replacement for a hung context and that we need to scrub some more. I did run locally first, so I presume that it's dependent on whatever random residual state we have in the context. Hmm. Or it's the trailing memset in the setup... -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb()
Quoting Dan Carpenter (2020-04-29 14:24:25)
> If intel_context_create() fails then it leads to an error pointer
> dereference. I shuffled things around to make error handling easier.
>
> Fixes: 1dd47b54baea ("drm/i915: Add live selftests for indirect ctx
> batchbuffers")
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 30 +++---
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index d3fa91aed7dee..c4bfad5c49dea 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -5795,26 +5795,29 @@ static int indirect_ctx_bb_check(struct intel_context
> *ce)
> static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> {
> struct intel_context *a, *b;
> - int err = 0;
> + int err;
>
> a = intel_context_create(engine);
> - b = intel_context_create(engine);
> -
> + if (IS_ERR(a))
> + return PTR_ERR(a);
> err = intel_context_pin(a);
> if (err)
> - return err;
> + goto put_a;
>
> - err = intel_context_pin(b);
> - if (err) {
> - intel_context_put(a);
> - return err;
> + b = intel_context_create(engine);
> + if (IS_ERR(b)) {
> + err = PTR_ERR(b);
> + goto unpin_a;
> }
> + err = intel_context_pin(b);
> + if (err)
> + goto put_b;
>
> /* We use the already reserved extra page in context state */
> if (!a->wa_bb_page) {
> GEM_BUG_ON(b->wa_bb_page);
> GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
> - goto out;
> + goto unpin_b;
> }
>
> /*
> @@ -5829,14 +5832,17 @@ static int __live_lrc_indirect_ctx_bb(struct
> intel_engine_cs *engine)
>
> err = indirect_ctx_bb_check(a);
> if (err)
> - goto out;
> + goto unpin_b;
>
> err = indirect_ctx_bb_check(b);
> -out:
> +
> +unpin_b:
> intel_context_unpin(b);
> +put_b:
> intel_context_put(b);
> -
> +unpin_a:
> intel_context_unpin(a);
> +put_a:
> intel_context_put(a);
Onion looks correct, and there should not be any issue with this
sequence of create/pin.
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow some leniency in PCU reads
== Series Details == Series: drm/i915: Allow some leniency in PCU reads URL : https://patchwork.freedesktop.org/series/76723/ State : success == Summary == CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17512 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17512/index.html Known issues Here are the changes found in Patchwork_17512 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@gt_contexts: - fi-bwr-2160:[PASS][1] -> [INCOMPLETE][2] ([i915#1726] / [i915#489]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17512/fi-bwr-2160/igt@i915_selftest@live@gt_contexts.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][3] ([i915#151]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-guc/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17512/fi-skl-guc/igt@i915_pm_...@module-reload.html [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1726]: https://gitlab.freedesktop.org/drm/intel/issues/1726 [i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489 Participating hosts (48 -> 42) -- Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8391 -> Patchwork_17512 CI-20190529: 20190529 CI_DRM_8391: 9cada6f702d618458eb6dda220f5cfefe655f475 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17512: 9c8b281eb20bc47534d6d123d8252d15a461beb0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9c8b281eb20b drm/i915: Allow some leniency in PCU reads == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17512/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm: Fix HDCP failures when SRM fw is missing
On Wed, Apr 29, 2020 at 9:50 AM Ramalingam C wrote:
>
> On 2020-04-14 at 15:02:55 -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > The SRM cleanup in 79643fddd6eb2 ("drm/hdcp: optimizing the srm
> > handling") inadvertently altered the behavior of HDCP auth when
> > the SRM firmware is missing. Before that patch, missing SRM was
> > interpreted as the device having no revoked keys. With that patch,
> > if the SRM fw file is missing we reject _all_ keys.
> >
> > This patch fixes that regression by returning success if the file
> > cannot be found. It also checks the return value from request_srm such
> > that we won't end up trying to parse the ksv list if there is an error
> > fetching it.
> >
> > Fixes: 79643fddd6eb ("drm/hdcp: optimizing the srm handling")
> > Cc: sta...@vger.kernel.org
> > Cc: Ramalingam C
> > Cc: Sean Paul
> > Cc: Maarten Lankhorst
> > Cc: Maxime Ripard
> > Cc: Thomas Zimmermann
> > Cc: David Airlie
> > Cc: Daniel Vetter
> > Cc: dri-de...@lists.freedesktop.org
> > Signed-off-by: Sean Paul
> >
> > Changes in v2:
> > -Noticed a couple other things to clean up
> > ---
> >
> > Sorry for the quick rev, noticed a couple other loose ends that should
> > be cleaned up.
> >
> > drivers/gpu/drm/drm_hdcp.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> > index 7f386adcf872..910108ccaae1 100644
> > --- a/drivers/gpu/drm/drm_hdcp.c
> > +++ b/drivers/gpu/drm/drm_hdcp.c
> > @@ -241,8 +241,12 @@ static int drm_hdcp_request_srm(struct drm_device
> > *drm_dev,
> >
> > ret = request_firmware_direct(&fw, (const char *)fw_name,
> > drm_dev->dev);
> > - if (ret < 0)
> > + if (ret < 0) {
> > + *revoked_ksv_cnt = 0;
> > + *revoked_ksv_list = NULL;
> These two variables are already initialized by the caller.
Right now it is, but that's not guaranteed. In the ret == 0 case, it's
pretty common for a caller to assume the called function has
validated/assigned all the function output.
> > + ret = 0;
> Missing of this should have been caught by CI. May be CI system always
> having the SRM file from previous execution. Never been removed. IGT
> need a fix to clean the prior SRM files before execution.
>
> CI fix shouldn't block this fix.
> > goto exit;
> > + }
> >
> > if (fw->size && fw->data)
> > ret = drm_hdcp_srm_update(fw->data, fw->size,
> > revoked_ksv_list,
> > @@ -287,6 +291,8 @@ int drm_hdcp_check_ksvs_revoked(struct drm_device
> > *drm_dev, u8 *ksvs,
> >
> > ret = drm_hdcp_request_srm(drm_dev, &revoked_ksv_list,
> > &revoked_ksv_cnt);
> > + if (ret)
> > + return ret;
> This error code also shouldn't effect the caller(i915)
Why not? I'd assume an invalid SRM revocation list should probably be
treated as failure?
> hence pushed a
> change https://patchwork.freedesktop.org/series/76730/
>
> With these addresed.
>
> LGTM.
>
> Reviewed-by: Ramalingam C
> >
> > /* revoked_ksv_cnt will be zero when above function failed */
> > for (i = 0; i < revoked_ksv_cnt; i++)
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/25] perf/core: Only copy-to-user after completely unlocking all locks, v3.
== Series Details ==
Series: series starting with [01/25] perf/core: Only copy-to-user after
completely unlocking all locks, v3.
URL : https://patchwork.freedesktop.org/series/76724/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
fafe194bca56 perf/core: Only copy-to-user after completely unlocking all locks,
v3.
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#17:
<4> [604.892540] 8264a558 (rcu_state.barrier_mutex){+.+.}, at:
rcu_barrier+0x23/0x190
-:106: WARNING:BAD_SIGN_OFF: Duplicate signature
#106:
Signed-off-by: Maarten Lankhorst
-:180: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#180: FILE: kernel/events/core.c:5174:
+__perf_read(struct perf_event *event, char __user *buf,
+ size_t count, u64 *values)
total: 0 errors, 2 warnings, 1 checks, 106 lines checked
03f36ece8c46 drm/i915/gt: Move the batch buffer pool from the engine to the gt
-:293: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#293:
deleted file mode 100644
-:607: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#607: FILE: drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h:1:
+/*
-:608: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#608: FILE: drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 3 warnings, 0 checks, 583 lines checked
ceef52523e21 Revert "drm/i915/gem: Drop relocation slowpath"
-:78: WARNING:LINE_SPACING: Missing a blank line after declarations
#78: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1628:
+ int err = __get_user(c, addr);
+ if (err)
total: 0 errors, 1 warnings, 0 checks, 257 lines checked
85895bb7e825 drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2.
-:506: WARNING:LONG_LINE: line over 100 characters
#506: FILE: drivers/gpu/drm/i915/i915_gem.c:1341:
+ while ((obj = list_first_entry_or_null(&ww->obj_list, struct
drm_i915_gem_object, obj_link))) {
total: 0 errors, 1 warnings, 0 checks, 481 lines checked
e4210d8c394b drm/i915: Remove locking from i915_gem_object_prepare_read/write
85aa13998baf drm/i915: Parse command buffer earlier in eb_relocate(slow)
bb53e9b6c6ca Revert "drm/i915/gem: Split eb_vma into its own allocation"
9a58917dabff drm/i915/gem: Make eb_add_lut interruptible wait on object lock.
2d8552c85070 drm/i915: Use per object locking in execbuf, v9.
-:703: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#703: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2761:
+ eb.reloc_pool = eb.batch_pool = NULL;
total: 0 errors, 0 warnings, 1 checks, 708 lines checked
42110a27a8ba drm/i915: Use ww locking in intel_renderstate.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Convert to using ww-waiting, and make sure we always pin intel_context_state,
total: 0 errors, 1 warnings, 0 checks, 207 lines checked
e116e8f69bb5 drm/i915: Add ww context handling to context_barrier_task
-:19: WARNING:LONG_LINE: line over 100 characters
#19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1097:
+ int (*pin)(struct intel_context *ce, struct
i915_gem_ww_ctx *ww, void *data),
total: 0 errors, 1 warnings, 0 checks, 146 lines checked
478459be927d drm/i915: Nuke arguments to eb_pin_engine
c462f8c0ca20 drm/i915: Pin engine before pinning all objects, v3.
5441a38d2e03 drm/i915: Rework intel_context pinning to do everything outside of
pin_mutex
-:125: CHECK:LINE_SPACING: Please don't use multiple blank lines
#125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176:
+
+
-:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#338: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3464:
+ *vaddr = i915_gem_object_pin_map(ce->state->obj,
+
i915_coherent_map_type(ce->engine->i915) |
total: 0 errors, 0 warnings, 2 checks, 435 lines checked
6c6ce377212c drm/i915: Make sure execbuffer always passes ww state to
i915_vma_pin.
-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:595:
+ err = i915_vma_pin_ww(vma, &eb->ww,
entry->pad_to_size, entry->alignment,
-:203: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a
separate line
#203: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2250:
+* hsw should have this fixed, but bdw mucks it up again. */
total: 0 errors, 1 warnings, 1 checks, 841 lines checked
258c3c07c168 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking
as well, v2.
76e03bb2d8db drm/i915: Kill last user of intel_context_create_request outside
of selftests
2bfb06126755 drm/i915: Convert i915_perf to ww locking as we
Re: [Intel-gfx] [PATCH] drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb()
Hi Dan,
On Wed, Apr 29, 2020 at 04:24:25PM +0300, Dan Carpenter wrote:
> If intel_context_create() fails then it leads to an error pointer
> dereference. I shuffled things around to make error handling easier.
>
> Fixes: 1dd47b54baea ("drm/i915: Add live selftests for indirect ctx
> batchbuffers")
> Signed-off-by: Dan Carpenter
Reviewed-by: Andi Shyti
Thanks,
Andi
___
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Re: [Intel-gfx] [PATCH] drm/i915: Avoid dereferencing a dead context
Quoting Tvrtko Ursulin (2020-04-29 14:42:44)
>
> On 28/04/2020 10:02, Chris Wilson wrote:
> > Once the intel_context is closed, the GEM context may be freed and so
> > the link from intel_context.gem_context is invalid.
> >
> > <3>[ 219.782944] BUG: KASAN: use-after-free in
> > intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <3>[ 219.782996] Read of size 8 at addr 8881d7dff0b8 by task
> > kworker/0:1/12
> >
> > <4>[ 219.783052] CPU: 0 PID: 12 Comm: kworker/0:1 Tainted: G U
> >5.7.0-rc2-g1f3ffd7683d54-kasan_118+ #1
> > <4>[ 219.783055] Hardware name: System manufacturer System Product
> > Name/Z170 PRO GAMING, BIOS 3402 04/26/2017
> > <4>[ 219.783105] Workqueue: events heartbeat [i915]
> > <4>[ 219.783109] Call Trace:
> > <4>[ 219.783113]
> > <4>[ 219.783119] dump_stack+0x96/0xdb
> > <4>[ 219.783177] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <4>[ 219.783182] print_address_description.constprop.6+0x16/0x310
> > <4>[ 219.783239] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <4>[ 219.783295] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <4>[ 219.783300] __kasan_report+0x137/0x190
> > <4>[ 219.783359] ? intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <4>[ 219.783366] kasan_report+0x32/0x50
> > <4>[ 219.783426] intel_engine_coredump_alloc+0x1bc3/0x2250 [i915]
> > <4>[ 219.783481] execlists_reset+0x39c/0x13d0 [i915]
> > <4>[ 219.783494] ? mark_held_locks+0x9e/0xe0
> > <4>[ 219.783546] ? execlists_hold+0xfc0/0xfc0 [i915]
> > <4>[ 219.783551] ? lockdep_hardirqs_on+0x348/0x5f0
> > <4>[ 219.783557] ? _raw_spin_unlock_irqrestore+0x34/0x60
> > <4>[ 219.783606] ? execlists_submission_tasklet+0x118/0x3a0 [i915]
> > <4>[ 219.783615] tasklet_action_common.isra.14+0x13b/0x410
> > <4>[ 219.783623] ? __do_softirq+0x1e4/0x9a7
> > <4>[ 219.783630] __do_softirq+0x226/0x9a7
> > <4>[ 219.783643] do_softirq_own_stack+0x2a/0x40
> > <4>[ 219.783647]
> > <4>[ 219.783692] ? heartbeat+0x3e2/0x10f0 [i915]
> > <4>[ 219.783696] do_softirq.part.13+0x49/0x50
> > <4>[ 219.783700] __local_bh_enable_ip+0x1a2/0x1e0
> > <4>[ 219.783748] heartbeat+0x409/0x10f0 [i915]
> > <4>[ 219.783801] ? __live_idle_pulse+0x9f0/0x9f0 [i915]
> > <4>[ 219.783806] ? lock_acquire+0x1ac/0x8a0
> > <4>[ 219.783811] ? process_one_work+0x811/0x1870
> > <4>[ 219.783827] ? rcu_read_lock_sched_held+0x9c/0xd0
> > <4>[ 219.783832] ? rcu_read_lock_bh_held+0xb0/0xb0
> > <4>[ 219.783836] ? _raw_spin_unlock_irq+0x1f/0x40
> > <4>[ 219.783845] process_one_work+0x8ca/0x1870
> > <4>[ 219.783848] ? lock_acquire+0x1ac/0x8a0
> > <4>[ 219.783852] ? worker_thread+0x1d0/0xb80
> > <4>[ 219.783864] ? pwq_dec_nr_in_flight+0x2c0/0x2c0
> > <4>[ 219.783870] ? do_raw_spin_lock+0x129/0x290
> > <4>[ 219.783886] worker_thread+0x82/0xb80
> > <4>[ 219.783895] ? __kthread_parkme+0xaf/0x1b0
> > <4>[ 219.783902] ? process_one_work+0x1870/0x1870
> > <4>[ 219.783906] kthread+0x34e/0x420
> > <4>[ 219.783911] ? kthread_create_on_node+0xc0/0xc0
> > <4>[ 219.783918] ret_from_fork+0x3a/0x50
> >
> > <3>[ 219.783950] Allocated by task 1264:
> > <4>[ 219.783975] save_stack+0x19/0x40
> > <4>[ 219.783978] __kasan_kmalloc.constprop.3+0xa0/0xd0
> > <4>[ 219.784029] i915_gem_create_context+0xa2/0xab8 [i915]
> > <4>[ 219.784081] i915_gem_context_create_ioctl+0x1fa/0x450 [i915]
> > <4>[ 219.784085] drm_ioctl_kernel+0x1d8/0x270
> > <4>[ 219.784088] drm_ioctl+0x676/0x930
> > <4>[ 219.784092] ksys_ioctl+0xb7/0xe0
> > <4>[ 219.784096] __x64_sys_ioctl+0x6a/0xb0
> > <4>[ 219.784100] do_syscall_64+0x94/0x530
> > <4>[ 219.784103] entry_SYSCALL_64_after_hwframe+0x49/0xb3
> >
> > <3>[ 219.784120] Freed by task 12:
> > <4>[ 219.784141] save_stack+0x19/0x40
> > <4>[ 219.784145] __kasan_slab_free+0x130/0x180
> > <4>[ 219.784148] kmem_cache_free_bulk+0x1bd/0x500
> > <4>[ 219.784152] kfree_rcu_work+0x1d8/0x890
> > <4>[ 219.784155] process_one_work+0x8ca/0x1870
> > <4>[ 219.784158] worker_thread+0x82/0xb80
> > <4>[ 219.784162] kthread+0x34e/0x420
> > <4>[ 219.784165] ret_from_fork+0x3a/0x50
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_gpu_error.c | 12 +++-
> > 1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 4d54dba35302..a976cd67b3b3 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -1207,8 +1207,6 @@ static void engine_record_registers(struct
> > intel_engine_coredump *ee)
> > static void record_request(const struct i915_request *request,
> > struct i915_request_coredump *erq)
> > {
> > - const struct i915_gem_context *ctx;
> > -
> > erq->flags = request->fence.flags;
> > erq->context = request->fence.context;
> > erq->seqno = request->fence.seqno;
> > @@ -1218,9 +1216,13 @@
Re: [Intel-gfx] [PATCH v2] drm: Fix HDCP failures when SRM fw is missing
On 2020-04-29 at 09:58:16 -0400, Sean Paul wrote:
> On Wed, Apr 29, 2020 at 9:50 AM Ramalingam C wrote:
> >
> > On 2020-04-14 at 15:02:55 -0400, Sean Paul wrote:
> > > From: Sean Paul
> > >
> > > The SRM cleanup in 79643fddd6eb2 ("drm/hdcp: optimizing the srm
> > > handling") inadvertently altered the behavior of HDCP auth when
> > > the SRM firmware is missing. Before that patch, missing SRM was
> > > interpreted as the device having no revoked keys. With that patch,
> > > if the SRM fw file is missing we reject _all_ keys.
> > >
> > > This patch fixes that regression by returning success if the file
> > > cannot be found. It also checks the return value from request_srm such
> > > that we won't end up trying to parse the ksv list if there is an error
> > > fetching it.
> > >
> > > Fixes: 79643fddd6eb ("drm/hdcp: optimizing the srm handling")
> > > Cc: sta...@vger.kernel.org
> > > Cc: Ramalingam C
> > > Cc: Sean Paul
> > > Cc: Maarten Lankhorst
> > > Cc: Maxime Ripard
> > > Cc: Thomas Zimmermann
> > > Cc: David Airlie
> > > Cc: Daniel Vetter
> > > Cc: dri-de...@lists.freedesktop.org
> > > Signed-off-by: Sean Paul
> > >
> > > Changes in v2:
> > > -Noticed a couple other things to clean up
> > > ---
> > >
> > > Sorry for the quick rev, noticed a couple other loose ends that should
> > > be cleaned up.
> > >
> > > drivers/gpu/drm/drm_hdcp.c | 8 +++-
> > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> > > index 7f386adcf872..910108ccaae1 100644
> > > --- a/drivers/gpu/drm/drm_hdcp.c
> > > +++ b/drivers/gpu/drm/drm_hdcp.c
> > > @@ -241,8 +241,12 @@ static int drm_hdcp_request_srm(struct drm_device
> > > *drm_dev,
> > >
> > > ret = request_firmware_direct(&fw, (const char *)fw_name,
> > > drm_dev->dev);
> > > - if (ret < 0)
> > > + if (ret < 0) {
> > > + *revoked_ksv_cnt = 0;
> > > + *revoked_ksv_list = NULL;
> > These two variables are already initialized by the caller.
>
> Right now it is, but that's not guaranteed. In the ret == 0 case, it's
> pretty common for a caller to assume the called function has
> validated/assigned all the function output.
Ok.
>
> > > + ret = 0;
> > Missing of this should have been caught by CI. May be CI system always
> > having the SRM file from previous execution. Never been removed. IGT
> > need a fix to clean the prior SRM files before execution.
> >
> > CI fix shouldn't block this fix.
> > > goto exit;
> > > + }
> > >
> > > if (fw->size && fw->data)
> > > ret = drm_hdcp_srm_update(fw->data, fw->size,
> > > revoked_ksv_list,
> > > @@ -287,6 +291,8 @@ int drm_hdcp_check_ksvs_revoked(struct drm_device
> > > *drm_dev, u8 *ksvs,
> > >
> > > ret = drm_hdcp_request_srm(drm_dev, &revoked_ksv_list,
> > > &revoked_ksv_cnt);
> > > + if (ret)
> > > + return ret;
> > This error code also shouldn't effect the caller(i915)
>
> Why not? I'd assume an invalid SRM revocation list should probably be
> treated as failure?
IMHO invalid SRM revocation need not be treated as HDCP authentication
failure.
First of all SRM need not supplied by all players. and incase, supplied
SRM is not as per the spec, then we dont have any list of revoked ID.
with this I dont think we need to fail the HDCP authentication. Until we
have valid list of revoked IDs from SRM, and the receiver ID is matching
to one of the revoked IDs, I wouldn't want to fail the HDCP
authentication.
-Ram
>
>
> > hence pushed a
> > change https://patchwork.freedesktop.org/series/76730/
> >
> > With these addresed.
> >
> > LGTM.
> >
> > Reviewed-by: Ramalingam C
> > >
> > > /* revoked_ksv_cnt will be zero when above function failed */
> > > for (i = 0; i < revoked_ksv_cnt; i++)
> > > --
> > > Sean Paul, Software Engineer, Google / Chromium OS
> > >
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/25] perf/core: Only copy-to-user after completely unlocking all locks, v3.
== Series Details == Series: series starting with [01/25] perf/core: Only copy-to-user after completely unlocking all locks, v3. URL : https://patchwork.freedesktop.org/series/76724/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17513 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17513 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17513, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17513: ### IGT changes ### Possible regressions * igt@gem_render_tiled_blits@basic: - fi-pnv-d510:[PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-pnv-d510/igt@gem_render_tiled_bl...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-pnv-d510/igt@gem_render_tiled_bl...@basic.html - fi-gdg-551: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-gdg-551/igt@gem_render_tiled_bl...@basic.html - fi-blb-e6850: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-blb-e6850/igt@gem_render_tiled_bl...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-blb-e6850/igt@gem_render_tiled_bl...@basic.html * igt@i915_module_load@reload: - fi-hsw-4770:[PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-hsw-4770/igt@i915_module_l...@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-hsw-4770/igt@i915_module_l...@reload.html * igt@i915_selftest@live@gt_pm: - fi-cml-s: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cml-s/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-cml-s/igt@i915_selftest@live@gt_pm.html - fi-icl-y: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-y/igt@i915_selftest@live@gt_pm.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-icl-y/igt@i915_selftest@live@gt_pm.html - fi-cfl-guc: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cfl-guc/igt@i915_selftest@live@gt_pm.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-cfl-guc/igt@i915_selftest@live@gt_pm.html - fi-skl-6700k2: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-skl-6700k2/igt@i915_selftest@live@gt_pm.html - fi-bsw-n3050: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html - fi-skl-guc: NOTRUN -> [INCOMPLETE][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-skl-guc/igt@i915_selftest@live@gt_pm.html - fi-kbl-x1275: [PASS][20] -> [INCOMPLETE][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-kbl-x1275/igt@i915_selftest@live@gt_pm.html - fi-bsw-kefka: [PASS][22] -> [INCOMPLETE][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html - fi-cfl-8700k: [PASS][24] -> [INCOMPLETE][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html - fi-icl-u2: [PASS][26] -> [INCOMPLETE][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-icl-u2/igt@i915_selftest@live@gt_pm.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17513/fi-icl-u2/igt@i915_selftest@live@gt_pm.html - fi-skl-6600u: [PASS][28] -> [INCOMPLETE][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-6600u/igt@i915_selftest@l
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for execlists
== Series Details == Series: series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for execlists URL : https://patchwork.freedesktop.org/series/76715/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8390_full -> Patchwork_17508_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_17508_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17508_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_17508_full: ### IGT changes ### Possible regressions * igt@perf@gen8-unprivileged-single-ctx-counters: - shard-apl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl4/igt@p...@gen8-unprivileged-single-ctx-counters.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-apl2/igt@p...@gen8-unprivileged-single-ctx-counters.html Known issues Here are the changes found in Patchwork_17508_full that come from known issues: ### IGT changes ### Issues hit * igt@gen9_exec_parse@allowed-all: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl3/igt@gen9_exec_pa...@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-kbl4/igt@gen9_exec_pa...@allowed-all.html * igt@kms_cursor_legacy@all-pipes-torture-bo: - shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([i915#128]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb6/igt@kms_cursor_leg...@all-pipes-torture-bo.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-iclb7/igt@kms_cursor_leg...@all-pipes-torture-bo.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#52] / [i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-glk7/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-ytiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-glk7/igt@kms_draw_...@draw-method-rgb565-mmap-gtt-ytiled.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180] / [i915#93] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-kbl4/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#49]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl2/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-skl1/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-move.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl4/igt@kms_...@bpc-switch-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-skl8/igt@kms_...@bpc-switch-dpms.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-kbl7/igt@kms_...@bpc-switch-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-kbl7/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17508/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +5 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8390/shard-apl4/igt@kms_vbl...@pipe-a-ts-continuation-suspend.
Re: [Intel-gfx] [PATCH v2] drm: Fix HDCP failures when SRM fw is missing
On Wed, Apr 29, 2020 at 10:22 AM Ramalingam C wrote:
>
> On 2020-04-29 at 09:58:16 -0400, Sean Paul wrote:
> > On Wed, Apr 29, 2020 at 9:50 AM Ramalingam C wrote:
> > >
> > > On 2020-04-14 at 15:02:55 -0400, Sean Paul wrote:
> > > > From: Sean Paul
> > > >
> > > > The SRM cleanup in 79643fddd6eb2 ("drm/hdcp: optimizing the srm
> > > > handling") inadvertently altered the behavior of HDCP auth when
> > > > the SRM firmware is missing. Before that patch, missing SRM was
> > > > interpreted as the device having no revoked keys. With that patch,
> > > > if the SRM fw file is missing we reject _all_ keys.
> > > >
> > > > This patch fixes that regression by returning success if the file
> > > > cannot be found. It also checks the return value from request_srm such
> > > > that we won't end up trying to parse the ksv list if there is an error
> > > > fetching it.
> > > >
> > > > Fixes: 79643fddd6eb ("drm/hdcp: optimizing the srm handling")
> > > > Cc: sta...@vger.kernel.org
> > > > Cc: Ramalingam C
> > > > Cc: Sean Paul
> > > > Cc: Maarten Lankhorst
> > > > Cc: Maxime Ripard
> > > > Cc: Thomas Zimmermann
> > > > Cc: David Airlie
> > > > Cc: Daniel Vetter
> > > > Cc: dri-de...@lists.freedesktop.org
> > > > Signed-off-by: Sean Paul
> > > >
> > > > Changes in v2:
> > > > -Noticed a couple other things to clean up
> > > > ---
> > > >
> > > > Sorry for the quick rev, noticed a couple other loose ends that should
> > > > be cleaned up.
> > > >
> > > > drivers/gpu/drm/drm_hdcp.c | 8 +++-
> > > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> > > > index 7f386adcf872..910108ccaae1 100644
> > > > --- a/drivers/gpu/drm/drm_hdcp.c
> > > > +++ b/drivers/gpu/drm/drm_hdcp.c
> > > > @@ -241,8 +241,12 @@ static int drm_hdcp_request_srm(struct drm_device
> > > > *drm_dev,
> > > >
> > > > ret = request_firmware_direct(&fw, (const char *)fw_name,
> > > > drm_dev->dev);
> > > > - if (ret < 0)
> > > > + if (ret < 0) {
> > > > + *revoked_ksv_cnt = 0;
> > > > + *revoked_ksv_list = NULL;
> > > These two variables are already initialized by the caller.
> >
> > Right now it is, but that's not guaranteed. In the ret == 0 case, it's
> > pretty common for a caller to assume the called function has
> > validated/assigned all the function output.
> Ok.
> >
> > > > + ret = 0;
> > > Missing of this should have been caught by CI. May be CI system always
> > > having the SRM file from previous execution. Never been removed. IGT
> > > need a fix to clean the prior SRM files before execution.
> > >
> > > CI fix shouldn't block this fix.
> > > > goto exit;
> > > > + }
> > > >
> > > > if (fw->size && fw->data)
> > > > ret = drm_hdcp_srm_update(fw->data, fw->size,
> > > > revoked_ksv_list,
> > > > @@ -287,6 +291,8 @@ int drm_hdcp_check_ksvs_revoked(struct drm_device
> > > > *drm_dev, u8 *ksvs,
> > > >
> > > > ret = drm_hdcp_request_srm(drm_dev, &revoked_ksv_list,
> > > > &revoked_ksv_cnt);
> > > > + if (ret)
> > > > + return ret;
> > > This error code also shouldn't effect the caller(i915)
> >
> > Why not? I'd assume an invalid SRM revocation list should probably be
> > treated as failure?
> IMHO invalid SRM revocation need not be treated as HDCP authentication
> failure.
>
> First of all SRM need not supplied by all players. and incase, supplied
> SRM is not as per the spec, then we dont have any list of revoked ID.
> with this I dont think we need to fail the HDCP authentication. Until we
> have valid list of revoked IDs from SRM, and the receiver ID is matching
> to one of the revoked IDs, I wouldn't want to fail the HDCP
> authentication.
>
Ok, thanks for the explanation. This all seems reasonable to me.
Looks like this can be applied as-is, right? I'll review the patch you
posted so we can ignore the -ve return values.
Thanks for the review!
Sean
> -Ram
> >
> >
> > > hence pushed a
> > > change https://patchwork.freedesktop.org/series/76730/
> > >
> > > With these addresed.
> > >
> > > LGTM.
> > >
> > > Reviewed-by: Ramalingam C
> > > >
> > > > /* revoked_ksv_cnt will be zero when above function failed */
> > > > for (i = 0; i < revoked_ksv_cnt; i++)
> > > > --
> > > > Sean Paul, Software Engineer, Google / Chromium OS
> > > >
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Re: [Intel-gfx] [PATCH] drm/i915/hdcp: Fix the return handling of drm_hdcp_check_ksvs_revoked
On Wed, Apr 29, 2020 at 9:46 AM Ramalingam C wrote:
>
> drm_hdcp_check_ksvs_revoked() returns the number of revoked keys and
> error codes when the SRM parsing is failed.
>
> Errors in SRM parsing can't affect the HDCP auth, hence with this patch,
> I915 will look out for revoked key count alone.
>
Reviewed-by: Sean Paul
> Signed-off-by: Ramalingam C
> cc: Sean Paul
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2cbc4619b4ce..96bf6def9830 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -576,7 +576,7 @@ int intel_hdcp_auth_downstream(struct intel_connector
> *connector)
> goto err;
>
> if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo,
> - num_downstream)) {
> + num_downstream) > 0) {
> drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n");
> ret = -EPERM;
> goto err;
> @@ -682,7 +682,7 @@ static int intel_hdcp_auth(struct intel_connector
> *connector)
> if (ret < 0)
> return ret;
>
> - if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1)) {
> + if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1) > 0) {
> drm_err(&dev_priv->drm, "BKSV is revoked\n");
> return -EPERM;
> }
> @@ -1283,7 +1283,7 @@ static int hdcp2_authentication_key_exchange(struct
> intel_connector *connector)
>
> if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
> msgs.send_cert.cert_rx.receiver_id,
> - 1)) {
> + 1) > 0) {
> drm_err(&dev_priv->drm, "Receiver ID is revoked\n");
> return -EPERM;
> }
> @@ -1484,7 +1484,7 @@ int hdcp2_authenticate_repeater_topology(struct
> intel_connector *connector)
> HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
> if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm,
> msgs.recvid_list.receiver_ids,
> - device_cnt)) {
> + device_cnt) > 0) {
> drm_err(&dev_priv->drm, "Revoked receiver ID(s) is in
> list\n");
> return -EPERM;
> }
> --
> 2.20.1
>
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> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[Intel-gfx] [PATCH i-g-t] perf: Flush the work between rounds of gen8-unprivileged-single-ctx-counter
Wait until the GPU is idle before starting a fresh round of probing gen8-unprivileged-single-ctx-counter. This avoids building up a huge backlog of render copies, hogging buffers and stale contexts, and invoking the oomkiller. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin --- tests/perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/perf.c b/tests/perf.c index 74fc8fd87..2d23a02c6 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -3787,6 +3787,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void) drm_intel_gem_context_destroy(context1); drm_intel_bufmgr_destroy(bufmgr); __perf_close(stream_fd); + gem_quiescent_gpu(drm_fd); } child_ret = igt_wait_helper(&child); -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb()
== Series Details == Series: drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb() URL : https://patchwork.freedesktop.org/series/76727/ State : success == Summary == CI Bug Log - changes from CI_DRM_8391 -> Patchwork_17514 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17514/index.html Known issues Here are the changes found in Patchwork_17514 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_pm_rpm@module-reload: - fi-skl-guc: [INCOMPLETE][1] ([i915#151]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-skl-guc/igt@i915_pm_...@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17514/fi-skl-guc/igt@i915_pm_...@module-reload.html Warnings * igt@i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8391/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17514/fi-kbl-x1275/igt@i915_pm_...@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (48 -> 41) -- Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8391 -> Patchwork_17514 CI-20190529: 20190529 CI_DRM_8391: 9cada6f702d618458eb6dda220f5cfefe655f475 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5614: d095827add11d4e8158b87683971ee659749d9a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17514: 5500fe83d497795edc05add948e67256091c872e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5500fe83d497 drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17514/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t] perf: Flush the work between rounds of gen8-unprivileged-single-ctx-counter
Oh... Is that on a low end platform? Looks alright : Reviewed-by: Lionel Landwerlin Thanks, -Lionel On 29/04/2020 17:51, Chris Wilson wrote: Wait until the GPU is idle before starting a fresh round of probing gen8-unprivileged-single-ctx-counter. This avoids building up a huge backlog of render copies, hogging buffers and stale contexts, and invoking the oomkiller. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin --- tests/perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/perf.c b/tests/perf.c index 74fc8fd87..2d23a02c6 100644 --- a/tests/perf.c +++ b/tests/perf.c @@ -3787,6 +3787,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void) drm_intel_gem_context_destroy(context1); drm_intel_bufmgr_destroy(bufmgr); __perf_close(stream_fd); + gem_quiescent_gpu(drm_fd); } child_ret = igt_wait_helper(&child); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] perf: Flush the work between rounds of gen8-unprivileged-single-ctx-counter
Quoting Lionel Landwerlin (2020-04-29 15:57:41) > Oh... Is that on a low end platform? glk. But it was mostly that it got stuck in the rut of hitting -EAGAIN. /* This needs to be investigated... From time * to time, the work we kick off doesn't seem * to happen. WTH?? */ Hmm. And that's before we release everything, so yes the leak is real and not being slow. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
