[Intel-gfx] ✓ Fi.CI.IGT: success for Add support for mipi dsi cmd mode (rev8)
== Series Details ==
Series: Add support for mipi dsi cmd mode (rev8)
URL : https://patchwork.freedesktop.org/series/69290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8138_full -> Patchwork_16982_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16982_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_preempt_timeout@timeout@rcs0}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl1/igt@sysfs_preempt_timeout@time...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-skl7/igt@sysfs_preempt_timeout@time...@rcs0.html
New tests
-
New tests have been introduced between CI_DRM_8138_full and
Patchwork_16982_full:
### New IGT tests (3) ###
* igt@sysfs_heartbeat_interval@off:
- Statuses :
- Exec time: [None] s
* igt@sysfs_heartbeat_interval@precise:
- Statuses :
- Exec time: [None] s
* igt@sysfs_preempt_timeout@idempotent:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_16982_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +6 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-iclb5/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#1402])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl8/igt@gem_ctx_persiste...@close-replace-race.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-skl6/igt@gem_ctx_persiste...@close-replace-race.html
* igt@gem_ctx_shared@q-independent-vebox:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#935])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl1/igt@gem_ctx_sha...@q-independent-vebox.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-skl7/igt@gem_ctx_sha...@q-independent-vebox.html
* igt@gem_exec_schedule@implicit-both-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb5/igt@gem_exec_sched...@implicit-both-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd.html
* igt@gem_exec_schedule@implicit-read-write-render:
- shard-snb: [PASS][11] -> [INCOMPLETE][12] ([i915#82])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-snb2/igt@gem_exec_sched...@implicit-read-write-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-snb5/igt@gem_exec_sched...@implicit-read-write-render.html
* igt@gem_exec_schedule@implicit-write-read-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276] / [i915#677])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_exec_sched...@implicit-write-read-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-iclb5/igt@gem_exec_sched...@implicit-write-read-bsd2.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#112146]) +2 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#644])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-glk4/igt@gem_pp...@flink-and-close-vma-leak.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-glk6/igt@gem_pp...@flink-and-close-vma-leak.html
- shard-apl: [PASS][19] -> [FAIL][20] ([i915#644])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16982/shard-apl3/igt@gem_pp...@flink-and-close-vma-leak.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#54])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html
[22]:
https://intel-gfx-ci.01.
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Check for a closed context when looking up an engine
== Series Details ==
Series: drm/i915/gem: Check for a closed context when looking up an engine
URL : https://patchwork.freedesktop.org/series/74750/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8138_full -> Patchwork_16984_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16984_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_preempt_timeout@timeout@rcs0}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl1/igt@sysfs_preempt_timeout@time...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-skl4/igt@sysfs_preempt_timeout@time...@rcs0.html
New tests
-
New tests have been introduced between CI_DRM_8138_full and
Patchwork_16984_full:
### New IGT tests (1) ###
* igt@sysfs_heartbeat_interval@off:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_16984_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@close-replace-race:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#1402])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl8/igt@gem_ctx_persiste...@close-replace-race.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-skl6/igt@gem_ctx_persiste...@close-replace-race.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#679])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-tglb7/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-tglb6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@vebox:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#1239])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-tglb7/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-tglb6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@vebox.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@implicit-write-read-bsd2:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_exec_sched...@implicit-write-read-bsd2.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb3/igt@gem_exec_sched...@implicit-write-read-bsd2.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +14 similar
issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_exec_schedule@pi-userfault-bsd:
- shard-iclb: [PASS][15] -> [SKIP][16] ([i915#677])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb8/igt@gem_exec_sched...@pi-userfault-bsd.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb1/igt@gem_exec_sched...@pi-userfault-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +4 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb8/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-iclb: [PASS][19] -> [INCOMPLETE][20] ([i915#1401])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb8/igt@gem_exec_whis...@basic-fds-all.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16984/shard-iclb1/igt@gem_exec_whis...@basic-fds-all.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][21] -> [FAIL][22] ([i915#644])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl8/igt@gem_pp...@flink-and-close-vma-leak.html
[22]:
Re: [Intel-gfx] [PATCH] drm/i915/gem: Check for a closed context when looking up an engine
On 16/03/2020 16:14, Chris Wilson wrote:
Beware that the context may already be closed as we try to lookup an
engine.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1389
Fixes: 130a95e9098e ("drm/i915/gem: Consolidate ctx->engines[] release")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/i915_gem_context.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 57b7ae2893e1..a09fd67fed1d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -192,12 +192,16 @@ i915_gem_context_unlock_engines(struct i915_gem_context
*ctx)
static inline struct intel_context *
i915_gem_context_get_engine(struct i915_gem_context *ctx, unsigned int idx)
{
- struct intel_context *ce = ERR_PTR(-EINVAL);
+ struct intel_context *ce;
rcu_read_lock(); {
struct i915_gem_engines *e = rcu_dereference(ctx->engines);
- if (likely(idx < e->num_engines && e->engines[idx]))
+ if (unlikely(e == NULL)) /* context was closed! */
+ ce = ERR_PTR(-ENOENT);
+ else if (likely(idx < e->num_engines && e->engines[idx]))
ce = intel_context_get(e->engines[idx]);
+ else
+ ce = ERR_PTR(-EINVAL);
} rcu_read_unlock();
return ce;
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Restore check for invalid vma for fencing
== Series Details ==
Series: drm/i915/gt: Restore check for invalid vma for fencing
URL : https://patchwork.freedesktop.org/series/74758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8138_full -> Patchwork_16985_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16985_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_preempt_timeout@timeout@rcs0}:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl1/igt@sysfs_preempt_timeout@time...@rcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-skl5/igt@sysfs_preempt_timeout@time...@rcs0.html
New tests
-
New tests have been introduced between CI_DRM_8138_full and
Patchwork_16985_full:
### New IGT tests (3) ###
* igt@sysfs_heartbeat_interval@off:
- Statuses :
- Exec time: [None] s
* igt@sysfs_heartbeat_interval@precise:
- Statuses :
- Exec time: [None] s
* igt@sysfs_preempt_timeout@idempotent:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_16985_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_persistence@legacy-engines-mixed-process@blt:
- shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] /
[i915#1197] / [i915#1239])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl1/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-apl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#679])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl1/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-apl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-independent-vebox:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#935])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl1/igt@gem_ctx_sha...@q-independent-vebox.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-skl5/igt@gem_ctx_sha...@q-independent-vebox.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_exec_schedule@implicit-write-read-bsd2:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276] / [i915#677])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_exec_sched...@implicit-write-read-bsd2.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-iclb5/igt@gem_exec_sched...@implicit-write-read-bsd2.html
* igt@gem_exec_schedule@independent-bsd2:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276]) +13 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-iclb8/igt@gem_exec_sched...@independent-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([i915#677]) +2 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-iclb4/igt@gem_exec_sched...@pi-distinct-iova-bsd.html
* igt@gem_exec_whisper@basic-fds-all:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#1401])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-tglb5/igt@gem_exec_whis...@basic-fds-all.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16985/shard-tglb3/igt@gem_exec_whis...@basic-fds-all.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-gl
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests (rev2)
Hi,
On Mon, 2020-03-16 at 19:25 +, Patchwork wrote:
> == Series Details ==
>
> Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent
> subtests (rev2)
> URL : https://patchwork.freedesktop.org/series/74201/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8137_full -> IGTPW_4307_full
>
>
> Summary
> ---
>
> **FAILURE**
False positive, see below.
> Serious unknown changes coming with IGTPW_4307_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_4307_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/index.html
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> IGTPW_4307_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@gem_ctx_shared@single-timeline:
> - shard-snb: NOTRUN -> [FAIL][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb4/igt@gem_ctx_sha...@single-timeline.html
> - shard-hsw: NOTRUN -> [FAIL][2] +1 similar issue
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@gem_ctx_sha...@single-timeline.html
>
> * igt@gem_exec_fence@basic-await@vcs0:
> - shard-kbl: [PASS][3] -> [FAIL][4] +3 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl1/igt@gem_exec_fence@basic-aw...@vcs0.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-kbl7/igt@gem_exec_fence@basic-aw...@vcs0.html
> - shard-iclb: [PASS][5] -> [FAIL][6]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@gem_exec_fence@basic-aw...@vcs0.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb5/igt@gem_exec_fence@basic-aw...@vcs0.html
> - shard-apl: [PASS][7] -> [FAIL][8] +2 similar issues
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> - shard-glk: [PASS][9] -> [FAIL][10] +2 similar issues
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk6/igt@gem_exec_fence@basic-aw...@vcs0.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-glk4/igt@gem_exec_fence@basic-aw...@vcs0.html
> - shard-tglb: [PASS][11] -> [FAIL][12] +2 similar issues
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb6/igt@gem_exec_fence@basic-aw...@vcs0.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@gem_exec_fence@basic-aw...@vcs0.html
Not related.
>
> * {igt@gem_userptr_blits@process-exit-mmap-busy@gtt} (NEW):
> - shard-iclb: NOTRUN -> [SKIP][13] +7 similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb3/igt@gem_userptr_blits@process-exit-mmap-b...@gtt.html
>
> * {igt@gem_userptr_blits@process-exit-mmap-busy@uc} (NEW):
> - shard-tglb: NOTRUN -> [SKIP][14] +11 similar issues
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html
Expected behavior.
>
> * igt@gem_wait@wait-rcs0:
> - shard-hsw: [PASS][15] -> [FAIL][16]
>[15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@gem_w...@wait-rcs0.html
>[16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@gem_w...@wait-rcs0.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
> - shard-snb: [PASS][17] -> [FAIL][18] +1 similar issue
>[17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-snb2/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-atomic.html
>[18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb5/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-atomic.html
Not related.
Thanks,
Janusz
>
>
> Warnings
>
> * igt@gem_exec_reloc@basic-spin-bsd:
> - shard-snb: [FAIL][19] ([i915#757]) -> [TIMEOUT][20]
>[19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-snb4/igt@gem_exec_re...@basic-spin-bsd.html
>[20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb6/igt@gem_exec_re...@basic-spin-bsd.html
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_8137_full and IGTPW_4307_full:
>
> ### New IGT tests (24) ###
>
> * igt@gem_userptr_blits@process-exit-mmap:
> - Statuses :
> - Exec time: [None] s
>
> * igt@gem_userptr_blits@process-exit-mmap-bu
[Intel-gfx] ✓ Fi.CI.IGT: success for Consider DBuf bandwidth when calculating CDCLK (rev2)
== Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : success == Summary == CI Bug Log - changes from CI_DRM_8138_full -> Patchwork_16987_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_16987_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb6/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-iclb4/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_schedule@implicit-both-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb5/igt@gem_exec_sched...@implicit-both-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-iclb2/igt@gem_exec_sched...@implicit-both-bsd.html * igt@gem_exec_schedule@implicit-write-read-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-iclb4/igt@gem_exec_sched...@implicit-write-read-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-iclb3/igt@gem_exec_sched...@implicit-write-read-bsd1.html * igt@gem_exec_whisper@basic-fds-all: - shard-tglb: [PASS][9] -> [INCOMPLETE][10] ([i915#1401]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-tglb5/igt@gem_exec_whis...@basic-fds-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-tglb8/igt@gem_exec_whis...@basic-fds-all.html * igt@i915_pm_sseu@full-enable: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#286]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl8/igt@i915_pm_s...@full-enable.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-skl8/igt@i915_pm_s...@full-enable.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl7/igt@i915_susp...@fence-restore-tiled2untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_color@pipe-c-ctm-max: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([i915#61]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-hsw2/igt@kms_co...@pipe-c-ctm-max.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-hsw1/igt@kms_co...@pipe-c-ctm-max.html * igt@kms_cursor_crc@pipe-a-cursor-128x128-random: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl2/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-skl4/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html - shard-apl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-apl3/igt@kms_cursor_...@pipe-a-cursor-128x128-random.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][23] -> [FAIL][24] ([i915#79]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-glk8/igt@kms_f...@flip-vs-expired-vblank.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16987/shard-glk8/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#34]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8138/shard-skl8/igt@kms_f...@plain-flip-ts-check-interruptible.html [26
[Intel-gfx] [PATCH v8 0/3] Dynamic EU configuration of Slice/Sub-slice/EU
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel This patch sets improves GPU power consumption on Linux kernel based OS such as Chromium OS, Ubuntu, etc. Following are the power savings. Power savings on GLK-GT1 Bobba platform running on Chrome OS. ---| App /KPI| % Power Benefit (mW) | |--| Hangout Call- 20 minute | 1.8% | Youtube 4K VPB | 14.13% | WebGL Aquarium | 13.76% | Unity3D | 6.78% | | | |--| Chrome PLT | BatteryLife Improves | | by ~45 minute| ---| Power savings on KBL-GT3 running on Android and Ubuntu (Linux). ---| App /KPI| % Power Benefit (mW) | |--| | Android | Ubuntu | |--|---| 3D Mark (Ice storm) | 2.30%| N.A. | TRex On screen | 2.49%| 2.97% | Manhattan On screen | 3.11%| 4.90% | Carchase On Screen | N.A. | 5.06% | AnTuTu 6.1.4| 3.42%| N.A. | SynMark2| N.A. | 1.7% | ---| We have also observed GPU core residencies improves by 1.035%. Technical Insights of the patch: Current GPU configuration code for i915 does not allow us to change EU/Slice/Sub-slice configuration dynamically. Its done only once while context is created. While particular graphics application is running, if we examine the command requests from user space, we observe that command density is not consistent. It means there is scope to change the graphics configuration dynamically even while context is running actively. This patch series proposes the solution to find the active pending load for all active context at given time and based on that, dynamically perform graphics configuration for each context. The feature can be enabled using sysfs. We examine pending commands for a context in the queue, essentially, we intercept them before they are executed by GPU and we update context with required number of EUs. One questions, what's the right number of EUs? Empirical data to achieve best performance in least power was considered. For the later one, we roughly categorized number of EUs logically based on platform. Now we compare number of pending commands with a particular threshold and then set number of EUs accordingly with update context. That threshold is also based on experiments & findings. If GPU is able to catch up with CPU, typically there are no pending commands, the EU config would remain unchanged there. In case there are more pending commands we reprogram context with higher number of EUs. Ankit Navik (3): drm/i915: Get active pending request for given context drm/i915: set optimum eu/slice/sub-slice configuration based on load type drm/i915: Predictive governor to control slice/subslice/eu drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++ drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 37 +++ drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 + drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 + drivers/gpu/drm/i915/gt/intel_context_types.h | 2 + drivers/gpu/drm/i915/gt/intel_lrc.c | 79 ++- drivers/gpu/drm/i915/i915_drv.h | 5 ++ drivers/gpu/drm/i915/i915_sysfs.c | 32 + drivers/gpu/drm/i915/intel_device_info.c | 59 - 9 files changed, 218 insertions(+), 4 deletions(-) -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 1/3] drm/i915: Get active pending request for given context
This patch gives us the active pending request count which is yet
to be submitted to the GPU.
V2:
* Change 64-bit to atomic for request count. (Tvrtko Ursulin)
V3:
* Remove mutex for request count.
* Rebase.
* Fixes hitting underflow for predictive request. (Tvrtko Ursulin)
V4:
* Rebase.
V5:
* Rebase.
V6:
* Rebase.
V7:
* Rebase.
* Add GEM_BUG_ON for req_cnt.
V8:
* Rebase.
Cc: Vipin Anand
Signed-off-by: Ankit Navik
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 5 +
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 9 +
4 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 026999b34abd..d0ff999429ff 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -879,6 +879,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
unsigned int flags)
}
trace_i915_context_create(ctx);
+ atomic_set(&ctx->req_cnt, 0);
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 28760bd03265..a9ba13f8865e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -171,6 +171,11 @@ struct i915_gem_context {
*/
struct radix_tree_root handles_vma;
+ /** req_cnt: tracks the pending commands, based on which we decide to
+* go for low/medium/high load configuration of the GPU.
+*/
+ atomic_t req_cnt;
+
/**
* @name: arbitrary name, used for user debug
*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..f90c968f95cd 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2565,6 +2565,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (batch->private)
intel_engine_pool_mark_active(batch->private, eb.request);
+ atomic_inc(&eb.gem_context->req_cnt);
+
trace_i915_request_queue(eb.request, eb.batch_flags);
err = eb_submit(&eb, batch);
err_request:
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 112531b29f59..ccfebebb0071 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2143,6 +2143,8 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
}
if (__i915_request_submit(rq)) {
+ struct i915_gem_context *ctx;
+
if (!merge) {
*port = execlists_schedule_in(last,
port - execlists->pending);
port++;
@@ -2158,6 +2160,13 @@ static void execlists_dequeue(struct intel_engine_cs
*engine)
submit = true;
last = rq;
+
+ ctx = rcu_dereference_protected(
+ rq->context->gem_context, true);
+
+ GEM_BUG_ON(atomic_read(&ctx->req_cnt));
+ if (atomic_read(&ctx->req_cnt) > 0)
+ atomic_dec(&ctx->req_cnt);
}
}
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration from
pre-defined optimum configuration table(opt_config).
It also introduce flag update_render_config which can set by any governor.
v2:
* Move static optimum_config to device init time.
* Rename function to appropriate name, fix data types and patch ordering.
* Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)
v3:
* Add safe guard check in i915_gem_context_set_load_type.
* Rename struct from optimum_config to i915_sseu_optimum_config to
avoid namespace clashes.
* Reduces memcpy for space efficient.
* Rebase.
* Improved commit message. (Tvrtko Ursulin)
v4:
* Move optimum config table to file scope. (Tvrtko Ursulin)
v5:
* Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
* Rebase.
v6:
* Rebase.
* Fix warnings.
v7:
* Fix return conditions.
* Remove i915_gem_context_set_load_type and move logic to
__execlists_update_reg_state. (Tvrtko Ursulin)
v8:
* Fix warnings.
* Rebase.
Cc: Vipin Anand
Signed-off-by: Ankit Navik
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 +
drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 32 +++
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 70 ++-
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/intel_device_info.c | 59 ++-
7 files changed, 169 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index d0ff999429ff..3aad45b0ba5a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -880,6 +880,9 @@ i915_gem_create_context(struct drm_i915_private *i915,
unsigned int flags)
trace_i915_context_create(ctx);
atomic_set(&ctx->req_cnt, 0);
+ ctx->slice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.slice_mask);
+ ctx->subslice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.subslice_mask[0]);
+ ctx->eu_cnt = RUNTIME_INFO(i915)->sseu.eu_per_subslice;
return ctx;
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index a9ba13f8865e..1af1acd73794 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -46,6 +46,19 @@ struct i915_gem_engines_iter {
const struct i915_gem_engines *engines;
};
+enum gem_load_type {
+ LOAD_TYPE_LOW,
+ LOAD_TYPE_MEDIUM,
+ LOAD_TYPE_HIGH,
+ LOAD_TYPE_LAST
+};
+
+struct i915_sseu_optimum_config {
+ u8 slice;
+ u8 subslice;
+ u8 eu;
+};
+
/**
* struct i915_gem_context - client state
*
@@ -155,6 +168,25 @@ struct i915_gem_context {
*/
atomic_t active_count;
+ /** slice_cnt: used to set the # of slices to be enabled. */
+ u8 slice_cnt;
+
+ /** subslice_cnt: used to set the # of subslices to be enabled. */
+ u8 subslice_cnt;
+
+ /** eu_cnt: used to set the # of eu to be enabled. */
+ u8 eu_cnt;
+
+ /** load_type: The designated load_type (high/medium/low) for a given
+* number of pending commands in the command queue.
+*/
+ enum gem_load_type load_type;
+
+ /** pending_load_type: The earlier load type that the GPU was configured
+* for (high/medium/low).
+*/
+ enum gem_load_type pending_load_type;
+
/**
* @hang_timestamp: The last time(s) this context caused a GPU hang
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
index 57a30956c922..4f51bfb9690c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
@@ -84,6 +84,8 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
if (ret)
return ret;
+ ce->user_sseu = true;
+
/* Nothing to do if unmodified. */
if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
goto unlock;
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 0f3b68b95c56..fd580026 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -93,6 +93,8 @@ struct intel_context {
const struct intel_context_ops *ops;
+ bool user_sseu;
+
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
in
Re: [Intel-gfx] [PATCH 3/4] drm/i915/perf: only append status when data is available
On 17/03/2020 00:16, Dixit, Ashutosh wrote: On Thu, 12 Mar 2020 16:05:01 -0700, Umesh Nerlige Ramappa wrote: From: Lionel Landwerlin The only bit of the status register we currently report in the i915-perf stream is the "report loss" bit. Only report this when we have some data to report with it. There was a kind of inconsistency here in that we could report report loss without appending the reports associated with the loss. Splitting hair a bit, but I am wondering if this is realistic? If reports have been lost in the middle of a OA buffer then there /will/ be some data from the hardware so head != tail. So is the situation which this patch is fixing ever been observed in practice? Also, if we are doing this, how about moving the entire status handling here, including intel_uncore_read() and OABUFFER_OVERFLOW handling (which I understand resets the stream so probably doesn't have associated data). In any case, since these are just random questions, this is: Reviewed-by: Ashutosh Dixit For some reason I thought this writing of lost report was inconsistent. But it's fairly unrelated to this series. Maybe drop this patch... -Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 3/3] drm/i915: Predictive governor to control slice/subslice/eu
Load classification is used for predictive governor to control
eu/slice/subslice based on workloads.
sysfs is provided to enable/disable the feature
V2:
* Fix code style.
* Move predictive_load_timer into a drm_i915_private
structure.
* Make generic function to set optimum config. (Tvrtko Ursulin)
V3:
* Rebase.
* Fix race condition for predictive load set.
* Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)
V4:
* Fix data type and initialization of mutex to protect predictive load
state.
* Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
* Move debugfs to kernel parameter.
V5:
* Rebase.
* Remove mutex for pred_timer
V6:
* Rebase.
* Fix warnings.
V7:
* Drop timer and move logic to __execlists_update_reg_state. (Tvrtko Ursulin)
* Remove kernel boot param and make it to sysfs entry. (Jani Nikula)
v8:
* Rebase.
Cc: Vipin Anand
Signed-off-by: Ankit Navik
---
drivers/gpu/drm/i915/i915_sysfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 45d32ef42787..5d76e4992c8d 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -433,12 +433,43 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return ret ?: count;
}
+static ssize_t deu_enable_show(struct device *kdev, struct device_attribute
*attr, char *buf)
+{
+ struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", i915->predictive_load_enable);
+}
+
+static ssize_t deu_enable_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
+ ssize_t ret;
+ u32 val;
+
+ ret = kstrtou32(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ /* Check invalid values */
+ if (val != 0 && val != 1)
+ ret = -EINVAL;
+
+ i915->predictive_load_enable = val;
+
+ return count;
+}
+
static DEVICE_ATTR_RO(gt_act_freq_mhz);
static DEVICE_ATTR_RO(gt_cur_freq_mhz);
static DEVICE_ATTR_RW(gt_boost_freq_mhz);
static DEVICE_ATTR_RW(gt_max_freq_mhz);
static DEVICE_ATTR_RW(gt_min_freq_mhz);
+static DEVICE_ATTR_RW(deu_enable);
+
static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute
*attr, char *buf);
@@ -474,6 +505,7 @@ static const struct attribute * const gen6_attrs[] = {
&dev_attr_gt_RP0_freq_mhz.attr,
&dev_attr_gt_RP1_freq_mhz.attr,
&dev_attr_gt_RPn_freq_mhz.attr,
+ &dev_attr_deu_enable.attr,
NULL,
};
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 1/3] drm/i915/perf: remove generated code
On 16/03/2020 20:46, Umesh Nerlige Ramappa wrote:
Looks good. Thanks for cleaning this up.
With s/mutex_lock/mutex_unlock/ below:
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
On Sat, Mar 14, 2020 at 12:33:29PM +0200, Lionel Landwerlin wrote:
A little bit of history :
Back when i915-perf was introduced (4.13), there was no way to
dynamically add new OA configurations to i915. Only the generated
configs baked in at build time were allowed.
It quickly became obvious that we would need to allow applications
to upload their own configurations, for instance to be able to test
new ones, and so by the next stable version (4.14) we added uAPIs
to allow uploading new configurations.
When adding that capability, we took the opportunity to remove most
HW configurations except the TestOa one which is a configuration
IGT would rely on to verify that the HW is outputting correct
values. At the time it made sense to have that confiuration in at
the same time a given HW platform added to the i915-perf driver.
Now that IGT has become the reference point for HW configurations (see
commit 53f8f541ca ("lib: Add i915_perf library"), previously this was
located in the GPUTop repository), the need for having those
configurations in i915-perf is gone.
On the Mesa side, we haven't relied on this test configuration for a
while. The MDAPI library always required 4.14 feature level and always
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
drivers/gpu/drm/i915/i915_perf_types.h | 2 -
drivers/gpu/drm/i915/oa/i915_oa_bdw.c | 90 ---
drivers/gpu/drm/i915/oa/i915_oa_bdw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cnl.c | 101 -
drivers/gpu/drm/i915/oa/i915_oa_cnl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_hsw.c | 118
drivers/gpu/drm/i915/oa/i915_oa_hsw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_icl.c | 98 -
drivers/gpu/drm/i915/oa/i915_oa_icl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 121 -
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 16 ---
drivers/gpu/drm/i915/selftests/i915_perf.c | 98 -
34 files changed, 96 insertions(+), 1757 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c
delete mode
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests (rev2)
Lakshmi, see below.
On Tue, Mar 17, 2020 at 09:53:51AM +0100, Janusz Krzysztofik wrote:
> Hi,
>
> On Mon, 2020-03-16 at 19:25 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent
> > subtests (rev2)
> > URL : https://patchwork.freedesktop.org/series/74201/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_8137_full -> IGTPW_4307_full
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
>
> False positive, see below.
>
> > Serious unknown changes coming with IGTPW_4307_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in IGTPW_4307_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/index.html
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> > IGTPW_4307_full:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@gem_ctx_shared@single-timeline:
> > - shard-snb: NOTRUN -> [FAIL][1]
> >[1]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb4/igt@gem_ctx_sha...@single-timeline.html
> > - shard-hsw: NOTRUN -> [FAIL][2] +1 similar issue
> >[2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@gem_ctx_sha...@single-timeline.html
> >
> > * igt@gem_exec_fence@basic-await@vcs0:
> > - shard-kbl: [PASS][3] -> [FAIL][4] +3 similar issues
> >[3]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl1/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-kbl7/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-iclb: [PASS][5] -> [FAIL][6]
> >[5]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb5/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-apl: [PASS][7] -> [FAIL][8] +2 similar issues
> >[7]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[8]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-glk: [PASS][9] -> [FAIL][10] +2 similar issues
> >[9]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk6/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[10]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-glk4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-tglb: [PASS][11] -> [FAIL][12] +2 similar issues
> >[11]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb6/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[12]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@gem_exec_fence@basic-aw...@vcs0.html
>
> Not related.
>
> >
> > * {igt@gem_userptr_blits@process-exit-mmap-busy@gtt} (NEW):
> > - shard-iclb: NOTRUN -> [SKIP][13] +7 similar issues
> >[13]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb3/igt@gem_userptr_blits@process-exit-mmap-b...@gtt.html
> >
> > * {igt@gem_userptr_blits@process-exit-mmap-busy@uc} (NEW):
> > - shard-tglb: NOTRUN -> [SKIP][14] +11 similar issues
> >[14]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@gem_userptr_blits@process-exit-mmap-b...@uc.html
>
> Expected behavior.
>
> >
> > * igt@gem_wait@wait-rcs0:
> > - shard-hsw: [PASS][15] -> [FAIL][16]
> >[15]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@gem_w...@wait-rcs0.html
> >[16]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@gem_w...@wait-rcs0.html
> >
> > * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
> > - shard-snb: [PASS][17] -> [FAIL][18] +1 similar issue
> >[17]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-snb2/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-atomic.html
> >[18]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb5/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-atomic.html
>
> Not related.
>
> Thanks,
> Janusz
>
>
> >
> >
> > Warnings
> >
> > * igt@gem_exec_reloc@basic-spin-bsd:
> > - shard-snb: [FAIL][19] ([i915#757]) -> [TIMEOUT][20]
> >[19]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-snb4/igt@gem_exec_re...@basic-spin-bsd.html
> >[20]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/sha
Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for Consider DBuf bandwidth when calculating CDCLK (rev2)
What is this weird DOC warning about? "Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c" - wondering, how is that related to this patch. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Patchwork Sent: Tuesday, March 17, 2020 2:36:10 AM To: Lisovskiy, Stanislav Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.DOCS: warning for Consider DBuf bandwidth when calculating CDCLK (rev2) == Series Details == Series: Consider DBuf bandwidth when calculating CDCLK (rev2) URL : https://patchwork.freedesktop.org/series/74739/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup URL : https://patchwork.freedesktop.org/series/74759/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8139_full -> Patchwork_16988_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16988_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16988_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16988_full: ### IGT changes ### Possible regressions * igt@gem_exec_alignment@single: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-kbl3/igt@gem_exec_alignm...@single.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-kbl1/igt@gem_exec_alignm...@single.html - shard-iclb: [PASS][3] -> [DMESG-WARN][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-iclb7/igt@gem_exec_alignm...@single.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-iclb5/igt@gem_exec_alignm...@single.html - shard-tglb: [PASS][5] -> [DMESG-WARN][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-tglb7/igt@gem_exec_alignm...@single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-tglb2/igt@gem_exec_alignm...@single.html - shard-apl: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-apl3/igt@gem_exec_alignm...@single.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-apl2/igt@gem_exec_alignm...@single.html * igt@gem_exec_parallel@vecs0-fds: - shard-skl: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-skl5/igt@gem_exec_paral...@vecs0-fds.html * igt@gem_softpin@invalid: - shard-skl: [PASS][10] -> [DMESG-WARN][11] +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-skl8/igt@gem_soft...@invalid.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-skl1/igt@gem_soft...@invalid.html - shard-kbl: [PASS][12] -> [INCOMPLETE][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-kbl7/igt@gem_soft...@invalid.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-kbl4/igt@gem_soft...@invalid.html - shard-glk: [PASS][14] -> [DMESG-WARN][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-glk8/igt@gem_soft...@invalid.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-glk9/igt@gem_soft...@invalid.html * igt@runner@aborted: - shard-tglb: NOTRUN -> ([FAIL][16], [FAIL][17]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-tglb2/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-tglb1/igt@run...@aborted.html Warnings * igt@runner@aborted: - shard-kbl: ([FAIL][18], [FAIL][19]) ([i915#1389] / [i915#1402] / [i915#92]) -> ([FAIL][20], [FAIL][21], [FAIL][22]) ([i915#92]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-kbl1/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-kbl1/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-kbl4/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-kbl1/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-kbl4/igt@run...@aborted.html - shard-apl: ([FAIL][23], [FAIL][24], [FAIL][25]) ([fdo#103927] / [i915#1402] / [i915#529]) -> ([FAIL][26], [FAIL][27], [FAIL][28]) ([fdo#103927]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-apl6/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-apl6/igt@run...@aborted.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8139/shard-apl4/igt@run...@aborted.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-apl2/igt@run...@aborted.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-apl2/igt@run...@aborted.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16988/shard-apl6/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_16988_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_asyn
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev8)
== Series Details ==
Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev8)
URL : https://patchwork.freedesktop.org/series/69980/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb031637fc75 drm/i915: Get active pending request for given context
-:95: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2164:
+ ctx = rcu_dereference_protected(
total: 0 errors, 0 warnings, 1 checks, 47 lines checked
a8e1bd3e403d drm/i915: set optimum eu/slice/sub-slice configuration based on
load type
-:231: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#231: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3079:
if (engine->class == RENDER_CLASS) {
+
-:233: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the
previous line
#233: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3081:
+ if (!ctx || !ctx->i915->predictive_load_enable
+|| ce->user_sseu) {
-:261: WARNING:TYPO_SPELLING: 'configration' may be misspelled - perhaps
'configuration'?
#261: FILE: drivers/gpu/drm/i915/i915_drv.h:927:
+ /* optimal slice/subslice/EU configration state */
-:331: CHECK:SPACING: No space is necessary after a cast
#331: FILE: drivers/gpu/drm/i915/intel_device_info.c:1075:
+ (struct i915_sseu_optimum_config *) glk_gt1_config;
-:337: CHECK:SPACING: No space is necessary after a cast
#337: FILE: drivers/gpu/drm/i915/intel_device_info.c:1081:
+ (struct i915_sseu_optimum_config *) kbl_gt2_config;
total: 0 errors, 1 warnings, 4 checks, 257 lines checked
0267ce00b30c drm/i915: Predictive governor to control slice/subslice/eu
-:37: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#37:
* Drop timer and move logic to __execlists_update_reg_state. (Tvrtko Ursulin)
total: 0 errors, 1 warnings, 0 checks, 50 lines checked
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev8)
== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev8) URL : https://patchwork.freedesktop.org/series/69980/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Get active pending request for given context Okay! Commit: drm/i915: set optimum eu/slice/sub-slice configuration based on load type +drivers/gpu/drm/i915/gt/intel_lrc.c:3086:59:expected struct i915_gem_context *ctx +drivers/gpu/drm/i915/gt/intel_lrc.c:3086:59:got struct i915_gem_context [noderef] *const gem_context +drivers/gpu/drm/i915/gt/intel_lrc.c:3086:59: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gt/intel_lrc.c:3112:15: warning: dereference of noderef expression +drivers/gpu/drm/i915/gt/intel_lrc.c:3112:45: warning: dereference of noderef expression +drivers/gpu/drm/i915/gt/intel_lrc.c:3113:19: warning: dereference of noderef expression +drivers/gpu/drm/i915/gt/intel_lrc.c:3113:48: warning: dereference of noderef expression Commit: drm/i915: Predictive governor to control slice/subslice/eu Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev8)
== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev8) URL : https://patchwork.freedesktop.org/series/69980/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8141 -> Patchwork_16989 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16989 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16989, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16989/index.html Changes --- No changes found Participating hosts (47 -> 12) -- ERROR: It appears as if the changes made in Patchwork_16989 prevented too many machines from booting. Missing(35): fi-kbl-soraka fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-icl-y fi-skl-lmem fi-icl-guc fi-icl-dsi fi-skl-6600u fi-cml-u2 fi-bxt-dsi fi-bdw-5557u fi-cml-s fi-tgl-u fi-bsw-n3050 fi-glk-dsi fi-kbl-7500u fi-bsw-nick fi-skl-6700k2 fi-kbl-r fi-ehl-1 fi-tgl-dsi fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8141 -> Patchwork_16989 CI-20190529: 20190529 CI_DRM_8141: f7be958f2574d30bad18983c3afe2c5401674dfb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5513: 417c926459dacf062f2945d3ba01a3f94551b16f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16989: 0267ce00b30c4ebd3b4de30a1edf7c19c1a43b49 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0267ce00b30c drm/i915: Predictive governor to control slice/subslice/eu a8e1bd3e403d drm/i915: set optimum eu/slice/sub-slice configuration based on load type bb031637fc75 drm/i915: Get active pending request for given context == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16989/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev8)
== Series Details == Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev8) URL : https://patchwork.freedesktop.org/series/69980/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 1/3] drm/i915/perf: remove generated code
A little bit of history :
Back when i915-perf was introduced (4.13), there was no way to
dynamically add new OA configurations to i915. Only the generated
configs baked in at build time were allowed.
It quickly became obvious that we would need to allow applications
to upload their own configurations, for instance to be able to test
new ones, and so by the next stable version (4.14) we added uAPIs
to allow uploading new configurations.
When adding that capability, we took the opportunity to remove most
HW configurations except the TestOa one which is a configuration
IGT would rely on to verify that the HW is outputting correct
values. At the time it made sense to have that confiuration in at
the same time a given HW platform added to the i915-perf driver.
Now that IGT has become the reference point for HW configurations (see
commit 53f8f541ca ("lib: Add i915_perf library"), previously this was
located in the GPUTop repository), the need for having those
configurations in i915-perf is gone.
On the Mesa side, we haven't relied on this test configuration for a
while. The MDAPI library always required 4.14 feature level and always
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
v5: Fix incorrect unlock in error path (Umesh)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
drivers/gpu/drm/i915/i915_perf_types.h | 2 -
drivers/gpu/drm/i915/oa/i915_oa_bdw.c | 90 ---
drivers/gpu/drm/i915/oa/i915_oa_bdw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cnl.c | 101 -
drivers/gpu/drm/i915/oa/i915_oa_cnl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_hsw.c | 118
drivers/gpu/drm/i915/oa/i915_oa_hsw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_icl.c | 98 -
drivers/gpu/drm/i915/oa/i915_oa_icl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 121 -
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 16 ---
drivers/gpu/drm/i915/selftests/i915_perf.c | 98 -
34 files changed, 96 insertions(+), 1757 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_s
[Intel-gfx] [PATCH v7 2/3] drm/i915/perf: remove redundant power configuration register override
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0069f09b988c..86c6abaa3e0e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2098,9 +2098,6 @@ gen8_update_reg_state_unlocked(const struct intel_context
*ce,
for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
reg_state[ctx_flexeu0 + i * 2 + 1] =
oa_config_flex_reg(stream->oa_config, flex_regs[i]);
-
- reg_state[CTX_R_PWR_CLK_STATE] =
- intel_sseu_make_rpcs(ce->engine->i915, &ce->sseu);
}
struct flex {
@@ -2906,10 +2903,6 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
/* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
stream = READ_ONCE(engine->i915->perf.exclusive_stream);
- /*
-* For gen12, only CTX_R_PWR_CLK_STATE needs update, but the caller
-* is already doing that, so nothing to be done for gen12 here.
-*/
if (stream && INTEL_GEN(stream->perf->i915) < 12)
gen8_update_reg_state_unlocked(ce, stream);
}
--
2.25.1
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[Intel-gfx] [PATCH v7 3/3] drm/i915/perf: introduce global sseu pinning
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power configuration to maintain its configuration.
As a result using OA (and NOA feeding into it) so far has required us
to use a power configuration that can work for all contexts. The only
power configuration fullfilling this is powergating half the execution
units.
This makes performance analysis for 3D workloads somewhat pointless.
Failing to find a solution that would work for everybody, this change
introduces a new i915-perf stream open parameter that punts the
decision off to userspace. If this parameter is omitted, the existing
Gen11 behavior remains (half EU array powergating).
This change takes the initiative to move all perf related sseu
configuration into i915_perf.c
v2: Make parameter priviliged if different from default
v3: Fix context modifying its sseu config while i915-perf is enabled
v4: Always consider global sseu a privileged operation (Tvrtko)
Override req_sseu point in intel_sseu_make_rpcs() (Tvrtko)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
v6: Actually commit the bits from v5...
Fixup some checkpath warnings
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 +
drivers/gpu/drm/i915/gt/intel_sseu.c| 33 ++--
drivers/gpu/drm/i915/i915_perf.c| 83 -
drivers/gpu/drm/i915/i915_perf_types.h | 7 ++
include/uapi/drm/i915_drm.h | 11 +++
6 files changed, 115 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 026999b34abd..c0e476fcd1fa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1401,10 +1401,10 @@ static int get_ringsize(struct i915_gem_context *ctx,
return 0;
}
-static int
-user_to_context_sseu(struct drm_i915_private *i915,
-const struct drm_i915_gem_context_param_sseu *user,
-struct intel_sseu *context)
+int
+i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+ const struct drm_i915_gem_context_param_sseu
*user,
+ struct intel_sseu *context)
{
const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
@@ -1539,7 +1539,7 @@ static int set_sseu(struct i915_gem_context *ctx,
goto out_ce;
}
- ret = user_to_context_sseu(i915, &user_sseu, &sseu);
+ ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
if (ret)
goto out_ce;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index f1d884d304bd..3702b2fb27ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -225,4 +225,8 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter
*it);
struct i915_lut_handle *i915_lut_handle_alloc(void);
void i915_lut_handle_free(struct i915_lut_handle *lut);
+int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+ const struct drm_i915_gem_context_param_sseu
*user,
+ struct intel_sseu *context);
+
#endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 74f793423231..d173271c7397 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -65,7 +65,6 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
{
const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
bool subslice_pg = sseu->has_subslice_pg;
- struct intel_sseu ctx_sseu;
u8 slices, subslices;
u32 rpcs = 0;
@@ -78,31 +77,13 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
/*
* If i915/perf is active, we want a stable powergating configuration
-* on the system.
-*
-* We could choose full enablement, but on ICL we know there are use
-* cases which disable slices for functional, apart for performance
-* reasons. So in this case we select a known stable subset.
+* on the system. Use the configuration pinned by i915/perf.
*/
- if (!i915->perf.exclusive_stream) {
- ctx_sseu = *req_sseu;
- } else {
- ctx_sseu = intel_sseu_from_device_info(sseu);
-
- if (IS_GEN(i915, 11)) {
- /*
-* We only need subslice count so it doesn't matter
-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v7,1/3] drm/i915/perf: remove generated code
== Series Details ==
Series: series starting with [v7,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74767/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dfa8113ae277 drm/i915/perf: remove generated code
-:24: WARNING:UNKNOWN_COMMIT_ID: Unknown commit id '53f8f541ca', maybe rebased
or not pulled?
#24:
commit 53f8f541ca ("lib: Add i915_perf library"), previously this was
-:208: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#208:
deleted file mode 100644
total: 0 errors, 2 warnings, 0 checks, 278 lines checked
1623895d809c drm/i915/perf: remove redundant power configuration register
override
ab46c9416005 drm/i915/perf: introduce global sseu pinning
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [v7,1/3] drm/i915/perf: remove generated code
== Series Details == Series: series starting with [v7,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74767/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
As we store the handle lookup inside a radix tree, we do not need the
gem_context->mutex except until we need to insert our lookup into the
common radix tree. This takes a small bit of rearranging to ensure that
the lut we insert into the tree is ready prior to actually inserting it
(as soon as it is exposed via the radixtree, it is visible to any other
submission).
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 43 ---
1 file changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..75529d8e0f08 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -481,7 +481,7 @@ eb_add_vma(struct i915_execbuffer *eb,
GEM_BUG_ON(i915_vma_is_closed(vma));
- ev->vma = i915_vma_get(vma);
+ ev->vma = vma;
ev->exec = entry;
ev->flags = entry->flags;
@@ -731,24 +731,25 @@ static int eb_select_context(struct i915_execbuffer *eb)
static int eb_lookup_vmas(struct i915_execbuffer *eb)
{
struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
+ unsigned int batch = eb_batch_index(eb);
struct drm_i915_gem_object *obj;
- unsigned int i, batch;
+ unsigned int i;
int err;
- if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
- return -ENOENT;
-
INIT_LIST_HEAD(&eb->relocs);
INIT_LIST_HEAD(&eb->unbound);
- batch = eb_batch_index(eb);
-
for (i = 0; i < eb->buffer_count; i++) {
u32 handle = eb->exec[i].handle;
struct i915_lut_handle *lut;
struct i915_vma *vma;
+lookup:
+ rcu_read_lock();
vma = radix_tree_lookup(handles_vma, handle);
+ if (likely(vma))
+ vma = i915_vma_tryget(vma);
+ rcu_read_unlock();
if (likely(vma))
goto add_vma;
@@ -770,26 +771,38 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb)
goto err_obj;
}
- err = radix_tree_insert(handles_vma, handle, vma);
- if (unlikely(err)) {
- i915_lut_handle_free(lut);
- goto err_obj;
- }
-
/* transfer ref to lut */
+ i915_gem_object_get(obj);
if (!atomic_fetch_inc(&vma->open_count))
i915_vma_reopen(vma);
lut->handle = handle;
lut->ctx = eb->gem_context;
+ mutex_lock(&eb->gem_context->mutex);
+ err = -ENOENT;
+ if (unlikely(!i915_gem_context_is_closed(eb->gem_context)))
+ err = radix_tree_insert(handles_vma, handle, vma);
+ mutex_unlock(&eb->gem_context->mutex);
+ if (unlikely(err)) {
+ atomic_dec(&vma->open_count);
+ i915_gem_object_put(obj);
+ i915_lut_handle_free(lut);
+ i915_gem_object_put(obj);
+ if (err == -EEXIST)
+ goto lookup;
+ goto err_vma;
+ }
+
i915_gem_object_lock(obj);
list_add(&lut->obj_link, &obj->lut_list);
i915_gem_object_unlock(obj);
add_vma:
err = eb_validate_vma(eb, &eb->exec[i], vma);
- if (unlikely(err))
+ if (unlikely(err)) {
+ i915_vma_put(vma);
goto err_vma;
+ }
eb_add_vma(eb, i, batch, vma);
}
@@ -1494,9 +1507,7 @@ static int eb_relocate(struct i915_execbuffer *eb)
{
int err;
- mutex_lock(&eb->gem_context->mutex);
err = eb_lookup_vmas(eb);
- mutex_unlock(&eb->gem_context->mutex);
if (err)
return err;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/12] drm/i915/gem: Teach execbuf how to wait on future syncobj
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 21 +--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..bbe501a3e619 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -2260,8 +2261,24 @@ await_fence_array(struct i915_execbuffer *eb,
continue;
fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
+ if (!fence) {
+ struct dma_fence *old;
+
+ fence = dma_fence_create_proxy();
+ if (!fence)
+ return -ENOMEM;
+
+ spin_lock(&syncobj->lock);
+ old = rcu_dereference_protected(syncobj->fence, true);
+ if (unlikely(old)) {
+ dma_fence_put(fence);
+ fence = dma_fence_get(old);
+ } else {
+ rcu_assign_pointer(syncobj->fence,
+ dma_fence_get(fence));
+ }
+ spin_unlock(&syncobj->lock);
+ }
err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/12] drm/i915/selftests: Add request throughput measurement to perf
Under ideal circumstances, the driver should be able to keep the GPU
fully saturated with work. Measure how close to ideal we get under the
harshest of conditions with no user payload.
v2: Also measure throughput using only one thread.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_request.c | 590 +-
2 files changed, 590 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 3bf7f53e9924..d8da142985eb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -16,5 +16,6 @@
* Tests are executed in order by igt/i915_selftest
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
+selftest(request, i915_request_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index f89d9c42f1fa..a32dfcc6c2ec 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
@@ -1233,7 +1234,7 @@ static int live_parallel_engines(void *arg)
struct igt_live_test t;
unsigned int idx;
- snprintf(name, sizeof(name), "%pS", fn);
+ snprintf(name, sizeof(name), "%ps", *fn);
err = igt_live_test_begin(&t, i915, __func__, name);
if (err)
break;
@@ -1470,3 +1471,590 @@ int i915_request_live_selftests(struct drm_i915_private
*i915)
return i915_subtests(tests, i915);
}
+
+static int switch_to_kernel_sync(struct intel_context *ce, int err)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0 && !err)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ while (!err && !intel_engine_is_idle(ce->engine))
+ intel_engine_flush_submission(ce->engine);
+
+ return err;
+}
+
+struct perf_stats {
+ struct intel_engine_cs *engine;
+ unsigned long count;
+ ktime_t time;
+ ktime_t busy;
+ u64 runtime;
+};
+
+struct perf_series {
+ struct drm_i915_private *i915;
+ unsigned int nengines;
+ struct intel_context *ce[];
+};
+
+static int s_sync0(void *arg)
+{
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+ int err = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ps->ce[idx]);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ if (++idx == ps->nengines)
+ idx = 0;
+ } while (!__igt_timeout(end_time, NULL));
+
+ return err;
+}
+
+static int s_sync1(void *arg)
+{
+ struct perf_series *ps = arg;
+ struct i915_request *prev = NULL;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+ int err = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ps->ce[idx]);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ if (prev && i915_request_wait(prev, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(prev);
+ prev = rq;
+ if (err)
+ break;
+
+ if (++idx == ps->nengines)
+ idx = 0;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_request_put(prev);
+
+ return err;
+}
+
+static int s_many(void *arg)
+{
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
+ unsigned int idx = 0;
+
+ GEM_BUG_ON(!ps->nengines);
+ do {
+
[Intel-gfx] [PATCH 05/12] dma-buf: Report signaled links inside dma-fence-chain
Whenever we walk along the dma-fence-chain, we prune signaled links to
keep the chain nice and tidy. This leads to situations where we can
prune a link and report the earlier fence as the target seqno --
violating our own consistency checks that the seqno is not more advanced
than the last element in a dma-fence-chain.
Report a NULL fence and success if the seqno has already been signaled.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/dma-fence-chain.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma-buf/dma-fence-chain.c
b/drivers/dma-buf/dma-fence-chain.c
index 3d123502ff12..c435bbba851c 100644
--- a/drivers/dma-buf/dma-fence-chain.c
+++ b/drivers/dma-buf/dma-fence-chain.c
@@ -99,6 +99,12 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence,
uint64_t seqno)
return -EINVAL;
dma_fence_chain_for_each(*pfence, &chain->base) {
+ if ((*pfence)->seqno < seqno) { /* already signaled */
+ dma_fence_put(*pfence);
+ *pfence = NULL;
+ break;
+ }
+
if ((*pfence)->context != chain->base.context ||
to_dma_fence_chain(*pfence)->prev_seqno < seqno)
break;
@@ -222,6 +228,7 @@ EXPORT_SYMBOL(dma_fence_chain_ops);
* @chain: the chain node to initialize
* @prev: the previous fence
* @fence: the current fence
+ * @seqno: the sequence number (syncpt) of the fence within the chain
*
* Initialize a new chain node and either start a new chain or add the node to
* the existing chain of the previous fence.
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/12] drm/i915/perf: Schedule oa_config after modifying the contexts
We wish that the scheduler emit the context modification commands prior
to enabling the oa_config, for which we must explicitly inform it of the
ordering constraints. This is especially important as we now wait for
the final oa_config setup to be completed and as this wait may be on a
distinct context to the state modifications, we need that command packet
to be always last in the queue.
We borrow the i915_active for its ability to track multiple timelines
and the last dma_fence on each; a flexible dma_resv. Keeping track of
each dma_fence is important for us so that we can efficiently schedule
the requests and reprioritise as required.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/display/intel_overlay.c | 8 +-
drivers/gpu/drm/i915/gt/intel_context_param.c | 2 +-
drivers/gpu/drm/i915/i915_active.c| 6 +-
drivers/gpu/drm/i915/i915_active.h| 2 +-
drivers/gpu/drm/i915/i915_perf.c | 154 +++---
drivers/gpu/drm/i915/i915_perf_types.h| 5 +-
drivers/gpu/drm/i915/i915_vma.h | 2 +-
drivers/gpu/drm/i915/selftests/i915_active.c | 4 +-
8 files changed, 115 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 481187223101..88711c2a74f6 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -272,7 +272,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
i915_request_add(rq);
- return i915_active_wait(&overlay->last_flip);
+ return i915_active_wait(&overlay->last_flip, TASK_INTERRUPTIBLE);
}
static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
@@ -429,14 +429,14 @@ static int intel_overlay_off(struct intel_overlay
*overlay)
intel_overlay_flip_prepare(overlay, NULL);
i915_request_add(rq);
- return i915_active_wait(&overlay->last_flip);
+ return i915_active_wait(&overlay->last_flip, TASK_INTERRUPTIBLE);
}
/* recover from an interruption due to a signal
* We have to be careful not to repeat work forever an make forward progess. */
static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
{
- return i915_active_wait(&overlay->last_flip);
+ return i915_active_wait(&overlay->last_flip, TASK_INTERRUPTIBLE);
}
/* Wait for pending overlay flip and release old frame.
@@ -477,7 +477,7 @@ static int intel_overlay_release_old_vid(struct
intel_overlay *overlay)
i915_request_add(rq);
- return i915_active_wait(&overlay->last_flip);
+ return i915_active_wait(&overlay->last_flip, TASK_INTERRUPTIBLE);
}
void intel_overlay_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c
b/drivers/gpu/drm/i915/gt/intel_context_param.c
index 65dcd090245d..903cce8c23c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_param.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_param.c
@@ -15,7 +15,7 @@ int intel_context_set_ring_size(struct intel_context *ce,
long sz)
if (intel_context_lock_pinned(ce))
return -EINTR;
- err = i915_active_wait(&ce->active);
+ err = i915_active_wait(&ce->active, TASK_INTERRUPTIBLE);
if (err < 0)
goto unlock;
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 535b8161a597..d26295a6812e 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -496,7 +496,7 @@ static int flush_lazy_signals(struct i915_active *ref)
return err;
}
-int i915_active_wait(struct i915_active *ref)
+int i915_active_wait(struct i915_active *ref, int state)
{
int err;
@@ -511,7 +511,9 @@ int i915_active_wait(struct i915_active *ref)
if (err)
return err;
- if (wait_var_event_interruptible(ref, i915_active_is_idle(ref)))
+ if (!i915_active_is_idle(ref) &&
+ ___wait_var_event(ref, i915_active_is_idle(ref),
+ state, 0, 0, schedule()))
return -EINTR;
flush_work(&ref->work);
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index bffbcf7751a7..224b95a95fcd 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -181,7 +181,7 @@ static inline bool i915_active_has_exclusive(struct
i915_active *ref)
return rcu_access_pointer(ref->excl.fence);
}
-int i915_active_wait(struct i915_active *ref);
+int i915_active_wait(struct i915_active *ref, int state);
int i915_sw_fence_await_active(struct i915_sw_fence *fence,
struct i915_active *ref,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1b074bb4a7fe..214e72670738 100644
--- a/drivers/gpu/drm/i915/i915_per
[Intel-gfx] [PATCH 07/12] dma-buf: Proxy fence, an unsignaled fence placeholder
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real fence completes, and any future listeners will instead be
attach directly to the real fence avoiding any indirection overhead.
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/dma-buf/Makefile | 13 +-
drivers/dma-buf/dma-fence-private.h | 20 +
drivers/dma-buf/dma-fence-proxy.c| 189 +
drivers/dma-buf/dma-fence.c | 4 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-proxy.c | 581 +++
include/linux/dma-fence-proxy.h | 20 +
7 files changed, 824 insertions(+), 4 deletions(-)
create mode 100644 drivers/dma-buf/dma-fence-private.h
create mode 100644 drivers/dma-buf/dma-fence-proxy.c
create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c
create mode 100644 include/linux/dma-fence-proxy.h
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 995e05f609ff..afaf6dadd9a3 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -1,6 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \
-dma-resv.o seqno-fence.o
+obj-y := \
+ dma-buf.o \
+ dma-fence.o \
+ dma-fence-array.o \
+ dma-fence-chain.o \
+ dma-fence-proxy.o \
+ dma-resv.o \
+ seqno-fence.o
obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o
obj-$(CONFIG_DMABUF_HEAPS) += heaps/
obj-$(CONFIG_SYNC_FILE)+= sync_file.o
@@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
dmabuf_selftests-y := \
selftest.o \
st-dma-fence.o \
- st-dma-fence-chain.o
+ st-dma-fence-chain.o \
+ st-dma-fence-proxy.o
obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/dma-fence-private.h
b/drivers/dma-buf/dma-fence-private.h
new file mode 100644
index ..6924d28af0fa
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-private.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Fence mechanism for dma-buf and to allow for asynchronous dma access
+ *
+ * Copyright (C) 2012 Canonical Ltd
+ * Copyright (C) 2012 Texas Instruments
+ *
+ * Authors:
+ * Rob Clark
+ * Maarten Lankhorst
+ */
+
+#ifndef DMA_FENCE_PRIVATE_H
+#define DMA_FENCE_PRIAVTE_H
+
+struct dma_fence;
+
+bool __dma_fence_enable_signaling(struct dma_fence *fence);
+
+#endif /* DMA_FENCE_PRIAVTE_H */
diff --git a/drivers/dma-buf/dma-fence-proxy.c
b/drivers/dma-buf/dma-fence-proxy.c
new file mode 100644
index ..6dce543d0757
--- /dev/null
+++ b/drivers/dma-buf/dma-fence-proxy.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dma-fence-proxy: placeholder unsignaled fence
+ *
+ * Copyright (C) 2017-2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "dma-fence-private.h"
+
+struct dma_fence_proxy {
+ struct dma_fence base;
+ spinlock_t lock;
+
+ struct dma_fence *real;
+ struct dma_fence_cb cb;
+ struct irq_work work;
+};
+
+static const char *proxy_get_driver_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_driver_name(real) : "proxy";
+}
+
+static const char *proxy_get_timeline_name(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+
+ return real ? real->ops->get_timeline_name(real) : "unset";
+}
+
+static void proxy_irq_work(struct irq_work *work)
+{
+ struct dma_fence_proxy *p = container_of(work, typeof(*p), work);
+
+ dma_fence_signal(&p->base);
+ dma_fence_put(&p->base);
+}
+
+static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb)
+{
+ struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb);
+
+ if (real->error)
+ dma_fence_set_error(&p->base, real->error);
+
+ /* Lower the height of the proxy chain -> single stack frame */
+ irq_work_queue(&p->work);
+}
+
+static bool proxy_enable_signaling(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof(*p), base);
+ struct dma_fence *real = READ_ONCE(p->real);
+ bool ret = true;
+
+ if (real) {
+ spin_lock_nested(real->lock, SINGLE_DEPTH_NESTING);
+ ret = __dma_fence_enable_signaling(real);
+ spin_unlock(real->lock);
+ }
+
+ return ret;
+}
+
+static void proxy_release(struct dma_fence *fence)
+{
+ struct dma_fence_proxy *p = container_of(fence, typeof
[Intel-gfx] [PATCH 10/12] drm/i915/gem: Allow combining submit-fences with syncobj
Fixes: a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +++---
include/uapi/drm/i915_drm.h| 7 ---
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index bbe501a3e619..675506ee392d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2225,7 +2225,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
- fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+ fences[n] = ptr_pack_bits(syncobj, fence.flags, 3);
}
return fences;
@@ -2256,7 +2256,7 @@ await_fence_array(struct i915_execbuffer *eb,
struct dma_fence *fence;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n], &flags, 3);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
@@ -2280,7 +2280,11 @@ await_fence_array(struct i915_execbuffer *eb,
spin_unlock(&syncobj->lock);
}
- err = i915_request_await_dma_fence(eb->request, fence);
+ if (flags & I915_EXEC_FENCE_WAIT_SUBMIT)
+ err = i915_request_await_execution(eb->request, fence,
+
eb->engine->bond_execute);
+ else
+ err = i915_request_await_dma_fence(eb->request, fence);
dma_fence_put(fence);
if (err < 0)
return err;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2813e579b480..3a24817ca25b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1040,9 +1040,10 @@ struct drm_i915_gem_exec_fence {
*/
__u32 handle;
-#define I915_EXEC_FENCE_WAIT(1<<0)
-#define I915_EXEC_FENCE_SIGNAL (1<<1)
-#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
+#define I915_EXEC_FENCE_WAIT(1u << 0)
+#define I915_EXEC_FENCE_SIGNAL (1u << 1)
+#define I915_EXEC_FENCE_WAIT_SUBMIT (1u << 2)
+#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_WAIT_SUBMIT << 1))
__u32 flags;
};
--
2.20.1
___
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[Intel-gfx] [PATCH 02/12] drm/i915: Wrap i915_active in a simple kreffed struct
For conveniences of callers that just want to use an i915_active to
track a wide array of concurrent timelines, wrap the base i915_active
struct inside a kref. This i915_active will self-destruct after use.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_active.c | 53 ++
drivers/gpu/drm/i915/i915_active.h | 4 +++
2 files changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index c4048628188a..535b8161a597 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -937,6 +937,59 @@ void i915_active_noop(struct dma_fence *fence, struct
dma_fence_cb *cb)
active_fence_cb(fence, cb);
}
+struct auto_active {
+ struct i915_active base;
+ struct kref ref;
+};
+
+struct i915_active *i915_active_get(struct i915_active *ref)
+{
+ struct auto_active *aa = container_of(ref, typeof(*aa), base);
+
+ kref_get(&aa->ref);
+ return &aa->base;
+}
+
+static void auto_release(struct kref *ref)
+{
+ struct auto_active *aa = container_of(ref, typeof(*aa), ref);
+
+ i915_active_fini(&aa->base);
+ kfree(aa);
+}
+
+void i915_active_put(struct i915_active *ref)
+{
+ struct auto_active *aa = container_of(ref, typeof(*aa), base);
+
+ kref_put(&aa->ref, auto_release);
+}
+
+static int auto_active(struct i915_active *ref)
+{
+ i915_active_get(ref);
+ return 0;
+}
+
+static void auto_retire(struct i915_active *ref)
+{
+ i915_active_put(ref);
+}
+
+struct i915_active *i915_active_create(void)
+{
+ struct auto_active *aa;
+
+ aa = kmalloc(sizeof(*aa), GFP_KERNEL);
+ if (!aa)
+ return NULL;
+
+ kref_init(&aa->ref);
+ i915_active_init(&aa->base, auto_active, auto_retire);
+
+ return &aa->base;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/i915_active.c"
#endif
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index b3282ae7913c..bffbcf7751a7 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -221,4 +221,8 @@ void i915_request_add_active_barriers(struct i915_request
*rq);
void i915_active_print(struct i915_active *ref, struct drm_printer *m);
void i915_active_unlock_wait(struct i915_active *ref);
+struct i915_active *i915_active_create(void);
+struct i915_active *i915_active_get(struct i915_active *ref);
+void i915_active_put(struct i915_active *ref);
+
#endif /* _I915_ACTIVE_H_ */
--
2.20.1
___
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[Intel-gfx] [PATCH 04/12] dma-buf: Prettify typecasts for dma-fence-chain
Inside dma-fence-chain, we use a cmpxchg on an RCU-protected pointer. To avoid the sparse warning for using the RCU pointer directly, we have to cast away the __rcu annotation. However, we don't need to use void* everywhere and can stick to the dma_fence*. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/dma-buf/dma-fence-chain.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index 44a741677d25..3d123502ff12 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -62,7 +62,8 @@ struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) replacement = NULL; } - tmp = cmpxchg((void **)&chain->prev, (void *)prev, (void *)replacement); + tmp = cmpxchg((struct dma_fence __force **)&chain->prev, + prev, replacement); if (tmp == prev) dma_fence_put(tmp); else -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/12] drm/syncobj: Allow use of dma-fence-proxy
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_syncobj.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 42d46414f767..e141db0e1eb6 100644
--- a/drivers/gpu/drm/drm_syncobj.c
+++ b/drivers/gpu/drm/drm_syncobj.c
@@ -184,6 +184,7 @@
*/
#include
+#include
#include
#include
#include
@@ -324,14 +325,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj,
struct dma_fence *old_fence;
struct syncobj_wait_entry *cur, *tmp;
- if (fence)
- dma_fence_get(fence);
-
spin_lock(&syncobj->lock);
- old_fence = rcu_dereference_protected(syncobj->fence,
- lockdep_is_held(&syncobj->lock));
- rcu_assign_pointer(syncobj->fence, fence);
+ old_fence = dma_fence_replace_proxy(&syncobj->fence, fence);
if (fence != old_fence) {
list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node)
--
2.20.1
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[Intel-gfx] [PATCH 06/12] dma-buf: Exercise dma-fence-chain under selftests
A few very simple testcases to exercise the dma-fence-chain API.
Signed-off-by: Chris Wilson
---
drivers/dma-buf/Makefile | 3 +-
drivers/dma-buf/selftests.h | 1 +
drivers/dma-buf/st-dma-fence-chain.c | 713 +++
3 files changed, 716 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma-buf/st-dma-fence-chain.c
diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile
index 9c190026bfab..995e05f609ff 100644
--- a/drivers/dma-buf/Makefile
+++ b/drivers/dma-buf/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o
dmabuf_selftests-y := \
selftest.o \
- st-dma-fence.o
+ st-dma-fence.o \
+ st-dma-fence-chain.o
obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o
diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h
index 5320386f02e5..55918ef9adab 100644
--- a/drivers/dma-buf/selftests.h
+++ b/drivers/dma-buf/selftests.h
@@ -11,3 +11,4 @@
*/
selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */
selftest(dma_fence, dma_fence)
+selftest(dma_fence_chain, dma_fence_chain)
diff --git a/drivers/dma-buf/st-dma-fence-chain.c
b/drivers/dma-buf/st-dma-fence-chain.c
new file mode 100644
index ..bd08ba67b03b
--- /dev/null
+++ b/drivers/dma-buf/st-dma-fence-chain.c
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "selftest.h"
+
+static struct kmem_cache *slab_fences;
+
+static inline struct mock_fence {
+ struct dma_fence base;
+ spinlock_t lock;
+} *to_mock_fence(struct dma_fence *f) {
+ return container_of(f, struct mock_fence, base);
+}
+
+static const char *mock_name(struct dma_fence *f)
+{
+ return "mock";
+}
+
+static void mock_fence_release(struct dma_fence *f)
+{
+ kmem_cache_free(slab_fences, to_mock_fence(f));
+}
+
+static const struct dma_fence_ops mock_ops = {
+ .get_driver_name = mock_name,
+ .get_timeline_name = mock_name,
+ .release = mock_fence_release,
+};
+
+static struct dma_fence *mock_fence(void)
+{
+ struct mock_fence *f;
+
+ f = kmem_cache_alloc(slab_fences, GFP_KERNEL);
+ if (!f)
+ return NULL;
+
+ spin_lock_init(&f->lock);
+ dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0);
+
+ return &f->base;
+}
+
+static inline struct mock_chain {
+ struct dma_fence_chain base;
+} *to_mock_chain(struct dma_fence *f) {
+ return container_of(f, struct mock_chain, base.base);
+}
+
+static struct dma_fence *mock_chain(struct dma_fence *prev,
+ struct dma_fence *fence,
+ u64 seqno)
+{
+ struct mock_chain *f;
+
+ f = kmalloc(sizeof(*f), GFP_KERNEL);
+ if (!f)
+ return NULL;
+
+ dma_fence_chain_init(&f->base,
+dma_fence_get(prev),
+dma_fence_get(fence),
+seqno);
+
+ return &f->base.base;
+}
+
+static int sanitycheck(void *arg)
+{
+ struct dma_fence *f, *chain;
+ int err = 0;
+
+ f = mock_fence();
+ if (!f)
+ return -ENOMEM;
+
+ chain = mock_chain(NULL, f, 1);
+ if (!chain)
+ err = -ENOMEM;
+
+ dma_fence_signal(f);
+ dma_fence_put(f);
+
+ dma_fence_put(chain);
+
+ return err;
+}
+
+struct fence_chains {
+ unsigned int chain_length;
+ struct dma_fence **fences;
+ struct dma_fence **chains;
+
+ struct dma_fence *tail;
+};
+
+static uint64_t seqno_inc(unsigned int i)
+{
+ return i + 1;
+}
+
+static int fence_chains_init(struct fence_chains *fc, unsigned int count,
+uint64_t (*seqno_fn)(unsigned int))
+{
+ unsigned int i;
+ int err = 0;
+
+ fc->chains = kvmalloc_array(count, sizeof(*fc->chains),
+ GFP_KERNEL | __GFP_ZERO);
+ if (!fc->chains)
+ return -ENOMEM;
+
+ fc->fences = kvmalloc_array(count, sizeof(*fc->fences),
+ GFP_KERNEL | __GFP_ZERO);
+ if (!fc->fences) {
+ err = -ENOMEM;
+ goto err_chains;
+ }
+
+ fc->tail = NULL;
+ for (i = 0; i < count; i++) {
+ fc->fences[i] = mock_fence();
+ if (!fc->fences[i]) {
+ err = -ENOMEM;
+ goto unwind;
+ }
+
+ fc->chains[i] = mock_chain(fc->tail,
+ fc->fences[i],
+ seqno_fn(i));
+ if (!fc->chains[i]) {
+ err = -ENOMEM;
+ goto unwind;
+ }
+
+ fc->tail = fc->chains[i];
+ }
[Intel-gfx] [PATCH 11/12] drm/i915/gt: Declare when we enabled timeslicing
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index b469de0dd9b6..424672ee7874 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -339,7 +339,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
return false;
- return intel_engine_has_semaphores(engine);
+ return (intel_engine_has_semaphores(engine) &&
+ intel_engine_has_preemption(engine));
}
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..b84fdd722781 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
else
disabled |= BIT(map[i].sched);
}
+
+ if (intel_engine_has_timeslices(engine))
+ enabled |= I915_SCHEDULER_CAP_TIMESLICING;
+ else
+ disabled |= I915_SCHEDULER_CAP_TIMESLICING;
}
i915->caps.scheduler = enabled & ~disabled;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3a24817ca25b..ff7be293ec31 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.20.1
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[Intel-gfx] [PATCH 12/12] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 40 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3aa8a652c16d..883a9b7fe88d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1295,6 +1295,12 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 80cdde712842..ac283ab5d89c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+ u32 yield;
+
/**
* @error_interrupt: CS Master EIR
*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ if (del_timer(&engine->execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/inte
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v7,1/3] drm/i915/perf: remove generated code
== Series Details == Series: series starting with [v7,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74767/ State : success == Summary == CI Bug Log - changes from CI_DRM_8141 -> Patchwork_16990 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/index.html Known issues Here are the changes found in Patchwork_16990 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1430] / [i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-cfl-guc/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/fi-cfl-guc/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-wf_vblank: - fi-bsw-n3050: [PASS][5] -> [FAIL][6] ([i915#34]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [INCOMPLETE][7] ([i915#189]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-icl-dsi/igt@i915_pm_...@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/fi-icl-dsi/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@execlists: - fi-cfl-8700k: [INCOMPLETE][9] ([i915#656]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (47 -> 42) -- Additional (1): fi-kbl-7560u Missing(6): fi-tgl-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8141 -> Patchwork_16990 CI-20190529: 20190529 CI_DRM_8141: f7be958f2574d30bad18983c3afe2c5401674dfb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5513: 417c926459dacf062f2945d3ba01a3f94551b16f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16990: ab46c9416005df7020efc6e5b516486f7e4409e7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ab46c9416005 drm/i915/perf: introduce global sseu pinning 1623895d809c drm/i915/perf: remove redundant power configuration register override dfa8113ae277 drm/i915/perf: remove generated code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] Revert "drm/i915/gem: Drop relocation slowpath"
This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
slowpath"). We need the slowpath relocation for taking ww-mutex
inside the page fault handler, and we will take this mutex when
pinning all objects.
Cc: Chris Wilson
Cc: Matthew Auld
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 239 +-
1 file changed, 235 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..0893ce781a84 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1440,7 +1440,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
* we would try to acquire the struct mutex again. Obviously
* this is bad and so lockdep complains vehemently.
*/
- copied = __copy_from_user(r, urelocs, count * sizeof(r[0]));
+ pagefault_disable();
+ copied = __copy_from_user_inatomic(r, urelocs, count *
sizeof(r[0]));
+ pagefault_enable();
if (unlikely(copied)) {
remain = -EFAULT;
goto out;
@@ -1490,6 +1492,236 @@ static int eb_relocate_vma(struct i915_execbuffer *eb,
struct eb_vma *ev)
return remain;
}
+static int
+eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev)
+{
+ const struct drm_i915_gem_exec_object2 *entry = ev->exec;
+ struct drm_i915_gem_relocation_entry *relocs =
+ u64_to_ptr(typeof(*relocs), entry->relocs_ptr);
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < entry->relocation_count; i++) {
+ u64 offset = eb_relocate_entry(eb, ev, &relocs[i]);
+
+ if ((s64)offset < 0) {
+ err = (int)offset;
+ goto err;
+ }
+ }
+ err = 0;
+err:
+ reloc_cache_reset(&eb->reloc_cache);
+ return err;
+}
+
+static int check_relocations(const struct drm_i915_gem_exec_object2 *entry)
+{
+ const char __user *addr, *end;
+ unsigned long size;
+ char __maybe_unused c;
+
+ size = entry->relocation_count;
+ if (size == 0)
+ return 0;
+
+ if (size > N_RELOC(ULONG_MAX))
+ return -EINVAL;
+
+ addr = u64_to_user_ptr(entry->relocs_ptr);
+ size *= sizeof(struct drm_i915_gem_relocation_entry);
+ if (!access_ok(addr, size))
+ return -EFAULT;
+
+ end = addr + size;
+ for (; addr < end; addr += PAGE_SIZE) {
+ int err = __get_user(c, addr);
+ if (err)
+ return err;
+ }
+ return __get_user(c, end - 1);
+}
+
+static int eb_copy_relocations(const struct i915_execbuffer *eb)
+{
+ struct drm_i915_gem_relocation_entry *relocs;
+ const unsigned int count = eb->buffer_count;
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < count; i++) {
+ const unsigned int nreloc = eb->exec[i].relocation_count;
+ struct drm_i915_gem_relocation_entry __user *urelocs;
+ unsigned long size;
+ unsigned long copied;
+
+ if (nreloc == 0)
+ continue;
+
+ err = check_relocations(&eb->exec[i]);
+ if (err)
+ goto err;
+
+ urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr);
+ size = nreloc * sizeof(*relocs);
+
+ relocs = kvmalloc_array(size, 1, GFP_KERNEL);
+ if (!relocs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ /* copy_from_user is limited to < 4GiB */
+ copied = 0;
+ do {
+ unsigned int len =
+ min_t(u64, BIT_ULL(31), size - copied);
+
+ if (__copy_from_user((char *)relocs + copied,
+(char __user *)urelocs + copied,
+len))
+ goto end;
+
+ copied += len;
+ } while (copied < size);
+
+ /*
+* As we do not update the known relocation offsets after
+* relocating (due to the complexities in lock handling),
+* we need to mark them as invalid now so that we force the
+* relocation processing next time. Just in case the target
+* object is evicted and then rebound into its old
+* presumed_offset before the next execbuffer - if that
+* happened we would make the mistake of assuming that the
+* relocations were valid.
+*/
+ if (!user_access_begin
Re: [Intel-gfx] [PATCH] Revert "drm/i915/gem: Drop relocation slowpath"
Quoting Maarten Lankhorst (2020-03-17 12:35:46)
> This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
> slowpath"). We need the slowpath relocation for taking ww-mutex
> inside the page fault handler, and we will take this mutex when
> pinning all objects.
Don't hold an exclusive lock across the relocation path; it's not
required.
-Chris
___
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2) URL : https://patchwork.freedesktop.org/series/74759/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Revert "drm/i915/gem: Drop relocation slowpath"
Op 17-03-2020 om 13:38 schreef Chris Wilson:
> Quoting Maarten Lankhorst (2020-03-17 12:35:46)
>> This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation
>> slowpath"). We need the slowpath relocation for taking ww-mutex
>> inside the page fault handler, and we will take this mutex when
>> pinning all objects.
> Don't hold an exclusive lock across the relocation path; it's not
> required.
> -Chris
Is -EAGAIN the only sign we need to drop locks for mmap or former slowpath
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2)
== Series Details ==
Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2)
URL : https://patchwork.freedesktop.org/series/74759/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8141 -> Patchwork_16991
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16991:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-ehl-1/igt@i915_selftest@l...@execlists.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-ehl-1/igt@i915_selftest@l...@execlists.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-ehl-1/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_16991 that come from known issues:
### IGT changes ###
Issues hit
* igt@fbdev@mmap:
- fi-kbl-7500u: [PASS][4] -> [SKIP][5] ([fdo#109271])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-kbl-7500u/igt@fb...@mmap.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-kbl-7500u/igt@fb...@mmap.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([fdo#111407])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [INCOMPLETE][8] ([i915#189]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@execlists:
- fi-cfl-8700k: [INCOMPLETE][10] ([i915#656]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (47 -> 36)
--
Additional (1): fi-kbl-7560u
Missing(12): fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-byt-squawks
fi-bsw-cyan fi-bwr-2160 fi-cfl-guc fi-gdg-551 fi-skl-lmem fi-byt-clapper
fi-bsw-nick fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8141 -> Patchwork_16991
CI-20190529: 20190529
CI_DRM_8141: f7be958f2574d30bad18983c3afe2c5401674dfb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5513: 417c926459dacf062f2945d3ba01a3f94551b16f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16991: 3ac212a31ac487c6cb1b1e72ca02963e9e008551 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3ac212a31ac4 drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/index.html
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf
== Series Details ==
Series: series starting with [01/12] drm/i915/selftests: Add request throughput
measurement to perf
URL : https://patchwork.freedesktop.org/series/74769/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0d574449054f drm/i915/selftests: Add request throughput measurement to perf
-:96: WARNING:LINE_SPACING: Missing a blank line after declarations
#96: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1519:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:130: WARNING:LINE_SPACING: Missing a blank line after declarations
#130: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1553:
+ struct i915_request *prev = NULL;
+ IGT_TIMEOUT(end_time);
-:165: WARNING:LINE_SPACING: Missing a blank line after declarations
#165: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1588:
+ struct perf_series *ps = arg;
+ IGT_TIMEOUT(end_time);
-:188: WARNING:LINE_SPACING: Missing a blank line after declarations
#188: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1611:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:196: WARNING:LINE_SPACING: Missing a blank line after declarations
#196: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1619:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:325: WARNING:LINE_SPACING: Missing a blank line after declarations
#325: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1748:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:393: WARNING:LINE_SPACING: Missing a blank line after declarations
#393: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1816:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:462: WARNING:LINE_SPACING: Missing a blank line after declarations
#462: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1885:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:518: WARNING:LINE_SPACING: Missing a blank line after declarations
#518: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1941:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:526: WARNING:LINE_SPACING: Missing a blank line after declarations
#526: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1949:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:571: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc
(sched/core.c)
#571: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1994:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 11 warnings, 0 checks, 611 lines checked
22069998921a drm/i915: Wrap i915_active in a simple kreffed struct
da8602561652 drm/i915/perf: Schedule oa_config after modifying the contexts
27864e4415fc dma-buf: Prettify typecasts for dma-fence-chain
e72f695e0d59 dma-buf: Report signaled links inside dma-fence-chain
6fb945deb41e dma-buf: Exercise dma-fence-chain under selftests
-:33: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#33:
new file mode 100644
-:61: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#61: FILE: drivers/dma-buf/st-dma-fence-chain.c:24:
+ spinlock_t lock;
-:235: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#235: FILE: drivers/dma-buf/st-dma-fence-chain.c:198:
+ pr_err("Reported %d for find_seqno(0)!\n", err);
-:244: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#244: FILE: drivers/dma-buf/st-dma-fence-chain.c:207:
+ pr_err("Reported %d for find_seqno(%d:%d)!\n",
-:249: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#249: FILE: drivers/dma-buf/st-dma-fence-chain.c:212:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:272: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#272: FILE: drivers/dma-buf/st-dma-fence-chain.c:235:
+ pr_err("Error not reported for future fence:
find_seqno(%d:%d)!\n",
-:286: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'find_seqno', this function's name, in a string
#286: FILE: drivers/dma-buf/st-dma-fence-chain.c:249:
+ pr_err("Incorrect fence reported by
find_seqno(%d:%d)\n",
-:737: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to
using 'dma_fence_chain', this function's name, in a string
#737: FILE: drivers/dma-buf/st-dma-fence-chain.c:700:
+ pr_info("sizeof(dma_fence_chain)=%zu\n",
total: 0 errors, 7 warnings, 1 checks, 725 lines checked
c3e54c28d94e dma-buf: Proxy fence, an unsignaled fence placeholder
Re: [Intel-gfx] [PATCH v1 1/3] drm/i915: Decouple cdclk calculation from modeset checks
On Mon, Mar 16, 2020 at 01:37:42PM +0200, Stanislav Lisovskiy wrote:
> We need to calculate cdclk after watermarks/ddb has been calculated
> as with recent hw CDCLK needs to be adjusted accordingly to DBuf
> requirements, which is not possible with current code organization.
>
> Setting CDCLK according to DBuf BW requirements and not just rejecting
> if it doesn't satisfy BW requirements, will allow us to save power when
> it is possible and gain additional bandwidth when it's needed - i.e
> boosting both our power management and perfomance capabilities.
>
> This patch is preparation for that, first we now extract modeset
> calculation from modeset checks, in order to call it after wm/ddb
> has been calculated.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 22
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8f23c4d51c33..cdff3054b344 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14542,6 +14542,14 @@ static int intel_modeset_checks(struct
> intel_atomic_state *state)
> return ret;
> }
>
> + return 0;
> +}
> +
> +static int intel_modeset_cdclk(struct intel_atomic_state *state)
> +{
Misleading name here since you didn't extract just the cdclk part.
IMO just move intel_modeset_calc_cdclk() alone out from
intel_modeset_checks(), and keep the reordering minimal in that
patch. Ie. just call intel_modeset_calc_cdclk() right after
intel_modeset_checks().
Then in the next patch you can do the
intel_modeset_calc_cdclk()+intel_atomic_check_crtcs() vs. wm reorder.
The two things that currently need cdclk in intel_crtc_atomic_check()
would appear to be ips and linetime watermarks. The rest looks like
safe to reorder.
Though at least one thing that I think is totally misplaced is the
.crtc_compute_clock() call. That really should be done much earlier,
even earlier than where it is now. However since it doesn't
adjust .crtc_clock with the results of the computation doesn't really
matter for now. So looks like we can ignore this particular mess
for now.
>
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + int ret;
> +
> ret = intel_modeset_calc_cdclk(state);
> if (ret)
> return ret;
> @@ -14879,10 +14887,6 @@ static int intel_atomic_check(struct drm_device *dev,
> goto fail;
> }
>
> - ret = intel_atomic_check_crtcs(state);
> - if (ret)
> - goto fail;
> -
> intel_fbc_choose_crtc(dev_priv, state);
> ret = calc_watermark_data(state);
> if (ret)
> @@ -14892,6 +14896,16 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> + if (any_ms) {
> + ret = intel_modeset_cdclk(state);
> + if (ret)
> + goto fail;
> + }
> +
> + ret = intel_atomic_check_crtcs(state);
> + if (ret)
> + goto fail;
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state) &&
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v8 1/3] drm/i915/perf: remove generated code
A little bit of history :
Back when i915-perf was introduced (4.13), there was no way to
dynamically add new OA configurations to i915. Only the generated
configs baked in at build time were allowed.
It quickly became obvious that we would need to allow applications
to upload their own configurations, for instance to be able to test
new ones, and so by the next stable version (4.14) we added uAPIs
to allow uploading new configurations.
When adding that capability, we took the opportunity to remove most
HW configurations except the TestOa one which is a configuration
IGT would rely on to verify that the HW is outputting correct
values. At the time it made sense to have that confiuration in at
the same time a given HW platform added to the i915-perf driver.
Now that IGT has become the reference point for HW configurations (see
commit 53f8f541ca ("lib: Add i915_perf library"), previously this was
located in the GPUTop repository), the need for having those
configurations in i915-perf is gone.
On the Mesa side, we haven't relied on this test configuration for a
while. The MDAPI library always required 4.14 feature level and always
loaded its configuration into i915.
I'm sure nobody will miss this generated stuff in i915 :)
v2: Fix selftests by creating an empty config
v3: Fix unlocking on allocation error (Dan Carpenter)
v4: Fixup checkpatch warnings
v5: Fix incorrect unlock in error path (Umesh)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/Makefile | 17 ---
drivers/gpu/drm/i915/i915_perf.c | 81 +-
drivers/gpu/drm/i915/i915_perf_types.h | 2 -
drivers/gpu/drm/i915/oa/i915_oa_bdw.c | 90 ---
drivers/gpu/drm/i915/oa/i915_oa_bdw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_bxt.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_chv.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_cnl.c | 101 -
drivers/gpu/drm/i915/oa/i915_oa_cnl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_glk.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_hsw.c | 118
drivers/gpu/drm/i915/oa/i915_oa_hsw.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_icl.c | 98 -
drivers/gpu/drm/i915/oa/i915_oa_icl.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c | 88 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c | 89 ---
drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h | 16 ---
drivers/gpu/drm/i915/oa/i915_oa_tgl.c | 121 -
drivers/gpu/drm/i915/oa/i915_oa_tgl.h | 16 ---
drivers/gpu/drm/i915/selftests/i915_perf.c | 98 -
34 files changed, 96 insertions(+), 1757 deletions(-)
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bdw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_bxt.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_chv.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_cnl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_glk.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_hsw.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_icl.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h
delete mode 100644 drivers/gpu/drm/i915/oa/i915_oa_s
[Intel-gfx] [PATCH v8 3/3] drm/i915/perf: introduce global sseu pinning
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power configuration to maintain its configuration.
As a result using OA (and NOA feeding into it) so far has required us
to use a power configuration that can work for all contexts. The only
power configuration fullfilling this is powergating half the execution
units.
This makes performance analysis for 3D workloads somewhat pointless.
Failing to find a solution that would work for everybody, this change
introduces a new i915-perf stream open parameter that punts the
decision off to userspace. If this parameter is omitted, the existing
Gen11 behavior remains (half EU array powergating).
This change takes the initiative to move all perf related sseu
configuration into i915_perf.c
v2: Make parameter priviliged if different from default
v3: Fix context modifying its sseu config while i915-perf is enabled
v4: Always consider global sseu a privileged operation (Tvrtko)
Override req_sseu point in intel_sseu_make_rpcs() (Tvrtko)
Remove unrelated changes (Tvrtko)
v5: Some typos (Tvrtko)
Process sseu param in read_properties_unlocked() (Tvrtko)
v6: Actually commit the bits from v5...
Fixup some checkpath warnings
v7: Only compare engine uabi field (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 10 +--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 4 ++
drivers/gpu/drm/i915/gt/intel_sseu.c| 33 ++---
drivers/gpu/drm/i915/i915_perf.c| 76 -
drivers/gpu/drm/i915/i915_perf_types.h | 7 ++
include/uapi/drm/i915_drm.h | 11 +++
6 files changed, 108 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 026999b34abd..c0e476fcd1fa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1401,10 +1401,10 @@ static int get_ringsize(struct i915_gem_context *ctx,
return 0;
}
-static int
-user_to_context_sseu(struct drm_i915_private *i915,
-const struct drm_i915_gem_context_param_sseu *user,
-struct intel_sseu *context)
+int
+i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+ const struct drm_i915_gem_context_param_sseu
*user,
+ struct intel_sseu *context)
{
const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu;
@@ -1539,7 +1539,7 @@ static int set_sseu(struct i915_gem_context *ctx,
goto out_ce;
}
- ret = user_to_context_sseu(i915, &user_sseu, &sseu);
+ ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu);
if (ret)
goto out_ce;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h
b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index f1d884d304bd..3702b2fb27ab 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -225,4 +225,8 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter
*it);
struct i915_lut_handle *i915_lut_handle_alloc(void);
void i915_lut_handle_free(struct i915_lut_handle *lut);
+int i915_gem_user_to_context_sseu(struct drm_i915_private *i915,
+ const struct drm_i915_gem_context_param_sseu
*user,
+ struct intel_sseu *context);
+
#endif /* !__I915_GEM_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 74f793423231..d173271c7397 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -65,7 +65,6 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
{
const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
bool subslice_pg = sseu->has_subslice_pg;
- struct intel_sseu ctx_sseu;
u8 slices, subslices;
u32 rpcs = 0;
@@ -78,31 +77,13 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
/*
* If i915/perf is active, we want a stable powergating configuration
-* on the system.
-*
-* We could choose full enablement, but on ICL we know there are use
-* cases which disable slices for functional, apart for performance
-* reasons. So in this case we select a known stable subset.
+* on the system. Use the configuration pinned by i915/perf.
*/
- if (!i915->perf.exclusive_stream) {
- ctx_sseu = *req_sseu;
- } else {
- ctx_sseu = intel_sseu_from_device_info(sseu);
-
- if (IS_GEN(i915, 11)) {
- /*
-* We only need subslice co
[Intel-gfx] [PATCH v8 2/3] drm/i915/perf: remove redundant power configuration register override
The caller of i915_oa_init_reg_state() already sets this.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_perf.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0069f09b988c..86c6abaa3e0e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2098,9 +2098,6 @@ gen8_update_reg_state_unlocked(const struct intel_context
*ce,
for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
reg_state[ctx_flexeu0 + i * 2 + 1] =
oa_config_flex_reg(stream->oa_config, flex_regs[i]);
-
- reg_state[CTX_R_PWR_CLK_STATE] =
- intel_sseu_make_rpcs(ce->engine->i915, &ce->sseu);
}
struct flex {
@@ -2906,10 +2903,6 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
/* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
stream = READ_ONCE(engine->i915->perf.exclusive_stream);
- /*
-* For gen12, only CTX_R_PWR_CLK_STATE needs update, but the caller
-* is already doing that, so nothing to be done for gen12 here.
-*/
if (stream && INTEL_GEN(stream->perf->i915) < 12)
gen8_update_reg_state_unlocked(ce, stream);
}
--
2.25.1
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf
== Series Details == Series: series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf URL : https://patchwork.freedesktop.org/series/74769/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf
== Series Details == Series: series starting with [01/12] drm/i915/selftests: Add request throughput measurement to perf URL : https://patchwork.freedesktop.org/series/74769/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8141 -> Patchwork_16992 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16992 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16992, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16992/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16992: ### IGT changes ### Possible regressions * igt@i915_selftest@live@execlists: - fi-kbl-x1275: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16992/fi-kbl-x1275/igt@i915_selftest@l...@execlists.html New tests - New tests have been introduced between CI_DRM_8141 and Patchwork_16992: ### New IGT tests (2) ### * igt@dmabuf@all@dma_fence_chain: - Statuses : 34 pass(s) - Exec time: [7.70, 31.87] s * igt@dmabuf@all@dma_fence_proxy: - Statuses : 34 pass(s) - Exec time: [0.03, 0.12] s Known issues Here are the changes found in Patchwork_16992 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927] / [i915#656]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16992/fi-bxt-dsi/igt@i915_selftest@l...@execlists.html Possible fixes * igt@i915_selftest@live@execlists: - fi-cfl-8700k: [INCOMPLETE][5] ([i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16992/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (47 -> 37) -- Additional (1): fi-kbl-7560u Missing(11): fi-bdw-samus fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-ilk-650 fi-elk-e7500 fi-blb-e6850 fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8141 -> Patchwork_16992 CI-20190529: 20190529 CI_DRM_8141: f7be958f2574d30bad18983c3afe2c5401674dfb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5513: 417c926459dacf062f2945d3ba01a3f94551b16f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16992: 70b9d252dbbd0c6e03c8e8057d8889227bf8df09 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 70b9d252dbbd drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore 33b7b12c8b42 drm/i915/gt: Declare when we enabled timeslicing 93996f119438 drm/i915/gem: Allow combining submit-fences with syncobj 25c7bc564fc2 drm/i915/gem: Teach execbuf how to wait on future syncobj 9a241d62343d drm/syncobj: Allow use of dma-fence-proxy c3e54c28d94e dma-buf: Proxy fence, an unsignaled fence placeholder 6fb945deb41e dma-buf: Exercise dma-fence-chain under selftests e72f695e0d59 dma-buf: Report signaled links inside dma-fence-chain 27864e4415fc dma-buf: Prettify typecasts for dma-fence-chain da8602561652 drm/i915/perf: Schedule oa_config after modifying the contexts 22069998921a drm/i915: Wrap i915_active in a simple kreffed struct 0d574449054f drm/i915/selftests: Add request throughput measurement to perf == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16992/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details == Series: Revert "drm/i915/gem: Drop relocation slowpath" URL : https://patchwork.freedesktop.org/series/74771/ State : warning == Summary == $ dim checkpatch origin/drm-tip d42d74d4a36d Revert "drm/i915/gem: Drop relocation slowpath" -:78: WARNING:LINE_SPACING: Missing a blank line after declarations #78: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1539: + int err = __get_user(c, addr); + if (err) total: 0 errors, 1 warnings, 0 checks, 257 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs
On Tue, Mar 17, 2020 at 12:43:38AM +0200, Stanislav Lisovskiy wrote:
> According to BSpec max BW per slice is calculated using formula
> Max BW = CDCLK * 64. Currently when calculating min CDCLK we
> account only per plane requirements, however in order to avoid
> FIFO underruns we need to estimate accumulated BW consumed by
> all planes(ddb entries basically) residing on that particular
> DBuf slice. This will allow us to put CDCLK lower and save power
> when we don't need that much bandwidth or gain additional
> performance once plane consumption grows.
>
> v2: - Fix long line warning
> - Limited new DBuf bw checks to only gens >= 11
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 46 +++
> drivers/gpu/drm/i915/display/intel_bw.h | 1 +
> drivers/gpu/drm/i915/display/intel_cdclk.c| 25 ++
> drivers/gpu/drm/i915/display/intel_display.c | 10 +++-
> .../drm/i915/display/intel_display_power.h| 1 +
> drivers/gpu/drm/i915/intel_pm.c | 34 +-
> drivers/gpu/drm/i915/intel_pm.h | 3 ++
> 7 files changed, 117 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..a85125110d7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -6,6 +6,7 @@
> #include
>
> #include "intel_bw.h"
> +#include "intel_pm.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
>
> @@ -334,6 +335,51 @@ static unsigned int intel_bw_crtc_data_rate(const struct
> intel_crtc_state *crtc_
> return data_rate;
> }
>
> +int intel_bw_calc_min_cdclk(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + int max_bw_per_dbuf[DBUF_SLICE_MAX];
> + int i = 0;
> + enum plane_id plane_id;
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> + int max_bw = 0;
> + int min_cdclk;
> +
> + memset(max_bw_per_dbuf, 0, sizeof(max_bw_per_dbuf[0]) * DBUF_SLICE_MAX);
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_ddb_entry *plane_alloc =
> + &crtc_state->wm.skl.plane_ddb_y[plane_id];
> + struct skl_ddb_entry *uv_plane_alloc =
> + &crtc_state->wm.skl.plane_ddb_uv[plane_id];
> + unsigned int data_rate =
> crtc_state->data_rate[plane_id];
> + int slice_id = 0;
> + u32 dbuf_mask = skl_ddb_dbuf_slice_mask(dev_priv,
> plane_alloc);
> +
> + dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv,
> uv_plane_alloc);
> +
> + DRM_DEBUG_KMS("Got dbuf mask %x for pipe %c ddb %d-%d
> plane %d data rate %d\n",
> + dbuf_mask, pipe_name(crtc->pipe),
> plane_alloc->start,
> + plane_alloc->end, plane_id, data_rate);
> +
> + while (dbuf_mask != 0) {
> + if (dbuf_mask & 1) {
> + max_bw_per_dbuf[slice_id] += data_rate;
> + max_bw = max(max_bw,
> max_bw_per_dbuf[slice_id]);
> + }
> + slice_id++;
> + dbuf_mask >>= 1;
> + }
> + }
> + }
Something like?
for_each_plane_id() {
for_each_dbuf_slice() {
skl_ddb_entry_for_slices(BIT(slice), &ddb_slice);
if (skl_ddb_entries_overlap(&ddb_slice, &ddb[plane_id])))
bw[slice] += data_rate;
}
}
But this seems to borked anyway since we only consider the crtcs in the
state, and there are those ugly FIXMEs below.
I have a feeling what we want is dbuf_state, and track the bw used for
each slice therein. Should also allow us to flag the cdclk recalculation
only when things actually change in a way that needs more cdclk, instead
of pessimising every plane enable/disable like you do below.
> +
> + min_cdclk = max_bw / 64;
> +
> + return min_cdclk;
> +}
> +
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index a8aa7624c5aa..8a522b571c51 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -29,5 +29,6 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>
[Intel-gfx] [PATCH v9] drm/i915/color: Extract icl_read_luts()
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
v2: -readout code for multisegmented gamma has to come
up with some intermediate entries that aren't preserved
in hardware (Jani N)
-linear interpolation (Ville)
-moved common code to check gamma_enable to specific funcs,
since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
-used single lut [Jani N]
-improved and more readable for loops [Jani N]
-read values directly to actual locations and then fill gaps [Jani N]
-moved cleaning to patch 1 [Jani N]
-renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
make it similar to icl_load_luts()
-renamed icl_compute_interpolated_gamma_blob() to
icl_compute_interpolated_gamma_lut_values() more sensible, I guess
v4: -removed interpolated func for creating gamma lut values
-removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA
correctly
v5: -added gamma_enable check inside read_luts()
v6: -renamed intel_color_lut_entry_equal() to intel_color_lut_entries_equal()
[Ville]
-changed if-else to switch [Ville]
-removed intel_color_lut_entry_multi_equal() [Ville]
v7: -checkpatch warnings
v8: -rebased
v9: -rebased, aligned with Ville's style of gamma cleanup
Signed-off-by: Swati Sharma
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_color.c | 121 ++---
drivers/gpu/drm/i915/i915_reg.h| 6 +
2 files changed, 109 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index c1cce93a1c25..98ece9cd7cdd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -460,6 +460,16 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry,
u32 val)
entry->blue =
intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
}
+static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32
udw)
+{
+ entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
+ entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) <<
6 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6
|
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -893,7 +903,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
- /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
+ /* FIXME LUT entries are 16 bit only, so we can prog 0x max */
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
@@ -1630,6 +1640,24 @@ static int glk_gamma_precision(const struct
intel_crtc_state *crtc_state)
}
}
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1641,7 +1669,9 @@ int intel_color_get_gamma_bit_precision(const struct
intel_crtc_state *crtc_stat
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -1658,9 +1688,9 @@ static bool err_check(struct d
Re: [Intel-gfx] [PATCH] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
Hi Chris,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20200316]
[cannot apply to v5.6-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-gem-Avoid-gem_context-mutex-for-simple-vma-lookup/20200317-110430
base: git://anongit.freedesktop.org/drm-intel for-linux-next
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot
Reported-by: Dan Carpenter
New smatch warnings:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:815 eb_lookup_vmas() error:
uninitialized symbol 'obj'.
Old smatch warnings:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c: reloc_move_to_gpu() warn:
maybe use && instead of &
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1599 eb_move_to_gpu() warn:
maybe use && instead of &
drivers/gpu/drm/i915/gem/i915_gem_context.h:201 i915_gem_context_get_engine()
warn: inconsistent indenting
drivers/gpu/drm/i915/gem/i915_gem_context.h:203 i915_gem_context_get_engine()
warn: inconsistent indenting
#
https://github.com/0day-ci/linux/commit/88e913b4b889b5b70ae708967ff75a04527b50af
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 88e913b4b889b5b70ae708967ff75a04527b50af
vim +/obj +815 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
2889caa9232109 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-16 731 static int eb_lookup_vmas(struct i915_execbuffer *eb)
3b96eff447b4ca drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2013-01-08 732 {
8f2a1057d6ec21 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2019-04-25 733 struct radix_tree_root *handles_vma =
&eb->gem_context->handles_vma;
ac70ebe873f516 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-09-12 734 struct drm_i915_gem_object *obj;
Uninitialized
746c8f143afad7 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2018-06-10 735 unsigned int i, batch;
2889caa9232109 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-16 736 int err;
3b96eff447b4ca drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2013-01-08 737
003d8b9143a69f drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-03 738 if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
003d8b9143a69f drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-03 739 return -ENOENT;
003d8b9143a69f drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-03 740
2889caa9232109 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-16 741 INIT_LIST_HEAD(&eb->relocs);
2889caa9232109 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-16 742 INIT_LIST_HEAD(&eb->unbound);
d55495b4dcce2e drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-15 743
746c8f143afad7 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2018-06-10 744 batch = eb_batch_index(eb);
746c8f143afad7 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2018-06-10 745
170fa29b14fadf drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-08-16 746 for (i = 0; i < eb->buffer_count; i++) {
170fa29b14fadf drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-08-16 747 u32 handle = eb->exec[i].handle;
d1b48c1e7184d9 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-08-16 748 struct i915_lut_handle *lut;
170fa29b14fadf drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-08-16 749 struct i915_vma *vma;
4ff4b44cbb70c2 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-06-16 750
88e913b4b889b5 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-16 751 lookup:
88e913b4b889b5 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-16 752 rcu_read_lock();
d1b48c1e7184d9 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson
2017-08-16 753 vma = radix_tree_lookup(handles_vma, handle);
88e913b4b889b5 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-16 754 if (likely(vma))
88e913b4b889b5 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
2020-03-16 755 vma = i915_vma_tryget(vma);
88e913b4b889b5 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Chris Wilson
20
[Intel-gfx] ✗ Fi.CI.DOCS: warning for Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details == Series: Revert "drm/i915/gem: Drop relocation slowpath" URL : https://patchwork.freedesktop.org/series/74771/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests (rev2)
I had to re-report more than once as there were many issues. All good now.
Thanks,
Lakshmi.
-Original Message-
From: Latvala, Petri
Sent: Tuesday, March 17, 2020 12:40 PM
To: Janusz Krzysztofik ; Vudum,
Lakshminarayana
Cc: igt-...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits:
Refresh other now MMAP_GTT dependent subtests (rev2)
Lakshmi, see below.
On Tue, Mar 17, 2020 at 09:53:51AM +0100, Janusz Krzysztofik wrote:
> Hi,
>
> On Mon, 2020-03-16 at 19:25 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent
> > subtests (rev2)
> > URL : https://patchwork.freedesktop.org/series/74201/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_8137_full -> IGTPW_4307_full
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
>
> False positive, see below.
>
> > Serious unknown changes coming with IGTPW_4307_full absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in IGTPW_4307_full, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in
> > CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/index.html
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> > IGTPW_4307_full:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@gem_ctx_shared@single-timeline:
> > - shard-snb: NOTRUN -> [FAIL][1]
> >[1]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb4/igt@gem_ctx_sha...@single-timeline.html
> > - shard-hsw: NOTRUN -> [FAIL][2] +1 similar issue
> >[2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@g
> > em_ctx_sha...@single-timeline.html
> >
> > * igt@gem_exec_fence@basic-await@vcs0:
> > - shard-kbl: [PASS][3] -> [FAIL][4] +3 similar issues
> >[3]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl1/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-kbl7/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-iclb: [PASS][5] -> [FAIL][6]
> >[5]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb5/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-apl: [PASS][7] -> [FAIL][8] +2 similar issues
> >[7]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[8]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-glk: [PASS][9] -> [FAIL][10] +2 similar issues
> >[9]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk6/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[10]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-glk4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > - shard-tglb: [PASS][11] -> [FAIL][12] +2 similar issues
> >[11]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb6/igt@gem_exec_fence@basic-aw...@vcs0.html
> >[12]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@
> > gem_exec_fence@basic-aw...@vcs0.html
>
> Not related.
>
> >
> > * {igt@gem_userptr_blits@process-exit-mmap-busy@gtt} (NEW):
> > - shard-iclb: NOTRUN -> [SKIP][13] +7 similar issues
> >[13]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb3/igt@
> > gem_userptr_blits@process-exit-mmap-b...@gtt.html
> >
> > * {igt@gem_userptr_blits@process-exit-mmap-busy@uc} (NEW):
> > - shard-tglb: NOTRUN -> [SKIP][14] +11 similar issues
> >[14]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@
> > gem_userptr_blits@process-exit-mmap-b...@uc.html
>
> Expected behavior.
>
> >
> > * igt@gem_wait@wait-rcs0:
> > - shard-hsw: [PASS][15] -> [FAIL][16]
> >[15]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@gem_w...@wait-rcs0.html
> >[16]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@g
> > em_w...@wait-rcs0.html
> >
> > * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic:
> > - shard-snb: [PASS][17] -> [FAIL][18] +1 similar issue
> >[17]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-snb2/igt@kms_cursor_leg...@flip-vs-cursor-busy-crc-atomic.html
> >[18]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-sn
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details == Series: Revert "drm/i915/gem: Drop relocation slowpath" URL : https://patchwork.freedesktop.org/series/74771/ State : success == Summary == CI Bug Log - changes from CI_DRM_8141 -> Patchwork_16993 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/index.html Known issues Here are the changes found in Patchwork_16993 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#323]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@i915_pm_rpm@module-reload: - fi-icl-dsi: [INCOMPLETE][3] ([i915#189]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-icl-dsi/igt@i915_pm_...@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/fi-icl-dsi/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@execlists: - fi-cfl-8700k: [INCOMPLETE][5] ([i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/fi-cfl-8700k/igt@i915_selftest@l...@execlists.html [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (47 -> 42) -- Additional (1): fi-kbl-7560u Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8141 -> Patchwork_16993 CI-20190529: 20190529 CI_DRM_8141: f7be958f2574d30bad18983c3afe2c5401674dfb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5513: 417c926459dacf062f2945d3ba01a3f94551b16f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16993: d42d74d4a36ddf371ee31de8cb126c9e1f8569ea @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d42d74d4a36d Revert "drm/i915/gem: Drop relocation slowpath" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
As we store the handle lookup inside a radix tree, we do not need the
gem_context->mutex except until we need to insert our lookup into the
common radix tree. This takes a small bit of rearranging to ensure that
the lut we insert into the tree is ready prior to actually inserting it
(as soon as it is exposed via the radixtree, it is visible to any other
submission).
v2: For brownie points, remove the goto spaghetti.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 129 +++---
1 file changed, 80 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..e9279ef27259 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -481,7 +481,7 @@ eb_add_vma(struct i915_execbuffer *eb,
GEM_BUG_ON(i915_vma_is_closed(vma));
- ev->vma = i915_vma_get(vma);
+ ev->vma = vma;
ev->exec = entry;
ev->flags = entry->flags;
@@ -728,77 +728,110 @@ static int eb_select_context(struct i915_execbuffer *eb)
return 0;
}
-static int eb_lookup_vmas(struct i915_execbuffer *eb)
+static int __eb_add_lut(struct i915_gem_context *ctx,
+ u32 handle, struct i915_vma *vma)
{
- struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
- struct drm_i915_gem_object *obj;
- unsigned int i, batch;
+ struct drm_i915_gem_object *obj = vma->obj;
+ struct i915_lut_handle *lut;
int err;
- if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
- return -ENOENT;
+ lut = i915_lut_handle_alloc();
+ if (unlikely(!lut))
+ return -ENOMEM;
- INIT_LIST_HEAD(&eb->relocs);
- INIT_LIST_HEAD(&eb->unbound);
+ i915_vma_get(vma);
+ if (!atomic_fetch_inc(&vma->open_count))
+ i915_vma_reopen(vma);
+ lut->handle = handle;
+ lut->ctx = ctx;
+
+ err = -EINTR;
+ if (!mutex_lock_interruptible(&ctx->mutex)) {
+ err = -ENOENT;
+ if (likely(!i915_gem_context_is_closed(ctx)))
+ err = radix_tree_insert(&ctx->handles_vma, handle, vma);
+ mutex_unlock(&ctx->mutex);
+ }
+ if (unlikely(err))
+ goto err;
- batch = eb_batch_index(eb);
+ i915_gem_object_lock(obj);
+ list_add(&lut->obj_link, &obj->lut_list);
+ i915_gem_object_unlock(obj);
- for (i = 0; i < eb->buffer_count; i++) {
- u32 handle = eb->exec[i].handle;
- struct i915_lut_handle *lut;
+ return 0;
+
+err:
+ atomic_dec(&vma->open_count);
+ i915_vma_put(vma);
+ i915_lut_handle_free(lut);
+ return err;
+}
+
+static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
+{
+ struct i915_gem_context *ctx = eb->gem_context;
+
+ do {
+ struct drm_i915_gem_object *obj;
struct i915_vma *vma;
+ int err;
- vma = radix_tree_lookup(handles_vma, handle);
+ rcu_read_lock();
+ vma = radix_tree_lookup(&ctx->handles_vma, handle);
if (likely(vma))
- goto add_vma;
+ vma = i915_vma_tryget(vma);
+ rcu_read_unlock();
+ if (likely(vma))
+ return vma;
obj = i915_gem_object_lookup(eb->file, handle);
- if (unlikely(!obj)) {
- err = -ENOENT;
- goto err_vma;
- }
+ if (unlikely(!obj))
+ return ERR_PTR(-ENOENT);
vma = i915_vma_instance(obj, eb->context->vm, NULL);
if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
+ i915_gem_object_put(obj);
+ return vma;
}
- lut = i915_lut_handle_alloc();
- if (unlikely(!lut)) {
- err = -ENOMEM;
- goto err_obj;
- }
+ err = __eb_add_lut(ctx, handle, vma);
+ if (likely(!err))
+ return vma;
- err = radix_tree_insert(handles_vma, handle, vma);
- if (unlikely(err)) {
- i915_lut_handle_free(lut);
- goto err_obj;
- }
+ i915_gem_object_put(obj);
+ if (err != -EEXIST)
+ return ERR_PTR(err);
+ } while (1);
+}
- /* transfer ref to lut */
- if (!atomic_fetch_inc(&vma->open_count))
- i915_vma_reopen(vma);
- lut->handle = handle;
- lut->ctx = eb->gem_context;
+static int eb_loo
[Intel-gfx] [CI] drm/i915: Fix up documentation paths after file moving
Redirect references to i915_gem_fence_reg.c to gt/intel_ggtt_fencing.c
Fixes: dec9cf9ee8cb ("drm/i915/gt: Pull restoration of GGTT fences underneath
the GT")
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
Documentation/gpu/i915.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index f6d363b6756e..429b08aac797 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -391,19 +391,19 @@ Global GTT views
GTT Fences and Swizzling
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
:internal:
Global GTT Fence Handling
~
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
:doc: fence register handling
Hardware Tiling and Swizzling Details
~
-.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_fence_reg.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
:doc: tiling swizzling details
Object Tiling IOCTLs
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v8,1/3] drm/i915/perf: remove generated code
== Series Details == Series: series starting with [v8,1/3] drm/i915/perf: remove generated code URL : https://patchwork.freedesktop.org/series/74773/ State : failure == Summary == Applying: drm/i915/perf: remove generated code Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/Makefile M drivers/gpu/drm/i915/i915_perf.c M drivers/gpu/drm/i915/i915_perf_types.h A drivers/gpu/drm/i915/oa/i915_oa_bdw.c A drivers/gpu/drm/i915/oa/i915_oa_bdw.h A drivers/gpu/drm/i915/oa/i915_oa_bxt.c A drivers/gpu/drm/i915/oa/i915_oa_bxt.h A drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c A drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h A drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c A drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h A drivers/gpu/drm/i915/oa/i915_oa_chv.c A drivers/gpu/drm/i915/oa/i915_oa_chv.h A drivers/gpu/drm/i915/oa/i915_oa_cnl.c A drivers/gpu/drm/i915/oa/i915_oa_cnl.h A drivers/gpu/drm/i915/oa/i915_oa_glk.c A drivers/gpu/drm/i915/oa/i915_oa_glk.h A drivers/gpu/drm/i915/oa/i915_oa_hsw.c A drivers/gpu/drm/i915/oa/i915_oa_hsw.h A drivers/gpu/drm/i915/oa/i915_oa_icl.c A drivers/gpu/drm/i915/oa/i915_oa_icl.h A drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c A drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h A drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c A drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h A drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c A drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h A drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c A drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h A drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c A drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h A drivers/gpu/drm/i915/oa/i915_oa_tgl.c A drivers/gpu/drm/i915/oa/i915_oa_tgl.h M drivers/gpu/drm/i915/selftests/i915_perf.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_perf_types.h Auto-merging drivers/gpu/drm/i915/i915_perf.c warning: inexact rename detection was skipped due to too many files. warning: you may want to set your merge.renamelimit variable to at least 67257 and retry the command. No changes -- Patch already applied. Applying: drm/i915/perf: remove redundant power configuration register override Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_perf.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_perf.c No changes -- Patch already applied. Applying: drm/i915/perf: introduce global sseu pinning Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_context.c M drivers/gpu/drm/i915/gem/i915_gem_context.h M drivers/gpu/drm/i915/gt/intel_sseu.c M drivers/gpu/drm/i915/i915_perf.c M drivers/gpu/drm/i915/i915_perf_types.h M include/uapi/drm/i915_drm.h Falling back to patching base and 3-way merge... No changes -- Patch already applied. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs
>Something like?
>for_each_plane_id() {
> for_each_dbuf_slice() {
> skl_ddb_entry_for_slices(BIT(slice), &ddb_slice);
>
>if (skl_ddb_entries_overlap(&ddb_slice, &ddb[plane_id])))
> bw[slice] += data_rate;
>}
>}
In fact even in your example this is not fully correct:
it should be then
for_each_new_crtc_in_state() => because there are multiple crtcs
for_each_plane_id() {
for_each_dbuf_slice() {
skl_ddb_entry_for_slices(BIT(slice), &ddb_slice);
if (skl_ddb_entries_overlap(&ddb_slice, &ddb[plane_id])))
bw[slice] += data_rate;
}
}
which would be in fact same complexity or even worse because in the patch
we get a mask of only used slices per plane ddb and then account for those
while here it would be iterating all slices everytime.
Slight difference but still.
I can of course make this function shorter, by implementing some helpers -
that's for sure.
>But this seems to borked anyway since we only consider the crtcs in the
>state, and there are those ugly FIXMEs below.
Those ugly FIXME's are there because of same issue that we don't
have a parent state for crtc_state in some situations.
Not this patch fault or subject in fact. We probably need some series
to somehow tackle this everywhere, so that those functions which
need intel_atomic_state can always find it.
So it is not those FIXME's in the patch which are ugly, but the code
which is calling this function, so that even though we have a crtc_state
we never now if we can have a parent atomic state, which is violating
OOP principles.
I.e it is called from intel_modeset_setup_hw_state _already_ in a hacky way.
>I have a feeling what we want is dbuf_state, and track the bw used for
>each slice therein. Should also allow us to flag the cdclk recalculation
>only when things actually change in a way that needs more cdclk, instead
>of pessimising every plane enable/disable like you do below.
I think CDCLK recalculation itself is pretty trivial - it is actually when we
really
needs to be changed, that is what we don't want to often, right?
To estimate if it needs to be flagged or not you will need exatly same code, i.e
calculating BW used per slice, while determining which ddb entries are related
to which slice.
In fact there are already IGT results(which pass) and CDCLK doesn't change too
often at all - because we change it only when we really need it otherwise
intel_crtc_compute_min_cdclk will return same value as before and nothing
changes.
If you really want so, we can start tracking it, once your dbuf_state patches
land - currently
the main problem is that we need finally a proper way to estimate CDCLK
without keeping it bumped all the time to make 8K happy, at the same time
we don't want FIFO underruns again.
Best Regards,
Lisovskiy Stanislav
From: Ville Syrjälä
Sent: Tuesday, March 17, 2020 3:46:35 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org; Ausmus, James; Saarinen, Jani; Roper,
Matthew D
Subject: Re: [PATCH v2 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw
needs
On Tue, Mar 17, 2020 at 12:43:38AM +0200, Stanislav Lisovskiy wrote:
> According to BSpec max BW per slice is calculated using formula
> Max BW = CDCLK * 64. Currently when calculating min CDCLK we
> account only per plane requirements, however in order to avoid
> FIFO underruns we need to estimate accumulated BW consumed by
> all planes(ddb entries basically) residing on that particular
> DBuf slice. This will allow us to put CDCLK lower and save power
> when we don't need that much bandwidth or gain additional
> performance once plane consumption grows.
>
> v2: - Fix long line warning
> - Limited new DBuf bw checks to only gens >= 11
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 46 +++
> drivers/gpu/drm/i915/display/intel_bw.h | 1 +
> drivers/gpu/drm/i915/display/intel_cdclk.c| 25 ++
> drivers/gpu/drm/i915/display/intel_display.c | 10 +++-
> .../drm/i915/display/intel_display_power.h| 1 +
> drivers/gpu/drm/i915/intel_pm.c | 34 +-
> drivers/gpu/drm/i915/intel_pm.h | 3 ++
> 7 files changed, 117 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..a85125110d7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -6,6 +6,7 @@
> #include
>
> #include "intel_bw.h"
> +#include "intel_pm.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
>
> @@ -334,6 +335,51 @@ static unsigned int intel_bw_crtc_data_rate(const struct
> intel_crtc_state *crtc_
>return data_rate;
> }
>
> +int intel_bw_calc_min_cdclk(struct intel_atomic_state *
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/color: Extract icl_read_luts()
== Series Details == Series: drm/i915/color: Extract icl_read_luts() URL : https://patchwork.freedesktop.org/series/74777/ State : warning == Summary == $ dim checkpatch origin/drm-tip af4d857eacf3 drm/i915/color: Extract icl_read_luts() -:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #29: -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA total: 0 errors, 1 warnings, 0 checks, 189 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PULL] drm-misc-next
Hi, Here is what should be the final drm-misc-next PR for 5.7. Maxime drm-misc-next-2020-03-17: drm-misc-next for 5.7: UAPI Changes: Cross-subsystem Changes: Core Changes: - dp-mst: Remove register_connector callback, add drm_dp_destroy_connector - Changes to scnprintf on multiple instances Driver Changes: - meson: Support for YUV420 - panel: Support Ortustech COM37H3M, idk-1110wr and idk-2121wr, multiple dotclock fixes The following changes since commit bc1a4130fc0309cc2f43b9cc616ebbc295e886ff: drm/virtio: add case for shmem objects in virtio_gpu_cleanup_object(..) (2020-03-09 10:44:34 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-03-17 for you to fetch changes up to 6afe6929964bca6847986d0507a555a041f07753: drm: Mark up racy check of drm_gem_object.handle_count (2020-03-16 10:31:35 +) drm-misc-next for 5.7: UAPI Changes: Cross-subsystem Changes: Core Changes: - dp-mst: Remove register_connector callback, add drm_dp_destroy_connector - Changes to scnprintf on multiple instances Driver Changes: - meson: Support for YUV420 - panel: Support Ortustech COM37H3M, idk-1110wr and idk-2121wr, multiple dotclock fixes Akeem G Abodunrin (1): drm/mm: Remove redundant assignment in drm_mm_reserve_node Benjamin Gaignard (4): drm: context: Clean up documentation drm: vm: Clean up documentation drm: bufs: Clean up documentation drm: lock: Clean up documentation Chris Wilson (2): drm/mm: Allow drm_mm_initialized() to be used outside of the locks drm: Mark up racy check of drm_gem_object.handle_count Christian König (1): drm/ttm: fix false positive assert Fabrizio Castro (2): dt-bindings: display: Add idk-2121wr binding dt-bindings: display: Add idk-1110wr binding H. Nikolaus Schaller (1): drm/panel-simple: Fix dotclock for Ortustech COM37H3M Heiko Stuebner (1): drm/rockchip: rgb: don't count non-existent devices when determining subdrivers Jonas Karlman (2): drm/bridge: dw-hdmi: set mtmdsclock for deep color drm/bridge: dw-hdmi: add max bpc connector property Kamlesh Gurudasani (1): drm/tiny: fix sparse warning: incorrect type in assignment (different base types) Kees Cook (1): drm/edid: Distribute switch variables for initialization Laurent Pinchart (1): drm: panel: Set connector type for OrtusTech COM43H4M85ULC panel Lyude Paul (3): drm/dp_mst: Make drm_dp_mst_dpcd_write() consistent with drm_dp_dpcd_write() drm/dp_mst: Fix drm_dp_check_mstb_guid() return code drm/dp_mst: Convert drm_dp_mst_topology_mgr.is_waiting_for_dwn_reply to bitfield Manasi Navare (2): drm/edid: Name the detailed monitor range flags drm/edid: Add function to parse EDID descriptors for monitor range Neil Armstrong (9): drm/bridge: dw-hdmi: Plug atomic state hooks to the default implementation drm/bridge: synopsys: dw-hdmi: add bus format negociation drm/bridge: synopsys: dw-hdmi: allow ycbcr420 modes for >= 0x200a drm/meson: venc: make drm_display_mode const drm/meson: meson_dw_hdmi: add bridge and switch to drm_bridge_funcs drm/meson: dw-hdmi: stop enforcing input_bus_format drm/meson: venc: add support for YUV420 setup drm/meson: vclk: add support for YUV420 setup drm/meson: Add YUV420 output support Pankaj Bharadiya (5): drm: Register connector instead of calling register_connector callback drm: Remove dp mst register connector callbacks drm/dp_mst: Remove register_connector callback drm: Add drm_dp_destroy_connector helper and use it drm: Remove drm dp mst destroy_connector callbacks Sam Ravnborg (1): dt-bindings: display: fix panel warnings Takashi Iwai (2): drm/ttm: Use scnprintf() for avoiding potential buffer overflow drm: sysfs: Use scnprintf() for avoiding potential buffer overflow Ville Syrjälä (5): drm/panel-novatek-nt35510: Fix dotclock drm/panel-ilitek-ili9322: Fix dotclocks drm/panel-lg-lg4573: Fix dotclock drm/panel-sony-acx424akp: Fix dotclocks drm/panel-simple: Fix dotclock for Logic PD Type 28 .../display/panel/advantech,idk-1110wr.yaml| 69 + .../display/panel/advantech,idk-2121wr.yaml| 122 .../bindings/display/panel/elida,kd35t133.yaml | 2 +- .../display/panel/leadtek,ltk500hd1829.yaml| 2 +- .../bindings/display/panel/novatek,nt35510.yaml| 4 +- .../bindings/display/panel/orisetech,otm8009a.yaml | 2 +- .../bindings/display/panel/panel-dpi.yaml | 2 +- .../bindings/display/panel/panel-simple-dsi.yaml | 2 +- .../bindings/display/panel/raydium,rm68200.yaml| 2 +- .../bindings/display/panel/xinpeng,xpp055c272.ya
Re: [Intel-gfx] [PATCH 02/12] drm/i915: Wrap i915_active in a simple kreffed struct
>-Original Message-
>From: Intel-gfx On Behalf Of Chris
>Wilson
>Sent: Tuesday, March 17, 2020 8:27 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 02/12] drm/i915: Wrap i915_active in a simple
>kreffed struct
>
>For conveniences of callers that just want to use an i915_active to
>track a wide array of concurrent timelines, wrap the base i915_active
>struct inside a kref. This i915_active will self-destruct after use.
>
>Signed-off-by: Chris Wilson
>Cc: Mika Kuoppala
>Reviewed-by: Mika Kuoppala
>---
> drivers/gpu/drm/i915/i915_active.c | 53
>++
> drivers/gpu/drm/i915/i915_active.h | 4 +++
> 2 files changed, 57 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_active.c
>b/drivers/gpu/drm/i915/i915_active.c
>index c4048628188a..535b8161a597 100644
>--- a/drivers/gpu/drm/i915/i915_active.c
>+++ b/drivers/gpu/drm/i915/i915_active.c
>@@ -937,6 +937,59 @@ void i915_active_noop(struct dma_fence *fence,
>struct dma_fence_cb *cb)
> active_fence_cb(fence, cb);
> }
>
>+struct auto_active {
>+ struct i915_active base;
>+ struct kref ref;
>+};
>+
>+struct i915_active *i915_active_get(struct i915_active *ref)
>+{
>+ struct auto_active *aa = container_of(ref, typeof(*aa), base);
>+
>+ kref_get(&aa->ref);
Does this need to be kref_get_unless_zero()?
I asked this a couple of days ago, but found that the email for
chris-wilson.co.uk had bounced. Not sure if you have answered this or not.
Thanks,
Mike
>+ return &aa->base;
>+}
>+
>+static void auto_release(struct kref *ref)
>+{
>+ struct auto_active *aa = container_of(ref, typeof(*aa), ref);
>+
>+ i915_active_fini(&aa->base);
>+ kfree(aa);
>+}
>+
>+void i915_active_put(struct i915_active *ref)
>+{
>+ struct auto_active *aa = container_of(ref, typeof(*aa), base);
>+
>+ kref_put(&aa->ref, auto_release);
>+}
>+
>+static int auto_active(struct i915_active *ref)
>+{
>+ i915_active_get(ref);
>+ return 0;
>+}
>+
>+static void auto_retire(struct i915_active *ref)
>+{
>+ i915_active_put(ref);
>+}
>+
>+struct i915_active *i915_active_create(void)
>+{
>+ struct auto_active *aa;
>+
>+ aa = kmalloc(sizeof(*aa), GFP_KERNEL);
>+ if (!aa)
>+ return NULL;
>+
>+ kref_init(&aa->ref);
>+ i915_active_init(&aa->base, auto_active, auto_retire);
>+
>+ return &aa->base;
>+}
>+
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> #include "selftests/i915_active.c"
> #endif
>diff --git a/drivers/gpu/drm/i915/i915_active.h
>b/drivers/gpu/drm/i915/i915_active.h
>index b3282ae7913c..bffbcf7751a7 100644
>--- a/drivers/gpu/drm/i915/i915_active.h
>+++ b/drivers/gpu/drm/i915/i915_active.h
>@@ -221,4 +221,8 @@ void i915_request_add_active_barriers(struct
>i915_request *rq);
> void i915_active_print(struct i915_active *ref, struct drm_printer *m);
> void i915_active_unlock_wait(struct i915_active *ref);
>
>+struct i915_active *i915_active_create(void);
>+struct i915_active *i915_active_get(struct i915_active *ref);
>+void i915_active_put(struct i915_active *ref);
>+
> #endif /* _I915_ACTIVE_H_ */
>--
>2.20.1
>
>___
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>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/color: Extract icl_read_luts()
== Series Details == Series: drm/i915/color: Extract icl_read_luts() URL : https://patchwork.freedesktop.org/series/74777/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/color: Extract icl_read_luts()
== Series Details == Series: drm/i915/color: Extract icl_read_luts() URL : https://patchwork.freedesktop.org/series/74777/ State : success == Summary == CI Bug Log - changes from CI_DRM_8142 -> Patchwork_16995 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/index.html Known issues Here are the changes found in Patchwork_16995 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@basic-rte: - fi-hsw-4770:[PASS][1] -> [SKIP][2] ([fdo#109271]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-hsw-4770/igt@i915_pm_...@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/fi-hsw-4770/igt@i915_pm_...@basic-rte.html Possible fixes * igt@i915_selftest@live@execlists: - fi-skl-lmem:[INCOMPLETE][3] ([i915#1430] / [i915#656]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-skl-lmem/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/fi-skl-lmem/igt@i915_selftest@l...@execlists.html - fi-kbl-soraka: [INCOMPLETE][5] ([fdo#112259] / [i915#1430] / [i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259 [i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (43 -> 42) -- Additional (5): fi-bdw-5557u fi-glk-dsi fi-cfl-8109u fi-blb-e6850 fi-skl-6700k2 Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8142 -> Patchwork_16995 CI-20190529: 20190529 CI_DRM_8142: 13dfeddee92ca6b9d134e036ae315e93b96023db @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5514: 921758a91a453e8148b3146ad874bbd4ae4364ec @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16995: af4d857eacf32bdd7d3599e4d6ba1711e385efb5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af4d857eacf3 drm/i915/color: Extract icl_read_luts() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3) URL : https://patchwork.freedesktop.org/series/74759/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3) URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8142 -> Patchwork_16996 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/index.html Known issues Here are the changes found in Patchwork_16996 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@execlists: - fi-skl-lmem:[INCOMPLETE][1] ([i915#1430] / [i915#656]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-skl-lmem/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/fi-skl-lmem/igt@i915_selftest@l...@execlists.html - fi-kbl-soraka: [INCOMPLETE][3] ([fdo#112259] / [i915#1430] / [i915#656]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html [fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259 [i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (43 -> 41) -- Additional (5): fi-bdw-5557u fi-glk-dsi fi-cfl-8109u fi-blb-e6850 fi-skl-6700k2 Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus fi-byt-clapper fi-bsw-nick fi-skl-6600u Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8142 -> Patchwork_16996 CI-20190529: 20190529 CI_DRM_8142: 13dfeddee92ca6b9d134e036ae315e93b96023db @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5514: 921758a91a453e8148b3146ad874bbd4ae4364ec @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16996: 14c937a62591a82e1bc1d11ebc58194af9959877 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 14c937a62591 drm/i915/gem: Avoid gem_context->mutex for simple vma lookup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix up documentation paths after file moving
== Series Details == Series: drm/i915: Fix up documentation paths after file moving URL : https://patchwork.freedesktop.org/series/74778/ State : success == Summary == CI Bug Log - changes from CI_DRM_8142 -> Patchwork_16997 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/index.html Known issues Here are the changes found in Patchwork_16997 that come from known issues: ### IGT changes ### Possible fixes * igt@i915_selftest@live@execlists: - fi-kbl-soraka: [INCOMPLETE][1] ([fdo#112259] / [i915#1430] / [i915#656]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/fi-kbl-soraka/igt@i915_selftest@l...@execlists.html Warnings * igt@runner@aborted: - fi-kbl-8809g: [FAIL][3] ([i915#1209]) -> [FAIL][4] ([i915#192] / [i915#193] / [i915#194]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/fi-kbl-8809g/igt@run...@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/fi-kbl-8809g/igt@run...@aborted.html [fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259 [i915#1209]: https://gitlab.freedesktop.org/drm/intel/issues/1209 [i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (43 -> 36) -- Additional (4): fi-glk-dsi fi-bdw-5557u fi-cfl-8109u fi-skl-6700k2 Missing(11): fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-kbl-7500u fi-skl-lmem fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8142 -> Patchwork_16997 CI-20190529: 20190529 CI_DRM_8142: 13dfeddee92ca6b9d134e036ae315e93b96023db @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5514: 921758a91a453e8148b3146ad874bbd4ae4364ec @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16997: af208eb667dc2f87b932606c3ff4190b8aaa0d94 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af208eb667dc drm/i915: Fix up documentation paths after file moving == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests (rev2)
On Tue, 2020-03-17 at 13:59 +, Vudum, Lakshminarayana wrote:
> I had to re-report more than once as there were many issues. All good now.
Thank you :-)
Janusz
>
> Thanks,
> Lakshmi.
> -Original Message-
> From: Latvala, Petri
> Sent: Tuesday, March 17, 2020 12:40 PM
> To: Janusz Krzysztofik ; Vudum,
> Lakshminarayana
> Cc: igt-...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for tests/gem_userptr_blits:
> Refresh other now MMAP_GTT dependent subtests (rev2)
>
> Lakshmi, see below.
>
> On Tue, Mar 17, 2020 at 09:53:51AM +0100, Janusz Krzysztofik wrote:
> > Hi,
> >
> > On Mon, 2020-03-16 at 19:25 +, Patchwork wrote:
> > > == Series Details ==
> > >
> > > Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent
> > > subtests (rev2)
> > > URL : https://patchwork.freedesktop.org/series/74201/
> > > State : failure
> > >
> > > == Summary ==
> > >
> > > CI Bug Log - changes from CI_DRM_8137_full -> IGTPW_4307_full
> > >
> > >
> > > Summary
> > > ---
> > >
> > > **FAILURE**
> >
> > False positive, see below.
> >
> > > Serious unknown changes coming with IGTPW_4307_full absolutely need to
> > > be
> > > verified manually.
> > >
> > > If you think the reported changes have nothing to do with the changes
> > > introduced in IGTPW_4307_full, please notify your bug team to allow them
> > > to document this new failure mode, which will reduce false positives in
> > > CI.
> > >
> > > External URL:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/index.html
> > >
> > > Possible new issues
> > > ---
> > >
> > > Here are the unknown changes that may have been introduced in
> > > IGTPW_4307_full:
> > >
> > > ### IGT changes ###
> > >
> > > Possible regressions
> > >
> > > * igt@gem_ctx_shared@single-timeline:
> > > - shard-snb: NOTRUN -> [FAIL][1]
> > >[1]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-snb4/igt@gem_ctx_sha...@single-timeline.html
> > > - shard-hsw: NOTRUN -> [FAIL][2] +1 similar issue
> > >[2]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@g
> > > em_ctx_sha...@single-timeline.html
> > >
> > > * igt@gem_exec_fence@basic-await@vcs0:
> > > - shard-kbl: [PASS][3] -> [FAIL][4] +3 similar issues
> > >[3]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-kbl1/igt@gem_exec_fence@basic-aw...@vcs0.html
> > >[4]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-kbl7/igt@gem_exec_fence@basic-aw...@vcs0.html
> > > - shard-iclb: [PASS][5] -> [FAIL][6]
> > >[5]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-iclb1/igt@gem_exec_fence@basic-aw...@vcs0.html
> > >[6]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb5/igt@gem_exec_fence@basic-aw...@vcs0.html
> > > - shard-apl: [PASS][7] -> [FAIL][8] +2 similar issues
> > >[7]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > >[8]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-apl4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > > - shard-glk: [PASS][9] -> [FAIL][10] +2 similar issues
> > >[9]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-glk6/igt@gem_exec_fence@basic-aw...@vcs0.html
> > >[10]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-glk4/igt@gem_exec_fence@basic-aw...@vcs0.html
> > > - shard-tglb: [PASS][11] -> [FAIL][12] +2 similar issues
> > >[11]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-tglb6/igt@gem_exec_fence@basic-aw...@vcs0.html
> > >[12]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@
> > > gem_exec_fence@basic-aw...@vcs0.html
> >
> > Not related.
> >
> > > * {igt@gem_userptr_blits@process-exit-mmap-busy@gtt} (NEW):
> > > - shard-iclb: NOTRUN -> [SKIP][13] +7 similar issues
> > >[13]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-iclb3/igt@
> > > gem_userptr_blits@process-exit-mmap-b...@gtt.html
> > >
> > > * {igt@gem_userptr_blits@process-exit-mmap-busy@uc} (NEW):
> > > - shard-tglb: NOTRUN -> [SKIP][14] +11 similar issues
> > >[14]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-tglb5/igt@
> > > gem_userptr_blits@process-exit-mmap-b...@uc.html
> >
> > Expected behavior.
> >
> > > * igt@gem_wait@wait-rcs0:
> > > - shard-hsw: [PASS][15] -> [FAIL][16]
> > >[15]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/shard-hsw2/igt@gem_w...@wait-rcs0.html
> > >[16]:
> > > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4307/shard-hsw2/igt@g
> > > em_w...@wait-rcs0.html
> > >
> > > * igt@kms_cursor_l
[Intel-gfx] [PATCH] drm/i915/gt: Always reschedule the new heartbeat
In order to better respond to new heartbeat intervals given via sysfs, always reprogramme an active heartbeat upon change (i.e. use mod_delayed_work to reschedule rather than queue_delayed_work which ignores an already active work.) Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index dd825718e4e5..5136c8bf112d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -31,7 +31,7 @@ static bool next_heartbeat(struct intel_engine_cs *engine) delay = msecs_to_jiffies_timeout(delay); if (delay >= HZ) delay = round_jiffies_up_relative(delay); - schedule_delayed_work(&engine->heartbeat.work, delay); + mod_delayed_work(system_wq, &engine->heartbeat.work, delay); return true; } -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Always reschedule the new heartbeat
On 17/03/2020 16:32, Chris Wilson wrote: In order to better respond to new heartbeat intervals given via sysfs, always reprogramme an active heartbeat upon change (i.e. use mod_delayed_work to reschedule rather than queue_delayed_work which ignores an already active work.) Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index dd825718e4e5..5136c8bf112d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -31,7 +31,7 @@ static bool next_heartbeat(struct intel_engine_cs *engine) delay = msecs_to_jiffies_timeout(delay); if (delay >= HZ) delay = round_jiffies_up_relative(delay); - schedule_delayed_work(&engine->heartbeat.work, delay); + mod_delayed_work(system_wq, &engine->heartbeat.work, delay); return true; } Reviewed-by: Tvrtko Ursulin What about the transition from disabled (or long) preempt timeout to a normal one? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/gt: Always reschedule the new heartbeat
Quoting Tvrtko Ursulin (2020-03-17 16:50:02) > > On 17/03/2020 16:32, Chris Wilson wrote: > > In order to better respond to new heartbeat intervals given via sysfs, > > always reprogramme an active heartbeat upon change (i.e. use > > mod_delayed_work to reschedule rather than queue_delayed_work which > > ignores an already active work.) > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > > b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > > index dd825718e4e5..5136c8bf112d 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > > @@ -31,7 +31,7 @@ static bool next_heartbeat(struct intel_engine_cs *engine) > > delay = msecs_to_jiffies_timeout(delay); > > if (delay >= HZ) > > delay = round_jiffies_up_relative(delay); > > - schedule_delayed_work(&engine->heartbeat.work, delay); > > + mod_delayed_work(system_wq, &engine->heartbeat.work, delay); > > > > return true; > > } > > > > Reviewed-by: Tvrtko Ursulin > > What about the transition from disabled (or long) preempt timeout to a > normal one? They all use next_heartbeat() (from calling intel_engine_unpark_heartbeat) to reschedule if going to an active heartbeat. On disable, we call intel_engine_park_heartbeat() which does the cancel_delayed_work. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v7,1/3] drm/i915/perf: remove generated code
== Series Details ==
Series: series starting with [v7,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74767/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8141_full -> Patchwork_16990_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_16990_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16990_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16990_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_whisper@basic-fds-forked:
- shard-iclb: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb1/igt@gem_exec_whis...@basic-fds-forked.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-iclb5/igt@gem_exec_whis...@basic-fds-forked.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@sysfs_heartbeat_interval@mixed@bcs0}:
- shard-iclb: [FAIL][3] ([i915#1459]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb5/igt@sysfs_heartbeat_interval@mi...@bcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-iclb7/igt@sysfs_heartbeat_interval@mi...@bcs0.html
- shard-kbl: [FAIL][5] ([i915#1459]) -> [INCOMPLETE][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-kbl7/igt@sysfs_heartbeat_interval@mi...@bcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-kbl7/igt@sysfs_heartbeat_interval@mi...@bcs0.html
New tests
-
New tests have been introduced between CI_DRM_8141_full and
Patchwork_16990_full:
### New IGT tests (2) ###
* igt@sysfs_heartbeat_interval@precise:
- Statuses :
- Exec time: [None] s
* igt@sysfs_preempt_timeout@idempotent:
- Statuses :
- Exec time: [None] s
Known issues
Here are the changes found in Patchwork_16990_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#69]) +2 similar
issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-skl9/igt@gem_ctx_isolat...@bcs0-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-skl2/igt@gem_ctx_isolat...@bcs0-s3.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#1402])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-kbl6/igt@gem_ctx_persiste...@close-replace-race.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-kbl6/igt@gem_ctx_persiste...@close-replace-race.html
* igt@gem_exec_schedule@implicit-read-write-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-iclb2/igt@gem_exec_sched...@implicit-read-write-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb6/igt@gem_exec_sched...@wide-bsd.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-iclb2/igt@gem_exec_sched...@wide-bsd.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1
similar issue
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-apl1/igt@gem_workarou...@suspend-resume.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-apl4/igt@gem_workarou...@suspend-resume.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +7
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#413])
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb5/igt@i915_pm_...@reset.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16990/shard-iclb6/igt@i915_pm_...@reset.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][21] -> [SKIP][
Re: [Intel-gfx] [PATCH v2] drm/i915/edp: Ignore short pulse when panel powered off
On Sat, 14 Mar 2020, Anshuman Gupta wrote:
> Few edp panels like Sharp is triggering short and long
> hpd pulse after panel is getting powered off.
> Currently driver is already ignoring long pulse for eDP
> panel but in order to process the short pulse, it turns on
> the VDD which requires panel power_cycle_delay + panel_power_on_delay
> these delay on Sharp panel introduced the responsiveness overhead
> of 800ms in the modeset sequence and as well is in suspend
> sequence.
> Ignoring any short pulse once panel is powered off.
>
> FIXME: It requires to wait for panel_power_off_delay in order
> to check the panel status, as panel triggers short pulse immediately
> after writing PP_OFF to PP_CTRL register.
>
> v2:
> - checking vdd along with panel power to ignore the hpd. [Jani,Ville]
>
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 27 +++--
> 1 file changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0a417cd2af2b..3475791d3bea 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6763,21 +6763,36 @@ static const struct drm_encoder_funcs
> intel_dp_enc_funcs = {
> .destroy = intel_dp_encoder_destroy,
> };
>
> +static bool intel_edp_have_power(struct intel_dp *intel_dp)
> +{
> + intel_wakeref_t wakeref;
> + bool powerd_on = false;
Nitpick, "powerd" seems like a typo. "have_power" to reflect the name of
the function?
> +
> + with_pps_lock(intel_dp, wakeref) {
> + powerd_on = edp_have_panel_power(intel_dp) &&
> + edp_have_panel_vdd(intel_dp);
> + }
> +
> + return powerd_on;
> +}
> +
> enum irqreturn
> intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> {
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
> + if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
> + !intel_edp_have_power(intel_dp)) {
This *enables* long hpd handling when eDP *does* have power. Not sure if
we want that. Erring on the safe side, this might be a better option:
if (intel_dig_port->base.type == INTEL_OUTPUT_EDP &&
(long_hpd || !intel_edp_have_power(intel_dp)))
> /*
> - * vdd off can generate a long pulse on eDP which
> + * vdd off can generate a hpd pulse on eDP which
>* would require vdd on to handle it, and thus we
>* would end up in an endless cycle of
> - * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
> + * "vdd off -> hpd -> vdd on -> detect -> vdd off -> ..."
>*/
> - DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
> - intel_dig_port->base.base.base.id,
> - intel_dig_port->base.base.name);
> + drm_dbg_kms(&i915->drm, "ignoring hpd on eDP [ENCODER:%d:%s]\n",
> + intel_dig_port->base.base.base.id,
> + intel_dig_port->base.base.name);
I think we may want to know whether it was a short or long hpd that was
ignored if we ever need to debug this again. (We will. ;)
Something along the lines of "ignoring %s hpd ...", long_hpd ? "long" :
"short".
Please keep the old logging macro here, in case this needs backporting
to older kernels. (In general not a huge fan of doing two independent
things at once.)
BR,
Jani.
> return IRQ_HANDLED;
> }
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev2) URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8141_full -> Patchwork_16991_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8141_full and Patchwork_16991_full: ### New IGT tests (2) ### * igt@sysfs_heartbeat_interval@precise: - Statuses : - Exec time: [None] s * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16991_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-apl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd: - shard-glk: [PASS][3] -> [INCOMPLETE][4] ([i915#1197] / [i915#1239] / [i915#58] / [k.org#198133]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-glk6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-glk9/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@render: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#679]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-glk6/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-glk9/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@render.html * igt@gem_exec_schedule@implicit-both-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb1/igt@gem_exec_sched...@implicit-both-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb8/igt@gem_exec_sched...@implicit-both-bsd1.html * igt@gem_exec_schedule@out-order-bsd2: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +11 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb2/igt@gem_exec_sched...@out-order-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb3/igt@gem_exec_sched...@out-order-bsd2.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb7/igt@gem_exec_sched...@pi-shared-iova-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb1/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html * igt@i915_pm_rps@reset: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#413]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb5/igt@i915_pm_...@reset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb5/igt@i915_pm_...@reset.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#69]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-skl6/igt@i915_susp...@forcewake.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-skl6/igt@i915_susp...@forcewake.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109349]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16991/shard-iclb1/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#46]) [23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Always reschedule the new heartbeat
== Series Details ==
Series: drm/i915/gt: Always reschedule the new heartbeat
URL : https://patchwork.freedesktop.org/series/74791/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8143 -> Patchwork_16998
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16998:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {fi-tgl-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/fi-tgl-u/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/fi-tgl-u/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (38 -> 40)
--
Additional (7): fi-bdw-5557u fi-snb-2520m fi-kbl-7500u fi-ivb-3770
fi-elk-e7500 fi-skl-lmem fi-skl-6600u
Missing(5): fi-byt-j1900 fi-byt-squawks fi-bwr-2160 fi-cfl-8109u
fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8143 -> Patchwork_16998
CI-20190529: 20190529
CI_DRM_8143: 6f22cb5a2b0ba7fc92e19c9d8a038d0cd9c0208a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5516: 59aa9e450a90b4dedbe6899fd17c317bbac741c4 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16998: db7a098d5f89c53e7a792ba3fad4c20e2f6be0e7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db7a098d5f89 drm/i915/gt: Always reschedule the new heartbeat
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/index.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/i915/gem: Drop relocation slowpath"
== Series Details == Series: Revert "drm/i915/gem: Drop relocation slowpath" URL : https://patchwork.freedesktop.org/series/74771/ State : success == Summary == CI Bug Log - changes from CI_DRM_8141_full -> Patchwork_16993_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8141_full and Patchwork_16993_full: ### New IGT tests (2) ### * igt@sysfs_heartbeat_interval@precise: - Statuses : - Exec time: [None] s * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16993_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([i915#1402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-kbl6/igt@gem_ctx_persiste...@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-kbl4/igt@gem_ctx_persiste...@close-replace-race.html - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#1402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-skl7/igt@gem_ctx_persiste...@close-replace-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-skl5/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@blt: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#1197] / [i915#1239]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-skl3/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@blt.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#679]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-skl3/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-skl9/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@bsd.html * igt@gem_exec_schedule@implicit-both-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb6/igt@gem_exec_sched...@implicit-both-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-iclb1/igt@gem_exec_sched...@implicit-both-bsd.html * igt@gem_exec_schedule@implicit-both-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb1/igt@gem_exec_sched...@implicit-both-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-iclb5/igt@gem_exec_sched...@implicit-both-bsd1.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb5/igt@gem_exec_sched...@preempt-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-iclb2/igt@gem_exec_sched...@preempt-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-apl8/igt@gem_workarou...@suspend-resume-context.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rps@reset: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#413]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb5/igt@i915_pm_...@reset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-iclb2/igt@i915_pm_...@reset.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109349]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-iclb8/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8141/shard-glk5/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16993/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +5 similar issues [23]: https
[Intel-gfx] Screen Flickering on DELL XPS-13-7390
Hello I installed opensuse Tumbleweed linux on a brand new Dell XPS-13-7390. Already during the installation, the screen started to flicker. Then I installed opensuse 15.1 on the same laptop and it worked without screen flickering. But after I run the online update it started to flicker again. I suspect that there are some changes in the newer kernel versions. Does anybody know why it does work with kernel 4.12.14-lp151.27-default and it doesn't work with a newer kernel. I opened a thread in the opensuse forum: https://forums.opensuse.org/showthread.php/539492-Screen-flickering-on-DELL-XPS-13-7390?p=2929887#post2929887 There you can see the outputs of inxi. Somebody recommended to ask here for advice. Is there anything I can do to get rid of this screen flickering? Thank you very much for your help Sent from [ProtonMail](https://protonmail.com), Swiss-based encrypted email.___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Screen Flickering on DELL XPS-13-7390
Hi Please test with drm-tip and file a bug attaching more information and logs: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs On Tue, 2020-03-17 at 18:56 +, Damian Hischier wrote: > Hello > > I installed opensuse Tumbleweed linux on a brand new Dell XPS-13- > 7390. Already during the installation, the screen started to flicker. > Then I installed opensuse 15.1 on the same laptop and it worked > without screen flickering. But after I run the online update it > started to flicker again. I suspect that there are some changes in > the newer kernel versions. Does anybody know why it does work with > kernel 4.12.14-lp151.27-default and it doesn't work with a newer > kernel. I opened a thread in the opensuse forum: > > https://forums.opensuse.org/showthread.php/539492-Screen-flickering-on-DELL-XPS-13-7390?p=2929887#post2929887 > > There you can see the outputs of inxi. Somebody recommended to ask > here for advice. Is there anything I can do to get rid of this screen > flickering? > > Thank you very much for your help > > Sent from ProtonMail, Swiss-based encrypted email. > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
As we store the handle lookup inside a radix tree, we do not need the
gem_context->mutex except until we need to insert our lookup into the
common radix tree. This takes a small bit of rearranging to ensure that
the lut we insert into the tree is ready prior to actually inserting it
(as soon as it is exposed via the radixtree, it is visible to any other
submission).
v2: For brownie points, remove the goto spaghetti.
v3: Tighten up the closed-handle checks.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 136 +++---
1 file changed, 87 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..9a781a2b144c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -481,7 +481,7 @@ eb_add_vma(struct i915_execbuffer *eb,
GEM_BUG_ON(i915_vma_is_closed(vma));
- ev->vma = i915_vma_get(vma);
+ ev->vma = vma;
ev->exec = entry;
ev->flags = entry->flags;
@@ -728,77 +728,117 @@ static int eb_select_context(struct i915_execbuffer *eb)
return 0;
}
-static int eb_lookup_vmas(struct i915_execbuffer *eb)
+static int __eb_add_lut(struct i915_execbuffer *eb,
+ u32 handle, struct i915_vma *vma)
{
- struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
- struct drm_i915_gem_object *obj;
- unsigned int i, batch;
+ struct i915_gem_context *ctx = eb->gem_context;
+ struct i915_lut_handle *lut;
int err;
- if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
- return -ENOENT;
+ lut = i915_lut_handle_alloc();
+ if (unlikely(!lut))
+ return -ENOMEM;
- INIT_LIST_HEAD(&eb->relocs);
- INIT_LIST_HEAD(&eb->unbound);
+ i915_vma_get(vma);
+ if (!atomic_fetch_inc(&vma->open_count))
+ i915_vma_reopen(vma);
+ lut->handle = handle;
+ lut->ctx = ctx;
+
+ /* Check that the context hasn't been closed in the meantime */
+ err = -EINTR;
+ if (!mutex_lock_interruptible(&ctx->mutex)) {
+ err = -ENOENT;
+ if (likely(!i915_gem_context_is_closed(ctx)))
+ err = radix_tree_insert(&ctx->handles_vma, handle, vma);
+ if (err == 0) { /* And nor has this handle */
+ struct drm_i915_gem_object *obj = vma->obj;
+
+ i915_gem_object_lock(obj);
+ if (i915_gem_object_lookup_rcu(eb->file, handle) ==
obj) {
+ list_add(&lut->obj_link, &obj->lut_list);
+ } else {
+ radix_tree_delete(&ctx->handles_vma, handle);
+ err = -ENOENT;
+ }
+ i915_gem_object_unlock(obj);
+ }
+ mutex_unlock(&ctx->mutex);
+ }
+ if (unlikely(err))
+ goto err;
- batch = eb_batch_index(eb);
+ return 0;
- for (i = 0; i < eb->buffer_count; i++) {
- u32 handle = eb->exec[i].handle;
- struct i915_lut_handle *lut;
+err:
+ atomic_dec(&vma->open_count);
+ i915_vma_put(vma);
+ i915_lut_handle_free(lut);
+ return err;
+}
+
+static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
+{
+ do {
+ struct drm_i915_gem_object *obj;
struct i915_vma *vma;
+ int err;
- vma = radix_tree_lookup(handles_vma, handle);
+ rcu_read_lock();
+ vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
+ if (likely(vma))
+ vma = i915_vma_tryget(vma);
+ rcu_read_unlock();
if (likely(vma))
- goto add_vma;
+ return vma;
obj = i915_gem_object_lookup(eb->file, handle);
- if (unlikely(!obj)) {
- err = -ENOENT;
- goto err_vma;
- }
+ if (unlikely(!obj))
+ return ERR_PTR(-ENOENT);
vma = i915_vma_instance(obj, eb->context->vm, NULL);
if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
+ i915_gem_object_put(obj);
+ return vma;
}
- lut = i915_lut_handle_alloc();
- if (unlikely(!lut)) {
- err = -ENOMEM;
- goto err_obj;
- }
+ err = __eb_add_lut(eb, handle, vma);
+ if (likely(!err))
+ return vma;
- err = radix_tree_insert(handles_vma, handle, vma)
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev4)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev4) URL : https://patchwork.freedesktop.org/series/74759/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8144 -> Patchwork_16999 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16999 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16999, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16999: ### IGT changes ### Possible regressions * igt@gem_busy@busy-all: - fi-bdw-5557u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-bdw-5557u/igt@gem_b...@busy-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-bdw-5557u/igt@gem_b...@busy-all.html - fi-kbl-8809g: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-8809g/igt@gem_b...@busy-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-kbl-8809g/igt@gem_b...@busy-all.html - fi-icl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-icl-guc/igt@gem_b...@busy-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-icl-guc/igt@gem_b...@busy-all.html - fi-kbl-r: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-r/igt@gem_b...@busy-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-kbl-r/igt@gem_b...@busy-all.html - fi-bsw-kefka: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-bsw-kefka/igt@gem_b...@busy-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-bsw-kefka/igt@gem_b...@busy-all.html - fi-icl-dsi: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-icl-dsi/igt@gem_b...@busy-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-icl-dsi/igt@gem_b...@busy-all.html - fi-kbl-guc: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-guc/igt@gem_b...@busy-all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-kbl-guc/igt@gem_b...@busy-all.html - fi-kbl-7500u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-7500u/igt@gem_b...@busy-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-kbl-7500u/igt@gem_b...@busy-all.html - fi-kbl-x1275: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-x1275/igt@gem_b...@busy-all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-kbl-x1275/igt@gem_b...@busy-all.html - fi-pnv-d510:[PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-pnv-d510/igt@gem_b...@busy-all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-pnv-d510/igt@gem_b...@busy-all.html - fi-icl-u2: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-icl-u2/igt@gem_b...@busy-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-icl-u2/igt@gem_b...@busy-all.html - fi-skl-6600u: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-skl-6600u/igt@gem_b...@busy-all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-skl-6600u/igt@gem_b...@busy-all.html - fi-cfl-8700k: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cfl-8700k/igt@gem_b...@busy-all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-cfl-8700k/igt@gem_b...@busy-all.html - fi-icl-y: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-icl-y/igt@gem_b...@busy-all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-icl-y/igt@gem_b...@busy-all.html - fi-snb-2520m: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-snb-2520m/igt@gem_b...@busy-all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16999/fi-snb-2520m/igt@gem_b...@busy-all.html - fi-ivb-3770:[PASS][31] -> [DMESG-WARN][32] [31]: https://intel-gfx-ci.01.org/tree/drm-
[Intel-gfx] [PATCH] drm/i915/tgl: Add new PCI IDs to TGL
Adding 4 new PCI IDs to TGL Bspec: 44455 Signed-off-by: Swathi Dhanavanthri --- include/drm/i915_pciids.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 1d2c12219f44..c299e26c99c5 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -599,6 +599,10 @@ INTEL_VGA_DEVICE(0x9A60, info), \ INTEL_VGA_DEVICE(0x9A68, info), \ INTEL_VGA_DEVICE(0x9A70, info), \ - INTEL_VGA_DEVICE(0x9A78, info) + INTEL_VGA_DEVICE(0x9A78, info), \ + INTEL_VGA_DEVICE(0x9AC9, info), \ + INTEL_VGA_DEVICE(0x9AF8, info), \ + INTEL_VGA_DEVICE(0x9AC0, info), \ + INTEL_VGA_DEVICE(0x9AD9, info) #endif /* _I915_PCIIDS_H */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Avoid gem_context->mutex for simple vma lookup
As we store the handle lookup inside a radix tree, we do not need the
gem_context->mutex except until we need to insert our lookup into the
common radix tree. This takes a small bit of rearranging to ensure that
the lut we insert into the tree is ready prior to actually inserting it
(as soon as it is exposed via the radixtree, it is visible to any other
submission).
v2: For brownie points, remove the goto spaghetti.
v3: Tighten up the closed-handle checks.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 136 +++---
1 file changed, 87 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3f4f28e9468..042a9ccf348f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -481,7 +481,7 @@ eb_add_vma(struct i915_execbuffer *eb,
GEM_BUG_ON(i915_vma_is_closed(vma));
- ev->vma = i915_vma_get(vma);
+ ev->vma = vma;
ev->exec = entry;
ev->flags = entry->flags;
@@ -728,77 +728,117 @@ static int eb_select_context(struct i915_execbuffer *eb)
return 0;
}
-static int eb_lookup_vmas(struct i915_execbuffer *eb)
+static int __eb_add_lut(struct i915_execbuffer *eb,
+ u32 handle, struct i915_vma *vma)
{
- struct radix_tree_root *handles_vma = &eb->gem_context->handles_vma;
- struct drm_i915_gem_object *obj;
- unsigned int i, batch;
+ struct i915_gem_context *ctx = eb->gem_context;
+ struct i915_lut_handle *lut;
int err;
- if (unlikely(i915_gem_context_is_closed(eb->gem_context)))
- return -ENOENT;
+ lut = i915_lut_handle_alloc();
+ if (unlikely(!lut))
+ return -ENOMEM;
- INIT_LIST_HEAD(&eb->relocs);
- INIT_LIST_HEAD(&eb->unbound);
+ i915_vma_get(vma);
+ if (!atomic_fetch_inc(&vma->open_count))
+ i915_vma_reopen(vma);
+ lut->handle = handle;
+ lut->ctx = ctx;
+
+ /* Check that the context hasn't been closed in the meantime */
+ err = -EINTR;
+ if (!mutex_lock_interruptible(&ctx->mutex)) {
+ err = -ENOENT;
+ if (likely(!i915_gem_context_is_closed(ctx)))
+ err = radix_tree_insert(&ctx->handles_vma, handle, vma);
+ if (err == 0) { /* And nor has this handle */
+ struct drm_i915_gem_object *obj = vma->obj;
+
+ i915_gem_object_lock(obj);
+ if (idr_find(&eb->file->object_idr, handle) == obj) {
+ list_add(&lut->obj_link, &obj->lut_list);
+ } else {
+ radix_tree_delete(&ctx->handles_vma, handle);
+ err = -ENOENT;
+ }
+ i915_gem_object_unlock(obj);
+ }
+ mutex_unlock(&ctx->mutex);
+ }
+ if (unlikely(err))
+ goto err;
- batch = eb_batch_index(eb);
+ return 0;
- for (i = 0; i < eb->buffer_count; i++) {
- u32 handle = eb->exec[i].handle;
- struct i915_lut_handle *lut;
+err:
+ atomic_dec(&vma->open_count);
+ i915_vma_put(vma);
+ i915_lut_handle_free(lut);
+ return err;
+}
+
+static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle)
+{
+ do {
+ struct drm_i915_gem_object *obj;
struct i915_vma *vma;
+ int err;
- vma = radix_tree_lookup(handles_vma, handle);
+ rcu_read_lock();
+ vma = radix_tree_lookup(&eb->gem_context->handles_vma, handle);
+ if (likely(vma))
+ vma = i915_vma_tryget(vma);
+ rcu_read_unlock();
if (likely(vma))
- goto add_vma;
+ return vma;
obj = i915_gem_object_lookup(eb->file, handle);
- if (unlikely(!obj)) {
- err = -ENOENT;
- goto err_vma;
- }
+ if (unlikely(!obj))
+ return ERR_PTR(-ENOENT);
vma = i915_vma_instance(obj, eb->context->vm, NULL);
if (IS_ERR(vma)) {
- err = PTR_ERR(vma);
- goto err_obj;
+ i915_gem_object_put(obj);
+ return vma;
}
- lut = i915_lut_handle_alloc();
- if (unlikely(!lut)) {
- err = -ENOMEM;
- goto err_obj;
- }
+ err = __eb_add_lut(eb, handle, vma);
+ if (likely(!err))
+ return vma;
- err = radix_tree_insert(handles_vma, handle, vma);
-
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/color: Extract icl_read_luts()
== Series Details == Series: drm/i915/color: Extract icl_read_luts() URL : https://patchwork.freedesktop.org/series/74777/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8142_full -> Patchwork_16995_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16995_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16995_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16995_full: ### IGT changes ### Possible regressions * igt@gem_set_tiling_vs_blt@untiled-to-tiled: - shard-iclb: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb3/igt@gem_set_tiling_vs_...@untiled-to-tiled.html * igt@perf_pmu@busy-no-semaphores-vecs0: - shard-skl: [PASS][2] -> [FAIL][3] +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-skl7/igt@perf_...@busy-no-semaphores-vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-skl8/igt@perf_...@busy-no-semaphores-vecs0.html New tests - New tests have been introduced between CI_DRM_8142_full and Patchwork_16995_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16995_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([i915#1402]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-tglb8/igt@gem_ctx_persiste...@close-replace-race.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-tglb2/igt@gem_ctx_persiste...@close-replace-race.html - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#1402]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-kbl2/igt@gem_ctx_persiste...@close-replace-race.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-kbl4/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#110854]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_balan...@smoke.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#112080]) +13 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276] / [i915#677]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd2.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb8/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][14] -> [SKIP][15] ([i915#677]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb6/igt@gem_exec_sched...@pi-shared-iova-bsd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb4/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#112146]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb3/igt@gem_exec_sched...@preemptive-hang-bsd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109276]) +23 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][20] -> [FAIL][21] ([i915#644]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-apl6/igt@gem_pp...@flink-and-close-vma-leak.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16995/shard-apl7/igt@gem_pp...@flink-and-close-vma-leak.html - shard-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Add new PCI IDs to TGL
== Series Details == Series: drm/i915/tgl: Add new PCI IDs to TGL URL : https://patchwork.freedesktop.org/series/74795/ State : success == Summary == CI Bug Log - changes from CI_DRM_8144 -> Patchwork_17000 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/index.html Known issues Here are the changes found in Patchwork_17000 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-cml-s: [PASS][1] -> [INCOMPLETE][2] ([i915#283] / [i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cml-s/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/fi-cml-s/igt@i915_selftest@l...@execlists.html * igt@kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635] / [i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/fi-icl-u2/igt@kms_chamel...@dp-crc-fast.html Possible fixes * igt@i915_selftest@live@execlists: - fi-cml-u2: [INCOMPLETE][5] ([i915#283] / [i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cml-u2/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/fi-cml-u2/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-cfl-8700k: [INCOMPLETE][7] ([i915#424]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 Participating hosts (45 -> 42) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(5): fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-byt-clapper Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8144 -> Patchwork_17000 CI-20190529: 20190529 CI_DRM_8144: e22a73e6b26efdc18bd44d26c93e16c2783ab3f4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5517: b77e3a470bdf1bc5f047ebb98ed8ca4738dd44c7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17000: db3b1ec37979435147262647bbfee65572faad0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == db3b1ec37979 drm/i915/tgl: Add new PCI IDs to TGL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev5)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev5) URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8144 -> Patchwork_17001 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/index.html Known issues Here are the changes found in Patchwork_17001 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live@execlists: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [i915#1430] / [i915#656]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-apl-guc/igt@i915_selftest@l...@execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/fi-apl-guc/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-cml-s: [PASS][3] -> [DMESG-FAIL][4] ([i915#877]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cml-s/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/fi-cml-s/igt@i915_selftest@live@gem_contexts.html Possible fixes * igt@i915_selftest@live@execlists: - fi-cml-u2: [INCOMPLETE][5] ([i915#283] / [i915#656]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cml-u2/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/fi-cml-u2/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gem_contexts: - fi-cfl-8700k: [INCOMPLETE][7] ([i915#424]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [i915#1430]: https://gitlab.freedesktop.org/drm/intel/issues/1430 [i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656 [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877 Participating hosts (45 -> 38) -- Additional (2): fi-kbl-soraka fi-kbl-7560u Missing(9): fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-skl-lmem fi-byt-clapper fi-skl-6600u fi-snb-2600 Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8144 -> Patchwork_17001 CI-20190529: 20190529 CI_DRM_8144: e22a73e6b26efdc18bd44d26c93e16c2783ab3f4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5517: b77e3a470bdf1bc5f047ebb98ed8ca4738dd44c7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17001: dad111ed0f4138aa9cea4cc980d1881b500726cf @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dad111ed0f41 drm/i915/gem: Avoid gem_context->mutex for simple vma lookup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev3) URL : https://patchwork.freedesktop.org/series/74759/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8142_full -> Patchwork_16996_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16996_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16996_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16996_full: ### IGT changes ### Possible regressions * igt@gem_set_tiling_vs_blt@untiled-to-tiled: - shard-iclb: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb1/igt@gem_set_tiling_vs_...@untiled-to-tiled.html New tests - New tests have been introduced between CI_DRM_8142_full and Patchwork_16996_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16996_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][2] -> [SKIP][3] ([fdo#110841]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb7/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#110854]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_balan...@smoke.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb5/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#112080]) +13 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@implicit-both-bsd: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#677]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb5/igt@gem_exec_sched...@implicit-both-bsd.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] / [i915#677]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd2.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb8/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +23 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112146]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][16] -> [FAIL][17] ([i915#644]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-glk3/igt@gem_pp...@flink-and-close-vma-leak.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-glk4/igt@gem_pp...@flink-and-close-vma-leak.html - shard-kbl: [PASS][18] -> [FAIL][19] ([i915#644]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-kbl1/igt@gem_pp...@flink-and-close-vma-leak.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-kbl3/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-kbl6/igt@i915_susp...@sysfs-reader.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16996/shard-kbl7/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@flip-vs-suspend: -
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix up documentation paths after file moving
== Series Details == Series: drm/i915: Fix up documentation paths after file moving URL : https://patchwork.freedesktop.org/series/74778/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8142_full -> Patchwork_16997_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16997_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16997_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16997_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@pi-common-render: - shard-skl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-skl9/igt@gem_exec_sched...@pi-common-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-skl2/igt@gem_exec_sched...@pi-common-render.html * igt@gem_set_tiling_vs_blt@untiled-to-tiled: - shard-iclb: NOTRUN -> [FAIL][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb5/igt@gem_set_tiling_vs_...@untiled-to-tiled.html * igt@perf_pmu@busy-no-semaphores-vecs0: - shard-tglb: [PASS][4] -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-tglb2/igt@perf_...@busy-no-semaphores-vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-tglb7/igt@perf_...@busy-no-semaphores-vecs0.html New tests - New tests have been introduced between CI_DRM_8142_full and Patchwork_16997_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16997_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-kbl: [PASS][6] -> [INCOMPLETE][7] ([i915#1402]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-kbl2/igt@gem_ctx_persiste...@close-replace-race.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-kbl4/igt@gem_ctx_persiste...@close-replace-race.html - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([i915#1402]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-skl8/igt@gem_ctx_persiste...@close-replace-race.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-skl5/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_ctx_persistence@processes: - shard-skl: [PASS][10] -> [FAIL][11] ([i915#570] / [i915#679]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-skl4/igt@gem_ctx_persiste...@processes.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-skl4/igt@gem_ctx_persiste...@processes.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#110854]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_balan...@smoke.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112080]) +10 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb2/igt@gem_exec_paral...@vcs1-fds.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb6/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109276] / [i915#677]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb4/igt@gem_exec_sched...@implicit-both-bsd2.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb7/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109276]) +22 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb5/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@pi-common-bsd: - shard-iclb: [PASS][20] -> [SKIP][21] ([i915#677]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8142/shard-iclb3/igt@gem_exec_sched...@pi-common-bsd.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16997/shard-iclb4/igt@gem_exec_sched...@pi-common-bsd.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][22] -> [S
Re: [Intel-gfx] [PATCH 07/10] cpufreq: intel_pstate: Implement VLP controller for HWP parts.
On Tue, 2020-03-10 at 14:42 -0700, Francisco Jerez wrote:
> This implements a simple variably low-pass-filtering governor in
> control of the HWP MIN/MAX PERF range based on the previously
> introduced get_vlp_target_range(). See "cpufreq: intel_pstate:
> Implement VLP controller target P-state range estimation." for the
> rationale.
I just gave a try on a pretty idle system with just systemd processes
and usual background tasks with nomodset.
I see that there HWP min is getting changed between 4-8. Why are
changing HWP dynamic range even on an idle system running no where
close to TDP?
Thanks,
Srinivas
>
> Signed-off-by: Francisco Jerez
> ---
> drivers/cpufreq/intel_pstate.c | 79
> +-
> 1 file changed, 77 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/intel_pstate.c
> b/drivers/cpufreq/intel_pstate.c
> index cecadfec8bc1..a01eed40d897 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -1905,6 +1905,20 @@ static void intel_pstate_reset_vlp(struct
> cpudata *cpu)
> vlp->gain = max(1, div_fp(1000, vlp_params.setpoint_0_pml));
> vlp->target.p_base = 0;
> vlp->stats.last_response_frequency_hz = vlp_params.avg_hz;
> +
> + if (hwp_active) {
> + const uint32_t p0 = max(cpu->pstate.min_pstate,
> + cpu->min_perf_ratio);
> + const uint32_t p1 = max_t(uint32_t, p0, cpu-
> >max_perf_ratio);
> + const uint64_t hwp_req = (READ_ONCE(cpu-
> >hwp_req_cached) &
> + ~(HWP_MAX_PERF(~0L) |
> + HWP_MIN_PERF(~0L) |
> + HWP_DESIRED_PERF(~0L))) |
> + HWP_MIN_PERF(p0) |
> HWP_MAX_PERF(p1);
> +
> + wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, hwp_req);
> + cpu->hwp_req_cached = hwp_req;
> + }
> }
>
> /**
> @@ -,6 +2236,46 @@ static void intel_pstate_adjust_pstate(struct
> cpudata *cpu)
> fp_toint(cpu->iowait_boost * 100));
> }
>
> +static void intel_pstate_adjust_pstate_range(struct cpudata *cpu,
> + const unsigned int
> range[])
> +{
> + const int from = cpu->hwp_req_cached;
> + unsigned int p0, p1, p_min, p_max;
> + struct sample *sample;
> + uint64_t hwp_req;
> +
> + update_turbo_state();
> +
> + p0 = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
> + p1 = max_t(unsigned int, p0, cpu->max_perf_ratio);
> + p_min = clamp_t(unsigned int, range[0], p0, p1);
> + p_max = clamp_t(unsigned int, range[1], p0, p1);
> +
> + trace_cpu_frequency(p_max * cpu->pstate.scaling, cpu->cpu);
> +
> + hwp_req = (READ_ONCE(cpu->hwp_req_cached) &
> +~(HWP_MAX_PERF(~0L) | HWP_MIN_PERF(~0L) |
> + HWP_DESIRED_PERF(~0L))) |
> + HWP_MIN_PERF(vlp_params.debug & 2 ? p0 : p_min) |
> + HWP_MAX_PERF(vlp_params.debug & 4 ? p1 : p_max);
> +
> + if (hwp_req != cpu->hwp_req_cached) {
> + wrmsrl(MSR_HWP_REQUEST, hwp_req);
> + cpu->hwp_req_cached = hwp_req;
> + }
> +
> + sample = &cpu->sample;
> + trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
> + fp_toint(sample->busy_scaled),
> + from,
> + hwp_req,
> + sample->mperf,
> + sample->aperf,
> + sample->tsc,
> + get_avg_frequency(cpu),
> + fp_toint(cpu->iowait_boost * 100));
> +}
> +
> static void intel_pstate_update_util(struct update_util_data *data,
> u64 time,
>unsigned int flags)
> {
> @@ -2260,6 +2314,22 @@ static void intel_pstate_update_util(struct
> update_util_data *data, u64 time,
> intel_pstate_adjust_pstate(cpu);
> }
>
> +/**
> + * Implementation of the cpufreq update_util hook based on the VLP
> + * controller (see get_vlp_target_range()).
> + */
> +static void intel_pstate_update_util_hwp_vlp(struct update_util_data
> *data,
> + u64 time, unsigned int
> flags)
> +{
> + struct cpudata *cpu = container_of(data, struct cpudata,
> update_util);
> +
> + if (update_vlp_sample(cpu, time, flags)) {
> + const struct vlp_target_range *target =
> + get_vlp_target_range(cpu);
> + intel_pstate_adjust_pstate_range(cpu, target->value);
> + }
> +}
> +
> static struct pstate_funcs core_funcs = {
> .get_max = core_get_max_pstate,
> .get_max_physical = core_get_max_pstate_physical,
> @@ -2389,6 +2459,9 @@ static int intel_pstate_init_cpu(unsigned int
> cpunum)
>
> intel_pstate_get_cpu_pstates(cpu);
>
> + if (pstate_funcs.update_util ==
> intel_pstate_update_util_hwp_vlp)
> +
Re: [Intel-gfx] [PATCH 1/4] drm/i915/perf: rework aging tail workaround
On 16/03/2020 21:23, Dixit, Ashutosh wrote:
On Thu, 12 Mar 2020 16:04:59 -0700, Umesh Nerlige Ramappa wrote:
From: Lionel Landwerlin
We're about to introduce an options to open the perf stream, giving
the user ability to configure how often it wants the kernel to poll
the OA registers for available data.
Right now the workaround against the OA tail pointer race condition
requires at least twice the internal kernel polling timer to make any
data available.
This changes introduce checks on the OA data written into the circular
buffer to make as much data as possible available on the first
iteration of the polling timer.
Excellent, this absolutely needs to be done, I was thinking it may be
possible even with the approach taken in the original code but the approach
here looks better. It is also a nice cleanup.
@@ -507,64 +487,76 @@ static bool oa_buffer_check_unlocked(struct
i915_perf_stream *stream)
now = ktime_get_mono_fast_ns();
- /* Update the aged tail
-*
-* Flip the tail pointer available for read()s once the aging tail is
-* old enough to trust that the corresponding data will be visible to
-* the CPU...
-*
-* Do this before updating the aging pointer in case we may be able to
-* immediately start aging a new pointer too (if new data has become
-* available) without needing to wait for a later hrtimer callback.
-*/
- if (aging_tail != INVALID_TAIL_PTR &&
- ((now - stream->oa_buffer.aging_timestamp) >
-OA_TAIL_MARGIN_NSEC)) {
-
- aged_idx ^= 1;
- stream->oa_buffer.aged_tail_idx = aged_idx;
+ if (hw_tail == stream->oa_buffer.aging_tail) {
+ /* If the HW tail hasn't move since the last check and the HW
+* tail has been aging for long enough, declare it the new
+* tail.
+*/
Is this really needed? True we will never return the last report but maybe
it's ok, save some code?
It doesn't look like a lot of code :)
+ if ((now - stream->oa_buffer.aging_timestamp) >
Do we need to initialize 'aging_timestamp = ktime_get_mono_fast_ns()' when
the stream is enabled?
Aye... I think aging_tail should probably be initialized to
INVALID_TAIL_PTR in init_oa_buffer() vfuncs.
So that on the first call it never matches : if (hw_tail ==
stream->oa_buffer.aging_tail)
And that aging_timestamp is set properly.
+ OA_TAIL_MARGIN_NSEC) {
+ stream->oa_buffer.tail =
+ stream->oa_buffer.aging_tail;
+ }
+ } else {
+ u32 head, tail, landed_report_heads;
- aged_tail = aging_tail;
+ /* NB: The head we observe here might effectively be a little
out of
+* date (between head and tails[aged_idx].offset if there is
currently
+* a read() in progress.
+*/
Is this comment correct? Aren't we are taking the same lock when updating
head after the read?
It seems the mention of tails[aged_idx].offset is definitely out of date.
That being said, the read is concurrent to this function (only the
update of head is locked).
That means the read code can be going through the reports while we're
going through a different set of reports in the same OA buffer.
+ head = stream->oa_buffer.head - gtt_offset;
- /* Mark that we need a new pointer to start aging... */
- stream->oa_buffer.tails[!aged_idx].offset = INVALID_TAIL_PTR;
- aging_tail = INVALID_TAIL_PTR;
- }
+ hw_tail -= gtt_offset;
- /* Update the aging tail
-*
-* We throttle aging tail updates until we have a new tail that
-* represents >= one report more data than is already available for
-* reading. This ensures there will be enough data for a successful
-* read once this new pointer has aged and ensures we will give the new
-* pointer time to age.
-*/
- if (aging_tail == INVALID_TAIL_PTR &&
- (aged_tail == INVALID_TAIL_PTR ||
-OA_TAKEN(hw_tail, aged_tail) >= report_size)) {
- struct i915_vma *vma = stream->oa_buffer.vma;
- u32 gtt_offset = i915_ggtt_offset(vma);
-
- /* Be paranoid and do a bounds check on the pointer read back
-* from hardware, just in case some spurious hardware condition
-* could put the tail out of bounds...
+ /* Walk the stream backward until we find at least 2 reports
+* with dword 0 & 1 not at 0. Since the circular buffer
+* pointers progress by increments of 64 bytes and that
+* reports can be up to 256 bytes long, we can't tell whether
+* a report has fully landed in memory before the first 2
+* dwor
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Always reschedule the new heartbeat
== Series Details == Series: drm/i915/gt: Always reschedule the new heartbeat URL : https://patchwork.freedesktop.org/series/74791/ State : success == Summary == CI Bug Log - changes from CI_DRM_8143_full -> Patchwork_16998_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_16998_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16998_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16998_full: ### IGT changes ### Warnings * igt@gem_exec_schedule@preempt-queue-chain-render: - shard-skl: [FAIL][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-skl8/igt@gem_exec_sched...@preempt-queue-chain-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-skl4/igt@gem_exec_sched...@preempt-queue-chain-render.html New tests - New tests have been introduced between CI_DRM_8143_full and Patchwork_16998_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16998_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-apl4/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_persistence@close-replace-race: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([i915#1402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-iclb2/igt@gem_ctx_persiste...@close-replace-race.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-iclb3/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_eio@suspend: - shard-glk: [PASS][7] -> [INCOMPLETE][8] ([i915#58] / [k.org#198133]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-glk9/igt@gem_...@suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-glk2/igt@gem_...@suspend.html * igt@gem_exec_schedule@implicit-read-write-bsd2: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276] / [i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-iclb6/igt@gem_exec_sched...@implicit-read-write-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-iclb3/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-iclb2/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +10 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-iclb7/igt@gem_exec_sched...@preempt-other-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-kbl2/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143/shard-skl1/igt@kms_...@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16998/shard-skl8/igt@kms_...@bpc-switch-dpms.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8143
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add new PCI IDs to TGL
== Series Details == Series: drm/i915/tgl: Add new PCI IDs to TGL URL : https://patchwork.freedesktop.org/series/74795/ State : success == Summary == CI Bug Log - changes from CI_DRM_8144_full -> Patchwork_17000_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8144_full and Patchwork_17000_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_17000_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +9 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb4/igt@gem_ctx_isolat...@vcs1-nonpriv.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-iclb5/igt@gem_ctx_isolat...@vcs1-nonpriv.html * igt@gem_ctx_persistence@close-replace-race: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#1402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl7/igt@gem_ctx_persiste...@close-replace-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-skl7/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_exec_schedule@implicit-read-write-bsd2: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [i915#677]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb1/igt@gem_exec_sched...@implicit-read-write-bsd2.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd2.html * igt@gem_exec_schedule@pi-distinct-iova-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb7/igt@gem_exec_sched...@pi-distinct-iova-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-iclb1/igt@gem_exec_sched...@pi-distinct-iova-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#644]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl6/igt@gem_pp...@flink-and-close-vma-leak.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-skl9/igt@gem_pp...@flink-and-close-vma-leak.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl3/igt@i915_susp...@sysfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-skl5/igt@i915_susp...@sysfs-reader.html * igt@kms_flip@plain-flip-ts-check-interruptible: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#34]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-apl7/igt@kms_f...@plain-flip-ts-check-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-apl3/igt@kms_f...@plain-flip-ts-check-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-kbl3/igt@kms_frontbuffer_track...@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-kbl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl7/igt@kms_...@bpc-switch.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-skl6/igt@kms_...@bpc-switch.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#648]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17000/shard-kbl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl4/igt@kms_plane_alpha_bl...@pipe
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev5)
== Series Details == Series: drm/i915/gem: Avoid gem_context->mutex for simple vma lookup (rev5) URL : https://patchwork.freedesktop.org/series/74759/ State : success == Summary == CI Bug Log - changes from CI_DRM_8144_full -> Patchwork_17001_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_8144_full and Patchwork_17001_full: ### New IGT tests (1) ### * igt@sysfs_preempt_timeout@idempotent: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_17001_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@busy-vcs1: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +12 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb1/igt@gem_b...@busy-vcs1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-iclb6/igt@gem_b...@busy-vcs1.html * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl10/igt@gem_ctx_isolat...@rcs0-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-skl5/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb1/igt@gem_exec_sched...@implicit-both-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-iclb6/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +21 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb1/igt@gem_exec_sched...@independent-bsd2.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-iclb6/igt@gem_exec_sched...@independent-bsd2.html * igt@gem_exec_schedule@pi-common-bsd: - shard-iclb: [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb3/igt@gem_exec_sched...@pi-common-bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-iclb2/igt@gem_exec_sched...@pi-common-bsd.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-iclb2/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-snb4/igt@kms_atomic_transit...@1x-modeset-transitions-nonblocking-fencing.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-snb4/igt@kms_atomic_transit...@1x-modeset-transitions-nonblocking-fencing.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][17] -> [FAIL][18] ([i915#72]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-skl6/igt@kms_...@bpc-switch-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-skl1/igt@kms_...@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#648]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8144/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17001/shard-kbl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_
[Intel-gfx] [PATCH v9 00/11] Convert PWM period and duty cycle to u64
Because period and duty cycle are defined in the PWM framework structs as ints with units of nanoseconds, the maximum time duration that can be set is limited to ~2.147 seconds. Consequently, applications desiring to set greater time periods via the PWM framework are not be able to do so - like, for instance, causing an LED to blink at an interval of 5 seconds. Redefining the period and duty cycle struct members in the core PWM framework structs as u64 values will enable larger time durations to be set and solve this problem. Such a change to the framework mandates that drivers using these struct members (and corresponding helper functions) also be modified correctly in order to prevent compilation errors. This patch series introduces the changes to all the drivers first, followed by the framework change at the very end so that when the latter is applied, all the drivers are in good shape and there are no compilation errors. Changes from v8: - Gathered all received "Acked-by: " and "Reviewed-by: " tags - Dropped patch to clk-pwm.c for reasons mentiond in [2] - Expanded audience of unreviewed patches Changes from v7: - Changed commit messages of all patches to be brief and to the point. - Added explanation of change in cover letter. - Dropped change to pwm-sti.c as upon review it was unnecessary as struct pwm_capture is not being modified in the PWM core. Changes from v6: - Split out the driver changes out into separate patches, one patch per file for ease of reviewing. Changes from v5: - Dropped the conversion of struct pwm_capture to u64 for reasons mentioned in https://www.spinics.net/lists/linux-pwm/msg11541.html Changes from v4: - Split the patch into two: one for changes to the drivers, and the actual switch to u64 for ease of reverting should the need arise. - Re-examined the patch and made the following corrections: * intel_panel.c: DIV64_U64_ROUND_UP -> DIV_ROUND_UP_ULL (as only the numerator would be 64-bit in this case). * pwm-sti.c: do_div -> div_u64 (do_div is optimized only for x86 architectures, and div_u64's comment block suggests to use this as much as possible). Changes from v3: - Rebased to current tip of for-next. Changes from v2: - Fixed %u -> %llu in a dev_dbg in pwm-stm32-lp.c, thanks to kbuild test robot - Added a couple of fixes to pwm-imx-tpm.c and pwm-sifive.c Changes from v1: - Fixed compilation errors seen when compiling for different archs. v1: - Reworked the change pushed upstream earlier [1] so as to not add an extension to an obsolete API. With this change, pwm_ops->apply() can be used to set pwm_state parameters as usual. [1] https://lore.kernel.org/lkml/20190916140048.GB7488@ulmo/ [2] https://lore.kernel.org/lkml/20200312190859.ga19...@codeaurora.org/ Guru Das Srinagesh (11): drm/i915: Use 64-bit division macro hwmon: pwm-fan: Use 64-bit division macro ir-rx51: Use 64-bit division macro pwm: clps711x: Use 64-bit division macro pwm: pwm-imx-tpm: Use 64-bit division macro pwm: imx27: Use 64-bit division macro and function pwm: sifive: Use 64-bit division macro pwm: stm32-lp: Use %llu format specifier for period pwm: sun4i: Use 64-bit division function backlight: pwm_bl: Use 64-bit division function pwm: core: Convert period and duty cycle to u64 drivers/gpu/drm/i915/display/intel_panel.c | 2 +- drivers/hwmon/pwm-fan.c| 2 +- drivers/media/rc/ir-rx51.c | 3 ++- drivers/pwm/core.c | 4 ++-- drivers/pwm/pwm-clps711x.c | 2 +- drivers/pwm/pwm-imx-tpm.c | 2 +- drivers/pwm/pwm-imx27.c| 5 ++--- drivers/pwm/pwm-sifive.c | 2 +- drivers/pwm/pwm-stm32-lp.c | 2 +- drivers/pwm/pwm-sun4i.c| 2 +- drivers/pwm/sysfs.c| 8 drivers/video/backlight/pwm_bl.c | 3 ++- include/linux/pwm.h| 12 ++-- 13 files changed, 25 insertions(+), 24 deletions(-) Cc: Lee Jones Cc: Daniel Thompson Cc: Jingoo Han Cc: Bartlomiej Zolnierkiewicz Cc: linux-fb...@vger.kernel.org Cc: Maxime Ripard Cc: Chen-Yu Tsai Cc: Philipp Zabel Cc: Fabrice Gasnier Cc: Maxime Coquelin Cc: Alexandre Torgue Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: linux-ri...@lists.infradead.org Cc: Yash Shah Cc: Atish Patra Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Alexander Shiyan Cc: Mauro Carvalho Chehab Cc: Richard Fontana Cc: Thomas Gleixner Cc: Kate Stewart Cc: Allison Randal Cc: linux-me...@vger.kernel.org Cc: Kamil Debski Cc: Bartlomiej Zolnierkiewicz Cc: Jean Delvare Cc: Guenter Roeck Cc: Liam Girdwood Cc: Mark Brown Cc: linux-hw...@vger.kernel.org Cc: Jani Nikula Cc: Joonas Lahti
[Intel-gfx] [PATCH v9 01/11] drm/i915: Use 64-bit division macro
Since the PWM framework is switching struct pwm_state.duty_cycle's datatype to u64, prepare for this transition by using DIV_ROUND_UP_ULL to handle a 64-bit dividend. Cc: Jani Nikula Cc: Joonas Lahtinen Cc: David Airlie Cc: Daniel Vetter Cc: Chris Wilson Cc: "Ville Syrjälä" Cc: intel-gfx@lists.freedesktop.org Cc: dri-de...@lists.freedesktop.org Cc: Rodrigo Vivi Cc: Maarten Lankhorst Signed-off-by: Guru Das Srinagesh --- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index bc14e9c..843cac1 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1868,7 +1868,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ - panel->backlight.level = DIV_ROUND_UP( + panel->backlight.level = DIV_ROUND_UP_ULL( pwm_get_duty_cycle(panel->backlight.pwm) * 100, CRC_PMIC_PWM_PERIOD_NS); panel->backlight.enabled = panel->backlight.level != 0; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
DP sink device sets the Ignore MSA bit in its
DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
ignore the MSA video timing paramaters and its ability to support
seamless video timing change over a range of timing exposed by
DisplayID and EDID.
This is required for the sink to indicate that it is Adaptive sync
capable.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Nicholas Kazlauskas
Signed-off-by: Manasi Navare
---
include/drm/drm_dp_helper.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c6119e4c169a..ccd6e2e988b9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8
dpcd[DP_RECEIVER_CAP_SIZE])
DP_ALTERNATE_SCRAMBLER_RESET_CAP;
}
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
+static inline bool
+drm_dp_sink_is_capable_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
+ DP_MSA_TIMING_PAR_IGNORED;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.19.1
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[Intel-gfx] [PATCH 3/3] drm/i915/dp: intel_dp connector hook for VRR support
This defines the get_vrr_support hook for intel DP connector
VRR support is set to true based on the DPCD ignore MSA and
EDID monitor range
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Nicholas Kazlauskas
Cc: Aditya Swarup
Signed-off-by: Manasi Navare
---
.../drm/i915/display/intel_display_types.h| 3 +++
drivers/gpu/drm/i915/display/intel_dp.c | 19 +++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5e00e611f077..cd37ee6db1ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1353,6 +1353,9 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
+
+ /* DP Variable refresh rate/ Adaptive sync support */
+ bool vrr_capable;
};
enum lspcon_vendor {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0a417cd2af2b..ccf5d868b5c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5860,6 +5860,24 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
return 0;
}
+static void intel_dp_get_vrr_support(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp =
intel_attached_dp(to_intel_connector(connector));
+ const struct drm_display_info *info = &connector->display_info;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ /*
+* DP Sink is capable of Variable refresh video timings if
+* Ignore MSA bit is set in DPCD.
+* EDID monitor range also should be atleast 10 for reasonable
+* Adaptive sync/ VRR end user experience.
+*/
+ if (INTEL_GEN(dev_priv) >= 12 &&
+ drm_dp_sink_is_capable_without_timing_msa(intel_dp->dpcd) &&
+ info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10)
+ intel_dp->vrr_capable = true;
+}
+
static int
intel_dp_connector_register(struct drm_connector *connector)
{
@@ -6756,6 +6774,7 @@ static const struct drm_connector_helper_funcs
intel_dp_connector_helper_funcs =
.get_modes = intel_dp_get_modes,
.mode_valid = intel_dp_mode_valid,
.atomic_check = intel_dp_connector_atomic_check,
+ .get_adaptive_sync_support = intel_dp_get_vrr_support,
};
static const struct drm_encoder_funcs intel_dp_enc_funcs = {
--
2.19.1
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[Intel-gfx] [PATCH 2/3] drm: Create a drm_connector_helper_funcs hook for Adaptive Sync support
This patch adds a hook in drm_connector_helper_funcs to get the
support of the driver for adaptive sync functionality.
This can be called in the connector probe helper function after
the connector detect() and get_modes() hooks to also
query the adaptive sync support of the driver.
Cc: Jani Nikula
Cc: Ville Syrjälä
Cc: Harry Wentland
Cc: Nicholas Kazlauskas
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/drm_probe_helper.c | 4
include/drm/drm_modeset_helper_vtables.h | 16
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 576b4b7dcd89..4403817bfb02 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -482,6 +482,10 @@ int drm_helper_probe_single_connector_modes(struct
drm_connector *connector,
count = (*connector_funcs->get_modes)(connector);
+ /* Get the Adaptive Sync Support if helper exists */
+ if (*connector_funcs->get_adaptive_sync_support)
+ (**connector_funcs->get_adaptive_sync_support)(connector);
+
/*
* Fallback for when DDC probe failed in drm_get_edid() and thus skipped
* override/firmware EDID.
diff --git a/include/drm/drm_modeset_helper_vtables.h
b/include/drm/drm_modeset_helper_vtables.h
index 7c20b1c8b6a7..0b203fdd25df 100644
--- a/include/drm/drm_modeset_helper_vtables.h
+++ b/include/drm/drm_modeset_helper_vtables.h
@@ -1079,6 +1079,22 @@ struct drm_connector_helper_funcs {
struct drm_writeback_job *job);
void (*cleanup_writeback_job)(struct drm_writeback_connector *connector,
struct drm_writeback_job *job);
+
+ /**
+* @get_adaptive_sync_support:
+*
+* This hook is used by the probe helper to get the driver's support
+* for adaptive sync or variable refresh rate.
+* This is called from drm_helper_probe_single_connector_modes()
+* This is called after the @get_modes hook so that the connector modes
+* are already obtained and EDID is parsed to obtain the monitor
+* range descriptor information.
+*
+* This hook is optional and defined only for the drivers and on
+* connectors that advertise adaptive sync support.
+*
+*/
+ void (*get_adaptive_sync_support)(struct drm_connector *connector);
};
/**
--
2.19.1
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[Intel-gfx] [PATCH v6 6/7] drm/i915/dp: Register definition for DP compliance register
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
v3: used trans_offset for offset calculation. [Manasi]
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 309cb7d96b35..8b6c9fbfe74b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9792,6 +9792,22 @@ enum skl_power_gate {
#define DDI_BUF_BALANCE_LEG_ENABLE(1 << 31)
#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A,
_DDI_BUF_TRANS_B) + (i) * 8 + 4)
+/* DDI DP Compliance Control */
+#define _DDI_DP_COMP_CTL_A 0x605F0
+#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe,
_DDI_DP_COMP_CTL_A)
+#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
+#define DDI_DP_COMP_CTL_D10_2(0 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
+#define DDI_DP_COMP_CTL_PRBS7(2 << 28)
+#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
+#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
+#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
+#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
+
+/* DDI DP Compliance Pattern */
+#define _DDI_DP_COMP_PAT_A 0x605F4
+#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_TRANS2(pipe,
_DDI_DP_COMP_PAT_A) + (i) * 4)
+
/* Sideband Interface (SBI) is programmed indirectly, via
* SBI_ADDR, which contains the register offset; and SBI_DATA,
* which contains the payload */
--
2.24.0
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