[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Replace zero-length array with flexible-array member
== Series Details == Series: drm: Replace zero-length array with flexible-array member URL : https://patchwork.freedesktop.org/series/73916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8008_full -> Patchwork_16708_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16708_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16708_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16708_full: ### IGT changes ### Possible regressions * igt@gem_exec_whisper@basic-fds-priority: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-tglb8/igt@gem_exec_whis...@basic-fds-priority.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-tglb6/igt@gem_exec_whis...@basic-fds-priority.html * igt@sw_sync@sync_multi_producer_single_consumer: - shard-skl: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-skl8/igt@sw_sync@sync_multi_producer_single_consumer.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-skl8/igt@sw_sync@sync_multi_producer_single_consumer.html Known issues Here are the changes found in Patchwork_16708_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-mixed-process@default: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#679]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-skl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@default.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-skl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@default.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@render: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#1239]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-skl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-skl8/igt@gem_ctx_persistence@legacy-engines-mixed-proc...@render.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112080]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-iclb6/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@implicit-read-write-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-iclb8/igt@gem_exec_sched...@implicit-read-write-bsd1.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-glk7/igt@gem_pp...@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-glk1/igt@gem_pp...@flink-and-close-vma-leak.html - shard-kbl: [PASS][17] -> [FAIL][18] ([i915#644]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-kbl2/igt@gem_pp...@flink-and-close-vma-leak.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-kbl3/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-apl4/igt@gem_workarou...@suspend-resume-context.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16708/shard-apl4/igt@gem_workarou...@suspend-resume-context.html * igt@i915_selftest@live_gt_heartbeat: - shard-skl: [PASS][21] -> [DMESG-FAIL][22] ([fdo#112406]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-skl1/igt@i915_selftest@live_gt_heartbeat.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_1670
Re: [Intel-gfx] [PATCH 01/10] drm/i915: Add i915 device based MISSING_CASE macro
On Thu, 27 Feb 2020, "Laxminarayan Bharadiya, Pankaj" wrote: > Hi Chris, > >> -Original Message- >> From: Chris Wilson >> Sent: 25 February 2020 19:32 >> To: David Airlie ; Joonas Lahtinen >> ; Laxminarayan Bharadiya, Pankaj >> ; Vivi, Rodrigo >> ; dan...@ffwll.ch; dri-de...@lists.freedesktop.org; >> intel-gfx@lists.freedesktop.org; jani.nik...@linux.intel.com >> Cc: Laxminarayan Bharadiya, Pankaj >> >> Subject: Re: [Intel-gfx][PATCH 01/10] drm/i915: Add i915 device based >> MISSING_CASE macro >> >> Quoting Pankaj Bharadiya (2020-02-25 13:47:00) >> > Now that we have struct drm_device based drm_WARN, introduce struct >> > drm_i915_private based i915_MISSING_CASE macro which uses >> drm_WARN so >> > that device specific information will also get printed in backtrace. >> > >> > i915_MISSING_CASE macro should be preferred over MISSING_CASE, >> > wherever possible. >> >> Whatever for? MISSING_CASE() itself should be a complete picture for the >> forgotten code. > > Are you saying, no need to have a new device specific macro? > > We want convert all the calls of WARN* with device specific drm_WARN* > in i915, hence I introduced new i915_MISSING_CASE macro. > > Jani, Will you please share your opinion on this? In general, many or most WARNs are device specific, and the device information is useful. However MISSING_CASE is about the *code*. That was the intent anyway. Perhaps there are cases where the device information might be useful, but for most cases probably not. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits
We need to be extremely careful inside i915_request_await_start() as it
needs to walk the list of requests in the foreign timeline with very
little protection. As we hold our own timeline mutex, we can not nest
inside the signaler's timeline mutex, so all that remains is our RCU
protection. However, to be safe we need to tell the compiler that we may
be traversing the list only under RCU protection, and furthermore we
need to start declaring requests as elements of the timeline from their
construction.
Fixes: 9ddc8ec027a3 ("drm/i915: Eliminate the trylock for awaiting an earlier
request")
Fixes: 6a79d848403d ("drm/i915: Lock signaler timeline while navigating")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 41 -
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d53af93b919b..e5a55801f753 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -290,7 +290,7 @@ bool i915_request_retire(struct i915_request *rq)
spin_unlock_irq(&rq->lock);
remove_from_client(rq);
- list_del(&rq->link);
+ list_del_rcu(&rq->link);
intel_context_exit(rq->context);
intel_context_unpin(rq->context);
@@ -736,6 +736,8 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
rq->infix = rq->ring->emit; /* end of header; start of user payload */
intel_context_mark_active(ce);
+ list_add_tail_rcu(&rq->link, &tl->requests);
+
return rq;
err_unwind:
@@ -792,13 +794,23 @@ i915_request_await_start(struct i915_request *rq, struct
i915_request *signal)
GEM_BUG_ON(i915_request_timeline(rq) ==
rcu_access_pointer(signal->timeline));
+ if (i915_request_started(signal))
+ return 0;
+
fence = NULL;
rcu_read_lock();
spin_lock_irq(&signal->lock);
- if (!i915_request_started(signal) &&
- !list_is_first(&signal->link,
- &rcu_dereference(signal->timeline)->requests)) {
- struct i915_request *prev = list_prev_entry(signal, link);
+ do {
+ struct list_head *pos = READ_ONCE(signal->link.prev);
+ struct i915_request *prev;
+
+ /* Confirm signal has not been retired, the link is valid */
+ if (unlikely(i915_request_started(signal)))
+ break;
+
+ /* Is signal the earliest request on its timeline? */
+ if (pos == &rcu_dereference(signal->timeline)->requests)
+ break;
/*
* Peek at the request before us in the timeline. That
@@ -806,13 +818,18 @@ i915_request_await_start(struct i915_request *rq, struct
i915_request *signal)
* after acquiring a reference to it, confirm that it is
* still part of the signaler's timeline.
*/
- if (i915_request_get_rcu(prev)) {
- if (list_next_entry(prev, link) == signal)
- fence = &prev->fence;
- else
- i915_request_put(prev);
+ prev = list_entry(pos, typeof(*prev), link);
+ if (!i915_request_get_rcu(prev))
+ break;
+
+ /* After the strong barrier, confirm prev is still attached */
+ if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
+ i915_request_put(prev);
+ break;
}
- }
+
+ fence = &prev->fence;
+ } while (0);
spin_unlock_irq(&signal->lock);
rcu_read_unlock();
if (!fence)
@@ -1253,8 +1270,6 @@ __i915_request_add_to_timeline(struct i915_request *rq)
0);
}
- list_add_tail(&rq->link, &timeline->requests);
-
/*
* Make sure that no request gazumped us - if it was allocated after
* our i915_request_alloc() and called __i915_request_add() before
--
2.25.1
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[Intel-gfx] [PATCH 04/20] drm/i915/perf: Wait for lrc_reconfigure on disable
Wait for the last request (and so waits for all context updates) when
disabling OA. This prevents a rather bizarre error seen on Skylake
where the context is subsequently corrupted. Let's play safe and assume
it may impact all.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2334c45f1d08..20c68b5dea63 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2191,7 +2191,8 @@ static int gen8_modify_context(struct intel_context *ce,
}
static int gen8_modify_self(struct intel_context *ce,
- const struct flex *flex, unsigned int count)
+ const struct flex *flex, unsigned int count,
+ bool sync)
{
struct i915_request *rq;
int err;
@@ -2204,7 +2205,12 @@ static int gen8_modify_self(struct intel_context *ce,
err = gen8_load_flex(rq, ce, flex, count);
+ i915_request_get(rq);
i915_request_add(rq);
+ if (sync && i915_request_wait(rq, 0, HZ) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
return err;
}
@@ -2281,7 +2287,7 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream, bool ena
return err;
/* Apply regs_lri using LRI with pinned context */
- return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri));
+ return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), false);
}
/*
@@ -2311,7 +2317,8 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream, bool ena
*/
static int oa_configure_all_contexts(struct i915_perf_stream *stream,
struct flex *regs,
-size_t num_regs)
+size_t num_regs,
+bool enable)
{
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
@@ -2368,7 +2375,7 @@ static int oa_configure_all_contexts(struct
i915_perf_stream *stream,
regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
- err = gen8_modify_self(ce, regs, num_regs);
+ err = gen8_modify_self(ce, regs, num_regs, !enable);
if (err)
return err;
}
@@ -2386,7 +2393,9 @@ static int gen12_configure_all_contexts(struct
i915_perf_stream *stream,
},
};
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+regs, ARRAY_SIZE(regs),
+oa_config);
}
static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
@@ -2423,7 +2432,9 @@ static int lrc_configure_all_contexts(struct
i915_perf_stream *stream,
for (i = 2; i < ARRAY_SIZE(regs); i++)
regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+regs, ARRAY_SIZE(regs),
+oa_config);
}
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
--
2.25.1
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[Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 189 ++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
2 files changed, 98 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..46e5e6116b7f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e,
unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,100 @@ static void kill_engines(struct i915_gem_engines
*engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err = 0;
+
+ /* serialises with
[Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
The engine->kernel_context is a special case for request emission. Since it is used as the barrier within the engine's wakeref, we must acquire the wakeref before submitting a request to the kernel_context. Reported-by: Lionel Landwerlin Signed-off-by: Chris Wilson Cc: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_perf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 0838a12e2dc5..2334c45f1d08 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2196,7 +2196,9 @@ static int gen8_modify_self(struct intel_context *ce, struct i915_request *rq; int err; + intel_engine_pm_get(ce->engine); rq = i915_request_create(ce); + intel_engine_pm_put(ce->engine); if (IS_ERR(rq)) return PTR_ERR(rq); -- 2.25.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/20] drm/i915/selftests: Check recovery from corrupted LRC
Check that we can recover if the LRC is totally corrupted. Based on a
very simple theory that anything that can be adjusted via the context
(i.e. on behalf of the user), should be under the purview of the
per-engine-reset.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 135 +
1 file changed, 135 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 810f7857ad26..d7f98aada626 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -5292,6 +5292,140 @@ static int live_lrc_isolation(void *arg)
return 0;
}
+static void garbage_reset(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ const unsigned int bit = I915_RESET_ENGINE + engine->id;
+ unsigned long *lock = &engine->gt->reset.flags;
+
+ if (test_and_set_bit(bit, lock))
+ return;
+
+ tasklet_disable(&engine->execlists.tasklet);
+
+ if (!rq->fence.error)
+ intel_engine_reset(engine, NULL);
+
+ tasklet_enable(&engine->execlists.tasklet);
+ clear_and_wake_up_bit(bit, lock);
+}
+
+static struct i915_request *garbage(struct intel_context *ce,
+ struct rnd_state *prng)
+{
+ struct i915_request *rq;
+ int err;
+
+ err = intel_context_pin(ce);
+ if (err)
+ return ERR_PTR(err);
+
+ prandom_bytes_state(prng,
+ ce->lrc_reg_state,
+ ce->engine->context_size -
+ LRC_STATE_PN * PAGE_SIZE);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+
+err_unpin:
+ intel_context_unpin(ce);
+ return ERR_PTR(err);
+}
+
+static int __lrc_garbage(struct intel_engine_cs *engine, struct rnd_state
*prng)
+{
+ struct intel_context *ce;
+ struct i915_request *hang;
+ int err = 0;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ hang = garbage(ce, prng);
+ if (IS_ERR(hang)) {
+ err = PTR_ERR(hang);
+ goto err_ce;
+ }
+
+ if (wait_for_submit(engine, hang, HZ / 2)) {
+ i915_request_put(hang);
+ err = -ETIME;
+ goto err_ce;
+ }
+
+ intel_context_set_banned(ce);
+ garbage_reset(engine, hang);
+
+ intel_engine_flush_submission(engine);
+ if (!hang->fence.error) {
+ i915_request_put(hang);
+ pr_err("%s: corrupted context was not reset\n",
+ engine->name);
+ err = -EINVAL;
+ goto err_ce;
+ }
+
+ if (i915_request_wait(hang, 0, HZ / 2) < 0) {
+ pr_err("%s: corrupted context did not recover\n",
+ engine->name);
+ i915_request_put(hang);
+ err = -EIO;
+ goto err_ce;
+ }
+ i915_request_put(hang);
+
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_lrc_garbage(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+* Verify that we can recover if one context state is completely
+* corrupted.
+*/
+
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ I915_RND_STATE(prng);
+ int err = 0, i;
+
+ if (!intel_has_reset_engine(engine->gt))
+ continue;
+
+ intel_engine_pm_get(engine);
+ for (i = 0; i < 3; i++) {
+ err = __lrc_garbage(engine, &prng);
+ if (err)
+ break;
+ }
+ intel_engine_pm_put(engine);
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int __live_pphwsp_runtime(struct intel_engine_cs *engine)
{
struct intel_context *ce;
@@ -5391,6 +5525,7 @@ int intel_lrc_live_selftests(struct drm_i915_private
*i915)
SUBTEST(live_lrc_gpr),
SUBTEST(live_lrc_isolation),
SUBTEST(live_lrc_timestamp),
+ SUBTEST(live_lrc_garbage),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 29c8c03c5caa..a32dc82a90d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -326,7 +326,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs
*engine)
if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
return false;
- return intel_engine_has_semaphores(engine);
+ return (intel_engine_has_semaphores(engine) &&
+ intel_engine_has_preemption(engine));
}
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..b84fdd722781 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private
*i915)
else
disabled |= BIT(map[i].sched);
}
+
+ if (intel_engine_has_timeslices(engine))
+ enabled |= I915_SCHEDULER_CAP_TIMESLICING;
+ else
+ disabled |= I915_SCHEDULER_CAP_TIMESLICING;
}
i915->caps.scheduler = enabled & ~disabled;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2813e579b480..4f903431a3fe 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES(1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
An odd and highly unlikely path caught us out. On delayed submission
(due to an asynchronous reset handler), we poked the priority_hint and
kicked the tasklet. However, we had already marked the device as wedged
and swapped out the tasklet for a no-op. The result was that we never
cleared the priority hint and became upset when we later checked.
<0> [574.303565] i915_sel-62782 481822445us : __i915_subtests: Running
intel_execlists_live_selftests/live_error_interrupt
<0> [574.303565] i915_sel-62782 481822472us : __engine_unpark:
:00:02.0 rcs0:
<0> [574.303565] i915_sel-62782 481822491us : __gt_unpark: :00:02.0
<0> [574.303565] i915_sel-62782 481823220us : execlists_context_reset:
:00:02.0 rcs0: context:f4ee reset
<0> [574.303565] i915_sel-62782 481824830us : __intel_context_active:
:00:02.0 rcs0: context:f51b active
<0> [574.303565] i915_sel-62782 481825258us : __intel_context_do_pin:
:00:02.0 rcs0: context:f51b pin ring:{start:6000, head:, tail:}
<0> [574.303565] i915_sel-62782 481825311us : __i915_request_commit:
:00:02.0 rcs0: fence f51b:2, current 0
<0> [574.303565] i915_sel-62782d..1 481825347us : __i915_request_submit:
:00:02.0 rcs0: fence f51b:2, current 0
<0> [574.303565] i915_sel-62782d..1 481825363us : trace_ports: :00:02.0
rcs0: submit { f51b:2, 0:0 }
<0> [574.303565] i915_sel-62782 481826809us : __intel_context_active:
:00:02.0 rcs0: context:f51c active
<0> [574.303565] -0 7d.h2 481827326us : cs_irq_handler:
:00:02.0 rcs0: CS error: 1
<0> [574.303565] -0 7..s1 481827377us : process_csb: :00:02.0
rcs0: cs-irq head=3, tail=4
<0> [574.303565] -0 7..s1 481827379us : process_csb: :00:02.0
rcs0: csb[4]: status=0x1001:0x
<0> [574.305593] -0 7..s1 481827385us : trace_ports: :00:02.0
rcs0: promote { f51b:2*, 0:0 }
<0> [574.305611] -0 7..s1 481828179us : execlists_reset:
:00:02.0 rcs0: reset for CS error
<0> [574.305611] i915_sel-62782 481828284us : __intel_context_do_pin:
:00:02.0 rcs0: context:f51c pin ring:{start:7000, head:, tail:}
<0> [574.305611] i915_sel-62782 481828345us : __i915_request_commit:
:00:02.0 rcs0: fence f51c:2, current 0
<0> [574.305611] -0 7dNs2 481847823us : __i915_request_unsubmit:
:00:02.0 rcs0: fence f51b:2, current 1
<0> [574.305611] -0 7dNs2 481847857us : execlists_hold:
:00:02.0 rcs0: fence f51b:2, current 1 on hold
<0> [574.305611] -0 7.Ns1 481847863us : intel_engine_reset:
:00:02.0 rcs0: flags=4
<0> [574.305611] -0 7.Ns1 481847945us : execlists_reset_prepare:
:00:02.0 rcs0: depth<-1
<0> [574.305611] -0 7.Ns1 481847946us : intel_engine_stop_cs:
:00:02.0 rcs0:
<0> [574.305611] -0 7.Ns1 538584284us : intel_engine_stop_cs:
:00:02.0 rcs0: timed out on STOP_RING -> IDLE
<0> [574.305611] -0 7.Ns1 538584347us : __intel_gt_reset:
:00:02.0 engine_mask=1
<0> [574.305611] -0 7.Ns1 538584406us : execlists_reset_rewind:
:00:02.0 rcs0:
<0> [574.305611] -0 7dNs2 538585050us : __i915_request_reset:
:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
<0> [574.305611] -0 7dNs2 538585063us : __execlists_reset:
:00:02.0 rcs0: replay {head:, tail:0068}
<0> [574.306565] -0 7.Ns1 538588457us :
intel_engine_cancel_stop_cs: :00:02.0 rcs0:
<0> [574.306565] -0 7dNs2 538588462us : __i915_request_submit:
:00:02.0 rcs0: fence f51c:2, current 0
<0> [574.306565] -0 7dNs2 538588471us : trace_ports: :00:02.0
rcs0: submit { f51c:2, 0:0 }
<0> [574.306565] -0 7.Ns1 538588474us : execlists_reset_finish:
:00:02.0 rcs0: depth->1
<0> [574.306565] kworker/-202 2 538588755us : i915_request_retire:
:00:02.0 rcs0: fence f51c:2, current 2
<0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: :00:02.0
rcs0: cs-irq head=11, tail=1
<0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: :00:02.0
rcs0: csb[0]: status=0x1001:0x
<0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: :00:02.0
rcs0: promote { f51c:2!, 0:0 }
<0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: :00:02.0
rcs0: csb[1]: status=0x1018:0x0020
<0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: :00:02.0
rcs0: completed { f51c:2!, 0:0 }
<0> [574.306565] kworker/-202 2 538588826us : intel_context_unpin:
:00:02.0 rcs0: context:f51c unpin
<0> [574.306565] i915_sel-62786 538589663us :
__intel_gt_set_wedged.part.32: :00:02.0 start
<0> [574.306565] i915_sel-62786 538589667us : execlists_reset_prepare:
:00:02.0 rcs0: depth<-0
<0> [574.306565] i915_sel-62786 538589710us : intel_engine_stop_cs:
:00:02.0 rcs0:
<0> [574.306565] i915_sel-62786 538589732us : execlis
[Intel-gfx] [PATCH 16/20] drm/i915/selftests: Add request throughput measurement to perf
Under ideal circumstances, the driver should be able to keep the GPU
fully saturated with work. Measure how close to ideal we get under the
harshest of conditions with no user payload.
Signed-off-by: Chris Wilson
---
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_request.c | 280 +-
2 files changed, 280 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 3bf7f53e9924..d8da142985eb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -16,5 +16,6 @@
* Tests are executed in order by igt/i915_selftest
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
+selftest(request, i915_request_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index f89d9c42f1fa..91f67995f0ac 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
@@ -1233,7 +1234,7 @@ static int live_parallel_engines(void *arg)
struct igt_live_test t;
unsigned int idx;
- snprintf(name, sizeof(name), "%pS", fn);
+ snprintf(name, sizeof(name), "%ps", *fn);
err = igt_live_test_begin(&t, i915, __func__, name);
if (err)
break;
@@ -1470,3 +1471,280 @@ int i915_request_live_selftests(struct drm_i915_private
*i915)
return i915_subtests(tests, i915);
}
+
+struct perf_parallel {
+ struct intel_engine_cs *engine;
+ unsigned long count;
+ ktime_t time;
+ ktime_t busy;
+ u64 runtime;
+};
+
+static int switch_to_kernel_sync(struct intel_context *ce, int err)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0 && !err)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ while (!err && !intel_engine_is_idle(ce->engine))
+ intel_engine_flush_submission(ce->engine);
+
+ return err;
+}
+
+static int perf_sync(void *arg)
+{
+ struct perf_parallel *p = arg;
+ struct intel_engine_cs *engine = p->engine;
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
+ unsigned long count;
+ bool busy;
+ int err = 0;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ busy = false;
+ if (intel_engine_supports_stats(engine) &&
+ !intel_enable_engine_stats(engine)) {
+ p->busy = intel_engine_get_busy_time(engine);
+ busy = true;
+ }
+
+ p->time = ktime_get();
+ count = 0;
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ err = 0;
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ count++;
+ } while (!__igt_timeout(end_time, NULL));
+ p->time = ktime_sub(ktime_get(), p->time);
+
+ if (busy) {
+ p->busy = ktime_sub(intel_engine_get_busy_time(engine),
+ p->busy);
+ intel_disable_engine_stats(engine);
+ }
+
+ err = switch_to_kernel_sync(ce, err);
+ p->runtime = intel_context_get_total_runtime_ns(ce);
+ p->count = count;
+
+ intel_context_unpin(ce);
+ intel_context_put(ce);
+ return err;
+}
+
+static int perf_many(void *arg)
+{
+ struct perf_parallel *p = arg;
+ struct intel_engine_cs *engine = p->engine;
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
+ unsigned long count;
+ int err = 0;
+ bool busy;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+
[Intel-gfx] [PATCH 15/20] drm/i915/selftests: Be a little more lenient for reset workers
Give the reset worker a kick before losing help when waiting for hang
recovery, as the CPU scheduler is a little unreliable.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 74 ++
1 file changed, 52 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 95da6b880e3f..af5b3da6d894 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -90,6 +90,48 @@ static int wait_for_submit(struct intel_engine_cs *engine,
return -ETIME;
}
+static int wait_for_reset(struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ unsigned long timeout)
+{
+ timeout += jiffies;
+ do {
+ cond_resched();
+ intel_engine_flush_submission(engine);
+
+ if (READ_ONCE(engine->execlists.pending[0]))
+ continue;
+
+ if (i915_request_completed(rq))
+ break;
+
+ if (READ_ONCE(rq->fence.error))
+ break;
+ } while (time_before(jiffies, timeout));
+
+ flush_scheduled_work();
+
+ if (rq->fence.error != -EIO) {
+ pr_err("%s: hanging request %llx:%lld not reset\n",
+ engine->name,
+ rq->fence.context,
+ rq->fence.seqno);
+ return -EINVAL;
+ }
+
+ /* Give the request a jiffie to complete after flushing the worker */
+ if (i915_request_wait(rq, 0,
+ max(0l, (long)(timeout - jiffies)) + 1) < 0) {
+ pr_err("%s: hanging request %llx:%lld did not complete\n",
+ engine->name,
+ rq->fence.context,
+ rq->fence.seqno);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
static int live_sanitycheck(void *arg)
{
struct intel_gt *gt = arg;
@@ -1805,14 +1847,9 @@ static int __cancel_active0(struct live_preempt_cancel
*arg)
if (err)
goto out;
- if (i915_request_wait(rq, 0, HZ / 5) < 0) {
- err = -EIO;
- goto out;
- }
-
- if (rq->fence.error != -EIO) {
- pr_err("Cancelled inflight0 request did not report -EIO\n");
- err = -EINVAL;
+ err = wait_for_reset(arg->engine, rq, HZ / 2);
+ if (err) {
+ pr_err("Cancelled inflight0 request did not reset\n");
goto out;
}
@@ -1870,10 +1907,9 @@ static int __cancel_active1(struct live_preempt_cancel
*arg)
goto out;
igt_spinner_end(&arg->a.spin);
- if (i915_request_wait(rq[1], 0, HZ / 5) < 0) {
- err = -EIO;
+ err = wait_for_reset(arg->engine, rq[1], HZ / 2);
+ if (err)
goto out;
- }
if (rq[0]->fence.error != 0) {
pr_err("Normal inflight0 request did not complete\n");
@@ -1953,10 +1989,9 @@ static int __cancel_queued(struct live_preempt_cancel
*arg)
if (err)
goto out;
- if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
- err = -EIO;
+ err = wait_for_reset(arg->engine, rq[2], HZ / 2);
+ if (err)
goto out;
- }
if (rq[0]->fence.error != -EIO) {
pr_err("Cancelled inflight0 request did not report -EIO\n");
@@ -2014,14 +2049,9 @@ static int __cancel_hostile(struct live_preempt_cancel
*arg)
if (err)
goto out;
- if (i915_request_wait(rq, 0, HZ / 5) < 0) {
- err = -EIO;
- goto out;
- }
-
- if (rq->fence.error != -EIO) {
- pr_err("Cancelled inflight0 request did not report -EIO\n");
- err = -EINVAL;
+ err = wait_for_reset(arg->engine, rq, HZ / 2);
+ if (err) {
+ pr_err("Cancelled inflight0 request did not reset\n");
goto out;
}
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/20] drm/i915/gt: Prevent allocation on a banned context
If a context is banned even before we submit our first request to it,
report the failure before we attempt to allocate any resources for the
context.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 8bb444cda14f..01474d3a558b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -51,6 +51,11 @@ int intel_context_alloc_state(struct intel_context *ce)
return -EINTR;
if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ if (intel_context_is_banned(ce)) {
+ err = -EIO;
+ goto unlock;
+ }
+
err = ce->ops->alloc(ce);
if (unlikely(err))
goto unlock;
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/20] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Kenneth Graunke
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 40 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 119c9cb24fd4..eec6e3245a97 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1288,6 +1288,12 @@ static void intel_engine_print_registers(struct
intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index b23366a81048..24cff658e6e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+* @yield: CCID at the time of the last semaphore-wait interrupt.
+*
+* Instead of leaving a semaphore busy-spinning on an engine, we would
+* like to switch to another ready context, i.e. yielding the semaphore
+* timeslice.
+*/
+ u32 yield;
+
/**
* @error_interrupt: CS Master EIR
*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ if (del_timer(&engine->execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/inte
[Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation
Record the LRC registers before/after a preemption event to ensure that
the first context sees nothing from the second client; at least in the
normal per-context register state.
References: https://gitlab.freedesktop.org/drm/intel/issues/1233
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 545 +
1 file changed, 545 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index febd608c23a7..810f7857ad26 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4748,6 +4748,550 @@ static int live_lrc_timestamp(void *arg)
return 0;
}
+static struct i915_vma *
+create_user_vma(struct i915_address_space *vm, unsigned long size)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(vm->i915, size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static struct i915_vma *
+store_context(struct intel_context *ce, struct i915_vma *scratch)
+{
+ struct i915_vma *batch;
+ u32 dw, x, *cs, *hw;
+
+ batch = create_user_vma(ce->vm, SZ_64K);
+ if (IS_ERR(batch))
+ return ERR_CAST(batch);
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ i915_vma_put(batch);
+ return ERR_CAST(cs);
+ }
+
+ x = 0;
+ dw = 0;
+ hw = ce->engine->pinned_default_state;
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+ do {
+ u32 lri = hw[dw];
+
+ if (lri == 0) {
+ dw++;
+ continue;
+ }
+
+ if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ lri &= 0x7f;
+ dw += lri + 2;
+ continue;
+ }
+
+ lri &= 0x7f;
+ lri++;
+ dw++;
+
+ while (lri) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = hw[dw];
+ *cs++ = lower_32_bits(scratch->node.start + x);
+ *cs++ = upper_32_bits(scratch->node.start + x);
+
+ dw += 2;
+ lri -= 2;
+ x += 4;
+ }
+ } while (dw < PAGE_SIZE / sizeof(u32) &&
+(hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ return batch;
+}
+
+static int move_to_active(struct i915_request *rq,
+ struct i915_vma *vma,
+ unsigned int flags)
+{
+ int err;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, flags);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, flags);
+ i915_vma_unlock(vma);
+
+ return err;
+}
+
+static struct i915_request *
+record_registers(struct intel_context *ce,
+struct i915_vma *before,
+struct i915_vma *after,
+u32 *sema)
+{
+ struct i915_vma *b_before, *b_after;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+
+ b_before = store_context(ce, before);
+ if (IS_ERR(b_before))
+ return ERR_CAST(b_before);
+
+ b_after = store_context(ce, after);
+ if (IS_ERR(b_after)) {
+ rq = ERR_CAST(b_after);
+ goto err_before;
+ }
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ goto err_after;
+
+ err = move_to_active(rq, before, EXEC_OBJECT_WRITE);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, b_before, 0);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, after, EXEC_OBJECT_WRITE);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, b_after, 0);
+ if (err)
+ goto err_rq;
+
+ cs = intel_ring_begin(rq, 14);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+ *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
+ *cs++ = lower_32_bits(b_before->node.start);
+ *cs++ = upper_32_bits(b_before->node.start);
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOB
[Intel-gfx] [PATCH 07/20] drm/i915/gem: Check that the context wasn't closed during setup
As setup takes a long time, the user may close the context during the
construction of the execbuf. In order to make sure we correctly track
all outstanding work with non-persistent contexts, we need to serialise
the submission with the context closure and mop up any leaks.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ac0e5fc5675e..d9392a8978f8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2735,6 +2735,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_batch_unpin;
}
+ /* Check that the context wasn't destroyed before setup */
+ if (!rcu_access_pointer(eb.context->gem_context)) {
+ err = -ENOENT;
+ goto err_request;
+ }
+
if (in_fence) {
err = i915_request_await_dma_fence(eb.request, in_fence);
if (err < 0)
--
2.25.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/20] drm/i915/perf: Mark up the racy use of perf->exclusive_stream
Inside the general i915_oa_init_reg_state() we avoid using the
perf->mutex. However, we rely on perf->exclusive_stream being valid to
access at that point, and for that we have to control the race with
disabling perf. This relies on the disabling being a heavy barrier that
inspects all active contexts, after marking the perf->exclusive_stream
as not available. This should ensure that there are no more concurrent
accesses to the perf->exclusive_stream as we destroy it.
Mark up the races around the perf->exclusive_stream so that they stand
out much more. (And hopefully we will be running kcsan to start
validating that the only races we have are carefully controlled.)
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e34c79df6ebc..0838a12e2dc5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1405,8 +1405,10 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
/*
* Unset exclusive_stream first, it will be checked while disabling
* the metric set on gen8+.
+*
+* See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
- perf->exclusive_stream = NULL;
+ WRITE_ONCE(perf->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -2847,7 +2849,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
goto err_oa_buf_alloc;
stream->ops = &i915_oa_stream_ops;
- perf->exclusive_stream = stream;
+ WRITE_ONCE(perf->exclusive_stream, stream);
ret = perf->ops.enable_metric_set(stream);
if (ret) {
@@ -2867,7 +2869,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
return 0;
err_enable:
- perf->exclusive_stream = NULL;
+ WRITE_ONCE(perf->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -2893,12 +2895,11 @@ void i915_oa_init_reg_state(const struct intel_context
*ce,
{
struct i915_perf_stream *stream;
- /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
-
if (engine->class != RENDER_CLASS)
return;
- stream = engine->i915->perf.exclusive_stream;
+ /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
+ stream = READ_ONCE(engine->i915->perf.exclusive_stream);
/*
* For gen12, only CTX_R_PWR_CLK_STATE needs update, but the caller
* is already doing that, so nothing to be done for gen12 here.
--
2.25.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits
Attaching to the i915_active barrier is a two stage process, and a flush
is only effective when the barrier is activation. Thus it is possible
for us to see a barrier, and attempt to flush, only for our flush to
have no effect. As such, before attempting to activate signaling on the
fence we need to double check it is a fence!
Fixes: d13a31770077 ("drm/i915: Flush idle barriers when waiting")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_active.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index 0b12d5023800..7b3d6c12ad61 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -453,6 +453,9 @@ static void enable_signaling(struct i915_active_fence
*active)
{
struct dma_fence *fence;
+ if (unlikely(is_barrier(active)))
+ return;
+
fence = i915_active_fence_get(active);
if (!fence)
return;
--
2.25.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/20] drm/i915/selftests: Disable heartbeat around manual pulse tests
Still chasing the mystery of the stray idle flush, let's ensure that the
heartbeat does not run at the same time as our test and confuse us.
References: https://gitlab.freedesktop.org/drm/intel/issues/541
Signed-off-by: Chris Wilson
---
.../drm/i915/gt/selftest_engine_heartbeat.c | 30 ---
drivers/gpu/drm/i915/selftests/i915_active.c | 3 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
index 43d4d589749f..697114dd1f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -142,6 +142,24 @@ static int __live_idle_pulse(struct intel_engine_cs
*engine,
return err;
}
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+unsigned long *saved)
+{
+ *saved = engine->props.heartbeat_interval_ms;
+ engine->props.heartbeat_interval_ms = 0;
+
+ intel_engine_pm_get(engine);
+ intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+ unsigned long saved)
+{
+ intel_engine_pm_put(engine);
+
+ engine->props.heartbeat_interval_ms = saved;
+}
+
static int live_idle_flush(void *arg)
{
struct intel_gt *gt = arg;
@@ -152,9 +170,11 @@ static int live_idle_flush(void *arg)
/* Check that we can flush the idle barriers */
for_each_engine(engine, gt, id) {
- intel_engine_pm_get(engine);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
err = __live_idle_pulse(engine, intel_engine_flush_barriers);
- intel_engine_pm_put(engine);
+ engine_heartbeat_enable(engine, heartbeat);
if (err)
break;
}
@@ -172,9 +192,11 @@ static int live_idle_pulse(void *arg)
/* Check that heartbeat pulses flush the idle barriers */
for_each_engine(engine, gt, id) {
- intel_engine_pm_get(engine);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
err = __live_idle_pulse(engine, intel_engine_pulse);
- intel_engine_pm_put(engine);
+ engine_heartbeat_enable(engine, heartbeat);
if (err && err != -ENODEV)
break;
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c
b/drivers/gpu/drm/i915/selftests/i915_active.c
index 067e30b8927f..3a37c67ab6c4 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -331,8 +331,7 @@ void i915_active_unlock_wait(struct i915_active *ref)
}
/* And wait for the retire callback */
- spin_lock_irq(&ref->tree_lock);
- spin_unlock_irq(&ref->tree_lock);
+ spin_unlock_wait(&ref->tree_lock);
/* ... which may have been on a thread instead */
flush_work(&ref->work);
--
2.25.1
___
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[Intel-gfx] [PATCH 14/20] drm/i915/selftests: Wait for the kernel context switch
As we require a context switch to ensure that the current context is
switched out and saved to memory, perform an explicit switch to the
kernel context and wait for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 37 +++---
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d7f98aada626..95da6b880e3f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4015,6 +4015,31 @@ static int emit_semaphore_signal(struct intel_context
*ce, void *slot)
return 0;
}
+static int context_sync(struct intel_context *ce)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+ int err = 0;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
static int live_lrc_layout(void *arg)
{
struct intel_gt *gt = arg;
@@ -4638,16 +4663,10 @@ static int __lrc_timestamp(const struct lrc_timestamp
*arg, bool preempt)
wmb();
}
- if (i915_request_wait(rq, 0, HZ / 2) < 0) {
- err = -ETIME;
- goto err;
- }
-
- /* and wait for switch to kernel */
- if (igt_flush_test(arg->engine->i915)) {
- err = -EIO;
+ /* and wait for switch to kernel (to save our context to memory) */
+ err = context_sync(arg->ce[0]);
+ if (err)
goto err;
- }
rmb();
--
2.25.1
___
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[Intel-gfx] [PATCH 19/20] drm/i915/execlists: Check the sentinel is alone in the ELSP
We only use sentinel requests for "preempt-to-idle" passes, so assert
that they are the only request in a new submission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 253e89fecd95..d907b5ebc1a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1448,6 +1448,7 @@ assert_pending_valid(const struct intel_engine_execlists
*execlists,
{
struct i915_request * const *port, *rq;
struct intel_context *ce = NULL;
+ bool sentinel = false;
trace_ports(execlists, msg, execlists->pending);
@@ -1481,6 +1482,26 @@ assert_pending_valid(const struct intel_engine_execlists
*execlists,
}
ce = rq->context;
+ /*
+* Sentinels are supposed to be lonely so they flush the
+* current exection off the HW. Check that they are the
+* only request in the pending submission.
+*/
+ if (sentinel) {
+ GEM_TRACE_ERR("context:%llx after sentinel in
pending[%zd]\n",
+ ce->timeline->fence_context,
+ port - execlists->pending);
+ return false;
+ }
+
+ sentinel = i915_request_has_sentinel(rq);
+ if (sentinel && port != execlists->pending) {
+ GEM_TRACE_ERR("sentinel context:%llx not in prime
position[%zd]\n",
+ ce->timeline->fence_context,
+ port - execlists->pending);
+ return false;
+ }
+
/* Hold tightly onto the lock to prevent concurrent retires! */
if (!spin_trylock_irqsave(&rq->lock, flags))
continue;
--
2.25.1
___
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[Intel-gfx] [PATCH 20/20] drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
To prevent the context from proceeding past the end of the request as we
unwind, we embed a semaphore into the footer of each request. (If the
context were to skip past the end of the request as we perform the
preemption, next time we reload the context it's RING_HEAD would be past
the RING_TAIL and instead of replaying the commands it would read the
read of the uninitialised ringbuffer.)
However, this requires us to keep the ring paused at the end of the
request until we have a change to process the preemption ack and remove
the semaphore. Our processing of acks is at the whim of ksoftirqd, and
so it is entirely possible that the GPU has to wait for the tasklet
before it can proceed with the next request.
It was suggested that we could also embed a MI_LOAD_REGISTER_MEM into
the footer to read the current RING_TAIL from the context, which would
allow us to not only avoid this round trip (and so release the context
as soon as we had submitted the preemption request to in ELSP), but also
skip using ELSP for lite-restores entirely. That has the nice benefit of
dramatically reducing contention and the frequency of interrupts when a
client submits two or more execbufs in rapid succession.
* This did not work out quite as well as anticipated due to us reloading
the new RING_TAIL from the context image moments before the HW acted
upon the ELSP. With the calamitous effect that we would submit a
preemption request with an identical RING_TAIL as the current RING_HEAD,
causing us to fail WaIdleLiteRestore and the HW stop working.
However, mmio access to RING_TAIL was defeatured in gen11 so we can only
employ this handy trick for gen8/gen9.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 23 +++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 93 +++-
2 files changed, 106 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 24cff658e6e5..ae8724915320 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -488,14 +488,15 @@ struct intel_engine_cs {
/* status_notifier: list of callbacks for context-switch changes */
struct atomic_notifier_head context_status_notifier;
-#define I915_ENGINE_USING_CMD_PARSER BIT(0)
-#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_PREEMPTION BIT(2)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
-#define I915_ENGINE_IS_VIRTUAL BIT(5)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
+#define I915_ENGINE_REQUIRES_CMD_PARSERBIT(0)
+#define I915_ENGINE_USING_CMD_PARSER BIT(1)
+#define I915_ENGINE_SUPPORTS_STATS BIT(2)
+#define I915_ENGINE_HAS_PREEMPTION BIT(3)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
+#define I915_ENGINE_HAS_TAIL_LRM BIT(5)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
+#define I915_ENGINE_IS_VIRTUAL BIT(7)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
unsigned int flags;
/*
@@ -592,6 +593,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
+static inline bool
+intel_engine_has_tail_lrm(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_HAS_TAIL_LRM;
+}
+
static inline bool
intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d907b5ebc1a4..4452c3d0ac85 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1861,6 +1861,76 @@ static inline void clear_ports(struct i915_request
**ports, int count)
memset_p((void **)ports, NULL, count);
}
+static struct i915_request *
+skip_lite_restore(struct intel_engine_cs *const engine,
+ struct i915_request *first,
+ bool *submit)
+{
+ struct intel_engine_execlists *const execlists = &engine->execlists;
+ struct i915_request *last = first;
+ struct rb_node *rb;
+
+ if (!intel_engine_has_tail_lrm(engine))
+ return last;
+
+ GEM_BUG_ON(*submit);
+ while ((rb = rb_first_cached(&execlists->queue))) {
+ struct i915_priolist *p = to_priolist(rb);
+ struct i915_request *rq, *rn;
+ int i;
+
+ priolist_for_each_request_consume(rq, rn, p, i) {
+ if (!can_merge_rq(last, rq))
+ goto out;
+
+ if (__i915_request_submit(rq)) {
+ *submit = true;
+ last = rq;
+ }
+
[Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
Pull the final atomic_dec of vm->open (marking the vm as closed)
underneath the same vm->mutex as used to close it. This is required to
correctly serialise with attempting to reuse the vma as the vm is closed
by a second thread.
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed
before we insert it")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 5 -
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c
b/drivers/gpu/drm/i915/gt/intel_gtt.c
index bb9a6e638175..dfb1be050cca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -171,7 +171,9 @@ void __i915_vm_close(struct i915_address_space *vm)
{
struct i915_vma *vma, *vn;
- mutex_lock(&vm->mutex);
+ if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex))
+ return;
+
list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
struct drm_i915_gem_object *obj = vma->obj;
@@ -186,6 +188,7 @@ void __i915_vm_close(struct i915_address_space *vm)
i915_gem_object_put(obj);
}
GEM_BUG_ON(!list_empty(&vm->bound_list));
+
mutex_unlock(&vm->mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 23004445806a..eac38c682ef4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -429,8 +429,7 @@ static inline void
i915_vm_close(struct i915_address_space *vm)
{
GEM_BUG_ON(!atomic_read(&vm->open));
- if (atomic_dec_and_test(&vm->open))
- __i915_vm_close(vm);
+ __i915_vm_close(vm);
i915_vm_put(vm);
}
--
2.25.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits
URL : https://patchwork.freedesktop.org/series/73999/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7e51c69c481c drm/i915: Skip barriers inside waits
c38fa802dbde drm/i915/perf: Mark up the racy use of perf->exclusive_stream
99d09399016d drm/i915/perf: Manually acquire engine-wakeref around use of
kernel_context
620ed478d877 drm/i915/perf: Wait for lrc_reconfigure on disable
6ea5a0b4ac2e drm/i915/gem: Consolidate ctx->engines[] release
645f9d790e24 drm/i915/gt: Prevent allocation on a banned context
8139afa5553c drm/i915/gem: Check that the context wasn't closed during setup
ea172d1def13 drm/i915/selftests: Disable heartbeat around manual pulse tests
1e35652986b0 drm/i915/gt: Reset queue_priority_hint after wedging
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
<0> [574.303565] i915_sel-62782 481822445us : __i915_subtests: Running
intel_execlists_live_selftests/live_error_interrupt
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
eb47d53f2699 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed
before we insert it")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 00de702c6c6f ("drm/i915: Check
that the vma hasn't been closed before we insert it")'
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed
before we insert it")
total: 1 errors, 1 warnings, 0 checks, 26 lines checked
b4dae8ef2ab9 drm/i915: Protect i915_request_await_start from early waits
37b9d01ab40f drm/i915/selftests: Verify LRC isolation
-:449: WARNING:MEMORY_BARRIER: memory barrier without comment
#449: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:5179:
+ wmb();
total: 0 errors, 1 warnings, 0 checks, 557 lines checked
7c5ae8cee59f drm/i915/selftests: Check recovery from corrupted LRC
481fd56c20dc drm/i915/selftests: Wait for the kernel context switch
558c7595b054 drm/i915/selftests: Be a little more lenient for reset workers
e88a1a284017 drm/i915/selftests: Add request throughput measurement to perf
-:90: WARNING:LINE_SPACING: Missing a blank line after declarations
#90: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1515:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:157: WARNING:LINE_SPACING: Missing a blank line after declarations
#157: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1582:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:213: WARNING:LINE_SPACING: Missing a blank line after declarations
#213: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1638:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:221: WARNING:LINE_SPACING: Missing a blank line after declarations
#221: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1646:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:263: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc
(sched/core.c)
#263: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1688:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 5 warnings, 0 checks, 301 lines checked
6dded72da559 drm/i915/gt: Declare when we enabled timeslicing
462b6fb118f9 drm/i915/gt: Yield the timeslice if caught waiting on a user
semaphore
fff3931b5bef drm/i915/execlists: Check the sentinel is alone in the ELSP
109102637575 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
___
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Re: [Intel-gfx] [PATCH 5/5] drm/amdgpu: implement amdgpu_gem_prime_move_notify v2
Am 26.02.20 um 17:32 schrieb Daniel Vetter:
On Tue, Feb 25, 2020 at 6:16 PM Daniel Vetter wrote:
On Mon, Feb 24, 2020 at 07:46:59PM +0100, Christian König wrote:
Am 23.02.20 um 17:54 schrieb Thomas Hellström (VMware):
On 2/23/20 4:45 PM, Christian König wrote:
Am 21.02.20 um 18:12 schrieb Daniel Vetter:
[SNIP]
Yeah the Great Plan (tm) is to fully rely on ww_mutex slowly
degenerating
into essentially a global lock. But only when there's actual contention
and thrashing.
Yes exactly. A really big problem in TTM is currently that we drop
the lock after evicting BOs because they tend to move in again
directly after that.
From practice I can also confirm that there is exactly zero benefit
from dropping locks early and reacquire them for example for the VM
page tables. That's just makes it more likely that somebody needs to
roll back and this is what we need to avoid in the first place.
If you have a benchmarking setup available it would be very interesting
for future reference to see how changing from WD to WW mutexes affects
the roll back frequency. WW is known to cause rollbacks much less
frequently but there is more work associated with each rollback.
Not of hand. To be honest I still have a hard time to get a grip on the
difference between WD and WW from the algorithm point of view. So I can't
judge that difference at all.
Contention on BO locks during command submission is perfectly fine
as long as this is as lightweight as possible while we don't have
trashing. When we have trashing multi submission performance is best
archived to just favor a single process to finish its business and
block everybody else.
Hmm. Sounds like we need a per-manager ww_rwsem protecting manager
allocation, taken in write-mode then there's thrashing. In read-mode
otherwise. That would limit the amount of "unnecessary" locks we'd have
to keep and reduce unwanted side-effects, (see below):
Well per-manager (you mean per domain here don't you?) doesn't sound like
that useful because we rarely use only one domain, but I'm actually
questioning for quite a while if the per BO lock scheme was the right
approach.
See from the performance aspect the closest to ideal solution I can think of
would be a ww_rwsem per user of a resource.
In other words we don't lock BOs, but instead a list of all their users and
when you want to evict a BO you need to walk that list and inform all users
that the BO will be moving.
During command submission you then have the fast path which rather just
grabs the read side of the user lock and check if all BOs are still in the
expected place.
If some BOs were evicted you back off and start the slow path, e.g. maybe
even copy additional data from userspace then grab the write side of the
lock etc.. etc...
That approach is similar to what we use in amdgpu with the per-VM BOs, but
goes a step further. Problem is that we are so used to per BO locks in the
kernel that this is probably not doable any more.
Yeah I think it'd be nice to have the same approach for shared bo too. I
guess what we could do is something like this (spinning your ww_rwmutex
idea a bit further):
dma_buf_read_lock(buf, vm)
{
if (enabled(CONFIG_DEBUG_WW_MUTEX_SLOWPATH))
{
check that vm is indeed listed in buf and splat if not
}
/* for a buf that's not shared in multiple vm we'd have buf->resv
* == vm->resv here */
return ww_mutex_lock(vm->resv);
}
dma_buf_write_lock(buf)
{
for_each_vm_in_buf(buf, vm) {
ww_mutex_lock(vm->resv);
}
}
Ideally we'd track all these vms with something slightly less shoddy than
a linked list :-) Resizeable array is probably pretty good, I think we
only ever need to go from buf -> vm list, not the other way round. At
least in dma_resv/dma_buf code, driver code ofc needs to keep a list of
all bo bound to a vm somewhere. But that's probably a much bigger
datastructure for tracking vma offsets and mappings and other things on
top.
Ofc to even just get there we'd need something like the sublock list to
keep track of all the additional locks we'd need for the writer lock. And
we'd need the release callback for backoff, so that we could also go
through the slowpath on a vm object that we're not holding a full
reference on. That also means vm need to be refcounted.
And the list of vms on a buffer need to be protected with some lock and
the usual kref_get_unless_zero trickery.
But with all this I think we can make the dma_buf_write_lock lock 100%
like the old per-buffer lock for everyone. And execbuf could switch over
to dma_buf_read_lock for shared buffers. Bonus points when the gpu context
just keeps track of a list of shared vm used by buffers in that context
...
That way we could make vm fastpath locking a la amdgpu opt-in, while
keeping everyone else on the per-object locking juices.
Thoughts?
At least to me that sounds like a plan.
One thing I just realized, which is nasty: The full
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Add request throughput measurement to perf
== Series Details ==
Series: drm/i915/selftests: Add request throughput measurement to perf
URL : https://patchwork.freedesktop.org/series/73930/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8008_full -> Patchwork_16712_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_16712_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16712_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_16712_full:
### IGT changes ###
Possible regressions
* {igt@i915_selftest@perf_request} (NEW):
- shard-tglb: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-tglb5/igt@i915_selftest@perf_request.html
- shard-iclb: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb4/igt@i915_selftest@perf_request.html
* igt@runner@aborted:
- shard-tglb: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-tglb5/igt@run...@aborted.html
* igt@sw_sync@sync_multi_producer_single_consumer:
- shard-skl: [PASS][4] -> [TIMEOUT][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-skl8/igt@sw_sync@sync_multi_producer_single_consumer.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-skl10/igt@sw_sync@sync_multi_producer_single_consumer.html
- shard-snb: [PASS][6] -> [TIMEOUT][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-snb5/igt@sw_sync@sync_multi_producer_single_consumer.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-snb2/igt@sw_sync@sync_multi_producer_single_consumer.html
- shard-iclb: [PASS][8] -> [TIMEOUT][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb1/igt@sw_sync@sync_multi_producer_single_consumer.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb3/igt@sw_sync@sync_multi_producer_single_consumer.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_ctx_ringsize@active@vcs1}:
- shard-iclb: [PASS][10] -> [INCOMPLETE][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb2/igt@gem_ctx_ringsize@act...@vcs1.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb2/igt@gem_ctx_ringsize@act...@vcs1.html
New tests
-
New tests have been introduced between CI_DRM_8008_full and
Patchwork_16712_full:
### New IGT tests (1) ###
* igt@i915_selftest@perf_request:
- Statuses : 6 incomplete(s)
- Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_16712_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +2
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#1277])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-tglb2/igt@gem_exec_balan...@hang.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-tglb5/igt@gem_exec_balan...@hang.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109276] / [i915#677])
+1 similar issue
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb4/igt@gem_exec_sched...@implicit-read-write-bsd1.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb3/igt@gem_exec_sched...@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#112146]) +8 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb5/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@i915_pm_rps@reset:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#413])
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb1/igt@i915_pm_...@reset.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16712/shard-iclb6/igt@i915_pm_...@r
Re: [Intel-gfx] [PATCH 5/5] drm/amdgpu: implement amdgpu_gem_prime_move_notify v2
On Thu, Feb 27, 2020 at 10:20 AM Christian König
wrote:
> Am 26.02.20 um 17:32 schrieb Daniel Vetter:
> > On Tue, Feb 25, 2020 at 6:16 PM Daniel Vetter wrote:
> >> On Mon, Feb 24, 2020 at 07:46:59PM +0100, Christian König wrote:
> >>> Am 23.02.20 um 17:54 schrieb Thomas Hellström (VMware):
> On 2/23/20 4:45 PM, Christian König wrote:
> > Am 21.02.20 um 18:12 schrieb Daniel Vetter:
> >> [SNIP]
> >> Yeah the Great Plan (tm) is to fully rely on ww_mutex slowly
> >> degenerating
> >> into essentially a global lock. But only when there's actual contention
> >> and thrashing.
> > Yes exactly. A really big problem in TTM is currently that we drop
> > the lock after evicting BOs because they tend to move in again
> > directly after that.
> >
> > From practice I can also confirm that there is exactly zero benefit
> > from dropping locks early and reacquire them for example for the VM
> > page tables. That's just makes it more likely that somebody needs to
> > roll back and this is what we need to avoid in the first place.
> If you have a benchmarking setup available it would be very interesting
> for future reference to see how changing from WD to WW mutexes affects
> the roll back frequency. WW is known to cause rollbacks much less
> frequently but there is more work associated with each rollback.
> >>> Not of hand. To be honest I still have a hard time to get a grip on the
> >>> difference between WD and WW from the algorithm point of view. So I can't
> >>> judge that difference at all.
> >>>
> > Contention on BO locks during command submission is perfectly fine
> > as long as this is as lightweight as possible while we don't have
> > trashing. When we have trashing multi submission performance is best
> > archived to just favor a single process to finish its business and
> > block everybody else.
> Hmm. Sounds like we need a per-manager ww_rwsem protecting manager
> allocation, taken in write-mode then there's thrashing. In read-mode
> otherwise. That would limit the amount of "unnecessary" locks we'd have
> to keep and reduce unwanted side-effects, (see below):
> >>> Well per-manager (you mean per domain here don't you?) doesn't sound like
> >>> that useful because we rarely use only one domain, but I'm actually
> >>> questioning for quite a while if the per BO lock scheme was the right
> >>> approach.
> >>>
> >>> See from the performance aspect the closest to ideal solution I can think
> >>> of
> >>> would be a ww_rwsem per user of a resource.
> >>>
> >>> In other words we don't lock BOs, but instead a list of all their users
> >>> and
> >>> when you want to evict a BO you need to walk that list and inform all
> >>> users
> >>> that the BO will be moving.
> >>>
> >>> During command submission you then have the fast path which rather just
> >>> grabs the read side of the user lock and check if all BOs are still in the
> >>> expected place.
> >>>
> >>> If some BOs were evicted you back off and start the slow path, e.g. maybe
> >>> even copy additional data from userspace then grab the write side of the
> >>> lock etc.. etc...
> >>>
> >>> That approach is similar to what we use in amdgpu with the per-VM BOs, but
> >>> goes a step further. Problem is that we are so used to per BO locks in the
> >>> kernel that this is probably not doable any more.
> >> Yeah I think it'd be nice to have the same approach for shared bo too. I
> >> guess what we could do is something like this (spinning your ww_rwmutex
> >> idea a bit further):
> >>
> >> dma_buf_read_lock(buf, vm)
> >> {
> >> if (enabled(CONFIG_DEBUG_WW_MUTEX_SLOWPATH))
> >> {
> >> check that vm is indeed listed in buf and splat if not
> >> }
> >>
> >> /* for a buf that's not shared in multiple vm we'd have buf->resv
> >> * == vm->resv here */
> >> return ww_mutex_lock(vm->resv);
> >> }
> >>
> >> dma_buf_write_lock(buf)
> >> {
> >> for_each_vm_in_buf(buf, vm) {
> >> ww_mutex_lock(vm->resv);
> >> }
> >> }
> >>
> >> Ideally we'd track all these vms with something slightly less shoddy than
> >> a linked list :-) Resizeable array is probably pretty good, I think we
> >> only ever need to go from buf -> vm list, not the other way round. At
> >> least in dma_resv/dma_buf code, driver code ofc needs to keep a list of
> >> all bo bound to a vm somewhere. But that's probably a much bigger
> >> datastructure for tracking vma offsets and mappings and other things on
> >> top.
> >>
> >> Ofc to even just get there we'd need something like the sublock list to
> >> keep track of all the additional locks we'd need for the writer lock. And
> >> we'd need the release callback for backoff, so that we could also go
> >> through the slowpath on a vm object that we're not holding a full
> >> reference on. That also means vm need to be refcounted.
> >>
> >> An
Re: [Intel-gfx] [PULL] gvt-next
On 2020.02.26 13:58:32 +0200, Jani Nikula wrote: > On Wed, 26 Feb 2020, Zhenyu Wang wrote: > > Hi, > > > > Here's gvt-next pull. Mostly for cleanup and kvmgt specific struct > > has been moved to its own module, also enable VFIO edid for all platform > > including CML. Pls see details below. > > What happened with [1]? Would've liked to see that moving forward. > > > [1] > http://patchwork.freedesktop.org/patch/msgid/20200117153554.3104278-1-ch...@chris-wilson.co.uk > I just pinged Zhuocheng for who I asked to help on verifying that, but looks still have problem to bring up and there're more warnings.. We'll try to resolve it asap. Sorry for the delay. > > > > Thanks > > -- > > The following changes since commit e24bcd34c1dd7dabde4a8546920537f7137e3c5f: > > > > drm/i915/dp: Add all tiled and port sync conns to modeset (2020-02-20 > > 13:55:02 +0530) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux tags/gvt-next-2020-02-26 > > > > for you to fetch changes up to a8bb49b64c4f4284fb36169bdd9fc6efd62eb26a: > > > > drm/i915/gvt: Fix drm_WARN issue where vgpu ptr is unavailable > > (2020-02-25 16:13:04 +0800) > > > > > > gvt-next-2020-02-26 > > > > - Enable VFIO edid for all platform (Zhenyu) > > - Code cleanup for attr group and unused vblank complete (Zhenyu, Julian) > > - Make gvt oblivious of kvmgt data structures (Julian) > > - Make WARN* drm specific (Pankaj) > > > > > > Julian Stecklina (2): > > drm/i915/gvt: remove unused vblank_done completion > > drm/i915/gvt: make gvt oblivious of kvmgt data structures > > > > Pankaj Bharadiya (2): > > drm/i915/gvt: Make WARN* drm specific where drm_priv ptr is available > > drm/i915/gvt: Make WARN* drm specific where vgpu ptr is available > > > > Tina Zhang (1): > > drm/i915/gvt: Fix drm_WARN issue where vgpu ptr is unavailable > > > > Zhenyu Wang (3): > > drm/i915/gvt: remove unused type attributes > > drm/i915/gvt: Enable vfio edid for all GVT supported platform > > Merge drm-intel-next-queued into gvt-next > > > > drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 +- > > drivers/gpu/drm/i915/gvt/cfg_space.c| 23 ++- > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 +- > > drivers/gpu/drm/i915/gvt/display.c | 6 +- > > drivers/gpu/drm/i915/gvt/dmabuf.c | 4 +- > > drivers/gpu/drm/i915/gvt/edid.c | 19 +- > > drivers/gpu/drm/i915/gvt/gtt.c | 21 ++- > > drivers/gpu/drm/i915/gvt/gvt.c | 8 +- > > drivers/gpu/drm/i915/gvt/gvt.h | 37 +--- > > drivers/gpu/drm/i915/gvt/handlers.c | 22 ++- > > drivers/gpu/drm/i915/gvt/interrupt.c| 15 +- > > drivers/gpu/drm/i915/gvt/kvmgt.c| 303 > > +++- > > drivers/gpu/drm/i915/gvt/mmio.c | 30 ++-- > > drivers/gpu/drm/i915/gvt/mmio_context.c | 6 +- > > drivers/gpu/drm/i915/gvt/scheduler.c| 6 +- > > drivers/gpu/drm/i915/gvt/vgpu.c | 10 +- > > 16 files changed, 304 insertions(+), 216 deletions(-) > > -- > Jani Nikula, Intel Open Source Graphics Center -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/20] drm/i915: Skip barriers inside waits
== Series Details == Series: series starting with [01/20] drm/i915: Skip barriers inside waits URL : https://patchwork.freedesktop.org/series/73999/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8013 -> Patchwork_16729 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16729 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16729, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16729: ### IGT changes ### Possible regressions * igt@core_auth@basic-auth: - fi-kbl-r: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-r/igt@core_a...@basic-auth.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-r/igt@core_a...@basic-auth.html - fi-bwr-2160:[PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bwr-2160/igt@core_a...@basic-auth.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bwr-2160/igt@core_a...@basic-auth.html - fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bdw-5557u/igt@core_a...@basic-auth.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bdw-5557u/igt@core_a...@basic-auth.html - fi-skl-guc: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-guc/igt@core_a...@basic-auth.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-guc/igt@core_a...@basic-auth.html - fi-kbl-8809g: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-8809g/igt@core_a...@basic-auth.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-8809g/igt@core_a...@basic-auth.html - fi-kbl-guc: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-guc/igt@core_a...@basic-auth.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-guc/igt@core_a...@basic-auth.html - fi-icl-dsi: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-dsi/igt@core_a...@basic-auth.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-dsi/igt@core_a...@basic-auth.html - fi-kbl-7500u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-7500u/igt@core_a...@basic-auth.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-7500u/igt@core_a...@basic-auth.html - fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-6600u/igt@core_a...@basic-auth.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-6600u/igt@core_a...@basic-auth.html - fi-icl-u2: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-u2/igt@core_a...@basic-auth.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-u2/igt@core_a...@basic-auth.html - fi-hsw-4770:[PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-hsw-4770/igt@core_a...@basic-auth.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-hsw-4770/igt@core_a...@basic-auth.html - fi-cfl-8700k: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-8700k/igt@core_a...@basic-auth.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cfl-8700k/igt@core_a...@basic-auth.html - fi-snb-2520m: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-snb-2520m/igt@core_a...@basic-auth.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-snb-2520m/igt@core_a...@basic-auth.html - fi-skl-lmem:[PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-lmem/igt@core_a...@basic-auth.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-lmem/igt@core_a...@basic-auth.html - fi-skl-6700k2: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-6700k2/igt@core_a...@basic-auth.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-6700k2/igt@core_a...@basic-auth.html - f
[Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Put the pin_if_active check back!
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 193 +++-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
2 files changed, 102 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..8e2f8ab8ce6e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e,
unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,104 @@ static void kill_engines(struct i915_gem_engines
*engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err = 0
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: conversion to drm_device based logging macros (rev4)
== Series Details == Series: drm/i915/display: conversion to drm_device based logging macros (rev4) URL : https://patchwork.freedesktop.org/series/72760/ State : warning == Summary == $ dim checkpatch origin/drm-tip c1ef2220a44e drm/i915/dsb: convert to drm_device based logging macros. 86a7f80aaa81 drm/i915/fbc: convert to drm_device based logging macros. e85eca106b1e drm/i915/fbdev: convert to drm_device based logging. 52091797541d drm/i915/fifo_underrun: convert to drm_device based logging. b67c2a76b9a9 drm/i915/gmbus: convert to drm_device based logging, d6b8e1e05480 drm/i915/hdcp: convert to struct drm_device based logging. 79f92fa059cb drm/i915/hotplug: convert to drm_device based logging. 23085b0407ab drm/i915/lpe_audio: convert to drm_device based logging macros. -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html total: 0 errors, 1 warnings, 0 checks, 68 lines checked 7dfa3b5fa559 drm/i915/lvds: convert to drm_device based logging macros. 0b7851f0573c drm/i915/overlay: convert to drm_device based logging. -:91: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #91: References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html total: 0 errors, 1 warnings, 0 checks, 41 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/17] drm/i915/gt: Reset queue_priority_hint after wedging
== Series Details == Series: series starting with [01/17] drm/i915/gt: Reset queue_priority_hint after wedging URL : https://patchwork.freedesktop.org/series/73947/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8008_full -> Patchwork_16714_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16714_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16714_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16714_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@gem-mmap-type@gtt: - shard-hsw: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw5/igt@i915_pm_rpm@gem-mmap-t...@gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw5/igt@i915_pm_rpm@gem-mmap-t...@gtt.html * igt@i915_selftest@mock_requests: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-tglb7/igt@i915_selftest@mock_requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-tglb2/igt@i915_selftest@mock_requests.html - shard-iclb: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb1/igt@i915_selftest@mock_requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-iclb4/igt@i915_selftest@mock_requests.html * igt@runner@aborted: - shard-tglb: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-tglb2/igt@run...@aborted.html Warnings * igt@runner@aborted: - shard-hsw: ([FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15]) ([fdo#111870] / [i915#226]) -> ([FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24]) ([fdo#111870] / [i915#226] / [i915#873]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw4/igt@run...@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw6/igt@run...@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw4/igt@run...@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw6/igt@run...@aborted.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw4/igt@run...@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw7/igt@run...@aborted.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw7/igt@run...@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-hsw5/igt@run...@aborted.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw5/igt@run...@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw4/igt@run...@aborted.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw5/igt@run...@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw4/igt@run...@aborted.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw5/igt@run...@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw7/igt@run...@aborted.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw6/igt@run...@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw6/igt@run...@aborted.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-hsw7/igt@run...@aborted.html New tests - New tests have been introduced between CI_DRM_8008_full and Patchwork_16714_full: ### New IGT tests (1) ### * igt@i915_selftest@perf_request: - Statuses : - Exec time: [None] s Known issues Here are the changes found in Patchwork_16714_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@close-replace-race: - shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([i915#1291]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-iclb8/igt@gem_ctx_persiste...@close-replace-race.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16714/shard-iclb6/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_exec_balancer@hang: - shard-tglb: [PASS][27] -> [FAIL][28] ([i915#1277]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8008/shard-tglb2/igt@gem_exec_balan...@hang.html [28]:
Re: [Intel-gfx] [PATCH] drm/i915/ggtt: do not set bits 1-11 in gen12 ptes
Daniele Ceraolo Spurio writes:
> On TGL, bits 2-4 in the GGTT PTE are not ignored anymore and are
> instead used for some extra VT-d capabilities. We don't (yet?) have
> support for those capabilities, but, given that we shared the pte_encode
> function betweed GGTT and PPGTT, we still set those bits to the PPGTT
> PPAT values. The DMA engine gets very confused when those bits are
> set while the iommu is enabled, leading to errors. E.g. when loading
> the GuC we get:
>
> [9.796218] DMAR: DRHD: handling fault status reg 2
> [9.796235] DMAR: [DMA Write] Request device [00:02.0] PASID
> fault addr 0 [fault reason 02] Present bit in context entry is clear
> [9.899215] [drm:intel_guc_fw_upload [i915]] *ERROR* GuC firmware
> signature verification failed
>
> To fix this, just have dedicated gen8_pte_encode function per type of
> gtt. Also, explicitly set vm->pte_encode for gen8_ppgtt, even if we
> don't use it, to make sure we don't accidentally assign it to the GGTT
> one, like we do for gen6_ppgtt, in case we need it in the future.
Nice find. Tho I feel that the subject and commit message needs
a bit massaging for future archeologists.
We are changing the gen8+ ggtt encoding and not only gen12 and
it should be noted.
>
> Reported-by: "Sodhi, Vunny"
> Signed-off-by: Daniele Ceraolo Spurio
> Cc: Chris Wilson
> Cc: Mika Kuoppala
> Cc: Matthew Auld
> Cc: Michal Wajdeczko
> ---
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 26 ++
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 13 ++---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 24
> drivers/gpu/drm/i915/gt/intel_gtt.h | 4
> 4 files changed, 36 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 4d1de2d97d5c..9aabc5815d38 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -25,6 +25,30 @@ static u64 gen8_pde_encode(const dma_addr_t addr,
> return pde;
> }
>
> +static u64 gen8_pte_encode(dma_addr_t addr,
> +enum i915_cache_level level,
> +u32 flags)
> +{
> + gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
> +
> + if (unlikely(flags & PTE_READ_ONLY))
> + pte &= ~_PAGE_RW;
> +
> + switch (level) {
> + case I915_CACHE_NONE:
> + pte |= PPAT_UNCACHED;
> + break;
> + case I915_CACHE_WT:
> + pte |= PPAT_DISPLAY_ELLC;
> + break;
> + default:
> + pte |= PPAT_CACHED;
> + break;
> + }
> +
> + return pte;
> +}
> +
> static void gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
> {
> struct drm_i915_private *i915 = ppgtt->vm.i915;
> @@ -706,6 +730,8 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
> ppgtt->vm.clear_range = gen8_ppgtt_clear;
>
> + ppgtt->vm.pte_encode = gen8_pte_encode;
> +
> if (intel_vgpu_active(gt->i915))
> gen8_ppgtt_notify_vgt(ppgtt, true);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 41a00281f364..e45eca985b14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -157,6 +157,13 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> intel_gtt_chipset_flush();
> }
>
> +static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + return addr | _PAGE_PRESENT;
The bspec is bit ambivalent in here. First it says R/W is ignored but
further ahead it states that bit0 and bit1 defines the validity
and rest are ignored for aperture/display.
This said, I am leaning to give a minimal set a try first :)
> +}
> +
> static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> {
> writeq(pte, addr);
> @@ -172,7 +179,7 @@ static void gen8_ggtt_insert_page(struct
> i915_address_space *vm,
> gen8_pte_t __iomem *pte =
> (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
>
> - gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
> + gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
Make me ponder why we don't use the vm->pte_encode all the way
as we have it :P
Nevertheless, with s/gen12/gen8 ggtt encoding in subject/
commit msg and this is,
Reviewed-by: Mika Kuoppala
>
> ggtt->invalidate(ggtt);
> }
> @@ -185,7 +192,7 @@ static void gen8_ggtt_insert_entries(struct
> i915_address_space *vm,
> struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> struct sgt_iter sgt_iter;
> gen8_pte_t __iomem *gtt_entries;
> - const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
> + const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
> dma_addr_t a
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: conversion to drm_device based logging macros (rev4)
== Series Details ==
Series: drm/i915/display: conversion to drm_device based logging macros (rev4)
URL : https://patchwork.freedesktop.org/series/72760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8013 -> Patchwork_16730
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_16730 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16730, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16730:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][1] -> [TIMEOUT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_16730 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u: [PASS][3] -> [INCOMPLETE][4] ([i915#1242])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
* igt@gem_exec_suspend@basic-s4-devices:
- fi-tgl-y: [PASS][5] -> [FAIL][6] ([CI#94])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-tgl-y/igt@gem_exec_susp...@basic-s4-devices.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111407])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][9] ([i915#44]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@prime_self_import@basic-llseek-size:
- fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12]
+1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-tgl-y/igt@prime_self_imp...@basic-llseek-size.html
Warnings
* igt@i915_selftest@live_gt_lrc:
- fi-tgl-y: [INCOMPLETE][13] ([CI#94] / [i915#1233]) ->
[DMESG-FAIL][14] ([CI#94] / [i915#1233])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-y/igt@i915_selftest@live_gt_lrc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16730/fi-tgl-y/igt@i915_selftest@live_gt_lrc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
Participating hosts (51 -> 41)
--
Missing(10): fi-hsw-4770r fi-bdw-5557u fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-elk-e7500 fi-byt-clapper fi-bsw-nick fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8013 -> Patchwork_16730
CI-20190529: 20190529
CI_DRM_8013: ddbaa8ebcf171da63385dccb8a6b4d0209c2f6fb @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5471: 668afe52887a164ee6a12fd1c898bc1c9086cf3e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16730: 0b7851f0573c7eeb936a533f4be35d7fde434734 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0b7851f0573c drm/i915/overlay: convert to drm_device based logging.
7dfa3b5fa559 drm/i915/lvds: convert to drm_device based logging macros.
23085b0407a
Re: [Intel-gfx] [PATCH] drm/i915/ggtt: do not set bits 1-11 in gen12 ptes
Quoting Mika Kuoppala (2020-02-27 10:51:46)
> Daniele Ceraolo Spurio writes:
> > static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> > {
> > writeq(pte, addr);
> > @@ -172,7 +179,7 @@ static void gen8_ggtt_insert_page(struct
> > i915_address_space *vm,
> > gen8_pte_t __iomem *pte =
> > (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
> >
> > - gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
> > + gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
>
> Make me ponder why we don't use the vm->pte_encode all the way
> as we have it :P
Don't use vfuncs if the target routine is known.
Apparently it's even cheaper to do a bsearch on a page of target
routines than it is to use retpolines.
Anyway, the era of vfuncs is over.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Remember to initialise the mock_context as well.
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 193 +-
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
.../gpu/drm/i915/gem/selftests/mock_context.c | 3 +
3 files changed, 105 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..cb6b6be48978 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e,
unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct
i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,104 @@ static void kill_engines(struct i915_gem_engines
*engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it
[Intel-gfx] [PATCH] drm/i915/perf: Wait for lrc_reconfigure on disable
Wait for the last request (and so waits for all context updates) when
disabling OA. This prevents a rather bizarre error seen on Skylake
where the context is subsequently corrupted. Let's play safe and assume
it may impact all.
Reported-by: Lionel Landwerlin
Signed-off-by: Chris Wilson
Cc: Lionel Landwerlin
---
Drop the notion of timeout, waiting appears critical.
---
drivers/gpu/drm/i915/i915_perf.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2334c45f1d08..bb380b0c4501 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2191,7 +2191,8 @@ static int gen8_modify_context(struct intel_context *ce,
}
static int gen8_modify_self(struct intel_context *ce,
- const struct flex *flex, unsigned int count)
+ const struct flex *flex, unsigned int count,
+ bool sync)
{
struct i915_request *rq;
int err;
@@ -2204,7 +2205,12 @@ static int gen8_modify_self(struct intel_context *ce,
err = gen8_load_flex(rq, ce, flex, count);
+ i915_request_get(rq);
i915_request_add(rq);
+ if (sync && i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
return err;
}
@@ -2281,7 +2287,7 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream, bool ena
return err;
/* Apply regs_lri using LRI with pinned context */
- return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri));
+ return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), false);
}
/*
@@ -2311,7 +2317,8 @@ static int gen12_configure_oar_context(struct
i915_perf_stream *stream, bool ena
*/
static int oa_configure_all_contexts(struct i915_perf_stream *stream,
struct flex *regs,
-size_t num_regs)
+size_t num_regs,
+bool enable)
{
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
@@ -2368,7 +2375,7 @@ static int oa_configure_all_contexts(struct
i915_perf_stream *stream,
regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
- err = gen8_modify_self(ce, regs, num_regs);
+ err = gen8_modify_self(ce, regs, num_regs, !enable);
if (err)
return err;
}
@@ -2386,7 +2393,9 @@ static int gen12_configure_all_contexts(struct
i915_perf_stream *stream,
},
};
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+regs, ARRAY_SIZE(regs),
+oa_config);
}
static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
@@ -2423,7 +2432,9 @@ static int lrc_configure_all_contexts(struct
i915_perf_stream *stream,
for (i = 2; i < ARRAY_SIZE(regs); i++)
regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+regs, ARRAY_SIZE(regs),
+oa_config);
}
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
--
2.25.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Set up PIPE_MISC truncate bit on tgl+
== Series Details ==
Series: drm/i915: Set up PIPE_MISC truncate bit on tgl+
URL : https://patchwork.freedesktop.org/series/73960/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8010 -> Patchwork_16719
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16719/index.html
Known issues
Here are the changes found in Patchwork_16719 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-dpms:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#261])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/fi-icl-dsi/igt@kms_f...@basic-flip-vs-dpms.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16719/fi-icl-dsi/igt@kms_f...@basic-flip-vs-dpms.html
Possible fixes
* igt@i915_selftest@live_active:
- {fi-ehl-1}: [DMESG-FAIL][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/fi-ehl-1/igt@i915_selftest@live_active.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16719/fi-ehl-1/igt@i915_selftest@live_active.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#261]: https://gitlab.freedesktop.org/drm/intel/issues/261
Participating hosts (51 -> 42)
--
Missing(9): fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-tgl-y fi-bsw-cyan
fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8010 -> Patchwork_16719
CI-20190529: 20190529
CI_DRM_8010: 97bbec4d80df1c6573fc7063ad830e8beefe07c8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5471: 668afe52887a164ee6a12fd1c898bc1c9086cf3e @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16719: c992e861fa194162dd6ed4add0b11e5eab3b47e5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c992e861fa19 drm/i915: Set up PIPE_MISC truncate bit on tgl+
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16719/index.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v18 5/8] drm/i915: Refactor intel_can_enable_sagv
Currently intel_can_enable_sagv function contains a mix of workarounds for different platforms some of them are not valid for gens >= 11 already, so lets split it into separate functions. v2: - Rework watermark calculation algorithm to attempt to calculate Level 0 watermark with added sagv block time latency and check if it fits in DBuf in order to determine if SAGV can be enabled already at this stage, just as BSpec 49325 states. if that fails rollback to usual Level 0 latency and disable SAGV. - Remove unneeded tabs(James Ausmus) v3: Rebased the patch v4: - Added back interlaced check for Gen12 and added separate function for TGL SAGV check (thanks to James Ausmus for spotting) - Removed unneeded gen check - Extracted Gen12 SAGV decision making code to a separate function from skl_compute_wm v5: - Added SAGV global state to dev_priv, because we need to track all pipes, not only those in atomic state. Each pipe has now correspondent bit mask reflecting, whether it can tolerate SAGV or not(thanks to Ville Syrjala for suggestions). - Now using active flag instead of enable in crc usage check. v6: - Fixed rebase conflicts v7: - kms_cursor_legacy seems to get broken because of multiple memcpy calls when copying level 0 water marks for enabled SAGV, to fix this now simply using that field right away, without copying, for that introduced a new wm_level accessor which decides which wm_level to return based on SAGV state. v8: - Protect crtc_sagv_mask same way as we do for other global state changes: i.e check if changes are needed, then grab all crtc locks to serialize the changes(Ville Syrjälä) - Add crtc_sagv_mask caching in order to avoid needless recalculations (Matthew Roper) - Put back Gen12 SAGV switch in order to get it enabled in separate patch(Matthew Roper) - Rename *_set_sagv_mask to *_compute_sagv_mask(Matthew Roper) - Check if there are no active pipes in intel_can_enable_sagv instead of platform specific functions(Matthew Roper), same for intel_has_sagv check. v9 - Switched to u8 for crtc_sagv_mask(Ville Syrjälä) - crtc_sagv_mask now is pipe_sagv_mask(Ville Syrjälä) - Extracted sagv checking logic from skl/icl/tgl_compute_sagv_mask - Extracted skl_plane_wm_level function and passing latency to separate patches(Ville Syrjälä) - Removed part of unneeded copy-paste from tgl_check_pipe_fits_sagv_wm (Ville Syrjälä) - Now using simple assignment for sagv_wm0 as it contains only pod types and no pointers(Ville Syrjälä) - Fixed intel_can_enable_sagv not to do double duty, now it only check SAGV bits by ANDing those between local and global state. The SAGV masks are now computed after watermarks are available, in order to be able to figure out if ddb ranges are fitting nicely. (Ville Syrjälä) - Now having uv_sagv_wm0 and sagv_wm0, otherwise we have wrong logic when using skl_plane_wm_level accessor, as we had previously for Gen11+ color plane and regular wm levels, so probably both has to be recalculated with additional SAGV block time for Level 0. v10: - Starting to use new global state for storing pipe_sagv_mask v11: - Fixed rebase conflict with recent drm-tip - Check if we really need to recalculate SAGV mask, otherwise bail out without making any changes. - Use cached SAGV result, instead of recalculating it everytime, if bw_state hasn't changed. v12: - Removed WARN from intel_can_enable_sagv, in some of the commits if we don't recalculated watermarks, bw_state is not recalculated, thus leading to SAGV state not recalculated by the commit state, which is still calling intel_can_enable_sagv function. Fix that by just analyzing the current global bw_state object - because we simply have no other objects related to that. v13: - Rebased, fixed warnings regarding long lines - Changed function call sites from intel_atomic_bw* to intel_wb_* as was suggested.(Jani Nikula) - Taken ddb_state_changed and bw_state_changed into use. v14: - total_affected_planes is no longer needed to check for ddb changes, just as active_pipe_changes. v15: - Fixed stupid mistake with uninitialized crtc in skl_compute_sagv_mask. Signed-off-by: Stanislav Lisovskiy Cc: Ville Syrjälä Cc: James Ausmus --- drivers/gpu/drm/i915/display/intel_bw.h | 18 + drivers/gpu/drm/i915/display/intel_display.c | 27 +- .../drm/i915/display/intel_display_types.h| 2 + drivers/gpu/drm/i915/intel_pm.c | 427 -- drivers/gpu/drm/i915/intel_pm.h | 4 +- 5 files changed, 436 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index b5f61463922f..c
[Intel-gfx] [PATCH 16/21] drm/i915: make *_debugfs_register() functions return void.
Since 987d65d01356 (drm: debugfs: make
drm_debugfs_create_files() never fail), drm_debugfs_create_files() never
fails and should return void. Therefore, remove its use as the
return value of i915_debugfs_register() and
intel_display_debugfs_register() and have both functions return void.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8
drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 8
drivers/gpu/drm/i915/i915_debugfs.h | 4 ++--
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 46954cc7b6c0..3b877c34c420 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1922,7 +1922,7 @@ static const struct {
{"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
};
-int intel_display_debugfs_register(struct drm_i915_private *i915)
+void intel_display_debugfs_register(struct drm_i915_private *i915)
{
struct drm_minor *minor = i915->drm.primary;
int i;
@@ -1935,9 +1935,9 @@ int intel_display_debugfs_register(struct
drm_i915_private *i915)
intel_display_debugfs_files[i].fops);
}
- return drm_debugfs_create_files(intel_display_debugfs_list,
- ARRAY_SIZE(intel_display_debugfs_list),
- minor->debugfs_root, minor);
+ drm_debugfs_create_files(intel_display_debugfs_list,
+ARRAY_SIZE(intel_display_debugfs_list),
+minor->debugfs_root, minor);
}
static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
index a3bea1ce04c2..a5cf7a6d3d34 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
@@ -10,10 +10,10 @@ struct drm_connector;
struct drm_i915_private;
#ifdef CONFIG_DEBUG_FS
-int intel_display_debugfs_register(struct drm_i915_private *i915);
+void intel_display_debugfs_register(struct drm_i915_private *i915);
int intel_connector_debugfs_add(struct drm_connector *connector);
#else
-static inline int intel_display_debugfs_register(struct drm_i915_private
*i915) { return 0; }
+static inline int intel_display_debugfs_register(struct drm_i915_private
*i915) {}
static inline int intel_connector_debugfs_add(struct drm_connector *connector)
{ return 0; }
#endif
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8f2525e4ce0f..de313199c714 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2392,7 +2392,7 @@ static const struct i915_debugfs_files {
{"i915_guc_log_relay", &i915_guc_log_relay_fops},
};
-int i915_debugfs_register(struct drm_i915_private *dev_priv)
+void i915_debugfs_register(struct drm_i915_private *dev_priv)
{
struct drm_minor *minor = dev_priv->drm.primary;
int i;
@@ -2409,7 +2409,7 @@ int i915_debugfs_register(struct drm_i915_private
*dev_priv)
i915_debugfs_files[i].fops);
}
- return drm_debugfs_create_files(i915_debugfs_list,
- I915_DEBUGFS_ENTRIES,
- minor->debugfs_root, minor);
+ drm_debugfs_create_files(i915_debugfs_list,
+I915_DEBUGFS_ENTRIES,
+minor->debugfs_root, minor);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.h
b/drivers/gpu/drm/i915/i915_debugfs.h
index 6da39c76ab5e..1de2736f1248 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.h
+++ b/drivers/gpu/drm/i915/i915_debugfs.h
@@ -12,10 +12,10 @@ struct drm_i915_private;
struct seq_file;
#ifdef CONFIG_DEBUG_FS
-int i915_debugfs_register(struct drm_i915_private *dev_priv);
+void i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object
*obj);
#else
-static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {
return 0; }
+static inline void i915_debugfs_register(struct drm_i915_private *dev_priv) {}
static inline void i915_debugfs_describe_obj(struct seq_file *m, struct
drm_i915_gem_object *obj) {}
#endif
--
2.25.0
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: reintroduce wait on OA configuration completion
We still need to wait for the initial OA configuration to happen
before we enable OA report writes to the OA buffer.
Signed-off-by: Lionel Landwerlin
Fixes: 15d0ace1f876 ("drm/i915/perf: execute OA configuration from command
stream")
---
drivers/gpu/drm/i915/i915_perf.c | 49 +++---
drivers/gpu/drm/i915/i915_perf_types.h | 8 +
2 files changed, 52 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f4e1dd525fa2..3883c21b13b2 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1378,6 +1378,23 @@ free_noa_wait(struct i915_perf_stream *stream)
i915_vma_unpin_and_release(&stream->noa_wait, 0);
}
+static int
+wait_and_put_configure_request(struct i915_perf_stream *stream)
+{
+ struct i915_request *rq = stream->configure_request;
+ int ret = 0;
+
+ stream->configure_request = NULL;
+ GEM_BUG_ON(rq == NULL);
+
+ if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ ret = -ETIME;
+
+ i915_request_put(rq);
+
+ return ret;
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
@@ -1390,6 +1407,7 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
*/
perf->exclusive_stream = NULL;
perf->ops.disable_metric_set(stream);
+ GEM_BUG_ON(stream->configure_request != NULL);
free_oa_buffer(stream);
@@ -1954,7 +1972,8 @@ get_oa_vma(struct i915_perf_stream *stream, struct
i915_oa_config *oa_config)
static int emit_oa_config(struct i915_perf_stream *stream,
struct i915_oa_config *oa_config,
- struct intel_context *ce)
+ struct intel_context *ce,
+ bool store_on_stream)
{
struct i915_request *rq;
struct i915_vma *vma;
@@ -1987,6 +2006,12 @@ static int emit_oa_config(struct i915_perf_stream
*stream,
err = rq->engine->emit_bb_start(rq,
vma->node.start, 0,
I915_DISPATCH_SECURE);
+
+ if (err == 0 && store_on_stream) {
+ GEM_BUG_ON(stream->configure_request != NULL);
+ stream->configure_request = i915_request_get(rq);
+ }
+
err_add_request:
i915_request_add(rq);
err_vma_unpin:
@@ -2020,7 +2045,9 @@ static int hsw_enable_metric_set(struct i915_perf_stream
*stream)
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
- return emit_oa_config(stream, stream->oa_config, oa_context(stream));
+ return emit_oa_config(stream, stream->oa_config,
+ oa_context(stream),
+ true /* store_on_stream */);
}
static void hsw_disable_metric_set(struct i915_perf_stream *stream)
@@ -2448,7 +2475,9 @@ static int gen8_enable_metric_set(struct i915_perf_stream
*stream)
if (ret)
return ret;
- return emit_oa_config(stream, oa_config, oa_context(stream));
+ return emit_oa_config(stream, oa_config,
+ oa_context(stream),
+ true /* store_on_stream */);
}
static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
@@ -2502,7 +2531,9 @@ static int gen12_enable_metric_set(struct
i915_perf_stream *stream)
return ret;
}
- return emit_oa_config(stream, oa_config, oa_context(stream));
+ return emit_oa_config(stream, oa_config,
+ oa_context(stream),
+ true /* store_on_stream */);
}
static void gen8_disable_metric_set(struct i915_perf_stream *stream)
@@ -2837,6 +2868,12 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
goto err_enable;
}
+ ret = wait_and_put_configure_request(stream);
+ if (ret) {
+ DRM_DEBUG("Wait on OA config request timed out\n");
+ goto err_enable;
+ }
+
DRM_DEBUG("opening stream oa config uuid=%s\n",
stream->oa_config->uuid);
@@ -2851,6 +2888,7 @@ static int i915_oa_stream_init(struct i915_perf_stream
*stream,
err_enable:
perf->exclusive_stream = NULL;
perf->ops.disable_metric_set(stream);
+ GEM_BUG_ON(stream->configure_request != NULL);
free_oa_buffer(stream);
@@ -3160,7 +3198,8 @@ static long i915_perf_config_locked(struct
i915_perf_stream *stream,
* When set globally, we use a low priority kernel context,
* so it will effectively take effect when idle.
*/
- err = emit_oa_config(stream, config, oa_context(stream));
+ err = emit_oa_config(stream, config, oa_context(stream),
+
Re: [Intel-gfx] [PATCH 16/21] drm/i915: make *_debugfs_register() functions return void.
On Thu, 27 Feb 2020, Wambui Karuga wrote:
> Since 987d65d01356 (drm: debugfs: make
> drm_debugfs_create_files() never fail), drm_debugfs_create_files() never
> fails and should return void. Therefore, remove its use as the
> return value of i915_debugfs_register() and
> intel_display_debugfs_register() and have both functions return void.
>
> Signed-off-by: Wambui Karuga
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 8
> drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 8
> drivers/gpu/drm/i915/i915_debugfs.h | 4 ++--
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 46954cc7b6c0..3b877c34c420 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1922,7 +1922,7 @@ static const struct {
> {"i915_edp_psr_debug", &i915_edp_psr_debug_fops},
> };
>
> -int intel_display_debugfs_register(struct drm_i915_private *i915)
> +void intel_display_debugfs_register(struct drm_i915_private *i915)
> {
> struct drm_minor *minor = i915->drm.primary;
> int i;
> @@ -1935,9 +1935,9 @@ int intel_display_debugfs_register(struct
> drm_i915_private *i915)
> intel_display_debugfs_files[i].fops);
> }
>
> - return drm_debugfs_create_files(intel_display_debugfs_list,
> - ARRAY_SIZE(intel_display_debugfs_list),
> - minor->debugfs_root, minor);
> + drm_debugfs_create_files(intel_display_debugfs_list,
> + ARRAY_SIZE(intel_display_debugfs_list),
> + minor->debugfs_root, minor);
> }
>
> static int i915_panel_show(struct seq_file *m, void *data)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> index a3bea1ce04c2..a5cf7a6d3d34 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> @@ -10,10 +10,10 @@ struct drm_connector;
> struct drm_i915_private;
>
> #ifdef CONFIG_DEBUG_FS
> -int intel_display_debugfs_register(struct drm_i915_private *i915);
> +void intel_display_debugfs_register(struct drm_i915_private *i915);
> int intel_connector_debugfs_add(struct drm_connector *connector);
> #else
> -static inline int intel_display_debugfs_register(struct drm_i915_private
> *i915) { return 0; }
> +static inline int intel_display_debugfs_register(struct drm_i915_private
> *i915) {}
You don't actually change the return type.
Otherwise, LGTM.
BR,
Jani.
> static inline int intel_connector_debugfs_add(struct drm_connector
> *connector) { return 0; }
> #endif
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8f2525e4ce0f..de313199c714 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2392,7 +2392,7 @@ static const struct i915_debugfs_files {
> {"i915_guc_log_relay", &i915_guc_log_relay_fops},
> };
>
> -int i915_debugfs_register(struct drm_i915_private *dev_priv)
> +void i915_debugfs_register(struct drm_i915_private *dev_priv)
> {
> struct drm_minor *minor = dev_priv->drm.primary;
> int i;
> @@ -2409,7 +2409,7 @@ int i915_debugfs_register(struct drm_i915_private
> *dev_priv)
> i915_debugfs_files[i].fops);
> }
>
> - return drm_debugfs_create_files(i915_debugfs_list,
> - I915_DEBUGFS_ENTRIES,
> - minor->debugfs_root, minor);
> + drm_debugfs_create_files(i915_debugfs_list,
> + I915_DEBUGFS_ENTRIES,
> + minor->debugfs_root, minor);
> }
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.h
> b/drivers/gpu/drm/i915/i915_debugfs.h
> index 6da39c76ab5e..1de2736f1248 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.h
> +++ b/drivers/gpu/drm/i915/i915_debugfs.h
> @@ -12,10 +12,10 @@ struct drm_i915_private;
> struct seq_file;
>
> #ifdef CONFIG_DEBUG_FS
> -int i915_debugfs_register(struct drm_i915_private *dev_priv);
> +void i915_debugfs_register(struct drm_i915_private *dev_priv);
> void i915_debugfs_describe_obj(struct seq_file *m, struct
> drm_i915_gem_object *obj);
> #else
> -static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {
> return 0; }
> +static inline void i915_debugfs_register(struct drm_i915_private *dev_priv)
> {}
> static inline void i915_debugfs_describe_obj(struct seq_file *m, struct
> drm_i915_gem_object *obj) {}
> #endif
--
Jani Nikula, Intel Open Source Graphics Center
__
Re: [Intel-gfx] [PATCH v4-CI] drm/i915/psr: Force PSR probe only after full initialization
On Fri, 21 Feb 2020, José Roberto de Souza wrote:
> Commit 60c6a14b489b ("drm/i915/display: Force the state compute phase
> once to enable PSR") was forcing the state compute too earlier
> causing errors because not everything was initialized, so here
> moving to the end of i915_driver_modeset_probe() when the display is
> all initialized.
Hmph, really not happy about the placement here. These are high level
functions, not a dumping ground for random feature specific hacks. :(
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5] drm/i915: Use intel_plane_data_rate for min_cdclk calculation
There seems to be a bit of confusing redundancy in a way, how
plane data rate/min cdclk are calculated.
In fact both min cdclk, pixel rate and plane data rate are all
part of the same formula as per BSpec.
However currently we have intel_plane_data_rate, which is used
to calculate plane data rate and which is also used in bandwidth
calculations. However for calculating min_cdclk we have another
piece of code, doing almost same calculation, but a bit differently
and in a different place. However as both are actually part of same
formula, probably would be wise to use plane data rate calculations
as a basis anyway, thus avoiding code duplication and possible bugs
related to this.
Another thing is that I've noticed that during min_cdclk calculations
we account for plane scaling, while for plane data rate, we don't.
crtc->pixel_rate seems to account only for pipe ratio, however it is
clearly stated in BSpec that plane data rate also need to account
plane ratio as well.
So what this commit does is:
- Adds a plane ratio calculation to intel_plane_data_rate
- Removes redundant calculations from skl_plane_min_cdclk which is
used for gen9+ and now uses intel_plane_data_rate as a basis from
there as well.
v2: - Don't use 64 division if not needed(Ville Syrjälä)
- Now use intel_plane_pixel_rate as a basis for calculations both
at intel_plane_data_rate and skl_plane_min_cdclk(Ville Syrjälä)
v3: - Again fix the division macro
- Fix plane_pixel_rate to pixel_rate at intel_plane_pixel_rate
callsites
v4: - Renamed skl_plane_ratio function back(Ville Syrjälä)
v5: - Don't precalculate plane pixel rate for invisible plane,
check for visibility first, as in invisible case it will
have dst_w and dst_h equal to zero, causing divide error.
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 26 ++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 15 ++-
3 files changed, 30 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c86d7a35c816..956af022cf5b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -133,15 +133,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
}
+unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ unsigned int src_w, src_h, dst_w, dst_h;
+
+ src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+ dst_w = drm_rect_width(&plane_state->uapi.dst);
+ dst_h = drm_rect_height(&plane_state->uapi.dst);
+
+ /* Downscaling limits the maximum pixel rate */
+ dst_w = min(src_w, dst_w);
+ dst_h = min(src_h, dst_h);
+
+ WARN_ON(!dst_w || !dst_h);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate,
+ src_w * src_h),
+ dst_w * dst_h);
+}
+
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
+ unsigned int pixel_rate;
if (!plane_state->uapi.visible)
return 0;
+ pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
+
cpp = fb->format->cpp[0];
/*
@@ -153,7 +177,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
if (fb->format->is_yuv && fb->format->num_planes > 1)
cpp *= 4;
- return cpp * crtc_state->pixel_rate;
+ return pixel_rate * cpp;
}
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 2bcf15e34728..a6bbf42bae1f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -18,6 +18,9 @@ struct intel_plane_state;
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state
*plane_state);
+
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7abeefe8dce5..d16e17be26b0 100644
--- a/drivers/g
[Intel-gfx] [PULL] drm-misc-next
Hi Dave, Daniel, Here's this week drm-misc-next PR. Thank! Maxime drm-misc-next-2020-02-27: drm-misc-next for $kernel-version: UAPI Changes: Cross-subsystem Changes: Core Changes: - bridge: huge rework to get rid of omap_dss custom display drivers Driver Changes: - hisilicon: some fixes related to modes it can deal with / default to - virtio: shmem and gpu context fixes and enhancements - sun4i: Support for LVDS on the A33 The following changes since commit d718e53a48f7bcfa6cdd0c00d5ed1fb516595446: drm/sun4i: tcon: Support LVDS output on Allwinner A20 (2020-02-20 18:25:36 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-02-27 for you to fetch changes up to 18b39fb975b79d6526449ca7c8ab504bc92e2825: drm/virtio: add virtio_gpu_is_shmem helper (2020-02-27 11:31:34 +0100) drm-misc-next for $kernel-version: UAPI Changes: Cross-subsystem Changes: Core Changes: - bridge: huge rework to get rid of omap_dss custom display drivers Driver Changes: - hisilicon: some fixes related to modes it can deal with / default to - virtio: shmem and gpu context fixes and enhancements - sun4i: Support for LVDS on the A33 Boris Brezillon (1): drm/bridge: panel: Propagate bus format/flags Gurchetan Singh (6): drm/virtio: use consistent names for drm_files drm/virtio: factor out context create hypercall drm/virtio: track whether or not a context has been initiated drm/virtio: enqueue virtio_gpu_create_context after the first 3D ioctl drm/virtio: make mmap callback consistent with callbacks drm/virtio: add virtio_gpu_is_shmem helper Laurent Pinchart (56): drm/bridge: lvds-codec: Add to_lvds_codec() function drm/bridge: lvds-codec: Constify the drm_bridge_funcs structure video: hdmi: Change return type of hdmi_avi_infoframe_init() to void drm/connector: Add helper to get a connector type name drm/edid: Add flag to drm_display_info to identify HDMI sinks drm/bridge: Document the drm_encoder.bridge_chain field as private drm/bridge: Fix atomic state ops documentation drm/bridge: Improve overview documentation drm/bridge: Add connector-related bridge operations and data drm/bridge: Add interlace_allowed flag to drm_bridge drm/bridge: Extend bridge API to disable connector creation drm/bridge: dumb-vga-dac: Rename internal symbols to simple-bridge drm/bridge: dumb-vga-dac: Rename driver to simple-bridge drm/bridge: simple-bridge: Add support for non-VGA bridges drm/bridge: simple-bridge: Add support for enable GPIO drm/bridge: simple-bridge: Add support for the TI OPA362 drm/bridge: Add bridge driver for display connectors drm/bridge: Add driver for the TI TPD12S015 HDMI level shifter drm/bridge: panel: Implement bridge connector operations drm/bridge: tfp410: Replace manual connector handling with bridge drm/bridge: tfp410: Allow operation without drm_connector drm: Add helper to create a connector for a chain of bridges drm/omap: dss: Cleanup DSS ports on initialisation failure drm/omap: Simplify HDMI mode and infoframe configuration drm/omap: Factor out display type to connector type conversion drm/omap: Use the drm_panel_bridge API drm/omap: dss: Fix output next device lookup in DT drm/omap: Add infrastructure to support drm_bridge local to DSS outputs drm/omap: dss: Make omap_dss_device_ops optional drm/omap: hdmi: Allocate EDID in the .read_edid() operation drm/omap: hdmi4: Rework EDID read to isolate data read drm/omap: hdmi5: Rework EDID read to isolate data read drm/omap: hdmi4: Register a drm_bridge for EDID read drm/omap: hdmi5: Register a drm_bridge for EDID read drm/omap: hdmi4: Move mode set, enable and disable operations to bridge drm/omap: hdmi5: Move mode set, enable and disable operations to bridge drm/omap: hdmi4: Implement drm_bridge .hpd_notify() operation drm/omap: dss: Remove .set_hdmi_mode() and .set_infoframe() operations drm/omap: venc: Register a drm_bridge drm/omap: Create connector for bridges drm/omap: Switch the HDMI and VENC outputs to drm_bridge drm/omap: Remove HPD, detect and EDID omapdss operations drm/omap: hdmi: Remove omap_dss_device operations drm/omap: venc: Remove omap_dss_device operations drm/omap: hdmi4: Simplify EDID read drm/omap: hdmi5: Simplify EDID read drm/omap: dpi: Sort includes alphabetically drm/omap: dpi: Reorder functions in sections drm/omap: dpi: Simplify clock setting API drm/omap: dpi: Register a drm_bridge drm/omap: sdi: Sort includes alphabetically drm/omap: sdi: Register a drm_bridge drm/om
Re: [Intel-gfx] [PATCH v5] drm/i915: Use intel_plane_data_rate for min_cdclk calculation
On Thu, Feb 27, 2020 at 03:20:10PM +0200, Stanislav Lisovskiy wrote:
> There seems to be a bit of confusing redundancy in a way, how
> plane data rate/min cdclk are calculated.
> In fact both min cdclk, pixel rate and plane data rate are all
> part of the same formula as per BSpec.
>
> However currently we have intel_plane_data_rate, which is used
> to calculate plane data rate and which is also used in bandwidth
> calculations. However for calculating min_cdclk we have another
> piece of code, doing almost same calculation, but a bit differently
> and in a different place. However as both are actually part of same
> formula, probably would be wise to use plane data rate calculations
> as a basis anyway, thus avoiding code duplication and possible bugs
> related to this.
>
> Another thing is that I've noticed that during min_cdclk calculations
> we account for plane scaling, while for plane data rate, we don't.
> crtc->pixel_rate seems to account only for pipe ratio, however it is
> clearly stated in BSpec that plane data rate also need to account
> plane ratio as well.
>
> So what this commit does is:
> - Adds a plane ratio calculation to intel_plane_data_rate
> - Removes redundant calculations from skl_plane_min_cdclk which is
> used for gen9+ and now uses intel_plane_data_rate as a basis from
> there as well.
>
> v2: - Don't use 64 division if not needed(Ville Syrjälä)
> - Now use intel_plane_pixel_rate as a basis for calculations both
> at intel_plane_data_rate and skl_plane_min_cdclk(Ville Syrjälä)
>
> v3: - Again fix the division macro
> - Fix plane_pixel_rate to pixel_rate at intel_plane_pixel_rate
> callsites
>
> v4: - Renamed skl_plane_ratio function back(Ville Syrjälä)
>
> v5: - Don't precalculate plane pixel rate for invisible plane,
> check for visibility first, as in invisible case it will
> have dst_w and dst_h equal to zero, causing divide error.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 26 ++-
> .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
> drivers/gpu/drm/i915/display/intel_sprite.c | 15 ++-
> 3 files changed, 30 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index c86d7a35c816..956af022cf5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -133,15 +133,39 @@ intel_plane_destroy_state(struct drm_plane *plane,
> kfree(plane_state);
> }
>
> +unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + unsigned int src_w, src_h, dst_w, dst_h;
> +
> + src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> + src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> + dst_w = drm_rect_width(&plane_state->uapi.dst);
> + dst_h = drm_rect_height(&plane_state->uapi.dst);
> +
> + /* Downscaling limits the maximum pixel rate */
> + dst_w = min(src_w, dst_w);
> + dst_h = min(src_h, dst_h);
> +
> + WARN_ON(!dst_w || !dst_h);
Pointless warn. You'll get a div by zero anyway.
> +
> + return DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate,
> + src_w * src_h),
Bogus alignment.
> + dst_w * dst_h);
> +}
> +
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> unsigned int cpp;
> + unsigned int pixel_rate;
>
> if (!plane_state->uapi.visible)
> return 0;
>
> + pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
> +
> cpp = fb->format->cpp[0];
>
> /*
> @@ -153,7 +177,7 @@ unsigned int intel_plane_data_rate(const struct
> intel_crtc_state *crtc_state,
> if (fb->format->is_yuv && fb->format->num_planes > 1)
> cpp *= 4;
>
> - return cpp * crtc_state->pixel_rate;
> + return pixel_rate * cpp;
> }
>
> int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> index 2bcf15e34728..a6bbf42bae1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> @@ -18,6 +18,9 @@ struct intel_plane_state;
>
> extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
>
> +unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state);
> +
> unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state
[Intel-gfx] [PATCH 1/3] drm/i915: split intel_modeset_init() pre/post gem init
Turn current intel_modeset_init() to a pre-gem init function, and add a
new intel_modeset_init() function and move all post-gem modeset init
there, in the correct layer. Again, apart from possible failure paths,
no functional changes.
v2: Rebased
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä # v1
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 28 ++--
drivers/gpu/drm/i915/display/intel_display.h | 1 +
drivers/gpu/drm/i915/i915_drv.c | 17 ++--
3 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b8e57ce096a7..988e5948a142 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17823,8 +17823,8 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
return 0;
}
-/* part #2: call after irq install */
-int intel_modeset_init(struct drm_i915_private *i915)
+/* part #2: call after irq install, but before gem init */
+int intel_modeset_init_nogem(struct drm_i915_private *i915)
{
struct drm_device *dev = &i915->drm;
enum pipe pipe;
@@ -17915,6 +17915,30 @@ int intel_modeset_init(struct drm_i915_private *i915)
return 0;
}
+/* part #3: call after gem init */
+int intel_modeset_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ intel_overlay_setup(i915);
+
+ if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
+ return 0;
+
+ ret = intel_fbdev_init(&i915->drm);
+ if (ret)
+ return ret;
+
+ /* Only enable hotplug handling once the fbdev is fully set up. */
+ intel_hpd_init(i915);
+
+ intel_init_ipc(i915);
+
+ intel_psr_set_force_mode_changed(i915->psr.dp);
+
+ return 0;
+}
+
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index adb1225a3480..ccfff497c8c1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -616,6 +616,7 @@ intel_format_info_is_yuv_semiplanar(const struct
drm_format_info *info,
/* modesetting */
void intel_modeset_init_hw(struct drm_i915_private *i915);
int intel_modeset_init_noirq(struct drm_i915_private *i915);
+int intel_modeset_init_nogem(struct drm_i915_private *i915);
int intel_modeset_init(struct drm_i915_private *i915);
void intel_modeset_driver_remove(struct drm_i915_private *i915);
void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b086132df1b7..56eaf81082f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -57,7 +57,6 @@
#include "display/intel_hotplug.h"
#include "display/intel_overlay.h"
#include "display/intel_pipe_crc.h"
-#include "display/intel_psr.h"
#include "display/intel_sprite.h"
#include "display/intel_vga.h"
@@ -257,7 +256,7 @@ static int i915_driver_modeset_probe(struct
drm_i915_private *i915)
/* Important: The output setup functions called by modeset_init need
* working irqs for e.g. gmbus and dp aux transfers. */
- ret = intel_modeset_init(i915);
+ ret = intel_modeset_init_nogem(i915);
if (ret)
goto out;
@@ -265,22 +264,10 @@ static int i915_driver_modeset_probe(struct
drm_i915_private *i915)
if (ret)
goto cleanup_modeset;
- intel_overlay_setup(i915);
-
- if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
- return 0;
-
- ret = intel_fbdev_init(&i915->drm);
+ ret = intel_modeset_init(i915);
if (ret)
goto cleanup_gem;
- /* Only enable hotplug handling once the fbdev is fully set up. */
- intel_hpd_init(i915);
-
- intel_init_ipc(i915);
-
- intel_psr_set_force_mode_changed(i915->psr.dp);
-
return 0;
cleanup_gem:
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: move more display related probe/remove stuff to display
With the intel_display_* probe/remove functions clarified, we can
continue with moving more related calls to the right layer:
- drm_vblank_init()
- intel_bios_init() and intel_bios_driver_remove()
- intel_vga_register() and intel_vga_unregister()
- intel_csr_ucode_init() and intel_csr_ucode_fini()
Unfortunately, for the time being, we also need to move a call to the
*wrong* layer: the power domain init.
v2: move probe failure while at it, power domain init
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 31
drivers/gpu/drm/i915/i915_drv.c | 39 +---
2 files changed, 32 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 988e5948a142..bcdc82a7bf30 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -65,6 +65,7 @@
#include "intel_bw.h"
#include "intel_cdclk.h"
#include "intel_color.h"
+#include "intel_csr.h"
#include "intel_display_types.h"
#include "intel_dp_link_training.h"
#include "intel_fbc.h"
@@ -17798,6 +17799,27 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
{
int ret;
+ if (i915_inject_probe_failure(i915))
+ return -ENODEV;
+
+ if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
+ ret = drm_vblank_init(&i915->drm,
+ INTEL_NUM_PIPES(i915));
+ if (ret)
+ goto out;
+ }
+
+ intel_bios_init(i915);
+
+ ret = intel_vga_register(i915);
+ if (ret)
+ goto out;
+
+ /* FIXME: completely on the wrong abstraction layer */
+ intel_power_domains_init_hw(i915, false);
+
+ intel_csr_ucode_init(i915);
+
i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
@@ -17821,6 +17843,9 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
intel_fbc_init(i915);
return 0;
+
+out:
+ return ret;
}
/* part #2: call after irq install, but before gem init */
@@ -18857,6 +18882,12 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915)
destroy_workqueue(i915->modeset_wq);
intel_fbc_cleanup_cfb(i915);
+
+ intel_bios_driver_remove(i915);
+
+ intel_vga_unregister(i915);
+
+ intel_csr_ucode_fini(i915);
}
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 56eaf81082f7..3899793c4db5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -215,38 +215,7 @@ intel_teardown_mchbar(struct drm_i915_private *dev_priv)
/* part #1: call before irq install */
static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915)
{
- int ret;
-
- if (i915_inject_probe_failure(i915))
- return -ENODEV;
-
- if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
- ret = drm_vblank_init(&i915->drm,
- INTEL_NUM_PIPES(i915));
- if (ret)
- goto out;
- }
-
- intel_bios_init(i915);
-
- ret = intel_vga_register(i915);
- if (ret)
- goto out;
-
- intel_power_domains_init_hw(i915, false);
-
- intel_csr_ucode_init(i915);
-
- ret = intel_modeset_init_noirq(i915);
- if (ret)
- goto cleanup_vga_client;
-
- return 0;
-
-cleanup_vga_client:
- intel_vga_unregister(i915);
-out:
- return ret;
+ return intel_modeset_init_noirq(i915);
}
/* part #2: call after irq install */
@@ -293,12 +262,6 @@ static void i915_driver_modeset_remove(struct
drm_i915_private *i915)
static void i915_driver_modeset_remove_noirq(struct drm_i915_private *i915)
{
intel_modeset_driver_remove_noirq(i915);
-
- intel_bios_driver_remove(i915);
-
- intel_vga_unregister(i915);
-
- intel_csr_ucode_fini(i915);
}
static void intel_init_dpio(struct drm_i915_private *dev_priv)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: remove the now redundant i915_driver_modeset_* call layer
The i915_driver_modeset_*() functions have become irrelevant, and the
extra layer can be removed.
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 76 +
1 file changed, 19 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3899793c4db5..e912fb75bd9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -212,58 +212,6 @@ intel_teardown_mchbar(struct drm_i915_private *dev_priv)
release_resource(&dev_priv->mch_res);
}
-/* part #1: call before irq install */
-static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915)
-{
- return intel_modeset_init_noirq(i915);
-}
-
-/* part #2: call after irq install */
-static int i915_driver_modeset_probe(struct drm_i915_private *i915)
-{
- int ret;
-
- /* Important: The output setup functions called by modeset_init need
-* working irqs for e.g. gmbus and dp aux transfers. */
- ret = intel_modeset_init_nogem(i915);
- if (ret)
- goto out;
-
- ret = i915_gem_init(i915);
- if (ret)
- goto cleanup_modeset;
-
- ret = intel_modeset_init(i915);
- if (ret)
- goto cleanup_gem;
-
- return 0;
-
-cleanup_gem:
- i915_gem_suspend(i915);
- i915_gem_driver_remove(i915);
- i915_gem_driver_release(i915);
-cleanup_modeset:
- /* FIXME */
- intel_modeset_driver_remove(i915);
- intel_irq_uninstall(i915);
- intel_modeset_driver_remove_noirq(i915);
-out:
- return ret;
-}
-
-/* part #1: call before irq uninstall */
-static void i915_driver_modeset_remove(struct drm_i915_private *i915)
-{
- intel_modeset_driver_remove(i915);
-}
-
-/* part #2: call after irq uninstall */
-static void i915_driver_modeset_remove_noirq(struct drm_i915_private *i915)
-{
- intel_modeset_driver_remove_noirq(i915);
-}
-
static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
/*
@@ -931,7 +879,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret < 0)
goto out_cleanup_mmio;
- ret = i915_driver_modeset_probe_noirq(i915);
+ ret = intel_modeset_init_noirq(i915);
if (ret < 0)
goto out_cleanup_hw;
@@ -939,10 +887,20 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
if (ret)
goto out_cleanup_modeset;
- ret = i915_driver_modeset_probe(i915);
- if (ret < 0)
+ /* Important: The output setup functions called by modeset_init need
+* working irqs for e.g. gmbus and dp aux transfers. */
+ ret = intel_modeset_init_nogem(i915);
+ if (ret)
goto out_cleanup_irq;
+ ret = i915_gem_init(i915);
+ if (ret)
+ goto out_cleanup_modeset;
+
+ ret = intel_modeset_init(i915);
+ if (ret)
+ goto out_cleanup_gem;
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -951,6 +909,10 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
return 0;
+out_cleanup_gem:
+ i915_gem_suspend(i915);
+ i915_gem_driver_remove(i915);
+ i915_gem_driver_release(i915);
out_cleanup_irq:
intel_irq_uninstall(i915);
out_cleanup_modeset:
@@ -987,11 +949,11 @@ void i915_driver_remove(struct drm_i915_private *i915)
intel_gvt_driver_remove(i915);
- i915_driver_modeset_remove(i915);
+ intel_modeset_driver_remove(i915);
intel_irq_uninstall(i915);
- i915_driver_modeset_remove_noirq(i915);
+ intel_modeset_driver_remove_noirq(i915);
i915_reset_error_state(i915);
i915_gem_driver_remove(i915);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: Use intel_plane_data_rate for min_cdclk calculation
On Thu, 2020-02-27 at 15:47 +0200, Ville Syrjälä wrote:
> On Thu, Feb 27, 2020 at 03:20:10PM +0200, Stanislav Lisovskiy wrote:
> > There seems to be a bit of confusing redundancy in a way, how
> > plane data rate/min cdclk are calculated.
> > In fact both min cdclk, pixel rate and plane data rate are all
> > part of the same formula as per BSpec.
> >
> > However currently we have intel_plane_data_rate, which is used
> > to calculate plane data rate and which is also used in bandwidth
> > calculations. However for calculating min_cdclk we have another
> > piece of code, doing almost same calculation, but a bit differently
> > and in a different place. However as both are actually part of same
> > formula, probably would be wise to use plane data rate calculations
> > as a basis anyway, thus avoiding code duplication and possible bugs
> > related to this.
> >
> > Another thing is that I've noticed that during min_cdclk
> > calculations
> > we account for plane scaling, while for plane data rate, we don't.
> > crtc->pixel_rate seems to account only for pipe ratio, however it
> > is
> > clearly stated in BSpec that plane data rate also need to account
> > plane ratio as well.
> >
> > So what this commit does is:
> > - Adds a plane ratio calculation to intel_plane_data_rate
> > - Removes redundant calculations from skl_plane_min_cdclk which is
> > used for gen9+ and now uses intel_plane_data_rate as a basis from
> > there as well.
> >
> > v2: - Don't use 64 division if not needed(Ville Syrjälä)
> > - Now use intel_plane_pixel_rate as a basis for calculations
> > both
> > at intel_plane_data_rate and skl_plane_min_cdclk(Ville
> > Syrjälä)
> >
> > v3: - Again fix the division macro
> > - Fix plane_pixel_rate to pixel_rate at intel_plane_pixel_rate
> > callsites
> >
> > v4: - Renamed skl_plane_ratio function back(Ville Syrjälä)
> >
> > v5: - Don't precalculate plane pixel rate for invisible plane,
> > check for visibility first, as in invisible case it will
> > have dst_w and dst_h equal to zero, causing divide error.
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 26
> > ++-
> > .../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 15 ++-
> > 3 files changed, 30 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index c86d7a35c816..956af022cf5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -133,15 +133,39 @@ intel_plane_destroy_state(struct drm_plane
> > *plane,
> > kfree(plane_state);
> > }
> >
> > +unsigned int intel_plane_pixel_rate(const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state)
> > +{
> > + unsigned int src_w, src_h, dst_w, dst_h;
> > +
> > + src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
> > + src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > + dst_w = drm_rect_width(&plane_state->uapi.dst);
> > + dst_h = drm_rect_height(&plane_state->uapi.dst);
> > +
> > + /* Downscaling limits the maximum pixel rate */
> > + dst_w = min(src_w, dst_w);
> > + dst_h = min(src_h, dst_h);
> > +
> > + WARN_ON(!dst_w || !dst_h);
>
> Pointless warn. You'll get a div by zero anyway.
>
> > +
> > + return DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate,
> > + src_w * src_h),
>
> Bogus alignment.
>
> > + dst_w * dst_h);
> > +}
> > +
> > unsigned int intel_plane_data_rate(const struct intel_crtc_state
> > *crtc_state,
> >const struct intel_plane_state
> > *plane_state)
> > {
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > unsigned int cpp;
> > + unsigned int pixel_rate;
> >
> > if (!plane_state->uapi.visible)
> > return 0;
> >
> > + pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
> > +
> > cpp = fb->format->cpp[0];
> >
> > /*
> > @@ -153,7 +177,7 @@ unsigned int intel_plane_data_rate(const struct
> > intel_crtc_state *crtc_state,
> > if (fb->format->is_yuv && fb->format->num_planes > 1)
> > cpp *= 4;
> >
> > - return cpp * crtc_state->pixel_rate;
> > + return pixel_rate * cpp;
> > }
> >
> > int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > index 2bcf15e34728..a6bbf42bae1f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
> > @@ -18,6 +18,9 @@ struct intel_plane_state;
> >
> > extern const struct drm_plane_helper_funcs
> > intel_pla
[Intel-gfx] [PATCH 1/3] drm/i915/vgpu: improve vgpu abstractions
Add intel_vgpu_register() abstraction, rename i915_detect_vgpu() to
intel_vgpu_detect() to match other function naming, un-inline
intel_vgpu_active(), intel_vgpu_has_full_ppgtt() and
intel_vgpu_has_huge_gtt() to reduce header interdependencies.
The i915_vgpu.[ch] filename and intel_vgpu_ prefix discrepancy remains.
Cc: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fbc.c| 1 +
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gt/gen8_ppgtt.c| 1 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
drivers/gpu/drm/i915/i915_drv.c | 10 ++-
drivers/gpu/drm/i915/i915_drv.h | 5
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 1 +
drivers/gpu/drm/i915/i915_vgpu.c| 31 +++--
drivers/gpu/drm/i915/i915_vgpu.h| 25 ++---
drivers/gpu/drm/i915/intel_gvt.c| 1 +
11 files changed, 47 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index ddf8d3bb7a7d..6cfe14393885 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -42,6 +42,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
+#include "i915_vgpu.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 22ad6dde46ce..ea5300cab9f4 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -40,6 +40,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
+#include "i915_vgpu.h"
#include "intel_atomic_plane.h"
#include "intel_display_types.h"
#include "intel_frontbuffer.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 491cfbaaa330..5557dfa83a7b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -13,6 +13,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
#include "i915_gem_stolen.h"
+#include "i915_vgpu.h"
/*
* The BIOS typically reserves some of the system's memory for the exclusive
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 4d1de2d97d5c..e70215cd40c0 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -8,6 +8,7 @@
#include "gen8_ppgtt.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
+#include "i915_pvinfo.h"
#include "i915_vgpu.h"
#include "intel_gt.h"
#include "intel_gtt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index bef132709854..0392d2c79de9 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
#include
#include "i915_drv.h"
+#include "i915_vgpu.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_rc6.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b086132df1b7..254144678e19 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -758,13 +758,7 @@ static void i915_driver_register(struct drm_i915_private
*dev_priv)
i915_gem_driver_register(dev_priv);
i915_pmu_register(dev_priv);
- /*
-* Notify a valid surface after modesetting,
-* when running inside a VM.
-*/
- if (intel_vgpu_active(dev_priv))
- intel_uncore_write(&dev_priv->uncore, vgtif_reg(display_ready),
- VGT_DRV_DISPLAY_READY);
+ intel_vgpu_register(dev_priv);
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
@@ -971,7 +965,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
- i915_detect_vgpu(i915);
+ intel_vgpu_detect(i915);
ret = i915_driver_mmio_probe(i915);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea13fc0b409b..a306ebe44a08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1755,11 +1755,6 @@ static inline bool intel_gvt_active(struct
drm_i915_private *dev_priv)
return dev_priv->gvt;
}
-static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
-{
- return dev_priv->vgpu.active;
-}
-
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 3704e32ecd9c..d152b648c73c 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -23
[Intel-gfx] [PATCH 2/3] drm/i915/gvt: make intel_gvt_active internal to intel_gvt
Nobody else uses it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/intel_gvt.c | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a306ebe44a08..e57d7122cd2b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1750,11 +1750,6 @@ void i915_driver_remove(struct drm_i915_private *i915);
int i915_resume_switcheroo(struct drm_i915_private *i915);
int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state);
-static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
-{
- return dev_priv->gvt;
-}
-
int i915_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 28753cf227a2..21b91313cc5d 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -125,6 +125,11 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
+static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->gvt;
+}
+
/**
* intel_gvt_driver_remove - cleanup GVT components when i915 driver is
* unbinding
--
2.20.1
___
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[Intel-gfx] [PATCH 3/3] drm/i915/gvt: only include intel_gvt.h where needed
i915_drv.c is the only caller. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 254144678e19..9803e84ddc0a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -80,6 +80,7 @@ #include "i915_trace.h" #include "i915_vgpu.h" #include "intel_dram.h" +#include "intel_gvt.h" #include "intel_memory_region.h" #include "intel_pm.h" #include "vlv_suspend.h" diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e57d7122cd2b..cac2d905830c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -105,8 +105,6 @@ #include "intel_region_lmem.h" -#include "intel_gvt.h" - /* General customization: */ -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/huc: Fix error reported by I915_PARAM_HUC_STATUS
On 2/26/2020 6:02 AM, Michal Wajdeczko wrote:
On 25.02.2020 08:49, Ye, Tony wrote:
On 2/21/2020 11:32 PM, Michal Wajdeczko wrote:
From commit 84b1ca2f0e68 ("drm/i915/uc: prefer intel_gt over i915
in GuC/HuC paths") we stopped using HUC_STATUS error -ENODEV only
to indicate lack of HuC hardware and we started to use this error
also for all other cases when HuC was not in use or supported.
Fix that by relying again on HAS_GT_UC macro, since currently
used function intel_huc_is_supported() is based on HuC firmware
support which could be unsupported also due to force disabled
GuC firmware.
v2: use 0 only for disabled, add more error codes for other failures
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Tony Ye
Cc: Robert M. Fosha
Reviewed-by: Daniele Ceraolo Spurio #v1
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 29 +-
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index a74b65694512..301bb5d5e59a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -200,9 +200,13 @@ int intel_huc_auth(struct intel_huc *huc)
* This function reads status register to verify if HuC
* firmware was successfully loaded.
*
- * Returns: 1 if HuC firmware is loaded and verified,
- * 0 if HuC firmware is not loaded and -ENODEV if HuC
- * is not present on this platform.
+ * Returns:
+ * * 1 if HuC firmware is loaded and verified,
+ * * 0 if HuC firmware was disabled,
+ * * -ENODEV if HuC is not present on this platform,
+ * * -ENOPKG if HuC firmware was not installed,
+ * * -ENOEXEC if HuC firmware is invalid,
+ * * -EACCES if HuC firmware was not authenticated.
*/
int intel_huc_check_status(struct intel_huc *huc)
{
@@ -210,11 +214,26 @@ int intel_huc_check_status(struct intel_huc *huc)
intel_wakeref_t wakeref;
u32 status = 0;
- if (!intel_huc_is_supported(huc))
+ if (!HAS_GT_UC(gt->i915))
return -ENODEV;
+ switch (__intel_uc_fw_status(&huc->fw)) {
+ case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
+ case INTEL_UC_FIRMWARE_DISABLED:
+ return 0;
+ case INTEL_UC_FIRMWARE_MISSING:
+ return -ENOPKG;
+ case INTEL_UC_FIRMWARE_ERROR:
+ return -ENOEXEC;
What about INTEL_UC_FIRMWARE_FAIL?
I assumed that we don't need to handle that case here, since we are
still checking HuC status register below.
But if you want we can improve:
1) return early if FAIL, then check register anyway
2) return early if FAIL, trust fw state and return 1 without checking
register (as same register was already checked when we mark fw state as
RUNNING)
The current version looks good to me. Thanks.
Reviewed-by: Tony Ye
Regards,
Tony
+ default:
+ break;
+ }
+
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
status = intel_uncore_read(gt->uncore, huc->status.reg);
- return (status & huc->status.mask) == huc->status.value;
+ if ((status & huc->status.mask) != huc->status.value)
+ return -EACCES;
+
+ return 1;
}
___
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[Intel-gfx] [PATCH] drm/i915/dram: hide the dram structs better
Finish the job started in d28ae3b28187 ("drm/i915: split out
intel_dram.[ch] from i915_drv.c") by moving struct dram_dimm_info and
dram_channel_info inside intel_dram.c, the only user of the structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_dram.c | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea13fc0b409b..c5a06f864123 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1274,16 +1274,6 @@ struct drm_i915_private {
*/
};
-struct dram_dimm_info {
- u8 size, width, ranks;
-};
-
-struct dram_channel_info {
- struct dram_dimm_info dimm_l, dimm_s;
- u8 ranks;
- bool is_16gb_dimm;
-};
-
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
return container_of(dev, struct drm_i915_private, drm);
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 9bb9dd724d3f..6b922efb1d7c 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -6,6 +6,16 @@
#include "i915_drv.h"
#include "intel_dram.h"
+struct dram_dimm_info {
+ u8 size, width, ranks;
+};
+
+struct dram_channel_info {
+ struct dram_dimm_info dimm_l, dimm_s;
+ u8 ranks;
+ bool is_16gb_dimm;
+};
+
#define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
static const char *intel_dram_type_str(enum intel_dram_type type)
--
2.20.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
URL : https://patchwork.freedesktop.org/series/73999/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ea6f01e92c61 drm/i915: Skip barriers inside waits
b03376b455cc drm/i915/perf: Mark up the racy use of perf->exclusive_stream
f20fed23b607 drm/i915/perf: Manually acquire engine-wakeref around use of
kernel_context
98bae29ebe79 drm/i915/perf: Wait for lrc_reconfigure on disable
47888c782e0c drm/i915/gem: Consolidate ctx->engines[] release
94b9a31f328b drm/i915/gt: Prevent allocation on a banned context
68e1c6076e91 drm/i915/gem: Check that the context wasn't closed during setup
695b915be561 drm/i915/selftests: Disable heartbeat around manual pulse tests
03901330 drm/i915/gt: Reset queue_priority_hint after wedging
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
<0> [574.303565] i915_sel-62782 481822445us : __i915_subtests: Running
intel_execlists_live_selftests/live_error_interrupt
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
19d8a9ec5a90 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed
before we insert it")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 00de702c6c6f ("drm/i915: Check
that the vma hasn't been closed before we insert it")'
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed
before we insert it")
total: 1 errors, 1 warnings, 0 checks, 26 lines checked
d144797bcc6e drm/i915: Protect i915_request_await_start from early waits
0258eb86abee drm/i915/selftests: Verify LRC isolation
-:449: WARNING:MEMORY_BARRIER: memory barrier without comment
#449: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:5179:
+ wmb();
total: 0 errors, 1 warnings, 0 checks, 557 lines checked
dac7e7aa2e04 drm/i915/selftests: Check recovery from corrupted LRC
097feb8cc312 drm/i915/selftests: Wait for the kernel context switch
f6ebc42863d7 drm/i915/selftests: Be a little more lenient for reset workers
cceba24157d6 drm/i915/selftests: Add request throughput measurement to perf
-:90: WARNING:LINE_SPACING: Missing a blank line after declarations
#90: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1515:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:157: WARNING:LINE_SPACING: Missing a blank line after declarations
#157: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1582:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:213: WARNING:LINE_SPACING: Missing a blank line after declarations
#213: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1638:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:221: WARNING:LINE_SPACING: Missing a blank line after declarations
#221: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1646:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:263: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc
(sched/core.c)
#263: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1688:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 5 warnings, 0 checks, 301 lines checked
ad7bfc55d410 drm/i915/gt: Declare when we enabled timeslicing
9f8c2239da44 drm/i915/gt: Yield the timeslice if caught waiting on a user
semaphore
8744e278c5f7 drm/i915/execlists: Check the sentinel is alone in the ELSP
720aff89c6c8 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
___
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[Intel-gfx] [PATCH v6] drm/i915: Use intel_plane_data_rate for min_cdclk calculation
There seems to be a bit of confusing redundancy in a way, how
plane data rate/min cdclk are calculated.
In fact both min cdclk, pixel rate and plane data rate are all
part of the same formula as per BSpec.
However currently we have intel_plane_data_rate, which is used
to calculate plane data rate and which is also used in bandwidth
calculations. However for calculating min_cdclk we have another
piece of code, doing almost same calculation, but a bit differently
and in a different place. However as both are actually part of same
formula, probably would be wise to use plane data rate calculations
as a basis anyway, thus avoiding code duplication and possible bugs
related to this.
Another thing is that I've noticed that during min_cdclk calculations
we account for plane scaling, while for plane data rate, we don't.
crtc->pixel_rate seems to account only for pipe ratio, however it is
clearly stated in BSpec that plane data rate also need to account
plane ratio as well.
So what this commit does is:
- Adds a plane ratio calculation to intel_plane_data_rate
- Removes redundant calculations from skl_plane_min_cdclk which is
used for gen9+ and now uses intel_plane_data_rate as a basis from
there as well.
v2: - Don't use 64 division if not needed(Ville Syrjälä)
- Now use intel_plane_pixel_rate as a basis for calculations both
at intel_plane_data_rate and skl_plane_min_cdclk(Ville Syrjälä)
v3: - Again fix the division macro
- Fix plane_pixel_rate to pixel_rate at intel_plane_pixel_rate
callsites
v4: - Renamed skl_plane_ratio function back(Ville Syrjälä)
v5: - Don't precalculate plane pixel rate for invisible plane,
check for visibility first, as in invisible case it will
have dst_w and dst_h equal to zero, causing divide error.
v6: - Removed useless warn in intel_plane_pixel_rate(Ville Syrjälä)
- Fixed alignment in intel_plane_data_rate(Ville Syrjälä)
- Changed pixel_rate type to be unsigned int in
skl_plane_min_cdclk(Ville Syrjälä)
Signed-off-by: Stanislav Lisovskiy
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 24 ++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 15 ++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index c86d7a35c816..457b258683d3 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -133,15 +133,37 @@ intel_plane_destroy_state(struct drm_plane *plane,
kfree(plane_state);
}
+unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ unsigned int src_w, src_h, dst_w, dst_h;
+ unsigned int pixel_rate = crtc_state->pixel_rate;
+
+ src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+ dst_w = drm_rect_width(&plane_state->uapi.dst);
+ dst_h = drm_rect_height(&plane_state->uapi.dst);
+
+ /* Downscaling limits the maximum pixel rate */
+ dst_w = min(src_w, dst_w);
+ dst_h = min(src_h, dst_h);
+
+ return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h),
+ dst_w * dst_h);
+}
+
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
+ unsigned int pixel_rate;
if (!plane_state->uapi.visible)
return 0;
+ pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
+
cpp = fb->format->cpp[0];
/*
@@ -153,7 +175,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
if (fb->format->is_yuv && fb->format->num_planes > 1)
cpp *= 4;
- return cpp * crtc_state->pixel_rate;
+ return pixel_rate * cpp;
}
int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 2bcf15e34728..a6bbf42bae1f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -18,6 +18,9 @@ struct intel_plane_state;
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
+unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state
*plane_state);
+
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
void intel_plane_copy_uapi_to_hw_st
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev6)
== Series Details == Series: Refactor Gen11+ SAGV support (rev6) URL : https://patchwork.freedesktop.org/series/73856/ State : warning == Summary == $ dim checkpatch origin/drm-tip a72659eb4666 drm/i915: Start passing latency as parameter 81ddfe1ca471 drm/i915: Introduce skl_plane_wm_level accessor. bb8fb326c38f drm/i915: Add intel_bw_get_*_state helpers 1f6cb30bce42 drm/i915: Introduce more *_state_changed indicators 0aad2ca03244 drm/i915: Refactor intel_can_enable_sagv -:806: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'state->active_pipe_changes != 0' #806: FILE: drivers/gpu/drm/i915/intel_pm.c:6183: + if ((state->active_pipe_changes != 0) || state->ddb_state_changed) total: 0 errors, 0 warnings, 1 checks, 679 lines checked 8b626dac4931 drm/i915: Added required new PCode commands 227852eaaaf7 drm/i915: Restrict qgv points which don't have enough bandwidth. 92ef8dc6a4f2 drm/i915: Enable SAGV support for Gen12 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev6)
== Series Details == Series: Refactor Gen11+ SAGV support (rev6) URL : https://patchwork.freedesktop.org/series/73856/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: Start passing latency as parameter Okay! Commit: drm/i915: Introduce skl_plane_wm_level accessor. Okay! Commit: drm/i915: Add intel_bw_get_*_state helpers Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
URL : https://patchwork.freedesktop.org/series/73999/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8018 -> Patchwork_16731
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_16731:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [DMESG-FAIL][1] ([i915#1233]) -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
- {fi-tgl-u}: [DMESG-FAIL][3] ([i915#1233]) -> [DMESG-FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
Known issues
Here are the changes found in Patchwork_16731 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gem_contexts:
- fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] ([i915#424])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111096] / [i915#323]) -> [FAIL][8]
([fdo#111407])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
Participating hosts (49 -> 43)
--
Additional (1): fi-byt-n2820
Missing(7): fi-ilk-m540 fi-byt-squawks fi-glk-dsi fi-bsw-cyan
fi-ctg-p8600 fi-tgl-y fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8018 -> Patchwork_16731
CI-20190529: 20190529
CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16731: 720aff89c6c8efa0deb0c662afc100e8a713db0a @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
720aff89c6c8 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
8744e278c5f7 drm/i915/execlists: Check the sentinel is alone in the ELSP
9f8c2239da44 drm/i915/gt: Yield the timeslice if caught waiting on a user
semaphore
ad7bfc55d410 drm/i915/gt: Declare when we enabled timeslicing
cceba24157d6 drm/i915/selftests: Add request throughput measurement to perf
f6ebc42863d7 drm/i915/selftests: Be a little more lenient for reset workers
097feb8cc312 drm/i915/selftests: Wait for the kernel context switch
dac7e7aa2e04 drm/i915/selftests: Check recovery from corrupted LRC
0258eb86abee drm/i915/selftests: Verify LRC isolation
d144797bcc6e drm/i915: Protect i915_request_await_start from early waits
19d8a9ec5a90 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
03901330 drm/i915/gt: Reset queue_priority_hint after wedging
695b915be561 drm/i915/selftests: Disable heartbeat around manual pulse tests
68e1c6076e91 drm/i915/gem: Check that the context wasn't closed during setup
94b9a31f328b drm/i915/gt: Prevent allocation on a banned context
47888c782e0c drm/i915/gem: Consolidate ctx->engines[] release
98bae29ebe79 drm/i915/perf: Wait for lrc_reconfigure on disable
f20fed23b607 drm/i915/perf: Manually acquire engine-wakeref around use of
kernel_context
b03376b455cc drm/i915/perf: Mark up the racy use of perf->exclusive_stream
ea6f01e92c61 drm/i915: Skip barriers inside waits
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/index.html
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Re: [Intel-gfx] [PATCH v18 2/8] drm/i915: Introduce skl_plane_wm_level accessor.
On Mon, Feb 24, 2020 at 05:32:34PM +0200, Stanislav Lisovskiy wrote:
> For future Gen12 SAGV implementation we need to
> seemlessly alter wm levels calculated, depending
> on whether we are allowed to enable SAGV or not.
>
> So this accessor will give additional flexibility
> to do that.
>
> Currently this accessor is still simply working
> as "pass-through" function. This will be changed
> in next coming patches from this series.
>
> v2: - plane_id -> plane->id(Ville Syrjälä)
When did I say that? Can't find a previous review of this patch.
Anywyas, that change seems to cause a lot of needless noise into the
patch, and atm I can't see why we'd require it.
> - Moved wm_level var to have more local scope
> (Ville Syrjälä)
> - Renamed yuv to color_plane(Ville Syrjälä) in
> skl_plane_wm_level
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 120 +---
> 1 file changed, 81 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d6933e382657..e1d167429489 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4548,6 +4548,18 @@ icl_get_total_relative_data_rate(struct
> intel_crtc_state *crtc_state,
> return total_data_rate;
> }
>
> +static const struct skl_wm_level *
> +skl_plane_wm_level(struct intel_plane *plane,
> +const struct intel_crtc_state *crtc_state,
nit: I'd put the crtc_state as the first parameter as that's the thing
we're operating on. The other stuff just specifies which piece we want
to dig out.
> +int level,
> +int color_plane)
> +{
> + const struct skl_plane_wm *wm =
> + &crtc_state->wm.skl.optimal.planes[plane->id];
> +
> + return color_plane ? &wm->uv_wm[level] : &wm->wm[level];
> +}
> +
> static int
> skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> @@ -4560,7 +4572,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *crtc_state)
> u16 total[I915_MAX_PLANES] = {};
> u16 uv_total[I915_MAX_PLANES] = {};
> u64 total_data_rate;
> - enum plane_id plane_id;
> + struct intel_plane *plane;
> int num_active;
> u64 plane_data_rate[I915_MAX_PLANES] = {};
> u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> @@ -4612,22 +4624,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *crtc_state)
>*/
> for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> blocks = 0;
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR) {
> - if (wm->wm[level].min_ddb_alloc >
> total[PLANE_CURSOR]) {
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane)
> {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_uv_level;
> +
> + wm_level = skl_plane_wm_level(plane, crtc_state,
> + level, false);
> + wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> + level, true);
false/true aren't particularly sensible color plane indices.
> +
> + if (plane->id == PLANE_CURSOR) {
> + if (wm_level->min_ddb_alloc >
> total[PLANE_CURSOR]) {
> drm_WARN_ON(&dev_priv->drm,
> - wm->wm[level].min_ddb_alloc
> != U16_MAX);
> + wm_level->min_ddb_alloc !=
> U16_MAX);
> blocks = U32_MAX;
> break;
> }
> continue;
> }
>
> - blocks += wm->wm[level].min_ddb_alloc;
> - blocks += wm->uv_wm[level].min_ddb_alloc;
> + blocks += wm_level->min_ddb_alloc;
> + blocks += wm_uv_level->min_ddb_alloc;
> }
>
> if (blocks <= alloc_size) {
> @@ -4649,13 +4667,18 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *crtc_state)
>* watermark level, plus an extra share of the leftover blocks
>* proportional to its relative data rate.
>*/
> - for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - const struct skl_plane_wm *wm =
> - &crtc_state->wm.skl.optimal.planes[plane_id];
> + for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> + const struct skl_wm_level *wm_level;
> + const struct skl_wm_level *wm_
Re: [Intel-gfx] [PATCH v18 3/8] drm/i915: Add intel_bw_get_*_state helpers
On Mon, Feb 24, 2020 at 05:32:35PM +0200, Stanislav Lisovskiy wrote:
> Add correspondent helpers to be able to get old/new bandwidth
> global state object.
>
> v2: - Fixed typo in function call
> v3: - Changed new functions naming to use convention proposed
> by Jani Nikula, i.e intel_bw_* in intel_bw.c file.
And now they no longer match the naming pattern used by all the
other simialr functions.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 33 ++---
> drivers/gpu/drm/i915/display/intel_bw.h | 9 +++
> 2 files changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 58b264bc318d..bdad7476dc7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -374,8 +374,35 @@ static unsigned int intel_bw_data_rate(struct
> drm_i915_private *dev_priv,
> return data_rate;
> }
>
> -static struct intel_bw_state *
> -intel_atomic_get_bw_state(struct intel_atomic_state *state)
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_old_global_obj_state(state,
> &dev_priv->bw_obj);
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *bw_state;
> +
> + bw_state = intel_atomic_get_new_global_obj_state(state,
> &dev_priv->bw_obj);
> +
> + if (IS_ERR(bw_state))
> + return ERR_CAST(bw_state);
> +
> + return to_intel_bw_state(bw_state);
> +}
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_global_state *bw_state;
> @@ -420,7 +447,7 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_atomic_get_bw_state(state);
> + bw_state = intel_bw_get_state(state);
> if (IS_ERR(bw_state))
> return PTR_ERR(bw_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index a8aa7624c5aa..b5f61463922f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -24,6 +24,15 @@ struct intel_bw_state {
>
> #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
>
> +struct intel_bw_state *
> +intel_bw_get_old_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_new_state(struct intel_atomic_state *state);
> +
> +struct intel_bw_state *
> +intel_bw_get_state(struct intel_atomic_state *state);
> +
> void intel_bw_init_hw(struct drm_i915_private *dev_priv);
> int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev6)
== Series Details == Series: Refactor Gen11+ SAGV support (rev6) URL : https://patchwork.freedesktop.org/series/73856/ State : success == Summary == CI Bug Log - changes from CI_DRM_8018 -> Patchwork_16732 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/index.html Known issues Here are the changes found in Patchwork_16732 that come from known issues: ### IGT changes ### Issues hit * igt@kms_busy@basic@flip: - fi-skl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#88]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-skl-guc/igt@kms_busy@ba...@flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-skl-guc/igt@kms_busy@ba...@flip.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-s: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cml-s/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cml-s/igt@kms_frontbuffer_track...@basic.html - fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html - fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_frontbuffer_track...@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-kbl-7500u/igt@kms_frontbuffer_track...@basic.html - fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#88]: https://gitlab.freedesktop.org/drm/intel/issues/88 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 41) -- Additional (1): fi-byt-n2820 Missing(9): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-tgl-y fi-bdw-samus fi-kbl-r Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8018 -> Patchwork_16732 CI-20190529: 20190529 CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16732: 92ef8dc6a4f25ddc463b7cc74d4dfafe8913e708 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 92ef8dc6a4f2 drm/i915: Enable SAGV support for Gen12 227852eaaaf7 drm/i915: Restrict qgv points which don't have enough bandwidth. 8b626dac4931 drm/i915: Added required new PCode commands 0aad2ca03244 drm/i915: Refactor intel_can_enable_sagv 1f6cb30bce42 drm/i915: Introduce more *_state_changed indicators bb8fb326c38f drm/i915: Add intel_bw_get_*_state helpers 81ddfe1ca471 drm/i915: Introduce skl_plane_wm_level accessor. a72659eb4666 drm/i915: Start passing latency as parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16732/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/crc: move pipe_crc from drm_i915_private to intel_crtc
Having an array pipe_crc[I915_MAX_PIPES] in struct drm_i915_private
should be an obvious clue this should be located in struct intel_crtc
instead. Make it so.
As a side-effect, fix some errors in indexing pipe_crc with both pipe
and crtc index. And, of course, reduce the size of i915_drv.h.
Cc: Anshuman Gupta
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
.../drm/i915/display/intel_display_types.h| 30 +++
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 17 +--
drivers/gpu/drm/i915/display/intel_pipe_crc.h | 4 +--
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 30 ---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
7 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b8e57ce096a7..f388cfaf408d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16705,6 +16705,8 @@ static int intel_crtc_init(struct drm_i915_private
*dev_priv, enum pipe pipe)
intel_color_init(crtc);
+ intel_crtc_crc_init(crtc);
+
drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0a06043d4d4c..ac5d066e23a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1045,6 +1045,32 @@ struct intel_crtc_state {
enum transcoder mst_master_transcoder;
};
+enum intel_pipe_crc_source {
+ INTEL_PIPE_CRC_SOURCE_NONE,
+ INTEL_PIPE_CRC_SOURCE_PLANE1,
+ INTEL_PIPE_CRC_SOURCE_PLANE2,
+ INTEL_PIPE_CRC_SOURCE_PLANE3,
+ INTEL_PIPE_CRC_SOURCE_PLANE4,
+ INTEL_PIPE_CRC_SOURCE_PLANE5,
+ INTEL_PIPE_CRC_SOURCE_PLANE6,
+ INTEL_PIPE_CRC_SOURCE_PLANE7,
+ INTEL_PIPE_CRC_SOURCE_PIPE,
+ /* TV/DP on pre-gen5/vlv can't use the pipe source. */
+ INTEL_PIPE_CRC_SOURCE_TV,
+ INTEL_PIPE_CRC_SOURCE_DP_B,
+ INTEL_PIPE_CRC_SOURCE_DP_C,
+ INTEL_PIPE_CRC_SOURCE_DP_D,
+ INTEL_PIPE_CRC_SOURCE_AUTO,
+ INTEL_PIPE_CRC_SOURCE_MAX,
+};
+
+#define INTEL_PIPE_CRC_ENTRIES_NR 128
+struct intel_pipe_crc {
+ spinlock_t lock;
+ int skipped;
+ enum intel_pipe_crc_source source;
+};
+
struct intel_crtc {
struct drm_crtc base;
enum pipe pipe;
@@ -1088,6 +1114,10 @@ struct intel_crtc {
/* per pipe DSB related info */
struct intel_dsb dsb;
+
+#ifdef CONFIG_DEBUG_FS
+ struct intel_pipe_crc pipe_crc;
+#endif
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 59d7e3cb3445..a9a5df2fee4d 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -441,15 +441,11 @@ display_crc_ctl_parse_source(const char *buf, enum
intel_pipe_crc_source *s)
return 0;
}
-void intel_display_crc_init(struct drm_i915_private *dev_priv)
+void intel_crtc_crc_init(struct intel_crtc *crtc)
{
- enum pipe pipe;
+ struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
- for_each_pipe(dev_priv, pipe) {
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
-
- spin_lock_init(&pipe_crc->lock);
- }
+ spin_lock_init(&pipe_crc->lock);
}
static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
@@ -587,7 +583,8 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
const char *source_name,
int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
{
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
enum intel_display_power_domain power_domain;
enum intel_pipe_crc_source source;
intel_wakeref_t wakeref;
@@ -640,7 +637,7 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc
*intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
+ struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
u32 val = 0;
if (!crtc->crc.opened)
@@ -660,7 +657,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc
*intel_crtc)
{
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
+ struct intel_p
Re: [Intel-gfx] [PATCH v18 4/8] drm/i915: Introduce more *_state_changed indicators
On Tue, Feb 25, 2020 at 04:57:33PM +0200, Stanislav Lisovskiy wrote:
> The reasoning behind this is such that current dependencies
> in the code are rather implicit in a sense, we have to constantly
> check a bunch of different bits like state->modeset,
> state->active_pipe_changes, which sometimes can indicate counter
> intuitive changes.
>
> By introducing more fine grained state change tracking we achieve
> better readability and dependency maintenance for the code.
>
> For example it is no longer needed to evaluate active_pipe_changes
> to understand if there were changes for wm/ddb - lets just have
> a correspondent bit in a state, called ddb_state_changed.
>
> active_pipe_changes just indicate whether there was some pipe added
> or removed. Then we evaluate if wm/ddb had been changed.
> Same for sagv/bw state. ddb changes may or may not affect if out
> bandwidth constraints have been changed.
>
> v2: Add support for older Gens in order not to introduce regressions
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 2 ++
> drivers/gpu/drm/i915/display/intel_bw.c | 28 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 16 ++
> .../drm/i915/display/intel_display_types.h| 32 ---
> drivers/gpu/drm/i915/intel_pm.c | 5 ++-
> 5 files changed, 62 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index d043057d2fa0..0db9c66d3c0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -525,6 +525,8 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
> state->dpll_set = state->modeset = false;
> state->global_state_changed = false;
> state->active_pipes = 0;
> + state->ddb_state_changed = false;
> + state->bw_state_changed = false;
Not really liking these.
After some pondering I was thinking along the lines of something simple
like this:
struct bw_state {
u8 sagv_reject;
};
bw_check()
{
for_each_crtc_in_state() {
if (sagv_possible(crtc_state))
new->sagv_reject &= ~BIT(pipe);
else
new->sagv_reject |= BIT(pipe);
}
calculate new->qgv_mask
}
> }
>
> struct intel_crtc_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index bdad7476dc7b..d5be603b8b03 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -424,9 +424,27 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> struct intel_crtc *crtc;
> int i, ret;
>
> - /* FIXME earlier gens need some checks too */
> - if (INTEL_GEN(dev_priv) < 11)
> + /*
> + * For earlier Gens let's consider bandwidth changed if ddb
> requirements,
> + * has been changed.
> + */
> + if (INTEL_GEN(dev_priv) < 11) {
> + if (state->ddb_state_changed) {
> + bw_state = intel_bw_get_state(state);
> + if (IS_ERR(bw_state))
> + return PTR_ERR(bw_state);
> +
> + ret = intel_atomic_lock_global_state(&bw_state->base);
> + if (ret)
> + return ret;
> +
> + DRM_DEBUG_KMS("Marking bw state changed for atomic
> state %p\n",
> + state);
> +
> + state->bw_state_changed = true;
> + }
> return 0;
> + }
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> @@ -447,7 +465,7 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_bw_get_state(state);
> + bw_state = intel_bw_get_state(state);
> if (IS_ERR(bw_state))
> return PTR_ERR(bw_state);
>
> @@ -468,6 +486,10 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> if (ret)
> return ret;
>
> + DRM_DEBUG_KMS("Marking bw state changed for atomic state %p\n", state);
> +
> + state->bw_state_changed = true;
> +
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3031e64ee518..137fb645097a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15540,8 +15540,10 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
Re: [Intel-gfx] [PATCH v18 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Tue, Feb 25, 2020 at 05:00:43PM +0200, Stanislav Lisovskiy wrote: > According to BSpec 53998, we should try to > restrict qgv points, which can't provide > enough bandwidth for desired display configuration. > > Currently we are just comparing against all of > those and take minimum(worst case). > > v2: Fixed wrong PCode reply mask, removed hardcoded > values. > > v3: Forbid simultaneous legacy SAGV PCode requests and > restricting qgv points. Put the actual restriction > to commit function, added serialization(thanks to Ville) > to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > v4: > - Minor code refactoring, fixed few typos(thanks to James Ausmus) > - Change the naming of qgv point > masking/unmasking functions(James Ausmus). > - Simplify the masking/unmasking operation itself, > as we don't need to mask only single point per request(James Ausmus) > - Reject and stick to highest bandwidth point if SAGV > can't be enabled(BSpec) > > v5: > - Add new mailbox reply codes, which seems to happen during boot > time for TGL and indicate that QGV setting is not yet available. > > v6: > - Increase number of supported QGV points to be in sync with BSpec. > > v7: - Rebased and resolved conflict to fix build failure. > - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus) > > v8: - Don't report an error if we can't restrict qgv points, as SAGV > can be disabled by BIOS, which is completely legal. So don't > make CI panic. Instead if we detect that there is only 1 QGV > point accessible just analyze if we can fit the required bandwidth > requirements, but no need in restricting. > > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV > simultaneously. > > v10: - Fix CDCLK corruption, because of global state getting serialized >without modeset, which caused copying of non-calculated cdclk >to be copied to dev_priv(thanks to Ville for the hint). > > v11: - Remove unneeded headers and spaces(Matthew Roper) > - Remove unneeded intel_qgv_info qi struct from bw check and zero >out the needed one(Matthew Roper) > - Changed QGV error message to have more clear meaning(Matthew Roper) > - Use state->modeset_set instead of any_ms(Matthew Roper) > - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used > - Keep using crtc_state->hw.active instead of .enable(Matthew Roper) > - Moved unrelated changes to other patch(using latency as parameter >for plane wm calculation, moved to SAGV refactoring patch) > > v12: - Fix rebase conflict with own temporary SAGV/QGV fix. > - Remove unnecessary mask being zero check when unmasking >qgv points as this is completely legal(Matt Roper) > - Check if we are setting the same mask as already being set >in hardware to prevent error from PCode. > - Fix error message when restricting/unrestricting qgv points >to "mask/unmask" which sounds more accurate(Matt Roper) > - Move sagv status setting to icl_get_bw_info from atomic check >as this should be calculated only once.(Matt Roper) > - Edited comments for the case when we can't enable SAGV and >use only 1 QGV point with highest bandwidth to be more >understandable.(Matt Roper) > > v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä) > - Changed comment for zero new_mask in qgv points masking function >to better reflect reality(Ville Syrjälä) > - Simplified bit mask operation in qgv points masking function >(Ville Syrjälä) > - Moved intel_qgv_points_mask closer to gen11 SAGV disabling, >however this still can't be under modeset condition(Ville Syrjälä) > - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask >(Ville Syrjälä) > - Extracted PCode changes to separate patch.(Ville Syrjälä) > - Now treat num_planes 0 same as 1 to avoid confusion and >returning max_bw as 0, which would prevent choosing QGV >point having max bandwidth in case if SAGV is not allowed, >as per BSpec(Ville Syrjälä) > - Do the actual qgv_points_mask swap in the same place as >all other global state parts like cdclk are swapped. >In the next patch, this all will be moved to bw state as >global state, once new global state patch series from Ville >lands > > v14: - Now using global state to serialize access to qgv points > - Added global state locking back, otherwise we seem to read >bw state in a wrong way. > > v15: - Added TODO comment for near atomic global state locking in >bw code. > > v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed >with Jani Nikula. > - Take bw_state_changed flag into use. > > Signed-off-by: Stanislav Lisovskiy >
Re: [Intel-gfx] [PATCH] drm/i915/crc: move pipe_crc from drm_i915_private to intel_crtc
On Thu, Feb 27, 2020 at 06:12:53PM +0200, Jani Nikula wrote:
> Having an array pipe_crc[I915_MAX_PIPES] in struct drm_i915_private
> should be an obvious clue this should be located in struct intel_crtc
> instead. Make it so.
>
> As a side-effect, fix some errors in indexing pipe_crc with both pipe
> and crtc index. And, of course, reduce the size of i915_drv.h.
>
> Cc: Anshuman Gupta
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
lgtm
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> .../drm/i915/display/intel_display_types.h| 30 +++
> drivers/gpu/drm/i915/display/intel_pipe_crc.c | 17 +--
> drivers/gpu/drm/i915/display/intel_pipe_crc.h | 4 +--
> drivers/gpu/drm/i915/i915_drv.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 30 ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 7 files changed, 42 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b8e57ce096a7..f388cfaf408d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -16705,6 +16705,8 @@ static int intel_crtc_init(struct drm_i915_private
> *dev_priv, enum pipe pipe)
>
> intel_color_init(crtc);
>
> + intel_crtc_crc_init(crtc);
> +
> drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0a06043d4d4c..ac5d066e23a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1045,6 +1045,32 @@ struct intel_crtc_state {
> enum transcoder mst_master_transcoder;
> };
>
> +enum intel_pipe_crc_source {
> + INTEL_PIPE_CRC_SOURCE_NONE,
> + INTEL_PIPE_CRC_SOURCE_PLANE1,
> + INTEL_PIPE_CRC_SOURCE_PLANE2,
> + INTEL_PIPE_CRC_SOURCE_PLANE3,
> + INTEL_PIPE_CRC_SOURCE_PLANE4,
> + INTEL_PIPE_CRC_SOURCE_PLANE5,
> + INTEL_PIPE_CRC_SOURCE_PLANE6,
> + INTEL_PIPE_CRC_SOURCE_PLANE7,
> + INTEL_PIPE_CRC_SOURCE_PIPE,
> + /* TV/DP on pre-gen5/vlv can't use the pipe source. */
> + INTEL_PIPE_CRC_SOURCE_TV,
> + INTEL_PIPE_CRC_SOURCE_DP_B,
> + INTEL_PIPE_CRC_SOURCE_DP_C,
> + INTEL_PIPE_CRC_SOURCE_DP_D,
> + INTEL_PIPE_CRC_SOURCE_AUTO,
> + INTEL_PIPE_CRC_SOURCE_MAX,
> +};
> +
> +#define INTEL_PIPE_CRC_ENTRIES_NR128
> +struct intel_pipe_crc {
> + spinlock_t lock;
> + int skipped;
> + enum intel_pipe_crc_source source;
> +};
> +
> struct intel_crtc {
> struct drm_crtc base;
> enum pipe pipe;
> @@ -1088,6 +1114,10 @@ struct intel_crtc {
>
> /* per pipe DSB related info */
> struct intel_dsb dsb;
> +
> +#ifdef CONFIG_DEBUG_FS
> + struct intel_pipe_crc pipe_crc;
> +#endif
> };
>
> struct intel_plane {
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> index 59d7e3cb3445..a9a5df2fee4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
> @@ -441,15 +441,11 @@ display_crc_ctl_parse_source(const char *buf, enum
> intel_pipe_crc_source *s)
> return 0;
> }
>
> -void intel_display_crc_init(struct drm_i915_private *dev_priv)
> +void intel_crtc_crc_init(struct intel_crtc *crtc)
> {
> - enum pipe pipe;
> + struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
>
> - for_each_pipe(dev_priv, pipe) {
> - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
> -
> - spin_lock_init(&pipe_crc->lock);
> - }
> + spin_lock_init(&pipe_crc->lock);
> }
>
> static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
> @@ -587,7 +583,8 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
> const char *source_name,
> int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
> enum intel_display_power_domain power_domain;
> enum intel_pipe_crc_source source;
> intel_wakeref_t wakeref;
> @@ -640,7 +637,7 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc
> *intel_crtc)
> {
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
> + struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc;
> u32 val = 0;
>
> if (!crtc->crc.opened)
> @@ -660,7 +657,7 @@ void intel_crtc_disable_p
Re: [Intel-gfx] [PATCH v18 1/8] drm/i915: Start passing latency as parameter
On Mon, Feb 24, 2020 at 05:32:33PM +0200, Stanislav Lisovskiy wrote:
> We need to start passing memory latency as a
> parameter when calculating plane wm levels,
> as latency can get changed in different
> circumstances(for example with or without SAGV).
> So we need to be more flexible on that matter.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/intel_pm.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ffac0b862ca5..d6933e382657 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4002,6 +4002,7 @@ static int skl_compute_wm_params(const struct
> intel_crtc_state *crtc_state,
>int color_plane);
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>int level,
> + u32 latency,
I'd make it just unsigned int or something all over. Otherwise lgtm
Reviewed-by: Ville Syrjälä
>const struct skl_wm_params *wp,
>const struct skl_wm_level *result_prev,
>struct skl_wm_level *result /* out */);
> @@ -4024,7 +4025,9 @@ skl_cursor_allocation(const struct intel_crtc_state
> *crtc_state,
> drm_WARN_ON(&dev_priv->drm, ret);
>
> for (level = 0; level <= max_level; level++) {
> - skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> + u32 latency = dev_priv->wm.skl_latency[level];
> +
> + skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> if (wm.min_ddb_alloc == U16_MAX)
> break;
>
> @@ -4978,12 +4981,12 @@ static bool skl_wm_has_lines(struct drm_i915_private
> *dev_priv, int level)
>
> static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>int level,
> + u32 latency,
>const struct skl_wm_params *wp,
>const struct skl_wm_level *result_prev,
>struct skl_wm_level *result /* out */)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> - u32 latency = dev_priv->wm.skl_latency[level];
> uint_fixed_16_16_t method1, method2;
> uint_fixed_16_16_t selected_result;
> u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -5112,9 +5115,10 @@ skl_compute_wm_levels(const struct intel_crtc_state
> *crtc_state,
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> + u32 latency = dev_priv->wm.skl_latency[level];
>
> - skl_compute_plane_wm(crtc_state, level, wm_params,
> - result_prev, result);
> + skl_compute_plane_wm(crtc_state, level, latency,
> + wm_params, result_prev, result);
>
> result_prev = result;
> }
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/perf: reintroduce wait on OA configuration completion
== Series Details == Series: drm/i915/perf: reintroduce wait on OA configuration completion URL : https://patchwork.freedesktop.org/series/74014/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9c67fa7e5fe9 drm/i915/perf: reintroduce wait on OA configuration completion -:28: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!rq" #28: FILE: drivers/gpu/drm/i915/i915_perf.c:1406: + GEM_BUG_ON(rq == NULL); -:45: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "stream->configure_request" #45: FILE: drivers/gpu/drm/i915/i915_perf.c:1428: + GEM_BUG_ON(stream->configure_request != NULL); -:65: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "stream->configure_request" #65: FILE: drivers/gpu/drm/i915/i915_perf.c:2029: + GEM_BUG_ON(stream->configure_request != NULL); -:122: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "stream->configure_request" #122: FILE: drivers/gpu/drm/i915/i915_perf.c:2909: + GEM_BUG_ON(stream->configure_request != NULL); total: 0 errors, 0 warnings, 4 checks, 123 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dram: hide the dram structs better
On Thu, Feb 27, 2020 at 04:53:59PM +0200, Jani Nikula wrote:
> Finish the job started in d28ae3b28187 ("drm/i915: split out
> intel_dram.[ch] from i915_drv.c") by moving struct dram_dimm_info and
> dram_channel_info inside intel_dram.c, the only user of the structs.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10 --
> drivers/gpu/drm/i915/intel_dram.c | 10 ++
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ea13fc0b409b..c5a06f864123 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1274,16 +1274,6 @@ struct drm_i915_private {
>*/
> };
>
> -struct dram_dimm_info {
> - u8 size, width, ranks;
> -};
> -
> -struct dram_channel_info {
> - struct dram_dimm_info dimm_l, dimm_s;
> - u8 ranks;
> - bool is_16gb_dimm;
> -};
> -
> static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
> {
> return container_of(dev, struct drm_i915_private, drm);
> diff --git a/drivers/gpu/drm/i915/intel_dram.c
> b/drivers/gpu/drm/i915/intel_dram.c
> index 9bb9dd724d3f..6b922efb1d7c 100644
> --- a/drivers/gpu/drm/i915/intel_dram.c
> +++ b/drivers/gpu/drm/i915/intel_dram.c
> @@ -6,6 +6,16 @@
> #include "i915_drv.h"
> #include "intel_dram.h"
>
> +struct dram_dimm_info {
> + u8 size, width, ranks;
> +};
> +
> +struct dram_channel_info {
> + struct dram_dimm_info dimm_l, dimm_s;
> + u8 ranks;
> + bool is_16gb_dimm;
> +};
> +
> #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
>
> static const char *intel_dram_type_str(enum intel_dram_type type)
> --
> 2.20.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH v2 16/20] drm/i915: Move pipe ddb entries into the dbuf state
From: Ville Syrjälä
The dbuf state will be where we collect all the inter-pipe dbuf
allocation stuff. Start by moving the actual per-pipe ddb entries
there.
v2: Rebase
Cc: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++
.../drm/i915/display/intel_display_types.h| 1 -
drivers/gpu/drm/i915/intel_pm.c | 16 ---
drivers/gpu/drm/i915/intel_pm.h | 4 +++
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a185b9e25cc3..9c6b9cebe8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15303,6 +15303,10 @@ static void intel_update_trans_port_sync_crtcs(struct
intel_crtc *crtc,
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_dbuf_state *old_dbuf_state =
+ intel_atomic_get_old_dbuf_state(state);
+ const struct intel_dbuf_state *new_dbuf_state =
+ intel_atomic_get_new_dbuf_state(state);
struct intel_crtc *crtc;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
@@ -15317,7 +15321,7 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
/* ignore allocations for crtc's that have been turned off. */
if (!needs_modeset(new_crtc_state)) {
- entries[pipe] = old_crtc_state->wm.skl.ddb;
+ entries[pipe] = old_dbuf_state->ddb[pipe];
update_pipes |= BIT(pipe);
} else {
modeset_pipes |= BIT(pipe);
@@ -15341,11 +15345,11 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
if ((update_pipes & BIT(pipe)) == 0)
continue;
- if
(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
+ if
(skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
entries,
I915_MAX_PIPES, pipe))
continue;
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
update_pipes &= ~BIT(pipe);
intel_update_crtc(crtc, state, old_crtc_state,
@@ -15357,8 +15361,8 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
* then we need to wait for a vblank to pass for the
* new ddb allocation to take effect.
*/
- if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
-&old_crtc_state->wm.skl.ddb) &&
+ if (!skl_ddb_entry_equal(&new_dbuf_state->ddb[pipe],
+&old_dbuf_state->ddb[pipe]) &&
(update_pipes | modeset_pipes))
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -15379,10 +15383,11 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
is_trans_port_sync_slave(new_crtc_state))
continue;
- drm_WARN_ON(&dev_priv->drm,
skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
-
entries, I915_MAX_PIPES, pipe));
+ drm_WARN_ON(&dev_priv->drm,
+
skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
+ entries,
I915_MAX_PIPES, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
modeset_pipes &= ~BIT(pipe);
if (is_trans_port_sync_mode(new_crtc_state)) {
@@ -15414,10 +15419,11 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
if ((modeset_pipes & BIT(pipe)) == 0)
continue;
- drm_WARN_ON(&dev_priv->drm,
skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
-
entries, I915_MAX_PIPES, pipe));
+ drm_WARN_ON(&dev_priv->drm,
+
skl_ddb_allocation_overlaps(&new_dbuf_state->ddb[pipe],
+ entries,
I915_MAX_PIPES, pipe));
- entries[pipe] = new_crtc_state->wm.skl.ddb;
+ entries[pipe] = new_dbuf_state->ddb[pipe];
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: reintroduce wait on OA configuration completion
== Series Details ==
Series: drm/i915/perf: reintroduce wait on OA configuration completion
URL : https://patchwork.freedesktop.org/series/74014/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8019 -> Patchwork_16733
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/index.html
Known issues
Here are the changes found in Patchwork_16733 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111096] / [i915#323])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Possible fixes
* igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [DMESG-FAIL][3] ([fdo#112406]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-u}: [DMESG-FAIL][5] ([i915#1233]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [FAIL][7] ([i915#217]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
Participating hosts (47 -> 43)
--
Additional (3): fi-byt-n2820 fi-bdw-5557u fi-bwr-2160
Missing(7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
fi-kbl-x1275 fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_8019 -> Patchwork_16733
CI-20190529: 20190529
CI_DRM_8019: c1fc892b1456a3b2b7f11482e52a126cc3ebedba @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16733: 9c67fa7e5fe967c01adda295714d355192a01590 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9c67fa7e5fe9 drm/i915/perf: reintroduce wait on OA configuration completion
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16733/index.html
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Re: [Intel-gfx] [PATCH v4-CI] drm/i915/psr: Force PSR probe only after full initialization
On Thu, 27 Feb 2020, Ross Zwisler wrote:
> On Thu, Feb 27, 2020 at 03:18:26PM +0200, Jani Nikula wrote:
>> On Fri, 21 Feb 2020, José Roberto de Souza wrote:
>> > Commit 60c6a14b489b ("drm/i915/display: Force the state compute phase
>> > once to enable PSR") was forcing the state compute too earlier
>> > causing errors because not everything was initialized, so here
>> > moving to the end of i915_driver_modeset_probe() when the display is
>> > all initialized.
>>
>> Hmph, really not happy about the placement here. These are high level
>> functions, not a dumping ground for random feature specific hacks. :(
>
> Should we just revert
>
> 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable
> PSR")
>
> and try to land a fixed-up version in the next kernel cycle? The current
> state is that my machine is completely unable to boot because of this issue,
> and I've confirmed that the above patch reverts cleanly and fixes the issue.
IIUC this patch, already committed as df1a5bfc16f3 ("drm/i915/psr: Force
PSR probe only after full initialization"), fixes the issue for you. At
least the Tested-by says so. ;) So we should just go with that.
I'm just being grumpy about the aesthetics of the implementation. I've
already incorporated some cleanup to this in an existing refactoring I
had [1].
BR,
Jani.
[1]
http://patchwork.freedesktop.org/patch/msgid/20200227135839.12912-1-jani.nik...@intel.com
--
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: split intel_modeset_init() pre/post gem init
== Series Details == Series: series starting with [1/3] drm/i915: split intel_modeset_init() pre/post gem init URL : https://patchwork.freedesktop.org/series/74021/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1f41c9f2b641 drm/i915: split intel_modeset_init() pre/post gem init fadf0879c983 drm/i915: move more display related probe/remove stuff to display b7f49adab789 drm/i915: remove the now redundant i915_driver_modeset_* call layer -:96: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #96: FILE: drivers/gpu/drm/i915/i915_drv.c:891: +* working irqs for e.g. gmbus and dp aux transfers. */ total: 0 errors, 1 warnings, 0 checks, 111 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: add i915_ioc32.h for compat
Keep reducing i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/i915_drv.h | 5 -
drivers/gpu/drm/i915/i915_ioc32.c | 6 --
drivers/gpu/drm/i915/i915_ioc32.h | 17 +
4 files changed, 23 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_ioc32.h
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b086132df1b7..45739c5d25eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -70,6 +70,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_ioc32.h"
#include "i915_irq.h"
#include "i915_memcpy.h"
#include "i915_perf.h"
@@ -1762,7 +1763,7 @@ static const struct file_operations i915_driver_fops = {
.mmap = i915_gem_mmap,
.poll = drm_poll,
.read = drm_read,
- .compat_ioctl = i915_compat_ioctl,
+ .compat_ioctl = i915_ioc32_compat_ioctl,
.llseek = noop_llseek,
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea13fc0b409b..ba523350cb9a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1737,11 +1737,6 @@ intel_ggtt_update_needs_vtd_wa(struct drm_i915_private
*dev_priv)
}
/* i915_drv.c */
-#ifdef CONFIG_COMPAT
-long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
-#else
-#define i915_compat_ioctl NULL
-#endif
extern const struct dev_pm_ops i915_pm_ops;
int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
diff --git a/drivers/gpu/drm/i915/i915_ioc32.c
b/drivers/gpu/drm/i915/i915_ioc32.c
index df7d19bd9b3a..8e45ca3d2ede 100644
--- a/drivers/gpu/drm/i915/i915_ioc32.c
+++ b/drivers/gpu/drm/i915/i915_ioc32.c
@@ -29,7 +29,9 @@
#include
#include
+
#include "i915_drv.h"
+#include "i915_ioc32.h"
struct drm_i915_getparam32 {
s32 param;
@@ -66,7 +68,7 @@ static drm_ioctl_compat_t *i915_compat_ioctls[] = {
};
/**
- * i915_compat_ioctl - handle the mistakes of the past
+ * i915_ioc32_compat_ioctl - handle the mistakes of the past
* @filp: the file pointer
* @cmd: the ioctl command (and encoded flags)
* @arg: the ioctl argument (from userspace)
@@ -74,7 +76,7 @@ static drm_ioctl_compat_t *i915_compat_ioctls[] = {
* Called whenever a 32-bit process running under a 64-bit kernel
* performs an ioctl on /dev/dri/card.
*/
-long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+long i915_ioc32_compat_ioctl(struct file *filp, unsigned int cmd, unsigned
long arg)
{
unsigned int nr = DRM_IOCTL_NR(cmd);
drm_ioctl_compat_t *fn = NULL;
diff --git a/drivers/gpu/drm/i915/i915_ioc32.h
b/drivers/gpu/drm/i915/i915_ioc32.h
new file mode 100644
index ..40dcd55ca213
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_ioc32.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __I915_IOC32_H__
+#define __I915_IOC32_H__
+
+#ifdef CONFIG_COMPAT
+struct file;
+long i915_ioc32_compat_ioctl(struct file *filp, unsigned int cmd,
+unsigned long arg);
+#else
+#define i915_ioc32_compat_ioctl NULL
+#endif
+
+#endif /* __I915_IOC32_H__ */
--
2.20.1
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[Intel-gfx] [PATCH 3/3] drm/i915: move watermark structs more towards usage
Shrink i915_drv.h a bit by moving watermark structs where they are
needed.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_types.h| 16
drivers/gpu/drm/i915/i915_drv.h | 40 ---
drivers/gpu/drm/i915/intel_pm.c | 24 +++
3 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0a06043d4d4c..2b357ca60454 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -641,6 +641,14 @@ struct intel_crtc_scaler_state {
/* Flag to use the scanline counter instead of the pixel counter */
#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
+struct intel_wm_level {
+ bool enable;
+ u32 pri_val;
+ u32 spr_val;
+ u32 cur_val;
+ u32 fbc_val;
+};
+
struct intel_pipe_wm {
struct intel_wm_level wm[5];
bool fbc_wm_enabled;
@@ -649,6 +657,14 @@ struct intel_pipe_wm {
bool sprites_scaled;
};
+struct skl_wm_level {
+ u16 min_ddb_alloc;
+ u16 plane_res_b;
+ u8 plane_res_l;
+ bool plane_en;
+ bool ignore_lines;
+};
+
struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 714d564ba900..2e33dc8b4495 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -59,7 +59,6 @@
#include
#include
-#include "i915_fixed.h"
#include "i915_params.h"
#include "i915_reg.h"
#include "i915_utils.h"
@@ -732,14 +731,6 @@ enum intel_ddb_partitioning {
INTEL_DDB_PART_5_6, /* IVB+ */
};
-struct intel_wm_level {
- bool enable;
- u32 pri_val;
- u32 spr_val;
- u32 cur_val;
- u32 fbc_val;
-};
-
struct ilk_wm_values {
u32 wm_pipe[3];
u32 wm_lp[3];
@@ -798,30 +789,6 @@ static inline bool skl_ddb_entry_equal(const struct
skl_ddb_entry *e1,
return false;
}
-struct skl_wm_level {
- u16 min_ddb_alloc;
- u16 plane_res_b;
- u8 plane_res_l;
- bool plane_en;
- bool ignore_lines;
-};
-
-/* Stores plane specific WM parameters */
-struct skl_wm_params {
- bool x_tiled, y_tiled;
- bool rc_surface;
- bool is_planar;
- u32 width;
- u8 cpp;
- u32 plane_pixel_rate;
- u32 y_min_scanlines;
- u32 plane_bytes_per_line;
- uint_fixed_16_16_t plane_blocks_per_line;
- uint_fixed_16_16_t y_tile_minimum;
- u32 linetime_us;
- u32 dbuf_block_size;
-};
-
enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_NONE,
INTEL_PIPE_CRC_SOURCE_PLANE1,
@@ -865,13 +832,6 @@ struct i915_virtual_gpu {
u32 caps;
};
-/* used in computing the new watermarks state */
-struct intel_wm_config {
- unsigned int num_pipes_active;
- bool sprites_enabled;
- bool sprites_scaled;
-};
-
struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22aa205793e5..033a790b3b85 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -40,12 +40,36 @@
#include "gt/intel_llc.h"
#include "i915_drv.h"
+#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
+/* Stores plane specific WM parameters */
+struct skl_wm_params {
+ bool x_tiled, y_tiled;
+ bool rc_surface;
+ bool is_planar;
+ u32 width;
+ u8 cpp;
+ u32 plane_pixel_rate;
+ u32 y_min_scanlines;
+ u32 plane_bytes_per_line;
+ uint_fixed_16_16_t plane_blocks_per_line;
+ uint_fixed_16_16_t y_tile_minimum;
+ u32 linetime_us;
+ u32 dbuf_block_size;
+};
+
+/* used in computing the new watermarks state */
+struct intel_wm_config {
+ unsigned int num_pipes_active;
+ bool sprites_enabled;
+ bool sprites_scaled;
+};
+
static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
{
if (HAS_LLC(dev_priv)) {
--
2.20.1
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[Intel-gfx] [PATCH 2/3] drm/i915: remove unused orig_clock i915 member
Unused since commit f97108d1d0fa ("drm/i915: add dynamic performance
control support for Ironlake"). That's a little over ten years. Good
riddance.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ba523350cb9a..714d564ba900 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1078,8 +1078,6 @@ struct drm_i915_private {
struct work_struct free_work;
} atomic_helper;
- u16 orig_clock;
-
bool mchbar_need_disable;
struct intel_l3_parity l3_parity;
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915/perf: reintroduce wait on OA configuration completion
Quoting Lionel Landwerlin (2020-02-27 12:43:56) > We still need to wait for the initial OA configuration to happen > before we enable OA report writes to the OA buffer. I can confirm this fixes the hang Lionel reported on Skylake [still odd that we can only get this to be an issue on skl]. However, Lionel mentioned that we should be more careful and ensure the emit_oa_config() request is scheduled last. We're currently looking at different ways we can do that. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix kbuild test robot build error
On 2020-02-27 at 09:04:03 +0200, Jani Nikula wrote:
> On Thu, 27 Feb 2020, Anshuman Gupta wrote:
> > Fix kbuild test robot build error for below commit
> > .
>
> The proper format to reference other commits is
>
> d54c1a513c48 ("drm/i915: Fix broken transcoder err state")
>
> If you put this magic spell in your ~/.gitconfig under [alias]:
>
> cite = "!f() { git log -1 '--pretty=format:%H (\"%s\")%n' $1 | sed -e
> 's/\\([0-f]\\{12\\}\\)[0-f]*/\\1/'; }; f"
>
> you can use 'git cite ' to give you the properly formatted
> citation.
Thanks Jani for the info.
>
> > has_transcoder() was unused because function which was using it
> > intel_display_capture_error_state() defined under
> > CONFIG_DRM_I915_CAPTURE_ERROR.
> > Moving has_transcoder() to under CONFIG_DRM_I915_CAPTURE_ERROR.
> > No functional change.
> >
> > Cc: Ville Syrjälä
> > Reported-by: kbuild test robot
> > Signed-off-by: Anshuman Gupta
>
> Fixes: d54c1a513c48 ("drm/i915: Fix broken transcoder err state")
I will incorporate above citation in commit log.
> Reviewed-by: Jani Nikula
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 18 +-
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2fd3ccd33e30..27ec245e0dd2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -249,15 +249,6 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv,
> > return dev_priv->fdi_pll_freq;
> > }
> >
> > -static bool
> > -has_transcoder(struct drm_i915_private *dev_priv, enum transcoder
> > cpu_transcoder)
> > -{
> > - if (cpu_transcoder == TRANSCODER_EDP)
> > - return HAS_TRANSCODER_EDP(dev_priv);
> > - else
> > - return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder);
> > -}
> > -
> > static const struct intel_limit intel_limits_i8xx_dac = {
> > .dot = { .min = 25000, .max = 35 },
> > .vco = { .min = 908000, .max = 1512000 },
> > @@ -18838,6 +18829,15 @@ void intel_modeset_driver_remove_noirq(struct
> > drm_i915_private *i915)
> >
> > #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
> >
> > +static bool
> > +has_transcoder(struct drm_i915_private *dev_priv, enum transcoder
> > cpu_transcoder)
> > +{
> > + if (cpu_transcoder == TRANSCODER_EDP)
> > + return HAS_TRANSCODER_EDP(dev_priv);
> > + else
> > + return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder);
> > +}
> > +
> > struct intel_display_error_state {
> >
> > u32 power_well_driver;
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: split intel_modeset_init() pre/post gem init
== Series Details == Series: series starting with [1/3] drm/i915: split intel_modeset_init() pre/post gem init URL : https://patchwork.freedesktop.org/series/74021/ State : success == Summary == CI Bug Log - changes from CI_DRM_8019 -> Patchwork_16734 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/index.html Known issues Here are the changes found in Patchwork_16734 that come from known issues: ### IGT changes ### Issues hit * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111407]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([i915#44]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-bxt-dsi: [DMESG-FAIL][5] ([fdo#112406]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [FAIL][7] ([i915#217]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8019/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44 Participating hosts (47 -> 43) -- Additional (2): fi-bdw-5557u fi-bwr-2160 Missing(6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_8019 -> Patchwork_16734 CI-20190529: 20190529 CI_DRM_8019: c1fc892b1456a3b2b7f11482e52a126cc3ebedba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16734: b7f49adab789477c1776c5c043e224d57c0c45bd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b7f49adab789 drm/i915: remove the now redundant i915_driver_modeset_* call layer fadf0879c983 drm/i915: move more display related probe/remove stuff to display 1f41c9f2b641 drm/i915: split intel_modeset_init() pre/post gem init == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16734/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/51] drm/: Use drmm_add_final_kfree
On Sat, Feb 22, 2020 at 03:16:24PM +, Russell King - ARM Linux admin wrote: > On Fri, Feb 21, 2020 at 10:02:46PM +0100, Daniel Vetter wrote: > > These are the leftover drivers that didn't have a ->release hook that > > needed to be updated. > > > > Signed-off-by: Daniel Vetter > > Cc: "James (Qian) Wang" > > Cc: Liviu Dudau > > Cc: Mihail Atanassov > > Cc: Russell King > > Cc: Hans de Goede > > --- > > drivers/gpu/drm/arm/display/komeda/komeda_kms.c | 2 ++ > > drivers/gpu/drm/armada/armada_drv.c | 2 ++ > > drivers/gpu/drm/vboxvideo/vbox_drv.c| 2 ++ > > 3 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/armada/armada_drv.c > > b/drivers/gpu/drm/armada/armada_drv.c > > index 197dca3fc84c..dd9ed71ed942 100644 > > --- a/drivers/gpu/drm/armada/armada_drv.c > > +++ b/drivers/gpu/drm/armada/armada_drv.c > > @@ -12,6 +12,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -103,6 +104,7 @@ static int armada_drm_bind(struct device *dev) > > kfree(priv); > > return ret; > > } > > + drmm_add_final_kfree(&priv->drm, priv); > > > > /* Remove early framebuffers */ > > ret = drm_fb_helper_remove_conflicting_framebuffers(NULL, > > I have no visibility of what the changes behind this are, so I > can't ack this change. dri-devel is on lore, you can grab the entire thread there with the new tooling that's being discussed on ksummit-discuss. I can't cc everyone on the entire thread for big changes like this because many smtp servers reject your mail with more than about 25 recipients. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/selftests: Disable heartbeat around manual pulse tests
== Series Details == Series: drm/i915/selftests: Disable heartbeat around manual pulse tests URL : https://patchwork.freedesktop.org/series/73958/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8010_full -> Patchwork_16718_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_16718_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16718_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_16718_full: ### IGT changes ### Possible regressions * igt@gem_exec_await@wide-contexts: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl6/igt@gem_exec_aw...@wide-contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-skl1/igt@gem_exec_aw...@wide-contexts.html Known issues Here are the changes found in Patchwork_16718_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@close-race: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#977]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-tglb1/igt@gem_b...@close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-tglb8/igt@gem_b...@close-race.html * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb4/igt@gem_b...@extended-parallel-vcs1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-iclb8/igt@gem_b...@extended-parallel-vcs1.html * igt@gem_ctx_persistence@close-replace-race: - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([fdo#103665] / [i915#1291]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-kbl2/igt@gem_ctx_persiste...@close-replace-race.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-kbl7/igt@gem_ctx_persiste...@close-replace-race.html * igt@gem_exec_balancer@hang: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#1277]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-tglb5/igt@gem_exec_balan...@hang.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-tglb2/igt@gem_exec_balan...@hang.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276] / [i915#677]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb1/igt@gem_exec_sched...@implicit-both-bsd2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-iclb6/igt@gem_exec_sched...@implicit-both-bsd2.html * igt@gem_exec_schedule@independent-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb3/igt@gem_exec_sched...@independent-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-iclb4/igt@gem_exec_sched...@independent-bsd.html * igt@gem_exec_schedule@pi-shared-iova-bsd: - shard-iclb: [PASS][15] -> [SKIP][16] ([i915#677]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb8/igt@gem_exec_sched...@pi-shared-iova-bsd.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-iclb4/igt@gem_exec_sched...@pi-shared-iova-bsd.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [PASS][17] -> [FAIL][18] ([i915#644]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-apl3/igt@gem_pp...@flink-and-close-vma-leak.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-apl4/igt@gem_pp...@flink-and-close-vma-leak.html - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#644]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-kbl3/igt@gem_pp...@flink-and-close-vma-leak.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-kbl7/igt@gem_pp...@flink-and-close-vma-leak.html * igt@gem_softpin@noreloc-s3: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#109100]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-iclb6/igt@gem_soft...@noreloc-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16718/shard-iclb3/igt@gem_soft...@noreloc-s3.html * igt@i915_selftest@live_active: - shard-skl: [PASS][23] -> [DMESG-FAIL][24] ([i915#666]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8010/shard-skl10/igt@i915_selftest@live_active.htm
Re: [Intel-gfx] [PATCH 12/13] drm/i915/hsw: Use the read-out WRPLL/SPLL state instead of reading out again
On Wed, Feb 26, 2020 at 10:34:54PM +0200, Imre Deak wrote:
> Instead of reading out the WRPLL/SPLL control values from HW, we can use
> the DPLL state that was already read out, or swapped-to.
>
> Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++-
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b87b4ff5de52..7e6da58a47c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> const struct intel_shared_dpll *pll)
> {
> - i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ?
> - WRPLL_CTL(0) : WRPLL_CTL(1);
> int refclk;
> int n, p, r;
> - u32 wrpll;
> + u32 wrpll = pll->state.hw_state.wrpll;
>
> - wrpll = intel_de_read(dev_priv, reg);
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> /*
> @@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct
> drm_i915_private *i915,
> {
> int link_clock = 0;
>
> - switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) {
> + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) {
> case SPLL_FREQ_810MHz:
> link_clock = 81000;
> break;
> --
> 2.23.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 11/13] drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
On Wed, Feb 26, 2020 at 10:34:53PM +0200, Imre Deak wrote:
> Split out the PLL parameter->frequency conversion logic for each type of
> PLL for symmetry with their corresponding inverse conversion functions.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 269 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 8 +-
> 4 files changed, 140 insertions(+), 145 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c38addd07e42..17cee6f80d8b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct
> intel_encoder *encoder,
> static void gen11_dsi_get_config(struct intel_encoder *encoder,
>struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>
> intel_dsc_get_config(encoder, pipe_config);
>
> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> - pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
> + pipe_config->port_clock = intel_dpll_get_freq(i915,
> + pipe_config->shared_dpll);
For this one I'm thinking it might be better to pass the pll state
instead. That way we could use this function already before we've
actually committed the state.
We can think about that later though.
Patches 1-11 look OK to me:
Reviewed-by: Ville Syrjälä
>
> pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
> if (intel_dsi->dual_link)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 5e6f81b140d4..284219da7df8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder
> *encoder,
> pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
> encoder->port);
> else
> - pipe_config->port_clock = intel_dpll_get_freq(encoder,
> - pipe_config);
> + pipe_config->port_clock =
> + intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
>
> ddi_dotclock_get(pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ebd55fdaf4cd..b87b4ff5de52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state
> *state,
> return true;
> }
>
> -static int hsw_ddi_clock_get(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_shared_dpll *pll = pipe_config->shared_dpll;
> -
> - switch (pll->info->id) {
> - case DPLL_ID_WRPLL1:
> - case DPLL_ID_WRPLL2:
> - return hsw_ddi_wrpll_get_freq(dev_priv, pll);
> - case DPLL_ID_SPLL:
> - return hsw_ddi_spll_get_freq(dev_priv, pll);
> - default:
> - return hsw_ddi_lcpll_get_freq(dev_priv, pll);
> - }
> -}
> -
> static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs
> hsw_ddi_wrpll_funcs = {
> .enable = hsw_ddi_wrpll_enable,
> .disable = hsw_ddi_wrpll_disable,
> .get_hw_state = hsw_ddi_wrpll_get_hw_state,
> + .get_freq = hsw_ddi_wrpll_get_freq,
> };
>
> static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
> .enable = hsw_ddi_spll_enable,
> .disable = hsw_ddi_spll_disable,
> .get_hw_state = hsw_ddi_spll_get_hw_state,
> + .get_freq = hsw_ddi_spll_get_freq,
> };
>
> static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
> @@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs
> hsw_ddi_lcpll_funcs = {
> .enable = hsw_ddi_lcpll_enable,
> .disable = hsw_ddi_lcpll_disable,
> .get_hw_state = hsw_ddi_lcpll_get_hw_state,
> + .get_freq = hsw_ddi_lcpll_get_freq,
> };
>
> static const struct dpll_info hsw_plls[] = {
> @@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct
> intel_crtc_state *crtc_state)
> return true;
> }
>
> -static int skl_calc_
[Intel-gfx] [PATCH] drm/i915: Fix kbuild test robot build error
Fixes: d54c1a513c48 ("drm/i915: Fix broken transcoder err state")
has_transcoder() was unused because function which was using it,
intel_display_capture_error_state() defined under
CONFIG_DRM_I915_CAPTURE_ERROR.
Moving has_transcoder() to under CONFIG_DRM_I915_CAPTURE_ERROR.
No functional change.
Cc: Ville Syrjälä
Reported-by: kbuild test robot
Reviewed-by: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2fd3ccd33e30..27ec245e0dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -249,15 +249,6 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv,
return dev_priv->fdi_pll_freq;
}
-static bool
-has_transcoder(struct drm_i915_private *dev_priv, enum transcoder
cpu_transcoder)
-{
- if (cpu_transcoder == TRANSCODER_EDP)
- return HAS_TRANSCODER_EDP(dev_priv);
- else
- return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder);
-}
-
static const struct intel_limit intel_limits_i8xx_dac = {
.dot = { .min = 25000, .max = 35 },
.vco = { .min = 908000, .max = 1512000 },
@@ -18838,6 +18829,15 @@ void intel_modeset_driver_remove_noirq(struct
drm_i915_private *i915)
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+static bool
+has_transcoder(struct drm_i915_private *dev_priv, enum transcoder
cpu_transcoder)
+{
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return HAS_TRANSCODER_EDP(dev_priv);
+ else
+ return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder);
+}
+
struct intel_display_error_state {
u32 power_well_driver;
--
2.25.1
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/vgpu: improve vgpu abstractions
== Series Details == Series: series starting with [1/3] drm/i915/vgpu: improve vgpu abstractions URL : https://patchwork.freedesktop.org/series/74024/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/vgpu: improve vgpu abstractions Okay! Commit: drm/i915/gvt: make intel_gvt_active internal to intel_gvt Okay! Commit: drm/i915/gvt: only include intel_gvt.h where needed +drivers/gpu/drm/i915/gvt/gvt.c:264:6: warning: symbol 'intel_gvt_clean_device' was not declared. Should it be static? +drivers/gpu/drm/i915/gvt/gvt.c:301:5: warning: symbol 'intel_gvt_init_device' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 13/13] drm/i915: Unify the DPLL ref clock frequency tracking
On Wed, Feb 26, 2020 at 10:34:55PM +0200, Imre Deak wrote:
> All platforms using the shared DPLL framework use 3 reference clocks for
> their DPLLs: SSC, non-SSC and DSI. For a more unified way across
> platforms store the frequency of these ref clocks as part of the DPLL
> global state. This also allows us to keep the HW access reading out the
> ref clock value separate from the DPLL frequency calculation that
> depends on the ref clock.
>
> For now add only the SSC and non-SSC ref clocks, as the pre-ICL DSI code
> has its own logic for calculating DPLL parameters instead of the shared
> DPLL framework.
>
> Signed-off-by: Imre Deak
> ---
> .../drm/i915/display/intel_display_debugfs.c | 5 +
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 132 +++---
> drivers/gpu/drm/i915/i915_drv.h | 5 +
> 3 files changed, 95 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d2461d7946bf..6675b7e34f0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -920,6 +920,11 @@ static int i915_shared_dplls_info(struct seq_file *m,
> void *unused)
> int i;
>
> drm_modeset_lock_all(dev);
> +
> + seq_printf(m, "PLL refclks: non-SSC: %d kHZ, SSC: %d kHZ\n",
nit: "kHz"
> +dev_priv->dpll.ref_clks.nssc,
> +dev_priv->dpll.ref_clks.ssc);
> +
> for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
> struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 7e6da58a47c9..44db46782770 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -56,6 +56,7 @@ struct intel_dpll_mgr {
> void (*update_active_dpll)(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> struct intel_encoder *encoder);
> + void (*update_ref_clks)(struct drm_i915_private *i915);
> void (*dump_hw_state)(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state);
> };
> @@ -886,16 +887,9 @@ static int hsw_ddi_wrpll_get_freq(struct
> drm_i915_private *dev_priv,
>
> switch (wrpll & WRPLL_REF_MASK) {
> case WRPLL_REF_SPECIAL_HSW:
> - /*
> - * muxed-SSC for BDW.
> - * non-SSC for non-ULT HSW. Check FUSE_STRAP3
> - * for the non-SSC reference frequency.
> - */
> + /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
> if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
> - if (intel_de_read(dev_priv, FUSE_STRAP3) &
> HSW_REF_CLK_SELECT)
> - refclk = 24;
> - else
> - refclk = 135;
> + refclk = dev_priv->dpll.ref_clks.nssc;
> break;
> }
> /* fall through */
> @@ -905,10 +899,10 @@ static int hsw_ddi_wrpll_get_freq(struct
> drm_i915_private *dev_priv,
>* code only cares about 5% accuracy, and spread is a max of
>* 0.5% downspread.
>*/
> - refclk = 135;
> + refclk = dev_priv->dpll.ref_clks.ssc;
> break;
> case WRPLL_REF_LCPLL:
> - refclk = 2700;
> + refclk = 270;
> break;
> default:
> MISSING_CASE(wrpll);
> @@ -920,7 +914,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private
> *dev_priv,
> n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
>
> /* Convert to KHz, p & r have a fixed point portion */
> - return (refclk * n * 100) / (p * r) * 2;
> + return (refclk * n / 10) / (p * r) * 2;
> }
>
> static struct intel_shared_dpll *
> @@ -1049,6 +1043,16 @@ static bool hsw_get_dpll(struct intel_atomic_state
> *state,
> return true;
> }
>
> +static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> +{
> + i915->dpll.ref_clks.ssc = 135000;
> + /* Non-SSC is only used on non-ULT HSW. */
> + if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> + i915->dpll.ref_clks.nssc = 24000;
> + else
> + i915->dpll.ref_clks.nssc = 135000;
I couldn't remember whether the PCH and CPU SSC references have the same
frquency. But looks like they do.
> +}
> +
> static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
> const struct intel_dpll_hw_state *hw_state)
> {
> @@ -1108,6 +1112,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
> .dpll_info = hsw_plls,
> .get_dplls = hsw_get_dpll
[Intel-gfx] [PATCH 01/51] mm/sl[uo]b: export __kmalloc_track(_node)_caller
slab does this already, and I want to use this in a memory allocation
tracker in drm for stuff that's tied to the lifetime of a drm_device,
not the underlying struct device. Kinda like devres, but for drm.
Acked-by: Andrew Morton
Signed-off-by: Daniel Vetter
Cc: Christoph Lameter
Cc: Pekka Enberg
Cc: David Rientjes
Cc: Joonsoo Kim
Cc: Andrew Morton
Cc: linux...@kvack.org
--
I plan to merge this through drm-misc-next (with Andrew's ack) once
the remainder of the drm series is in shape.
-Daniel
---
mm/slob.c | 2 ++
mm/slub.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/mm/slob.c b/mm/slob.c
index fa53e9f73893..ac2aecfbc7a8 100644
--- a/mm/slob.c
+++ b/mm/slob.c
@@ -524,6 +524,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t gfp,
unsigned long caller)
{
return __do_kmalloc_node(size, gfp, NUMA_NO_NODE, caller);
}
+EXPORT_SYMBOL(__kmalloc_track_caller);
#ifdef CONFIG_NUMA
void *__kmalloc_node_track_caller(size_t size, gfp_t gfp,
@@ -531,6 +532,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t gfp,
{
return __do_kmalloc_node(size, gfp, node, caller);
}
+EXPORT_SYMBOL(__kmalloc_node_track_caller);
#endif
void kfree(const void *block)
diff --git a/mm/slub.c b/mm/slub.c
index be2854b5b1c9..7271fb235ed8 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -4358,6 +4358,7 @@ void *__kmalloc_track_caller(size_t size, gfp_t gfpflags,
unsigned long caller)
return ret;
}
+EXPORT_SYMBOL(__kmalloc_track_caller);
#ifdef CONFIG_NUMA
void *__kmalloc_node_track_caller(size_t size, gfp_t gfpflags,
@@ -4388,6 +4389,7 @@ void *__kmalloc_node_track_caller(size_t size, gfp_t
gfpflags,
return ret;
}
+EXPORT_SYMBOL(__kmalloc_node_track_caller);
#endif
#ifdef CONFIG_SYSFS
--
2.24.1
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[Intel-gfx] [PATCH 00/51] drm managed resources, v3
Hi all, Bunch more bugfixes (intel-gfx-ci wasn't fully happy yet, and justifiedly so) all over, bunch more acks/reviews. Still need a lot more review and acks. Recommended reading order is still to start with the doc patch at the end for the big picture, then the code changes in sequence. Also cc imx folks, they've realized that devm_kzalloc isn't a great idea the hard way. Cheers, Daniel Daniel Vetter (51): mm/sl[uo]b: export __kmalloc_track(_node)_caller drm/i915: Don't clear drvdata in ->release drm: add managed resources tied to drm_device drm: Set final_kfree in drm_dev_alloc drm/mipi_dbi: Use drmm_add_final_kfree in all drivers drm/udl: Use drmm_add_final_kfree drm/qxl: Use drmm_add_final_kfree drm/i915: Use drmm_add_final_kfree drm/cirrus: Use drmm_add_final_kfree drm/v3d: Use drmm_add_final_kfree drm/tidss: Use drmm_add_final_kfree drm/mcde: Use drmm_add_final_kfree drm/vgem: Use drmm_add_final_kfree drm/vkms: Use drmm_add_final_kfree drm/repaper: Use drmm_add_final_kfree drm/inigenic: Use drmm_add_final_kfree drm/gm12u320: Use drmm_add_final_kfree drm/: Use drmm_add_final_kfree drm: Cleanups after drmm_add_final_kfree rollout drm: Handle dev->unique with drmm_ drm: Use drmm_ for drm_dev_init cleanup drm: manage drm_minor cleanup with drmm_ drm: Manage drm_gem_init with drmm_ drm: Manage drm_vblank_cleanup with drmm_ drm: Garbage collect drm_dev_fini drm: Manage drm_mode_config_init with drmm_ drm/bochs: Remove leftover drm_atomic_helper_shutdown drm/bochs: Drop explicit drm_mode_config_cleanup drm/cirrus: Drop explicit drm_mode_config_cleanup call drm/cirrus: Fully embrace devm_ drm/ingenic: Drop explicit drm_mode_config_cleanup call drm/mcde: Drop explicit drm_mode_config_cleanup call drm/mcde: More devm_drm_dev_init drm/meson: Drop explicit drm_mode_config_cleanup call drm/pl111: Drop explicit drm_mode_config_cleanup call drm/rcar-du: Drop explicit drm_mode_config_cleanup call drm/rockchip: Drop explicit drm_mode_config_cleanup call drm/stm: Drop explicit drm_mode_config_cleanup call drm/shmob: Drop explicit drm_mode_config_cleanup call drm/mtk: Drop explicit drm_mode_config_cleanup call drm/tidss: Drop explicit drm_mode_config_cleanup call drm/gm12u320: More drmm_ drm/gm12u320: Use devm_drm_dev_init drm/gm12u320: Use helpers for shutdown/suspend/resume drm/gm12u320: Simplify upload work drm/repaper: Drop explicit drm_mode_config_cleanup call drm/mipi-dbi: Move drm_mode_config_init into mipi library drm/mipi-dbi: Drop explicit drm_mode_config_cleanup call drm/udl: Drop explicit drm_mode_config_cleanup call drm/udl: drop drm_driver.release hook drm: Add docs for managed resources Documentation/gpu/drm-internals.rst | 12 + drivers/gpu/drm/Makefile | 3 +- .../gpu/drm/arm/display/komeda/komeda_kms.c | 2 + drivers/gpu/drm/armada/armada_drv.c | 2 + drivers/gpu/drm/bochs/bochs.h | 1 - drivers/gpu/drm/bochs/bochs_drv.c | 6 +- drivers/gpu/drm/bochs/bochs_kms.c | 15 +- drivers/gpu/drm/cirrus/cirrus.c | 74 ++--- drivers/gpu/drm/drm_drv.c | 219 ++--- drivers/gpu/drm/drm_gem.c | 21 +- drivers/gpu/drm/drm_internal.h| 5 +- drivers/gpu/drm/drm_managed.c | 294 ++ drivers/gpu/drm/drm_mipi_dbi.c| 24 +- drivers/gpu/drm/drm_mode_config.c | 13 +- drivers/gpu/drm/drm_vblank.c | 31 +- drivers/gpu/drm/i915/i915_drv.c | 22 +- drivers/gpu/drm/i915/i915_drv.h | 3 + .../gpu/drm/i915/selftests/mock_gem_device.c | 33 +- drivers/gpu/drm/ingenic/ingenic-drm.c | 17 +- drivers/gpu/drm/mcde/mcde_drv.c | 35 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.c| 9 +- drivers/gpu/drm/meson/meson_drv.c | 5 +- drivers/gpu/drm/pl111/pl111_drv.c | 12 +- drivers/gpu/drm/qxl/qxl_drv.c | 2 - drivers/gpu/drm/qxl/qxl_kms.c | 2 + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 1 - drivers/gpu/drm/rcar-du/rcar_du_kms.c | 4 +- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 12 +- drivers/gpu/drm/shmobile/shmob_drm_drv.c | 2 - drivers/gpu/drm/shmobile/shmob_drm_kms.c | 6 +- drivers/gpu/drm/stm/drv.c | 10 +- drivers/gpu/drm/tidss/tidss_drv.c | 10 +- drivers/gpu/drm/tidss/tidss_kms.c | 19 +- drivers/gpu/drm/tidss/tidss_kms.h | 1 - drivers/gpu/drm/tiny/gm12u320.c | 226 +- drivers/gpu/drm/tiny/hx8357d.c| 5 +- drivers/gpu/drm/tiny/ili9225.c| 5 +- drivers/gpu/drm/tiny/ili9341.c| 5 +- drivers/gpu/drm/tiny/ili9486.c| 5 +- drivers/gpu/drm/tiny/mi0283qt.c
[Intel-gfx] [PATCH 10/51] drm/v3d: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function.
I also noticed that the unwind code is wrong, after drm_dev_init the
drm_device owns the v3d allocation, so the kfree(v3d) is a double-free.
Reorder the setup to fix this issue.
After a bit more prep in drivers and drm core v3d should be able to
switch over to devm_drm_dev_init, which should clean this up further.
Acked-by: Eric Anholt
Signed-off-by: Daniel Vetter
Cc: Eric Anholt
---
drivers/gpu/drm/v3d/v3d_drv.c | 38 ++-
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c
index eaa8e9682373..8d0c0daaac81 100644
--- a/drivers/gpu/drm/v3d/v3d_drv.c
+++ b/drivers/gpu/drm/v3d/v3d_drv.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include "v3d_drv.h"
@@ -257,13 +258,23 @@ static int v3d_platform_drm_probe(struct platform_device
*pdev)
v3d->pdev = pdev;
drm = &v3d->drm;
+ ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
+ if (ret) {
+ kfree(v3d);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, drm);
+ drm->dev_private = v3d;
+ drmm_add_final_kfree(drm, v3d);
+
ret = map_regs(v3d, &v3d->hub_regs, "hub");
if (ret)
- goto dev_free;
+ goto dev_destroy;
ret = map_regs(v3d, &v3d->core_regs[0], "core0");
if (ret)
- goto dev_free;
+ goto dev_destroy;
mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
dev->coherent_dma_mask =
@@ -281,21 +292,21 @@ static int v3d_platform_drm_probe(struct platform_device
*pdev)
ret = PTR_ERR(v3d->reset);
if (ret == -EPROBE_DEFER)
- goto dev_free;
+ goto dev_destroy;
v3d->reset = NULL;
ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
if (ret) {
dev_err(dev,
"Failed to get reset control or bridge regs\n");
- goto dev_free;
+ goto dev_destroy;
}
}
if (v3d->ver < 41) {
ret = map_regs(v3d, &v3d->gca_regs, "gca");
if (ret)
- goto dev_free;
+ goto dev_destroy;
}
v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
@@ -303,23 +314,16 @@ static int v3d_platform_drm_probe(struct platform_device
*pdev)
if (!v3d->mmu_scratch) {
dev_err(dev, "Failed to allocate MMU scratch page\n");
ret = -ENOMEM;
- goto dev_free;
+ goto dev_destroy;
}
pm_runtime_use_autosuspend(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_enable(dev);
- ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
- if (ret)
- goto dma_free;
-
- platform_set_drvdata(pdev, drm);
- drm->dev_private = v3d;
-
ret = v3d_gem_init(drm);
if (ret)
- goto dev_destroy;
+ goto dma_free;
ret = v3d_irq_init(v3d);
if (ret)
@@ -335,12 +339,10 @@ static int v3d_platform_drm_probe(struct platform_device
*pdev)
v3d_irq_disable(v3d);
gem_destroy:
v3d_gem_destroy(drm);
-dev_destroy:
- drm_dev_put(drm);
dma_free:
dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
-dev_free:
- kfree(v3d);
+dev_destroy:
+ drm_dev_put(drm);
return ret;
}
--
2.24.1
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[Intel-gfx] [PATCH 02/51] drm/i915: Don't clear drvdata in ->release
For two reasons: - The driver core clears this already for us after we're unloaded in __device_release_driver(). - It's way too late, the drm_device ->release callback might massively outlive the underlying physical device, since a drm_device can't be kept alive by open drm_file or well really anything else userspace is still hanging onto. So if we clear this ourselves, we should clear it in the pci ->remove callback, not in the drm_device ->relase callback. Looking at git history this was fixed in the driver core with commit 0998d0631001288a5974afc0b2a5f568bcdecb4d Author: Hans de Goede Date: Wed May 23 00:09:34 2012 +0200 device-core: Ensure drvdata = NULL when no driver is bound v2: Cite the core fix in the commit message (Chris). Cc: Greg Kroah-Hartman Cc: Chris Wilson Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b086132df1b7..0b59a9bd2581 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -913,9 +913,6 @@ static void i915_driver_destroy(struct drm_i915_private *i915) drm_dev_fini(&i915->drm); kfree(i915); - - /* And make sure we never chase our dangling pointer from pci_dev */ - pci_set_drvdata(pdev, NULL); } /** -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/51] drm/mcde: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function. Reviewed-by: Linus Walleij Signed-off-by: Daniel Vetter Cc: Linus Walleij --- drivers/gpu/drm/mcde/mcde_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mcde/mcde_drv.c b/drivers/gpu/drm/mcde/mcde_drv.c index f28cb7a576ba..7474481503a1 100644 --- a/drivers/gpu/drm/mcde/mcde_drv.c +++ b/drivers/gpu/drm/mcde/mcde_drv.c @@ -72,6 +72,7 @@ #include #include #include +#include #include #include #include @@ -223,7 +224,6 @@ static void mcde_release(struct drm_device *drm) drm_mode_config_cleanup(drm); drm_dev_fini(drm); - kfree(mcde); } DEFINE_DRM_GEM_CMA_FOPS(drm_fops); @@ -330,6 +330,7 @@ static int mcde_probe(struct platform_device *pdev) } drm = &mcde->drm; drm->dev_private = mcde; + drmm_add_final_kfree(drm, mcde); platform_set_drvdata(pdev, drm); /* Enable continuous updates: this is what Linux' framebuffer expects */ -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/51] drm/gm12u320: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function. Reviewed-by: Hans de Goede Signed-off-by: Daniel Vetter Cc: Hans de Goede --- drivers/gpu/drm/tiny/gm12u320.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c index a48173441ae0..524ca0941cf9 100644 --- a/drivers/gpu/drm/tiny/gm12u320.c +++ b/drivers/gpu/drm/tiny/gm12u320.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -637,7 +638,6 @@ static void gm12u320_driver_release(struct drm_device *dev) gm12u320_usb_free(gm12u320); drm_mode_config_cleanup(dev); drm_dev_fini(dev); - kfree(gm12u320); } DEFINE_DRM_GEM_FOPS(gm12u320_fops); @@ -692,6 +692,7 @@ static int gm12u320_usb_probe(struct usb_interface *interface, return ret; } dev->dev_private = gm12u320; + drmm_add_final_kfree(dev, gm12u320); drm_mode_config_init(dev); dev->mode_config.min_width = GM12U320_USER_WIDTH; -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/51] drm/i915: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function.
The mock device in the selftests needed it's pci_device split
up from the drm_device. In the future we could simplify this again
by allocating the pci_device as a managed allocation too.
v2: I overlooked that i915_driver_destroy is also called in the
unwind code of the error path. There we need a drm_dev_put.
Similar for the mock object.
Now the problem with that is that the drm_driver->release callbacks
for both the real driver and the mock one assume everything has been
set up. Hence going through that path for a partially set up driver
will result in issues. Quickest fix is to disable the ->release() hook
until the driver is fully initialized, and keep the onion unwinding.
Long term would be cleanest to move everything over to drmm_ release
actions, but that's a lot of work for a big driver like i915. Plus
more core work needed first anyway.
v3: Fix i915_drm pointer wrangling in mock_gem_device. Also switch
over to start using drm_dev_put() to clean up even on the error path.
Aside I think the current error path is leaking the allocation.
Signed-off-by: Daniel Vetter
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Cc: Andi Shyti
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Cc: Daniel Vetter
Cc: Abdiel Janulgue
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 31 ++-
3 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0b59a9bd2581..4119e57b0c5b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -43,6 +43,7 @@
#include
#include
#include
+#include
#include
#include "display/intel_acpi.h"
@@ -894,6 +895,8 @@ i915_driver_create(struct pci_dev *pdev, const struct
pci_device_id *ent)
return ERR_PTR(err);
}
+ drmm_add_final_kfree(&i915->drm, i915);
+
i915->drm.pdev = pdev;
pci_set_drvdata(pdev, i915);
@@ -912,7 +915,6 @@ static void i915_driver_destroy(struct drm_i915_private
*i915)
struct pci_dev *pdev = i915->drm.pdev;
drm_dev_fini(&i915->drm);
- kfree(i915);
}
/**
@@ -996,6 +998,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
i915_welcome_messages(i915);
+ i915->do_release = true;
+
return 0;
out_cleanup_irq:
@@ -1016,6 +1020,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct
pci_device_id *ent)
out_fini:
i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
i915_driver_destroy(i915);
+ drm_dev_put(&i915->drm);
return ret;
}
@@ -1055,6 +1060,9 @@ static void i915_driver_release(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
+ if (!dev_priv->do_release)
+ return;
+
disable_rpm_wakeref_asserts(rpm);
i915_gem_driver_release(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ea13fc0b409b..31c40e35f497 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -884,6 +884,9 @@ struct i915_selftest_stash {
struct drm_i915_private {
struct drm_device drm;
+ /* FIXME: Device release actions should all be moved to drmm_ */
+ bool do_release;
+
const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
struct intel_driver_caps caps;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 754d0eb6beaa..c85bbc88f504 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -25,6 +25,8 @@
#include
#include
+#include
+
#include "gt/intel_gt.h"
#include "gt/intel_gt_requests.h"
#include "gt/mock_engine.h"
@@ -55,6 +57,9 @@ static void mock_device_release(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
+ if (!i915->do_release)
+ goto out;
+
mock_device_flush(i915);
intel_gt_driver_remove(&i915->gt);
@@ -72,7 +77,9 @@ static void mock_device_release(struct drm_device *dev)
drm_mode_config_cleanup(&i915->drm);
drm_dev_fini(&i915->drm);
+out:
put_device(&i915->drm.pdev->dev);
+ kfree(i915->drm.pdev);
}
static struct drm_driver mock_driver = {
@@ -114,9 +121,14 @@ struct drm_i915_private *mock_gem_device(void)
struct pci_dev *pdev;
int err;
- pdev = kzalloc(sizeof(*pdev) + sizeof(*i915), GFP_KER
[Intel-gfx] [PATCH 04/51] drm: Set final_kfree in drm_dev_alloc
I also did a full review of all callers, and only the xen driver forgot to call drm_dev_put in the failure path. Fix that up too. v2: I noticed that xen has a drm_driver.release hook, and uses drm_dev_alloc(). We need to remove the kfree from xen_drm_drv_release(). bochs also has a release hook, but leaked the drm_device ever since commit 0a6659bdc5e8221da99eebb176fd9591435e38de Author: Gerd Hoffmann Date: Tue Dec 17 18:04:46 2013 +0100 drm/bochs: new driver This patch here fixes that leak. Same for virtio, started leaking with commit b1df3a2b24a917f8853d43fe9683c0e360d2c33a Author: Gerd Hoffmann Date: Tue Feb 11 14:58:04 2020 +0100 drm/virtio: add drm_driver.release callback. Cc: Gerd Hoffmann Cc: Oleksandr Andrushchenko Cc: xen-de...@lists.xenproject.org Reviewed-by: Oleksandr Andrushchenko Signed-off-by: Daniel Vetter Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: Oleksandr Andrushchenko Cc: xen-de...@lists.xenproject.org --- drivers/gpu/drm/drm_drv.c | 3 +++ drivers/gpu/drm/xen/xen_drm_front.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 3e5627d6eba6..9e62e28bbc62 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include @@ -819,6 +820,8 @@ struct drm_device *drm_dev_alloc(struct drm_driver *driver, return ERR_PTR(ret); } + drmm_add_final_kfree(dev, dev); + return dev; } EXPORT_SYMBOL(drm_dev_alloc); diff --git a/drivers/gpu/drm/xen/xen_drm_front.c b/drivers/gpu/drm/xen/xen_drm_front.c index 4be49c1aef51..d22b5da38935 100644 --- a/drivers/gpu/drm/xen/xen_drm_front.c +++ b/drivers/gpu/drm/xen/xen_drm_front.c @@ -461,7 +461,6 @@ static void xen_drm_drv_release(struct drm_device *dev) drm_mode_config_cleanup(dev); drm_dev_fini(dev); - kfree(dev); if (front_info->cfg.be_alloc) xenbus_switch_state(front_info->xb_dev, @@ -561,6 +560,7 @@ static int xen_drm_drv_init(struct xen_drm_front_info *front_info) fail_modeset: drm_kms_helper_poll_fini(drm_dev); drm_mode_config_cleanup(drm_dev); + drm_dev_put(drm_dev); fail: kfree(drm_info); return ret; -- 2.24.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/51] drm/mipi_dbi: Use drmm_add_final_kfree in all drivers
They all share mipi_dbi_release so we need to switch them all
together. With this we can drop the final kfree from the release
function.
Aside, I think we could perhaps have a tiny additional helper for
these mipi_dbi drivers, the first few lines around devm_drm_dev_init
are all the same (except for the drm_driver pointer).
Reviewed-by: Noralf Trønnes
Tested-by: Noralf Trønnes
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
Cc: David Airlie
Cc: Daniel Vetter
Cc: Eric Anholt
Cc: David Lechner
Cc: Kamlesh Gurudasani
Cc: "Noralf Trønnes"
Cc: Sam Ravnborg
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_mipi_dbi.c | 3 ---
drivers/gpu/drm/tiny/hx8357d.c | 2 ++
drivers/gpu/drm/tiny/ili9225.c | 2 ++
drivers/gpu/drm/tiny/ili9341.c | 2 ++
drivers/gpu/drm/tiny/ili9486.c | 2 ++
drivers/gpu/drm/tiny/mi0283qt.c | 2 ++
drivers/gpu/drm/tiny/st7586.c | 2 ++
drivers/gpu/drm/tiny/st7735r.c | 2 ++
8 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
index 558baf989f5a..069603dfcd10 100644
--- a/drivers/gpu/drm/drm_mipi_dbi.c
+++ b/drivers/gpu/drm/drm_mipi_dbi.c
@@ -588,13 +588,10 @@ EXPORT_SYMBOL(mipi_dbi_dev_init);
*/
void mipi_dbi_release(struct drm_device *drm)
{
- struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(drm);
-
DRM_DEBUG_DRIVER("\n");
drm_mode_config_cleanup(drm);
drm_dev_fini(drm);
- kfree(dbidev);
}
EXPORT_SYMBOL(mipi_dbi_release);
diff --git a/drivers/gpu/drm/tiny/hx8357d.c b/drivers/gpu/drm/tiny/hx8357d.c
index 9af8ff84974f..42bc5dadcb1c 100644
--- a/drivers/gpu/drm/tiny/hx8357d.c
+++ b/drivers/gpu/drm/tiny/hx8357d.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -236,6 +237,7 @@ static int hx8357d_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/ili9225.c b/drivers/gpu/drm/tiny/ili9225.c
index 802fb8dde1b6..aae88dc5b3f7 100644
--- a/drivers/gpu/drm/tiny/ili9225.c
+++ b/drivers/gpu/drm/tiny/ili9225.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#include
#include
@@ -387,6 +388,7 @@ static int ili9225_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/ili9341.c b/drivers/gpu/drm/tiny/ili9341.c
index 33b51dc7faa8..7d40cb4ff72b 100644
--- a/drivers/gpu/drm/tiny/ili9341.c
+++ b/drivers/gpu/drm/tiny/ili9341.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -194,6 +195,7 @@ static int ili9341_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/ili9486.c b/drivers/gpu/drm/tiny/ili9486.c
index 5084b38c1a71..7d735fc67498 100644
--- a/drivers/gpu/drm/tiny/ili9486.c
+++ b/drivers/gpu/drm/tiny/ili9486.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
#include
@@ -208,6 +209,7 @@ static int ili9486_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/mi0283qt.c b/drivers/gpu/drm/tiny/mi0283qt.c
index e2cfd9a17143..8555a56bce8c 100644
--- a/drivers/gpu/drm/tiny/mi0283qt.c
+++ b/drivers/gpu/drm/tiny/mi0283qt.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -198,6 +199,7 @@ static int mi0283qt_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c
index 9ef559dd3191..427c2561f5f4 100644
--- a/drivers/gpu/drm/tiny/st7586.c
+++ b/drivers/gpu/drm/tiny/st7586.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
@@ -328,6 +329,7 @@ static int st7586_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_final_kfree(drm, dbidev);
drm_mode_config_init(drm);
diff --git a/drivers/gpu/drm/tiny/st7735r.c b/drivers/gpu/drm/tiny/st7735r.c
index 18b925df6e51..b447235c3d47 100644
--- a/drivers/gpu/drm/tiny/st7735r.c
+++ b/drivers/gpu/drm/tiny/st7735r.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#define ST7735R_FRMCTR10xb1
@@ -209,6 +210,7 @@ static int st7735r_probe(struct spi_device *spi)
kfree(dbidev);
return ret;
}
+ drmm_add_fi
[Intel-gfx] [PATCH 20/51] drm: Handle dev->unique with drmm_
We need to add a drmm_kstrdup for this, but let's start somewhere.
This is not exactly perfect onion unwinding, but it's jsut a kfree so
doesn't really matter at all.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_drv.c | 5 ++---
drivers/gpu/drm/drm_managed.c | 16
include/drm/drm_managed.h | 1 +
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 1ee606b4a4f9..782fd5d6f8b2 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -777,7 +777,6 @@ void drm_dev_fini(struct drm_device *dev)
mutex_destroy(&dev->filelist_mutex);
mutex_destroy(&dev->struct_mutex);
drm_legacy_destroy_members(dev);
- kfree(dev->unique);
}
EXPORT_SYMBOL(drm_dev_fini);
@@ -1063,8 +1062,8 @@ EXPORT_SYMBOL(drm_dev_unregister);
*/
int drm_dev_set_unique(struct drm_device *dev, const char *name)
{
- kfree(dev->unique);
- dev->unique = kstrdup(name, GFP_KERNEL);
+ drmm_kfree(dev, dev->unique);
+ dev->unique = drmm_kstrdup(dev, name, GFP_KERNEL);
return dev->unique ? 0 : -ENOMEM;
}
diff --git a/drivers/gpu/drm/drm_managed.c b/drivers/gpu/drm/drm_managed.c
index a36d4604ee18..cc917187a723 100644
--- a/drivers/gpu/drm/drm_managed.c
+++ b/drivers/gpu/drm/drm_managed.c
@@ -149,6 +149,22 @@ void *drmm_kmalloc(struct drm_device *dev, size_t size,
gfp_t gfp)
}
EXPORT_SYMBOL(drmm_kmalloc);
+char *drmm_kstrdup(struct drm_device *dev, const char *s, gfp_t gfp)
+{
+ size_t size;
+ char *buf;
+
+ if (!s)
+ return NULL;
+
+ size = strlen(s) + 1;
+ buf = drmm_kmalloc(dev, size, gfp);
+ if (buf)
+ memcpy(buf, s, size);
+ return buf;
+}
+EXPORT_SYMBOL_GPL(drmm_kstrdup);
+
void drmm_kfree(struct drm_device *dev, void *data)
{
struct drmres *dr_match = NULL, *dr;
diff --git a/include/drm/drm_managed.h b/include/drm/drm_managed.h
index 7b5df7d09b19..89e6fce9f689 100644
--- a/include/drm/drm_managed.h
+++ b/include/drm/drm_managed.h
@@ -24,6 +24,7 @@ static inline void *drmm_kzalloc(struct drm_device *dev,
size_t size, gfp_t gfp)
{
return drmm_kmalloc(dev, size, gfp | __GFP_ZERO);
}
+char *drmm_kstrdup(struct drm_device *dev, const char *s, gfp_t gfp);
void drmm_kfree(struct drm_device *dev, void *data);
--
2.24.1
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[Intel-gfx] [PATCH 19/51] drm: Cleanups after drmm_add_final_kfree rollout
A few things:
- Update the example driver in the documentation.
- We can drop the old kfree in drm_dev_release.
- Add a WARN_ON check in drm_dev_register to make sure everyone calls
drmm_add_final_kfree and there's no leaks.
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_drv.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 9e62e28bbc62..1ee606b4a4f9 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -297,8 +297,6 @@ void drm_minor_release(struct drm_minor *minor)
*
* drm_mode_config_cleanup(drm);
* drm_dev_fini(drm);
- * kfree(priv->userspace_facing);
- * kfree(priv);
* }
*
* static struct drm_driver driver_drm_driver = {
@@ -326,10 +324,11 @@ void drm_minor_release(struct drm_minor *minor)
* kfree(drm);
* return ret;
* }
+ * drmm_add_final_kfree(drm, priv);
*
* drm_mode_config_init(drm);
*
- * priv->userspace_facing = kzalloc(..., GFP_KERNEL);
+ * priv->userspace_facing = drmm_kzalloc(..., GFP_KERNEL);
* if (!priv->userspace_facing)
* return -ENOMEM;
*
@@ -834,10 +833,6 @@ static void drm_dev_release(struct kref *ref)
dev->driver->release(dev);
} else {
drm_dev_fini(dev);
- if (!dev->managed.final_kfree) {
- WARN_ON(!list_empty(&dev->managed.resources));
- kfree(dev);
- }
}
drm_managed_release(dev);
@@ -960,6 +955,8 @@ int drm_dev_register(struct drm_device *dev, unsigned long
flags)
struct drm_driver *driver = dev->driver;
int ret;
+ WARN_ON(!dev->managed.final_kfree);
+
if (drm_dev_needs_global_mutex(dev))
mutex_lock(&drm_global_mutex);
--
2.24.1
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[Intel-gfx] [PATCH 16/51] drm/inigenic: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function.
Signed-off-by: Daniel Vetter
Cc: Paul Cercueil
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 9dfe7cb530e1..e2c832eb4e9a 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -23,6 +23,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -490,11 +491,8 @@ static irqreturn_t ingenic_drm_irq_handler(int irq, void
*arg)
static void ingenic_drm_release(struct drm_device *drm)
{
- struct ingenic_drm *priv = drm_device_get_priv(drm);
-
drm_mode_config_cleanup(drm);
drm_dev_fini(drm);
- kfree(priv);
}
static int ingenic_drm_enable_vblank(struct drm_crtc *crtc)
@@ -639,6 +637,7 @@ static int ingenic_drm_probe(struct platform_device *pdev)
kfree(priv);
return ret;
}
+ drmm_add_final_kfree(drm, priv);
drm_mode_config_init(drm);
drm->mode_config.min_width = 0;
--
2.24.1
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[Intel-gfx] [PATCH 15/51] drm/repaper: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function.
Reviewed-by: Noralf Trønnes
Signed-off-by: Daniel Vetter
Cc: "Noralf Trønnes"
---
drivers/gpu/drm/tiny/repaper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tiny/repaper.c b/drivers/gpu/drm/tiny/repaper.c
index f5ebcaf7ee3a..df5654ef53ee 100644
--- a/drivers/gpu/drm/tiny/repaper.c
+++ b/drivers/gpu/drm/tiny/repaper.c
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -910,13 +911,10 @@ static const struct drm_mode_config_funcs
repaper_mode_config_funcs = {
static void repaper_release(struct drm_device *drm)
{
- struct repaper_epd *epd = drm_to_epd(drm);
-
DRM_DEBUG_DRIVER("\n");
drm_mode_config_cleanup(drm);
drm_dev_fini(drm);
- kfree(epd);
}
static const uint32_t repaper_formats[] = {
@@ -1024,6 +1022,7 @@ static int repaper_probe(struct spi_device *spi)
kfree(epd);
return ret;
}
+ drmm_add_final_kfree(drm, epd);
drm_mode_config_init(drm);
drm->mode_config.funcs = &repaper_mode_config_funcs;
--
2.24.1
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[Intel-gfx] [PATCH 09/51] drm/cirrus: Use drmm_add_final_kfree
With this we can drop the final kfree from the release function.
I also noticed that cirrus forgot to call drm_dev_fini().
v2: Don't call kfree(cirrus) after we've handed overship of that to
drm_device and the drmm_ stuff.
Signed-off-by: Daniel Vetter
Cc: Dave Airlie
Cc: Gerd Hoffmann
Cc: Daniel Vetter
Cc: "Noralf Trønnes"
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thomas Zimmermann
Cc: virtualizat...@lists.linux-foundation.org
---
drivers/gpu/drm/cirrus/cirrus.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/cirrus/cirrus.c b/drivers/gpu/drm/cirrus/cirrus.c
index d2ff63ce8eaf..2232556ce34c 100644
--- a/drivers/gpu/drm/cirrus/cirrus.c
+++ b/drivers/gpu/drm/cirrus/cirrus.c
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -527,10 +528,8 @@ static void cirrus_mode_config_init(struct cirrus_device
*cirrus)
static void cirrus_release(struct drm_device *dev)
{
- struct cirrus_device *cirrus = dev->dev_private;
-
drm_mode_config_cleanup(dev);
- kfree(cirrus);
+ drm_dev_fini(dev);
}
DEFINE_DRM_GEM_FOPS(cirrus_fops);
@@ -575,9 +574,12 @@ static int cirrus_pci_probe(struct pci_dev *pdev,
dev = &cirrus->dev;
ret = drm_dev_init(dev, &cirrus_driver, &pdev->dev);
- if (ret)
- goto err_free_cirrus;
+ if (ret) {
+ kfree(cirrus);
+ goto err_pci_release;
+ }
dev->dev_private = cirrus;
+ drmm_add_final_kfree(dev, cirrus);
ret = -ENOMEM;
cirrus->vram = ioremap(pci_resource_start(pdev, 0),
@@ -618,8 +620,6 @@ static int cirrus_pci_probe(struct pci_dev *pdev,
iounmap(cirrus->vram);
err_dev_put:
drm_dev_put(dev);
-err_free_cirrus:
- kfree(cirrus);
err_pci_release:
pci_release_regions(pdev);
return ret;
--
2.24.1
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