Re: [Intel-gfx] [PATCH v2] drm/i915/vbt: Handle generic DTD block
On Mon, 28 Oct 2019, Matt Roper wrote:
> VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
> old LFP panel mode data in block 42. Let's start parsing this block to
> fill in the panel fixed mode on devices with a >=229 VBT.
>
> v2:
> * Update according to the recent updates:
> - DTD size is now 16 bits instead of 24
> - polarity is now just a single bit for hsync and vsync and is
> properly documented
> * Minor checkpatch fix
>
> Bspec: 54751
> Bspec: 20148
> Cc: Jani Nikula
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 87 ++-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 31 +++
> 2 files changed, 115 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 63c1bd4c2954..0d1504e23a49 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -202,6 +202,72 @@ get_lvds_fp_timing(const struct bdb_header *bdb,
> return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
> }
>
> +static struct drm_display_mode *
> +parse_generic_dtd(struct drm_i915_private *dev_priv,
> + const struct bdb_generic_dtd *generic_dtd)
> +{
> + const struct bdb_generic_dtd_entry *dtd;
> + struct drm_display_mode *panel_fixed_mode;
> + int num_dtd;
> +
> + if (generic_dtd->gdtd_size < sizeof(struct bdb_generic_dtd_entry)) {
> + DRM_ERROR("GDTD size %u is too small.\n",
> + generic_dtd->gdtd_size);
> + return NULL;
I think in the future we may want to copy this to an allocated dtd entry
with zero padding so we don't have to care in the parser. But this can
be like this for now.
> + } else if (generic_dtd->gdtd_size !=
> +sizeof(struct bdb_generic_dtd_entry)) {
> + DRM_ERROR("Unexpected GDTD size %u\n", generic_dtd->gdtd_size);
> + /* DTD has unknown fields, but keep going */
> + }
> +
> + num_dtd = (get_blocksize(generic_dtd) -
> +sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size;
> + if (dev_priv->vbt.panel_type > num_dtd) {
> + DRM_ERROR("Panel type %d not found in table of %d DTD's\n",
> + dev_priv->vbt.panel_type, num_dtd);
> + return NULL;
> + }
> +
> + dtd = &generic_dtd->dtd[dev_priv->vbt.panel_type];
> +
> + panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
> + if (!panel_fixed_mode)
> + return NULL;
> +
> + panel_fixed_mode->hdisplay = dtd->hactive;
> + panel_fixed_mode->hsync_start =
> + panel_fixed_mode->hdisplay + dtd->hfront_porch;
> + panel_fixed_mode->hsync_end =
> + panel_fixed_mode->hsync_start + dtd->hsync;
> + panel_fixed_mode->htotal = panel_fixed_mode->hsync_end;
> +
> + panel_fixed_mode->vdisplay = dtd->vactive;
> + panel_fixed_mode->vsync_start =
> + panel_fixed_mode->vdisplay + dtd->vfront_porch;
> + panel_fixed_mode->vsync_end =
> + panel_fixed_mode->vsync_start + dtd->vsync;
> + panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end;
> +
> + panel_fixed_mode->clock = dtd->pixel_clock;
> + panel_fixed_mode->width_mm = dtd->width_mm;
> + panel_fixed_mode->height_mm = dtd->height_mm;
> +
> + panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
> + drm_mode_set_name(panel_fixed_mode);
> +
> + if (dtd->hsync_polarity)
> + panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
> + else
> + panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
> +
> + if (dtd->vsync_polarity)
> + panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
> + else
> + panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
> +
> + return panel_fixed_mode;
> +}
> +
> /* Try to find integrated panel data */
> static void
> parse_lfp_panel_data(struct drm_i915_private *dev_priv,
> @@ -210,6 +276,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
> const struct bdb_lvds_options *lvds_options;
> const struct bdb_lvds_lfp_data *lvds_lfp_data;
> const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
> + const struct bdb_generic_dtd *generic_dtd;
> const struct lvds_dvo_timing *panel_dvo_timing;
> const struct lvds_fp_timing *fp_timing;
> struct drm_display_mode *panel_fixed_mode;
> @@ -262,6 +329,18 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
> break;
> }
>
> + if (bdb->version >= 229) {
> + generic_dtd = find_section(bdb, BDB_GENERIC_DTD);
> + if (!generic_dtd)
> + return;
> +
> + panel_fixed_mode = parse_generic_dtd(dev_priv, generic_dtd);
> + if (!panel_fixed_mode)
> + return;
Knowing how it is with VBTs... maybe we should fa
[Intel-gfx] [CI 01/12] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and planar YUV support having
extra planes outside of the core's view that wouldn't be added otherwise.
Changes since v1:
- Always add all planes, to handle force plane updates to work correctly
with a disabled cursor plane.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 41 +--
.../gpu/drm/i915/display/intel_atomic_plane.c | 15 +++
drivers/gpu/drm/i915/display/intel_cdclk.c| 15 ---
drivers/gpu/drm/i915/display/intel_color.c| 7 ++--
.../drm/i915/display/intel_display_types.h| 6 +++
drivers/gpu/drm/i915/intel_pm.c | 14 ---
6 files changed, 62 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 9cd6d2348a1e..80df6c233581 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -313,13 +313,10 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_plane *plane = NULL;
- struct intel_plane *intel_plane;
- struct intel_plane_state *plane_state = NULL;
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
struct drm_atomic_state *drm_state = crtc_state->base.state;
- struct intel_atomic_state *intel_state =
to_intel_atomic_state(drm_state);
+ struct intel_atomic_state *state = to_intel_atomic_state(drm_state);
int num_scalers_need;
int i;
@@ -346,6 +343,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* walkthrough scaler_users bits and start assigning scalers */
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
+ struct intel_plane_state *plane_state = NULL;
int *scaler_id;
const char *name;
int idx;
@@ -361,19 +359,16 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
/* panel fitter case: assign as a crtc scaler */
scaler_id = &scaler_state->scaler_id;
} else {
- name = "PLANE";
+ struct intel_plane *plane;
/* plane scaler case: assign as a plane scaler */
/* find the plane that set the bit as scaler_user */
- plane = drm_state->planes[i].ptr;
/*
* to enable/disable hq mode, add planes that are using
scaler
* into this transaction
*/
- if (!plane) {
- struct drm_plane_state *state;
-
+ if (!drm_state->planes[i].ptr) {
/*
* GLK+ scalers don't have a HQ mode so it
* isn't necessary to change between HQ and dyn
mode
@@ -382,24 +377,28 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
if (INTEL_GEN(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv))
continue;
- plane = drm_plane_from_index(&dev_priv->drm, i);
- state = drm_atomic_get_plane_state(drm_state,
plane);
- if (IS_ERR(state)) {
- DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state\n",
- plane->base.id);
- return PTR_ERR(state);
+ plane =
to_intel_plane(drm_plane_from_index(&dev_priv->drm, i));
+ plane_state =
+
intel_atomic_get_plane_state_after_check(state,
+
crtc_state,
+
plane);
+ if (IS_ERR(plane_state)) {
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state: %li\n",
+ plane->base.base.id,
PTR_ERR(plane_state));
+ return PTR_ERR(plane_state);
}
+ } else {
+ plane =
to_intel_plane(drm_state->pl
[Intel-gfx] [CI 02/12] drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Changes since v2:
- Incorporate Ville's feedback.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 12
drivers/gpu/drm/i915/display/intel_psr.c | 16 +++-
drivers/gpu/drm/i915/intel_pm.c | 6 ++
4 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..9a7c15fad367 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16720,8 +16720,7 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16733,15 +16732,17 @@ static int intel_initial_commit(struct drm_device
*dev)
retry:
state->acquire_ctx = &ctx;
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_crtc_state(state, crtc);
+
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->base.active) {
+ ret = drm_atomic_add_affected_planes(state,
&crtc->base);
if (ret)
goto out;
@@ -16751,7 +16752,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->base.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a9962846a503..42d26214fb23 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -168,7 +168,6 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
struct intel_connector *intel_connector =
to_intel_connector(connector);
struct drm_crtc *new_crtc = new_conn_state->crtc;
- struct drm_crtc_state *crtc_state;
struct drm_dp_mst_topology_mgr *mgr;
int ret;
@@ -183,11 +182,16 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
* connector
*/
if (new_crtc) {
- crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
+ struct intel_atomic_state *intel_state =
+ to_intel_atomic_state(state);
+ struct intel_crtc *intel_crtc = to_intel_crtc(new_crtc);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(intel_state,
+ intel_crtc);
if (!crtc_state ||
- !drm_atomic_crtc_needs_modeset(crtc_state) ||
- crtc_state->enable)
+ !drm_atomic_crtc_needs_modeset(&crtc_state->base) ||
+ crtc_state->base.enable)
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6a9f322d3fca..359a60762b49 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
+#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
@@ -1096,7 +1097,7 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
struct drm_device *dev = &dev_priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct drm_crtc *crtc;
+ struct intel_crtc *crtc;
int err;
state = drm_atomic_state_alloc(dev);
@@ -1107,21 +1108,18 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
state->acquire_ctx = &ctx;
retry:
- drm_for_each_crtc(crtc, dev) {
- struct drm_crtc_state *crtc_state;
-
[Intel-gfx] [CI 03/12] drm/i915: Add aliases for uapi and hw to crtc_state
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
drivers/gpu/drm/i915/display/intel_display.c | 2 ++
drivers/gpu/drm/i915/display/intel_display.h | 6 ++---
.../drm/i915/display/intel_display_types.h| 27 ++-
4 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 80df6c233581..619e7da4e4a5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -186,9 +186,10 @@ intel_digital_connector_duplicate_state(struct
drm_connector *connector)
struct drm_crtc_state *
intel_crtc_duplicate_state(struct drm_crtc *crtc)
{
+ const struct intel_crtc_state *old_crtc_state =
to_intel_crtc_state(crtc->state);
struct intel_crtc_state *crtc_state;
- crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL);
+ crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
if (!crtc_state)
return NULL;
@@ -219,7 +220,10 @@ void
intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
- drm_atomic_helper_crtc_destroy_state(crtc, state);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
+
+ __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
+ kfree(crtc_state);
}
static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state
*scaler_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9a7c15fad367..d0df9b24a969 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12595,6 +12595,8 @@ clear_intel_crtc_state(struct intel_crtc_state
*crtc_state)
/* Keep base drm_crtc_state intact, only clear our extended struct */
BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, uapi));
+ BUILD_BUG_ON(offsetof(struct intel_crtc_state, hw));
memcpy(&crtc_state->base + 1, &saved_state->base + 1,
sizeof(*crtc_state) - sizeof(crtc_state->base));
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index ca7ca2804d8b..ca3eb6a1c125 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -447,10 +447,10 @@ enum phy_fia {
#define intel_atomic_crtc_state_for_each_plane_state( \
plane, plane_state, \
crtc_state) \
- for_each_intel_plane_mask(((crtc_state)->base.state->dev), (plane), \
- ((crtc_state)->base.plane_mask)) \
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
+ ((crtc_state)->uapi.plane_mask)) \
for_each_if ((plane_state = \
-
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->base.state,
&plane->base
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
&plane->base
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 61e9db041613..573ced9dc909 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -757,7 +757,32 @@ enum intel_output_format {
};
struct intel_crtc_state {
+ union {
struct drm_crtc_state base;
+ /*
+* uapi (drm) state. This is the software state shown to userspace.
+* In particular, the following members are used for bookkeeping:
+* - crtc
+* - state
+* - *_changed
+* - event
+* - commit
+* - mode_blob
+*/
+ struct drm_crtc_state uapi;
+
+ /*
+* actual hardware state, the state we program to the hardware.
+* The following members are used to verify the hardware state:
+* - enable
+* - active
+* - mode / adjusted_mode
+* - color property blobs.
+*
+* During initial hw readout, they need to be copied to uapi.
+*/
+ struct drm_crtc_state hw;
+ };
/**
* quirks - bitfield with hw state readout quirks
@@ -1112,7 +1137,7 @@ struct cxsr_latency {
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state,
base)
#define to_intel_crtc(x) container_of(x, struct intel_crtc
[Intel-gfx] [CI 05/12] drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw.
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x
Signed-off-by: Maarten Lankhorst
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/drm_dp_mst_topology.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi.c| 12 +-
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c| 8 +-
drivers/gpu/drm/i915/display/intel_color.c| 108
drivers/gpu/drm/i915/display/intel_crt.c | 18 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 260 +-
drivers/gpu/drm/i915/display/intel_dp.c | 22 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 12 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +-
drivers/gpu/drm/i915/display/intel_lspcon.c | 4 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 8 +-
drivers/gpu/drm/i915/display/intel_panel.c| 8 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 12 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 16 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi.c| 10 +-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 56 ++--
25 files changed, 318 insertions(+), 313 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 85bef73a6763..fddea7acf7d8 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#endif
#include
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..4ec493e4755b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder
*encoder,
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
u32 dss_ctl2;
u16 hactive = adjusted_mode->crtc_hdisplay;
u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
enum port port;
enum transcoder dsi_trans;
/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder
*encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
if (intel_dsi->dual_link) {
adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder
*encoder,
pipe_config->port_clock =
cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
- pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+ pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
if (intel_dsi->dual_link)
- pipe_config->base.adjusted_mode.crtc_clock *= 2;
+ pipe_config->hw.adjusted_mode.crtc_clock *= 2;
gen11_dsi_get_timings(encoder, pipe_config);
pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder
*encoder,
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->hw.adjusted_mode;
pipe_config->output_fo
[Intel-gfx] [CI 07/12] drm/i915: Complete crtc hw/uapi split, v4.
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediately after drm_atomic_helper_check_modeset().
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
Changes since v2:
- Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
- Make a intel_crtc_prepare_state() function that clears the crtc_state
and copies hw members.
- Remove setting uapi.adjusted_mode, we now have a direct call to
drm_calc_timestamping_constants().
Changes since v3:
- Rename prefix copy_hw_to_uapi_state() with intel_crtc.
- Copy color blobs to uapi as well.
- Add a intel_crtc_copy_uapi_to_hw_state_nomodeset() function for clarity.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44 ++
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 80 ---
.../drm/i915/display/intel_display_types.h| 9 ++-
4 files changed, 118 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 366275dc113d..557178906ccf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return &crtc_state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+
+ if (crtc_state->uapi.degamma_lut)
+ crtc_state->hw.degamma_lut =
+ drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ else
+ crtc_state->hw.degamma_lut = NULL;
+
+ if (crtc_state->uapi.gamma_lut)
+ crtc_state->hw.gamma_lut =
+ drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ else
+ crtc_state->hw.gamma_lut = NULL;
+
+ if (crtc_state->uapi.ctm)
+ crtc_state->hw.ctm =
+ drm_property_blob_get(crtc_state->uapi.ctm);
+ else
+ crtc_state->hw.ctm = NULL;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 49d5cb1b9e0a..7b49623419ba 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -36,6 +36,8 @@ intel_digital_connector_duplicate_state(struct drm_connector
*connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1bc008c094e4..a765794597ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7185,6 +7185,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+ intel_crtc_free_hw
[Intel-gfx] [CI 10/12] drm/i915: Perform automated conversions for plane uapi/hw split, base -> hw.
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 6 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 133 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 8 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 90 ++--
drivers/gpu/drm/i915/intel_pm.c | 32 ++---
7 files changed, 139 insertions(+), 138 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 557178906ccf..fb4126de994d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -296,9 +296,9 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->is_yuv &&
- plane_state->base.fb->format->num_planes > 1) {
+ if (plane_state && plane_state->hw.fb &&
+ plane_state->hw.fb->format->is_yuv &&
+ plane_state->hw.fb->format->num_planes > 1) {
struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 987f7545d45f..cac1d6ae67f6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -118,7 +118,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
if (!plane_state->base.visible)
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
- const struct drm_framebuffer *fb = new_plane_state->base.fb;
+ const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -192,7 +192,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->min_cdclk[plane->id] = 0;
new_plane_state->base.visible = false;
- if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+ if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
ret = plane->check_plane(new_crtc_state, new_plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cd9d68245f53..fbbe6f752716 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2215,7 +2215,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
int color_plane)
{
- const struct drm_framebuffer *fb = state->base.fb;
+ const struct drm_framebuffer *fb = state->hw.fb;
unsigned int cpp = fb->format->cpp[color_plane];
unsigned int pitch = state->color_plane[color_plane].stride;
@@ -2316,8 +2316,8 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int
*y,
int color_plane,
u32 old_offset, u32 new_offset)
{
- return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
- state->base.rotation,
+ return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
+ state->hw.rotation,
state->color_plane[color_plane].stride,
old_offset, new_offset);
}
@@ -2393,8 +2393,8 @@ static u32 intel_plane_compute_aligned_offset(int *x, int
*y,
{
struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
- const struct drm_framebuffer *fb = state->base.fb;
- unsigned int rotation = state->base.rotation;
+ const struct drm_framebuffer *fb = state->hw.fb;
+ u
[Intel-gfx] [CI 11/12] drm/i915: Perform automated conversions for plane uapi/hw split, base -> uapi.
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 32 +-
drivers/gpu/drm/i915/display/intel_display.c | 298 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 136
drivers/gpu/drm/i915/intel_pm.c | 57 ++--
7 files changed, 271 insertions(+), 268 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index fb4126de994d..cb5c914f627f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -299,7 +299,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
plane_state->hw.fb->format->num_planes > 1) {
- struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
+ struct intel_plane *plane =
to_intel_plane(plane_state->uapi.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
mode = SKL_PS_SCALER_MODE_NV12;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cac1d6ae67f6..ba7d5421f791 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -56,7 +56,7 @@ struct intel_plane *intel_plane_alloc(void)
return ERR_PTR(-ENOMEM);
}
- __drm_atomic_helper_plane_reset(&plane->base, &plane_state->base);
+ __drm_atomic_helper_plane_reset(&plane->base, &plane_state->uapi);
plane_state->scaler_id = -1;
return plane;
@@ -88,12 +88,12 @@ intel_plane_duplicate_state(struct drm_plane *plane)
if (!intel_state)
return NULL;
- __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
+ __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
intel_state->vma = NULL;
intel_state->flags = 0;
- return &intel_state->base;
+ return &intel_state->uapi;
}
/**
@@ -111,7 +111,7 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct intel_plane_state *plane_state = to_intel_plane_state(state);
WARN_ON(plane_state->vma);
- __drm_atomic_helper_plane_destroy_state(&plane_state->base);
+ __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
kfree(plane_state);
}
@@ -121,7 +121,7 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int cpp;
- if (!plane_state->base.visible)
+ if (!plane_state->uapi.visible)
return 0;
cpp = fb->format->cpp[0];
@@ -144,10 +144,10 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
*state,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct intel_plane_state *plane_state =
intel_atomic_get_new_plane_state(state, plane);
- struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->uapi.crtc);
struct intel_crtc_state *crtc_state;
- if (!plane_state->base.visible || !plane->min_cdclk)
+ if (!plane_state->uapi.visible || !plane->min_cdclk)
return false;
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@@ -181,7 +181,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
- struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
const struct drm_framebuffer *fb = new_plane_state->hw.fb;
int ret;
@@ -190,7 +190,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
new_crtc_state->min_cdclk[plane->id] = 0;
- new_plane_state->base.visible = false;
+ new_plane_state->uapi.visible = false;
if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
return 0;
@@ -200,18 +200,18
[Intel-gfx] [CI 08/12] drm/i915: Add aliases for uapi and hw to plane_state
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.../gpu/drm/i915/display/intel_display_types.h | 8 ++--
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 78e145e7c04d..0bfaeb9b7eb9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -80,22 +80,20 @@ void intel_plane_free(struct intel_plane *plane)
struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane *plane)
{
- struct drm_plane_state *state;
struct intel_plane_state *intel_state;
- intel_state = kmemdup(plane->state, sizeof(*intel_state), GFP_KERNEL);
+ intel_state = to_intel_plane_state(plane->state);
+ intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
if (!intel_state)
return NULL;
- state = &intel_state->base;
-
- __drm_atomic_helper_plane_duplicate_state(plane, state);
+ __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->base);
intel_state->vma = NULL;
intel_state->flags = 0;
- return state;
+ return &intel_state->base;
}
/**
@@ -110,9 +108,11 @@ void
intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
- WARN_ON(to_intel_plane_state(state)->vma);
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
- drm_atomic_helper_plane_destroy_state(plane, state);
+ __drm_atomic_helper_plane_destroy_state(&plane_state->base);
+ kfree(plane_state);
}
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bcf5f7640307..e43d5a09550d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -523,7 +523,11 @@ struct intel_atomic_state {
};
struct intel_plane_state {
- struct drm_plane_state base;
+ union {
+ struct drm_plane_state base;
+ struct drm_plane_state uapi;
+ struct drm_plane_state hw;
+ };
struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
@@ -1143,7 +1147,7 @@ struct cxsr_latency {
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
-#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
+#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
struct intel_hdmi {
--
2.23.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 04/12] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() definitely needs to check for uapi enable,
otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
Changes since v1:
- Actually set uapi.active in get_load_detect_pipe().
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 42 ++--
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d0df9b24a969..4baa0226abff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11433,7 +11433,7 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
goto fail;
}
- crtc_state->base.active = crtc_state->base.enable = true;
+ crtc_state->uapi.active = true;
if (!mode)
mode = &load_detect_mode;
@@ -13080,19 +13080,19 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(output_types);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
- PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
+ PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
@@ -13109,17 +13109,17 @@ intel_pipe_config_compare(const struct
intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_INTERLACE);
if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NHSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_PVSYNC);
- PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
+ PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
DRM_MODE_FLAG_NVSYNC);
}
@@ -13158,7 +13158,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
if (bp_gamma)
- PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut,
bp_gamma);
+ PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut,
bp_gamma);
}
@@ -13203,7 +13203,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
+ PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
PIPE_CONF_CHECK_I(min_voltage_level);
@@ -14010,7 +14010,7 @@ static int intel_atomic_check(struct drm_device *dev,
if (!needs_modeset(new_crtc_
[Intel-gfx] [CI 09/12] drm/i915: Perform manual conversions for plane uapi/hw split
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity look at the uapi state always
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 0bfaeb9b7eb9..987f7545d45f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -225,11 +225,11 @@ static struct intel_crtc *
get_crtc_from_states(const struct intel_plane_state *old_plane_state,
const struct intel_plane_state *new_plane_state)
{
- if (new_plane_state->base.crtc)
- return to_intel_crtc(new_plane_state->base.crtc);
+ if (new_plane_state->uapi.crtc)
+ return to_intel_crtc(new_plane_state->uapi.crtc);
- if (old_plane_state->base.crtc)
- return to_intel_crtc(old_plane_state->base.crtc);
+ if (old_plane_state->uapi.crtc)
+ return to_intel_crtc(old_plane_state->uapi.crtc);
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a765794597ed..cd9d68245f53 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15359,12 +15359,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
* take the slowpath. Only changing fb or position should be
* in the fastpath.
*/
- if (old_plane_state->base.crtc != &crtc->base ||
+ if (old_plane_state->uapi.crtc != &crtc->base ||
old_plane_state->base.src_w != src_w ||
old_plane_state->base.src_h != src_h ||
old_plane_state->base.crtc_w != crtc_w ||
old_plane_state->base.crtc_h != crtc_h ||
- !old_plane_state->base.fb != !fb)
+ !old_plane_state->uapi.fb != !fb)
goto slow;
new_plane_state =
to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
--
2.23.0
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[Intel-gfx] [CI 12/12] drm/i915: Complete plane hw and uapi split, v2.
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at plane_state.
Changes since v1:
- Do not clear hw state on duplication.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 37 ++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h| 23 +---
4 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index ba7d5421f791..75a5004b234e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -93,6 +93,10 @@ intel_plane_duplicate_state(struct drm_plane *plane)
intel_state->vma = NULL;
intel_state->flags = 0;
+ /* add reference to fb */
+ if (intel_state->hw.fb)
+ drm_framebuffer_get(intel_state->hw.fb);
+
return &intel_state->uapi;
}
@@ -112,6 +116,8 @@ intel_plane_destroy_state(struct drm_plane *plane,
WARN_ON(plane_state->vma);
__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
kfree(plane_state);
}
@@ -176,15 +182,44 @@ bool intel_plane_calc_min_cdclk(struct intel_atomic_state
*state,
return false;
}
+static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
+{
+ if (plane_state->hw.fb)
+ drm_framebuffer_put(plane_state->hw.fb);
+
+ memset(&plane_state->hw, 0, sizeof(plane_state->hw));
+}
+
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state)
+{
+ intel_plane_clear_hw_state(plane_state);
+
+ plane_state->hw.crtc = from_plane_state->uapi.crtc;
+ plane_state->hw.fb = from_plane_state->uapi.fb;
+ if (plane_state->hw.fb)
+ drm_framebuffer_get(plane_state->hw.fb);
+
+ plane_state->hw.alpha = from_plane_state->uapi.alpha;
+ plane_state->hw.pixel_blend_mode =
+ from_plane_state->uapi.pixel_blend_mode;
+ plane_state->hw.rotation = from_plane_state->uapi.rotation;
+ plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
+ plane_state->hw.color_range = from_plane_state->uapi.color_range;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
- const struct drm_framebuffer *fb = new_plane_state->hw.fb;
+ const struct drm_framebuffer *fb;
int ret;
+ intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state);
+ fb = new_plane_state->hw.fb;
+
new_crtc_state->active_planes &= ~BIT(plane->id);
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index e61e9a82aadf..cdb0f97d09f9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -20,6 +20,8 @@ extern const struct drm_plane_helper_funcs
intel_plane_helper_funcs;
unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
+void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
+ const struct intel_plane_state
*from_plane_state);
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 91a059e5fdcb..ed9504d0336e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3283,6 +3283,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
plane_state->fb = fb;
plane_state->crtc = &intel_crtc->base;
+ intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
atomic_or(to_intel_plane(primary)->front
Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On 10/23/2019 9:07 PM, Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
drivers/vfio/mdev/mdev_private.h | 2 +
include/linux/mdev.h | 6 ++
include/linux/virtio_mdev_ops.h | 159 +++
4 files changed, 187 insertions(+)
create mode 100644 include/linux/virtio_mdev_ops.h
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index 555bd61d8c38..9b00c3513120 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -76,6 +76,26 @@ const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct
mdev_device *mdev)
}
EXPORT_SYMBOL(mdev_get_vfio_ops);
+/* Specify the virtio device ops for the mdev device, this
+ * must be called during create() callback for virtio mdev device.
+ */
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops)
+{
+ mdev_set_class(mdev, MDEV_CLASS_ID_VIRTIO);
+ mdev->virtio_ops = virtio_ops;
+}
+EXPORT_SYMBOL(mdev_set_virtio_ops);
+
+/* Get the virtio device ops for the mdev device. */
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev)
+{
+ WARN_ON(mdev->class_id != MDEV_CLASS_ID_VIRTIO);
+ return mdev->virtio_ops;
+}
+EXPORT_SYMBOL(mdev_get_virtio_ops);
+
struct device *mdev_dev(struct mdev_device *mdev)
{
return &mdev->dev;
diff --git a/drivers/vfio/mdev/mdev_private.h b/drivers/vfio/mdev/mdev_private.h
index 0770410ded2a..7b47890c34e7 100644
--- a/drivers/vfio/mdev/mdev_private.h
+++ b/drivers/vfio/mdev/mdev_private.h
@@ -11,6 +11,7 @@
#define MDEV_PRIVATE_H
#include
+#include
int mdev_bus_register(void);
void mdev_bus_unregister(void);
@@ -38,6 +39,7 @@ struct mdev_device {
u16 class_id;
union {
const struct vfio_mdev_device_ops *vfio_ops;
+ const struct virtio_mdev_device_ops *virtio_ops;
};
};
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 4625f1a11014..9b69b0bbebfd 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -17,6 +17,7 @@
struct mdev_device;
struct vfio_mdev_device_ops;
+struct virtio_mdev_device_ops;
/*
* Called by the parent device driver to set the device which represents
@@ -112,6 +113,10 @@ void mdev_set_class(struct mdev_device *mdev, u16 id);
void mdev_set_vfio_ops(struct mdev_device *mdev,
const struct vfio_mdev_device_ops *vfio_ops);
const struct vfio_mdev_device_ops *mdev_get_vfio_ops(struct mdev_device
*mdev);
+void mdev_set_virtio_ops(struct mdev_device *mdev,
+const struct virtio_mdev_device_ops *virtio_ops);
+const struct virtio_mdev_device_ops *
+mdev_get_virtio_ops(struct mdev_device *mdev);
extern struct bus_type mdev_bus_type;
@@ -127,6 +132,7 @@ struct mdev_device *mdev_from_dev(struct device *dev);
enum {
MDEV_CLASS_ID_VFIO = 1,
+ MDEV_CLASS_ID_VIRTIO = 2,
/* New entries must be added here */
};
diff --git a/include/linux/virtio_mdev_ops.h b/include/linux/virtio_mdev_ops.h
new file mode 100644
index ..d417b41f2845
--- /dev/null
+++ b/include/linux/virtio_mdev_ops.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Virtio mediated device driver
+ *
+ * Copyright 2019, Red Hat Corp.
+ * Author: Jason Wang
+ */
+#ifndef _LINUX_VIRTIO_MDEV_H
+#define _LINUX_VIRTIO_MDEV_H
+
+#include
+#include
+#include
+
+#define VIRTIO_MDEV_DEVICE_API_STRING "virtio-mdev"
+#define VIRTIO_MDEV_F_VERSION_1 0x1
+
+struct virtio_mdev_callback {
+ irqreturn_t (*callback)(void *data);
+ void *private;
+};
+
+/**
+ * struct vfio_mdev_device_ops - Structure to be registered for each
+ * mdev device to register the device for virtio/vhost drivers.
+ *
+ * The device ops that is supported by VIRTIO_MDEV_F_VERSION_1, the
+ * callbacks are mandatory unless explicity mentioned.
+ *
+ * @set_vq_address:Set the address of virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @desc_area: address of desc area
+ * @driver_area: address of driver area
+ * @device_area: address of device area
+ * Returns integer: success (0) or error (< 0)
+ * @set_vq_num:Set the size of virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @num: the size of virtqueue
+ * @kick_vq: Kick the virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @s
Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
On Tue, 29 Oct 2019 08:31:22 +0800 Changbin Du wrote: > Here python is different from C. Both empty string and None are False in > python. > Note such condition is common in python. Treating both as a False value is reasonably common. Treating them elsewhere in the same code block as separate values is less so; that's the part I would prefer to avoid. Thanks, jon ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 1/2] drm/i915/cml: Remove unsupport PCI ID
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some PCI
IDs were removed from CML IDs in BSpec.
v2: remove some inaccurate descriptions.
v3: fix typo.
v4: add missing version number.
v5: no update.
v6: update patch comment.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -448,9 +448,7 @@
#define INTEL_CML_GT1_IDS(info)\
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAB, info), \
INTEL_VGA_DEVICE(0x9BAC, info), \
- INTEL_VGA_DEVICE(0x9BA0, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
@@ -460,9 +458,7 @@
#define INTEL_CML_GT2_IDS(info)\
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCB, info), \
INTEL_VGA_DEVICE(0x9BCC, info), \
- INTEL_VGA_DEVICE(0x9BC0, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
--
2.17.1
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[Intel-gfx] [PATCH v6 2/2] drm/i915/cml: Separate U series pci id from origianl list.
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
v2: add missing comma in subplatform_ult_ids[].
v3: no update.
v4: no update.
v5: no update.
v6: no update.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bd9211b3d76e..e876621f6aaf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -863,6 +863,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CML_U_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CML_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..23c59e19832b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -775,6 +775,8 @@ static const u16 subplatform_ult_ids[] = {
INTEL_WHL_U_GT1_IDS(0),
INTEL_WHL_U_GT2_IDS(0),
INTEL_WHL_U_GT3_IDS(0),
+ INTEL_CML_U_GT1_IDS(0),
+ INTEL_CML_U_GT2_IDS(0),
};
static const u16 subplatform_ulx_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 56e823cdc717..02f10c4f5ec7 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -446,24 +446,28 @@
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info)\
- INTEL_VGA_DEVICE(0x9B21, info), \
- INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAC, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
INTEL_VGA_DEVICE(0x9BA2, info)
+#define INTEL_CML_U_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B21, info), \
+ INTEL_VGA_DEVICE(0x9BAA, info), \
+ INTEL_VGA_DEVICE(0x9BAC, info)
+
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info)\
- INTEL_VGA_DEVICE(0x9B41, info), \
- INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCC, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
INTEL_VGA_DEVICE(0x9BC2, info)
+#define INTEL_CML_U_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B41, info), \
+ INTEL_VGA_DEVICE(0x9BCA, info), \
+ INTEL_VGA_DEVICE(0x9BCC, info)
+
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -529,7 +533,9 @@
INTEL_WHL_U_GT3_IDS(info), \
INTEL_AML_CFL_GT2_IDS(info), \
INTEL_CML_GT1_IDS(info), \
- INTEL_CML_GT2_IDS(info)
+ INTEL_CML_GT2_IDS(info), \
+ INTEL_CML_U_GT1_IDS(info), \
+ INTEL_CML_U_GT2_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
--
2.17.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/12] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
== Series Details ==
Series: series starting with [CI,01/12] drm/i915: Introduce
intel_atomic_get_plane_state_after_check(), v2.
URL : https://patchwork.freedesktop.org/series/68694/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
874fbe7ef3ea drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
-:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#87: FILE: drivers/gpu/drm/i915/display/intel_atomic.c:387:
+ DRM_DEBUG_KMS("Failed to add [PLANE:%d]
to drm_state: %li\n",
+ plane->base.base.id,
PTR_ERR(plane_state));
total: 0 errors, 1 warnings, 1 checks, 185 lines checked
4f1d48454ee1 drm/i915: Handle a few more cases for crtc hw/uapi split, v3.
3687c3a98282 drm/i915: Add aliases for uapi and hw to crtc_state
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/display/intel_display.h:453:
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
&plane->base
total: 0 errors, 1 warnings, 0 checks, 83 lines checked
ffd35e35db81 drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
05e6016b7e5d drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> hw.
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#10:
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
-:1423: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#1423: FILE: drivers/gpu/drm/i915/display/intel_display.c:17296:
+ crtc_state->hw.active = crtc_state->hw.enable =
total: 0 errors, 1 warnings, 1 checks, 2068 lines checked
3a334a01e03a drm/i915: Perform automated conversions for crtc uapi/hw split,
base -> uapi.
-:2400: ERROR:CODE_INDENT: code indent should use tabs where possible
#2400: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+^I^I^I^I new_crtc_state->uapi.event);$
-:2400: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2400: FILE: drivers/gpu/drm/i915/display/intel_sprite.c:211:
+ drm_crtc_arm_vblank_event(&crtc->base,
+ new_crtc_state->uapi.event);
total: 1 errors, 0 warnings, 1 checks, 2552 lines checked
073cf0005a71 drm/i915: Complete crtc hw/uapi split, v4.
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#15:
- Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
total: 0 errors, 1 warnings, 0 checks, 245 lines checked
c602b94e8725 drm/i915: Add aliases for uapi and hw to plane_state
-:49: WARNING:LINE_SPACING: Missing a blank line after declarations
#49: FILE: drivers/gpu/drm/i915/display/intel_atomic_plane.c:112:
+ struct intel_plane_state *plane_state = to_intel_plane_state(state);
+ WARN_ON(plane_state->vma);
total: 0 errors, 1 warnings, 0 checks, 59 lines checked
c4c09c715aaa drm/i915: Perform manual conversions for plane uapi/hw split
bf75017f95eb drm/i915: Perform automated conversions for plane uapi/hw split,
base -> hw.
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#11:
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
-:922: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
"plane_state->hw.fb"
#922: FILE: drivers/gpu/drm/i915/intel_pm.c:804:
+ return plane_state->hw.fb != NULL;
total: 0 errors, 1 warnings, 1 checks, 903 lines checked
23683bbe1ff3 drm/i915: Perform automated conversions for plane uapi/hw split,
base -> uapi.
-:745: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#745: FILE: drivers/gpu/drm/i915/display/intel_display.c:11181:
+ unsigned width = drm_rect_width(&plane_state->uapi.dst);
-:746: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#746: FILE: drivers/gpu/drm/i915/display/intel_display.c:11182:
+ unsigned height = drm_rect_height(&plane_state->uapi.dst);
-:814: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#814: FILE: drivers/gpu/drm/i915/display/intel_display.c:11784:
+ plane_state->uapi.visible = visible = false;
-:1614: WARNING:LONG_LINE: line over 100 characters
#1614: FILE: drivers/gpu/drm/i915/intel_pm.c:3103:
+ (drm_rect_width(&sprstate->uapi.dst) !=
drm_rect_width(&sprstate->uapi.src) >> 16 ||
-:1615: WARNING:LONG_LINE: line over 100 characters
#1615: FILE: drivers/gpu/drm/i915/intel_pm.c:3104:
+drm_rect_height(&sprstat
Re: [Intel-gfx] [PATCH RESEND 6/8] drm/print: convert debug category macros into an enum
Quoting Jani Nikula (2019-10-28 12:38:20)
> Mostly for improved documentation, convert the debug category macros
> into an enum. Drop unused DRM_UT_NONE. Document previously undocumented
> categories.
>
> Signed-off-by: Jani Nikula
> +enum drm_debug_category {
> + /**
> +* @DRM_UT_CORE: Used in the generic drm code: drm_ioctl.c, drm_mm.c,
> +* drm_memory.c, ...
> +*/
> + DRM_UT_CORE = 0x01,
While here, why not BIT()
Reviewed-by: Joonas Lahtinen
Regards, Joonas
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,01/12] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2.
== Series Details == Series: series starting with [CI,01/12] drm/i915: Introduce intel_atomic_get_plane_state_after_check(), v2. URL : https://patchwork.freedesktop.org/series/68694/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15042 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15042 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15042, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/index.html Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15042: ### IGT changes ### Possible regressions * igt@kms_force_connector_basic@force-load-detect: - fi-hsw-4770:[PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-hsw-4770/igt@kms_force_connector_ba...@force-load-detect.html - fi-ivb-3770:[PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-ivb-3770/igt@kms_force_connector_ba...@force-load-detect.html - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-byt-j1900/igt@kms_force_connector_ba...@force-load-detect.html - fi-blb-e6850: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-blb-e6850/igt@kms_force_connector_ba...@force-load-detect.html - fi-snb-2600:[PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-snb-2600/igt@kms_force_connector_ba...@force-load-detect.html - fi-elk-e7500: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-elk-e7500/igt@kms_force_connector_ba...@force-load-detect.html - fi-ilk-650: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-ilk-650/igt@kms_force_connector_ba...@force-load-detect.html - fi-pnv-d510:[PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-pnv-d510/igt@kms_force_connector_ba...@force-load-detect.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-pnv-d510/igt@kms_force_connector_ba...@force-load-detect.html - fi-snb-2520m: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-snb-2520m/igt@kms_force_connector_ba...@force-load-detect.html Known issues Here are the changes found in Patchwork_15042 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-u3: [PASS][19] -> [INCOMPLETE][20] ([fdo#107713] / [fdo#109100]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-icl-u3/igt@gem_ctx_cre...@basic-files.html * igt@gem_ctx_param@basic-default: - fi-apl-guc: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-apl-guc/igt@gem_ctx_pa...@basic-default.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-apl-guc/igt@gem_ctx_pa...@basic-default.html * igt@i915_selftest@live_gem_contexts: - fi-bsw-n3050: [PASS][23] -> [INCOMPLETE][24] ([fdo# 111542]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15042/fi-bsw-n3050/igt@i915_
Re: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-BDW sprites
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-
>BDW sprites
>
>From: Ville Syrjälä
>
>SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose them.
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 16
> 1 file changed, 16 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 633fa8069348..90b0e65420a5 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1054,6 +1054,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB:
> sprctl |= SPRITE_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010 |
>SPRITE_RGB_ORDER_RGBX;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SPRITE_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
> break;
>@@ -1288,6 +1294,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB:
> dvscntr |= DVS_FORMAT_RGBX888;
> break;
>+ case DRM_FORMAT_XBGR2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR;
>+ break;
>+ case DRM_FORMAT_XRGB2101010:
>+ dvscntr |= DVS_FORMAT_RGBX101010;
>+ break;
> case DRM_FORMAT_YUYV:
> dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
> break;
>@@ -1983,6 +1995,8 @@ static const u64 i9xx_plane_format_modifiers[] = {
>static
>const u32 snb_plane_formats[] = {
> DRM_FORMAT_XBGR,
> DRM_FORMAT_XRGB,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
The order seems inconsistent with but I guess you have a patch fixing the
ordering, so should be ok.
Reviewed-by: Uma Shankar
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2193,6 +2207,8 @@ static bool snb_sprite_format_mod_supported(struct
>drm_plane *_plane,
> switch (format) {
> case DRM_FORMAT_XRGB:
> case DRM_FORMAT_XBGR:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
>___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Avoid HPD poll detect triggering a new detect cycle
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle
URL : https://patchwork.freedesktop.org/series/68644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15019_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15019_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@fds:
- {shard-tglb}: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-tglb1/igt@gem_exec_paral...@fds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-tglb6/igt@gem_exec_paral...@fds.html
* igt@gem_sync@basic-each:
- {shard-tglb}: [INCOMPLETE][3] ([fdo#111647]) -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-tglb3/igt@gem_s...@basic-each.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-tglb7/igt@gem_s...@basic-each.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- {shard-tglb}: [PASS][5] -> [SKIP][6] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
Known issues
Here are the changes found in Patchwork_15019_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-none:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080])
+2 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb1/igt@gem_ctx_isolat...@vcs1-none.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb6/igt@gem_ctx_isolat...@vcs1-none.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +16 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb2/igt@gem_ctx_swi...@vcs1-heavy.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb8/igt@gem_ctx_swi...@vcs1-heavy.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#110854])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb1/igt@gem_exec_balan...@smoke.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb7/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_capture@capture-bsd2:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109276]) +18 similar
issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb2/igt@gem_exec_capt...@capture-bsd2.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb8/igt@gem_exec_capt...@capture-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +7 similar
issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb6/igt@gem_exec_sched...@preempt-other-chain-bsd.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-iclb4/igt@gem_exec_sched...@preempt-other-chain-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-apl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103927]) +1
similar issue
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-apl3/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-apl4/igt@gem_persistent_rel...@forked-interruptible-thrash-inactive.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1
similar issue
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-apl3/igt@gem_workarou...@suspend-resume.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15019/shard-apl6/igt@gem_workarou...@suspend-resume.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
- shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([fdo#107713])
[23]:
https://intel-gf
[Intel-gfx] [PATCH] drm/i915/gt: Make timeslice duration configurable
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspace semaphores. However, not all workloads necessarily benefit
from timeslicing and in the extreme some sysadmin may want to disable or
reduce the timeslicing granularity.
The timeslicing mechanism can be compiled out with
./scripts/config --set-val DRM_I915_TIMESLICE_DURATION 0
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/Kconfig.profile | 15
drivers/gpu/drm/i915/gt/intel_engine.h | 9 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 39 ++--
drivers/gpu/drm/i915/gt/selftest_lrc.c | 13 ++-
6 files changed, 65 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.profile
b/drivers/gpu/drm/i915/Kconfig.profile
index 8ab7af5eb311..1799537a3228 100644
--- a/drivers/gpu/drm/i915/Kconfig.profile
+++ b/drivers/gpu/drm/i915/Kconfig.profile
@@ -59,3 +59,18 @@ config DRM_I915_STOP_TIMEOUT
damage as the system is reset in order to recover. The corollary is
that the reset itself may take longer and so be more disruptive to
interactive or low latency workloads.
+
+config DRM_I915_TIMESLICE_DURATION
+ int "Scheduling quantum for userspace batches (ms, jiffy granularity)"
+ default 1 # milliseconds
+ help
+ When two user batches of equal priority are executing, we will
+ alternate execution of each batch to ensure forward progress of
+ all users. This is necessary in some cases where there may be
+ an implicit dependency between those batches that requires
+ concurrent execution in order for them to proceed, e.g. they
+ interact with each other via userspace semaphores. Each context
+ is scheduled for execution for the timeslice duration, before
+ switching to the next context.
+
+ May be 0 to disable timeslicing.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index c6895938b626..0597b77f5818 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -335,4 +335,13 @@ intel_engine_has_preempt_reset(const struct
intel_engine_cs *engine)
return intel_engine_has_preemption(engine);
}
+static inline bool
+intel_engine_has_timeslices(const struct intel_engine_cs *engine)
+{
+ if (!CONFIG_DRM_I915_TIMESLICE_DURATION)
+ return 0;
+
+ return intel_engine_has_semaphores(engine);
+}
+
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9cc1ea6519ec..2afa2ef90482 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -315,6 +315,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum
intel_engine_id id)
CONFIG_DRM_I915_PREEMPT_TIMEOUT;
engine->props.stop_timeout_ms =
CONFIG_DRM_I915_STOP_TIMEOUT;
+ engine->props.timeslice_duration_ms =
+ CONFIG_DRM_I915_TIMESLICE_DURATION;
/*
* To be overridden by the backend on setup. However to facilitate
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e8ea12b96755..c5d1047a4bc5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -523,6 +523,7 @@ struct intel_engine_cs {
unsigned long heartbeat_interval_ms;
unsigned long preempt_timeout_ms;
unsigned long stop_timeout_ms;
+ unsigned long timeslice_duration_ms;
} props;
};
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 2f474c1f5c54..6fb3def5ba16 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1467,7 +1467,7 @@ need_timeslice(struct intel_engine_cs *engine, const
struct i915_request *rq)
{
int hint;
- if (!intel_engine_has_semaphores(engine))
+ if (!intel_engine_has_timeslices(engine))
return false;
if (list_is_last(&rq->sched.link, &engine->active.requests))
@@ -1488,15 +1488,32 @@ switch_prio(struct intel_engine_cs *engine, const
struct i915_request *rq)
return rq_prio(list_next_entry(rq, sched.link));
}
-static bool
-enable_timeslice(const struct intel_engine_execlists *execlists)
+static inline unsigned long
+timeslice(const struct intel_engine_cs *engine)
+{
+ return READ_ONCE(engine->props.timeslice_duration_ms);
+}
Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
On Mon, Oct 28, 2019 at 11:24:22AM +0200, Jani Nikula wrote:
> On Fri, 25 Oct 2019, Changbin Du wrote:
> > On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> >> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> >> > On Sun, 20 Oct 2019 21:17:17 +0800
> >> > Changbin Du wrote:
> >> >
> >> >> The 'functions' directive is not only for functions, but also works for
> >> >> structs/unions. So the name is misleading. This patch renames it to
> >> >> 'identifiers', which specific the functions/types to be included in
> >> >> documentation. We keep the old name as an alias of the new one before
> >> >> all documentation are updated.
> >> >>
> >> >> Signed-off-by: Changbin Du
> >> >
> >> > So I think this is basically OK, but I have one more request...
> >> >
> >> > [...]
> >> >
> >> >> diff --git a/Documentation/sphinx/kerneldoc.py
> >> >> b/Documentation/sphinx/kerneldoc.py
> >> >> index 1159405cb920..0689f9c37f1e 100644
> >> >> --- a/Documentation/sphinx/kerneldoc.py
> >> >> +++ b/Documentation/sphinx/kerneldoc.py
> >> >> @@ -59,9 +59,10 @@ class KernelDocDirective(Directive):
> >> >> optional_arguments = 4
> >> >> option_spec = {
> >> >> 'doc': directives.unchanged_required,
> >> >> -'functions': directives.unchanged,
> >> >> 'export': directives.unchanged,
> >> >> 'internal': directives.unchanged,
> >> >> +'identifiers': directives.unchanged,
> >> >> +'functions': directives.unchanged, # alias of 'identifiers'
> >> >> }
> >> >> has_content = False
> >> >>
> >> >> @@ -71,6 +72,7 @@ class KernelDocDirective(Directive):
> >> >>
> >> >> filename = env.config.kerneldoc_srctree + '/' +
> >> >> self.arguments[0]
> >> >> export_file_patterns = []
> >> >> +identifiers = None
> >> >>
> >> >> # Tell sphinx of the dependency
> >> >> env.note_dependency(os.path.abspath(filename))
> >> >> @@ -86,19 +88,22 @@ class KernelDocDirective(Directive):
> >> >> export_file_patterns =
> >> >> str(self.options.get('internal')).split()
> >> >> elif 'doc' in self.options:
> >> >> cmd += ['-function', str(self.options.get('doc'))]
> >> >> +elif 'identifiers' in self.options:
> >> >> +identifiers = self.options.get('identifiers').split()
> >> >> elif 'functions' in self.options:
> >> >> -functions = self.options.get('functions').split()
> >> >> -if functions:
> >> >> -for f in functions:
> >> >> -cmd += ['-function', f]
> >> >> -else:
> >> >> -cmd += ['-no-doc-sections']
> >> >> +identifiers = self.options.get('functions').split()
> >> >
> >> > Rather than do this, can you just change the elif line to read:
> >> >
> >> > elif ('identifiers' in self.options) or ('functions' in
> >> > self.options):
> >> >
> >> > ...then leave the rest of the code intact? It keeps the logic together,
> >> > and avoids the confusing distinction between identifiers=='' and
> >> > identifiers==None .
> >>
> >> I think the problem is you still need to distinguish between the two for
> >> the get('functions') part.
> >>
> >> One option is to rename 'functions' to 'identifiers' in the above block,
> >> and put something like this above the whole if ladder (untested):
> >>
> >> # backward compat
> >> if 'functions' in self.options:
> >> if 'identifiers' in self.options:
> >> kernellog.warn(env.app, "fail")
> > This will miss the content of 'functions' directive if both exist in
> > same doc.
>
> Did you not notice your patch does the same, except silently, while this
> would produce a warning? Which one is less surprising?
>
yes, my mistake. Mine does the same thing.
> >
> >> else:
> >> self.options.set('identifiers',
> >> self.options.get('functions'))
> >>
> >> BR,
> >> Jani.
> >>
> > After comparing, I still perfer my original code which is simpler. :)
>
> But is it, really? I agree with Jon about the distinction between None
> and '' being confusing.
>
Here python is different from C. Both empty string and None are False in python.
Note such condition is common in python.
Again, I am ok with both.
>
> BR,
> Jani.
>
>
>
> >
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Cheers,
Changbin Du
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: Avoid HPD poll detect triggering a new detect cycle
On Mon, 28 Oct 2019 at 14:16, Imre Deak wrote:
>
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events that may have happened when such a power well was
> off.
>
> Thus a detect cycle started by polling could start a new detect cycle if
> a power well in the display core domain gets enabled during detect and
> stays enabled after detect completes. That in turn can lead to a
> detection cycle runaway.
>
> To prevent re-triggering a poll-detect cycle make sure we drop all power
> references we acquired during detect synchronously by the end of detect.
> This will let the poll-detect logic continue with polling (matching the
> off state of the corresponding power wells) instead of scheduling a new
> detection cycle.
>
> Fixes: 6cfe7ec02e85 ("drm/i915: Remove the unneeded AUX power ref from
> intel_dp_detect()")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112125
> Reported-and-tested-by: Val Kulkov
> Reported-and-tested-by: wangqr
> Cc: Val Kulkov
> Cc: wangqr
> Cc: Ville Syrjälä
> Signed-off-by: Imre Deak
Confirming that this latest revision of the patch fixes the issue.
Tested on linux-drm-tip-git
5.4.865162.dd5bccfa3b5d-1 on Eglobal NUC Fanless Mini PC Intel N3150.
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Re: [Intel-gfx] [RFC 0/3] Display uncore
On Wed, 07 Aug 2019, Daniele Ceraolo Spurio wrote: > I've been trying to identify MMIO ranges to clearly define what belongs > to display_uncore to do a check on access, but there are lots of > exceptions and differences across gens (with a few more coming with TGL), > so I don't think that's a viable way. The alternative option implemented > here is to differentiate the register by type, which should ensure we > never mix them up, but at the cost of a more complex transition. > > Thoughts? I'm very open to (and I actually hope for) better ideas. Has there been any progress in this front lately, or have I just missed it? BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH RESEND 6/8] drm/print: convert debug category macros into an enum
On Tue, 29 Oct 2019, Joonas Lahtinen wrote:
> Quoting Jani Nikula (2019-10-28 12:38:20)
>> Mostly for improved documentation, convert the debug category macros
>> into an enum. Drop unused DRM_UT_NONE. Document previously undocumented
>> categories.
>>
>> Signed-off-by: Jani Nikula
>
>
>
>> +enum drm_debug_category {
>> + /**
>> +* @DRM_UT_CORE: Used in the generic drm code: drm_ioctl.c, drm_mm.c,
>> +* drm_memory.c, ...
>> +*/
>> + DRM_UT_CORE = 0x01,
>
> While here, why not BIT()
Thought about it, but since this is what folks look at when adding the
drm.debug module parameter, it's perhaps easier to combine the hex
values than just the bit positions? *shrug* Could go either way.
BR,
Jani.
>
> Reviewed-by: Joonas Lahtinen
>
> Regards, Joonas
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v6,1/2] drm/i915/cml: Remove unsupport PCI ID
== Series Details == Series: series starting with [v6,1/2] drm/i915/cml: Remove unsupport PCI ID URL : https://patchwork.freedesktop.org/series/68698/ State : failure == Summary == Applying: drm/i915/cml: Remove unsupport PCI ID Applying: drm/i915/cml: Separate U series pci id from origianl list. error: sha1 information is lacking or useless (include/drm/i915_pciids.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/cml: Separate U series pci id from origianl list. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Make timeslice duration configurable
== Series Details ==
Series: drm/i915/gt: Make timeslice duration configurable
URL : https://patchwork.freedesktop.org/series/68701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15044
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/index.html
Known issues
Here are the changes found in Patchwork_15044 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724] /
[fdo#112052 ])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@gem_flink_ba...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-u3/igt@gem_flink_ba...@basic.html
Possible fixes
* igt@gem_exec_create@basic:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +2
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@gem_exec_cre...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-u3/igt@gem_exec_cre...@basic.html
* igt@gem_exec_suspend@basic-s3:
- {fi-cml-s}: [DMESG-WARN][5] ([fdo#111764]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-cml-s/igt@gem_exec_susp...@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-u4}:[DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u4/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-u4/igt@i915_pm_...@module-reload.html
- fi-icl-u3: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-u3/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109635 ]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052
Participating hosts (51 -> 43)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7208 -> Patchwork_15044
CI-20190529: 20190529
CI_DRM_7208: 0e6cec76a950de7c4284f588846616027080ec3d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15044: 89a2657a1a0eb3ec70fcbb613c1cc649a133bbe9 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
89a2657a1a0e drm/i915/gt: Make timeslice duration configurable
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15044/index.html
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[Intel-gfx] [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Auld Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9cc1ea6519ec..355523114c71 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture
Since we have no way access it from the CPU. For such cases just fallback to internal objects. Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/gt/intel_ring.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index fa01c1407760..ece20504d240 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -108,7 +108,9 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct drm_i915_gem_object *obj; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(i915, size); + obj = ERR_PTR(-ENODEV); + if (i915_ggtt_has_aperture(ggtt)) + obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); if (IS_ERR(obj)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/7] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 66 ++-
2 files changed, 65 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 73dad8c6acc2..ba047e329028 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2661,7 +2661,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(&ggtt->error_capture);
+ if (drm_mm_node_allocated(&ggtt->error_capture))
+ drm_mm_remove_node(&ggtt->error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (ggtt->mappable_end) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9bcdcebd2948..d7540c283de8 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = &c->zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -966,7 +969,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -992,17 +994,54 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(&ggtt->error_capture);
+
ret = -EINVAL;
- for_each_sgt_daddr(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(&ggtt->error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_daddr(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
+ ret = compress_page(compress, (void __forc
[Intel-gfx] [PATCH 2/7] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 ++---
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eebc7fee81e2..73dad8c6acc2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2770,7 +2770,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
i915_address_space_fini(&ggtt->vm);
arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
+
+ if (ggtt->iomap.size)
+ io_mapping_fini(&ggtt->iomap);
}
/**
@@ -2997,10 +2999,12 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ if (!IS_DGFX(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3223,14 +3227,17 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
- if (!io_mapping_init_wc(&ggtt->iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(&ggtt->vm);
- return -EIO;
- }
+ if (ggtt->mappable_end) {
+ if (!io_mapping_init_wc(&ggtt->iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(&ggtt->vm);
+ return -EIO;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
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[Intel-gfx] [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f074f1de66e8..2809aa41 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -575,6 +575,11 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
int i915_init_ggtt(struct drm_i915_private *dev_priv);
void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
+static inline bool i915_ggtt_has_aperture(struct i915_ggtt *ggtt)
+{
+ return ggtt->mappable_end > 0;
+}
+
int i915_ppgtt_init_hw(struct intel_gt *gt);
struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
--
2.20.1
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[Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 321189e1b0f2..71efccfde122 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(ggtt); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!i915_ggtt_has_aperture(ggtt)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 7/7] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 4
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 0a195e5b98e6..279e9047bc6d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -250,7 +250,10 @@ static bool always_valid(struct context *ctx)
static bool needs_fence_registers(struct context *ctx)
{
- return !intel_gt_is_wedged(ctx->engine->gt);
+ if (intel_gt_is_wedged(ctx->engine->gt))
+ return false;
+
+ return ctx->engine->gt->ggtt->num_fences;
}
static bool needs_mi_store_dword(struct context *ctx)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index d45a93928ff5..29b2077b73d2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -301,6 +301,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!i915_ggtt_has_aperture(&i915->ggtt))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -431,6 +434,9 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
+ if (!i915_ggtt_has_aperture(&i915->ggtt))
+ return 0;
+
/*
* igt_partial_tiling() does an exhastive check of partial tiling
* chunking, but will undoubtably run out of time. Here, we do a
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index b7207b488391..8abc0a1d692b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1149,8 +1149,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1186,10 +1190,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 6d22567ad620..e378543ed453 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -45,6 +45,10 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ /* XXX: fsck. needs some more thought... */
+ if (!i915_ggtt_has_aperture(ggtt))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index a1cb072e4a1b..3f7e80fb3bbd 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1149,6 +1149,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!i915_ggtt_has_aperture(ggtt))
+ return 0;
+
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.20.1
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Re: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV primary planes
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV
>primary
>planes
>
>From: Ville Syrjälä
>
>Currently we expose VLV/CHV alpha blending only on the sprite planes, but the
>primary planes can do it as well. Let's flip it on.
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_display.c | 57 +++-
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 57 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1a533ccdb54f..1cdcd0ea0564 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -98,6 +98,20 @@ static const u32 i965_primary_formats[] = {
> DRM_FORMAT_XBGR2101010,
> };
>
>+/* Primary plane formats for vlv/chv */ static const u32
>+vlv_primary_formats[] = {
>+ DRM_FORMAT_C8,
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_XRGB,
>+ DRM_FORMAT_XBGR,
>+ DRM_FORMAT_ARGB,
>+ DRM_FORMAT_ABGR,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
>+};
>+
> static const u64 i9xx_format_modifiers[] = {
> I915_FORMAT_MOD_X_TILED,
> DRM_FORMAT_MOD_LINEAR,
>@@ -2952,6 +2966,8 @@ static int i9xx_format_to_fourcc(int format)
> switch (format) {
> case DISPPLANE_8BPP:
> return DRM_FORMAT_C8;
>+ case DISPPLANE_BGRA555:
>+ return DRM_FORMAT_ARGB1555;
> case DISPPLANE_BGRX555:
> return DRM_FORMAT_XRGB1555;
> case DISPPLANE_BGRX565:
>@@ -2961,10 +2977,18 @@ static int i9xx_format_to_fourcc(int format)
> return DRM_FORMAT_XRGB;
> case DISPPLANE_RGBX888:
> return DRM_FORMAT_XBGR;
>+ case DISPPLANE_BGRA888:
>+ return DRM_FORMAT_ARGB;
>+ case DISPPLANE_RGBA888:
>+ return DRM_FORMAT_ABGR;
> case DISPPLANE_BGRX101010:
> return DRM_FORMAT_XRGB2101010;
> case DISPPLANE_RGBX101010:
> return DRM_FORMAT_XBGR2101010;
>+ case DISPPLANE_BGRA101010:
>+ return DRM_FORMAT_ARGB2101010;
>+ case DISPPLANE_RGBA101010:
>+ return DRM_FORMAT_ABGR2101010;
> }
> }
>
>@@ -3639,6 +3663,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XRGB1555:
> dspcntr |= DISPPLANE_BGRX555;
> break;
>+ case DRM_FORMAT_ARGB1555:
>+ dspcntr |= DISPPLANE_BGRA555;
>+ break;
> case DRM_FORMAT_RGB565:
> dspcntr |= DISPPLANE_BGRX565;
> break;
>@@ -3648,12 +3675,24 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_XBGR:
> dspcntr |= DISPPLANE_RGBX888;
> break;
>+ case DRM_FORMAT_ARGB:
>+ dspcntr |= DISPPLANE_BGRA888;
>+ break;
>+ case DRM_FORMAT_ABGR:
>+ dspcntr |= DISPPLANE_RGBA888;
>+ break;
> case DRM_FORMAT_XRGB2101010:
> dspcntr |= DISPPLANE_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> dspcntr |= DISPPLANE_RGBX101010;
> break;
>+ case DRM_FORMAT_ARGB2101010:
>+ dspcntr |= DISPPLANE_BGRA101010;
>+ break;
>+ case DRM_FORMAT_ABGR2101010:
>+ dspcntr |= DISPPLANE_RGBA101010;
>+ break;
> default:
> MISSING_CASE(fb->format->format);
> return 0;
>@@ -14634,8 +14673,12 @@ static bool i965_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB:
> case DRM_FORMAT_XBGR:
>+ case DRM_FORMAT_ARGB:
>+ case DRM_FORMAT_ABGR:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return modifier == DRM_FORMAT_MOD_LINEAR ||
> modifier == I915_FORMAT_MOD_X_TILED;
> default:
>@@ -14855,7 +14898,19 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> fbc->possible_framebuffer_bits |= plane->frontbuffer_bit;
> }
>
>- if (INTEL_GEN(dev_priv) >= 4) {
>+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>+ formats = vlv_primary_formats;
>+ num_formats = ARRAY_SIZE(vlv_primary_formats);
>+ modifiers = i9xx_format_modifiers;
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disab
Re: [Intel-gfx] [PATCH 1/7] drm/i915: define i915_ggtt_has_aperture
Quoting Matthew Auld (2019-10-29 09:58:50) > From: Daniele Ceraolo Spurio > > The following patches in the series will use it to avoid certain > operations when the mappable aperture is not available in HW. > > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/7] drm/i915: do not map aperture if it is not available.
Quoting Matthew Auld (2019-10-29 09:58:51) > From: Daniele Ceraolo Spurio > > Skip both setup and cleanup of the aperture mapping if the HW doesn't > have an aperture bar. > > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Matthew Auld > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 31 ++--- > 1 file changed, 19 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index eebc7fee81e2..73dad8c6acc2 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2770,7 +2770,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt) > i915_address_space_fini(&ggtt->vm); > > arch_phys_wc_del(ggtt->mtrr); > - io_mapping_fini(&ggtt->iomap); > + > + if (ggtt->iomap.size) > + io_mapping_fini(&ggtt->iomap); Marginally annoying we had not made io_mapping_fini() nop-proof. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dp: Do not switch aux to TBT mode for non-TC ports
On Mon, Oct 28, 2019 at 06:10:14PM -0700, José Roberto de Souza wrote:
> Non-TC ports always have tc_mode == TC_PORT_TBT_ALT so it was
> switching aux to TC mode for all combo-phy ports, happily this did
> not caused any issue but is better follow BSpec.
> Also this is reserved bit before ICL.
>
> Fixes: 6f211ed43438 ("drm/i915/icl: Set TBT IO in Aux transaction")
This actually
Fixes: e9b7e1422d40 ("drm/i915: Sanitize the terminology used for TypeC port
modes")
thanks for spotting it.
> Cc: Imre Deak
> Signed-off-by: José Roberto de Souza
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 86989ec25bc6..379623397301 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1291,6 +1291,9 @@ static u32 skl_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> u32 unused)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *i915 =
> + to_i915(intel_dig_port->base.base.dev);
> + enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
> u32 ret;
>
> ret = DP_AUX_CH_CTL_SEND_BUSY |
> @@ -1303,7 +1306,8 @@ static u32 skl_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
>
> - if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> + if (intel_phy_is_tc(i915, phy) &&
> + intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> ret |= DP_AUX_CH_CTL_TBT_IO;
>
> return ret;
> --
> 2.23.0
>
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Re: [Intel-gfx] [PATCH 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
Quoting Matthew Auld (2019-10-29 09:58:52) > From: Daniele Ceraolo Spurio > > We can't fence anything without aperture. > > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Stuart Summers > Signed-off-by: Matthew Auld Neat. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/7] drm/i915: error capture with no ggtt slot
Quoting Matthew Auld (2019-10-29 09:58:53)
> From: Daniele Ceraolo Spurio
>
> If the aperture is not available in HW we can't use a ggtt slot and wc
> copy, so fall back to regular kmap.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
> ---
> + } else if (i915_gem_object_is_lmem(vma->obj)) {
> + struct intel_memory_region *mem = vma->obj->mm.region;
> + dma_addr_t dma;
> +
> + for_each_sgt_daddr(dma, iter, vma->pages) {
> + void __iomem *s;
> +
> + s = io_mapping_map_atomic_wc(&mem->iomap, dma);
> + ret = compress_page(compress, s, dst);
Just a (void __force *)s required here.
Reviewed-by: Chris Wilson
-Chris
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Re: [Intel-gfx] [PATCH 5/7] drm/i915: Don't try to place HWS in non-existing mappable region
Quoting Matthew Auld (2019-10-29 09:58:54) > From: Michal Wajdeczko > > HWS placement restrictions can't just rely on HAS_LLC flag. > > Signed-off-by: Michal Wajdeczko > Signed-off-by: Matthew Auld > Cc: Daniele Ceraolo Spurio > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 9cc1ea6519ec..355523114c71 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs > *engine, > unsigned int flags; > > flags = PIN_GLOBAL; > - if (!HAS_LLC(engine->i915)) > + if (!HAS_LLC(engine->i915) && > i915_ggtt_has_aperture(engine->gt->ggtt)) > /* > * On g33, we cannot place HWS above 256MiB, so > * restrict its pinning to the low mappable arena. How we will laugh if it turns out future HW cannot handle having the HWSP placed anywhere! :) Acked-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture
Quoting Matthew Auld (2019-10-29 09:58:55) > Since we have no way access it from the CPU. For such cases just > fallback to internal objects. > > Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/7] drm/i915/selftests: check for missing aperture
Quoting Matthew Auld (2019-10-29 09:58:56)
> We may be missing support for the mappable aperture on some platforms.
>
> Signed-off-by: Matthew Auld
> Cc: Daniele Ceraolo Spurio
> ---
> .../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
> drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
> drivers/gpu/drm/i915/selftests/i915_gem.c | 4
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
> 5 files changed, 27 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> index 0a195e5b98e6..279e9047bc6d 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
> @@ -250,7 +250,10 @@ static bool always_valid(struct context *ctx)
>
> static bool needs_fence_registers(struct context *ctx)
> {
I vote for a struct intel_gt *gt = ctx->engine->gt;
> - return !intel_gt_is_wedged(ctx->engine->gt);
> + if (intel_gt_is_wedged(ctx->engine->gt))
> + return false;
> +
> + return ctx->engine->gt->ggtt->num_fences;
> }
Reviewed-by: Chris Wilson
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/6] drm/i915: Fix i845/i865 cursor width
== Series Details == Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width URL : https://patchwork.freedesktop.org/series/68646/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15021_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_15021_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15021_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_15021_full: ### IGT changes ### Possible regressions * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-skl10/igt@kms_rotation_...@multiplane-rotation-cropping-bottom.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-skl3/igt@kms_rotation_...@multiplane-rotation-cropping-bottom.html Known issues Here are the changes found in Patchwork_15021_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-skl6/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-skl1/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [fdo#112080]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb4/igt@gem_ctx_isolat...@vcs1-reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-iclb8/igt@gem_ctx_isolat...@vcs1-reset.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb6/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-iclb1/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_ctx_switch@vcs1-heavy-queue: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112080]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb2/igt@gem_ctx_swi...@vcs1-heavy-queue.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-iclb3/igt@gem_ctx_swi...@vcs1-heavy-queue.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#110854]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb1/igt@gem_exec_balan...@smoke.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-iclb6/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@out-order-bsd1: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109276]) +10 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb2/igt@gem_exec_sched...@out-order-bsd1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-iclb3/igt@gem_exec_sched...@out-order-bsd1.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html - shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-apl3/igt@gem_workarou...@suspend-resume-context.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-apl6/igt@gem_workarou...@suspend-resume-context.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: [PASS][21] -> [FAIL][22] ([fdo#105363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-apl3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15021/shard-apl6/igt@kms_f...@flip-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
== Series Details == Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture URL : https://patchwork.freedesktop.org/series/68705/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6d8f88fa8405 drm/i915: define i915_ggtt_has_aperture d802efde66e4 drm/i915: do not map aperture if it is not available. -:38: CHECK:SPACING: No space is necessary after a cast #38: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:3004: + (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2), total: 0 errors, 0 warnings, 1 checks, 50 lines checked a7a2178c7393 drm/i915: set num_fence_regs to 0 if there is no aperture 7cfb9135592b drm/i915: error capture with no ggtt slot 8bb585d4866a drm/i915: Don't try to place HWS in non-existing mappable region 1c42b31bf095 drm/i915: don't allocate the ring in stolen if we lack aperture 5a85b5a48a60 drm/i915/selftests: check for missing aperture ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check a few more fixed locations within the context image (rev2)
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image (rev2)
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15022_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_15022_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_userptr_blits@stress-purge}:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-skl7/igt@gem_userptr_bl...@stress-purge.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-skl3/igt@gem_userptr_bl...@stress-purge.html
Known issues
Here are the changes found in Patchwork_15022_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080])
+1 similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb4/igt@gem_ctx_isolat...@vcs1-reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-iclb5/igt@gem_ctx_isolat...@vcs1-reset.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +12 similar
issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb2/igt@gem_ctx_swi...@vcs1-heavy.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-iclb3/igt@gem_ctx_swi...@vcs1-heavy.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#109661])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-snb5/igt@gem_...@reset-stress.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-snb7/igt@gem_...@reset-stress.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +16 similar
issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb4/igt@gem_exec_sched...@fifo-bsd1.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-iclb5/igt@gem_exec_sched...@fifo-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +6 similar
issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb5/igt@gem_exec_sched...@preemptive-hang-bsd.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-skl4/igt@gem_soft...@noreloc-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-skl10/igt@gem_soft...@noreloc-s3.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-snb7/igt@gem_userptr_bl...@dmabuf-sync.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-snb1/igt@gem_userptr_bl...@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-hsw2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2
similar issues
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-kbl4/igt@gem_workarou...@suspend-resume-fd.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-kbl6/igt@gem_workarou...@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-apl8/igt@kms_cursor_...@pipe-c-cursor-suspend.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15022/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +7 similar
issues
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7201/shard-iclb6/igt@kms_frontbuffer_track
[Intel-gfx] [RESEND PATCH i-g-t v2 1/1] tests/i915_module_load: Use new name of fault injection module parameter
Name of the i915 module parameter providing fault injection function is
changing for consistency with a new convention of naming i915 driver
internal functions called from the driver PCI .probe entry point. Adjust
the test to use the new name.
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
tests/i915/i915_module_load.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index 7fe83520..a620ab41 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -356,7 +356,7 @@ igt_main
igt_i915_driver_unload();
- while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+ while (inject_fault("i915", "inject_probe_failure", ++i) == 0)
;
/* We expect to hit at least one fault! */
--
2.21.0
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[Intel-gfx] [RESEND PATCH i-g-t v2 0/1] tests/i915_module_load: Use new name of fault injection module parameter
Name of the i915 module parameter providing fault injection function is changing for consistency with a new convention of naming i915 driver internal functions called from the driver PCI .probe entry point. Adjust the test to use the new name. v2: * add R-b (thanks Chris), * add cover letter to correctly support joint testing with a corresponding kernel driver side patch. Janusz Krzysztofik (1): tests/i915_module_load: Use new name of fault injection module parameter tests/i915/i915_module_load.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
== Series Details == Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture URL : https://patchwork.freedesktop.org/series/68705/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: define i915_ggtt_has_aperture Okay! Commit: drm/i915: do not map aperture if it is not available. Okay! Commit: drm/i915: set num_fence_regs to 0 if there is no aperture Okay! Commit: drm/i915: error capture with no ggtt slot - +drivers/gpu/drm/i915/i915_gpu_error.c:1023:55:expected void *src +drivers/gpu/drm/i915/i915_gpu_error.c:1023:55:got void [noderef] *[assigned] s +drivers/gpu/drm/i915/i915_gpu_error.c:1023:55: warning: incorrect type in argument 2 (different address spaces) Commit: drm/i915: Don't try to place HWS in non-existing mappable region Okay! Commit: drm/i915: don't allocate the ring in stolen if we lack aperture Okay! Commit: drm/i915/selftests: check for missing aperture Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RESUBMIT PATCH v2 2/2] drm/i915: Rename "inject_load_failure" module parameter
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
consequently") deliberately left the name of the module parameter
unchanged as that would require a corresponding change on IGT size.
Now as the IGT side change has been submitted, complete the switch to
the "probe" nomenclature.
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_params.c | 2 +-
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_utils.c | 10 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 4f1806f65040..3fa79adb2c1c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -166,7 +166,7 @@ i915_param_named_unsafe(enable_dp_mst, bool, 0600,
"Enable multi-stream transport (MST) for new DisplayPort sinks.
(default: true)");
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
-i915_param_named_unsafe(inject_load_failure, uint, 0400,
+i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
#endif
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 56058978bb27..a276317ad74b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -62,7 +62,7 @@ struct drm_printer;
param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO)) \
param(int, edp_vswing, 0) \
param(int, reset, 3) \
- param(unsigned int, inject_load_failure, 0) \
+ param(unsigned int, inject_probe_failure, 0) \
param(int, fastboot, -1) \
param(int, enable_dpcd_backlight, 0) \
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE) \
diff --git a/drivers/gpu/drm/i915/i915_utils.c
b/drivers/gpu/drm/i915/i915_utils.c
index abe81ddde20e..0348c6d0ef5f 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -57,22 +57,22 @@ static unsigned int i915_probe_fail_count;
int __i915_inject_probe_error(struct drm_i915_private *i915, int err,
const char *func, int line)
{
- if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
+ if (i915_probe_fail_count >= i915_modparams.inject_probe_failure)
return 0;
- if (++i915_probe_fail_count < i915_modparams.inject_load_failure)
+ if (++i915_probe_fail_count < i915_modparams.inject_probe_failure)
return 0;
__i915_printk(i915, KERN_INFO,
"Injecting failure %d at checkpoint %u [%s:%d]\n",
- err, i915_modparams.inject_load_failure, func, line);
- i915_modparams.inject_load_failure = 0;
+ err, i915_modparams.inject_probe_failure, func, line);
+ i915_modparams.inject_probe_failure = 0;
return err;
}
bool i915_error_injected(void)
{
- return i915_probe_fail_count && !i915_modparams.inject_load_failure;
+ return i915_probe_fail_count && !i915_modparams.inject_probe_failure;
}
#endif
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RESUBMIT PATCH v2 1/2] drm/i915: Fix i915_inject_load_error() name to read *_probe_*
Commit 50d84418f586 ("drm/i915: Add i915 to i915_inject_probe_failure")
introduced new functions unfortunately named incompatibly with rules
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
"_probe" consequently"). Fix it for consistency.
Suggested-by: Michał Wajdeczko
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++-
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.c | 4 ++--
drivers/gpu/drm/i915/i915_utils.h | 12 +--
7 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 009e54a3764f..3d83e4146208 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1125,7 +1125,7 @@ int intel_guc_submission_enable(struct intel_guc *guc)
enum intel_engine_id id;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 8be515c8d0f0..32a069841c14 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -63,7 +63,7 @@ static int intel_huc_rsa_data_create(struct intel_huc *huc)
void *vaddr;
int err;
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
@@ -161,7 +161,7 @@ int intel_huc_auth(struct intel_huc *huc)
if (!intel_uc_fw_is_loaded(&huc->fw))
return -ENOEXEC;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3fdbc935d155..629b19377a29 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -20,7 +20,7 @@ static int __intel_uc_reset_hw(struct intel_uc *uc)
int ret;
u32 guc_status;
- ret = i915_inject_load_error(gt->i915, -ENXIO);
+ ret = i915_inject_probe_error(gt->i915, -ENXIO);
if (ret)
return ret;
@@ -197,7 +197,7 @@ static int guc_enable_communication(struct intel_guc *guc)
GEM_BUG_ON(guc_communication_enabled(guc));
- ret = i915_inject_load_error(i915, -ENXIO);
+ ret = i915_inject_probe_error(i915, -ENXIO);
if (ret)
return ret;
@@ -372,7 +372,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK));
GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK);
- err = i915_inject_load_error(gt->i915, -ENXIO);
+ err = i915_inject_probe_error(gt->i915, -ENXIO);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bb4889d2346d..26beccff0908 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -220,29 +220,31 @@ static void __force_fw_fetch_failures(struct intel_uc_fw
*uc_fw,
{
bool user = e == -EINVAL;
- if (i915_inject_load_error(i915, e)) {
+ if (i915_inject_probe_error(i915, e)) {
/* non-existing blob */
uc_fw->path = "";
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next major version */
uc_fw->major_ver_wanted += 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (i915_inject_load_error(i915, e)) {
+ } else if (i915_inject_probe_error(i915, e)) {
/* require next minor version */
uc_fw->minor_ver_wanted += 1;
uc_fw->user_overridden = user;
- } else if (uc_fw->major_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if (uc_fw->major_ver_wanted &&
+ i915_inject_probe_error(i915, e)) {
/* require prev major version */
uc_fw->major_ver_wanted -= 1;
uc_fw->minor_ver_wanted = 0;
uc_fw->user_overridden = user;
- } else if (uc_fw->minor_ver_wanted && i915_inject_load_error(i915, e)) {
+ } else if (uc_f
[Intel-gfx] [RESUBMIT PATCH v2 0/2] drm/i915: Conclude load -> probe naming convention switch
Test-with: <20191029101751.5848-2-janusz.krzyszto...@linux.intel.com> The purpose is: * to fix incompatible names of new functions introduced meanwhile, * to complete postponed rename of module parameter. v2: * drop unnecessary statement about custom user applications from commit message of 2/2, there are no such (Chris), * add R-b (thanks Chris), * use correct message ID of (also rerolled) IGT counterpart to be tested with. Janusz Krzysztofik (2): drm/i915: Fix i915_inject_load_error() name to read *_probe_* drm/i915: Rename "inject_load_failure" module parameter .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_huc.c| 4 ++-- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 6 +++--- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 20 ++- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/gpu/drm/i915/i915_params.c| 2 +- drivers/gpu/drm/i915/i915_params.h| 2 +- drivers/gpu/drm/i915/i915_utils.c | 14 ++--- drivers/gpu/drm/i915/i915_utils.h | 12 +-- 9 files changed, 34 insertions(+), 32 deletions(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_15031 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15031, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_15031:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-kbl-guc: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_15031 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-read-noreloc:
- fi-icl-u3: [PASS][2] -> [DMESG-WARN][3] ([fdo#107724]) +1
similar issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [PASS][4] -> [TIMEOUT][5] ([fdo#112162])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-guc/igt@i915_selftest@live_blt.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-icl-u2: [PASS][6] -> [TIMEOUT][7] ([fdo#112162])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@i915_selftest@live_blt.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-whl-u: [PASS][8] -> [INCOMPLETE][9] ([fdo#112162])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-whl-u/igt@i915_selftest@live_client.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-whl-u/igt@i915_selftest@live_client.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][10] -> [FAIL][11] ([fdo#109570])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][12] ([fdo#103927] / [fdo#111381]) ->
[PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][14] ([fdo#107724]) -> [PASS][15] +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* igt@i915_selftest@live_blt:
- fi-glk-dsi: [TIMEOUT][16] ([fdo#112162]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-glk-dsi/igt@i915_selftest@live_blt.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-cfl-8700k: [TIMEOUT][18] ([fdo#112162]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-cfl-8700k/igt@i915_selftest@live_blt.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-cfl-8700k/igt@i915_selftest@live_blt.html
- fi-skl-iommu: [TIMEOUT][20] ([fdo#112162]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-skl-iommu/igt@i915_selftest@live_blt.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-skl-iommu/igt@i915_selftest@live_blt.html
- {fi-tgl-u}: [TIMEOUT][22] ([fdo#112162]) -> [PASS][23]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-tgl-u/igt@i915_selftest@live_blt.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-tgl-u/igt@i915_selftest@live_blt.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][24] ([fdo#102505] / [fdo#106107] /
[fdo#110390]) -> [DMESG-WARN][25] ([fdo#102505] / [fdo#110390])
[Intel-gfx] [PATCH v2 7/7] drm/i915/selftests: check for missing aperture
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 7 ++-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++
drivers/gpu/drm/i915/selftests/i915_gem.c | 4
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++
5 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index 0a195e5b98e6..2b29f6b4e1dd 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -250,7 +250,12 @@ static bool always_valid(struct context *ctx)
static bool needs_fence_registers(struct context *ctx)
{
- return !intel_gt_is_wedged(ctx->engine->gt);
+ struct intel_gt *gt = ctx->engine->gt;
+
+ if (intel_gt_is_wedged(gt))
+ return false;
+
+ return gt->ggtt->num_fences;
}
static bool needs_mi_store_dword(struct context *ctx)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index d45a93928ff5..29b2077b73d2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -301,6 +301,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!i915_ggtt_has_aperture(&i915->ggtt))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -431,6 +434,9 @@ static int igt_smoke_tiling(void *arg)
IGT_TIMEOUT(end);
int err;
+ if (!i915_ggtt_has_aperture(&i915->ggtt))
+ return 0;
+
/*
* igt_partial_tiling() does an exhastive check of partial tiling
* chunking, but will undoubtably run out of time. Here, we do a
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index b7207b488391..8abc0a1d692b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1149,8 +1149,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1186,10 +1190,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c
b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 6d22567ad620..e378543ed453 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -45,6 +45,10 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ /* XXX: fsck. needs some more thought... */
+ if (!i915_ggtt_has_aperture(ggtt))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index a1cb072e4a1b..3f7e80fb3bbd 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1149,6 +1149,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!i915_ggtt_has_aperture(ggtt))
+ return 0;
+
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/7] drm/i915: define i915_ggtt_has_aperture
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f074f1de66e8..2809aa41 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -575,6 +575,11 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
int i915_init_ggtt(struct drm_i915_private *dev_priv);
void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
+static inline bool i915_ggtt_has_aperture(struct i915_ggtt *ggtt)
+{
+ return ggtt->mappable_end > 0;
+}
+
int i915_ppgtt_init_hw(struct intel_gt *gt);
struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 6/7] drm/i915: don't allocate the ring in stolen if we lack aperture
Since we have no way access it from the CPU. For such cases just fallback to internal objects. Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_ring.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index fa01c1407760..ece20504d240 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -108,7 +108,9 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct drm_i915_gem_object *obj; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(i915, size); + obj = ERR_PTR(-ENODEV); + if (i915_ggtt_has_aperture(ggtt)) + obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); if (IS_ERR(obj)) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/7] drm/i915: do not map aperture if it is not available.
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 ++---
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eebc7fee81e2..73dad8c6acc2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2770,7 +2770,9 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
i915_address_space_fini(&ggtt->vm);
arch_phys_wc_del(ggtt->mtrr);
- io_mapping_fini(&ggtt->iomap);
+
+ if (ggtt->iomap.size)
+ io_mapping_fini(&ggtt->iomap);
}
/**
@@ -2997,10 +2999,12 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
- ggtt->gmadr =
- (struct resource) DEFINE_RES_MEM(pci_resource_start(pdev, 2),
-pci_resource_len(pdev, 2));
- ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ if (!IS_DGFX(dev_priv)) {
+ ggtt->gmadr =
+ (struct resource)
DEFINE_RES_MEM(pci_resource_start(pdev, 2),
+pci_resource_len(pdev,
2));
+ ggtt->mappable_end = resource_size(&ggtt->gmadr);
+ }
err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
if (!err)
@@ -3223,14 +3227,17 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
- if (!io_mapping_init_wc(&ggtt->iomap,
- ggtt->gmadr.start,
- ggtt->mappable_end)) {
- ggtt->vm.cleanup(&ggtt->vm);
- return -EIO;
- }
+ if (ggtt->mappable_end) {
+ if (!io_mapping_init_wc(&ggtt->iomap,
+ ggtt->gmadr.start,
+ ggtt->mappable_end)) {
+ ggtt->vm.cleanup(&ggtt->vm);
+ return -EIO;
+ }
- ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
+ ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
+ ggtt->mappable_end);
+ }
i915_ggtt_init_fences(ggtt);
--
2.20.1
___
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[Intel-gfx] [PATCH v2 4/7] drm/i915: error capture with no ggtt slot
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
drivers/gpu/drm/i915/i915_gpu_error.c | 66 ++-
2 files changed, 65 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 73dad8c6acc2..ba047e329028 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2661,7 +2661,8 @@ static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
{
ggtt_release_guc_top(ggtt);
- drm_mm_remove_node(&ggtt->error_capture);
+ if (drm_mm_node_allocated(&ggtt->error_capture))
+ drm_mm_remove_node(&ggtt->error_capture);
}
static int init_ggtt(struct i915_ggtt *ggtt)
@@ -2692,13 +2693,15 @@ static int init_ggtt(struct i915_ggtt *ggtt)
if (ret)
return ret;
- /* Reserve a mappable slot for our lockless error capture */
- ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->error_capture,
- PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
- 0, ggtt->mappable_end,
- DRM_MM_INSERT_LOW);
- if (ret)
- return ret;
+ if (ggtt->mappable_end) {
+ /* Reserve a mappable slot for our lockless error capture */
+ ret = drm_mm_insert_node_in_range(&ggtt->vm.mm,
&ggtt->error_capture,
+ PAGE_SIZE, 0,
I915_COLOR_UNEVICTABLE,
+ 0, ggtt->mappable_end,
+ DRM_MM_INSERT_LOW);
+ if (ret)
+ return ret;
+ }
/*
* The upper portion of the GuC address space has a sizeable hole
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9bcdcebd2948..7672d4c4552f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -40,6 +40,7 @@
#include "display/intel_overlay.h"
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_lmem.h"
#include "i915_drv.h"
#include "i915_gpu_error.h"
@@ -235,6 +236,7 @@ struct compress {
struct pagevec pool;
struct z_stream_s zstream;
void *tmp;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -292,7 +294,7 @@ static int compress_page(struct compress *c,
struct z_stream_s *zstream = &c->zstream;
zstream->next_in = src;
- if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
+ if (c->wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
zstream->next_in = c->tmp;
zstream->avail_in = PAGE_SIZE;
@@ -367,6 +369,7 @@ static void err_compression_marker(struct
drm_i915_error_state_buf *m)
struct compress {
struct pagevec pool;
+ bool wc;
};
static bool compress_init(struct compress *c)
@@ -389,7 +392,7 @@ static int compress_page(struct compress *c,
if (!ptr)
return -ENOMEM;
- if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
+ if (!(c->wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
memcpy(ptr, src, PAGE_SIZE);
dst->pages[dst->page_count++] = ptr;
@@ -966,7 +969,6 @@ i915_error_object_create(struct drm_i915_private *i915,
struct drm_i915_error_object *dst;
unsigned long num_pages;
struct sgt_iter iter;
- dma_addr_t dma;
int ret;
might_sleep();
@@ -992,17 +994,54 @@ i915_error_object_create(struct drm_i915_private *i915,
dst->page_count = 0;
dst->unused = 0;
+ compress->wc = i915_gem_object_is_lmem(vma->obj) ||
+ drm_mm_node_allocated(&ggtt->error_capture);
+
ret = -EINVAL;
- for_each_sgt_daddr(dma, iter, vma->pages) {
+ if (drm_mm_node_allocated(&ggtt->error_capture)) {
void __iomem *s;
+ dma_addr_t dma;
- ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
+ for_each_sgt_daddr(dma, iter, vma->pages) {
+ ggtt->vm.insert_page(&ggtt->vm, dma, slot,
+I915_CACHE_NONE, 0);
- s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
- ret = compress_page(compress, (void __force *)s, dst);
- io_mapping_unmap(s);
- if (ret)
- break;
+ s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
+ ret = compress_p
[Intel-gfx] [PATCH v2 5/7] drm/i915: Don't try to place HWS in non-existing mappable region
From: Michal Wajdeczko HWS placement restrictions can't just rely on HAS_LLC flag. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Auld Cc: Daniele Ceraolo Spurio Acked-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 9cc1ea6519ec..355523114c71 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -528,7 +528,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, unsigned int flags; flags = PIN_GLOBAL; - if (!HAS_LLC(engine->i915)) + if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt)) /* * On g33, we cannot place HWS above 256MiB, so * restrict its pinning to the low mappable arena. -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/7] drm/i915: set num_fence_regs to 0 if there is no aperture
From: Daniele Ceraolo Spurio We can't fence anything without aperture. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Stuart Summers Signed-off-by: Matthew Auld Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 321189e1b0f2..71efccfde122 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt) detect_bit_6_swizzle(ggtt); - if (INTEL_GEN(i915) >= 7 && - !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) + if (!i915_ggtt_has_aperture(ggtt)) + num_fences = 0; + else if (INTEL_GEN(i915) >= 7 && +!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) num_fences = 32; else if (INTEL_GEN(i915) >= 4 || IS_I945G(i915) || IS_I945GM(i915) || -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
>
>From: Ville Syrjälä
>
>VLV/CHV sprite planes also support the C8 format. Let's expose that.
Looks good to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index fb36da58390a..4cd0982dc8a2 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -846,6 +846,9 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_VYUY:
> sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
> break;
>+ case DRM_FORMAT_C8:
>+ sprctl |= SP_FORMAT_8BPP;
>+ break;
> case DRM_FORMAT_RGB565:
> sprctl |= SP_FORMAT_BGR565;
> break;
>@@ -2010,6 +2013,7 @@ static const u32 snb_plane_formats[] = { };
>
> static const u32 vlv_plane_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR,
> DRM_FORMAT_ARGB,
>@@ -2024,6 +2028,7 @@ static const u32 vlv_plane_formats[] = { };
>
> static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
> DRM_FORMAT_ABGR,
> DRM_FORMAT_ARGB,
>@@ -2256,6 +2261,7 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> }
>
> switch (format) {
>+ case DRM_FORMAT_C8:
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_ABGR:
> case DRM_FORMAT_ARGB:
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index
>74bb5a6cbe4f..577468928ffa 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6546,6 +6546,7 @@ enum {
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
> #define SP_FORMAT_YUV422(0x0 << 26)
>+#define SP_FORMAT_8BPP (0x2 << 26)
> #define SP_FORMAT_BGR565(0x5 << 26)
> #define SP_FORMAT_BGRX (0x6 << 26)
> #define SP_FORMAT_BGRA (0x7 << 26)
>--
>2.21.0
>
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>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
== Series Details ==
Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68705/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15045
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/index.html
Known issues
Here are the changes found in Patchwork_15045 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u3/igt@gem_mmap_...@basic-small-bo-tiledy.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_exec_create@basic:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +2
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@gem_exec_cre...@basic.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u3/igt@gem_exec_cre...@basic.html
* igt@i915_pm_rpm@module-reload:
- {fi-icl-u4}:[DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u4/igt@i915_pm_...@module-reload.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u4/igt@i915_pm_...@module-reload.html
- fi-icl-u3: [DMESG-WARN][9] ([fdo#106107]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u3/igt@i915_pm_...@module-reload.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u3/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live_execlists:
- {fi-icl-guc}: [INCOMPLETE][11] ([fdo#107713]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-guc/igt@i915_selftest@live_execlists.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-guc/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][13] ([fdo#102505] / [fdo#110390]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [FAIL][15] ([fdo#109635 ]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7208/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15045/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
Participating hosts (51 -> 43)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7208 -> Patchwork_15045
CI-20190529: 20190529
CI_DRM_7208: 0e6cec76a950de7c4284f588846616027080ec3d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5248: 81e55f1f97d73e48f00caa7e4fb98295023c5afa @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15045: 5a85b5a48a60eca3deee049cfa34597569b22498 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5a85b5a48a60 drm/i915/selftests: check for missing aperture
1c42b31bf095 drm/i915: don't allocate the ring in stolen if we lack aperture
8bb585d4866a drm/i915: Don't try to place HWS in non-existing mappable region
7cfb9135592b drm/i915: error capture with no ggtt slot
a7a2178c7393 drm/i915: set num_fence_regs to 0 if there is no aperture
d802efde66e4 drm/i915: do not map aperture if it i
[Intel-gfx] [PATCH] drm/i915/display: only include intel_dp_link_training.h where needed
The intel_dp_link_training.h include has no need or place in
intel_display.h. Include it in intel_display.c instead.
Cc:
Cc: Manasi Navare
Fixes: eadf6f9170d5 ("drm/i915/display/icl: Enable master-slaves in trans port
sync")
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_display.h | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..505d697f6b4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -66,6 +66,7 @@
#include "intel_cdclk.h"
#include "intel_color.h"
#include "intel_display_types.h"
+#include "intel_dp_link_training.h"
#include "intel_fbc.h"
#include "intel_fbdev.h"
#include "intel_fifo_underrun.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index ca7ca2804d8b..7278f9aee8ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -27,7 +27,6 @@
#include
#include
-#include "intel_dp_link_training.h"
enum link_m_n_set;
struct dpll;
--
2.20.1
___
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Re: [Intel-gfx] [PATCH V5 4/6] mdev: introduce virtio device and its device ops
On 2019/10/29 下午3:42, Zhu Lingshan wrote:
>>
>> + void (*set_status)(struct mdev_device *mdev, u8 status);
>
> Hi Jason
>
> Is it possible to make set_status() return an u8 or bool, because this
> may fail in real hardware. Without a returned code, I am not sure
> whether it is a good idea to set the status | NEED_RESET when fail.
>
> Thanks,
> BR
> Zhu Lingshan
Hi:
It's possible but I'm not sure whether any user will care about it. E.g
see virtio_add_status():
void virtio_add_status(struct virtio_device *dev, unsigned int status)
{
might_sleep();
dev->config->set_status(dev, dev->config->get_status(dev) | status);
}
EXPORT_SYMBOL_GPL(virtio_add_status);
And I believe how it work should be:
virtio_add_status(xyz);
status = virtio_get_status();
if (!(status & xyz))
error;
Thanks
___
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[Intel-gfx] [RFC 2/2] drm/i915/audio: replace I915_*() calls with the new intel_de_*() calls
Not for merging, for demo only.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 113 +++--
1 file changed, 59 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 85e6b2bbb34f..46d7bd977510 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -32,6 +32,7 @@
#include "intel_audio.h"
#include "intel_display_types.h"
#include "intel_lpe_audio.h"
+#include "intel_display_uncore.h"
/**
* DOC: High Definition Audio over HDMI and Display Port
@@ -291,18 +292,18 @@ static bool intel_eld_uptodate(struct drm_connector
*connector,
u32 tmp;
int i;
- tmp = I915_READ(reg_eldv);
+ tmp = intel_de_read(dev_priv, reg_eldv);
tmp &= bits_eldv;
if (!tmp)
return false;
- tmp = I915_READ(reg_elda);
+ tmp = intel_de_read(dev_priv, reg_elda);
tmp &= ~bits_elda;
- I915_WRITE(reg_elda, tmp);
+ intel_de_write(dev_priv, reg_elda, tmp);
for (i = 0; i < drm_eld_size(eld) / 4; i++)
- if (I915_READ(reg_edid) != *((const u32 *)eld + i))
+ if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld +
i))
return false;
return true;
@@ -317,16 +318,16 @@ static void g4x_audio_codec_disable(struct intel_encoder
*encoder,
DRM_DEBUG_KMS("Disable audio codec\n");
- tmp = I915_READ(G4X_AUD_VID_DID);
+ tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
else
eldv = G4X_ELDV_DEVCTG;
/* Invalidate ELD */
- tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
tmp &= ~eldv;
- I915_WRITE(G4X_AUD_CNTL_ST, tmp);
+ intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
}
static void g4x_audio_codec_enable(struct intel_encoder *encoder,
@@ -342,7 +343,7 @@ static void g4x_audio_codec_enable(struct intel_encoder
*encoder,
DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
- tmp = I915_READ(G4X_AUD_VID_DID);
+ tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
eldv = G4X_ELDV_DEVCL_DEVBLC;
else
@@ -354,19 +355,20 @@ static void g4x_audio_codec_enable(struct intel_encoder
*encoder,
G4X_HDMIW_HDMIEDID))
return;
- tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
len = (tmp >> 9) & 0x1f;/* ELD buffer size */
- I915_WRITE(G4X_AUD_CNTL_ST, tmp);
+ intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
len = min(drm_eld_size(eld) / 4, len);
DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++)
- I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
+ intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID,
+ *((const u32 *)eld + i));
- tmp = I915_READ(G4X_AUD_CNTL_ST);
+ tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
tmp |= eldv;
- I915_WRITE(G4X_AUD_CNTL_ST, tmp);
+ intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
}
static void
@@ -388,7 +390,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
else
DRM_DEBUG_KMS("using automatic Maud, Naud\n");
- tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
@@ -400,9 +402,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_CONFIG_N_PROG_ENABLE;
}
- I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp);
+ intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
- tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
tmp &= ~AUD_CONFIG_M_MASK;
tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
@@ -413,7 +415,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
tmp |= AUD_M_CTS_M_PROG_ENABLE;
}
- I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
+ intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
}
static void
@@ -429,7 +431,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
rate = acomp ? acomp->aud_sample_rate[port] : 0;
- tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
+ tmp = intel_de_read(dev_priv,
[Intel-gfx] [RFC 1/2] drm/i915: add display uncore helpers
Add convenience helpers for the most common uncore operations with
struct drm_i915_private * as context rather than struct intel_uncore *.
The goal is to replace all instances of I915_READ(),
I915_POSTING_READ(), and I915_WRITE() in display/ with these, to finally
be able to get rid of the implicit dev_priv local parameter use.
The idea is that any non-u32 reads or writes are special enough that
they can use the intel_uncore_* functions directly.
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Lucas De Marchi
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
Let the name bikeshedding commence! Some options are:
- intel_de_read, intel_de_write (this patch, de for display engine)
- intel_display_read, intel_display_write (too long I think)
- intel_read, intel_write
- i915_read, i915_write
- display_read, display_write
- ?
Here's a draft cocci patch that could be used on display/ subdir, en
masse:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
Conveniently, we *know* dev_priv is everywhere the change is needed.
This enables us to make the s/dev_priv/i915/ rename on top. We also need
to discuss whether it's better to separate the steps to two (even if in
the same patch series) or if it's better to add the dev_priv parameter
as i915 directly.
---
.../drm/i915/display/intel_display_uncore.h | 36 +++
1 file changed, 36 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_uncore.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_uncore.h
b/drivers/gpu/drm/i915/display/intel_display_uncore.h
new file mode 100644
index ..e6c8c56fb0f9
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_uncore.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_UNCORE_H__
+#define __INTEL_DISPLAY_UNCORE_H__
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_uncore.h"
+
+static inline u32 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
+{
+ return intel_uncore_read(&i915->uncore, reg);
+}
+
+static inline void intel_de_posting_read(struct drm_i915_private *i915,
+i915_reg_t reg)
+{
+ intel_uncore_posting_read(&i915->uncore, reg);
+}
+
+static inline void intel_de_write(struct drm_i915_private *i915, i915_reg_t
reg,
+ u32 val)
+{
+ intel_uncore_write(&i915->uncore, reg, val);
+}
+
+static inline void intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg,
+ u32 clear, u32 set)
+{
+ intel_uncore_rmw(&i915->uncore, reg, clear, set);
+}
+
+#endif /* __INTEL_DISPLAY_UNCORE_H__ */
--
2.20.1
___
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Re: [Intel-gfx] [PATCH] drm/i915/display: only include intel_dp_link_training.h where needed
On Tue, 29 Oct 2019, Jani Nikula wrote:
> The intel_dp_link_training.h include has no need or place in
> intel_display.h. Include it in intel_display.c instead.
>
> Cc:
Whoops, obviously to be removed before merging.
BR,
Jani.
>
> Cc: Manasi Navare
> Fixes: eadf6f9170d5 ("drm/i915/display/icl: Enable master-slaves in trans
> port sync")
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.h | 1 -
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 9dce2e9e5376..505d697f6b4c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -66,6 +66,7 @@
> #include "intel_cdclk.h"
> #include "intel_color.h"
> #include "intel_display_types.h"
> +#include "intel_dp_link_training.h"
> #include "intel_fbc.h"
> #include "intel_fbdev.h"
> #include "intel_fifo_underrun.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index ca7ca2804d8b..7278f9aee8ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -27,7 +27,6 @@
>
> #include
> #include
> -#include "intel_dp_link_training.h"
>
> enum link_m_n_set;
> struct dpll;
--
Jani Nikula, Intel Open Source Graphics Center
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Conclude load -> probe naming convention switch (rev2)
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch (rev2)
URL : https://patchwork.freedesktop.org/series/67454/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2fff720f7c40 drm/i915: Fix i915_inject_load_error() name to read *_probe_*
-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit f2db53f14d3d ("drm/i915: Replace
"_load" with "_probe" consequently")'
#11:
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
total: 1 errors, 0 warnings, 0 checks, 158 lines checked
dbed42546cef drm/i915: Rename "inject_load_failure" module parameter
-:9: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'Commit f2db53f14d3d ("drm/i915: Replace
"_load" with "_probe" consequently")'
#9:
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/i915_params.c:170:
+i915_param_named_unsafe(inject_probe_failure, uint, 0400,
"Force an error after a number of failure check points (0:disabled
(default), N:force failure at the Nth failure check point)");
total: 1 errors, 0 warnings, 1 checks, 43 lines checked
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Re: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B sprites on CHV
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B
>sprites on CHV
>
>From: Ville Syrjälä
>
>CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats.
>On VLV and CHV pipe A/C these are only supported by the the primary plane. Add
>the
Drop the redundant "the".
CHV indeed has this additional capability on pipe B (MPO pipe) sprites.
Overall changes look good to me.
Reviewed-by: Uma Shankar
>require bits to expose the new formats.
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 33 +++--
> drivers/gpu/drm/i915/i915_reg.h | 14 +
> 2 files changed, 39 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 90b0e65420a5..fb36da58390a 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -861,6 +861,12 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ABGR2101010:
> sprctl |= SP_FORMAT_RGBA1010102;
> break;
>+ case DRM_FORMAT_XRGB2101010:
>+ sprctl |= SP_FORMAT_BGRX1010102;
>+ break;
>+ case DRM_FORMAT_ARGB2101010:
>+ sprctl |= SP_FORMAT_BGRA1010102;
>+ break;
> case DRM_FORMAT_XBGR:
> sprctl |= SP_FORMAT_RGBX;
> break;
>@@ -2017,6 +2023,22 @@ static const u32 vlv_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
>+static const u32 chv_pipe_b_sprite_formats[] = {
>+ DRM_FORMAT_RGB565,
>+ DRM_FORMAT_ABGR,
>+ DRM_FORMAT_ARGB,
>+ DRM_FORMAT_XBGR,
>+ DRM_FORMAT_XRGB,
>+ DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_YUYV,
>+ DRM_FORMAT_YVYU,
>+ DRM_FORMAT_UYVY,
>+ DRM_FORMAT_VYUY,
>+};
>+
> static const u32 skl_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>@@ -2241,6 +2263,8 @@ static bool vlv_sprite_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_XRGB:
> case DRM_FORMAT_XBGR2101010:
> case DRM_FORMAT_ABGR2101010:
>+ case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2637,8 +2661,13 @@ intel_sprite_plane_create(struct drm_i915_private
>*dev_priv,
> plane->get_hw_state = vlv_plane_get_hw_state;
> plane->check_plane = vlv_sprite_check;
>
>- formats = vlv_plane_formats;
>- num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
>+ formats = chv_pipe_b_sprite_formats;
>+ num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats);
>+ } else {
>+ formats = vlv_plane_formats;
>+ num_formats = ARRAY_SIZE(vlv_plane_formats);
>+ }
> modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &vlv_sprite_funcs;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index
>8bd75eff1266..74bb5a6cbe4f 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -6545,12 +6545,14 @@ enum {
> #define SP_ENABLE (1 << 31)
> #define SP_GAMMA_ENABLE (1 << 30)
> #define SP_PIXFORMAT_MASK (0xf << 26)
>-#define SP_FORMAT_YUV422(0 << 26)
>-#define SP_FORMAT_BGR565(5 << 26)
>-#define SP_FORMAT_BGRX (6 << 26)
>-#define SP_FORMAT_BGRA (7 << 26)
>-#define SP_FORMAT_RGBX1010102 (8 << 26)
>-#define SP_FORMAT_RGBA1010102 (9 << 26)
>+#define SP_FORMAT_YUV422(0x0 << 26)
>+#define SP_FORMAT_BGR565(0x5 << 26)
>+#define SP_FORMAT_BGRX (0x6 << 26)
>+#define SP_FORMAT_BGRA (0x7 << 26)
>+#define SP_FORMAT_RGBX1010102 (0x8 << 26)
>+#define SP_FORMAT_RGBA1010102 (0x9 << 26)
>+#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */
>+#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */
> #define SP_FORMAT_RGBX (0xe << 26)
> #define SP_FORMAT_RGBA (0xf << 26)
> #define SP_ALPHA_PREMULTIPLY(1 << 23) /* CHV pipe B */
>--
>2.21.0
>
>___
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>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-g
Re: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for icl+
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Wednesday, October 9, 2019 4:14 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for
>icl+
>
>From: Ville Syrjälä
>
>ICL+ again supports alpha blending with 10bpc pixel formats.
>Expose them.
>
>v2: Add all the stuff I missed earlier!
Changes look good to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_display.c | 19 +++
>drivers/gpu/drm/i915/display/intel_sprite.c | 10 ++
> 2 files changed, 25 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..19a0c8cfb151 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -3031,10 +3031,17 @@ int skl_format_to_fourcc(int format, bool rgb_order,
>bool alpha)
> return DRM_FORMAT_XRGB;
> }
> case PLANE_CTL_FORMAT_XRGB_2101010:
>- if (rgb_order)
>- return DRM_FORMAT_XBGR2101010;
>- else
>- return DRM_FORMAT_XRGB2101010;
>+ if (rgb_order) {
>+ if (alpha)
>+ return DRM_FORMAT_ABGR2101010;
>+ else
>+ return DRM_FORMAT_XBGR2101010;
>+ } else {
>+ if (alpha)
>+ return DRM_FORMAT_ARGB2101010;
>+ else
>+ return DRM_FORMAT_XRGB2101010;
>+ }
> case PLANE_CTL_FORMAT_XRGB_16161616F:
> if (rgb_order) {
> if (alpha)
>@@ -4024,8 +4031,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_ARGB:
> return PLANE_CTL_FORMAT_XRGB_;
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ABGR2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010 |
>PLANE_CTL_ORDER_RGBX;
> case DRM_FORMAT_XRGB2101010:
>+ case DRM_FORMAT_ARGB2101010:
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
>@@ -5617,6 +5626,8 @@ static int skl_update_scaler_plane(struct
>intel_crtc_state
>*crtc_state,
> case DRM_FORMAT_ARGB:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_XBGR16161616F:
> case DRM_FORMAT_ABGR16161616F:
> case DRM_FORMAT_XRGB16161616F:
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index 4cd0982dc8a2..df3ca75580d7 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2103,6 +2103,8 @@ static const u32 icl_sdr_y_plane_formats[] = {
> DRM_FORMAT_ABGR,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2124,6 +2126,8 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> DRM_FORMAT_ABGR,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2149,6 +2153,8 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_ABGR,
> DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_XRGB16161616F,
> DRM_FORMAT_XBGR16161616F,
> DRM_FORMAT_ARGB16161616F,
>@@ -2315,6 +2321,8 @@ static bool skl_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>@@ -2367,6 +2375,8 @@ static bool gen12_plane_format_mod_supported(struct
>drm_plane *_plane,
> case DRM_FORMAT_RGB565:
> case DRM_FORMAT_XRGB2101010:
> case DRM_FORMAT_XBGR2101010:
>+ case DRM_FORMAT_ARGB2101010:
>+ case DRM_FORMAT_ABGR2101010:
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
>--
>2.21.0
>
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Re: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
>
>From: Ville Syrjälä
>
>Let's try to keep the pixel format arrays somewhat sorted:
>1. RGB before YUV
>2. smaller bpp before larger bpp
>3. X before A
>4. RGB before BGR
Changes look good to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>drivers/gpu/drm/i915/display/intel_sprite.c | 20 ++--
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 1cdcd0ea0564..a8124f01bdb2 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -83,8 +83,8 @@
> /* Primary plane formats for gen <= 3 */ static const u32
> i8xx_primary_formats[] = {
> DRM_FORMAT_C8,
>- DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB1555,
>+ DRM_FORMAT_RGB565,
> DRM_FORMAT_XRGB,
> };
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index aaabeaf11ae9..cc9e5c9668b1 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -2002,10 +2002,10 @@ static const u64 i9xx_plane_format_modifiers[] = { };
>
> static const u32 snb_plane_formats[] = {
>- DRM_FORMAT_XBGR,
> DRM_FORMAT_XRGB,
>- DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR,
> DRM_FORMAT_XBGR2101010,
>+ DRM_FORMAT_XRGB2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>@@ -2015,10 +2015,10 @@ static const u32 snb_plane_formats[] = { static const
>u32 vlv_plane_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR,
>- DRM_FORMAT_ARGB,
>- DRM_FORMAT_XBGR,
> DRM_FORMAT_XRGB,
>+ DRM_FORMAT_XBGR,
>+ DRM_FORMAT_ARGB,
>+ DRM_FORMAT_ABGR,
> DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
>@@ -2030,14 +2030,14 @@ static const u32 vlv_plane_formats[] = { static const
>u32
>chv_pipe_b_sprite_formats[] = {
> DRM_FORMAT_C8,
> DRM_FORMAT_RGB565,
>- DRM_FORMAT_ABGR,
>- DRM_FORMAT_ARGB,
>- DRM_FORMAT_XBGR,
> DRM_FORMAT_XRGB,
>- DRM_FORMAT_XBGR2101010,
>- DRM_FORMAT_ABGR2101010,
>+ DRM_FORMAT_XBGR,
>+ DRM_FORMAT_ARGB,
>+ DRM_FORMAT_ABGR,
> DRM_FORMAT_XRGB2101010,
>+ DRM_FORMAT_XBGR2101010,
> DRM_FORMAT_ARGB2101010,
>+ DRM_FORMAT_ABGR2101010,
> DRM_FORMAT_YUYV,
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
>--
>2.21.0
>
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/7] drm/i915: define i915_ggtt_has_aperture
== Series Details == Series: series starting with [v2,1/7] drm/i915: define i915_ggtt_has_aperture URL : https://patchwork.freedesktop.org/series/68710/ State : failure == Summary == Applying: drm/i915: define i915_ggtt_has_aperture Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_gem_gtt.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915: define i915_ggtt_has_aperture When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission
On Mon, 28 Oct 2019 22:25:27 +0100, wrote:
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the GuC suspend/remove entirely as we do
not need to save the GuC submission status.
v2: Do not suspend/resume the GuC on platforms that do not support
Guc Submission.
Signed-off-by: Don Hiatt
---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3fdbc935d155..04031564f0b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -572,10 +572,19 @@ void intel_uc_runtime_suspend(struct intel_uc *uc)
if (!intel_guc_is_running(guc))
return;
+ /*
+* If GuC communciation is enabled but submission is not supported,
typo
+* we do not need to suspend the GuC but we do need to disable the
+* GuC communication on suspend.
+*/
+ if (!guc->submission_supported)
Using submission_supported flag directly can be tricky, as today it
is always set to false, but in the future it may indicate either that
submission is supported by the driver/fw and/or enabled by modparam.
There is no guarantee that it will reflect actual runtime status,
as even supported/unblocked guc submission may fallback to execlists.
We may need something like intel_guc_submission_is_active() that will
reflect actual mode of submission currently used by the driver.
+ goto guc_disable_comm;
and maybe we can move above logic to intel_guc_suspend()
to do not introduce extra goto's ?
+
err = intel_guc_suspend(guc);
if (err)
DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
+guc_disable_comm:
guc_disable_communication(guc);
}
@@ -605,6 +614,14 @@ static int __uc_resume(struct intel_uc *uc, bool
enable_communication)
if (enable_communication)
guc_enable_communication(guc);
+ /*
+* If GuC communciation is enabled but submission is not supported,
typo
+* we do not need to resume the GuC but we do need to enable the
+* GuC communication on resume (above).
+*/
+ if (!guc->submission_supported)
+ return 0;
see suspend case comment
+
err = intel_guc_resume(guc);
if (err) {
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
Thanks,
Michal
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Re: [Intel-gfx] [RESEND PATCH i-g-t v2 1/1] tests/i915_module_load: Use new name of fault injection module parameter
Quoting Janusz Krzysztofik (2019-10-29 10:17:51)
> Name of the i915 module parameter providing fault injection function is
> changing for consistency with a new convention of naming i915 driver
> internal functions called from the driver PCI .probe entry point. Adjust
> the test to use the new name.
>
> Suggested-by: Joonas Lahtinen
> Signed-off-by: Janusz Krzysztofik
> Cc: Michał Wajdeczko
> Cc: Michał Winiarski
> Cc: Piotr Piórkowski
> Cc: Tomasz Lis
> Cc: Joonas Lahtinen
> Reviewed-by: Chris Wilson
> ---
> tests/i915/i915_module_load.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
> index 7fe83520..a620ab41 100644
> --- a/tests/i915/i915_module_load.c
> +++ b/tests/i915/i915_module_load.c
> @@ -356,7 +356,7 @@ igt_main
>
> igt_i915_driver_unload();
>
> - while (inject_fault("i915", "inject_load_failure", ++i) == 0)
> + while (inject_fault("i915", "inject_probe_failure", ++i) == 0)
Hmm, I could do with a transition period so that we don't lose reload
tests on linus/stable.
-Chris
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: only include intel_dp_link_training.h where needed
== Series Details == Series: drm/i915/display: only include intel_dp_link_training.h where needed URL : https://patchwork.freedesktop.org/series/68711/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1b222834c572 drm/i915/display: only include intel_dp_link_training.h where needed -:10: WARNING:BAD_SIGN_OFF: Use a single space after Cc: #10: Cc: -:10: ERROR:BAD_SIGN_OFF: Unrecognized email address: '' #10: Cc: total: 1 errors, 1 warnings, 0 checks, 14 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] tests/i915_module_load: Use new name of fault injection module parameter
From: Janusz Krzysztofik
Name of the i915 module parameter providing fault injection function is
changing for consistency with a new convention of naming i915 driver
internal functions called from the driver PCI .probe entry point. Adjust
the test to use the new name.
[ickle: keep the old parameter name around for stable testing]
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz Krzysztofik
Cc: Michał Wajdeczko
Cc: Michał Winiarski
Cc: Piotr Piórkowski
Cc: Tomasz Lis
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
lib/igt_kmod.c| 40 +++
lib/igt_kmod.h| 2 ++
tests/i915/i915_module_load.c | 8 ++-
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
index c3da46678..f43da9f42 100644
--- a/lib/igt_kmod.c
+++ b/lib/igt_kmod.c
@@ -153,6 +153,46 @@ static int modprobe(struct kmod_module *kmod, const char
*options)
NULL, NULL, NULL);
}
+/**
+ * igt_kmod_has_param:
+ * @mod_name: The name of the module
+ * @param: The name of the parameter
+ *
+ * Returns: true if the module has the parameter, false otherwise.
+ */
+bool igt_kmod_has_param(const char *module_name, const char *param)
+{
+ struct kmod_module *kmod;
+ struct kmod_list *d, *pre;
+ bool result = false;
+
+ if (kmod_module_new_from_name(kmod_ctx(), module_name, &kmod))
+ return false;
+
+ pre = NULL;
+ if (!kmod_module_get_info(kmod, &pre))
+ goto out;
+
+ kmod_list_foreach(d, pre) {
+ const char *key, *val;
+
+ key = kmod_module_info_get_key(d);
+ if (strcmp(key, "parmtype"))
+ continue;
+
+ val = kmod_module_info_get_value(d);
+ if (val && strcmp(val, param) == 0) {
+ result = true;
+ break;
+ }
+ }
+ kmod_module_info_free_list(pre);
+
+out:
+ kmod_module_unref(kmod);
+ return result;
+}
+
/**
* igt_kmod_load:
* @mod_name: The name of the module
diff --git a/lib/igt_kmod.h b/lib/igt_kmod.h
index 87d36d400..e47ff2df6 100644
--- a/lib/igt_kmod.h
+++ b/lib/igt_kmod.h
@@ -31,6 +31,8 @@
bool igt_kmod_is_loaded(const char *mod_name);
void igt_kmod_list_loaded(void);
+bool igt_kmod_has_param(const char *mod_name, const char *param);
+
int igt_kmod_load(const char *mod_name, const char *opts);
int igt_kmod_unload(const char *mod_name, unsigned int flags);
diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
index f42083f53..7d9a5cfd2 100644
--- a/tests/i915/i915_module_load.c
+++ b/tests/i915/i915_module_load.c
@@ -350,11 +350,17 @@ igt_main
}
igt_subtest("reload-with-fault-injection") {
+ const char *param;
int i = 0;
igt_i915_driver_unload();
- while (inject_fault("i915", "inject_load_failure", ++i) == 0)
+ param = "inject_probe_failure";
+ if (!igt_kmod_has_param("i915", param))
+ param = "inject_load_failure";
+ igt_require(igt_kmod_has_param("i915", param));
+
+ while (inject_fault("i915", param, ++i) == 0)
;
/* We expect to hit at least one fault! */
--
2.24.0.rc1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/index.html
Known issues
Here are the changes found in Patchwork_15031 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_reloc@basic-write-read-noreloc:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-write-read-noreloc.html
* igt@i915_selftest@live_blt:
- fi-kbl-guc: [PASS][3] -> [TIMEOUT][4] ([fdo#112162])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-kbl-guc/igt@i915_selftest@live_blt.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-kbl-guc/igt@i915_selftest@live_blt.html
- fi-icl-u2: [PASS][5] -> [TIMEOUT][6] ([fdo#112162])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@i915_selftest@live_blt.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_client:
- fi-whl-u: [PASS][7] -> [INCOMPLETE][8] ([fdo#112162])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-whl-u/igt@i915_selftest@live_client.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-whl-u/igt@i915_selftest@live_client.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [PASS][9] -> [FAIL][10] ([fdo#109570])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927] / [fdo#111381]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* igt@i915_selftest@live_blt:
- fi-glk-dsi: [TIMEOUT][15] ([fdo#112162]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-glk-dsi/igt@i915_selftest@live_blt.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-glk-dsi/igt@i915_selftest@live_blt.html
- fi-cfl-8700k: [TIMEOUT][17] ([fdo#112162]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-cfl-8700k/igt@i915_selftest@live_blt.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-cfl-8700k/igt@i915_selftest@live_blt.html
- fi-skl-iommu: [TIMEOUT][19] ([fdo#112162]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-skl-iommu/igt@i915_selftest@live_blt.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-skl-iommu/igt@i915_selftest@live_blt.html
- {fi-tgl-u}: [TIMEOUT][21] ([fdo#112162]) -> [PASS][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-tgl-u/igt@i915_selftest@live_blt.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-tgl-u/igt@i915_selftest@live_blt.html
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][23] ([fdo#102505] / [fdo#106107] /
[fdo#110390]) -> [DMESG-WARN][24] ([fdo#102505] / [fdo#110390])
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7205/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15031/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bu
Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>From: Ville Syrjälä
>
>According to the spec color keying is not supported with
>fp16 pixel formats on skl+. Reject that combo.
>
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++
> 1 file changed, 18 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>b/drivers/gpu/drm/i915/display/intel_sprite.c
>index cc9e5c9668b1..d6cd46e3f738 100644
>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
> return 0;
> }
>
>+static bool format_is_fp16(u32 format)
>+{
>+ switch (format) {
>+ case DRM_FORMAT_XRGB16161616F:
>+ case DRM_FORMAT_XBGR16161616F:
>+ case DRM_FORMAT_ARGB16161616F:
>+ case DRM_FORMAT_ABGR16161616F:
>+ return true;
>+ default:
>+ return false;
>+ }
>+}
>+
> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state) {
> @@ -
>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct intel_crtc_state
>*crtc_state,
> return -EINVAL;
> }
>
>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>formats\n");
It seems even "Indexed 8 bit formats" also don't support Color Keying. May be
you can extend it to
even C8.
>+ return -EINVAL;
>+ }
>+
> return 0;
> }
>
>--
>2.21.0
>
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Simply walk back along request timeline on reset (rev6)
== Series Details == Series: drm/i915/execlists: Simply walk back along request timeline on reset (rev6) URL : https://patchwork.freedesktop.org/series/68601/ State : success == Summary == CI Bug Log - changes from CI_DRM_7203_full -> Patchwork_15023_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15023_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-iclb1/igt@gem_ctx_isolat...@vcs1-reset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-iclb5/igt@gem_ctx_isolat...@vcs1-reset.html * igt@gem_exec_schedule@wide-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-iclb4/igt@gem_exec_sched...@wide-bsd.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-hsw: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-snb5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-snb2/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy.html * igt@i915_selftest@mock_requests: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#112156]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl5/igt@i915_selftest@mock_requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-skl5/igt@i915_selftest@mock_requests.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-apl3/igt@i915_susp...@debugfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-apl1/igt@i915_susp...@debugfs-reader.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([fdo#106107]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl10/igt@kms_co...@pipe-a-ctm-0-75.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-skl1/igt@kms_co...@pipe-a-ctm-0-75.html * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge: - shard-apl: [PASS][17] -> [INCOMPLETE][18] ([fdo#103927]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-apl4/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-apl8/igt@kms_cursor_edge_w...@pipe-a-64x64-bottom-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][19] -> [FAIL][20] ([fdo#105767]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#102670]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl3/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-skl7/igt@kms_cursor_leg...@flip-vs-cursor-atomic.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#109507]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl9/igt@kms_f...@flip-vs-suspend-interruptible.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15023/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-hsw: [PASS][25] -> [INCOMPLETE][26] ([fdo#103540]) [25]: https://inte
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/selftests: Initialise ret
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Initialise ret URL : https://patchwork.freedesktop.org/series/68662/ State : success == Summary == CI Bug Log - changes from CI_DRM_7203_full -> Patchwork_15025_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15025_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-iclb1/igt@gem_ctx_isolat...@vcs1-reset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-iclb7/igt@gem_ctx_isolat...@vcs1-reset.html * igt@gem_exec_schedule@preempt-contexts-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-iclb7/igt@gem_exec_sched...@preempt-contexts-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-iclb4/igt@gem_exec_sched...@preempt-contexts-bsd.html * igt@gem_persistent_relocs@forked-thrashing: - shard-kbl: [PASS][5] -> [FAIL][6] ([fdo#112037]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-kbl6/igt@gem_persistent_rel...@forked-thrashing.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-kbl3/igt@gem_persistent_rel...@forked-thrashing.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-snb: [PASS][7] -> [DMESG-WARN][8] ([fdo#111870]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-snb7/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_selftest@mock_requests: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#112156]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl5/igt@i915_selftest@mock_requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-skl2/igt@i915_selftest@mock_requests.html * igt@kms_color@pipe-b-ctm-0-25: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([fdo#106107]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl2/igt@kms_co...@pipe-b-ctm-0-25.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-skl9/igt@kms_co...@pipe-b-ctm-0-25.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#105767]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#104873]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-glk6/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-legacy.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-skl4/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][19] -> [FAIL][20] ([fdo#105363]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-glk8/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-glk3/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-apl2/igt@kms_f...@flip-vs-suspend-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-apl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7203/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15025/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
Re: [Intel-gfx] [PATCH] drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
On 10/25/2019 8:52 PM, Animesh Manna wrote:
On 10/17/2019 9:28 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global
GTT
and not in the mappable region.
Currently tested and working without any regression, waiting for
confirmation from h/w team, will update soon.
Got confirmation from h/w team, changes are ok to me.
Reviewed-by: Animesh Manna
Thanks Chris, Tvrtko for the learning.
Regards,
Animesh
Regards,
Animesh
Signed-off-by: Tvrtko Ursulin
Cc: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bb5a0e91b370..d8ad5fe1efef 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -119,7 +119,7 @@ intel_dsb_get(struct intel_crtc *crtc)
goto err;
}
-vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_ERROR("Vma creation failed\n");
i915_gem_object_put(obj);
___
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Re: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color keying is active
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color
>keying is active
>
>From: Ville Syrjälä
>
>The spec says that color keying and HDR mode are mutually exclusive.
>So let's not enable HDR mode when color keying is active.
Looks good to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 +
> drivers/gpu/drm/i915/display/intel_display.c | 13 ++---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> 3 files changed, 16 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>index 98b7766eaa7a..f64204f6f37f 100644
>--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>@@ -150,6 +150,7 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> new_crtc_state->active_planes &= ~BIT(plane->id);
> new_crtc_state->nv12_planes &= ~BIT(plane->id);
> new_crtc_state->c8_planes &= ~BIT(plane->id);
>+ new_crtc_state->ckey_planes &= ~BIT(plane->id);
> new_crtc_state->data_rate[plane->id] = 0;
> new_plane_state->base.visible = false;
>
>@@ -172,6 +173,10 @@ int intel_plane_atomic_check_with_state(const struct
>intel_crtc_state *old_crtc_
> fb->format->format == DRM_FORMAT_C8)
> new_crtc_state->c8_planes |= BIT(plane->id);
>
>+ if (new_plane_state->base.visible &&
>+ new_plane_state->ckey.flags)
>+ new_crtc_state->ckey_planes |= BIT(plane->id);
>+
> if (new_plane_state->base.visible || old_plane_state->base.visible)
> new_crtc_state->update_planes |= BIT(plane->id);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index a8124f01bdb2..c553a3417891 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -9514,6 +9514,15 @@ static void haswell_set_pipeconf(const struct
>intel_crtc_state *crtc_state)
> POSTING_READ(PIPECONF(cpu_transcoder));
> }
>
>+static bool icl_can_hdr_mode(const struct intel_crtc_state *crtc_state)
>+{
>+ u8 ckey_planes = crtc_state->ckey_planes;
>+ u8 sdr_planes = crtc_state->active_planes &
>+ ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR));
>+
>+ return !ckey_planes && !sdr_planes;
>+}
>+
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>@@ -9549,9 +9558,7 @@ static void bdw_set_pipemisc(const struct
>intel_crtc_state
>*crtc_state)
> val |= PIPEMISC_YUV420_ENABLE |
> PIPEMISC_YUV420_MODE_FULL_BLEND;
>
>- if (INTEL_GEN(dev_priv) >= 11 &&
>- (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
>- BIT(PLANE_CURSOR))) == 0)
>+ if (INTEL_GEN(dev_priv) >= 11 && icl_can_hdr_mode(crtc_state))
> val |= PIPEMISC_HDR_MODE_PRECISION;
>
> I915_WRITE(PIPEMISC(crtc->pipe), val); diff --git
>a/drivers/gpu/drm/i915/display/intel_display_types.h
>b/drivers/gpu/drm/i915/display/intel_display_types.h
>index 40390d855815..4935ea41d3e1 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_types.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>@@ -949,6 +949,7 @@ struct intel_crtc_state {
> u8 active_planes;
> u8 nv12_planes;
> u8 c8_planes;
>+ u8 ckey_planes;
>
> /* bitmask of planes that will be updated during the commit */
> u8 update_planes;
>--
>2.21.0
>
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[Intel-gfx] [PATCH] drm/i915: Nuke 'mode' argument to intel_get_load_detect_pipe()
From: Ville Syrjälä
We always pass mode==NULL to intel_get_load_detect_pipe(). Remove
the pointless function argument.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
4 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index ff6126ea793c..25118619e240 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -844,7 +844,7 @@ intel_crt_detect(struct drm_connector *connector,
}
/* for pre-945g platforms use load detect */
- ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
+ ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
if (ret > 0) {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e56a75c07043..1862546356fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11328,7 +11328,6 @@ static int intel_modeset_disable_planes(struct
drm_atomic_state *state,
}
int intel_get_load_detect_pipe(struct drm_connector *connector,
- const struct drm_display_mode *mode,
struct intel_load_detect_pipe *old,
struct drm_modeset_acquire_ctx *ctx)
{
@@ -11435,10 +11434,8 @@ int intel_get_load_detect_pipe(struct drm_connector
*connector,
crtc_state->base.active = crtc_state->base.enable = true;
- if (!mode)
- mode = &load_detect_mode;
-
- ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
+ ret = drm_atomic_set_mode_for_crtc(&crtc_state->base,
+ &load_detect_mode);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index ca7ca2804d8b..355c50088589 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -509,7 +509,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
struct intel_digital_port *dport,
unsigned int expected_mask);
int intel_get_load_detect_pipe(struct drm_connector *connector,
- const struct drm_display_mode *mode,
struct intel_load_detect_pipe *old,
struct drm_modeset_acquire_ctx *ctx);
void intel_release_load_detect_pipe(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c
b/drivers/gpu/drm/i915/display/intel_tv.c
index 70726b481244..5556d8300a88 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1701,7 +1701,7 @@ intel_tv_detect(struct drm_connector *connector,
struct intel_load_detect_pipe tmp;
int ret;
- ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
+ ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
if (ret < 0)
return ret;
--
2.23.0
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Re: [Intel-gfx] [CI 04/12] drm/i915: Perform manual conversions for crtc uapi/hw split, v2.
On Tue, Oct 29, 2019 at 08:22:21AM +0100, Maarten Lankhorst wrote:
> intel_get_load_detect_pipe() needs to set uapi active,
> uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
> so we can remove it.
>
> intel_pipe_config_compare() needs to look at hw state, but I didn't
> change spatch to look at it. It's easy enough to do manually.
>
> intel_atomic_check() definitely needs to check for uapi enable,
> otherwise intel_modeset_pipe_config cannot copy uapi state to hw.
>
> Changes since v1:
> - Actually set uapi.active in get_load_detect_pipe().
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 42 ++--
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d0df9b24a969..4baa0226abff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11433,7 +11433,7 @@ int intel_get_load_detect_pipe(struct drm_connector
> *connector,
> goto fail;
> }
>
> - crtc_state->base.active = crtc_state->base.enable = true;
> + crtc_state->uapi.active = true;
The fact that load detection broke in ci makes this a bit suspicious.
But AFAICS it should work.
Hmm. Long ago I had a patch to fix something in
drm_atomic_set_mode_for_crtc()...
https://patchwork.freedesktop.org/patch/262996/?series=52778&rev=1
Doesn't seem like it should make a difference unless somehow uapi.mode
is left with the load detect mode but uapi.enable is set to false before
another call to drm_atomic_set_mode_for_crtc(load_detect_mode).
>
> if (!mode)
> mode = &load_detect_mode;
> @@ -13080,19 +13080,19 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_X(output_types);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
>
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
> - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> + PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
>
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(output_format);
> @@ -13109,17 +13109,17 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
>
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_INTERLACE);
>
> if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NHSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_PVSYNC);
> - PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
> + PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
> DRM_MODE_FLAG_NVSYNC);
> }
>
> @@ -13158,7 +13158,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
> if (bp_gamma)
> - PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, base.gamma_lut,
> bp_gamma);
> + PIPE_CONF_CHECK_COLOR
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in intel_primary_plane_create()
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in
>intel_primary_plane_create()
>
>From: Ville Syrjälä
>
>Lots of redundant assignments inside intel_primary_plane_create().
>Get rid of them.
Looks good to me.
Reviewed-by: Uma Shankar
>Signed-off-by: Ville Syrjälä
>---
> drivers/gpu/drm/i915/display/intel_display.c | 43 +++-
> 1 file changed, 14 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index c553a3417891..2acec838fb8e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -14873,7 +14873,6 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> unsigned int possible_crtcs;
>- const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
>@@ -14908,53 +14907,39 @@ intel_primary_plane_create(struct drm_i915_private
>*dev_priv, enum pipe pipe)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> formats = vlv_primary_formats;
> num_formats = ARRAY_SIZE(vlv_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>-
>- plane_funcs = &i965_plane_funcs;
> } else {
> formats = i8xx_primary_formats;
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
>- modifiers = i9xx_format_modifiers;
>-
>- plane->max_stride = i9xx_plane_max_stride;
>- plane->update_plane = i9xx_update_plane;
>- plane->disable_plane = i9xx_disable_plane;
>- plane->get_hw_state = i9xx_plane_get_hw_state;
>- plane->check_plane = i9xx_plane_check;
>+ }
>
>+ if (INTEL_GEN(dev_priv) >= 4)
>+ plane_funcs = &i965_plane_funcs;
>+ else
> plane_funcs = &i8xx_plane_funcs;
>- }
>+
>+ plane->max_stride = i9xx_plane_max_stride;
>+ plane->update_plane = i9xx_update_plane;
>+ plane->disable_plane = i9xx_disable_plane;
>+ plane->get_hw_state = i9xx_plane_get_hw_state;
>+ plane->check_plane = i9xx_plane_check;
>
> possible_crtcs = BIT(pipe);
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> possible_crtcs, plane_funcs,
>- formats, num_formats, modifiers,
>+ formats, num_formats,
>+ i9xx_format_modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
>--
>2.21.0
>
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Re: [Intel-gfx] [PATCH] drm/dp: Increase link status size
On Tue, 29 Oct 2019, Thierry Reding wrote:
> From: Thierry Reding
>
> The current link status contains bytes 0x202 through 0x207, but we also
> want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> so that the post-cursor adjustment can be queried during link training.
We don't currently use this in i915 (we probably should), so the impact
here is that we'll just read more DPCD than before. I quickly perused
i915, and this does not appear to directly break anything. I think the
change is probably fine, but at the same time it freaks me out a bit...
If you don't mind, please resend this with Cc:
intel-gfx@lists.freedesktop.org to have our CI crunch through it across
a number of platforms. Would give me a warm fuzzy feeling. :)
With the caveat that I didn't look at any other drivers besides i915,
Reviewed-by: Jani Nikula
>
> Reported-by: coverity-bot
> Addresses-Coverity-ID: 1487366 ("Memory - corruptions")
> Fixes: 79465e0ffeb9 ("drm/dp: Add helper to get post-cursor adjustments")
> Signed-off-by: Thierry Reding
> ---
> I vaguely recall once carrying a patch to do this, but I can't find any
> trace of it.
>
> include/drm/drm_dp_helper.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 51ecb5112ef8..9581dec900ba 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1121,7 +1121,7 @@
> #define DP_MST_PHYSICAL_PORT_0 0
> #define DP_MST_LOGICAL_PORT_0 8
>
> -#define DP_LINK_STATUS_SIZE 6
> +#define DP_LINK_STATUS_SIZE 11
> bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
> int lane_count);
> bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH i-g-t] tests/i915_module_load: Use new name of fault injection module parameter
Hi Chris,
On Tuesday, October 29, 2019 1:49:26 PM CET Chris Wilson wrote:
> From: Janusz Krzysztofik
>
> Name of the i915 module parameter providing fault injection function is
> changing for consistency with a new convention of naming i915 driver
> internal functions called from the driver PCI .probe entry point. Adjust
> the test to use the new name.
>
> [ickle: keep the old parameter name around for stable testing]
>
> Suggested-by: Joonas Lahtinen
> Signed-off-by: Janusz Krzysztofik
> Cc: Michał Wajdeczko
> Cc: Michał Winiarski
> Cc: Piotr Piórkowski
> Cc: Tomasz Lis
> Cc: Joonas Lahtinen
> Reviewed-by: Chris Wilson
> ---
> lib/igt_kmod.c| 40 +++
> lib/igt_kmod.h| 2 ++
> tests/i915/i915_module_load.c | 8 ++-
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> index c3da46678..f43da9f42 100644
> --- a/lib/igt_kmod.c
> +++ b/lib/igt_kmod.c
> @@ -153,6 +153,46 @@ static int modprobe(struct kmod_module *kmod, const
char *options)
> NULL, NULL,
NULL);
> }
>
> +/**
> + * igt_kmod_has_param:
> + * @mod_name: The name of the module
> + * @param: The name of the parameter
> + *
> + * Returns: true if the module has the parameter, false otherwise.
> + */
> +bool igt_kmod_has_param(const char *module_name, const char *param)
> +{
> + struct kmod_module *kmod;
> + struct kmod_list *d, *pre;
> + bool result = false;
> +
> + if (kmod_module_new_from_name(kmod_ctx(), module_name, &kmod))
> + return false;
> +
> + pre = NULL;
> + if (!kmod_module_get_info(kmod, &pre))
> + goto out;
> +
> + kmod_list_foreach(d, pre) {
> + const char *key, *val;
> +
> + key = kmod_module_info_get_key(d);
> + if (strcmp(key, "parmtype"))
> + continue;
> +
> + val = kmod_module_info_get_value(d);
> + if (val && strcmp(val, param) == 0) {
> + result = true;
> + break;
> + }
> + }
> + kmod_module_info_free_list(pre);
> +
> +out:
> + kmod_module_unref(kmod);
> + return result;
> +}
> +
> /**
> * igt_kmod_load:
> * @mod_name: The name of the module
> diff --git a/lib/igt_kmod.h b/lib/igt_kmod.h
> index 87d36d400..e47ff2df6 100644
> --- a/lib/igt_kmod.h
> +++ b/lib/igt_kmod.h
> @@ -31,6 +31,8 @@
> bool igt_kmod_is_loaded(const char *mod_name);
> void igt_kmod_list_loaded(void);
>
> +bool igt_kmod_has_param(const char *mod_name, const char *param);
> +
> int igt_kmod_load(const char *mod_name, const char *opts);
> int igt_kmod_unload(const char *mod_name, unsigned int flags);
>
> diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
> index f42083f53..7d9a5cfd2 100644
> --- a/tests/i915/i915_module_load.c
> +++ b/tests/i915/i915_module_load.c
> @@ -350,11 +350,17 @@ igt_main
> }
>
> igt_subtest("reload-with-fault-injection") {
> + const char *param;
> int i = 0;
>
> igt_i915_driver_unload();
>
> - while (inject_fault("i915", "inject_load_failure", +
+i) == 0)
> + param = "inject_probe_failure";
> + if (!igt_kmod_has_param("i915", param))
> + param = "inject_load_failure";
> + igt_require(igt_kmod_has_param("i915", param));
> +
> + while (inject_fault("i915", param, ++i) == 0)
> ;
My first thought was to just retry the loop with the old parameter name if the
new one fails but I'm OK with your approach (maybe there will be other users
of the new library helper). In case R-b is needed, please tell me.
Thanks,
Janusz
>
> /* We expect to hit at least one fault! */
>
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Re: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>-Original Message-
>From: Shankar, Uma
>Sent: Tuesday, October 29, 2019 6:38 PM
>To: Ville Syrjala ;
>intel-gfx@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>
>
>>-Original Message-
>>From: Intel-gfx On Behalf Of
>>Ville Syrjala
>>Sent: Tuesday, October 8, 2019 9:45 PM
>>To: intel-gfx@lists.freedesktop.org
>>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>>
>>From: Ville Syrjälä
>>
>>According to the spec color keying is not supported with
>>fp16 pixel formats on skl+. Reject that combo.
>>
>>Signed-off-by: Ville Syrjälä
>>---
>> drivers/gpu/drm/i915/display/intel_sprite.c | 18 ++
>> 1 file changed, 18 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
>>b/drivers/gpu/drm/i915/display/intel_sprite.c
>>index cc9e5c9668b1..d6cd46e3f738 100644
>>--- a/drivers/gpu/drm/i915/display/intel_sprite.c
>>+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>>@@ -1689,6 +1689,19 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
>> return 0;
>> }
>>
>>+static bool format_is_fp16(u32 format) {
>>+ switch (format) {
>>+ case DRM_FORMAT_XRGB16161616F:
>>+ case DRM_FORMAT_XBGR16161616F:
>>+ case DRM_FORMAT_ARGB16161616F:
>>+ case DRM_FORMAT_ABGR16161616F:
>>+ return true;
>>+ default:
>>+ return false;
>>+ }
>>+}
>>+
>> static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>>const struct intel_plane_state *plane_state) {
>> @@ -
>>1760,6 +1773,11 @@ static int skl_plane_check_fb(const struct
>>intel_crtc_state *crtc_state,
>> return -EINVAL;
>> }
>>
>>+ if (plane_state->ckey.flags && format_is_fp16(fb->format->format)) {
>>+ DRM_DEBUG_KMS("Color keying not supported with fp16
>>formats\n");
>
>It seems even "Indexed 8 bit formats" also don't support Color Keying. May be
>you
>can extend it to even C8.
wrt C8, at the bit definition of color keying on PLANE_CTL the description says
"Plane color keying is not compatible with the Indexed 8-bit pixel format.",
but on capability it do list C8. So not sure what is correct.
>
>>+ return -EINVAL;
>>+ }
>>+
>> return 0;
>> }
>>
>>--
>>2.21.0
>>
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Re: [Intel-gfx] [PATCH i-g-t] tests/i915_module_load: Use new name of fault injection module parameter
Quoting Janusz Krzysztofik (2019-10-29 13:35:48)
> > diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
> > index f42083f53..7d9a5cfd2 100644
> > --- a/tests/i915/i915_module_load.c
> > +++ b/tests/i915/i915_module_load.c
> > @@ -350,11 +350,17 @@ igt_main
> > }
> >
> > igt_subtest("reload-with-fault-injection") {
> > + const char *param;
> > int i = 0;
> >
> > igt_i915_driver_unload();
> >
> > - while (inject_fault("i915", "inject_load_failure", +
> +i) == 0)
> > + param = "inject_probe_failure";
> > + if (!igt_kmod_has_param("i915", param))
> > + param = "inject_load_failure";
> > + igt_require(igt_kmod_has_param("i915", param));
> > +
> > + while (inject_fault("i915", param, ++i) == 0)
> > ;
>
> My first thought was to just retry the loop with the old parameter name if
> the
> new one fails but I'm OK with your approach (maybe there will be other users
> of the new library helper). In case R-b is needed, please tell me.
I first did the repeated loop as well. I thought people might object to
that as being a little too hacky :)
There's a few more places were we might want to use param probing --
currently we try and ignore modparams as ABI as much as possible!
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/print: cleanup and new drm_device based logging (rev3)
== Series Details == Series: drm/print: cleanup and new drm_device based logging (rev3) URL : https://patchwork.freedesktop.org/series/67795/ State : success == Summary == CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15026_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15026_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-iclb6/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-iclb1/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-iclb6/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preempt-queue-contexts-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +10 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-bsd1.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-snb: [PASS][9] -> [FAIL][10] ([fdo#112037]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb2/igt@gem_persistent_rel...@forked-interruptible-thrashing.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-snb4/igt@gem_persistent_rel...@forked-interruptible-thrashing.html * igt@gem_userptr_blits@map-fixed-invalidate-busy: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-snb2/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@kms_busy@basic-flip-a: - shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl6/igt@kms_b...@basic-flip-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-apl8/igt@kms_b...@basic-flip-a.html * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([fdo#102614]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw5/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-hsw5/igt@kms_cursor_leg...@cursor-vs-flip-varying-size.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#109507]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl2/igt@kms_f...@flip-vs-suspend-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@modeset-vs-vblank-race: - shard-hsw: [PASS][21] -> [DMESG-FAIL][22] ([fdo#102614]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw5/igt@kms_f...@modeset-vs-vblank-race.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-hsw5/igt@kms_f...@modeset-vs-vblank-race.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103167]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb3/igt@kms_frontbuffer_track...@fbc-stridechange.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15026/shard-iclb7/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_plane
[Intel-gfx] [RESEND PATCH] drm/dp: Increase link status size
From: Thierry Reding
The current link status contains bytes 0x202 through 0x207, but we also
want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
so that the post-cursor adjustment can be queried during link training.
Reported-by: coverity-bot
Addresses-Coverity-ID: 1487366 ("Memory - corruptions")
Fixes: 79465e0ffeb9 ("drm/dp: Add helper to get post-cursor adjustments")
Signed-off-by: Thierry Reding
---
include/drm/drm_dp_helper.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 51ecb5112ef8..9581dec900ba 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1121,7 +1121,7 @@
#define DP_MST_PHYSICAL_PORT_0 0
#define DP_MST_LOGICAL_PORT_0 8
-#define DP_LINK_STATUS_SIZE 6
+#define DP_LINK_STATUS_SIZE 11
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
--
2.23.0
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions
== Series Details == Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type definitions URL : https://patchwork.freedesktop.org/series/68664/ State : success == Summary == CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15027_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15027_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_eio@reset-stress: - shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb5/igt@gem_...@reset-stress.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-snb5/igt@gem_...@reset-stress.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb7/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb1/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb8/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_linear_blits@interruptible: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927] / [fdo#112067]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl6/igt@gem_linear_bl...@interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl2/igt@gem_linear_bl...@interruptible.html * igt@gem_linear_blits@normal: - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl6/igt@gem_linear_bl...@normal.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-apl6/igt@gem_linear_bl...@normal.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup: - shard-hsw: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw4/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw5/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-snb: [PASS][17] -> [DMESG-WARN][18] ([fdo#111870]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb6/igt@gem_userptr_bl...@sync-unmap-cycles.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-snb4/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_selftest@live_hangcheck: - shard-hsw: [PASS][19] -> [DMESG-FAIL][20] ([fdo#111991]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw2/igt@i915_selftest@live_hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-hsw6/igt@i915_selftest@live_hangcheck.html - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713] / [fdo#108569]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@i915_selftest@live_hangcheck.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-iclb2/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl1/igt@i915_susp...@sysfs-reader.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15027/shard-skl9/igt@i915_susp...@sysfs-reader.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([fdo#106107]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl5/igt@kms_co...@pipe-b-ctm-0-
Re: [Intel-gfx] [PATCH] drm/dp: Increase link status size
On Tue, Oct 29, 2019 at 03:32:41PM +0200, Jani Nikula wrote: > On Tue, 29 Oct 2019, Thierry Reding wrote: > > From: Thierry Reding > > > > The current link status contains bytes 0x202 through 0x207, but we also > > want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c) > > so that the post-cursor adjustment can be queried during link training. > > We don't currently use this in i915 (we probably should), so the impact > here is that we'll just read more DPCD than before. I quickly perused > i915, and this does not appear to directly break anything. I think the > change is probably fine, but at the same time it freaks me out a bit... > > If you don't mind, please resend this with Cc: > intel-gfx@lists.freedesktop.org to have our CI crunch through it across > a number of platforms. Would give me a warm fuzzy feeling. :) > > With the caveat that I didn't look at any other drivers besides i915, > > Reviewed-by: Jani Nikula Done, thanks. Thierry signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
== Series Details == Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2) URL : https://patchwork.freedesktop.org/series/68654/ State : success == Summary == CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15029_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15029_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-iclb8/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-iclb8/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112146]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-iclb8/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl8/igt@gem_soft...@noreloc-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-apl6/igt@gem_soft...@noreloc-s3.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-snb4/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([fdo#111870]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw4/igt@gem_userptr_bl...@sync-unmap-cycles.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-hsw2/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_selftest@mock_requests: - shard-glk: [PASS][15] -> [INCOMPLETE][16] ([fdo#103359] / [k.org#198133]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-glk9/igt@i915_selftest@mock_requests.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-glk7/igt@i915_selftest@mock_requests.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-skl2/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@plain-flip-ts-check: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#100368]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl10/igt@kms_f...@plain-flip-ts-check.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-skl1/igt@kms_f...@plain-flip-ts-check.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15029/shard-kbl3/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: add support to one DP-MST stream
== Series Details == Series: drm/i915/tgl: add support to one DP-MST stream URL : https://patchwork.freedesktop.org/series/68671/ State : success == Summary == CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15030_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_15030_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs1-dirty-create: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276] / [fdo#112080]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_ctx_isolat...@vcs1-dirty-create.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb5/igt@gem_ctx_isolat...@vcs1-dirty-create.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112146]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb2/igt@gem_exec_as...@concurrent-writes-bsd.html * igt@gem_exec_parallel@vcs1-fds: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb4/igt@gem_exec_sched...@promotion-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb7/igt@gem_exec_sched...@promotion-bsd1.html * igt@gem_userptr_blits@dmabuf-sync: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111870]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-snb2/igt@gem_userptr_bl...@dmabuf-sync.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-snb5/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@sync-unmap-cycles: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([fdo#111870]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-hsw4/igt@gem_userptr_bl...@sync-unmap-cycles.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-hsw2/igt@gem_userptr_bl...@sync-unmap-cycles.html * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] / [fdo#108840]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb8/igt@i915_pm_...@modeset-stress-extra-wait.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb1/igt@i915_pm_...@modeset-stress-extra-wait.html * igt@kms_color@pipe-c-ctm-blue-to-red: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-iclb7/igt@kms_co...@pipe-c-ctm-blue-to-red.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-iclb1/igt@kms_co...@pipe-c-ctm-blue-to-red.html * igt@kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([fdo#110741]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl8/igt@kms_cursor_...@pipe-b-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-skl10/igt@kms_cursor_...@pipe-b-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-apl7/igt@kms_cursor_...@pipe-c-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-suspend.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#105363]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#109507]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7204/shard-skl3/igt@kms_f...@flip-vs-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15030/shard-skl7/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#103167]) +4 similar issues [25]: https://intel-gfx-ci.01.org
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Conclude load -> probe naming convention switch (rev2)
== Series Details == Series: drm/i915: Conclude load -> probe naming convention switch (rev2) URL : https://patchwork.freedesktop.org/series/67454/ State : success == Summary == CI Bug Log - changes from CI_DRM_7209 -> Patchwork_15046 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15046/index.html Known issues Here are the changes found in Patchwork_15046 that come from known issues: ### IGT changes ### Issues hit * igt@gem_flink_basic@double-flink: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7209/fi-icl-u3/igt@gem_flink_ba...@double-flink.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15046/fi-icl-u3/igt@gem_flink_ba...@double-flink.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7209/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15046/fi-icl-u3/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@gem_flink_basic@basic: - fi-icl-u3: [DMESG-WARN][5] ([fdo#107724] / [fdo#112052 ]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7209/fi-icl-u3/igt@gem_flink_ba...@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15046/fi-icl-u3/igt@gem_flink_ba...@basic.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#112052 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112052 Participating hosts (47 -> 41) -- Additional (3): fi-kbl-soraka fi-gdg-551 fi-pnv-d510 Missing(9): fi-ilk-m540 fi-bxt-dsi fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * IGT: IGT_5249 -> IGTPW_3627 * Linux: CI_DRM_7209 -> Patchwork_15046 CI-20190529: 20190529 CI_DRM_7209: 11dd694075dfa8fbf60b2aa67d547652c2541764 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_3627: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3627/index.html IGT_5249: aee019cec9d7f3002371f6ddf102cb67d9976b71 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15046: dbed42546cef3ef052d5a872c4b2251e3428fe6a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dbed42546cef drm/i915: Rename "inject_load_failure" module parameter 2fff720f7c40 drm/i915: Fix i915_inject_load_error() name to read *_probe_* == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15046/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [RFC,1/2] drm/i915: add display uncore helpers
== Series Details == Series: series starting with [RFC,1/2] drm/i915: add display uncore helpers URL : https://patchwork.freedesktop.org/series/68713/ State : warning == Summary == $ dim checkpatch origin/drm-tip dfb3731d13b1 drm/i915: add display uncore helpers -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 36 lines checked 2f185690934e drm/i915/audio: replace I915_*() calls with the new intel_de_*() calls -:314: WARNING:LONG_LINE: line over 100 characters #314: FILE: drivers/gpu/drm/i915/display/intel_audio.c:869: + (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE)); total: 0 errors, 1 warnings, 0 checks, 313 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/perf: ensure selftests select valid format
Gen12 only support a single report format :
I915_OA_FORMAT_A32u40_A4u32_B8_C8
Signed-off-by: Lionel Landwerlin
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
---
drivers/gpu/drm/i915/selftests/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
b/drivers/gpu/drm/i915/selftests/i915_perf.c
index dc6d689e4251..aabd07f67e49 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -23,7 +23,8 @@ test_stream(struct i915_perf *perf)
I915_ENGINE_CLASS_RENDER,
0),
.sample_flags = SAMPLE_OA_REPORT,
- .oa_format = I915_OA_FORMAT_C4_B8,
+ .oa_format = IS_GEN(perf->i915, 12) ?
+ I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_C4_B8,
.metrics_set = 1,
};
struct i915_perf_stream *stream;
--
2.24.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 07/12] drm/i915: Complete crtc hw/uapi split, v4.
On Tue, Oct 29, 2019 at 08:22:24AM +0100, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> before color management is checked.
>
> Changes since v1:
> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
> - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
> Changes since v2:
> - Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
> - Make a intel_crtc_prepare_state() function that clears the crtc_state
> and copies hw members.
> - Remove setting uapi.adjusted_mode, we now have a direct call to
> drm_calc_timestamping_constants().
> Changes since v3:
> - Rename prefix copy_hw_to_uapi_state() with intel_crtc.
> - Copy color blobs to uapi as well.
> - Add a intel_crtc_copy_uapi_to_hw_state_nomodeset() function for clarity.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 44 ++
> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 80 ---
> .../drm/i915/display/intel_display_types.h| 9 ++-
> 4 files changed, 118 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 366275dc113d..557178906ccf 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>
> __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
>
> + /* copy color blobs */
> + if (crtc_state->hw.degamma_lut)
> + drm_property_blob_get(crtc_state->hw.degamma_lut);
> + if (crtc_state->hw.ctm)
> + drm_property_blob_get(crtc_state->hw.ctm);
> + if (crtc_state->hw.gamma_lut)
> + drm_property_blob_get(crtc_state->hw.gamma_lut);
> +
> crtc_state->update_pipe = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> @@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> return &crtc_state->uapi;
> }
>
> +static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
> +{
> + drm_property_blob_put(crtc_state->hw.degamma_lut);
> + drm_property_blob_put(crtc_state->hw.gamma_lut);
> + drm_property_blob_put(crtc_state->hw.ctm);
> +}
> +
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> +{
> + intel_crtc_put_color_blobs(crtc_state);
> +}
> +
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> +{
> + intel_crtc_put_color_blobs(crtc_state);
> +
> + if (crtc_state->uapi.degamma_lut)
> + crtc_state->hw.degamma_lut =
> + drm_property_blob_get(crtc_state->uapi.degamma_lut);
> + else
> + crtc_state->hw.degamma_lut = NULL;
> +
> + if (crtc_state->uapi.gamma_lut)
> + crtc_state->hw.gamma_lut =
> + drm_property_blob_get(crtc_state->uapi.gamma_lut);
> + else
> + crtc_state->hw.gamma_lut = NULL;
> +
> + if (crtc_state->uapi.ctm)
> + crtc_state->hw.ctm =
> + drm_property_blob_get(crtc_state->uapi.ctm);
> + else
> + crtc_state->hw.ctm = NULL;
> +}
> +
> /**
> * intel_crtc_destroy_state - destroy crtc state
> * @crtc: drm crtc
> @@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>
> __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> + intel_crtc_free_hw_state(crtc_state);
> kfree(crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 49d5cb1b9e0a..7b49623419ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -36,6 +36,8 @@ intel_digital_connector_duplicate_state(struct
> drm_connector *connector);
> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 1bc008c094e4..a765794597ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_di
