Re: [Intel-gfx] [PATCH 02/11] drm/i915: Put future HW and their uAPIs under STAGING & BROKEN
On Thu, 24 Oct 2019, Chris Wilson wrote: > We would like some freedom to break the user API/ABI for future HW but > yet still expose the driver for upstream development on that HW. > Currently, we have the i915.force_probe module parameter to avoid binding > to HW while the driver is under development, but that is still a little > too soft with respect to the stringent no-regression rules if we also > plan to be redesigning the uAPI to go along with the new HW. > > To allow the uAPI to be changed during development, only expose that API > and in development HW under STAGING (and BROKEN). Hopefully, making it > explicit that such interfaces to that HW are under development and not > to be blindly enabled by distributions. > > Signed-off-by: Chris Wilson > Cc: Daniel Vetter > Cc: Joonas Lahtinen > Cc: Jani Nikula > Cc: Rodrigo Vivi > Cc: Dave Airlie > --- > drivers/gpu/drm/i915/Kconfig | 8 > drivers/gpu/drm/i915/Kconfig.debug| 1 + > drivers/gpu/drm/i915/Kconfig.unstable | 20 > 3 files changed, 29 insertions(+) > create mode 100644 drivers/gpu/drm/i915/Kconfig.unstable > > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig > index 3c6d57df262d..1fd9e665b742 100644 > --- a/drivers/gpu/drm/i915/Kconfig > +++ b/drivers/gpu/drm/i915/Kconfig > @@ -148,3 +148,11 @@ menu "drm/i915 Profile Guided Optimisation" > depends on DRM_I915 > source "drivers/gpu/drm/i915/Kconfig.profile" > endmenu > + > +menu "drm/i915 Ustable Evolution" > + visible if EXPERT > + visible if STAGING > + visible if BROKEN The kconfig docs fail to mention whether multiple "visible if" statements are combined with OR or AND. The kernel tree lacks any prior art. How about visible if EXPERT && STAGING && BROKEN which should be fine and apparently matches your intent? No biggie though, it's the actually config option that matters. FWIW, this is Acked-by: Jani Nikula though it's Dave's ack that really matters here. BR, Jani. > + depends on DRM_I915 > + source "drivers/gpu/drm/i915/Kconfig.unstable" > +endmenu > diff --git a/drivers/gpu/drm/i915/Kconfig.debug > b/drivers/gpu/drm/i915/Kconfig.debug > index d2ba8f7e5e50..ef123eb29168 100644 > --- a/drivers/gpu/drm/i915/Kconfig.debug > +++ b/drivers/gpu/drm/i915/Kconfig.debug > @@ -44,6 +44,7 @@ config DRM_I915_DEBUG > select DRM_I915_SELFTEST > select DRM_I915_DEBUG_RUNTIME_PM > select DRM_I915_DEBUG_MMIO > + select BROKEN # for prototype uAPI > default n > help > Choose this option to turn on extra driver debugging that may affect > diff --git a/drivers/gpu/drm/i915/Kconfig.unstable > b/drivers/gpu/drm/i915/Kconfig.unstable > new file mode 100644 > index ..ecc8458b5a32 > --- /dev/null > +++ b/drivers/gpu/drm/i915/Kconfig.unstable > @@ -0,0 +1,20 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config DRM_I915_UNSTABLE > + bool "Enable unstable API for early prototype development" > + depends on EXPERT > + depends on STAGING > + depends on BROKEN # should never be enabled by distros! > + # We use the dependency on !COMPILE_TEST to not be enabled in > + # allmodconfig or allyesconfig configurations > + depends on !COMPILE_TEST > + default n > + help > + Enable prototype uAPI under general discussion before they are > + finalized. Such prototypes may be withdrawn or substantially > + changed before release. They are only enabled here so that a wide > + number of interested parties (userspace driver developers) can > + verify that the uAPI meet their expectations. > + > + Recommended for driver developers _only_. > + > + If in the slightest bit of doubt, say "N". -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/cml: Remove unsupport PCI ID
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them avoid unexpected issue.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -448,9 +448,7 @@
#define INTEL_CML_GT1_IDS(info)\
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAB, info), \
INTEL_VGA_DEVICE(0x9BAC, info), \
- INTEL_VGA_DEVICE(0x9BA0, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
@@ -460,9 +458,7 @@
#define INTEL_CML_GT2_IDS(info)\
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCB, info), \
INTEL_VGA_DEVICE(0x9BCC, info), \
- INTEL_VGA_DEVICE(0x9BC0, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
--
2.17.1
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[Intel-gfx] [PATCH 2/2] drm/i915/cml: Separate U sereis pci id from origianl list.
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bd9211b3d76e..e876621f6aaf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -863,6 +863,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CML_U_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CML_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..82d3b193eaec 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -775,6 +775,8 @@ static const u16 subplatform_ult_ids[] = {
INTEL_WHL_U_GT1_IDS(0),
INTEL_WHL_U_GT2_IDS(0),
INTEL_WHL_U_GT3_IDS(0),
+ INTEL_CML_U_GT1_IDS(0),
+ INTEL_CML_U_GT2_IDS(0)
};
static const u16 subplatform_ulx_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 56e823cdc717..02f10c4f5ec7 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -446,24 +446,28 @@
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info)\
- INTEL_VGA_DEVICE(0x9B21, info), \
- INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAC, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
INTEL_VGA_DEVICE(0x9BA2, info)
+#define INTEL_CML_U_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B21, info), \
+ INTEL_VGA_DEVICE(0x9BAA, info), \
+ INTEL_VGA_DEVICE(0x9BAC, info)
+
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info)\
- INTEL_VGA_DEVICE(0x9B41, info), \
- INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCC, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
INTEL_VGA_DEVICE(0x9BC2, info)
+#define INTEL_CML_U_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B41, info), \
+ INTEL_VGA_DEVICE(0x9BCA, info), \
+ INTEL_VGA_DEVICE(0x9BCC, info)
+
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -529,7 +533,9 @@
INTEL_WHL_U_GT3_IDS(info), \
INTEL_AML_CFL_GT2_IDS(info), \
INTEL_CML_GT1_IDS(info), \
- INTEL_CML_GT2_IDS(info)
+ INTEL_CML_GT2_IDS(info), \
+ INTEL_CML_U_GT1_IDS(info), \
+ INTEL_CML_U_GT2_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
--
2.17.1
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/cml: Remove unsupport PCI ID
On Fri, 25 Oct 2019, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some sku
> is not support yet so remove them avoid unexpected issue.
Please elaborate.
BR,
Jani.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Cooper Chiou
> Signed-off-by: Lee Shawn C
> ---
> include/drm/i915_pciids.h | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index a70c982ddff9..56e823cdc717 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -448,9 +448,7 @@
> #define INTEL_CML_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x9B21, info), \
> INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAB, info), \
> INTEL_VGA_DEVICE(0x9BAC, info), \
> - INTEL_VGA_DEVICE(0x9BA0, info), \
> INTEL_VGA_DEVICE(0x9BA5, info), \
> INTEL_VGA_DEVICE(0x9BA8, info), \
> INTEL_VGA_DEVICE(0x9BA4, info), \
> @@ -460,9 +458,7 @@
> #define INTEL_CML_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x9B41, info), \
> INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCB, info), \
> INTEL_VGA_DEVICE(0x9BCC, info), \
> - INTEL_VGA_DEVICE(0x9BC0, info), \
> INTEL_VGA_DEVICE(0x9BC5, info), \
> INTEL_VGA_DEVICE(0x9BC8, info), \
> INTEL_VGA_DEVICE(0x9BC4, info), \
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/cml: Separate U sereis pci id from origianl list.
On Fri, 25 Oct 2019, Lee Shawn C wrote:
> U series device need different DDI buffer setup for eDP
> and DP. If driver did not recognize ULT id proerply.
> The setting for H and S series would be used.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Cooper Chiou
> Signed-off-by: Lee Shawn C
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 2 ++
> include/drm/i915_pciids.h| 20 +---
> 3 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bd9211b3d76e..e876621f6aaf 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -863,6 +863,8 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
> INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
> + INTEL_CML_U_GT1_IDS(&intel_coffeelake_gt1_info),
> + INTEL_CML_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_CNL_IDS(&intel_cannonlake_info),
> INTEL_ICL_11_IDS(&intel_icelake_11_info),
> INTEL_EHL_IDS(&intel_elkhartlake_info),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index f99c9fd497b2..82d3b193eaec 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -775,6 +775,8 @@ static const u16 subplatform_ult_ids[] = {
> INTEL_WHL_U_GT1_IDS(0),
> INTEL_WHL_U_GT2_IDS(0),
> INTEL_WHL_U_GT3_IDS(0),
> + INTEL_CML_U_GT1_IDS(0),
> + INTEL_CML_U_GT2_IDS(0)
Missing comma at the end.
BR,
Jani.
> };
>
> static const u16 subplatform_ulx_ids[] = {
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 56e823cdc717..02f10c4f5ec7 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -446,24 +446,28 @@
>
> /* CML GT1 */
> #define INTEL_CML_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B21, info), \
> - INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAC, info), \
> INTEL_VGA_DEVICE(0x9BA5, info), \
> INTEL_VGA_DEVICE(0x9BA8, info), \
> INTEL_VGA_DEVICE(0x9BA4, info), \
> INTEL_VGA_DEVICE(0x9BA2, info)
>
> +#define INTEL_CML_U_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x9B21, info), \
> + INTEL_VGA_DEVICE(0x9BAA, info), \
> + INTEL_VGA_DEVICE(0x9BAC, info)
> +
> /* CML GT2 */
> #define INTEL_CML_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x9B41, info), \
> - INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCC, info), \
> INTEL_VGA_DEVICE(0x9BC5, info), \
> INTEL_VGA_DEVICE(0x9BC8, info), \
> INTEL_VGA_DEVICE(0x9BC4, info), \
> INTEL_VGA_DEVICE(0x9BC2, info)
>
> +#define INTEL_CML_U_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x9B41, info), \
> + INTEL_VGA_DEVICE(0x9BCA, info), \
> + INTEL_VGA_DEVICE(0x9BCC, info)
> +
> #define INTEL_KBL_IDS(info) \
> INTEL_KBL_GT1_IDS(info), \
> INTEL_KBL_GT2_IDS(info), \
> @@ -529,7 +533,9 @@
> INTEL_WHL_U_GT3_IDS(info), \
> INTEL_AML_CFL_GT2_IDS(info), \
> INTEL_CML_GT1_IDS(info), \
> - INTEL_CML_GT2_IDS(info)
> + INTEL_CML_GT2_IDS(info), \
> + INTEL_CML_U_GT1_IDS(info), \
> + INTEL_CML_U_GT2_IDS(info)
>
> /* CNL */
> #define INTEL_CNL_PORT_F_IDS(info) \
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v3.
Op 24-10-2019 om 17:21 schreef Ville Syrjälä:
> On Thu, Oct 24, 2019 at 02:47:59PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>> Color blobs are copied in crtc atomic_check(), right
>> before color management is checked.
>>
>> Changes since v1:
>> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
>> - Clear crtc_state->hw on disable, instead of using clear_intel_crtc_state().
>> Changes since v2:
>> - Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
>> - Make a intel_crtc_prepare_state() function that clears the crtc_state
>> and copies hw members.
>> - Remove setting uapi.adjusted_mode, we now have a direct call to
>> drm_calc_timestamping_constants().
>>
>> Signed-off-by: Maarten Lankhorst
>> ---
>> drivers/gpu/drm/i915/display/intel_atomic.c | 44 +++
>> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
>> drivers/gpu/drm/i915/display/intel_display.c | 56 +++
>> .../drm/i915/display/intel_display_types.h| 9 +--
>> 4 files changed, 95 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
>> b/drivers/gpu/drm/i915/display/intel_atomic.c
>> index 7cf13b9c7d38..266d0ce9d03d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>>
>> __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
>>
>> +/* copy color blobs */
>> +if (crtc_state->hw.degamma_lut)
>> +drm_property_blob_get(crtc_state->hw.degamma_lut);
>> +if (crtc_state->hw.ctm)
>> +drm_property_blob_get(crtc_state->hw.ctm);
>> +if (crtc_state->hw.gamma_lut)
>> +drm_property_blob_get(crtc_state->hw.gamma_lut);
>> +
>> crtc_state->update_pipe = false;
>> crtc_state->disable_lp_wm = false;
>> crtc_state->disable_cxsr = false;
>> @@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>> return &crtc_state->uapi;
>> }
>>
>> +static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
>> +{
>> +drm_property_blob_put(crtc_state->hw.degamma_lut);
>> +drm_property_blob_put(crtc_state->hw.gamma_lut);
>> +drm_property_blob_put(crtc_state->hw.ctm);
>> +}
>> +
>> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
>> +{
>> +intel_crtc_put_color_blobs(crtc_state);
>> +}
>> +
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> This is only used in intel_display.c so should perhaps live there?
>
>> +{
>> +intel_crtc_put_color_blobs(crtc_state);
>> +
>> +if (crtc_state->uapi.degamma_lut)
>> +crtc_state->hw.degamma_lut =
>> +drm_property_blob_get(crtc_state->uapi.degamma_lut);
>> +else
>> +crtc_state->hw.degamma_lut = NULL;
>> +
>> +if (crtc_state->uapi.gamma_lut)
>> +crtc_state->hw.gamma_lut =
>> +drm_property_blob_get(crtc_state->uapi.gamma_lut);
>> +else
>> +crtc_state->hw.gamma_lut = NULL;
>> +
>> +if (crtc_state->uapi.ctm)
>> +crtc_state->hw.ctm =
>> +drm_property_blob_get(crtc_state->uapi.ctm);
>> +else
>> +crtc_state->hw.ctm = NULL;
>> +}
>> +
>> /**
>> * intel_crtc_destroy_state - destroy crtc state
>> * @crtc: drm crtc
>> @@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>>
>> __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
>> +intel_crtc_free_hw_state(crtc_state);
>> kfree(crtc_state);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
>> b/drivers/gpu/drm/i915/display/intel_atomic.h
>> index 58065d3161a3..42be91e0772a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
>> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
>> @@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct
>> drm_connector *connector);
>> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
>> void intel_crtc_destroy_state(struct drm_crtc *crtc,
>> struct drm_crtc_state *state);
>> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
>> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>> void intel_atomic_state_clear(struct drm_atomic_state *state);
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index 11dd7a182543..2dbc1df9505a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/cml: Remove unsupport PCI ID
== Series Details == Series: series starting with [1/2] drm/i915/cml: Remove unsupport PCI ID URL : https://patchwork.freedesktop.org/series/68547/ State : failure == Summary == Applying: drm/i915/cml: Remove unsupport PCI ID Applying: drm/i915/cml: Separate U sereis pci id from origianl list. error: sha1 information is lacking or useless (include/drm/i915_pciids.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/cml: Separate U sereis pci id from origianl list. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Move intel_engine_context_in/out into intel_lrc.c
From: Tvrtko Ursulin
Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 55 --
drivers/gpu/drm/i915/gt/intel_lrc.c| 55 ++
2 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 97bbdd9773c9..c6895938b626 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -290,61 +290,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
struct drm_printer *m,
const char *header, ...);
-static inline void intel_engine_context_in(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (READ_ONCE(engine->stats.enabled) == 0)
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
-
- if (engine->stats.enabled > 0) {
- if (engine->stats.active++ == 0)
- engine->stats.start = ktime_get();
- GEM_BUG_ON(engine->stats.active == 0);
- }
-
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
-static inline void intel_engine_context_out(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (READ_ONCE(engine->stats.enabled) == 0)
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
-
- if (engine->stats.enabled > 0) {
- ktime_t last;
-
- if (engine->stats.active && --engine->stats.active == 0) {
- /*
-* Decrement the active context count and in case GPU
-* is now idle add up to the running total.
-*/
- last = ktime_sub(ktime_get(), engine->stats.start);
-
- engine->stats.total = ktime_add(engine->stats.total,
- last);
- } else if (engine->stats.active == 0) {
- /*
-* After turning on engine stats, context out might be
-* the first event in which case we account from the
-* time stats gathering was turned on.
-*/
- last = ktime_sub(ktime_get(), engine->stats.enabled_at);
-
- engine->stats.total = ktime_add(engine->stats.total,
- last);
- }
- }
-
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
int intel_enable_engine_stats(struct intel_engine_cs *engine);
void intel_disable_engine_stats(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 73eae85a2cc9..523de1fd4452 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -944,6 +944,61 @@ execlists_context_status_change(struct i915_request *rq,
unsigned long status)
status, rq);
}
+static void intel_engine_context_in(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ if (READ_ONCE(engine->stats.enabled) == 0)
+ return;
+
+ write_seqlock_irqsave(&engine->stats.lock, flags);
+
+ if (engine->stats.enabled > 0) {
+ if (engine->stats.active++ == 0)
+ engine->stats.start = ktime_get();
+ GEM_BUG_ON(engine->stats.active == 0);
+ }
+
+ write_sequnlock_irqrestore(&engine->stats.lock, flags);
+}
+
+static void intel_engine_context_out(struct intel_engine_cs *engine)
+{
+ unsigned long flags;
+
+ if (READ_ONCE(engine->stats.enabled) == 0)
+ return;
+
+ write_seqlock_irqsave(&engine->stats.lock, flags);
+
+ if (engine->stats.enabled > 0) {
+ ktime_t last;
+
+ if (engine->stats.active && --engine->stats.active == 0) {
+ /*
+* Decrement the active context count and in case GPU
+* is now idle add up to the running total.
+*/
+ last = ktime_sub(ktime_get(), engine->stats.start);
+
+ engine->stats.total = ktime_add(engine->stats.total,
+ last);
+ } else if (engine->stats.active == 0) {
+ /*
+* After turning on engine stats, context out might be
+* the first event in which case we account from the
+* time stats gathering was turned on.
+*/
+ last = ktime_sub(ktime_get(), eng
Re: [Intel-gfx] [PATCH 01/11] drm/i915/gem: Make context persistence optional
Quoting Chris Wilson (2019-10-24 14:40:18)
> Our existing behaviour is to allow contexts and their GPU requests to
> persist past the point of closure until the requests are complete. This
> allows clients to operate in a 'fire-and-forget' manner where they can
> setup a rendering pipeline and hand it over to the display server and
> immediately exiting. As the rendering pipeline is kept alive until
> completion, the display server (or other consumer) can use the results
> in the future and present them to the user.
>
> However, not all clients want this persistent behaviour and would prefer
> that the contexts are cleaned up immediately upon closure. This ensures
> that when clients are run without hangchecking, any GPU hang is
> terminated with the process and does not continue to hog resources.
It's worth mentioning GPU compute workloads of indeterminate length
as an example for increased clarity.
> By defining a context property to allow clients to control persistence
> explicitly, we can remove the blanket advice to disable hangchecking
> that seems to be far too prevalent.
I would drop this paragraph from this patch, as it doesn't (yet) make
sense.
> The default behaviour for new controls is the legacy persistence mode.
> New clients will have to opt out for immediate cleanup on context
> closure.
"... have to opt in to immediate ..." reads more clear.
> If the hangchecking modparam is disabled, so is persistent
> context support -- all contexts will be terminated on closure.
Let's add here that it has actually been a source of bug reports
in the past that we don't terminate the workoads. So we expect
this behaviour change to be welcomed by the compute users who
have been instructed to disable the hanghceck in the past.
A couple of comments below. But anyway, with the uAPI comment
and commit message clarified this is:
Reviewed-by: Joonas Lahtinen
Still needs the Link:, though.
> Testcase: igt/gem_ctx_persistence
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michał Winiarski
> Cc: Jon Bloomfield
> Reviewed-by: Jon Bloomfield
> Reviewed-by: Tvrtko Ursulin
> +static int __context_set_persistence(struct i915_gem_context *ctx, bool
> state)
> +{
> + if (i915_gem_context_is_persistent(ctx) == state)
> + return 0;
> +
> + if (state) {
> + /*
> +* Only contexts that are short-lived [that will expire or be
> +* reset] are allowed to survive past termination. We require
> +* hangcheck to ensure that the persistent requests are
> healthy.
> +*/
> + if (!i915_modparams.enable_hangcheck)
> + return -EINVAL;
This is slightly confusing as the default is to enable persistence.
Disabling and re-enabling would result -EINVAL. But I guess it's no
problem to lift such restriction later.
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1572,6 +1572,21 @@ struct drm_i915_gem_context_param {
> * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
> */
> #define I915_CONTEXT_PARAM_ENGINES 0xa
> +
> +/*
> + * I915_CONTEXT_PARAM_PERSISTENCE:
> + *
> + * Allow the context and active rendering to survive the process until
> + * completion. Persistence allows fire-and-forget clients to queue up a
> + * bunch of work, hand the output over to a display server and the quit.
> + * If the context is not marked as persistent, upon closing (either via
".. is marked as not persistent," is more clear.
Regards, Joonas
> + * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
> + * or process termination), the context and any outstanding requests will be
> + * cancelled (and exported fences for cancelled requests marked as -EIO).
> + *
> + * By default, new contexts allow persistence.
> + */
___
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Re: [Intel-gfx] [PATCH] drm/i915: Move intel_engine_context_in/out into intel_lrc.c
Quoting Tvrtko Ursulin (2019-10-25 10:09:52)
> From: Tvrtko Ursulin
>
> Intel_lrc.c is the only caller and so to avoid some header file ordering
> issues in future patches move these two over there.
How much pain would you feel if we did intel_lrc.c +
intel_execlists_submission.c earlier rather than later?
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 55 --
> drivers/gpu/drm/i915/gt/intel_lrc.c| 55 ++
> 2 files changed, 55 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 97bbdd9773c9..c6895938b626 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -290,61 +290,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>struct drm_printer *m,
>const char *header, ...);
>
> -static inline void intel_engine_context_in(struct intel_engine_cs *engine)
> -{
> - unsigned long flags;
> -
> - if (READ_ONCE(engine->stats.enabled) == 0)
> - return;
> -
> - write_seqlock_irqsave(&engine->stats.lock, flags);
> -
> - if (engine->stats.enabled > 0) {
> - if (engine->stats.active++ == 0)
> - engine->stats.start = ktime_get();
> - GEM_BUG_ON(engine->stats.active == 0);
> - }
> -
> - write_sequnlock_irqrestore(&engine->stats.lock, flags);
> -}
> -
> -static inline void intel_engine_context_out(struct intel_engine_cs *engine)
> -{
> - unsigned long flags;
> -
> - if (READ_ONCE(engine->stats.enabled) == 0)
> - return;
> -
> - write_seqlock_irqsave(&engine->stats.lock, flags);
> -
> - if (engine->stats.enabled > 0) {
> - ktime_t last;
> -
> - if (engine->stats.active && --engine->stats.active == 0) {
> - /*
> -* Decrement the active context count and in case GPU
> -* is now idle add up to the running total.
> -*/
> - last = ktime_sub(ktime_get(), engine->stats.start);
> -
> - engine->stats.total = ktime_add(engine->stats.total,
> - last);
> - } else if (engine->stats.active == 0) {
> - /*
> -* After turning on engine stats, context out might be
> -* the first event in which case we account from the
> -* time stats gathering was turned on.
> -*/
> - last = ktime_sub(ktime_get(),
> engine->stats.enabled_at);
> -
> - engine->stats.total = ktime_add(engine->stats.total,
> - last);
> - }
> - }
> -
> - write_sequnlock_irqrestore(&engine->stats.lock, flags);
> -}
> -
> int intel_enable_engine_stats(struct intel_engine_cs *engine);
> void intel_disable_engine_stats(struct intel_engine_cs *engine);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 73eae85a2cc9..523de1fd4452 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -944,6 +944,61 @@ execlists_context_status_change(struct i915_request *rq,
> unsigned long status)
>status, rq);
> }
>
> +static void intel_engine_context_in(struct intel_engine_cs *engine)
stats_in() / stats_out() ?
Now that's it entirely local and we may end up doing other per-context
in/out ops?
Purely mechanical, so
Reviewed-by: Chris Wilson
-Chris
___
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[Intel-gfx] [PATCH] drm/i915/selftests: Tweak the default subtest runtime
BAT is growing a little fat and CI is under pressure and needs to trim
off some redundant runtime. An easy option to reduce the selftest
runtimes, so try halving our default subtest timeout. While this reduces
the number of iterations used, for the majority of tests that are
passing, repeat runs (with different CI_DRM) will make up the
difference -- a negative consequence though is that we may reduce the
frequency of sporadic failures. Hopefully, we have no tests that were
crucially dependent on the fixed 1s timeout...
Suggested-by: Tomi Sarvela
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/selftests/i915_selftest.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c
b/drivers/gpu/drm/i915/selftests/i915_selftest.c
index 92c9193cdc85..a6cca4ad96f6 100644
--- a/drivers/gpu/drm/i915/selftests/i915_selftest.c
+++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c
@@ -30,7 +30,7 @@
#include "igt_flush_test.h"
struct i915_selftest i915_selftest __read_mostly = {
- .timeout_ms = 1000,
+ .timeout_ms = 500,
};
int i915_mock_sanitycheck(void)
--
2.24.0.rc0
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Re: [Intel-gfx] [PATCH] drm/i915/selftests: Tweak the default subtest runtime
On Fri, 25 Oct 2019 at 10:27, Chris Wilson wrote: > > BAT is growing a little fat and CI is under pressure and needs to trim > off some redundant runtime. An easy option to reduce the selftest > runtimes, so try halving our default subtest timeout. While this reduces > the number of iterations used, for the majority of tests that are > passing, repeat runs (with different CI_DRM) will make up the > difference -- a negative consequence though is that we may reduce the > frequency of sporadic failures. Hopefully, we have no tests that were > crucially dependent on the fixed 1s timeout... > > Suggested-by: Tomi Sarvela > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 0/2] Refactor Gen11+ SAGV support
For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. Stanislav Lisovskiy (2): drm/i915: Refactor intel_can_enable_sagv drm/i915: Restrict qgv points which don't have enough bandwidth. drivers/gpu/drm/i915/display/intel_atomic.c | 16 ++ drivers/gpu/drm/i915/display/intel_atomic.h | 3 + drivers/gpu/drm/i915/display/intel_bw.c | 111 ++-- drivers/gpu/drm/i915/display/intel_bw.h | 2 + drivers/gpu/drm/i915/display/intel_display.c | 57 +++- .../drm/i915/display/intel_display_types.h| 11 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 254 +- drivers/gpu/drm/i915/intel_sideband.c | 27 +- 10 files changed, 452 insertions(+), 36 deletions(-) -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 1/2] drm/i915: Refactor intel_can_enable_sagv
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with added sagv block time latency and
check if it fits in DBuf in order to
determine if SAGV can be enabled already
at this stage, just as BSpec 49325 states.
if that fails rollback to usual Level 0
latency and disable SAGV.
- Remove unneeded tabs(James Ausmus)
v3: Rebased the patch
v4: - Added back interlaced check for Gen12 and
added separate function for TGL SAGV check
(thanks to James Ausmus for spotting)
- Removed unneeded gen check
- Extracted Gen12 SAGV decision making code
to a separate function from skl_compute_wm
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
.../drm/i915/display/intel_display_types.h| 8 +
drivers/gpu/drm/i915/intel_pm.c | 254 +-
2 files changed, 254 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8358152e403e..f09c80c96470 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,13 @@ struct intel_atomic_state {
*/
u8 active_pipe_changes;
+ /*
+* For Gen12 only after calculating watermarks with
+* additional latency, we can determine if SAGV can be enabled
+* or not for that particular configuration.
+*/
+ bool gen12_can_sagv;
+
u8 active_pipes;
/* minimum acceptable cdclk for each pipe */
int min_cdclk[I915_MAX_PIPES];
@@ -642,6 +649,7 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm_l0;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 362234449087..b61eb6aaa89b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3751,7 +3751,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool skl_can_enable_sagv(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3817,6 +3817,95 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
return true;
}
+bool icl_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+* If there are no active CRTCs, no additional checks need be performed
+*/
+ if (hweight8(state->active_pipes) == 0)
+ return true;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+new_crtc_state, i) {
+ unsigned int flags = crtc->base.state->adjusted_mode.flags;
+
+ if (flags & DRM_MODE_FLAG_INTERLACE)
+ return false;
+
+ if (!new_crtc_state->base.enable)
+ continue;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+
&new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+!wm->wm[level].plane_en; --level) {
+ }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+* If any of the planes on this pipe don't enable
+* wm levels that incur memory latencies higher than
+* sagv_block_time_us we can't enable SAGV.
+*/
+ if (latency < dev_priv->sagv_block_time_us)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+bool tgl_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int i;
+
+ if (!state->gen12_can_sagv)
+ return
[Intel-gfx] [PATCH v8 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
Reviewed-by: James Ausmus
Signed-off-by: Stanislav Lisovskiy
Cc: Ville Syrjälä
Cc: James Ausmus
---
drivers/gpu/drm/i915/display/intel_atomic.c | 16 +++
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_bw.c | 111 ++
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 57 -
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_sideband.c | 27 -
9 files changed, 198 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index c5a552a69752..b3f4f02f380b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return &crtc_state->base;
}
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ return 0;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..fd17b3ca257f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -7,6 +7,7 @@
#define __INTEL_ATOMIC_H__
#include
+#include "intel_display_types.h"
struct drm_atomic_state;
struct drm_connector;
@@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 22e83f857de8..60249d9776d1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,14 +8,20 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
};
+
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 4
+
struct intel_qgv_info {
- struct intel_qgv_point points[3];
+ struct intel_qgv_point points[NUM_SAGV_POINTS];
u8 num_points;
u8 num_channels;
u8 t_bl;
@@ -113,6 +119,27 @@ static int icl_pcode_read_qgv_point_info(struct
drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move intel_engine_context_in/out into intel_lrc.c
== Series Details ==
Series: drm/i915: Move intel_engine_context_in/out into intel_lrc.c
URL : https://patchwork.freedesktop.org/series/68553/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7181 -> Patchwork_14977
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14977:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_psr@primary_page_flip:
- {fi-tgl-u2}:[PASS][1] -> [SKIP][2] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
Known issues
Here are the changes found in Patchwork_14977 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [PASS][3] -> [SKIP][4] ([fdo#109271]) +26 similar
issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-skl-6770hq/igt@kms_f...@basic-flip-vs-dpms.html
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-icl-u3/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@gem_cpu_reloc@basic:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-icl-u3/igt@gem_cpu_re...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-icl-u3/igt@gem_cpu_re...@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@i915_pm_rpm@module-reload:
- fi-icl-u2: [DMESG-WARN][11] ([fdo#106107] / [fdo#110595]) ->
[DMESG-WARN][12] ([fdo#110595])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7181/fi-icl-u2/igt@i915_pm_...@module-reload.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/fi-icl-u2/igt@i915_pm_...@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 43)
--
Missing(9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7181 -> Patchwork_14977
CI-20190529: 20190529
CI_DRM_7181: 82bef2c192f27eda0e06beba9d3fc5bc6fc12d76 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5238: b82351ff958ea7932e6bb55b7619ce6178fe99c9 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14977: 3a70efbd50947dbd058d0a51c44bfe2319ca9589 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3a70efbd5094 drm/i915: Move intel_engine_context_in/out into intel_lrc.c
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14977/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 08/14] drm/i915: Complete crtc hw/uapi split, v3.
On Fri, Oct 25, 2019 at 11:00:06AM +0200, Maarten Lankhorst wrote:
> Op 24-10-2019 om 17:21 schreef Ville Syrjälä:
> > On Thu, Oct 24, 2019 at 02:47:59PM +0200, Maarten Lankhorst wrote:
> >> Now that we separated everything into uapi and hw, it's
> >> time to make the split definitive. Remove the union and
> >> make a copy of the hw state on modeset and fastset.
> >>
> >> Color blobs are copied in crtc atomic_check(), right
> >> before color management is checked.
> >>
> >> Changes since v1:
> >> - Copy all blobs immediately after drm_atomic_helper_check_modeset().
> >> - Clear crtc_state->hw on disable, instead of using
> >> clear_intel_crtc_state().
> >> Changes since v2:
> >> - Use intel_crtc_free_hw_state + clear in intel_crtc_disable_noatomic().
> >> - Make a intel_crtc_prepare_state() function that clears the crtc_state
> >> and copies hw members.
> >> - Remove setting uapi.adjusted_mode, we now have a direct call to
> >> drm_calc_timestamping_constants().
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> ---
> >> drivers/gpu/drm/i915/display/intel_atomic.c | 44 +++
> >> drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
> >> drivers/gpu/drm/i915/display/intel_display.c | 56 +++
> >> .../drm/i915/display/intel_display_types.h| 9 +--
> >> 4 files changed, 95 insertions(+), 16 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> index 7cf13b9c7d38..266d0ce9d03d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> >> @@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >>
> >>__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
> >>
> >> + /* copy color blobs */
> >> + if (crtc_state->hw.degamma_lut)
> >> + drm_property_blob_get(crtc_state->hw.degamma_lut);
> >> + if (crtc_state->hw.ctm)
> >> + drm_property_blob_get(crtc_state->hw.ctm);
> >> + if (crtc_state->hw.gamma_lut)
> >> + drm_property_blob_get(crtc_state->hw.gamma_lut);
> >> +
> >>crtc_state->update_pipe = false;
> >>crtc_state->disable_lp_wm = false;
> >>crtc_state->disable_cxsr = false;
> >> @@ -208,6 +216,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> >>return &crtc_state->uapi;
> >> }
> >>
> >> +static void intel_crtc_put_color_blobs(struct intel_crtc_state
> >> *crtc_state)
> >> +{
> >> + drm_property_blob_put(crtc_state->hw.degamma_lut);
> >> + drm_property_blob_put(crtc_state->hw.gamma_lut);
> >> + drm_property_blob_put(crtc_state->hw.ctm);
> >> +}
> >> +
> >> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
> >> +{
> >> + intel_crtc_put_color_blobs(crtc_state);
> >> +}
> >> +
> >> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
> > This is only used in intel_display.c so should perhaps live there?
> >
> >> +{
> >> + intel_crtc_put_color_blobs(crtc_state);
> >> +
> >> + if (crtc_state->uapi.degamma_lut)
> >> + crtc_state->hw.degamma_lut =
> >> + drm_property_blob_get(crtc_state->uapi.degamma_lut);
> >> + else
> >> + crtc_state->hw.degamma_lut = NULL;
> >> +
> >> + if (crtc_state->uapi.gamma_lut)
> >> + crtc_state->hw.gamma_lut =
> >> + drm_property_blob_get(crtc_state->uapi.gamma_lut);
> >> + else
> >> + crtc_state->hw.gamma_lut = NULL;
> >> +
> >> + if (crtc_state->uapi.ctm)
> >> + crtc_state->hw.ctm =
> >> + drm_property_blob_get(crtc_state->uapi.ctm);
> >> + else
> >> + crtc_state->hw.ctm = NULL;
> >> +}
> >> +
> >> /**
> >> * intel_crtc_destroy_state - destroy crtc state
> >> * @crtc: drm crtc
> >> @@ -223,6 +266,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> >>struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
> >>
> >>__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> >> + intel_crtc_free_hw_state(crtc_state);
> >>kfree(crtc_state);
> >> }
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> >> b/drivers/gpu/drm/i915/display/intel_atomic.h
> >> index 58065d3161a3..42be91e0772a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> >> @@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct
> >> drm_connector *connector);
> >> struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
> >> void intel_crtc_destroy_state(struct drm_crtc *crtc,
> >> struct drm_crtc_state *state);
> >> +void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
> >> +void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
> >> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> >> void intel_atomic_state_clear(struct drm_atomic_state *state);
> >>
> >> diff --git a/d
Re: [Intel-gfx] [PATCH v8 1/2] drm/i915: Refactor intel_can_enable_sagv
On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark calculation algorithm to
> attempt to calculate Level 0 watermark
> with added sagv block time latency and
> check if it fits in DBuf in order to
> determine if SAGV can be enabled already
> at this stage, just as BSpec 49325 states.
> if that fails rollback to usual Level 0
> latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
>
> v3: Rebased the patch
>
> v4: - Added back interlaced check for Gen12 and
> added separate function for TGL SAGV check
> (thanks to James Ausmus for spotting)
> - Removed unneeded gen check
> - Extracted Gen12 SAGV decision making code
> to a separate function from skl_compute_wm
>
> Signed-off-by: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Cc: James Ausmus
> ---
> .../drm/i915/display/intel_display_types.h| 8 +
> drivers/gpu/drm/i915/intel_pm.c | 254 +-
> 2 files changed, 254 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8358152e403e..f09c80c96470 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,13 @@ struct intel_atomic_state {
>*/
> u8 active_pipe_changes;
>
> + /*
> + * For Gen12 only after calculating watermarks with
> + * additional latency, we can determine if SAGV can be enabled
> + * or not for that particular configuration.
> + */
> + bool gen12_can_sagv;
> +
> u8 active_pipes;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> @@ -642,6 +649,7 @@ struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm_l0;
sagv_wm0 (or maybe even just sagv_wm) would be a bit less ugly
name I think.
> bool is_planar;
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 362234449087..b61eb6aaa89b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3751,7 +3751,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool skl_can_enable_sagv(struct intel_atomic_state *state)
> {
> struct drm_device *dev = state->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3817,6 +3817,95 @@ bool intel_can_enable_sagv(struct intel_atomic_state
> *state)
> return true;
> }
>
> +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> + /*
> + * If there are no active CRTCs, no additional checks need be performed
> + */
> + if (hweight8(state->active_pipes) == 0)
> + return true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + unsigned int flags = crtc->base.state->adjusted_mode.flags;
> +
> + if (flags & DRM_MODE_FLAG_INTERLACE)
> + return false;
> +
> + if (!new_crtc_state->base.enable)
> + continue;
Do we use active or enable elsewhere to decide whether to compute wms
for a pipe? Should be consistent here so we don't get into some wonky
state where we didn't compute normal wms but are computing the sagv wm.
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> +
> &new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> + !wm->wm[level].plane_en; --level) {
> + }
> +
> + latency = dev_priv->wm.skl_latency[level];
> +
> + /*
> + * If any of the planes on this pipe don't enable
> + * wm levels that incur memory late
Re: [Intel-gfx] [PATCH v8 1/2] drm/i915: Refactor intel_can_enable_sagv
On Fri, 2019-10-25 at 13:24 +0300, Ville Syrjälä wrote:
> On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> >
> > v2:
> > - Rework watermark calculation algorithm to
> > attempt to calculate Level 0 watermark
> > with added sagv block time latency and
> > check if it fits in DBuf in order to
> > determine if SAGV can be enabled already
> > at this stage, just as BSpec 49325 states.
> > if that fails rollback to usual Level 0
> > latency and disable SAGV.
> > - Remove unneeded tabs(James Ausmus)
> >
> > v3: Rebased the patch
> >
> > v4: - Added back interlaced check for Gen12 and
> > added separate function for TGL SAGV check
> > (thanks to James Ausmus for spotting)
> > - Removed unneeded gen check
> > - Extracted Gen12 SAGV decision making code
> > to a separate function from skl_compute_wm
> >
> > Signed-off-by: Stanislav Lisovskiy
> > Cc: Ville Syrjälä
> > Cc: James Ausmus
> > ---
> > .../drm/i915/display/intel_display_types.h| 8 +
> > drivers/gpu/drm/i915/intel_pm.c | 254
> > +-
> > 2 files changed, 254 insertions(+), 8 deletions(-)
> >
> >
> Do we use active or enable elsewhere to decide whether to compute wms
> for a pipe? Should be consistent here so we don't get into some wonky
> state where we didn't compute normal wms but are computing the sagv
> wm.
Good question, I have seen it either this or that everywhere, so we
probably need to discuss which one I should use.
>
> > +
> > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > + struct skl_plane_wm *wm =
> > + &new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +
> > + /* Skip this plane if it's not enabled */
> > + if (!wm->wm[0].plane_en)
> > + continue;
> > +
> > + /* Find the highest enabled wm level for this
> > plane */
> > + for (level = ilk_wm_max_level(dev_priv);
> > +!wm->wm[level].plane_en; --level) {
> > + }
> > +
> > + latency = dev_priv->wm.skl_latency[level];
> > +
> > + /*
> > +* If any of the planes on this pipe don't
> > enable
> > +* wm levels that incur memory latencies higher
> > than
> > +* sagv_block_time_us we can't enable SAGV.
> > +*/
> > + if (latency < dev_priv->sagv_block_time_us)
> > + return false;
> > + }
> > + }
> > +
> > + return true;
> > +}
> > +
> >
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > + struct drm_device *dev = state->base.dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > +
> > + if (INTEL_GEN(dev_priv) >= 12)
> > + return tgl_can_enable_sagv(state);
> > + else if (INTEL_GEN(dev_priv) == 11)
> > + return icl_can_enable_sagv(state);
> > +
> > + return skl_can_enable_sagv(state);
>
> Why do we have three separate code paths now? I believe there should
> be
> just two.
>
> Also if you go to the trouble of adding dev_priv->..can_sagv just
> make
> it work for all platforms.
..can_sagv is not in dev_priv - it is part of intel_atomic_state,
so at least here I avoided using dev_priv.
>
> >
> >
> > + /*
> > +* Lets assume we can tolerate SAGV for now,
> > +* until watermark calculations prove the opposite
> > +* if any of the pipe planes in the state will
> > +* fail the requirements it will be assigned to false
> > +* in skl_compute_ddb.
> > +*/
> > + state->gen12_can_sagv = true;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > + new_crtc_state, i) {
> > + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > + if (ret) {
> > + state->gen12_can_sagv = false;
> > + break;
> + }
>
> This is not going to work. We need the infromation from _all_ pipes,
> not
> just the ones in the state. We probably want to make that can_sagv
> thing
> a bitmask of pipes so that we don't have to have all pipes in the
> state.
But isn't it so that even if at least one plane/pipe can't tolerate
SAGV, we can't enable it already? So what is the point of checking
other planes/pipes then?
Or may be I'm missing something here.
>
> > + }
> > +
> > + if (state->gen12_can_sagv) {
> > + /*
> > +* If we determined that we can actually enable SAGV,
> > then
> > +* actually use those levels
> > tgl_check_pipe_fits_sagv_wm
>
[Intel-gfx] [PATCH i-g-t] benchmarks/gem_wsim: Cleanup register access on exit
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 87f873b0e..337e13f91 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -3072,8 +3072,6 @@ static void init_clocks(void)
uint32_t rcs_start, rcs_end;
double overhead, t;
- intel_register_access_init(&mmio_data, intel_get_pci_device(), false,
fd);
-
if (verbose <= 1)
return;
@@ -3114,6 +3112,7 @@ int main(int argc, char **argv)
struct w_arg *w_args = NULL;
unsigned int tolerance_pct = 1;
const struct workload_balancer *balancer = NULL;
+ int exitcode = EXIT_FAILURE;
char *endptr = NULL;
int prio = 0;
double t;
@@ -3128,6 +3127,8 @@ int main(int argc, char **argv)
fd = __drm_open_driver(DRIVER_INTEL);
igt_require(fd);
+ intel_register_access_init(&mmio_data, intel_get_pci_device(), false,
fd);
+
init_clocks();
master_prng = time(NULL);
@@ -3138,7 +3139,7 @@ int main(int argc, char **argv)
case 'W':
if (master_workload >= 0) {
wsim_err("Only one master workload can be
given!\n");
- return 1;
+ goto err;
}
master_workload = nr_w_args;
/* Fall through */
@@ -3152,7 +3153,7 @@ int main(int argc, char **argv)
case 'a':
if (append_workload_arg) {
wsim_err("Only one append workload can be
given!\n");
- return 1;
+ goto err;
}
append_workload_arg = optarg;
break;
@@ -3217,7 +3218,7 @@ int main(int argc, char **argv)
if (!balancer) {
wsim_err("Unknown balancing mode '%s'!\n",
optarg);
- return 1;
+ goto err;
}
break;
case 'I':
@@ -3225,20 +3226,20 @@ int main(int argc, char **argv)
break;
case 'h':
print_help();
- return 0;
+ goto out;
default:
- return 1;
+ goto err;
}
}
if ((flags & HEARTBEAT) && !(flags & SEQNO)) {
wsim_err("Heartbeat needs a seqno based balancer!\n");
- return 1;
+ goto err;
}
if ((flags & VCS2REMAP) && (flags & I915)) {
wsim_err("VCS remapping not supported with i915 balancing!\n");
- return 1;
+ goto err;
}
if (!nop_calibration) {
@@ -3250,29 +3251,29 @@ int main(int argc, char **argv)
printf("Nop calibration for %uus delay is %lu.\n",
nop_calibration_us, nop_calibration);
- return 0;
+ goto out;
}
if (!nr_w_args) {
wsim_err("No workload descriptor(s)!\n");
- return 1;
+ goto err;
}
if (nr_w_args > 1 && clients > 1) {
wsim_err("Cloned clients cannot be combined with multiple
workloads!\n");
- return 1;
+ goto err;
}
if ((flags & GLOBAL_BALANCE) && !balancer) {
wsim_err("Balancer not specified in global balancing mode!\n");
- return 1;
+ goto err;
}
if (append_workload_arg) {
append_workload_arg =
load_workload_descriptor(append_workload_arg);
if (!append_workload_arg) {
wsim_err("Failed to load append workload
descriptor!\n");
- return 1;
+ goto err;
}
}
@@ -3281,7 +3282,7 @@ int main(int argc, char **argv)
app_w = parse_workload(&arg, flags, NULL);
if (!app_w) {
wsim_err("Failed to parse append workload!\n");
- return 1;
+ goto err;
}
}
@@ -3293,13 +3294,13 @@ int main(int argc, char **argv)
if (!w_args[i].desc) {
wsim_err("Failed to load workload descriptor %u!\n", i);
- return 1;
+ goto err;
}
wrk[i] = parse_workload(&w_args[i], flags, app_w);
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Tweak the default subtest runtime
== Series Details ==
Series: drm/i915/selftests: Tweak the default subtest runtime
URL : https://patchwork.freedesktop.org/series/68554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7182 -> Patchwork_14978
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/index.html
Known issues
Here are the changes found in Patchwork_14978 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@bad-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-icl-u3/igt@gem_ba...@bad-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-icl-u3/igt@gem_ba...@bad-close.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-r: [PASS][3] -> [INCOMPLETE][4] ([fdo#111975])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-kbl-r/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
Possible fixes
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-icl-u3/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8109u: [DMESG-FAIL][7] ([fdo#112050 ]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-skl-iommu: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-skl-iommu/igt@i915_selftest@live_gt_heartbeat.html
* {igt@i915_selftest@live_gt_timelines}:
- {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111831]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-tgl-u/igt@i915_selftest@live_gt_timelines.html
* igt@i915_selftest@live_hangcheck:
- {fi-icl-guc}: [INCOMPLETE][13] ([fdo#107713] / [fdo#108569]) ->
[PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][15] ([fdo#111600]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7182/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14978/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111831]: https://bugs.freedesktop.org/show_bug.cgi?id=111831
[fdo#111975]: https://bugs.freedesktop.org/show_bug.cgi?id=111975
[fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (52 -> 43)
--
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7182 -> Patchwork_14978
CI-20190529: 20190529
CI_DRM_7182: 7000e765954904ea5a55ab4c60366b113221ec71 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5239: fb817cd37bcd5192d5749d464129a31c7bb852e5 @
git://anongit.freedesktop.org/xorg/app/int
Re: [Intel-gfx] [PATCH v8 1/2] drm/i915: Refactor intel_can_enable_sagv
On Fri, 2019-10-25 at 10:44 +, Lisovskiy, Stanislav wrote:
> On Fri, 2019-10-25 at 13:24 +0300, Ville Syrjälä wrote:
> > On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy
> > wrote:
> > > Currently intel_can_enable_sagv function contains
> > > a mix of workarounds for different platforms
> > > some of them are not valid for gens >= 11 already,
> > > so lets split it into separate functions.
> > >
> > > v2:
> > > - Rework watermark calculation algorithm to
> > > attempt to calculate Level 0 watermark
> > > with added sagv block time latency and
> > > check if it fits in DBuf in order to
> > > determine if SAGV can be enabled already
> > > at this stage, just as BSpec 49325 states.
> > > if that fails rollback to usual Level 0
> > > latency and disable SAGV.
> > > - Remove unneeded tabs(James Ausmus)
> > >
> > > v3: Rebased the patch
> > >
> > > v4: - Added back interlaced check for Gen12 and
> > > added separate function for TGL SAGV check
> > > (thanks to James Ausmus for spotting)
> > > - Removed unneeded gen check
> > > - Extracted Gen12 SAGV decision making code
> > > to a separate function from skl_compute_wm
> > >
> > > Signed-off-by: Stanislav Lisovskiy > > >
> > > Cc: Ville Syrjälä
> > > Cc: James Ausmus
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 8 +
> > > drivers/gpu/drm/i915/intel_pm.c | 254
> > > +-
> > > 2 files changed, 254 insertions(+), 8 deletions(-)
> > >
> > >
> >
> > >
> > >
> > > + /*
> > > + * Lets assume we can tolerate SAGV for now,
> > > + * until watermark calculations prove the opposite
> > > + * if any of the pipe planes in the state will
> > > + * fail the requirements it will be assigned to false
> > > + * in skl_compute_ddb.
> > > + */
> > > + state->gen12_can_sagv = true;
> > > +
> > > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > + new_crtc_state, i) {
> > > + ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > > + if (ret) {
> > > + state->gen12_can_sagv = false;
> > > + break;
> >
> > + }
> >
> > This is not going to work. We need the infromation from _all_
> > pipes,
> > not
> > just the ones in the state. We probably want to make that can_sagv
> > thing
> > a bitmask of pipes so that we don't have to have all pipes in the
> > state.
>
> But isn't it so that even if at least one plane/pipe can't tolerate
> SAGV, we can't enable it already? So what is the point of checking
> other planes/pipes then?
> Or may be I'm missing something here.
Ok, I think I get your point actually. As we don't have all pipes in
the state we might wrongly come to conclusion that we can enable SAGV
here. Also probably it really means that I will have to move
gen12_can_sagv from intel_atomic_state to our favourite dev_priv struct
as we will have to track all of the pipes in global state.
Regarding 3 different code paths from can_enable_sagv problem is that
in reality as I understand those are different, for example we disable
SAGV for SKL if there multiple active pipes, while for ICL we don't.
Also as we discussed ICL and TGL have completely different ways of
treating sagv_block_time(at least according to current BSpec) I could
unite all of those functions to one however it
would then contains multiple platform checks and stuff like that.
>
> >
> > > + }
> > > +
> > > + if (state->gen12_can_sagv) {
> > > + /*
> > > + * If we determined that we can actually enable SAGV,
> > > then
> > > + * actually use those levels
> > > tgl_check_pipe_fits_sagv_wm
> > > + * has already taken care of checking if L0 + sagv
> > > block time
> > > + * fits into ddb.
> > > + */
> > > + for_each_oldnew_intel_crtc_in_state(state, crtc,
> > > old_crtc_state,
> > > + new_crtc_state, i) {
> > > + struct intel_plane *plane;
> > > + for_each_intel_plane_on_crtc(&dev_priv->drm,
> > > crtc, plane) {
> > > + enum plane_id plane_id = plane->id;
> > > + struct skl_plane_wm *plane_wm = \
> > > + &new_crtc_state-
> > > > wm.skl.optimal.planes[plane_id];
> > >
> > > + struct skl_wm_level *sagv_wm0 =
> > > &plane_wm->sagv_wm_l0;
> > > + struct skl_wm_level *l0_wm0 =
> > > &plane_wm->wm[0];
> > > +
> > > + memcpy(l0_wm0, sagv_wm0, sizeof(struct
> > > skl_wm_level));
> > > + }
> > > + }
> > > + }
> > > +}
> > > +
> > > static int
> > > skl_compute_wm(struct intel_atomic_state *state)
> > > {
> > > + struct drm_device *dev = state->base.dev;
> > > + const struct drm_i915_private *dev_priv = to_i915(dev);
> > > struct intel_crtc *c
[Intel-gfx] [PATCH] drm/i915/selftests/blt: add some kthreads into the mix
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture of ctx priorities per thread to make pre-emption a
possibility.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
.../i915/gem/selftests/i915_gem_object_blt.c | 144 +++---
1 file changed, 121 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 9ec55b3a3815..41e0bd6a175c 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -7,34 +7,53 @@
#include "i915_selftest.h"
+#include "gem/i915_gem_context.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
#include "selftests/mock_drm.h"
#include "huge_gem_object.h"
#include "mock_context.h"
-static int igt_fill_blt(void *arg)
+struct igt_thread_arg {
+ struct drm_i915_private *i915;
+ struct rnd_state *prng;
+};
+
+static int igt_fill_blt_thread(void *arg)
{
- struct drm_i915_private *i915 = arg;
- struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct igt_thread_arg *thread = arg;
+ struct drm_i915_private *i915 = thread->i915;
+ struct rnd_state *prng = thread->prng;
struct drm_i915_gem_object *obj;
- struct rnd_state prng;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ unsigned int prio;
IGT_TIMEOUT(end);
- u32 *vaddr;
- int err = 0;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_file;
+ }
- prandom_seed_state(&prng, i915_selftest.random_seed);
+ prio = prandom_u32_state(prng) % I915_PRIORITY_MAX;
+ ctx->sched.priority = I915_USER_PRIORITY(prio);
- /*
-* XXX: needs some threads to scale all these tests, also maybe throw
-* in submission from higher priority context to see if we are
-* preempted for very large objects...
-*/
+ ce = i915_gem_context_get_engine(ctx, BCS0);
+ GEM_BUG_ON(IS_ERR(ce));
do {
const u32 max_block_size = S16_MAX * PAGE_SIZE;
- u32 sz = min_t(u64, ce->vm->total >> 4,
prandom_u32_state(&prng));
+ u32 sz = min_t(u64, ce->vm->total >> 4,
prandom_u32_state(prng));
u32 phys_sz = sz % (max_block_size + 1);
- u32 val = prandom_u32_state(&prng);
+ u32 val = prandom_u32_state(prng);
+ u32 *vaddr;
u32 i;
sz = round_up(sz, PAGE_SIZE);
@@ -98,26 +117,47 @@ static int igt_fill_blt(void *arg)
if (err == -ENOMEM)
err = 0;
+ intel_context_put(ce);
+out_file:
+ mock_file_free(i915, file);
return err;
}
-static int igt_copy_blt(void *arg)
+static int igt_copy_blt_thread(void *arg)
{
- struct drm_i915_private *i915 = arg;
- struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct igt_thread_arg *thread = arg;
+ struct drm_i915_private *i915 = thread->i915;
+ struct rnd_state *prng = thread->prng;
struct drm_i915_gem_object *src, *dst;
- struct rnd_state prng;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ unsigned int prio;
IGT_TIMEOUT(end);
- u32 *vaddr;
- int err = 0;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_file;
+ }
- prandom_seed_state(&prng, i915_selftest.random_seed);
+ prio = prandom_u32_state(prng) % I915_PRIORITY_MAX;
+ ctx->sched.priority = I915_USER_PRIORITY(prio);
+
+ ce = i915_gem_context_get_engine(ctx, BCS0);
+ GEM_BUG_ON(IS_ERR(ce));
do {
const u32 max_block_size = S16_MAX * PAGE_SIZE;
- u32 sz = min_t(u64, ce->vm->total >> 4,
prandom_u32_state(&prng));
+ u32 sz = min_t(u64, ce->vm->total >> 4,
prandom_u32_state(prng));
u32 phys_sz = sz % (max_block_size + 1);
- u32 val = prandom_u32_state(&prng);
+ u32 val = prandom_u32_state(prng);
+ u32 *vaddr;
u32 i;
sz = round_up(sz, PAGE_SIZE);
@@ -201,9 +241,67 @@ static int igt_copy_blt(void *arg)
if (err == -EN
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> Hi,
>
> Thanks for your review and comments. Please see inline below.
>
> On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> wrote:
> >
> > On Tue, Oct 22, 2019 at 05:12:06PM -0700, Rajat Jain wrote:
> > > Certain laptops now come with panels that have integrated privacy
> > > screens on them. This patch adds support for such panels by adding
> > > a privacy-screen property to the drm_connector for the panel, that
> > > the userspace can then use to control and check the status. The idea
> > > was discussed here:
> > >
> > > https://lkml.org/lkml/2019/10/1/786
> > >
> > > ACPI methods are used to identify, query and control privacy screen:
> > >
> > > * Identifying an ACPI object corresponding to the panel: The patch
> > > follows ACPI Spec 6.3 (available at
> > > https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf).
> > > Pages 1119 - 1123 describe what I believe, is a standard way of
> > > identifying / addressing "display panels" in the ACPI tables, thus
> > > allowing kernel to attach ACPI nodes to the panel. IMHO, this ability
> > > to identify and attach ACPI nodes to drm connectors may be useful for
> > > reasons other privacy-screens, in future.
> > >
> > > * Identifying the presence of privacy screen, and controlling it, is done
> > > via ACPI _DSM methods.
> > >
> > > Currently, this is done only for the Intel display ports. But in future,
> > > this can be done for any other ports if the hardware becomes available
> > > (e.g. external monitors supporting integrated privacy screens?).
> > >
> > > Also, this code can be extended in future to support non-ACPI methods
> > > (e.g. using a kernel GPIO driver to toggle a gpio that controls the
> > > privacy-screen).
> > >
> > > Signed-off-by: Rajat Jain
> > > ---
> > > drivers/gpu/drm/Makefile| 1 +
> > > drivers/gpu/drm/drm_atomic_uapi.c | 5 +
> > > drivers/gpu/drm/drm_connector.c | 38 +
> > > drivers/gpu/drm/drm_privacy_screen.c| 176
> > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> > > include/drm/drm_connector.h | 18 +++
> > > include/drm/drm_mode_config.h | 7 +
> > > include/drm/drm_privacy_screen.h| 33 +
> > > 8 files changed, 281 insertions(+)
> > > create mode 100644 drivers/gpu/drm/drm_privacy_screen.c
> > > create mode 100644 include/drm/drm_privacy_screen.h
> >
> > I like this much better than the prior proposal to use sysfs. However
> > the support currently looks a bit tangled. I realize that we only have a
> > single implementation for this in hardware right now, so there's no use
> > in over-engineering things, but I think we can do a better job from the
> > start without getting into too many abstractions. See below.
> >
> > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > > index 82ff826b33cc..e1fc33d69bb7 100644
> > > --- a/drivers/gpu/drm/Makefile
> > > +++ b/drivers/gpu/drm/Makefile
> > > @@ -19,6 +19,7 @@ drm-y := drm_auth.o drm_cache.o \
> > > drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
> > > drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o
> > >
> > > +drm-$(CONFIG_ACPI) += drm_privacy_screen.o
> > > drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o
> > > drm_dma.o drm_scatter.o drm_lock.o
> > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
> > > drm-$(CONFIG_DRM_VM) += drm_vm.o
> > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > index 7a26bfb5329c..44131165e4ea 100644
> > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > @@ -30,6 +30,7 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > >
> > > @@ -766,6 +767,8 @@ static int drm_atomic_connector_set_property(struct
> > > drm_connector *connector,
> > > fence_ptr);
> > > } else if (property == connector->max_bpc_property) {
> > > state->max_requested_bpc = val;
> > > + } else if (property == config->privacy_screen_property) {
> > > + drm_privacy_screen_set_val(connector, val);
> >
> > This doesn't look right. Shouldn't you store the value in the connector
> > state and then leave it up to the connector driver to set it
> > appropriately? I think that also has the advantage of untangling this
> > support a little.
>
> Hopefully this gets answered in my explanations below.
>
> >
> > > } else if (connector->funcs->atomic_set_property) {
> > > return connector->funcs->atomic_set_property(connector,
> > > state, property, val);
> > > @@ -842,6 +845,8 @@ drm_atomic_connector_get_property(struct
> > > drm_connector *connector,
> > > *val = 0;
> > > } else if (property == connect
Re: [Intel-gfx] [PATCH] drm/i915/selftests/blt: add some kthreads into the mix
Quoting Matthew Auld (2019-10-25 12:24:42)
> We can be more aggressive in our testing by launching a number of
> kthreads, where each is submitting its own copy or fill batches on a set
> of random sized objects. Also since the underlying fill and copy batches
> can be pre-empted mid-batch(for particularly large objects), throw in a
> random mixture of ctx priorities per thread to make pre-emption a
> possibility.
>
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> .../i915/gem/selftests/i915_gem_object_blt.c | 144 +++---
> 1 file changed, 121 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> index 9ec55b3a3815..41e0bd6a175c 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
> @@ -7,34 +7,53 @@
>
> #include "i915_selftest.h"
>
> +#include "gem/i915_gem_context.h"
> #include "selftests/igt_flush_test.h"
> +#include "selftests/i915_random.h"
> #include "selftests/mock_drm.h"
> #include "huge_gem_object.h"
> #include "mock_context.h"
>
> -static int igt_fill_blt(void *arg)
> +struct igt_thread_arg {
> + struct drm_i915_private *i915;
> + struct rnd_state *prng;
> +};
> +
> +static int igt_fill_blt_thread(void *arg)
> {
> - struct drm_i915_private *i915 = arg;
> - struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> + struct igt_thread_arg *thread = arg;
> + struct drm_i915_private *i915 = thread->i915;
> + struct rnd_state *prng = thread->prng;
> struct drm_i915_gem_object *obj;
> - struct rnd_state prng;
> + struct i915_gem_context *ctx;
> + struct intel_context *ce;
> + struct drm_file *file;
> + unsigned int prio;
> IGT_TIMEOUT(end);
> - u32 *vaddr;
> - int err = 0;
> + int err;
> +
> + file = mock_file(i915);
> + if (IS_ERR(file))
> + return PTR_ERR(file);
> +
> + ctx = live_context(i915, file);
> + if (IS_ERR(ctx)) {
> + err = PTR_ERR(ctx);
> + goto out_file;
> + }
>
> - prandom_seed_state(&prng, i915_selftest.random_seed);
> + prio = prandom_u32_state(prng) % I915_PRIORITY_MAX;
> + ctx->sched.priority = I915_USER_PRIORITY(prio);
>
> - /*
> -* XXX: needs some threads to scale all these tests, also maybe throw
> -* in submission from higher priority context to see if we are
> -* preempted for very large objects...
> -*/
> + ce = i915_gem_context_get_engine(ctx, BCS0);
> + GEM_BUG_ON(IS_ERR(ce));
>
> do {
> const u32 max_block_size = S16_MAX * PAGE_SIZE;
> - u32 sz = min_t(u64, ce->vm->total >> 4,
> prandom_u32_state(&prng));
> + u32 sz = min_t(u64, ce->vm->total >> 4,
> prandom_u32_state(prng));
> u32 phys_sz = sz % (max_block_size + 1);
> - u32 val = prandom_u32_state(&prng);
> + u32 val = prandom_u32_state(prng);
> + u32 *vaddr;
> u32 i;
>
> sz = round_up(sz, PAGE_SIZE);
> @@ -98,26 +117,47 @@ static int igt_fill_blt(void *arg)
> if (err == -ENOMEM)
> err = 0;
>
> + intel_context_put(ce);
> +out_file:
> + mock_file_free(i915, file);
> return err;
> }
>
> -static int igt_copy_blt(void *arg)
> +static int igt_copy_blt_thread(void *arg)
> {
> - struct drm_i915_private *i915 = arg;
> - struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> + struct igt_thread_arg *thread = arg;
> + struct drm_i915_private *i915 = thread->i915;
> + struct rnd_state *prng = thread->prng;
> struct drm_i915_gem_object *src, *dst;
> - struct rnd_state prng;
> + struct i915_gem_context *ctx;
> + struct intel_context *ce;
> + struct drm_file *file;
> + unsigned int prio;
> IGT_TIMEOUT(end);
> - u32 *vaddr;
> - int err = 0;
> + int err;
> +
> + file = mock_file(i915);
> + if (IS_ERR(file))
> + return PTR_ERR(file);
> +
> + ctx = live_context(i915, file);
> + if (IS_ERR(ctx)) {
> + err = PTR_ERR(ctx);
> + goto out_file;
> + }
>
> - prandom_seed_state(&prng, i915_selftest.random_seed);
> + prio = prandom_u32_state(prng) % I915_PRIORITY_MAX;
prio = i915_prandom_u32_max_state(prng, I915_PRIORITY_MAX);
Usual prng dilemma of high bits being more random than low bits, and it
avoids the divide. (Nice trick to remember :)
> + ctx->sched.priority = I915_USER_PRIORITY(prio);
> +
> + ce = i915_gem_context_get_engine(ctx, BCS0);
> + GEM_BUG_ON(IS_ERR(ce));
>
> do {
> const u32 max_block_size = S16_MAX * PAGE_SIZE;
> -
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/bios: add compression parameter block definition (rev2)
== Series Details ==
Series: drm/i915/bios: add compression parameter block definition (rev2)
URL : https://patchwork.freedesktop.org/series/68396/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7169_full -> Patchwork_14961_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14961_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14961_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14961_full:
### IGT changes ###
Possible regressions
* igt@gem_ctx_shared@q-promotion-bsd1:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-skl5/igt@gem_ctx_sha...@q-promotion-bsd1.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-skl10/igt@gem_ctx_sha...@q-promotion-bsd1.html
* igt@gem_exec_parallel@fds:
- shard-kbl: NOTRUN -> [FAIL][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-kbl6/igt@gem_exec_paral...@fds.html
Warnings
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [SKIP][4] ([fdo#111325]) -> [FAIL][5]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb4/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-iclb3/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ctx_shared@q-promotion-bsd1:
- {shard-tglb}: [PASS][6] -> [FAIL][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-tglb7/igt@gem_ctx_sha...@q-promotion-bsd1.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-tglb8/igt@gem_ctx_sha...@q-promotion-bsd1.html
Known issues
Here are the changes found in Patchwork_14961_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +6
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-kbl4/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_switch@vcs1-heavy:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#112080]) +11 similar
issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb4/igt@gem_ctx_swi...@vcs1-heavy.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-iclb3/igt@gem_ctx_swi...@vcs1-heavy.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +14 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) +4 similar
issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb8/igt@gem_exec_sched...@wide-bsd.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-apl: [PASS][16] -> [INCOMPLETE][17] ([fdo#103927])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-apl8/igt@gem_pp...@blt-vs-render-ctx0.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-apl2/igt@gem_pp...@blt-vs-render-ctx0.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-snb4/igt@gem_userptr_bl...@dmabuf-unsync.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-snb2/igt@gem_userptr_bl...@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870]) +1
similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14961/shard-hsw8/igt@gem_userptr_bl...@map-fixed-invalidate-bu
Re: [Intel-gfx] [PATCH 1/2] drm/i915/cml: Remove unsupport PCI ID
On Fri, 25 Oct 2019, Jani Nikula wrote:
>On Fri, 25 Oct 2019, Lee Shawn C wrote:
>> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
>> introduced new PCI ID that CML support. But some sku is not support
>> yet so remove them avoid unexpected issue.
>
>Please elaborate.
>
>BR,
>Jani.
>
So far, I did not meet real issue. Just find some sku were removed
from support list.
>
>>
>> Cc: Rodrigo Vivi
>> Cc: Jani Nikula
>> Cc: Lucas De Marchi
>> Cc: Anusha Srivatsa
>> Cc: Cooper Chiou
>> Signed-off-by: Lee Shawn C
>> ---
>> include/drm/i915_pciids.h | 4
>> 1 file changed, 4 deletions(-)
>>
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index a70c982ddff9..56e823cdc717 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -448,9 +448,7 @@
>> #define INTEL_CML_GT1_IDS(info) \
>> INTEL_VGA_DEVICE(0x9B21, info), \
>> INTEL_VGA_DEVICE(0x9BAA, info), \
>> -INTEL_VGA_DEVICE(0x9BAB, info), \
>> INTEL_VGA_DEVICE(0x9BAC, info), \
>> -INTEL_VGA_DEVICE(0x9BA0, info), \
>> INTEL_VGA_DEVICE(0x9BA5, info), \
>> INTEL_VGA_DEVICE(0x9BA8, info), \
>> INTEL_VGA_DEVICE(0x9BA4, info), \
>> @@ -460,9 +458,7 @@
>> #define INTEL_CML_GT2_IDS(info) \
>> INTEL_VGA_DEVICE(0x9B41, info), \
>> INTEL_VGA_DEVICE(0x9BCA, info), \
>> -INTEL_VGA_DEVICE(0x9BCB, info), \
>> INTEL_VGA_DEVICE(0x9BCC, info), \
>> -INTEL_VGA_DEVICE(0x9BC0, info), \
>> INTEL_VGA_DEVICE(0x9BC5, info), \
>> INTEL_VGA_DEVICE(0x9BC8, info), \
>> INTEL_VGA_DEVICE(0x9BC4, info), \
>
>--
>Jani Nikula, Intel Open Source Graphics Center
>
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: capture aux page table error register
TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
drivers/gpu/drm/i915/i915_gpu_error.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5cf4eed5add8..0c4d8a895feb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -741,6 +741,9 @@ static void __err_print_to_sgl(struct
drm_i915_error_state_buf *m,
if (IS_GEN_RANGE(m->i915, 8, 11))
err_printf(m, "GTT_CACHE_EN: 0x%08x\n", error->gtt_cache);
+ if (IS_TIGERLAKE(m->i915))
+ err_printf(m, "AUX_ERR_DBG: 0x%08x\n", error->aux_err_dbg);
+
for (ee = error->engine; ee; ee = ee->next)
error_print_engine(m, ee, error->epoch);
@@ -1563,6 +1566,11 @@ static void capture_reg_state(struct i915_gpu_state
*error)
if (IS_GEN_RANGE(i915, 8, 11))
error->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
+ if (IS_TIGERLAKE(i915)) {
+ error->aux_err_dbg = intel_uncore_read(uncore,
+ GEN12_AUX_ERR_DBG);
+ }
+
/* 4: Everything else */
if (INTEL_GEN(i915) >= 11) {
error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 7f1cd0b1fef7..e0c38b01ed18 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -75,6 +75,7 @@ struct i915_gpu_state {
u32 gab_ctl;
u32 gfx_mode;
u32 gtt_cache;
+ u32 aux_err_dbg; /* tigerlake */
u32 nfence;
u64 fence[I915_MAX_NUM_FENCES];
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 855db888516c..62b0b59bf02e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2602,6 +2602,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL(1 << 4)
+#define GEN12_AUX_ERR_DBG _MMIO(0x43f4)
+
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM (1 << 31)
--
2.24.0.rc0.303.g954a862665
___
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Re: [Intel-gfx] [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
On Thu, Oct 24, 2019 at 09:24:18PM +0300, Gwan-gyeong Mun wrote: > It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe > updates to make sure that we enable sending of VSC SDP and HDR Metadata > Infoframe SDP packet (when applicable) on fastsets. I think we first need to move the stuff into the crtc state and add real precompute+readout+state check. Then we could start thinking about optimizing things for fastsets. > In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP, > It adds intel_enable_infoframe() function to handle enabling/disabling of > each Video DIP. And it add intel_infoframe_enabled() function to get an > enabled state of a specific infoframe. > > Gwan-gyeong Mun (5): > drm/i915: Add whether or not to enable an each of Video DIP > drm/i915: Add checking a specific Video DIP is enabled or not > drm/i915/dp: Stop sending of VSC SDP when it is not needed > drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not > needed > drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe > updates > > drivers/gpu/drm/i915/display/intel_ddi.c | 2 + > .../drm/i915/display/intel_display_types.h| 4 ++ > drivers/gpu/drm/i915/display/intel_dp.c | 20 ++- > drivers/gpu/drm/i915/display/intel_hdmi.c | 56 +++ > drivers/gpu/drm/i915/display/intel_hdmi.h | 6 ++ > 5 files changed, 86 insertions(+), 2 deletions(-) > > -- > 2.23.0 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: capture aux page table error register
Quoting Lionel Landwerlin (2019-10-25 13:17:18) > TGL introduced a feature in which we map the main surface to the > auxilliary surface. If we screw up the page tables, the HW has a > register to tell us which engine encounters a fault in the page table > walk. Platform specific, or for likely all gen12 and then gen12+? > Signed-off-by: Lionel Landwerlin Acked-by: Chris Wilson I'm reminded of my desire to just grab a snapshot of all nearby mmio and zip it up. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/2] commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)' introduced new PCI ID that CML support. But some sku is not support yet so remove them.
v2: remove some inaccurate descriptions. Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Lucas De Marchi Cc: Anusha Srivatsa Cc: Cooper Chiou Signed-off-by: Lee Shawn C --- include/drm/i915_pciids.h | 4 1 file changed, 4 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index a70c982ddff9..56e823cdc717 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -448,9 +448,7 @@ #define INTEL_CML_GT1_IDS(info)\ INTEL_VGA_DEVICE(0x9B21, info), \ INTEL_VGA_DEVICE(0x9BAA, info), \ - INTEL_VGA_DEVICE(0x9BAB, info), \ INTEL_VGA_DEVICE(0x9BAC, info), \ - INTEL_VGA_DEVICE(0x9BA0, info), \ INTEL_VGA_DEVICE(0x9BA5, info), \ INTEL_VGA_DEVICE(0x9BA8, info), \ INTEL_VGA_DEVICE(0x9BA4, info), \ @@ -460,9 +458,7 @@ #define INTEL_CML_GT2_IDS(info)\ INTEL_VGA_DEVICE(0x9B41, info), \ INTEL_VGA_DEVICE(0x9BCA, info), \ - INTEL_VGA_DEVICE(0x9BCB, info), \ INTEL_VGA_DEVICE(0x9BCC, info), \ - INTEL_VGA_DEVICE(0x9BC0, info), \ INTEL_VGA_DEVICE(0x9BC5, info), \ INTEL_VGA_DEVICE(0x9BC8, info), \ INTEL_VGA_DEVICE(0x9BC4, info), \ -- 2.17.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/cml: Separate U sereis pci id from origianl list.
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
v2 : add missing comma in subplatform_ult_ids[].
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 2 ++
include/drm/i915_pciids.h| 20 +---
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bd9211b3d76e..e876621f6aaf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -863,6 +863,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
+ INTEL_CML_U_GT1_IDS(&intel_coffeelake_gt1_info),
+ INTEL_CML_U_GT2_IDS(&intel_coffeelake_gt2_info),
INTEL_CNL_IDS(&intel_cannonlake_info),
INTEL_ICL_11_IDS(&intel_icelake_11_info),
INTEL_EHL_IDS(&intel_elkhartlake_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..23c59e19832b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -775,6 +775,8 @@ static const u16 subplatform_ult_ids[] = {
INTEL_WHL_U_GT1_IDS(0),
INTEL_WHL_U_GT2_IDS(0),
INTEL_WHL_U_GT3_IDS(0),
+ INTEL_CML_U_GT1_IDS(0),
+ INTEL_CML_U_GT2_IDS(0),
};
static const u16 subplatform_ulx_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 56e823cdc717..02f10c4f5ec7 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -446,24 +446,28 @@
/* CML GT1 */
#define INTEL_CML_GT1_IDS(info)\
- INTEL_VGA_DEVICE(0x9B21, info), \
- INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAC, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
INTEL_VGA_DEVICE(0x9BA2, info)
+#define INTEL_CML_U_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B21, info), \
+ INTEL_VGA_DEVICE(0x9BAA, info), \
+ INTEL_VGA_DEVICE(0x9BAC, info)
+
/* CML GT2 */
#define INTEL_CML_GT2_IDS(info)\
- INTEL_VGA_DEVICE(0x9B41, info), \
- INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCC, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
INTEL_VGA_DEVICE(0x9BC2, info)
+#define INTEL_CML_U_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x9B41, info), \
+ INTEL_VGA_DEVICE(0x9BCA, info), \
+ INTEL_VGA_DEVICE(0x9BCC, info)
+
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -529,7 +533,9 @@
INTEL_WHL_U_GT3_IDS(info), \
INTEL_AML_CFL_GT2_IDS(info), \
INTEL_CML_GT1_IDS(info), \
- INTEL_CML_GT2_IDS(info)
+ INTEL_CML_GT2_IDS(info), \
+ INTEL_CML_U_GT1_IDS(info), \
+ INTEL_CML_U_GT2_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
--
2.17.1
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Re: [Intel-gfx] [PATCH] drm/i915: capture aux page table error register
On 25/10/2019 15:22, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-10-25 13:17:18) TGL introduced a feature in which we map the main surface to the auxilliary surface. If we screw up the page tables, the HW has a register to tell us which engine encounters a fault in the page table walk. Platform specific, or for likely all gen12 and then gen12+? It also applies to the new DGFX patches that started trickling down. Though I don't know where the Gen12 boundary is which is why I went with platform name. In Mesa we went for a flag on the device_info struct so it's easy to toggle on/off for a particular product. Signed-off-by: Lionel Landwerlin Acked-by: Chris Wilson I'm reminded of my desire to just grab a snapshot of all nearby mmio and zip it up. Yep... And jsonify it or something? ;) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/cml: Remove unsupport PCI ID
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them.
v2: remove some inaccurate descriptions.
v3: fix typo.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -448,9 +448,7 @@
#define INTEL_CML_GT1_IDS(info)\
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAB, info), \
INTEL_VGA_DEVICE(0x9BAC, info), \
- INTEL_VGA_DEVICE(0x9BA0, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
@@ -460,9 +458,7 @@
#define INTEL_CML_GT2_IDS(info)\
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCB, info), \
INTEL_VGA_DEVICE(0x9BCC, info), \
- INTEL_VGA_DEVICE(0x9BC0, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
--
2.17.1
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[Intel-gfx] [PATCH v4] drm/i915/cml: Remove unsupport PCI ID
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them.
v2: remove some inaccurate descriptions.
v3: fix typo.
v4: add missing version number.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index a70c982ddff9..56e823cdc717 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -448,9 +448,7 @@
#define INTEL_CML_GT1_IDS(info)\
INTEL_VGA_DEVICE(0x9B21, info), \
INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAB, info), \
INTEL_VGA_DEVICE(0x9BAC, info), \
- INTEL_VGA_DEVICE(0x9BA0, info), \
INTEL_VGA_DEVICE(0x9BA5, info), \
INTEL_VGA_DEVICE(0x9BA8, info), \
INTEL_VGA_DEVICE(0x9BA4, info), \
@@ -460,9 +458,7 @@
#define INTEL_CML_GT2_IDS(info)\
INTEL_VGA_DEVICE(0x9B41, info), \
INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCB, info), \
INTEL_VGA_DEVICE(0x9BCC, info), \
- INTEL_VGA_DEVICE(0x9BC0, info), \
INTEL_VGA_DEVICE(0x9BC5, info), \
INTEL_VGA_DEVICE(0x9BC8, info), \
INTEL_VGA_DEVICE(0x9BC4, info), \
--
2.17.1
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Re: [Intel-gfx] [PATCH i-g-t] benchmarks/gem_wsim: Cleanup register access on exit
On 25/10/2019 11:59, Chris Wilson wrote:
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 87f873b0e..337e13f91 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -3072,8 +3072,6 @@ static void init_clocks(void)
uint32_t rcs_start, rcs_end;
double overhead, t;
- intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
-
if (verbose <= 1)
return;
@@ -3114,6 +3112,7 @@ int main(int argc, char **argv)
struct w_arg *w_args = NULL;
unsigned int tolerance_pct = 1;
const struct workload_balancer *balancer = NULL;
+ int exitcode = EXIT_FAILURE;
char *endptr = NULL;
int prio = 0;
double t;
@@ -3128,6 +3127,8 @@ int main(int argc, char **argv)
fd = __drm_open_driver(DRIVER_INTEL);
igt_require(fd);
+ intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
+
init_clocks();
master_prng = time(NULL);
@@ -3138,7 +3139,7 @@ int main(int argc, char **argv)
case 'W':
if (master_workload >= 0) {
wsim_err("Only one master workload can be
given!\n");
- return 1;
+ goto err;
}
master_workload = nr_w_args;
/* Fall through */
@@ -3152,7 +3153,7 @@ int main(int argc, char **argv)
case 'a':
if (append_workload_arg) {
wsim_err("Only one append workload can be
given!\n");
- return 1;
+ goto err;
}
append_workload_arg = optarg;
break;
@@ -3217,7 +3218,7 @@ int main(int argc, char **argv)
if (!balancer) {
wsim_err("Unknown balancing mode '%s'!\n",
optarg);
- return 1;
+ goto err;
}
break;
case 'I':
@@ -3225,20 +3226,20 @@ int main(int argc, char **argv)
break;
case 'h':
print_help();
- return 0;
+ goto out;
default:
- return 1;
+ goto err;
}
}
if ((flags & HEARTBEAT) && !(flags & SEQNO)) {
wsim_err("Heartbeat needs a seqno based balancer!\n");
- return 1;
+ goto err;
}
if ((flags & VCS2REMAP) && (flags & I915)) {
wsim_err("VCS remapping not supported with i915 balancing!\n");
- return 1;
+ goto err;
}
if (!nop_calibration) {
@@ -3250,29 +3251,29 @@ int main(int argc, char **argv)
printf("Nop calibration for %uus delay is %lu.\n",
nop_calibration_us, nop_calibration);
- return 0;
+ goto out;
}
if (!nr_w_args) {
wsim_err("No workload descriptor(s)!\n");
- return 1;
+ goto err;
}
if (nr_w_args > 1 && clients > 1) {
wsim_err("Cloned clients cannot be combined with multiple
workloads!\n");
- return 1;
+ goto err;
}
if ((flags & GLOBAL_BALANCE) && !balancer) {
wsim_err("Balancer not specified in global balancing mode!\n");
- return 1;
+ goto err;
}
if (append_workload_arg) {
append_workload_arg =
load_workload_descriptor(append_workload_arg);
if (!append_workload_arg) {
wsim_err("Failed to load append workload
descriptor!\n");
- return 1;
+ goto err;
}
}
@@ -3281,7 +3282,7 @@ int main(int argc, char **argv)
app_w = parse_workload(&arg, flags, NULL);
if (!app_w) {
wsim_err("Failed to parse append workload!\n");
- return 1;
+ goto err;
}
}
@@ -3293,13 +3294,13 @@ int main(int argc, char **argv)
if (!w_args[i].desc) {
wsim_err("Failed to load workload descriptor %u!\n", i);
- return 1;
+ goto err;
}
wrk[i] = parse_workload(&w_args[i], flags, app_w);
if (!
Re: [Intel-gfx] [PATCH] drm/i915: Move intel_engine_context_in/out into intel_lrc.c
On 25/10/2019 10:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-25 10:09:52)
From: Tvrtko Ursulin
Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.
How much pain would you feel if we did intel_lrc.c +
intel_execlists_submission.c earlier rather than later?
Par for course as you like to say. :)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 55 --
drivers/gpu/drm/i915/gt/intel_lrc.c| 55 ++
2 files changed, 55 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 97bbdd9773c9..c6895938b626 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -290,61 +290,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
struct drm_printer *m,
const char *header, ...);
-static inline void intel_engine_context_in(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (READ_ONCE(engine->stats.enabled) == 0)
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
-
- if (engine->stats.enabled > 0) {
- if (engine->stats.active++ == 0)
- engine->stats.start = ktime_get();
- GEM_BUG_ON(engine->stats.active == 0);
- }
-
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
-static inline void intel_engine_context_out(struct intel_engine_cs *engine)
-{
- unsigned long flags;
-
- if (READ_ONCE(engine->stats.enabled) == 0)
- return;
-
- write_seqlock_irqsave(&engine->stats.lock, flags);
-
- if (engine->stats.enabled > 0) {
- ktime_t last;
-
- if (engine->stats.active && --engine->stats.active == 0) {
- /*
-* Decrement the active context count and in case GPU
-* is now idle add up to the running total.
-*/
- last = ktime_sub(ktime_get(), engine->stats.start);
-
- engine->stats.total = ktime_add(engine->stats.total,
- last);
- } else if (engine->stats.active == 0) {
- /*
-* After turning on engine stats, context out might be
-* the first event in which case we account from the
-* time stats gathering was turned on.
-*/
- last = ktime_sub(ktime_get(), engine->stats.enabled_at);
-
- engine->stats.total = ktime_add(engine->stats.total,
- last);
- }
- }
-
- write_sequnlock_irqrestore(&engine->stats.lock, flags);
-}
-
int intel_enable_engine_stats(struct intel_engine_cs *engine);
void intel_disable_engine_stats(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 73eae85a2cc9..523de1fd4452 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -944,6 +944,61 @@ execlists_context_status_change(struct i915_request *rq,
unsigned long status)
status, rq);
}
+static void intel_engine_context_in(struct intel_engine_cs *engine)
stats_in() / stats_out() ?
Now that's it entirely local and we may end up doing other per-context
in/out ops?
Yeah, could make sense. I did rename it to intel_context_in/out in a
local patch which adds per ce stats. Lets see when I un-bit-rot that
work how it will look.
Purely mechanical, so
Reviewed-by: Chris Wilson
In the meantime I have pushed this so at least header file is smaller.
Thanks.
Regards,
Tvrtko
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Convert PAT setup to uncore mmio
== Series Details ==
Series: drm/i915: Convert PAT setup to uncore mmio
URL : https://patchwork.freedesktop.org/series/68503/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7169_full -> Patchwork_14962_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14962_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14962_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_14962_full:
### IGT changes ###
Possible regressions
* igt@gem_exec_parallel@fds:
- shard-kbl: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-kbl6/igt@gem_exec_paral...@fds.html
Warnings
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
- shard-iclb: [SKIP][2] ([fdo#111325]) -> [FAIL][3]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb4/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb6/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide-bsd2:
- {shard-tglb}: [PASS][4] -> [FAIL][5] +1 similar issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-tglb7/igt@gem_exec_sched...@wide-bsd2.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-tglb7/igt@gem_exec_sched...@wide-bsd2.html
* igt@perf_pmu@enable-race-vecs0:
- {shard-tglb}: [PASS][6] -> [INCOMPLETE][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-tglb1/igt@perf_...@enable-race-vecs0.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-tglb3/igt@perf_...@enable-race-vecs0.html
Known issues
Here are the changes found in Patchwork_14962_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([fdo#108566]) +5
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html
* igt@gem_ctx_isolation@vcs1-dirty-switch:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109276] / [fdo#112080])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb1/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb3/igt@gem_ctx_isolat...@vcs1-dirty-switch.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#111325]) +7 similar
issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb5/igt@gem_exec_as...@concurrent-writes-bsd.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb4/igt@gem_exec_as...@concurrent-writes-bsd.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#110854])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb4/igt@gem_exec_balan...@smoke.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb5/igt@gem_exec_balan...@smoke.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#112080]) +13 similar
issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb4/igt@gem_exec_paral...@vcs1-fds.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb5/igt@gem_exec_paral...@vcs1-fds.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109276]) +19 similar
issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-iclb2/igt@gem_exec_sched...@preempt-queue-bsd1.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-iclb7/igt@gem_exec_sched...@preempt-queue-bsd1.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-hsw: [PASS][20] -> [DMESG-WARN][21] ([fdo#111870]) +1
similar issue
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7169/shard-hsw6/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14962/shard-hsw1/igt@gem_userptr_bl...@map-fixed-invalidate-busy-gup.html
- shard-snb: [PASS][22] -> [DMESG-WARN][23] (
[Intel-gfx] [PATCH v2 2/5] drm/i915: Add checking a specific Video DIP is enabled or not
Because DP ports don't use intel_hdmi_infoframes_enabled() machanism,
DP ports requires a way to check a specific infoframe (aka. Video DIP )
is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 21 +
drivers/gpu/drm/i915/display/intel_hdmi.h | 3 +++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b62afeccd44e..6a3dff9b5ef9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -621,6 +621,27 @@ void intel_enable_infoframe(struct intel_encoder *encoder,
}
}
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ u32 val = 0;
+
+ val = dig_port->infoframes_enabled(encoder, crtc_state);
+
+ if (HAS_DDI(dev_priv)) {
+ if (val & hsw_infoframe_enable(type))
+ return true;
+ } else {
+ if (val & g4x_infoframe_enable(type))
+ return true;
+ }
+
+ return false;
+}
+
u32 intel_hdmi_infoframe_enable(unsigned int type)
{
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 86f925526514..96d50f591b69 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -51,5 +51,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
const struct intel_crtc_state *crtc_state,
unsigned int type);
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+const struct intel_crtc_state *crtc_state,
+unsigned int type);
#endif /* __INTEL_HDMI_H__ */
--
2.23.0
___
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[Intel-gfx] [PATCH v2 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe updates to make sure that we enable sending of VSC SDP and HDR Metadata Infoframe SDP packet (when applicable) on fastsets. In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP, It adds intel_enable_infoframe() function to handle enabling/disabling of each Video DIP. And it add intel_infoframe_enabled() function to get an enabled state of a specific infoframe. v2: Minor style fix Gwan-gyeong Mun (5): drm/i915: Add whether or not to enable an each of Video DIP drm/i915: Add checking a specific Video DIP is enabled or not drm/i915/dp: Stop sending of VSC SDP when it is not needed drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates drivers/gpu/drm/i915/display/intel_ddi.c | 2 + .../drm/i915/display/intel_display_types.h| 4 ++ drivers/gpu/drm/i915/display/intel_dp.c | 21 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 57 +++ drivers/gpu/drm/i915/display/intel_hdmi.h | 6 ++ 5 files changed, 88 insertions(+), 2 deletions(-) -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/5] drm/i915: Add whether or not to enable an each of Video DIP
Because DP ports don't use set_infoframes() / intel_write_infoframe()
machanisms, DP ports requires a handling of enabling/disabling of each
Video DIP when a changing usage of video DIP for SDP transmission such as
whether or not to use HDR.
For now it only adds enable_infoframe() callback for hsw platform.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
---
.../drm/i915/display/intel_display_types.h| 4 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 36 +++
drivers/gpu/drm/i915/display/intel_hdmi.h | 3 ++
3 files changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index bac40482a2aa..a541c8cc8d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1305,6 +1305,10 @@ struct intel_digital_port {
const struct intel_crtc_state *crtc_state,
unsigned int type,
void *frame, ssize_t len);
+ void (*enable_infoframe)(struct intel_encoder *encoder,
+bool enable,
+const struct intel_crtc_state *crtc_state,
+unsigned int type);
void (*set_infoframes)(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..b62afeccd44e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -559,6 +559,24 @@ static void hsw_read_infoframe(struct intel_encoder
*encoder,
type, i >> 2));
}
+static void hsw_enable_infoframe(struct intel_encoder *encoder,
+bool enable,
+const struct intel_crtc_state *crtc_state,
+unsigned int type)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+ u32 val = I915_READ(ctl_reg);
+
+ if (enable)
+ val |= hsw_infoframe_enable(type);
+ else
+ val &= ~hsw_infoframe_enable(type);
+
+ I915_WRITE(ctl_reg, val);
+ POSTING_READ(ctl_reg);
+}
+
static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
@@ -586,6 +604,23 @@ static const u8 infoframe_type_to_idx[] = {
HDMI_INFOFRAME_TYPE_DRM,
};
+void intel_enable_infoframe(struct intel_encoder *encoder,
+ bool enable,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ if (dig_port->enable_infoframe) {
+ dig_port->enable_infoframe(encoder, enable, crtc_state, type);
+ } else {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not
implemented!",
+ INTEL_GEN(dev_priv));
+ }
+}
+
u32 intel_hdmi_infoframe_enable(unsigned int type)
{
int i;
@@ -3104,6 +3139,7 @@ void intel_infoframe_init(struct intel_digital_port
*intel_dig_port)
} else {
intel_dig_port->write_infoframe = hsw_write_infoframe;
intel_dig_port->read_infoframe = hsw_read_infoframe;
+ intel_dig_port->enable_infoframe = hsw_enable_infoframe;
intel_dig_port->set_infoframes = hsw_set_infoframes;
intel_dig_port->infoframes_enabled =
hsw_infoframes_enabled;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index cf1ea5427639..86f925526514 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -48,5 +48,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
enum hdmi_infoframe_type type,
union hdmi_infoframe *frame);
+void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
+ const struct intel_crtc_state *crtc_state,
+ unsigned int type);
#endif /* __INTEL_HDMI_H__ */
--
2.23.0
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[Intel-gfx] [PATCH v2 3/5] drm/i915/dp: Stop sending of VSC SDP when it is not needed
It prevents sending VSC SDP Packet to a receiver when VSC SDP is not
needed. Because VSC SDP is used for PSR, YCbCr 420, HDR BT.2020 and etc,
it checks PSR is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 521ce23f38ac..ed6845485b41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4735,8 +4735,16 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+ if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ struct intel_digital_port *intel_dig_port =
dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+
+ if (!intel_psr_enabled(intel_dp) &&
+ intel_infoframe_enabled(encoder, crtc_state, DP_SDP_VSC))
+ intel_enable_infoframe(encoder, false, crtc_state,
DP_SDP_VSC);
+
return;
+ }
intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
}
--
2.23.0
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[Intel-gfx] [PATCH v2 4/5] drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
It prevents sending HDR Metadata Infoframe SDP packet to a receiver when
HDR Metadata Infoframe SDP is not needed.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ed6845485b41..5d17819d3a19 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4753,8 +4753,17 @@ void intel_dp_hdr_metadata_enable(struct intel_dp
*intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
- if (!conn_state->hdr_output_metadata)
+ if (!conn_state->hdr_output_metadata) {
+ struct intel_digital_port *intel_dig_port =
dp_to_dig_port(intel_dp);
+ struct intel_encoder *encoder = &intel_dig_port->base;
+
+ if (intel_infoframe_enabled(encoder, crtc_state,
+ HDMI_PACKET_TYPE_GAMUT_METADATA))
+ intel_enable_infoframe(encoder, false, crtc_state,
+ HDMI_PACKET_TYPE_GAMUT_METADATA);
+
return;
+ }
intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
crtc_state,
--
2.23.0
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[Intel-gfx] [PATCH v2 5/5] drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
Call intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe updates to make sure that we enable sending of VSC SDP and HDR Metadata Infoframe SDP packet (when applicable) on fastsets. These functions check pipe state and when the features does not need, they disable the features. Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1a49266f4f57..e07591ff2a6e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4020,6 +4020,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, intel_ddi_set_dp_msa(crtc_state, conn_state); intel_psr_update(intel_dp, crtc_state); + intel_dp_vsc_enable(intel_dp, crtc_state, conn_state); + intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state); intel_edp_drrs_enable(intel_dp, crtc_state); intel_panel_update_backlight(encoder, crtc_state, conn_state); -- 2.23.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] CI: Test revert some of the documentation fixes
This reverts commit 900554dc6bfc996ad07b9e187bbfd3864cd5bed0 to make
sure that Fi.CI.DOCS complains :-)
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 2a104c64291d..104cf6d42333 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -337,11 +337,6 @@ struct intel_shared_dpll {
* @info: platform specific info
*/
const struct dpll_info *info;
-
- /**
-* @wakeref: In some platforms a device-level runtime pm reference may
-* need to be grabbed to disable DC states while this DPLL is enabled
-*/
intel_wakeref_t wakeref;
};
--
2.21.0
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[Intel-gfx] [PATCH 1/2] drm/i915: Encapsulate kconfig constant values inside boolean predicates
Avoid angering clang and smatch by using a constant value in a '&&' test,
by forcing that constant value into a boolean.
E.g.,
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of
logical '&&' with constant operand [-Wconstant-logical-operand]
if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) {
^ ~~~
Reported-by: kbuild test robot
Signed-off-by: Chris Wilson
Cc: Nathan Chancellor
Cc: Nick Desaulniers
Cc: Jani Nikula
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 3 ++-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 ++--
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_utils.h| 13 +
5 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 55f1f93c0925..414fc55c9dd0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -325,7 +325,8 @@ static bool __cancel_engine(struct intel_engine_cs *engine)
* kill the banned context, we fallback to doing a local reset
* instead.
*/
- if (CONFIG_DRM_I915_PREEMPT_TIMEOUT && !intel_engine_pulse(engine))
+ if (IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT) &&
+ !intel_engine_pulse(engine))
return true;
/* If we are unable to send a pulse, try resetting this engine. */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index fd4122d8c0a9..e3002849844b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -312,7 +312,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
list_add(&obj->userfault_link, &i915->ggtt.userfault_list);
mutex_unlock(&i915->ggtt.vm.mutex);
- if (CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND)
+ if (IS_ACTIVE(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND))
intel_wakeref_auto(&i915->ggtt.userfault_wakeref,
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
index 9977f59f6b53..5051f304705b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c
@@ -133,7 +133,7 @@ static void heartbeat(struct work_struct *wrk)
void intel_engine_unpark_heartbeat(struct intel_engine_cs *engine)
{
- if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL)
+ if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL))
return;
next_heartbeat(engine);
@@ -156,7 +156,7 @@ int intel_engine_set_heartbeat(struct intel_engine_cs
*engine,
int err;
/* Send one last pulse before to cleanup persistent hogs */
- if (!delay && CONFIG_DRM_I915_PREEMPT_TIMEOUT) {
+ if (!delay && IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT)) {
err = intel_engine_pulse(engine);
if (err)
return err;
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 932c5cf190b5..19a1d447ab8d 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1447,7 +1447,7 @@ long i915_request_wait(struct i915_request *rq,
* completion. That requires having a good predictor for the request
* duration, which we currently lack.
*/
- if (CONFIG_DRM_I915_SPIN_REQUEST &&
+ if (IS_ACTIVE(CONFIG_DRM_I915_SPIN_REQUEST) &&
__i915_spin_request(rq, state, CONFIG_DRM_I915_SPIN_REQUEST)) {
dma_fence_signal(&rq->fence);
goto out;
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 94f136d8a5fd..da205a4bdfdc 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -430,4 +430,17 @@ static inline bool timer_expired(const struct timer_list
*t)
return READ_ONCE(t->expires) && !timer_pending(t);
}
+/*
+ * This is a lookalike for IS_ENABLED() that takes a kconfig value,
+ * e.g. CONFIG_DRM_I915_SPIN_REQUEST, and evaluates whether it is non-zero
+ * i.e. active. Wrapping up the config inside a boolean context prevents
+ * clang and smatch from complaining about potential issues in confusing
+ * logical-&& with bitwise-& for constants.
+ *
+ * Sadly IS_ENABLED() itself does not work with kconfig values.
+ *
+ * Returns 0 if config is 0, 1 if set to any value.
+ */
+#define IS_ACTIVE(config) ((config) != 0)
+
#endif /* !__I915_UTILS_H */
--
2.24.0.rc0
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[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Initialise err in case there are no engines!
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:255 live_heartbeat_fast() error: uninitialized symbol 'err'. drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:320 live_heartbeat_off() error: uninitialized symbol 'err'. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 768f032e6578..155c508024df 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -240,7 +240,7 @@ static int live_heartbeat_fast(void *arg) struct intel_gt *gt = arg; struct intel_engine_cs *engine; enum intel_engine_id id; - int err; + int err = 0; /* Check that the heartbeat ticks at the desired rate. */ if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) @@ -302,7 +302,7 @@ static int live_heartbeat_off(void *arg) struct intel_gt *gt = arg; struct intel_engine_cs *engine; enum intel_engine_id id; - int err; + int err = 0; /* Check that we can turn off heartbeat and not interrupt VIP */ if (!CONFIG_DRM_I915_HEARTBEAT_INTERVAL) -- 2.24.0.rc0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] CI: Test revert some of the documentation fixes
Hi Arek,
can you please:
1. use the format:
commit 900554dc6bfc ("drm/i915: Describe structure member in
documentation")
when referring to a commit that has been applied.
chekcpatch.pl should have complained.
2. Sign off the commit
3. because this is a fix, please add the tag.
Fixes: 900554dc6bfc ("drm/i915: Describe structure member in
documentation")
4. use the drm/i915/display prefix at the title line because this
patch is only implicitly related to CI.
Unless whoever is going to push the patch will take care of this.
On Fri, Oct 25, 2019 at 04:18:26PM +0300, Arkadiusz Hiler wrote:
> This reverts commit 900554dc6bfc996ad07b9e187bbfd3864cd5bed0 to make
> sure that Fi.CI.DOCS complains :-)
we don't like people that smile in here! be serious or use only the
sad face to be more in line! :-(
Andi
PS :-P
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor Gen11+ SAGV support (rev4)
== Series Details == Series: Refactor Gen11+ SAGV support (rev4) URL : https://patchwork.freedesktop.org/series/68028/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h AR drivers/gpu/drm/i915/built-in.a CC [M] drivers/gpu/drm/i915/display/intel_atomic.o drivers/gpu/drm/i915/display/intel_atomic.c:488:5: error: redefinition of ‘intel_atomic_serialize_global_state’ int intel_atomic_serialize_global_state(struct intel_atomic_state *state) ^~~ drivers/gpu/drm/i915/display/intel_atomic.c:210:5: note: previous definition of ‘intel_atomic_serialize_global_state’ was here int intel_atomic_serialize_global_state(struct intel_atomic_state *state) ^~~ scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/display/intel_atomic.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_atomic.o] Error 1 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1649: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 0/5] Per client engine busyness (all aboard the sysfs train!)
From: Tvrtko Ursulin It was quite some time since I last posted this RFC, but recently there has been some new interest, this time from OpenCL and related customers, so I decided to give it a quick respin and test the waters. This time round it has been really hastily rebased since the upstream changed quite a lot and I have very little confidence it is technically correct. But it is enough to illustrate a point of what this feature could provide: In short it enables a "top-like" display for GPU tasks. Or with a screenshot: intel-gpu-top - 948/ 999 MHz;0% RC6; 3.65 Watts; 2165 irqs/s IMC reads: 5015 MiB/s IMC writes: 143 MiB/s ENGINE BUSY MI_SEMA MI_WAIT Render/3D/0 56.60% |███▋ | 0% 0% Blitter/0 95.65% |██▊ | 0% 0% Video/0 40.92% | | 0% 0% VideoEnhance/00.00% | | 0% 0% PIDNAME RCS BCS VCS VECS 5347gem_wsim |███▍||███▏||██▌ || | 4929Xorg |▎ |||||| | 5305glxgears ||||||| | 5303glxgears ||||||| | 5024 xfwm4 ||||||| | 4929Xorg ||||||| | Implementation wise we would get a a bunch of per-drm-client-per-engine-class files in sysfs like: # cd /sys/class/drm/card0/clients/ # tree . ├── 7 │ ├── busy │ │ ├── 0 │ │ ├── 1 │ │ ├── 2 │ │ └── 3 │ ├── name │ └── pid ├── 8 │ ├── busy │ │ ├── 0 │ │ ├── 1 │ │ ├── 2 │ │ └── 3 │ ├── name │ └── pid ├── 9 │ ├── busy │ │ ├── 0 │ │ ├── 1 │ │ ├── 2 │ │ └── 3 │ ├── name │ └── pid └── enable_stats I will post the corresponding patch to intel_gpu_top for reference as well. Tvrtko Ursulin (5): drm/i915: Track per-context engine busyness drm/i915: Expose list of clients in sysfs drm/i915: Update client name on context create drm/i915: Expose per-engine client busyness drm/i915: Add sysfs toggle to enable per-client engine stats drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 +- drivers/gpu/drm/i915/gt/intel_context.c | 20 ++ drivers/gpu/drm/i915/gt/intel_context.h | 9 + drivers/gpu/drm/i915/gt/intel_context_types.h | 9 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 66 +- drivers/gpu/drm/i915/i915_drv.h | 38 +++ drivers/gpu/drm/i915/i915_gem.c | 218 +- drivers/gpu/drm/i915/i915_sysfs.c | 81 +++ 9 files changed, 451 insertions(+), 23 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC 2/5] drm/i915: Expose list of clients in sysfs
From: Tvrtko Ursulin
Expose a list of clients with open file handles in sysfs.
This will be a basis for a top-like utility showing per-client and per-
engine GPU load.
Currently we only expose each client's pid and name under opaque numbered
directories in /sys/class/drm/card0/clients/.
For instance:
/sys/class/drm/card0/clients/3/name: Xorg
/sys/class/drm/card0/clients/3/pid: 5664
v2:
Chris Wilson:
* Enclose new members into dedicated structs.
* Protect against failed sysfs registration.
v3:
* sysfs_attr_init.
v4:
* Fix for internal clients.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 19 +
drivers/gpu/drm/i915/i915_gem.c | 124 --
drivers/gpu/drm/i915/i915_sysfs.c | 8 ++
3 files changed, 143 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 16e58a74fa6f..4dc8cadf56eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -222,6 +222,20 @@ struct drm_i915_file_private {
/** ban_score: Accumulated score of all ctx bans and fast hangs. */
atomic_t ban_score;
unsigned long hang_timestamp;
+
+ struct i915_drm_client {
+ unsigned int id;
+
+ pid_t pid;
+ char *name;
+
+ struct kobject *root;
+
+ struct {
+ struct device_attribute pid;
+ struct device_attribute name;
+ } attr;
+ } client;
};
/* Interface history:
@@ -1372,6 +1386,11 @@ struct drm_i915_private {
struct i915_pmu pmu;
+ struct i915_drm_clients {
+ struct kobject *root;
+ atomic_t serial;
+ } clients;
+
struct i915_hdcp_comp_master *hdcp_master;
bool hdcp_comp_added;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 319e96d833fa..d8d352efb9ef 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1492,6 +1492,99 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
return 0;
}
+static ssize_t
+show_client_name(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_file_private *file_priv =
+ container_of(attr, struct drm_i915_file_private,
+client.attr.name);
+
+ return snprintf(buf, PAGE_SIZE, "%s", file_priv->client.name);
+}
+
+static ssize_t
+show_client_pid(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ struct drm_i915_file_private *file_priv =
+ container_of(attr, struct drm_i915_file_private,
+client.attr.pid);
+
+ return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
+}
+
+static int
+i915_gem_add_client(struct drm_i915_private *i915,
+ struct drm_i915_file_private *file_priv,
+ struct task_struct *task,
+ unsigned int serial)
+{
+ int ret = -ENOMEM;
+ struct device_attribute *attr;
+ char id[32];
+
+ if (!i915->clients.root)
+ return 0; /* intel_fbdev_init registers a client before sysfs */
+
+ file_priv->client.name = kstrdup(task->comm, GFP_KERNEL);
+ if (!file_priv->client.name)
+ goto err_name;
+
+ snprintf(id, sizeof(id), "%u", serial);
+ file_priv->client.root = kobject_create_and_add(id,
+ i915->clients.root);
+ if (!file_priv->client.root)
+ goto err_client;
+
+ attr = &file_priv->client.attr.name;
+ sysfs_attr_init(&attr->attr);
+ attr->attr.name = "name";
+ attr->attr.mode = 0444;
+ attr->show = show_client_name;
+
+ ret = sysfs_create_file(file_priv->client.root,
+ (struct attribute *)attr);
+ if (ret)
+ goto err_attr_name;
+
+ attr = &file_priv->client.attr.pid;
+ sysfs_attr_init(&attr->attr);
+ attr->attr.name = "pid";
+ attr->attr.mode = 0444;
+ attr->show = show_client_pid;
+
+ ret = sysfs_create_file(file_priv->client.root,
+ (struct attribute *)attr);
+ if (ret)
+ goto err_attr_pid;
+
+ file_priv->client.pid = pid_nr(get_task_pid(task, PIDTYPE_PID));
+
+ return 0;
+
+err_attr_pid:
+ sysfs_remove_file(file_priv->client.root,
+ (struct attribute *)&file_priv->client.attr.name);
+err_attr_name:
+ kobject_put(file_priv->client.root);
+err_client:
+ kfree(file_priv->client.name);
+err_name:
+ return ret;
+}
+
+static void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
+{
+ if (!file_priv->client.name)
+ return; /* intel_fbdev_init registers a client before sysfs */
+
+ sysfs_remove_file(file_priv->client.root,
+
[Intel-gfx] [RFC 3/5] drm/i915: Update client name on context create
From: Tvrtko Ursulin
Some clients have the DRM fd passed to them over a socket by the X server.
Grab the real client and pid when they create their first context and
update the exposed data for more useful enumeration.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 ++---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
3 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 55f1f93c0925..c7f6684eb366 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2084,6 +2084,8 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
{
struct drm_i915_private *i915 = to_i915(dev);
struct drm_i915_gem_context_create_ext *args = data;
+ pid_t pid = pid_nr(get_task_pid(current, PIDTYPE_PID));
+ struct drm_i915_file_private *file_priv = file->driver_priv;
struct create_ext ext_data;
int ret;
@@ -2097,14 +2099,23 @@ int i915_gem_context_create_ioctl(struct drm_device
*dev, void *data,
if (ret)
return ret;
- ext_data.fpriv = file->driver_priv;
+ ext_data.fpriv = file_priv;
if (client_is_banned(ext_data.fpriv)) {
DRM_DEBUG("client %s[%d] banned from creating ctx\n",
- current->comm,
- pid_nr(get_task_pid(current, PIDTYPE_PID)));
+ current->comm, pid);
return -EIO;
}
+ mutex_lock(&dev->struct_mutex);
+ if (file_priv->client.pid != pid) {
+ i915_gem_remove_client(file_priv);
+ ret = i915_gem_add_client(i915, file_priv, current,
+ file_priv->client.id);
+ }
+ mutex_unlock(&dev->struct_mutex);
+ if (ret)
+ return ret;
+
ext_data.ctx = i915_gem_create_context(i915, args->flags);
if (IS_ERR(ext_data.ctx))
return PTR_ERR(ext_data.ctx);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4dc8cadf56eb..b8f7b0637224 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1983,6 +1983,13 @@ void i915_gem_suspend_late(struct drm_i915_private
*dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
+int
+i915_gem_add_client(struct drm_i915_private *i915,
+ struct drm_i915_file_private *file_priv,
+ struct task_struct *task,
+ unsigned int serial);
+void i915_gem_remove_client(struct drm_i915_file_private *file_priv);
+
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d8d352efb9ef..54a00c954066 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1512,7 +1512,7 @@ show_client_pid(struct device *kdev, struct
device_attribute *attr, char *buf)
return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
}
-static int
+int
i915_gem_add_client(struct drm_i915_private *i915,
struct drm_i915_file_private *file_priv,
struct task_struct *task,
@@ -1572,7 +1572,7 @@ i915_gem_add_client(struct drm_i915_private *i915,
return ret;
}
-static void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
+void i915_gem_remove_client(struct drm_i915_file_private *file_priv)
{
if (!file_priv->client.name)
return; /* intel_fbdev_init registers a client before sysfs */
--
2.20.1
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[Intel-gfx] [RFC 4/5] drm/i915: Expose per-engine client busyness
From: Tvrtko Ursulin
Expose per-client and per-engine busyness under the previously added sysfs
client root.
The new files are one per-engine instance and located under the 'busy'
directory. Each contains a monotonically increasing nano-second resolution
times each client's jobs were executing on the GPU.
This enables userspace to create a top-like tool for GPU utilization:
==
intel-gpu-top - 935/ 935 MHz;0% RC6; 14.73 Watts; 1097 irqs/s
IMC reads: 1401 MiB/s
IMC writes:4 MiB/s
ENGINE BUSY MI_SEMA MI_WAIT
Render/3D/0 63.73% |███ | 3% 0%
Blitter/09.53% |██▊ | 6% 0%
Video/0 39.32% |███▊ | 16% 0%
Video/1 15.62% |▋ | 0% 0%
VideoEnhance/00.00% | | 0% 0%
PIDNAME RCS BCS VCS VECS
4084gem_wsim |█▌ ||█ || || |
4086gem_wsim |█▌ || ||███|| |
==
v2: Use intel_context_engine_get_busy_time.
v3: New directory structure.
v4: Rebase.
v5: sysfs_attr_init.
v6: Small tidy in i915_gem_add_client.
v7: Rebase to be engine class based.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++
drivers/gpu/drm/i915/i915_gem.c | 102 ++--
2 files changed, 106 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b8f7b0637224..45f0e2455322 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -186,6 +186,12 @@ struct drm_i915_private;
struct i915_mm_struct;
struct i915_mmu_object;
+struct i915_engine_busy_attribute {
+ struct device_attribute attr;
+ struct drm_i915_file_private *file_priv;
+ unsigned int engine_class;
+};
+
struct drm_i915_file_private {
struct drm_i915_private *dev_priv;
@@ -230,10 +236,12 @@ struct drm_i915_file_private {
char *name;
struct kobject *root;
+ struct kobject *busy_root;
struct {
struct device_attribute pid;
struct device_attribute name;
+ struct i915_engine_busy_attribute
busy[MAX_ENGINE_CLASS];
} attr;
} client;
};
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 54a00c954066..b3d21b6b570c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1512,15 +1512,67 @@ show_client_pid(struct device *kdev, struct
device_attribute *attr, char *buf)
return snprintf(buf, PAGE_SIZE, "%u", file_priv->client.pid);
}
+struct busy_ctx {
+ unsigned int engine_class;
+ u64 total;
+};
+
+static int busy_add(int id, void *p, void *data)
+{
+ struct busy_ctx *bc = data;
+ struct i915_gem_context *ctx = p;
+ unsigned int engine_class = bc->engine_class;
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+ uint64_t total = bc->total;
+
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ if (ce->engine->uabi_class == engine_class)
+ total += ktime_to_ns(intel_context_get_busy_time(ce));
+ }
+ i915_gem_context_unlock_engines(ctx);
+
+ bc->total = total;
+
+ return 0;
+}
+
+static ssize_t
+show_client_busy(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ struct i915_engine_busy_attribute *i915_attr =
+ container_of(attr, typeof(*i915_attr), attr);
+ struct drm_i915_file_private *file_priv = i915_attr->file_priv;
+ struct busy_ctx bc = { .engine_class = i915_attr->engine_class };
+ int ret;
+
+ ret = mutex_lock_interruptible(&file_priv->context_idr_lock);
+ if (ret)
+ return ret;
+
+ idr_for_each(&file_priv->context_idr, busy_add, &bc);
+
+ mutex_unlock(&file_priv->context_idr_lock);
+
+ return snprintf(buf, PAGE_SIZE, "%llu\n", bc.total);
+}
+
+static const char *uabi_class_names[] = {
+ [I915_ENGINE_CLASS_RENDER] = "0",
+ [I915_ENGINE_CLASS_COPY] = "1",
+ [I915_ENGINE_CLASS_VIDEO] = "2",
+ [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "3",
+};
+
int
i915_gem_add_client(struct drm_i915_private *i915,
struct drm_i915_file_private *file_priv,
struct task_struct *task,
unsigned int serial)
{
- int ret = -ENOMEM;
+ int i, ret = -ENOMEM;
struct device_attribute *attr;
- char id[32];
+ char idstr[32
[Intel-gfx] [RFC 1/5] drm/i915: Track per-context engine busyness
From: Tvrtko Ursulin
Some customers want to know how much of the GPU time are their clients
using in order to make dynamic load balancing decisions.
With the hooks already in place which track the overall engine busyness,
we can extend that slightly to split that time between contexts.
v2: Fix accounting for tail updates.
v3: Rebase.
v4: Mark currently running contexts as active on stats enable.
v5: Include some headers to fix the build.
v6: Added fine grained lock.
v7: Convert to seqlock. (Chris Wilson)
v8: Rebase and tidy with helpers.
v9: Rebase.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 20 ++
drivers/gpu/drm/i915/gt/intel_context.h | 9 +++
drivers/gpu/drm/i915/gt/intel_context_types.h | 9 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 16 -
drivers/gpu/drm/i915/gt/intel_lrc.c | 66 ---
5 files changed, 108 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index ee9d2bcd2c13..3d68720df512 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -248,6 +248,7 @@ intel_context_init(struct intel_context *ce,
INIT_LIST_HEAD(&ce->signals);
mutex_init(&ce->pin_mutex);
+ seqlock_init(&ce->stats.lock);
i915_active_init(&ce->active,
__intel_context_active, __intel_context_retire);
@@ -348,6 +349,25 @@ struct i915_request *intel_context_create_request(struct
intel_context *ce)
return rq;
}
+ktime_t intel_context_get_busy_time(struct intel_context *ce)
+{
+ unsigned int seq;
+ ktime_t total;
+
+ do {
+ seq = read_seqbegin(&ce->stats.lock);
+
+ total = ce->stats.total;
+
+ if (ce->stats.active)
+ total = ktime_add(total,
+ ktime_sub(ktime_get(),
+ ce->stats.start));
+ } while (read_seqretry(&ce->stats.lock, seq));
+
+ return total;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_context.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 68b3d317d959..c7ab8efa3573 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -153,4 +153,13 @@ static inline struct intel_ring
*__intel_context_ring_size(u64 sz)
return u64_to_ptr(struct intel_ring, sz);
}
+static inline void
+__intel_context_stats_start(struct intel_context_stats *stats, ktime_t now)
+{
+ stats->start = now;
+ stats->active = true;
+}
+
+ktime_t intel_context_get_busy_time(struct intel_context *ce);
+
#endif /* __INTEL_CONTEXT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 6959b05ae5f8..b3384e01d033 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include "i915_active_types.h"
#include "i915_utils.h"
@@ -75,6 +76,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+
+ /** stats: Context GPU engine busyness tracking. */
+ struct intel_context_stats {
+ seqlock_t lock;
+ bool active;
+ ktime_t start;
+ ktime_t total;
+ } stats;
};
#endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9cc1ea6519ec..6792ec01f3f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1568,8 +1568,20 @@ int intel_enable_engine_stats(struct intel_engine_cs
*engine)
engine->stats.enabled_at = ktime_get();
- /* XXX submission method oblivious? */
- for (port = execlists->active; (rq = *port); port++)
+ /*
+* Mark currently running context as active.
+* XXX submission method oblivious?
+*/
+
+ rq = NULL;
+ port = execlists->active;
+ if (port)
+ rq = *port;
+ if (rq)
+ __intel_context_stats_start(&rq->hw_context->stats,
+ engine->stats.enabled_at);
+
+ for (; (rq = *port); port++)
engine->stats.active++;
for (port = execlists->pending; (rq = *port); port++) {
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 523de1fd4452..2305d7a7ac68 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -944,26 +944,60
[Intel-gfx] [RFC 5/5] drm/i915: Add sysfs toggle to enable per-client engine stats
From: Tvrtko Ursulin
By default we are not collecting any per-engine and per-context
statistcs.
Add a new sysfs toggle to enable this facility:
$ echo 1 >/sys/class/drm/card0/clients/enable_stats
v2: Rebase.
v3: sysfs_attr_init.
v4: Scheduler caps.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_sysfs.c | 73 +++
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 45f0e2455322..3d2459e9fff4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1397,6 +1397,10 @@ struct drm_i915_private {
struct i915_drm_clients {
struct kobject *root;
atomic_t serial;
+ struct {
+ bool enabled;
+ struct device_attribute attr;
+ } stats;
} clients;
struct i915_hdcp_comp_master *hdcp_master;
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index a9f27f4fc245..b061baf5da49 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -569,9 +569,67 @@ static void i915_setup_error_capture(struct device *kdev)
{}
static void i915_teardown_error_capture(struct device *kdev) {}
#endif
+static ssize_t
+show_client_stats(struct device *kdev, struct device_attribute *attr, char
*buf)
+{
+ struct drm_i915_private *i915 =
+ container_of(attr, struct drm_i915_private, clients.stats.attr);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", i915->clients.stats.enabled);
+}
+
+static ssize_t
+store_client_stats(struct device *kdev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *i915 =
+ container_of(attr, struct drm_i915_private, clients.stats.attr);
+ bool disable = false;
+ bool enable = false;
+ bool val = false;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int ret;
+
+/* Use RCS as proxy for all engines. */
+ if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS))
+ return -EINVAL;
+
+ ret = kstrtobool(buf, &val);
+ if (ret)
+ return ret;
+
+ ret = i915_mutex_lock_interruptible(&i915->drm);
+ if (ret)
+ return ret;
+
+ if (val && !i915->clients.stats.enabled)
+ enable = true;
+ else if (!val && i915->clients.stats.enabled)
+ disable = true;
+
+ if (!enable && !disable)
+ goto out;
+
+ for_each_engine(engine, i915, id) {
+ if (enable)
+ WARN_ON_ONCE(intel_enable_engine_stats(engine));
+ else if (disable)
+ intel_disable_engine_stats(engine);
+ }
+
+ i915->clients.stats.enabled = val;
+
+out:
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return count;
+}
+
void i915_setup_sysfs(struct drm_i915_private *dev_priv)
{
struct device *kdev = dev_priv->drm.primary->kdev;
+ struct device_attribute *attr;
int ret;
dev_priv->clients.root =
@@ -579,6 +637,18 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
if (!dev_priv->clients.root)
DRM_ERROR("Per-client sysfs setup failed\n");
+ attr = &dev_priv->clients.stats.attr;
+ sysfs_attr_init(&attr->attr);
+ attr->attr.name = "enable_stats";
+ attr->attr.mode = 0664;
+ attr->show = show_client_stats;
+ attr->store = store_client_stats;
+
+ ret = sysfs_create_file(dev_priv->clients.root,
+ (struct attribute *)attr);
+ if (ret)
+ DRM_ERROR("Per-client sysfs setup failed! (%d)\n", ret);
+
#ifdef CONFIG_PM
if (HAS_RC6(dev_priv)) {
ret = sysfs_merge_group(&kdev->kobj,
@@ -640,6 +710,9 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
#endif
+ sysfs_remove_file(dev_priv->clients.root,
+ (struct attribute *)&dev_priv->clients.stats.attr);
+
if (dev_priv->clients.root)
kobject_put(dev_priv->clients.root);
}
--
2.20.1
___
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[Intel-gfx] [RFC i-g-t 0/1] Per client engine busyness
From: Tvrtko Ursulin intel_gpu_top counterpart for the equally named i915 series. For reference only at this stage. Tvrtko Ursulin (1): intel-gpu-top: Support for client stats tools/intel_gpu_top.c | 590 +- 1 file changed, 584 insertions(+), 6 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC i-g-t 1/1] intel-gpu-top: Support for client stats
From: Tvrtko Ursulin
Adds support for per-client engine busyness stats i915 exports in sysfs
and produces output like the below:
==
intel-gpu-top - 935/ 935 MHz;0% RC6; 14.73 Watts; 1097 irqs/s
IMC reads: 1401 MiB/s
IMC writes:4 MiB/s
ENGINE BUSY MI_SEMA MI_WAIT
Render/3D/0 63.73% |███ | 3% 0%
Blitter/09.53% |██▊ | 6% 0%
Video/0 39.32% |███▊ | 16% 0%
Video/1 15.62% |▋ | 0% 0%
VideoEnhance/00.00% | | 0% 0%
PIDNAME RCS BCS VCS VECS
4084gem_wsim |█▌ ||█ || || |
4086gem_wsim |█▌ || ||███|| |
==
Apart from the existing physical engine utilization it now also shows
utilization per client and per engine class.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 590 +-
1 file changed, 584 insertions(+), 6 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c539ed..50e9c153329a 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -659,8 +659,403 @@ static void pmu_sample(struct engines *engines)
}
}
+enum client_status {
+ FREE = 0, /* mbz */
+ ALIVE,
+ PROBE
+};
+
+struct clients;
+
+struct client {
+ struct clients *clients;
+
+ enum client_status status;
+ unsigned int id;
+ unsigned int pid;
+ char name[128];
+ unsigned int samples;
+ unsigned long total;
+ struct engines *engines;
+ unsigned long *val;
+ uint64_t *last;
+};
+
+struct engine_class {
+ unsigned int class;
+ const char *name;
+ unsigned int num_engines;
+};
+
+struct clients {
+ unsigned int num_classes;
+ struct engine_class *class;
+
+ unsigned int num_clients;
+ struct client *client;
+};
+
+#define for_each_client(clients, c, tmp) \
+ for ((tmp) = (clients)->num_clients, c = (clients)->client; \
+(tmp > 0); (tmp)--, (c)++)
+
+#define SYSFS_ENABLE "/sys/class/drm/card0/clients/enable_stats"
+
+bool __stats_enabled;
+
+static int __set_stats(bool val)
+{
+ int fd, ret;
+
+ fd = open(SYSFS_ENABLE, O_WRONLY);
+ if (fd < 0)
+ return -errno;
+
+ ret = write(fd, val ? "1" : "0", 2);
+ if (ret < 0)
+ return -errno;
+ else if (ret < 2)
+ return 1;
+
+ close(fd);
+
+ return 0;
+}
+
+static void __restore_stats(void)
+{
+ int ret;
+
+ if (__stats_enabled)
+ return;
+
+ ret = __set_stats(false);
+ if (ret)
+ fprintf(stderr, "Failed to disable per-client stats! (%d)\n",
+ ret);
+}
+
+static void __restore_stats_signal(int sig)
+{
+ exit(0);
+}
+
+static int enable_stats(void)
+{
+ int fd, ret;
+
+ fd = open(SYSFS_ENABLE, O_RDONLY);
+ if (fd < 0)
+ return -errno;
+
+ close(fd);
+
+ __stats_enabled = filename_to_u64(SYSFS_ENABLE, 10);
+ if (__stats_enabled)
+ return 0;
+
+ ret = __set_stats(true);
+ if (!ret) {
+ if (atexit(__restore_stats))
+ fprintf(stderr, "Failed to register exit handler!");
+
+ if (signal(SIGINT, __restore_stats_signal))
+ fprintf(stderr, "Failed to register signal handler!");
+ } else {
+ fprintf(stderr, "Failed to enable per-client stats! (%d)\n",
+ ret);
+ }
+
+ return ret;
+}
+
+static struct clients *init_clients(void)
+{
+ struct clients *clients = malloc(sizeof(*clients));
+
+ if (enable_stats()) {
+ free(clients);
+ return NULL;
+ }
+
+ return memset(clients, 0, sizeof(*clients));
+}
+
+#define SYSFS_CLIENTS "/sys/class/drm/card0/clients"
+
+static uint64_t read_client_busy(unsigned int id, unsigned int class)
+{
+ char buf[256];
+ ssize_t ret;
+
+ ret = snprintf(buf, sizeof(buf),
+ SYSFS_CLIENTS "/%u/busy/%u",
+ id, class);
+ assert(ret > 0 && ret < sizeof(buf));
+ if (ret <= 0 || ret == sizeof(buf))
+ return 0;
+
+ return filename_to_u64(buf, 10);
+}
+
+static struct client *
+find_client(struct clients *clients, enum client_status status, unsigned int
id)
+{
+ struct client *c;
+ int tmp;
+
+ for_each_client(clients, c, tmp) {
+ if ((status == FREE && c->status ==
[Intel-gfx] [PATCH i-g-t] lib/i915: Use explicit iterator names in for_each_engine()
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:653:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, other) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:652:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../tests/i915/gem_exec_schedule.c: In function ‘measure_semaphore_power’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1740:3: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1719:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, signaler) {
^~~~
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
benchmarks/gem_syslatency.c | 16 +--
lib/i915/gem_ring.c | 4 +-
lib/igt_gt.h| 24 +++--
tests/amdgpu/amd_prime.c| 6 +-
tests/i915/gem_bad_reloc.c | 4 +-
tests/i915/gem_busy.c | 4 +-
tests/i915/gem_concurrent_all.c | 7 +-
tests/i915/gem_cs_prefetch.c| 2 +-
tests/i915/gem_ctx_create.c | 12 +--
tests/i915/gem_ctx_shared.c | 43
tests/i915/gem_ctx_switch.c | 2 +-
tests/i915/gem_ctx_thrash.c | 14 ++-
tests/i915/gem_eio.c| 29 +++---
tests/i915/gem_exec_async.c | 13 ++-
tests/i915/gem_exec_await.c | 7 +-
tests/i915/gem_exec_capture.c | 6 +-
tests/i915/gem_exec_create.c| 8 +-
tests/i915/gem_exec_fence.c | 61 ++-
tests/i915/gem_exec_flush.c | 2 +-
tests/i915/gem_exec_gttfill.c | 11 +-
tests/i915/gem_exec_latency.c | 33 +++---
tests/i915/gem_exec_nop.c | 44
tests/i915/gem_exec_params.c| 14 +--
tests/i915/gem_exec_reloc.c | 8 +-
tests/i915/gem_exec_reuse.c | 6 +-
tests/i915/gem_exec_schedule.c | 172 +++-
tests/i915/gem_exec_suspend.c | 20 ++--
tests/i915/gem_exec_whisper.c | 8 +-
tests/i915/gem_mocs_settings.c | 6 +-
tests/i915/gem_reset_stats.c| 10 +-
tests/i915/gem_ring_sync_loop.c | 5 +-
tests/i915/gem_ringfill.c | 3 +-
tests/i915/gem_shrink.c | 5 +-
tests/i915/gem_spin_batch.c | 2 +-
tests/i915/gem_storedw_loop.c | 2 +-
tests/i915/gem_sync.c | 97 +-
tests/i915/gem_userptr_blits.c | 7 +-
tests/i915/i915_module_load.c | 12 +--
tests/kms_busy.c| 30 +++---
tests/prime_busy.c | 8 +-
tests/prime_vgem.c | 16 +--
41 files changed, 363 insertions(+), 420 deletions(-)
diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d7cf0ed49..402306300 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -79,17 +79,6 @@ static void force_low_latency(void)
#define ENGINE_FLAGS (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
-static bool ignore_engine(int fd, unsigned engine)
-{
- if (engine == 0)
- return true;
-
- if (gem_has_bsd2(fd) && engine == I915_EXEC_BSD)
- return true;
-
- return false;
-}
-
static void *gem_busyspin(void *arg)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -100,14 +89,13 @@ static void *gem_busyspin(void *arg)
bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
unsigned engines[16];
unsigned nengine;
- unsigned engine;
int fd;
fd = drm_open_driver(DRIVER_INTEL);
nengine = 0;
- for_each_engine(fd, engine)
- if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
+ for_each_physical_engine(e, fd)
+ engines[nengine++] = eb_ring(e);
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(fd, 4096);
diff --git a/lib/i915/gem_ring.c b/lib/i915/gem_ring.c
index 5ca2a728b..99f4741cb
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/7] drm/i915: support creating LMEM objects (rev2)
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects
(rev2)
URL : https://patchwork.freedesktop.org/series/68502/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3c03a1e2a25 drm/i915: support creating LMEM objects
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#36:
new file mode 100644
-:71: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#71: FILE: drivers/gpu/drm/i915/gem/i915_gem_lmem.c:31:
+ struct drm_i915_gem_object *$
total: 0 errors, 2 warnings, 0 checks, 206 lines checked
ca9ba1aa485f drm/i915: setup io-mapping for LMEM
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 34 lines checked
10f04b34b04a drm/i915/lmem: support kernel mapping
-:201: WARNING:LINE_SPACING: Missing a blank line after declarations
#201: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:284:
+ struct drm_i915_gem_object *obj;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 271 lines checked
401720633e05 drm/i915/selftests: add write-dword test for LMEM
-:84: WARNING:LINE_SPACING: Missing a blank line after declarations
#84: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:313:
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
-:164: WARNING:LINE_SPACING: Missing a blank line after declarations
#164: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:407:
+ struct drm_file *file;
+ I915_RND_STATE(prng);
total: 0 errors, 2 warnings, 0 checks, 193 lines checked
586f7e7fc336 drm/i915/selftests: extend coverage to include LMEM huge-pages
48ce2647381c drm/i915/selftests: prefer random sizes for the huge-GTT-page
smoke tests
-:82: WARNING:NEW_TYPEDEFS: do not add new typedefs
#82: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1319:
+typedef struct drm_i915_gem_object *
total: 0 errors, 1 warnings, 0 checks, 292 lines checked
bc315feae100 drm/i915/selftests: add sanity selftest for huge-GTT-pages
-:54: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#54: FILE: drivers/gpu/drm/i915/gem/selftests/huge_pages.c:1476:
+^I^I{ SZ_64K, ^I SZ_64K, },$
total: 0 errors, 1 warnings, 0 checks, 117 lines checked
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915: support creating LMEM objects (rev2)
== Series Details == Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects (rev2) URL : https://patchwork.freedesktop.org/series/68502/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915: support creating LMEM objects Okay! Commit: drm/i915: setup io-mapping for LMEM Okay! Commit: drm/i915/lmem: support kernel mapping +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:177:42: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:expected void * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51:got void [noderef] * +drivers/gpu/drm/i915/gem/i915_gem_pages.c:254:51: warning: incorrect type in return expression (different address spaces) +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:expected void [noderef] *vaddr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42:got void *[assigned] ptr +drivers/gpu/drm/i915/gem/i915_gem_pages.c:337:42: warning: incorrect type in argument 1 (different address spaces) Commit: drm/i915/selftests: add write-dword test for LMEM - +drivers/gpu/drm/i915/selftests/intel_memory_region.c:309:49: error: incompatible types in conditional expression (different address spaces) Commit: drm/i915/selftests: extend coverage to include LMEM huge-pages Okay! Commit: drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests Okay! Commit: drm/i915/selftests: add sanity selftest for huge-GTT-pages Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC 2/5] drm/i915: Expose list of clients in sysfs
Quoting Tvrtko Ursulin (2019-10-25 15:21:28)
> int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
> {
> + int ret = -ENOMEM;
> struct drm_i915_file_private *file_priv;
> - int ret;
>
> DRM_DEBUG("\n");
>
> file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
> if (!file_priv)
> - return -ENOMEM;
> + goto err_alloc;
> +
> + file_priv->client.id = atomic_inc_return(&i915->clients.serial);
We should make this a cyclic ida to avoid reuse on wraparound. 32b
wraps will happen, and they will still have client 0 alive! :)
That will mean we need a lock.
(Of course you could use -EEXIST from add_client and keep incrementing
serial until you find a hole :)
-Chris
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Re: [Intel-gfx] [RFC 3/5] drm/i915: Update client name on context create
Quoting Tvrtko Ursulin (2019-10-25 15:21:29)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 55f1f93c0925..c7f6684eb366 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -2084,6 +2084,8 @@ int i915_gem_context_create_ioctl(struct drm_device
> *dev, void *data,
> {
> struct drm_i915_private *i915 = to_i915(dev);
> struct drm_i915_gem_context_create_ext *args = data;
> + pid_t pid = pid_nr(get_task_pid(current, PIDTYPE_PID));
> + struct drm_i915_file_private *file_priv = file->driver_priv;
> struct create_ext ext_data;
> int ret;
>
> @@ -2097,14 +2099,23 @@ int i915_gem_context_create_ioctl(struct drm_device
> *dev, void *data,
> if (ret)
> return ret;
>
> - ext_data.fpriv = file->driver_priv;
> + ext_data.fpriv = file_priv;
> if (client_is_banned(ext_data.fpriv)) {
> DRM_DEBUG("client %s[%d] banned from creating ctx\n",
> - current->comm,
> - pid_nr(get_task_pid(current, PIDTYPE_PID)));
> + current->comm, pid);
> return -EIO;
> }
>
> + mutex_lock(&dev->struct_mutex);
> + if (file_priv->client.pid != pid) {
> + i915_gem_remove_client(file_priv);
> + ret = i915_gem_add_client(i915, file_priv, current,
> + file_priv->client.id);
> + }
> + mutex_unlock(&dev->struct_mutex);
You are serialising against multiple context_create_ioctl from the same
file, right? Could abuse fpriv->context_idr_lock. Or add a new one.
> + if (ret)
> + return ret;
> +
Hmm, is get_task_pid() the one that returns a reference to the pid_t?
Aye, it is, we need a put_pid().
-Chris
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Re: [Intel-gfx] [RFC 4/5] drm/i915: Expose per-engine client busyness
Quoting Tvrtko Ursulin (2019-10-25 15:21:30)
> +static int busy_add(int id, void *p, void *data)
> +{
> + struct busy_ctx *bc = data;
> + struct i915_gem_context *ctx = p;
> + unsigned int engine_class = bc->engine_class;
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> + uint64_t total = bc->total;
> +
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + if (ce->engine->uabi_class == engine_class)
> + total += ktime_to_ns(intel_context_get_busy_time(ce));
> + }
> + i915_gem_context_unlock_engines(ctx);
> +
> + bc->total = total;
> +
> + return 0;
> +}
> +
> +static ssize_t
> +show_client_busy(struct device *kdev, struct device_attribute *attr, char
> *buf)
> +{
> + struct i915_engine_busy_attribute *i915_attr =
> + container_of(attr, typeof(*i915_attr), attr);
> + struct drm_i915_file_private *file_priv = i915_attr->file_priv;
> + struct busy_ctx bc = { .engine_class = i915_attr->engine_class };
> + int ret;
> +
> + ret = mutex_lock_interruptible(&file_priv->context_idr_lock);
> + if (ret)
> + return ret;
> +
> + idr_for_each(&file_priv->context_idr, busy_add, &bc);
If you don a hard hat, this can all be done under rcu_read_lock().
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915: support creating LMEM objects (rev2)
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects
(rev2)
URL : https://patchwork.freedesktop.org/series/68502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14980
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/index.html
New tests
-
New tests have been introduced between CI_DRM_7186 and Patchwork_14980:
### New IGT tests (1) ###
* igt@i915_selftest@live_memory_region:
- Statuses : 41 pass(s)
- Exec time: [0.35, 1.40] s
Known issues
Here are the changes found in Patchwork_14980 that come from known issues:
### IGT changes ###
Issues hit
* igt@prime_vgem@basic-fence-read:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_v...@basic-fence-read.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/fi-icl-u3/igt@prime_v...@basic-fence-read.html
Possible fixes
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-byt-n2820: [DMESG-FAIL][3] -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][5] ([fdo#111407]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 43)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7186 -> Patchwork_14980
CI-20190529: 20190529
CI_DRM_7186: ce03ec86789ef8fc41a56176e5f2a9251182183c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5241: 17b87c378fa155390b13a43f141371fd899d567b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14980: bc315feae100b98a71815c25eddecea46cc447ca @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc315feae100 drm/i915/selftests: add sanity selftest for huge-GTT-pages
48ce2647381c drm/i915/selftests: prefer random sizes for the huge-GTT-page
smoke tests
586f7e7fc336 drm/i915/selftests: extend coverage to include LMEM huge-pages
401720633e05 drm/i915/selftests: add write-dword test for LMEM
10f04b34b04a drm/i915/lmem: support kernel mapping
ca9ba1aa485f drm/i915: setup io-mapping for LMEM
b3c03a1e2a25 drm/i915: support creating LMEM objects
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14980/index.html
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Re: [Intel-gfx] [RFC 5/5] drm/i915: Add sysfs toggle to enable per-client engine stats
Quoting Tvrtko Ursulin (2019-10-25 15:21:31)
> + ret = i915_mutex_lock_interruptible(&i915->drm);
> + if (ret)
> + return ret;
> +
> + if (val && !i915->clients.stats.enabled)
> + enable = true;
> + else if (!val && i915->clients.stats.enabled)
> + disable = true;
The struct_mutex is just for atomically enabling/disabling stats, right?
Only one user may toggle status at a time.
I'd wrap it a i915->spinlock just so the locking is clear from the
outset.
> + if (!enable && !disable)
> + goto out;
> +
> + for_each_engine(engine, i915, id) {
A quick s/for_each_engine/for_each_uabi_engine/
> + if (enable)
> + WARN_ON_ONCE(intel_enable_engine_stats(engine));
> + else if (disable)
> + intel_disable_engine_stats(engine);
> + }
> +
> + i915->clients.stats.enabled = val;
Now as for whether we want a toggle approach, or only while the file is
open (and refcount)?
-Chris
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Re: [Intel-gfx] [igt-dev] [RFC i-g-t 1/1] intel-gpu-top: Support for client stats
Quoting Tvrtko Ursulin (2019-10-25 15:24:10) > From: Tvrtko Ursulin > > Adds support for per-client engine busyness stats i915 exports in sysfs > and produces output like the below: > > == > intel-gpu-top - 935/ 935 MHz;0% RC6; 14.73 Watts; 1097 irqs/s Could we get "gpu / pkg Watts" pretty please? Are irq/s interesting with execlists? Originally the idea was to say how many times clients were sleeping and being woken up. Now we interrupt to wipe the gpu's nose when it sneezes. > > IMC reads: 1401 MiB/s > IMC writes:4 MiB/s > > ENGINE BUSY MI_SEMA MI_WAIT > Render/3D/0 63.73% |███ | 3% 0% >Blitter/09.53% |██▊ | 6% 0% > Video/0 39.32% |███▊ | 16% 0% > Video/1 15.62% |▋ | 0% 0% > VideoEnhance/00.00% | | 0% 0% > > PIDNAME RCS BCS VCS VECS > 4084gem_wsim |█▌ ||█ || || | > 4086gem_wsim |█▌ || ||███|| | > == > > Apart from the existing physical engine utilization it now also shows > utilization per client and per engine class. > > Signed-off-by: Tvrtko Ursulin > --- > +#define SYSFS_CLIENTS "/sys/class/drm/card0/clients" We need to somehow pull the right card. Nothing shocking here. Where's the intel-gpu-overlay integration? ;) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/dsb: Remove PIN_MAPPABLE from the DSB object VMA
On 10/17/2019 9:28 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global GTT
and not in the mappable region.
Currently tested and working without any regression, waiting for
confirmation from h/w team, will update soon.
Regards,
Animesh
Signed-off-by: Tvrtko Ursulin
Cc: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bb5a0e91b370..d8ad5fe1efef 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -119,7 +119,7 @@ intel_dsb_get(struct intel_crtc *crtc)
goto err;
}
- vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
if (IS_ERR(vma)) {
DRM_ERROR("Vma creation failed\n");
i915_gem_object_put(obj);
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[Intel-gfx] [PATCH i-g-t] lib/i915: Use explicit iterator names in for_each_engine()
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:653:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, other) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:652:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../tests/i915/gem_exec_schedule.c: In function ‘measure_semaphore_power’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1740:3: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1719:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, signaler) {
^~~~
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
benchmarks/gem_syslatency.c | 16 +--
lib/i915/gem_ring.c | 4 +-
lib/igt_gt.h| 24 +++--
tests/amdgpu/amd_prime.c| 6 +-
tests/i915/gem_bad_reloc.c | 4 +-
tests/i915/gem_busy.c | 4 +-
tests/i915/gem_concurrent_all.c | 7 +-
tests/i915/gem_cs_prefetch.c| 2 +-
tests/i915/gem_ctx_create.c | 12 +--
tests/i915/gem_ctx_shared.c | 43
tests/i915/gem_ctx_switch.c | 2 +-
tests/i915/gem_ctx_thrash.c | 14 ++-
tests/i915/gem_eio.c| 29 +++---
tests/i915/gem_exec_async.c | 13 ++-
tests/i915/gem_exec_await.c | 7 +-
tests/i915/gem_exec_capture.c | 6 +-
tests/i915/gem_exec_create.c| 8 +-
tests/i915/gem_exec_fence.c | 61 ++-
tests/i915/gem_exec_flush.c | 2 +-
tests/i915/gem_exec_gttfill.c | 11 +-
tests/i915/gem_exec_latency.c | 33 +++---
tests/i915/gem_exec_nop.c | 44
tests/i915/gem_exec_params.c| 14 +--
tests/i915/gem_exec_reloc.c | 8 +-
tests/i915/gem_exec_reuse.c | 6 +-
tests/i915/gem_exec_schedule.c | 172 +++-
tests/i915/gem_exec_suspend.c | 20 ++--
tests/i915/gem_exec_whisper.c | 8 +-
tests/i915/gem_mocs_settings.c | 6 +-
tests/i915/gem_reset_stats.c| 10 +-
tests/i915/gem_ring_sync_loop.c | 5 +-
tests/i915/gem_ringfill.c | 3 +-
tests/i915/gem_shrink.c | 5 +-
tests/i915/gem_spin_batch.c | 2 +-
tests/i915/gem_storedw_loop.c | 2 +-
tests/i915/gem_sync.c | 99 +-
tests/i915/gem_userptr_blits.c | 7 +-
tests/i915/i915_module_load.c | 16 +--
tests/kms_busy.c| 30 +++---
tests/prime_busy.c | 8 +-
tests/prime_vgem.c | 16 +--
41 files changed, 366 insertions(+), 423 deletions(-)
diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d7cf0ed49..402306300 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -79,17 +79,6 @@ static void force_low_latency(void)
#define ENGINE_FLAGS (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
-static bool ignore_engine(int fd, unsigned engine)
-{
- if (engine == 0)
- return true;
-
- if (gem_has_bsd2(fd) && engine == I915_EXEC_BSD)
- return true;
-
- return false;
-}
-
static void *gem_busyspin(void *arg)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -100,14 +89,13 @@ static void *gem_busyspin(void *arg)
bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
unsigned engines[16];
unsigned nengine;
- unsigned engine;
int fd;
fd = drm_open_driver(DRIVER_INTEL);
nengine = 0;
- for_each_engine(fd, engine)
- if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
+ for_each_physical_engine(e, fd)
+ engines[nengine++] = eb_ring(e);
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(fd, 4096);
diff --git a/lib/i915/gem_ring.c b/lib/i915/gem_ring.c
index 5ca2a728b..99f4741cb
[Intel-gfx] [CI 1/7] drm/i915: support creating LMEM objects
From: Matthew Auld
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 57 +++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 29 ++
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/intel_region_lmem.c | 16 ++
drivers/gpu/drm/i915/intel_region_lmem.h | 11
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/intel_memory_region.c | 40 +
8 files changed, 159 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_lmem.h
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.c
create mode 100644 drivers/gpu/drm/i915/intel_region_lmem.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9bf1c0b20370..2f64db45f8e0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -120,6 +120,7 @@ gem-y += \
gem/i915_gem_internal.o \
gem/i915_gem_object.o \
gem/i915_gem_object_blt.o \
+ gem/i915_gem_lmem.o \
gem/i915_gem_mman.o \
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
@@ -148,6 +149,7 @@ i915-y += \
i915_scheduler.o \
i915_trace_points.o \
i915_vma.o \
+ intel_region_lmem.o \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
new file mode 100644
index ..6a38d8028110
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_memory_region.h"
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
+#include "i915_drv.h"
+
+const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .get_pages = i915_gem_object_get_pages_buddy,
+ .put_pages = i915_gem_object_put_pages_buddy,
+ .release = i915_gem_object_release_memory_region,
+};
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ return obj->ops == &i915_gem_lmem_obj_ops;
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags)
+{
+ return
i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
+size, flags);
+}
+
+struct drm_i915_gem_object *
+__i915_gem_lmem_object_create(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags)
+{
+ static struct lock_class_key lock_class;
+ struct drm_i915_private *i915 = mem->i915;
+ struct drm_i915_gem_object *obj;
+
+ if (size > BIT(mem->mm.max_order) * mem->mm.chunk_size)
+ return ERR_PTR(-E2BIG);
+
+ obj = i915_gem_object_alloc();
+ if (!obj)
+ return ERR_PTR(-ENOMEM);
+
+ drm_gem_private_object_init(&i915->drm, &obj->base, size);
+ i915_gem_object_init(obj, &i915_gem_lmem_obj_ops, &lock_class);
+
+ obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
+
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
+
+ i915_gem_object_init_memory_region(obj, mem, flags);
+
+ return obj;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
new file mode 100644
index ..fc3f15580fe3
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __I915_GEM_LMEM_H
+#define __I915_GEM_LMEM_H
+
+#include
+
+struct drm_i915_private;
+struct drm_i915_gem_object;
+struct intel_memory_region;
+
+extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+
+bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
+struct drm_i915_gem_object *
+i915_gem_object_create_lmem(struct drm_i915_private *i915,
+ resource_size_t size,
+ unsigned int flags);
+
+struct drm_i915_gem_object *
+__i915_gem_lmem_object_create(struct intel_memory_region *mem,
+ resource_size_t size,
+ unsigned int flags);
+
+#endif /* !__I915_GEM_LMEM_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 16e58a74fa6f..dc33f096200e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_dr
[Intel-gfx] [CI 5/7] drm/i915/selftests: extend coverage to include LMEM huge-pages
From: Matthew Auld
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 123 +-
1 file changed, 122 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index dac8344507c1..fa134a82083d 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -9,6 +9,7 @@
#include "i915_selftest.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
@@ -983,7 +984,8 @@ static int gpu_write(struct intel_context *ce,
vma->size >> PAGE_SHIFT, val);
}
-static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+static int
+__cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val)
{
unsigned int needs_flush;
unsigned long n;
@@ -1015,6 +1017,51 @@ static int cpu_check(struct drm_i915_gem_object *obj,
u32 dword, u32 val)
return err;
}
+static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32
val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ if (i915_gem_object_has_struct_page(obj))
+ return __cpu_check_shmem(obj, dword, val);
+ else if (i915_gem_object_is_lmem(obj))
+ return __cpu_check_lmem(obj, dword, val);
+
+ return -ENODEV;
+}
+
static int __igt_write_huge(struct intel_context *ce,
struct drm_i915_gem_object *obj,
u64 size, u64 offset,
@@ -1399,6 +1446,79 @@ static int igt_ppgtt_gemfs_huge(void *arg)
return err;
}
+static int igt_ppgtt_lmem_huge(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ struct drm_i915_gem_object *obj;
+ static const unsigned int sizes[] = {
+ SZ_64K,
+ SZ_512K,
+ SZ_1M,
+ SZ_2M,
+ };
+ int i;
+ int err;
+
+ if (!HAS_LMEM(i915)) {
+ pr_info("device lacks LMEM support, skipping\n");
+ return 0;
+ }
+
+ /*
+* Sanity check that the HW uses huge pages correctly through LMEM
+* -- ensure that our writes land in the right place.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
+ unsigned int size = sizes[i];
+
+ obj = i915_gem_object_create_lmem(i915, size,
+ I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -E2BIG) {
+ pr_info("object too big for region!\n");
+ return 0;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ goto out_put;
+
+ if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
+ pr_info("LMEM unable to allocate huge-page(s) with
size=%u\n",
+ size);
+ goto out_unpin;
+ }
+
+ err = igt_write_huge(ctx, obj);
+ if (err) {
+ pr_err("LMEM write-huge failed with size=%u\n", size);
+ goto out_unpin;
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+ }
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_u
[Intel-gfx] [CI 7/7] drm/i915/selftests: add sanity selftest for huge-GTT-pages
From: Matthew Auld
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely. Also
rather than do this for every backend, just limit to our two memory
types: system and local.
Suggested-by: Chris Wilson
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 99 +++
1 file changed, 99 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index b777999655b0..688c49a24f32 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1342,6 +1342,12 @@ igt_create_internal(struct drm_i915_private *i915, u32
size, u32 flags)
return i915_gem_object_create_internal(i915, size);
}
+static struct drm_i915_gem_object *
+igt_create_system(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return huge_pages_object(i915, size, size);
+}
+
static struct drm_i915_gem_object *
igt_create_local(struct drm_i915_private *i915, u32 size, u32 flags)
{
@@ -1452,6 +1458,98 @@ static int igt_ppgtt_smoke_huge(void *arg)
return err;
}
+static int igt_ppgtt_sanity_check(void *arg)
+{
+ struct i915_gem_context *ctx = arg;
+ struct drm_i915_private *i915 = ctx->i915;
+ unsigned int supported = INTEL_INFO(i915)->page_sizes;
+ struct {
+ igt_create_fn fn;
+ unsigned int flags;
+ } backends[] = {
+ { igt_create_system, 0,},
+ { igt_create_local, I915_BO_ALLOC_CONTIGUOUS, },
+ };
+ struct {
+ u32 size;
+ u32 pages;
+ } combos[] = {
+ { SZ_64K, SZ_64K },
+ { SZ_2M,SZ_2M },
+ { SZ_2M,SZ_64K },
+ { SZ_2M - SZ_64K, SZ_64K },
+ { SZ_2M - SZ_4K,SZ_64K | SZ_4K },
+ { SZ_2M + SZ_4K,SZ_64K | SZ_4K },
+ { SZ_2M + SZ_4K,SZ_2M | SZ_4K },
+ { SZ_2M + SZ_64K, SZ_2M | SZ_64K },
+ };
+ int i, j;
+ int err;
+
+ if (supported == I915_GTT_PAGE_SIZE_4K)
+ return 0;
+
+ /*
+* Sanity check that the HW behaves with a limited set of combinations.
+* We already have a bunch of randomised testing, which should give us
+* a decent amount of variation between runs, however we should keep
+* this to limit the chances of introducing a temporary regression, by
+* testing the most obvious cases that might make something blow up.
+*/
+
+ for (i = 0; i < ARRAY_SIZE(backends); ++i) {
+ for (j = 0; j < ARRAY_SIZE(combos); ++j) {
+ struct drm_i915_gem_object *obj;
+ u32 size = combos[j].size;
+ u32 pages = combos[j].pages;
+
+ obj = backends[i].fn(i915, size, backends[i].flags);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ if (err == -ENODEV) {
+ pr_info("Device lacks local memory,
skipping\n");
+ err = 0;
+ break;
+ }
+
+ return err;
+ }
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ i915_gem_object_put(obj);
+ goto out;
+ }
+
+ GEM_BUG_ON(pages > obj->base.size);
+ pages = pages & supported;
+
+ if (pages)
+ obj->mm.page_sizes.sg = pages;
+
+ err = igt_write_huge(ctx, obj);
+
+ i915_gem_object_unpin_pages(obj);
+ __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
+ i915_gem_object_put(obj);
+
+ if (err) {
+ pr_err("%s write-huge failed with size=%u
pages=%u i=%d, j=%d\n",
+ __func__, size, pages, i, j);
+ goto out;
+ }
+ }
+
+ cond_resched();
+ }
+
+out:
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_ppgtt_pin_update(void *arg)
{
struct i915_gem_context *ctx = arg;
@@ -1812,6 +1910,7 @@ int i915_gem_huge_page_live_selftests(struct
drm_i915_private *i915)
SUBT
[Intel-gfx] [CI 4/7] drm/i915/selftests: add write-dword test for LMEM
From: Matthew Auld
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../drm/i915/selftests/intel_memory_region.c | 166 ++
1 file changed, 166 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 2e0f91fac85d..8bc6fadd14fb 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -11,9 +11,11 @@
#include "mock_gem_device.h"
#include "mock_region.h"
+#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_object_blt.h"
+#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_gt.h"
#include "selftests/igt_flush_test.h"
@@ -256,6 +258,125 @@ static int igt_mock_contiguous(void *arg)
return err;
}
+static int igt_gpu_write_dw(struct intel_context *ce,
+ struct i915_vma *vma,
+ u32 dword,
+ u32 value)
+{
+ return igt_gpu_fill_dw(ce, vma, dword * sizeof(u32),
+ vma->size >> PAGE_SHIFT, value);
+}
+
+static int igt_cpu_check(struct drm_i915_gem_object *obj, u32 dword, u32 val)
+{
+ unsigned long n;
+ int err;
+
+ i915_gem_object_lock(obj);
+ err = i915_gem_object_set_to_wc_domain(obj, false);
+ i915_gem_object_unlock(obj);
+ if (err)
+ return err;
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err)
+ return err;
+
+ for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) {
+ u32 __iomem *base;
+ u32 read_val;
+
+ base = i915_gem_object_lmem_io_map_page_atomic(obj, n);
+
+ read_val = ioread32(base + dword);
+ io_mapping_unmap_atomic(base);
+ if (read_val != val) {
+ pr_err("n=%lu base[%u]=%u, val=%u\n",
+ n, dword, read_val, val);
+ err = -EINVAL;
+ break;
+ }
+ }
+
+ i915_gem_object_unpin_pages(obj);
+ return err;
+}
+
+static int igt_gpu_write(struct i915_gem_context *ctx,
+struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_engines *engines;
+ struct i915_gem_engines_iter it;
+ struct i915_address_space *vm;
+ struct intel_context *ce;
+ I915_RND_STATE(prng);
+ IGT_TIMEOUT(end_time);
+ unsigned int count;
+ struct i915_vma *vma;
+ int *order;
+ int i, n;
+ int err = 0;
+
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+
+ n = 0;
+ count = 0;
+ for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+ count++;
+ if (!intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ vm = ce->vm;
+ n++;
+ }
+ i915_gem_context_unlock_engines(ctx);
+ if (!n)
+ return 0;
+
+ order = i915_random_order(count * count, &prng);
+ if (!order)
+ return -ENOMEM;
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out_free;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto out_free;
+
+ i = 0;
+ engines = i915_gem_context_lock_engines(ctx);
+ do {
+ u32 rng = prandom_u32_state(&prng);
+ u32 dword = offset_in_page(rng) / 4;
+
+ ce = engines->engines[order[i] % engines->num_engines];
+ i = (i + 1) % (count * count);
+ if (!ce || !intel_engine_can_store_dword(ce->engine))
+ continue;
+
+ err = igt_gpu_write_dw(ce, vma, dword, rng);
+ if (err)
+ break;
+
+ err = igt_cpu_check(obj, dword, rng);
+ if (err)
+ break;
+ } while (!__igt_timeout(end_time, NULL));
+ i915_gem_context_unlock_engines(ctx);
+
+out_free:
+ kfree(order);
+
+ if (err == -ENOMEM)
+ err = 0;
+
+ return err;
+}
+
static int igt_lmem_create(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -277,6 +398,50 @@ static int igt_lmem_create(void *arg)
return err;
}
+static int igt_lmem_write_gpu(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ struct drm_file *file;
+ I915_RND_STATE(prng);
+ u32 sz;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_
[Intel-gfx] [CI 6/7] drm/i915/selftests: prefer random sizes for the huge-GTT-page smoke tests
From: Matthew Auld
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 229 ++
1 file changed, 80 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index fa134a82083d..b777999655b0 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1317,204 +1317,137 @@ static int igt_ppgtt_exhaust_huge(void *arg)
return err;
}
-static int igt_ppgtt_internal_huge(void *arg)
-{
- struct i915_gem_context *ctx = arg;
- struct drm_i915_private *i915 = ctx->i915;
- struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_64K,
- SZ_128K,
- SZ_256K,
- SZ_512K,
- SZ_1M,
- SZ_2M,
- };
- int i;
- int err;
-
- /*
-* Sanity check that the HW uses huge pages correctly through internal
-* -- ensure that our writes land in the right place.
-*/
-
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_internal(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
-
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_64K) {
- pr_info("internal unable to allocate huge-page(s) with
size=%u\n",
- size);
- goto out_unpin;
- }
-
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("internal write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
-
- i915_gem_object_unpin_pages(obj);
- __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
- i915_gem_object_put(obj);
- }
-
- return 0;
-
-out_unpin:
- i915_gem_object_unpin_pages(obj);
-out_put:
- i915_gem_object_put(obj);
-
- return err;
-}
+typedef struct drm_i915_gem_object *
+(*igt_create_fn)(struct drm_i915_private *i915, u32 size, u32 flags);
static inline bool igt_can_allocate_thp(struct drm_i915_private *i915)
{
return i915->mm.gemfs && has_transparent_hugepage();
}
-static int igt_ppgtt_gemfs_huge(void *arg)
+static struct drm_i915_gem_object *
+igt_create_shmem(struct drm_i915_private *i915, u32 size, u32 flags)
{
- struct i915_gem_context *ctx = arg;
- struct drm_i915_private *i915 = ctx->i915;
- struct drm_i915_gem_object *obj;
- static const unsigned int sizes[] = {
- SZ_2M,
- SZ_4M,
- SZ_8M,
- SZ_16M,
- SZ_32M,
- };
- int i;
- int err;
-
- /*
-* Sanity check that the HW uses huge pages correctly through gemfs --
-* ensure that our writes land in the right place.
-*/
-
if (!igt_can_allocate_thp(i915)) {
- pr_info("missing THP support, skipping\n");
- return 0;
+ pr_info("%s missing THP support, skipping\n", __func__);
+ return ERR_PTR(-ENODEV);
}
- for (i = 0; i < ARRAY_SIZE(sizes); ++i) {
- unsigned int size = sizes[i];
-
- obj = i915_gem_object_create_shmem(i915, size);
- if (IS_ERR(obj))
- return PTR_ERR(obj);
-
- err = i915_gem_object_pin_pages(obj);
- if (err)
- goto out_put;
+ return i915_gem_object_create_shmem(i915, size);
+}
- if (obj->mm.page_sizes.phys < I915_GTT_PAGE_SIZE_2M) {
- pr_info("finishing test early, gemfs unable to allocate
huge-page(s) with size=%u\n",
- size);
- goto out_unpin;
- }
+static struct drm_i915_gem_object *
+igt_create_internal(struct drm_i915_private *i915, u32 size, u32 flags)
+{
+ return i915_gem_object_create_internal(i915, size);
+}
- err = igt_write_huge(ctx, obj);
- if (err) {
- pr_err("gemfs write-huge failed with size=%u\n",
- size);
- goto out_unpin;
- }
+static struct drm_i915_gem_object *
+igt_create_local(struct drm_i915_private *i915, u32 size
[Intel-gfx] [CI 2/7] drm/i915: setup io-mapping for LMEM
From: Abdiel Janulgue
Create an io-mapping to describe the CPU aperture for lmem.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c
b/drivers/gpu/drm/i915/intel_region_lmem.c
index 199532056e1b..9a351af45ce6 100644
--- a/drivers/gpu/drm/i915/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/intel_region_lmem.c
@@ -9,8 +9,32 @@
#include "gem/i915_gem_region.h"
#include "intel_region_lmem.h"
+static void
+region_lmem_release(struct intel_memory_region *mem)
+{
+ io_mapping_fini(&mem->iomap);
+ intel_memory_region_release_buddy(mem);
+}
+
+static int
+region_lmem_init(struct intel_memory_region *mem)
+{
+ int ret;
+
+ if (!io_mapping_init_wc(&mem->iomap,
+ mem->io_start,
+ resource_size(&mem->region)))
+ return -EIO;
+
+ ret = intel_memory_region_init_buddy(mem);
+ if (ret)
+ io_mapping_fini(&mem->iomap);
+
+ return ret;
+}
+
const struct intel_memory_region_ops intel_region_lmem_ops = {
- .init = intel_memory_region_init_buddy,
- .release = intel_memory_region_release_buddy,
+ .init = region_lmem_init,
+ .release = region_lmem_release,
.create_object = __i915_gem_lmem_object_create,
};
--
2.24.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/7] drm/i915/lmem: support kernel mapping
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 39 ++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 8 ++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 38 +++---
.../drm/i915/selftests/intel_memory_region.c | 113 ++
5 files changed, 189 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index 6a38d8028110..926f6c940e0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -9,11 +9,50 @@
#include "i915_drv.h"
const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops = {
+ .flags = I915_GEM_OBJECT_HAS_IOMEM,
+
.get_pages = i915_gem_object_get_pages_buddy,
.put_pages = i915_gem_object_put_pages_buddy,
.release = i915_gem_object_release_memory_region,
};
+/* XXX: Time to vfunc your life up? */
+void __iomem *
+i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, PAGE_SIZE);
+}
+
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ resource_size_t offset;
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset);
+}
+
+void __iomem *
+i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned long size)
+{
+ resource_size_t offset;
+
+ GEM_BUG_ON(!i915_gem_object_is_contiguous(obj));
+
+ offset = i915_gem_object_get_dma_address(obj, n);
+
+ return io_mapping_map_wc(&obj->mm.region->iomap, offset, size);
+}
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
{
return obj->ops == &i915_gem_lmem_obj_ops;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index fc3f15580fe3..7c176b8b7d2f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -14,6 +14,14 @@ struct intel_memory_region;
extern const struct drm_i915_gem_object_ops i915_gem_lmem_obj_ops;
+void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
+ unsigned long n, unsigned long size);
+void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj,
+ unsigned long n);
+void __iomem *
+i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj,
+ unsigned long n);
+
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index a387e3ee728b..96008374a412 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -31,10 +31,11 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGEBIT(0)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
-#define I915_GEM_OBJECT_IS_PROXY BIT(2)
-#define I915_GEM_OBJECT_NO_GGTTBIT(3)
-#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(4)
+#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
+#define I915_GEM_OBJECT_IS_PROXY BIT(3)
+#define I915_GEM_OBJECT_NO_GGTTBIT(4)
+#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(5)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index b0ec0959c13f..803bb7399cc6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "i915_gem_object.h"
#include "i915_scatterlist.h"
+#include "i915_gem_lmem.h"
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
@@ -154,6 +155,16 @@ static void __i915_gem_object_reset_page_iter(struct
drm_i915_gem_object *obj)
rcu_read_unlock();
}
+static void unmap_object(struct drm_i915_gem_object *obj, void *ptr)
+{
+
Re: [Intel-gfx] [igt-dev] [RFC i-g-t 1/1] intel-gpu-top: Support for client stats
On 25/10/2019 16:13, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-10-25 15:24:10) From: Tvrtko Ursulin Adds support for per-client engine busyness stats i915 exports in sysfs and produces output like the below: == intel-gpu-top - 935/ 935 MHz;0% RC6; 14.73 Watts; 1097 irqs/s Could we get "gpu / pkg Watts" pretty please? Sure, next week or so. Are irq/s interesting with execlists? Originally the idea was to say how many times clients were sleeping and being woken up. Now we interrupt to wipe the gpu's nose when it sneezes. IMC reads: 1401 MiB/s IMC writes:4 MiB/s ENGINE BUSY MI_SEMA MI_WAIT Render/3D/0 63.73% |███ | 3% 0% Blitter/09.53% |██▊ | 6% 0% Video/0 39.32% |███▊ | 16% 0% Video/1 15.62% |▋ | 0% 0% VideoEnhance/00.00% | | 0% 0% PIDNAME RCS BCS VCS VECS 4084gem_wsim |█▌ ||█ || || | 4086gem_wsim |█▌ || ||███|| | == Apart from the existing physical engine utilization it now also shows utilization per client and per engine class. Signed-off-by: Tvrtko Ursulin --- +#define SYSFS_CLIENTS "/sys/class/drm/card0/clients" We need to somehow pull the right card. Yeah, as I said RFC and reference only. :) Nothing shocking here. Where's the intel-gpu-overlay integration? ;) Maybe intel-gpu-overlay should become an output plugin for intel_gpu_top. :) Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests/blt: add some kthreads into the mix
== Series Details ==
Series: drm/i915/selftests/blt: add some kthreads into the mix
URL : https://patchwork.freedesktop.org/series/68563/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f43a0146b3fc drm/i915/selftests/blt: add some kthreads into the mix
-:159: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#159: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:253:
+{
+
-:169: WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply
#169: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c:263:
+ tsk = kzalloc(n_cpus * sizeof(struct task_struct *), GFP_KERNEL);
total: 0 errors, 1 warnings, 1 checks, 190 lines checked
___
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[Intel-gfx] [PATCH i-g-t] lib/i915: Use explicit iterator names in for_each_engine()
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:653:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, other) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:652:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../tests/i915/gem_exec_schedule.c: In function ‘measure_semaphore_power’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous local
[-Wshadow]
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1740:3: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, engine) {
^~~~
../lib/igt_gt.h:84:44: note: shadowed declaration is here
for (const struct intel_execution_engine *e__ = intel_execution_engines;\
^~~
../tests/i915/gem_exec_schedule.c:1719:2: note: in expansion of macro
‘for_each_physical_engine’
for_each_physical_engine(i915, signaler) {
^~~~
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
benchmarks/gem_syslatency.c | 16 +--
lib/i915/gem_ring.c | 4 +-
lib/igt_gt.h| 24 +++--
tests/amdgpu/amd_prime.c| 6 +-
tests/i915/gem_bad_reloc.c | 4 +-
tests/i915/gem_busy.c | 4 +-
tests/i915/gem_concurrent_all.c | 7 +-
tests/i915/gem_cs_prefetch.c| 2 +-
tests/i915/gem_ctx_create.c | 12 +--
tests/i915/gem_ctx_shared.c | 43
tests/i915/gem_ctx_switch.c | 2 +-
tests/i915/gem_ctx_thrash.c | 14 ++-
tests/i915/gem_eio.c| 29 +++---
tests/i915/gem_exec_async.c | 13 ++-
tests/i915/gem_exec_await.c | 7 +-
tests/i915/gem_exec_capture.c | 6 +-
tests/i915/gem_exec_create.c| 8 +-
tests/i915/gem_exec_fence.c | 61 ++-
tests/i915/gem_exec_flush.c | 2 +-
tests/i915/gem_exec_gttfill.c | 11 +-
tests/i915/gem_exec_latency.c | 33 +++---
tests/i915/gem_exec_nop.c | 44
tests/i915/gem_exec_params.c| 14 +--
tests/i915/gem_exec_reloc.c | 8 +-
tests/i915/gem_exec_reuse.c | 6 +-
tests/i915/gem_exec_schedule.c | 172 +++-
tests/i915/gem_exec_suspend.c | 20 ++--
tests/i915/gem_exec_whisper.c | 8 +-
tests/i915/gem_mocs_settings.c | 6 +-
tests/i915/gem_reset_stats.c| 10 +-
tests/i915/gem_ring_sync_loop.c | 5 +-
tests/i915/gem_ringfill.c | 3 +-
tests/i915/gem_shrink.c | 5 +-
tests/i915/gem_spin_batch.c | 2 +-
tests/i915/gem_storedw_loop.c | 2 +-
tests/i915/gem_sync.c | 99 +-
tests/i915/gem_userptr_blits.c | 7 +-
tests/i915/i915_module_load.c | 22 ++--
tests/kms_busy.c| 30 +++---
tests/prime_busy.c | 8 +-
tests/prime_vgem.c | 16 +--
41 files changed, 368 insertions(+), 427 deletions(-)
diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d7cf0ed49..402306300 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -79,17 +79,6 @@ static void force_low_latency(void)
#define ENGINE_FLAGS (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
-static bool ignore_engine(int fd, unsigned engine)
-{
- if (engine == 0)
- return true;
-
- if (gem_has_bsd2(fd) && engine == I915_EXEC_BSD)
- return true;
-
- return false;
-}
-
static void *gem_busyspin(void *arg)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
@@ -100,14 +89,13 @@ static void *gem_busyspin(void *arg)
bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
unsigned engines[16];
unsigned nengine;
- unsigned engine;
int fd;
fd = drm_open_driver(DRIVER_INTEL);
nengine = 0;
- for_each_engine(fd, engine)
- if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
+ for_each_physical_engine(e, fd)
+ engines[nengine++] = eb_ring(e);
memset(obj, 0, sizeof(obj));
obj[0].handle = gem_create(fd, 4096);
diff --git a/lib/i915/gem_ring.c b/lib/i915/gem_ring.c
index 5ca2a728b..99f4741cb
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests/blt: add some kthreads into the mix
== Series Details ==
Series: drm/i915/selftests/blt: add some kthreads into the mix
URL : https://patchwork.freedesktop.org/series/68563/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14981
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14981 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14981, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14981:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-bsw-n3050/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14981 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@flink-lifetime:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-icl-u3/igt@gem_flink_ba...@flink-lifetime.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [PASS][7] -> [WARN][8] ([fdo#109483])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-byt-n2820: [DMESG-FAIL][11] ([fdo#112096]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][13] ([fdo#111600]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +1
similar issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14981/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 43)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squ
[Intel-gfx] [PATCH] drm/i915/pmu: Initialise the spinlock before registering
As the GT may be running in parallel with the module initialisation
code, we may enter i915_pmu_gt_parked() as we are executing
i915_pmu_register(). We have to init the spinlock before we mark
pmu.event_init so that it is available for use by i915_pmu_gt_parked()
(which may run as soon as event_init is set).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_pmu.c | 37 +
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 85912917c062..b5b67c0624ff 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1101,20 +1101,6 @@ void i915_pmu_register(struct drm_i915_private *i915)
return;
}
- i915_pmu_events_attr_group.attrs = create_event_attributes(pmu);
- if (!i915_pmu_events_attr_group.attrs)
- goto err;
-
- pmu->base.attr_groups = i915_pmu_attr_groups;
- pmu->base.task_ctx_nr = perf_invalid_context;
- pmu->base.event_init= i915_pmu_event_init;
- pmu->base.add = i915_pmu_event_add;
- pmu->base.del = i915_pmu_event_del;
- pmu->base.start = i915_pmu_event_start;
- pmu->base.stop = i915_pmu_event_stop;
- pmu->base.read = i915_pmu_event_read;
- pmu->base.event_idx = i915_pmu_event_event_idx;
-
spin_lock_init(&pmu->lock);
hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
pmu->timer.function = i915_sample;
@@ -1128,9 +1114,23 @@ void i915_pmu_register(struct drm_i915_private *i915)
if (!pmu->name)
goto err;
+ i915_pmu_events_attr_group.attrs = create_event_attributes(pmu);
+ if (!i915_pmu_events_attr_group.attrs)
+ goto err_name;
+
+ pmu->base.attr_groups = i915_pmu_attr_groups;
+ pmu->base.task_ctx_nr = perf_invalid_context;
+ pmu->base.event_init= i915_pmu_event_init;
+ pmu->base.add = i915_pmu_event_add;
+ pmu->base.del = i915_pmu_event_del;
+ pmu->base.start = i915_pmu_event_start;
+ pmu->base.stop = i915_pmu_event_stop;
+ pmu->base.read = i915_pmu_event_read;
+ pmu->base.event_idx = i915_pmu_event_event_idx;
+
ret = perf_pmu_register(&pmu->base, pmu->name, -1);
if (ret)
- goto err_name;
+ goto err_attr;
ret = i915_pmu_register_cpuhp_state(pmu);
if (ret)
@@ -1140,13 +1140,14 @@ void i915_pmu_register(struct drm_i915_private *i915)
err_unreg:
perf_pmu_unregister(&pmu->base);
+err_attr:
+ pmu->base.event_init = NULL;
+ free_event_attributes(pmu);
err_name:
if (!is_igp(i915))
kfree(pmu->name);
err:
- pmu->base.event_init = NULL;
- free_event_attributes(pmu);
- DRM_NOTE("Failed to register PMU! (err=%d)\n", ret);
+ dev_notice(i915->drm.dev, "Failed to register PMU!\n");
}
void i915_pmu_unregister(struct drm_i915_private *i915)
--
2.24.0.rc1
___
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Re: [Intel-gfx] [PATCH 3/4] drm/i915: do not set MOCS control values on dgfx
On 10/24/19 12:51 PM, Lucas De Marchi wrote: On dgfx there's no LLC and eDRAM control table. Since now this also means the device has global MOCS, just return early on the initialization function. L3 settings still apply and still need to be tweaked. Bspec: 45101 Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_mocs.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 932833e5b712..9e19637e0225 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -462,6 +462,12 @@ static void intel_mocs_init_global(struct intel_gt *gt) struct drm_i915_mocs_table table; unsigned int index; + /* +* LLC and eDRAM control values are not only applicable to dgfx the "only" in this sentence is confusing IMO. With it removed: Reviewed-by: Daniele Ceraolo Spurio Daniele +*/ + if (IS_DGFX(gt->i915)) + return; + GEM_BUG_ON(!HAS_GLOBAL_MOCS_REGISTERS(gt->i915)); if (!get_mocs_settings(gt->i915, &table)) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: capture aux page table error register
== Series Details == Series: drm/i915: capture aux page table error register URL : https://patchwork.freedesktop.org/series/68565/ State : warning == Summary == $ dim checkpatch origin/drm-tip 71955d0b2b64 drm/i915: capture aux page table error register -:7: WARNING:TYPO_SPELLING: 'auxilliary' may be misspelled - perhaps 'auxiliary'? #7: auxilliary surface. If we screw up the page tables, the HW has a total: 0 errors, 1 warnings, 0 checks, 35 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drm/i915/cml: Remove unsupport PCI ID
On Sat, Oct 26, 2019 at 04:32:25AM +0800, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some sku
> is not support yet so remove them.
A better description would be that some PCI IDs were removed from the
CML IDs in BSpec. The "not support yet" implies some i915 driver
problem, when this is just a sync w/ BSpec updates.
Thanks!
-James
>
> v2: remove some inaccurate descriptions.
> v3: fix typo.
> v4: add missing version number.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Cooper Chiou
> Signed-off-by: Lee Shawn C
> ---
> include/drm/i915_pciids.h | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index a70c982ddff9..56e823cdc717 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -448,9 +448,7 @@
> #define INTEL_CML_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x9B21, info), \
> INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAB, info), \
> INTEL_VGA_DEVICE(0x9BAC, info), \
> - INTEL_VGA_DEVICE(0x9BA0, info), \
> INTEL_VGA_DEVICE(0x9BA5, info), \
> INTEL_VGA_DEVICE(0x9BA8, info), \
> INTEL_VGA_DEVICE(0x9BA4, info), \
> @@ -460,9 +458,7 @@
> #define INTEL_CML_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x9B41, info), \
> INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCB, info), \
> INTEL_VGA_DEVICE(0x9BCC, info), \
> - INTEL_VGA_DEVICE(0x9BC0, info), \
> INTEL_VGA_DEVICE(0x9BC5, info), \
> INTEL_VGA_DEVICE(0x9BC8, info), \
> INTEL_VGA_DEVICE(0x9BC4, info), \
> --
> 2.17.1
>
> ___
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Re: [Intel-gfx] [PATCH v2] kernel-doc: rename the kernel-doc directive 'functions' to 'identifiers'
On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> > On Sun, 20 Oct 2019 21:17:17 +0800
> > Changbin Du wrote:
> >
> >> The 'functions' directive is not only for functions, but also works for
> >> structs/unions. So the name is misleading. This patch renames it to
> >> 'identifiers', which specific the functions/types to be included in
> >> documentation. We keep the old name as an alias of the new one before
> >> all documentation are updated.
> >>
> >> Signed-off-by: Changbin Du
> >
> > So I think this is basically OK, but I have one more request...
> >
> > [...]
> >
> >> diff --git a/Documentation/sphinx/kerneldoc.py
> >> b/Documentation/sphinx/kerneldoc.py
> >> index 1159405cb920..0689f9c37f1e 100644
> >> --- a/Documentation/sphinx/kerneldoc.py
> >> +++ b/Documentation/sphinx/kerneldoc.py
> >> @@ -59,9 +59,10 @@ class KernelDocDirective(Directive):
> >> optional_arguments = 4
> >> option_spec = {
> >> 'doc': directives.unchanged_required,
> >> -'functions': directives.unchanged,
> >> 'export': directives.unchanged,
> >> 'internal': directives.unchanged,
> >> +'identifiers': directives.unchanged,
> >> +'functions': directives.unchanged, # alias of 'identifiers'
> >> }
> >> has_content = False
> >>
> >> @@ -71,6 +72,7 @@ class KernelDocDirective(Directive):
> >>
> >> filename = env.config.kerneldoc_srctree + '/' + self.arguments[0]
> >> export_file_patterns = []
> >> +identifiers = None
> >>
> >> # Tell sphinx of the dependency
> >> env.note_dependency(os.path.abspath(filename))
> >> @@ -86,19 +88,22 @@ class KernelDocDirective(Directive):
> >> export_file_patterns =
> >> str(self.options.get('internal')).split()
> >> elif 'doc' in self.options:
> >> cmd += ['-function', str(self.options.get('doc'))]
> >> +elif 'identifiers' in self.options:
> >> +identifiers = self.options.get('identifiers').split()
> >> elif 'functions' in self.options:
> >> -functions = self.options.get('functions').split()
> >> -if functions:
> >> -for f in functions:
> >> -cmd += ['-function', f]
> >> -else:
> >> -cmd += ['-no-doc-sections']
> >> +identifiers = self.options.get('functions').split()
> >
> > Rather than do this, can you just change the elif line to read:
> >
> > elif ('identifiers' in self.options) or ('functions' in self.options):
> >
> > ...then leave the rest of the code intact? It keeps the logic together,
> > and avoids the confusing distinction between identifiers=='' and
> > identifiers==None .
>
> I think the problem is you still need to distinguish between the two for
> the get('functions') part.
>
> One option is to rename 'functions' to 'identifiers' in the above block,
> and put something like this above the whole if ladder (untested):
>
> # backward compat
> if 'functions' in self.options:
> if 'identifiers' in self.options:
> kernellog.warn(env.app, "fail")
This will miss the content of 'functions' directive if both exist in
same doc.
> else:
> self.options.set('identifiers', self.options.get('functions'))
>
> BR,
> Jani.
>
After comparing, I still perfer my original code which is simpler. :)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Cheers,
Changbin Du
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v4] drm/i915/cml: Remove unsupport PCI ID (rev5)
== Series Details == Series: series starting with [v4] drm/i915/cml: Remove unsupport PCI ID (rev5) URL : https://patchwork.freedesktop.org/series/68547/ State : failure == Summary == Applying: drm/i915/cml: Remove unsupport PCI ID Applying: drm/i915/cml: Separate U sereis pci id from origianl list. error: sha1 information is lacking or useless (include/drm/i915_pciids.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915/cml: Separate U sereis pci id from origianl list. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: capture aux page table error register
== Series Details ==
Series: drm/i915: capture aux page table error register
URL : https://patchwork.freedesktop.org/series/68565/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14982
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14982 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14982, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14982:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14982 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bwr-2160:[PASS][5] -> [FAIL][6] ([fdo#100368])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-bwr-2160/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@prime_busy@basic-before-default:
- fi-icl-u3: [PASS][7] -> [DMESG-WARN][8] ([fdo#107724]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_b...@basic-before-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-icl-u3/igt@prime_b...@basic-before-default.html
Possible fixes
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-byt-n2820: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/fi-icl-u3/igt@prime_v...@basic-wait-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 42)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-bsw-cyan fi-icl-y fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7186 -> Patchwork_14982
CI-20190529: 20190529
CI_DRM_7186: ce03ec86789ef8fc41a56176e5f2a9251182183c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5241: 17b87c378fa155390b13a43f141371fd899d567b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14982: 71955d0b2b641acecbd534e2c1a5a30455756ea7 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
71955d0b2b64 drm/i915: capture aux page table error register
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14982/index.html
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Re: [Intel-gfx] [PATCH] drm/i915: Fix PCH reference clock for FDI on HSW/BDW
On Wed, Oct 23, 2019 at 03:44:50PM +0300, Imre Deak wrote:
> On Tue, Oct 22, 2019 at 09:56:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The change to skip the PCH reference initialization during fastboot
> > did end up breaking FDI. To fix that let's try to do the PCH reference
> > init whenever we're disabling a DPLL that was using said reference
> > previously.
> >
> > Cc: sta...@vger.kernel.org
> > Tested-by: Andrija
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112084
> > Fixes: b16c7ed95caf ("drm/i915: Do not touch the PCH SSC reference if a PLL
> > is using it")
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Imre Deak
CI had some bsd fails which are not relevant, so pushed to dinq.
Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 +++
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > 3 files changed, 23 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 236fdf122e47..da76f794a965 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9359,7 +9359,6 @@ static bool wrpll_uses_pch_ssc(struct
> > drm_i915_private *dev_priv,
> > static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
> > {
> > struct intel_encoder *encoder;
> > - bool pch_ssc_in_use = false;
> > bool has_fdi = false;
> >
> > for_each_intel_encoder(&dev_priv->drm, encoder) {
> > @@ -9387,22 +9386,24 @@ static void lpt_init_pch_refclk(struct
> > drm_i915_private *dev_priv)
> > * clock hierarchy. That would also allow us to do
> > * clock bending finally.
> > */
> > + dev_priv->pch_ssc_use = 0;
> > +
> > if (spll_uses_pch_ssc(dev_priv)) {
> > DRM_DEBUG_KMS("SPLL using PCH SSC\n");
> > - pch_ssc_in_use = true;
> > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
> > }
> >
> > if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
> > DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
> > - pch_ssc_in_use = true;
> > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
> > }
> >
> > if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
> > DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
> > - pch_ssc_in_use = true;
> > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
> > }
> >
> > - if (pch_ssc_in_use)
> > + if (dev_priv->pch_ssc_use)
> > return;
> >
> > if (has_fdi) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index ec10fa7d3c69..3ce0a023eee0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -526,16 +526,31 @@ static void hsw_ddi_wrpll_disable(struct
> > drm_i915_private *dev_priv,
> > val = I915_READ(WRPLL_CTL(id));
> > I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
> > POSTING_READ(WRPLL_CTL(id));
> > +
> > + /*
> > +* Try to set up the PCH reference clock once all DPLLs
> > +* that depend on it have been shut down.
> > +*/
> > + if (dev_priv->pch_ssc_use & BIT(id))
> > + intel_init_pch_refclk(dev_priv);
> > }
> >
> > static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
> > struct intel_shared_dpll *pll)
> > {
> > + enum intel_dpll_id id = pll->info->id;
> > u32 val;
> >
> > val = I915_READ(SPLL_CTL);
> > I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
> > POSTING_READ(SPLL_CTL);
> > +
> > + /*
> > +* Try to set up the PCH reference clock once all DPLLs
> > +* that depend on it have been shut down.
> > +*/
> > + if (dev_priv->pch_ssc_use & BIT(id))
> > + intel_init_pch_refclk(dev_priv);
> > }
> >
> > static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 8882c0908c3b..5332825e0ce4 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1348,6 +1348,8 @@ struct drm_i915_private {
> > } contexts;
> > } gem;
> >
> > + u8 pch_ssc_use;
> > +
> > /* For i915gm/i945gm vblank irq workaround */
> > u8 vblank_enabled;
> >
> > --
> > 2.21.0
> >
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
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Intel
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[Intel-gfx] [PATCH v2] drm/i915/selftests/blt: add some kthreads into the mix
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture of ctx priorities per thread to make pre-emption a
possibility.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
.../i915/gem/selftests/i915_gem_object_blt.c | 178 +++---
1 file changed, 153 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
index 9ec55b3a3815..9666c0aeb6de 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
@@ -7,36 +7,67 @@
#include "i915_selftest.h"
+#include "gem/i915_gem_context.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/i915_random.h"
#include "selftests/mock_drm.h"
#include "huge_gem_object.h"
#include "mock_context.h"
-static int igt_fill_blt(void *arg)
+struct igt_thread_arg {
+ struct drm_i915_private *i915;
+ struct rnd_state prng;
+ unsigned int n_cpus;
+};
+
+static int igt_fill_blt_thread(void *arg)
{
- struct drm_i915_private *i915 = arg;
- struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct igt_thread_arg *thread = arg;
+ struct drm_i915_private *i915 = thread->i915;
+ struct rnd_state *prng = &thread->prng;
struct drm_i915_gem_object *obj;
- struct rnd_state prng;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ unsigned int prio;
IGT_TIMEOUT(end);
- u32 *vaddr;
- int err = 0;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
- prandom_seed_state(&prng, i915_selftest.random_seed);
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_file;
+ }
- /*
-* XXX: needs some threads to scale all these tests, also maybe throw
-* in submission from higher priority context to see if we are
-* preempted for very large objects...
-*/
+ prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
+ ctx->sched.priority = I915_USER_PRIORITY(prio);
+
+ ce = i915_gem_context_get_engine(ctx, BCS0);
+ GEM_BUG_ON(IS_ERR(ce));
do {
const u32 max_block_size = S16_MAX * PAGE_SIZE;
- u32 sz = min_t(u64, ce->vm->total >> 4,
prandom_u32_state(&prng));
- u32 phys_sz = sz % (max_block_size + 1);
- u32 val = prandom_u32_state(&prng);
+ u32 val = prandom_u32_state(prng);
+ u64 total = ce->vm->total;
+ u32 phys_sz;
+ u32 sz;
+ u32 *vaddr;
u32 i;
+ /*
+* If we have a tiny shared address space, like for the GGTT
+* then we can't be too greedy.
+*/
+ if (i915_is_ggtt(ce->vm))
+ total = div64_u64(total, thread->n_cpus);
+
+ sz = min_t(u64, total >> 4, prandom_u32_state(prng));
+ phys_sz = sz % (max_block_size + 1);
+
sz = round_up(sz, PAGE_SIZE);
phys_sz = round_up(phys_sz, PAGE_SIZE);
@@ -98,28 +129,56 @@ static int igt_fill_blt(void *arg)
if (err == -ENOMEM)
err = 0;
+ intel_context_put(ce);
+out_file:
+ mock_file_free(i915, file);
return err;
}
-static int igt_copy_blt(void *arg)
+static int igt_copy_blt_thread(void *arg)
{
- struct drm_i915_private *i915 = arg;
- struct intel_context *ce = i915->engine[BCS0]->kernel_context;
+ struct igt_thread_arg *thread = arg;
+ struct drm_i915_private *i915 = thread->i915;
+ struct rnd_state *prng = &thread->prng;
struct drm_i915_gem_object *src, *dst;
- struct rnd_state prng;
+ struct i915_gem_context *ctx;
+ struct intel_context *ce;
+ struct drm_file *file;
+ unsigned int prio;
IGT_TIMEOUT(end);
- u32 *vaddr;
- int err = 0;
+ int err;
+
+ file = mock_file(i915);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
- prandom_seed_state(&prng, i915_selftest.random_seed);
+ ctx = live_context(i915, file);
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto out_file;
+ }
+
+ prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng);
+ ctx->sched.priority = I915_USER_PRIORITY(prio);
+
+ ce = i915_gem_context_get_engine(ctx, BCS0);
+ GEM_BUG_ON(IS_ERR(ce));
do {
const u32
Re: [Intel-gfx] [PATCH] drm/i915: capture aux page table error register
Quoting Lionel Landwerlin (2019-10-25 13:29:46) > On 25/10/2019 15:22, Chris Wilson wrote: > > Quoting Lionel Landwerlin (2019-10-25 13:17:18) > >> TGL introduced a feature in which we map the main surface to the > >> auxilliary surface. If we screw up the page tables, the HW has a > >> register to tell us which engine encounters a fault in the page table > >> walk. > > Platform specific, or for likely all gen12 and then gen12+? > > > It also applies to the new DGFX patches that started trickling down. > > Though I don't know where the Gen12 boundary is which is why I went with > platform name. I gambled and applied to it to gen12. Thanks, pushed. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/pmu: Initialise the spinlock before registering
On Fri, 25 Oct 2019 at 17:55, Chris Wilson wrote: > > As the GT may be running in parallel with the module initialisation > code, we may enter i915_pmu_gt_parked() as we are executing > i915_pmu_register(). We have to init the spinlock before we mark > pmu.event_init so that it is available for use by i915_pmu_gt_parked() > (which may run as soon as event_init is set). > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112127 > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Update VSC SDP / HDR Metadata SDP states on pipe updates. (rev2)
== Series Details ==
Series: Update VSC SDP / HDR Metadata SDP states on pipe updates. (rev2)
URL : https://patchwork.freedesktop.org/series/68531/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14984
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/index.html
Known issues
Here are the changes found in Patchwork_14984 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@bad-open:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1
similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/fi-icl-u3/igt@gem_flink_ba...@bad-open.html
Possible fixes
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-byt-n2820: [DMESG-FAIL][3] ([fdo#112096]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/fi-byt-n2820/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_busy@basic-flip-a:
- {fi-tgl-u2}:[DMESG-WARN][5] ([fdo#111600]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/fi-tgl-u2/igt@kms_b...@basic-flip-a.html
* igt@prime_vgem@basic-wait-default:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-icl-u3/igt@prime_v...@basic-wait-default.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/fi-icl-u3/igt@prime_v...@basic-wait-default.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111407]) -> [FAIL][10] ([fdo#111045]
/ [fdo#111096])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7186/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 42)
--
Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-icl-y fi-byt-clapper
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7186 -> Patchwork_14984
CI-20190529: 20190529
CI_DRM_7186: ce03ec86789ef8fc41a56176e5f2a9251182183c @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5241: 17b87c378fa155390b13a43f141371fd899d567b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14984: 292ef3c53a3d9ca15836e3b9a6686b751937d62b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
292ef3c53a3d drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
updates
0b64a1799b48 drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
needed
e0e6ba499fc5 drm/i915/dp: Stop sending of VSC SDP when it is not needed
990662350f3c drm/i915: Add checking a specific Video DIP is enabled or not
6a402331faeb drm/i915: Add whether or not to enable an each of Video DIP
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14984/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CI: Test revert some of the documentation fixes
== Series Details == Series: CI: Test revert some of the documentation fixes URL : https://patchwork.freedesktop.org/series/68567/ State : warning == Summary == $ dim checkpatch origin/drm-tip 919d7fcfb94e CI: Test revert some of the documentation fixes -:24: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 0 warnings, 0 checks, 11 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.DOCS: warning for CI: Test revert some of the documentation fixes
== Series Details == Series: CI: Test revert some of the documentation fixes URL : https://patchwork.freedesktop.org/series/68567/ State : warning == Summary == $ make htmldocs 2>&1 | grep i915 | grep -v "reading sources" | grep -v "writing output" ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:342: warning: Function parameter or member 'wakeref' not described in 'intel_shared_dpll' ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/11] drm/i915/gem: Make context persistence optional
On Thu, Oct 24, 2019 at 6:40 AM Chris Wilson
wrote:
> Our existing behaviour is to allow contexts and their GPU requests to
> persist past the point of closure until the requests are complete. This
> allows clients to operate in a 'fire-and-forget' manner where they can
> setup a rendering pipeline and hand it over to the display server and
> immediately exiting. As the rendering pipeline is kept alive until
> completion, the display server (or other consumer) can use the results
> in the future and present them to the user.
>
> However, not all clients want this persistent behaviour and would prefer
> that the contexts are cleaned up immediately upon closure. This ensures
> that when clients are run without hangchecking, any GPU hang is
> terminated with the process and does not continue to hog resources.
>
> By defining a context property to allow clients to control persistence
> explicitly, we can remove the blanket advice to disable hangchecking
> that seems to be far too prevalent.
>
Just to be clear, when you say "disable hangchecking" do you mean disabling
it for all processes via a kernel parameter at boot time or a sysfs entry
or similar? Or is there some mechanism whereby a context can request no
hang checking?
> The default behaviour for new controls is the legacy persistence mode.
> New clients will have to opt out for immediate cleanup on context
> closure. If the hangchecking modparam is disabled, so is persistent
> context support -- all contexts will be terminated on closure.
>
What happens to fences when the context is cancelled? Is it the same
behavior as we have today for when a GPU hang is detected and a context is
banned?
--Jason
> Testcase: igt/gem_ctx_persistence
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Michał Winiarski
> Cc: Jon Bloomfield
> Reviewed-by: Jon Bloomfield
> Reviewed-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 50 ++-
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 15 ++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
> .../gpu/drm/i915/gem/selftests/mock_context.c | 2 +
> include/uapi/drm/i915_drm.h | 15 ++
> 5 files changed, 82 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 55f1f93c0925..0f1bbf5d1a11 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -437,12 +437,39 @@ static void context_close(struct i915_gem_context
> *ctx)
> * case we opt to forcibly kill off all remaining requests on
> * context close.
> */
> - if (!i915_modparams.enable_hangcheck)
> + if (!i915_gem_context_is_persistent(ctx) ||
> + !i915_modparams.enable_hangcheck)
> kill_context(ctx);
>
> i915_gem_context_put(ctx);
> }
>
> +static int __context_set_persistence(struct i915_gem_context *ctx, bool
> state)
> +{
> + if (i915_gem_context_is_persistent(ctx) == state)
> + return 0;
> +
> + if (state) {
> + /*
> +* Only contexts that are short-lived [that will expire or
> be
> +* reset] are allowed to survive past termination. We
> require
> +* hangcheck to ensure that the persistent requests are
> healthy.
> +*/
> + if (!i915_modparams.enable_hangcheck)
> + return -EINVAL;
> +
> + i915_gem_context_set_persistence(ctx);
> + } else {
> + /* To cancel a context we use "preempt-to-idle" */
> + if (!(ctx->i915->caps.scheduler &
> I915_SCHEDULER_CAP_PREEMPTION))
> + return -ENODEV;
> +
> + i915_gem_context_clear_persistence(ctx);
> + }
> +
> + return 0;
> +}
> +
> static struct i915_gem_context *
> __create_context(struct drm_i915_private *i915)
> {
> @@ -477,6 +504,7 @@ __create_context(struct drm_i915_private *i915)
>
> i915_gem_context_set_bannable(ctx);
> i915_gem_context_set_recoverable(ctx);
> + __context_set_persistence(ctx, true /* cgroup hook? */);
>
> for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
> ctx->hang_timestamp[i] = jiffies -
> CONTEXT_FAST_HANG_JIFFIES;
> @@ -633,6 +661,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
> *i915, int prio)
> return ctx;
>
> i915_gem_context_clear_bannable(ctx);
> + i915_gem_context_set_persistence(ctx);
> ctx->sched.priority = I915_USER_PRIORITY(prio);
>
> GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
> @@ -1743,6 +1772,16 @@ get_engines(struct i915_gem_context *ctx,
> return err;
> }
>
> +static int
> +set_persistence(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + if (args->size)
> +
[Intel-gfx] ✗ Fi.CI.BAT: failure for CI: Test revert some of the documentation fixes
== Series Details ==
Series: CI: Test revert some of the documentation fixes
URL : https://patchwork.freedesktop.org/series/68567/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7187 -> Patchwork_14985
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_14985 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14985, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/index.html
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_14985:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
Known issues
Here are the changes found in Patchwork_14985 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1
similar issue
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-icl-u3/igt@gem_flink_ba...@double-flink.html
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6] +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-icl-u3/igt@gem_exec_susp...@basic-s4-devices.html
* {igt@i915_selftest@live_gt_heartbeat}:
- {fi-icl-dsi}: [DMESG-FAIL][7] ([fdo#112096]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-icl-dsi/igt@i915_selftest@live_gt_heartbeat.html
- fi-cml-u2: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-cml-u2/igt@i915_selftest@live_gt_heartbeat.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-cml-u2/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#111407]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7187/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (49 -> 42)
--
Additional (1): fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_7187 -> Patchwork_14985
CI-20190529: 20190529
CI_DRM_7187: 9df5aeba240a65ea80008020d3027484bc6055b3 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5241: 17b87c378fa155390b13a43f141371fd899d567b @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14985: 919d7fcfb94ebb45d46f04dc505d53453b85264b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
919d7fcfb94e CI: Test revert some of the documentation fixes
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14985/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Encapsulate kconfig constant values inside boolean predicates
== Series Details == Series: series starting with [1/2] drm/i915: Encapsulate kconfig constant values inside boolean predicates URL : https://patchwork.freedesktop.org/series/68569/ State : warning == Summary == $ dim checkpatch origin/drm-tip 96cf8a97600c drm/i915: Encapsulate kconfig constant values inside boolean predicates 0147bb0ed1c5 drm/i915/selftests: Initialise err in case there are no engines! -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:255 live_heartbeat_fast() error: uninitialized symbol 'err'. total: 0 errors, 1 warnings, 0 checks, 16 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Fri, Oct 25, 2019 at 12:53:52PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
>
> v4:
> - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
> masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
> as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
> can't be enabled(BSpec)
>
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
> time for TGL and indicate that QGV setting is not yet available.
>
> v6:
> - Increase number of supported QGV points to be in sync with BSpec.
>
> Reviewed-by: James Ausmus
> Signed-off-by: Stanislav Lisovskiy
> Cc: Ville Syrjälä
> Cc: James Ausmus
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 16 +++
> drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
> drivers/gpu/drm/i915/display/intel_bw.c | 111 ++
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 57 -
> .../drm/i915/display/intel_display_types.h| 3 +
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_sideband.c | 27 -
> 9 files changed, 198 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..b3f4f02f380b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> return &crtc_state->base;
> }
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +
> /**
> * intel_crtc_destroy_state - destroy crtc state
> * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
> #define __INTEL_ATOMIC_H__
>
> #include
> +#include "intel_display_types.h"
>
> struct drm_atomic_state;
> struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *state);
>
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
> struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..60249d9776d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,14 +8,20 @@
> #include "intel_bw.h"
> #include "intel_display_types.h"
> #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
>
> /* Parameters for Qclk Geyserville (QGV) */
> struct intel_qgv_point {
> u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
> };
>
> +
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 4
Shouldn't this be defined in intel_bw.h?
From what I'm seeing in BSpec 53998 (Gen12), in the
MAILBOX_GTDRIVER_CMD_SAGV_DE_MEM_SS_CONFIG section, there can be 8
points (even though the pseudo-code a couple of sections later defines
it as 4), and it looks like BSpec 54023 (Gen11) has the same bit
defines. I think I trust the bit defines more than the pseudo-code :)
With the above fixed, my R-b from version applies to this version.
Thanks!
-James
> +
> struct intel_qgv_info {
> - struct intel_qgv_point points[3];
> + struct intel_qgv
Re: [Intel-gfx] [PATCH] drm: Add support for integrated privacy screens
On Fri, Oct 25, 2019 at 1:36 PM Thierry Reding wrote:
>
> On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> > Hi,
> >
> > Thanks for your review and comments. Please see inline below.
> >
> > On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> > wrote:
> > >
> > > On Tue, Oct 22, 2019 at 05:12:06PM -0700, Rajat Jain wrote:
> > > > Certain laptops now come with panels that have integrated privacy
> > > > screens on them. This patch adds support for such panels by adding
> > > > a privacy-screen property to the drm_connector for the panel, that
> > > > the userspace can then use to control and check the status. The idea
> > > > was discussed here:
> > > >
> > > > https://lkml.org/lkml/2019/10/1/786
> > > >
> > > > ACPI methods are used to identify, query and control privacy screen:
> > > >
> > > > * Identifying an ACPI object corresponding to the panel: The patch
> > > > follows ACPI Spec 6.3 (available at
> > > > https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf).
> > > > Pages 1119 - 1123 describe what I believe, is a standard way of
> > > > identifying / addressing "display panels" in the ACPI tables, thus
> > > > allowing kernel to attach ACPI nodes to the panel. IMHO, this ability
> > > > to identify and attach ACPI nodes to drm connectors may be useful for
> > > > reasons other privacy-screens, in future.
> > > >
> > > > * Identifying the presence of privacy screen, and controlling it, is
> > > > done
> > > > via ACPI _DSM methods.
> > > >
> > > > Currently, this is done only for the Intel display ports. But in future,
> > > > this can be done for any other ports if the hardware becomes available
> > > > (e.g. external monitors supporting integrated privacy screens?).
> > > >
> > > > Also, this code can be extended in future to support non-ACPI methods
> > > > (e.g. using a kernel GPIO driver to toggle a gpio that controls the
> > > > privacy-screen).
> > > >
> > > > Signed-off-by: Rajat Jain
> > > > ---
> > > > drivers/gpu/drm/Makefile| 1 +
> > > > drivers/gpu/drm/drm_atomic_uapi.c | 5 +
> > > > drivers/gpu/drm/drm_connector.c | 38 +
> > > > drivers/gpu/drm/drm_privacy_screen.c| 176
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +
> > > > include/drm/drm_connector.h | 18 +++
> > > > include/drm/drm_mode_config.h | 7 +
> > > > include/drm/drm_privacy_screen.h| 33 +
> > > > 8 files changed, 281 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/drm_privacy_screen.c
> > > > create mode 100644 include/drm/drm_privacy_screen.h
> > >
> > > I like this much better than the prior proposal to use sysfs. However
> > > the support currently looks a bit tangled. I realize that we only have a
> > > single implementation for this in hardware right now, so there's no use
> > > in over-engineering things, but I think we can do a better job from the
> > > start without getting into too many abstractions. See below.
> > >
> > > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> > > > index 82ff826b33cc..e1fc33d69bb7 100644
> > > > --- a/drivers/gpu/drm/Makefile
> > > > +++ b/drivers/gpu/drm/Makefile
> > > > @@ -19,6 +19,7 @@ drm-y := drm_auth.o drm_cache.o \
> > > > drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
> > > > drm_client_modeset.o drm_atomic_uapi.o drm_hdcp.o
> > > >
> > > > +drm-$(CONFIG_ACPI) += drm_privacy_screen.o
> > > > drm-$(CONFIG_DRM_LEGACY) += drm_legacy_misc.o drm_bufs.o drm_context.o
> > > > drm_dma.o drm_scatter.o drm_lock.o
> > > > drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
> > > > drm-$(CONFIG_DRM_VM) += drm_vm.o
> > > > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > index 7a26bfb5329c..44131165e4ea 100644
> > > > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > > > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > > > @@ -30,6 +30,7 @@
> > > > #include
> > > > #include
> > > > #include
> > > > +#include
> > > > #include
> > > > #include
> > > >
> > > > @@ -766,6 +767,8 @@ static int drm_atomic_connector_set_property(struct
> > > > drm_connector *connector,
> > > > fence_ptr);
> > > > } else if (property == connector->max_bpc_property) {
> > > > state->max_requested_bpc = val;
> > > > + } else if (property == config->privacy_screen_property) {
> > > > + drm_privacy_screen_set_val(connector, val);
> > >
> > > This doesn't look right. Shouldn't you store the value in the connector
> > > state and then leave it up to the connector driver to set it
> > > appropriately? I think that also has the advantage of untangling this
> > > support a little.
> >
> > Hopefully this gets answered in my explanations below.
> >
> > >
> > > > } else if (connector->funcs->atomic_set_property) {
> > > > return connector->f
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_suspend: Exercise S0 (aka s2idle)
Chris Wilson writes:
> Exercise the first level of suspend, S0. This is basically the same as
> our runtime-suspend, we need to put the device to sleep but otherwise
> it is left powered up.
>
> Ideally, we would measure the energy consumption in this state.
This and the others.
Reviewed-by: Mika Kuoppala
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=111909
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_exec_suspend.c | 16
> tests/intel-ci/fast-feedback.testlist | 1 +
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/tests/i915/gem_exec_suspend.c b/tests/i915/gem_exec_suspend.c
> index e43a16e9e..f25f1a86b 100644
> --- a/tests/i915/gem_exec_suspend.c
> +++ b/tests/i915/gem_exec_suspend.c
> @@ -32,10 +32,11 @@
> #include "igt_dummyload.h"
>
> #define NOSLEEP 0
> -#define SUSPEND_DEVICES 1
> -#define SUSPEND 2
> -#define HIBERNATE_DEVICES 3
> -#define HIBERNATE 4
> +#define IDLE 1
> +#define SUSPEND_DEVICES 2
> +#define SUSPEND 3
> +#define HIBERNATE_DEVICES 4
> +#define HIBERNATE 5
> #define mode(x) ((x) & 0xff)
>
> #define LOCAL_I915_EXEC_BSD_SHIFT (13)
> @@ -195,6 +196,11 @@ static void run_test(int fd, unsigned engine, unsigned
> flags)
> case NOSLEEP:
> break;
>
> + case IDLE:
> + igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE,
> + SUSPEND_TEST_NONE);
> + break;
> +
> case SUSPEND_DEVICES:
> igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
> SUSPEND_TEST_DEVICES);
> @@ -255,6 +261,8 @@ igt_main
>
> igt_subtest("basic")
> run_test(fd, ALL_ENGINES, NOSLEEP);
> + igt_subtest("basic-S0")
> + run_test(fd, ALL_ENGINES, IDLE);
> igt_subtest("basic-S3-devices")
> run_test(fd, ALL_ENGINES, SUSPEND_DEVICES);
> igt_subtest("basic-S3")
> diff --git a/tests/intel-ci/fast-feedback.testlist
> b/tests/intel-ci/fast-feedback.testlist
> index e78e7fd0c..2553a68c3 100644
> --- a/tests/intel-ci/fast-feedback.testlist
> +++ b/tests/intel-ci/fast-feedback.testlist
> @@ -56,6 +56,7 @@ igt@gem_exec_reloc@basic-write-read-active
> igt@gem_exec_reloc@basic-softpin
> igt@gem_exec_store@basic-all
> igt@gem_exec_suspend@basic
> +igt@gem_exec_suspend@basic-s0
> igt@gem_exec_suspend@basic-s3
> igt@gem_exec_suspend@basic-s4-devices
> igt@gem_flink_basic@bad-flink
> --
> 2.23.0
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
On Mon, Oct 21, 2019 at 06:28:18AM +, Lin, Wayne wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Monday, October 14, 2019 10:42 PM
> > To: Lin, Wayne
> > Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
> >
> > On Mon, Oct 14, 2019 at 09:27:07AM +, Lin, Wayne wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Ville Syrjala
> > > > Sent: Friday, October 4, 2019 10:19 PM
> > > > To: dri-de...@lists.freedesktop.org
> > > > Cc: intel-gfx@lists.freedesktop.org; Lin, Wayne
> > > > Subject: [PATCH 4/4] drm/edid: Prep for HDMI VIC aspect ratio (WIP)
> > > >
> > > > From: Ville Syrjälä
> > > >
> > > > I think this should provide most of necessary logic for adding
> > > > aspecr ratios to the HDMI 4k modes.
> > > >
> > > > Cc: Wayne Lin
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/drm_edid.c | 37
> > > > +++--
> > > > 1 file changed, 31 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > > > index
> > > > c7f9f7ca75a2..c76814edc784 100644
> > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > @@ -3210,6 +3210,11 @@ static enum hdmi_picture_aspect
> > > > drm_get_cea_aspect_ratio(const u8 video_code)
> > > > return edid_cea_modes[video_code].picture_aspect_ratio;
> > > > }
> > > >
> > > > +static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8
> > > > +video_code) {
> > > > + return edid_4k_modes[video_code].picture_aspect_ratio;
> > > > +}
> > > > +
> > >
> > > There are no picture_aspect_ratio attributes defined for modes in
> > > edid_4k_modes[] now. Should add on those definitions.
> > >
> > > > /*
> > > > * Calculate the alternate clock for HDMI modes (those from the
> > > > HDMI vendor
> > > > * specific block).
> > > > @@ -3236,6 +3241,9 @@ static u8
> > > > drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode
> > *to_
> > > > if (!to_match->clock)
> > > > return 0;
> > > >
> > > > + if (to_match->picture_aspect_ratio)
> > > > + match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
> > > > +
> > > > for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
> > > > const struct drm_display_mode *hdmi_mode =
> > &edid_4k_modes[vic];
> > > > unsigned int clock1, clock2;
> > > > @@ -3271,6 +3279,9 @@ static u8 drm_match_hdmi_mode(const struct
> > > > drm_display_mode *to_match)
> > > > if (!to_match->clock)
> > > > return 0;
> > > >
> > > > + if (to_match->picture_aspect_ratio)
> > > > + match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
> > > > +
> > > > for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
> > > > const struct drm_display_mode *hdmi_mode =
> > &edid_4k_modes[vic];
> > > > unsigned int clock1, clock2;
> > >
> > > Current code in drm_match_hdmi_mdoe() &
> > > drm_match_hdmi_mode_clock_tolerance()
> > > use hdmi_mode_alternate_clock() to find alternate clocks.
> > > In hdmi_mode_alternate_clock(), it adds an exception for VIC 4 mode
> > > (4096x2160@24) due to there is no alternate clock defined for that
> > > mode in HDMI1.4b. But HDMI2.0 adds 23.98Hz for that mode. Maybe we
> > should also revise that part.
> >
> > I'm tempted to just remove that exception. I have a hard time imagining it
> > causing serious problems.
>
> Thanks for your time.
> I've run smoke test and CTS to verify these patches (with adding the aspect
> ratio
> attribute to edid_4k_modes[] and removing the exception for23.98Hz). So far it
> looks good on my environment. Is there any further modification should be done
> on these patches?
Can't think of anything right now. I pushed the other three patches
already, so I guess now you could pull this last patch into your
patch set and repost the lot?
>
> >
> > >
> > > > @@ -5218,6 +5229,7 @@
> > > > drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe
> > > > *frame,
> > > > const struct drm_display_mode
> > > > *mode) {
> > > > enum hdmi_picture_aspect picture_aspect;
> > > > + u8 vic, hdmi_vic;
> > > > int err;
> > > >
> > > > if (!frame || !mode)
> > > > @@ -5230,7 +5242,8 @@
> > > > drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe
> > > > *frame,
> > > > if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > > > frame->pixel_repeat = 1;
> > > >
> > > > - frame->video_code = drm_mode_cea_vic(connector, mode);
> > > > + vic = drm_mode_cea_vic(connector, mode);
> > > > + hdmi_vic = drm_mode_hdmi_vic(connector, mode);
> > > >
> > > > frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
> > > >
> > > > @@ -5244,11 +5257,15 @@
