[Intel-gfx] [PATCH v8 04/10] drm/i915/dsb: Indexed register write function for DSB.
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code comment. (Shashank)
v4: cosmetic changes done. (Shashank)
v5: reset ins_start_offset. (Jani)
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 67
drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
2 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index f94cd6dc98b6..0b5119135d4d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -12,8 +12,10 @@
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_BYTE_EN0xF
#define DSB_BYTE_EN_SHIFT 20
+#define DSB_REG_VALUE_MASK 0xf
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
+ }
+
+ /*
+* For example the buffer will look like below for 3 dwords for auto
+* increment register:
+* ++
+* | size = 3 | offset &| value1 | value2 | value3 | zero |
+* | | opcode |||||
+* ++
+* + + +++++
+* 0 4 812 16 20 24
+* Byte
+*
+* As every instruction is 8 byte aligned the index of dsb instruction
+* will start always from even number while dealing with u32 array. If
+* we are writing odd no of dwords, Zeros will be added in the end for
+* padding.
+*/
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ dsb->ins_start_offset = dsb->free_pos;
+
+ /* Update the size. */
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 0686d67b34d5..d6ced4422814 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -30,11 +30,19 @@ struct intel_dsb {
* and help in calculating tail of command buffer.
*/
int free_pos;
+
+ /*
+* ins_start_offset will help to store start address
+* of the dsb instuction of auto-increment register.
+*/
+ u32 ins_start_offset;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val);
#
[Intel-gfx] [PATCH v8 03/10] drm/i915/dsb: single register write function for DSB.
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
v4: macro of indexed-write is moved. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 29
drivers/gpu/drm/i915/display/intel_dsb.h | 9
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2ed277670f15..f94cd6dc98b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,12 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -76,5 +82,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(&dsb->vma, 0);
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 2c0f60c5f66c..0686d67b34d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -22,10 +24,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating tail of command buffer.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.22.0
___
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[Intel-gfx] [PATCH v8 00/10] DSB enablement.
Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. v3: As per review comments from Chris and Jani, - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) - Simplified and optimized code few places. (Chris) - Called dsb-api directly in callsites instead going via I915_WRITE. (Jani) v4: Addressed review commnets from Shashank. v5: Addressed review commnets from Shashank and Jani. v6: Addressed review commnets from Shashank. v7: Addressed review commnets from Shashank and Jani. v8: Addressed review commnets from Shashank and Jani. Animesh Manna (10): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. drm/i915/dsb: Documentation for DSB. Documentation/gpu/i915.rst| 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c| 63 ++-- .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 336 ++ drivers/gpu/drm/i915/display/intel_dsb.h | 49 +++ drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 455 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 01/10] drm/i915/dsb: feature flag added for display state buffer.
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4faec2f94e19..84b9b138d7ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1863,6 +1863,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d4c288860aed..0cdc2465534b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.22.0
___
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[Intel-gfx] [PATCH v8 02/10] drm/i915/dsb: DSB context creation.
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
v4: for simplification and based on current usage added single dsb
object in intel_crtc. (Shashank)
v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
v6:
- refcount machanism added.
- Used atomic_add_return and atomic_dec_and_test instead of
atomic_inc and atomic_dec. (Jani)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 80 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 116 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..49c902b00484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1033,6 +1033,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index ..2ed277670f15
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_dsb *dsb = &crtc->dsb;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_DSB(i915))
+ return dsb;
+
+ if (atomic_add_return(1, &dsb->refcount) != 1)
+ return dsb;
+
+ dsb->id = DSB1;
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Gem object creation failed\n");
+ goto err;
+ }
+
+ mutex_lock(&i915->drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ i915_vma_unpin_and_release(&vma, 0);
+ dsb->cmd_buf = NULL;
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!HAS_DSB(i915))
+ return;
+
+ if (WARN_ON(atomic_read(&dsb->refcount) == 0))
+ return;
+
+ if (atomic_dec_and_test(&dsb->refcount)) {
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_gem_object_unpin_map(dsb->vma->obj);
+ i915_vma_unpin_and_release(&dsb->vma, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
+ dsb->cmd_buf = NULL;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/d
[Intel-gfx] [PATCH v8 05/10] drm/i915/dsb: Check DSB engine status.
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0b5119135d4d..bcc4d16c3b4b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,15 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xf
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e3a6178aff4..01ed543c28e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11687,4 +11687,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.22.0
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[Intel-gfx] [PATCH v8 10/10] drm/i915/dsb: Documentation for DSB.
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
drivers/gpu/drm/i915/display/intel_dsb.c | 68
2 files changed, 77 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index e249ea7b0ec7..465779670fd4 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 000291c100a0..768841a8883b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,23 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
@@ -66,6 +83,17 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb
*dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate DSB context and return a DSB instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function provides handle of a DSB instance, for the further DSB
+ * operations.
+ *
+ * Returns: address of Intel_dsb instance requested for.
+ * Failure: Returns the same DSB instance, but without a command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -116,6 +144,14 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function destroys the DSB context allocated by a dsb_get(), by
+ * unpinning and releasing the VMA object associated with it.
+ */
+
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -138,6 +174,19 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+/**
+ * intel_dsb_indexed_reg_write() -Write to the DSB context for auto
+ * increment register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB for auto-increment register. During command buffer overflow,
+ * a warning is thrown and rest all erroneous condition register programming
+ * is done through mmio write.
+ */
+
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
@@ -202,6 +251,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the DSB context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning is thrown
+ * and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -224,6 +285,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
--
2.22.0
__
[Intel-gfx] [PATCH v8 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
v4: reset ins_start_offset after commit. (Jani)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 43
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index e00ec196133e..000291c100a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -223,3 +223,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(&dsb->cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index d6ced4422814..dca4e632dd3c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -44,5 +44,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca90f66393c..f37428e99a5a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11691,6 +11691,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index bcc4d16c3b4b..e00ec196133e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 01ed543c28e6..5ca90f66393c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11692,6 +11692,7 @@ enum skl_power_gate {
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
#endif /* _I915_REG_H_ */
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v8 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in future
based on need.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
v3:
- modified the code as per single dsb instance per crtc. (Shashank)
- Added dsb get/put call in platform specific load_lut hook. (Jani)
- removed dsb pointer from dev_priv. (Jani)
v4: simplified code by dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 63 ++
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308dc136c..40af3fe2c3c9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,10 +625,15 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
+
+ intel_dsb_put(dsb);
}
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -787,22 +793,23 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_put(dsb);
}
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
u32 i;
@@ -813,26 +820,29 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* Superfine segment has 9 entries, corresponding to values
* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
*/
- I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = &lut[i];
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
+
[Intel-gfx] [PATCH v8 09/10] drm/i915/dsb: Enable DSB for gen12.
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fe6941c8fc99..c2faa679658c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info
intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drm/i915: Add TigerLake bandwidth checking
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec 53998.
v2: Start using same icl_get_bw_info function to avoid
code duplication. Moved mpagesize to memory info
related structure as it is now dependent on memory type.
Fixed qi.t_bl field assignment.
v3: Removed mpagesize as unused. Duplicate code and redundant blankline
fixed.
v4: Changed ordering of IS_GEN checks as agreed. Minor commit
message fixes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 26 +
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 688858ebe4d0..cd58e47ab7b2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -56,7 +56,10 @@ static int icl_pcode_read_mem_global_info(struct
drm_i915_private *dev_priv,
qi->num_channels = (val & 0xf0) >> 4;
qi->num_points = (val & 0xf00) >> 8;
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+ if (IS_GEN(dev_priv, 12))
+ qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
+ else if (IS_GEN(dev_priv, 11))
+ qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
return 0;
}
@@ -132,20 +135,25 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info
*qi)
}
struct intel_sa_info {
- u8 deburst, mpagesize, deprogbwlimit, displayrtids;
+ u16 displayrtids;
+ u8 deburst, deprogbwlimit;
};
static const struct intel_sa_info icl_sa_info = {
.deburst = 8,
- .mpagesize = 16,
.deprogbwlimit = 25, /* GB/s */
.displayrtids = 128,
};
-static int icl_get_bw_info(struct drm_i915_private *dev_priv)
+static const struct intel_sa_info tgl_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 34, /* GB/s */
+ .displayrtids = 256,
+};
+
+static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
- const struct intel_sa_info *sa = &icl_sa_info;
bool is_y_tile = true; /* assume y tile may be used */
int num_channels;
int deinterleave;
@@ -233,14 +241,16 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
- icl_get_bw_info(dev_priv);
+ if (IS_GEN(dev_priv, 12))
+ icl_get_bw_info(dev_priv, &tgl_sa_info);
+ else if (IS_GEN(dev_priv, 11))
+ icl_get_bw_info(dev_priv, &icl_sa_info);
}
static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
int num_planes)
{
- if (IS_GEN(dev_priv, 11))
+ if (INTEL_GEN(dev_priv) >= 11)
/*
* FIXME with SAGV disabled maybe we can assume
* point 1 will always be used? Seems to match
--
2.17.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSB enablement. (rev8)
== Series Details == Series: DSB enablement. (rev8) URL : https://patchwork.freedesktop.org/series/63013/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7569987ee218 drm/i915/dsb: feature flag added for display state buffer. 9c2ddae7699f drm/i915/dsb: DSB context creation. -:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #63: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 134 lines checked f1208dc5b909 drm/i915/dsb: single register write function for DSB. 5cc47cfee7c4 drm/i915/dsb: Indexed register write function for DSB. d3aa91f40ae4 drm/i915/dsb: Check DSB engine status. 847b4adf2d7b drm/i915/dsb: functions to enable/disable DSB engine. 79792563fbb5 drm/i915/dsb: function to trigger workload execution of DSB. e04bec9f5bf7 drm/i915/dsb: Enable gamma lut programming using DSB. 85a7068c2087 drm/i915/dsb: Enable DSB for gen12. c7ffef8e464c drm/i915/dsb: Documentation for DSB. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSB enablement. (rev8)
== Series Details == Series: DSB enablement. (rev8) URL : https://patchwork.freedesktop.org/series/63013/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.6.0 Commit: drm/i915/dsb: feature flag added for display state buffer. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for DSB enablement. (rev8)
== Series Details ==
Series: DSB enablement. (rev8)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14468
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/
Known issues
Here are the changes found in Patchwork_14468 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_gtt:
- fi-glk-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103359] /
[k.org#198133])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-glk-dsi/igt@i915_selftest@live_gtt.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/fi-glk-dsi/igt@i915_selftest@live_gtt.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
* igt@vgem_basic@unload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1
similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@vgem_ba...@unload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/fi-icl-u3/igt@vgem_ba...@unload.html
Possible fixes
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][7] ([fdo#109483]) -> [PASS][8] +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10] +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@prime_v...@basic-busy-default.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/fi-icl-u3/igt@prime_v...@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (53 -> 46)
--
Additional (1): fi-pnv-d510
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-
* CI: CI-20190529 -> None
* Linux: CI_DRM_6925 -> Patchwork_14468
CI-20190529: 20190529
CI_DRM_6925: ccd2c9cb3fd35f9654cdf6743bdecfb489fba70a @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5193: 924e5c59dbb82938e743efd6b0812eeb5760b70d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14468: c7ffef8e464c5fb5d9d96f49062f8e68fb2db4bc @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c7ffef8e464c drm/i915/dsb: Documentation for DSB.
85a7068c2087 drm/i915/dsb: Enable DSB for gen12.
e04bec9f5bf7 drm/i915/dsb: Enable gamma lut programming using DSB.
79792563fbb5 drm/i915/dsb: function to trigger workload execution of DSB.
847b4adf2d7b drm/i915/dsb: functions to enable/disable DSB engine.
d3aa91f40ae4 drm/i915/dsb: Check DSB engine status.
5cc47cfee7c4 drm/i915/dsb: Indexed register write function for DSB.
f1208dc5b909 drm/i915/dsb: single register write function for DSB.
9c2ddae7699f drm/i915/dsb: DSB context creation.
7569987ee218 drm/i915/dsb: feature flag added for display state buffer.
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14468/index.html
___
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[Intel-gfx] [PATCH] Revert "drm/i915/tgl: Implement Wa_1406941453"
Our sanitychecks indicate that while this register is context
saved/restore, the HW does not preserve this bit within the register --
it likely doesn't exist, or one of those mythical bits that the
architects insist does something despite all appearances to the
contrary.
For reference, SAMPLER_MODE is already in i915_reg.h as
GEN10_SAMPLER_MODE and is being setup in icl_ctx_workarounds_init() as
opposed to the chosen location here of rcs_engine_wa_init).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111754
Fixes: 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453")
Testcase: igt/i915_selftest/live_workarounds
Signed-off-by: Chris Wilson
Cc: Lucas De Marchi
Cc: Stuart Summers
Cc: Radhakrishna Sripada
Cc: Jani Nikula
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ---
drivers/gpu/drm/i915/i915_reg.h | 3 ---
2 files changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 25ae60846398..ba65e5018978 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1260,13 +1260,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_GEN(i915, 12)) {
- /* Wa_1406941453:tgl */
- wa_masked_en(wal,
-SAMPLER_MODE,
-SAMPLER_ENABLE_SMALL_PL);
- }
-
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e3a6178aff4..f8f52ae6cc6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8965,9 +8965,6 @@ enum {
#define GEN9_DG_MIRROR_FIX_ENABLE(1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
-#define SAMPLER_MODE _MMIO(0xe18c)
-#define SAMPLER_ENABLE_SMALL_PL (1 << 15)
-
#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
#define FLOW_CONTROL_ENABLE (1 << 15)
#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE(1 << 8)
--
2.23.0
___
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Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Suspend pre-parser across GTT invalidations
Chris Wilson writes:
> Before we execute a batch, we must first issue any and all TLB
> invalidations so that batch picks up the new page table entries.
> Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> invalidate pipe-control and allowing the loading of the batch buffer
> before we have setup its page table (and so it loads the wrong page and
> executes indefinitely).
>
> The igt_cs_tlb indicates that this issue can only be observed on rcs,
> even though the preparser is common to all engines. Alternatively, we
> could do TLB shootdown via mmio on updating the GTT.
>
> By inserting the pre-parser disable inside EMIT_INVALIDATE, we will also
> accidentally fixup execution that writes into subsequent batches, such
> as gem_exec_whisper and even relocations performed on the GPU. We should
> be careful not to allow this disable to become baked into the uABI!
>
> Testcase: igt/i915_selftests/live_gtt/igt_cs_tlb
> Signed-off-by: Chris Wilson
> Cc: Daniele Ceraolo Spurio
> Cc: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 75 -
> 1 file changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index a99166a2d2eb..60b7b163c3d0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2807,6 +2807,79 @@ static int gen11_emit_flush_render(struct i915_request
> *request,
> return 0;
> }
>
> +static u32 preparser_disable(bool state)
> +{
> + return MI_ARB_CHECK | 1 << 8 | state;
> +}
Descriptive enough, so no need to define the mask.
Acked-by: Mika Kuoppala
> +
> +static int gen12_emit_flush_render(struct i915_request *request,
> +u32 mode)
> +{
> + struct intel_engine_cs *engine = request->engine;
> + const u32 scratch_addr =
> + intel_gt_scratch_offset(engine->gt,
> + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> +
> + if (mode & EMIT_FLUSH) {
> + u32 flags = 0;
> + u32 *cs;
> +
> + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> + flags |= PIPE_CONTROL_FLUSH_ENABLE;
> +
> + flags |= PIPE_CONTROL_QW_WRITE;
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + flags |= PIPE_CONTROL_CS_STALL;
> +
> + cs = intel_ring_begin(request, 6);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
> + intel_ring_advance(request, cs);
> + }
> +
> + if (mode & EMIT_INVALIDATE) {
> + u32 flags = 0;
> + u32 *cs;
> +
> + flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_TLB_INVALIDATE;
> + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> +
> + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> + flags |= PIPE_CONTROL_QW_WRITE;
> +
> + flags |= PIPE_CONTROL_CS_STALL;
> +
> + cs = intel_ring_begin(request, 8);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + /*
> + * Prevent the pre-parser from skipping past the TLB
> + * invalidate and loading a stale page for the batch
> + * buffer / request payload.
> + */
> + *cs++ = preparser_disable(true);
> +
> + cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
> +
> + *cs++ = preparser_disable(false);
> + intel_ring_advance(request, cs);
> + }
> +
> + return 0;
> +}
> +
> /*
> * Reserve space for 2 NOOPs at the end of each request to be
> * used as a workaround for not being allowed to do lite
> @@ -3072,7 +3145,7 @@ static void rcs_submission_override(struct
> intel_engine_cs *engine)
> {
> switch (INTEL_GEN(engine->i915)) {
> case 12:
> - engine->emit_flush = gen11_emit_flush_render;
> + engine->emit_flush = gen12_emit_flush_render;
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> break;
> case 11:
> --
> 2.23.0
___
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[Intel-gfx] [RFC PATCH V2 0/6] mdev based hardware virtio offloading support
Hi all: There are hardware that can do virtio datapath offloading while having its own control path. This path tries to implement a mdev based unified API to support using kernel virtio driver to drive those devices. This is done by introducing a new mdev transport for virtio (virtio_mdev) and register itself as a new kind of mdev driver. Then it provides a unified way for kernel virtio driver to talk with mdev device implementation. Though the series only contain kernel driver support, the goal is to make the transport generic enough to support userspace drivers. This means vhost-mdev[1] could be built on top as well by resuing the transport. A sample driver is also implemented which simulate a virito-net loopback ethernet device on top of vringh + workqueue. This could be used as a reference implementation for real hardware driver. Consider mdev framework only support VFIO device and driver right now, this series also extend it to support other types. This is done through introducing class id to the device and pairing it with id_talbe claimed by the driver. On top, this seris also decouple device specific parents ops out of the common ones. Pktgen test was done with virito-net + mvnet loop back device. Please review. Changes from V1: - rename device id to class id - add docs for class id and device specific ops (device_ops) - split device_ops into seperate headers - drop the mdev_set_dma_ops() - use device_ops to implement the transport API, then it's not a part of UAPI any more - use GFP_ATOMIC in mvnet sample device and other tweaks - set_vring_base/get_vring_base support for mvnet device Jason Wang (6): mdev: class id support mdev: introduce device specific ops mdev: introduce virtio device and its device ops virtio: introudce a mdev based transport vringh: fix copy direction of vringh_iov_push_kern() docs: Sample driver to demonstrate how to implement virtio-mdev framework .../driver-api/vfio-mediated-device.rst | 11 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 17 +- drivers/s390/cio/vfio_ccw_ops.c | 17 +- drivers/s390/crypto/vfio_ap_ops.c | 14 +- drivers/vfio/mdev/Kconfig | 7 + drivers/vfio/mdev/Makefile| 1 + drivers/vfio/mdev/mdev_core.c | 21 +- drivers/vfio/mdev/mdev_driver.c | 14 + drivers/vfio/mdev/mdev_private.h | 1 + drivers/vfio/mdev/vfio_mdev.c | 37 +- drivers/vfio/mdev/virtio_mdev.c | 418 +++ drivers/vhost/vringh.c| 8 +- include/linux/mdev.h | 46 +- include/linux/mod_devicetable.h | 8 + include/linux/vfio_mdev.h | 50 ++ include/linux/virtio_mdev.h | 141 samples/Kconfig | 7 + samples/vfio-mdev/Makefile| 1 + samples/vfio-mdev/mbochs.c| 19 +- samples/vfio-mdev/mdpy.c | 19 +- samples/vfio-mdev/mtty.c | 17 +- samples/vfio-mdev/mvnet.c | 688 ++ 22 files changed, 1473 insertions(+), 89 deletions(-) create mode 100644 drivers/vfio/mdev/virtio_mdev.c create mode 100644 include/linux/vfio_mdev.h create mode 100644 include/linux/virtio_mdev.h create mode 100644 samples/vfio-mdev/mvnet.c -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC PATCH V2 1/6] mdev: class id support
Mdev bus only support vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
one example is virtio-mdev[1] driver. This means we need to add device
class id support in bus match method to pair the mdev device and mdev
driver correctly.
So this patch add id_table to mdev_driver and id for mdev parent, and
implement the match method for mdev bus.
Signed-off-by: Jason Wang
---
Documentation/driver-api/vfio-mediated-device.rst | 7 +--
drivers/gpu/drm/i915/gvt/kvmgt.c | 2 +-
drivers/s390/cio/vfio_ccw_ops.c | 2 +-
drivers/s390/crypto/vfio_ap_ops.c | 3 ++-
drivers/vfio/mdev/mdev_core.c | 14 --
drivers/vfio/mdev/mdev_driver.c | 14 ++
drivers/vfio/mdev/mdev_private.h | 1 +
drivers/vfio/mdev/vfio_mdev.c | 6 ++
include/linux/mdev.h | 6 +-
include/linux/mod_devicetable.h | 8
samples/vfio-mdev/mbochs.c| 2 +-
samples/vfio-mdev/mdpy.c | 2 +-
samples/vfio-mdev/mtty.c | 2 +-
13 files changed, 58 insertions(+), 11 deletions(-)
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 25eb7d5b834b..0d6e85155b9b 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -102,12 +102,14 @@ structure to represent a mediated device's driver::
* @probe: called when new device created
* @remove: called when device removed
* @driver: device driver structure
+ * @id_table: the ids serviced by this driver.
*/
struct mdev_driver {
const char *name;
int (*probe) (struct device *dev);
void (*remove) (struct device *dev);
struct device_driverdriver;
+const struct mdev_class_id *id_table;
};
A mediated bus driver for mdev should use this structure in the function calls
@@ -116,7 +118,7 @@ to register and unregister itself with the core driver:
* Register::
extern int mdev_register_driver(struct mdev_driver *drv,
- struct module *owner);
+ struct module *owner);
* Unregister::
@@ -163,7 +165,8 @@ A driver should use the mdev_parent_ops structure in the
function call to
register itself with the mdev core driver::
extern int mdev_register_device(struct device *dev,
-const struct mdev_parent_ops *ops);
+const struct mdev_parent_ops *ops,
+ u8 class_id);
However, the mdev_parent_ops structure is not required in the function call
that a driver should use to unregister itself with the mdev core driver::
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 23aa3e50cbf8..19d51a35f019 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1625,7 +1625,7 @@ static int kvmgt_host_init(struct device *dev, void *gvt,
const void *ops)
return -EFAULT;
intel_vgpu_ops.supported_type_groups = kvm_vgpu_type_groups;
- return mdev_register_device(dev, &intel_vgpu_ops);
+ return mdev_register_vfio_device(dev, &intel_vgpu_ops);
}
static void kvmgt_host_exit(struct device *dev)
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index 5eb61116ca6f..f87d9409e290 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -578,7 +578,7 @@ static const struct mdev_parent_ops vfio_ccw_mdev_ops = {
int vfio_ccw_mdev_reg(struct subchannel *sch)
{
- return mdev_register_device(&sch->dev, &vfio_ccw_mdev_ops);
+ return mdev_register_vfio_device(&sch->dev, &vfio_ccw_mdev_ops);
}
void vfio_ccw_mdev_unreg(struct subchannel *sch)
diff --git a/drivers/s390/crypto/vfio_ap_ops.c
b/drivers/s390/crypto/vfio_ap_ops.c
index 0604b49a4d32..eacbde3c7a97 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -1295,7 +1295,8 @@ int vfio_ap_mdev_register(void)
{
atomic_set(&matrix_dev->available_instances, MAX_ZDEV_ENTRIES_EXT);
- return mdev_register_device(&matrix_dev->device, &vfio_ap_matrix_ops);
+ return mdev_register_vfio_device(&matrix_dev->device,
+&vfio_ap_matrix_ops);
}
void vfio_ap_mdev_unregister(void)
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index b558d4cfd082..a02c256a3514 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -135,11 +135,14 @@ static int mdev_device_remove_cb(struct device *dev, void
[Intel-gfx] [RFC PATCH V2 2/6] mdev: introduce device specific ops
Currently, except for the crate and remove. The rest fields of
mdev_parent_ops is just designed for vfio-mdev driver and may not help
for kernel mdev driver. So follow the device id support by previous
patch, this patch introduces device specific ops which points to
device specific ops (e.g vfio ops). This allows the future drivers
like virtio-mdev to implement its own device specific ops.
Signed-off-by: Jason Wang
---
.../driver-api/vfio-mediated-device.rst | 4 +-
drivers/gpu/drm/i915/gvt/kvmgt.c | 15 +++---
drivers/s390/cio/vfio_ccw_ops.c | 15 --
drivers/s390/crypto/vfio_ap_ops.c | 11 ++--
drivers/vfio/mdev/vfio_mdev.c | 31 +++-
include/linux/mdev.h | 39 ++-
include/linux/vfio_mdev.h | 50 +++
samples/vfio-mdev/mbochs.c| 17 ---
samples/vfio-mdev/mdpy.c | 17 ---
samples/vfio-mdev/mtty.c | 15 --
10 files changed, 136 insertions(+), 78 deletions(-)
create mode 100644 include/linux/vfio_mdev.h
diff --git a/Documentation/driver-api/vfio-mediated-device.rst
b/Documentation/driver-api/vfio-mediated-device.rst
index 0d6e85155b9b..f48454bb60b9 100644
--- a/Documentation/driver-api/vfio-mediated-device.rst
+++ b/Documentation/driver-api/vfio-mediated-device.rst
@@ -152,7 +152,9 @@ callbacks per mdev parent device, per mdev type, or any
other categorization.
Vendor drivers are expected to be fully asynchronous in this respect or
provide their own internal resource protection.)
-The callbacks in the mdev_parent_ops structure are as follows:
+The device specific callbacks are referred through device_ops pointer
+in mdev_parent_ops. For vfio-mdev device, its callbacks in device_ops
+are as follows:
* open: open callback of mediated device
* close: close callback of mediated device
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 19d51a35f019..8ea86b1e69f1 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#include
#include
@@ -1600,20 +1601,22 @@ static const struct attribute_group
*intel_vgpu_groups[] = {
NULL,
};
-static struct mdev_parent_ops intel_vgpu_ops = {
- .mdev_attr_groups = intel_vgpu_groups,
- .create = intel_vgpu_create,
- .remove = intel_vgpu_remove,
-
+static struct vfio_mdev_parent_ops intel_vfio_vgpu_ops = {
.open = intel_vgpu_open,
.release= intel_vgpu_release,
-
.read = intel_vgpu_read,
.write = intel_vgpu_write,
.mmap = intel_vgpu_mmap,
.ioctl = intel_vgpu_ioctl,
};
+static struct mdev_parent_ops intel_vgpu_ops = {
+ .mdev_attr_groups = intel_vgpu_groups,
+ .create = intel_vgpu_create,
+ .remove = intel_vgpu_remove,
+ .device_ops = &intel_vfio_vgpu_ops,
+};
+
static int kvmgt_host_init(struct device *dev, void *gvt, const void *ops)
{
struct attribute **kvm_type_attrs;
diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c
index f87d9409e290..e01247cc61b8 100644
--- a/drivers/s390/cio/vfio_ccw_ops.c
+++ b/drivers/s390/cio/vfio_ccw_ops.c
@@ -12,6 +12,7 @@
#include
#include
+#include
#include
#include
@@ -564,11 +565,7 @@ static ssize_t vfio_ccw_mdev_ioctl(struct mdev_device
*mdev,
}
}
-static const struct mdev_parent_ops vfio_ccw_mdev_ops = {
- .owner = THIS_MODULE,
- .supported_type_groups = mdev_type_groups,
- .create = vfio_ccw_mdev_create,
- .remove = vfio_ccw_mdev_remove,
+static const struct vfio_mdev_parent_ops vfio_mdev_ops = {
.open = vfio_ccw_mdev_open,
.release= vfio_ccw_mdev_release,
.read = vfio_ccw_mdev_read,
@@ -576,6 +573,14 @@ static const struct mdev_parent_ops vfio_ccw_mdev_ops = {
.ioctl = vfio_ccw_mdev_ioctl,
};
+static const struct mdev_parent_ops vfio_ccw_mdev_ops = {
+ .owner = THIS_MODULE,
+ .supported_type_groups = mdev_type_groups,
+ .create = vfio_ccw_mdev_create,
+ .remove = vfio_ccw_mdev_remove,
+ .device_ops = &vfio_mdev_ops,
+};
+
int vfio_ccw_mdev_reg(struct subchannel *sch)
{
return mdev_register_vfio_device(&sch->dev, &vfio_ccw_mdev_ops);
diff --git a/drivers/s390/crypto/vfio_ap_ops.c
b/drivers/s390/crypto/vfio_ap_ops.c
index eacbde3c7a97..685ec5946c7b 100644
--- a/drivers/s390/crypto/vfio_ap_ops.c
+++ b/drivers/s390/crypto/vfio_ap_ops.c
@@ -16,6 +16,7 @@
#incl
[Intel-gfx] [RFC PATCH V2 3/6] mdev: introduce virtio device and its device ops
This patch implements basic support for mdev driver that support
virtio transport for kernel driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c | 7 ++
include/linux/mdev.h | 3 +
include/linux/virtio_mdev.h | 141 ++
3 files changed, 151 insertions(+)
create mode 100644 include/linux/virtio_mdev.h
diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c
index a02c256a3514..6d39caf96222 100644
--- a/drivers/vfio/mdev/mdev_core.c
+++ b/drivers/vfio/mdev/mdev_core.c
@@ -220,6 +220,13 @@ int mdev_register_vfio_device(struct device *dev,
}
EXPORT_SYMBOL(mdev_register_vfio_device);
+int mdev_register_virtio_device(struct device *dev,
+ const struct mdev_parent_ops *ops)
+{
+ return mdev_register_device(dev, ops, MDEV_ID_VIRTIO);
+}
+EXPORT_SYMBOL(mdev_register_virtio_device);
+
/*
* mdev_unregister_device : Unregister a parent device
* @dev: device structure representing parent device.
diff --git a/include/linux/mdev.h b/include/linux/mdev.h
index 99fdfd74433d..780150c61493 100644
--- a/include/linux/mdev.h
+++ b/include/linux/mdev.h
@@ -109,6 +109,8 @@ extern struct bus_type mdev_bus_type;
int mdev_register_vfio_device(struct device *dev,
const struct mdev_parent_ops *ops);
+int mdev_register_virtio_device(struct device *dev,
+ const struct mdev_parent_ops *ops);
void mdev_unregister_device(struct device *dev);
int mdev_register_driver(struct mdev_driver *drv, struct module *owner);
@@ -119,5 +121,6 @@ struct device *mdev_dev(struct mdev_device *mdev);
struct mdev_device *mdev_from_dev(struct device *dev);
#define MDEV_ID_VFIO 1 /* VFIO device */
+#define MDEV_ID_VIRTIO 2 /* Virtio Device */
#endif /* MDEV_H */
diff --git a/include/linux/virtio_mdev.h b/include/linux/virtio_mdev.h
new file mode 100644
index ..003314a76f5b
--- /dev/null
+++ b/include/linux/virtio_mdev.h
@@ -0,0 +1,141 @@
+/*
+ * Virtio mediated device driver
+ *
+ * Copyright 2019, Red Hat Corp.
+ * Author: Jason Wang
+ */
+#ifndef _LINUX_VIRTIO_MDEV_H
+#define _LINUX_VIRTIO_MDEV_H
+
+#include
+#include
+
+#define VIRTIO_MDEV_DEVICE_API_STRING "virtio-mdev"
+
+struct virtio_mdev_callback {
+ irqreturn_t (*callback)(void *);
+ void *private;
+};
+
+/**
+ * struct vfio_mdev_parent_ops - Structure to be registered for each
+ * parent device to register the device to virtio-mdev module.
+ *
+ * @set_vq_address:Set the address of virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @desc_area: address of desc area
+ * @driver_area: address of driver area
+ * @device_area: address of device area
+ * Returns integer: success (0) or error (< 0)
+ * @set_vq_num:Set the size of virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @num: the size of virtqueue
+ * @kick_vq: Kick the virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @set_vq_cb: Set the interrut calback function for a
virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @cb: virtio-mdev interrupt callback structure
+ * @set_vq_ready: Set ready status for a virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @ready: ready (true) not ready(false)
+ * @get_vq_ready: Get ready status for a virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * Returns boolean: ready (true) or not (false)
+ * @set_vq_state: Set the state for a virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * @state: virtqueue state (last_avail_idx)
+ * Returns integer: success (0) or error (< 0)
+ * @get_vq_state: Get the state for a virtqueue
+ * @mdev: mediated device
+ * @idx: virtqueue index
+ * Returns virtqueue state (last_avail_idx)
+ * @get_vq_align: Get the virtqueue align requirement
+ * for the device
+ * @mdev: mediated device
+ * Returns virtqueue algin requirement
+ * @get_features: Get virtio features supporte
[Intel-gfx] [RFC PATCH V2 4/6] virtio: introudce a mdev based transport
This path introduces a new mdev transport for virtio. This is used to
use kernel virtio driver to drive the mediated device that is capable
of populating virtqueue directly.
A new virtio-mdev driver will be registered to the mdev bus, when a
new virtio-mdev device is probed, it will register the device with
mdev based config ops. This means, unlike the exist hardware
transport, this is a software transport between mdev driver and mdev
device. The transport was implemented through device specific ops
which is a part of mdev_parent_ops now.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/Kconfig | 7 +
drivers/vfio/mdev/Makefile | 1 +
drivers/vfio/mdev/virtio_mdev.c | 418
3 files changed, 426 insertions(+)
create mode 100644 drivers/vfio/mdev/virtio_mdev.c
diff --git a/drivers/vfio/mdev/Kconfig b/drivers/vfio/mdev/Kconfig
index 5da27f2100f9..c488c31fc137 100644
--- a/drivers/vfio/mdev/Kconfig
+++ b/drivers/vfio/mdev/Kconfig
@@ -16,3 +16,10 @@ config VFIO_MDEV_DEVICE
default n
help
VFIO based driver for Mediated devices.
+
+config VIRTIO_MDEV_DEVICE
+ tristate "VIRTIO driver for Mediated devices"
+ depends on VFIO_MDEV && VIRTIO
+ default n
+ help
+ VIRTIO based driver for Mediated devices.
diff --git a/drivers/vfio/mdev/Makefile b/drivers/vfio/mdev/Makefile
index 101516fdf375..99d31e29c23e 100644
--- a/drivers/vfio/mdev/Makefile
+++ b/drivers/vfio/mdev/Makefile
@@ -4,3 +4,4 @@ mdev-y := mdev_core.o mdev_sysfs.o mdev_driver.o
obj-$(CONFIG_VFIO_MDEV) += mdev.o
obj-$(CONFIG_VFIO_MDEV_DEVICE) += vfio_mdev.o
+obj-$(CONFIG_VIRTIO_MDEV_DEVICE) += virtio_mdev.o
diff --git a/drivers/vfio/mdev/virtio_mdev.c b/drivers/vfio/mdev/virtio_mdev.c
new file mode 100644
index ..cee73fe392bb
--- /dev/null
+++ b/drivers/vfio/mdev/virtio_mdev.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * VIRTIO based driver for Mediated device
+ *
+ * Copyright (c) 2019, Red Hat. All rights reserved.
+ * Author: Jason Wang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mdev_private.h"
+
+#define DRIVER_VERSION "0.1"
+#define DRIVER_AUTHOR "Red Hat Corporation"
+#define DRIVER_DESC "VIRTIO based driver for Mediated device"
+
+#define to_virtio_mdev_device(dev) \
+ container_of(dev, struct virtio_mdev_device, vdev)
+
+struct virtio_mdev_device {
+ struct virtio_device vdev;
+ struct mdev_device *mdev;
+ unsigned long version;
+
+ struct virtqueue **vqs;
+ spinlock_t lock;
+};
+
+struct virtio_mdev_vq_info {
+ /* the actual virtqueue */
+ struct virtqueue *vq;
+
+ /* the list node for the virtqueues list */
+ struct list_head node;
+};
+
+static struct mdev_device *vm_get_mdev(struct virtio_device *vdev)
+{
+ struct virtio_mdev_device *vm_dev = to_virtio_mdev_device(vdev);
+ struct mdev_device *mdev = vm_dev->mdev;
+
+ return mdev;
+}
+
+static const struct virtio_mdev_parent_ops
+*mdev_get_parent_ops(struct mdev_device *mdev)
+{
+ struct mdev_parent *parent = mdev->parent;
+
+ return parent->ops->device_ops;
+}
+
+static void virtio_mdev_get(struct virtio_device *vdev, unsigned offset,
+ void *buf, unsigned len)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ ops->get_config(mdev, offset, buf, len);
+}
+
+static void virtio_mdev_set(struct virtio_device *vdev, unsigned offset,
+ const void *buf, unsigned len)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ ops->set_config(mdev, offset, buf, len);
+}
+
+static u32 virtio_mdev_generation(struct virtio_device *vdev)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ return ops->get_generation(mdev);
+}
+
+static u8 virtio_mdev_get_status(struct virtio_device *vdev)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ return ops->get_status(mdev);
+}
+
+static void virtio_mdev_set_status(struct virtio_device *vdev, u8 status)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ return ops->set_status(mdev, status);
+}
+
+static void virtio_mdev_reset(struct virtio_device *vdev)
+{
+ struct mdev_device *mdev = vm_get_mdev(vdev);
+ const struct virtio_mdev_parent_ops *ops = mdev_get_parent_ops(mdev);
+
+ return ops->set_status(mdev, 0);
+}
+
+static bool virtio_mdev_notify(struct virtqueue *vq)
+{
+ struct mdev_device *md
[Intel-gfx] [RFC PATCH V2 6/6] docs: Sample driver to demonstrate how to implement virtio-mdev framework
This sample driver creates mdev device that simulate virtio net device
over virtio mdev transport. The device is implemented through vringh
and workqueue. A device specific dma ops is to make sure HVA is used
directly as the IOVA. This should be sufficient for kernel virtio
driver to work.
No more work for userspace VFIO based vhost-mdev driver to work. E.g
through notifier, it will be addressed in the future.
Signed-off-by: Jason Wang
---
samples/Kconfig| 7 +
samples/vfio-mdev/Makefile | 1 +
samples/vfio-mdev/mvnet.c | 688 +
3 files changed, 696 insertions(+)
create mode 100644 samples/vfio-mdev/mvnet.c
diff --git a/samples/Kconfig b/samples/Kconfig
index c8dacb4dda80..a1a1ca2c00b7 100644
--- a/samples/Kconfig
+++ b/samples/Kconfig
@@ -131,6 +131,13 @@ config SAMPLE_VFIO_MDEV_MDPY
mediated device. It is a simple framebuffer and supports
the region display interface (VFIO_GFX_PLANE_TYPE_REGION).
+config SAMPLE_VIRTIO_MDEV_NET
+tristate "Build virtio mdev net example mediated device sample code --
loadable modules only"
+ depends on VIRTIO_MDEV_DEVICE && VHOST_RING && m
+ help
+ Build a networking sample device for use as a virtio
+ mediated device.
+
config SAMPLE_VFIO_MDEV_MDPY_FB
tristate "Build VFIO mdpy example guest fbdev driver -- loadable module
only"
depends on FB && m
diff --git a/samples/vfio-mdev/Makefile b/samples/vfio-mdev/Makefile
index 10d179c4fdeb..f34af90ed0a0 100644
--- a/samples/vfio-mdev/Makefile
+++ b/samples/vfio-mdev/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_SAMPLE_VFIO_MDEV_MTTY) += mtty.o
obj-$(CONFIG_SAMPLE_VFIO_MDEV_MDPY) += mdpy.o
obj-$(CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB) += mdpy-fb.o
obj-$(CONFIG_SAMPLE_VFIO_MDEV_MBOCHS) += mbochs.o
+obj-$(CONFIG_SAMPLE_VIRTIO_MDEV_NET) += mvnet.o
diff --git a/samples/vfio-mdev/mvnet.c b/samples/vfio-mdev/mvnet.c
new file mode 100644
index ..e1036e753c76
--- /dev/null
+++ b/samples/vfio-mdev/mvnet.c
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Mediated virtual virtio-net device driver.
+ *
+ * Copyright (c) 2019, Red Hat Inc. All rights reserved.
+ * Author: Jason Wang
+ *
+ * Sample driver that creates mdev device that simulates ethernet loopback
+ * device.
+ *
+ * Usage:
+ *
+ * # modprobe virtio_mdev
+ * # modprobe mvnet
+ * # cd /sys/devices/virtual/mvnet/mvnet/mdev_supported_types/mvnet-
+ * # echo "83b8f4f2-509f-382f-3c1e-e6bfe0fa1001" > ./create
+ * # cd devices/83b8f4f2-509f-382f-3c1e-e6bfe0fa1001
+ * # ls -d virtio0
+ * virtio0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERSION_STRING "0.1"
+#define DRIVER_AUTHOR "Red Hat Corporation"
+
+#define MVNET_CLASS_NAME "mvnet"
+#define MVNET_NAME "mvnet"
+
+/*
+ * Global Structures
+ */
+
+static struct mvnet_dev {
+ struct class*vd_class;
+ struct idr vd_idr;
+ struct device dev;
+} mvnet_dev;
+
+struct mvnet_virtqueue {
+ struct vringh vring;
+ struct vringh_kiov iov;
+ unsigned short head;
+ bool ready;
+ u64 desc_addr;
+ u64 device_addr;
+ u64 driver_addr;
+ u32 num;
+ void *private;
+ irqreturn_t (*cb)(void *);
+};
+
+#define MVNET_QUEUE_ALIGN PAGE_SIZE
+#define MVNET_QUEUE_MAX 256
+#define MVNET_DEVICE_ID 0x1
+#define MVNET_VENDOR_ID 0
+
+u64 mvnet_features = (1ULL << VIRTIO_F_ANY_LAYOUT) |
+(1ULL << VIRTIO_F_VERSION_1) |
+(1ULL << VIRTIO_F_IOMMU_PLATFORM) ;
+
+/* State of each mdev device */
+struct mvnet_state {
+ struct mvnet_virtqueue vqs[2];
+ struct work_struct work;
+ spinlock_t lock;
+ struct mdev_device *mdev;
+ struct virtio_net_config config;
+ void *buffer;
+ u32 status;
+ u32 generation;
+ u64 features;
+ struct list_head next;
+};
+
+static struct mutex mdev_list_lock;
+static struct list_head mdev_devices_list;
+
+static void mvnet_queue_ready(struct mvnet_state *mvnet, unsigned idx)
+{
+ struct mvnet_virtqueue *vq = &mvnet->vqs[idx];
+ int ret;
+
+ ret = vringh_init_kern(&vq->vring, mvnet_features, MVNET_QUEUE_MAX,
+ false, (struct vring_desc *)vq->desc_addr,
+ (struct vring_avail *)vq->driver_addr,
+ (struct vring_used *)vq->device_addr);
+}
+
+static void mvnet_vq_reset(struct mvnet_virtqueue *vq)
+{
+ vq->ready = 0;
+ vq->desc_addr = 0;
+ vq->driver_addr = 0;
+ vq->device_addr = 0;
+ vq->cb = NULL;
+ vq->private = NULL;
+ vringh_init_kern(&vq->vring, mvnet_features, MVNET_QUEUE_MAX,
+ false, 0, 0, 0);
+}
+
+static void mvnet_reset(struct mvnet_state *mvn
[Intel-gfx] [RFC PATCH V2 5/6] vringh: fix copy direction of vringh_iov_push_kern()
We want to copy from iov to buf, so the direction was wrong.
Signed-off-by: Jason Wang
---
drivers/vhost/vringh.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/vhost/vringh.c b/drivers/vhost/vringh.c
index 08ad0d1f0476..a0a2d74967ef 100644
--- a/drivers/vhost/vringh.c
+++ b/drivers/vhost/vringh.c
@@ -852,6 +852,12 @@ static inline int xfer_kern(void *src, void *dst, size_t
len)
return 0;
}
+static inline int kern_xfer(void *dst, void *src, size_t len)
+{
+ memcpy(dst, src, len);
+ return 0;
+}
+
/**
* vringh_init_kern - initialize a vringh for a kernelspace vring.
* @vrh: the vringh to initialize.
@@ -958,7 +964,7 @@ EXPORT_SYMBOL(vringh_iov_pull_kern);
ssize_t vringh_iov_push_kern(struct vringh_kiov *wiov,
const void *src, size_t len)
{
- return vringh_iov_xfer(wiov, (void *)src, len, xfer_kern);
+ return vringh_iov_xfer(wiov, (void *)src, len, kern_xfer);
}
EXPORT_SYMBOL(vringh_iov_push_kern);
--
2.19.1
___
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[Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from overtaking each other on preemption
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its master,
creating an implicit dependency -- if we ignore that implicit dependency
and allow the bonded request to run on the same engine and before its
master, we will cause a GPU hang.
We can prevent this inversion by restricting which engines we allow
ourselves to jump to upon preemption, i.e. baking in the arrangement
established at first execution. (We should also consider capturing the
implicit dependency using i915_sched_add_dependency(), but first we need
to think about the constraints that requires on the execution/retirement
ordering.)
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
References: ee1136908e9b ("drm/i915/execlists: Virtual engine bonding")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a99166a2d2eb..7920649e4d87 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3755,18 +3755,21 @@ static void
virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
{
struct virtual_engine *ve = to_virtual_engine(rq->engine);
+ intel_engine_mask_t allowed, exec;
struct ve_bond *bond;
bond = virtual_find_bond(ve, to_request(signal)->engine);
- if (bond) {
- intel_engine_mask_t old, new, cmp;
+ if (!bond)
+ return;
- cmp = READ_ONCE(rq->execution_mask);
- do {
- old = cmp;
- new = cmp & bond->sibling_mask;
- } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old);
- }
+ /* Restrict the bonded request to run on only the slaved engines */
+ allowed = bond->sibling_mask & ~to_request(signal)->engine->mask;
+ exec = READ_ONCE(rq->execution_mask);
+ while (!try_cmpxchg(&rq->execution_mask, &exec, exec & allowed))
+ ;
+
+ /* Prevent the master from being re-run on the slaved engines */
+ to_request(signal)->execution_mask &= ~allowed;
}
struct intel_context *
--
2.23.0
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[Intel-gfx] [PATCH] drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
When audio power domain is suspended, the display driver must
save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
systems. The initial value of the register is set by BIOS and
is read by driver during the audio component init sequence.
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 17 +++--
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index aac089c79ceb..54638d99e021 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -852,10 +852,17 @@ static unsigned long
i915_audio_component_get_power(struct device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
- /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
- if (dev_priv->audio_power_refcount++ == 0)
+ if (dev_priv->audio_power_refcount++ == 0) {
+ if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
+ I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
+ DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n",
+ dev_priv->audio_freq_cntrl);
+ }
+
+ /* Force CDCLK to 2*BCLK as long as we need audio powered. */
if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, true);
+ }
return ret;
}
@@ -1116,6 +1123,12 @@ static void i915_audio_component_init(struct
drm_i915_private *dev_priv)
return;
}
+ if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
+ dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
+ DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n",
+ dev_priv->audio_freq_cntrl);
+ }
+
dev_priv->audio_component_registered = true;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4faec2f94e19..5bb19f1c0ef4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1540,6 +1540,7 @@ struct drm_i915_private {
*/
struct mutex av_mutex;
int audio_power_refcount;
+ u32 audio_freq_cntrl;
struct {
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..dff077aa4cc6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9119,6 +9119,8 @@ enum {
#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
#define SKL_AUD_CODEC_WAKE_SIGNAL(1 << 15)
+#define AUD_FREQ_CNTRL _MMIO(0x65900)
+
/*
* HSW - ICL power wells
*
--
2.18.0
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[Intel-gfx] [PATCH v4] drm/i915: Add TigerLake bandwidth checking
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec 53998.
v2: Start using same icl_get_bw_info function to avoid
code duplication. Moved mpagesize to memory info
related structure as it is now dependent on memory type.
Fixed qi.t_bl field assignment.
v3: Removed mpagesize as unused. Duplicate code and redundant blankline
fixed.
v4: Changed ordering of IS_GEN checks as agreed. Minor commit
message fixes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111600
Reviewed-by: James Ausmus
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 26 +
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 688858ebe4d0..cd58e47ab7b2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -56,7 +56,10 @@ static int icl_pcode_read_mem_global_info(struct
drm_i915_private *dev_priv,
qi->num_channels = (val & 0xf0) >> 4;
qi->num_points = (val & 0xf00) >> 8;
- qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+ if (IS_GEN(dev_priv, 12))
+ qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
+ else if (IS_GEN(dev_priv, 11))
+ qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
return 0;
}
@@ -132,20 +135,25 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info
*qi)
}
struct intel_sa_info {
- u8 deburst, mpagesize, deprogbwlimit, displayrtids;
+ u16 displayrtids;
+ u8 deburst, deprogbwlimit;
};
static const struct intel_sa_info icl_sa_info = {
.deburst = 8,
- .mpagesize = 16,
.deprogbwlimit = 25, /* GB/s */
.displayrtids = 128,
};
-static int icl_get_bw_info(struct drm_i915_private *dev_priv)
+static const struct intel_sa_info tgl_sa_info = {
+ .deburst = 16,
+ .deprogbwlimit = 34, /* GB/s */
+ .displayrtids = 256,
+};
+
+static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct
intel_sa_info *sa)
{
struct intel_qgv_info qi = {};
- const struct intel_sa_info *sa = &icl_sa_info;
bool is_y_tile = true; /* assume y tile may be used */
int num_channels;
int deinterleave;
@@ -233,14 +241,16 @@ static unsigned int icl_max_bw(struct drm_i915_private
*dev_priv,
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
{
- if (IS_GEN(dev_priv, 11))
- icl_get_bw_info(dev_priv);
+ if (IS_GEN(dev_priv, 12))
+ icl_get_bw_info(dev_priv, &tgl_sa_info);
+ else if (IS_GEN(dev_priv, 11))
+ icl_get_bw_info(dev_priv, &icl_sa_info);
}
static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
int num_planes)
{
- if (IS_GEN(dev_priv, 11))
+ if (INTEL_GEN(dev_priv) >= 11)
/*
* FIXME with SAGV disabled maybe we can assume
* point 1 will always be used? Seems to match
--
2.17.1
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[Intel-gfx] [PATCH v1] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 57 +++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index cd58e47ab7b2..f65e4aec6ecc 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -90,6 +90,25 @@ static int icl_pcode_read_qgv_point_info(struct
drm_i915_private *dev_priv,
return 0;
}
+static int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ 0xff, points_mask,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -354,7 +373,9 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 points_mask = 0;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -398,10 +419,40 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
+ ret = icl_get_qgv_points(dev_priv, &qi);
+ if (ret < 0) {
+ goto fallback;
+ }
+
+ for (i = 0; i < qi.num_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ if (max_data_rate < data_rate) {
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
restricted\n",
+ i, max_data_rate, data_rate);
+ points_mask |= 1 << i;
+ } else
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
unrestricted\n",
+ i, max_data_rate, data_rate);
+ }
+
+ if (points_mask >= ((1 << qi.num_points) - 1)) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
+ return -EINVAL;
+ }
+
+ ret = icl_pcode_restrict_qgv_points(dev_priv, points_mask);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Could not restrict required gqv points(%d)\n",
ret);
+ goto fallback;
+ }
+
+ return 0;
+
+fallback:
+ max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+
if (data_rate > max_data_rate) {
DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s
(%d active planes)\n",
data_rate, max_data_rate, num_active_planes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..df26d15dcbb5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8845,6 +8845,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) <<
16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
--
2.17.1
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Re: [Intel-gfx] [PATCH v2 1/3] drm/i915: Mark i915_request.timeline as a volatile, rcu pointer
On 19/09/2019 18:49, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-19 18:11:14)
On 19/09/2019 14:26, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-19 14:02:19)
On 19/09/2019 12:19, Chris Wilson wrote:
+static struct intel_timeline *get_timeline(struct i915_request *rq)
+{
+ struct intel_timeline *tl;
+
+ /*
+ * Even though we are holding the engine->active.lock here, there
+ * is no control over the submission queue per-se and we are
+ * inspecting the active state at a random point in time, with an
+ * unknown queue. Play safe and make sure the timeline remains valid.
+ * (Only being used for pretty printing, one extra kref shouldn't
+ * cause a camel stampede!)
+ */
+ rcu_read_lock();
+ tl = rcu_dereference(rq->timeline);
+ if (!kref_get_unless_zero(&tl->kref))
+ tl = NULL;
+ rcu_read_unlock();
How can it be NULL under the active lock? Isn't that the same assertion
from i915_timeline_get_active.
Not NULL, but retired. The difference is that during submission we know
that this request's context/timeline must be currently pinned until
a subsequent request (containing the idle-barriers) is submitted. The
danger I worry about here is that subsequent idle request may be already
submitted and since the queued requests may *already* have been retired,
the timeline may be unpinned and indeed dropped it's last reference.
But here it is under the engine->active.lock with interrupts disabled
and the requests are fetched from execlists ports. Timeline is not
guaranteed to be kept alive under these conditions? intel_context
reference will be held until process_csb schedules it out so I'd expect
timeline and hwsp to be there. But I could be lost in the new scheme of
things.
I felt it was prudent to only rely on the active pin. You are right in
that we have a context reference if it is in active, and that context
holds a reference to the timeline. But... engine->active.lock is not
the lock that guards rq->timeline, so I feel uneasy on extending
i915_request_active_timeline() too far. Outside of the submission
pathway, inside a pretty printer, it feels safer (whatever changes may
come we don't have to worry about it) to not assume anything and just
use the failsafe rcu_dereference() + kref.
Well okay, I can accept that in the overall situation.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Suspend pre-parser across GTT invalidations (rev2)
== Series Details == Series: drm/i915/tgl: Suspend pre-parser across GTT invalidations (rev2) URL : https://patchwork.freedesktop.org/series/66703/ State : success == Summary == CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14461_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14461_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vecs0-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl10/igt@gem_ctx_isolat...@vecs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-skl8/igt@gem_ctx_isolat...@vecs0-s3.html * igt@gem_ctx_switch@legacy-vebox: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb8/igt@gem_ctx_swi...@legacy-vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-iclb1/igt@gem_ctx_swi...@legacy-vebox.html * igt@gem_exec_nop@basic-sequential: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#110255]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb1/igt@gem_exec_...@basic-sequential.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-iclb7/igt@gem_exec_...@basic-sequential.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb8/igt@gem_exec_sched...@preempt-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-iclb1/igt@gem_exec_sched...@preempt-bsd.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl1/igt@kms_cursor_...@pipe-c-cursor-128x128-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-apl4/igt@kms_cursor_...@pipe-c-cursor-128x128-offscreen.html * igt@kms_flip@flip-vs-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#109507]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl1/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-skl1/igt@kms_f...@flip-vs-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [PASS][15] -> [INCOMPLETE][16] ([fdo#105411]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-snb7/igt@kms_f...@flip-vs-suspend-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-snb1/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-ts-check: - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#100368]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-glk9/igt@kms_f...@plain-flip-ts-check.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-glk1/igt@kms_f...@plain-flip-ts-check.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb7/igt@kms_frontbuffer_track...@fbc-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-iclb8/igt@kms_frontbuffer_track...@fbc-suspend.html - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl6/igt@kms_frontbuffer_track...@fbc-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-apl1/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108] / [fdo#106978]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl3/igt@kms_frontbuffer_track...@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14461/shard-skl5/igt@kms_frontbuffer_track...@psr-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl1/igt@kms_plane_alpha_bl...@pipe
Re: [Intel-gfx] [PATCH v8 04/10] drm/i915/dsb: Indexed register write function for DSB.
On Fri, 20 Sep 2019, Animesh Manna wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by using ALIGN(). (Chris)
> v3: ascii table added as code comment. (Shashank)
> v4: cosmetic changes done. (Shashank)
> v5: reset ins_start_offset. (Jani)
>
> Cc: Shashank Sharma
> Cc: Imre Deak
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Reviewed-by: Shashank Sharma
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 67
> drivers/gpu/drm/i915/display/intel_dsb.h | 8 +++
> 2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index f94cd6dc98b6..0b5119135d4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -12,8 +12,10 @@
> /* DSB opcodes. */
> #define DSB_OPCODE_SHIFT 24
> #define DSB_OPCODE_MMIO_WRITE0x1
> +#define DSB_OPCODE_INDEXED_WRITE 0x9
> #define DSB_BYTE_EN 0xF
> #define DSB_BYTE_EN_SHIFT20
> +#define DSB_REG_VALUE_MASK 0xf
>
> struct intel_dsb *
> intel_dsb_get(struct intel_crtc *crtc)
> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
> mutex_unlock(&i915->drm.struct_mutex);
> dsb->cmd_buf = NULL;
> dsb->free_pos = 0;
> + dsb->ins_start_offset = 0;
This is not enough to address the sequence I described. Sure, we're not
hitting the issue now, but it's not a benign thing.
So imagine you do:
intel_dsb_get()
intel_dsb_indexed_reg_write(dsb, FOO, 0);
intel_dsb_indexed_reg_write(dsb, FOO, 0);
intel_dsb_reg_write(dsb, BAR, 0);
intel_dsb_indexed_reg_write(dsb, FOO, 0);
intel_dsb_commit()
intel_dsb_put()
Do you see what happens in the last indexed write? It looks at the
*first* indexed writes for whether this is a continuation, updating the
size there, ignoring the fact that there's something else in between.
BR,
Jani.
> }
> }
>
> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> + u32 val)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 *buf = dsb->cmd_buf;
> + u32 reg_val;
> +
> + if (!buf) {
> + I915_WRITE(reg, val);
> + return;
> + }
> +
> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
> + DRM_DEBUG_KMS("DSB buffer overflow\n");
> + return;
> + }
> +
> + /*
> + * For example the buffer will look like below for 3 dwords for auto
> + * increment register:
> + * ++
> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
> + * | | opcode |||||
> + * ++
> + * + + +++++
> + * 0 4 812 16 20 24
> + * Byte
> + *
> + * As every instruction is 8 byte aligned the index of dsb instruction
> + * will start always from even number while dealing with u32 array. If
> + * we are writing odd no of dwords, Zeros will be added in the end for
> + * padding.
> + */
> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
> + if (reg_val != i915_mmio_reg_offset(reg)) {
> + /* Every instruction should be 8 byte aligned. */
> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +
> + dsb->ins_start_offset = dsb->free_pos;
> +
> + /* Update the size. */
> + buf[dsb->free_pos++] = 1;
> +
> + /* Update the opcode and reg. */
> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
> + DSB_OPCODE_SHIFT) |
> + i915_mmio_reg_offset(reg);
> +
> + /* Update the value. */
> + buf[dsb->free_pos++] = val;
> + } else {
> + /* Update the new value. */
> + buf[dsb->free_pos++] = val;
> +
> + /* Update the size. */
> + buf[dsb->ins_start_offset]++;
> + }
> +
> + /* if number of data words is odd, then the last dword should be 0.*/
> + if (dsb->free_pos & 0x1)
> + buf[dsb->free_pos] = 0;
> +}
> +
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> {
> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 0686d67b34d
Re: [Intel-gfx] [PATCH] drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
On Fri, 20 Sep 2019, Kai Vehmanen wrote:
> When audio power domain is suspended, the display driver must
> save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
> systems. The initial value of the register is set by BIOS and
> is read by driver during the audio component init sequence.
>
> Cc: Jani Nikula
> Cc: Imre Deak
> Signed-off-by: Kai Vehmanen
Thanks for the patch, let's wait for the CI results.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 17 +++--
> drivers/gpu/drm/i915/i915_drv.h| 1 +
> drivers/gpu/drm/i915/i915_reg.h| 2 ++
> 3 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index aac089c79ceb..54638d99e021 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -852,10 +852,17 @@ static unsigned long
> i915_audio_component_get_power(struct device *kdev)
>
> ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
>
> - /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
> - if (dev_priv->audio_power_refcount++ == 0)
> + if (dev_priv->audio_power_refcount++ == 0) {
> + if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
> + I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl);
> + DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n",
> + dev_priv->audio_freq_cntrl);
> + }
> +
> + /* Force CDCLK to 2*BCLK as long as we need audio powered. */
> if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> glk_force_audio_cdclk(dev_priv, true);
> + }
>
> return ret;
> }
> @@ -1116,6 +1123,12 @@ static void i915_audio_component_init(struct
> drm_i915_private *dev_priv)
> return;
> }
>
> + if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) {
> + dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL);
> + DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n",
> + dev_priv->audio_freq_cntrl);
> + }
> +
> dev_priv->audio_component_registered = true;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4faec2f94e19..5bb19f1c0ef4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1540,6 +1540,7 @@ struct drm_i915_private {
>*/
> struct mutex av_mutex;
> int audio_power_refcount;
> + u32 audio_freq_cntrl;
>
> struct {
> struct mutex mutex;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ecebc82f..dff077aa4cc6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9119,6 +9119,8 @@ enum {
> #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
> #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
>
> +#define AUD_FREQ_CNTRL _MMIO(0x65900)
> +
> /*
> * HSW - ICL power wells
> *
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Suspend pre-parser across GTT invalidations
Quoting Mika Kuoppala (2019-09-20 09:14:36)
> Chris Wilson writes:
>
> > Before we execute a batch, we must first issue any and all TLB
> > invalidations so that batch picks up the new page table entries.
> > Tigerlake's preparser is weakening our post-sync CS_STALL inside the
> > invalidate pipe-control and allowing the loading of the batch buffer
> > before we have setup its page table (and so it loads the wrong page and
> > executes indefinitely).
> >
> > The igt_cs_tlb indicates that this issue can only be observed on rcs,
> > even though the preparser is common to all engines. Alternatively, we
> > could do TLB shootdown via mmio on updating the GTT.
> >
> > By inserting the pre-parser disable inside EMIT_INVALIDATE, we will also
> > accidentally fixup execution that writes into subsequent batches, such
> > as gem_exec_whisper and even relocations performed on the GPU. We should
> > be careful not to allow this disable to become baked into the uABI!
> >
> > Testcase: igt/i915_selftests/live_gtt/igt_cs_tlb
> > Signed-off-by: Chris Wilson
> > Cc: Daniele Ceraolo Spurio
> > Cc: Mika Kuoppala
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 75 -
> > 1 file changed, 74 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index a99166a2d2eb..60b7b163c3d0 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -2807,6 +2807,79 @@ static int gen11_emit_flush_render(struct
> > i915_request *request,
> > return 0;
> > }
> >
> > +static u32 preparser_disable(bool state)
> > +{
> > + return MI_ARB_CHECK | 1 << 8 | state;
> > +}
>
> Descriptive enough, so no need to define the mask.
>
> Acked-by: Mika Kuoppala
I touched up the note on the impact of disabling the optimisation on the
uABI. This clears up the remaining errors in BAT on rcs0, so just the
vexing multi-engine problem to solve.
-Chris
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[Intel-gfx] ✗ Fi.CI.IGT: failure for adding gamma state checker for icl+ platforms (rev3)
== Series Details == Series: adding gamma state checker for icl+ platforms (rev3) URL : https://patchwork.freedesktop.org/series/66811/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14463_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14463_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14463_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14463_full: ### IGT changes ### Possible regressions * igt@kms_color@pipe-a-degamma: - shard-iclb: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb6/igt@kms_co...@pipe-a-degamma.html * igt@kms_color@pipe-b-gamma: - shard-iclb: [PASS][2] -> [DMESG-WARN][3] +10 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb6/igt@kms_co...@pipe-b-gamma.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb7/igt@kms_co...@pipe-b-gamma.html Warnings * igt@kms_color@pipe-b-ctm-0-25: - shard-iclb: [FAIL][4] ([fdo#110920]) -> [DMESG-FAIL][5] +5 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@kms_co...@pipe-b-ctm-0-25.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb8/igt@kms_co...@pipe-b-ctm-0-25.html * igt@kms_color@pipe-c-degamma: - shard-iclb: [FAIL][6] ([fdo#104782]) -> [DMESG-FAIL][7] +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_co...@pipe-c-degamma.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb8/igt@kms_co...@pipe-c-degamma.html Known issues Here are the changes found in Patchwork_14463_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl2/igt@gem_ctx_isolat...@rcs0-s3.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl1/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110841]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_ctx_shared@q-smoketest-bsd2: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +6 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@gem_ctx_sha...@q-smoketest-bsd2.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb5/igt@gem_ctx_sha...@q-smoketest-bsd2.html * igt@gem_exec_schedule@preempt-queue-contexts-bsd: - shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@gem_exec_sched...@preempt-queue-contexts-bsd.html * igt@i915_selftest@live_execlists: - shard-skl: [PASS][16] -> [DMESG-FAIL][17] ([fdo#08]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl10/igt@i915_selftest@live_execlists.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl8/igt@i915_selftest@live_execlists.html * igt@kms_flip@flip-vs-expired-vblank: - shard-glk: [PASS][18] -> [FAIL][19] ([fdo#105363]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-glk6/igt@kms_f...@flip-vs-expired-vblank.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-glk4/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][22] -> [DMESG-WARN][23] ([fdo#108566]) +2 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-t
[Intel-gfx] [PATCH] drm/i915/perf: Fix use of kernel-doc format in structure members.
Insert structure members names into their descriptions to follow
kernel-doc format.
Reviewed-by: Chris Wilson
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d1949a78c44..dc6c9f52d3a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1225,7 +1225,7 @@ struct i915_perf_stream {
struct i915_oa_config *oa_config;
/**
-* The OA context specific information.
+* @pinned_ctx: The OA context specific information.
*/
struct intel_context *pinned_ctx;
u32 specific_ctx_id;
@@ -1239,7 +1239,7 @@ struct i915_perf_stream {
int period_exponent;
/**
-* State of the OA buffer.
+* @oa_buffer: State of the OA buffer.
*/
struct {
struct i915_vma *vma;
@@ -1250,7 +1250,7 @@ struct i915_perf_stream {
int size_exponent;
/**
-* Locks reads and writes to all head/tail state
+* @ptr_lock: Locks reads and writes to all head/tail state
*
* Consider: the head and tail pointer state needs to be read
* consistently from a hrtimer callback (atomic context) and
@@ -1272,8 +1272,8 @@ struct i915_perf_stream {
spinlock_t ptr_lock;
/**
-* One 'aging' tail pointer and one 'aged' tail pointer ready to
-* used for reading.
+* @tails: One 'aging' tail pointer and one 'aged' tail pointer
+* ready to used for reading.
*
* Initial values of 0x are invalid and imply that an
* update is required (and should be ignored by an attempted
@@ -1284,21 +1284,23 @@ struct i915_perf_stream {
} tails[2];
/**
-* Index for the aged tail ready to read() data up to.
+* @aged_tail_idx: Index for the aged tail ready to read() data
+* up to.
*/
unsigned int aged_tail_idx;
/**
-* A monotonic timestamp for when the current aging tail pointer
-* was read; used to determine when it is old enough to trust.
+* @aging_timestamp: A monotonic timestamp for when the current
+* aging tail pointer was read; used to determine when it is old
+* enough to trust.
*/
u64 aging_timestamp;
/**
-* Although we can always read back the head pointer register,
-* we prefer to avoid trusting the HW state, just to avoid any
-* risk that some hardware condition could * somehow bump the
-* head pointer unpredictably and cause us to forward the wrong
+* @head: Although we can always read back the head pointer
+* register, we prefer to avoid trusting the HW state, just to
+* avoid any risk that some hardware condition could somehow
bump
+* the head pointer unpredictably and cause us to forward the
wrong
* OA buffer data to userspace.
*/
u32 head;
--
2.19.0
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Re: [Intel-gfx] [PATCH] drm/i915/perf: Fix use of kernel-doc format in structure members.
On 20/09/2019 12:47, Anna Karas wrote:
Insert structure members names into their descriptions to follow
kernel-doc format.
Reviewed-by: Chris Wilson
Signed-off-by: Anna Karas
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d1949a78c44..dc6c9f52d3a5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1225,7 +1225,7 @@ struct i915_perf_stream {
struct i915_oa_config *oa_config;
/**
-* The OA context specific information.
+* @pinned_ctx: The OA context specific information.
*/
struct intel_context *pinned_ctx;
u32 specific_ctx_id;
@@ -1239,7 +1239,7 @@ struct i915_perf_stream {
int period_exponent;
/**
-* State of the OA buffer.
+* @oa_buffer: State of the OA buffer.
*/
struct {
struct i915_vma *vma;
@@ -1250,7 +1250,7 @@ struct i915_perf_stream {
int size_exponent;
/**
-* Locks reads and writes to all head/tail state
+* @ptr_lock: Locks reads and writes to all head/tail state
*
* Consider: the head and tail pointer state needs to be read
* consistently from a hrtimer callback (atomic context) and
@@ -1272,8 +1272,8 @@ struct i915_perf_stream {
spinlock_t ptr_lock;
/**
-* One 'aging' tail pointer and one 'aged' tail pointer ready to
-* used for reading.
+* @tails: One 'aging' tail pointer and one 'aged' tail pointer
+* ready to used for reading.
*
* Initial values of 0x are invalid and imply that an
* update is required (and should be ignored by an attempted
@@ -1284,21 +1284,23 @@ struct i915_perf_stream {
} tails[2];
/**
-* Index for the aged tail ready to read() data up to.
+* @aged_tail_idx: Index for the aged tail ready to read() data
+* up to.
*/
unsigned int aged_tail_idx;
/**
-* A monotonic timestamp for when the current aging tail pointer
-* was read; used to determine when it is old enough to trust.
+* @aging_timestamp: A monotonic timestamp for when the current
+* aging tail pointer was read; used to determine when it is old
+* enough to trust.
*/
u64 aging_timestamp;
/**
-* Although we can always read back the head pointer register,
-* we prefer to avoid trusting the HW state, just to avoid any
-* risk that some hardware condition could * somehow bump the
-* head pointer unpredictably and cause us to forward the wrong
+* @head: Although we can always read back the head pointer
+* register, we prefer to avoid trusting the HW state, just to
+* avoid any risk that some hardware condition could somehow
bump
+* the head pointer unpredictably and cause us to forward the
wrong
* OA buffer data to userspace.
*/
u32 head;
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Re: [Intel-gfx] [PATCH] Revert "drm/i915/tgl: Implement Wa_1406941453"
Quoting Chris Wilson (2019-09-20 09:12:54)
> Our sanitychecks indicate that while this register is context
> saved/restore, the HW does not preserve this bit within the register --
> it likely doesn't exist, or one of those mythical bits that the
> architects insist does something despite all appearances to the
> contrary.
>
> For reference, SAMPLER_MODE is already in i915_reg.h as
> GEN10_SAMPLER_MODE and is being setup in icl_ctx_workarounds_init() as
> opposed to the chosen location here of rcs_engine_wa_init).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111754
> Fixes: 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453")
> Testcase: igt/i915_selftest/live_workarounds
> Signed-off-by: Chris Wilson
> Cc: Lucas De Marchi
> Cc: Stuart Summers
> Cc: Radhakrishna Sripada
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
Lucas said last night in response to the CI error,
"Yes, let's revert until I find out what I should really do."
which I am going to take as a preemptive ack :)
Acked-by: Lucas De Marchi
-Chris
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Re: [Intel-gfx] [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
On Thu, 19 Sep 2019, Swati Sharma wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> Following are the main changes done in this patch:
> 1. gamma_enable checks made specific to platform func()
>since icl doeesn't support that and enable gamma through mode
> 2. lut[0] and lut[8] enteries should be same superfine and coarse;
>superfine and fine segments respectively, checked twice-no harm
> 3. Removed temporary lut
> 4. Coarse segment interpolated gamma values loop start from 2
>instead of 0, since actual h/w values started getting overrided.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 216
> +++--
> drivers/gpu/drm/i915/i915_reg.h| 7 +
> 2 files changed, 208 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 765482d..ad548ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
> *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_gamma_precision(crtc_state);
> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>
[Intel-gfx] [PATCH v2] drm/i915: Restrict qgv points which don't have enough bandwidth.
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_bw.c | 58 +++--
drivers/gpu/drm/i915/i915_reg.h | 3 ++
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index cd58e47ab7b2..7653cbdb0ee4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -90,6 +90,26 @@ static int icl_pcode_read_qgv_point_info(struct
drm_i915_private *dev_priv,
return 0;
}
+static int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -354,7 +374,9 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
- int i;
+ int i, ret;
+ struct intel_qgv_info qi = {};
+ u32 points_mask = 0;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -398,10 +420,40 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
data_rate = intel_bw_data_rate(dev_priv, bw_state);
num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
data_rate = DIV_ROUND_UP(data_rate, 1000);
+ ret = icl_get_qgv_points(dev_priv, &qi);
+ if (ret < 0) {
+ goto fallback;
+ }
+
+ for (i = 0; i < qi.num_points; i++) {
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ if (max_data_rate < data_rate) {
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
restricted\n",
+ i, max_data_rate, data_rate);
+ points_mask |= 1 << i;
+ } else
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
unrestricted\n",
+ i, max_data_rate, data_rate);
+ }
+
+ if (points_mask >= ((1 << qi.num_points) - 1)) {
+ DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
+ return -EINVAL;
+ }
+
+ ret = icl_pcode_restrict_qgv_points(dev_priv, points_mask);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("Could not restrict required gqv points(%d)\n",
ret);
+ goto fallback;
+ }
+
+ return 0;
+
+fallback:
+ max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+
if (data_rate > max_data_rate) {
DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s
(%d active planes)\n",
data_rate, max_data_rate, num_active_planes);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..fe327fee8781 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8845,6 +8845,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)(((point) <<
16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
@@ -8856,6 +8857,8 @@ enum {
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
#define GEN9_SAGV_ENABLE 0x3
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
#define GEN6_PCODE_DATA_MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915/tgl: Implement Wa_1406941453"
== Series Details ==
Series: Revert "drm/i915/tgl: Implement Wa_1406941453"
URL : https://patchwork.freedesktop.org/series/66986/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6927 -> Patchwork_14469
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/
Known issues
Here are the changes found in Patchwork_14469 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][1] -> [FAIL][2] ([fdo#103167])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-icl-u3/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@gem_ctx_create@basic-files:
- {fi-icl-guc}: [INCOMPLETE][3] ([fdo#107713] / [fdo#109100]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html
- {fi-tgl-u2}:[INCOMPLETE][5] ([fdo#111735]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-tgl-u2/igt@gem_ctx_cre...@basic-files.html
- {fi-icl-dsi}: [INCOMPLETE][7] ([fdo#107713] / [fdo#109100]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-icl-dsi/igt@gem_ctx_cre...@basic-files.html
* igt@gem_ctx_switch@legacy-render:
- fi-apl-guc: [INCOMPLETE][9] ([fdo#103927] / [fdo#111381]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-apl-guc/igt@gem_ctx_swi...@legacy-render.html
* igt@gem_exec_reloc@basic-gtt-read:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1
similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-icl-u3/igt@gem_exec_re...@basic-gtt-read.html
* igt@i915_selftest@live_workarounds:
- {fi-tgl-u}: [DMESG-FAIL][13] ([fdo#111754]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-tgl-u/igt@i915_selftest@live_workarounds.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-tgl-u/igt@i915_selftest@live_workarounds.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [FAIL][15] ([fdo#91]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-skl-6700k2/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-skl-6700k2: [FAIL][17] ([fdo#90]) -> [PASS][18] +1 similar
issue
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-skl-6700k2/igt@kms_chamel...@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-skl-6700k2: [FAIL][19] -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-skl-6700k2/igt@kms_chamel...@hdmi-hpd-fast.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-skl-6700k2/igt@kms_chamel...@hdmi-hpd-fast.html
Warnings
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][21] ([fdo#111096]) -> [FAIL][22] ([fdo#111407])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6927/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14469/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#90]: https://bugs.freedesktop.org/show_bug.cgi?id=90
[fdo#91]: https://bugs.freedesktop.
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Support for DP HDR outputs (rev9)
== Series Details == Series: drm/i915/dp: Support for DP HDR outputs (rev9) URL : https://patchwork.freedesktop.org/series/65656/ State : success == Summary == CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14464_full Summary --- **SUCCESS** No regressions found. New tests - New tests have been introduced between CI_DRM_6925_full and Patchwork_14464_full: ### New Piglit tests (7) ### * spec@arb_gpu_shader5@texturegather@vs-rgba-2-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegather@vs-rgba-3-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffset@vs-rgba-0-float-2darray-const: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-1-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-2-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec@arb_gpu_shader5@texturegatheroffsets@vs-rgba-3-float-2d: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues Here are the changes found in Patchwork_14464_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_ctx_shared@exec-single-timeline-bsd: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb4/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-iclb8/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preemptive-hang-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#111325]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb7/igt@gem_exec_sched...@preemptive-hang-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-iclb2/igt@gem_exec_sched...@preemptive-hang-bsd.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-apl2/igt@gem_workarou...@suspend-resume-context.html * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen: - shard-hsw: [PASS][13] -> [DMESG-FAIL][14] ([fdo#102614] / [fdo#103232]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-hsw4/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-hsw5/igt@kms_cursor_...@pipe-a-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen: - shard-iclb: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_cursor_...@pipe-b-cursor-64x64-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-iclb7/igt@kms_cursor_...@pipe-b-cursor-64x64-onscreen.html * igt@kms_cursor_edge_walk@pipe-c-128x128-right-edge: - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#104671]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl4/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14464/shard-kbl1/igt@kms_cursor_edge_w...@pipe-c-128x128-right-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][19] -> [FAIL][20] ([fdo#105767]) [19]: https://inte
[Intel-gfx] [PATCH 04/23] drm/i915: Handle a few more cases for hw/sw split
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead. Look at uapi/hw where appropriate.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 6818cbd00ac2..32bbb5bf48f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16081,8 +16081,8 @@ static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
struct drm_modeset_acquire_ctx ctx;
- struct drm_crtc *crtc;
- struct drm_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
int ret = 0;
state = drm_atomic_state_alloc(dev);
@@ -16094,15 +16094,15 @@ static int intel_initial_commit(struct drm_device
*dev)
retry:
state->acquire_ctx = &ctx;
- drm_for_each_crtc(crtc, dev) {
- crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ for_each_intel_crtc(dev, crtc) {
+ crtc_state = intel_atomic_get_crtc_state(state, crtc);
if (IS_ERR(crtc_state)) {
ret = PTR_ERR(crtc_state);
goto out;
}
- if (crtc_state->active) {
- ret = drm_atomic_add_affected_planes(state, crtc);
+ if (crtc_state->hw.active) {
+ ret = drm_atomic_add_affected_planes(state,
&crtc->base);
if (ret)
goto out;
@@ -16112,7 +16112,7 @@ static int intel_initial_commit(struct drm_device *dev)
* having a proper LUT loaded. Remove once we
* have readout for pipe gamma enable.
*/
- crtc_state->color_mgmt_changed = true;
+ crtc_state->uapi.color_mgmt_changed = true;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 76f066b1dfe5..5127ec037b7b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -187,7 +187,7 @@ intel_dp_mst_atomic_check(struct drm_connector *connector,
if (!crtc_state ||
!drm_atomic_crtc_needs_modeset(crtc_state) ||
- crtc_state->enable)
+ to_intel_crtc_state(crtc_state)->hw.enable)
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 8988dbe8c19e..979e166f5639 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1068,9 +1068,9 @@ static int intel_psr_fastset_force(struct
drm_i915_private *dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (crtc_state->active && intel_crtc_state->has_psr) {
+ if (intel_crtc_state->hw.active && intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
- crtc_state->mode_changed = true;
+ intel_crtc_state->uapi.mode_changed = true;
break;
}
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/23] drm/i915: Disable FBC in bigjoiner configuration.
Is there any point in having FBC enabled on half a screen? I suppose it could still save power, but just feels wrong.. Can always be enabled later again if required. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/display/intel_fbc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index c6cc3775f3b8..e4d678d425e4 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1056,6 +1056,8 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, continue; crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + if (crtc_state->bigjoiner) + continue; crtc_state->enable_fbc = true; crtc_chosen = true; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/23] HAX drm/i915: Disable FEC entirely for now
I get a permanent FIFO underrun when enabling FEC with big joiner,
so for now disable it.
It seems that even at 1024x768 resolution without bigjoiner we don't
get a working configuration. Flag is set but vblank timing shows that
vblanks are delivered slightly faster, so the extra overhead we
calculated for data M/N goes unused.
Not-Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4dfb78dc7fa2..02242a16640b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1877,7 +1877,8 @@ static bool intel_dp_source_supports_dsc(struct intel_dp
*intel_dp,
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
const struct intel_crtc_state *pipe_config)
{
- if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
+ /* HACK: Disable FEC until we solved FIFO underruns */
+ if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable && 0)
return false;
return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
@@ -2024,8 +2025,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
int pipe_bpp;
int ret;
+ /* HACK: Disable FEC until we solved FIFO underruns */
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, pipe_config);
+ intel_dp_supports_fec(intel_dp, pipe_config) && 0;
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/23] drm/i915: Try to make bigjoiner work in atomic check.
When the clock is higher than the dotclock, try with 2 pipes enabled.
If we can enable 2, then we will go into big joiner mode, and steal
the adjacent crtc.
This only links the crtc's in software, no hardware or plane
programming is done yet. Blobs are also copied from the master's
crtc_state, so it doesn't depend at commit time on the other
crtc_state.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 15 +-
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +-
drivers/gpu/drm/i915/display/intel_display.c | 197 +-
.../drm/i915/display/intel_display_types.h| 11 +-
drivers/gpu/drm/i915/display/intel_dp.c | 25 ++-
5 files changed, 228 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index c50e0b218bd6..0db04064c86e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -228,25 +228,26 @@ void intel_crtc_free_hw_state(struct intel_crtc_state
*crtc_state)
intel_crtc_put_color_blobs(crtc_state);
}
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state *from_crtc_state)
{
intel_crtc_put_color_blobs(crtc_state);
- if (crtc_state->uapi.degamma_lut)
+ if (from_crtc_state->uapi.degamma_lut)
crtc_state->hw.degamma_lut =
- drm_property_blob_get(crtc_state->uapi.degamma_lut);
+
drm_property_blob_get(from_crtc_state->uapi.degamma_lut);
else
crtc_state->hw.degamma_lut = NULL;
- if (crtc_state->uapi.gamma_lut)
+ if (from_crtc_state->uapi.gamma_lut)
crtc_state->hw.gamma_lut =
- drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ drm_property_blob_get(from_crtc_state->uapi.gamma_lut);
else
crtc_state->hw.gamma_lut = NULL;
- if (crtc_state->uapi.ctm)
+ if (from_crtc_state->uapi.ctm)
crtc_state->hw.ctm =
- drm_property_blob_get(crtc_state->uapi.ctm);
+ drm_property_blob_get(from_crtc_state->uapi.ctm);
else
crtc_state->hw.ctm = NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 42be91e0772a..8da84d64aa04 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -36,7 +36,8 @@ struct drm_crtc_state *intel_crtc_duplicate_state(struct
drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
-void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
+const struct intel_crtc_state
*from_crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ba52a70840fd..143d531c4c81 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7434,7 +7434,7 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int clock_limit = dev_priv->max_dotclk_freq;
if (INTEL_GEN(dev_priv) < 4) {
@@ -7451,6 +7451,25 @@ static int intel_crtc_compute_config(struct intel_crtc
*crtc,
}
}
+ /*
+* copy hw mode to transcoder mode.
+* This matters mostly for big joiner, which splits the mode in half.
+*/
+ pipe_config->hw.transcoder_mode = pipe_config->hw.adjusted_mode;
+ if (pipe_config->bigjoiner) {
+ /* Make sure the crtc config is halved horizontally */
+ adjusted_mode->crtc_clock /= 2;
+ adjusted_mode->crtc_hdisplay /= 2;
+ adjusted_mode->crtc_hblank_start /= 2;
+ adjusted_mode->crtc_hblank_end /= 2;
+ adjusted_mode->crtc_hsync_start /= 2;
+ adjusted_mode->crtc_hsync_end /= 2;
+ adjusted_mode->crtc_htotal /= 2;
+ adjusted_mode->crtc_hskew /= 2;
+
+ pipe_config->pipe_src_w /= 2;
+ }
+
if (adjusted_mod
[Intel-gfx] [PATCH 17/23] drm/i915: Add intel_update_bigjoiner handling.
Enabling is done in a special sequence and to be fair, so should
plane updates be. Ideally the end user never notices the second
pipe is used, so use the vblank evasion to cover both pipes.
This way ideally everything will be tear free, and updates are
really atomic as userspace expects it.
The disable sequence still needs some love, but otherwise bigjoiner
is close to ready now.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 118 ---
drivers/gpu/drm/i915/display/intel_sprite.c | 22 +++-
drivers/gpu/drm/i915/display/intel_sprite.h | 3 +-
3 files changed, 123 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index acb3c5974e99..7f86c358cf45 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14230,7 +14230,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
else
i9xx_update_planes_on_crtc(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(new_crtc_state, NULL);
if (new_crtc_state->update_pipe && !modeset &&
old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
@@ -14312,6 +14312,56 @@ static void intel_commit_modeset_disables(struct
intel_atomic_state *state)
}
}
+static void intel_update_bigjoiner(struct intel_crtc *crtc,
+ struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ bool modeset = needs_modeset(new_crtc_state);
+ struct intel_crtc *slave = new_crtc_state->bigjoiner_linked_crtc;
+ struct intel_crtc_state *new_slave_crtc_state =
+ intel_atomic_get_new_crtc_state(state, slave);
+ struct intel_crtc_state *old_slave_crtc_state =
+ intel_atomic_get_old_crtc_state(state, slave);
+
+ if (modeset) {
+ /* Enable slave first */
+ update_scanline_offset(new_slave_crtc_state);
+ drm_calc_timestamping_constants(&slave->base,
&new_slave_crtc_state->hw.transcoder_mode);
+ dev_priv->display.crtc_enable(new_slave_crtc_state, state);
+
+ /* Then master */
+ update_scanline_offset(new_crtc_state);
+ drm_calc_timestamping_constants(&crtc->base,
&new_crtc_state->hw.transcoder_mode);
+ dev_priv->display.crtc_enable(new_crtc_state, state);
+
+ /* vblanks work again, re-enable pipe CRC. */
+ intel_crtc_enable_pipe_crc(crtc);
+
+ } else {
+ intel_pre_plane_update(old_crtc_state, new_crtc_state);
+ intel_pre_plane_update(old_slave_crtc_state,
new_slave_crtc_state);
+
+ if (new_crtc_state->update_pipe)
+ intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ }
+
+ /*
+* Perform vblank evasion around commit operation, and make sure to
+* commit both planes simultaneously for best results.
+*/
+ intel_pipe_update_start(new_crtc_state);
+
+ commit_pipe_config(state, old_crtc_state, new_crtc_state);
+ commit_pipe_config(state, old_slave_crtc_state, new_slave_crtc_state);
+
+ skl_update_planes_on_crtc(state, crtc);
+ icl_update_bigjoiner_planes_on_crtc(state, slave);
+
+ intel_pipe_update_end(new_crtc_state, new_slave_crtc_state);
+}
+
static void intel_commit_modeset_enables(struct intel_atomic_state *state)
{
struct intel_crtc *crtc;
@@ -14330,7 +14380,7 @@ static void intel_commit_modeset_enables(struct
intel_atomic_state *state)
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc *crtc;
+ struct intel_crtc *crtc, *slave;
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
unsigned int updated = 0;
bool progress;
@@ -14339,11 +14389,47 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
u8 required_slices = state->wm_results.ddb.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
+ struct skl_ddb_entry new_entries[I915_MAX_PIPES] = {};
+ const struct intel_crtc_state *slave_crtc_state;
+ u32 dirty_pipes = state->wm_results.dirty_pipes;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
+ if (new_crtc_state->bigjoiner_slave) {
+ /* clear dirty bit, we're updated in master */
+ dirty_pipes &= ~drm_crtc_mask(&crtc->
[Intel-gfx] [PATCH 14/23] drm/i915: Prepare update_slave() for bigjoiner plane updates
We want to program slave planes with the master plane_state for
properties such as FB, rotation, coordinates, etc, but the
slave plane_state for all programming parameters.
Instead of special casing NV12 Y-planes, we make the code more
generic, Y planes are programmed with separate state from the UV
plane.
This will allow us to program planes on a bigjoiner slave crtc in
a similar way.
This also requires the VMA to be copied to the slave, which is
done in prepare_plane_fb().
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 21 +++---
.../gpu/drm/i915/display/intel_atomic_plane.h | 3 -
drivers/gpu/drm/i915/display/intel_display.c | 56 --
drivers/gpu/drm/i915/display/intel_display.h | 3 +-
.../drm/i915/display/intel_display_types.h| 6 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 75 ++-
6 files changed, 106 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a1a34b9981cc..964db7774d10 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -277,14 +277,15 @@ void intel_update_plane(struct intel_plane *plane,
plane->update_plane(plane, crtc_state, plane_state);
}
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+static void intel_update_slave(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state
*master_plane_state,
+ const struct intel_plane_state
*slave_plane_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
trace_intel_update_plane(&plane->base, crtc);
- plane->update_slave(plane, crtc_state, plane_state);
+ plane->update_slave(plane, crtc_state, master_plane_state,
slave_plane_state);
}
void intel_disable_plane(struct intel_plane *plane,
@@ -324,6 +325,8 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
} else if (new_plane_state->planar_slave) {
struct intel_plane *master =
new_plane_state->planar_linked_plane;
+ struct intel_plane_state *master_plane_state =
+ intel_atomic_get_new_plane_state(state, master);
/*
* We update the slave plane from this function because
@@ -331,13 +334,11 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
* callback runs into issues when the Y plane is
* reassigned, disabled or used by a different plane.
*
-* The slave plane is updated with the master plane's
-* plane_state.
+* The slave plane is updated with the master's
+* plane_state as extra argument.
*/
- new_plane_state =
- intel_atomic_get_new_plane_state(state, master);
-
- intel_update_slave(plane, new_crtc_state,
new_plane_state);
+ intel_update_slave(plane, new_crtc_state,
+ master_plane_state, new_plane_state);
} else {
intel_disable_plane(plane, new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index cb7ef4f9eafd..33fb85cd3909 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -23,9 +23,6 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
void intel_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
-void intel_update_slave(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state);
void intel_disable_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
struct intel_plane *intel_plane_alloc(void);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 0424a378eb51..df588bf47559 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3972,11 +3972,12 @@ static unsigned int skl_plane_stride_mult(const struct
drm_framebuffer *fb,
return intel
[Intel-gfx] [PATCH 20/23] drm/i915: Make prepare_plane_fb() work with bigjoiner planes
Similar to plane programming, we need a separate master_plane_state from
which we will read all atomic properties, and plane_state for the real
coordinates.
Although we add all planes with icl_add_linked_planes(),
icl_check_nv12_planes() may add extra Y planes on the slave CRTC.
For those planes, the corresponding planes on the master CRTC
are not added, so we have to be slightly more careful in that case.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 ++
drivers/gpu/drm/i915/display/intel_display.c | 71 +++
3 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a0c1d1696c8c..9fca9e90af58 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -204,7 +204,7 @@ struct intel_crtc *
intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
const struct intel_plane_state
*old_plane_state,
const struct intel_plane_state
*new_plane_state)
- {
+{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index c98ccf8114c3..d789a1886908 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -52,5 +52,9 @@ int intel_atomic_plane_check_scaling(struct intel_crtc_state
*crtc_state,
const struct intel_plane_state
*master_plane_state,
struct intel_plane_state *plane_state,
int min_scale, int max_scale);
+struct intel_crtc *
+intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
+const struct intel_plane_state
*old_plane_state,
+const struct intel_plane_state
*new_plane_state);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 690c3d10ce44..8e1fab0fe7b5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14929,11 +14929,12 @@ static void add_rps_boost_after_vblank(struct
drm_crtc *crtc,
add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
}
-static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
+static int intel_plane_pin_fb(const struct intel_plane_state
*master_plane_state,
+ struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct drm_framebuffer *fb = plane_state->base.fb;
+ struct drm_framebuffer *fb = master_plane_state->base.fb;
struct i915_vma *vma;
if (plane->id == PLANE_CURSOR &&
@@ -14992,21 +14993,27 @@ static void fb_obj_bump_render_priority(struct
drm_i915_gem_object *obj)
* Returns 0 on success, negative error code on failure.
*/
int
-intel_prepare_plane_fb(struct drm_plane *plane,
- struct drm_plane_state *new_state)
+intel_prepare_plane_fb(struct drm_plane *drm_plane,
+ struct drm_plane_state *_new_plane_state)
{
- struct intel_atomic_state *intel_state =
- to_intel_atomic_state(new_state->state);
- struct drm_i915_private *dev_priv = to_i915(plane->dev);
- struct drm_framebuffer *fb = new_state->fb;
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
+ struct intel_plane *plane = to_intel_plane(drm_plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(_new_plane_state->state);
+ struct intel_plane_state *new_plane_state =
to_intel_plane_state(_new_plane_state);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ const struct intel_plane_state *new_master_plane_state =
new_plane_state;
+ struct drm_i915_gem_object *obj, *old_obj;
+ struct intel_crtc *crtc;
int ret;
- if (old_obj) {
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(intel_state,
-
to_intel_crtc(plane->state->crtc));
+ old_obj = intel_fb_obj(old_plane_state->base.fb);
+ if (!old_plane_state->bigjoiner_s
[Intel-gfx] [PATCH 22/23] drm/i915: Add debugfs dumping for bigjoiner.
It's useful to know what the actual clipped state is, rather than
the unclipped crtc properties.
This is useful when a plane is spread across 2 crtc's, where the
slave crtc has no own plane properties but derives its clipped
values from the master crtc.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 -
1 file changed, 17 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1c4c3972fd23..c3d12ab37cad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2661,42 +2661,31 @@ static void intel_plane_info(struct seq_file *m, struct
intel_crtc *intel_crtc)
struct intel_plane *intel_plane;
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- struct drm_plane_state *state;
+ struct intel_plane_state *state;
struct drm_plane *plane = &intel_plane->base;
struct drm_format_name_buf format_name;
char rot_str[48];
- if (!plane->state) {
- seq_puts(m, "plane->state is NULL!\n");
- continue;
- }
-
- state = plane->state;
+ state = to_intel_plane_state(plane->state);
- if (state->fb) {
- drm_get_format_name(state->fb->format->format,
+ if (state->base.fb) {
+ drm_get_format_name(state->base.fb->format->format,
&format_name);
+ } else if (state->bigjoiner_slave) {
+ sprintf(format_name.str, "(slave)");
} else {
sprintf(format_name.str, "N/A");
}
- plane_rotation(rot_str, sizeof(rot_str), state->rotation);
+ plane_rotation(rot_str, sizeof(rot_str), state->base.rotation);
- seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d,
crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u,
format=%s, rotation=%s\n",
+ seq_printf(m, "\t--Plane id %d: type=%s, %sclipped
crtc="DRM_RECT_FMT", clipped src="DRM_RECT_FP_FMT", format=%s, rotation=%s\n",
plane->base.id,
plane_type(intel_plane->base.type),
- state->crtc_x, state->crtc_y,
- state->crtc_w, state->crtc_h,
- (state->src_x >> 16),
- ((state->src_x & 0x) * 15625) >> 10,
- (state->src_y >> 16),
- ((state->src_y & 0x) * 15625) >> 10,
- (state->src_w >> 16),
- ((state->src_w & 0x) * 15625) >> 10,
- (state->src_h >> 16),
- ((state->src_h & 0x) * 15625) >> 10,
- format_name.str,
- rot_str);
+ state->base.visible ? "visible, " : "",
+ DRM_RECT_ARG(&state->base.dst),
+ DRM_RECT_FP_ARG(&state->base.src),
+ format_name.str, rot_str);
}
}
@@ -2752,6 +2741,11 @@ static int i915_display_info(struct seq_file *m, void
*unused)
yesno(pipe_config->hw.active),
pipe_config->pipe_src_w, pipe_config->pipe_src_h,
yesno(pipe_config->dither), pipe_config->pipe_bpp);
+ if (pipe_config->bigjoiner)
+ seq_printf(m, "\tLinked to [CRTC:%d:%s] as a %s\n",
+
pipe_config->bigjoiner_linked_crtc->base.base.id,
+
pipe_config->bigjoiner_linked_crtc->base.name,
+ pipe_config->bigjoiner_slave ? "slave" :
"master");
if (pipe_config->hw.active) {
struct intel_plane *cursor =
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/23] drm/i915: Prepare atomic plane check for bigjoiner planes
A lot of delta, the main difference is that the master_plane_state is
not the same plane_state as being written to.
We read all properties like color key, crtc, fb, rotation from the
master_plane_state and coordinate properties.
The coordinate properties are different between the 2 bigjoiner planes,
as one gets the left and the other gets the right side.
Fortunately the drm core already has a src and dst rect, so we write
those for each plane separately.
In case of cursor, we don't use the clipped coordinates, but the raw
source coordinates from the master_plane_state instead.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 88 +++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 213 ++
drivers/gpu/drm/i915/display/intel_display.h | 5 +-
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_sprite.c | 71 +++---
drivers/gpu/drm/i915/display/intel_sprite.h | 6 +-
8 files changed, 258 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 0db04064c86e..a8f34254cd2a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -297,9 +297,10 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->is_yuv &&
- plane_state->base.fb->format->num_planes > 1) {
+ if (plane_state && (plane_state->linked_plane ||
+(!plane_state->bigjoiner_slave && plane_state->base.fb &&
+ plane_state->base.fb->format->is_yuv &&
+ plane_state->base.fb->format->num_planes > 1))) {
struct intel_plane *plane =
to_intel_plane(plane_state->base.plane);
if (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 5db091e4ad6a..a0c1d1696c8c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -115,10 +115,11 @@ intel_plane_destroy_state(struct drm_plane *plane,
drm_atomic_helper_plane_destroy_state(plane, state);
}
-unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
+static unsigned int intel_plane_data_rate(const struct intel_crtc_state
*crtc_state,
+ const struct intel_plane_state
*master_plane_state,
+ const struct intel_plane_state
*plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_framebuffer *fb = master_plane_state->base.fb;
unsigned int cpp;
if (!plane_state->base.visible)
@@ -143,8 +144,12 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state
*new_plane_state)
{
+ const struct intel_plane_state *new_master_plane_state =
new_plane_state;
+ const struct intel_plane_state *old_master_plane_state =
old_plane_state;
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
- const struct drm_framebuffer *fb = new_plane_state->base.fb;
+ const struct drm_framebuffer *fb;
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_plane_state->base.state);
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -153,10 +158,21 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->data_rate[plane->id] = 0;
new_plane_state->base.visible = false;
- if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
+ if (old_plane_state->bigjoiner_slave)
+ old_master_plane_state =
+ intel_atomic_get_old_plane_state(state,
+ old_plane_state->bigjoiner_plane);
+
+ if (new_plane_state->bigjoiner_slave)
+ new_master_plane_state =
+ intel_atomic_get_new_plane_state(state,
+ new_plane_state->bigjoiner_plane);
+
+ if (!new_master_plane_state->base.crtc &&
!old_master_plane_state->base.crtc)
return 0;
- ret = plane->check_plane(new_crtc_state, new_plane_state);
+ ret = plane->check_plane(new_crtc_state,
+
[Intel-gfx] [PATCH 01/23] drm/i915/dp: Fix dsc bpp calculations, v2.
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
with the calculations breaking at HBR3.
As a result our calculated bpp was way too high, and the link width
limitation never came into effect.
Print out the resulting bpp calcululations as a sanity check, just
in case we ever have to debug it later on again.
We also used the wrong factor for FEC. While bspec mentions 2.4%,
all the calculations use 1/0.972261, and the same ratio should be
applied to data M/N as well, so use it there when FEC is enabled.
Make sure we don't break hw readout, and read out FEC enable state
and correct the DDI clock readout for the new values.
Together with the next commit, this causes FEC to work correctly
with big joiner, while also having the correct refresh rate
reported in kms_setmode.basic.
Signed-off-by: Maarten Lankhorst
Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice
Count for DSC")
Cc: # v5.0+
Cc: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_ddi.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 195 ++-
drivers/gpu/drm/i915/display/intel_dp.h | 6 +-
4 files changed, 128 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..1b59b852874b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1479,6 +1479,10 @@ static void ddi_dotclock_get(struct intel_crtc_state
*pipe_config)
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
+ /* fec adds overhead to the data M/N values, correct for it */
+ if (pipe_config->fec_enable)
+ dotclock = intel_dp_fec_to_mode_clock(dotclock);
+
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
@@ -4031,7 +4035,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
case TRANS_DDI_MODE_SELECT_FDI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
break;
- case TRANS_DDI_MODE_SELECT_DP_SST:
+ case TRANS_DDI_MODE_SELECT_DP_SST: {
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
if (encoder->type == INTEL_OUTPUT_EDP)
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
else
@@ -4039,7 +4045,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
pipe_config->lane_count =
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT)
+ 1;
intel_dp_get_m_n(intel_crtc, pipe_config);
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ pipe_config->fec_enable =
+ I915_READ(intel_dp->regs.dp_tp_ctl) &
+ DP_TP_CTL_FEC_ENABLE;
+ DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
+ encoder->base.base.id, encoder->base.name,
+ pipe_config->fec_enable);
+ }
+
break;
+ }
case TRANS_DDI_MODE_SELECT_DP_MST:
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
pipe_config->lane_count =
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e0033d99f6e3..7996864e6f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12773,6 +12773,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
PIPE_CONF_CHECK_BOOL(has_infoframe);
+ PIPE_CONF_CHECK_BOOL(fec_enable);
PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index ccaf9f00b747..4dfb78dc7fa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,8 +76,8 @@
#define DP_DSC_MAX_ENC_THROUGHPUT_034
#define DP_DSC_MAX_ENC_THROUGHPUT_140
-/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
-#define DP_DSC_FEC_OVERHEAD_FACTOR 976
+/* DP DSC FEC Overhead factor = 1/(0.972261) */
+#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
/* Compliance test status bits */
#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
@@ -492,6 +492,104 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
return 0;
}
+static inline u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
+{
+ return div_u64(mul_u32_u32(mode_clock, 100U),
+ DP_DSC_FEC_OVERHEAD_FACTOR);
+}
+
+u32 inte
[Intel-gfx] [PATCH 16/23] drm/i915: Program planes in bigjoiner mode.
Now that we can program planes from the update_slave callback, and
we have done all fb pinning correctly, it's time to program those
planes as well.
We use the update_slave callback as it allows us to use the
separate states correctly.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 53 +++
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
3 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cc088676f0a2..5db091e4ad6a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -366,6 +366,59 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
}
}
+void icl_update_bigjoiner_planes_on_crtc(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct skl_ddb_entry entries_y[I915_MAX_PLANES];
+ struct skl_ddb_entry entries_uv[I915_MAX_PLANES];
+ u32 update_mask = new_crtc_state->update_planes;
+ struct intel_plane *plane;
+
+ memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y,
+ sizeof(old_crtc_state->wm.skl.plane_ddb_y));
+ memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv,
+ sizeof(old_crtc_state->wm.skl.plane_ddb_uv));
+
+ while ((plane = skl_next_plane_to_commit(state, crtc,
+entries_y, entries_uv,
+&update_mask))) {
+ struct intel_plane_state *new_plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ const struct intel_plane_state *master_plane_state;
+
+ if (new_plane_state->base.visible) {
+ master_plane_state =
+ intel_atomic_get_new_plane_state(state,
new_plane_state->bigjoiner_plane);
+
+ intel_update_slave(plane, new_crtc_state,
+ master_plane_state, new_plane_state);
+ } else if (new_plane_state->slave) {
+ /*
+* bigjoiner slave + planar slave.
+* The correct sequence is to get from the planar slave
to planar master,
+* then to the master plane state for the
master_plane_state.
+*/
+
+ struct intel_plane *linked =
new_plane_state->linked_plane;
+ const struct intel_plane_state *uv_plane_state =
+ intel_atomic_get_new_plane_state(state, linked);
+
+ linked = uv_plane_state->bigjoiner_plane;
+ master_plane_state =
+ intel_atomic_get_new_plane_state(state, linked);
+
+ intel_update_slave(plane, new_crtc_state,
+ master_plane_state, new_plane_state);
+ } else {
+ intel_disable_plane(plane, new_crtc_state);
+ }
+ }
+}
+
void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 901a50e6e2d3..1cffda2b50b5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -30,6 +30,8 @@ void intel_plane_free(struct intel_plane *plane);
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
void intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state);
+void icl_update_bigjoiner_planes_on_crtc(struct intel_atomic_state *state,
+struct intel_crtc *crtc);
void skl_update_planes_on_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 06ceac4f1436..acb3c5974e99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14223,8 +14223,8 @@ static void intel_update_crtc(struct intel_crtc *crtc,
commit_pipe_config(state, old_crtc_state, new_crtc_state);
- if (new_crtc_state->bigjoiner)
- {/* Not supported yet */
[Intel-gfx] [PATCH 23/23] HAX to make it work on the icelake test system
Can't figure out how it works, so just removing it..
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/drm_dp_helper.c | 4 ++--
include/drm/drm_dp_helper.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f373798d82f6..a990073c7adf 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1374,7 +1374,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
} else {
@@ -1398,7 +1398,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
- return 2;
+ return 4;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
return 1;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index ed1a985745ba..065b65350fce 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1222,6 +1222,7 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpc[DP_DSC_RECEIVER_CAP_SI
static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
{
+ return dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT];
return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
DP_DSC_DECOMPRESSION_IS_SUPPORTED;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/23] drm/i915: Enable big joiner support in enable and disable sequences.
Make vdsc work when no output is enabled. The big joiner needs VDSC
on the slave, so enable it and set the appropriate bits.
Also update timestamping constants, because slave crtc's are not
updated in drm_atomic_helper_update_legacy_modeset_state().
This should be enough to bring up CRTC's in a big joiner configuration,
without any plane configuration on the second pipe yet.
HOWEVER, we bring up the crtc's in the wrong order. We need to make
sure that the master crtc is brought up after the slave crtc, we
don't do that yet. This is done correctly later in this series.
The next steps are to add atomic commit, and make sure we enable and
update both master and slave in the correct order.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ddi.c | 55 ++-
drivers/gpu/drm/i915/display/intel_display.c | 402 --
.../drm/i915/display/intel_display_types.h| 17 +
drivers/gpu/drm/i915/display/intel_dp.c | 18 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 122 --
drivers/gpu/drm/i915/display/intel_vdsc.h | 2 +
6 files changed, 418 insertions(+), 198 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c775fd205915..a26155f90261 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1694,6 +1694,13 @@ static void intel_ddi_clock_get(struct intel_encoder
*encoder,
skl_ddi_clock_get(encoder, pipe_config);
else if (INTEL_GEN(dev_priv) <= 8)
hsw_ddi_clock_get(encoder, pipe_config);
+
+ if (pipe_config->bigjoiner) {
+ pipe_config->hw.transcoder_mode.crtc_clock =
+ pipe_config->hw.adjusted_mode.crtc_clock;
+
+ pipe_config->hw.adjusted_mode.crtc_clock /= 2;
+ }
}
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
@@ -2176,13 +2183,6 @@ static void intel_ddi_get_power_domains(struct
intel_encoder *encoder,
intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
-
- /*
-* VDSC power is needed when DSC is enabled
-*/
- if (crtc_state->dsc_params.compression_enable)
- intel_display_power_get(dev_priv,
- intel_dsc_power_domain(crtc_state));
}
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -3290,7 +3290,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder
*encoder,
/* 7.l */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3361,7 +3362,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
*encoder,
if (!is_mst)
intel_ddi_enable_pipe_clock(crtc_state);
- intel_dsc_enable(encoder, crtc_state);
+ if (!crtc_state->bigjoiner)
+ intel_dsc_enable(encoder, crtc_state);
}
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3972,19 +3974,18 @@ void intel_ddi_compute_min_voltage_level(struct
drm_i915_private *dev_priv,
crtc_state->min_voltage_level = 2;
}
-void intel_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config)
+static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 temp, flags = 0;
- /* XXX: DSI transcoder paranoia */
- if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
+ if (!(temp & TRANS_DDI_FUNC_ENABLE))
return;
- temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (temp & TRANS_DDI_PHSYNC)
flags |= DRM_MODE_FLAG_PHSYNC;
else
@@ -4066,6 +4067,29 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
default:
break;
}
+}
+
+void intel_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+
+ /* XXX: DSI transcoder paranoia */
+ if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
+ return;
+
+ intel_ddi_read_func_ctl(encoder, pipe_config);
+ if (pipe_config->bigjoiner_slave
[Intel-gfx] [PATCH 05/23] drm/i915: Complete sw/hw split
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 44 +++
drivers/gpu/drm/i915/display/intel_atomic.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 39 +---
.../drm/i915/display/intel_display_types.h| 8 ++--
4 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index f4440ede95c5..fb550d3cea7f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -195,6 +195,14 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
+ /* copy color blobs */
+ if (crtc_state->hw.degamma_lut)
+ drm_property_blob_get(crtc_state->hw.degamma_lut);
+ if (crtc_state->hw.ctm)
+ drm_property_blob_get(crtc_state->hw.ctm);
+ if (crtc_state->hw.gamma_lut)
+ drm_property_blob_get(crtc_state->hw.gamma_lut);
+
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
@@ -209,6 +217,41 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
return &crtc_state->uapi;
}
+static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ drm_property_blob_put(crtc_state->hw.degamma_lut);
+ drm_property_blob_put(crtc_state->hw.gamma_lut);
+ drm_property_blob_put(crtc_state->hw.ctm);
+}
+
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+}
+
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state)
+{
+ intel_crtc_put_color_blobs(crtc_state);
+
+ if (crtc_state->uapi.degamma_lut)
+ crtc_state->hw.degamma_lut =
+ drm_property_blob_get(crtc_state->uapi.degamma_lut);
+ else
+ crtc_state->hw.degamma_lut = NULL;
+
+ if (crtc_state->uapi.gamma_lut)
+ crtc_state->hw.gamma_lut =
+ drm_property_blob_get(crtc_state->uapi.gamma_lut);
+ else
+ crtc_state->hw.gamma_lut = NULL;
+
+ if (crtc_state->uapi.ctm)
+ crtc_state->hw.ctm =
+ drm_property_blob_get(crtc_state->uapi.ctm);
+ else
+ crtc_state->hw.ctm = NULL;
+}
+
/**
* intel_crtc_destroy_state - destroy crtc state
* @crtc: drm crtc
@@ -224,6 +267,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
kfree(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..42be91e0772a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,8 @@ intel_digital_connector_duplicate_state(struct drm_connector
*connector);
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
+void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state);
+void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 32bbb5bf48f3..e40485a1e503 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -114,6 +114,7 @@ static const u64 cursor_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static void copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state);
static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
@@ -7097,6 +7098,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc,
crtc->enabled = false;
crtc->state->connector_mask = 0;
crtc->state->encoder_mask = 0;
+ copy_uapi_to_hw_state(to_intel_crtc_state(crtc->state));
for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
encoder->base.crtc = NULL;
@@ -11804,6 +11806,9 @@ static int intel_crtc_atomic_check(struct drm_crtc
*_crtc,
if (mode_changed || crtc_state->upd
[Intel-gfx] [PATCH 06/23] drm/i915: Get rid of crtc_state->fb_changed
We had this as an optimization to not do a plane update, but we killed
it off because there are so many reasons we may have to do a plane
update or fastset that it's best to just assume everything changed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c| 1 -
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index fb550d3cea7f..4b4eee9c49f5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -208,7 +208,6 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->disable_cxsr = false;
crtc_state->update_wm_pre = false;
crtc_state->update_wm_post = false;
- crtc_state->fb_changed = false;
crtc_state->fifo_changed = false;
crtc_state->wm.need_postvbl_update = false;
crtc_state->fb_bits = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e40485a1e503..520c66071e67 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11521,7 +11521,6 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
bool was_crtc_enabled = old_crtc_state->hw.active;
bool is_crtc_enabled = crtc_state->hw.active;
bool turn_off, turn_on, visible, was_visible;
- struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
@@ -11555,18 +11554,11 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
if (!was_visible && !visible)
return 0;
- if (fb != old_plane_state->base.fb)
- crtc_state->fb_changed = true;
-
turn_off = was_visible && (!visible || mode_changed);
turn_on = visible && (!was_visible || mode_changed);
- DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
+ DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off
%i, on %i, ms %i\n",
crtc->base.base.id, crtc->base.name,
-plane->base.base.id, plane->base.name,
-fb ? fb->base.id : -1);
-
- DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms
%i\n",
plane->base.base.id, plane->base.name,
was_visible, visible,
turn_off, turn_on, mode_changed);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index e81b785cc8f2..57dbcfc126df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -792,7 +792,6 @@ struct intel_crtc_state {
bool update_pipe; /* can a fast modeset be performed? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
- bool fb_changed; /* fb on any of the planes is changed */
bool fifo_changed; /* FIFO split is changed */
/* Pipe source size (ie. panel fitter input size)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/23] drm/i915: Rename planar linked plane variables
Rename linked_plane to planar_linked_plane and slave to planar_slave,
this will make it easier to keep apart bigjoiner linking and planar plane
linking.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 7 --
.../gpu/drm/i915/display/intel_atomic_plane.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display.c | 22 +--
.../drm/i915/display/intel_display_types.h| 8 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 12 +-
6 files changed, 30 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 4b4eee9c49f5..158594e64bb9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -311,10 +311,13 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
*/
mode = PS_SCALER_MODE_NORMAL;
} else {
+ struct intel_plane *linked =
+ plane_state->planar_linked_plane;
+
mode = PS_SCALER_MODE_PLANAR;
- if (plane_state->linked_plane)
- mode |=
PS_PLANE_Y_SEL(plane_state->linked_plane->id);
+ if (linked)
+ mode |= PS_PLANE_Y_SEL(linked->id);
}
} else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
mode = PS_SCALER_MODE_NORMAL;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 1f50b15ec704..a1a34b9981cc 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -321,9 +321,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
if (new_plane_state->base.visible) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
- } else if (new_plane_state->slave) {
+ } else if (new_plane_state->planar_slave) {
struct intel_plane *master =
- new_plane_state->linked_plane;
+ new_plane_state->planar_linked_plane;
/*
* We update the slave plane from this function because
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index fd8b398733b8..ba52a70840fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11666,7 +11666,7 @@ static int icl_add_linked_planes(struct
intel_atomic_state *state)
int i;
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- linked = plane_state->linked_plane;
+ linked = plane_state->planar_linked_plane;
if (!linked)
continue;
@@ -11675,8 +11675,8 @@ static int icl_add_linked_planes(struct
intel_atomic_state *state)
if (IS_ERR(linked_plane_state))
return PTR_ERR(linked_plane_state);
- WARN_ON(linked_plane_state->linked_plane != plane);
- WARN_ON(linked_plane_state->slave == plane_state->slave);
+ WARN_ON(linked_plane_state->planar_linked_plane != plane);
+ WARN_ON(linked_plane_state->planar_slave ==
plane_state->planar_slave);
}
return 0;
@@ -11699,16 +11699,16 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
* in the crtc_state->active_planes mask.
*/
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
- if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
+ if (plane->pipe != crtc->pipe ||
!plane_state->planar_linked_plane)
continue;
- plane_state->linked_plane = NULL;
- if (plane_state->slave && !plane_state->base.visible) {
+ plane_state->planar_linked_plane = NULL;
+ if (plane_state->planar_slave && !plane_state->base.visible) {
crtc_state->active_planes &= ~BIT(plane->id);
crtc_state->update_planes |= BIT(plane->id);
}
- plane_state->slave = false;
+ plane_state->planar_slave = false;
}
if (!crtc_state->nv12_planes)
@@ -11742,10 +11742,10 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
return -EINVAL;
}
- plane_state->linked_plane = linked;
+ plane_state->planar_linked_plane = linked;
- linked_state->slave = true;
-
[Intel-gfx] [PATCH 10/23] drm/i915/dp: Allow big joiner modes in intel_dp_mode_valid()
Small changes to intel_dp_mode_valid(), allow listing modes that
can only be supported in the bigjoiner configuration, which is
not supported yet.
Also unexport a few functions only used internally in intel_dp.c
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_dp.c | 98 +++--
1 file changed, 75 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2fceb71f7f70..046e1662d1e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -247,7 +247,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
}
static int
-intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
+intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp, bool
allow_bigjoiner)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &intel_dig_port->base;
@@ -257,6 +257,9 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
+ if (allow_bigjoiner && INTEL_GEN(dev_priv) >= 11)
+ max_dotclk *= 2;
+
if (type != DP_DS_PORT_TYPE_VGA)
return max_dotclk;
@@ -505,8 +508,10 @@ u32 intel_dp_fec_to_mode_clock(u32 fec_clock)
100U);
}
-static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay)
+static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *dev_priv,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -523,6 +528,10 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32
lane_count,
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
mode_hdisplay;
+
+ if (bigjoiner)
+ max_bpp_small_joiner_ram *= 2;
+
DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
/*
@@ -531,6 +540,15 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32
lane_count,
*/
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
+ if (bigjoiner) {
+ u32 max_bpp_bigjoiner =
+ dev_priv->max_cdclk_freq * 48 /
+ intel_dp_mode_to_fec_clock(mode_clock);
+
+ DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
+ bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
+ }
+
/* Error out if the max bpp is less than smallest allowed valid bpp */
if (bits_per_pixel < valid_dsc_bpp[0]) {
DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
@@ -553,7 +571,8 @@ static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32
lane_count,
}
static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay)
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
u8 min_slice_count, i;
int max_slice_width;
@@ -578,12 +597,20 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp
*intel_dp,
/* Find the closest match to the valid slice count values */
for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
- if (valid_dsc_slicecount[i] >
- drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
- false))
+ u8 test_slice_count = bigjoiner ?
+ 2 * valid_dsc_slicecount[i] :
+ valid_dsc_slicecount[i];
+
+ if (test_slice_count >
+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
break;
- if (min_slice_count <= valid_dsc_slicecount[i])
- return valid_dsc_slicecount[i];
+
+ /* big joiner needs small joiner to be enabled */
+ if (bigjoiner && test_slice_count < 4)
+ continue;
+
+ if (min_slice_count <= test_slice_count)
+ return test_slice_count;
}
DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
@@ -603,11 +630,15 @@ intel_dp_mode_valid(struct drm_connector *connector,
int max_dotclk;
u16 dsc_max_output_bpp = 0;
u8 dsc_slice_count = 0;
+ bool dsc = false, bigjoiner = false;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
- max_dotclk =
[Intel-gfx] [PATCH 15/23] drm/i915: Link planes in a bigjoiner configuration.
Make sure that when a plane is set in a bigjoiner mode, we will add
their counterpart to the atomic state as well. This will allow us to
make sure all state is available when planes are checked.
Because of the funny interactions with bigjoiner and planar YUV
formats, we may end up adding a lot of planes, so we have to keep
iterating until we no longer add any planes.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 31 +++-
.../gpu/drm/i915/display/intel_atomic_plane.h | 4 +
drivers/gpu/drm/i915/display/intel_display.c | 142 --
.../drm/i915/display/intel_display_types.h| 11 ++
4 files changed, 172 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 964db7774d10..cc088676f0a2 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -182,16 +182,36 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
old_plane_state,
new_plane_state);
}
-static struct intel_crtc *
-get_crtc_from_states(const struct intel_plane_state *old_plane_state,
-const struct intel_plane_state *new_plane_state)
-{
+struct intel_crtc *
+intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
+const struct intel_plane_state
*old_plane_state,
+const struct intel_plane_state
*new_plane_state)
+ {
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+
if (new_plane_state->base.crtc)
return to_intel_crtc(new_plane_state->base.crtc);
if (old_plane_state->base.crtc)
return to_intel_crtc(old_plane_state->base.crtc);
+ if (new_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *new_master_plane_state =
+ intel_atomic_get_new_plane_state(state,
new_plane_state->bigjoiner_plane);
+
+ if (new_master_plane_state->base.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
+ if (old_plane_state->bigjoiner_slave) {
+ const struct intel_plane_state *old_master_plane_state =
+ intel_atomic_get_old_plane_state(state,
old_plane_state->bigjoiner_plane);
+
+ if (old_master_plane_state->base.crtc)
+ return intel_get_crtc_for_pipe(dev_priv, plane->pipe);
+ }
+
return NULL;
}
@@ -206,7 +226,8 @@ static int intel_plane_atomic_check(struct drm_plane
*_plane,
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
struct intel_crtc *crtc =
- get_crtc_from_states(old_plane_state, new_plane_state);
+ intel_plane_get_crtc_from_states(state, old_plane_state,
+new_plane_state);
const struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index 33fb85cd3909..901a50e6e2d3 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -42,5 +42,9 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state *plane_state);
+struct intel_crtc *
+intel_plane_get_crtc_from_states(struct intel_atomic_state *state,
+const struct intel_plane_state
*old_plane_state,
+const struct intel_plane_state
*new_plane_state);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index df588bf47559..06ceac4f1436 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11811,24 +11811,101 @@ static bool check_single_encoder_cloning(struct
drm_atomic_state *state,
return true;
}
+static int icl_add_dependent_planes(struct intel_atomic_state *state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane_state *new_plane_state;
+ struct intel_plane *plane;
+ int ret = 0;
+
+ plane = plane_state->bigjoiner_plane;
+ if (plane && !intel_atomic_get_new_plane_state(state, plane)) {
+ new_plane_state = intel_atomic_get_plane_stat
[Intel-gfx] [PATCH 09/23] drm/i915: Do not add all planes when checking scalers on glk+
We cannot switch between HQ and normal mode on GLK+, so only
add planes on platforms where it makes sense.
We could probably restrict it even more to only add when scaler
users toggles between 1 and 2, but lets just leave it for now.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 158594e64bb9..c50e0b218bd6 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -421,6 +421,11 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
*/
if (!plane) {
struct drm_plane_state *state;
+
+ /* No need to reprogram, we're not changing
scaling mode */
+ if (INTEL_GEN(dev_priv) >= 10 ||
IS_GEMINILAKE(dev_priv))
+ continue;
+
plane = drm_plane_from_index(&dev_priv->drm, i);
state = drm_atomic_get_plane_state(drm_state,
plane);
if (IS_ERR(state)) {
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/23] drm/i915: Remove begin/finish_crtc_commit.
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 124 ---
1 file changed, 52 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 520c66071e67..fd8b398733b8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -136,8 +136,6 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
static void chv_prepare_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *pipe_config);
-static void intel_begin_crtc_commit(struct intel_atomic_state *, struct
intel_crtc *);
-static void intel_finish_crtc_commit(struct intel_atomic_state *, struct
intel_crtc *);
static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
@@ -13673,13 +13671,54 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc
*crtc)
return crtc->base.funcs->get_vblank_counter(&crtc->base);
}
+void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ if (!IS_GEN(dev_priv, 2))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
true);
+
+ if (crtc_state->has_pch_encoder) {
+ enum pipe pch_transcoder =
+ intel_crtc_pch_transcoder(crtc);
+
+ intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
true);
+ }
+}
+
+static void commit_pipe_config(struct intel_atomic_state *state,
+ struct intel_crtc_state *old_crtc_state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ bool modeset = needs_modeset(new_crtc_state);
+
+ if (!modeset) {
+ if (new_crtc_state->uapi.color_mgmt_changed ||
+ new_crtc_state->update_pipe)
+ intel_color_commit(new_crtc_state);
+
+ if (new_crtc_state->update_pipe)
+ intel_update_pipe_config(old_crtc_state,
new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 9)
+ skl_detach_scalers(new_crtc_state);
+
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
+ }
+
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state,
+ new_crtc_state);
+}
+
static void intel_update_crtc(struct intel_crtc *crtc,
struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
- struct drm_device *dev = state->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state,
@@ -13703,14 +13742,21 @@ static void intel_update_crtc(struct intel_crtc *crtc,
else if (new_plane_state)
intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
- intel_begin_crtc_commit(state, crtc);
+ /* Perform vblank evasion around commit operation */
+ intel_pipe_update_start(new_crtc_state);
+
+ commit_pipe_config(state, old_crtc_state, new_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
skl_update_planes_on_crtc(state, crtc);
else
i9xx_update_planes_on_crtc(state, crtc);
- intel_finish_crtc_commit(state, crtc);
+ intel_pipe_update_end(new_crtc_state);
+
+ if (new_crtc_state->update_pipe && !modeset &&
+ old_crtc_state->hw.mode.private_flags & I915_MODE_FLAG_INHERITED)
+ intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
}
static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
@@ -14507,72 +14553,6 @@ skl_max_scale(const struct intel_crtc_state
*crtc_state,
return max_scale;
}
-static void intel_begin_crtc_commit(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_crtc_state *old_
[Intel-gfx] [PATCH 21/23] drm/i915: Make sure watermarks work correctly with bigjoiner as well.
For bigjoiner, we cannot do drm_atomic_crtc_state_for_each_plane_state()
on the crtc, because planes don't match the drm core state.
We need a separate master_plane_state for all the properties,
and a slave_plane_state for the rectangles/visibility etc.
This is similar to how we handle the Y plane, because it won't be
directly calculated either. Instead it's calculated from the master
crtc.
Add a intel_atomic_crtc_state_for_each_plane_state macro, which
iterates over master_plane_state and obtains slave_plane_state
as well. This cleans up code slightly as well.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 2 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.h | 20 +-
drivers/gpu/drm/i915/intel_pm.c | 201 ++
4 files changed, 134 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index a8f34254cd2a..add77e33e54e 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -297,7 +297,7 @@ static void intel_atomic_setup_scaler(struct
intel_crtc_scaler_state *scaler_sta
return;
/* set scaler mode */
- if (plane_state && (plane_state->linked_plane ||
+ if (plane_state && (plane_state->planar_linked_plane ||
(!plane_state->bigjoiner_slave && plane_state->base.fb &&
plane_state->base.fb->format->is_yuv &&
plane_state->base.fb->format->num_planes > 1))) {
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 9fca9e90af58..f471bb30c20a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -414,14 +414,14 @@ void icl_update_bigjoiner_planes_on_crtc(struct
intel_atomic_state *state,
intel_update_slave(plane, new_crtc_state,
master_plane_state, new_plane_state);
- } else if (new_plane_state->slave) {
+ } else if (new_plane_state->planar_slave) {
/*
* bigjoiner slave + planar slave.
* The correct sequence is to get from the planar slave
to planar master,
* then to the master plane state for the
master_plane_state.
*/
- struct intel_plane *linked =
new_plane_state->linked_plane;
+ struct intel_plane *linked =
new_plane_state->planar_linked_plane;
const struct intel_plane_state *uv_plane_state =
intel_atomic_get_new_plane_state(state, linked);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index a8b2198fcef1..14717a59e677 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -350,7 +350,7 @@ enum phy_fia {
&(dev)->mode_config.plane_list, \
base.head) \
for_each_if((plane_mask) & \
- drm_plane_mask(&intel_plane->base)))
+ drm_plane_mask(&intel_plane->base))
#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
list_for_each_entry(intel_plane,\
@@ -440,6 +440,24 @@ enum phy_fia {
(__i)--) \
for_each_if(crtc)
+#define intel_atomic_crtc_state_for_each_plane_state( \
+ plane, master_plane_state, plane_state, \
+ crtc_state) \
+ for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
+ (((crtc_state)->bigjoiner_slave ? \
+ intel_atomic_get_new_crtc_state( \
+
to_intel_atomic_state((crtc_state)->uapi.state), \
+ (crtc_state)->bigjoiner_linked_crtc) : \
+ (crtc_state))->uapi.plane_mask)) \
+ for_each_if master_plane_state) = \
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
&plane->base))), \
+ ((plane) = (master_plane_state)->bigjoiner_slave
? \
+(master_plane_state)->bigjoiner_plane
: \
+(plane)), \
+ ((plane_state) =
(master_plane_state)->bigjoiner_slave ? \
+
to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state,
&plane->base)) : \
+ (mas
[Intel-gfx] [PATCH 13/23] drm/i915: Make hardware readout work on i915.
Unfortunately I have no way to test this, but it should be correct
if the bios sets up bigjoiner in a sane way.
Skip iterating over bigjoiner slaves, only the master has the state we
care about.
Add the width of the bigjoiner slave to the reconstructed fb.
Hide the bigjoiner slave to userspace, and double the mode on bigjoiner
master.
And last, disable bigjoiner slave from primary if reconstruction fails.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 65 +++-
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8c08c4914c9b..0424a378eb51 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3177,6 +3177,8 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
struct intel_plane *intel_plane = to_intel_plane(primary);
struct intel_plane_state *intel_state =
to_intel_plane_state(plane_state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(intel_crtc->base.state);
struct drm_framebuffer *fb;
if (!plane_config->fb)
@@ -3199,7 +3201,7 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
if (c == &intel_crtc->base)
continue;
- if (!to_intel_crtc(c)->active)
+ if (!to_intel_crtc_state(c->state)->uapi.active)
continue;
state = to_intel_plane_state(c->primary->state);
@@ -3221,6 +3223,12 @@ intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc,
* pretend the BIOS never had it enabled.
*/
intel_plane_disable_noatomic(intel_crtc, intel_plane);
+ if (crtc_state->bigjoiner) {
+ struct intel_crtc *slave =
+ crtc_state->bigjoiner_linked_crtc;
+
+ intel_plane_disable_noatomic(slave,
to_intel_plane(slave->base.primary));
+ }
return;
@@ -9918,6 +9926,7 @@ static void
skylake_get_initial_plane_config(struct intel_crtc *crtc,
struct intel_initial_plane_config
*plane_config)
{
+ struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
@@ -10021,6 +10030,18 @@ skylake_get_initial_plane_config(struct intel_crtc
*crtc,
fb->height = ((val >> 16) & 0x) + 1;
fb->width = ((val >> 0) & 0x) + 1;
+ /* add bigjoiner slave as well, if the fb stretches both */
+ if (crtc_state->bigjoiner) {
+ enum pipe bigjoiner_pipe =
crtc_state->bigjoiner_linked_crtc->pipe;
+
+ if (fb->width == crtc_state->pipe_src_w &&
+ (I915_READ(PLANE_SURF(bigjoiner_pipe, plane_id)) &
0xf000) == plane_config->base) {
+ val =
I915_READ(PLANE_SIZE(crtc_state->bigjoiner_linked_crtc->pipe, plane_id));
+ fb->height += ((val >> 16) & 0xfff) + 1;
+ fb->width += ((val >> 0) & 0x1fff) + 1;
+ }
+ }
+
val = I915_READ(PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
@@ -16814,7 +16835,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
/* Adjust the state of the output pipe according to whether we
* have active connectors/encoders. */
- if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc))
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+ !crtc_state->bigjoiner_slave)
intel_crtc_disable_noatomic(&crtc->base, ctx);
if (crtc_state->hw.active || HAS_GMCH(dev_priv)) {
@@ -17136,6 +17158,9 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
struct intel_plane *plane;
int min_cdclk = 0;
+ if (crtc_state->bigjoiner_slave)
+ continue;
+
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
if (crtc_state->hw.active) {
intel_mode_from_pipe_config(&crtc->base.mode,
crtc_state);
@@ -17144,7 +17169,8 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode,
crtc_state);
crtc_state->hw.mode = crtc->base.mode;
- WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state,
&crtc->base.mode));
+ if (!crtc_state->bigjoiner_slave)
+
WARN_ON(drm_atom
Re: [Intel-gfx] [PATCH 2/9] drm/print: add drm_debug_enabled()
On Monday, 2019-09-16 16:23:13 +0300, Jani Nikula wrote:
> On Mon, 16 Sep 2019, Eric Engestrom wrote:
> > On Monday, 2019-09-16 11:53:24 +0300, Jani Nikula wrote:
> >> On Fri, 13 Sep 2019, Eric Engestrom wrote:
> >> > On Friday, 2019-09-13 14:51:39 +0300, Jani Nikula wrote:
> >> >> Add helper to check if a drm debug category is enabled. Convert drm core
> >> >> to use it. No functional changes.
> >> >>
> >> >> Signed-off-by: Jani Nikula
> >> >> ---
> >> >> drivers/gpu/drm/drm_atomic_uapi.c | 2 +-
> >> >> drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++---
> >> >> drivers/gpu/drm/drm_edid.c| 2 +-
> >> >> drivers/gpu/drm/drm_edid_load.c | 2 +-
> >> >> drivers/gpu/drm/drm_mipi_dbi.c| 4 ++--
> >> >> drivers/gpu/drm/drm_print.c | 4 ++--
> >> >> drivers/gpu/drm/drm_vblank.c | 6 +++---
> >> >> include/drm/drm_print.h | 5 +
> >> >> 8 files changed, 18 insertions(+), 13 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> >> >> b/drivers/gpu/drm/drm_atomic_uapi.c
> >> >> index 5a5b42db6f2a..6576cd997cbd 100644
> >> >> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> >> >> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> >> >> @@ -1406,7 +1406,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> >> >> } else if (arg->flags & DRM_MODE_ATOMIC_NONBLOCK) {
> >> >> ret = drm_atomic_nonblocking_commit(state);
> >> >> } else {
> >> >> - if (unlikely(drm_debug & DRM_UT_STATE))
> >> >> + if (unlikely(drm_debug_enabled(DRM_UT_STATE)))
> >> >> drm_atomic_print_state(state);
> >> >>
> >> >> ret = drm_atomic_commit(state);
> >> >> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> >> >> b/drivers/gpu/drm/drm_dp_mst_topology.c
> >> >> index 97216099a718..f47c5b6b51f7 100644
> >> >> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> >> >> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> >> >> @@ -1180,7 +1180,7 @@ static int drm_dp_mst_wait_tx_reply(struct
> >> >> drm_dp_mst_branch *mstb,
> >> >> }
> >> >> }
> >> >> out:
> >> >> - if (unlikely(ret == -EIO && drm_debug & DRM_UT_DP)) {
> >> >> + if (unlikely(ret == -EIO && drm_debug_enabled(DRM_UT_DP))) {
> >> >> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
> >> >>
> >> >> drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
> >> >> @@ -2321,7 +2321,7 @@ static int process_single_tx_qlock(struct
> >> >> drm_dp_mst_topology_mgr *mgr,
> >> >> idx += tosend + 1;
> >> >>
> >> >> ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
> >> >> - if (unlikely(ret && drm_debug & DRM_UT_DP)) {
> >> >> + if (unlikely(ret && drm_debug_enabled(DRM_UT_DP))) {
> >> >> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
> >> >>
> >> >> drm_printf(&p, "sideband msg failed to send\n");
> >> >> @@ -2388,7 +2388,7 @@ static void drm_dp_queue_down_tx(struct
> >> >> drm_dp_mst_topology_mgr *mgr,
> >> >> mutex_lock(&mgr->qlock);
> >> >> list_add_tail(&txmsg->next, &mgr->tx_msg_downq);
> >> >>
> >> >> - if (unlikely(drm_debug & DRM_UT_DP)) {
> >> >> + if (unlikely(drm_debug_enabled(DRM_UT_DP))) {
> >> >> struct drm_printer p = drm_debug_printer(DBG_PREFIX);
> >> >>
> >> >> drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
> >> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> >> index 12c783f4d956..58dad4d24cd4 100644
> >> >> --- a/drivers/gpu/drm/drm_edid.c
> >> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> >> @@ -1551,7 +1551,7 @@ static void connector_bad_edid(struct
> >> >> drm_connector *connector,
> >> >> {
> >> >> int i;
> >> >>
> >> >> - if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
> >> >> + if (connector->bad_edid_counter++ &&
> >> >> !drm_debug_enabled(DRM_UT_KMS))
> >> >> return;
> >> >>
> >> >> dev_warn(connector->dev->dev,
> >> >> diff --git a/drivers/gpu/drm/drm_edid_load.c
> >> >> b/drivers/gpu/drm/drm_edid_load.c
> >> >> index d38b3b255926..37d8ba3ddb46 100644
> >> >> --- a/drivers/gpu/drm/drm_edid_load.c
> >> >> +++ b/drivers/gpu/drm/drm_edid_load.c
> >> >> @@ -175,7 +175,7 @@ static void *edid_load(struct drm_connector
> >> >> *connector, const char *name,
> >> >> u8 *edid;
> >> >> int fwsize, builtin;
> >> >> int i, valid_extensions = 0;
> >> >> - bool print_bad_edid = !connector->bad_edid_counter ||
> >> >> (drm_debug & DRM_UT_KMS);
> >> >> + bool print_bad_edid = !connector->bad_edid_counter ||
> >> >> drm_debug_enabled(DRM_UT_KMS);
> >> >>
> >> >> builtin = match_string(generic_edid_name, GENERIC_EDIDS, name);
> >> >> if (builtin >= 0) {
> >> >> diff --git a/drivers/gpu/drm/drm_mipi_dbi.c
> >> >> b/drivers/gpu/drm/drm_mipi_dbi.c
> >> >> index f8154316a3b0..
Re: [Intel-gfx] [v3][PATCH 1/3] drm/i915/color: Fix formatting issues
On Thu, 19 Sep 2019, Swati Sharma wrote:
> Fixed few formatting issues in multi-segmented load_lut().
>
> v3: -style nitting [Jani]
> -balanced parentheses moved from patch 2 to 1 [Jani]
> -subject prefix change [Jani]
> -added commit message [Jani]
>
> Signed-off-by: Swati Sharma
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 34
> ++
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 318308d..765482d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut
> *color)
> u32 i;
>
> /*
> - * Every entry in the multi-segment LUT is corresponding to a superfine
> - * segment step which is 1/(8 * 128 * 256).
> + * Program Super Fine segment (let's call it seg1)...
>*
> - * Superfine segment has 9 entries, corresponding to values
> - * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
> + * Super Fine segment's step is 1/(8 * 128 * 256) and it has
> + * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
> + * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
>*/
> I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
>
> @@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut
> *color)
> u32 i;
>
> /*
> - *
>* Program Fine segment (let's call it seg2)...
>*
> - * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256)
> - * ... 256/(128*256). So in order to program fine segment of LUT we
> - * need to pick every 8'th entry in LUT, and program 256 indexes.
> + * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 *
> 256)
> + * ... 256/(128 * 256). So in order to program fine segment of LUT we
> + * need to pick every 8th entry in the LUT, and program 256 indexes.
>*
>* PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
> - * with seg2[0] being unused by the hardware.
> + * seg2[0] being unused by the hardware.
>*/
> I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> for (i = 1; i < 257; i++) {
> entry = &lut[i * 8];
> I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
> @@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut
> *color)
> /*
>* Program Coarse segment (let's call it seg3)...
>*
> - * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
> - * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
> + * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
> + * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
>* above, we need to pick every (8 * 128)th entry in LUT, and
>* program 256 of those.
>*
> @@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state
> *crtc_state)
> case GAMMA_MODE_MODE_8BIT:
> i9xx_load_luts(crtc_state);
> break;
> -
> case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> icl_program_gamma_superfine_segment(crtc_state);
> icl_program_gamma_multi_segment(crtc_state);
> break;
> -
> default:
> bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
> ivb_load_lut_ext_max(crtc);
> @@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc)
> else
> dev_priv->display.color_commit = ilk_color_commit;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> - } else if (INTEL_GEN(dev_priv) >= 8)
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> dev_priv->display.load_luts = bdw_load_luts;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> dev_priv->display.load_luts = ivb_load_luts;
> - else {
> + } else {
> dev_priv->display.load_luts = ilk_load_luts;
> dev_priv->display.read_luts = ilk_read_luts;
> }
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Move the SAMPLER_MODE setup into the context
== Series Details == Series: drm/i915/tgl: Move the SAMPLER_MODE setup into the context URL : https://patchwork.freedesktop.org/series/66954/ State : success == Summary == CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14465_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_14465_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl2/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-apl8/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb4/igt@gem_exec_balan...@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +20 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb5/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb8/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb1/igt@gem_exec_sched...@preempt-queue-contexts-chain-bsd.html * igt@i915_selftest@mock_fence: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@i915_selftest@mock_fence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb7/igt@i915_selftest@mock_fence.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#105767]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-suspend: - shard-kbl: [PASS][13] -> [FAIL][14] ([fdo#103375]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl1/igt@kms_f...@flip-vs-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-kbl1/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl1/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-skl5/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_psr2_su@page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb5/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl10/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14465/shard-skl3/igt@kms_vbl...@pipe-c-ts-continuation-suspend.html * igt@kms_vblank@pipe-c-wait-forked-busy-hang: - shard-hsw: [P
Re: [Intel-gfx] [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
On Thu, 19 Sep 2019, Swati Sharma wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> Following are the main changes done in this patch:
> 1. gamma_enable checks made specific to platform func()
>since icl doeesn't support that and enable gamma through mode
> 2. lut[0] and lut[8] enteries should be same superfine and coarse;
>superfine and fine segments respectively, checked twice-no harm
> 3. Removed temporary lut
> 4. Coarse segment interpolated gamma values loop start from 2
>instead of 0, since actual h/w values started getting overrided.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
>
> Signed-off-by: Swati Sharma
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 216
> +++--
> drivers/gpu/drm/i915/i915_reg.h| 7 +
> 2 files changed, 208 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 765482d..ad548ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state
> *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct
> intel_crtc_state *crtc_state)
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
> *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_gamma_precision(crtc_state);
> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
>
[Intel-gfx] [PATCH v9 01/10] drm/i915/dsb: feature flag added for display state buffer.
Display State Buffer(DSB) is a new hardware capability, introduced
in GEN12 display. DSB allows a driver to batch-program display HW
registers.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4faec2f94e19..84b9b138d7ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1863,6 +1863,8 @@ static inline struct drm_i915_private
*pdev_to_i915(struct pci_dev *pdev)
(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
INTEL_INFO(dev_priv)->gen == (n))
+#define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
+
/*
* Return true if revision is in range [since,until] inclusive.
*
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index d4c288860aed..0cdc2465534b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -135,6 +135,7 @@ enum intel_ppgtt_type {
func(has_csr); \
func(has_ddi); \
func(has_dp_mst); \
+ func(has_dsb); \
func(has_fbc); \
func(has_gmch); \
func(has_hotplug); \
--
2.22.0
___
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[Intel-gfx] [PATCH v9 00/10] DSB enablement.
Display State Buffer (DSB) is hardware capability which allows driver to batch submit HW programming. As part of initial enablement common api created which currently used to program gamma lut proramming. Going forwad DSB support can be added for HDR and flip related operation. HSDES: 1209978241 BSpec: 32020 v1: Initial version. v2: Move intel_dsb files under display folder and fixed an issue. v3: As per review comments from Chris and Jani, - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) - Simplified and optimized code few places. (Chris) - Called dsb-api directly in callsites instead going via I915_WRITE. (Jani) v4: Addressed review commnets from Shashank. v5: Addressed review commnets from Shashank and Jani. v6: Addressed review commnets from Shashank. v7: Addressed review commnets from Shashank and Jani. v8: Addressed review commnets from Shashank and Jani. v9: Addressed review commnets from Jani. Animesh Manna (10): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: single register write function for DSB. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. drm/i915/dsb: Documentation for DSB. Documentation/gpu/i915.rst| 9 + drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_color.c| 63 ++-- .../drm/i915/display/intel_display_types.h| 3 + drivers/gpu/drm/i915/display/intel_dsb.c | 337 ++ drivers/gpu/drm/i915/display/intel_dsb.h | 50 +++ drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 3 +- drivers/gpu/drm/i915/i915_reg.h | 10 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 10 files changed, 457 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 02/10] drm/i915/dsb: DSB context creation.
This patch adds a function, which will internally get the gem buffer
for DSB engine. The GEM buffer is from global GTT, and is mapped into
CPU domain, contains the data + opcode to be feed to DSB engine.
v1: Initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can be derived through vma object. (Chris)
v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank)
v4: for simplification and based on current usage added single dsb
object in intel_crtc. (Shashank)
v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank)
v6:
- refcount machanism added.
- Used atomic_add_return and atomic_dec_and_test instead of
atomic_inc and atomic_dec. (Jani)
Cc: Imre Deak
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_types.h| 3 +
drivers/gpu/drm/i915/display/intel_dsb.c | 80 +++
drivers/gpu/drm/i915/display/intel_dsb.h | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
5 files changed, 116 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c
create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 658b930d34a8..6313e7b4bd78 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -172,6 +172,7 @@ i915-y += \
display/intel_display_power.o \
display/intel_dpio_phy.o \
display/intel_dpll_mgr.o \
+ display/intel_dsb.o \
display/intel_fbc.o \
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..49c902b00484 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1033,6 +1033,9 @@ struct intel_crtc {
/* scalers available on this crtc */
int num_scalers;
+
+ /* per pipe DSB related info */
+ struct intel_dsb dsb;
};
struct intel_plane {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
new file mode 100644
index ..2ed277670f15
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+
+struct intel_dsb *
+intel_dsb_get(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(dev);
+ struct intel_dsb *dsb = &crtc->dsb;
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ intel_wakeref_t wakeref;
+
+ if (!HAS_DSB(i915))
+ return dsb;
+
+ if (atomic_add_return(1, &dsb->refcount) != 1)
+ return dsb;
+
+ dsb->id = DSB1;
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Gem object creation failed\n");
+ goto err;
+ }
+
+ mutex_lock(&i915->drm.struct_mutex);
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("Vma creation failed\n");
+ i915_gem_object_put(obj);
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+
+ dsb->cmd_buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
+ if (IS_ERR(dsb->cmd_buf)) {
+ DRM_ERROR("Command buffer creation failed\n");
+ i915_vma_unpin_and_release(&vma, 0);
+ dsb->cmd_buf = NULL;
+ atomic_dec(&dsb->refcount);
+ goto err;
+ }
+ dsb->vma = vma;
+
+err:
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+ return dsb;
+}
+
+void intel_dsb_put(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!HAS_DSB(i915))
+ return;
+
+ if (WARN_ON(atomic_read(&dsb->refcount) == 0))
+ return;
+
+ if (atomic_dec_and_test(&dsb->refcount)) {
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_gem_object_unpin_map(dsb->vma->obj);
+ i915_vma_unpin_and_release(&dsb->vma, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
+ dsb->cmd_buf = NULL;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/d
[Intel-gfx] [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. DSB feature can be used for bulk register
programming e.g. gamma lut programming, HDR meta data programming.
v1: initial version.
v2: simplified code by using ALIGN(). (Chris)
v3: ascii table added as code comment. (Shashank)
v4: cosmetic changes done. (Shashank)
v5: reset ins_start_offset. (Jani)
v6: update ins_start_offset in inel_dsb_reg_write.
Cc: Shashank Sharma
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 68
drivers/gpu/drm/i915/display/intel_dsb.h | 9
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index f94cd6dc98b6..faa853b08458 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -12,8 +12,10 @@
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_OPCODE_INDEXED_WRITE 0x9
#define DSB_BYTE_EN0xF
#define DSB_BYTE_EN_SHIFT 20
+#define DSB_REG_VALUE_MASK 0xf
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
@@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
}
}
+void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
+u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+ u32 reg_val;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
+ }
+
+ /*
+* For example the buffer will look like below for 3 dwords for auto
+* increment register:
+* ++
+* | size = 3 | offset &| value1 | value2 | value3 | zero |
+* | | opcode |||||
+* ++
+* + + +++++
+* 0 4 812 16 20 24
+* Byte
+*
+* As every instruction is 8 byte aligned the index of dsb instruction
+* will start always from even number while dealing with u32 array. If
+* we are writing odd no of dwords, Zeros will be added in the end for
+* padding.
+*/
+ reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+ if (reg_val != i915_mmio_reg_offset(reg)) {
+ /* Every instruction should be 8 byte aligned. */
+ dsb->free_pos = ALIGN(dsb->free_pos, 2);
+
+ dsb->ins_start_offset = dsb->free_pos;
+
+ /* Update the size. */
+ buf[dsb->free_pos++] = 1;
+
+ /* Update the opcode and reg. */
+ buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
+ DSB_OPCODE_SHIFT) |
+ i915_mmio_reg_offset(reg);
+
+ /* Update the value. */
+ buf[dsb->free_pos++] = val;
+ } else {
+ /* Update the new value. */
+ buf[dsb->free_pos++] = val;
+
+ /* Update the size. */
+ buf[dsb->ins_start_offset]++;
+ }
+
+ /* if number of data words is odd, then the last dword should be 0.*/
+ if (dsb->free_pos & 0x1)
+ buf[dsb->free_pos] = 0;
+}
+
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
return;
}
+ dsb->ins_start_offset = dsb->free_pos;
buf[dsb->free_pos++] = val;
buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 0686d67b34d5..2ae22f7309a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -30,11 +30,20 @@ struct intel_dsb {
* and help in calculating tail of command buffer.
*/
int free_pos;
+
+ /*
+* ins_start_offset will help to store start addres
[Intel-gfx] [PATCH v9 03/10] drm/i915/dsb: single register write function for DSB.
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
v1: Initial version.
v2: Unused macro removed and cosmetic changes done. (Shashank)
v3: set free_pos to zero in dsb-put() instead dsb-get() and
a cosmetic change. (Shashank)
v4: macro of indexed-write is moved. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 29
drivers/gpu/drm/i915/display/intel_dsb.h | 9
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2ed277670f15..f94cd6dc98b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,12 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/* DSB opcodes. */
+#define DSB_OPCODE_SHIFT 24
+#define DSB_OPCODE_MMIO_WRITE 0x1
+#define DSB_BYTE_EN0xF
+#define DSB_BYTE_EN_SHIFT 20
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -76,5 +82,28 @@ void intel_dsb_put(struct intel_dsb *dsb)
i915_vma_unpin_and_release(&dsb->vma, 0);
mutex_unlock(&i915->drm.struct_mutex);
dsb->cmd_buf = NULL;
+ dsb->free_pos = 0;
+ }
+}
+
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ u32 *buf = dsb->cmd_buf;
+
+ if (!buf) {
+ I915_WRITE(reg, val);
+ return;
+ }
+
+ if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
+ DRM_DEBUG_KMS("DSB buffer overflow\n");
+ return;
}
+
+ buf[dsb->free_pos++] = val;
+ buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 2c0f60c5f66c..0686d67b34d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -6,6 +6,8 @@
#ifndef _INTEL_DSB_H
#define _INTEL_DSB_H
+#include "i915_reg.h"
+
struct intel_crtc;
struct i915_vma;
@@ -22,10 +24,17 @@ struct intel_dsb {
enum dsb_id id;
u32 *cmd_buf;
struct i915_vma *vma;
+
+ /*
+* free_pos will point the first free entry position
+* and help in calculating tail of command buffer.
+*/
+ int free_pos;
};
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc);
void intel_dsb_put(struct intel_dsb *dsb);
+void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
#endif
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 08/10] drm/i915/dsb: Enable gamma lut programming using DSB.
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in future
based on need.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
v3:
- modified the code as per single dsb instance per crtc. (Shashank)
- Added dsb get/put call in platform specific load_lut hook. (Jani)
- removed dsb pointer from dev_priv. (Jani)
v4: simplified code by dropping ref-count implementation. (Shashank)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_color.c | 63 ++
1 file changed, 41 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308dc136c..40af3fe2c3c9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -611,12 +611,13 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Program the max register to clamp values > 1.0. */
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16);
/*
* Program the gc max 2 register to clamp values > 1.0.
@@ -624,10 +625,15 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
* from 3.0 to 7.0
*/
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), 1 << 16);
- I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ 1 << 16);
+ intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ 1 << 16);
}
+
+ intel_dsb_put(dsb);
}
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
@@ -787,22 +793,23 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
/* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), color->red);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), color->green);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ intel_dsb_put(dsb);
}
static void
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *blob = crtc_state->base.gamma_lut;
const struct drm_color_lut *lut = blob->data;
+ struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
u32 i;
@@ -813,26 +820,29 @@ icl_program_gamma_superfine_segment(const struct
intel_crtc_state *crtc_state)
* Superfine segment has 9 entries, corresponding to values
* 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) 8/(8 * 128 * 256).
*/
- I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+ intel_dsb_reg_write(dsb, PREC_PAL_MULTI_SEG_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
for (i = 0; i < 9; i++) {
const struct drm_color_lut *entry = &lut[i];
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_ldw(entry));
- I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe),
- ilk_lut_12p4_udw(entry));
+ intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
+
[Intel-gfx] [PATCH v9 05/10] drm/i915/dsb: Check DSB engine status.
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index faa853b08458..650b18a6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -17,6 +17,15 @@
#define DSB_BYTE_EN_SHIFT 20
#define DSB_REG_VALUE_MASK 0xf
+static inline bool is_dsb_busy(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f8f52ae6cc6f..01952fae5348 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11684,4 +11684,11 @@ enum skl_power_gate {
#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE 0x70B00
+#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_STATUS (1 << 0)
+
#endif /* _I915_REG_H_ */
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 07/10] drm/i915/dsb: function to trigger workload execution of DSB.
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code few places. (Chris)
v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank)
v4: reset ins_start_offset after commit. (Jani)
Cc: Imre Deak
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 43
drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6fb4529689f1..f4c0b37683a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -224,3 +224,46 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
(DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
i915_mmio_reg_offset(reg);
}
+
+void intel_dsb_commit(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tail;
+
+ if (!dsb->free_pos)
+ return;
+
+ if (!intel_dsb_enable_engine(dsb))
+ goto reset;
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(&dsb->cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dsb)) {
+ DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n");
+ goto reset;
+ }
+ DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dsb), 1)) {
+ DRM_ERROR("Timed out waiting for DSB workload completion.\n");
+ goto reset;
+ }
+
+reset:
+ dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
+ intel_dsb_disable_engine(dsb);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
b/drivers/gpu/drm/i915/display/intel_dsb.h
index 2ae22f7309a7..c77ce76fd226 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -45,5 +45,6 @@ void intel_dsb_put(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val);
+void intel_dsb_commit(struct intel_dsb *dsb);
#endif
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0ef2f3be5d30..22e3e610c649 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11688,6 +11688,8 @@ enum skl_power_gate {
#define _DSBSL_INSTANCE_BASE 0x70B00
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 10/10] drm/i915/dsb: Documentation for DSB.
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
drivers/gpu/drm/i915/display/intel_dsb.c | 68
2 files changed, 77 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index e249ea7b0ec7..465779670fd4 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -246,6 +246,15 @@ Display PLLs
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
:internal:
+Display State Buffer
+
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :doc: DSB
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
+ :internal:
+
Memory Management and Command Submission
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index f4c0b37683a5..0a0a1536ac96 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -9,6 +9,23 @@
#define DSB_BUF_SIZE(2 * PAGE_SIZE)
+/**
+ * DOC: DSB
+ *
+ * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
+ * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
+ * engine that can be programmed to download the DSB from memory.
+ * It allows driver to batch submit display HW programming. This helps to
+ * reduce loading time and CPU activity, thereby making the context switch
+ * faster. DSB Support added from Gen12 Intel graphics based platform.
+ *
+ * DSB's can access only the pipe, plane, and transcoder Data Island Packet
+ * registers.
+ *
+ * DSB HW can support only register writes (both indexed and direct MMIO
+ * writes). There are no registers reads possible with DSB HW engine.
+ */
+
/* DSB opcodes. */
#define DSB_OPCODE_SHIFT 24
#define DSB_OPCODE_MMIO_WRITE 0x1
@@ -66,6 +83,17 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb
*dsb)
return true;
}
+/**
+ * intel_dsb_get() - Allocate DSB context and return a DSB instance.
+ * @crtc: intel_crtc structure to get pipe info.
+ *
+ * This function provides handle of a DSB instance, for the further DSB
+ * operations.
+ *
+ * Returns: address of Intel_dsb instance requested for.
+ * Failure: Returns the same DSB instance, but without a command buffer.
+ */
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
@@ -116,6 +144,14 @@ intel_dsb_get(struct intel_crtc *crtc)
return dsb;
}
+/**
+ * intel_dsb_put() - To destroy DSB context.
+ * @dsb: intel_dsb structure.
+ *
+ * This function destroys the DSB context allocated by a dsb_get(), by
+ * unpinning and releasing the VMA object associated with it.
+ */
+
void intel_dsb_put(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -138,6 +174,19 @@ void intel_dsb_put(struct intel_dsb *dsb)
}
}
+/**
+ * intel_dsb_indexed_reg_write() -Write to the DSB context for auto
+ * increment register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB for auto-increment register. During command buffer overflow,
+ * a warning is thrown and rest all erroneous condition register programming
+ * is done through mmio write.
+ */
+
void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
u32 val)
{
@@ -202,6 +251,18 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb,
i915_reg_t reg,
buf[dsb->free_pos] = 0;
}
+/**
+ * intel_dsb_reg_write() -Write to the DSB context for normal
+ * register.
+ * @dsb: intel_dsb structure.
+ * @reg: register address.
+ * @val: value.
+ *
+ * This function is used for writing register-value pair in command
+ * buffer of DSB. During command buffer overflow, a warning is thrown
+ * and rest all erroneous condition register programming is done
+ * through mmio write.
+ */
void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
@@ -225,6 +286,13 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t
reg, u32 val)
i915_mmio_reg_offset(reg);
}
+/**
+ * intel_dsb_commit() - Trigger workload execution of DSB.
+ * @dsb: intel_dsb structure.
+ *
+ * This function is used to do actual write to hardware using DSB.
+ * On errors, fall back to MMIO. Also this function help to reset the context.
+ */
void intel_dsb_commit(struct intel_dsb *dsb)
{
struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
--
2.22.0
__
[Intel-gfx] [PATCH v9 09/10] drm/i915/dsb: Enable DSB for gen12.
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fe6941c8fc99..c2faa679658c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -787,7 +787,8 @@ static const struct intel_device_info
intel_elkhartlake_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- .has_global_mocs = 1
+ .has_global_mocs = 1, \
+ .display.has_dsb = 1
static const struct intel_device_info intel_tigerlake_12_info = {
GEN12_FEATURES,
--
2.22.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v9 06/10] drm/i915/dsb: functions to enable/disable DSB engine.
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Reviewed-by: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 40
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 650b18a6..6fb4529689f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
}
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl |= DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 dsb_ctrl;
+
+ dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+ if (DSB_STATUS & dsb_ctrl) {
+ DRM_DEBUG_KMS("DSB engine is busy.\n");
+ return false;
+ }
+
+ dsb_ctrl &= ~DSB_ENABLE;
+ I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+ POSTING_READ(DSB_CTRL(pipe, dsb->id));
+ return true;
+}
+
struct intel_dsb *
intel_dsb_get(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 01952fae5348..0ef2f3be5d30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11689,6 +11689,7 @@ enum skl_power_gate {
#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \
(pipe) * 0x1000 + (id) * 100)
#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define DSB_ENABLE (1 << 31)
#define DSB_STATUS (1 << 0)
#endif /* _I915_REG_H_ */
--
2.22.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mdev based hardware virtio offloading support
== Series Details == Series: mdev based hardware virtio offloading support URL : https://patchwork.freedesktop.org/series/66989/ State : warning == Summary == $ dim checkpatch origin/drm-tip 32afcef2acff mdev: class id support 8efae9b60a78 mdev: introduce device specific ops -:309: ERROR:CODE_INDENT: code indent should use tabs where possible #309: FILE: include/linux/mdev.h:111: + const struct mdev_parent_ops *ops);$ -:309: WARNING:LEADING_SPACE: please, no spaces at the start of a line #309: FILE: include/linux/mdev.h:111: + const struct mdev_parent_ops *ops);$ -:314: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #314: new file mode 100644 total: 1 errors, 2 warnings, 0 checks, 410 lines checked 7bbada3ad14d mdev: introduce virtio device and its device ops -:50: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #50: new file mode 100644 -:55: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #55: FILE: include/linux/virtio_mdev.h:1: +/* -:70: WARNING:FUNCTION_ARGUMENTS: function definition argument 'void *' should also have an identifier name #70: FILE: include/linux/virtio_mdev.h:16: + irqreturn_t (*callback)(void *); -:175: ERROR:CODE_INDENT: code indent should use tabs where possible #175: FILE: include/linux/virtio_mdev.h:121: +/* Device ops */$ -:186: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #186: FILE: include/linux/virtio_mdev.h:132: + void (*get_config)(struct mdev_device *mdev, unsigned offset, -:187: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #187: FILE: include/linux/virtio_mdev.h:133: + void *buf, unsigned len); -:188: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #188: FILE: include/linux/virtio_mdev.h:134: + void (*set_config)(struct mdev_device *mdev, unsigned offset, -:189: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #189: FILE: include/linux/virtio_mdev.h:135: + const void *buf, unsigned len); total: 1 errors, 7 warnings, 0 checks, 168 lines checked 61e824bf250a virtio: introudce a mdev based transport -:44: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #44: new file mode 100644 -:84: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #84: FILE: drivers/vfio/mdev/virtio_mdev.c:36: + spinlock_t lock; -:111: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #111: FILE: drivers/vfio/mdev/virtio_mdev.c:63: +static void virtio_mdev_get(struct virtio_device *vdev, unsigned offset, -:112: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #112: FILE: drivers/vfio/mdev/virtio_mdev.c:64: + void *buf, unsigned len) -:120: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #120: FILE: drivers/vfio/mdev/virtio_mdev.c:72: +static void virtio_mdev_set(struct virtio_device *vdev, unsigned offset, -:121: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #121: FILE: drivers/vfio/mdev/virtio_mdev.c:73: + const void *buf, unsigned len) -:189: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #189: FILE: drivers/vfio/mdev/virtio_mdev.c:141: +virtio_mdev_setup_vq(struct virtio_device *vdev, unsigned index, -:268: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #268: FILE: drivers/vfio/mdev/virtio_mdev.c:220: + +} -:294: WARNING:RETURN_VOID: void function return statements are not generally useful #294: FILE: drivers/vfio/mdev/virtio_mdev.c:246: + return; +} -:296: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #296: FILE: drivers/vfio/mdev/virtio_mdev.c:248: +static int virtio_mdev_find_vqs(struct virtio_device *vdev, unsigned nvqs, -:308: WARNING:LINE_SPACING: Missing a blank line after declarations #308: FILE: drivers/vfio/mdev/virtio_mdev.c:260: + int i, err, queue_idx = 0; + vm_dev->vqs = kmalloc_array(queue_idx, sizeof(*vm_dev->vqs), -:429: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #429: FILE: drivers/vfio/mdev/virtio_mdev.c:381: + +} total: 0 errors, 9 warnings, 3 checks, 432 lines checked 17f868b5d9a4 vringh: fix copy direction of vringh_iov_push_kern() 822c68b1ca18 docs: Sample driver to demonstrate how to implement virtio-mdev framework -:26: WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully #26: FILE: samples/Kconfig:134: +config SAMPLE_VIRTIO_MDEV_NET -:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #46: new file mode 100644 -:118: WARNING:FUNCTION_ARGUMENTS: function definition a
Re: [Intel-gfx] [PATCH v9 04/10] drm/i915/dsb: Indexed register write function for DSB.
On Fri, 20 Sep 2019, Animesh Manna wrote:
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. DSB feature can be used for bulk register
> programming e.g. gamma lut programming, HDR meta data programming.
>
> v1: initial version.
> v2: simplified code by using ALIGN(). (Chris)
> v3: ascii table added as code comment. (Shashank)
> v4: cosmetic changes done. (Shashank)
> v5: reset ins_start_offset. (Jani)
> v6: update ins_start_offset in inel_dsb_reg_write.
>
> Cc: Shashank Sharma
> Cc: Imre Deak
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Reviewed-by: Shashank Sharma
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 68
> drivers/gpu/drm/i915/display/intel_dsb.h | 9
> 2 files changed, 77 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index f94cd6dc98b6..faa853b08458 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -12,8 +12,10 @@
> /* DSB opcodes. */
> #define DSB_OPCODE_SHIFT 24
> #define DSB_OPCODE_MMIO_WRITE0x1
> +#define DSB_OPCODE_INDEXED_WRITE 0x9
> #define DSB_BYTE_EN 0xF
> #define DSB_BYTE_EN_SHIFT20
> +#define DSB_REG_VALUE_MASK 0xf
>
> struct intel_dsb *
> intel_dsb_get(struct intel_crtc *crtc)
> @@ -83,9 +85,74 @@ void intel_dsb_put(struct intel_dsb *dsb)
> mutex_unlock(&i915->drm.struct_mutex);
> dsb->cmd_buf = NULL;
> dsb->free_pos = 0;
> + dsb->ins_start_offset = 0;
> }
> }
>
> +void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> + u32 val)
> +{
> + struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 *buf = dsb->cmd_buf;
> + u32 reg_val;
> +
> + if (!buf) {
> + I915_WRITE(reg, val);
> + return;
> + }
> +
> + if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) {
> + DRM_DEBUG_KMS("DSB buffer overflow\n");
> + return;
> + }
> +
> + /*
> + * For example the buffer will look like below for 3 dwords for auto
> + * increment register:
> + * ++
> + * | size = 3 | offset &| value1 | value2 | value3 | zero |
> + * | | opcode |||||
> + * ++
> + * + + +++++
> + * 0 4 812 16 20 24
> + * Byte
> + *
> + * As every instruction is 8 byte aligned the index of dsb instruction
> + * will start always from even number while dealing with u32 array. If
> + * we are writing odd no of dwords, Zeros will be added in the end for
> + * padding.
> + */
> + reg_val = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
> + if (reg_val != i915_mmio_reg_offset(reg)) {
> + /* Every instruction should be 8 byte aligned. */
> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +
> + dsb->ins_start_offset = dsb->free_pos;
> +
> + /* Update the size. */
> + buf[dsb->free_pos++] = 1;
> +
> + /* Update the opcode and reg. */
> + buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE <<
> + DSB_OPCODE_SHIFT) |
> + i915_mmio_reg_offset(reg);
> +
> + /* Update the value. */
> + buf[dsb->free_pos++] = val;
> + } else {
> + /* Update the new value. */
> + buf[dsb->free_pos++] = val;
> +
> + /* Update the size. */
> + buf[dsb->ins_start_offset]++;
> + }
> +
> + /* if number of data words is odd, then the last dword should be 0.*/
> + if (dsb->free_pos & 0x1)
> + buf[dsb->free_pos] = 0;
> +}
> +
> void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> {
> struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> @@ -102,6 +169,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
> i915_reg_t reg, u32 val)
> return;
> }
>
> + dsb->ins_start_offset = dsb->free_pos;
Okay, I'm being a pedant, but that's kind of part of the job
description, I'm afraid.
What if:
intel_dsb_get()
intel_dsb_reg_write(dsb, FOO, 0);
intel_dsb_indexed_reg_write(dsb, FOO, 0);
intel_dsb_commit()
intel_dsb_put()
BR,
Jani.
> buf[dsb->free_pos++] = val;
> buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
> (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) |
> diff --git a/drivers/gpu/drm/i915/display/i
[Intel-gfx] [PATCH] drm/i915: Mark contents as dirty on a write fault
Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
Flush pages on acquisition"), we no longer mark the contents as dirty on
a write fault. This has the issue of us then not marking the pages as
dirty on releasing the buffer, which means the contents are not written
out to the swap device (should we ever pick that buffer as a victim).
Notably, this is visible in the dumb buffer interface used for cursors.
Having updated the cursor contents via mmap, and swapped away, if the
shrinker should evict the old cursor, upon next reuse, the cursor would
be invisible.
E.g. echo 80 > /proc/sys/kernel/sysrq ; echo f > /proc/sysrq-trigger
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111541
Fixes: a679f58d0510 ("drm/i915: Flush pages on acquisition")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Ville Syrjälä
Cc: # v5.2+
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1748e63156a2..860b751c51f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -319,7 +319,11 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
intel_wakeref_auto(&i915->ggtt.userfault_wakeref,
msecs_to_jiffies_timeout(CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND));
- i915_vma_set_ggtt_write(vma);
+ if (write) {
+ GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
+ i915_vma_set_ggtt_write(vma);
+ obj->mm.dirty = true;
+ }
err_fence:
i915_vma_unpin_fence(vma);
--
2.23.0
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Re: [Intel-gfx] [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Prepare the pipe csc for YCbCr output on ilk/snb. The main difference
> to IVB+ is the lack of explicit post offsets, and instead we must
> configure the CSC info RGB->YUV mode (which takes care of offsetting
> Cb/Cr properly) and enable the "black screen offset" bit to add the
> required offset to Y.
>
> And while at it throw some comments around the bit defines to
> document which platforms have which bits.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 25 +---
> --
> drivers/gpu/drm/i915/i915_reg.h| 10 -
> 2 files changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 736c42720daf..a902f7809840 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1213,6 +1213,21 @@ static u32 ilk_gamma_mode(const struct
> intel_crtc_state *crtc_state)
> return GAMMA_MODE_MODE_10BIT;
> }
>
> +static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
> +{
> + /*
> + * CSC comes after the LUT in RGB->YCbCr mode.
> + * RGB->YCbCr needs the limited range offsets added to
> + * the output. RGB limited range output is handled by
> + * the hw automagically elsewhere.
> + */
> + if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> + return CSC_BLACK_SCREEN_OFFSET;
> +
> + return CSC_MODE_YUV_TO_RGB |
> + CSC_POSITION_BEFORE_GAMMA;
> +}
> +
> static int ilk_color_check(struct intel_crtc_state *crtc_state)
> {
> int ret;
> @@ -1226,15 +1241,15 @@ static int ilk_color_check(struct
> intel_crtc_state *crtc_state)
> !crtc_state->c8_planes;
>
> /*
> - * We don't expose the ctm on ilk/snb currently,
> - * nor do we enable YCbCr output. Also RGB limited
> - * range output is handled by the hw automagically.
> + * We don't expose the ctm on ilk/snb currently, also RGB
> + * limited range output is handled by the hw automagically.
>*/
> - crtc_state->csc_enable = false;
> + crtc_state->csc_enable =
> + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
>
> crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
>
> - crtc_state->csc_mode = 0;
> + crtc_state->csc_mode = ilk_csc_mode(crtc_state);
>
> ret = intel_color_add_affected_planes(crtc_state);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 58471312b8b2..33d535ae0944 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10106,11 +10106,11 @@ enum skl_power_gate {
> #define _PIPE_A_CSC_COEFF_BV 0x49024
>
> #define _PIPE_A_CSC_MODE 0x49028
> -#define ICL_CSC_ENABLE (1 << 31)
> -#define ICL_OUTPUT_CSC_ENABLE (1 << 30)
> -#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
> -#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
> -#define CSC_MODE_YUV_TO_RGB (1 << 0)
> +#define ICL_CSC_ENABLE (1 << 31) /* icl+ */
> +#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
> +#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
> +#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
> +#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
>
> #define _PIPE_A_CSC_PREOFF_HI0x49030
> #define _PIPE_A_CSC_PREOFF_ME0x49034
The changes look good to me.
Reviewed-by: Gwan-gyeong Mun
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Re: [Intel-gfx] [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:03 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On HSW the pipe colorspace is configured via PIPECONF
> > (as opposed to PIPEMISC in BDW+). Let's configure+readout
> > that stuff correctly.
> >
> > Enablling YCbCr 4:4:4 output will now be a simple matter of
> Typo: Enablling -> Enabling
> > setting crtc_state->output_format appropriately in the encoder
> > .compute_config().
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 13 -
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 1dd1aa29a649..bd3ff96c1618 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9430,6 +9430,10 @@ static void haswell_set_pipeconf(const
> > struct
> > intel_crtc_state *crtc_state)
> > else
> > val |= PIPECONF_PROGRESSIVE;
> >
> > + if (IS_HASWELL(dev_priv) &&
> > + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> > + val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
> > +
> > I915_WRITE(PIPECONF(cpu_transcoder), val);
> > POSTING_READ(PIPECONF(cpu_transcoder));
> > }
> > @@ -10423,7 +10427,14 @@ static bool haswell_get_pipe_config(struct
> > intel_crtc *crtc,
> >
> > intel_get_pipe_src_size(crtc, pipe_config);
> >
> > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
> > + if (IS_HASWELL(dev_priv)) {
> > + u32 tmp = I915_READ(PIPECONF(pipe_config-
> > > cpu_transcoder));
> > +
> > + if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
> > + pipe_config->output_format =
> > INTEL_OUTPUT_FORMAT_YCBCR444;
> > + else
> > + pipe_config->output_format =
> > INTEL_OUTPUT_FORMAT_RGB;
> > + } else {
> > pipe_config->output_format =
> > bdw_get_pipemisc_output_format(crtc);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 66f7f417231f..58471312b8b2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5712,6 +5712,7 @@ enum {
> > #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
> > #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
> > #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
> > +#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /*
> > hsw only
> > */
> > #define PIPECONF_BPC_MASK(0x7 << 5)
> > #define PIPECONF_8BPC(0 << 5)
> > #define PIPECONF_10BPC (1 << 5)
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Re: [Intel-gfx] [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun
On Wed, 2019-09-18 at 19:05 +, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On ILK-IVB the pipe colorspace is configured via PIPECONF
> > (as opposed to PIPEMISC in BDW+). Let's configure+readout
> > that stuff correctly.
> >
> > Enablling YCbCr 4:4:4 output will now be a simple matter of
> Typo: Enablling -> Enabling
> > setting crtc_state->output_format appropriately in the encoder
> > .compute_config(). However, when we do that we must be
> > aware of the fact that YCbCr DP output doesn't seem to work
> > on ILK (resulting image is totally garbled), but on SNB+
> > it works fine. However HDMI YCbCr output does work correctly
> > even on ILK.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 21
> > +++-
> > drivers/gpu/drm/i915/i915_reg.h | 4
> > 2 files changed, 24 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index bd3ff96c1618..8e98715cd63b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9406,9 +9406,19 @@ static void ironlake_set_pipeconf(const
> > struct
> > intel_crtc_state *crtc_state)
> > else
> > val |= PIPECONF_PROGRESSIVE;
> >
> > + /*
> > +* This would end up with an odd purple hue over
> > +* the entire display. Make sure we don't do it.
> > +*/
> > + WARN_ON(crtc_state->limited_color_range &&
> > + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
> > +
> > if (crtc_state->limited_color_range)
> > val |= PIPECONF_COLOR_RANGE_SELECT;
> >
> > + if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> > + val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
> > +
> > val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >
> > I915_WRITE(PIPECONF(pipe), val);
> > @@ -9945,7 +9955,6 @@ static bool ironlake_get_pipe_config(struct
> > intel_crtc *crtc,
> > if (!wakeref)
> > return false;
> >
> > - pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> > pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> > pipe_config->shared_dpll = NULL;
> >
> > @@ -9974,6 +9983,16 @@ static bool ironlake_get_pipe_config(struct
> > intel_crtc *crtc,
> > if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> > pipe_config->limited_color_range = true;
> >
> > + switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
> > + case PIPECONF_OUTPUT_COLORSPACE_YUV601:
> > + case PIPECONF_OUTPUT_COLORSPACE_YUV709:
> > + pipe_config->output_format =
> > INTEL_OUTPUT_FORMAT_YCBCR444;
> > + break;
> > + default:
> > + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> > + break;
> > + }
> > +
> > pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK)
> > PIPECONF_GAMMA_MODE_SHIFT;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 33d535ae0944..3d33a1e03a45 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5712,6 +5712,10 @@ enum {
> > #define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
> > #define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
> > #define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
> > +#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
> > +#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
> > +#define PIPECONF_OUTPUT_COLORSPACE_YUV601(1 << 11) /*
> > ilk-ivb */
> > +#define PIPECONF_OUTPUT_COLORSPACE_YUV709(2 << 11) /*
> > ilk-ivb */
> > #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /*
> > hsw only
> > */
> > #define PIPECONF_BPC_MASK(0x7 << 5)
> > #define PIPECONF_8BPC(0 << 5)
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Re: [Intel-gfx] [PATCH] drm/i915: Mark contents as dirty on a write fault
Quoting Chris Wilson (2019-09-20 13:18:21)
> Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
> Flush pages on acquisition"), we no longer mark the contents as dirty on
> a write fault. This has the issue of us then not marking the pages as
> dirty on releasing the buffer, which means the contents are not written
> out to the swap device (should we ever pick that buffer as a victim).
> Notably, this is visible in the dumb buffer interface used for cursors.
> Having updated the cursor contents via mmap, and swapped away, if the
> shrinker should evict the old cursor, upon next reuse, the cursor would
> be invisible.
Hmm, I think the dumb interface may be missing a few steps around the
place to ensure the contents are flushed.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from overtaking each other on preemption
On 20/09/2019 09:36, Chris Wilson wrote:
Force bonded requests to run on distinct engines so that they cannot be
shuffled onto the same engine where timeslicing will reverse the order.
A bonded request will often wait on a semaphore signaled by its master,
creating an implicit dependency -- if we ignore that implicit dependency
and allow the bonded request to run on the same engine and before its
master, we will cause a GPU hang.
We can prevent this inversion by restricting which engines we allow
ourselves to jump to upon preemption, i.e. baking in the arrangement
established at first execution. (We should also consider capturing the
implicit dependency using i915_sched_add_dependency(), but first we need
to think about the constraints that requires on the execution/retirement
ordering.)
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
References: ee1136908e9b ("drm/i915/execlists: Virtual engine bonding")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a99166a2d2eb..7920649e4d87 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3755,18 +3755,21 @@ static void
virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
{
struct virtual_engine *ve = to_virtual_engine(rq->engine);
+ intel_engine_mask_t allowed, exec;
struct ve_bond *bond;
bond = virtual_find_bond(ve, to_request(signal)->engine);
- if (bond) {
- intel_engine_mask_t old, new, cmp;
+ if (!bond)
+ return;
- cmp = READ_ONCE(rq->execution_mask);
- do {
- old = cmp;
- new = cmp & bond->sibling_mask;
- } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old);
- }
+ /* Restrict the bonded request to run on only the slaved engines */
+ allowed = bond->sibling_mask & ~to_request(signal)->engine->mask;
Hmm.. isn't it a miss on the uapi level that we allow master to be
mentioned in the list of bonds? That's the only scenario where this line
does something I think. So should we just forbid this setup on the uapi
level?
+ exec = READ_ONCE(rq->execution_mask);
+ while (!try_cmpxchg(&rq->execution_mask, &exec, exec & allowed))
+ ;
+
+ /* Prevent the master from being re-run on the slaved engines */
+ to_request(signal)->execution_mask &= ~allowed;
This sounds unfortunate for future scheduling. There shouldn't be a
fundamental reason why next execution for the master couldn't be on an
engine which can also be a slave. So if we have:
master
.veng=vcs0,vcs1
slave
.veng=vcs0,vcs1
.bond(master=vcs0, mask=vcs1)
.bond(master=vcs1, mask=vcs0)
This should be allowed setup but with this change it would fix the
master to only be one of the options.
Is the real problem that after preemption for timeslicing and subsequent
re-submit we miss some hooks to re-evaluate the bonded relationship?
I guess looking would be hard to do any peeking from one submission
tasklet to another (different engines) to check if one of the pair is
already executing again and so to pick the other end correctly?
I think in practical terms for media this work since they are not
setting it up like my sketch shows. So it could be just fine in practice
for current users.
Regards,
Tvrtko
}
struct intel_context *
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add memory type decoding for bandwidth checking
On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> The memory type values have changed in TGL, so we need to translate them
> differently than ICL.
>
> BSpec: 53998
>
> Cc: Ville Syrjälä
> Cc: Stanislav Lisovskiy
> Signed-off-by: James Ausmus
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 59 ++---
> 1 file changed, 43 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 688858ebe4d0..11224d9a6752 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -35,22 +35,49 @@ static int icl_pcode_read_mem_global_info(struct
> drm_i915_private *dev_priv,
> if (ret)
> return ret;
>
> - switch (val & 0xf) {
> - case 0:
> - qi->dram_type = INTEL_DRAM_DDR4;
> - break;
> - case 1:
> - qi->dram_type = INTEL_DRAM_DDR3;
> - break;
> - case 2:
> - qi->dram_type = INTEL_DRAM_LPDDR3;
> - break;
> - case 3:
> - qi->dram_type = INTEL_DRAM_LPDDR3;
This should be LPDDR4 actually. Doesn't really matter but would be nice
to fix as well.
> - break;
> - default:
> - MISSING_CASE(val & 0xf);
> - break;
> + if (IS_GEN(dev_priv, 12)) {
> + switch (val & 0xf) {
> + case 0:
> + qi->dram_type = INTEL_DRAM_DDR4;
> + break;
> + case 3:
> + qi->dram_type = INTEL_DRAM_LPDDR4;
> + break;
> + case 4:
> + qi->dram_type = INTEL_DRAM_DDR3;
> + break;
> + case 5:
> + qi->dram_type = INTEL_DRAM_LPDDR3;
> + break;
> + case 1:
> + case 2:
> + /* Unimplemented */
Seems pointless to list these.
The numbers match bspec. Unfortunatley I can't get tgl
configdb to cooperate so can't double check against the
MC register definition.
Reviewed-by: Ville Syrjälä
> + /* fall through */
> + default:
> + MISSING_CASE(val & 0xf);
> + break;
> + }
> + } else if (IS_GEN(dev_priv, 11)) {
> + switch (val & 0xf) {
> + case 0:
> + qi->dram_type = INTEL_DRAM_DDR4;
> + break;
> + case 1:
> + qi->dram_type = INTEL_DRAM_DDR3;
> + break;
> + case 2:
> + qi->dram_type = INTEL_DRAM_LPDDR3;
> + break;
> + case 3:
> + qi->dram_type = INTEL_DRAM_LPDDR3;
> + break;
> + default:
> + MISSING_CASE(val & 0xf);
> + break;
> + }
> + } else {
> + MISSING_CASE(INTEL_GEN(dev_priv));
> + qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
> }
>
> qi->num_channels = (val & 0xf0) >> 4;
> --
> 2.22.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Mark contents as dirty on a write fault
Quoting Chris Wilson (2019-09-20 13:22:13)
> Quoting Chris Wilson (2019-09-20 13:18:21)
> > Since dropping the set-to-gtt-domain in commit a679f58d0510 ("drm/i915:
> > Flush pages on acquisition"), we no longer mark the contents as dirty on
> > a write fault. This has the issue of us then not marking the pages as
> > dirty on releasing the buffer, which means the contents are not written
> > out to the swap device (should we ever pick that buffer as a victim).
> > Notably, this is visible in the dumb buffer interface used for cursors.
> > Having updated the cursor contents via mmap, and swapped away, if the
> > shrinker should evict the old cursor, upon next reuse, the cursor would
> > be invisible.
>
> Hmm, I think the dumb interface may be missing a few steps around the
> place to ensure the contents are flushed.
No, it's fine. We do the flush in pinning pages, the only thing that was
dropped was then marking the content as dirty.
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for mdev based hardware virtio offloading support
== Series Details == Series: mdev based hardware virtio offloading support URL : https://patchwork.freedesktop.org/series/66989/ State : success == Summary == CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14470 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/ Known issues Here are the changes found in Patchwork_14470 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-short: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@gem_mmap_...@basic-short.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-icl-u3/igt@gem_mmap_...@basic-short.html * igt@i915_selftest@live_gem_contexts: - fi-skl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#111700]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@gem_ctx_switch@legacy-render: - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713] / [fdo#111381]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-blb-e6850/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@kms_addfb_basic@addfb25-x-tiled: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700 Participating hosts (54 -> 48) -- Additional (1): fi-hsw-4770r Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6928 -> Patchwork_14470 CI-20190529: 20190529 CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14470: 822c68b1ca1845b6e2a38ae71547e9d9b4a5fadb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 822c68b1ca18 docs: Sample driver to demonstrate how to implement virtio-mdev framework 17f868b5d9a4 vringh: fix copy direction of vringh_iov_push_kern() 61e824bf250a virtio: introudce a mdev based transport 7bbada3ad14d mdev: introduce virtio device and its device ops 8efae9b60a78 mdev: introduce device specific ops 32afcef2acff mdev: class id support == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14470/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Prevent bonded requests from overtaking each other on preemption
== Series Details ==
Series: drm/i915: Prevent bonded requests from overtaking each other on
preemption
URL : https://patchwork.freedesktop.org/series/66990/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7885378114ae drm/i915: Prevent bonded requests from overtaking each other on
preemption
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit ee1136908e9b
("drm/i915/execlists: Virtual engine bonding")'
#22:
References: ee1136908e9b ("drm/i915/execlists: Virtual engine bonding")
total: 1 errors, 0 warnings, 0 checks, 29 lines checked
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Re: [Intel-gfx] [PATCH] drm/i915: Prevent bonded requests from overtaking each other on preemption
Quoting Tvrtko Ursulin (2019-09-20 13:24:47)
>
> On 20/09/2019 09:36, Chris Wilson wrote:
> > Force bonded requests to run on distinct engines so that they cannot be
> > shuffled onto the same engine where timeslicing will reverse the order.
> > A bonded request will often wait on a semaphore signaled by its master,
> > creating an implicit dependency -- if we ignore that implicit dependency
> > and allow the bonded request to run on the same engine and before its
> > master, we will cause a GPU hang.
> >
> > We can prevent this inversion by restricting which engines we allow
> > ourselves to jump to upon preemption, i.e. baking in the arrangement
> > established at first execution. (We should also consider capturing the
> > implicit dependency using i915_sched_add_dependency(), but first we need
> > to think about the constraints that requires on the execution/retirement
> > ordering.)
> >
> > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
> > References: ee1136908e9b ("drm/i915/execlists: Virtual engine bonding")
> > Signed-off-by: Chris Wilson
> > Cc: Mika Kuoppala
> > Cc: Tvrtko Ursulin
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 19 +++
> > 1 file changed, 11 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index a99166a2d2eb..7920649e4d87 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -3755,18 +3755,21 @@ static void
> > virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
> > {
> > struct virtual_engine *ve = to_virtual_engine(rq->engine);
> > + intel_engine_mask_t allowed, exec;
> > struct ve_bond *bond;
> >
> > bond = virtual_find_bond(ve, to_request(signal)->engine);
> > - if (bond) {
> > - intel_engine_mask_t old, new, cmp;
> > + if (!bond)
> > + return;
> >
> > - cmp = READ_ONCE(rq->execution_mask);
> > - do {
> > - old = cmp;
> > - new = cmp & bond->sibling_mask;
> > - } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) !=
> > old);
> > - }
> > + /* Restrict the bonded request to run on only the slaved engines */
> > + allowed = bond->sibling_mask & ~to_request(signal)->engine->mask;
>
> Hmm.. isn't it a miss on the uapi level that we allow master to be
> mentioned in the list of bonds? That's the only scenario where this line
> does something I think. So should we just forbid this setup on the uapi
> level?
That's just a lot of digging!
> > + exec = READ_ONCE(rq->execution_mask);
> > + while (!try_cmpxchg(&rq->execution_mask, &exec, exec & allowed))
> > + ;
> > +
> > + /* Prevent the master from being re-run on the slaved engines */
> > + to_request(signal)->execution_mask &= ~allowed;
>
> This sounds unfortunate for future scheduling. There shouldn't be a
> fundamental reason why next execution for the master couldn't be on an
> engine which can also be a slave. So if we have:
Note though that we do not reset the execution_mask at any point :)
That's actually harder to do than it sounds, as after the bonded
execution, they are no longer linked. :|
> master
>.veng=vcs0,vcs1
> slave
>.veng=vcs0,vcs1
>.bond(master=vcs0, mask=vcs1)
>.bond(master=vcs1, mask=vcs0)
>
> This should be allowed setup but with this change it would fix the
> master to only be one of the options.
It would fix it to the first one it selected and executed on. It can
still pick either vcs0 or vcs1 and the slave would then be on vcs1 or
vcs0 respectively.
> Is the real problem that after preemption for timeslicing and subsequent
> re-submit we miss some hooks to re-evaluate the bonded relationship?
That doesn't exist, yes. But it's more than that, as we don't have the
notion of global preemption -- we don't evaluate between engines whether
or not there are cross dependencies.
> I guess looking would be hard to do any peeking from one submission
> tasklet to another (different engines) to check if one of the pair is
> already executing again and so to pick the other end correctly?
Hard indeed. I would throw a flag onto the request that says if you
preempt me, stop the world (intel_engine_mask_t perhaps). Even that
requires some tricks we don't yet have. But we can't touch the other
engines within the tasklet unless we can come up with a lockless
strategy (hence the strategy of punting to a supreme thread with
oversight of all engines, gah.)
> I think in practical terms for media this work since they are not
> setting it up like my sketch shows. So it could be just fine in practice
> for current users.
I think your example works better than you think -- we just end up
concreted into our first choice and can't jump around hogs in the
system. (For example, to prove the above, we can launch tw
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC
== Series Details == Series: series starting with [CI,1/2] drm/i915/uc: Update HuC firmware naming convention and load latest HuC URL : https://patchwork.freedesktop.org/series/66955/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14466_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_14466_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14466_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_14466_full: ### IGT changes ### Possible regressions * igt@i915_suspend@debugfs-reader: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@i915_susp...@debugfs-reader.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-iclb4/igt@i915_susp...@debugfs-reader.html Known issues Here are the changes found in Patchwork_14466_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +14 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-kbl2/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#110854]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb4/igt@gem_exec_balan...@smoke.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-iclb7/igt@gem_exec_balan...@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb3/igt@gem_exec_sched...@preempt-other-chain-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-iclb1/igt@gem_exec_sched...@preempt-other-chain-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +16 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb1/igt@gem_exec_sched...@preempt-queue-bsd1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-iclb3/igt@gem_exec_sched...@preempt-queue-bsd1.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl2/igt@gem_workarou...@suspend-resume-context.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-apl1/igt@gem_workarou...@suspend-resume-context.html * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-skl: [PASS][13] -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl10/igt@i915_pm_rc6_reside...@rc6-accuracy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-skl5/igt@i915_pm_rc6_reside...@rc6-accuracy.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-skl6/igt@kms_f...@flip-vs-expired-vblank-interruptible.html - shard-glk: [PASS][17] -> [FAIL][18] ([fdo#105363]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-glk5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-glk1/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#109507]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl6/igt@kms_f...@flip-vs-suspend-interruptible.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html - shard-hsw: [PASS][21] -> [INCOMPLETE][22] ([fdo#103540]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-hsw1/igt@kms_f...@flip-vs-suspend-interruptible.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14466/shard-hsw2/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-in
Re: [Intel-gfx] [PATCH 03/12] drm/i915: Fix AVI infoframe quantization range for YCbCr output
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're configuring the AVI infoframe quantization range bits as if
> we're always transmitting RGB pixels. Let's fix this so that we
> correctly indicate limited range YCC quantization range when
> transmitting YCbCr instead.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_hdmi.c | 15 ++-
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 9bf28de10401..b8100cf21dd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -724,11 +724,16 @@ intel_hdmi_compute_avi_infoframe(struct
> intel_encoder *encoder,
>
> drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
>
> - drm_hdmi_avi_infoframe_quant_range(frame, connector,
> -adjusted_mode,
> -crtc_state-
> >limited_color_range ?
> -HDMI_QUANTIZATION_RANGE_LIMI
> TED :
> -HDMI_QUANTIZATION_RANGE_FULL
> );
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
> + drm_hdmi_avi_infoframe_quant_range(frame, connector,
> +adjusted_mode,
> +crtc_state-
> >limited_color_range ?
> +HDMI_QUANTIZATION_RA
> NGE_LIMITED :
> +HDMI_QUANTIZATION_RA
> NGE_FULL);
> + } else {
> + frame->quantization_range =
> HDMI_QUANTIZATION_RANGE_DEFAULT;
> + frame->ycc_quantization_range =
> HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
> + }
>
> drm_hdmi_avi_infoframe_content_type(frame, conn_state);
>
The changes look good to me.
Reviewed-by: Gwan-gyeong Mun
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Prevent bonded requests from overtaking each other on preemption
== Series Details == Series: drm/i915: Prevent bonded requests from overtaking each other on preemption URL : https://patchwork.freedesktop.org/series/66990/ State : success == Summary == CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14471 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/ Known issues Here are the changes found in Patchwork_14471 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_switch@legacy-render: - fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927] / [fdo#111381]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-bxt-dsi/igt@gem_ctx_swi...@legacy-render.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([fdo#111407]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@prime_self_import@basic-with_fd_dup: - fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-icl-u3/igt@prime_self_import@basic-with_fd_dup.html Possible fixes * igt@gem_ctx_switch@legacy-render: - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713] / [fdo#111381]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-blb-e6850/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@kms_addfb_basic@addfb25-x-tiled: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 Participating hosts (54 -> 48) -- Additional (1): fi-hsw-4770r Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6928 -> Patchwork_14471 CI-20190529: 20190529 CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14471: 7885378114aefe9decb3c6ea2f10b575ed807d98 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7885378114ae drm/i915: Prevent bonded requests from overtaking each other on preemption == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14471/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] status of the " CRTC background color" series
Hi all, Any update on this series ? Last time I looked, everything looked ready and waiting to be merged. JJ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case).
>
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
>
> Signed-off-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 58 +++--
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> 2 files changed, 58 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index cd58e47ab7b2..7653cbdb0ee4 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -90,6 +90,26 @@ static int icl_pcode_read_qgv_point_info(struct
> drm_i915_private *dev_priv,
> return 0;
> }
>
> +static int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +
> static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> struct intel_qgv_info *qi)
> {
> @@ -354,7 +374,9 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> - int i;
> + int i, ret;
> + struct intel_qgv_info qi = {};
> + u32 points_mask = 0;
>
> /* FIXME earlier gens need some checks too */
> if (INTEL_GEN(dev_priv) < 11)
> @@ -398,10 +420,40 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> data_rate = intel_bw_data_rate(dev_priv, bw_state);
> num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>
> - max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> -
> data_rate = DIV_ROUND_UP(data_rate, 1000);
>
> + ret = icl_get_qgv_points(dev_priv, &qi);
> + if (ret < 0) {
> + goto fallback;
If we don't have that we don't have any idea about bw limits. So
probably just return 0 here.
> + }
> +
> + for (i = 0; i < qi.num_points; i++) {
> + max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> + if (max_data_rate < data_rate) {
> + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
> restricted\n",
> + i, max_data_rate, data_rate);
> + points_mask |= 1 << i;
I think just marking the accepted levels in the mask would make things
simpler...
> + } else
> + DRM_DEBUG_KMS("QGV point %d: max bw %d required %d
> unrestricted\n",
> + i, max_data_rate, data_rate);
> + }
> +
> + if (points_mask >= ((1 << qi.num_points) - 1)) {
... eg. this can then just be 'if (points_mask == 0)'
> + DRM_DEBUG_KMS("Could not find any suitable QGV points\n");
> + return -EINVAL;
> + }
> +
> + ret = icl_pcode_restrict_qgv_points(dev_priv, points_mask);
> + if (ret < 0) {
> + DRM_DEBUG_KMS("Could not restrict required gqv points(%d)\n",
> ret);
> + goto fallback;
Seems like dead code to me.
We'll need to account for the SAGV yes/no in here as well. That is, if
SAGV is off due to watermarks we'll need to restrict things to the
highest QGV point only. Also using both the QGV point restriction
pcode command and the legacy SAGV pcode command at the same time sounds
rather risky to me. I suspect pcode might not expect that. So we need
to rework this on a slightly bigger scale.
> + }
> +
> + return 0;
> +
> +fallback:
> + max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> +
> if (data_rate > max_data_rate) {
> DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s
> (%d active planes)\n",
> data_rate, max_data_rate, num_active_planes);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ecebc82f..fe327fee8781 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8845,6 +8845,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO(0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(poin
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend
== Series Details == Series: drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend URL : https://patchwork.freedesktop.org/series/66991/ State : success == Summary == CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14472 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/ Known issues Here are the changes found in Patchwork_14472 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap_gtt@basic-small-bo: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html * igt@i915_module_load@reload: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] / [fdo#111214]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@i915_module_l...@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-icl-u3/igt@i915_module_l...@reload.html * igt@kms_chamelium@dp-edid-read: - fi-kbl-7500u: [PASS][5] -> [WARN][6] ([fdo#109483]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html Possible fixes * igt@gem_ctx_switch@legacy-render: - fi-icl-u2: [INCOMPLETE][7] ([fdo#107713] / [fdo#111381]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html * igt@i915_module_load@reload: - fi-blb-e6850: [INCOMPLETE][9] ([fdo#107718]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-blb-e6850/igt@i915_module_l...@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-blb-e6850/igt@i915_module_l...@reload.html * igt@kms_addfb_basic@addfb25-x-tiled: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 Participating hosts (54 -> 47) -- Additional (1): fi-hsw-4770r Missing(8): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6928 -> Patchwork_14472 CI-20190529: 20190529 CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14472: 475f7d6ead72e2bbce59c1e39d52e7b8701bebaa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 475f7d6ead72 drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14472/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add memory type decoding for bandwidth checking
On Fri, Sep 20, 2019 at 03:29:06PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate them
> > differently than ICL.
> >
> > BSpec: 53998
> >
> > Cc: Ville Syrjälä
> > Cc: Stanislav Lisovskiy
> > Signed-off-by: James Ausmus
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 59 ++---
> > 1 file changed, 43 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 688858ebe4d0..11224d9a6752 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -35,22 +35,49 @@ static int icl_pcode_read_mem_global_info(struct
> > drm_i915_private *dev_priv,
> > if (ret)
> > return ret;
> >
> > - switch (val & 0xf) {
> > - case 0:
> > - qi->dram_type = INTEL_DRAM_DDR4;
> > - break;
> > - case 1:
> > - qi->dram_type = INTEL_DRAM_DDR3;
> > - break;
> > - case 2:
> > - qi->dram_type = INTEL_DRAM_LPDDR3;
> > - break;
> > - case 3:
> > - qi->dram_type = INTEL_DRAM_LPDDR3;
>
> This should be LPDDR4 actually. Doesn't really matter but would be nice
> to fix as well.
Either my git send-email config or the ML seems to be eating my original
patch mail, and it's not hitting the list, patchwork, or CI, so will
have to send a v2 anyway and I will fix this up in that.
>
> > - break;
> > - default:
> > - MISSING_CASE(val & 0xf);
> > - break;
> > + if (IS_GEN(dev_priv, 12)) {
> > + switch (val & 0xf) {
> > + case 0:
> > + qi->dram_type = INTEL_DRAM_DDR4;
> > + break;
> > + case 3:
> > + qi->dram_type = INTEL_DRAM_LPDDR4;
> > + break;
> > + case 4:
> > + qi->dram_type = INTEL_DRAM_DDR3;
> > + break;
> > + case 5:
> > + qi->dram_type = INTEL_DRAM_LPDDR3;
> > + break;
> > + case 1:
> > + case 2:
> > + /* Unimplemented */
>
> Seems pointless to list these.
Will drop in v2.
>
> The numbers match bspec. Unfortunatley I can't get tgl
> configdb to cooperate so can't double check against the
> MC register definition.
>
> Reviewed-by: Ville Syrjälä
Thanks!
-James
>
> > + /* fall through */
> > + default:
> > + MISSING_CASE(val & 0xf);
> > + break;
> > + }
> > + } else if (IS_GEN(dev_priv, 11)) {
> > + switch (val & 0xf) {
> > + case 0:
> > + qi->dram_type = INTEL_DRAM_DDR4;
> > + break;
> > + case 1:
> > + qi->dram_type = INTEL_DRAM_DDR3;
> > + break;
> > + case 2:
> > + qi->dram_type = INTEL_DRAM_LPDDR3;
> > + break;
> > + case 3:
> > + qi->dram_type = INTEL_DRAM_LPDDR3;
> > + break;
> > + default:
> > + MISSING_CASE(val & 0xf);
> > + break;
> > + }
> > + } else {
> > + MISSING_CASE(INTEL_GEN(dev_priv));
> > + qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
> > }
> >
> > qi->num_channels = (val & 0xf0) >> 4;
> > --
> > 2.22.1
>
> --
> Ville Syrjälä
> Intel
___
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Re: [Intel-gfx] [PATCH v2] drm/i915: Restrict qgv points which don't have enough bandwidth.
On Fri, 2019-09-20 at 16:19 +0300, Ville Syrjälä wrote:
> On Fri, Sep 20, 2019 at 01:44:13PM +0300, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> >
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> >
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> > values.
> >
> > Signed-off-by: Stanislav Lisovskiy
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 58
> > +++--
> > drivers/gpu/drm/i915/i915_reg.h | 3 ++
> > 2 files changed, 58 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index cd58e47ab7b2..7653cbdb0ee4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -90,6 +90,26 @@ static int icl_pcode_read_qgv_point_info(struct
> > drm_i915_private *dev_priv,
> > return 0;
> > }
> >
> > +static int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv, u32 points_mask)
> > +{
> > + int ret;
> > +
> > + /* bspec says to keep retrying for at least 1 ms */
> > + ret = skl_pcode_request(dev_priv,
> > ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> > + points_mask,
> > + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> > + GEN11_PCODE_POINTS_RESTRICTED,
> > + 1);
> > +
> > + if (ret < 0) {
> > + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +
> > static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> > struct intel_qgv_info *qi)
> > {
> > @@ -354,7 +374,9 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > unsigned int data_rate, max_data_rate;
> > unsigned int num_active_planes;
> > struct intel_crtc *crtc;
> > - int i;
> > + int i, ret;
> > + struct intel_qgv_info qi = {};
> > + u32 points_mask = 0;
> >
> > /* FIXME earlier gens need some checks too */
> > if (INTEL_GEN(dev_priv) < 11)
> > @@ -398,10 +420,40 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> > data_rate = intel_bw_data_rate(dev_priv, bw_state);
> > num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >
> > - max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > -
> > data_rate = DIV_ROUND_UP(data_rate, 1000);
> >
> > + ret = icl_get_qgv_points(dev_priv, &qi);
> > + if (ret < 0) {
> > + goto fallback;
>
> If we don't have that we don't have any idea about bw limits. So
> probably just return 0 here.
>
> > + }
> > +
> > + for (i = 0; i < qi.num_points; i++) {
> > + max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > + if (max_data_rate < data_rate) {
> > + DRM_DEBUG_KMS("QGV point %d: max bw %d required
> > %d restricted\n",
> > + i, max_data_rate, data_rate);
> > + points_mask |= 1 << i;
>
> I think just marking the accepted levels in the mask would make
> things
> simpler...
>
> > + } else
> > + DRM_DEBUG_KMS("QGV point %d: max bw %d required
> > %d unrestricted\n",
> > + i, max_data_rate, data_rate);
> > + }
> > +
> > + if (points_mask >= ((1 << qi.num_points) - 1)) {
>
> ... eg. this can then just be 'if (points_mask == 0)'
>
> > + DRM_DEBUG_KMS("Could not find any suitable QGV
> > points\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = icl_pcode_restrict_qgv_points(dev_priv, points_mask);
> > + if (ret < 0) {
> > + DRM_DEBUG_KMS("Could not restrict required gqv
> > points(%d)\n", ret);
> > + goto fallback;
>
> Seems like dead code to me.
>
> We'll need to account for the SAGV yes/no in here as well. That is,
> if
> SAGV is off due to watermarks we'll need to restrict things to the
> highest QGV point only. Also using both the QGV point restriction
> pcode command and the legacy SAGV pcode command at the same time
> sounds
> rather risky to me. I suspect pcode might not expect that. So we need
> to rework this on a slightly bigger scale.
Well, I suspected that it's not going to be that easy..
Probably you mean that this has to be somehow put in sync with
intel_disable_sagv calls, so we need to mutually exclude those
and/or take into account.
>
> > + }
> > +
> > + return 0;
> > +
> > +fallback:
> > + max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > +
> > if (data_rate > max_data_rate) {
> > DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available
> > %d MB/s (%d active planes)\n",
> > data_rat
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add TigerLake bandwidth checking (rev5)
== Series Details == Series: drm/i915: Add TigerLake bandwidth checking (rev5) URL : https://patchwork.freedesktop.org/series/66817/ State : success == Summary == CI Bug Log - changes from CI_DRM_6928 -> Patchwork_14473 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/ Known issues Here are the changes found in Patchwork_14473 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic-small-bo: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@gem_m...@basic-small-bo.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-icl-u3/igt@gem_m...@basic-small-bo.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-guc: [PASS][3] -> [INCOMPLETE][4] ([fdo#106070] / [fdo#111514] / [fdo#111700]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: [PASS][7] -> [INCOMPLETE][8] ([fdo#107718]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-blb-e6850/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Possible fixes * igt@gem_ctx_switch@legacy-render: - fi-icl-u2: [INCOMPLETE][9] ([fdo#107713] / [fdo#111381]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html * igt@kms_addfb_basic@addfb25-x-tiled: - fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6928/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/fi-icl-u3/igt@kms_addfb_ba...@addfb25-x-tiled.html [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111514]: https://bugs.freedesktop.org/show_bug.cgi?id=111514 [fdo#111700]: https://bugs.freedesktop.org/show_bug.cgi?id=111700 Participating hosts (54 -> 46) -- Additional (1): fi-hsw-4770r Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-hsw-4770 fi-icl-y fi-bsw-kefka fi-bdw-samus Build changes - * CI: CI-20190529 -> None * Linux: CI_DRM_6928 -> Patchwork_14473 CI-20190529: 20190529 CI_DRM_6928: 74bb5b031ca11c7036f7be21f42a73a057fc8da8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5194: 531d3d02d5e7a2a84d61b92b28fa01b822afc399 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14473: 81aa9b483640803e2090893356912534fd416e28 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 81aa9b483640 drm/i915: Add TigerLake bandwidth checking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14473/index.html ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
