[Intel-gfx] [PATCH i-g-t] i915/gem_ppgtt: Remove defunct test
i915_gem_gtt_info has been removed and so flink-and-exit-vma-leak is
defunct.
Signed-off-by: Chris Wilson
---
tests/i915/gem_ppgtt.c | 43 --
1 file changed, 43 deletions(-)
diff --git a/tests/i915/gem_ppgtt.c b/tests/i915/gem_ppgtt.c
index b905ea559..0d40a7b78 100644
--- a/tests/i915/gem_ppgtt.c
+++ b/tests/i915/gem_ppgtt.c
@@ -289,46 +289,6 @@ static void flink_and_close(void)
close(fd2);
}
-static void flink_and_exit(void)
-{
- uint32_t fd, fd2, fd3;
- uint32_t bo, flinked_bo, name;
- char match[20];
-
- fd = drm_open_driver(DRIVER_INTEL);
- igt_require(gem_uses_full_ppgtt(fd));
-
- bo = gem_create(fd, 4096);
- name = gem_flink(fd, bo);
- snprintf(match, sizeof(match), "(name: %u)", name);
-
- fd2 = drm_open_driver(DRIVER_INTEL);
- flinked_bo = gem_open(fd2, name);
-
- /* Verify VMA is not there yet. */
- igt_assert(!igt_debugfs_search(fd, "i915_gem_gtt", match));
-
- exec_and_get_offset(fd2, flinked_bo);
-
- /* Verify VMA has been created. */
- igt_assert(igt_debugfs_search(fd, "i915_gem_gtt", match));
-
- /* Close the context. */
- close(fd2);
-
- /* Execute a different and unrelated (wrt object sharing) context to
-* ensure engine drops its last context reference.
-*/
- fd3 = drm_open_driver(DRIVER_INTEL);
- exec_and_get_offset(fd3, gem_create(fd3, 4096));
- close(fd3);
-
- igt_drop_caches_set(fd, DROP_ACTIVE | DROP_RETIRE | DROP_IDLE);
- igt_assert(!igt_debugfs_search(fd, "i915_gem_gtt", match));
-
- close(fd);
-}
-
#define N_CHILD 8
igt_main
{
@@ -364,7 +324,4 @@ igt_main
igt_subtest("flink-and-close-vma-leak")
flink_and_close();
-
- igt_subtest("flink-and-exit-vma-leak")
- flink_and_exit();
}
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: fix whitelist on Gen10+
== Series Details == Series: drm/i915/perf: fix whitelist on Gen10+ URL : https://patchwork.freedesktop.org/series/61467/ State : success == Summary == CI Bug Log - changes from CI_DRM_6179_full -> Patchwork_13155_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13155_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl5/igt@gem_soft...@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-skl9/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-kbl: [PASS][3] -> [FAIL][4] ([fdo#108686]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl2/igt@gem_tiled_swapp...@non-threaded.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-kbl7/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107773]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl3/igt@i915_susp...@debugfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-skl4/igt@i915_susp...@debugfs-reader.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-kbl6/igt@i915_susp...@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-kbl3/igt@i915_susp...@sysfs-reader.html * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions: - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([fdo#103540]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-hsw4/igt@kms_cursor_leg...@cursora-vs-flipa-atomic-transitions.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-hsw4/igt@kms_cursor_leg...@cursora-vs-flipa-atomic-transitions.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108040]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-pgflip-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-skl8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#103167]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-apl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-skl10/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13155/shard-iclb5/igt@kms_psr@psr2_no_drrs.html * igt@perf_pmu@rc6-runtime-pm-long: - shard-apl: [PASS][23] -> [FAIL][24] ([fdo#105010]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6179/shard-apl6/igt@perf_...@rc6-runtime-pm-long.html [24]: https://inte
Re: [PATCH 2/2] drm/i915: Skip object locking around a no-op set-domain ioctl
Hi! > This patch causes lockups in firefox. They appear like non-fatal hangs > of the webpage contents, "fixable" with alt-tab or a background system > load. I have verified that reverting the commit 754a254427 on top of > current Linus tree fixes the problem. This is still broken in v5.2-rc3. I have also verified that the particular commit, if backported to v5.1 release, breaks firefox there too in the same way. (for reference:) commit 754a25442705c4f90e0d05f1a7bd303ffe700ca9 Author: Chris Wilson Date: Thu Mar 21 16:19:08 2019 + drm/i915: Skip object locking around a no-op set-domain ioctl
[Intel-gfx] linux-next: unable to fetch the drm-intel-fixes tree
Hi all, Trying to fetch the drm-intel-fixes tree today gives me this error: - fatal: Could not read from remote repository. Please make sure you have the correct access rights and the repository exists. - The same for drm-misc-fixes, drm-intel and drm-misc. These are all hosted on git://anongit.freedesktop.org/ . -- Cheers, Stephen Rothwell pgpurRd_qWJTU.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: unable to fetch the drm-intel-fixes tree
Hi Stephen, On Mon, 3 Jun 2019 08:20:51 +1000 Stephen Rothwell wrote: > > Hi all, > > Trying to fetch the drm-intel-fixes tree today gives me this error: > > - > fatal: Could not read from remote repository. > > Please make sure you have the correct access rights > and the repository exists. > - > > The same for drm-misc-fixes, drm-intel and drm-misc. These are all > hosted on git://anongit.freedesktop.org/ . Also the drm-tegra tree. -- Cheers, Stephen Rothwell pgpnIUkr3w3JC.pgp Description: OpenPGP digital signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] question about i915 GPU driver in VM
> Hi, > > I'm trying to get iGPU passthrough working in a VM running on a Chrome OS > "7th Generation (Kaby Lake) Intel Core i5-7Y57 with HD Graphics 615" device. > I'm able to pass the iGPU through to the VM and execute the i915 driver, but > the driver doesn't succeed in getting the system to the point where the > screen works. > > With physical access to the iGPU from inside the guest, is it reasonable to > just run the same kernel/driver that works on the host and expect it to work? > Or are there often extra hoops to jump through even with > physical/unemulated access to the host GPU and CPU? [Zhang, Xiong Y] yes, both host and guest use the same kernel/driver. > > On a higher level, it would help if anyone had an idea from the logs below if > I'm "close" to getting this to work? Or maybe its hard to say? [Zhang, Xiong Y] it is close to work. > > NOTE: I totally avoid touching the GPU in the host, and have verified that the > i915 driver in the guest should have all the info (e.g. > OpRegion tables) it needs to drive the GPU. Interestingly, running > i915 in the VM causes the VM kernel to crash at random code paths unless I > wait until after system startup to modprobe i915. The VM doesn't crash at all > if I disable i915. These crashes happen well after i915 is done trying to > initialize the GPU, so not sure if i915 is touching memory it shouldn't be or > what.. [Zhang, Xiong Y] Please check whether intel_iommu is enabled on host or not. If it isn't , please add intel_iommu=on to host grub. is the dmesg from host or guest ? If it is guest, this message shouldn't appear according to your qemu boot parameter. > [0.475961] [drm:i915_ggtt_probe_hw] GTT stolen size = 64M > [0.476927] [drm:i915_gem_init_stolen] Memory reserved for graphics > device: 65536K, usable: 64512K Please paste qemu output. thanks > > Thanks, > Micah > > KERNEL CONSOLE (modified for brevity): > localhost ~ # qemu-system-x86_64 -serial mon:stdio -m 2G -smp 2 -M pc -vga > none -usbdevice tablet -cpu host,-invpcid,-tsc-deadline,check -drive > 'file=/mnt/stateful_partition/chromiumos_test_image.bin,index=0,media=dis > k,cache=unsafe,format=raw' > -enable-kvm -device > vfio-pci,x-igd-opregion=on,host=00:02.0,id=hostdev0,bus=pci.0,addr=0x2,ro > mbar=0 > -device 'virtio-net,netdev=eth0' -netdev > 'user,id=eth0,net=10.0.2.0/27,hostfwd=tcp:127.0.0.1:9222-:22' > qemu-system-x86_64: -usbdevice tablet: '-usbdevice' is deprecated, please > use '-device usb-...' instead > qemu-system-x86_64: -device > vfio-pci,x-igd-opregion=on,host=00:02.0,id=hostdev0,bus=pci.0,addr=0x2,ro > mbar=0: > IGD device :00:02.0 has no ROM, legacy mode disabled VNC server > running on 127.0.0.1:5900 > [0.00] Linux version 4.14.114 > (mort...@mortonm2.mtv.corp.google.com) (Chromium OS > 9.0_pre353983_p20190325-r11 clang version 9.0.0 > (/var/cache/chromeos-cache/distfiles/host/egit-src/clang.git > 171531e31716e2db2c372cf8b57220ddf9e721d8) > (/var/cache/chromeos-cache/distfiles/host/egit-src/llvm.git > 5077597e0d5b86d9f9c27286d8b28f8b3645a74c) (based on LLVM 9.0.0svn)) > #14 SMP PREEMPT Fri May 31 09:50:35 PDT 2019 > [0.00] Command line: BOOT_IMAGE=vmlinuz.A init=/sbin/init > boot=local rootwait ro noresume noswap loglevel=7 noinitrd > console=ttyS0 disablevmx=off > root=PARTUUID=60B83A78-8581-014B-8942-6128789234C3 i915.modeset=1 > cros_legacy cros_debug > > [snip] > > [0.00] Reserving Intel graphics memory at [mem > 0x7c00-0x7fff] > > [snip] > > [0.415534] ACPI: PCI Interrupt Link [LNKB] enabled at IRQ 10 > [0.416418] [drm:i915_driver_load] Assuming SunrisePoint PCH > [0.417296] [drm:intel_power_domains_init] Allowed DC state mask 03 > [0.418290] [drm:intel_device_info_dump] i915 device info: > platform=KABYLAKE gen=9 pciid=0x591e rev=0x02 > [0.418292] [drm:intel_device_info_dump] i915 device info: is_mobile: > no > [0.419684] [drm:intel_device_info_dump] i915 device info: is_lp: no > [0.420740] [drm:intel_device_info_dump] i915 device info: > is_alpha_support: no > [0.421712] [drm:intel_device_info_dump] i915 device info: > has_64bit_reloc: yes > [0.422806] [drm:intel_device_info_dump] i915 device info: > has_aliasing_ppgtt: yes > [0.423900] [drm:intel_device_info_dump] i915 device info: has_csr: yes > [0.425036] [drm:intel_device_info_dump] i915 device info: has_ddi: yes > [0.426033] [drm:intel_device_info_dump] i915 device info: has_dp_mst: > yes > [0.427040] [drm:intel_device_info_dump] i915 device info: > has_reset_engine: yes > [0.428076] [drm:intel_device_info_dump] i915 device info: has_fbc: yes > [0.429180] [drm:intel_device_info_dump] i915 device info: > has_fpga_dbg: yes > [0.430181] [drm:intel_device_info_dump] i915 device info: > has_full_ppgtt: yes > [0.431726] [drm:intel_device_info_dump] i915 device info: > has_full_48bit_ppgtt: yes > [0.432810] [drm:intel_device_info_dump] i915 device info: > has_gmch_display: no > [0.43
[Intel-gfx] [PATCH v6 5/8] drm/i915/gvt: GVTg handle pv_caps PVINFO register
implement pv_caps PVINFO register handler in GVTg to
control different level pv optimization within guest.
report VGT_CAPS_PV capability in pvinfo page for guest.
v0: RFC.
v1: rebase.
v2: rebase.
v3: renamed enable_pvmmio to pvmmio_caps which is used for host
pv caps.
v4: renamed pvmmio_caps to pv_caps.
v5: rebase.
v6: rebase.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/handlers.c | 4
drivers/gpu/drm/i915/gvt/vgpu.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 7732caa..fd2f72c 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1194,6 +1194,7 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
break;
case 0x78010: /* vgt_caps */
case 0x7881c:
+ case _vgtif_reg(pv_caps):
break;
default:
invalid_read = true;
@@ -1267,6 +1268,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
case _vgtif_reg(g2v_notify):
ret = handle_g2v_notification(vgpu, data);
break;
+ case _vgtif_reg(pv_caps):
+ DRM_INFO("vgpu id=%d pv caps =0x%x\n", vgpu->id, data);
+ break;
/* add xhot and yhot to handled list to avoid error log */
case _vgtif_reg(cursor_x_hot):
case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 44ce3c2..3ecc45a 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -47,6 +47,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PV;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
@@ -531,6 +532,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
+ int pv_caps = vgpu_vreg_t(vgpu, vgtif_reg(pv_caps));
gvt_dbg_core("--\n");
gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -562,6 +564,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu,
bool dmlr,
intel_vgpu_reset_mmio(vgpu, dmlr);
populate_pvinfo_page(vgpu);
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = pv_caps;
intel_vgpu_reset_display(vgpu);
if (dmlr) {
--
2.7.4
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[Intel-gfx] [PATCH v6 7/8] drm/i915/gvt: GVTg support ppgtt pv optimization
This patch handles ppgtt update from g2v notification.
It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.
It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and removes the cost of write
protection from the original shadow page mechansim.
v0: RFC.
v1: rebase.
v2: rebase.
v3: report pv pggtt cap to guest.
v4: renamed VGPU_PVMMIO with VGPU_PVCAP for name consistance, no PV
support if gfx vtd enabled.
v5: rebase.
v6: rebase.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/gtt.c | 317
drivers/gpu/drm/i915/gvt/gtt.h | 9 +
drivers/gpu/drm/i915/gvt/gvt.h | 4 +
drivers/gpu/drm/i915/gvt/handlers.c | 12 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 3 +
5 files changed, 344 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index d767c45..b78b872 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1761,6 +1761,25 @@ static int ppgtt_handle_guest_write_page_table_bytes(
return 0;
}
+static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
+{
+ struct intel_vgpu *vgpu = mm->vgpu;
+ struct intel_gvt *gvt = vgpu->gvt;
+ struct intel_gvt_gtt *gtt = &gvt->gtt;
+ struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ struct intel_gvt_gtt_entry se;
+
+ i915_ppgtt_put(mm->ppgtt);
+
+ ppgtt_get_shadow_root_entry(mm, &se, 0);
+ if (!ops->test_present(&se))
+ return;
+ se.val64 = 0;
+ ppgtt_set_shadow_root_entry(mm, &se, 0);
+
+ mm->ppgtt_mm.shadowed = false;
+}
+
static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
{
struct intel_vgpu *vgpu = mm->vgpu;
@@ -1773,6 +1792,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
if (!mm->ppgtt_mm.shadowed)
return;
+ if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE)) {
+ invalidate_mm_pv(mm);
+ return;
+ }
+
for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
ppgtt_get_shadow_root_entry(mm, &se, index);
@@ -1790,6 +1814,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
mm->ppgtt_mm.shadowed = false;
}
+static int shadow_mm_pv(struct intel_vgpu_mm *mm)
+{
+ struct intel_vgpu *vgpu = mm->vgpu;
+ struct intel_gvt *gvt = vgpu->gvt;
+ struct intel_gvt_gtt_entry se;
+
+ mm->ppgtt = i915_ppgtt_create(gvt->dev_priv);
+ if (IS_ERR(mm->ppgtt)) {
+ gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+ px_dma(&mm->ppgtt->pml4));
+ return PTR_ERR(mm->ppgtt);
+ }
+
+ se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
+ se.val64 = px_dma(&mm->ppgtt->pml4);
+ ppgtt_set_shadow_root_entry(mm, &se, 0);
+ mm->ppgtt_mm.shadowed = true;
+
+ return 0;
+}
static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
{
@@ -1804,6 +1848,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
if (mm->ppgtt_mm.shadowed)
return 0;
+ if (VGPU_PVCAP(mm->vgpu, PV_PPGTT_UPDATE))
+ return shadow_mm_pv(mm);
+
mm->ppgtt_mm.shadowed = true;
for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
@@ -2806,3 +2853,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
intel_vgpu_destroy_all_ppgtt_mm(vgpu);
intel_vgpu_reset_ggtt(vgpu, true);
}
+
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
+{
+ struct intel_vgpu_mm *mm;
+ int ret = 0;
+ u32 offset;
+ struct pv_ppgtt_update pv_ppgtt;
+
+ offset = offsetof(struct gvt_shared_page, buf.pv_ppgtt);
+ intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+
+ mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+ if (!mm) {
+ gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+ ret = -EINVAL;
+ } else {
+ ret = mm->ppgtt->vm.allocate_va_range(&mm->ppgtt->vm,
+ pv_ppgtt.start, pv_ppgtt.length);
+ if (ret)
+ gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
+ }
+
+ return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
+{
+ struct intel_vgpu_mm *mm;
+ int ret = 0;
+ u32 offset;
+ struct pv_ppgtt_update pv_ppgtt;
+
+ offset = offsetof(struct gvt_shared_page, buf.pv_ppgtt);
+ intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+ mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+ if (!mm) {
+ gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+ ret = -EI
[Intel-gfx] [PATCH v6 4/8] drm/i915: vgpu context submission pv optimization
It is performance optimization to override the actual submisison backend
in order to eliminate execlists csb process and reduce mmio trap numbers
for workload submission without context switch interrupt by talking with
GVT via PV submisison notification mechanism between guest and GVT.
Use PV_SUBMISSION to control this level of pv optimization.
v0: RFC.
v1: rebase.
v2: added pv ops for pv context submission. to maximize code resuse,
introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of
submit_ports and preempt_context implemented.
v3:
1. to reduce more code duplication, code refactor and replaced 2 ops
"submit_ports & preempt_contex" from v2 by 1 ops "write_desc"
in engine structure. pv version of write_des implemented.
2. added VGT_G2V_ELSP_SUBMIT for g2v pv notification.
v4: implemented pv elsp submission tasklet as the backend workload
submisison by talking to GVT with PV notificaiton mechanism and renamed
VGT_G2V_ELSP_SUBMIT to VGT_G2V_PV_SUBMISIION.
v5: addressed v4 comments from Chris, intel_pv_submission.c added.
v6: addressed v5 comments from Chris, replaced engine id by hw_id.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c| 8 +-
drivers/gpu/drm/i915/i915_pvinfo.h | 1 +
drivers/gpu/drm/i915/i915_vgpu.c | 8 +-
drivers/gpu/drm/i915/i915_vgpu.h | 3 +
drivers/gpu/drm/i915/intel_pv_submission.c | 166 +
6 files changed, 184 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_pv_submission.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a7850bb..86d11ba 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -215,7 +215,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/igt_spinner.o
# virtual gpu code
-i915-y += i915_vgpu.o
+i915-y += i915_vgpu.o intel_pv_submission.o
# perf code
i915-y += i915_perf.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index fed7048..86f46dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2644,11 +2644,15 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->unpark = NULL;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
- if (!intel_vgpu_active(engine->i915))
- engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
+ engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
if (engine->preempt_context &&
HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+
+ if (intel_vgpu_active(engine->i915)) {
+ engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
+ intel_vgpu_config_pv_caps(engine->i915, PV_SUBMISSION, engine);
+ }
}
static void execlists_destroy(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 2408a9d..362d898 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -50,6 +50,7 @@ enum vgt_g2v_type {
VGT_G2V_PPGTT_L4_ALLOC,
VGT_G2V_PPGTT_L4_CLEAR,
VGT_G2V_PPGTT_L4_INSERT,
+ VGT_G2V_PV_SUBMISSION,
VGT_G2V_MAX,
};
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 418582c..723aa80 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -81,7 +81,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
dev_priv->vgpu.active = true;
/* guest driver PV capability */
- dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE;
+ dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE | PV_SUBMISSION;
if (!intel_vgpu_check_pv_caps(dev_priv)) {
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
@@ -361,6 +361,7 @@ void intel_vgpu_config_pv_caps(struct drm_i915_private
*dev_priv,
enum pv_caps cap, void *data)
{
struct i915_hw_ppgtt *ppgtt;
+ struct intel_engine_cs *engine;
if (!intel_vgpu_enabled_pv_caps(dev_priv, cap))
return;
@@ -371,6 +372,11 @@ void intel_vgpu_config_pv_caps(struct drm_i915_private
*dev_priv,
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
}
+
+ if (cap == PV_SUBMISSION) {
+ engine = (struct intel_engine_cs *)data;
+ vgpu_set_pv_submission(engine);
+ }
}
/*
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index 7a39748..c5b1c33 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -31,6 +31,7 @@
*/
enum pv_caps {
PV_PPGTT_UPDATE = 0x1,
+ PV_SUBMISSION = 0x2,
[Intel-gfx] [PATCH v6 0/8] i915 vgpu PV to improve vgpu performance
To improve vgpu performance, it could implement some PV optimization such as to reduce the mmio access trap numbers or eliminate certain piece of HW emulation within guest driver to reduce vm exit/vm enter cost. the solutions in this patch set are implemented two PV optimizations based on the shared memory region between guest and GVTg for data communication. The shared memory region is allocated by guest driver and this region's memory guest physical address will be passed to GVTg through PVINFO register and later GVTg can access this region directly without trap cost to achieve data exchange purpose between guest and GVTg. in this patch set, 2 kind of PV optimization implemented controlled by pv_caps PVINO register with different pv bit. 1. workload PV submission (context submission): reduce 4 traps to 1 trap and eliminated execlists HW behaviour emulation. 2. ppgtt PV update: eliminate the cost of ppgtt write protection. based on the experiment, for small workloads, specifally, glxgears with vblank_mode off, the average performance gain on single vgpu is 30~50%. for large workload such as media and 3D, the average performance gain is about 4%. based on the PV mechanism, it could achive more vgpu feature optimization such as globle GTT update, display plane and water mark update. v0: RFC patch set v1: addressed RFC review comments v2: addressed v1 review comments, added pv callbacks for pv operations v3: 1. addressed v2 review comments, removed pv callbacks code duplication in v2 and unified pv calls under g2v notification register. different g2v pv notifications defined. 2. dropped pv master irq feature due to hard conflict with recnet i915 change and take time to rework. v4: 1. addressed v3 review comments. 2. extended workload PV submission by skip execlists HW behaviour emulation and context switch interrupt injection. v5: 1. addressed v4 review comments from Chris for pv submission. 2. per-engine communication between PV guest and host. v6: 1. addressed v5 review comment from Chris for pv submission. 2. addressed v5 review comment from Zhenyu for PV version support. Xiaolin Zhang (8): drm/i915: introduced vgpu pv capability drm/i915: vgpu shared memory setup for pv optimization drm/i915: vgpu ppgtt update pv optimization drm/i915: vgpu context submission pv optimization drm/i915/gvt: GVTg handle pv_caps PVINFO register drm/i915/gvt: GVTg handle shared_page setup drm/i915/gvt: GVTg support ppgtt pv optimization drm/i915/gvt: GVTg support context submission pv optimization drivers/gpu/drm/i915/Makefile | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c| 8 +- drivers/gpu/drm/i915/gvt/execlist.c| 6 + drivers/gpu/drm/i915/gvt/gtt.c | 317 + drivers/gpu/drm/i915/gvt/gtt.h | 9 + drivers/gpu/drm/i915/gvt/gvt.h | 12 +- drivers/gpu/drm/i915/gvt/handlers.c| 65 +- drivers/gpu/drm/i915/gvt/vgpu.c| 50 + drivers/gpu/drm/i915/i915_drv.h| 5 +- drivers/gpu/drm/i915/i915_gem.c| 3 +- drivers/gpu/drm/i915/i915_gem_gtt.c| 9 +- drivers/gpu/drm/i915/i915_gem_gtt.h| 8 + drivers/gpu/drm/i915/i915_pvinfo.h | 12 +- drivers/gpu/drm/i915/i915_vgpu.c | 182 - drivers/gpu/drm/i915/i915_vgpu.h | 59 ++ drivers/gpu/drm/i915/intel_pv_submission.c | 166 +++ 16 files changed, 900 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_pv_submission.c -- 2.7.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 3/8] drm/i915: vgpu ppgtt update pv optimization
This patch extends vgpu ppgtt g2v notification to notify host
GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4
and insert_4lvl.
These updates use the shared memory page to pass struct pv_ppgtt_update
from guest to GVT which is used for pv optimiation implemeation within
host GVT side.
This patch also add one new pv_caps level to control ppgtt update.
Use PV_PPGTT_UPDATE to control this level of pv optimization.
v0: RFC.
v1: rebased.
v2: added pv callbacks for vm.{allocate_va_range, insert_entries,
clear_range} within ppgtt.
v3: rebased, disable huge page ppgtt support when using PVMMIO ppgtt
update due to complex and performance impact.
v4: moved alloc/insert/clear_4lvl pv callbacks into i915_vgpu_pv.c and
added a single intel_vgpu_config_pv_caps() for vgpu pv callbacks setup.
v5: rebase.
v6: rebase.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_gem.c | 3 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 8
drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++
drivers/gpu/drm/i915/i915_vgpu.c| 84 +
drivers/gpu/drm/i915/i915_vgpu.h| 17
6 files changed, 120 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4739a630..975c784 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1507,7 +1507,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
int ret;
/* We need to fallback to 4K pages if host doesn't support huge gtt. */
- if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+ if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
+ || intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE))
mkwrite_device_info(dev_priv)->page_sizes =
I915_GTT_PAGE_SIZE_4K;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ca8a69e..480e8f4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -926,7 +926,7 @@ static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
* This is the top-level structure in 4-level page tables used on gen8+.
* Empty entries are always scratch pml4e.
*/
-static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1165,7 +1165,7 @@ static void gen8_ppgtt_insert_huge_entries(struct
i915_vma *vma,
} while (iter->sg);
}
-static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct i915_vma *vma,
enum i915_cache_level cache_level,
u32 flags)
@@ -1447,7 +1447,7 @@ static int gen8_ppgtt_alloc_3lvl(struct
i915_address_space *vm,
&i915_vm_to_ppgtt(vm)->pdp, start, length);
}
-static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
u64 start, u64 length)
{
struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
@@ -1579,6 +1579,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
drm_i915_private *i915)
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+
+ if (intel_vgpu_active(i915))
+ intel_vgpu_config_pv_caps(i915, PV_PPGTT_UPDATE, ppgtt);
} else {
err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
if (err)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 73b6608..2372f03 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -646,6 +646,14 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
+void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
+void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level, u32 flags);
+int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
+ u64 start, u64 length);
+
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 465
[Intel-gfx] [PATCH v6 1/8] drm/i915: introduced vgpu pv capability
pv capability for vgpu was introduced by pv_caps in struct
i915_virtual_gpu and a new pv_caps register for host GVT
was defined in struct vgt_if for vgpu pv optimization.
both of them are used to control different feature pv optimization
supported and implemented by both guest and host.
These fields are default zero, no any pv feature enabled.
it also adds VGT_CAPS_PV capability BIT for guest to check GVTg
can support PV feature or not.
v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v2: rebase.
v3: distinct pv caps from guest and host. renamed enable_pvmmio to
pvmmio_caps which is used for host pv caps.
v4: consolidated all pv related functons into a single file i915_vgpu.c
and renamed pvmmio to pv_caps.
v5: rebase.
v6: rebase.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_pvinfo.h | 5 -
drivers/gpu/drm/i915/i915_vgpu.c | 44 +-
drivers/gpu/drm/i915/i915_vgpu.h | 8 +++
4 files changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76f2bf9..2bb38b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -90,6 +90,7 @@
#include "i915_vma.h"
#include "intel_gvt.h"
+#include "i915_pvinfo.h"
/* General customization:
*/
@@ -1242,6 +1243,7 @@ struct i915_frontbuffer_tracking {
struct i915_virtual_gpu {
bool active;
u32 caps;
+ u32 pv_caps;
};
/* used in computing the new watermarks state */
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 969e514..619305a 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -55,6 +55,7 @@ enum vgt_g2v_type {
#define VGT_CAPS_FULL_PPGTTBIT(2)
#define VGT_CAPS_HWSP_EMULATIONBIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
+#define VGT_CAPS_PVBIT(5)
struct vgt_if {
u64 magic; /* VGT_MAGIC */
@@ -107,7 +108,9 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
- u32 rsv7[0x200 - 24];/* pad to one page */
+ u32 pv_caps;
+
+ u32 rsv7[0x200 - 25];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 94d3992..bb9f988 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -79,7 +79,14 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
dev_priv->vgpu.active = true;
- DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+ if (!intel_vgpu_check_pv_caps(dev_priv)) {
+ DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+ return;
+ }
+
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n",
+ dev_priv->vgpu.pv_caps);
}
bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
@@ -274,3 +281,38 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
DRM_ERROR("VGT balloon fail\n");
return ret;
}
+
+/*
+ * i915 vgpu PV support for Linux
+ */
+
+/**
+ * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
+ * @dev_priv: i915 device private
+ *
+ * This function is called at the initialization stage, to detect VGPU
+ * PV capabilities
+ *
+ * If guest wants to enable pv_caps, it needs to config it explicitly
+ * through vgt_if interface from gvt layer.
+ */
+bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 gvt_pvcaps;
+ u32 pvcaps = 0;
+
+ if (!intel_vgpu_has_pv_caps(dev_priv))
+ return false;
+
+ /* PV capability negotiation between PV guest and GVT */
+ gvt_pvcaps = __raw_uncore_read32(uncore, vgtif_reg(pv_caps));
+ pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps;
+ dev_priv->vgpu.pv_caps = pvcaps;
+ __raw_uncore_write32(uncore, vgtif_reg(pv_caps), pvcaps);
+
+ if (!pvcaps)
+ return false;
+
+ return true;
+}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index ebe1b7b..91010fc 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -42,7 +42,15 @@ intel_vgpu_has_huge_gtt(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
}
+static inline bool
+intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->vgpu.caps & VGT_CAPS_PV;
+}
+
int intel_vgt_balloon(struct drm_i915_private *dev_priv);
void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
+/* i915 vgpu
[Intel-gfx] [PATCH v6 8/8] drm/i915/gvt: GVTg support context submission pv optimization
implemented context submission pv optimizaiton within GVTg.
GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost and eliminate execlist HW behavior emulation
without injecting context switch interrupt to guest under PV
submisison mechanism.
v0: RFC.
v1: rebase.
v2: rebase.
v3: report pv context submission cap and handle VGT_G2V_ELSP_SUBMIT
g2v pv notification.
v4: eliminate execlist HW emulation and don't inject context switch
interrupt to guest under PV submisison mechanism.
v5: rebase.
v6: rebase.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/execlist.c | 6 ++
drivers/gpu/drm/i915/gvt/handlers.c | 29 -
drivers/gpu/drm/i915/gvt/vgpu.c | 1 +
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index f21b8fb..e52bfd6 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -382,6 +382,9 @@ static int prepare_execlist_workload(struct
intel_vgpu_workload *workload)
int ring_id = workload->ring_id;
int ret;
+ if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+ return 0;
+
if (!workload->emulate_schedule_in)
return 0;
@@ -429,6 +432,9 @@ static int complete_execlist_workload(struct
intel_vgpu_workload *workload)
goto out;
}
+ if (VGPU_PVCAP(vgpu, PV_SUBMISSION))
+ goto out;
+
ret = emulate_execlist_ctx_schedule_out(execlist, &workload->ctx_desc);
out:
intel_vgpu_unpin_mm(workload->shadow_mm);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index 1e09c23..9cff9396 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1692,6 +1692,31 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
}
+static int handle_pv_submission(struct intel_vgpu *vgpu, int ring_id)
+{
+ struct intel_vgpu_execlist *execlist;
+ u32 hw_id = vgpu->gvt->dev_priv->engine[ring_id]->hw_id;
+ u32 pv_elsp_off = offsetof(struct gvt_shared_page, buf.pv_elsp);
+ u32 submitted_off = offsetof(struct gvt_shared_page, buf.submitted);
+ bool submitted = true;
+ int ret;
+
+ execlist = &vgpu->submission.execlist[ring_id];
+
+ pv_elsp_off += hw_id * sizeof(struct pv_submission);
+ if (intel_gvt_read_shared_page(vgpu, pv_elsp_off,
+ &execlist->elsp_dwords.data, sizeof(struct pv_submission)))
+ return -EINVAL;
+
+ ret = intel_vgpu_submit_execlist(vgpu, ring_id);
+ if (ret)
+ submitted = false;
+
+ submitted_off += hw_id;
+ ret = intel_gvt_write_shared_page(vgpu, submitted_off, &submitted, 1);
+ return ret;
+}
+
static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
@@ -1703,8 +1728,10 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
return -EINVAL;
- execlist = &vgpu->submission.execlist[ring_id];
+ if (VGPU_PVCAP(vgpu, PV_SUBMISSION) && VGT_G2V_PV_SUBMISSION == data)
+ return handle_pv_submission(vgpu, ring_id);
+ execlist = &vgpu->submission.execlist[ring_id];
execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
if (execlist->elsp_dwords.index == 3) {
ret = intel_vgpu_submit_execlist(vgpu, ring_id);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 57eaf56..debdb88 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -51,6 +51,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
if (!intel_vtd_active())
vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = PV_PPGTT_UPDATE;
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) |= PV_SUBMISSION;
vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
vgpu_aperture_gmadr_base(vgpu);
--
2.7.4
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v6 2/8] drm/i915: vgpu shared memory setup for pv optimization
To enable vgpu pv features, we need to setup a shared memory page
which will be used for data exchange directly accessed between both
guest and backend i915 driver to avoid emulation trap cost.
guest i915 will allocate this page memory and then pass it's physical
address to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page meory without any trap cost with the
help form hyperviser's read guest gpa functionality.
guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT
once shared memory setup finished.
the layout of the shared_page also defined as well in this patch which
is used for pv features implementation.
v0: RFC.
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure.
v2: packed i915_virtual_gpu structure.
v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup
v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c.
v5: per engine desc data in shared memory.
v6: added version support in shared memory (Zhenyu).
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/i915_drv.h| 3 ++-
drivers/gpu/drm/i915/i915_pvinfo.h | 5 +++-
drivers/gpu/drm/i915/i915_vgpu.c | 48 ++
drivers/gpu/drm/i915/i915_vgpu.h | 31
4 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2bb38b4..9ccf37b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1244,7 +1244,8 @@ struct i915_virtual_gpu {
bool active;
u32 caps;
u32 pv_caps;
-};
+ struct gvt_shared_page *shared_page;
+} __packed;
/* used in computing the new watermarks state */
struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index 619305a..4657bf7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,7 @@ enum vgt_g2v_type {
VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
VGT_G2V_EXECLIST_CONTEXT_CREATE,
VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+ VGT_G2V_SHARED_PAGE_SETUP,
VGT_G2V_MAX,
};
@@ -110,7 +111,9 @@ struct vgt_if {
u32 pv_caps;
- u32 rsv7[0x200 - 25];/* pad to one page */
+ u64 shared_page_gpa;
+
+ u32 rsv7[0x200 - 27];/* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index bb9f988..6020515 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -135,6 +135,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
for (i = 0; i < 4; i++)
vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
+
+ if (dev_priv->vgpu.shared_page)
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
}
static int vgt_balloon_space(struct i915_ggtt *ggtt,
@@ -286,6 +289,46 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv)
* i915 vgpu PV support for Linux
*/
+/*
+ * shared_page setup for VGPU PV features
+ */
+static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ struct gvt_shared_page *shared_page;
+ u64 gpa;
+ u16 ver_maj, ver_min;
+
+ shared_page = (struct gvt_shared_page *)get_zeroed_page(GFP_KERNEL);
+ if (!shared_page) {
+ DRM_INFO("out of memory for shared page memory\n");
+ return -ENOMEM;
+ }
+
+ /* pass guest memory pa address to GVT and then read back to verify */
+ gpa = __pa(shared_page);
+ __raw_uncore_write64(uncore, vgtif_reg(shared_page_gpa), gpa);
+ if (gpa != __raw_uncore_read64(uncore, vgtif_reg(shared_page_gpa))) {
+ DRM_INFO("vgpu: passed shared_page_gpa failed\n");
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
+ return -EIO;
+ }
+
+ __raw_uncore_write32(uncore, vgtif_reg(g2v_notify),
+ VGT_G2V_SHARED_PAGE_SETUP);
+ ver_maj = shared_page->ver_major;
+ ver_min = shared_page->ver_minor;
+ DRM_INFO("vgpu PV ver major %d and minor %d\n", ver_maj, ver_min);
+ if (ver_maj != PV_MAJOR || ver_min != PV_MINOR) {
+ DRM_INFO("vgpu: shared_page format incompatible\n");
+ free_page((unsigned long)dev_priv->vgpu.shared_page);
+ return -EIO;
+ }
+
+ dev_priv->vgpu.shared_page = shared_page;
+ return 0;
+}
+
/**
* intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities
* @dev_priv: i915 device private
@@ -305,9 +348,14 @@ bool intel_vgpu_check_pv_caps(struct drm_i915_private
*dev_priv)
if (!intel_vgpu_has_pv_caps(dev_priv))
return false;
+ if (intel_vgpu_setup_shared_page(dev_priv
[Intel-gfx] [PATCH v6 6/8] drm/i915/gvt: GVTg handle shared_page setup
GVTg implemented shared_page setup operation and read_shared_page
functionality based on hypervisor_read_gpa().
the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.
v0: RFC.
v1: rebase.
v2: rebase.
v3: added shared_page_gpa check and if read_gpa failure, return zero
memory and handle VGT_G2V_SHARED_PAGE_SETUP g2v notification
v4: rebase.
v5: rebase.
v6: rebase, added PV version support.
Signed-off-by: Xiaolin Zhang
---
drivers/gpu/drm/i915/gvt/gvt.h | 8 ++-
drivers/gpu/drm/i915/gvt/handlers.c | 20 +
drivers/gpu/drm/i915/gvt/vgpu.c | 43 +
3 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index b54f2bd..1efbf68 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -49,6 +49,7 @@
#include "fb_decoder.h"
#include "dmabuf.h"
#include "page_track.h"
+#include "i915_vgpu.h"
#define GVT_MAX_VGPU 8
@@ -229,6 +230,8 @@ struct intel_vgpu {
struct completion vblank_done;
u32 scan_nonprivbb;
+ u64 shared_page_gpa;
+ bool shared_page_enabled;
};
/* validating GM healthy status*/
@@ -686,7 +689,10 @@ int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
int intel_gvt_debugfs_init(struct intel_gvt *gvt);
void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
-
+int intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
+int intel_gvt_write_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
#include "trace.h"
#include "mpt.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index fd2f72c..79679da 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1195,6 +1195,8 @@ static int pvinfo_mmio_read(struct intel_vgpu *vgpu,
unsigned int offset,
case 0x78010: /* vgt_caps */
case 0x7881c:
case _vgtif_reg(pv_caps):
+ case _vgtif_reg(shared_page_gpa):
+ case _vgtif_reg(shared_page_gpa) + 4:
break;
default:
invalid_read = true;
@@ -1212,6 +1214,9 @@ static int handle_g2v_notification(struct intel_vgpu
*vgpu, int notification)
enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
struct intel_vgpu_mm *mm;
u64 *pdps;
+ unsigned long gpa, gfn;
+ u16 ver_major = PV_MAJOR;
+ u16 ver_minor = PV_MINOR;
pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
@@ -1225,6 +1230,19 @@ static int handle_g2v_notification(struct intel_vgpu
*vgpu, int notification)
case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
+ case VGT_G2V_SHARED_PAGE_SETUP:
+ gpa = vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa));
+ gfn = gpa >> PAGE_SHIFT;
+ if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
+ vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = 0;
+ return 0;
+ }
+ vgpu->shared_page_gpa = gpa;
+ vgpu->shared_page_enabled = true;
+
+ intel_gvt_write_shared_page(vgpu, 0, &ver_major, 2);
+ intel_gvt_write_shared_page(vgpu, 2, &ver_minor, 2);
+ break;
case VGT_G2V_EXECLIST_CONTEXT_CREATE:
case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
case 1: /* Remove this in guest driver. */
@@ -1284,6 +1302,8 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu,
unsigned int offset,
case _vgtif_reg(pdp[3].hi):
case _vgtif_reg(execlist_context_descriptor_lo):
case _vgtif_reg(execlist_context_descriptor_hi):
+ case _vgtif_reg(shared_page_gpa):
+ case _vgtif_reg(shared_page_gpa) + 4:
break;
case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 3ecc45a..8cba30d 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -63,6 +63,8 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
+ vgpu_vreg64_t(vgpu, vgtif_reg(shared_page_gpa)) = 0;
+
gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
@@ -593,3 +595,44 @@ void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
intel_gvt_reset_vgpu_locked
