[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details ==
Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow
contexts
URL : https://patchwork.freedesktop.org/series/59970/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12883
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/59970/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12883:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_mmap_gtt@basic-read-no-prefault:
- {fi-cml-u}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/fi-cml-u/igt@gem_mmap_...@basic-read-no-prefault.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/fi-cml-u/igt@gem_mmap_...@basic-read-no-prefault.html
* igt@kms_chamelium@dp-edid-read:
- {fi-icl-u2}:NOTRUN -> [FAIL][3] +3 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Known issues
Here are the changes found in Patchwork_12883 that come from known issues:
### IGT changes ###
Possible fixes
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][4] ([fdo#109271] / [fdo#109278]) -> [PASS][5]
+2 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/fi-kbl-7567u/igt@kms_b...@basic-flip-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (36 -> 41)
--
Additional (11): fi-bxt-dsi fi-icl-u2 fi-snb-2520m fi-byt-clapper
fi-kbl-x1275 fi-icl-u3 fi-pnv-d510 fi-icl-y fi-byt-n2820 fi-bsw-kefka
fi-skl-6700k2
Missing(6): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-ctg-p8600
fi-bdw-samus fi-kbl-r
Build changes
-
* Linux: CI_DRM_6002 -> Patchwork_12883
CI_DRM_6002: 8e38b2c2f198640d840047e426ac009b59977633 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4966: a75429544f5721316b04a36551c57573e0c79486 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12883: 611e2f8185edadaa39814e9ec2a8f2a985d7da5c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
611e2f8185ed drm/i915: Move i915_request_alloc into selftests/
b8b3deab7463 drm/i915: Remove intel_context.active_link
1de6fe8b4c6b drm/i915: Switch back to an array of logical per-engine HW contexts
0c2380ccd81d drm/i915: Split engine setup/init into two phases
395147ecd9d8 drm/i915: Pass intel_context to intel_context_pin_lock()
b4ff336e38f5 drm/i915/selftests: Pass around intel_context for sseu
60311bf7fbd6 drm/i915/selftests: Use the real kernel context for sseu isolation
tests
14347632fcb4 drm/i915: Export intel_context_instance()
800faa589858 drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/
___
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Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming
On Thu, Apr 25, 2019 at 12:24 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> When I refactored the code into its own function I accidentally
> misplaced the <<16 shifts for some of the registers causing us
> to lose the blue channel entirely.
>
> We should really find a way to test this...
>
> Cc: Uma Shankar
> Fixes: d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming")
> Signed-off-by: Ville Syrjälä
+Clint
Does this fix the problem you reported earlier this week?
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/intel_color.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index ca341a9e47e6..9093daabc290 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -173,13 +173,13 @@ static void icl_update_output_csc(struct intel_crtc
> *crtc,
> I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
> coeff[1]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
> coeff[4]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
> coeff[7]);
> - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
> + I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
>
> I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
> I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
___
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[Intel-gfx] [PATCH i-g-t] i915/gem_tiling_max_stride: Skip if chipset is unknown
If we can't match the devid to a chipset, we do not have a reference for
the tiling strides. Instead of randomly failing, skip with a
semi-informative message.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523
Signed-off-by: Chris Wilson
---
tests/i915/gem_tiling_max_stride.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/tests/i915/gem_tiling_max_stride.c
b/tests/i915/gem_tiling_max_stride.c
index a6f97a915..0e99d979f 100644
--- a/tests/i915/gem_tiling_max_stride.c
+++ b/tests/i915/gem_tiling_max_stride.c
@@ -72,16 +72,18 @@ igt_simple_main
devid = intel_get_drm_devid(fd);
- if (intel_gen(devid) >= 7)
+ if (intel_gen(devid) >= 7) {
stride = 256 * 1024;
- else if (intel_gen(devid) >= 4)
+ } else if (intel_gen(devid) >= 4) {
stride = 128 * 1024;
- else {
- if (IS_GEN2(devid)) {
- tile_width = 128;
- tile_height = 16;
- }
+ } else if (intel_gen(devid) >= 3) {
+ stride = 8 * 1024;
+ } else if (intel_gen(devid) >= 2) {
+ tile_width = 128;
+ tile_height = 16;
stride = 8 * 1024;
+ } else {
+ igt_skip("Unknown Intel chipset, devid=%04x\n", devid);
}
size = stride * tile_height;
--
2.20.1
___
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Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
On 18/04/2019 18:06, Tvrtko Ursulin wrote: From: Tvrtko Ursulin WaEnableStateCacheRedirectToCS context workaround configures the L3 cache to benefit 3d workloads but media has different requirements. Remove the workaround and whitelist the register to allow any userspace configure the behaviour to their liking. v2: * Remove the workaround apart from adding the whitelist. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin Cc: kevin...@intel.com Cc: xiaogang...@intel.com Acked-by: Lionel Landwerlin Mesa commits : commit db5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (anv) commit eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (i965) commit d1be67db39463b48369cb71979ed18662b2c157e (iris) --- drivers/gpu/drm/i915/intel_workarounds.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index b3cbed1ee1c9..baed186724d2 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -556,10 +556,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine) WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN11_TDL_CLOCK_GATING_FIX_DISABLE); - /* WaEnableStateCacheRedirectToCS:icl */ - WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1, - GEN11_STATE_CACHE_REDIRECT_TO_CS); - /* Wa_2006665173:icl (pre-prod) */ if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, @@ -1070,6 +1066,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) /* WaAllowUMDToModifySamplerMode:icl */ whitelist_reg(w, GEN10_SAMPLER_MODE); + + /* WaEnableStateCacheRedirectToCS:icl */ + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); } void intel_engine_init_whitelist(struct intel_engine_cs *engine) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 2/8] drm/i915: Lift acquiring the vlv punit magic to a common sb-get
As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and release, moving it from the lowlevel punit rw
routine to the callers. In the first step, we move the punit magic into
the common sideband lock so that we can acquire a bunch of ports
simultaneously, and if need be extend the workaround protection later.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 124 +---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +-
drivers/gpu/drm/i915/intel_display.c| 37 +++
drivers/gpu/drm/i915/intel_dp.c | 4 +-
drivers/gpu/drm/i915/intel_dpio_phy.c | 37 +++
drivers/gpu/drm/i915/intel_dsi_vbt.c| 8 +-
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
drivers/gpu/drm/i915/intel_sideband.c | 45 ++---
drivers/gpu/drm/i915/vlv_dsi.c | 8 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c | 14 +--
12 files changed, 206 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 662dbd2e3245..b2215fb7f562 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3442,25 +3442,119 @@ int skl_pcode_request(struct drm_i915_private
*dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
/* intel_sideband.c */
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
-int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
-u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg,
u32 val);
-u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int
reg, u32 val);
+
+enum {
+ VLV_IOSF_SB_BUNIT,
+ VLV_IOSF_SB_CCK,
+ VLV_IOSF_SB_CCU,
+ VLV_IOSF_SB_DPIO,
+ VLV_IOSF_SB_FLISDSI,
+ VLV_IOSF_SB_GPIO,
+ VLV_IOSF_SB_NC,
+ VLV_IOSF_SB_PUNIT,
+};
+
+void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
+u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *i915,
+ u8 port, u32 reg, u32 val);
+void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
+
+static inline void vlv_bunit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_bunit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+static inline void vlv_cck_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
+void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_cck_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+static inline void vlv_ccu_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_ccu_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+static inline void vlv_dpio_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *i915,
+ enum pipe pipe, int reg, u32 val);
+
+static inline void vlv_dpio_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
+
[Intel-gfx] [CI 4/8] drm/i915: Replace pcu_lock with sb_lock
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pcu_lock is now redudant
and can be separated from its other use to regulate RPS (essentially
giving RPS a lock all of its own).
v2: Extract a couple of minor bug fixes.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++---
drivers/gpu/drm/i915/intel_cdclk.c | 28 --
drivers/gpu/drm/i915/intel_display.c| 6 --
drivers/gpu/drm/i915/intel_hdcp.c | 2 -
drivers/gpu/drm/i915/intel_pm.c | 128 +++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 --
drivers/gpu/drm/i915/intel_sideband.c | 4 -
10 files changed, 81 insertions(+), 168 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 6d98299fac67..3e1922e2185c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1046,8 +1046,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 rpmodectl, freq_sts;
- mutex_lock(&dev_priv->pcu_lock);
-
rpmodectl = I915_READ(GEN6_RP_CONTROL);
seq_printf(m, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
@@ -1082,7 +1080,6 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv, rps->efficient_freq));
- mutex_unlock(&dev_priv->pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
@@ -1487,12 +1484,9 @@ static int gen6_drpc_info(struct seq_file *m)
gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(dev_priv) <= 7) {
- mutex_lock(&dev_priv->pcu_lock);
+ if (INTEL_GEN(dev_priv) <= 7)
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
&rc6vids);
- mutex_unlock(&dev_priv->pcu_lock);
- }
seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -1756,17 +1750,10 @@ static int i915_ring_freq_table(struct seq_file *m,
void *unused)
unsigned int max_gpu_freq, min_gpu_freq;
intel_wakeref_t wakeref;
int gpu_freq, ia_freq;
- int ret;
if (!HAS_LLC(dev_priv))
return -ENODEV;
- wakeref = intel_runtime_pm_get(dev_priv);
-
- ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
- if (ret)
- goto out;
-
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
@@ -1777,6 +1764,7 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring
freq (MHz)\n");
+ wakeref = intel_runtime_pm_get(dev_priv);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
sandybridge_pcode_read(dev_priv,
@@ -1790,12 +1778,9 @@ static int i915_ring_freq_table(struct seq_file *m, void
*unused)
((ia_freq >> 0) & 0xff) * 100,
((ia_freq >> 8) & 0xff) * 100);
}
-
- mutex_unlock(&dev_priv->pcu_lock);
-
-out:
intel_runtime_pm_put(dev_priv, wakeref);
- return ret;
+
+ return 0;
}
static int i915_opregion(struct seq_file *m, void *unused)
@@ -2032,13 +2017,11 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
- mutex_unlock(&dev_priv->pcu_lock);
} else {
act_freq = intel_get_cagf(dev_priv,
I915_READ(GEN6_RPSTAT1));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i
[Intel-gfx] [CI 7/8] drm/i915: Merge sandybridge_pcode_(read|write)
These routines are identical except in the nature of the value parameter.
For writes it is a pure in-param, but for a read, we need an out-param.
Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/intel_pm.c | 115 +++-
1 file changed, 40 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4b763c28222f..4b1cd9041b33 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9704,12 +9704,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_UNIMPLEMENTED_CMD:
@@ -9722,17 +9720,15 @@ static inline int gen6_check_mailbox_status(struct
drm_i915_private *dev_priv)
case GEN6_PCODE_TIMEOUT:
return -ETIMEDOUT;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_ILLEGAL_CMD:
@@ -9744,19 +9740,21 @@ static inline int gen7_check_mailbox_status(struct
drm_i915_private *dev_priv)
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static int
-__sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
+ u32 mbox, u32 *val,
+ int fast_timeout_us,
+ int slow_timeout_ms,
+ bool is_read)
{
- int status;
-
lockdep_assert_held(&dev_priv->sb_lock);
- /* GEN6_PCODE_* are outside of the forcewake domain, we can
+ /*
+* GEN6_PCODE_* are outside of the forcewake domain, we can
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
@@ -9770,70 +9768,37 @@ __sandybridge_pcode_read(struct drm_i915_private
*dev_priv, u32 mbox, u32 *val)
if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY,
0,
-500, 0, NULL))
+fast_timeout_us,
+slow_timeout_ms,
+&mbox))
return -ETIMEDOUT;
- *val = I915_READ_FW(GEN6_PCODE_DATA);
- I915_WRITE_FW(GEN6_PCODE_DATA, 0);
+ if (is_read)
+ *val = I915_READ_FW(GEN6_PCODE_DATA);
if (INTEL_GEN(dev_priv) > 6)
- status = gen7_check_mailbox_status(dev_priv);
+ return gen7_check_mailbox_status(dev_priv, mbox);
else
- status = gen6_check_mailbox_status(dev_priv);
-
- return status;
+ return gen6_check_mailbox_status(dev_priv, mbox);
}
int
sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
{
- int status;
+ int err;
mutex_lock(&dev_priv->sb_lock);
- status = __sandybridge_pcode_read(dev_priv, mbox, val);
+ err = __sandybridge_pcode_rw(dev_priv, mbox, val,
+500, 0,
+true);
mutex_unlock(&dev_priv->sb_lock);
- if (status) {
+ if (err) {
DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox
access failed for %ps: %d\n",
-mbox, __builtin_return_address(0), status);
+mbox, __builtin_return_address(0), err);
}
- return status;
-}
-
-static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
-u32 mbox, u32 val,
-
[Intel-gfx] [CI 3/8] drm/i915: Lift sideband locking for vlv_punit_(read|write)
Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
into their callers, so that we can lock the sideband once for a sequence
of operations, rather than perform the heavyweight acquisition on each
request.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++
drivers/gpu/drm/i915/i915_sysfs.c | 14
drivers/gpu/drm/i915/intel_cdclk.c | 23 ++---
drivers/gpu/drm/i915/intel_display.c| 16 +
drivers/gpu/drm/i915/intel_pm.c | 46 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++
drivers/gpu/drm/i915/intel_sideband.c | 18 ++
7 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 00d3ff746eb1..6d98299fac67 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1057,7 +1057,10 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
+ vlv_punit_get(dev_priv);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
+
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -2030,8 +2033,10 @@ static int i915_rps_boost_info(struct seq_file *m, void
*data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
mutex_unlock(&dev_priv->pcu_lock);
} else {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..bfabb3de4808 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -259,25 +259,25 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
intel_wakeref_t wakeref;
- int ret;
+ u32 freq;
wakeref = intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- u32 freq;
+ vlv_punit_get(dev_priv);
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
+ vlv_punit_put(dev_priv);
+
+ freq = (freq >> 8) & 0xff;
} else {
- ret = intel_gpu_freq(dev_priv,
-intel_get_cagf(dev_priv,
- I915_READ(GEN6_RPSTAT1)));
+ freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1));
}
mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv, wakeref);
- return snprintf(buf, PAGE_SIZE, "%d\n", ret);
+ return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
}
static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 5845d0a37599..9dd22203a7e8 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -464,13 +464,19 @@ static void vlv_get_cdclk(struct drm_i915_private
*dev_priv,
{
u32 val;
+ mutex_lock(&dev_priv->pcu_lock);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
+
cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_state->vco);
- mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
+
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
mutex_unlock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv))
@@ -545,6 +551,11 @@ static void vlv_set_cdclk(struct drm_i915_private
*dev_priv,
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) |
+ BIT(VLV_IOSF_SB_BUNIT) |
+ BIT(VLV_IOSF_SB_PUNIT));
+
mutex_lock(&dev_p
[Intel-gfx] [CI 1/8] drm/i915: Disable preemption and sleeping while using the punit sideband
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idle) doesn't provide a sufficient barrier to ensure that all core
are indeed awake (out of Cstate) and that the package is awake. To do so,
we need to supplement the pm_qos with a manual ping on_each_cpu.
v2: Restrict the heavy-weight wakeup to just the ISOF_PORT_PUNIT, there
is insufficient evidence to implicate a wider problem atm. Similarly,
restrict the w/a to Valleyview, as Cherryview doesn't have an angry cadre
of users.
The working theory, courtesy of Ville and Hans, is the issue lies within
the power delivery and so is likely to be unit and board specific and
occurs when both the unit/fw require extra power at the same time as the
cpu package is changing its own power state.
References: https://bugzilla.kernel.org/show_bug.cgi?id=109051
References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
References: https://bugzilla.kernel.org/show_bug.cgi?id=195255
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Hans de Goede
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 203 +-
3 files changed, 139 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 824409ffd03f..aacc8dd6ecfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -886,6 +886,9 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
mutex_init(&dev_priv->backlight_lock);
mutex_init(&dev_priv->sb_lock);
+ pm_qos_add_request(&dev_priv->sb_qos,
+ PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+
mutex_init(&dev_priv->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
@@ -945,6 +948,9 @@ static void i915_driver_cleanup_early(struct
drm_i915_private *dev_priv)
i915_gem_cleanup_early(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
+
+ pm_qos_remove_request(&dev_priv->sb_qos);
+ mutex_destroy(&dev_priv->sb_lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5c77bf5b735b..662dbd2e3245 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1561,6 +1561,7 @@ struct drm_i915_private {
/* Sideband mailbox protection */
struct mutex sb_lock;
+ struct pm_qos_request sb_qos;
/** Cached value of IMR to avoid reads in updating the bitfield */
union {
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 57de41b1f989..fc8913461622 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -22,6 +22,8 @@
*
*/
+#include
+
#include "i915_drv.h"
#include "intel_drv.h"
@@ -39,19 +41,50 @@
/* Private register write, double-word addressing, non-posted */
#define SB_CRWRDA_NP 0x07
-static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
- u32 port, u32 opcode, u32 addr, u32 *val)
+static void ping(void *info)
{
- u32 cmd, be = 0xf, bar = 0;
- bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
+}
- cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
- (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
- (bar << IOSF_BAR_SHIFT);
+static void __vlv_punit_get(struct drm_i915_private *i915)
+{
+ iosf_mbi_punit_acquire();
- WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
+ /*
+* Prevent the cpu from sleeping while we use this sideband, otherwise
+* the punit may cause a machine hang. The issue appears to be isolated
+* with changing the power state of the CPU package while changing
+* the power state via the punit, and we have only observed it
+* reliably on 4-core Baytail systems suggesting the issue is in the
+* power delivery mechanism and likely to be be board/function
+* specific. Hence we presume the workaround needs only be applied
+* to the Valleyview P-unit and not all sideband communications.
+*/
+ if (IS_VALLEYVIEW(i915)) {
+ pm_qos_update_request(&i915->sb_qos, 0);
+ on_each_cpu(ping, NULL, 1);
+ }
+}
- if (intel_wait_for_register(&dev_priv->uncore,
+static void __vlv_punit_put(struct drm_i915_private *i915)
+{
+ if (IS_VALLEYVIEW(i915))
+ pm_qos_update_request(&i915->sb_qos, PM_QOS_DEFAULT_VALUE);
+
+ iosf_mbi_punit_release();
+}
+
+static int vlv_sideband_rw(struct drm_i915_private *i915,
+
[Intel-gfx] [CI 5/8] drm/i915: Separate sideband declarations to intel_sideband.h
Split the sideback declarations out of the ginormous i915_drv.h
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile.header-test | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 120
drivers/gpu/drm/i915/i915_sysfs.c | 2 +
drivers/gpu/drm/i915/intel_cdclk.c| 1 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 13 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 2 +
drivers/gpu/drm/i915/intel_sideband.h | 130 ++
drivers/gpu/drm/i915/vlv_dsi.c| 2 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c| 4 +-
16 files changed, 157 insertions(+), 126 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_sideband.h
diff --git a/drivers/gpu/drm/i915/Makefile.header-test
b/drivers/gpu/drm/i915/Makefile.header-test
index 702e3a7ade4c..325071da0ff7 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -30,6 +30,7 @@ header_test := \
intel_pipe_crc.h \
intel_pm.h \
intel_psr.h \
+ intel_sideband.h \
intel_sdvo.h \
intel_sprite.h \
intel_tv.h \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e1922e2185c..bc94b778da6f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -42,6 +42,7 @@
#include "intel_hdmi.h"
#include "intel_pm.h"
#include "intel_psr.h"
+#include "intel_sideband.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ca1b35d8faca..c18b28271bfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -541,11 +541,6 @@ enum intel_pch {
PCH_ICP,/* Ice Lake PCH */
};
-enum intel_sbi_destination {
- SBI_ICLK,
- SBI_MPHY,
-};
-
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
@@ -3435,121 +3430,6 @@ int sandybridge_pcode_write_timeout(struct
drm_i915_private *dev_priv, u32 mbox,
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-/* intel_sideband.c */
-
-enum {
- VLV_IOSF_SB_BUNIT,
- VLV_IOSF_SB_CCK,
- VLV_IOSF_SB_CCU,
- VLV_IOSF_SB_DPIO,
- VLV_IOSF_SB_FLISDSI,
- VLV_IOSF_SB_GPIO,
- VLV_IOSF_SB_NC,
- VLV_IOSF_SB_PUNIT,
-};
-
-void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
- u8 port, u32 reg, u32 val);
-void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
-
-static inline void vlv_bunit_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_bunit_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-static inline void vlv_cck_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
-void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_cck_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-static inline void vlv_ccu_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_ccu_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-static inline void vlv_dpio_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *i915,
- enum pipe pipe, int reg, u32 val);
-
-static inline void vlv_dpio_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
-}
-
-u32 vlv_flisds
[Intel-gfx] [CI 8/8] drm/i915: Move sandybride pcode access to intel_sideband.c
sandybride_pcode is another sideband, so move it to their new home.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 195 -
drivers/gpu/drm/i915/intel_sideband.c | 196 ++
drivers/gpu/drm/i915/intel_sideband.h | 10 ++
5 files changed, 207 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c18b28271bfd..1cea98f8b85c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3420,16 +3420,6 @@ intel_display_capture_error_state(struct
drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_display_error_state
*error);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32
*val);
-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32
mbox,
- u32 val, int fast_timeout_us,
- int slow_timeout_ms);
-#define sandybridge_pcode_write(dev_priv, mbox, val) \
- sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
-
-int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms);
-
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
b/drivers/gpu/drm/i915/intel_hdcp.c
index 2476e867981d..ca5982e45e3e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -16,6 +16,7 @@
#include "i915_reg.h"
#include "intel_drv.h"
#include "intel_hdcp.h"
+#include "intel_sideband.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4b1cd9041b33..3687e9165956 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9704,201 +9704,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_UNIMPLEMENTED_CMD:
- return -ENODEV;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- case GEN6_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN7_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- case GEN7_PCODE_ILLEGAL_DATA:
- return -EINVAL;
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
- u32 mbox, u32 *val,
- int fast_timeout_us,
- int slow_timeout_ms,
- bool is_read)
-{
- lockdep_assert_held(&dev_priv->sb_lock);
-
- /*
-* GEN6_PCODE_* are outside of the forcewake domain, we can
-* use te fw I915_READ variants to reduce the amount of work
-* required when reading/writing.
-*/
-
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
- return -EAGAIN;
-
- I915_WRITE_FW(GEN6_PCODE_DATA, *val);
- I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
- I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
-
- if (__intel_wait_for_register_fw(&dev_priv->uncore,
-GEN6_PCODE_MAILBOX, GEN6_PCODE_READY,
0,
-fast_timeout_us,
-slow_timeout_ms,
-&mbox))
- return -ETIMEDOUT;
-
- if (is_read)
- *val = I915_READ_FW(GEN6_PCODE_DATA);
-
-
[Intel-gfx] [CI 6/8] drm/i915: Merge sbi read/write into a single accessor
Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.
v2: Restore vlv_flisdsi_read() lost during rebasing.
Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sideband.c | 94 +++
1 file changed, 38 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index 5c3ae5185a01..7113fb8850d6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -273,81 +273,63 @@ void vlv_flisdsi_write(struct drm_i915_private *i915, u32
reg, u32 val)
}
/* SBI access */
-u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
- enum intel_sbi_destination destination)
+static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination,
+ u32 *val, bool is_read)
{
- u32 value = 0;
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 cmd;
- lockdep_assert_held(&dev_priv->sb_lock);
+ lockdep_assert_held(&i915->sb_lock);
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
+ if (intel_wait_for_register_fw(uncore,
+ SBI_CTL_STAT, SBI_BUSY, 0,
+ 100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
- return 0;
+ return -EBUSY;
}
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, 0);
+ intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
+ intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
if (destination == SBI_ICLK)
- value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
+ cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
else
- value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
- I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
-
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
+ cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
+ if (!is_read)
+ cmd |= BIT(8);
+ intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
+
+ if (__intel_wait_for_register_fw(uncore,
+SBI_CTL_STAT, SBI_BUSY, 0,
+100, 100, &cmd)) {
DRM_ERROR("timeout waiting for SBI to complete read\n");
- return 0;
+ return -ETIMEDOUT;
}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+ if (cmd & SBI_RESPONSE_FAIL) {
DRM_ERROR("error during SBI read of reg %x\n", reg);
- return 0;
+ return -ENXIO;
}
- return I915_READ(SBI_DATA);
+ if (is_read)
+ *val = intel_uncore_read_fw(uncore, SBI_DATA);
+
+ return 0;
}
-void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
-enum intel_sbi_destination destination)
+u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination)
{
- u32 tmp;
+ u32 result = 0;
- lockdep_assert_held(&dev_priv->sb_lock);
+ intel_sbi_rw(i915, reg, destination, &result, true);
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to become ready\n");
- return;
- }
-
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, value);
-
- if (destination == SBI_ICLK)
- tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
- else
- tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
- I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
-
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to complete write\n");
- return;
- }
+ return result;
+}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
- DRM_ERROR("error during SBI write of %x to reg %x\n",
- value, reg);
- return;
- }
+void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
+enum intel_s
Re: [Intel-gfx] [PATCH v3 0/9] drm/i915/perf: add OA interrupt support
FYI, MDAPI got tired of waiting for this to land upstream : https://github.com/intel/metrics-discovery/commit/7b6399d5d5e5ef5fcc018a48853b46d0803da441 Apart from squashing the last commit, any other change needed? Thanks, -Lionel On 03/04/2019 00:36, Lionel Landwerlin wrote: On 02/04/2019 14:49, Joonas Lahtinen wrote: Quoting Lionel Landwerlin (2019-03-25 12:34:44) Ping? The last patch should be squashed, I think we want to minimize the amount of versions. Or do you intend to backport only portion of the series somewhere? No backport intended :) Can you link to the userspace side changes? https://github.com/rib/gputop/pull/198 Regards, Joonas On 26/02/2019 14:29, Lionel Landwerlin wrote: Hi all, This third iteration adds an i915 perf revision number through getparam so that application can more easily find out what feature of i915-perf are available. The patches containing uAPI updates have been updated to indicate what version is required to those changes to be available. Cheers, Lionel Landwerlin (9): drm/i915/perf: rework aging tail workaround drm/i915/perf: move pollin setup to non hw specific code drm/i915/perf: only append status when data is available drm/i915/perf: introduce a versioning of the i915-perf uapi drm/i915/perf: add new open param to configure polling of OA buffer drm/i915: handle interrupts from the OA unit drm/i915/perf: add interrupt enabling parameter drm/i915/perf: add flushing ioctl drm/i915/perf: bump i915-perf revision drivers/gpu/drm/i915/i915_drv.c | 3 + drivers/gpu/drm/i915/i915_drv.h | 59 +++- drivers/gpu/drm/i915/i915_irq.c | 39 ++- drivers/gpu/drm/i915/i915_perf.c | 403 ++-- drivers/gpu/drm/i915/i915_reg.h | 7 + drivers/gpu/drm/i915/intel_ringbuffer.c | 2 + include/uapi/drm/i915_drm.h | 61 7 files changed, 390 insertions(+), 184 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
+ Anuj Quoting Lionel Landwerlin (2019-04-26 11:13:58) > On 18/04/2019 18:06, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > > > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache > > to benefit 3d workloads but media has different requirements. > > > > Remove the workaround and whitelist the register to allow any userspace > > configure the behaviour to their liking. > > > > v2: > > * Remove the workaround apart from adding the whitelist. > > > > Signed-off-by: Tvrtko Ursulin > > Cc: Lionel Landwerlin > > Cc: kevin...@intel.com > > Cc: xiaogang...@intel.com > > > Acked-by: Lionel Landwerlin > > > Mesa commits : > > commit db5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (anv) > > commit eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (i965) > > commit d1be67db39463b48369cb71979ed18662b2c157e (iris) Could somebody confirm that applying this patch does not cause hangs in older mesa, and the performance drop (if any) is insignificant? Best Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/icl: Factor out combo PHY lane power setup helper
== Series Details == Series: series starting with [v2,1/2] drm/i915/icl: Factor out combo PHY lane power setup helper URL : https://patchwork.freedesktop.org/series/59954/ State : success == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12877_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12877_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb6/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-iclb3/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rpm@legacy-planes: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#107807]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl5/igt@i915_pm_...@legacy-planes.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl6/igt@i915_pm_...@legacy-planes.html * igt@kms_cursor_crc@cursor-64x64-dpms: - shard-skl: [PASS][5] -> [FAIL][6] ([fdo#103232]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl8/igt@kms_cursor_...@cursor-64x64-dpms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl5/igt@kms_cursor_...@cursor-64x64-dpms.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-pgflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-indfb-pgflip-blt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl3/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-b.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl5/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_psr2...@frontbuffer.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-iclb1/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-iclb8/igt@kms_psr@psr2_sprite_render.html * igt@kms_psr@suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#107773]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl7/igt@kms_...@suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-skl1/igt@kms_...@suspend.html * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103665]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-kbl4/igt@kms_rotation_...@multiplane-rotation.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-kbl4/igt@kms_rotation_...@multiplane-rotation.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12877/shard-apl7/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [INCOMPLETE][25] ([fdo#103665]) -> [PASS][26] [25]
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : warning == Summary == $ dim checkpatch origin/drm-tip ab284a305f9c drm/i915: Disable preemption and sleeping while using the punit sideband e7be3c512489 drm/i915: Lift acquiring the vlv punit magic to a common sb-get 8358de9d6280 drm/i915: Lift sideband locking for vlv_punit_(read|write) e0a643c560ce drm/i915: Replace pcu_lock with sb_lock f826ec971392 drm/i915: Separate sideband declarations to intel_sideband.h -:328: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #328: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 402 lines checked cc3096c5f676 drm/i915: Merge sbi read/write into a single accessor fce0d4113122 drm/i915: Merge sandybridge_pcode_(read|write) 12cdeff071d7 drm/i915: Move sandybride pcode access to intel_sideband.c ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Disable preemption and sleeping while using the punit sideband -drivers/gpu/drm/i915/selftests/../i915_drv.h:3611:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3612:16: warning: expression using sizeof(void) Commit: drm/i915: Lift acquiring the vlv punit magic to a common sb-get -drivers/gpu/drm/i915/selftests/../i915_drv.h:3612:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) Commit: drm/i915: Lift sideband locking for vlv_punit_(read|write) Okay! Commit: drm/i915: Replace pcu_lock with sb_lock -drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) Commit: drm/i915: Separate sideband declarations to intel_sideband.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3580:16: warning: expression using sizeof(void) Commit: drm/i915: Merge sbi read/write into a single accessor Okay! Commit: drm/i915: Merge sandybridge_pcode_(read|write) Okay! Commit: drm/i915: Move sandybride pcode access to intel_sideband.c -drivers/gpu/drm/i915/selftests/../i915_drv.h:3580:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping
while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59980/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6002 -> Patchwork_12884
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/59980/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12884:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_chamelium@dp-hpd-fast:
- {fi-icl-u2}:NOTRUN -> [FAIL][1] +3 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/fi-icl-u2/igt@kms_chamel...@dp-hpd-fast.html
Known issues
Here are the changes found in Patchwork_12884 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_cpu_reloc@basic:
- fi-apl-guc: [PASS][2] -> [INCOMPLETE][3] ([fdo#103927])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/fi-apl-guc/igt@gem_cpu_re...@basic.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/fi-apl-guc/igt@gem_cpu_re...@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][4] -> [INCOMPLETE][5] ([fdo#107718])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
Participating hosts (36 -> 36)
--
Additional (7): fi-bxt-dsi fi-icl-u2 fi-snb-2520m fi-kbl-x1275 fi-icl-u3
fi-icl-y fi-byt-clapper
Missing(7): fi-kbl-soraka fi-kbl-7567u fi-ilk-m540 fi-kbl-guc
fi-ctg-p8600 fi-hsw-4770 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6002 -> Patchwork_12884
CI_DRM_6002: 8e38b2c2f198640d840047e426ac009b59977633 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4966: a75429544f5721316b04a36551c57573e0c79486 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12884: 12cdeff071d7601ee42d29ea9f22cfa7ed8fb5e3 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
12cdeff071d7 drm/i915: Move sandybride pcode access to intel_sideband.c
fce0d4113122 drm/i915: Merge sandybridge_pcode_(read|write)
cc3096c5f676 drm/i915: Merge sbi read/write into a single accessor
f826ec971392 drm/i915: Separate sideband declarations to intel_sideband.h
e0a643c560ce drm/i915: Replace pcu_lock with sb_lock
8358de9d6280 drm/i915: Lift sideband locking for vlv_punit_(read|write)
e7be3c512489 drm/i915: Lift acquiring the vlv punit magic to a common sb-get
ab284a305f9c drm/i915: Disable preemption and sleeping while using the punit
sideband
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix ICL output CSC programming
== Series Details == Series: drm/i915: Fix ICL output CSC programming URL : https://patchwork.freedesktop.org/series/59955/ State : success == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12878_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12878_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-snb5/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-snb2/igt@gem_...@unwedge-stress.html * igt@gem_exec_whisper@normal: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl1/igt@gem_exec_whis...@normal.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-apl8/igt@gem_exec_whis...@normal.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107773]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl5/igt@gem_soft...@noreloc-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-skl1/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#108686]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-hsw2/igt@gem_tiled_swapp...@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-hsw2/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl4/igt@i915_susp...@debugfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-apl6/igt@i915_susp...@debugfs-reader.html * igt@kms_cursor_crc@cursor-64x64-dpms: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103232]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl8/igt@kms_cursor_...@cursor-64x64-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-skl7/igt@kms_cursor_...@cursor-64x64-dpms.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: [PASS][13] -> [FAIL][14] ([fdo#102887] / [fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-glk4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-glk5/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl10/igt@kms_flip_til...@flip-changes-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-skl7/igt@kms_flip_til...@flip-changes-tiling.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-iclb4/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl8/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-skl7/igt@kms_plane_alpha_bl...@pipe-b-coverage-7efc.html * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: [PASS][21] -> [SKIP][22] ([fdo#109271] / [fdo#109278]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-glk9/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-glk5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109642]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_psr2...@frontbuffer.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12878/shard-iclb3/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues [25]: https://intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Fix 90/270 degree rotated RGB565 src coord checks
== Series Details == Series: drm/i915: Fix 90/270 degree rotated RGB565 src coord checks URL : https://patchwork.freedesktop.org/series/59956/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12879_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12879_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12879_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12879_full: ### IGT changes ### Possible regressions * igt@kms_ccs@pipe-b-crc-primary-basic: - shard-kbl: [PASS][1] -> [FAIL][2] +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-kbl7/igt@kms_...@pipe-b-crc-primary-basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-kbl3/igt@kms_...@pipe-b-crc-primary-basic.html * igt@kms_ccs@pipe-b-crc-primary-rotation-180: - shard-glk: [PASS][3] -> [FAIL][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-glk5/igt@kms_...@pipe-b-crc-primary-rotation-180.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-glk1/igt@kms_...@pipe-b-crc-primary-rotation-180.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-apl: [PASS][5] -> [FAIL][6] +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl7/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-apl6/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html Warnings * igt@kms_content_protection@legacy: - shard-apl: [FAIL][7] ([fdo#110321] / [fdo#110336]) -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl4/igt@kms_content_protect...@legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-apl8/igt@kms_content_protect...@legacy.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-glk: [SKIP][9] ([fdo#109271]) -> [FAIL][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-glk2/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-glk2/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html Known issues Here are the changes found in Patchwork_12879_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl2/igt@gem_workarou...@suspend-resume.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-apl5/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_rpm@legacy-planes: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#107807]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl5/igt@i915_pm_...@legacy-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-skl9/igt@i915_pm_...@legacy-planes.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#109052]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-kbl4/igt@kms_pl...@pixel-format-pipe-a-planes-source-clamping.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-kbl2/igt@kms_pl...@pixel-format-pipe-a-planes-source-clamping.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#109052]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl10/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-skl8/igt@kms_pl...@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([fdo#103665]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-kbl4/igt@kms_rotation_...@multiplane-rotation.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12879/shard-kbl5/igt@kms_rotation_...@multiplane-rotation.html * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: [PASS][21] -> [DMESG-FAIL][22] ([fdo#105763]) [21]: https://intel-gfx-ci.01.org/tr
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/7] drm/i915: Introduce intel_irq
== Series Details == Series: series starting with [1/7] drm/i915: Introduce intel_irq URL : https://patchwork.freedesktop.org/series/59958/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6000_full -> Patchwork_12880_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12880_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12880_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12880_full: ### IGT changes ### Possible regressions * igt@gem_mmap_wc@write-cpu-read-wc: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl8/igt@gem_mmap...@write-cpu-read-wc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-skl10/igt@gem_mmap...@write-cpu-read-wc.html Known issues Here are the changes found in Patchwork_12880_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@vcs0-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl1/igt@gem_ctx_isolat...@vcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-skl6/igt@gem_ctx_isolat...@vcs0-s3.html * igt@i915_pm_rpm@universal-planes: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#107807]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl2/igt@i915_pm_...@universal-planes.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-skl10/igt@i915_pm_...@universal-planes.html * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-skl4/igt@kms_f...@flip-vs-expired-vblank-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-skl7/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-skl1/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-c.html * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-glk9/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-glk6/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_psr2...@frontbuffer.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-iclb5/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([fdo#108566]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-apl2/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12880/shard-apl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes * igt@kms_cursor_crc@cursor-256x256-suspend: - shard-kbl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6000/shard-kbl5/igt@kms_cursor_...@cursor-256x256-suspend.html [22]: ht
Re: [Intel-gfx] [PATCH v7] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote: > On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote: > > On Fri, 05 Apr 2019, Aditya Swarup wrote: > > > From: Clinton Taylor > > > > > > v2: Fix commit msg to reflect why issue occurs(Jani) > > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color. > > > > > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa) > > > doesn't work correctly using xrandr max bpc property. When we > > > connect a monitor which supports deep color, the highest deep color > > > setting is selected; which sets GCP_COLOR_INDICATION. When we change > > > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which > > > doesn't allow the switch back to 8 bit color. > > > > > > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville) > > > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc. > > > > > > Drop the changes in intel_hdmi_compute_config as desired_bpp > > > is needed to change values for pipe_bpp based on bw_constrained flag. > > > > > > v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION. > > > > > > v6: Fix comment formatting (Ville) > > > > > > v7: Add reviewed by Ville > > > > > > Signed-off-by: Clinton Taylor > > > Signed-off-by: Aditya Swarup > > > Cc: Ville Syrjälä > > > Cc: Jani Nikula > > > Cc: Manasi Navare > > > Reviewed-by: Ville Syrjälä > > > --- > > > drivers/gpu/drm/i915/intel_hdmi.c | 7 +-- > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > > > b/drivers/gpu/drm/i915/intel_hdmi.c > > > index 5ccb305a6e1c..f2c0aba4371b 100644 > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > > @@ -962,8 +962,11 @@ static void intel_hdmi_compute_gcp_infoframe(struct > > > intel_encoder *encoder, > > > crtc_state->infoframes.enable |= > > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); > > > > > > - /* Indicate color depth whenever the sink supports deep color */ > > > - if (hdmi_sink_is_deep_color(conn_state)) > > > + /* Indicate color depth whenever the sink supports deep color > > > + * Also, 8bpc + color depth indication is no longer supported > > > + * for HSW+ platforms. > > > + */ > > > > Frankly the comment confuses me as the condition has nothing to do with > > HSW+ and applies for pre-HSW as well. And the "whenever" in the first > > line is no longer true. > > You are correct, Clint and me spent time investigating this Spec/HW > monstrosity for the correct conditions required for sending > GCP_COLOR_INDICATION. > > > > > I do understand the point here, we don't need to use color indication > > when we're not using deep color anyway, and moreover this combo isn't > > supported on HSW+. > > > > The final question is, under what circumstances would we use pipe_bpp > > > 24 when the sink does *not* support bpc > 8? > > > > IOW, could we simply use > > > > if (crtc_state->pipe_bpp > 24) > > > > here? > No we do need the check for sink, as that is the real check for > determining whether sink supports deep color or not. For some platforms, > we do send GCP_COLOR_INDICATION even for 8 bpc when the sink supports > deep color. This will be clear with the next version of the patch. I think Jani is right. pipe_bpp will not be > 24 unless the sink support deep color. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work correctly using xrandr max bpc property. When we
> connect a monitor which supports deep color, the highest deep color
> setting is selected; which sets GCP_COLOR_INDICATION. When we change
> the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> doesn't allow the switch back to 8 bit color.
>
> v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville)
> Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
>
> Drop the changes in intel_hdmi_compute_config as desired_bpp
> is needed to change values for pipe_bpp based on bw_constrained flag.
>
> v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
>
> v6: Fix comment formatting (Ville)
>
> v7: Add reviewed by Ville
>
> v8: Set GCP_COLOR_INDICATION based on spec:
> For Gen 7.5 or later platforms, indicate color depth only for deep
> color modes. Bspec: 8135,7751,50524
>
> Pre DDI platforms, indicate color depth if deep color is supported
> by sink. Bspec: 7854
>
> Exception: CHERRYVIEW behaves like Pre DDI platforms.
> Bspec: 15975
>
> Check pipe_bpp is less than bpp * 3 in hdmi_deep_color_possible,
> to not set 12 bit deep color for every modeset. This fixes the issue
> where 12 bit color was selected even when user selected 10 bit.(Ville)
>
> Co-Developed-by: Aditya Swarup
> Co-Developed-by: Ville Syrjälä
> Signed-off-by: Clinton Taylor
> Signed-off-by: Aditya Swarup
> Cc: Ville Syrjälä
> Cc: Jani Nikula
> Cc: Manasi Navare
> Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index e1005d7b75fd..620bc89e2120 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -973,9 +973,18 @@ static void intel_hdmi_compute_gcp_infoframe(struct
> intel_encoder *encoder,
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
>
> - /* Indicate color depth whenever the sink supports deep color */
> - if (hdmi_sink_is_deep_color(conn_state))
> - crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> + /* Indicate color depth whenever the sink supports deep color:
> + * For Gen 7.5 or later platforms, indicate color depth only for deep
> + * color modes.
> + * Pre DDI platforms, indicate color depth if deep color is supported
> + * by sink.
> + * Exception: CHERRYVIEW behaves like Pre DDI platforms.
> + */
> + if (hdmi_sink_is_deep_color(conn_state)) {
> + if(!HAS_DDI(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> +crtc_state->pipe_bpp > 24)
I prefer the earlier version. Less special casing.
> + crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> + }
>
> /* Enable default_phase whenever the display mode is suitably aligned */
> if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> @@ -2172,7 +2181,7 @@ static bool hdmi_deep_color_possible(const struct
> intel_crtc_state *crtc_state,
> if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
> return false;
>
> - if (crtc_state->pipe_bpp <= 8*3)
> + if (crtc_state->pipe_bpp < bpc*3)
This should be a separate patch.
> return false;
>
> if (!crtc_state->has_hdmi_sink)
> --
> 2.17.1
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/3] drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
Quoting Ville Syrjälä (2019-04-23 16:36:47)
> On Fri, Apr 19, 2019 at 12:17:47PM +0100, Chris Wilson wrote:
> > Despite what I think the prm recommends, commit f2253bd9859b
> > ("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
> > to be a huge mistake when enabling Ironlake contexts as the GPU would
> > hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
> > MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
> > simple rendercopies with igt, do not suffer).
>
> Where is the recommendation you mention? I couldn't immediately find it
> in the docs. I did find the following statemtement:
Sadly, it probably Chinese whispers from our code comments. I have
recollection of us having a comment about expected ordering and not
obeying because we "always invalidate before the batch". I have some
recollection of seeing related instructions in the ye old bspec, but I
cannot lay my hands on anything concreter right now.
> "[DevCTG+]: For the invalidate operation of the pipe control, the
> following pointers are affected. The
> invalidate operation affects the restore of these packets. If the pipe
> control invalidate operation is completed
> before the context save, the indirect pointers will not be restored from
> memory.
> 1. Pipeline State Pointer
> 2. Media State Pointer
> 3. Constant Buffer Packet"
>
> Which maybe has something to do with this ordering?
That's very interesting. If the invalidate is preventing the loading of
dangling pointer, then yes, it fits with the observation in this patch.
There's also a comment about ensure we flush media before switching to a
3D context (which we do by virtue of the flush-everything after a
request -- or we should!).
> But it's all black magic anyways. If it works it works.
> Reviewed-by: Ville Syrjälä
Proof is in the eating. Ta,
-Chris
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Re: [Intel-gfx] [PATCH 01/45] drm/i915: Seal races between async GPU cancellation, retirement and signaling
On 25/04/2019 11:42, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-04-25 11:35:01)
On 25/04/2019 10:19, Chris Wilson wrote:
Currently there is an underlying assumption that i915_request_unsubmit()
is synchronous wrt the GPU -- that is the request is no longer in flight
as we remove it. In the near future that may change, and this may upset
our signaling as we can process an interrupt for that request while it
is no longer in flight.
CPU0 CPU1
intel_engine_breadcrumbs_irq
(queue request completion)
i915_request_cancel_signaling
... ...
i915_request_enable_signaling
dma_fence_signal
Hence in the time it took us to drop the lock to signal the request, a
preemption event may have occurred and re-queued the request. In the
process, that request would have seen I915_FENCE_FLAG_SIGNAL clear and
so reused the rq->signal_link that was in use on CPU0, leading to bad
pointer chasing in intel_engine_breadcrumbs_irq.
A related issue was that if someone started listening for a signal on a
completed but no longer in-flight request, we missed the opportunity to
immediately signal that request.
Furthermore, as intel_contexts may be immediately released during
request retirement, in order to be entirely sure that
intel_engine_breadcrumbs_irq may no longer dereference the intel_context
(ce->signals and ce->signal_link), we must wait for irq spinlock.
In order to prevent the race, we use a bit in the fence.flags to signal
the transfer onto the signal list inside intel_engine_breadcrumbs_irq.
For simplicity, we use the DMA_FENCE_FLAG_SIGNALED_BIT as it then
quickly signals to any outside observer that the fence is indeed signaled.
Fixes: 52c0fdb25c7c ("drm/i915: Replace global breadcrumbs with per-context
interrupt tracking")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/dma-buf/dma-fence.c | 1 +
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 58 +
drivers/gpu/drm/i915/i915_request.c | 1 +
3 files changed, 39 insertions(+), 21 deletions(-)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 3aa8733f832a..9bf06042619a 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -29,6 +29,7 @@
EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit);
EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal);
+EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled);
static DEFINE_SPINLOCK(dma_fence_stub_lock);
static struct dma_fence dma_fence_stub;
diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
index 3cbffd400b1b..4283224249d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
@@ -23,6 +23,7 @@
*/
#include
+#include
#include
#include "i915_drv.h"
@@ -83,6 +84,7 @@ static inline bool __request_completed(const struct
i915_request *rq)
void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
+ const ktime_t timestamp = ktime_get();
struct intel_context *ce, *cn;
struct list_head *pos, *next;
LIST_HEAD(signal);
@@ -104,6 +106,11 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
GEM_BUG_ON(!test_bit(I915_FENCE_FLAG_SIGNAL,
&rq->fence.flags));
+ clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
+
+ if (test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+ &rq->fence.flags))
+ continue;
/*
* Queue for execution after dropping the signaling
@@ -111,14 +118,6 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs
*engine)
* more signalers to the same context or engine.
*/
i915_request_get(rq);
-
- /*
- * We may race with direct invocation of
- * dma_fence_signal(), e.g. i915_request_retire(),
- * so we need to acquire our reference to the request
- * before we cancel the breadcrumb.
- */
- clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
list_add_tail(&rq->signal_link, &signal);
}
@@ -140,8 +139,21 @@ void intel_engine_breadcrumbs_irq(struct intel_engine_cs *engine)
list_for_each_safe(pos, next, &signal) {
struct i915_request *rq =
list_entry(pos, typeof(*rq), signal_link);
+ struct dma_fence_cb *cur, *tmp;
+
+ trace_dma_fence_signaled(&rq->fence);
+
+ rq-
Re: [Intel-gfx] [PATCH 24/45] drm/i915: Split GEM object type definition to its own header
On Thu, 25 Apr 2019, Chris Wilson wrote:
> For convenience in avoiding inline spaghetti, keep the type definition
> as a separate header.
>
> Signed-off-by: Chris Wilson
> Reviewed-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gem/Makefile | 1 +
> drivers/gpu/drm/i915/gem/Makefile.header-test | 16 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 285 +
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +-
> drivers/gpu/drm/i915/i915_gem_batch_pool.h| 3 +-
> drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
> drivers/gpu/drm/i915/i915_gem_object.h| 295 +-
> 9 files changed, 312 insertions(+), 294 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gem/Makefile
> create mode 100644 drivers/gpu/drm/i915/gem/Makefile.header-test
> create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 58643373495c..def781c9ea69 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -85,6 +85,7 @@ gt-$(CONFIG_DRM_I915_SELFTEST) += \
> i915-y += $(gt-y)
>
> # GEM (Graphics Execution Management) code
> +obj-y += gem/
I think this warrants similar treatment as gt/. Posted standalone
instead of hidden in a series, explicit acks.
Provided the split makes sense to Joonas,
Acked-by: Jani Nikula
> i915-y += \
> i915_active.o \
> i915_cmd_parser.o \
> diff --git a/drivers/gpu/drm/i915/gem/Makefile
> b/drivers/gpu/drm/i915/gem/Makefile
> new file mode 100644
> index ..07e7b8b840ea
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/Makefile
> @@ -0,0 +1 @@
> +include $(src)/Makefile.header-test # Extra header tests
> diff --git a/drivers/gpu/drm/i915/gem/Makefile.header-test
> b/drivers/gpu/drm/i915/gem/Makefile.header-test
> new file mode 100644
> index ..61e06cbb4b32
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/Makefile.header-test
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: MIT
> +# Copyright © 2019 Intel Corporation
> +
> +# Test the headers are compilable as standalone units
> +header_test := $(notdir $(wildcard $(src)/*.h))
> +
> +quiet_cmd_header_test = HDRTEST $@
> + cmd_header_test = echo "\#include \"$( $@
> +
> +header_test_%.c: %.h
> + $(call cmd,header_test)
> +
> +extra-$(CONFIG_DRM_I915_WERROR) += \
> + $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
> +
> +clean-files += $(foreach h,$(header_test),$(patsubst
> %.h,header_test_%.c,$(h)))
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> new file mode 100644
> index ..e4b50944f553
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -0,0 +1,285 @@
> +/*
> + * SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2016 Intel Corporation
> + */
> +
> +#ifndef __I915_GEM_OBJECT_TYPES_H__
> +#define __I915_GEM_OBJECT_TYPES_H__
> +
> +#include
> +
> +#include
> +
> +#include "../i915_active.h"
> +#include "../i915_selftest.h"
> +
> +struct drm_i915_gem_object;
> +
> +/*
> + * struct i915_lut_handle tracks the fast lookups from handle to vma used
> + * for execbuf. Although we use a radixtree for that mapping, in order to
> + * remove them as the object or context is closed, we need a secondary list
> + * and a translation entry (i915_lut_handle).
> + */
> +struct i915_lut_handle {
> + struct list_head obj_link;
> + struct list_head ctx_link;
> + struct i915_gem_context *ctx;
> + u32 handle;
> +};
> +
> +struct drm_i915_gem_object_ops {
> + unsigned int flags;
> +#define I915_GEM_OBJECT_HAS_STRUCT_PAGE BIT(0)
> +#define I915_GEM_OBJECT_IS_SHRINKABLEBIT(1)
> +#define I915_GEM_OBJECT_IS_PROXY BIT(2)
> +#define I915_GEM_OBJECT_ASYNC_CANCEL BIT(3)
> +
> + /* Interface between the GEM object and its backing storage.
> + * get_pages() is called once prior to the use of the associated set
> + * of pages before to binding them into the GTT, and put_pages() is
> + * called after we no longer need them. As we expect there to be
> + * associated cost with migrating pages between the backing storage
> + * and making them available for the GPU (e.g. clflush), we may hold
> + * onto the pages after they are no longer referenced by the GPU
> + * in case they may be used again shortly (for example migrating the
> + * pages to a different memory domain within the GTT). put_pages()
> + * will therefore most likely be called when the object itself is
> + * being released or under memory pressure (where we attempt to
> + * reap pages for the shrinker).
> + */
> + int (*get_pages)(struct drm_i915_gem_object *obj);
> + void (*put_pages)(struct drm_i915_gem_object *obj,
> +
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev7)
== Series Details == Series: drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color (rev7) URL : https://patchwork.freedesktop.org/series/58912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6001_full -> Patchwork_12881_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12881_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12881_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12881_full: ### IGT changes ### Possible regressions * igt@gem_persistent_relocs@forked-thrashing: - shard-skl: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl4/igt@gem_persistent_rel...@forked-thrashing.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl8/igt@gem_persistent_rel...@forked-thrashing.html Known issues Here are the changes found in Patchwork_12881_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([fdo#103665]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-kbl5/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +7 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-apl3/igt@gem_workarou...@suspend-resume.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-apl2/igt@gem_workarou...@suspend-resume.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107773]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl10/igt@i915_pm_backlight@fade_with_suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl8/igt@i915_pm_backlight@fade_with_suspend.html * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#103232]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl2/igt@kms_cursor_...@cursor-128x128-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl2/igt@kms_cursor_...@cursor-128x128-suspend.html * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#106509] / [fdo#107409]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-glk9/igt@kms_cursor_leg...@2x-nonblocking-modeset-vs-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-glk1/igt@kms_cursor_leg...@2x-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#103184]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl4/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl7/igt@kms_draw_...@draw-method-xrgb2101010-mmap-cpu-untiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-apl: [PASS][15] -> [FAIL][16] ([fdo#102887] / [fdo#105363]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-apl7/igt@kms_f...@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-apl1/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#103167]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl4/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl7/igt@kms_frontbuffer_track...@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6001/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12881/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html Possible fixes * igt@gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][21] ([fdo#108686]) -> [PASS][22
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
On 4/13/2019 12:00 AM, Ville Syrjala wrote:
From: Ville Syrjälä
The pipe has a special HDR mode with higher precision when only
HDR planes are active. Let's use it.
Curiously this fixes the kms_color gamma/degamma tests when
using a HDR plane, which is always the case unless one hacks
the test to use an SDR plane. If one does hack the test to use
an SDR plane it does pass already.
I have no actual explanation how the output after the gamma
LUT can be different between the two modes. The way the tests
are written should mean that the output should be identical
between the solid color vs. the gradient. But clearly that
somehow doesn't hold true for the HDR planes in non-HDR pipe
mode. Anyways, as long as we stick to one type of plane the
test should produce sensible results now.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 7 +++
drivers/gpu/drm/i915/intel_sprite.h | 12
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f28..90d60ecd3317 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5767,6 +5767,7 @@ enum {
#define _PIPE_MISC_B 0x71030
#define PIPEMISC_YUV420_ENABLE (1 << 27)
#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
+#define PIPEMISC_HDR_MODE(1 << 23) /* icl+ */
#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
#define PIPEMISC_DITHER_BPC_MASK(7 << 5)
#define PIPEMISC_DITHER_8_BPC (0 << 5)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 490bd49ff42a..d0dbdbd5db3f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
intel_crtc_state *old_crtc_sta
ironlake_pfit_disable(old_crtc_state);
}
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+ bdw_set_pipemisc(new_crtc_state);
+
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
}
@@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
intel_crtc_state *crtc_state)
val |= PIPEMISC_YUV420_ENABLE |
PIPEMISC_YUV420_MODE_FULL_BLEND;
+ if (INTEL_GEN(dev_priv) >= 11 &&
+ (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
+ val |= PIPEMISC_HDR_MODE;
+
Shouldn't we check if the content being played on plane is HDR before
enabling this bit (even though I am not sure if there is any harm in
doing that)? Or maybe check the connector->output_hdr_metadata ? Most of
the times we would be sending SDR buffers on this plane. What happens
exactly when we set this bit ? The bspec says:
"This field enables the HDR mode, allowing for higher precision output
from the HDR supporting planes and bypassing the SDR planes in blending. "
- Shashank
I915_WRITE(PIPEMISC(crtc->pipe), val);
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.h b/drivers/gpu/drm/i915/intel_sprite.h
index 84be8686be16..500f6bffb139 100644
--- a/drivers/gpu/drm/i915/intel_sprite.h
+++ b/drivers/gpu/drm/i915/intel_sprite.h
@@ -43,13 +43,17 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id)
return false;
}
+static inline u8 icl_hdr_plane_mask(void)
+{
+ return BIT(PLANE_PRIMARY) |
+ BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
+}
+
static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{
- if (INTEL_GEN(dev_priv) < 11)
- return false;
-
- return plane_id < PLANE_SPRITE2;
+ return INTEL_GEN(dev_priv) >= 11 &&
+ icl_hdr_plane_mask() & BIT(plane_id);
}
#endif /* __INTEL_SPRITE_H__ */
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details == Series: series starting with [1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/59970/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12883_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12883_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12883_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12883_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock_requests: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl4/igt@i915_selftest@mock_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-skl5/igt@i915_selftest@mock_requests.html Known issues Here are the changes found in Patchwork_12883_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl7/igt@gem_ctx_isolat...@bcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-skl5/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-hsw3/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-hsw1/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_pm_rpm@i2c: - shard-iclb: [PASS][7] -> [DMESG-WARN][8] ([fdo#109982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-iclb8/igt@i915_pm_...@i2c.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-iclb2/igt@i915_pm_...@i2c.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-apl5/igt@i915_susp...@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-apl2/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-iclb3/igt@kms_frontbuffer_track...@fbc-stridechange.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-iclb4/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: [PASS][13] -> [SKIP][14] ([fdo#109271] / [fdo#109278]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-glk9/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-glk7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-iclb2/igt@kms_psr@psr2_basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-iclb5/igt@kms_psr@psr2_basic.html * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#109016]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-kbl2/igt@kms_rotation_...@multiplane-rotation-cropping-top.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-kbl1/igt@kms_rotation_...@multiplane-rotation-cropping-top.html * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([fdo#104108]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl3/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-skl9/igt@kms_vbl...@pipe-c-ts-continuation-dpms-suspend.html Possible fixes * igt@gem_eio@in-flight-suspend: - shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-apl6/igt@gem_...@in-flight-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12883/shard-apl4/igt@gem_...@in-flight-suspend.html * i
Re: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming
Reviewed-by: Swati Sharma
Thanks and Regards,
Swati
-Original Message-
From: Intel-gfx On Behalf Of Ville
Syrjala
Sent: Friday, April 26, 2019 12:54 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Fix ICL output CSC programming
From: Ville Syrjälä
When I refactored the code into its own function I accidentally misplaced the
<<16 shifts for some of the registers causing us to lose the blue channel
entirely.
We should really find a way to test this...
Cc: Uma Shankar
Fixes: d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ca341a9e47e6..9093daabc290 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -173,13 +173,13 @@ static void icl_update_output_csc(struct intel_crtc *crtc,
I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
coeff[1]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
coeff[4]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
coeff[7]);
- I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
+ I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16);
I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
--
2.21.0
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Re: [Intel-gfx] [PATCH] drm/i915: Clean up cherryview_load_luts()
Reviewed-by: Swati Sharma
Thanks and Regards,
Swati
-Original Message-
From: Intel-gfx On Behalf Of Ville
Syrjala
Sent: Monday, April 8, 2019 5:48 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Clean up cherryview_load_luts()
From: Ville Syrjälä
I like my functions simple, so split up the low level bits from
cherryview_load_luts() into separate functions. Also rename the whole thing to
chv_load_luts() to match the new world order.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_color.c | 98 ++
1 file changed, 60 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ca341a9e47e6..9e34aba4d630 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -784,13 +784,65 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
-static void cherryview_load_luts(const struct intel_crtc_state *crtc_state)
+static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) {
+ return drm_color_lut_extract(color->green, 14) << 16 |
+ drm_color_lut_extract(color->blue, 14); }
+
+static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) {
+ return drm_color_lut_extract(color->red, 14); }
+
+static void chv_load_cgm_degamma(struct intel_crtc *crtc,
+const struct drm_property_blob *blob) {
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ for (i = 0; i < lut_size; i++) {
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0),
+ chv_cgm_degamma_ldw(&lut[i]));
+ I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1),
+ chv_cgm_degamma_udw(&lut[i]));
+ }
+}
+
+static u32 chv_cgm_gamma_ldw(const struct drm_color_lut *color) {
+ return drm_color_lut_extract(color->green, 10) << 16 |
+ drm_color_lut_extract(color->blue, 10); }
+
+static u32 chv_cgm_gamma_udw(const struct drm_color_lut *color) {
+ return drm_color_lut_extract(color->red, 10); }
+
+static void chv_load_cgm_gamma(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob) {
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
+ enum pipe pipe = crtc->pipe;
+
+ for (i = 0; i < lut_size; i++) {
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0),
+ chv_cgm_gamma_ldw(&lut[i]));
+ I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1),
+ chv_cgm_gamma_udw(&lut[i]));
+ }
+}
+
+static void chv_load_luts(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
- enum pipe pipe = crtc->pipe;
cherryview_load_csc_matrix(crtc_state);
@@ -799,41 +851,11 @@ static void cherryview_load_luts(const struct
intel_crtc_state *crtc_state)
return;
}
- if (degamma_lut) {
- const struct drm_color_lut *lut = degamma_lut->data;
- int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ if (degamma_lut)
+ chv_load_cgm_degamma(crtc, degamma_lut);
- for (i = 0; i < lut_size; i++) {
- u32 word0, word1;
-
- /* Write LUT in U0.14 format. */
- word0 =
- (drm_color_lut_extract(lut[i].green, 14) << 16) |
- drm_color_lut_extract(lut[i].blue, 14);
- word1 = drm_color_lut_extract(lut[i].red, 14);
-
- I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
- I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
- }
- }
-
- if (gamma_lut) {
- const struct drm_color_lut *lut = gamma_lut->data;
- int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
-
- for (i = 0; i < lut_size; i++) {
- u32 word0, word1;
-
- /* Write LUT in U0.10 format. */
- word0 =
- (drm_color_lut_extract(lut[i].green, 10) << 16) |
- drm_color_lut_extract(lut[i].blue, 10);
- word1 = drm_color_lut_extract(lut[i].red, 10);
-
- I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
-
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used
On Fri, Apr 26, 2019 at 06:40:11PM +0530, Sharma, Shashank wrote:
>
> On 4/13/2019 12:00 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The pipe has a special HDR mode with higher precision when only
> > HDR planes are active. Let's use it.
> >
> > Curiously this fixes the kms_color gamma/degamma tests when
> > using a HDR plane, which is always the case unless one hacks
> > the test to use an SDR plane. If one does hack the test to use
> > an SDR plane it does pass already.
> >
> > I have no actual explanation how the output after the gamma
> > LUT can be different between the two modes. The way the tests
> > are written should mean that the output should be identical
> > between the solid color vs. the gradient. But clearly that
> > somehow doesn't hold true for the HDR planes in non-HDR pipe
> > mode. Anyways, as long as we stick to one type of plane the
> > test should produce sensible results now.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 7 +++
> > drivers/gpu/drm/i915/intel_sprite.h | 12
> > 3 files changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 8ad2f0a03f28..90d60ecd3317 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5767,6 +5767,7 @@ enum {
> > #define _PIPE_MISC_B 0x71030
> > #define PIPEMISC_YUV420_ENABLE (1 << 27)
> > #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26)
> > +#define PIPEMISC_HDR_MODE(1 << 23) /* icl+ */
> > #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
> > #define PIPEMISC_DITHER_BPC_MASK(7 << 5)
> > #define PIPEMISC_DITHER_8_BPC (0 << 5)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 490bd49ff42a..d0dbdbd5db3f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4055,6 +4055,9 @@ static void intel_update_pipe_config(const struct
> > intel_crtc_state *old_crtc_sta
> > ironlake_pfit_disable(old_crtc_state);
> > }
> >
> > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > + bdw_set_pipemisc(new_crtc_state);
> > +
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_set_pipe_chicken(crtc);
> > }
> > @@ -8869,6 +8872,10 @@ static void bdw_set_pipemisc(const struct
> > intel_crtc_state *crtc_state)
> > val |= PIPEMISC_YUV420_ENABLE |
> > PIPEMISC_YUV420_MODE_FULL_BLEND;
> >
> > + if (INTEL_GEN(dev_priv) >= 11 &&
> > + (crtc_state->active_planes & ~icl_hdr_plane_mask()) == 0)
> > + val |= PIPEMISC_HDR_MODE;
> > +
>
> Shouldn't we check if the content being played on plane is HDR before
> enabling this bit (even though I am not sure if there is any harm in
> doing that)? Or maybe check the connector->output_hdr_metadata ? Most of
> the times we would be sending SDR buffers on this plane. What happens
> exactly when we set this bit ? The bspec says:
>
> "This field enables the HDR mode, allowing for higher precision output
> from the HDR supporting planes and bypassing the SDR planes in blending. "
I think the bit is just misnamed (like most things with "HDR" in their
name). It's just a "gimme moar precision" bit.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband
== Series Details == Series: series starting with [CI,1/8] drm/i915: Disable preemption and sleeping while using the punit sideband URL : https://patchwork.freedesktop.org/series/59980/ State : success == Summary == CI Bug Log - changes from CI_DRM_6002_full -> Patchwork_12884_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12884_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([fdo#108901]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl2/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-skl1/igt@debugfs_test@read_all_entries.html * igt@gem_softpin@noreloc-s3: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([fdo#104108] / [fdo#107773]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl10/igt@gem_soft...@noreloc-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-skl2/igt@gem_soft...@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-glk1/igt@gem_tiled_swapp...@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-apl7/igt@gem_workarou...@suspend-resume.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-apl1/igt@gem_workarou...@suspend-resume.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-hsw5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-hsw5/igt@kms_cursor_leg...@flip-vs-cursor-toggle.html * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-hsw: [PASS][11] -> [DMESG-FAIL][12] ([fdo#102614] / [fdo#103060]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-hsw5/igt@kms_f...@2x-dpms-vs-vblank-race-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-hsw5/igt@kms_f...@2x-dpms-vs-vblank-race-interruptible.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-skl1/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#102887]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-glk7/igt@kms_f...@flip-vs-expired-vblank.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-glk9/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-iclb6/igt@kms_frontbuffer_track...@fbcpsr-1p-pri-indfb-multidraw.html * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: - shard-glk: [PASS][19] -> [SKIP][20] ([fdo#109271] / [fdo#109278]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-glk9/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-glk6/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-iclb2/igt@kms_psr@psr2_basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-iclb4/igt@kms_psr@psr2_basic.html Possible fixes * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [INCOMPLETE][23] ([fdo#103665]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6002/shard-kbl5/igt@gem_ctx_isolat...@rcs0-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12884/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html * igt@gem_eio@in-flight-suspend: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][2
Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+
On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2019-04-15 15:16:41) > > > From: Ville Syrjälä > > > > > > Since SKL the eLLC has been sitting on the far side of the system > > > agent, meaning the display engine can utilize it. Let's enable that. > > > > > > I chose WB for the caching mode, because my numbers are indicating > > > that WT might actually be WB and WC might actually be UC. I'm not > > > 100% sure that is indeed the case but at least my simple rendercopy > > > based benchmark didn't see any difference in performance. > > > > > > Also if I configure things to do LLCeLLC+WT I still get cache dirt > > > on my screen, suggesting that is in fact operating in WB mode > > > anyway. This is also the reason I had to fix the MOCS target cache > > > to really say PTE rather than LLC+eLLC. > > > > We also need to check with hybrid setups that supply buffers via prime, > > and we may need to end up marking those as explicitly uncached. > > I think all memory access should be able to snoop the eLLC. But yeah, > this should be confirmed on actual hardware. Anyone have a prime setup > handy? It occurred to me that finding a machine for this might be a little difficult as most gt3e/gt4e chips are only available in laptops/nucs/etc. IIRC there are some Xeons that would qualify, but I suppose those are somewhat rare. Not sure if there are any other desktop parts that have ellc. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_tiling_max_stride: Skip if chipset is unknown
On Fri, Apr 26, 2019 at 08:56:45AM +0100, Chris Wilson wrote:
> If we can't match the devid to a chipset, we do not have a reference for
> the tiling strides. Instead of randomly failing, skip with a
> semi-informative message.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110523
> Signed-off-by: Chris Wilson
Reviewed-by: Ville Syrjälä
> ---
> tests/i915/gem_tiling_max_stride.c | 16 +---
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/tests/i915/gem_tiling_max_stride.c
> b/tests/i915/gem_tiling_max_stride.c
> index a6f97a915..0e99d979f 100644
> --- a/tests/i915/gem_tiling_max_stride.c
> +++ b/tests/i915/gem_tiling_max_stride.c
> @@ -72,16 +72,18 @@ igt_simple_main
>
> devid = intel_get_drm_devid(fd);
>
> - if (intel_gen(devid) >= 7)
> + if (intel_gen(devid) >= 7) {
> stride = 256 * 1024;
> - else if (intel_gen(devid) >= 4)
> + } else if (intel_gen(devid) >= 4) {
> stride = 128 * 1024;
> - else {
> - if (IS_GEN2(devid)) {
> - tile_width = 128;
> - tile_height = 16;
> - }
> + } else if (intel_gen(devid) >= 3) {
> + stride = 8 * 1024;
> + } else if (intel_gen(devid) >= 2) {
> + tile_width = 128;
> + tile_height = 16;
> stride = 8 * 1024;
> + } else {
> + igt_skip("Unknown Intel chipset, devid=%04x\n", devid);
> }
>
> size = stride * tile_height;
> --
> 2.20.1
>
> ___
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> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
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Intel
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Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+
Quoting Ville Syrjälä (2019-04-26 15:54:54) > On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > > Quoting Ville Syrjala (2019-04-15 15:16:41) > > > > From: Ville Syrjälä > > > > > > > > Since SKL the eLLC has been sitting on the far side of the system > > > > agent, meaning the display engine can utilize it. Let's enable that. > > > > > > > > I chose WB for the caching mode, because my numbers are indicating > > > > that WT might actually be WB and WC might actually be UC. I'm not > > > > 100% sure that is indeed the case but at least my simple rendercopy > > > > based benchmark didn't see any difference in performance. > > > > > > > > Also if I configure things to do LLCeLLC+WT I still get cache dirt > > > > on my screen, suggesting that is in fact operating in WB mode > > > > anyway. This is also the reason I had to fix the MOCS target cache > > > > to really say PTE rather than LLC+eLLC. > > > > > > We also need to check with hybrid setups that supply buffers via prime, > > > and we may need to end up marking those as explicitly uncached. > > > > I think all memory access should be able to snoop the eLLC. But yeah, > > this should be confirmed on actual hardware. Anyone have a prime setup > > handy? > > It occurred to me that finding a machine for this might be a little > difficult as most gt3e/gt4e chips are only available in laptops/nucs/etc. > IIRC there are some Xeons that would qualify, but I suppose those are > somewhat rare. Not sure if there are any other desktop parts that have > ellc. For now at least. Would an ePCI be a fun mix of coherency problems? Not that they are any more common. Did you finish up the rendercopy tests? I think I saw that you were working on something that looked like it could be used for verifying rendering into the frontbuffer (or at least leaving cache dirty prior to flips)? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/
On Fri, Apr 26, 2019 at 12:56:48PM +1000, Dave Airlie wrote:
> Daniel, drm-misc-next-fixes?
Makes sense. Pushed.
Cheers, Daniel
>
> Dave.
>
> On Fri, 26 Apr 2019 at 12:25, wrote:
> >
> > Hi Dave,
> >
> > > -Original Message-
> > > From: Dave Airlie [mailto:airl...@gmail.com]
> > > Sent: Friday, April 26, 2019 11:19 AM
> > > To: Yamada, Masahiro/山田 真弘
> > > Cc: David Airlie ; Daniel Vetter ;
> > > dri-devel ; nouveau
> > > ; Sam Ravnborg ; David
> > > (ChunMing) Zhou ; amd-gfx mailing list
> > > ; James (Qian) Wang
> > > ; Ben Skeggs ;
> > > linux-arm-msm ; Intel Graphics
> > > Development ;
> > > intel-gvt-...@lists.freedesktop.org; Linux Kernel Mailing List
> > > ; Christian König
> > > ; Alex Deucher ;
> > > freedr...@lists.freedesktop.org
> > > Subject: Re: [Intel-gfx] [PATCH v2] drm: prefix header search paths with
> > > $(srctree)/
> > >
> > > On Fri, 26 Apr 2019 at 11:46, Masahiro Yamada
> > > wrote:
> > > >
> > > > Hi.
> > > >
> > > >
> > > > On Fri, Mar 29, 2019 at 8:37 PM Masahiro Yamada
> > > > wrote:
> > > > >
> > > > > Currently, the Kbuild core manipulates header search paths in a crazy
> > > > > way [1].
> > > > >
> > > > > To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> > > > > the search paths in the srctree. Some Makefiles are already written
> > > in
> > > > > that way, but not all. The goal of this work is to make the notation
> > > > > consistent, and finally get rid of the gross hacks.
> > > > >
> > > > > Having whitespaces after -I does not matter since commit 48f6e3cf5bc6
> > > > > ("kbuild: do not drop -I without parameter").
> > > > >
> > > > > [1]: https://patchwork.kernel.org/patch/9632347/
> > > > >
> > > > > Signed-off-by: Masahiro Yamada
> > > > > Reviewed-by: Sam Ravnborg
> > > > > ---
> > > > >
> > > > > I put all gpu/drm changes into a single patch because
> > > > > they are trivial conversion.
> > > > >
> > > > > If you are interested in the big picture of this work,
> > > > > the full patch set is available at the following URL.
> > > > >
> > > > >
> > > git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.g
> > > it build-test
> > > >
> > > >
> > > > Is somebody taking care of this?
> > > >
> > >
> > > Are you expecting this to be merged in the drm tree? if so please
> > > indicate that when posting.
> >
> >
> > Sorry for unclearness.
> >
> > Could you apply this to your drm tree?
> >
> > Thanks.
> >
> >
> >
> >
> > > I'd assumed this would go via kbuild tree.
> > >
> > > If the later,
> > > Acked-by: Dave Airlie
> > > Dave.
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Enable eLLC caching of display buffers for SKL+
On Fri, Apr 26, 2019 at 04:01:02PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2019-04-26 15:54:54) > > On Wed, Apr 17, 2019 at 08:15:43PM +0300, Ville Syrjälä wrote: > > > On Wed, Apr 17, 2019 at 08:09:07AM +0100, Chris Wilson wrote: > > > > Quoting Ville Syrjala (2019-04-15 15:16:41) > > > > > From: Ville Syrjälä > > > > > > > > > > Since SKL the eLLC has been sitting on the far side of the system > > > > > agent, meaning the display engine can utilize it. Let's enable that. > > > > > > > > > > I chose WB for the caching mode, because my numbers are indicating > > > > > that WT might actually be WB and WC might actually be UC. I'm not > > > > > 100% sure that is indeed the case but at least my simple rendercopy > > > > > based benchmark didn't see any difference in performance. > > > > > > > > > > Also if I configure things to do LLCeLLC+WT I still get cache dirt > > > > > on my screen, suggesting that is in fact operating in WB mode > > > > > anyway. This is also the reason I had to fix the MOCS target cache > > > > > to really say PTE rather than LLC+eLLC. > > > > > > > > We also need to check with hybrid setups that supply buffers via prime, > > > > and we may need to end up marking those as explicitly uncached. > > > > > > I think all memory access should be able to snoop the eLLC. But yeah, > > > this should be confirmed on actual hardware. Anyone have a prime setup > > > handy? > > > > It occurred to me that finding a machine for this might be a little > > difficult as most gt3e/gt4e chips are only available in laptops/nucs/etc. > > IIRC there are some Xeons that would qualify, but I suppose those are > > somewhat rare. Not sure if there are any other desktop parts that have > > ellc. > > For now at least. Would an ePCI be a fun mix of coherency problems? Not > that they are any more common. Hmm. I keep forgetting what century we're in. Some kind of external thunderbolt enclosure might do the trick. Never actually seen one but I suppose it shouldn't be an impossible task to procure some. > > Did you finish up the rendercopy tests? I think I saw that you were > working on something that looked like it could be used for verifying > rendering into the frontbuffer (or at least leaving cache dirty prior to > flips)? I just fixed up the mocs setup in rendercopy. I didn't write a specific testase yet. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH xf86-video-intel v2 1/2] sna: Refactor property parsing
From: Ville Syrjälä
Generalize the code that parses the plane properties to be useable
for crtc (or any kms object) properties as well.
v2: plane 'type' prop is enum not range!
Cc: Mario Kleiner
Signed-off-by: Ville Syrjälä
---
src/sna/sna_display.c | 69 ++-
1 file changed, 49 insertions(+), 20 deletions(-)
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 119ea981d243..41edfec12839 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -215,6 +215,7 @@ struct sna_crtc {
uint32_t rotation;
struct plane {
uint32_t id;
+ uint32_t type;
struct {
uint32_t prop;
uint32_t supported;
@@ -3391,33 +3392,40 @@ void sna_crtc_set_sprite_colorspace(xf86CrtcPtr crtc,
p->color_encoding.values[colorspace]);
}
-static int plane_details(struct sna *sna, struct plane *p)
+typedef void (*parse_prop_func)(struct sna *sna,
+ struct drm_mode_get_property *prop,
+ uint64_t value,
+ void *data);
+static void parse_props(struct sna *sna,
+ uint32_t obj_type, uint32_t obj_id,
+ parse_prop_func parse_prop,
+ void *data)
{
#define N_STACK_PROPS 32 /* must be a multiple of 2 */
struct local_mode_obj_get_properties arg;
uint64_t stack[N_STACK_PROPS + N_STACK_PROPS/2];
uint64_t *values = stack;
uint32_t *props = (uint32_t *)(values + N_STACK_PROPS);
- int i, type = DRM_PLANE_TYPE_OVERLAY;
+ int i;
memset(&arg, 0, sizeof(struct local_mode_obj_get_properties));
- arg.obj_id = p->id;
- arg.obj_type = LOCAL_MODE_OBJECT_PLANE;
+ arg.obj_id = obj_id;
+ arg.obj_type = obj_type;
arg.props_ptr = (uintptr_t)props;
arg.prop_values_ptr = (uintptr_t)values;
arg.count_props = N_STACK_PROPS;
if (drmIoctl(sna->kgem.fd, LOCAL_IOCTL_MODE_OBJ_GETPROPERTIES, &arg))
- return -1;
+ return;
DBG(("%s: object %d (type %x) has %d props\n", __FUNCTION__,
-p->id, LOCAL_MODE_OBJECT_PLANE, arg.count_props));
+obj_id, obj_type, arg.count_props));
if (arg.count_props > N_STACK_PROPS) {
values = malloc(2*sizeof(uint64_t)*arg.count_props);
if (values == NULL)
- return -1;
+ return;
props = (uint32_t *)(values + arg.count_props);
@@ -3444,27 +3452,48 @@ static int plane_details(struct sna *sna, struct plane
*p)
DBG(("%s: prop[%d] .id=%ld, .name=%s, .flags=%x, .value=%ld\n",
__FUNCTION__, i,
(long)props[i], prop.name, (unsigned)prop.flags,
(long)values[i]));
- if (strcmp(prop.name, "type") == 0) {
- type = values[i];
- } else if (prop_is_rotation(&prop)) {
- parse_rotation_prop(sna, p, &prop, values[i]);
- } else if (prop_is_color_encoding(&prop)) {
- parse_color_encoding_prop(sna, p, &prop, values[i]);
- }
+ parse_prop(sna, &prop, values[i], data);
}
- p->rotation.supported &= DBG_NATIVE_ROTATION;
- if (!xf86ReturnOptValBool(sna->Options, OPTION_ROTATION, TRUE))
- p->rotation.supported = RR_Rotate_0;
-
if (values != stack)
free(values);
- DBG(("%s: plane=%d type=%d\n", __FUNCTION__, p->id, type));
- return type;
#undef N_STACK_PROPS
}
+static bool prop_is_type(const struct drm_mode_get_property *prop)
+{
+ return prop_has_type_and_name(prop, 3, "type");
+}
+
+static void plane_parse_prop(struct sna *sna,
+struct drm_mode_get_property *prop,
+uint64_t value, void *data)
+{
+ struct plane *p = data;
+
+ if (prop_is_type(prop))
+ p->type = value;
+ else if (prop_is_rotation(prop))
+ parse_rotation_prop(sna, p, prop, value);
+ else if (prop_is_color_encoding(prop))
+ parse_color_encoding_prop(sna, p, prop, value);
+}
+
+static int plane_details(struct sna *sna, struct plane *p)
+{
+ parse_props(sna, LOCAL_MODE_OBJECT_PLANE, p->id,
+ plane_parse_prop, p);
+
+ p->rotation.supported &= DBG_NATIVE_ROTATION;
+ if (!xf86ReturnOptValBool(sna->Options, OPTION_ROTATION, TRUE))
+ p->rotation.supported = RR_Rotate_0;
+
+ DBG(("%s: plane=%d type=%d\n", __FUNCTION__, p->id, p->type));
+
+ return p->type;
+}
+
static void add_sprite_plane(struct sna_crtc *crtc,
struct plane *details)
{
--
2.21.0
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[Intel-gfx] [PATCH xf86-video-intel v2 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property
From: Ville Syrjälä
Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
the running with > 8bpc.
v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc
Cc: Mario Kleiner
Signed-off-by: Ville Syrjälä
---
src/sna/sna_display.c | 245 +++---
1 file changed, 207 insertions(+), 38 deletions(-)
diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c
index 41edfec12839..6d671dce8c14 100644
--- a/src/sna/sna_display.c
+++ b/src/sna/sna_display.c
@@ -127,6 +127,7 @@ struct local_mode_obj_get_properties {
uint32_t obj_type;
uint32_t pad;
};
+#define LOCAL_MODE_OBJECT_CRTC 0x
#define LOCAL_MODE_OBJECT_PLANE 0x
struct local_mode_set_plane {
@@ -229,6 +230,11 @@ struct sna_crtc {
} primary;
struct list sprites;
+ struct drm_color_lut *gamma_lut;
+ uint64_t gamma_lut_prop;
+ uint64_t gamma_lut_blob;
+ uint32_t gamma_lut_size;
+
uint32_t mode_serial, flip_serial;
uint32_t last_seq, wrap_seq;
@@ -317,6 +323,9 @@ static void __sna_output_dpms(xf86OutputPtr output, int
dpms, int fixup);
static void sna_crtc_disable_cursor(struct sna *sna, struct sna_crtc *crtc);
static bool sna_crtc_flip(struct sna *sna, struct sna_crtc *crtc,
struct kgem_bo *bo, int x, int y);
+static void sna_crtc_gamma_set(xf86CrtcPtr crtc,
+ CARD16 *red, CARD16 *green,
+ CARD16 *blue, int size);
static bool is_zaphod(ScrnInfoPtr scrn)
{
@@ -3150,11 +3159,9 @@ sna_crtc_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr
mode,
mode->VDisplay <= sna->mode.max_crtc_height);
#if HAS_GAMMA
- drmModeCrtcSetGamma(sna->kgem.fd, __sna_crtc_id(sna_crtc),
- crtc->gamma_size,
- crtc->gamma_red,
- crtc->gamma_green,
- crtc->gamma_blue);
+ sna_crtc_gamma_set(crtc,
+ crtc->gamma_red, crtc->gamma_green,
+ crtc->gamma_blue, crtc->gamma_size);
#endif
saved_kmode = sna_crtc->kmode;
@@ -3212,12 +3219,44 @@ void sna_mode_adjust_frame(struct sna *sna, int x, int
y)
static void
sna_crtc_gamma_set(xf86CrtcPtr crtc,
- CARD16 *red, CARD16 *green, CARD16 *blue, int size)
+ CARD16 *red, CARD16 *green, CARD16 *blue, int size)
{
- assert(to_sna_crtc(crtc));
- drmModeCrtcSetGamma(to_sna(crtc->scrn)->kgem.fd,
- sna_crtc_id(crtc),
- size, red, green, blue);
+ struct sna *sna = to_sna(crtc->scrn);
+ struct sna_crtc *sna_crtc = to_sna_crtc(crtc);
+ struct drm_color_lut *lut = sna_crtc->gamma_lut;
+ uint32_t blob_size = size * sizeof(lut[0]);
+ uint32_t blob_id;
+ int ret, i;
+
+ DBG(("%s: gamma_size %d\n", __FUNCTION__, size));
+
+ if (!lut) {
+ assert(size == 256);
+
+ drmModeCrtcSetGamma(to_sna(crtc->scrn)->kgem.fd,
+ sna_crtc_id(crtc),
+ size, red, green, blue);
+ return;
+ }
+
+ assert(size == sna_crtc->gamma_lut_size);
+
+ for (i = 0; i < size; i++) {
+ lut[i].red = red[i];
+ lut[i].green = green[i];
+ lut[i].blue = blue[i];
+ }
+
+ ret = drmModeCreatePropertyBlob(sna->kgem.fd, lut, blob_size, &blob_id);
+ if (ret)
+ return;
+
+ ret = drmModeObjectSetProperty(sna->kgem.fd,
+ sna_crtc->id, DRM_MODE_OBJECT_CRTC,
+ sna_crtc->gamma_lut_prop,
+ blob_id);
+
+ drmModeDestroyPropertyBlob(sna->kgem.fd, blob_id);
}
static void
@@ -3229,6 +3268,8 @@ sna_crtc_destroy(xf86CrtcPtr crtc)
if (sna_crtc == NULL)
return;
+ free(sna_crtc->gamma_lut);
+
list_for_each_entry_safe(sprite, sn, &sna_crtc->sprites, link)
free(sprite);
@@ -3663,6 +3704,55 @@ bool sna_has_sprite_format(struct sna *sna, uint32_t
format)
return false;
}
+inline static bool prop_is_gamma_lut(const struct drm_mode_get_property *prop)
+{
+ return prop_has_type_and_name(prop, 4, "GAMMA_LUT");
+}
+
+inline static bool prop_is_gamma_lut_size(const struct drm_mode_get_property
*prop)
+{
+ return prop_has_type_and_name(prop, 1, "GAMMA_LUT_SIZE");
+}
+
+static void sna_crtc_parse_prop(struct sna *sna,
+ struct drm_mode_get_property *prop,
+ uint64_t value, void *data)
+{
+ struct sna_crtc *crtc = data;
+
+ if (prop_is_gamma_lut(prop)) {
+ crtc->gamma_lut_prop = prop->prop_id;
+ crtc->gamma_lut_blob = value;
+ } else if (prop_is_gamma_lut_s
[Intel-gfx] [CI 1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
Our eventual goal is to rid request construction of struct_mutex, with
the short term step of lifting the struct_mutex requirements into the
higher levels (i.e. the caller must ensure that the context is already
pinned into the GTT). In this patch, we pin GVT's shadow context upon
allocation and so keep them pinned into the GGTT for as long as the
virtual machine is alive, and so we can use the simpler request
construction path safe in the knowledge that the hard work is already
done.
Signed-off-by: Chris Wilson
Cc: Zhenyu Wang
Acked-by: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
drivers/gpu/drm/i915/gvt/kvmgt.c| 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 3 +-
drivers/gpu/drm/i915/gvt/scheduler.c| 142
4 files changed, 73 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index f5a328b5290a..b54f2bdc13a4 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -149,9 +149,9 @@ struct intel_vgpu_submission_ops {
struct intel_vgpu_submission {
struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
struct list_head workload_q_head[I915_NUM_ENGINES];
+ struct intel_context *shadow[I915_NUM_ENGINES];
struct kmem_cache *workloads;
atomic_t running_workload_num;
- struct i915_gem_context *shadow_ctx;
union {
u64 i915_context_pml4;
u64 i915_context_pdps[GEN8_3LVL_PDPES];
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index a68addf95c23..144301b778df 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1576,7 +1576,7 @@ hw_id_show(struct device *dev, struct device_attribute
*attr,
struct intel_vgpu *vgpu = (struct intel_vgpu *)
mdev_get_drvdata(mdev);
return sprintf(buf, "%u\n",
- vgpu->submission.shadow_ctx->hw_id);
+ vgpu->submission.shadow[0]->gem_context->hw_id);
}
return sprintf(buf, "\n");
}
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c
b/drivers/gpu/drm/i915/gvt/mmio_context.c
index e7e14c842be4..b8823495022b 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -495,8 +495,7 @@ static void switch_mmio(struct intel_vgpu *pre,
* itself.
*/
if (mmio->in_context &&
-
!is_inhibit_context(intel_context_lookup(s->shadow_ctx,
-
dev_priv->engine[ring_id])))
+ !is_inhibit_context(s->shadow[ring_id]))
continue;
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 8998fa5ab198..5da50201eb41 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -36,6 +36,7 @@
#include
#include "i915_drv.h"
+#include "i915_gem_pm.h"
#include "gvt.h"
#define RING_CTX_OFF(x) \
@@ -277,18 +278,23 @@ static int shadow_context_status_change(struct
notifier_block *nb,
return NOTIFY_OK;
}
-static void shadow_context_descriptor_update(struct intel_context *ce)
+static void
+shadow_context_descriptor_update(struct intel_context *ce,
+struct intel_vgpu_workload *workload)
{
- u64 desc = 0;
-
- desc = ce->lrc_desc;
+ u64 desc = ce->lrc_desc;
- /* Update bits 0-11 of the context descriptor which includes flags
+ /*
+* Update bits 0-11 of the context descriptor which includes flags
* like GEN8_CTX_* cached in desc_template
*/
desc &= U64_MAX << 12;
desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
+ desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
+ desc |= workload->ctx_desc.addressing_mode <<
+ GEN8_CTX_ADDRESSING_MODE_SHIFT;
+
ce->lrc_desc = desc;
}
@@ -365,26 +371,22 @@ intel_gvt_workload_req_alloc(struct intel_vgpu_workload
*workload)
{
struct intel_vgpu *vgpu = workload->vgpu;
struct intel_vgpu_submission *s = &vgpu->submission;
- struct i915_gem_context *shadow_ctx = s->shadow_ctx;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id];
struct i915_request *rq;
- int ret = 0;
lockdep_assert_held(&dev_priv->drm.struct_mutex);
if (workload->req)
- goto out;
+ return 0;
- rq = i915_request_alloc(engine, shadow_ctx);
+ rq = i915_request_create(s->shadow[workload->ring_id]);
if (IS_ERR(rq)) {
gvt_vgpu_err("fail to allocate ge
[Intel-gfx] [CI 2/9] drm/i915: Export intel_context_instance()
We want to pass in a intel_context into intel_context_pin() and that
requires us to first be able to lookup the intel_context!
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c| 37 +++---
drivers/gpu/drm/i915/gt/intel_context.h| 19 +++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 -
drivers/gpu/drm/i915/gt/mock_engine.c | 8 -
drivers/gpu/drm/i915/gvt/scheduler.c | 7 +++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 +--
drivers/gpu/drm/i915/i915_perf.c | 21
drivers/gpu/drm/i915/i915_request.c| 11 ++-
8 files changed, 83 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 298e463ad082..8b386202b374 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -104,7 +104,7 @@ void __intel_context_remove(struct intel_context *ce)
spin_unlock(&ctx->hw_contexts_lock);
}
-static struct intel_context *
+struct intel_context *
intel_context_instance(struct i915_gem_context *ctx,
struct intel_engine_cs *engine)
{
@@ -112,7 +112,7 @@ intel_context_instance(struct i915_gem_context *ctx,
ce = intel_context_lookup(ctx, engine);
if (likely(ce))
- return ce;
+ return intel_context_get(ce);
ce = intel_context_alloc();
if (!ce)
@@ -125,7 +125,7 @@ intel_context_instance(struct i915_gem_context *ctx,
intel_context_free(ce);
GEM_BUG_ON(intel_context_lookup(ctx, engine) != pos);
- return pos;
+ return intel_context_get(pos);
}
struct intel_context *
@@ -139,30 +139,30 @@ intel_context_pin_lock(struct i915_gem_context *ctx,
if (IS_ERR(ce))
return ce;
- if (mutex_lock_interruptible(&ce->pin_mutex))
+ if (mutex_lock_interruptible(&ce->pin_mutex)) {
+ intel_context_put(ce);
return ERR_PTR(-EINTR);
+ }
return ce;
}
-struct intel_context *
-intel_context_pin(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
+void intel_context_pin_unlock(struct intel_context *ce)
+ __releases(ce->pin_mutex)
{
- struct intel_context *ce;
- int err;
-
- ce = intel_context_instance(ctx, engine);
- if (IS_ERR(ce))
- return ce;
+ mutex_unlock(&ce->pin_mutex);
+ intel_context_put(ce);
+}
- if (likely(atomic_inc_not_zero(&ce->pin_count)))
- return ce;
+int __intel_context_do_pin(struct intel_context *ce)
+{
+ int err;
if (mutex_lock_interruptible(&ce->pin_mutex))
- return ERR_PTR(-EINTR);
+ return -EINTR;
if (likely(!atomic_read(&ce->pin_count))) {
+ struct i915_gem_context *ctx = ce->gem_context;
intel_wakeref_t wakeref;
err = 0;
@@ -172,7 +172,6 @@ intel_context_pin(struct i915_gem_context *ctx,
goto err;
i915_gem_context_get(ctx);
- GEM_BUG_ON(ce->gem_context != ctx);
mutex_lock(&ctx->mutex);
list_add(&ce->active_link, &ctx->active_engines);
@@ -186,11 +185,11 @@ intel_context_pin(struct i915_gem_context *ctx,
GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */
mutex_unlock(&ce->pin_mutex);
- return ce;
+ return 0;
err:
mutex_unlock(&ce->pin_mutex);
- return ERR_PTR(err);
+ return err;
}
void intel_context_unpin(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index 60379eb37949..b9a574587eb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -49,11 +49,7 @@ intel_context_is_pinned(struct intel_context *ce)
return atomic_read(&ce->pin_count);
}
-static inline void intel_context_pin_unlock(struct intel_context *ce)
-__releases(ce->pin_mutex)
-{
- mutex_unlock(&ce->pin_mutex);
-}
+void intel_context_pin_unlock(struct intel_context *ce);
struct intel_context *
__intel_context_insert(struct i915_gem_context *ctx,
@@ -63,7 +59,18 @@ void
__intel_context_remove(struct intel_context *ce);
struct intel_context *
-intel_context_pin(struct i915_gem_context *ctx, struct intel_engine_cs
*engine);
+intel_context_instance(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine);
+
+int __intel_context_do_pin(struct intel_context *ce);
+
+static inline int intel_context_pin(struct intel_context *ce)
+{
+ if (likely(atomic_inc_not_zero(&ce->pin_count)))
+ return 0;
+
+ return __intel_context_do_pin(ce);
+}
static inline void __intel_context_pin(struct intel_context *ce)
{
diff --git a/drivers/gpu/drm/i91
[Intel-gfx] [CI 8/9] drm/i915: Remove intel_context.active_link
We no longer need to track the active intel_contexts within each engine,
allowing us to drop a tricky mutex_lock from inside unpin (which may
occur inside fs_reclaim).
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 11 +--
drivers/gpu/drm/i915/gt/intel_context_types.h | 1 -
drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
drivers/gpu/drm/i915/i915_gem_context.c | 2 --
drivers/gpu/drm/i915/i915_gem_context_types.h | 1 -
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 1 -
7 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5e506e648454..1f1761fc6597 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -49,7 +49,6 @@ int __intel_context_do_pin(struct intel_context *ce)
return -EINTR;
if (likely(!atomic_read(&ce->pin_count))) {
- struct i915_gem_context *ctx = ce->gem_context;
intel_wakeref_t wakeref;
err = 0;
@@ -58,11 +57,7 @@ int __intel_context_do_pin(struct intel_context *ce)
if (err)
goto err;
- i915_gem_context_get(ctx);
-
- mutex_lock(&ctx->mutex);
- list_add(&ce->active_link, &ctx->active_engines);
- mutex_unlock(&ctx->mutex);
+ i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */
intel_context_get(ce);
smp_mb__before_atomic(); /* flush pin before it is visible */
@@ -91,10 +86,6 @@ void intel_context_unpin(struct intel_context *ce)
if (likely(atomic_dec_and_test(&ce->pin_count))) {
ce->ops->unpin(ce);
- mutex_lock(&ce->gem_context->mutex);
- list_del(&ce->active_link);
- mutex_unlock(&ce->gem_context->mutex);
-
i915_gem_context_put(ce->gem_context);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 3579c2708321..d5a7dbd0daee 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -38,7 +38,6 @@ struct intel_context {
struct intel_engine_cs *engine;
struct intel_engine_cs *active;
- struct list_head active_link;
struct list_head signal_link;
struct list_head signals;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bc94b778da6f..ffbf5d920429 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -34,6 +34,7 @@
#include "gt/intel_reset.h"
+#include "i915_gem_context.h"
#include "intel_dp.h"
#include "intel_drv.h"
#include "intel_fbc.h"
@@ -397,14 +398,17 @@ static void print_context_stats(struct seq_file *m,
struct i915_gem_context *ctx;
list_for_each_entry(ctx, &i915->contexts.list, link) {
+ struct i915_gem_engines_iter it;
struct intel_context *ce;
- list_for_each_entry(ce, &ctx->active_engines, active_link) {
+ for_each_gem_engine(ce,
+ i915_gem_context_lock_engines(ctx), it) {
if (ce->state)
per_file_stats(0, ce->state->obj, &kstats);
if (ce->ring)
per_file_stats(0, ce->ring->vma->obj, &kstats);
}
+ i915_gem_context_unlock_engines(ctx);
if (!IS_ERR_OR_NULL(ctx->file_priv)) {
struct file_stats stats = { .vm = &ctx->ppgtt->vm, };
@@ -1882,6 +1886,7 @@ static int i915_context_status(struct seq_file *m, void
*unused)
return ret;
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
+ struct i915_gem_engines_iter it;
struct intel_context *ce;
seq_puts(m, "HW context ");
@@ -1906,7 +1911,8 @@ static int i915_context_status(struct seq_file *m, void
*unused)
seq_putc(m, ctx->remap_slice ? 'R' : 'r');
seq_putc(m, '\n');
- list_for_each_entry(ce, &ctx->active_engines, active_link) {
+ for_each_gem_engine(ce,
+ i915_gem_context_lock_engines(ctx), it) {
seq_printf(m, "%s: ", ce->engine->name);
if (ce->state)
describe_obj(m, ce->state->obj);
@@ -1914,6 +1920,7 @@ static int i915_context_status(struct seq_file *m, void
*unused)
describe_ctx_ring(m, ce->ring);
seq_putc(m, '\n');
[Intel-gfx] [CI 6/9] drm/i915: Split engine setup/init into two phases
In the next patch, we require the engine vfuncs setup prior to
initialising the pinned kernel contexts, so split the vfunc setup from
the engine initialisation and call it earlier.
v2: s/setup_xcs/setup_common/ for intel_ring_submission_setup()
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h| 8 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 99
drivers/gpu/drm/i915/gt/intel_lrc.c | 74 ++
drivers/gpu/drm/i915/gt/intel_lrc.h | 5 +-
drivers/gpu/drm/i915/gt/intel_ringbuffer.c| 232 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 48 ++--
drivers/gpu/drm/i915/gt/mock_engine.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 6 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 12 +-
10 files changed, 245 insertions(+), 244 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index a228dc1774d8..3e53f53bc52b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -362,14 +362,12 @@ __intel_ring_space(unsigned int head, unsigned int tail,
unsigned int size)
return (head - tail - CACHELINE_BYTES) & (size - 1);
}
-int intel_engine_setup_common(struct intel_engine_cs *engine);
+int intel_engines_setup(struct drm_i915_private *i915);
int intel_engine_init_common(struct intel_engine_cs *engine);
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
-int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
-int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
-int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
-int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
+int intel_ring_submission_setup(struct intel_engine_cs *engine);
+int intel_ring_submission_init(struct intel_engine_cs *engine);
int intel_engine_stop_cs(struct intel_engine_cs *engine);
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 5a6b81836902..7682f16fa567 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -50,35 +50,24 @@
struct engine_class_info {
const char *name;
- int (*init_legacy)(struct intel_engine_cs *engine);
- int (*init_execlists)(struct intel_engine_cs *engine);
-
u8 uabi_class;
};
static const struct engine_class_info intel_engine_classes[] = {
[RENDER_CLASS] = {
.name = "rcs",
- .init_execlists = logical_render_ring_init,
- .init_legacy = intel_init_render_ring_buffer,
.uabi_class = I915_ENGINE_CLASS_RENDER,
},
[COPY_ENGINE_CLASS] = {
.name = "bcs",
- .init_execlists = logical_xcs_ring_init,
- .init_legacy = intel_init_blt_ring_buffer,
.uabi_class = I915_ENGINE_CLASS_COPY,
},
[VIDEO_DECODE_CLASS] = {
.name = "vcs",
- .init_execlists = logical_xcs_ring_init,
- .init_legacy = intel_init_bsd_ring_buffer,
.uabi_class = I915_ENGINE_CLASS_VIDEO,
},
[VIDEO_ENHANCEMENT_CLASS] = {
.name = "vecs",
- .init_execlists = logical_xcs_ring_init,
- .init_legacy = intel_init_vebox_ring_buffer,
.uabi_class = I915_ENGINE_CLASS_VIDEO_ENHANCE,
},
};
@@ -416,48 +405,39 @@ int intel_engines_init_mmio(struct drm_i915_private
*dev_priv)
/**
* intel_engines_init() - init the Engine Command Streamers
- * @dev_priv: i915 device private
+ * @i915: i915 device private
*
* Return: non-zero if the initialization failed.
*/
-int intel_engines_init(struct drm_i915_private *dev_priv)
+int intel_engines_init(struct drm_i915_private *i915)
{
+ int (*init)(struct intel_engine_cs *engine);
struct intel_engine_cs *engine;
enum intel_engine_id id, err_id;
int err;
- for_each_engine(engine, dev_priv, id) {
- const struct engine_class_info *class_info =
- &intel_engine_classes[engine->class];
- int (*init)(struct intel_engine_cs *engine);
-
- if (HAS_EXECLISTS(dev_priv))
- init = class_info->init_execlists;
- else
- init = class_info->init_legacy;
+ if (HAS_EXECLISTS(i915))
+ init = intel_execlists_submission_init;
+ else
+ init = intel_ring_submission_init;
- err = -EINVAL;
+ for_each_engine(engine, i915, id) {
err_id = id;
- if (GEM_DEBUG_WARN_ON(!init))
- goto cleanup;
-
err = init(engine);
[Intel-gfx] [CI 5/9] drm/i915: Pass intel_context to intel_context_pin_lock()
Move the intel_context_instance() to the caller so that we can decouple
ourselves from one context instance per engine.
v2: Rename pin_lock() to lock_pinned(), hopefully that is clearer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 26 --
drivers/gpu/drm/i915/gt/intel_context.h | 34 +--
drivers/gpu/drm/i915/i915_gem_context.c | 92 +++
.../gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
4 files changed, 82 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 8b386202b374..15ac99c5dd4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -128,32 +128,6 @@ intel_context_instance(struct i915_gem_context *ctx,
return intel_context_get(pos);
}
-struct intel_context *
-intel_context_pin_lock(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
- __acquires(ce->pin_mutex)
-{
- struct intel_context *ce;
-
- ce = intel_context_instance(ctx, engine);
- if (IS_ERR(ce))
- return ce;
-
- if (mutex_lock_interruptible(&ce->pin_mutex)) {
- intel_context_put(ce);
- return ERR_PTR(-EINTR);
- }
-
- return ce;
-}
-
-void intel_context_pin_unlock(struct intel_context *ce)
- __releases(ce->pin_mutex)
-{
- mutex_unlock(&ce->pin_mutex);
- intel_context_put(ce);
-}
-
int __intel_context_do_pin(struct intel_context *ce)
{
int err;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
b/drivers/gpu/drm/i915/gt/intel_context.h
index b9a574587eb3..b746add6b71d 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -31,25 +31,45 @@ intel_context_lookup(struct i915_gem_context *ctx,
struct intel_engine_cs *engine);
/**
- * intel_context_pin_lock - Stablises the 'pinned' status of the HW context
- * @ctx - the parent GEM context
- * @engine - the target HW engine
+ * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context
+ * @ce - the context
*
* Acquire a lock on the pinned status of the HW context, such that the context
* can neither be bound to the GPU or unbound whilst the lock is held, i.e.
* intel_context_is_pinned() remains stable.
*/
-struct intel_context *
-intel_context_pin_lock(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine);
+static inline int intel_context_lock_pinned(struct intel_context *ce)
+ __acquires(ce->pin_mutex)
+{
+ return mutex_lock_interruptible(&ce->pin_mutex);
+}
+/**
+ * intel_context_is_pinned - Reports the 'pinned' status
+ * @ce - the context
+ *
+ * While in use by the GPU, the context, along with its ring and page
+ * tables is pinned into memory and the GTT.
+ *
+ * Returns: true if the context is currently pinned for use by the GPU.
+ */
static inline bool
intel_context_is_pinned(struct intel_context *ce)
{
return atomic_read(&ce->pin_count);
}
-void intel_context_pin_unlock(struct intel_context *ce);
+/**
+ * intel_context_unlock_pinned - Releases the earlier locking of 'pinned'
status
+ * @ce - the context
+ *
+ * Releases the lock earlier acquired by intel_context_unlock_pinned().
+ */
+static inline void intel_context_unlock_pinned(struct intel_context *ce)
+ __releases(ce->pin_mutex)
+{
+ mutex_unlock(&ce->pin_mutex);
+}
struct intel_context *
__intel_context_insert(struct i915_gem_context *ctx,
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 05496ea7a123..d9db3fea151c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -141,6 +141,18 @@ static void lut_close(struct i915_gem_context *ctx)
rcu_read_unlock();
}
+static struct intel_context *
+lookup_user_engine(struct i915_gem_context *ctx, u16 class, u16 instance)
+{
+ struct intel_engine_cs *engine;
+
+ engine = intel_engine_lookup_user(ctx->i915, class, instance);
+ if (!engine)
+ return ERR_PTR(-EINVAL);
+
+ return intel_context_instance(ctx, engine);
+}
+
static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
{
unsigned int max;
@@ -1132,19 +1144,17 @@ gen8_modify_rpcs(struct intel_context *ce, struct
intel_sseu sseu)
}
static int
-__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_sseu sseu)
+__intel_context_reconfigure_sseu(struct intel_context *ce,
+struct intel_sseu sseu)
{
- struct intel_context *ce;
- int ret = 0;
+ int ret;
- GEM_BUG_ON(INTEL_GEN(ctx->i915) < 8);
- GEM_BUG_ON(engine->id != RCS0);
+
[Intel-gfx] [CI 3/9] drm/i915/selftests: Use the real kernel context for sseu isolation tests
Simply the setup slightly for the sseu selftests to use the actual
kernel_context.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 71d896bbade2..807644ae6877 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -957,7 +957,6 @@ __sseu_finish(struct drm_i915_private *i915,
const char *name,
unsigned int flags,
struct i915_gem_context *ctx,
- struct i915_gem_context *kctx,
struct intel_engine_cs *engine,
struct drm_i915_gem_object *obj,
unsigned int expected,
@@ -979,7 +978,8 @@ __sseu_finish(struct drm_i915_private *i915,
if (ret)
goto out;
- ret = __read_slice_count(i915, kctx, engine, obj, NULL, &rpcs);
+ ret = __read_slice_count(i915, i915->kernel_context, engine, obj,
+NULL, &rpcs);
ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!");
out:
@@ -1011,22 +1011,17 @@ __sseu_test(struct drm_i915_private *i915,
struct intel_sseu sseu)
{
struct igt_spinner *spin = NULL;
- struct i915_gem_context *kctx;
int ret;
- kctx = kernel_context(i915);
- if (IS_ERR(kctx))
- return PTR_ERR(kctx);
-
ret = __sseu_prepare(i915, name, flags, ctx, engine, &spin);
if (ret)
- goto out_context;
+ return ret;
ret = __i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
if (ret)
goto out_spin;
- ret = __sseu_finish(i915, name, flags, ctx, kctx, engine, obj,
+ ret = __sseu_finish(i915, name, flags, ctx, engine, obj,
hweight32(sseu.slice_mask), spin);
out_spin:
@@ -1035,10 +1030,6 @@ __sseu_test(struct drm_i915_private *i915,
igt_spinner_fini(spin);
kfree(spin);
}
-
-out_context:
- kernel_context_close(kctx);
-
return ret;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 7/9] drm/i915: Switch back to an array of logical per-engine HW contexts
We switched to a tree of per-engine HW context to accommodate the
introduction of virtual engines. However, we plan to also support
multiple instances of the same engine within the GEM context, defeating
our use of the engine as a key to looking up the HW context. Just
allocate a logical per-engine instance and always use an index into the
ctx->engines[]. Later on, this ctx->engines[] may be replaced by a user
specified map.
v2: Add for_each_gem_engine() helper to iterator within the engines lock
v3: intel_context_create_request() helper
v4: s/unsigned long/unsigned int/ 4 billion engines is quite enough.
v5: Push iterator locking to caller
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_context.c | 112 --
drivers/gpu/drm/i915/gt/intel_context.h | 27 +
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/mock_engine.c | 3 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 24 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 96 +--
drivers/gpu/drm/i915/i915_gem_context.h | 58 +
drivers/gpu/drm/i915/i915_gem_context_types.h | 40 ++-
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 70 +--
drivers/gpu/drm/i915/i915_perf.c | 80 +++--
drivers/gpu/drm/i915/i915_request.c | 15 +--
drivers/gpu/drm/i915/intel_guc_submission.c | 22 ++--
.../gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 14 ++-
16 files changed, 328 insertions(+), 241 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 15ac99c5dd4a..5e506e648454 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -17,7 +17,7 @@ static struct i915_global_context {
struct kmem_cache *slab_ce;
} global;
-struct intel_context *intel_context_alloc(void)
+static struct intel_context *intel_context_alloc(void)
{
return kmem_cache_zalloc(global.slab_ce, GFP_KERNEL);
}
@@ -28,104 +28,17 @@ void intel_context_free(struct intel_context *ce)
}
struct intel_context *
-intel_context_lookup(struct i915_gem_context *ctx,
+intel_context_create(struct i915_gem_context *ctx,
struct intel_engine_cs *engine)
{
- struct intel_context *ce = NULL;
- struct rb_node *p;
-
- spin_lock(&ctx->hw_contexts_lock);
- p = ctx->hw_contexts.rb_node;
- while (p) {
- struct intel_context *this =
- rb_entry(p, struct intel_context, node);
-
- if (this->engine == engine) {
- GEM_BUG_ON(this->gem_context != ctx);
- ce = this;
- break;
- }
-
- if (this->engine < engine)
- p = p->rb_right;
- else
- p = p->rb_left;
- }
- spin_unlock(&ctx->hw_contexts_lock);
-
- return ce;
-}
-
-struct intel_context *
-__intel_context_insert(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_context *ce)
-{
- struct rb_node **p, *parent;
- int err = 0;
-
- spin_lock(&ctx->hw_contexts_lock);
-
- parent = NULL;
- p = &ctx->hw_contexts.rb_node;
- while (*p) {
- struct intel_context *this;
-
- parent = *p;
- this = rb_entry(parent, struct intel_context, node);
-
- if (this->engine == engine) {
- err = -EEXIST;
- ce = this;
- break;
- }
-
- if (this->engine < engine)
- p = &parent->rb_right;
- else
- p = &parent->rb_left;
- }
- if (!err) {
- rb_link_node(&ce->node, parent, p);
- rb_insert_color(&ce->node, &ctx->hw_contexts);
- }
-
- spin_unlock(&ctx->hw_contexts_lock);
-
- return ce;
-}
-
-void __intel_context_remove(struct intel_context *ce)
-{
- struct i915_gem_context *ctx = ce->gem_context;
-
- spin_lock(&ctx->hw_contexts_lock);
- rb_erase(&ce->node, &ctx->hw_contexts);
- spin_unlock(&ctx->hw_contexts_lock);
-}
-
-struct intel_context *
-intel_context_instance(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
- struct intel_context *ce, *pos;
-
- ce = intel_context_lookup(ctx, engine);
- if (likely(ce))
- return intel_context_get(ce);
+ struct intel_context *ce;
ce = intel_context_alloc();
if (!ce)
return ERR_PTR(-ENOMEM);
intel_cont
[Intel-gfx] [CI 9/9] drm/i915: Move i915_request_alloc into selftests/
Having transitioned GEM over to using intel_context as its primary means
of tracking the GEM context and engine combined and using
i915_request_create(), we can move the older i915_request_alloc()
helper function into selftests/ where the remaining users are confined.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++--
drivers/gpu/drm/i915/gt/selftest_lrc.c| 13 ---
.../gpu/drm/i915/gt/selftest_workarounds.c| 15 +++-
drivers/gpu/drm/i915/i915_request.c | 38 ---
drivers/gpu/drm/i915/i915_request.h | 3 --
drivers/gpu/drm/i915/selftests/huge_pages.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_gem.c | 5 ++-
.../gpu/drm/i915/selftests/i915_gem_context.c | 13 ---
.../gpu/drm/i915/selftests/i915_gem_evict.c | 3 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +-
.../gpu/drm/i915/selftests/igt_gem_utils.c| 34 +
.../gpu/drm/i915/selftests/igt_gem_utils.h| 17 +
drivers/gpu/drm/i915/selftests/igt_spinner.c | 3 +-
drivers/gpu/drm/i915/selftests/mock_request.c | 3 +-
15 files changed, 89 insertions(+), 75 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/igt_gem_utils.c
create mode 100644 drivers/gpu/drm/i915/selftests/igt_gem_utils.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index dd8d923aa1c6..58643373495c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -193,6 +193,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/i915_random.o \
selftests/i915_selftest.o \
selftests/igt_flush_test.o \
+ selftests/igt_gem_utils.o \
selftests/igt_live_test.o \
selftests/igt_reset.o \
selftests/igt_spinner.o
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 9dece55a091c..dab3d30c9c73 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -29,6 +29,7 @@
#include "i915_selftest.h"
#include "selftests/i915_random.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/igt_gem_utils.h"
#include "selftests/igt_reset.h"
#include "selftests/igt_wedge_me.h"
@@ -175,7 +176,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs
*engine)
if (err)
goto unpin_vma;
- rq = i915_request_alloc(engine, h->ctx);
+ rq = igt_request_alloc(h->ctx, engine);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto unpin_hws;
@@ -455,7 +456,7 @@ static int igt_reset_nop(void *arg)
for (i = 0; i < 16; i++) {
struct i915_request *rq;
- rq = i915_request_alloc(engine, ctx);
+ rq = igt_request_alloc(ctx, engine);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
break;
@@ -554,7 +555,7 @@ static int igt_reset_nop_engine(void *arg)
for (i = 0; i < 16; i++) {
struct i915_request *rq;
- rq = i915_request_alloc(engine, ctx);
+ rq = igt_request_alloc(ctx, engine);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
break;
@@ -800,7 +801,7 @@ static int active_engine(void *data)
struct i915_request *new;
mutex_lock(&engine->i915->drm.struct_mutex);
- new = i915_request_alloc(engine, ctx[idx]);
+ new = igt_request_alloc(ctx[idx], engine);
if (IS_ERR(new)) {
mutex_unlock(&engine->i915->drm.struct_mutex);
err = PTR_ERR(new);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index cd0551f97c2f..84538f69185b 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -10,6 +10,7 @@
#include "i915_selftest.h"
#include "selftests/i915_random.h"
#include "selftests/igt_flush_test.h"
+#include "selftests/igt_gem_utils.h"
#include "selftests/igt_live_test.h"
#include "selftests/igt_spinner.h"
#include "selftests/mock_context.h"
@@ -148,7 +149,7 @@ static int live_busywait_preempt(void *arg)
* fails, we hang instead.
*/
- lo = i915_request_alloc(engine, ctx_lo);
+ lo = igt_request_alloc(ctx_lo, engine);
if (IS_ERR(lo)) {
err = PTR_ERR(lo);
goto err_vma;
@@ -192,7 +193,7 @@ static int live_busywait_preempt(void *arg)
[Intel-gfx] [CI 4/9] drm/i915/selftests: Pass around intel_context for sseu
Combine the (i915_gem_context, intel_engine) into a single parameter,
the intel_context for convenience and later simplification.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 74 +++
1 file changed, 44 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 807644ae6877..8e2a94333559 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -755,8 +755,7 @@ static struct i915_vma *rpcs_query_batch(struct i915_vma
*vma)
static int
emit_rpcs_query(struct drm_i915_gem_object *obj,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
+ struct intel_context *ce,
struct i915_request **rq_out)
{
struct i915_request *rq;
@@ -764,9 +763,9 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
struct i915_vma *vma;
int err;
- GEM_BUG_ON(!intel_engine_can_store_dword(engine));
+ GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
- vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
+ vma = i915_vma_instance(obj, &ce->gem_context->ppgtt->vm, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
@@ -784,13 +783,15 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
goto err_vma;
}
- rq = i915_request_alloc(engine, ctx);
+ rq = i915_request_create(ce);
if (IS_ERR(rq)) {
err = PTR_ERR(rq);
goto err_batch;
}
- err = engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0);
+ err = rq->engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
if (err)
goto err_request;
@@ -834,8 +835,7 @@ static int
__sseu_prepare(struct drm_i915_private *i915,
const char *name,
unsigned int flags,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
+ struct intel_context *ce,
struct igt_spinner **spin)
{
struct i915_request *rq;
@@ -853,7 +853,10 @@ __sseu_prepare(struct drm_i915_private *i915,
if (ret)
goto err_free;
- rq = igt_spinner_create_request(*spin, ctx, engine, MI_NOOP);
+ rq = igt_spinner_create_request(*spin,
+ ce->gem_context,
+ ce->engine,
+ MI_NOOP);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
goto err_fini;
@@ -880,8 +883,7 @@ __sseu_prepare(struct drm_i915_private *i915,
static int
__read_slice_count(struct drm_i915_private *i915,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
+ struct intel_context *ce,
struct drm_i915_gem_object *obj,
struct igt_spinner *spin,
u32 *rpcs)
@@ -892,7 +894,7 @@ __read_slice_count(struct drm_i915_private *i915,
u32 *buf, val;
long ret;
- ret = emit_rpcs_query(obj, ctx, engine, &rq);
+ ret = emit_rpcs_query(obj, ce, &rq);
if (ret)
return ret;
@@ -956,29 +958,28 @@ static int
__sseu_finish(struct drm_i915_private *i915,
const char *name,
unsigned int flags,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
+ struct intel_context *ce,
struct drm_i915_gem_object *obj,
unsigned int expected,
struct igt_spinner *spin)
{
- unsigned int slices = hweight32(engine->sseu.slice_mask);
+ unsigned int slices = hweight32(ce->engine->sseu.slice_mask);
u32 rpcs = 0;
int ret = 0;
if (flags & TEST_RESET) {
- ret = i915_reset_engine(engine, "sseu");
+ ret = i915_reset_engine(ce->engine, "sseu");
if (ret)
goto out;
}
- ret = __read_slice_count(i915, ctx, engine, obj,
+ ret = __read_slice_count(i915, ce, obj,
flags & TEST_RESET ? NULL : spin, &rpcs);
ret = __check_rpcs(name, rpcs, ret, expected, "Context", "!");
if (ret)
goto out;
- ret = __read_slice_count(i915, i915->kernel_context, engine, obj,
+ ret = __read_slice_count(i915, ce->engine->kernel_context, obj,
NULL, &rpcs);
ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!");
@@ -993,7 +994,7 @@ __sseu_finish(struct drm_i915_private *i915,
if (ret)
return ret;
-
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : warning == Summary == $ dim checkpatch origin/drm-tip df18fb0cb42a drm/i915/gvt: Pin the per-engine GVT shadow contexts e21e4dc54c65 drm/i915: Export intel_context_instance() 059c3b36d6aa drm/i915/selftests: Use the real kernel context for sseu isolation tests e18447869df3 drm/i915/selftests: Pass around intel_context for sseu 6cd19bc51af2 drm/i915: Pass intel_context to intel_context_pin_lock() 5a139a452c59 drm/i915: Split engine setup/init into two phases db367156d990 drm/i915: Switch back to an array of logical per-engine HW contexts -:588: WARNING:LINE_SPACING: Missing a blank line after declarations #588: FILE: drivers/gpu/drm/i915/i915_gem_context.h:214: + struct i915_gem_engines *e = rcu_dereference(ctx->engines); + if (likely(idx < e->num_engines && e->engines[idx])) -:607: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'it' - possible side-effects? #607: FILE: drivers/gpu/drm/i915/i915_gem_context.h:233: +#define for_each_gem_engine(ce, engines, it) \ + for (i915_gem_engines_iter_init(&(it), (engines)); \ +((ce) = i915_gem_engines_iter_next(&(it)));) total: 0 errors, 1 warnings, 1 checks, 962 lines checked 3ad89dd1bd8f drm/i915: Remove intel_context.active_link 68ad0fba195d drm/i915: Move i915_request_alloc into selftests/ -:421: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #421: new file mode 100644 -:426: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #426: FILE: drivers/gpu/drm/i915/selftests/igt_gem_utils.c:1: +/* -:427: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #427: FILE: drivers/gpu/drm/i915/selftests/igt_gem_utils.c:2: + * SPDX-License-Identifier: MIT -:466: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #466: FILE: drivers/gpu/drm/i915/selftests/igt_gem_utils.h:1: +/* -:467: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #467: FILE: drivers/gpu/drm/i915/selftests/igt_gem_utils.h:2: + * SPDX-License-Identifier: MIT total: 0 errors, 5 warnings, 0 checks, 408 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
Joonas, Mesa now applies this WA on ICL and we're not seeing any regressions in CI. I tested Mesa with and without this patch applied to kernel. I don't see any performance impact to Manhattan from GfxBench5. I'm little surprised to see it's not really helping benchmark performance in Mesa. I'll dig bit more to figure out a possible explanation. I haven't tried any other benchmarks with this patch. Thanks Anuj On 04/26/2019 01:31 AM, Joonas Lahtinen wrote: + Anuj Quoting Lionel Landwerlin (2019-04-26 11:13:58) On 18/04/2019 18:06, Tvrtko Ursulin wrote: From: Tvrtko Ursulin WaEnableStateCacheRedirectToCS context workaround configures the L3 cache to benefit 3d workloads but media has different requirements. Remove the workaround and whitelist the register to allow any userspace configure the behaviour to their liking. v2: * Remove the workaround apart from adding the whitelist. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin Cc: kevin...@intel.com Cc: xiaogang...@intel.com Acked-by: Lionel Landwerlin Mesa commits : commit db5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (anv) commit eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (i965) commit d1be67db39463b48369cb71979ed18662b2c157e (iris) Could somebody confirm that applying this patch does not cause hangs in older mesa, and the performance drop (if any) is insignificant? Best Regards, Joonas ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/gvt: Pin the per-engine GVT shadow contexts Okay! Commit: drm/i915: Export intel_context_instance() -O:drivers/gpu/drm/i915/gt/intel_context.c:131:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit +drivers/gpu/drm/i915/gt/intel_context.c:131:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit +drivers/gpu/drm/i915/gt/intel_context.c:150:6: warning: context imbalance in 'intel_context_pin_unlock' - wrong count at exit Commit: drm/i915/selftests: Use the real kernel context for sseu isolation tests Okay! Commit: drm/i915/selftests: Pass around intel_context for sseu Okay! Commit: drm/i915: Pass intel_context to intel_context_pin_lock() -O:drivers/gpu/drm/i915/gt/intel_context.c:131:22: warning: context imbalance in 'intel_context_pin_lock' - wrong count at exit -O:drivers/gpu/drm/i915/gt/intel_context.c:150:6: warning: context imbalance in 'intel_context_pin_unlock' - wrong count at exit Commit: drm/i915: Split engine setup/init into two phases Okay! Commit: drm/i915: Switch back to an array of logical per-engine HW contexts +./include/linux/overflow.h:285:13: error: incorrect type in conditional +./include/linux/overflow.h:285:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/overflow.h:285:13:got void +./include/linux/overflow.h:285:13: warning: call with no type! +./include/linux/overflow.h:287:13: error: incorrect type in conditional +./include/linux/overflow.h:287:13: error: undefined identifier '__builtin_add_overflow' +./include/linux/overflow.h:287:13:got void +./include/linux/overflow.h:287:13: warning: call with no type! Commit: drm/i915: Remove intel_context.active_link Okay! Commit: drm/i915: Move i915_request_alloc into selftests/ +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1
On Thu, Apr 18, 2019 at 3:06 AM Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin > > WaEnableStateCacheRedirectToCS context workaround configures the L3 cache > to benefit 3d workloads but media has different requirements. > > Remove the workaround and whitelist the register to allow any userspace > configure the behaviour to their liking. > > v2: > * Remove the workaround apart from adding the whitelist. > > Signed-off-by: Tvrtko Ursulin > Cc: Lionel Landwerlin > Cc: kevin...@intel.com > Cc: xiaogang...@intel.com > --- > drivers/gpu/drm/i915/intel_workarounds.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c > b/drivers/gpu/drm/i915/intel_workarounds.c > index b3cbed1ee1c9..baed186724d2 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -556,10 +556,6 @@ static void icl_ctx_workarounds_init(struct > intel_engine_cs *engine) > WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > GEN11_TDL_CLOCK_GATING_FIX_DISABLE); > > - /* WaEnableStateCacheRedirectToCS:icl */ > - WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1, > - GEN11_STATE_CACHE_REDIRECT_TO_CS); > - > /* Wa_2006665173:icl (pre-prod) */ > if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > @@ -1070,6 +1066,9 @@ static void icl_whitelist_build(struct i915_wa_list *w) > > /* WaAllowUMDToModifySamplerMode:icl */ > whitelist_reg(w, GEN10_SAMPLER_MODE); > + > + /* WaEnableStateCacheRedirectToCS:icl */ > + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > -- > 2.19.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx Acked-by: Anuj Phogat ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts
== Series Details == Series: series starting with [CI,1/9] drm/i915/gvt: Pin the per-engine GVT shadow contexts URL : https://patchwork.freedesktop.org/series/60004/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6006 -> Patchwork_12885 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12885 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12885, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60004/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12885: ### IGT changes ### Possible regressions * igt@gem_exec_create@basic: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6006/fi-blb-e6850/igt@gem_exec_cre...@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12885/fi-blb-e6850/igt@gem_exec_cre...@basic.html Known issues Here are the changes found in Patchwork_12885 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_basic@create-fd-close: - fi-skl-6700k2: [INCOMPLETE][3] -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6006/fi-skl-6700k2/igt@gem_ba...@create-fd-close.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12885/fi-skl-6700k2/igt@gem_ba...@create-fd-close.html Participating hosts (25 -> 23) -- ERROR: It appears as if the changes made in Patchwork_12885 prevented too many machines from booting. Additional (11): fi-skl-gvtdvm fi-byt-j1900 fi-skl-6260u fi-snb-2520m fi-kbl-7500u fi-bxt-j4205 fi-ivb-3770 fi-icl-u3 fi-cfl-8109u fi-skl-iommu fi-icl-dsi Missing(13): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-skl-guc fi-bdw-gvtdvm fi-byt-squawks fi-apl-guc fi-byt-clapper fi-kbl-x1275 fi-icl-y fi-byt-n2820 fi-bsw-kefka fi-snb-2600 Build changes - * Linux: CI_DRM_6006 -> Patchwork_12885 CI_DRM_6006: f2b80d9616c3ced3d5e04bba276c4e57265faabb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4968: caed251990f35bfe45368f803980071a73e36315 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12885: 68ad0fba195d3e0399a2ae9aeee8c772323a34a5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 68ad0fba195d drm/i915: Move i915_request_alloc into selftests/ 3ad89dd1bd8f drm/i915: Remove intel_context.active_link db367156d990 drm/i915: Switch back to an array of logical per-engine HW contexts 5a139a452c59 drm/i915: Split engine setup/init into two phases 6cd19bc51af2 drm/i915: Pass intel_context to intel_context_pin_lock() e18447869df3 drm/i915/selftests: Pass around intel_context for sseu 059c3b36d6aa drm/i915/selftests: Use the real kernel context for sseu isolation tests e21e4dc54c65 drm/i915: Export intel_context_instance() df18fb0cb42a drm/i915/gvt: Pin the per-engine GVT shadow contexts == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12885/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma
From: Uma Shankar
Add macros to define multi segmented gamma registers
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b74824f0b5b1..fc50e85ca895 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7198,6 +7198,7 @@ enum {
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
@@ -10144,6 +10145,22 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Add registers for Gen11 Multi Segmented Gamma Mode */
+#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08
+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15)
+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_INDEX_A, \
+ _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_DATA_A, \
+ _PAL_PREC_MULTI_SEG_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
2.17.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Change gamma/degamma_lut_size data type to u32
Currently, data type of gamma_lut_size & degamma_lut_size elements
in intel_device_info is u16, which means it can accommodate maximum
64k values. In case of ICL multisegmented gamma, the size of gamma
LUT is 256K.
This patch changes the data type of both of these elements to u32.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_device_info.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..67677c356716 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -179,8 +179,8 @@ struct intel_device_info {
int cursor_offsets[I915_MAX_PIPES];
struct color_luts {
- u16 degamma_lut_size;
- u16 gamma_lut_size;
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
u32 degamma_lut_tests;
u32 gamma_lut_tests;
} color;
--
2.17.1
___
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[Intel-gfx] [PATCH 3/3] drm/i915/icl: Add Multi-segmented gamma support
ICL introduces a new gamma correction mode in display engine, called
multi-segmented-gamma mode. This mode allows users to program the
darker region of the gamma curve with sueprfine precision. An
example use case for this is HDR curves (like PQ ST-2084).
If we plot a gamma correction curve from value range between 0.0 to 1.0,
ICL's multi-segment has 3 different sections:
- superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
- fine segment: 257 values, ranges between 0 - 1/(128)
- corase segment: 257 values, ranges between 0 - 1
This patch:
- Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256),
so that userspace can program with highest precision supported.
- Changes default gamma mode (non-legacy) to multi-segmented-gamma mode.
- Adds functions to program/detect multi-segment gamma.
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Suggested-by: Ville Syrjälä
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c| 3 +-
drivers/gpu/drm/i915/intel_color.c | 155 -
2 files changed, 156 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ffa2ee70a03d..83698951760b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -749,7 +749,8 @@ static const struct intel_device_info intel_cannonlake_info
= {
GEN(11), \
.ddb_size = 2048, \
.has_logical_ring_elsq = 1, \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262144 }
+
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ca341a9e47e6..d1fb79a5d764 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -41,6 +41,7 @@
#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
#define LEGACY_LUT_LENGTH 256
+#define ICL_MULTISEG_LUT_LENGTH(256 * 128 * 8)
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -58,6 +59,12 @@
#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+enum icl_ms_gamma_segments {
+ ICL_MS_GAMMA_SEG_SUPERFINE,
+ ICL_MS_GAMMA_SEG_FINE,
+ ICL_MS_GAMMA_SEG_COARSE,
+};
+
static const u16 ilk_csc_off_zero[3] = {};
static const u16 ilk_csc_coeff_identity[9] = {
@@ -767,6 +774,149 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
}
}
+/* ilk+ "12.4" interpolated format (high 10 bits) */
+static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
+{
+ return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
+ (color->blue >> 6);
+}
+
+/* ilk+ "12.4" interpolated format (low 6 bits) */
+static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
+{
+ return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
+ (color->blue & 0x3f);
+}
+
+static void
+icl_program_gamma_gcmax(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ /*
+* Program the max register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 1.0
+*/
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+* Program the max register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 1.0 to 3.0
+*/
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+* Program the gc max 2 register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 3.0 to 7.0
+*/
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+}
+
+static void
+icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state,
+ const struct drm_property_blob *blob,
+ enum icl_ms_gamma_segments segment)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_color_lut *lut = blob->data;
+ enum pipe pipe = crtc->pipe;
+ u32
Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add register definitions for Multi Segmented gamma
On Fri, Apr 26, 2019 at 11:31:50PM +0530, Shashank Sharma wrote:
> From: Uma Shankar
>
> Add macros to define multi segmented gamma registers
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b74824f0b5b1..fc50e85ca895 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7198,6 +7198,7 @@ enum {
> #define GAMMA_MODE_MODE_10BIT (1 << 0)
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
+ /* ivb-bdw */
> +#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
+ /* icl+ */
So people don't get super confused about the conflicting values.
>
> /* DMC/CSR */
> #define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
> @@ -10144,6 +10145,22 @@ enum skl_power_gate {
> #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
> _PRE_CSC_GAMC_INDEX_B)
> #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe,
> _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
>
> +/* Add registers for Gen11 Multi Segmented Gamma Mode */
> +#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408
> +#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08
> +#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15)
> +#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0)
> +
> +#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
> +#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
> +
> +#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
> + _PAL_PREC_MULTI_SEG_INDEX_A, \
> + _PAL_PREC_MULTI_SEG_INDEX_B)
> +#define PREC_PAL_MULTI_SEG_DATA(pipe)_MMIO_PIPE(pipe, \
> + _PAL_PREC_MULTI_SEG_DATA_A, \
> + _PAL_PREC_MULTI_SEG_DATA_B)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> --
> 2.17.1
--
Ville Syrjälä
Intel
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[Intel-gfx] [PATCH 1/3] drm/i915/execlists: Flush the tasklet on parking
Tidy up the cleanup sequence by always ensure that the tasklet is
flushed on parking (before we cleanup). The parking provides a
convenient point to ensure that the backend is truly idle.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 25 +++--
drivers/gpu/drm/i915/intel_guc_submission.c | 1 +
2 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 01f58a152a9e..ea7794d368d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2331,27 +2331,18 @@ static int gen8_init_rcs_context(struct i915_request
*rq)
return i915_gem_render_state_emit(rq);
}
+static void execlists_park(struct intel_engine_cs *engine)
+{
+ tasklet_kill(&engine->execlists.tasklet);
+}
+
/**
* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
* @engine: Engine Command Streamer.
*/
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv;
-
- /*
-* Tasklet cannot be active at this point due intel_mark_active/idle
-* so this is just for documentation.
-*/
- if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
-&engine->execlists.tasklet.state)))
- tasklet_kill(&engine->execlists.tasklet);
-
- dev_priv = engine->i915;
-
- if (engine->buffer) {
- WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
- }
+ struct drm_i915_private *i915 = engine->i915;
if (engine->cleanup)
engine->cleanup(engine);
@@ -2361,7 +2352,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs
*engine)
lrc_destroy_wa_ctx(engine);
engine->i915 = NULL;
- dev_priv->engine[engine->id] = NULL;
+ i915->engine[engine->id] = NULL;
kfree(engine);
}
@@ -2376,7 +2367,7 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->reset.reset = execlists_reset;
engine->reset.finish = execlists_reset_finish;
- engine->park = NULL;
+ engine->park = execlists_park;
engine->unpark = NULL;
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 4c814344809c..ed94001028f2 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1363,6 +1363,7 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
static void guc_submission_park(struct intel_engine_cs *engine)
{
+ tasklet_kill(&engine->execlists.tasklet);
intel_engine_unpin_breadcrumbs_irq(engine);
engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
--
2.20.1
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[Intel-gfx] [PATCH 3/3] drm/i915: Convert inconsistent static engine tables into an init error
Remove the modification of the "constant" device info by promoting the
inconsistent intel_engine static table into an initialisation error.
Now, if we add a new engine into the device_info, we must first add that
engine information into the intel_engines.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 30 ---
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 570c9a4813d1..c232e80d187c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -366,21 +366,20 @@ void intel_engines_cleanup(struct drm_i915_private *i915)
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
- * @dev_priv: i915 device private
+ * @i915: i915 device private
*
* Return: non-zero if the initialization failed.
*/
int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(i915);
- const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
- unsigned int mask = 0;
unsigned int i;
int err;
- WARN_ON(engine_mask == 0);
- WARN_ON(engine_mask &
- GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
+ /* We always presume we have at least RCS available for later probing */
+ if (GEM_WARN_ON(!HAS_ENGINE(i915, RCS0))) {
+ err = -ENODEV;
+ goto cleanup;
+ }
if (i915_inject_load_failure())
return -ENODEV;
@@ -392,25 +391,16 @@ int intel_engines_init_mmio(struct drm_i915_private *i915)
err = intel_engine_setup(i915, i);
if (err)
goto cleanup;
-
- mask |= BIT(i);
}
- /*
-* Catch failures to update intel_engines table when the new engines
-* are added to the driver by a warning and disabling the forgotten
-* engines.
-*/
- if (WARN_ON(mask != engine_mask))
- device_info->engine_mask = mask;
-
- /* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
+ /* Catch failures to update intel_engines table for new engines. */
+ if (GEM_WARN_ON(INTEL_INFO(i915)->engine_mask >> i)) {
err = -ENODEV;
goto cleanup;
}
- RUNTIME_INFO(i915)->num_engines = hweight32(mask);
+ RUNTIME_INFO(i915)->num_engines =
+ hweight32(INTEL_INFO(i915)->engine_mask);
i915_check_and_clear_faults(i915);
--
2.20.1
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[Intel-gfx] [PATCH 2/3] drm/i915: Move the engine->destroy() vfunc onto the engine
Make the engine responsible for cleaning itself up!
This removes the i915->gt.cleanup vfunc that has been annoying the
casual reader and myself for the last several years, and helps keep a
future patch to add more cleanup tidy.
v2: Assert that engine->destroy is set after the backend starts
allocating its own state.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 4 ++
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 66 +++-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 29 +++--
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 35 +--
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/i915_gem.c | 19 +-
7 files changed, 68 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
b/drivers/gpu/drm/i915/gt/intel_engine.h
index 3e53f53bc52b..f5b0f27cecb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -362,7 +362,11 @@ __intel_ring_space(unsigned int head, unsigned int tail,
unsigned int size)
return (head - tail - CACHELINE_BYTES) & (size - 1);
}
+int intel_engines_init_mmio(struct drm_i915_private *i915);
int intel_engines_setup(struct drm_i915_private *i915);
+int intel_engines_init(struct drm_i915_private *i915);
+void intel_engines_cleanup(struct drm_i915_private *i915);
+
int intel_engine_init_common(struct intel_engine_cs *engine);
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..570c9a4813d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -319,6 +319,12 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
engine->class = info->class;
engine->instance = info->instance;
+ /*
+* To be overridden by the backend on setup. However to facilitate
+* cleanup on error during setup, we always provide the destroy vfunc.
+*/
+ engine->destroy = (typeof(engine->destroy))kfree;
+
engine->uabi_class = intel_engine_classes[info->class].uabi_class;
engine->context_size = __intel_engine_context_size(dev_priv,
@@ -343,18 +349,31 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
return 0;
}
+/**
+ * intel_engines_cleanup() - free the resources allocated for Command Streamers
+ * @i915: the i915 device private
+ */
+void intel_engines_cleanup(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, i915, id) {
+ engine->destroy(engine);
+ i915->engine[id] = NULL;
+ }
+}
+
/**
* intel_engines_init_mmio() - allocate and prepare the Engine Command
Streamers
* @dev_priv: i915 device private
*
* Return: non-zero if the initialization failed.
*/
-int intel_engines_init_mmio(struct drm_i915_private *dev_priv)
+int intel_engines_init_mmio(struct drm_i915_private *i915)
{
- struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
- const unsigned int engine_mask = INTEL_INFO(dev_priv)->engine_mask;
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
+ struct intel_device_info *device_info = mkwrite_device_info(i915);
+ const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;
unsigned int mask = 0;
unsigned int i;
int err;
@@ -367,10 +386,10 @@ int intel_engines_init_mmio(struct drm_i915_private
*dev_priv)
return -ENODEV;
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
- if (!HAS_ENGINE(dev_priv, i))
+ if (!HAS_ENGINE(i915, i))
continue;
- err = intel_engine_setup(dev_priv, i);
+ err = intel_engine_setup(i915, i);
if (err)
goto cleanup;
@@ -386,20 +405,19 @@ int intel_engines_init_mmio(struct drm_i915_private
*dev_priv)
device_info->engine_mask = mask;
/* We always presume we have at least RCS available for later probing */
- if (WARN_ON(!HAS_ENGINE(dev_priv, RCS0))) {
+ if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
err = -ENODEV;
goto cleanup;
}
- RUNTIME_INFO(dev_priv)->num_engines = hweight32(mask);
+ RUNTIME_INFO(i915)->num_engines = hweight32(mask);
- i915_check_and_clear_faults(dev_priv);
+ i915_check_and_clear_faults(i915);
return 0;
cleanup:
- for_each_engine(engine, dev_priv, id)
- kfree(engine);
+ intel_engines_cleanup(i915);
return err;
}
@@ -413,7 +431,7 @@ int intel_engines_init(struct drm_i915_private *i915)
{
i
Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > From: Clinton Taylor
> >
> > v2: Fix commit msg to reflect why issue occurs(Jani)
> > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
> >
> > Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> > doesn't work correctly using xrandr max bpc property. When we
> > connect a monitor which supports deep color, the highest deep color
> > setting is selected; which sets GCP_COLOR_INDICATION. When we change
> > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> > doesn't allow the switch back to 8 bit color.
> >
> > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville)
> > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
> >
> > Drop the changes in intel_hdmi_compute_config as desired_bpp
> > is needed to change values for pipe_bpp based on bw_constrained flag.
> >
> > v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
> >
> > v6: Fix comment formatting (Ville)
> >
> > v7: Add reviewed by Ville
> >
> > v8: Set GCP_COLOR_INDICATION based on spec:
> > For Gen 7.5 or later platforms, indicate color depth only for deep
> > color modes. Bspec: 8135,7751,50524
> >
> > Pre DDI platforms, indicate color depth if deep color is supported
> > by sink. Bspec: 7854
> >
> > Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > Bspec: 15975
> >
> > Check pipe_bpp is less than bpp * 3 in hdmi_deep_color_possible,
> > to not set 12 bit deep color for every modeset. This fixes the issue
> > where 12 bit color was selected even when user selected 10 bit.(Ville)
> >
> > Co-Developed-by: Aditya Swarup
> > Co-Developed-by: Ville Syrjälä
> > Signed-off-by: Clinton Taylor
> > Signed-off-by: Aditya Swarup
> > Cc: Ville Syrjälä
> > Cc: Jani Nikula
> > Cc: Manasi Navare
> > Reviewed-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_hdmi.c | 17 +
> > 1 file changed, 13 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > b/drivers/gpu/drm/i915/intel_hdmi.c
> > index e1005d7b75fd..620bc89e2120 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -973,9 +973,18 @@ static void intel_hdmi_compute_gcp_infoframe(struct
> > intel_encoder *encoder,
> > crtc_state->infoframes.enable |=
> > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
> >
> > - /* Indicate color depth whenever the sink supports deep color */
> > - if (hdmi_sink_is_deep_color(conn_state))
> > - crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > + /* Indicate color depth whenever the sink supports deep color:
> > +* For Gen 7.5 or later platforms, indicate color depth only for deep
> > +* color modes.
> > +* Pre DDI platforms, indicate color depth if deep color is supported
> > +* by sink.
> > +* Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > +*/
> > + if (hdmi_sink_is_deep_color(conn_state)) {
> > + if(!HAS_DDI(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > + crtc_state->pipe_bpp > 24)
>
> I prefer the earlier version. Less special casing.
Then we won't be following spec for pre DDI platforms and CHV. These
conditions are required according to Bspec pages mentioned in the commit
message.
Also, hdmi_sink_is_deep_color check is required for pre DDI platforms,
since we send GCP_COLOR_INDICATION for 24 bit color as long as display
supports deep color.
>
> > + crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > + }
> >
> > /* Enable default_phase whenever the display mode is suitably aligned */
> > if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> > @@ -2172,7 +2181,7 @@ static bool hdmi_deep_color_possible(const struct
> > intel_crtc_state *crtc_state,
> > if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
> > return false;
> >
> > - if (crtc_state->pipe_bpp <= 8*3)
> > + if (crtc_state->pipe_bpp < bpc*3)
>
> This should be a separate patch.
I will create a new patch for this.
>
> > return false;
> >
> > if (!crtc_state->has_hdmi_sink)
> > --
> > 2.17.1
>
> --
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Add Multi-segmented gamma support
On Fri, Apr 26, 2019 at 11:31:51PM +0530, Shashank Sharma wrote:
> ICL introduces a new gamma correction mode in display engine, called
> multi-segmented-gamma mode. This mode allows users to program the
> darker region of the gamma curve with sueprfine precision. An
> example use case for this is HDR curves (like PQ ST-2084).
>
> If we plot a gamma correction curve from value range between 0.0 to 1.0,
> ICL's multi-segment has 3 different sections:
> - superfine segment: 9 values, ranges between 0 - 1/(128 * 256)
> - fine segment: 257 values, ranges between 0 - 1/(128)
> - corase segment: 257 values, ranges between 0 - 1
>
> This patch:
> - Changes gamma LUTs size for ICL/GEN11 to 262144 entries (8 * 128 * 256),
> so that userspace can program with highest precision supported.
> - Changes default gamma mode (non-legacy) to multi-segmented-gamma mode.
> - Adds functions to program/detect multi-segment gamma.
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Cc: Daniel Vetter
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Shashank Sharma
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_pci.c| 3 +-
> drivers/gpu/drm/i915/intel_color.c | 155 -
> 2 files changed, 156 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index ffa2ee70a03d..83698951760b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -749,7 +749,8 @@ static const struct intel_device_info
> intel_cannonlake_info = {
> GEN(11), \
> .ddb_size = 2048, \
> .has_logical_ring_elsq = 1, \
> - .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 262144 }
> +
>
> static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index ca341a9e47e6..d1fb79a5d764 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -41,6 +41,7 @@
> #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
>
> #define LEGACY_LUT_LENGTH256
> +#define ICL_MULTISEG_LUT_LENGTH (256 * 128 * 8)
> /*
> * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> * format). This macro takes the coefficient we want transformed and the
> @@ -58,6 +59,12 @@
>
> #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
>
> +enum icl_ms_gamma_segments {
> + ICL_MS_GAMMA_SEG_SUPERFINE,
> + ICL_MS_GAMMA_SEG_FINE,
> + ICL_MS_GAMMA_SEG_COARSE,
> +};
> +
> static const u16 ilk_csc_off_zero[3] = {};
>
> static const u16 ilk_csc_coeff_identity[9] = {
> @@ -767,6 +774,149 @@ static void glk_load_luts(const struct intel_crtc_state
> *crtc_state)
> }
> }
>
> +/* ilk+ "12.4" interpolated format (high 10 bits) */
> +static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> +{
> + return (color->red >> 6) << 20 | (color->green >> 6) << 10 |
> + (color->blue >> 6);
> +}
> +
> +/* ilk+ "12.4" interpolated format (low 6 bits) */
> +static u32 ilk_lut_12p4_udw(const struct drm_color_lut *color)
> +{
> + return (color->red & 0x3f) << 24 | (color->green & 0x3f) << 14 |
> + (color->blue & 0x3f);
> +}
> +
> +static void
> +icl_program_gamma_gcmax(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> +
> + /*
> + * Program the max register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 1.0
> + */
> + I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16));
> + I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16));
> + I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16));
This one I think we want to program based on the provide LUT. It's the
last entry that still gets used in interpolation for <1.0 values.
Or at least that's the way it works with the 12p4 mode IIRC. I don't
actually remember how it goes with the multi segment mode.
> +
> + /*
> + * Program the max register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 1.0 to 3.0
> + */
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
> +
> + /*
> + * Program the gc max 2 register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 3.0 to 7.0
> + */
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1
Re: [Intel-gfx] [PATCH v7] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Fri, Apr 26, 2019 at 01:12:58PM +0300, Ville Syrjälä wrote: > On Thu, Apr 25, 2019 at 01:44:37PM -0700, Aditya Swarup wrote: > > On Wed, Apr 17, 2019 at 12:57:44PM +0300, Jani Nikula wrote: > > > On Fri, 05 Apr 2019, Aditya Swarup wrote: > > > > From: Clinton Taylor > > > > > > > > v2: Fix commit msg to reflect why issue occurs(Jani) > > > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color. > > > > > > > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa) > > > > doesn't work correctly using xrandr max bpc property. When we > > > > connect a monitor which supports deep color, the highest deep color > > > > setting is selected; which sets GCP_COLOR_INDICATION. When we change > > > > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which > > > > doesn't allow the switch back to 8 bit color. > > > > > > > > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville) > > > > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc. > > > > > > > > Drop the changes in intel_hdmi_compute_config as desired_bpp > > > > is needed to change values for pipe_bpp based on bw_constrained flag. > > > > > > > > v5: Fix missing logical && in condition for setting > > > > GCP_COLOR_INDICATION. > > > > > > > > v6: Fix comment formatting (Ville) > > > > > > > > v7: Add reviewed by Ville > > > > > > > > Signed-off-by: Clinton Taylor > > > > Signed-off-by: Aditya Swarup > > > > Cc: Ville Syrjälä > > > > Cc: Jani Nikula > > > > Cc: Manasi Navare > > > > Reviewed-by: Ville Syrjälä > > > > --- > > > > drivers/gpu/drm/i915/intel_hdmi.c | 7 +-- > > > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > > > > b/drivers/gpu/drm/i915/intel_hdmi.c > > > > index 5ccb305a6e1c..f2c0aba4371b 100644 > > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c > > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > > > > @@ -962,8 +962,11 @@ static void > > > > intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, > > > > crtc_state->infoframes.enable |= > > > > > > > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); > > > > > > > > - /* Indicate color depth whenever the sink supports deep color */ > > > > - if (hdmi_sink_is_deep_color(conn_state)) > > > > + /* Indicate color depth whenever the sink supports deep color > > > > +* Also, 8bpc + color depth indication is no longer supported > > > > +* for HSW+ platforms. > > > > +*/ > > > > > > Frankly the comment confuses me as the condition has nothing to do with > > > HSW+ and applies for pre-HSW as well. And the "whenever" in the first > > > line is no longer true. > > > > You are correct, Clint and me spent time investigating this Spec/HW > > monstrosity for the correct conditions required for sending > > GCP_COLOR_INDICATION. > > > > > > > > I do understand the point here, we don't need to use color indication > > > when we're not using deep color anyway, and moreover this combo isn't > > > supported on HSW+. > > > > > > The final question is, under what circumstances would we use pipe_bpp > > > > 24 when the sink does *not* support bpc > 8? > > > > > > IOW, could we simply use > > > > > > if (crtc_state->pipe_bpp > 24) > > > > > > here? > > No we do need the check for sink, as that is the real check for > > determining whether sink supports deep color or not. For some platforms, > > we do send GCP_COLOR_INDICATION even for 8 bpc when the sink supports > > deep color. This will be clear with the next version of the patch. > > I think Jani is right. pipe_bpp will not be > 24 unless the sink support > deep color. I have described why we need the check for sink on the next revision of the patch. > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > > From: Clinton Taylor
> > >
> > > v2: Fix commit msg to reflect why issue occurs(Jani)
> > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
> > >
> > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> > > doesn't work correctly using xrandr max bpc property. When we
> > > connect a monitor which supports deep color, the highest deep color
> > > setting is selected; which sets GCP_COLOR_INDICATION. When we change
> > > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> > > doesn't allow the switch back to 8 bit color.
> > >
> > > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville)
> > > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
> > >
> > > Drop the changes in intel_hdmi_compute_config as desired_bpp
> > > is needed to change values for pipe_bpp based on bw_constrained flag.
> > >
> > > v5: Fix missing logical && in condition for setting GCP_COLOR_INDICATION.
> > >
> > > v6: Fix comment formatting (Ville)
> > >
> > > v7: Add reviewed by Ville
> > >
> > > v8: Set GCP_COLOR_INDICATION based on spec:
> > > For Gen 7.5 or later platforms, indicate color depth only for deep
> > > color modes. Bspec: 8135,7751,50524
> > >
> > > Pre DDI platforms, indicate color depth if deep color is supported
> > > by sink. Bspec: 7854
> > >
> > > Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > Bspec: 15975
> > >
> > > Check pipe_bpp is less than bpp * 3 in hdmi_deep_color_possible,
> > > to not set 12 bit deep color for every modeset. This fixes the issue
> > > where 12 bit color was selected even when user selected 10 bit.(Ville)
> > >
> > > Co-Developed-by: Aditya Swarup
> > > Co-Developed-by: Ville Syrjälä
> > > Signed-off-by: Clinton Taylor
> > > Signed-off-by: Aditya Swarup
> > > Cc: Ville Syrjälä
> > > Cc: Jani Nikula
> > > Cc: Manasi Navare
> > > Reviewed-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/intel_hdmi.c | 17 +
> > > 1 file changed, 13 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index e1005d7b75fd..620bc89e2120 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -973,9 +973,18 @@ static void intel_hdmi_compute_gcp_infoframe(struct
> > > intel_encoder *encoder,
> > > crtc_state->infoframes.enable |=
> > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
> > >
> > > - /* Indicate color depth whenever the sink supports deep color */
> > > - if (hdmi_sink_is_deep_color(conn_state))
> > > - crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > > + /* Indicate color depth whenever the sink supports deep color:
> > > + * For Gen 7.5 or later platforms, indicate color depth only for deep
> > > + * color modes.
> > > + * Pre DDI platforms, indicate color depth if deep color is supported
> > > + * by sink.
> > > + * Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > + */
> > > + if (hdmi_sink_is_deep_color(conn_state)) {
> > > + if(!HAS_DDI(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > > +crtc_state->pipe_bpp > 24)
> >
> > I prefer the earlier version. Less special casing.
> Then we won't be following spec for pre DDI platforms and CHV. These
> conditions are required according to Bspec pages mentioned in the commit
> message.
>
> Also, hdmi_sink_is_deep_color check is required for pre DDI platforms,
> since we send GCP_COLOR_INDICATION for 24 bit color as long as display
> supports deep color.
We don't have to send it for 24bpp even if the old hw supports doing so.
Well, the HDMI spec does say
"Once a Source sends a GCP with non-zero CD to a sink, it should
continue sending GCPs with non-zero CD at least once per video
field even if reverting to 24-bit color, as long as the Sink
continues to support Deep Color."
so I guess we should maybe send it? But maybe that only applies if
we would swich the color deph without a full modeset (can't really
see how that would work in the first place considering the symbol
clock needs to be adjusted too).
Anyways, I think it's better to just stick to a uniform behaviour
across all platforms here.
> >
> > > + crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > > + }
> > >
> > > /* Enable default_phase whenever the display mode is suitably aligned */
> > > if (gcp_default_phase_possible(crtc_state->pipe_bpp,
> > > @@ -2172,7 +2181,7 @@ static bool hdmi_deep_color_possible(const struct
> > > intel_crtc_state *crtc_state,
> > > if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
> > > return false;
> > >
> > > - if (crtc_state->pipe_bpp <= 8*3)
> > > + if (crtc_state->pipe_bpp < bpc*3
Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > > > From: Clinton Taylor
> > > >
> > > > v2: Fix commit msg to reflect why issue occurs(Jani)
> > > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
> > > >
> > > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> > > > doesn't work correctly using xrandr max bpc property. When we
> > > > connect a monitor which supports deep color, the highest deep color
> > > > setting is selected; which sets GCP_COLOR_INDICATION. When we change
> > > > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> > > > doesn't allow the switch back to 8 bit color.
> > > >
> > > > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville)
> > > > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
> > > >
> > > > Drop the changes in intel_hdmi_compute_config as desired_bpp
> > > > is needed to change values for pipe_bpp based on bw_constrained flag.
> > > >
> > > > v5: Fix missing logical && in condition for setting
> > > > GCP_COLOR_INDICATION.
> > > >
> > > > v6: Fix comment formatting (Ville)
> > > >
> > > > v7: Add reviewed by Ville
> > > >
> > > > v8: Set GCP_COLOR_INDICATION based on spec:
> > > > For Gen 7.5 or later platforms, indicate color depth only for deep
> > > > color modes. Bspec: 8135,7751,50524
> > > >
> > > > Pre DDI platforms, indicate color depth if deep color is supported
> > > > by sink. Bspec: 7854
> > > >
> > > > Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > > Bspec: 15975
> > > >
> > > > Check pipe_bpp is less than bpp * 3 in hdmi_deep_color_possible,
> > > > to not set 12 bit deep color for every modeset. This fixes the issue
> > > > where 12 bit color was selected even when user selected 10 bit.(Ville)
> > > >
> > > > Co-Developed-by: Aditya Swarup
> > > > Co-Developed-by: Ville Syrjälä
> > > > Signed-off-by: Clinton Taylor
> > > > Signed-off-by: Aditya Swarup
> > > > Cc: Ville Syrjälä
> > > > Cc: Jani Nikula
> > > > Cc: Manasi Navare
> > > > Reviewed-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/i915/intel_hdmi.c | 17 +
> > > > 1 file changed, 13 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > index e1005d7b75fd..620bc89e2120 100644
> > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > @@ -973,9 +973,18 @@ static void
> > > > intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
> > > > crtc_state->infoframes.enable |=
> > > >
> > > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
> > > >
> > > > - /* Indicate color depth whenever the sink supports deep color */
> > > > - if (hdmi_sink_is_deep_color(conn_state))
> > > > - crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > > > + /* Indicate color depth whenever the sink supports deep color:
> > > > +* For Gen 7.5 or later platforms, indicate color depth only
> > > > for deep
> > > > +* color modes.
> > > > +* Pre DDI platforms, indicate color depth if deep color is
> > > > supported
> > > > +* by sink.
> > > > +* Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > > +*/
> > > > + if (hdmi_sink_is_deep_color(conn_state)) {
> > > > + if(!HAS_DDI(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > > > + crtc_state->pipe_bpp > 24)
> > >
> > > I prefer the earlier version. Less special casing.
> > Then we won't be following spec for pre DDI platforms and CHV. These
> > conditions are required according to Bspec pages mentioned in the commit
> > message.
> >
> > Also, hdmi_sink_is_deep_color check is required for pre DDI platforms,
> > since we send GCP_COLOR_INDICATION for 24 bit color as long as display
> > supports deep color.
>
> We don't have to send it for 24bpp even if the old hw supports doing so.
>
> Well, the HDMI spec does say
> "Once a Source sends a GCP with non-zero CD to a sink, it should
> continue sending GCPs with non-zero CD at least once per video
> field even if reverting to 24-bit color, as long as the Sink
> continues to support Deep Color."
>
> so I guess we should maybe send it? But maybe that only applies if
> we would swich the color deph without a full modeset (can't really
> see how that would work in the first place considering the symbol
> clock needs to be adjusted too).
>
> Anyways, I think it's better to just stick to a uniform behaviour
> across all platforms here.
I don't have any problems with that but according to
Bspec: 7854
"This bit must be set when in deep color mode. It may optionally be
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32
== Series Details == Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32 URL : https://patchwork.freedesktop.org/series/60007/ State : success == Summary == CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12886 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/60007/revisions/1/mbox/ Changes --- No changes found Participating hosts (38 -> 21) -- Additional (1): fi-kbl-guc Missing(18): fi-ilk-m540 fi-bxt-dsi fi-skl-gvtdvm fi-byt-j1900 fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-skl-6260u fi-snb-2520m fi-kbl-7500u fi-kbl-x1275 fi-bxt-j4205 fi-cfl-8109u fi-bsw-kefka fi-skl-lmem fi-blb-e6850 fi-byt-n2820 fi-byt-clapper Build changes - * Linux: CI_DRM_6007 -> Patchwork_12886 CI_DRM_6007: 846376257e91f6e49cf7d6b59b0a6cbb0ce7cd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4968: caed251990f35bfe45368f803980071a73e36315 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12886: 134f19eee2761d15bf9502f8589384131f232328 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 134f19eee276 drm/i915/icl: Add Multi-segmented gamma support 9b3b15815c7b drm/i915/icl: Add register definitions for Multi Segmented gamma 4e85a5a0c432 drm/i915: Change gamma/degamma_lut_size data type to u32 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8] drm/i915/icl: Set GCP_COLOR_INDICATION only for 10/12 bit deep color
On Fri, Apr 26, 2019 at 11:53:54AM -0700, Aditya Swarup wrote:
> On Fri, Apr 26, 2019 at 09:41:06PM +0300, Ville Syrjälä wrote:
> > On Fri, Apr 26, 2019 at 11:22:02AM -0700, Aditya Swarup wrote:
> > > On Fri, Apr 26, 2019 at 01:14:44PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 25, 2019 at 06:19:50PM -0700, Aditya Swarup wrote:
> > > > > From: Clinton Taylor
> > > > >
> > > > > v2: Fix commit msg to reflect why issue occurs(Jani)
> > > > > Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
> > > > >
> > > > > Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> > > > > doesn't work correctly using xrandr max bpc property. When we
> > > > > connect a monitor which supports deep color, the highest deep color
> > > > > setting is selected; which sets GCP_COLOR_INDICATION. When we change
> > > > > the setting to 8 bit color, we still set GCP_COLOR_INDICATION which
> > > > > doesn't allow the switch back to 8 bit color.
> > > > >
> > > > > v3,4: Add comments & drop changes in intel_hdmi_compute_config(Ville)
> > > > > Since HSW+, GCP_COLOR_INDICATION is not required for 8bpc.
> > > > >
> > > > > Drop the changes in intel_hdmi_compute_config as desired_bpp
> > > > > is needed to change values for pipe_bpp based on bw_constrained flag.
> > > > >
> > > > > v5: Fix missing logical && in condition for setting
> > > > > GCP_COLOR_INDICATION.
> > > > >
> > > > > v6: Fix comment formatting (Ville)
> > > > >
> > > > > v7: Add reviewed by Ville
> > > > >
> > > > > v8: Set GCP_COLOR_INDICATION based on spec:
> > > > > For Gen 7.5 or later platforms, indicate color depth only for deep
> > > > > color modes. Bspec: 8135,7751,50524
> > > > >
> > > > > Pre DDI platforms, indicate color depth if deep color is supported
> > > > > by sink. Bspec: 7854
> > > > >
> > > > > Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > > > Bspec: 15975
> > > > >
> > > > > Check pipe_bpp is less than bpp * 3 in hdmi_deep_color_possible,
> > > > > to not set 12 bit deep color for every modeset. This fixes the issue
> > > > > where 12 bit color was selected even when user selected 10 bit.(Ville)
> > > > >
> > > > > Co-Developed-by: Aditya Swarup
> > > > > Co-Developed-by: Ville Syrjälä
> > > > > Signed-off-by: Clinton Taylor
> > > > > Signed-off-by: Aditya Swarup
> > > > > Cc: Ville Syrjälä
> > > > > Cc: Jani Nikula
> > > > > Cc: Manasi Navare
> > > > > Reviewed-by: Ville Syrjälä
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_hdmi.c | 17 +
> > > > > 1 file changed, 13 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > > b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > > index e1005d7b75fd..620bc89e2120 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > > > @@ -973,9 +973,18 @@ static void
> > > > > intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
> > > > > crtc_state->infoframes.enable |=
> > > > >
> > > > > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
> > > > >
> > > > > - /* Indicate color depth whenever the sink supports deep color */
> > > > > - if (hdmi_sink_is_deep_color(conn_state))
> > > > > - crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
> > > > > + /* Indicate color depth whenever the sink supports deep color:
> > > > > + * For Gen 7.5 or later platforms, indicate color depth only
> > > > > for deep
> > > > > + * color modes.
> > > > > + * Pre DDI platforms, indicate color depth if deep color is
> > > > > supported
> > > > > + * by sink.
> > > > > + * Exception: CHERRYVIEW behaves like Pre DDI platforms.
> > > > > + */
> > > > > + if (hdmi_sink_is_deep_color(conn_state)) {
> > > > > + if(!HAS_DDI(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > > > > +crtc_state->pipe_bpp > 24)
> > > >
> > > > I prefer the earlier version. Less special casing.
> > > Then we won't be following spec for pre DDI platforms and CHV. These
> > > conditions are required according to Bspec pages mentioned in the commit
> > > message.
> > >
> > > Also, hdmi_sink_is_deep_color check is required for pre DDI platforms,
> > > since we send GCP_COLOR_INDICATION for 24 bit color as long as display
> > > supports deep color.
> >
> > We don't have to send it for 24bpp even if the old hw supports doing so.
> >
> > Well, the HDMI spec does say
> > "Once a Source sends a GCP with non-zero CD to a sink, it should
> > continue sending GCPs with non-zero CD at least once per video
> > field even if reverting to 24-bit color, as long as the Sink
> > continues to support Deep Color."
> >
> > so I guess we should maybe send it? But maybe that only applies if
> > we would swich the color deph without a full modeset (can't really
> > see how that would work in the first place considering the symbol
> > clock needs to be adjusted too
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking
== Series Details == Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60008/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Flush the tasklet on parking Okay! Commit: drm/i915: Move the engine->destroy() vfunc onto the engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3564:16: warning: expression using sizeof(void) Commit: drm/i915: Convert inconsistent static engine tables into an init error Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking
== Series Details == Series: series starting with [1/3] drm/i915/execlists: Flush the tasklet on parking URL : https://patchwork.freedesktop.org/series/60008/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12887 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12887 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12887, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/60008/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12887: ### IGT changes ### Possible regressions * igt@gem_ctx_create@basic-files: - fi-skl-6260u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-skl-6260u/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-skl-6260u/igt@gem_ctx_cre...@basic-files.html - fi-ilk-650: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-ilk-650/igt@gem_ctx_cre...@basic-files.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-ilk-650/igt@gem_ctx_cre...@basic-files.html - fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-bdw-5557u/igt@gem_ctx_cre...@basic-files.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-bdw-5557u/igt@gem_ctx_cre...@basic-files.html Known issues Here are the changes found in Patchwork_12887 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-elk-e7500: [PASS][7] -> [INCOMPLETE][8] ([fdo#103989]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-elk-e7500/igt@gem_ctx_cre...@basic-files.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-elk-e7500/igt@gem_ctx_cre...@basic-files.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: [PASS][9] -> [FAIL][10] ([fdo#103191]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-byt-clapper/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-byt-clapper/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: [FAIL][11] ([fdo#103167]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-byt-clapper/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/fi-byt-clapper/igt@kms_frontbuffer_track...@basic.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103989]: https://bugs.freedesktop.org/show_bug.cgi?id=103989 Participating hosts (38 -> 25) -- Missing(13): fi-ilk-m540 fi-skl-guc fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-snb-2520m fi-whl-u fi-kbl-x1275 fi-cfl-8109u fi-skl-iommu fi-skl-lmem fi-skl-6700k2 Build changes - * Linux: CI_DRM_6007 -> Patchwork_12887 CI_DRM_6007: 846376257e91f6e49cf7d6b59b0a6cbb0ce7cd53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4968: caed251990f35bfe45368f803980071a73e36315 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12887: 7fe1de21e49b0507eaa34ee5ad239943537697b2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7fe1de21e49b drm/i915: Convert inconsistent static engine tables into an init error 90ea6e349760 drm/i915: Move the engine->destroy() vfunc onto the engine 63dc38684fd3 drm/i915/execlists: Flush the tasklet on parking == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12887/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Expand subslice mask
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: fix spacing in set_sseu_info args
use set_sseu_info to initialize sseu data when building
device status in debugfs
rename variables in intel_engine_types.h to avoid checkpatch
warnings
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.h | 44 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 43 +++---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c| 5 +-
drivers/gpu/drm/i915/i915_query.c| 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 139 +++
10 files changed, 182 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f7308479d511..8922358ee6c6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -908,7 +908,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private
*dev_priv)
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 mcr_s_ss_select;
u32 slice = fls(sseu->slice_mask);
- u32 subslice = fls(sseu->subslice_mask[slice]);
+ u32 subslice = fls(sseu->subslice_mask[slice * sseu->ss_stride]);
if (IS_GEN(dev_priv, 10))
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
@@ -984,6 +984,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *dev_priv = engine->i915;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -1001,7 +1002,8 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice,
+subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(dev_priv, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index d972c339309c..fa70528963a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -534,20 +534,22 @@ intel_engine_needs_breadcrumb_tasklet(const struct
intel_engine_cs *engine)
return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
-1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
-(slice__) < I915_MAX_SLICES; \
-(subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ?
(subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) &&
\
- (BIT(subslice__) &
instdone_subslice_mask(dev_priv__)))
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? \
+ 1 : (sseu___)->slice_mask) & \
+ BIT(slice___)) \
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ ((IS_GEN(dev_priv__, 7) ? \
+ 1 : (sseu__)->subslice_mask[slice__ * (sseu__)->ss_stride + \
+ subslice__ / BITS_PER_BYTE]) & \
+BIT(subslice__ % BITS_PER_BYTE)) \
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+(subslice_) = ((subslice_) + 1) < I915_MAX_SUBSLICES ? (subslice_)
+ 1 : 0, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if(instdone_has_slice(dev_priv_, sseu_, slice) && \
+ instdone_has_subslice(d
[Intel-gfx] [PATCH 0/5] Refactor to expand subslice mask
This patch series contains a few code clean-up patches, followed by a patch which changes the storage of the subslice mask to better match the userspace access through the I915_QUERY_TOPOLOGY_INFO ioctl. The index into the subslice_mask array is then calculated: slice * subslice stride + subslice index / 8 v2: fix i915_pm_sseu test failure v3: no changes to patches in the series, just resending to pick up in CI correctly v4: rebase Stuart Summers (5): drm/i915: Use local variable for SSEU info in GETPARAM ioctl drm/i915: Add macro for SSEU stride calculation drm/i915: Move calculation of subslices per slice to new function drm/i915: Move sseu helper functions to intel_sseu.h drm/i915: Expand subslice mask drivers/gpu/drm/i915/gt/intel_engine_cs.c| 6 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 32 +++-- drivers/gpu/drm/i915/gt/intel_hangcheck.c| 3 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 96 - drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 45 +++--- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_gpu_error.c| 5 +- drivers/gpu/drm/i915/i915_query.c| 15 +- drivers/gpu/drm/i915/intel_device_info.c | 143 +++ drivers/gpu/drm/i915/intel_device_info.h | 47 -- 11 files changed, 245 insertions(+), 164 deletions(-) -- 2.21.0.5.gaeb582a983 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Move calculation of subslices per slice to new function
Add a new function to return the number of subslices per slice to
consolidate code usage.
v2: rebase on changes to move sseu struct to intel_sseu.h
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 6 ++
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 4 ++--
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2cbf0981b44f..b553d7280f35 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -62,6 +62,12 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline unsigned int
+sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+{
+ return hweight8(sseu->subslice_mask[slice]);
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index ffbf5d920429..0ecf006d26b3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4184,7 +4184,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool
is_available_info,
sseu_subslice_total(sseu));
for (s = 0; s < fls(sseu->slice_mask); s++) {
seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, hweight8(sseu->subslice_mask[s]));
+ s, sseu_subslices_per_slice(sseu, s));
}
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 6af480b95bc6..559cf0d0628e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,7 +93,7 @@ static void sseu_dump(const struct sseu_dev_info *sseu,
struct drm_printer *p)
drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
@@ -126,7 +126,7 @@ void intel_device_info_dump_topology(const struct
sseu_dev_info *sseu,
for (s = 0; s < sseu->max_slices; s++) {
drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
- s, hweight8(sseu->subslice_mask[s]),
+ s, sseu_subslices_per_slice(sseu, s),
sseu->subslice_mask[s]);
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.21.0.5.gaeb582a983
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915: Add macro for SSEU stride calculation
Subslice stride and EU stride are calculated multiple times in
i915_query. Move this calculation to a macro to reduce code duplication.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
drivers/gpu/drm/i915/i915_query.c| 17 -
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 73bc824094e8..2cbf0981b44f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
+#define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE)
struct sseu_dev_info {
u8 slice_mask;
diff --git a/drivers/gpu/drm/i915/i915_query.c
b/drivers/gpu/drm/i915/i915_query.c
index 782183b78f49..7c1708c22811 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,6 +37,8 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -48,12 +50,10 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices *
- DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
- eu_length = sseu->max_slices * sseu->max_subslices *
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
-
- total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
+ subslice_length = sseu->max_slices * subslice_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ total_length = sizeof(topo) + slice_length + subslice_length +
+ eu_length;
ret = copy_query_item(&topo, sizeof(topo), total_length,
query_item);
@@ -69,10 +69,9 @@ static int query_topology_info(struct drm_i915_private
*dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = DIV_ROUND_UP(sseu->max_subslices, BITS_PER_BYTE);
+ topo.subslice_stride = subslice_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride =
- DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+ topo.eu_stride = eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
--
2.21.0.5.gaeb582a983
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/5] drm/i915: Use local variable for SSEU info in GETPARAM ioctl
In the GETPARAM ioctl handler, use a local variable to consolidate
usage of SSEU runtime info.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aacc8dd6ecfd..b6ce7580d414 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -321,6 +321,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
+ struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
drm_i915_getparam_t *param = data;
int value;
@@ -374,12 +375,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(sseu);
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
+ value = sseu->eu_total;
if (!value)
return -ENODEV;
break;
@@ -396,7 +397,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
value = intel_huc_check_status(&dev_priv->huc);
@@ -446,12 +447,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
+ value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
+ value = sseu->subslice_mask[0];
if (!value)
return -ENODEV;
break;
--
2.21.0.5.gaeb582a983
___
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[Intel-gfx] [PATCH 4/5] drm/i915: Move sseu helper functions to intel_sseu.h
Signed-off-by: Stuart Summers
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 47
drivers/gpu/drm/i915/intel_device_info.h | 47
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b553d7280f35..0dfbed547da5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -62,12 +62,59 @@ intel_sseu_from_device_info(const struct sseu_dev_info
*sseu)
return value;
}
+static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
+{
+ unsigned int i, total = 0;
+
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+ total += hweight8(sseu->subslice_mask[i]);
+
+ return total;
+}
+
static inline unsigned int
sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
return hweight8(sseu->subslice_mask[slice]);
}
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+ BITS_PER_BYTE);
+ int slice_stride = sseu->max_subslices * subslice_stride;
+
+ return slice * slice_stride + subslice * subslice_stride;
+}
+
+static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
+ int slice, int subslice)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+ u16 eu_mask = 0;
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
+ (i * BITS_PER_BYTE);
+ }
+
+ return eu_mask;
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+ int slice, int subslice, u16 eu_mask)
+{
+ int i, offset = sseu_eu_idx(sseu, slice, subslice);
+
+ for (i = 0;
+i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
+ sseu->eu_mask[offset + i] =
+ (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+}
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 5a2e17d6146b..6412a9c72898 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -218,53 +218,6 @@ struct intel_driver_caps {
bool has_logical_contexts:1;
};
-static inline unsigned int sseu_subslice_total(const struct sseu_dev_info
*sseu)
-{
- unsigned int i, total = 0;
-
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
- BITS_PER_BYTE);
- int slice_stride = sseu->max_subslices * subslice_stride;
-
- return slice * slice_stride + subslice * subslice_stride;
-}
-
-static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
- int slice, int subslice)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
- (i * BITS_PER_BYTE);
- }
-
- return eu_mask;
-}
-
-static inline void sseu_set_eus(struct sseu_dev_info *sseu,
- int slice, int subslice, u16 eu_mask)
-{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0;
-i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
- }
-}
-
const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
--
2.21.0.5.gaeb582a983
___
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Refactor to expand subslice mask (rev3)
== Series Details == Series: Refactor to expand subslice mask (rev3) URL : https://patchwork.freedesktop.org/series/59742/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC drivers/gpu/drm/i915/gt/header_test_intel_sseu.o In file included from drivers/gpu/drm/i915/gt/header_test_intel_sseu.c:1:0: drivers/gpu/drm/i915/gt/intel_sseu.h:16:31: error: implicit declaration of function ‘DIV_ROUND_UP’ [-Werror=implicit-function-declaration] #define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE) ^ drivers/gpu/drm/i915/gt/intel_sseu.h:17:33: note: in expansion of macro ‘GEN_SSEU_STRIDE’ #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) ^~~ drivers/gpu/drm/i915/gt/intel_sseu.h:21:36: note: in expansion of macro ‘GEN_MAX_SUBSLICE_STRIDE’ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; ^~~ drivers/gpu/drm/i915/gt/intel_sseu.h:16:50: error: ‘BITS_PER_BYTE’ undeclared here (not in a function); did you mean ‘BITS_PER_LONG’? #define GEN_SSEU_STRIDE(bits) DIV_ROUND_UP(bits, BITS_PER_BYTE) ^ drivers/gpu/drm/i915/gt/intel_sseu.h:17:33: note: in expansion of macro ‘GEN_SSEU_STRIDE’ #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) ^~~ drivers/gpu/drm/i915/gt/intel_sseu.h:21:36: note: in expansion of macro ‘GEN_MAX_SUBSLICE_STRIDE’ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; ^~~ drivers/gpu/drm/i915/gt/intel_sseu.h: In function ‘sseu_subslice_total’: drivers/gpu/drm/i915/gt/intel_sseu.h:84:18: error: implicit declaration of function ‘ARRAY_SIZE’ [-Werror=implicit-function-declaration] for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) ^~ drivers/gpu/drm/i915/gt/intel_sseu.h:85:12: error: implicit declaration of function ‘hweight8’ [-Werror=implicit-function-declaration] total += hweight8(sseu->subslice_mask[i]); ^~~~ drivers/gpu/drm/i915/gt/intel_sseu.h: In function ‘sseu_copy_subslices’: drivers/gpu/drm/i915/gt/intel_sseu.h:108:2: error: implicit declaration of function ‘memcpy’ [-Werror=implicit-function-declaration] memcpy(&to_mask[offset], &from_mask[offset], sseu->ss_stride); ^~ drivers/gpu/drm/i915/gt/intel_sseu.h:108:2: error: incompatible implicit declaration of built-in function ‘memcpy’ [-Werror] drivers/gpu/drm/i915/gt/intel_sseu.h:108:2: note: include ‘’ or provide a declaration of ‘memcpy’ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'drivers/gpu/drm/i915/gt/header_test_intel_sseu.o' failed make[5]: *** [drivers/gpu/drm/i915/gt/header_test_intel_sseu.o] Error 1 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm/i915/gt' failed make[4]: *** [drivers/gpu/drm/i915/gt] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:486: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1051: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: add in-kernel blitter client
The plan is to use the blitter engine for async object clearing when
using local memory, but before we can move the worker to get_pages() we
have to first tame some more of our struct_mutex usage. With this in
mind we should be able to upstream the object clearing as some
selftests, which should serve as a guinea pig for the ongoing locking
rework and upcoming asyc get_pages() framework.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_client_blt.c| 186 ++
drivers/gpu/drm/i915/i915_gem_client_blt.h| 21 ++
drivers/gpu/drm/i915/i915_gem_object_blt.c| 91 +
drivers/gpu/drm/i915/i915_gem_object_blt.h| 23 +++
.../drm/i915/selftests/i915_gem_client_blt.c | 123
.../drm/i915/selftests/i915_gem_object_blt.c | 111 +++
.../drm/i915/selftests/i915_live_selftests.h | 2 +
11 files changed, 564 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_client_blt.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_client_blt.h
create mode 100644 drivers/gpu/drm/i915/i915_gem_object_blt.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_object_blt.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_client_blt.c
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_object_blt.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 58643373495c..fc123221304e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -90,6 +90,7 @@ i915-y += \
i915_cmd_parser.o \
i915_gem_batch_pool.o \
i915_gem_clflush.o \
+ i915_gem_client_blt.o \
i915_gem_context.o \
i915_gem_dmabuf.o \
i915_gem_evict.o \
@@ -99,6 +100,7 @@ i915-y += \
i915_gem_internal.o \
i915_gem.o \
i915_gem_object.o \
+ i915_gem_object_blt.o \
i915_gem_pm.o \
i915_gem_render_state.o \
i915_gem_shrinker.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index a34ece53a771..7e95827b0726 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -180,6 +180,7 @@
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
+#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22)
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
#define XY_SRC_COPY_BLT_CMD((2<<29)|(0x53<<22)|6)
#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1cea98f8b85c..61f95391edf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2945,6 +2945,9 @@ dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
unsigned long n);
+struct sg_table *
+__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj);
+
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
struct sg_table *pages,
unsigned int sg_page_sizes);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4c1793b1012e..65b6d7b7b624 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2121,7 +2121,7 @@ static void __i915_gem_object_reset_page_iter(struct
drm_i915_gem_object *obj)
rcu_read_unlock();
}
-static struct sg_table *
+struct sg_table *
__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = to_i915(obj->base.dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_client_blt.c
b/drivers/gpu/drm/i915/i915_gem_client_blt.c
new file mode 100644
index ..7fd977d54b57
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_client_blt.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+#include "i915_gem_client_blt.h"
+
+#include "i915_gem_object_blt.h"
+#include "intel_drv.h"
+
+static struct drm_i915_gem_object *
+create_sleeve(struct drm_i915_private *i915,
+ struct sg_table *pages,
+ unsigned int page_sizes,
+ u64 size)
+{
+ struct drm_i915_gem_object *sleeve;
+
+ /* XXX: sketchy af */
+ sleeve = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(sleeve))
+ return sleeve;
+
+ mutex_lock(&sleeve->mm.lock);
+
+ atomic_inc(&sleeve->mm.pages_pin_count);
+ __i915_gem_object_set_pages(sleeve, pages, page_sizes);
+
+ mutex_unlock(&sleeve->mm.lock);
+
+ return sleeve;
+}
+
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add in-kernel blitter client
== Series Details ==
Series: drm/i915: add in-kernel blitter client
URL : https://patchwork.freedesktop.org/series/60017/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
658ea31e573a drm/i915: add in-kernel blitter client
-:43: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:183:
+#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22)
^
-:43: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:183:
+#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22)
^
-:75: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#75:
new file mode 100644
-:228: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!work"
#228: FILE: drivers/gpu/drm/i915/i915_gem_client_blt.c:149:
+ if (work == NULL) {
-:328: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#328: FILE: drivers/gpu/drm/i915/i915_gem_object_blt.c:30:
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7-2);
^
-:337: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#337: FILE: drivers/gpu/drm/i915/i915_gem_object_blt.c:39:
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6-2);
^
-:441: WARNING:LINE_SPACING: Missing a blank line after declarations
#441: FILE: drivers/gpu/drm/i915/selftests/i915_gem_client_blt.c:17:
+ struct rnd_state prng;
+ IGT_TIMEOUT(end);
-:570: WARNING:LINE_SPACING: Missing a blank line after declarations
#570: FILE: drivers/gpu/drm/i915/selftests/i915_gem_object_blt.c:17:
+ struct rnd_state prng;
+ IGT_TIMEOUT(end);
total: 0 errors, 3 warnings, 5 checks, 601 lines checked
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add in-kernel blitter client
== Series Details == Series: drm/i915: add in-kernel blitter client URL : https://patchwork.freedesktop.org/series/60017/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: add in-kernel blitter client +drivers/gpu/drm/i915/i915_gem_client_blt.h:11:22: warning: symbol 'ce' was not declared. Should it be static? -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3573:16: warning: expression using sizeof(void) +./include/linux/reservation.h:220:20: warning: dereference of noderef expression +./include/linux/reservation.h:220:45: warning: dereference of noderef expression +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: add in-kernel blitter client
Quoting Matthew Auld (2019-04-26 23:17:05)
> The plan is to use the blitter engine for async object clearing when
> using local memory, but before we can move the worker to get_pages() we
> have to first tame some more of our struct_mutex usage. With this in
> mind we should be able to upstream the object clearing as some
> selftests, which should serve as a guinea pig for the ongoing locking
> rework and upcoming asyc get_pages() framework.
>
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_client_blt.c| 186 ++
> drivers/gpu/drm/i915/i915_gem_client_blt.h| 21 ++
> drivers/gpu/drm/i915/i915_gem_object_blt.c| 91 +
> drivers/gpu/drm/i915/i915_gem_object_blt.h| 23 +++
> .../drm/i915/selftests/i915_gem_client_blt.c | 123
> .../drm/i915/selftests/i915_gem_object_blt.c | 111 +++
> .../drm/i915/selftests/i915_live_selftests.h | 2 +
> 11 files changed, 564 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/i915_gem_client_blt.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_client_blt.h
> create mode 100644 drivers/gpu/drm/i915/i915_gem_object_blt.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_object_blt.h
> create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_client_blt.c
> create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_object_blt.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 58643373495c..fc123221304e 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -90,6 +90,7 @@ i915-y += \
> i915_cmd_parser.o \
> i915_gem_batch_pool.o \
> i915_gem_clflush.o \
> + i915_gem_client_blt.o \
> i915_gem_context.o \
> i915_gem_dmabuf.o \
> i915_gem_evict.o \
> @@ -99,6 +100,7 @@ i915-y += \
> i915_gem_internal.o \
> i915_gem.o \
> i915_gem_object.o \
> + i915_gem_object_blt.o \
> i915_gem_pm.o \
> i915_gem_render_state.o \
> i915_gem_shrinker.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index a34ece53a771..7e95827b0726 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -180,6 +180,7 @@
> #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
>
> #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
> +#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22)
> #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
> #define XY_SRC_COPY_BLT_CMD((2<<29)|(0x53<<22)|6)
> #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1cea98f8b85c..61f95391edf0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2945,6 +2945,9 @@ dma_addr_t
> i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
> unsigned long n);
>
> +struct sg_table *
> +__i915_gem_object_unset_pages(struct drm_i915_gem_object *obj);
> +
> void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
> struct sg_table *pages,
> unsigned int sg_page_sizes);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4c1793b1012e..65b6d7b7b624 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2121,7 +2121,7 @@ static void __i915_gem_object_reset_page_iter(struct
> drm_i915_gem_object *obj)
> rcu_read_unlock();
> }
>
> -static struct sg_table *
> +struct sg_table *
> __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
> {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_client_blt.c
> b/drivers/gpu/drm/i915/i915_gem_client_blt.c
> new file mode 100644
> index ..7fd977d54b57
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_gem_client_blt.c
> @@ -0,0 +1,186 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +#include "i915_gem_client_blt.h"
> +
> +#include "i915_gem_object_blt.h"
> +#include "intel_drv.h"
> +
> +static struct drm_i915_gem_object *
> +create_sleeve(struct drm_i915_private *i915,
> + struct sg_table *pages,
> + unsigned int page_sizes,
> + u64 size)
> +{
> + struct drm_i915_gem_object *sleeve;
> +
> + /* XXX: sketchy af */
> + sleeve = i915_gem_object_create_internal(i915, size);
> + if
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: add in-kernel blitter client
== Series Details ==
Series: drm/i915: add in-kernel blitter client
URL : https://patchwork.freedesktop.org/series/60017/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6007 -> Patchwork_12889
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12889 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12889, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/60017/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12889:
### IGT changes ###
Possible regressions
* igt@gem_exec_create@basic:
- fi-kbl-7567u: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-kbl-7567u/igt@gem_exec_cre...@basic.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-kbl-7567u/igt@gem_exec_cre...@basic.html
* igt@gem_exec_fence@nb-await-default:
- fi-kbl-x1275: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/fi-kbl-x1275/igt@gem_exec_fe...@nb-await-default.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-kbl-x1275/igt@gem_exec_fe...@nb-await-default.html
* {igt@i915_selftest@live_blt} (NEW):
- fi-bxt-j4205: NOTRUN -> [DMESG-WARN][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bxt-j4205/igt@i915_selftest@live_blt.html
- fi-whl-u: NOTRUN -> [DMESG-WARN][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-whl-u/igt@i915_selftest@live_blt.html
- fi-bdw-5557u: NOTRUN -> [DMESG-WARN][7]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bdw-5557u/igt@i915_selftest@live_blt.html
- fi-icl-u3: NOTRUN -> [DMESG-WARN][8]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-icl-u3/igt@i915_selftest@live_blt.html
- {fi-cml-u}: NOTRUN -> [DMESG-WARN][9]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-cml-u/igt@i915_selftest@live_blt.html
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][10]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-cfl-8109u/igt@i915_selftest@live_blt.html
- fi-skl-lmem:NOTRUN -> [DMESG-WARN][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-skl-lmem/igt@i915_selftest@live_blt.html
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][12]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-kbl-8809g/igt@i915_selftest@live_blt.html
- fi-hsw-4770r: NOTRUN -> [DMESG-WARN][13]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-hsw-4770r/igt@i915_selftest@live_blt.html
- fi-hsw-peppy: NOTRUN -> [DMESG-WARN][14]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-hsw-peppy/igt@i915_selftest@live_blt.html
- fi-skl-6600u: NOTRUN -> [DMESG-WARN][15]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-skl-6600u/igt@i915_selftest@live_blt.html
- fi-bdw-gvtdvm: NOTRUN -> [DMESG-WARN][16]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bdw-gvtdvm/igt@i915_selftest@live_blt.html
- fi-skl-gvtdvm: NOTRUN -> [DMESG-WARN][17]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-skl-gvtdvm/igt@i915_selftest@live_blt.html
- fi-skl-6260u: NOTRUN -> [DMESG-WARN][18]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-skl-6260u/igt@i915_selftest@live_blt.html
* igt@runner@aborted:
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][19]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-hsw-4770r: NOTRUN -> [FAIL][20]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-hsw-4770r/igt@run...@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][21]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-cfl-8109u/igt@run...@aborted.html
- fi-hsw-peppy: NOTRUN -> [FAIL][22]
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-hsw-peppy/igt@run...@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][23]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-kbl-8809g/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][24]
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bdw-5557u/igt@run...@aborted.html
- fi-bxt-j4205: NOTRUN -> [FAIL][25]
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12889/fi-bxt-j4205/igt@run...@aborted.html
- fi-whl-u: NOTRUN -> [FAIL][26]
[26]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32
== Series Details == Series: series starting with [1/3] drm/i915: Change gamma/degamma_lut_size data type to u32 URL : https://patchwork.freedesktop.org/series/60007/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6007_full -> Patchwork_12886_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12886_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12886_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12886_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock_requests: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-skl6/igt@i915_selftest@mock_requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-skl2/igt@i915_selftest@mock_requests.html * igt@kms_color@pipe-a-ctm-0-5: - shard-iclb: [PASS][3] -> [FAIL][4] +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-iclb6/igt@kms_co...@pipe-a-ctm-0-5.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-iclb7/igt@kms_co...@pipe-a-ctm-0-5.html * igt@runner@aborted: - shard-snb: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-snb2/igt@run...@aborted.html Known issues Here are the changes found in Patchwork_12886_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-apl: [PASS][6] -> [DMESG-WARN][7] ([fdo#108566]) +4 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-apl6/igt@gem_ctx_isolat...@bcs0-s3.html * igt@kms_cursor_legacy@all-pipes-forked-bo: - shard-apl: [PASS][8] -> [INCOMPLETE][9] ([fdo#103927]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-apl7/igt@kms_cursor_leg...@all-pipes-forked-bo.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-apl7/igt@kms_cursor_leg...@all-pipes-forked-bo.html * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#109349]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-iclb2/igt@kms_dp_...@basic-dsc-enable-edp.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-iclb3/igt@kms_dp_...@basic-dsc-enable-edp.html * igt@kms_flip@flip-vs-modeset-interruptible: - shard-hsw: [PASS][12] -> [DMESG-WARN][13] ([fdo#102614]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-hsw5/igt@kms_f...@flip-vs-modeset-interruptible.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-hsw5/igt@kms_f...@flip-vs-modeset-interruptible.html * igt@kms_flip@flip-vs-suspend: - shard-hsw: [PASS][14] -> [INCOMPLETE][15] ([fdo#103540]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-hsw6/igt@kms_f...@flip-vs-suspend.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-hsw8/igt@kms_f...@flip-vs-suspend.html - shard-skl: [PASS][16] -> [INCOMPLETE][17] ([fdo#109507]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-skl9/igt@kms_f...@flip-vs-suspend.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-skl3/igt@kms_f...@flip-vs-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][18] -> [FAIL][19] ([fdo#103167]) +6 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-iclb5/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103166]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#109441]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6007/shard-iclb2/igt@kms_psr@psr2_no_drrs.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12886/shard-iclb1/igt@kms_psr@psr2_no_dr
