[Intel-gfx] [PATCH 16/30] drm/i915/guc: Define GuC firmware version for Icelake
Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index c937a648c2a1..c88a089885a0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -55,9 +55,16 @@
#define KBL_GUC_FW_PATCH 3
#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+#define ICL_GUC_FW_PREFIX icl
+#define ICL_GUC_FW_MAJOR 32
+#define ICL_GUC_FW_MINOR 0
+#define ICL_GUC_FW_PATCH 3
+#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
+
MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
@@ -73,6 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
+ } else if (IS_ICELAKE(i915)) {
+ guc_fw->path = ICL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
guc_fw->path = KBL_GUC_FIRMWARE_PATH;
guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
--
2.19.2
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[Intel-gfx] [PATCH 03/30] drm/i915/guc: Update GuC firmware versions and names
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
---
drivers/gpu/drm/i915/intel_guc_fw.c | 76 -
1 file changed, 42 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
b/drivers/gpu/drm/i915/intel_guc_fw.c
index 792a551450c7..c937a648c2a1 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -30,53 +30,61 @@
#include "intel_guc_fw.h"
#include "i915_drv.h"
-#define SKL_FW_MAJOR 9
-#define SKL_FW_MINOR 33
-
-#define BXT_FW_MAJOR 9
-#define BXT_FW_MINOR 29
-
-#define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 39
-
-#define GUC_FW_PATH(platform, major, minor) \
- "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_"
__stringify(minor) ".bin"
-
-#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
-MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
-
-#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
-MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
-
-#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
-MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+#define __MAKE_GUC_FW_PATH(KEY) \
+ "i915/" \
+ __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
+ __stringify(KEY##_GUC_FW_MAJOR) "." \
+ __stringify(KEY##_GUC_FW_MINOR) "." \
+ __stringify(KEY##_GUC_FW_PATCH) ".bin"
+
+#define SKL_GUC_FW_PREFIX skl
+#define SKL_GUC_FW_MAJOR 32
+#define SKL_GUC_FW_MINOR 0
+#define SKL_GUC_FW_PATCH 3
+#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
+
+#define BXT_GUC_FW_PREFIX bxt
+#define BXT_GUC_FW_MAJOR 32
+#define BXT_GUC_FW_MINOR 0
+#define BXT_GUC_FW_PATCH 3
+#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
+
+#define KBL_GUC_FW_PREFIX kbl
+#define KBL_GUC_FW_MAJOR 32
+#define KBL_GUC_FW_MINOR 0
+#define KBL_GUC_FW_PATCH 3
+#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
+
+MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
+MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_i915(guc);
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(dev_priv))
+ if (!HAS_GUC(i915))
return;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
guc_fw->major_ver_wanted = 0;
guc_fw->minor_ver_wanted = 0;
- } else if (IS_SKYLAKE(dev_priv)) {
- guc_fw->path = I915_SKL_GUC_UCODE;
- guc_fw->major_ver_wanted = SKL_FW_MAJOR;
- guc_fw->minor_ver_wanted = SKL_FW_MINOR;
- } else if (IS_BROXTON(dev_priv)) {
- guc_fw->path = I915_BXT_GUC_UCODE;
- guc_fw->major_ver_wanted = BXT_FW_MAJOR;
- guc_fw->minor_ver_wanted = BXT_FW_MINOR;
- } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
- guc_fw->path = I915_KBL_GUC_UCODE;
- guc_fw->major_ver_wanted = KBL_FW_MAJOR;
- guc_fw->minor_ver_wanted = KBL_FW_MINOR;
+ } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
+ guc_fw->path = KBL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
+ } else if (IS_BROXTON(i915)) {
+ guc_fw->path = BXT_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
+ } else if (IS_SKYLAKE(i915)) {
+ guc_fw->path = SKL_GUC_FIRMWARE_PATH;
+ guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
+ guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
}
}
--
2.19.2
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[Intel-gfx] [PATCH 17/30] drm/i915/huc: Define HuC firmware version for Icelake
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
b/drivers/gpu/drm/i915/intel_huc_fw.c
index 68d47c105939..b8e160dc4621 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -34,6 +34,10 @@
#define KBL_HUC_FW_MINOR 00
#define KBL_BLD_NUM 1810
+#define ICL_HUC_FW_MAJOR 8
+#define ICL_HUC_FW_MINOR 4
+#define ICL_BLD_NUM 3132
+
#define HUC_FW_PATH(platform, major, minor, bld_num) \
"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
__stringify(minor) "_" __stringify(bld_num) ".bin"
@@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
KBL_HUC_FW_MINOR, KBL_BLD_NUM)
MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
+#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
+ ICL_HUC_FW_MINOR, ICL_BLD_NUM)
+MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
+
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
@@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
huc_fw->path = I915_KBL_HUC_UCODE;
huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
+ } else if (IS_ICELAKE(dev_priv)) {
+ huc_fw->path = I915_ICL_HUC_UCODE;
+ huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
+ huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
}
}
--
2.19.2
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[Intel-gfx] [PATCH 11/30] drm/i915/guc: New GuC interrupt register for Gen11
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_guc.c | 14 +-
drivers/gpu/drm/i915/intel_guc_reg.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 483c7019f817..5bc9bc7c956a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc)
I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
+static void gen11_guc_raise_irq(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+}
+
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
{
GEM_BUG_ON(!guc->send_regs.base);
@@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(&guc->ct);
intel_guc_log_init_early(&guc->log);
@@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc)
spin_lock_init(&guc->irq_lock);
guc->send = intel_guc_send_nop;
guc->handler = intel_guc_to_host_event_handler_nop;
- guc->notify = gen8_guc_raise_irq;
+ if (INTEL_GEN(i915) >= 11)
+ guc->notify = gen11_guc_raise_irq;
+ else
+ guc->notify = gen8_guc_raise_irq;
}
static int guc_init_wq(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index 57e7ad522c2f..aec02eddbaed 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -103,6 +103,7 @@
#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
#define GUC_SEND_TRIGGER (1<<0)
+#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
#define GUC_NUM_DOORBELLS 256
--
2.19.2
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[Intel-gfx] [PATCH 13/30] drm/i915/guc: Update GuC CTB response definition
From: Oscar Mateo
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c
b/drivers/gpu/drm/i915/intel_guc_ct.c
index dde1dc0d6e69..2d5dc2aa22a7 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header)
static inline bool ct_header_is_response(u32 header)
{
- return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT;
+ return !!(header & GUC_CT_MSG_IS_RESPONSE);
}
static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 68dfeecf7b26..115c693daf8e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -361,6 +361,7 @@ struct guc_ct_buffer_desc {
*
* bit[4..0] message len (in dwords)
* bit[7..5] reserved
+ * bit[8] response (G2H only)
* bit[8] write fence to desc
* bit[9] write status to H2G buff
* bit[10] send status (via G2H)
@@ -369,6 +370,7 @@ struct guc_ct_buffer_desc {
*/
#define GUC_CT_MSG_LEN_SHIFT 0
#define GUC_CT_MSG_LEN_MASK0x1F
+#define GUC_CT_MSG_IS_RESPONSE (1 << 8)
#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF(1 << 9)
#define GUC_CT_MSG_SEND_STATUS (1 << 10)
--
2.19.2
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[Intel-gfx] [PATCH 14/30] drm/i915/guc: Enable GuC CTB communication on Gen11
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a7e1611af26d..112cfaacc013 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -720,6 +720,7 @@ static const struct intel_device_info intel_cannonlake_info
= {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .has_guc_ct = 1, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
--
2.19.2
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[Intel-gfx] [PATCH 12/30] drm/i915/guc: New GuC scratch registers for Gen11
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_guc.c | 12 +---
drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 5bc9bc7c956a..e54de551b567 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
enum forcewake_domains fw_domains = 0;
unsigned int i;
- guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
- guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
- BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
+ guc->send_regs.base =
+ i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
+ guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
+ } else {
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+ BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
+ }
for (i = 0; i < guc->send_regs.count; i++) {
fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
b/drivers/gpu/drm/i915/intel_guc_reg.h
index aec02eddbaed..d26de5193568 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -51,6 +51,9 @@
#define SOFT_SCRATCH(n)_MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT 16
+#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
+#define GEN11_SOFT_SCRATCH_COUNT 4
+
#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
#define UOS_RSA_SCRATCH_COUNT 64
--
2.19.2
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[Intel-gfx] [PATCH 25/30] drm/i915/guc: New engine-reset-complete message
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc.c | 29 +++
drivers/gpu/drm/i915/intel_guc_fwif.h | 3 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index abedb8982040..c9fbda2e8a78 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -27,6 +27,9 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
+static void guc_handle_engine_reset_completed(struct intel_guc *guc,
+ const u32 engine_class);
+
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -517,6 +520,12 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc
*guc,
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
intel_guc_log_handle_flush_event(&guc->log);
+ if (msg & INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE) {
+ if (len != 3)
+ return -EPROTO;
+ guc_handle_engine_reset_completed(guc, payload[1]);
+ }
+
return 0;
}
@@ -615,6 +624,7 @@ guc_set_class_under_reset(struct intel_guc *guc, unsigned
int guc_class)
{
GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
guc->engine_class_under_reset |= BIT(guc_class);
+ intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
}
static inline void
@@ -622,6 +632,7 @@ guc_clear_class_under_reset(struct intel_guc *guc, unsigned
int guc_class)
{
GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES);
guc->engine_class_under_reset &= ~BIT(guc_class);
+ intel_guc_disable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE);
}
static inline bool
@@ -686,6 +697,24 @@ int intel_guc_reset_engine(struct intel_guc *guc,
return ret;
}
+/*
+ * GuC notifies host that reset engine has completed.
+ * This message should only be received after a request-reset h2g,
+ * so check that and clear the engine_class_under_reset flag.
+ */
+static void guc_handle_engine_reset_completed(struct intel_guc *guc,
+ const u32 engine_class)
+{
+ if (engine_class >= GUC_MAX_ENGINE_CLASSES ||
+ !guc_is_class_under_reset(guc, engine_class)) {
+ DRM_WARN("Unexpected reset-complete for engine class: %d",
+engine_class);
+ return;
+ }
+
+ guc_clear_class_under_reset(guc, engine_class);
+}
+
/**
* intel_guc_resume() - notify GuC resuming from suspend state
* @guc: the guc
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 004d3d882f6f..3b037a9e3181 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -722,7 +722,8 @@ enum intel_guc_response_status {
/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
enum intel_guc_recv_message {
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
- INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3),
+ INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE = BIT(25),
};
#endif
--
2.19.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/30] drm/i915/guc: Make use of the SW counter field in the context descriptor
From: Oscar Mateo
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the maximum number of
concurrent contexts we want to allow, so ideally we want to employ
every possible bit available. Unfortunately, a further limitation in
the interface with the GuC means the combination of SW Context ID +
SW Counter has to be unique within the same engine class (as we use
the SW Context ID to index in the GuC stage descriptor pool, and the
Engine Class + SW Counter to index in the 2-dimensional lrc array).
This essentially means we need to somehow encode the engine instance.
Since the BSpec allows 6 bits for engine instance, we use the whole
SW counter for this task. If the limitation of 2032 maximum simultaneous
contexts is too restrictive, we can always squeeze things a bit more
(3 extras bits for hw_id, 3 bits for instance) and things will still
work (Gen11 does not instance more than 8 engines of any class).
Another alternative would be to generate the hw_id per HW context
instead of per GEM context, but that has other problems (e.g. maximum
number of user-created contexts would be variable, no relationship
between a GuC principal descriptor and the proxy descriptor it uses, ...)
Bspec: 12254
Signed-off-by: Oscar Mateo
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Lionel Landwerlin
Cc: Michal Winiarski
Cc: Tomasz Lis
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h| 9 -
drivers/gpu/drm/i915/i915_gem_context.c| 6 +-
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
drivers/gpu/drm/i915/intel_context_types.h | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 12 +---
6 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f75600fa77c6..b3d5b715b637 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1758,14 +1758,21 @@ struct drm_i915_private {
struct llist_head free_list;
struct work_struct free_work;
- /* The hw wants to have a stable context identifier for the
+ /*
+* The HW wants to have a stable context identifier for the
* lifetime of the context (for OA, PASID, faults, etc).
* This is limited in execlists to 21 bits.
+* In enhanced execlist (GEN11+) this is limited to 11 bits
+* (the SW Context ID field) but GuC limits it further so
+* without taking advantage of part of the SW counter field the
+* firmware only supports a max number of contexts equal to the
+* number of entries in the GuC stage descriptor pool.
*/
struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC GUC_MAX_STAGE_DESCRIPTORS
struct list_head hw_id_list;
} contexts;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 662da485e15f..d882525f67a3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -144,8 +144,12 @@ static inline int new_hw_id(struct drm_i915_private *i915,
gfp_t gfp)
lockdep_assert_held(&i915->contexts.mutex);
+ BUILD_BUG_ON(GUC_MAX_STAGE_DESCRIPTORS > GEN11_MAX_CONTEXT_HW_ID);
+
if (INTEL_GEN(i915) >= 11)
- max = GEN11_MAX_CONTEXT_HW_ID;
+ max = USES_GUC_SUBMISSION(i915) ?
+ GEN11_MAX_CONTEXT_HW_ID_WITH_GUC :
+ GEN11_MAX_CONTEXT_HW_ID;
else if (USES_GUC_SUBMISSION(i915))
/*
* When using GuC in proxy submission, GuC consumes the
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 39a4804091d7..08fb77333d85 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1292,6 +1292,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream
*stream)
case 11: {
i915->perf.oa.specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) <<
(GEN11_SW_CTX_ID_SHIFT - 32) |
+ ((1U << GEN11_SW_COUNTER_WIDTH) - 1) <<
(GEN11_SW_COUNTER_SHIFT - 32) |
((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) <<
(GEN11_ENGINE_INSTANCE_SHIFT - 32) |
((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) <<
(GEN11_ENGINE_CLASS_
[Intel-gfx] [PATCH 19/30] drm/i915/guc: New GuC IDs based on engine class and instance
From: Daniele Ceraolo Spurio Starting from Gen11, the ID to be provided to GuC needs to contain the engine class in bits [0..2] and the instance in bits [3..6]. NOTE: this patch breaks pointer dereferences in some existing GuC functions that use the guc_id to dereference arrays but these functions are not used for now as we have GuC submission disabled and we will update these functions in follow up patch which requires new IDs. Bspec: 20944 Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Oscar Mateo Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko Cc: Michal Winiarski Cc: Tomasz Lis Cc: Joonas Lahtinen Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++- drivers/gpu/drm/i915/intel_guc_fwif.h | 19 +++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index f777afc33d8a..6e0efdd5d354 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -312,7 +312,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->i915 = dev_priv; engine->uncore = &dev_priv->uncore; __sprint_engine_name(engine->name, info); - engine->hw_id = engine->guc_id = info->hw_id; + engine->hw_id = info->hw_id; + engine->guc_id = MAKE_GUC_ID(info->class, info->instance); engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); engine->class = info->class; engine->instance = info->instance; diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 115c693daf8e..61f718b907f3 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -117,6 +117,25 @@ #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ +/* + * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. + * Bit 7 can be used for operations that apply to all engine classes&instances. + */ +#define GUC_ENGINE_CLASS_SHIFT 0 +#define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) +#define GUC_ENGINE_INSTANCE_SHIFT 3 +#define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) +#define GUC_ENGINE_ALL_INSTANCES (1 << 7) + +#define MAKE_GUC_ID(class, instance) \ + (((class) << GUC_ENGINE_CLASS_SHIFT) | \ +((instance) << GUC_ENGINE_INSTANCE_SHIFT)) + +#define GUC_ID_TO_ENGINE_CLASS(guc_id) \ + (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) +#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ + (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) + /** * DOC: GuC Firmware Layout * -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 28/30] drm/i915/guc: Correctly handle GuC interrupts on Gen11
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++-
drivers/gpu/drm/i915/i915_irq.c | 76 +---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_guc_reg.h | 18 +++
4 files changed, 94 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 120b0967c4e8..3b18fdbdea60 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1577,7 +1577,11 @@ struct drm_i915_private {
u32 pm_imr;
u32 pm_ier;
u32 pm_rps_events;
- u32 pm_guc_events;
+ union {
+ /* RPS and GuC share a register pre-Gen11 */
+ u32 pm_guc_events;
+ u32 guc_events;
+ };
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3dd971c09d52..c1b4fbd5f496 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -573,6 +573,44 @@ static void gen9_disable_guc_interrupts(struct
drm_i915_private *dev_priv)
gen9_reset_guc_interrupts(dev_priv);
}
+static void gen11_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+
+ while (gen11_reset_one_iir(dev_priv, 0, GEN11_GUC))
+ ;
+
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+static void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ if (!dev_priv->guc_interrupts.enabled) {
+ u32 guc_events = dev_priv->guc_events << 16;
+
+ WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events);
+ dev_priv->guc_interrupts.enabled = true;
+ }
+ spin_unlock_irq(&dev_priv->irq_lock);
+}
+
+static void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ dev_priv->guc_interrupts.enabled = false;
+
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+
+ spin_unlock_irq(&dev_priv->irq_lock);
+ synchronize_irq(dev_priv->drm.irq);
+
+ gen11_reset_guc_interrupts(dev_priv);
+}
+
/**
* bdw_update_port_irq - update DE port interrupt
* @dev_priv: driver private
@@ -1823,6 +1861,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private
*dev_priv, u32 gt_iir)
intel_guc_to_host_event_handler(&dev_priv->guc);
}
+static void gen11_guc_irq_handler(struct drm_i915_private *dev_priv, u16 iir)
+{
+ if (iir & GEN11_GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(&dev_priv->guc);
+}
+
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
{
enum pipe pipe;
@@ -2945,11 +2989,17 @@ static void
gen11_other_irq_handler(struct drm_i915_private * const i915,
const u8 instance, const u16 iir)
{
- if (instance == OTHER_GTPM_INSTANCE)
+ switch (instance) {
+ case OTHER_GUC_INSTANCE:
+ return gen11_guc_irq_handler(i915, iir);
+
+ case OTHER_GTPM_INSTANCE:
return gen6_rps_irq_handler(i915, iir);
- WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
- instance, iir);
+ default:
+ WARN_ONCE(1, "unhandled other irq instance=0x%x, iir=0x%x\n",
+ instance, iir);
+ }
}
static void
@@ -3469,6 +3519,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private
*dev_priv)
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void gen11_irq_reset(struct drm_device *dev)
@@ -4111,6 +4163,10 @@ static void gen11_gt_irq_postinstall(struct
drm_i915_private *dev_priv)
dev_priv->pm_imr = ~dev_priv->pm_ier;
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+
+ /* Same thing for GuC interrupts */
+ I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
}
static void icp_irq_postinstall(struct drm_device *dev)
@@ -4611,8 +4667,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
- if (HAS_GUC_SCHED(dev_priv))
- dev_priv->
[Intel-gfx] [PATCH 23/30] drm/i915/guc: Add support for resume-parsing wq item
Since fw version 25.161, GuC lets us know when an engine had to be reset
due to a hang in another dependent engine, by setting BIT(engine_class) in
the queue_engine_error field. GuC will ignore any other wq item until this
flag is cleared.
To restart the workqueue processing for that engine, we must insert a
special wq item called resume-parsing and wait until the queue_engine_error
field is updated.
Co-Developed-by: Michel Thierry
Co-Developed-by: Michal Wajdeczko
Signed-off-by: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Tomasz Lis
---
drivers/gpu/drm/i915/intel_guc_submission.c | 92 +++--
1 file changed, 86 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 1a27352b73a9..b0b10cac9b9b 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -427,6 +427,76 @@ static void guc_proxy_stage_desc_fini(struct
intel_guc_client *client)
memset(desc, 0, sizeof(*desc));
}
+static u32 get_wq_offset(struct guc_process_desc *desc)
+{
+ const size_t wqi_size = sizeof(struct guc_wq_item);
+ u32 wq_off;
+
+ /*
+* Free space is guaranteed, either by normal port submission or
+* because we waited for the wq_resume to be processed.
+*/
+ wq_off = READ_ONCE(desc->tail);
+ GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
+ GUC_WQ_SIZE) < wqi_size);
+ GEM_BUG_ON(wq_off & (wqi_size - 1));
+
+ return wq_off;
+}
+
+static void write_wqi(struct guc_process_desc *desc, u32 wq_off)
+{
+ const size_t wqi_size = sizeof(struct guc_wq_item);
+
+ WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
+}
+
+static void guc_append_wq_resume_parsing_item(struct intel_guc_client *client,
+ struct intel_engine_cs *engine)
+{
+ struct guc_process_desc *desc = __get_process_desc(client);
+ const u32 target_engine = engine->guc_id;
+ const u32 wqi_resume = WQ_TYPE_RESUME |
+ (target_engine << WQ_TARGET_SHIFT) |
+ (0 << WQ_LEN_SHIFT);
+ const u32 wqi_noop = WQ_TYPE_NOOP |
+ (target_engine << WQ_TARGET_SHIFT) |
+ (0 << WQ_LEN_SHIFT);
+ struct guc_wq_item *wqi;
+ u32 wq_off;
+
+ lockdep_assert_held(&client->wq_lock);
+
+ wq_off = get_wq_offset(desc);
+ wqi = client->vaddr + wq_off + GUC_DB_SIZE;
+
+ /*
+* Submit 4 wq_items (1 RESUME_WQ_PARSING followed by 3 NOOPs) in
+* order to keep it the same size as a 'normal' wq_item.
+*/
+ wqi->header = wqi_resume;
+ wqi->context_desc = wqi_noop;
+ wqi->submit_element_info = wqi_noop;
+ wqi->fence_id = wqi_noop;
+
+ write_wqi(desc, wq_off);
+}
+
+#define GUC_WAIT_FOR_ENGINE_ERROR_CLEANED_MS 10
+
+static void guc_wait_wq_resumed(struct intel_guc_client *client,
+ struct intel_engine_cs *engine)
+{
+ struct guc_process_desc *desc = __get_process_desc(client);
+ u8 guc_class = engine->class;
+
+ lockdep_assert_held(&client->wq_lock);
+
+ /* must wait for the flag to be cleared */
+ WARN_ON(wait_for_atomic(!(desc->queue_engine_error & BIT(guc_class)),
+ GUC_WAIT_FOR_ENGINE_ERROR_CLEANED_MS));
+}
+
/* Construct a Work Item and append it to the GuC's Work Queue */
static void guc_wq_item_append(struct intel_guc_client *client,
struct intel_context *ce,
@@ -454,11 +524,7 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
/* We expect the WQ to be active if we're appending items to it */
GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
- /* Free space is guaranteed. */
- wq_off = READ_ONCE(desc->tail);
- GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
- GUC_WQ_SIZE) < wqi_size);
- GEM_BUG_ON(wq_off & (wqi_size - 1));
+ wq_off = get_wq_offset(desc);
/* WQ starts from the page after doorbell / process_desc */
wqi = client->vaddr + wq_off + GUC_DB_SIZE;
@@ -481,7 +547,7 @@ static void guc_wq_item_append(struct intel_guc_client
*client,
}
/* Make the update visible to GuC */
- WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
+ write_wqi(desc, wq_off);
}
static void guc_ring_doorbell(struct intel_guc_client *client)
@@ -505,6 +571,14 @@ static void guc_ring_doorbell(struct intel_guc_client
*client)
GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
}
+static bool guc_needs_wq_resume_parsing_item(struct intel_guc_client *client,
+u32 target_engine_c
[Intel-gfx] [PATCH 26/30] drm/i915/guc: Properly capture & release GuC interrupts on Gen11
From: Oscar Mateo
With the new interrupt re-partitioning in Gen11, GuC controls by itself
the interrupts it receives, so steering bits and registers have been
defeatured. Being this the case, when the GuC is in control of
submissions we won't know what to do with the ctx switch interrupt
in the driver, so disable it.
Bspec: 12609
Bspec: 10800
Bspec: 10932
Bspec: 10934
Bspec: 9517
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Michal Winiarski
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 57 -
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 455b2bf691b5..4de6474b6a25 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4634,7 +4634,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) <= 7)
rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
- if (INTEL_GEN(dev_priv) >= 8)
+ if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index b0b10cac9b9b..e3f6e2b1aa99 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1263,7 +1263,7 @@ void intel_guc_submission_fini(struct intel_guc *guc)
guc_stage_desc_pool_destroy(guc);
}
-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
+static void gen8_guc_interrupts_capture(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
struct intel_engine_cs *engine;
@@ -1308,7 +1308,7 @@ static void guc_interrupts_capture(struct
drm_i915_private *dev_priv)
rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
}
-static void guc_interrupts_release(struct drm_i915_private *dev_priv)
+static void gen8_guc_interrupts_release(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
struct intel_engine_cs *engine;
@@ -1333,6 +1333,59 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
}
+static void gen11_guc_interrupts_capture(struct drm_i915_private *dev_priv)
+{
+ struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ u32 tmp;
+ u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
+
+ /* Don't handle ctx switch interrupt in GuC submission mode */
+ tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+ tmp &= ~(irqs << 16 | irqs);
+ I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp);
+
+ tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+ tmp &= ~(irqs << 16 | irqs);
+ I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp);
+
+ /* GuC needs ARAT expired interrupt unmasked */
+ rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
+}
+
+static void gen11_guc_interrupts_release(struct drm_i915_private *dev_priv)
+{
+ struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ u32 tmp;
+ u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
+
+ /* Handle ctx switch interrupts again */
+ tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
+ tmp |= (irqs << 16 | irqs);
+ I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp);
+
+ tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
+ tmp |= (irqs << 16 | irqs);
+ I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp);
+
+ rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
+}
+
+static void guc_interrupts_capture(struct drm_i915_private *i915)
+{
+ if (INTEL_GEN(i915) >= 11)
+ gen11_guc_interrupts_capture(i915);
+ else
+ gen8_guc_interrupts_capture(i915);
+}
+
+static void guc_interrupts_release(struct drm_i915_private *i915)
+{
+ if (INTEL_GEN(i915) >= 11)
+ gen11_guc_interrupts_release(i915);
+ else
+ gen8_guc_interrupts_release(i915);
+}
+
static void guc_submission_park(struct intel_engine_cs *engine)
{
intel_engine_unpin_breadcrumbs_irq(engine);
--
2.19.2
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[Intel-gfx] [PATCH 27/30] drm/i915/guc: Create vfuncs for the GuC interrupts control functions
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 22 ++
drivers/gpu/drm/i915/i915_irq.c | 18 --
drivers/gpu/drm/i915/intel_drv.h | 3 ---
drivers/gpu/drm/i915/intel_guc.h | 1 -
drivers/gpu/drm/i915/intel_uc.c | 6 +++---
5 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e7d0f3d2c82..120b0967c4e8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1580,6 +1580,13 @@ struct drm_i915_private {
u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
+ struct {
+ bool enabled;
+ void (*reset)(struct drm_i915_private *i915);
+ void (*enable)(struct drm_i915_private *i915);
+ void (*disable)(struct drm_i915_private *i915);
+ } guc_interrupts;
+
struct i915_hotplug hotplug;
struct intel_fbc fbc;
struct i915_drrs drrs;
@@ -2716,6 +2723,21 @@ extern void intel_irq_fini(struct drm_i915_private
*dev_priv);
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
+static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.reset(i915);
+}
+
+static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.enable(i915);
+}
+
+static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915)
+{
+ i915->guc_interrupts.disable(i915);
+}
+
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
return dev_priv->gvt;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4de6474b6a25..3dd971c09d52 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -535,7 +535,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private
*dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
@@ -544,26 +544,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private
*dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts_enabled) {
+ if (!dev_priv->guc_interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts_enabled = true;
+ dev_priv->guc_interrupts.enabled = true;
gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
}
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
{
assert_rpm_wakelock_held(dev_priv);
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts_enabled = false;
+ dev_priv->guc_interrupts.enabled = false;
gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
@@ -4637,6 +4637,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
+ if (INTEL_GEN(dev_priv) >= 9) {
+ dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts;
+ dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts;
+ dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts;
+ }
+
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
dev->driver->get_vblank_counter = g4x_get_vblank_counter;
else if (INTEL_GEN(dev_priv) >= 3)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f8c7b291fdc3..1739f2fe5288 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1618,9 +1618,6 @@ void gen8_irq_power_well_post_enable(struct
drm_i915_private *dev_priv,
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
-void gen9_re
[Intel-gfx] [PATCH] drm/i915: add immutable zpos plane properties
From: emersion
This adds basic immutable support for the zpos property. The zpos increases
from bottom to top: primary, sprites, cursor.
Signed-off-by: Simon Ser
---
This is based on a previous patch by Ville [1] that I wanted to review.
Unfortunately the patch no longer applies, so here is a new one.
[1]: https://patchwork.freedesktop.org/patch/225887/?series=43902&rev=1
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_sprite.c | 5 -
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799..f0a85a75bd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14323,7 +14323,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
const u64 *modifiers;
const u32 *formats;
int num_formats;
- int ret;
+ int ret, zpos;
if (INTEL_GEN(dev_priv) >= 9)
return skl_universal_plane_create(dev_priv, pipe,
@@ -14412,6 +14412,9 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
DRM_MODE_ROTATE_0,
supported_rotations);
+ zpos = 0;
+ drm_plane_create_zpos_immutable_property(&plane->base, zpos);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
@@ -14428,7 +14431,7 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
{
unsigned int possible_crtcs;
struct intel_plane *cursor;
- int ret;
+ int ret, zpos;
cursor = intel_plane_alloc();
if (IS_ERR(cursor))
@@ -14477,6 +14480,9 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0 |
DRM_MODE_ROTATE_180);
+ zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
+ drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
+
drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
return cursor;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 65de7387bf..48bd8f9079 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2354,7 +2354,7 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
const u64 *modifiers;
const u32 *formats;
int num_formats;
- int ret;
+ int ret, zpos;
if (INTEL_GEN(dev_priv) >= 9)
return skl_universal_plane_create(dev_priv, pipe,
@@ -2444,6 +2444,9 @@ intel_sprite_plane_create(struct drm_i915_private
*dev_priv,
DRM_COLOR_YCBCR_BT709,
DRM_COLOR_YCBCR_LIMITED_RANGE);
+ zpos = sprite + 1;
+ drm_plane_create_zpos_immutable_property(&plane->base, zpos);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
--
2.21.0
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Re: [Intel-gfx] [PATCH 20/30] drm/i915/guc: Make use of the SW counter field in the context descriptor
Quoting Michal Wajdeczko (2019-03-29 22:11:08) > From: Oscar Mateo > > The new context descriptor format contains two assignable fields: > the SW Context ID (technically 11 bits, but practically limited to 2032 > entries due to some being reserved for future use by the GuC) and the > SW Counter (6 bits). Phooey, I've dropped use of the hw id. So no limit at all in execlists, and no contention on pinning the hw id. We could land that and move this mechanism to the guc backend so that it doesn't impact anything else. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 28/30] drm/i915/guc: Correctly handle GuC interrupts on Gen11
Quoting Michal Wajdeczko (2019-03-29 22:11:16)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3dd971c09d52..c1b4fbd5f496 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -573,6 +573,44 @@ static void gen9_disable_guc_interrupts(struct
> drm_i915_private *dev_priv)
> gen9_reset_guc_interrupts(dev_priv);
> }
>
> +static void gen11_reset_guc_interrupts(struct drm_i915_private *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> +
> + while (gen11_reset_one_iir(dev_priv, 0, GEN11_GUC))
> + ;
I have to say this and gen11_reset_rps_interupts() is brave. Are these
registers move than double-buffered? Should we throw in a '&& loops++ < 3'?
-Chris
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Re: [Intel-gfx] [PATCH v4] drm/i915/icl: Fix clockgating issue when using scalers
On Fri, 2019-03-29 at 20:39 +0200, Ville Syrjälä wrote:
> On Thu, Mar 28, 2019 at 10:35:19AM -0700, Radhakrishna Sripada wrote:
> > Fixes the clock-gating issue when pipe scaling is enabled.
> > (Lineage #2006604312)
> >
> > V2: Fix typo in headline(Chris)
> > Handle the non double buffered nature of the register(Ville)
> > V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks
> > unrelated.
> > V4: Split the icl and skl wa's(Ville)
> >
> > Cc: Chris Wilson
> > Cc: Ville Syrjala
> > Cc: Rodrigo Vivi
> > Cc: Aditya Swarup
> > Signed-off-by: Radhakrishna Sripada > >
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 48 --
> > --
> > 1 file changed, 34 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 8576a7f799f2..c3ca9cfd36fe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -466,6 +466,7 @@ static const struct intel_limit
> > intel_limits_bxt = {
> > .p2 = { .p2_slow = 1, .p2_fast = 20 },
> > };
> >
> > +/* WA Display #0827: Gen9:all */
> > static void
> > skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool
> > enable)
> > {
> > @@ -478,6 +479,17 @@ skl_wa_clkgate(struct drm_i915_private
> > *dev_priv, int pipe, bool enable)
> >~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
> > }
> >
> > +/* Wa_2006604312:icl */
> > +static void
> > +icl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool
> > enable)
>
> These functions names (including the skl one) are rather too generic
> and don't describe which clock gating we're disabling. But fixing
> that is probably material for another patch.
Sure let me spin out another patch for this.
>
> > +{
> > + if (enable)
> > + I915_WRITE(CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS);
> > + else
> > + I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > + I915_READ(CLKGATE_DIS_PSL(pipe)) &
> > ~DPFR_GATING_DIS);
>
> No RMW for enable but RMW for disable? Seems rather inconsistent.
Sure looks inconsistent. Let me fix it next rev.
>
> > +}
> > +
> > static bool
> > needs_modeset(const struct drm_crtc_state *state)
> > {
> > @@ -5481,14 +5493,18 @@ static bool
> > hsw_post_update_enable_ips(const struct intel_crtc_state
> > *old_crtc_s
> > return !old_crtc_state->ips_enabled;
> > }
> >
> > -static bool needs_nv12_wa(struct drm_i915_private *dev_priv,
> > - const struct intel_crtc_state *crtc_state)
> > +static bool skl_needs_clk_wa(struct drm_i915_private *dev_priv,
> > +const struct intel_crtc_state *crtc_state)
>
> Still mixing our workarounds more than I'd like. I suggest keeping
> the two entirely separate.
Sure let me separate it completely. Avoids duplicating checks as well.
Thanks,
Radhakrishna(RK) Sripada
>
> > {
> > - if (!crtc_state->nv12_planes)
> > - return false;
> > -
> > /* WA Display #0827: Gen9:all */
> > - if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
> > + if (!!crtc_state->nv12_planes && IS_GEN(dev_priv, 9) &&
> > + !IS_GEMINILAKE(dev_priv))
> > + return true;
> > +
> > + /*
> > +* Wa_2006604312:icl
> > +*/
> > + if (IS_ICELAKE(dev_priv) && crtc_state->pch_pfit.enabled)
> > return true;
> >
> > return false;
> > @@ -5527,10 +5543,12 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> > intel_post_enable_primary(&crtc->base,
> > pipe_config);
> > }
> >
> > - /* Display WA 827 */
> > - if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - !needs_nv12_wa(dev_priv, pipe_config)) {
> > - skl_wa_clkgate(dev_priv, crtc->pipe, false);
> > + if (skl_needs_clk_wa(dev_priv, old_crtc_state) &&
> > + !skl_needs_clk_wa(dev_priv, pipe_config)) {
> > + if (IS_ICELAKE(dev_priv))
> > + icl_wa_clkgate(dev_priv, crtc->pipe, false);
> > + else
> > + skl_wa_clkgate(dev_priv, crtc->pipe, false);
> > }
> > }
> >
> > @@ -5566,10 +5584,12 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> > intel_set_cpu_fifo_underrun_reporting(dev_priv,
> > crtc->pipe, false);
> > }
> >
> > - /* Display WA 827 */
> > - if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> > - needs_nv12_wa(dev_priv, pipe_config)) {
> > - skl_wa_clkgate(dev_priv, crtc->pipe, true);
> > + if (!skl_needs_clk_wa(dev_priv, old_crtc_state) &&
> > + skl_needs_clk_wa(dev_priv, pipe_config)) {
> > + if (IS_ICELAKE(dev_priv))
> > + icl_wa_clkgate(dev_priv, crtc->pipe, true);
> > + else
> > + skl_wa_clkgate(dev_priv, crtc->pipe, true);
> > }
> >
> > /*
> > --
> > 2.20.0.rc2.7.g965798d1f299
>
>
___
[Intel-gfx] [PATCH v2] drm/i915/guc: Retry GuC load for all load failures
Currently we only retry to load GuC firmware if the load fails due to
timeout. On Gen9 GuC loading may fail for different reasons, not just
hang/timeout. Direction from the GuC team is to retry for all cases of
GuC load failure on Gen9, not just for timeout.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108593
Signed-off-by: Robert M. Fosha
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2d360d53757f..25b80ffe71ad 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -375,7 +375,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
intel_guc_init_params(guc);
ret = intel_guc_fw_upload(guc);
- if (ret == 0 || ret != -ETIMEDOUT)
+ if (ret == 0)
break;
DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
--
2.21.0.5.gaeb582a983
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC 32.0.3
== Series Details == Series: GuC 32.0.3 URL : https://patchwork.freedesktop.org/series/58760/ State : warning == Summary == $ dim checkpatch origin/drm-tip 07625b512895 drm/i915/guc: Don't allow GuC submission on pre-Gen11 a79bbfbbcaeb drm/i915/guc: Simplify preparation of GuC parameter block 94c06af628c8 drm/i915/guc: Update GuC firmware versions and names 281a7ab1800e drm/i915/guc: Update GuC firmware CSS header b0fe25ecbdef drm/i915/guc: Update GuC boot parameters 172024033ca9 drm/i915/guc: Update GuC sleep status values fafcf0016350 drm/i915/guc: Update GuC sample-forcewake command e2444d3152fe drm/i915/guc: Always ask GuC to update power domain states 4055e1730306 drm/i915/guc: Update GuC ADS object definition d84c83744126 drm/i915/guc: Reset GuC ADS during sanitize 2e657fbac482 drm/i915/guc: New GuC interrupt register for Gen11 36baa8c466aa drm/i915/guc: New GuC scratch registers for Gen11 dd29e99702e0 drm/i915/guc: Update GuC CTB response definition -:45: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Oscar Mateo ' total: 0 errors, 1 warnings, 0 checks, 22 lines checked a7a0c4502b4b drm/i915/guc: Enable GuC CTB communication on Gen11 051158fa445c drm/i915/huc: New HuC status register for Gen11 3b30d337fd57 drm/i915/guc: Define GuC firmware version for Icelake c8f0b2a34b8c drm/i915/huc: Define HuC firmware version for Icelake 8c06d748e638 drm/i915/guc: Treat GuC initialization failure as -EIO c7046bd151d8 drm/i915/guc: New GuC IDs based on engine class and instance c0ef43eabfe1 drm/i915/guc: Make use of the SW counter field in the context descriptor 4387539fbd4e drm/i915/guc: New GuC stage descriptors -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/i915_debugfs.c:2285: + seq_printf(m, "\t\tHW context desc: 0x%x:0x%x\n", + lower_32_bits(lrc->hw_context_desc), -:355: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #355: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:194: + GEM_BUG_ON(!I915_SELFTEST_ONLY(client->guc->starting_proxy_id) && + client->stage_id < GUC_MAX_PPAL_STAGE_DESCRIPTORS); total: 0 errors, 0 warnings, 2 checks, 801 lines checked 58d9cb8849cd drm/i915/guc: New GuC workqueue item submission mechanism f9208efef283 drm/i915/guc: Add support for resume-parsing wq item -:15: WARNING:BAD_SIGN_OFF: 'Co-developed-by:' is the preferred signature form #15: Co-Developed-by: Michel Thierry -:16: WARNING:BAD_SIGN_OFF: 'Co-developed-by:' is the preferred signature form #16: Co-Developed-by: Michal Wajdeczko total: 0 errors, 2 warnings, 0 checks, 125 lines checked 5c5d17e155bf drm/i915/guc: New reset-engine command -:11: WARNING:BAD_SIGN_OFF: 'Co-developed-by:' is the preferred signature form #11: Co-Developed-by: Michel Thierry total: 0 errors, 1 warnings, 0 checks, 102 lines checked c9d66fb31815 drm/i915/guc: New engine-reset-complete message dbfc310b9339 drm/i915/guc: Properly capture & release GuC interrupts on Gen11 e174c48db89e drm/i915/guc: Create vfuncs for the GuC interrupts control functions 1cb3055da417 drm/i915/guc: Correctly handle GuC interrupts on Gen11 e693e55b1a34 HAX: prevent CI failures on pre-Gen11 configs with forced GuC 915a4cffdbb4 HAX: Enable HuC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for GuC 32.0.3
== Series Details == Series: GuC 32.0.3 URL : https://patchwork.freedesktop.org/series/58760/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/guc: Don't allow GuC submission on pre-Gen11 Okay! Commit: drm/i915/guc: Simplify preparation of GuC parameter block Okay! Commit: drm/i915/guc: Update GuC firmware versions and names Okay! Commit: drm/i915/guc: Update GuC firmware CSS header Okay! Commit: drm/i915/guc: Update GuC boot parameters Okay! Commit: drm/i915/guc: Update GuC sleep status values Okay! Commit: drm/i915/guc: Update GuC sample-forcewake command Okay! Commit: drm/i915/guc: Always ask GuC to update power domain states Okay! Commit: drm/i915/guc: Update GuC ADS object definition Okay! Commit: drm/i915/guc: Reset GuC ADS during sanitize Okay! Commit: drm/i915/guc: New GuC interrupt register for Gen11 Okay! Commit: drm/i915/guc: New GuC scratch registers for Gen11 Okay! Commit: drm/i915/guc: Update GuC CTB response definition Okay! Commit: drm/i915/guc: Enable GuC CTB communication on Gen11 Okay! Commit: drm/i915/huc: New HuC status register for Gen11 Okay! Commit: drm/i915/guc: Define GuC firmware version for Icelake Okay! Commit: drm/i915/huc: Define HuC firmware version for Icelake Okay! Commit: drm/i915/guc: Treat GuC initialization failure as -EIO Okay! Commit: drm/i915/guc: New GuC IDs based on engine class and instance Okay! Commit: drm/i915/guc: Make use of the SW counter field in the context descriptor -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3577:16: warning: expression using sizeof(void) Commit: drm/i915/guc: New GuC stage descriptors -drivers/gpu/drm/i915/selftests/../i915_drv.h:3577:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3578:16: warning: expression using sizeof(void) Commit: drm/i915/guc: New GuC workqueue item submission mechanism Okay! Commit: drm/i915/guc: Add support for resume-parsing wq item Okay! Commit: drm/i915/guc: New reset-engine command Okay! Commit: drm/i915/guc: New engine-reset-complete message Okay! Commit: drm/i915/guc: Properly capture & release GuC interrupts on Gen11 Okay! Commit: drm/i915/guc: Create vfuncs for the GuC interrupts control functions -drivers/gpu/drm/i915/selftests/../i915_drv.h:3578:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3600:16: warning: expression using sizeof(void) Commit: drm/i915/guc: Correctly handle GuC interrupts on Gen11 -drivers/gpu/drm/i915/selftests/../i915_drv.h:3600:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3604:16: warning: expression using sizeof(void) Commit: HAX: prevent CI failures on pre-Gen11 configs with forced GuC Okay! Commit: HAX: Enable HuC Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Engine relative MMIO
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engine
and not absolute addresses.
The LRI command has support for engine relative addressing. However,
the mechanism is not transparent to the driver. The scheme for Gen11
(MI_LRI_ADD_CS_MMIO_START) requires the LRI address to have no
absolute engine base component. The hardware then adds on the correct
engine offset at execution time.
Due to the non-trivial and differing schemes on different hardware, it
is not possible to simply update the code that creates the LRI
commands to set a remap flag and let the hardware get on with it.
Instead, this patch adds function wrappers for generating the LRI
command itself and then for constructing the correct address to use
with the LRI.
v2: Fix build break in GVT. Remove flags parameter [review feedback
from Chris W].
v3: Fix build break in selftest. Rebase to newer base tree and fix
merge conflict.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 16 +++-
drivers/gpu/drm/i915/i915_cmd_parser.c| 4 +-
drivers/gpu/drm/i915/i915_gem_context.c | 12 +--
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 4 +-
drivers/gpu/drm/i915/i915_perf.c | 19 +++--
drivers/gpu/drm/i915/intel_engine_cs.c| 11 +++
drivers/gpu/drm/i915/intel_gpu_commands.h | 6 +-
drivers/gpu/drm/i915/intel_lrc.c | 80 ++-
drivers/gpu/drm/i915/intel_lrc_reg.h | 4 +-
drivers/gpu/drm/i915/intel_mocs.c | 17 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 45 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
.../drm/i915/selftests/intel_workarounds.c| 9 ++-
14 files changed, 154 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c
b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 76630fbe51b6..1d24095b345a 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -199,14 +199,14 @@ restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(count);
+ *cs++ = i915_get_lri_cmd(req->engine, count);
for (mmio = gvt->engine_mmio_list.mmio;
i915_mmio_reg_valid(mmio->reg); mmio++) {
if (mmio->ring_id != ring_id ||
!mmio->in_context)
continue;
- *cs++ = i915_mmio_reg_offset(mmio->reg);
+ *cs++ = i915_get_lri_reg(req->engine, mmio->reg);
*cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
(mmio->mask << 16);
gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx,
vgpu:%d, rind_id:%d\n",
@@ -234,7 +234,11 @@ restore_render_mocs_control_for_inhibit(struct intel_vgpu
*vgpu,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
+ /*
+* GEN9_GFX_MOCS is not engine relative, therefore there is no
+* need for relative addressing.
+*/
+ *cs++ = __MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
for (index = 0; index < GEN9_MOCS_SIZE; index++) {
*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
@@ -261,7 +265,11 @@ restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu
*vgpu,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
+ /*
+* GEN9_LNCFCMOCS is not engine relative, therefore there is no
+* need for relative addressing.
+*/
+ *cs++ = __MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 503d548a55f7..91ebe18aacc6 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -220,7 +220,7 @@ static const struct drm_i915_cmd_descriptor common_cmds[] =
{
CMD( MI_SUSPEND_FLUSH, SMI,F, 1, S ),
CMD( MI_SEMAPHORE_MBOX,SMI, !F, 0xFF, R ),
CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
- CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
+ CMD( __MI_LOAD_REGISTER_IMM(1),SMI, !F, 0xFF, W,
.reg = { .offset = 1, .mask = 0x007C, .step = 2 }),
CMD( MI_STORE_REGISTER_MEM,SMI,F, 3, W | B,
.reg = { .offset = 1, .mask = 0x007
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add immutable zpos plane properties
== Series Details == Series: drm/i915: add immutable zpos plane properties URL : https://patchwork.freedesktop.org/series/58761/ State : warning == Summary == $ dim checkpatch origin/drm-tip a8460dd85471 drm/i915: add immutable zpos plane properties -:75: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'emersion ' total: 0 errors, 1 warnings, 0 checks, 51 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for GuC 32.0.3
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12637
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12637 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12637, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58760/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12637:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_uncore:
- fi-kbl-x1275: PASS -> DMESG-FAIL
- fi-kbl-8809g: PASS -> DMESG-FAIL
- fi-cfl-8700k: PASS -> DMESG-FAIL
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-icl-u2: PASS -> SKIP +3
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
- fi-icl-u3: PASS -> SKIP +3
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_gttfill@basic:
- {fi-icl-guc}: NOTRUN -> SKIP
Known issues
Here are the changes found in Patchwork_12637 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_hangman@error-state-basic:
- fi-skl-gvtdvm: PASS -> SKIP [fdo#109271] +3
- fi-skl-6770hq: PASS -> SKIP [fdo#109271] +3
- fi-kbl-r: PASS -> SKIP [fdo#109271] +3
- fi-kbl-8809g: PASS -> SKIP [fdo#109271]
- fi-skl-6600u: PASS -> SKIP [fdo#109271] +3
- fi-kbl-x1275: PASS -> SKIP [fdo#109271] +3
- fi-skl-iommu: PASS -> SKIP [fdo#109271] +3
- fi-kbl-7500u: PASS -> SKIP [fdo#109271]
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744]
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-cfl-8700k: PASS -> SKIP [fdo#109271] +3
- fi-skl-6260u: PASS -> SKIP [fdo#109271] +3
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +3
- fi-cfl-8109u: PASS -> SKIP [fdo#109271] +3
- fi-whl-u: PASS -> SKIP [fdo#109271] +3
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48
- fi-skl-6700k2: PASS -> SKIP [fdo#109271] +3
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@runner@aborted:
- fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602]
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: FAIL [fdo#103167] -> PASS
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-icl-u3: FAIL [fdo#104008] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108743]: https://bugs.freedesktop.org/show_bug.cgi?id=108743
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (50 -> 40)
--
Additional (1): fi-icl-guc
Missing(11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-bxt-j
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: add immutable zpos plane properties
== Series Details == Series: drm/i915: add immutable zpos plane properties URL : https://patchwork.freedesktop.org/series/58761/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12638 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12638 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12638, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/58761/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12638: ### IGT changes ### Possible regressions * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-bsw-kefka: PASS -> FAIL Known issues Here are the changes found in Patchwork_12638 that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] * igt@runner@aborted: - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (50 -> 36) -- Missing(14): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-kbl-x1275 fi-icl-u3 fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_5840 -> Patchwork_12638 CI_DRM_5840: db336fee1090f4207856469e57d04bcf56fe9e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4913: e408d569973b610ba4aafdba016c48b25e563468 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12638: a8460dd85471c4633e93a73db5881d09cc8f68ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a8460dd85471 drm/i915: add immutable zpos plane properties == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12638/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GuC 32.0.3
Quoting Patchwork (2019-03-30 00:34:48)
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_gttfill@basic:
> - {fi-icl-guc}: NOTRUN -> SKIP
What CI doesn't say is that in the 3 runs, each time fi-icl-guc hits the
same deadlock in S3 (gem_exec_susped). intel_uc_suspend? But the trace
isn't conclusive.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Retry GuC load for all load failures (rev2)
== Series Details == Series: drm/i915/guc: Retry GuC load for all load failures (rev2) URL : https://patchwork.freedesktop.org/series/58758/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12639 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58758/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12639 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-icl-u3: PASS -> FAIL [fdo#103375] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1 * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: PASS -> FAIL [fdo#103182] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: FAIL [fdo#103167] -> PASS * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: FAIL [fdo#104008] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 Participating hosts (50 -> 41) -- Missing(9): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-skl-6600u Build changes - * Linux: CI_DRM_5840 -> Patchwork_12639 CI_DRM_5840: db336fee1090f4207856469e57d04bcf56fe9e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4913: e408d569973b610ba4aafdba016c48b25e563468 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12639: 78169131042b7b14ecaa64e16044461b6fde5b0e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 78169131042b drm/i915/guc: Retry GuC load for all load failures == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12639/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Engine relative MMIO (rev3)
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3f3b4a23cc5 drm/i915: Engine relative MMIO
-:89: ERROR:SPACING: space prohibited after that open parenthesis '('
#89: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:223:
+ CMD( __MI_LOAD_REGISTER_IMM(1),SMI, !F, 0xFF, W,
-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/i915_cmd_parser.c:224:
+ CMD( __MI_LOAD_REGISTER_IMM(1),SMI, !F, 0xFF, W,
.reg = { .offset = 1, .mask = 0x007C, .step = 2 }),
-:249: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#249: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:130:
+#define __MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
^
-:249: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#249: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:130:
+#define __MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
^
-:251: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#251: FILE: drivers/gpu/drm/i915/intel_gpu_commands.h:132:
+#define MI_LRI_ADD_CS_MMIO_START (1<<19)
^
-:538: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#538: FILE: drivers/gpu/drm/i915/intel_ringbuffer.c:1771:
+ *cs++ = i915_get_lri_cmd(rq->engine, GEN7_L3LOG_SIZE/4);
^
-:606: CHECK:CAMELCASE: Avoid CamelCase:
#606: FILE: drivers/gpu/drm/i915/selftests/intel_workarounds.c:490:
+ u32 regLRI = i915_get_lri_reg(engine,
engine->whitelist.list[i].reg);
total: 1 errors, 0 warnings, 6 checks, 505 lines checked
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[Intel-gfx] [PATCH v5 3/3] drm/i915/icl: Fix clockgating issue when using scalers
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
V5: Split the checks for icl and skl(Ville)
Cc: Chris Wilson
Cc: Ville Syrjala
Cc: Rodrigo Vivi
Cc: Aditya Swarup
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 41
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f54183761a40..61bdef1b19a1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -466,6 +466,7 @@ static const struct intel_limit intel_limits_bxt = {
.p2 = { .p2_slow = 1, .p2_fast = 20 },
};
+/* WA Display #0827: Gen9:all */
static void
skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
@@ -479,6 +480,18 @@ skl_wa_827(struct drm_i915_private *dev_priv, int pipe,
bool enable)
~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
}
+/* Wa_2006604312:icl */
+static void
+icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, int pipe, bool
enable)
+{
+ if (enable)
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
+ else
+ I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
+}
+
static bool
needs_modeset(const struct drm_crtc_state *state)
{
@@ -5495,6 +5508,16 @@ static bool needs_nv12_wa(struct drm_i915_private
*dev_priv,
return false;
}
+static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *crtc_state)
+{
+ /* Wa_2006604312:icl */
+ if (crtc_state->pch_pfit.enabled && IS_ICELAKE(dev_priv))
+ return true;
+
+ return false;
+}
+
static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
@@ -5528,11 +5551,13 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
intel_post_enable_primary(&crtc->base, pipe_config);
}
- /* Display WA 827 */
if (needs_nv12_wa(dev_priv, old_crtc_state) &&
- !needs_nv12_wa(dev_priv, pipe_config)) {
+ !needs_nv12_wa(dev_priv, pipe_config))
skl_wa_827(dev_priv, crtc->pipe, false);
- }
+
+ if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
+ !needs_scalerclk_wa(dev_priv, pipe_config))
+ icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
}
static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
@@ -5568,10 +5593,14 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
}
/* Display WA 827 */
- if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
- needs_nv12_wa(dev_priv, pipe_config)) {
+ if (needs_nv12_wa(dev_priv, old_crtc_state) &&
+ !needs_nv12_wa(dev_priv, pipe_config))
skl_wa_827(dev_priv, crtc->pipe, true);
- }
+
+ /* Wa_2006604312:icl */
+ if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
+ !needs_scalerclk_wa(dev_priv, pipe_config))
+ icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
/*
* Vblank time updates from the shadow to live plane control register
--
2.20.0.rc2.7.g965798d1f299
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[Intel-gfx] [PATCH v5 2/3] drm/i915: Fix the inconsistent RMW in WA 827
RMW is used only in the disable path. Using it in enable path
for consistency.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 30aa1e5324f7..f54183761a40 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -471,6 +471,7 @@ skl_wa_827(struct drm_i915_private *dev_priv, int pipe,
bool enable)
{
if (enable)
I915_WRITE(CLKGATE_DIS_PSL(pipe),
+ I915_READ(CLKGATE_DIS_PSL(pipe)) |
DUPS1_GATING_DIS | DUPS2_GATING_DIS);
else
I915_WRITE(CLKGATE_DIS_PSL(pipe),
--
2.20.0.rc2.7.g965798d1f299
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[Intel-gfx] [PATCH v5 1/3] drm/i915: Rename skl_wa_clkgating to the actual WA
No functional change. Renaming the function to reflect the specific WA.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..30aa1e5324f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -467,7 +467,7 @@ static const struct intel_limit intel_limits_bxt = {
};
static void
-skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)
+skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool enable)
{
if (enable)
I915_WRITE(CLKGATE_DIS_PSL(pipe),
@@ -5530,7 +5530,7 @@ static void intel_post_plane_update(struct
intel_crtc_state *old_crtc_state)
/* Display WA 827 */
if (needs_nv12_wa(dev_priv, old_crtc_state) &&
!needs_nv12_wa(dev_priv, pipe_config)) {
- skl_wa_clkgate(dev_priv, crtc->pipe, false);
+ skl_wa_827(dev_priv, crtc->pipe, false);
}
}
@@ -5569,7 +5569,7 @@ static void intel_pre_plane_update(struct
intel_crtc_state *old_crtc_state,
/* Display WA 827 */
if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
needs_nv12_wa(dev_priv, pipe_config)) {
- skl_wa_clkgate(dev_priv, crtc->pipe, true);
+ skl_wa_827(dev_priv, crtc->pipe, true);
}
/*
--
2.20.0.rc2.7.g965798d1f299
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Engine relative MMIO (rev3)
== Series Details == Series: drm/i915: Engine relative MMIO (rev3) URL : https://patchwork.freedesktop.org/series/57117/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12640 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57117/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12640 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#107362] * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182] Possible fixes * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: FAIL [fdo#104008] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (50 -> 42) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5840 -> Patchwork_12640 CI_DRM_5840: db336fee1090f4207856469e57d04bcf56fe9e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4913: e408d569973b610ba4aafdba016c48b25e563468 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12640: a3f3b4a23cc5437903bbef7ff6e7af7000949f14 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a3f3b4a23cc5 drm/i915: Engine relative MMIO == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12640/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Retry GuC load for all load failures
== Series Details == Series: drm/i915/guc: Retry GuC load for all load failures URL : https://patchwork.freedesktop.org/series/58758/ State : success == Summary == CI Bug Log - changes from CI_DRM_5839_full -> Patchwork_12636_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12636_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@bsd1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +156 * igt@gem_exec_store@cachelines-bsd1: - shard-snb: NOTRUN -> SKIP [fdo#109271] +129 * igt@gem_softpin@noreloc-s3: - shard-apl: PASS -> DMESG-WARN [fdo#108566] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@kms_atomic_transition@5x-modeset-transitions-fencing: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14 * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-pageflip-hang-newfb-render-c: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +17 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-iclb: PASS -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@hdmi-hpd-after-suspend: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_cursor_crc@cursor-512x512-random: - shard-apl: NOTRUN -> SKIP [fdo#109271] +23 * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +1 * igt@kms_flip@flip-vs-expired-vblank: - shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_flip@modeset-vs-vblank-race: - shard-apl: PASS -> FAIL [fdo#103060] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#103167] +11 * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-skl: NOTRUN -> FAIL [fdo#105683] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-skl: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: PASS -> FAIL [fdo#109247] +10 * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_psr2_su@page_flip: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +6 * igt@kms_psr@primary_render: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +2 * igt@kms_psr@psr2_sprite_blt: - shard-iclb: PASS -> SKIP [fdo#109441] +1 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] * igt@prime_busy@wait-after-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +1 Possible fixes * igt@gem_create@create-clear: - shard-snb: INCOMPLETE [fdo#105411] -> PASS - shard-iclb: INCOMPLETE [fdo#109100] -> PASS * igt@gem_mmap_gtt@hang: - shard-iclb: FAIL [fdo#109677] -> PASS * igt@i915_pm_rpm@system-suspend: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] / [fdo#107807] -> PASS * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-kbl: INCOMPLETE [fdo#103665] -> PASS * igt@kms_cursor_crc@cursor-256x85-onscreen: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-iclb: FAIL [fdo#103355] -> PASS * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-glk: FAIL [fdo#103060] -> PASS +1 * igt@kms_flip@flip-vs-suspend: - shard-snb: DMESG-WARN [fdo#102365] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: FAIL [fdo#103167] -> PASS +5 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu: - shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS * igt@kms_frontbuf
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix clockgating issue when using scalars (rev5)
== Series Details == Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5) URL : https://patchwork.freedesktop.org/series/58081/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12641 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58081/revisions/5/mbox/ Known issues Here are the changes found in Patchwork_12641 that come from known issues: ### IGT changes ### Issues hit * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@prime_vgem@basic-fence-flip: - fi-icl-u3: FAIL [fdo#104008] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (50 -> 42) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-bdw-samus Build changes - * Linux: CI_DRM_5840 -> Patchwork_12641 CI_DRM_5840: db336fee1090f4207856469e57d04bcf56fe9e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4913: e408d569973b610ba4aafdba016c48b25e563468 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12641: 74365944dd6b06fd27bdd8e9153965e686c39a6f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 74365944dd6b drm/i915/icl: Fix clockgating issue when using scalers c6a6b19159ab drm/i915: Fix the inconsistent RMW in WA 827 9041bfaf4bf9 drm/i915: Rename skl_wa_clkgating to the actual WA == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12641/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Retry GuC load for all load failures (rev2)
== Series Details == Series: drm/i915/guc: Retry GuC load for all load failures (rev2) URL : https://patchwork.freedesktop.org/series/58758/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12639_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12639_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> SKIP [fdo#109271] +83 * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +156 * igt@gem_mmap_gtt@big-copy: - shard-iclb: PASS -> TIMEOUT [fdo#109673] * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-iclb: PASS -> INCOMPLETE [fdo#109801] * igt@gem_wait@write-busy-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait: - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] * igt@kms_atomic_transition@3x-modeset-transitions-fencing: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7 * igt@kms_chamelium@dp-hpd-fast: - shard-iclb: NOTRUN -> SKIP [fdo#109284] * igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 * igt@kms_cursor_crc@cursor-512x170-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +2 * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +63 * igt@kms_flip@dpms-vs-vblank-race-interruptible: - shard-glk: PASS -> FAIL [fdo#103060] * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#103167] +9 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: PASS -> FAIL [fdo#109247] +20 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +3 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-kbl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_cursor_render: - shard-iclb: PASS -> SKIP [fdo#109441] +4 * igt@kms_psr@sprite_mmap_cpu: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +3 * igt@kms_setmode@basic: - shard-iclb: NOTRUN -> FAIL [fdo#99912] - shard-kbl: NOTRUN -> FAIL [fdo#99912] - shard-snb: NOTRUN -> FAIL [fdo#99912] * igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: PASS -> FAIL [fdo#104894] +2 * igt@prime_udl: - shard-iclb: NOTRUN -> SKIP [fdo#109291] Possible fixes * igt@gem_eio@in-flight-suspend: - shard-snb: FAIL [fdo#103375] -> PASS * igt@i915_suspend@forcewake: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: FAIL [fdo#103355] -> PASS * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-ytiled: - shard-glk: FAIL [fdo#107791] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-iclb: FAIL [fdo#109247] -> PASS +12 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-iclb:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Engine relative MMIO (rev3)
== Series Details == Series: drm/i915: Engine relative MMIO (rev3) URL : https://patchwork.freedesktop.org/series/57117/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12640_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12640_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries_display_off: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] * igt@gem_ctx_isolation@vecs0-s3: - shard-apl: PASS -> DMESG-WARN [fdo#108566] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +111 * igt@gem_wait@write-busy-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@i915_pm_rpm@i2c: - shard-iclb: PASS -> DMESG-WARN [fdo#109982] * igt@kms_atomic_transition@3x-modeset-transitions-fencing: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +4 * igt@kms_chamelium@dp-hpd-fast: - shard-iclb: NOTRUN -> SKIP [fdo#109284] * igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13 * igt@kms_cursor_crc@cursor-512x170-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +2 * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: PASS -> FAIL [fdo#104873] * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +63 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-apl: PASS -> FAIL [fdo#102887] / [fdo#105363] * igt@kms_flip@plain-flip-fb-recreate-interruptible: - shard-skl: PASS -> FAIL [fdo#100368] * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#109247] +14 * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-kbl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@no_drrs: - shard-iclb: PASS -> FAIL [fdo#108341] * igt@kms_psr@psr2_cursor_render: - shard-iclb: PASS -> SKIP [fdo#109441] +4 * igt@kms_psr@psr2_dpms: - shard-iclb: NOTRUN -> SKIP [fdo#109441] * igt@kms_psr@sprite_plane_onoff: - shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +1 * igt@kms_setmode@basic: - shard-iclb: NOTRUN -> FAIL [fdo#99912] - shard-kbl: NOTRUN -> FAIL [fdo#99912] - shard-snb: NOTRUN -> FAIL [fdo#99912] * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_vblank@pipe-b-ts-continuation-modeset-rpm: - shard-apl: PASS -> FAIL [fdo#104894] +1 * igt@perf@blocking: - shard-iclb: PASS -> FAIL [fdo#108587] * igt@prime_udl: - shard-iclb: NOTRUN -> SKIP [fdo#109291] Possible fixes * igt@gem_eio@in-flight-suspend: - shard-snb:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Fix clockgating issue when using scalars (rev5)
== Series Details == Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5) URL : https://patchwork.freedesktop.org/series/58081/ State : success == Summary == CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12641_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_12641_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12641_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12641_full: ### IGT changes ### Warnings * igt@syncobj_wait@invalid-reset-illegal-handle: - shard-skl: PASS -> ( 2 PASS ) +5 Known issues Here are the changes found in Patchwork_12641_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-skl: NOTRUN -> SKIP [fdo#109271] +65 * igt@gem_exec_schedule@preempt-other-chain-blt: - shard-snb: NOTRUN -> SKIP [fdo#109271] +111 * igt@gem_exec_schedule@wide-render: - shard-iclb: PASS -> FAIL [fdo#109633] * igt@gem_partial_pwrite_pread@writes-after-reads-uncached: - shard-iclb: NOTRUN -> TIMEOUT [fdo#109673] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> DMESG-WARN [fdo#108686] * igt@gem_wait@write-busy-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +3 * igt@kms_atomic_transition@3x-modeset-transitions-fencing: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-e: - shard-kbl: NOTRUN -> SKIP [fdo#105602] / [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-hpd-fast: - shard-iclb: NOTRUN -> SKIP [fdo#109284] * igt@kms_chv_cursor_fail@pipe-c-256x256-bottom-edge: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13 * igt@kms_color@pipe-b-ctm-negative: - shard-kbl: PASS -> DMESG-FAIL [fdo#103558] / [fdo#105602] * igt@kms_cursor_crc@cursor-512x170-onscreen: - shard-iclb: NOTRUN -> SKIP [fdo#109279] * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +2 * igt@kms_fbcon_fbt@fbc: - shard-iclb: PASS -> DMESG-WARN [fdo#109593] * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +57 * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: - shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +28 * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-iclb: PASS -> FAIL [fdo#103167] +7 * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +5 * igt@kms_frontbuffer_tracking@fbcpsr-badstride: - shard-kbl: NOTRUN -> SKIP [fdo#105602] / [fdo#109271] +5 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#109247] +2 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +12 * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-kbl: NOTRUN -> DMESG-FAIL [fdo#103558] / [fdo#105602] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: NOTRUN -> FAIL [fdo#108145] +2 * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] * igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-glk: PASS -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#10964
Re: [Intel-gfx] [PATCH v4 4/8] drm/i915: vgpu context submission pv optimization
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> It is performance optimization to override the actual submisison backend
> in order to eliminate execlists csb process and reduce mmio trap numbers
> for workload submission without contextswith interrupt by talking with
> GVT via PV submisison notification mechanism between guest and GVT.
> Use PV_SUBMISSION to control this level of pv optimization.
>
> v0: RFC
> v1: rebase
> v2: added pv ops for pv context submission. to maximize code resuse,
> introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
> (set_default_submission) in engine structure. pv version of
> submit_ports and preempt_context implemented.
> v3:
> 1. to reduce more code duplication, code refactor and replaced 2 ops
> "submit_ports & preempt_contex" from v2 by 1 ops "write_desc"
> in engine structure. pv version of write_des implemented.
> 2. added VGT_G2V_ELSP_SUBMIT for g2v pv notification.
> v4: implemented pv elsp submission tasklet as the backend workload
> submisison by talking to GVT with PV notificaiton mechanism and renamed
> VGT_G2V_ELSP_SUBMIT to VGT_G2V_PV_SUBMISIION.
>
> Signed-off-by: Xiaolin Zhang
> ---
> drivers/gpu/drm/i915/i915_irq.c| 2 +
> drivers/gpu/drm/i915/i915_pvinfo.h | 1 +
> drivers/gpu/drm/i915/i915_vgpu.c | 158
> -
> drivers/gpu/drm/i915/i915_vgpu.h | 10 +++
> drivers/gpu/drm/i915/intel_lrc.c | 3 +
> 5 files changed, 173 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f78829..28e8ee0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -37,6 +37,7 @@
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "intel_drv.h"
> +#include "i915_vgpu.h"
>
> /**
> * DOC: interrupt handling
> @@ -1470,6 +1471,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
> iir)
> if (iir & GT_RENDER_USER_INTERRUPT) {
> intel_engine_breadcrumbs_irq(engine);
> tasklet |= USES_GUC_SUBMISSION(engine->i915);
> + tasklet |= USES_PV_SUBMISSION(engine->i915);
You call this an optimisation!
-Chris
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Finish the GAMMA_LUT stuff
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff
URL : https://patchwork.freedesktop.org/series/58698/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12623_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12623_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12623_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12623_full:
### IGT changes ###
Possible regressions
* igt@kms_color@pipe-b-ctm-green-to-red:
- shard-iclb: PASS -> DMESG-WARN +10
* igt@kms_color@pipe-c-ctm-0-25:
- shard-iclb: NOTRUN -> DMESG-WARN
* igt@kms_color@pipe-invalid-lut-sizes:
- shard-snb: PASS -> FAIL
Warnings
* igt@kms_color@pipe-a-degamma:
- shard-iclb: FAIL [fdo#104782] -> DMESG-FAIL +1
* igt@kms_color@pipe-c-ctm-max:
- shard-iclb: FAIL [fdo#108147] -> DMESG-FAIL +1
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@pixel-format-pipe-a-planes}:
- shard-iclb: PASS -> FAIL +5
Known issues
Here are the changes found in Patchwork_12623_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@bcs0-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-iclb: PASS -> TIMEOUT [fdo#109673] +2
* igt@i915_pm_rpm@i2c:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@legacy-planes:
- shard-iclb: PASS -> INCOMPLETE [fdo#108840] / [fdo#109369]
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-iclb: PASS -> DMESG-WARN [fdo#109638]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-glk: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1
* igt@kms_chamelium@hdmi-crc-abgr:
- shard-iclb: NOTRUN -> SKIP [fdo#109284]
* igt@kms_color@pipe-b-legacy-gamma:
- shard-iclb: PASS -> FAIL [fdo#104782] +2
* igt@kms_cursor_crc@cursor-128x128-dpms:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic:
- shard-iclb: PASS -> FAIL [fdo#103355]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#109507]
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-iclb: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-iclb: PASS -> FAIL [fdo#109247] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +100
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7
* igt@kms_plane@plane-panning-bottom-right-pipe-c-planes:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr@cursor_mmap_cpu:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215]
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-iclb: PASS -> FAIL [fdo#104894]
* igt@perf@blocking:
- shard-iclb: PASS -> FAIL [fdo#108587] +1
* igt@perf_pmu@busy-accuracy-50-vcs1:
-
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h (rev5)
== Series Details ==
Series: drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h (rev5)
URL : https://patchwork.freedesktop.org/series/58052/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12624_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12624_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_workarounds@suspend-resume:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +8
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-glk: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1
* igt@kms_content_protection@legacy:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +71
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@perf_pmu@busy-accuracy-50-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +80
* igt@perf_pmu@busy-hang-vcs1:
- shard-apl: NOTRUN -> SKIP [fdo#109271]
Possible fixes
* igt@kms_cursor_crc@cursor-128x128-suspend:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-glk: FAIL [fdo#107791] -> PASS
* igt@kms_flip@busy-flip:
- shard-skl: FAIL [fdo#103257] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* {igt@kms_plane@pixel-format-pipe-a-planes-source-clamping}:
- shard-glk: SKIP [fdo#109271] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103257]: https://bugs.freedesktop.org/show_bug.cgi?id=103257
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 8)
--
Missing(2): shard-hsw shard-iclb
Build changes
-
* Linux: CI_DRM_5832 -> Patchwork_12624
CI_DRM_5832: f1fc30ad3723a8b6265c2edf50a7f637ecd75a23 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12624: bd4fcb4edac9380ff47cc2e9ce17687ec197b755 @
git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12624/
___
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Re: [Intel-gfx] [PATCH] drm/i915: adding state checker for gamma lut values
On Thu, 28 Mar 2019, Matt Roper wrote: > I agree with Jani's feedback and have a couple other comments inline below. Thanks Matt, good stuff here. One naming note below. > What does the "internal" in this name refer to? I think just something > like i9xx_get_gamma_config() would be sufficient > > Actually the term "gamma_config" on these functions makes me think we're > going to be reading out the gamma mode register as well, although that's > actually done in foo_get_pipe_config(). Maybe just calling this > something like "i9xx_get_gamma_lut()" or "i9xx_readout_gamma_lut()" > would be more clear? I'd like to retain "get" and "config" in the names, just to mentally map to what's going on. Having "gamma lut" in there is good too to distinguish from *_get_pipe_config(). BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] Device id consolidation
On 28/03/2019 09:39, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-03-28 09:23:24) On 26/03/2019 07:40, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Series removes device id checks from i915_drv.h macros and consolidates them to i915_pciids.h as the main "database", while making intel_device_info.c reference the former, expanding the existing concept of a platform mask by a few low bits reserved for sub-platform mask. This has a two-fold positive effect of firstly consolidating the list of device ids to one location, and secondly removing the if-ladders from every IS__ call site. Maintenance burden is not completely removed but should be improved. One case in point is that I have found some disagreements between device id listed in i915_pciids.h and i915_drv.h. At the same time platform mask code is generalized to an array of u32 to accomodate the addition of EHL and avoid spilling into u64 which would cause a small code size increase. Downside is that any platforms on the u32 boundary, like currently ICL and EHL, lose the benefit of optimizing the "IS_ICELAKE || IS_ELKHARTLAKE" checks into a single conditional, although at the moment there aren't any such call-sites. Before vs after for the whole series: textdata bss dec hex filename 1891093 439037424 1942420 1da394 i915.ko.0 1890434 439037424 1941761 1da101 i915.ko.1 add/remove: 12/3 grow/shrink: 92/121 up/down: 1974/-1769 (205) ... Total: Before=1286293, After=1286498, chg +0.02% After patch 4 v8: textdata bss dec hex filename 1904423 438917424 1955738 1dd79a i915.ko.0 1903354 438917424 1954669 1dd36d i915.ko.1 add/remove: 8/3 grow/shrink: 94/124 up/down: 1623/-1889 (-266) ... Total: Before=1293823, After=1293557, chg -0.02% The series is an improvement, both for the reader and for the compiler, Reviewed-by: Chris Wilson Thanks. Jani, Lucas? Passable? Still some objections? Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0x.
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Shashank Sharma
Cc: "Kumar, Kiran S"
Cc: Kausal Malladi
Cc: Lionel Landwerlin
Cc: Matt Roper
Cc: Rob Bradford
Cc: Daniel Stone
Cc: Stefan Schake
Cc: Eric Anholt
Cc: Maarten Lankhorst
Cc: Harry Wentland
Cc: Leo Li
Cc: amd-...@lists.freedesktop.org
Cc: James (Qian) Wang
Cc: Liviu Dudau
Cc: Mali DP Maintainers
Cc: CK Hu
Cc: Philipp Zabel
Cc: Yannick Fertre
Cc: Philippe Cornu
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Cc: Tomi Valkeinen
Cc: Boris Brezillon
Signed-off-by: Daniel Vetter Signed-off-by: Daniel
Vetter
---
include/uapi/drm/drm_mode.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 09d72966899a..83cd1636b9be 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -621,7 +621,8 @@ struct drm_color_ctm {
struct drm_color_lut {
/*
-* Data is U0.16 fixed point format.
+* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
+* 0x == 1.0.
*/
__u16 red;
__u16 green;
--
2.20.1
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Re: [Intel-gfx] [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform
On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Concept of a sub-platform already exist in our code (like ULX and ULT
> platform variants and similar),implemented via the macros which check a
> list of device ids to determine a match.
>
> With this patch we consolidate device ids checking into a single function
> called during early driver load.
>
> A few low bits in the platform mask are reserved for sub-platform
> identification and defined as a per-platform namespace.
>
> At the same time it future proofs the platform_mask handling by preparing
> the code for easy extending, and tidies the very verbose WARN strings
> generated when IS_PLATFORM macros are embedded into a WARN type
> statements.
>
> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
> v3: Chris was right, there is an ordering problem.
>
> v4:
> * Catch-up with new sub-platforms.
> * Rebase for RUNTIME_INFO.
> * Drop subplatform mask union tricks and convert platform_mask to an
>array for extensibility.
>
> v5:
> * Fix subplatform check.
> * Protect against forgetting to expand subplatform bits.
> * Remove platform enum tallying.
> * Add subplatform to error state. (Chris)
> * Drop macros and just use static inlines.
> * Remove redundant IRONLAKE_M. (Ville)
>
> v6:
> * Split out Ironlake change.
> * Optimize subplatform check.
> * Use __always_inline. (Lucas)
> * Add platform_mask comment. (Paulo)
> * Pass stored runtime info in error capture. (Chris)
>
> v7:
> * Rebased for new AML ULX device id.
> * Bump platform mask array size for EHL.
> * Stop mentioning device ids in intel_device_subplatform_init by using
>the trick of splitting macros i915_pciids.h. (Jani)
> * AML seems to be either a subplatform of KBL or CFL so express it like
>that.
>
> v8:
> * Use one device id table per subplatform. (Jani)
>
> Signed-off-by: Tvrtko Ursulin
> Suggested-by: Chris Wilson
> Cc: Chris Wilson
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Jose Souza
> Cc: Ville Syrjälä
> Cc: Paulo Zanoni
> Reviewed-by: Chris Wilson # v6
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8 +-
> drivers/gpu/drm/i915/i915_drv.h | 123 ---
> drivers/gpu/drm/i915/i915_gpu_error.c| 3 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 93 +
> drivers/gpu/drm/i915/intel_device_info.h | 27 -
> 6 files changed, 214 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f1334f5d4ead..74734d7661e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private
> *dev_priv)
> if (i915_inject_load_failure())
> return -ENODEV;
>
> + intel_device_info_subplatform_init(dev_priv);
> +
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> mutex_init(&dev_priv->backlight_lock);
> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct
> drm_i915_private *dev_priv)
> if (drm_debug & DRM_UT_DRIVER) {
> struct drm_printer p = drm_debug_printer("i915 device info:");
>
> - drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
> + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
> (subplatform=0x%x) gen=%i\n",
> INTEL_DEVID(dev_priv),
> INTEL_REVID(dev_priv),
> intel_platform_name(INTEL_INFO(dev_priv)->platform),
> +intel_subplatform(RUNTIME_INFO(dev_priv),
> + INTEL_INFO(dev_priv)->platform),
> INTEL_GEN(dev_priv));
>
> intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct
> pci_device_id *ent)
> memcpy(device_info, match_info, sizeof(*device_info));
> RUNTIME_INFO(i915)->device_id = pdev->device;
>
> - BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> - BITS_PER_TYPE(device_info->platform_mask));
> BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>
> return i915;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9d3cab9406e1..b7d3f3a45ed9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
> -#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask &
> BIT(p))
> +static __always_inline unsigned int
> +__platform_mask_index(const struct intel_runtime_info *info,
> + enum intel_platform p)
> +{
> + const unsigned int
[Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Verify that using HW semaphores doesn't block
We may use HW semaphores to schedule nearly-ready work such that they
are already spinning on the GPU waiting for the completion on another
engine. However, we don't want for that spinning task to actually block
any real work should it be scheduled.
v2: No typeof autos
v3: Don't cheat, check gen8 as well
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/gem_exec_schedule.c | 87 ++
1 file changed, 87 insertions(+)
diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c
index 4f0577b4e..3df319bcc 100644
--- a/tests/i915/gem_exec_schedule.c
+++ b/tests/i915/gem_exec_schedule.c
@@ -48,6 +48,10 @@
#define MAX_CONTEXTS 1024
+#define LOCAL_I915_EXEC_BSD_SHIFT (13)
+#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
+#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
+
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
static inline
@@ -320,6 +324,86 @@ static void smoketest(int fd, unsigned ring, unsigned
timeout)
}
}
+static uint32_t __batch_create(int i915, uint32_t offset)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(i915, ALIGN(offset + 4, 4096));
+ gem_write(i915, handle, offset, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static uint32_t batch_create(int i915)
+{
+ return __batch_create(i915, 0);
+}
+
+static void semaphore_userlock(int i915)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = batch_create(i915),
+ };
+ igt_spin_t *spin = NULL;
+ unsigned int engine;
+ uint32_t scratch;
+
+ igt_require(gem_scheduler_has_semaphores(i915));
+
+ /*
+* Given the use of semaphores to govern parallel submission
+* of nearly-ready work to HW, we still want to run actually
+* ready work immediately. Without semaphores, the dependent
+* work wouldn't be submitted so our ready work will run.
+*/
+
+ scratch = gem_create(i915, 4096);
+ for_each_physical_engine(i915, engine) {
+ if (!spin) {
+ spin = igt_spin_batch_new(i915,
+ .dependency = scratch,
+ .engine = engine);
+ } else {
+ uint64_t saved = spin->execbuf.flags;
+
+ spin->execbuf.flags &= ~ENGINE_MASK;
+ spin->execbuf.flags |= engine;
+
+ gem_execbuf(i915, &spin->execbuf);
+
+ spin->execbuf.flags = saved;
+ }
+ }
+ igt_require(spin);
+ gem_close(i915, scratch);
+
+ /*
+* On all dependent engines, the request may be executing (busywaiting
+* on a HW semaphore) but it should not prevent any real work from
+* taking precedence.
+*/
+ scratch = gem_context_create(i915);
+ for_each_physical_engine(i915, engine) {
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = engine,
+ .rsvd1 = scratch,
+ };
+
+ if (engine == (spin->execbuf.flags & ENGINE_MASK))
+ continue;
+
+ gem_execbuf(i915, &execbuf);
+ }
+ gem_context_destroy(i915, scratch);
+ gem_sync(i915, obj.handle); /* to hang unless we can preempt */
+ gem_close(i915, obj.handle);
+
+ igt_spin_batch_free(i915, spin);
+}
+
static void reorder(int fd, unsigned ring, unsigned flags)
#define EQUAL 1
{
@@ -1307,6 +1391,9 @@ igt_main
igt_require(gem_scheduler_has_ctx_priority(fd));
}
+ igt_subtest("semaphore-user")
+ semaphore_userlock(fd);
+
igt_subtest("smoketest-all")
smoketest(fd, ALL_ENGINES, 30);
--
2.20.1
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add 10bit LUT for ilk/snb
Op 28-03-2019 om 22:05 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Plop in support for 10bit LUT on ilk/snb.
>
> There is no split gamma mode on these platforms, so we have
> to choose between degamma and gamma. That could be a runtime choice
> but for now let's just advertize the gamma as having 1024 entries.
> We'll also keep the ctm hidden for now.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_pci.c| 4 +++
> drivers/gpu/drm/i915/i915_reg.h| 9 ++
> drivers/gpu/drm/i915/intel_color.c | 44 ++
> 3 files changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 385056752939..0971eee4a4d1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -116,6 +116,8 @@
> [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> }
>
> +#define ILK_COLORS \
> + .color = { .gamma_lut_size = 1024 }
> #define IVB_COLORS \
> .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
> #define CHV_COLORS \
> @@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = {
> .has_rc6 = 0, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES
>
> static const struct intel_device_info intel_ironlake_d_info = {
> @@ -353,6 +356,7 @@ static const struct intel_device_info
> intel_ironlake_m_info = {
> .ppgtt_size = 31, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> + ILK_COLORS, \
> GEN_DEFAULT_PAGE_SIZES
>
> #define SNB_D_PLATFORM \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eb7e93354cfe..f6a5d8f11368 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7209,6 +7209,15 @@ enum {
> #define _LGC_PALETTE_B 0x4a800
> #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A,
> _LGC_PALETTE_B) + (i) * 4)
>
> +/* ilk/snb precision palette */
> +#define _PREC_PALETTE_A 0x4b000
> +#define _PREC_PALETTE_B 0x4c000
> +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A,
> _PREC_PALETTE_B) + (i) * 4)
> +
> +#define _PREC_PIPEAGCMAX 0x4d000
> +#define _PREC_PIPEBGCMAX 0x4d010
> +#define PREC_PIPEGCMAX(pipe, i)_MMIO(_PIPE(pipe, _PIPEAGCMAX,
> _PIPEBGCMAX) + (i) * 4)
> +
> #define _GAMMA_MODE_A0x4a480
> #define _GAMMA_MODE_B0x4ac80
> #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 70a71c92e3e5..8e03f066adf7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -468,6 +468,29 @@ static void skl_color_commit(const struct
> intel_crtc_state *crtc_state)
> ilk_load_csc_matrix(crtc_state);
> }
>
> +static void ilk_load_lut_10(struct intel_crtc *crtc,
> + const struct drm_property_blob *blob)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + const struct drm_color_lut *lut = blob->data;
> + int i, lut_size = drm_color_lut_size(blob);
> + enum pipe pipe = crtc->pipe;
> +
> + for (i = 0; i < lut_size; i++)
> + I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i]));
> +}
> +
> +static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> +
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + i9xx_load_luts(crtc_state);
> + else
> + ilk_load_lut_10(crtc, gamma_lut);
> +}
> +
> /*
> * IVB/HSW Bspec / PAL_PREC_INDEX:
> * "Restriction : Index auto increment mode is not
> @@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state
> *crtc_state)
> return 0;
> }
>
> +static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->gamma_enable ||
> + crtc_state_is_legacy_gamma(crtc_state))
> + return GAMMA_MODE_MODE_8BIT;
> + else
> + return GAMMA_MODE_MODE_10BIT;
> +}
> +
> static int ilk_color_check(struct intel_crtc_state *crtc_state)
> {
> int ret;
> @@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state
> *crtc_state)
>*/
> crtc_state->csc_enable = false;
>
> - /* We don't expose fancy gamma modes on ilk/snb currently */
> - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> + crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
>
> crtc_state->csc_mode = 0;
>
> @@ -1178,14 +1209,15 @@ void intel_color_init(struct intel_crtc *crtc)
> else if (INTEL_GEN(dev_priv) >= 7)
> dev_priv->d
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/gamma: Clarify gamma lut uapi
== Series Details == Series: drm/gamma: Clarify gamma lut uapi URL : https://patchwork.freedesktop.org/series/58718/ State : success == Summary == CI Bug Log - changes from CI_DRM_5835 -> Patchwork_12626 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58718/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12626 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_gttfill@basic: - fi-skl-gvtdvm: NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_suspend@basic-s3: - fi-icl-u3: PASS -> FAIL [fdo#103375] - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@gem_workarounds@basic-read: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57 * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] +1 * igt@kms_busy@basic-flip-c: - fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 - fi-skl-6600u: NOTRUN -> SKIP [fdo#109271] +31 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: PASS -> FAIL [fdo#103167] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@gem_exec_suspend@basic-s4-devices: - fi-skl-6600u: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (43 -> 41) -- Additional (3): fi-hsw-4770r fi-skl-gvtdvm fi-snb-2600 Missing(5): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-icl-dsi fi-bdw-samus Build changes - * Linux: CI_DRM_5835 -> Patchwork_12626 CI_DRM_5835: a87cb5da301d892d69d44b106a007caea8386935 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4911: d9fe699ea45406e279b78d1afdb4d57a205a3c99 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12626: eb8630f6603d1dec660988f98aaf839239178405 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == eb8630f6603d drm/gamma: Clarify gamma lut uapi == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12626/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
On Thu, Mar 28, 2019 at 05:16:03PM -0700, Matt Roper wrote:
> On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Using the split gamma mode when we don't have to has the annoying
> > requirement of loading a linear LUT to the unused half. Instead
> > let's make life simpler by switching to the 10bit gamma mode
> > and duplicating each entry.
> >
> > This also allows us to load the software gamma LUT into the
> > hardware degamma LUT, thus removing some of the buggy
> > configurations we currently allow (YCbCr/limited range RGB
> > + gamma LUT). We do still have other configurations that are
> > also buggy, but those will need more complicated fixes
> > or they just need to be rejected. Sadly GLK doesn't have
> > this flexibility anymore and the degamma and gamma LUTs
> > are very different so no help there.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/i915_reg.h| 1 +
> > drivers/gpu/drm/i915/intel_color.c | 159 +++--
> > 2 files changed, 86 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index c866379a521b..eb7e93354cfe 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10127,6 +10127,7 @@ enum skl_power_gate {
> > #define PAL_PREC_SPLIT_MODE (1 << 31)
> > #define PAL_PREC_AUTO_INCREMENT (1 << 15)
> > #define PAL_PREC_INDEX_VALUE_MASK(0x3ff << 0)
> > +#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
> > #define _PAL_PREC_DATA_A 0x4A404
> > #define _PAL_PREC_DATA_B 0x4AC04
> > #define _PAL_PREC_DATA_C 0x4B404
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index d7c38a2bbd8f..ed4bd9bd15f5 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -466,72 +466,32 @@ static void skl_color_commit(const struct
> > intel_crtc_state *crtc_state)
> > ilk_load_csc_matrix(crtc_state);
> > }
> >
> > -static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> > +static void bdw_load_lut_10(struct intel_crtc *crtc,
> > + const struct drm_property_blob *blob,
> > + u32 prec_index, bool duplicate)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > - u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > + const struct drm_color_lut *lut = blob->data;
> > + int i, lut_size = drm_color_lut_size(blob);
> > enum pipe pipe = crtc->pipe;
> >
> > - I915_WRITE(PREC_PAL_INDEX(pipe),
> > - PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> > -
> > - if (degamma_lut) {
> > - const struct drm_color_lut *lut = degamma_lut->data;
> > + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
> > + PAL_PREC_AUTO_INCREMENT);
> >
> > - for (i = 0; i < lut_size; i++)
> > - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> > - } else {
> > + /*
> > +* We advertize the split gamma sizes. When not using split
> > +* gamma we just duplicate each entry.
> > +*
> > +* TODO: expose the full LUT to userspace
>
> Any reason not to just do this immediately? Throwing away half the
> table entries if we decide we need split mode doesn't seem any harder
> than duplicating the entries when we decide we don't. The color
> management kerneldoc already explicitly recommends this approach for
> hardware that can support multiple gamma modes, so I don't think we need
> any new ABI to handle it.
Hmm. I guess that apporach could be doable. It might be a bit annoying
for userspace though if it expects a direct color visual. But at least
for X we won't use degamma/ctm anyway so seems like it should work out
just fine.
>
> > +*/
> > + if (duplicate) {
> > for (i = 0; i < lut_size; i++) {
> > - u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> > -
> > - I915_WRITE(PREC_PAL_DATA(pipe),
> > - (v << 20) | (v << 10) | v);
> > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> > }
> > - }
> > -}
> > -
> > -static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state,
> > u32 offset)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > - const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > - u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > - enum pipe pipe = crtc->pipe;
> > -
> >
Re: [Intel-gfx] RMW considered harmful (was: Re: [PATCH 2/2] drm/i915/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports)
On Thu, 28 Mar 2019, Manasi Navare wrote: > On Thu, Mar 28, 2019 at 11:18:56AM +0200, Jani Nikula wrote: >> On Fri, 22 Mar 2019, Manasi Navare wrote: >> > On Fri, Mar 22, 2019 at 09:28:01PM +0200, Jani Nikula wrote: >> >> On Fri, 22 Mar 2019, Ville Syrjälä wrote: >> >> > On Fri, Mar 22, 2019 at 11:44:21AM -0700, Manasi Navare wrote: >> >> >> On Fri, Mar 22, 2019 at 08:09:50PM +0200, Ville Syrjälä wrote: >> >> >> > In that case there is no point in doing a rmw. >> >> >> >> >> >> But isnt it always a good idea to do rmw? I mean what if the master >> >> >> select was set to something else earlier? >> >> > >> >> > RMW is the root of many evils. It should be avoided unless there is a >> >> > really compelling reason to use it. >> >> >> >> Hear, hear! >> >> >> >> We have the software state that we want to write to the hardware. If we >> >> use RMW to do this, it might all work by coincidence due to the old >> >> values in the registers, or it might just as well break by coincidence >> >> due to some garbage in the registers. >> >> >> >> In most cases, there should only be one place that writes a particular >> >> display register during modeset. Sometimes this isn't possible, and RMW >> >> is required. >> >> >> >> Some registers also have reserved bits potentially used by the hardware >> >> that must not be changed, and RMW is required. These are documented in >> >> bspec. >> >> >> >> BR, >> >> Jani. >> >> >> > >> > Thanks for the explanation. It does make sense now that we are doing a >> > full modeset, we should just be then writing the value directly? The >> > only concern I have is that say DSI code sets this somewhere els ein >> > the modeset path, then we would need to modify this to do RMW or >> > always make sure DSI also uses the same function for writing to this >> > reg. What do you suggest doing now? >> >> I think all encoders in a tile group are always of the same type. > > Yes all the encoders in tile group are always same type. > >> >> If the tile grouping in your patch is based purely on EDID, we may need >> to enforce this. Surely genlock only works on encoders of the same type? >> > > So all the slaves and their master will always be of same type and yes it is > based on the EDID tile block parsing. > But just to double sure I think when i assign the master slave pointers, I > should > check that the connector type is the same. > >> In any case DSI (at least currently) does not use tile groups, and will >> never be mixed up in non-DSI tile groups. The DSI transcoders are >> separate from other transcoders, so we're not writing the same registers >> here. >> >> --- >> >> Looking at the code, I am wondering if this should be pushed to encoder >> hooks instead of adding into crtc enable. > > As per the Bspec sequence, this needs to happen before enabling the > TRANS_DDI_FUNC_CTL and after the link training, so I put in the > crtc_enable hook, which encoder hooks are you suggesting adding this? Maybe go with what you have now first, this can be pushed to encoders later if needed. (I hope I don't regret this. ;) BR, Jani. > > Regards > Manasi >> >> BR, >> Jani. >> >> >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Finish the GAMMA_LUT stuff
On Fri, Mar 29, 2019 at 08:34:03AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Finish the GAMMA_LUT stuff
> URL : https://patchwork.freedesktop.org/series/58698/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12623_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_12623_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_12623_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_12623_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_color@pipe-b-ctm-green-to-red:
> - shard-iclb: PASS -> DMESG-WARN +10
<1> [1836.559333] BUG: unable to handle kernel NULL pointer dereference at
0048
<1> [1836.559337] #PF error: [normal kernel read fault]
<6> [1836.559339] PGD 0 P4D 0
<4> [1836.559342] Oops: [#1] PREEMPT SMP NOPTI
<4> [1836.559344] CPU: 6 PID: 4350 Comm: kms_color Tainted: G U
5.1.0-rc2-CI-Patchwork_12623+ #1
<4> [1836.559346] Hardware name: Intel Corporation Ice Lake Client
Platform/IceLake U DDR4 SODIMM PD RVP, BIOS ICLSFWR1.R00.3087.A00.1902250334
02/25/2019
<4> [1836.559391] RIP: 0010:bdw_load_lut_10+0x1b/0x130 [i915]
Whoops. Will need to be a bit more careful with gamma_mode on icl.
>
> * igt@kms_color@pipe-c-ctm-0-25:
> - shard-iclb: NOTRUN -> DMESG-WARN
>
> * igt@kms_color@pipe-invalid-lut-sizes:
> - shard-snb: PASS -> FAIL
>
>
> Warnings
>
> * igt@kms_color@pipe-a-degamma:
> - shard-iclb: FAIL [fdo#104782] -> DMESG-FAIL +1
>
> * igt@kms_color@pipe-c-ctm-max:
> - shard-iclb: FAIL [fdo#108147] -> DMESG-FAIL +1
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@kms_plane@pixel-format-pipe-a-planes}:
> - shard-iclb: PASS -> FAIL +5
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_12623_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_isolation@bcs0-s3:
> - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
>
> * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
> - shard-iclb: PASS -> TIMEOUT [fdo#109673] +2
>
> * igt@i915_pm_rpm@i2c:
> - shard-skl: PASS -> INCOMPLETE [fdo#107807]
>
> * igt@i915_pm_rpm@legacy-planes:
> - shard-iclb: PASS -> INCOMPLETE [fdo#108840] / [fdo#109369]
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-iclb: PASS -> DMESG-WARN [fdo#109638]
>
> * igt@kms_atomic_transition@3x-modeset-transitions:
> - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
> - shard-glk: PASS -> DMESG-WARN [fdo#110222]
>
> * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#110222] +1
>
> * igt@kms_chamelium@hdmi-crc-abgr:
> - shard-iclb: NOTRUN -> SKIP [fdo#109284]
>
> * igt@kms_color@pipe-b-legacy-gamma:
> - shard-iclb: PASS -> FAIL [fdo#104782] +2
>
> * igt@kms_cursor_crc@cursor-128x128-dpms:
> - shard-skl: NOTRUN -> FAIL [fdo#103232]
>
> * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
> - shard-iclb: PASS -> FAIL [fdo#103355]
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: NOTRUN -> FAIL [fdo#105363]
>
> * igt@kms_flip@flip-vs-suspend-interruptible:
> - shard-skl: NOTRUN -> INCOMPLETE [fdo#109507]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
> - shard-iclb: PASS -> FAIL [fdo#103167] +3
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
> - shard-skl: NOTRUN -> FAIL [fdo#103167]
>
> * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu:
> - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
> - shard-iclb: PASS -> FAIL [fdo#109247] +2
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
> - shard-snb: NOTRUN -> SKIP [fdo#109271] +100
>
> * igt@kms_panel_fitting@legacy:
> - shard-skl: NOTRUN -> FAIL [fdo#105456]
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-d:
> - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278
Re: [Intel-gfx] [v6 02/13] drm: Parse HDR metadata info from EDID
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 49 ++
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fa39592..fd8a621a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2840,6 +2840,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK 0x04
+#define HDR_STATIC_METADATA_BLOCK 0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
#define EXT_VIDEO_DATA_BLOCK_420 0x0E
@@ -3587,6 +3588,12 @@ static int add_3d_struct_modes(struct drm_connector
*connector, u16 structure,
}
static int
+cea_db_payload_len_ext(const u8 *db)
+{
+ return (db[0] & 0x1f) - 1;
+}
+
+static int
cea_db_extended_tag(const u8 *db)
{
return db[1];
@@ -3822,6 +3829,46 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
+{
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != HDR_STATIC_METADATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static uint8_t eotf_supported(const u8 *edid_ext)
+{
+ return edid_ext[2] &
+ (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+BIT(HDMI_EOTF_SMPTE_ST2084));
+}
+
+static uint8_t hdr_metadata_type(const u8 *edid_ext)
+{
+ return edid_ext[3] &
+ BIT(HDMI_STATIC_METADATA_TYPE1);
+}
+
+static void
+drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
+{
+ u16 len;
+
+ len = cea_db_payload_len_ext(db);
+ connector->hdr_metadata.eotf = eotf_supported(db);
+ connector->hdr_metadata.metadata_type = hdr_metadata_type(db);
+
+ if (len >= 5)
+ connector->hdr_metadata.max_fall = db[5];
+ if (len >= 4)
Little bike shed, If we pass >=5 we need not to compare >= 4, or we
should check >=4 first and then >=5 in sequence.
With that change ( and assuming you fixed the checkpatch stuff already),
please feel free to use:
Reviewed-by: Shashank Sharma
+ connector->hdr_metadata.max_cll = db[4];
+}
+
static void
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
@@ -4449,6 +4496,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_y420cmdb_bitmap(connector, db);
if (cea_db_is_vcdb(db))
drm_parse_vcdb(connector, db);
+ if (cea_db_is_hdmi_hdr_metadata_block(db))
+ drm_parse_hdr_metadata_block(connector, db);
}
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/
Currently, the Kbuild core manipulates header search paths in a crazy
way [1].
To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
the search paths in the srctree. Some Makefiles are already written in
that way, but not all. The goal of this work is to make the notation
consistent, and finally get rid of the gross hacks.
Having whitespaces after -I does not matter since commit 48f6e3cf5bc6
("kbuild: do not drop -I without parameter").
[1]: https://patchwork.kernel.org/patch/9632347/
Signed-off-by: Masahiro Yamada
Reviewed-by: Sam Ravnborg
---
I put all gpu/drm changes into a single patch because
they are trivial conversion.
If you are interested in the big picture of this work,
the full patch set is available at the following URL.
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
build-test
Changes in v2:
- fix up the new driver komeda
- Add Sam's Reviewed-by
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/lib/Makefile| 2 +-
drivers/gpu/drm/arm/display/komeda/Makefile | 4 ++--
drivers/gpu/drm/i915/gvt/Makefile | 2 +-
drivers/gpu/drm/msm/Makefile| 6 +++---
drivers/gpu/drm/nouveau/Kbuild | 8
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 466da59..62bf9da 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -23,7 +23,7 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-FULL_AMD_PATH=$(src)/..
+FULL_AMD_PATH=$(srctree)/$(src)/..
DISPLAY_FOLDER_NAME=display
FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)
diff --git a/drivers/gpu/drm/amd/lib/Makefile b/drivers/gpu/drm/amd/lib/Makefile
index 6902430..d534992 100644
--- a/drivers/gpu/drm/amd/lib/Makefile
+++ b/drivers/gpu/drm/amd/lib/Makefile
@@ -27,6 +27,6 @@
# driver components or later moved to kernel/lib for sharing with
# other drivers.
-ccflags-y := -I$(src)/../include
+ccflags-y := -I $(srctree)/$(src)/../include
obj-$(CONFIG_CHASH) += chash.o
diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
b/drivers/gpu/drm/arm/display/komeda/Makefile
index 1b875e5..a72e30c 100644
--- a/drivers/gpu/drm/arm/display/komeda/Makefile
+++ b/drivers/gpu/drm/arm/display/komeda/Makefile
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-y := \
- -I$(src)/../include \
- -I$(src)
+ -I $(srctree)/$(src)/../include \
+ -I $(srctree)/$(src)
komeda-y := \
komeda_drv.o \
diff --git a/drivers/gpu/drm/i915/gvt/Makefile
b/drivers/gpu/drm/i915/gvt/Makefile
index 271fb46..ea8324a 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -5,5 +5,5 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o
trace_points.o firmware.o \
execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o
debugfs.o \
fb_decoder.o dmabuf.o page_track.o
-ccflags-y += -I$(src) -I$(src)/$(GVT_DIR)
+ccflags-y += -I $(srctree)/$(src) -I
$(srctree)/$(src)/$(GVT_DIR)/
i915-y += $(addprefix $(GVT_DIR)/,
$(GVT_SOURCE))
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 56a70c7..b7b1ebd 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-ccflags-y := -Idrivers/gpu/drm/msm
-ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
-ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
+ccflags-y := -I $(srctree)/$(src)
+ccflags-y += -I $(srctree)/$(src)/disp/dpu1
+ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
msm-y := \
adreno/adreno_device.o \
diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild
index ea3035e..4fae728 100644
--- a/drivers/gpu/drm/nouveau/Kbuild
+++ b/drivers/gpu/drm/nouveau/Kbuild
@@ -1,7 +1,7 @@
-ccflags-y += -I$(src)/include
-ccflags-y += -I$(src)/include/nvkm
-ccflags-y += -I$(src)/nvkm
-ccflags-y += -I$(src)
+ccflags-y += -I $(srctree)/$(src)/include
+ccflags-y += -I $(srctree)/$(src)/include/nvkm
+ccflags-y += -I $(srctree)/$(src)/nvkm
+ccflags-y += -I $(srctree)/$(src)
# NVKM - HW resource manager
#- code also used by various userspace tools/tests
--
2.7.4
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Re: [Intel-gfx] [v6 07/13] drm/i915: Write HDR infoframe and send to panel
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation in compute config.
v6: Addressed Shashank's review comment. Added HDR metadata
support from GEN10 onwards as per Shashank's recommendation.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 41 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9f188e..c6c3cc7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1043,6 +1043,7 @@ struct intel_crtc_state {
union hdmi_infoframe avi;
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
+ union hdmi_infoframe drm;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f06237..e4bc7fc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -555,6 +555,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
HDMI_INFOFRAME_TYPE_AVI,
HDMI_INFOFRAME_TYPE_SPD,
HDMI_INFOFRAME_TYPE_VENDOR,
+ HDMI_INFOFRAME_TYPE_DRM,
};
u32 intel_hdmi_infoframe_enable(unsigned int type)
@@ -777,6 +778,30 @@ void intel_read_infoframe(struct intel_encoder *encoder,
return true;
}
+static bool
+intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state,
+struct drm_connector_state *conn_state)
+{
+ struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
+ struct hdr_static_metadata *hdr_metadata;
+ int ret;
+
+ hdr_metadata = (struct hdr_static_metadata *)
+ conn_state->hdr_output_metadata_blob_ptr->data;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(frame, hdr_metadata);
+ if (ret < 0) {
+ DRM_ERROR("couldn't set HDR metadata in infoframe\n");
+ return false;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
+
+ return true;
+}
+
static void g4x_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
@@ -1175,6 +1200,9 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_write_infoframe(encoder, crtc_state,
HDMI_INFOFRAME_TYPE_VENDOR,
&crtc_state->infoframes.hdmi);
+ intel_write_infoframe(encoder, crtc_state,
We should have a GEN check here also, else, there could be case where we
dint compute infoframes <=10 but wrote it, which will write garbage.
- Shashank
+ HDMI_INFOFRAME_TYPE_DRM,
+ &crtc_state->infoframes.drm);
}
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
@@ -2381,6 +2409,19 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
}
+ /*
+* Support HDR Metadata from Gen10 onwards
+* ToDo: Gen9 also can support HDR with LSPCON.
+* Support for the same to be enabled later.
+*/
+ if (INTEL_GEN(dev_priv) >= 10) {
+ if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config,
+ conn_state)) {
+ DRM_DEBUG_KMS("bad DRM infoframe\n");
+ return -EINVAL;
+ }
+ }
+
return 0;
}
___
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Re: [Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/
On Fri, Mar 29, 2019 at 08:32:41PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> that way, but not all. The goal of this work is to make the notation
> consistent, and finally get rid of the gross hacks.
>
> Having whitespaces after -I does not matter since commit 48f6e3cf5bc6
> ("kbuild: do not drop -I without parameter").
>
> [1]: https://patchwork.kernel.org/patch/9632347/
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Sam Ravnborg
> ---
>
> I put all gpu/drm changes into a single patch because
> they are trivial conversion.
>
> If you are interested in the big picture of this work,
> the full patch set is available at the following URL.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
> build-test
>
>
> Changes in v2:
> - fix up the new driver komeda
> - Add Sam's Reviewed-by
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/lib/Makefile| 2 +-
> drivers/gpu/drm/arm/display/komeda/Makefile | 4 ++--
> drivers/gpu/drm/i915/gvt/Makefile | 2 +-
> drivers/gpu/drm/msm/Makefile| 6 +++---
> drivers/gpu/drm/nouveau/Kbuild | 8
> 6 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 466da59..62bf9da 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -23,7 +23,7 @@
> # Makefile for the drm device driver. This driver provides support for the
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
>
> -FULL_AMD_PATH=$(src)/..
> +FULL_AMD_PATH=$(srctree)/$(src)/..
> DISPLAY_FOLDER_NAME=display
> FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)
>
> diff --git a/drivers/gpu/drm/amd/lib/Makefile
> b/drivers/gpu/drm/amd/lib/Makefile
> index 6902430..d534992 100644
> --- a/drivers/gpu/drm/amd/lib/Makefile
> +++ b/drivers/gpu/drm/amd/lib/Makefile
> @@ -27,6 +27,6 @@
> # driver components or later moved to kernel/lib for sharing with
> # other drivers.
>
> -ccflags-y := -I$(src)/../include
> +ccflags-y := -I $(srctree)/$(src)/../include
>
> obj-$(CONFIG_CHASH) += chash.o
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index 1b875e5..a72e30c 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -1,8 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
>
> ccflags-y := \
> - -I$(src)/../include \
> - -I$(src)
> + -I $(srctree)/$(src)/../include \
> + -I $(srctree)/$(src)
>
> komeda-y := \
> komeda_drv.o \
> diff --git a/drivers/gpu/drm/i915/gvt/Makefile
> b/drivers/gpu/drm/i915/gvt/Makefile
> index 271fb46..ea8324a 100644
> --- a/drivers/gpu/drm/i915/gvt/Makefile
> +++ b/drivers/gpu/drm/i915/gvt/Makefile
> @@ -5,5 +5,5 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o
> trace_points.o firmware.o \
> execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o
> debugfs.o \
> fb_decoder.o dmabuf.o page_track.o
>
> -ccflags-y+= -I$(src) -I$(src)/$(GVT_DIR)
> +ccflags-y+= -I $(srctree)/$(src) -I
> $(srctree)/$(src)/$(GVT_DIR)/
> i915-y += $(addprefix $(GVT_DIR)/,
> $(GVT_SOURCE))
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 56a70c7..b7b1ebd 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> -ccflags-y := -Idrivers/gpu/drm/msm
> -ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
> -ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
> +ccflags-y := -I $(srctree)/$(src)
> +ccflags-y += -I $(srctree)/$(src)/disp/dpu1
> +ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
>
> msm-y := \
> adreno/adreno_device.o \
> diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild
> index ea3035e..4fae728 100644
> --- a/drivers/gpu/drm/nouveau/Kbuild
> +++ b/drivers/gpu/drm/nouveau/Kbuild
> @@ -1,7 +1,7 @@
> -ccflags-y += -I$(src)/include
> -ccflags-y += -I$(src)/include/nvkm
> -ccflags-y += -I$(src)/nvkm
> -ccflags-y += -I$(src)
> +ccflags-y += -I $(srctree)/$(src)/include
> +ccflags-y += -I $(srctree)/$(src)/include/nvkm
> +ccflags-y += -I $(srctree)/$(src)/nvkm
> +ccflags-y += -I $(srctree)/$(src)
>
> # NVKM - HW resource manager
> #- code also used by various userspace tools/tests
> --
> 2.7.4
--
Reviewed-by: James Qian Wang (Arm Technology China)
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Re: [Intel-gfx] [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform
On 29/03/2019 09:54, Jani Nikula wrote:
On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Concept of a sub-platform already exist in our code (like ULX and ULT
platform variants and similar),implemented via the macros which check a
list of device ids to determine a match.
With this patch we consolidate device ids checking into a single function
called during early driver load.
A few low bits in the platform mask are reserved for sub-platform
identification and defined as a per-platform namespace.
At the same time it future proofs the platform_mask handling by preparing
the code for easy extending, and tidies the very verbose WARN strings
generated when IS_PLATFORM macros are embedded into a WARN type
statements.
v2: Fixed IS_SUBPLATFORM. Updated commit msg.
v3: Chris was right, there is an ordering problem.
v4:
* Catch-up with new sub-platforms.
* Rebase for RUNTIME_INFO.
* Drop subplatform mask union tricks and convert platform_mask to an
array for extensibility.
v5:
* Fix subplatform check.
* Protect against forgetting to expand subplatform bits.
* Remove platform enum tallying.
* Add subplatform to error state. (Chris)
* Drop macros and just use static inlines.
* Remove redundant IRONLAKE_M. (Ville)
v6:
* Split out Ironlake change.
* Optimize subplatform check.
* Use __always_inline. (Lucas)
* Add platform_mask comment. (Paulo)
* Pass stored runtime info in error capture. (Chris)
v7:
* Rebased for new AML ULX device id.
* Bump platform mask array size for EHL.
* Stop mentioning device ids in intel_device_subplatform_init by using
the trick of splitting macros i915_pciids.h. (Jani)
* AML seems to be either a subplatform of KBL or CFL so express it like
that.
v8:
* Use one device id table per subplatform. (Jani)
Signed-off-by: Tvrtko Ursulin
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Jose Souza
Cc: Ville Syrjälä
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson # v6
---
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 123 ---
drivers/gpu/drm/i915/i915_gpu_error.c| 3 +
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 93 +
drivers/gpu/drm/i915/intel_device_info.h | 27 -
6 files changed, 214 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f1334f5d4ead..74734d7661e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -868,6 +868,8 @@ static int i915_driver_init_early(struct drm_i915_private
*dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
+ intel_device_info_subplatform_init(dev_priv);
+
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
mutex_init(&dev_priv->backlight_lock);
@@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct
drm_i915_private *dev_priv)
if (drm_debug & DRM_UT_DRIVER) {
struct drm_printer p = drm_debug_printer("i915 device info:");
- drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
+ drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
(subplatform=0x%x) gen=%i\n",
INTEL_DEVID(dev_priv),
INTEL_REVID(dev_priv),
intel_platform_name(INTEL_INFO(dev_priv)->platform),
+ intel_subplatform(RUNTIME_INFO(dev_priv),
+INTEL_INFO(dev_priv)->platform),
INTEL_GEN(dev_priv));
intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
@@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct
pci_device_id *ent)
memcpy(device_info, match_info, sizeof(*device_info));
RUNTIME_INFO(i915)->device_id = pdev->device;
- BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-BITS_PER_TYPE(device_info->platform_mask));
BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
return i915;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d3cab9406e1..b7d3f3a45ed9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
+static __always_inline unsigned int
+__platform_mask_index(const struct intel_runtime_info *info,
+ enum intel_platform p)
+{
+ const unsigned int pbits =
+ BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
+
+ /* Expand the platform_mask array if this fa
Re: [Intel-gfx] [v6 12/13] drm/i915: Set Infoframe for non modeset case for HDR
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 69aa0d1..a27aab9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3566,6 +3566,10 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
@@ -3575,6 +3579,15 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder,
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
+
+ /* Set the infoframe for NON modeset cases as well */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ conn_state->hdr_metadata_changed)
+ intel_dig_port->set_infoframes(encoder,
+
crtc_state->has_infoframe,
+ crtc_state, conn_state);
+ }
}
Looks good to me, Please feel free to use:
Reviewed-by: Shashank Sharma
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: prefix header search paths with $(srctree)/ (rev2)
== Series Details == Series: drm: prefix header search paths with $(srctree)/ (rev2) URL : https://patchwork.freedesktop.org/series/56020/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: prefix header search paths with $(srctree)/ - +./arch/x86/include/asm/pgtable_64.h:61:9: warning: cast from non-scalar +./arch/x86/include/asm/pgtable_64.h:61:9: warning: cast to non-scalar +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:193:16: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:271:16: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:347:16: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:390:16: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:585:16: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:710:24: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c:142:39: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:344:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:347:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:350:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:354:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:356:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:361:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:379:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:382:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:385:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:390:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:391:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:394:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:405:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:411:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:418:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:419:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:422:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:430:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:439:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:440:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:489:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:492:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:493:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:500:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:547:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:549:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restr
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: move the edram detection out of uncore init
Quoting Patchwork (2019-03-29 05:40:25) > == Series Details == > > Series: drm/i915: move the edram detection out of uncore init > URL : https://patchwork.freedesktop.org/series/58684/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5831_full -> Patchwork_12621_full > > > Summary > --- > > **SUCCESS** > > No regressions found. (Question for the audience do we have a gen7 Crystalwell in there? Hopefully at least one bdw gte, but we definitely do have a kbl gte.) And pushed. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 13/13] video/hdmi: Add const variants for drm infoframe
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Added the const version of infoframe for DRM metadata
for HDR.
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 63 ++--
include/linux/hdmi.h | 5 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 80bb0ee..f9ca555 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -668,6 +668,30 @@ int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe
*frame)
}
EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+static int hdmi_drm_infoframe_check_only(const struct hdmi_drm_infoframe *frame)
+{
+ if (frame->type != HDMI_INFOFRAME_TYPE_DRM ||
+ frame->version != 1)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * hdmi_drm_infoframe_check() - check a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Validates that the infoframe is consistent and updates derived fields
+ * (eg. length) based on other fields.
+ *
This comment doesn't match what's being done in this function, as,
hdmi_drm_infoframe_check_only() doesn't validate length.
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame)
+{
+ return hdmi_drm_infoframe_check_only(frame);
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_check);
+
/**
* hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
* @frame: HDMI DRM infoframe
@@ -682,8 +706,8 @@ int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe
*frame)
* Returns the number of bytes packed into the binary buffer or a negative
* error code on failure.
*/
-ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
- size_t size)
+ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
+void *buffer, size_t size)
{
u8 *ptr = buffer;
size_t length;
@@ -736,6 +760,37 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
return length;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_pack_only);
+
+/**
+ * hdmi_drm_infoframe_pack() - check a HDMI DRM infoframe,
+ * and write it to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Validates that the infoframe is consistent and updates derived fields
+ * (eg. length) based on other fields, after which it packs the information
+ * contained in the @frame structure into a binary representation that
+ * can be written into the corresponding controller registers. This function
+ * also computes the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns the number of bytes packed into the binary buffer or a negative
+ * error code on failure.
+ */
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame,
+ void *buffer, size_t size)
+{
+ int ret;
+
+ ret = hdmi_drm_infoframe_check(frame);
+ if (ret)
+ return ret;
+
+ return hdmi_drm_infoframe_pack_only(frame, buffer, size);
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_pack);
/*
* hdmi_vendor_any_infoframe_check() - check a vendor infoframe
@@ -845,6 +900,10 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
length = hdmi_avi_infoframe_pack_only(&frame->avi,
buffer, size);
break;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ length = hdmi_drm_infoframe_pack_only(&frame->drm,
+ buffer, size);
+ break;
case HDMI_INFOFRAME_TYPE_SPD:
length = hdmi_spd_infoframe_pack_only(&frame->spd,
buffer, size);
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 202ed4a..fd8e534 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -213,6 +213,11 @@ ssize_t hdmi_avi_infoframe_pack_only(const struct
hdmi_avi_infoframe *frame,
void *buffer, size_t size);
int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame);
int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame);
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
+ size_t size);
+ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
+void *buffer, size_t size);
+int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
With that minor comment related to description fixed, this patch looks
good to me. Please feel free to use:
Reviewed-by: Shashank Sharma
- Shashank
___
[Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register programming
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
Reported-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ff910ed..dd179a8 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_DATA(pipe), word);
}
- /* Program the max register to clamp values > 1.0. */
- i = lut_size - 1;
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
- drm_color_lut_extract(lut[i].red, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
- drm_color_lut_extract(lut[i].green, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
- drm_color_lut_extract(lut[i].blue, 16));
+ /*
+* Program the max register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 1.0 to 3.0
+*/
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
(v << 20) | (v << 10) | v);
}
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
}
/*
--
1.9.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] Fixed GC MAX register programming for gamma luts
Register offsets used to program GC max were not correct. This series fixes the same, also limits the values to accurately clamp at 1.0. Also added support to program EXT2 GC Max needed for values from 3.0 to 7.0. Limiting it again to 1.0 due to ABI limitations. Uma Shankar (2): drm/i915: Fix GCMAX color register programming drm/i915: Program EXT2 GC MAX registers drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_color.c | 50 +- 2 files changed, 40 insertions(+), 11 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 28
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379..341f03e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10144,6 +10144,7 @@ enum skl_power_gate {
#define PREC_PAL_DATA(pipe)_MMIO_PIPE(pipe, _PAL_PREC_DATA_A,
_PAL_PREC_DATA_B)
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index dd179a8..84aa5e7 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
+
+ /*
+* Program the gc max 2 register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 3.0 to 7.0
+*/
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ (1 << 16) - 1);
+ }
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -537,6 +551,20 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
+
+ /*
+* Program the gc max 2 register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 3.0 to 7.0
+*/
+ if (INTEL_GEN(dev_priv) >= 10) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
+ (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
+ (1 << 16) - 1);
+ }
}
/*
--
1.9.1
___
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Re: [Intel-gfx] [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 4:17 PM
>To: Roper, Matthew D
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
>Subject: Re: [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
>
>On Thu, Mar 28, 2019 at 05:16:03PM -0700, Matt Roper wrote:
>> On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
>> > From: Ville Syrjälä
>> >
>> > Using the split gamma mode when we don't have to has the annoying
>> > requirement of loading a linear LUT to the unused half. Instead
>> > let's make life simpler by switching to the 10bit gamma mode and
>> > duplicating each entry.
>> >
>> > This also allows us to load the software gamma LUT into the hardware
>> > degamma LUT, thus removing some of the buggy configurations we
>> > currently allow (YCbCr/limited range RGB
>> > + gamma LUT). We do still have other configurations that are
>> > also buggy, but those will need more complicated fixes or they just
>> > need to be rejected. Sadly GLK doesn't have this flexibility anymore
>> > and the degamma and gamma LUTs are very different so no help there.
>> >
>> > Signed-off-by: Ville Syrjälä
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h| 1 +
>> > drivers/gpu/drm/i915/intel_color.c | 159
>> > +++--
>> > 2 files changed, 86 insertions(+), 74 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index c866379a521b..eb7e93354cfe
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -10127,6 +10127,7 @@ enum skl_power_gate {
>> > #define PAL_PREC_SPLIT_MODE (1 << 31)
>> > #define PAL_PREC_AUTO_INCREMENT (1 << 15)
>> > #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
>> > +#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
>> > #define _PAL_PREC_DATA_A 0x4A404
>> > #define _PAL_PREC_DATA_B 0x4AC04
>> > #define _PAL_PREC_DATA_C 0x4B404
>> > diff --git a/drivers/gpu/drm/i915/intel_color.c
>> > b/drivers/gpu/drm/i915/intel_color.c
>> > index d7c38a2bbd8f..ed4bd9bd15f5 100644
>> > --- a/drivers/gpu/drm/i915/intel_color.c
>> > +++ b/drivers/gpu/drm/i915/intel_color.c
>> > @@ -466,72 +466,32 @@ static void skl_color_commit(const struct
>intel_crtc_state *crtc_state)
>> >ilk_load_csc_matrix(crtc_state);
>> > }
>> >
>> > -static void bdw_load_degamma_lut(const struct intel_crtc_state
>> > *crtc_state)
>> > +static void bdw_load_lut_10(struct intel_crtc *crtc,
>> > + const struct drm_property_blob *blob,
>> > + u32 prec_index, bool duplicate)
>> > {
>> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> >struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > - const struct drm_property_blob *degamma_lut = crtc_state-
>>base.degamma_lut;
>> > - u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>> > + const struct drm_color_lut *lut = blob->data;
>> > + int i, lut_size = drm_color_lut_size(blob);
>> >enum pipe pipe = crtc->pipe;
>> >
>> > - I915_WRITE(PREC_PAL_INDEX(pipe),
>> > - PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>> > -
>> > - if (degamma_lut) {
>> > - const struct drm_color_lut *lut = degamma_lut->data;
>> > + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
>> > + PAL_PREC_AUTO_INCREMENT);
>> >
>> > - for (i = 0; i < lut_size; i++)
>> > - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>> > - } else {
>> > + /*
>> > + * We advertize the split gamma sizes. When not using split
>> > + * gamma we just duplicate each entry.
>> > + *
>> > + * TODO: expose the full LUT to userspace
>>
>> Any reason not to just do this immediately? Throwing away half the
>> table entries if we decide we need split mode doesn't seem any harder
>> than duplicating the entries when we decide we don't. The color
>> management kerneldoc already explicitly recommends this approach for
>> hardware that can support multiple gamma modes, so I don't think we
>> need any new ABI to handle it.
>
>Hmm. I guess that apporach could be doable. It might be a bit annoying for
>userspace
>though if it expects a direct color visual. But at least for X we won't use
>degamma/ctm anyway so seems like it should work out just fine.
>
>>
>> > + */
>> > + if (duplicate) {
>> >for (i = 0; i < lut_size; i++) {
>> > - u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
>> > -
>> > - I915_WRITE(PREC_PAL_DATA(pipe),
>> > - (v << 20) | (v << 10) | v);
>> > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>> > + I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
>> >}
>> > - }
>> > -}
>> > -
>> > -static void bdw_load_gamma_lut(const struct intel_crtc_state
>> > *crtc_state, u32 offset) -{
>> > - s
Re: [Intel-gfx] [v6 10/13] drm/i915: Enable infoframes on GLK+ for HDR
On 3/20/2019 4:18 PM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 18 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31a3020..fe931e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4718,6 +4718,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET (1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT25
@@ -8156,6 +8157,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8169,6 +8171,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8194,6 +8197,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e4bc7fc..8decafd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -134,6 +134,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -159,6 +161,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -545,7 +549,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
I think this should also be GEN check protected, as
hsw_infoframes_enabled will be called by many platforms, and before GLK
they cant support DRM_IF.
}
static const u8 infoframe_type_to_idx[] = {
@@ -1177,7 +1182,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+VIDEO_DIP_ENABLE_DRM_GLK);
Same here.
- Shashank
if (!enable) {
I915_WRITE(reg, val);
@@ -1200,9 +1206,11 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_write_infoframe(encoder, crtc_state,
HDMI_INFOFRAME_TYPE_VENDOR,
&crtc_state->infoframes.hdmi);
- intel_write_infoframe(encoder, crtc_state,
- HDMI_INFOFRAME_TYPE_DRM,
- &crtc_state->infoframes.drm);
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/gamma: Clarify gamma lut uapi
== Series Details ==
Series: drm/gamma: Clarify gamma lut uapi
URL : https://patchwork.freedesktop.org/series/58718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5835_full -> Patchwork_12626_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12626_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_bad_reloc@negative-reloc-lut-bsd1:
- shard-glk: NOTRUN -> SKIP [fdo#109271] +3
* igt@gem_ctx_isolation@vcs1-reset:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +2
* igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109283]
* igt@gem_exec_store@cachelines-bsd1:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +42
* igt@gem_mocs_settings@mocs-rc6-dirty-render:
- shard-iclb: NOTRUN -> SKIP [fdo#110206]
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: PASS -> INCOMPLETE [fdo#109801]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-iclb: NOTRUN -> INCOMPLETE [fdo#109801]
* igt@gem_pread@stolen-snoop:
- shard-iclb: NOTRUN -> SKIP [fdo#109277]
* igt@gem_pwrite@huge-gtt-fbr:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@i915_pm_rpm@basic-pci-d3-state:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-f:
- shard-iclb: NOTRUN -> SKIP [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-oldfb-render-e:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-hpd-fast:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +20
* igt@kms_chamelium@hdmi-cmp-nv12:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +1
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-iclb: PASS -> FAIL [fdo#103355] +2
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-glk: PASS -> FAIL [fdo#107791]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-kbl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +6
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#109247] +14
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_psr@cursor_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +1
* igt@kms_psr@cursor_render:
- shard-iclb: PASS -> DMESG-WARN [fdo#110025]
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-iclb: NOTRUN -> SKIP [fdo#109291]
Possible fixes
* igt@drm_import_export@prime:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@i915_pm_rpm@i2c:
- shard-iclb: DMESG-WARN [fdo#109982] -> PASS
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +1
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-glk: FAIL [fdo#100368] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
- shard-kbl: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#103167] -> PASS +8
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-skl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +14
* {igt@kms_plane@pixel-format-pipe-c-planes}:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1
* igt@kms_psr
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts
== Series Details == Series: Fixed GC MAX register programming for gamma luts URL : https://patchwork.freedesktop.org/series/58734/ State : warning == Summary == $ dim checkpatch origin/drm-tip ecab4c425422 drm/i915: Fix GCMAX color register programming ca881c02da68 drm/i915: Program EXT2 GC MAX registers -:21: WARNING:LONG_LINE: line over 100 characters #21: FILE: drivers/gpu/drm/i915/i915_reg.h:10147: +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) total: 0 errors, 1 warnings, 0 checks, 47 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: prefix header search paths with $(srctree)/ (rev2)
== Series Details == Series: drm: prefix header search paths with $(srctree)/ (rev2) URL : https://patchwork.freedesktop.org/series/56020/ State : success == Summary == CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12627 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/56020/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12627 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: FAIL [fdo#103182] -> PASS +1 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 Participating hosts (46 -> 40) -- Additional (1): fi-hsw-4770r Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-bdw-samus Build changes - * Linux: CI_DRM_5837 -> Patchwork_12627 CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12627: aea6edcde250fe5ca661940207b2ed56f2cb32c3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aea6edcde250 drm: prefix header search paths with $(srctree)/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12627/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 11/13] drm/i915:Enabled Modeset when HDR Infoframe changes
On 3/20/2019 4:18 PM, Uma Shankar wrote:
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b844e88..4ff6042 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -102,6 +102,16 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return -EINVAL;
}
+static bool blob_equal(const struct drm_property_blob *a,
+ const struct drm_property_blob *b)
+{
+ if (a && b)
+ return a->length == b->length &&
+ !memcmp(a->data, b->data, a->length);
+
+ return !a == !b;
+}
+
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state)
{
@@ -129,7 +139,10 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->base.colorspace != old_conn_state->base.colorspace
||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
- new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
+ new_conn_state->base.scaling_mode !=
+ old_conn_state->base.scaling_mode ||
+ !blob_equal(new_conn_state->base.hdr_output_metadata_blob_ptr,
If you are keeping this line ahead of the upper one due to 80 char
limit, please pull that one also two tabs back, right now this is not
even looking good.
+ old_conn_state->base.hdr_output_metadata_blob_ptr))
crtc_state->mode_changed = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8decafd..4d06734 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -792,6 +792,10 @@ void intel_read_infoframe(struct intel_encoder *encoder,
struct hdr_static_metadata *hdr_metadata;
int ret;
+ if (!conn_state->hdr_output_metadata_blob_ptr ||
+ conn_state->hdr_output_metadata_blob_ptr->length == 0)
+ return true;
+
This patch needs a rebase on the latest code, as this is definitely not
where we want this code :-)
- Shashank
hdr_metadata = (struct hdr_static_metadata *)
conn_state->hdr_output_metadata_blob_ptr->data;
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts
== Series Details == Series: Fixed GC MAX register programming for gamma luts URL : https://patchwork.freedesktop.org/series/58734/ State : success == Summary == CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12628 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58734/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12628 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@amdgpu/amd_basic@semaphore: - fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +28 * igt@gem_exec_store@basic-bsd1: - fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_suspend@basic-s4-devices: - fi-kbl-7500u: PASS -> DMESG-WARN [fdo#105128] / [fdo#107139] * igt@i915_selftest@live_hangcheck: - fi-icl-u3: PASS -> INCOMPLETE [fdo#108569] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#102505] / [fdo#103558] / [fdo#105079] / [fdo#105602] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: DMESG-WARN [fdo#103841] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2 * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079 [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (46 -> 42) -- Additional (2): fi-hsw-4770r fi-kbl-r Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_5837 -> Patchwork_12628 CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12628: ca881c02da6850d30d460ac48aa7ffe065bf0237 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ca881c02da68 drm/i915: Program EXT2 GC MAX registers ecab4c425422 drm/i915: Fix GCMAX color register programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12628/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v8 4/4] drm/i915: Introduce concept of a sub-platform
On Fri, 29 Mar 2019, Tvrtko Ursulin wrote:
> On 29/03/2019 09:54, Jani Nikula wrote:
>> On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> Concept of a sub-platform already exist in our code (like ULX and ULT
>>> platform variants and similar),implemented via the macros which check a
>>> list of device ids to determine a match.
>>>
>>> With this patch we consolidate device ids checking into a single function
>>> called during early driver load.
>>>
>>> A few low bits in the platform mask are reserved for sub-platform
>>> identification and defined as a per-platform namespace.
>>>
>>> At the same time it future proofs the platform_mask handling by preparing
>>> the code for easy extending, and tidies the very verbose WARN strings
>>> generated when IS_PLATFORM macros are embedded into a WARN type
>>> statements.
>>>
>>> v2: Fixed IS_SUBPLATFORM. Updated commit msg.
>>> v3: Chris was right, there is an ordering problem.
>>>
>>> v4:
>>> * Catch-up with new sub-platforms.
>>> * Rebase for RUNTIME_INFO.
>>> * Drop subplatform mask union tricks and convert platform_mask to an
>>> array for extensibility.
>>>
>>> v5:
>>> * Fix subplatform check.
>>> * Protect against forgetting to expand subplatform bits.
>>> * Remove platform enum tallying.
>>> * Add subplatform to error state. (Chris)
>>> * Drop macros and just use static inlines.
>>> * Remove redundant IRONLAKE_M. (Ville)
>>>
>>> v6:
>>> * Split out Ironlake change.
>>> * Optimize subplatform check.
>>> * Use __always_inline. (Lucas)
>>> * Add platform_mask comment. (Paulo)
>>> * Pass stored runtime info in error capture. (Chris)
>>>
>>> v7:
>>> * Rebased for new AML ULX device id.
>>> * Bump platform mask array size for EHL.
>>> * Stop mentioning device ids in intel_device_subplatform_init by using
>>> the trick of splitting macros i915_pciids.h. (Jani)
>>> * AML seems to be either a subplatform of KBL or CFL so express it like
>>> that.
>>>
>>> v8:
>>> * Use one device id table per subplatform. (Jani)
>>>
>>> Signed-off-by: Tvrtko Ursulin
>>> Suggested-by: Chris Wilson
>>> Cc: Chris Wilson
>>> Cc: Jani Nikula
>>> Cc: Lucas De Marchi
>>> Cc: Jose Souza
>>> Cc: Ville Syrjälä
>>> Cc: Paulo Zanoni
>>> Reviewed-by: Chris Wilson # v6
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.c | 8 +-
>>> drivers/gpu/drm/i915/i915_drv.h | 123 ---
>>> drivers/gpu/drm/i915/i915_gpu_error.c| 3 +
>>> drivers/gpu/drm/i915/i915_pci.c | 2 +-
>>> drivers/gpu/drm/i915/intel_device_info.c | 93 +
>>> drivers/gpu/drm/i915/intel_device_info.h | 27 -
>>> 6 files changed, 214 insertions(+), 42 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index f1334f5d4ead..74734d7661e5 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -868,6 +868,8 @@ static int i915_driver_init_early(struct
>>> drm_i915_private *dev_priv)
>>> if (i915_inject_load_failure())
>>> return -ENODEV;
>>>
>>> + intel_device_info_subplatform_init(dev_priv);
>>> +
>>> spin_lock_init(&dev_priv->irq_lock);
>>> spin_lock_init(&dev_priv->gpu_error.lock);
>>> mutex_init(&dev_priv->backlight_lock);
>>> @@ -1718,10 +1720,12 @@ static void i915_welcome_messages(struct
>>> drm_i915_private *dev_priv)
>>> if (drm_debug & DRM_UT_DRIVER) {
>>> struct drm_printer p = drm_debug_printer("i915 device info:");
>>>
>>> - drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
>>> + drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s
>>> (subplatform=0x%x) gen=%i\n",
>>>INTEL_DEVID(dev_priv),
>>>INTEL_REVID(dev_priv),
>>>intel_platform_name(INTEL_INFO(dev_priv)->platform),
>>> + intel_subplatform(RUNTIME_INFO(dev_priv),
>>> +INTEL_INFO(dev_priv)->platform),
>>>INTEL_GEN(dev_priv));
>>>
>>> intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
>>> @@ -1764,8 +1768,6 @@ i915_driver_create(struct pci_dev *pdev, const struct
>>> pci_device_id *ent)
>>> memcpy(device_info, match_info, sizeof(*device_info));
>>> RUNTIME_INFO(i915)->device_id = pdev->device;
>>>
>>> - BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
>>> -BITS_PER_TYPE(device_info->platform_mask));
>>> BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
>>>
>>> return i915;
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 9d3cab9406e1..b7d3f3a45ed9 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2298,7 +2298,67 @@ static inline unsigned int i915_sg_segment_size(void)
>>> #define IS_REVID(p, since, until) \
>>> (INTEL
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register programming
On Fri, Mar 29, 2019 at 06:19:18PM +0530, Uma Shankar wrote:
> GC MAX register is used to program values from 1.0 to
> less than 3.0. A different register was used instead of
> the intended one. Fixed the same.
>
> Currently limiting it to 1.0 due to ABI limitations.
>
> Reported-by: Ville Syrjälä
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_color.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index ff910ed..dd179a8 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct
> intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_DATA(pipe), word);
> }
>
> - /* Program the max register to clamp values > 1.0. */
> - i = lut_size - 1;
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
> -drm_color_lut_extract(lut[i].red, 16));
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
> -drm_color_lut_extract(lut[i].green, 16));
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
> -drm_color_lut_extract(lut[i].blue, 16));
> + /*
> + * Program the max register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 1.0 to 3.0
> + */
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
Maybe we want these to be just 1<<16 to match how we set up the glk+
degamma?
> } else {
> for (i = 0; i < lut_size; i++) {
> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> @@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct
> intel_crtc_state *crtc_state, u32 of
> (v << 20) | (v << 10) | v);
> }
>
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
> - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> }
>
> /*
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote:
> EXT2 GC MAX registers are introduced from Gen10+ to
> program values from 3.0 to 7.0. Enabled the same, but
> currently limiting it to 1.0 as userspace ABI is limited
> at that currently.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> drivers/gpu/drm/i915/intel_color.c | 28
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c866379..341f03e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10144,6 +10144,7 @@ enum skl_power_gate {
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A,
> _PAL_PREC_DATA_B)
> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
> _PAL_PREC_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> +#define PREC_PAL_EXT2_GC_MAX(pipe, i)_MMIO(_PIPE(pipe,
> _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
>
> #define _PRE_CSC_GAMC_INDEX_A0x4A484
> #define _PRE_CSC_GAMC_INDEX_B0x4AC84
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index dd179a8..84aa5e7 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct
> intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> +
> + /*
> + * Program the gc max 2 register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 3.0 to 7.0
> + */
> + if (INTEL_GEN(dev_priv) >= 10) {
|| IS_GEMINILAKE
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
> +(1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
> +(1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
> +(1 << 16) - 1);
> + }
> } else {
> for (i = 0; i < lut_size; i++) {
> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
> @@ -537,6 +551,20 @@ static void bdw_load_gamma_lut(const struct
> intel_crtc_state *crtc_state, u32 of
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
> +
> + /*
> + * Program the gc max 2 register to clamp values > 1.0.
> + * ToDo: Extend the ABI to be able to program values
> + * from 3.0 to 7.0
> + */
> + if (INTEL_GEN(dev_priv) >= 10) {
same
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
> +(1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
> +(1 << 16) - 1);
> + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
> +(1 << 16) - 1);
> + }
> }
>
> /*
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/execlists: Enable coarse preemption boundaries for gen8
When we introduced preemption, we chose to keep it disabled for gen8 as
supporting preemption inside GPGPU user batches required various w/a in
userspace. Since then, the desire to preempt long queues of requests
between batches (e.g. within busywaiting semaphores) has grown. So allow
arbitration within the busywaits and between requests, but disable
arbitration within user batches so that we can preempt between requests
and not risk breaking GPGPU.
However, since this preemption is much coarser and doesn't interfere
with userspace, we decline to include it amongst the scheduler
capabilities. (This is also required for us to skip over the preemption
selftests that expect to be able to preempt user batches.)
Testcase: igt/gem_exec_scheduler/semaphore-user
References: beecec901790 ("drm/i915/execlists: Preemption!")
Fixes: e88619646971 ("drm/i915: Use HW semaphores for inter-engine
synchronisation on gen8+")
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c| 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 49 --
drivers/gpu/drm/i915/selftests/intel_lrc.c | 180 +
3 files changed, 217 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 662da485e15f..92993db38aad 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -562,7 +562,7 @@ static void init_contexts(struct drm_i915_private *i915)
static bool needs_preempt_context(struct drm_i915_private *i915)
{
- return HAS_LOGICAL_RING_PREEMPTION(i915);
+ return HAS_EXECLISTS(i915);
}
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index bec232acc8d7..b380688a0c1c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -233,7 +233,7 @@ static inline bool need_preempt(const struct
intel_engine_cs *engine,
{
int last_prio;
- if (!intel_engine_has_preemption(engine))
+ if (!engine->preempt_context)
return false;
if (i915_request_completed(rq))
@@ -2035,7 +2035,7 @@ static int gen8_emit_bb_start(struct i915_request *rq,
{
u32 *cs;
- cs = intel_ring_begin(rq, 6);
+ cs = intel_ring_begin(rq, 4);
if (IS_ERR(cs))
return PTR_ERR(cs);
@@ -2046,16 +2046,35 @@ static int gen8_emit_bb_start(struct i915_request *rq,
* particular all the gen that do not need the w/a at all!), if we
* took care to make sure that on every switch into this context
* (both ordinary and for preemption) that arbitrartion was enabled
-* we would be fine. However, there doesn't seem to be a downside to
-* being paranoid and making sure it is set before each batch and
-* every context-switch.
-*
-* Note that if we fail to enable arbitration before the request
-* is complete, then we do not see the context-switch interrupt and
-* the engine hangs (with RING_HEAD == RING_TAIL).
-*
-* That satisfies both the GPGPU w/a and our heavy-handed paranoia.
+* we would be fine. However, for gen8 there is another w/a that
+* requires us to not preempt inside GPGPU execution, so we keep
+* arbitration disabled for gen8 batches. Arbitration will be
+* re-enabled before we close the request
+* (engine->emit_fini_breadcrumb).
*/
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+
+ /* FIXME(BDW): Address space and security selectors. */
+ *cs++ = MI_BATCH_BUFFER_START_GEN8 |
+ (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int gen9_emit_bb_start(struct i915_request *rq,
+ u64 offset, u32 len,
+ const unsigned int flags)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
/* FIXME(BDW): Address space and security selectors. */
@@ -2316,7 +2335,8 @@ void intel_execlists_set_default_submission(struct
intel_engine_cs *engine)
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
if (!intel_vgpu_active(engine->i915))
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
- if (engine->preempt_context)
+ if (engine->preempt_context &&
+ HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
@@ -2350,7 +2370,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs
*engine)
* until a more refined solution exists.
*/
}
- engine->emi
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
On Fri, Mar 29, 2019 at 12:47:02PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 28, 2019 at 05:16:03PM -0700, Matt Roper wrote:
> > On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Using the split gamma mode when we don't have to has the annoying
> > > requirement of loading a linear LUT to the unused half. Instead
> > > let's make life simpler by switching to the 10bit gamma mode
> > > and duplicating each entry.
> > >
> > > This also allows us to load the software gamma LUT into the
> > > hardware degamma LUT, thus removing some of the buggy
> > > configurations we currently allow (YCbCr/limited range RGB
> > > + gamma LUT). We do still have other configurations that are
> > > also buggy, but those will need more complicated fixes
> > > or they just need to be rejected. Sadly GLK doesn't have
> > > this flexibility anymore and the degamma and gamma LUTs
> > > are very different so no help there.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h| 1 +
> > > drivers/gpu/drm/i915/intel_color.c | 159 +++--
> > > 2 files changed, 86 insertions(+), 74 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index c866379a521b..eb7e93354cfe 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -10127,6 +10127,7 @@ enum skl_power_gate {
> > > #define PAL_PREC_SPLIT_MODE(1 << 31)
> > > #define PAL_PREC_AUTO_INCREMENT(1 << 15)
> > > #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
> > > +#define PAL_PREC_INDEX_VALUE(x)((x) << 0)
> > > #define _PAL_PREC_DATA_A 0x4A404
> > > #define _PAL_PREC_DATA_B 0x4AC04
> > > #define _PAL_PREC_DATA_C 0x4B404
> > > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > > b/drivers/gpu/drm/i915/intel_color.c
> > > index d7c38a2bbd8f..ed4bd9bd15f5 100644
> > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > @@ -466,72 +466,32 @@ static void skl_color_commit(const struct
> > > intel_crtc_state *crtc_state)
> > > ilk_load_csc_matrix(crtc_state);
> > > }
> > >
> > > -static void bdw_load_degamma_lut(const struct intel_crtc_state
> > > *crtc_state)
> > > +static void bdw_load_lut_10(struct intel_crtc *crtc,
> > > + const struct drm_property_blob *blob,
> > > + u32 prec_index, bool duplicate)
> > > {
> > > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > - const struct drm_property_blob *degamma_lut =
> > > crtc_state->base.degamma_lut;
> > > - u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > > + const struct drm_color_lut *lut = blob->data;
> > > + int i, lut_size = drm_color_lut_size(blob);
> > > enum pipe pipe = crtc->pipe;
> > >
> > > - I915_WRITE(PREC_PAL_INDEX(pipe),
> > > -PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> > > -
> > > - if (degamma_lut) {
> > > - const struct drm_color_lut *lut = degamma_lut->data;
> > > + I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
> > > +PAL_PREC_AUTO_INCREMENT);
> > >
> > > - for (i = 0; i < lut_size; i++)
> > > - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
> > > - } else {
> > > + /*
> > > + * We advertize the split gamma sizes. When not using split
> > > + * gamma we just duplicate each entry.
> > > + *
> > > + * TODO: expose the full LUT to userspace
> >
> > Any reason not to just do this immediately? Throwing away half the
> > table entries if we decide we need split mode doesn't seem any harder
> > than duplicating the entries when we decide we don't. The color
> > management kerneldoc already explicitly recommends this approach for
> > hardware that can support multiple gamma modes, so I don't think we need
> > any new ABI to handle it.
>
> Hmm. I guess that apporach could be doable. It might be a bit annoying
> for userspace though if it expects a direct color visual. But at least
> for X we won't use degamma/ctm anyway so seems like it should work out
> just fine.
As usual this needs a bit of care when picking the LUT entries we
use. I think I'll send that as a followup.
--
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Intel
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register programming
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 6:40 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
>Maarten
>Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register
>programming
>
>On Fri, Mar 29, 2019 at 06:19:18PM +0530, Uma Shankar wrote:
>> GC MAX register is used to program values from 1.0 to less than 3.0. A
>> different register was used instead of the intended one. Fixed the
>> same.
>>
>> Currently limiting it to 1.0 due to ABI limitations.
>>
>> Reported-by: Ville Syrjälä
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_color.c | 22 +++---
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index ff910ed..dd179a8 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct
>intel_crtc_state *crtc_state, u32 of
>> I915_WRITE(PREC_PAL_DATA(pipe), word);
>> }
>>
>> -/* Program the max register to clamp values > 1.0. */
>> -i = lut_size - 1;
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
>> - drm_color_lut_extract(lut[i].red, 16));
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
>> - drm_color_lut_extract(lut[i].green, 16));
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
>> - drm_color_lut_extract(lut[i].blue, 16));
>> +/*
>> + * Program the max register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 1.0 to 3.0
>> + */
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>
>Maybe we want these to be just 1<<16 to match how we set up the glk+ degamma?
Sure, will update it.
>> } else {
>> for (i = 0; i < lut_size; i++) {
>> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@
>> -534,9 +534,9
>> @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state,
>> u32
>of
>> (v << 20) | (v << 10) | v);
>> }
>>
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
>> -I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> }
>>
>> /*
>> --
>> 1.9.1
>>
>> ___
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
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>Intel
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 6:41 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
>Maarten
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers
>
>On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote:
>> EXT2 GC MAX registers are introduced from Gen10+ to program values
>> from 3.0 to 7.0. Enabled the same, but currently limiting it to 1.0 as
>> userspace ABI is limited at that currently.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/i915_reg.h| 1 +
>> drivers/gpu/drm/i915/intel_color.c | 28
>> 2 files changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index c866379..341f03e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10144,6 +10144,7 @@ enum skl_power_gate {
>> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe,
>_PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
>> #define PREC_PAL_GC_MAX(pipe, i)_MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
>_PAL_PREC_GC_MAX_B) + (i) * 4)
>> #define PREC_PAL_EXT_GC_MAX(pipe, i)_MMIO(_PIPE(pipe,
>_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
>> +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
>_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
>>
>> #define _PRE_CSC_GAMC_INDEX_A 0x4A484
>> #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index dd179a8..84aa5e7 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct
>intel_crtc_state *crtc_state, u32 of
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> +
>> +/*
>> + * Program the gc max 2 register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 3.0 to 7.0
>> + */
>> +if (INTEL_GEN(dev_priv) >= 10) {
>
>|| IS_GEMINILAKE
Yeah, GLK needs to be added here. Will update it.
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
>> + (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
>> + (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
>> + (1 << 16) - 1);
>> +}
>> } else {
>> for (i = 0; i < lut_size; i++) {
>> u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@
>> -537,6 +551,20
>> @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state,
>> u32
>of
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1);
>> +
>> +/*
>> + * Program the gc max 2 register to clamp values > 1.0.
>> + * ToDo: Extend the ABI to be able to program values
>> + * from 3.0 to 7.0
>> + */
>> +if (INTEL_GEN(dev_priv) >= 10) {
>
>same
>
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0),
>> + (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1),
>> + (1 << 16) - 1);
>> +I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2),
>> + (1 << 16) - 1);
>> +}
>> }
>>
>> /*
>> --
>> 1.9.1
>>
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>--
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>Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Enable coarse preemption boundaries for gen8
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
678a3d72d2b3 drm/i915/execlists: Enable coarse preemption boundaries for gen8
-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit beecec901790
("drm/i915/execlists: Preemption!")'
#21:
References: beecec901790 ("drm/i915/execlists: Preemption!")
total: 1 errors, 0 warnings, 0 checks, 280 lines checked
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/execlists: Enable coarse preemption boundaries for gen8
== Series Details == Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8 URL : https://patchwork.freedesktop.org/series/58738/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Enable coarse preemption boundaries for gen8 +drivers/gpu/drm/i915/selftests/intel_lrc.c:121:54: warning: Using plain integer as NULL pointer ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v2 1/2] drm/i915: Fix GCMAX color register programming
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
v2: Updated the 1.0 programming and aligned as per GLK, based
on Ville's feedback.
Reported-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index ff910ed..c776159 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_DATA(pipe), word);
}
- /* Program the max register to clamp values > 1.0. */
- i = lut_size - 1;
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
- drm_color_lut_extract(lut[i].red, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
- drm_color_lut_extract(lut[i].green, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
- drm_color_lut_extract(lut[i].blue, 16));
+ /*
+* Program the max register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 1.0 to 3.0
+*/
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
(v << 20) | (v << 10) | v);
}
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
}
/*
--
1.9.1
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[Intel-gfx] [v2 2/2] drm/i915: Program EXT2 GC MAX registers
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
v2: Updated the 1.0 programming and aligned as per GLK, also added
GLK along with GEN10+ check, as per Ville's feedback.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 22 ++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379..341f03e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10144,6 +10144,7 @@ enum skl_power_gate {
#define PREC_PAL_DATA(pipe)_MMIO_PIPE(pipe, _PAL_PREC_DATA_A,
_PAL_PREC_DATA_B)
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A,
_PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
_PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index c776159..f2907cf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -526,6 +526,17 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+* Program the gc max 2 register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 3.0 to 7.0
+*/
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+ }
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -537,6 +548,17 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+* Program the gc max 2 register to clamp values > 1.0.
+* ToDo: Extend the ABI to be able to program values
+* from 3.0 to 7.0
+*/
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+ }
}
/*
--
1.9.1
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[Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma luts
Register offsets used to program GC max were not correct. This series fixes the same, also limits the values to accurately clamp at 1.0. Also added support to program EXT2 GC Max needed for values from 3.0 to 7.0. Limiting it again to 1.0 due to ABI limitations. v2: Addressed Ville's review comments. Uma Shankar (2): drm/i915: Fix GCMAX color register programming drm/i915: Program EXT2 GC MAX registers drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_color.c | 44 -- 2 files changed, 34 insertions(+), 11 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v6 12/13] drm/i915: Set Infoframe for non modeset case for HDR
On Wed, Mar 20, 2019 at 04:18:25PM +0530, Uma Shankar wrote:
> HDR metadata requires a infoframe to be set. Due to fastset,
> full modeset is not performed hence adding it to update_pipe
> to handle that.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 69aa0d1..a27aab9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3566,6 +3566,10 @@ static void intel_ddi_update_pipe(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *intel_dig_port =
> + enc_to_dig_port(&encoder->base);
> +
> if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
>
> @@ -3575,6 +3579,15 @@ static void intel_ddi_update_pipe(struct intel_encoder
> *encoder,
> else if (conn_state->content_protection ==
>DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
> intel_hdcp_disable(to_intel_connector(conn_state->connector));
> +
> + /* Set the infoframe for NON modeset cases as well */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
> + conn_state->hdr_metadata_changed)
> + intel_dig_port->set_infoframes(encoder,
> +
> crtc_state->has_infoframe,
> +crtc_state, conn_state);
I don't think this should be tied to the drm infoframe. It should
be totally generic. IIRC there is also some magic dance we may have
to perform when updating infoframes with the port enabled. But the
details escape right now.
> + }
> }
>
> static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> --
> 1.9.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel
___
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[Intel-gfx] [PATCH v2 2/6] drm/i915: Don't use split gamma when we don't have to
From: Ville Syrjälä
Using the split gamma mode when we don't have to has the annoying
requirement of loading a linear LUT to the unused half. Instead
let's make life simpler by switching to the 10bit gamma mode
and duplicating each entry.
This also allows us to load the software gamma LUT into the
hardware degamma LUT, thus removing some of the buggy
configurations we currently allow (YCbCr/limited range RGB
+ gamma LUT). We do still have other configurations that are
also buggy, but those will need more complicated fixes
or they just need to be rejected. Sadly GLK doesn't have
this flexibility anymore and the degamma and gamma LUTs
are very different so no help there.
v2: Apply a mask when checking gamma_mode on icl since it
contains more bits than just the gamma mode
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h| 2 +
drivers/gpu/drm/i915/intel_color.c | 160 -
2 files changed, 88 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379a521b..863ba687226c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7214,6 +7214,7 @@ enum {
#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
#define PRE_CSC_GAMMA_ENABLE (1 << 31)
#define POST_CSC_GAMMA_ENABLE (1 << 30)
+#define GAMMA_MODE_MODE_MASK (3 << 0)
#define GAMMA_MODE_MODE_8BIT (0 << 0)
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
@@ -10127,6 +10128,7 @@ enum skl_power_gate {
#define PAL_PREC_SPLIT_MODE (1 << 31)
#define PAL_PREC_AUTO_INCREMENT (1 << 15)
#define PAL_PREC_INDEX_VALUE_MASK(0x3ff << 0)
+#define PAL_PREC_INDEX_VALUE(x) ((x) << 0)
#define _PAL_PREC_DATA_A 0x4A404
#define _PAL_PREC_DATA_B 0x4AC04
#define _PAL_PREC_DATA_C 0x4B404
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index d7c38a2bbd8f..f789a9fd9ba2 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -466,72 +466,32 @@ static void skl_color_commit(const struct
intel_crtc_state *crtc_state)
ilk_load_csc_matrix(crtc_state);
}
-static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
+static void bdw_load_lut_10(struct intel_crtc *crtc,
+ const struct drm_property_blob *blob,
+ u32 prec_index, bool duplicate)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_property_blob *degamma_lut =
crtc_state->base.degamma_lut;
- u32 i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ const struct drm_color_lut *lut = blob->data;
+ int i, lut_size = drm_color_lut_size(blob);
enum pipe pipe = crtc->pipe;
- I915_WRITE(PREC_PAL_INDEX(pipe),
- PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
-
- if (degamma_lut) {
- const struct drm_color_lut *lut = degamma_lut->data;
+ I915_WRITE(PREC_PAL_INDEX(pipe), prec_index |
+ PAL_PREC_AUTO_INCREMENT);
- for (i = 0; i < lut_size; i++)
- I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
- } else {
+ /*
+* We advertize the split gamma sizes. When not using split
+* gamma we just duplicate each entry.
+*
+* TODO: expose the full LUT to userspace
+*/
+ if (duplicate) {
for (i = 0; i < lut_size; i++) {
- u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
-
- I915_WRITE(PREC_PAL_DATA(pipe),
- (v << 20) | (v << 10) | v);
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
+ I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
}
- }
-}
-
-static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32
offset)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
- u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
- enum pipe pipe = crtc->pipe;
-
- WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
-
- I915_WRITE(PREC_PAL_INDEX(pipe),
- (offset ? PAL_PREC_SPLIT_MODE : 0) |
- PAL_PREC_AUTO_INCREMENT |
- offset);
-
- if (gamma_lut) {
- const struct drm_color_lut *lut = gamma_lut->data;
-
+ } else {
for (i = 0; i < lut_size; i++)
I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(&lut[i]));
-
- /* Program the max regist
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Enable coarse preemption boundaries for gen8
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12629
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58738/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12629 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@gem_exec_store@basic-bsd1:
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_chamelium@vga-edid-read:
- fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109513]: https://bugs.freedesktop.org/show_bug.cgi?id=109513
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (46 -> 37)
--
Additional (2): fi-hsw-4770r fi-kbl-r
Missing(11): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u
fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-gdg-551 fi-icl-u3 fi-bsw-kefka
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5837 -> Patchwork_12629
CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12629: 678a3d72d2b39d0f1ade4d219e49dc746e60e9a8 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
678a3d72d2b3 drm/i915/execlists: Enable coarse preemption boundaries for gen8
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12629/
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Enable coarse preemption boundaries for gen8
Quoting Patchwork (2019-03-29 14:16:21) > == Series Details == > > Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8 > URL : https://patchwork.freedesktop.org/series/58738/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12629 > > > Summary > --- > > **SUCCESS** * wipes brow with relief > Participating hosts (46 -> 37) > -- > > Additional (2): fi-hsw-4770r fi-kbl-r > Missing(11): fi-kbl-soraka fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u > fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-gdg-551 fi-icl-u3 fi-bsw-kefka > fi-bdw-samus But all icls were on vacation, so missing a tiny bit of HW coverage. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm: prefix header search paths with $(srctree)/
On Fri, Mar 29, 2019 at 08:32:41PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> that way, but not all. The goal of this work is to make the notation
> consistent, and finally get rid of the gross hacks.
>
> Having whitespaces after -I does not matter since commit 48f6e3cf5bc6
> ("kbuild: do not drop -I without parameter").
>
> [1]: https://patchwork.kernel.org/patch/9632347/
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Sam Ravnborg
> ---
>
> I put all gpu/drm changes into a single patch because
> they are trivial conversion.
>
> If you are interested in the big picture of this work,
> the full patch set is available at the following URL.
>
> git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git
> build-test
>
>
> Changes in v2:
> - fix up the new driver komeda
> - Add Sam's Reviewed-by
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
> drivers/gpu/drm/amd/lib/Makefile| 2 +-
> drivers/gpu/drm/arm/display/komeda/Makefile | 4 ++--
> drivers/gpu/drm/i915/gvt/Makefile | 2 +-
> drivers/gpu/drm/msm/Makefile| 6 +++---
> drivers/gpu/drm/nouveau/Kbuild | 8
> 6 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 466da59..62bf9da 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -23,7 +23,7 @@
> # Makefile for the drm device driver. This driver provides support for the
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
>
> -FULL_AMD_PATH=$(src)/..
> +FULL_AMD_PATH=$(srctree)/$(src)/..
> DISPLAY_FOLDER_NAME=display
> FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME)
>
> diff --git a/drivers/gpu/drm/amd/lib/Makefile
> b/drivers/gpu/drm/amd/lib/Makefile
> index 6902430..d534992 100644
> --- a/drivers/gpu/drm/amd/lib/Makefile
> +++ b/drivers/gpu/drm/amd/lib/Makefile
> @@ -27,6 +27,6 @@
> # driver components or later moved to kernel/lib for sharing with
> # other drivers.
>
> -ccflags-y := -I$(src)/../include
> +ccflags-y := -I $(srctree)/$(src)/../include
>
> obj-$(CONFIG_CHASH) += chash.o
> diff --git a/drivers/gpu/drm/arm/display/komeda/Makefile
> b/drivers/gpu/drm/arm/display/komeda/Makefile
> index 1b875e5..a72e30c 100644
> --- a/drivers/gpu/drm/arm/display/komeda/Makefile
> +++ b/drivers/gpu/drm/arm/display/komeda/Makefile
> @@ -1,8 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
>
> ccflags-y := \
> - -I$(src)/../include \
> - -I$(src)
> + -I $(srctree)/$(src)/../include \
> + -I $(srctree)/$(src)
>
> komeda-y := \
> komeda_drv.o \
For komeda:
Acked-by: Liviu Dudau
I'm assuming the series in going to be merged into one go, so I don't
have to take the individual patch in my tree, but if I'm wrong please
let me know.
Best regards,
Liviu
> diff --git a/drivers/gpu/drm/i915/gvt/Makefile
> b/drivers/gpu/drm/i915/gvt/Makefile
> index 271fb46..ea8324a 100644
> --- a/drivers/gpu/drm/i915/gvt/Makefile
> +++ b/drivers/gpu/drm/i915/gvt/Makefile
> @@ -5,5 +5,5 @@ GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o
> trace_points.o firmware.o \
> execlist.o scheduler.o sched_policy.o mmio_context.o cmd_parser.o
> debugfs.o \
> fb_decoder.o dmabuf.o page_track.o
>
> -ccflags-y+= -I$(src) -I$(src)/$(GVT_DIR)
> +ccflags-y+= -I $(srctree)/$(src) -I
> $(srctree)/$(src)/$(GVT_DIR)/
> i915-y += $(addprefix $(GVT_DIR)/,
> $(GVT_SOURCE))
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 56a70c7..b7b1ebd 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> -ccflags-y := -Idrivers/gpu/drm/msm
> -ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
> -ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
> +ccflags-y := -I $(srctree)/$(src)
> +ccflags-y += -I $(srctree)/$(src)/disp/dpu1
> +ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
>
> msm-y := \
> adreno/adreno_device.o \
> diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild
> index ea3035e..4fae728 100644
> --- a/drivers/gpu/drm/nouveau/Kbuild
> +++ b/drivers/gpu/drm/nouveau/Kbuild
> @@ -1,7 +1,7 @@
> -ccflags-y += -I$(src)/include
> -ccflags-y += -I$(src)/include/nvkm
> -ccflags-y += -I$(src)/nvkm
> -ccflags-y += -I$(src)
> +ccflags-y += -I $(srctree)/$(src)/include
> +ccflags-y += -I $(srctree)/$(src)/include/nvkm
> +ccflags-y += -I $(srctree)/$(src)/nvkm
> +ccflags-y += -I $(srctree)/$(src)
>
> # NVKM - HW resource manager
> #- code also used by various
Re: [Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Cc: Shashank Sharma
> Cc: "Kumar, Kiran S"
> Cc: Kausal Malladi
> Cc: Lionel Landwerlin
> Cc: Matt Roper
> Cc: Rob Bradford
> Cc: Daniel Stone
> Cc: Stefan Schake
> Cc: Eric Anholt
> Cc: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: amd-...@lists.freedesktop.org
> Cc: James (Qian) Wang
> Cc: Liviu Dudau
> Cc: Mali DP Maintainers
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Yannick Fertre
> Cc: Philippe Cornu
> Cc: Benjamin Gaignard
> Cc: Vincent Abriou
> Cc: Tomi Valkeinen
> Cc: Boris Brezillon
> Signed-off-by: Daniel Vetter Signed-off-by: Daniel
> Vetter
Acked-by: Liviu Dudau
Best regards,
Liviu
> ---
> include/uapi/drm/drm_mode.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 09d72966899a..83cd1636b9be 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -621,7 +621,8 @@ struct drm_color_ctm {
>
> struct drm_color_lut {
> /*
> - * Data is U0.16 fixed point format.
> + * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
> + * 0x == 1.0.
>*/
> __u16 red;
> __u16 green;
> --
> 2.20.1
>
--
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---
¯\_(ツ)_/¯
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Re: [Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
On 29/03/2019 09:20, Daniel Vetter wrote:
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0x.
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Shashank Sharma
Cc: "Kumar, Kiran S"
Cc: Kausal Malladi
Cc: Lionel Landwerlin
Cc: Matt Roper
Cc: Rob Bradford
Cc: Daniel Stone
Cc: Stefan Schake
Cc: Eric Anholt
Cc: Maarten Lankhorst
Cc: Harry Wentland
Cc: Leo Li
Cc: amd-...@lists.freedesktop.org
Cc: James (Qian) Wang
Cc: Liviu Dudau
Cc: Mali DP Maintainers
Cc: CK Hu
Cc: Philipp Zabel
Cc: Yannick Fertre
Cc: Philippe Cornu
Cc: Benjamin Gaignard
Cc: Vincent Abriou
Cc: Tomi Valkeinen
Cc: Boris Brezillon
Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter
---
include/uapi/drm/drm_mode.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 09d72966899a..83cd1636b9be 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -621,7 +621,8 @@ struct drm_color_ctm {
struct drm_color_lut {
/*
-* Data is U0.16 fixed point format.
+* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
+* 0x == 1.0.
*/
__u16 red;
__u16 green;
Thanks, that was the intention when it was introduced.
Acked-by: Lionel Landwerlin
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Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma luts
On 29/03/2019 14:29, Uma Shankar wrote: Register offsets used to program GC max were not correct. This series fixes the same, also limits the values to accurately clamp at 1.0. Also added support to program EXT2 GC Max needed for values from 3.0 to 7.0. Limiting it again to 1.0 due to ABI limitations. v2: Addressed Ville's review comments. Uma Shankar (2): drm/i915: Fix GCMAX color register programming drm/i915: Program EXT2 GC MAX registers drivers/gpu/drm/i915/i915_reg.h| 1 + drivers/gpu/drm/i915/intel_color.c | 44 -- 2 files changed, 34 insertions(+), 11 deletions(-) Curious about whether that fixed some of the issues you were seeing with the igt tests? :) -Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Cc: Shashank Sharma
> Cc: "Kumar, Kiran S"
> Cc: Kausal Malladi
> Cc: Lionel Landwerlin
> Cc: Matt Roper
> Cc: Rob Bradford
> Cc: Daniel Stone
> Cc: Stefan Schake
> Cc: Eric Anholt
> Cc: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: amd-...@lists.freedesktop.org
> Cc: James (Qian) Wang
> Cc: Liviu Dudau
> Cc: Mali DP Maintainers
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Yannick Fertre
> Cc: Philippe Cornu
> Cc: Benjamin Gaignard
> Cc: Vincent Abriou
> Cc: Tomi Valkeinen
> Cc: Boris Brezillon
> Signed-off-by: Daniel Vetter Signed-off-by: Daniel
> Vetter
> ---
> include/uapi/drm/drm_mode.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 09d72966899a..83cd1636b9be 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -621,7 +621,8 @@ struct drm_color_ctm {
>
> struct drm_color_lut {
> /*
> - * Data is U0.16 fixed point format.
> + * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
> + * 0x == 1.0.
>*/
Reviewed-by: Ville Syrjälä
> __u16 red;
> __u16 green;
> --
> 2.20.1
--
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts (rev2)
== Series Details == Series: Fixed GC MAX register programming for gamma luts (rev2) URL : https://patchwork.freedesktop.org/series/58734/ State : warning == Summary == $ dim checkpatch origin/drm-tip 88164253880f drm/i915: Fix GCMAX color register programming cad25ef86aee drm/i915: Program EXT2 GC MAX registers -:24: WARNING:LONG_LINE: line over 100 characters #24: FILE: drivers/gpu/drm/i915/i915_reg.h:10147: +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) total: 0 errors, 1 warnings, 0 checks, 41 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma luts
>-Original Message- >From: Landwerlin, Lionel G >Sent: Friday, March 29, 2019 8:00 PM >To: Shankar, Uma ; intel-gfx@lists.freedesktop.org >Cc: Syrjala, Ville ; Lankhorst, Maarten > >Subject: Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma >luts > >On 29/03/2019 14:29, Uma Shankar wrote: >> Register offsets used to program GC max were not correct. This series >> fixes the same, also limits the values to accurately clamp at 1.0. >> Also added support to program EXT2 GC Max needed for values from 3.0 >> to 7.0. Limiting it again to 1.0 due to ABI limitations. >> >> v2: Addressed Ville's review comments. >> >> Uma Shankar (2): >>drm/i915: Fix GCMAX color register programming >>drm/i915: Program EXT2 GC MAX registers >> >> drivers/gpu/drm/i915/i915_reg.h| 1 + >> drivers/gpu/drm/i915/intel_color.c | 44 >> -- >> 2 files changed, 34 insertions(+), 11 deletions(-) >> >Curious about whether that fixed some of the issues you were seeing with the >igt >tests? :) Unfortunately No Lionel, the test results are still the same :( > > >-Lionel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts (rev2)
== Series Details == Series: Fixed GC MAX register programming for gamma luts (rev2) URL : https://patchwork.freedesktop.org/series/58734/ State : success == Summary == CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12630 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58734/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12630 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_store@basic-bsd1: - fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41 * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_uncore: - fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110210] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2 * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: FAIL [fdo#103182] -> PASS +1 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (46 -> 40) -- Additional (2): fi-hsw-4770r fi-kbl-r Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bwr-2160 fi-bsw-cyan fi-bdw-samus Build changes - * Linux: CI_DRM_5837 -> Patchwork_12630 CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12630: cad25ef86aeec8f53dca8f9267402a8cf7ee705f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cad25ef86aee drm/i915: Program EXT2 GC MAX registers 88164253880f drm/i915: Fix GCMAX color register programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12630/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] linux-next: Tree for Mar 29 (i915, no ACPI)
On 3/28/19 8:18 PM, Stephen Rothwell wrote: > Hi all, > > Changes since 20190328: > > The pidfd tree lost its build failures. > on x86_64, when # CONFIG_ACPI is not set/enabled: ld: drivers/gpu/drm/i915/intel_panel.o: in function `intel_backlight_device_register': intel_panel.c:(.text+0x2c49): undefined reference to `backlight_device_register' ld: drivers/gpu/drm/i915/intel_panel.o: in function `intel_backlight_device_unregister': intel_panel.c:(.text+0x2d01): undefined reference to `backlight_device_unregister' Full randconfig file is attached. -- ~Randy # # Automatically generated file; DO NOT EDIT. # Linux/x86_64 5.1.0-rc2 Kernel Configuration # # # Compiler: gcc (SUSE Linux) 4.8.5 # CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=40805 CONFIG_CLANG_VERSION=0 CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_USELIB=y # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set # CONFIG_PREEMPT_NONE is not set # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set # CONFIG_PSI is not set # # RCU Subsystem # CONFIG_PREEMPT_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_LOG_BUF_SHIFT=17 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_CFS_BANDWIDTH is not set CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y # CONFIG_CGROUP_HUGETLB is not set # CONFIG_CGROUP_DEVICE is not set CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y # CONFIG_SYSFS_DEPRECATED is not set CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y # CONFIG_RD_LZMA is not set # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_ANON_INODES=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_BPF=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_PRINTK_NMI=y CONFIG_BUG=y CONFIG_PCSPKR_PLATFORM=y # CONFIG_BASE_FULL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y # CONFIG_AIO is not set CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y CONFIG_DEBUG_RSEQ=y CONFIG_EMBEDDED=y CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y # CONFIG_PC104 is not set # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y CONFIG_
Re: [Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Cc: Shashank Sharma
> Cc: "Kumar, Kiran S"
> Cc: Kausal Malladi
> Cc: Lionel Landwerlin
> Cc: Matt Roper
> Cc: Rob Bradford
> Cc: Daniel Stone
> Cc: Stefan Schake
> Cc: Eric Anholt
> Cc: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: amd-...@lists.freedesktop.org
> Cc: James (Qian) Wang
> Cc: Liviu Dudau
> Cc: Mali DP Maintainers
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Yannick Fertre
> Cc: Philippe Cornu
> Cc: Benjamin Gaignard
> Cc: Vincent Abriou
> Cc: Tomi Valkeinen
> Cc: Boris Brezillon
> Signed-off-by: Daniel Vetter Signed-off-by: Daniel
> Vetter
Looks like you're missing a newline between your two s-o-b's. But the
patch is
Reviewed-by: Matt Roper
> ---
> include/uapi/drm/drm_mode.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 09d72966899a..83cd1636b9be 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -621,7 +621,8 @@ struct drm_color_ctm {
>
> struct drm_color_lut {
> /*
> - * Data is U0.16 fixed point format.
> + * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
> + * 0x == 1.0.
>*/
> __u16 red;
> __u16 green;
> --
> 2.20.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Finish the GAMMA_LUT stuff (rev2)
== Series Details == Series: drm/i915: Finish the GAMMA_LUT stuff (rev2) URL : https://patchwork.freedesktop.org/series/58698/ State : success == Summary == CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12631 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58698/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12631 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-compute: - fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094] * igt@gem_exec_store@basic-bsd1: - fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41 * igt@i915_selftest@live_contexts: - fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@i915_selftest@live_hangcheck: - fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744] * igt@kms_busy@basic-flip-a: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_chamelium@vga-edid-read: - fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45 * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@runner@aborted: - fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602] - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2 * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094 [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 [fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235 Participating hosts (46 -> 40) -- Additional (2): fi-hsw-4770r fi-kbl-r Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-byt-n2820 fi-bdw-samus Build changes - * Linux: CI_DRM_5837 -> Patchwork_12631 CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12631: b44543b6b7646b03ab01690656847bcb18b5e033 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b44543b6b764 drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3 07bfd29fc7f8 drm/i915: Add "10.6" LUT mode for i965+ 5c7693fa7681 drm/i915: Add 10bit LUT for ilk/snb 60c673dde0b6 drm/i915: Implement split/10bit gamma for ivb/hsw f4ad2738a70b drm/i915: Don't use split gamma when we don't have to f87bd1be9aa8 drm/i915: Extract ilk_lut_10() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12631/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 4/8] drm/i915: vgpu context submission pv optimization
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f78829..28e8ee0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -37,6 +37,7 @@
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "intel_drv.h"
> +#include "i915_vgpu.h"
>
> /**
> * DOC: interrupt handling
> @@ -1470,6 +1471,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
> iir)
> if (iir & GT_RENDER_USER_INTERRUPT) {
> intel_engine_breadcrumbs_irq(engine);
> tasklet |= USES_GUC_SUBMISSION(engine->i915);
> + tasklet |= USES_PV_SUBMISSION(engine->i915);
We should move this to an engine->flag.
> }
>
> if (tasklet)
> +static void vgpu_pv_set_default_submission(struct intel_engine_cs *engine)
> +{
> + /*
> +* We inherit a bunch of functions from execlists that we'd like
> +* to keep using:
> +*
> +*engine->submit_request = execlists_submit_request;
> +*engine->cancel_requests = execlists_cancel_requests;
> +*engine->schedule = execlists_schedule;
> +*
> +* But we need to override the actual submission backend in order
> +* to talk to the GVT with PV notification message.
> +*/
> + intel_execlists_set_default_submission(engine);
> +
> + engine->execlists.tasklet.func = vgpu_pv_submission_tasklet;
You need to pin the breadcrumbs irq, or it will not fire on every
request.
I'd push for this to live in intel_pv_submission.c or
intel_vgpu_submission.c
> @@ -401,6 +551,12 @@ void intel_vgpu_config_pv_caps(struct drm_i915_private
> *dev_priv,
> ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
> ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
> }
> +
> + if (cap == PV_SUBMISSION) {
> + engine = (struct intel_engine_cs *)data;
> + engine->set_default_submission =
> vgpu_pv_set_default_submission;
> + engine->set_default_submission(engine);
> + }
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index c1b9780..0a66714 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2352,6 +2352,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs
> *engine)
> */
> }
> engine->emit_bb_start = gen8_emit_bb_start;
> +
> + if (intel_vgpu_active(engine->i915))
> + intel_vgpu_config_pv_caps(engine->i915, PV_SUBMISSION,
> engine);
That pair is ugly. Should clean up the engine initialisation so that it
doesn't involve placing a chunk of code in a foreign class.
-Chris
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[Intel-gfx] [PATCH] drm/i915: Move the decision to use the breadcrumb tasklet to the backend
Use the engine->flags to store whether we want to kick the submission
tasklet on receipt of a breadcrumb interrupt, so that this decision can
be made by the submission backend and not dependent on a limited feature
test within the interrupt handler. This should make it easier to adapt
different submission backends.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Xiaolin Zhang
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_engine_types.h | 7 +++
drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 455b2bf691b5..aa107a78cb36 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1470,7 +1470,7 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32
iir)
if (iir & GT_RENDER_USER_INTERRUPT) {
intel_engine_breadcrumbs_irq(engine);
- tasklet |= USES_GUC_SUBMISSION(engine->i915);
+ tasklet |= intel_engine_needs_breadcrumb_tasklet(engine);
}
if (tasklet)
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
b/drivers/gpu/drm/i915/intel_engine_types.h
index b3249bf6a65f..5c3f567a7a20 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -425,6 +425,7 @@ struct intel_engine_cs {
#define I915_ENGINE_SUPPORTS_STATS BIT(1)
#define I915_ENGINE_HAS_PREEMPTION BIT(2)
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
unsigned int flags;
/*
@@ -508,6 +509,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs
*engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
+static inline bool
+intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index c4ad73980988..c5896d47 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -1262,10 +1262,12 @@ static void guc_interrupts_release(struct
drm_i915_private *dev_priv)
static void guc_submission_park(struct intel_engine_cs *engine)
{
intel_engine_unpin_breadcrumbs_irq(engine);
+ engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
}
static void guc_submission_unpark(struct intel_engine_cs *engine)
{
+ engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
intel_engine_pin_breadcrumbs_irq(engine);
}
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/gamma: Clarify gamma lut uapi
On 3/29/19 10:20 AM, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Cc: Shashank Sharma
> Cc: "Kumar, Kiran S"
> Cc: Kausal Malladi
> Cc: Lionel Landwerlin
> Cc: Matt Roper
> Cc: Rob Bradford
> Cc: Daniel Stone
> Cc: Stefan Schake
> Cc: Eric Anholt
> Cc: Maarten Lankhorst
> Cc: Harry Wentland
> Cc: Leo Li
> Cc: amd-...@lists.freedesktop.org
> Cc: James (Qian) Wang
> Cc: Liviu Dudau
> Cc: Mali DP Maintainers
> Cc: CK Hu
> Cc: Philipp Zabel
> Cc: Yannick Fertre
> Cc: Philippe Cornu
> Cc: Benjamin Gaignard
> Cc: Vincent Abriou
> Cc: Tomi Valkeinen
> Cc: Boris Brezillon
> Signed-off-by: Daniel Vetter Signed-off-by: Daniel
> Vetter
> ---
> include/uapi/drm/drm_mode.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 09d72966899a..83cd1636b9be 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -621,7 +621,8 @@ struct drm_color_ctm {
>
> struct drm_color_lut {
> /*
> - * Data is U0.16 fixed point format.
> + * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
> + * 0x == 1.0.
for stm,
Reviewed-by: Philippe Cornu
Many thanks
Philippe :-)
>*/
> __u16 red;
> __u16 green;
>
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Re: [Intel-gfx] [PATCH v4 0/8] i915 vgpu PV to improve vgpu performance
Quoting Xiaolin Zhang (2019-03-29 13:32:36) > To improve vgpu performance, it could implement some PV optimization > such as to reduce the mmio access trap numbers or eliminate certain piece > of HW emulation within guest driver to reduce vm exit/vm enter cost. Where's the CI for this patchset? The lack of interrupts to drive submission should have shown up, and if not, we need some testcases to make sure it doesn't happen again. Everytime I see a gvt patch, I ask if we can get some coverage in intel-gfx-ci :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
