Re: [Intel-gfx] [v5 03/13] drm: Parse Colorimetry data block from EDID
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 1:01 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com
>Subject: RE: [v5 03/13] drm: Parse Colorimetry data block from EDID
>
>
>
>> -Original Message-
>> From: Shankar, Uma
>> Sent: Monday, March 11, 2019 9:28 AM
>> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
>> Cc: Lankhorst, Maarten ; Syrjala, Ville
>> ; Sharma, Shashank
>> ; emil.l.veli...@gmail.com;
>> brian.star...@arm.com; liviu.du...@arm.com; Shankar, Uma
>>
>> Subject: [v5 03/13] drm: Parse Colorimetry data block from EDID
>>
>> CEA 861.3 spec adds colorimetry data block for HDMI.
>> Parsing the block to get the colorimetry data from panel.
>>
>> v2: Rebase
>>
>> v3: No Change
>>
>> v4: Addressed Shashank's review comments. Updated colorimetry field to
>> 16 bit as
>> DCI-P3 got added in CEA 861-G spec, as pointed out by Shashank.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/drm_edid.c | 26 ++
>> include/drm/drm_connector.h | 3 +++
>> 2 files changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index
>> c5a81b8..0470845 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -2834,6 +2834,7 @@ static int drm_cvt_modes(struct drm_connector
>> *connector,
>> #define VIDEO_BLOCK 0x02
>> #define VENDOR_BLOCK0x03
>> #define SPEAKER_BLOCK 0x04
>> +#define COLORIMETRY_DATA_BLOCK 0x5
>> #define HDR_STATIC_METADATA_BLOCK 0x6
>> #define USE_EXTENDED_TAG 0x07
>> #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 @@ -3823,6 +3824,29 @@ static
>> void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
>> mode->clock = clock;
>> }
>>
>> +static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db) {
>Same comment for the opening brace above ?
Again this looks like mail client issue.
>> +if (cea_db_tag(db) != USE_EXTENDED_TAG)
>> +return false;
>> +
>> +if (db[1] != COLORIMETRY_DATA_BLOCK)
>Space before '!' ?
Same here.
>> +return false;
>> +
>> +return true;
>> +}
>> +
>> +static void
>> +drm_parse_colorimetry_data_block(struct drm_connector *connector,
>> +const
>> +u8 *db) {
>> +struct drm_hdmi_info *info = &connector->display_info.hdmi;
>> +uint16_t len;
>> +
>> +len = cea_db_payload_len_ext(db);
>> +/* As per CEA 861-G spec */
>> +info->colorimetry = ((db[3] & (0x1 << 7)) << 1) | db[2]; }
>This means we are setting the 15th bit for DCI-P3 then there is a gap of 7
>bits, and
>then there are other bits. Do we want to make DCI-P3 as bit 8 ? Anyways this
>can be
>differed for a discussion later.
This is at 8th position only. We are shifting the db[3] which is 8 bit by 1
and keeping the 7th bit (DCI-P3)
at the 8th position (if we count from 0).
Regards,
Uma Shankar
>> +
>> +
>> static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) {
>> if (cea_db_tag(db) != USE_EXTENDED_TAG) @@ -4495,6 +4519,8 @@ static
>> void drm_parse_cea_ext(struct drm_connector *connector,
>> drm_parse_vcdb(connector, db);
>> if (cea_db_is_hdmi_hdr_metadata_block(db))
>> drm_parse_hdr_metadata_block(connector, db);
>> +if (cea_db_is_hdmi_colorimetry_data_block(db))
>> +drm_parse_colorimetry_data_block(connector, db);
>> }
>> }
>>
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
>> index 29388bd..94f926e 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -206,6 +206,9 @@ struct drm_hdmi_info {
>>
>> /** @y420_dc_modes: bitmap of deep color support index */
>> u8 y420_dc_modes;
>> +
>> +/* @colorimetry: bitmap of supported colorimetry modes */
>> +u16 colorimetry;
>- Shashank
>> };
>>
>> /**
>> --
>> 1.9.1
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Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Introduce i9xx_has_pfit()
On 19/03/2019 14:23, Ville Syrjala wrote:
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
v2: s/gen4/gen>=4/ (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf2af75..98270d0cd763 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7961,14 +7961,22 @@ static int vlv_crtc_compute_clock(struct intel_crtc
*crtc,
return 0;
}
+static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
+{
+ if (IS_I830(dev_priv))
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 4 ||
+ IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
+}
+
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
- if (INTEL_GEN(dev_priv) <= 3 &&
- (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
+ if (!i9xx_has_pfit(dev_priv))
return;
tmp = I915_READ(PFIT_CONTROL);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [v5 04/13] drm/i915: Attach HDR metadata property to connector
>-Original Message- >From: Sharma, Shashank >Sent: Friday, March 15, 2019 1:06 PM >To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri- >de...@lists.freedesktop.org >Cc: Lankhorst, Maarten ; Syrjala, Ville >; emil.l.veli...@gmail.com; brian.star...@arm.com; >liviu.du...@arm.com >Subject: RE: [v5 04/13] drm/i915: Attach HDR metadata property to connector > > > >> -Original Message- >> From: Shankar, Uma >> Sent: Monday, March 11, 2019 9:28 AM >> To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org >> Cc: Lankhorst, Maarten ; Syrjala, Ville >> ; Sharma, Shashank >> ; emil.l.veli...@gmail.com; >> brian.star...@arm.com; liviu.du...@arm.com; Shankar, Uma >> >> Subject: [v5 04/13] drm/i915: Attach HDR metadata property to >> connector >> >> Attach HDR metadata property to connector object. >> >> v2: Rebase >> >> v3: Updated the property name as per updated name while creating hdr >> metadata property >> >> Signed-off-by: Uma Shankar >> --- >> drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c >> b/drivers/gpu/drm/i915/intel_hdmi.c >> index cd422a7..0952475 100644 >> --- a/drivers/gpu/drm/i915/intel_hdmi.c >> +++ b/drivers/gpu/drm/i915/intel_hdmi.c >> @@ -2719,6 +2719,8 @@ static void intel_hdmi_destroy(struct >> drm_connector >> *connector) >> >> drm_connector_attach_content_type_property(connector); >> connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; >> +drm_object_attach_property(&connector->base, >> +connector->dev->mode_config.hdr_output_metadata_property, 0); >'connector->dev' should be aligned to the line above, but seems like you have >done >this to meet the 80 char limit. >May be a local ptr variable will help with 80 char. Thanks Shashank, the name itself is a bit long. I will align it and can see crossing 80 characters for these kind of cases is ok. Being done in driver at several places. Thanks for the review. Regards, Uma Shankar > >Apart from that, looks good to me, and feel free to use: >Reviewed-by: Shashank Sharma >> >> if (!HAS_GMCH(dev_priv)) >> drm_connector_attach_max_bpc_property(connector, 8, 12); >> -- >> 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/selftests: add test to verify get/put fw domains
From: Daniele Ceraolo Spurio
Exercise acquiring and releasing forcewake around register reads. In
order to read a register behind a GT powerwell, we need to instruct that
powerwell to wake up using a forcewake. When we no longer require the GT
powerwell, we tell the GT to release our forcewake. Inside the
forcewake, the register read should work but outside it should just
return garbage, 0 being the most common garbage. Thus we can detect when
we are inside and outside of the forcewake with just a simple register
read, and so can verify that the GT powerwell is released when we say
so.
v2: Picked the right forcewaked register to return 0 outside of
forcewake is an art.
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 134 +-
1 file changed, 128 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 81d9d31042a9..84ce50d732b7 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -119,9 +119,130 @@ int intel_uncore_mock_selftests(void)
return 0;
}
-static int intel_uncore_check_forcewake_domains(struct drm_i915_private
*dev_priv)
+static int live_forcewake_ops(void *arg)
+{
+ static const struct reg {
+ unsigned long platforms;
+ const char *name;
+ unsigned int offset;
+ } registers[] = {
+ {
+ INTEL_GEN_MASK(6, 7),
+ "RING_START",
+ 0x38,
+ },
+ {
+ INTEL_GEN_MASK(8, BITS_PER_LONG - 1),
+ "RING_MI_MODE",
+ 0x9c,
+ }
+ };
+ const struct reg *r;
+ struct drm_i915_private *i915 = arg;
+ struct intel_uncore_forcewake_domain *domain;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ intel_wakeref_t wakeref;
+ unsigned int tmp;
+ int err = 0;
+
+ GEM_BUG_ON(i915->gt.awake);
+
+ /* vlv/chv with their pcu behave differently wrt reads */
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ pr_debug("PCU fakes forcewake badly; skipping\n");
+ return 0;
+ }
+
+ /* We have to pick carefully to get the exact behaviour we need */
+ for (r = registers; r->name; r++)
+ if (r->platforms & INTEL_INFO(i915)->gen_mask)
+ break;
+ if (!r->name) {
+ pr_debug("Forcewaked register not known for %s; skipping\n",
+intel_platform_name(INTEL_INFO(i915)->platform));
+ return 0;
+ }
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ for_each_fw_domain(domain, i915, tmp) {
+ smp_store_mb(domain->active, false);
+ if (!hrtimer_cancel(&domain->timer))
+ continue;
+
+ intel_uncore_fw_release_timer(&domain->timer);
+ }
+
+ for_each_engine(engine, i915, id) {
+ i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
+ u32 __iomem *reg = i915->regs + engine->mmio_base + r->offset;
+ enum forcewake_domains fw_domains;
+ u32 val;
+
+ if (!engine->default_state)
+ continue;
+
+ fw_domains = intel_uncore_forcewake_for_reg(i915, mmio,
+ FW_REG_READ);
+ if (!fw_domains)
+ continue;
+
+ for_each_fw_domain_masked(domain, fw_domains, i915, tmp) {
+ if (!domain->wake_count)
+ continue;
+
+ pr_err("fw_domain %s still active, aborting test!\n",
+
intel_uncore_forcewake_domain_to_str(domain->id));
+ err = -EINVAL;
+ goto out_rpm;
+ }
+
+ intel_uncore_forcewake_get(i915, fw_domains);
+ val = readl(reg);
+ intel_uncore_forcewake_put(i915, fw_domains);
+
+ /* Flush the forcewake release (delayed onto a timer) */
+ for_each_fw_domain_masked(domain, fw_domains, i915, tmp) {
+ smp_store_mb(domain->active, false);
+ if (hrtimer_cancel(&domain->timer))
+ intel_uncore_fw_release_timer(&domain->timer);
+
+ preempt_disable();
+ err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
+ preempt_enable();
+ if (err) {
+ pr_err("Failed to clear fw_domain %s\n",
+
intel_uncore_forcewake_domain
Re: [Intel-gfx] [v5 03/13] drm: Parse Colorimetry data block from EDID
On 3/20/2019 12:47 PM, Shankar, Uma wrote:
-Original Message-
From: Sharma, Shashank
Sent: Friday, March 15, 2019 1:01 PM
To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; emil.l.veli...@gmail.com; brian.star...@arm.com;
liviu.du...@arm.com
Subject: RE: [v5 03/13] drm: Parse Colorimetry data block from EDID
-Original Message-
From: Shankar, Uma
Sent: Monday, March 11, 2019 9:28 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; Sharma, Shashank
; emil.l.veli...@gmail.com;
brian.star...@arm.com; liviu.du...@arm.com; Shankar, Uma
Subject: [v5 03/13] drm: Parse Colorimetry data block from EDID
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from panel.
v2: Rebase
v3: No Change
v4: Addressed Shashank's review comments. Updated colorimetry field to
16 bit as
DCI-P3 got added in CEA 861-G spec, as pointed out by Shashank.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 26 ++
include/drm/drm_connector.h | 3 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index
c5a81b8..0470845 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2834,6 +2834,7 @@ static int drm_cvt_modes(struct drm_connector
*connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK 0x04
+#define COLORIMETRY_DATA_BLOCK 0x5
#define HDR_STATIC_METADATA_BLOCK 0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00 @@ -3823,6 +3824,29 @@ static
void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db) {
Same comment for the opening brace above ?
Again this looks like mail client issue.
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != COLORIMETRY_DATA_BLOCK)
Space before '!' ?
Same here.
+ return false;
+
+ return true;
+}
+
+static void
+drm_parse_colorimetry_data_block(struct drm_connector *connector,
+const
+u8 *db) {
+ struct drm_hdmi_info *info = &connector->display_info.hdmi;
+ uint16_t len;
+
+ len = cea_db_payload_len_ext(db);
+ /* As per CEA 861-G spec */
+ info->colorimetry = ((db[3] & (0x1 << 7)) << 1) | db[2]; }
This means we are setting the 15th bit for DCI-P3 then there is a gap of 7
bits, and
then there are other bits. Do we want to make DCI-P3 as bit 8 ? Anyways this
can be
differed for a discussion later.
This is at 8th position only. We are shifting the db[3] which is 8 bit by 1
and keeping the 7th bit (DCI-P3)
at the 8th position (if we count from 0).
Regards,
Uma Shankar
My bad, its 8th bit only.
If those above alignment problems are checked already, feel free to use
Reviewed-by: Shashank Sharma
- Shashank
+
+
static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) {
if (cea_db_tag(db) != USE_EXTENDED_TAG) @@ -4495,6 +4519,8 @@ static
void drm_parse_cea_ext(struct drm_connector *connector,
drm_parse_vcdb(connector, db);
if (cea_db_is_hdmi_hdr_metadata_block(db))
drm_parse_hdr_metadata_block(connector, db);
+ if (cea_db_is_hdmi_colorimetry_data_block(db))
+ drm_parse_colorimetry_data_block(connector, db);
}
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 29388bd..94f926e 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -206,6 +206,9 @@ struct drm_hdmi_info {
/** @y420_dc_modes: bitmap of deep color support index */
u8 y420_dc_modes;
+
+ /* @colorimetry: bitmap of supported colorimetry modes */
+ u16 colorimetry;
- Shashank
};
/**
--
1.9.1
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Re: [Intel-gfx] [PATCH 3/3] drm/i915/selftests: Provide stub reset functions
Chris Wilson writes:
> If a test fails, we quite often mark the device as wedged. Provide the
> stub functions so that we can wedge the mock device, and avoid exploding
> on test failures.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109981
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/selftests/mock_engine.c | 36
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c
> b/drivers/gpu/drm/i915/selftests/mock_engine.c
> index 639d36eb904a..61744819172b 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_engine.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
> @@ -198,6 +198,37 @@ static void mock_submit_request(struct i915_request
> *request)
> spin_unlock_irqrestore(&engine->hw_lock, flags);
> }
>
> +static void mock_reset_prepare(struct intel_engine_cs *engine)
> +{
> +}
> +
> +static void mock_reset(struct intel_engine_cs *engine, bool stalled)
> +{
> + GEM_BUG_ON(stalled);
> +}
> +
> +static void mock_reset_finish(struct intel_engine_cs *engine)
> +{
> +}
> +
> +static void mock_cancel_requests(struct intel_engine_cs *engine)
> +{
> + struct i915_request *request;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&engine->timeline.lock, flags);
> +
> + /* Mark all submitted requests as skipped. */
> + list_for_each_entry(request, &engine->timeline.requests, sched.link) {
> + if (!i915_request_signaled(request))
> + dma_fence_set_error(&request->fence, -EIO);
> +
> + i915_request_mark_complete(request);
> + }
> +
> + spin_unlock_irqrestore(&engine->timeline.lock, flags);
> +}
> +
> struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
> const char *name,
> int id)
> @@ -223,6 +254,11 @@ struct intel_engine_cs *mock_engine(struct
> drm_i915_private *i915,
> engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
> engine->base.submit_request = mock_submit_request;
>
> + engine->base.reset.prepare = mock_reset_prepare;
> + engine->base.reset.reset = mock_reset;
> + engine->base.reset.finish = mock_reset_finish;
> + engine->base.cancel_requests = mock_cancel_requests;
> +
> if (i915_timeline_init(i915,
> &engine->base.timeline,
> engine->base.name,
> --
> 2.20.1
___
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Re: [Intel-gfx] [v5 03/13] drm: Parse Colorimetry data block from EDID
>On 3/20/2019 12:47 PM, Shankar, Uma wrote:
>>
>>> -Original Message-
>>> From: Sharma, Shashank
>>> Sent: Friday, March 15, 2019 1:01 PM
>>> To: Shankar, Uma ;
>>> intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org
>>> Cc: Lankhorst, Maarten ; Syrjala, Ville
>>> ; emil.l.veli...@gmail.com;
>>> brian.star...@arm.com; liviu.du...@arm.com
>>> Subject: RE: [v5 03/13] drm: Parse Colorimetry data block from EDID
>>>
>>>
>>>
-Original Message-
From: Shankar, Uma
Sent: Monday, March 11, 2019 9:28 AM
To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; Sharma, Shashank
; emil.l.veli...@gmail.com;
brian.star...@arm.com; liviu.du...@arm.com; Shankar, Uma
Subject: [v5 03/13] drm: Parse Colorimetry data block from EDID
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from panel.
v2: Rebase
v3: No Change
v4: Addressed Shashank's review comments. Updated colorimetry field
to
16 bit as
DCI-P3 got added in CEA 861-G spec, as pointed out by Shashank.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 26 ++
include/drm/drm_connector.h | 3 +++
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index
c5a81b8..0470845 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2834,6 +2834,7 @@ static int drm_cvt_modes(struct drm_connector
*connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK0x04
+#define COLORIMETRY_DATA_BLOCK0x5
#define HDR_STATIC_METADATA_BLOCK0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00 @@ -3823,6 +3824,29 @@
static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db) {
>>> Same comment for the opening brace above ?
>> Again this looks like mail client issue.
>>
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != COLORIMETRY_DATA_BLOCK)
>>> Space before '!' ?
>> Same here.
>>
+ return false;
+
+ return true;
+}
+
+static void
+drm_parse_colorimetry_data_block(struct drm_connector *connector,
+const
+u8 *db) {
+ struct drm_hdmi_info *info = &connector->display_info.hdmi;
+ uint16_t len;
+
+ len = cea_db_payload_len_ext(db);
+ /* As per CEA 861-G spec */
+ info->colorimetry = ((db[3] & (0x1 << 7)) << 1) | db[2]; }
>>> This means we are setting the 15th bit for DCI-P3 then there is a gap
>>> of 7 bits, and then there are other bits. Do we want to make DCI-P3
>>> as bit 8 ? Anyways this can be differed for a discussion later.
>> This is at 8th position only. We are shifting the db[3] which is 8
>> bit by 1 and keeping the 7th bit (DCI-P3) at the 8th position (if we count
>> from 0).
>>
>> Regards,
>> Uma Shankar
>
>My bad, its 8th bit only.
>
>If those above alignment problems are checked already, feel free to use
>
>Reviewed-by: Shashank Sharma
No Issues, Thanks Shashank.
Regards,
Uma Shankar
>- Shashank
>
+
+
static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) {
if (cea_db_tag(db) != USE_EXTENDED_TAG) @@ -4495,6 +4519,8 @@
static void drm_parse_cea_ext(struct drm_connector *connector,
drm_parse_vcdb(connector, db);
if (cea_db_is_hdmi_hdr_metadata_block(db))
drm_parse_hdr_metadata_block(connector, db);
+ if (cea_db_is_hdmi_colorimetry_data_block(db))
+ drm_parse_colorimetry_data_block(connector, db);
}
}
diff --git a/include/drm/drm_connector.h
b/include/drm/drm_connector.h index 29388bd..94f926e 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -206,6 +206,9 @@ struct drm_hdmi_info {
/** @y420_dc_modes: bitmap of deep color support index */
u8 y420_dc_modes;
+
+ /* @colorimetry: bitmap of supported colorimetry modes */
+ u16 colorimetry;
>>> - Shashank
};
/**
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
On Tue, 19 Mar 2019, Manasi Navare wrote:
> This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> to correctly do the left shifting to set the port sync
> master select correctly.
> I have tested this fix on ICL.
>
> Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers")
> Cc: Madhav Chauhan
> Cc: Jani Nikula
> Signed-off-by: Manasi Navare
Auch.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85e8d1a1f70b..7a9d867eb49b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9352,7 +9352,7 @@ enum skl_power_gate {
> #define TRANS_DDI_FUNC_CTL2(tran)_MMIO_TRANS2(tran, \
>_TRANS_DDI_FUNC_CTL2_A)
> #define PORT_SYNC_MODE_ENABLE (1 << 4)
> -#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
> +#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
> #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
> #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT 0
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
== Series Details == Series: drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro URL : https://patchwork.freedesktop.org/series/58204/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5775_full -> Patchwork_12520_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12520_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12520_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12520_full: ### IGT changes ### Possible regressions * igt@gem_create@create-clear: - shard-iclb: PASS -> DMESG-WARN * igt@runner@aborted: - shard-iclb: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12520_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_big: - shard-hsw: PASS -> TIMEOUT [fdo#107936] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> DMESG-WARN [fdo#108686] * igt@gem_wait@wait-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@kms_atomic_transition@5x-modeset-transitions-fencing: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@basic-flip-e: - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-hang-oldfb-render-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_chamelium@hdmi-cmp-yv16: - shard-skl: NOTRUN -> SKIP [fdo#109271] +17 * igt@kms_cursor_crc@cursor-256x256-sliding: - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_draw_crc@draw-method-xrgb-mmap-cpu-xtiled: - shard-skl: PASS -> FAIL [fdo#107791] * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: PASS -> INCOMPLETE [fdo#109507] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-glk: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: - shard-apl: NOTRUN -> SKIP [fdo#109271] +9 * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite: - shard-skl: PASS -> FAIL [fdo#105682] +1 * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-iclb: PASS -> FAIL [fdo#103167] +8 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +11 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt: - shard-hsw: NOTRUN -> SKIP [fdo#109271] +36 * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@psr2_primary_mmap_cpu: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +16 * igt@kms_psr@psr2_sprite_plane_onoff: - shard-iclb: PASS -> SKIP [fdo#109441] +2 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: PASS -> FAIL [fdo#109016] * igt@kms_setmode@basic: - shard-apl: PASS -> FAIL [fdo#99912] - shard-hsw: PASS -> FAIL [fdo#99912] - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: PASS -> FAIL [fdo#104894] Possible fixes * igt@gem_eio@reset-stress: - shard-snb: FAIL [fdo#109661] -> PASS * igt@i915_selftest@live_workarounds: - shard-iclb: DMESG-FAIL [fdo#108954] -> PASS * igt@kms_ccs@pipe-b-crc-sprite-planes-basic: - shard-iclb: FAIL [fdo#107725] -> PASS * igt@kms_cursor_crc@cursor-128x42-ons
[Intel-gfx] [PATCH v8 4/4] drm/i915: Skip modeset for cdclk changes if possible
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe needs a modeset (or was disabled).
- Split CDCLK change to a pre/post plane update step.
v3:
- Use correct version of CDCLK state as old state. (Ville)
- Remove unused intel_cdclk_can_skip_modeset()
v4:
- For consistency call intel_set_cdclk_post_plane_update() only during
modesets (and not fastsets).
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
Tested-by: Abhay Kumar
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_cdclk.c | 142 +++
drivers/gpu/drm/i915/intel_display.c | 42 ++-
drivers/gpu/drm/i915/intel_drv.h | 17 -
5 files changed, 170 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b10cee4e77f..d8f91525c94c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -277,7 +277,8 @@ struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state);
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9b69cec21f7b..12b8170ced96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9521,7 +9521,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
-#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
+#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE(1 << 16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 5c25626f8cf0..48cc42a7ef4f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -516,7 +516,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv)
}
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -598,7 +599,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -697,7 +699,8 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
}
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val;
@@ -987,7 +990,8 @@ static void skl_dpll0_disable(struct drm_i915_private
*dev_priv)
}
static void skl_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
@@ -1158,7 +1162,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state);
+ skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
}
/**
@@ -1176,7 +1180,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.vco = 0;
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state);
[Intel-gfx] [PATCH v8 2/4] drm/i915: Save the old CDCLK atomic state
The old state will be needed by an upcoming patch to determine if the
commit increases or decreases CDCLK, so move the old state to the atomic
state (while keeping the new one in dev_priv). cdclk.logical and
cdclk.actual in the atomic state isn't used atm anywhere after the
atomic check phase, so this should be safe.
v2:
- Use swap() instead of opencoding it. (Ville)
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_cdclk.c | 20
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 7dcca84f31d1..5c25626f8cf0 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2100,6 +2100,26 @@ bool intel_cdclk_changed(const struct intel_cdclk_state
*a,
a->voltage_level != b->voltage_level;
}
+/**
+ * intel_cdclk_swap_state - make atomic CDCLK configuration effective
+ * @state: atomic state
+ *
+ * This is the CDCLK version of drm_atomic_helper_swap_state() since the
+ * helper does not handle driver-specific global state.
+ *
+ * Similarly to the atomic helpers this function does a complete swap,
+ * i.e. it also puts the old state into @state. This is used by the commit
+ * code to determine how CDCLK has changed (for instance did it increase or
+ * decrease).
+ */
+void intel_cdclk_swap_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ swap(state->cdclk.logical, dev_priv->cdclk.logical);
+ swap(state->cdclk.actual, dev_priv->cdclk.actual);
+}
+
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
const char *context)
{
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b4199cd53349..9c4ad124302c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13663,10 +13663,10 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_state->min_voltage_level,
sizeof(intel_state->min_voltage_level));
dev_priv->active_crtcs = intel_state->active_crtcs;
- dev_priv->cdclk.logical = intel_state->cdclk.logical;
- dev_priv->cdclk.actual = intel_state->cdclk.actual;
dev_priv->cdclk.force_min_cdclk =
intel_state->cdclk.force_min_cdclk;
+
+ intel_cdclk_swap_state(intel_state);
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b84e557c267..85dd6a9d1e42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1698,6 +1698,7 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_state *a,
const struct intel_cdclk_state *b);
bool intel_cdclk_changed(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
+void intel_cdclk_swap_state(struct intel_atomic_state *state);
void intel_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state);
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
--
2.13.2
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Re: [Intel-gfx] [v5 06/13] drm: Enable HDR infoframe support
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 1:54 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com; Ville Syrjälä
>Subject: Re: [v5 06/13] drm: Enable HDR infoframe support
>
>
>On 3/11/2019 9:27 AM, Uma Shankar wrote:
>> Enable Dynamic Range and Mastering Infoframe for HDR content, which is
>> defined in CEA 861.3 spec.
>>
>> The metadata will be computed based on blending policy in userspace
>> compositors and passed as a connector property blob to driver. The
>> same will be sent as infoframe to panel which support HDR.
>>
>> v2: Rebase and added Ville's POC changes.
>>
>> v3: No Change
>>
>> v4: Addressed Shashank's review comments and merged the patch making
>> drm infoframe function arguments as constant.
>>
>> v5: Rebase
>>
>> Signed-off-by: Uma Shankar
>> Signed-off-by: Ville Syrjälä
>> ---
>> drivers/gpu/drm/drm_edid.c | 58
>> drivers/video/hdmi.c | 129
>+
>> include/drm/drm_edid.h | 4 ++
>> include/linux/hdmi.h | 22
>> 4 files changed, 213 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 0470845..49f8340 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -4914,6 +4914,64 @@ static bool is_hdmi2_sink(struct drm_connector
>*connector)
>> }
>>
>> /**
>> + * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
>> + * HDR metadata from userspace
>> + * @frame: HDMI AVI infoframe
>> + * @hdr_source_metadata: hdr_source_metadata info from userspace
>> + *
>> + * Return: 0 on success or a negative error code on failure.
>> + */
>> +int
>> +drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
>> +void *hdr_metadata)
>Alignment with bracket above
This is email client issue.
>> +{
>> +struct hdr_static_metadata *hdr_source_metadata;
>> +int err, i;
>> +
>> +if (!frame || !hdr_metadata)
>> +return true;
>> +
>> +err = hdmi_drm_infoframe_init(frame);
>> +if (err < 0)
>> +return err;
>> +
>> +DRM_DEBUG_KMS("type = %x\n", frame->type);
>> +
>> +hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
>> +
>> +frame->length = sizeof(struct hdr_static_metadata);
>> +
>extra blank line
Sure, will fix this.
>> +
>> +frame->eotf = hdr_source_metadata->eotf;
>> +frame->metadata_type = hdr_source_metadata->metadata_type;
>> +
>> +for (i = 0; i < 3; i++) {
>> +frame->display_primaries[i].x =
>> +hdr_source_metadata->display_primaries[i].x;
>> +frame->display_primaries[i].y =
>> +hdr_source_metadata->display_primaries[i].y;
>> +}
>memcpy here to avoid loop ?
I feel it makes it more clear as what data is getting copied. If no hard
objection,
let's keep it this way.
>> +
>> +frame->white_point.x = hdr_source_metadata->white_point.x;
>> +frame->white_point.y = hdr_source_metadata->white_point.y;
>> +
>> +frame->max_mastering_display_luminance =
>> +hdr_source_metadata->max_mastering_display_luminance;
>> +frame->min_mastering_display_luminance =
>> +hdr_source_metadata->min_mastering_display_luminance;
>> +
>> +frame->max_cll = hdr_source_metadata->max_cll;
>> +frame->max_fall = hdr_source_metadata->max_fall;
>> +
>In fact the structures look so analogues, can we do a complete memcpy of one
>structure to other ? or the sequence of the elements is different ?
There are slightly different elements as well so it would be good to have
member by member copy.
This will also help check in case any issues with metadata input.
>> +hdmi_infoframe_log(KERN_CRIT, NULL,
>> + (union hdmi_infoframe *)frame);
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
>> +
>> +
>> +/**
>>* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe
>with
>>* data from a DRM display
>> mode
>>* @frame: HDMI AVI infoframe
>> diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index
>> 799ae49..7ab8086 100644
>> --- a/drivers/video/hdmi.c
>> +++ b/drivers/video/hdmi.c
>> @@ -650,6 +650,93 @@ ssize_t hdmi_vendor_infoframe_pack(struct
>hdmi_vendor_infoframe *frame,
>> return 0;
>> }
>>
>> +/**
>> + * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and
>> + * mastering infoframe
>> + * @frame: HDMI DRM infoframe
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) {
>> +memset(frame, 0, sizeof(*frame));
>> +
>> +fr
[Intel-gfx] [PATCH] drm/i915/selftests: Mark up preemption tests for hang detection
Use the igt_live_test framework for detecting whether an unwanted hang
occurred during test execution, and report failure if it does.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 38 --
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c
b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index 42068ed5eec0..59bc39275589 100644
--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
@@ -10,6 +10,7 @@
#include "../i915_selftest.h"
#include "igt_flush_test.h"
+#include "igt_live_test.h"
#include "igt_spinner.h"
#include "i915_random.h"
@@ -113,11 +114,17 @@ static int live_preempt(void *arg)
I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY);
for_each_engine(engine, i915, id) {
+ struct igt_live_test t;
struct i915_request *rq;
if (!intel_engine_has_preemption(engine))
continue;
+ if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
+ err = -EIO;
+ goto err_ctx_lo;
+ }
+
rq = igt_spinner_create_request(&spin_lo, ctx_lo, engine,
MI_ARB_CHECK);
if (IS_ERR(rq)) {
@@ -153,7 +160,8 @@ static int live_preempt(void *arg)
igt_spinner_end(&spin_hi);
igt_spinner_end(&spin_lo);
- if (igt_flush_test(i915, I915_WAIT_LOCKED)) {
+
+ if (igt_live_test_end(&t)) {
err = -EIO;
goto err_ctx_lo;
}
@@ -207,11 +215,17 @@ static int live_late_preempt(void *arg)
goto err_ctx_hi;
for_each_engine(engine, i915, id) {
+ struct igt_live_test t;
struct i915_request *rq;
if (!intel_engine_has_preemption(engine))
continue;
+ if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
+ err = -EIO;
+ goto err_ctx_lo;
+ }
+
rq = igt_spinner_create_request(&spin_lo, ctx_lo, engine,
MI_ARB_CHECK);
if (IS_ERR(rq)) {
@@ -250,7 +264,8 @@ static int live_late_preempt(void *arg)
igt_spinner_end(&spin_hi);
igt_spinner_end(&spin_lo);
- if (igt_flush_test(i915, I915_WAIT_LOCKED)) {
+
+ if (igt_live_test_end(&t)) {
err = -EIO;
goto err_ctx_lo;
}
@@ -615,6 +630,7 @@ static int live_chain_preempt(void *arg)
struct i915_sched_attr attr = {
.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
};
+ struct igt_live_test t;
struct i915_request *rq;
int ring_size, count, i;
@@ -641,6 +657,11 @@ static int live_chain_preempt(void *arg)
goto err_wedged;
}
+ if (igt_live_test_begin(&t, i915, __func__, engine->name)) {
+ err = -EIO;
+ goto err_wedged;
+ }
+
for_each_prime_number_from(count, 1, ring_size) {
rq = igt_spinner_create_request(&hi.spin,
hi.ctx, engine,
@@ -699,6 +720,11 @@ static int live_chain_preempt(void *arg)
goto err_wedged;
}
}
+
+ if (igt_live_test_end(&t)) {
+ err = -EIO;
+ goto err_wedged;
+ }
}
err = 0;
@@ -1022,6 +1048,7 @@ static int live_preempt_smoke(void *arg)
};
const unsigned int phase[] = { 0, BATCH };
intel_wakeref_t wakeref;
+ struct igt_live_test t;
int err = -ENOMEM;
u32 *cs;
int n;
@@ -1058,6 +1085,11 @@ static int live_preempt_smoke(void *arg)
if (err)
goto err_batch;
+ if (igt_live_test_begin(&t, smoke.i915, __func__, "all")) {
+ err = -EIO;
+ goto err_batch;
+ }
+
for (n = 0; n < smoke.ncontext; n++) {
smoke.contexts[n] = kernel_context(smoke.i915);
if (!smoke.contexts[n])
@@ -1075,7 +1107,7 @@ static int live_preempt_smoke(void *arg)
}
err_ctx:
- if (igt_flush_test(smoke.i915, I915_WAIT_LOCKED))
+ if (igt_live_test_end(&t))
err = -EIO;
for (n = 0; n < smoke.ncontext; n++) {
--
2.20.1
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Re: [Intel-gfx] [v5 07/13] drm/i915: Write HDR infoframe and send to panel
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 4:38 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com
>Subject: Re: [v5 07/13] drm/i915: Write HDR infoframe and send to panel
>
>
>On 3/11/2019 9:27 AM, Uma Shankar wrote:
>> Enable writing of HDR metadata infoframe to panel.
>> The data will be provid by usersapace compositors, based on blending
>> policies and passsed to driver through a blob property.
>>
>> v2: Rebase
>>
>> v3: Fixed a warning message
>>
>> v4: Addressed Shashank's review comments
>>
>> v5: Rebase. Added infoframe calculation in compute config.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/intel_drv.h | 1 +
>> drivers/gpu/drm/i915/intel_hdmi.c | 33 +
>> 2 files changed, 34 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 58483f8..a5ee124 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1037,6 +1037,7 @@ struct intel_crtc_state {
>> union hdmi_infoframe avi;
>> union hdmi_infoframe spd;
>> union hdmi_infoframe hdmi;
>> +union hdmi_infoframe drm;
>> } infoframes;
>>
>> /* HDMI scrambling status */
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>> b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 0952475..ea7afa0 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -555,6 +555,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
>*encoder,
>> HDMI_INFOFRAME_TYPE_AVI,
>> HDMI_INFOFRAME_TYPE_SPD,
>> HDMI_INFOFRAME_TYPE_VENDOR,
>> +HDMI_INFOFRAME_TYPE_DRM,
>> };
>>
>> u32 intel_hdmi_infoframe_enable(unsigned int type) @@ -777,6 +778,30
>> @@ void intel_read_infoframe(struct intel_encoder *encoder,
>> return true;
>> }
>>
>> +static bool
>> +intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
>> + struct intel_crtc_state *crtc_state,
>> + struct drm_connector_state *conn_state) {
>> +struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
>> +struct hdr_static_metadata *hdr_metadata;
>> +int ret;
>> +
>
>Don't we need a GEN/monitor check before going ahead with HDR metadata ?
Sure, will add that check.
Regards,
Uma Shankar
>- Shashank
>
>> +hdr_metadata = (struct hdr_static_metadata *)
>> +conn_state->hdr_output_metadata_blob_ptr->data;
>> +
>> +ret = drm_hdmi_infoframe_set_hdr_metadata(frame, hdr_metadata);
>> +if (ret < 0) {
>> +DRM_ERROR("couldn't set HDR metadata in infoframe\n");
>> +return false;
>> +}
>> +
>> +crtc_state->infoframes.enable |=
>> +intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
>> +
>> +return true;
>> +}
>> +
>> static void g4x_set_infoframes(struct intel_encoder *encoder,
>> bool enable,
>> const struct intel_crtc_state *crtc_state, @@
>> -1175,6
>> +1200,9 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,
>> intel_write_infoframe(encoder, crtc_state,
>>HDMI_INFOFRAME_TYPE_VENDOR,
>>&crtc_state->infoframes.hdmi);
>> +intel_write_infoframe(encoder, crtc_state,
>> + HDMI_INFOFRAME_TYPE_DRM,
>> + &crtc_state->infoframes.drm);
>> }
>>
>> void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi,
>> bool enable) @@ -2381,6 +2409,11 @@ int intel_hdmi_compute_config(struct
>intel_encoder *encoder,
>> return -EINVAL;
>> }
>>
>> +if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config,
>> conn_state)) {
>> +DRM_DEBUG_KMS("bad DRM infoframe\n");
>> +return -EINVAL;
>> +}
>> +
>> return 0;
>> }
>>
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Re: [Intel-gfx] [PATCH v7 4/4] drm/i915: Skip modeset for cdclk changes if possible
Hi Imre, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on next-20190320] [cannot apply to v5.1-rc1] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Imre-Deak/drm-i915-Ensure-minimum-CDCLK-requirement-for-audio/20190320-130829 base: git://anongit.freedesktop.org/drm-intel for-linux-next reproduce: make htmldocs All warnings (new ones prefixed by >>): net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.last_rate' not described in 'sta_info' net/mac80211/sta_info.h:590: warning: Function parameter or member 'tx_stats.msdu' not described in 'sta_info' kernel/rcu/tree.c:711: warning: Excess function parameter 'irq' description in 'rcu_nmi_exit' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.cb' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.poll' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_excl.active' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.cb' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.poll' not described in 'dma_buf' include/linux/dma-buf.h:304: warning: Function parameter or member 'cb_shared.active' not described in 'dma_buf' include/linux/firmware/intel/stratix10-svc-client.h:1: warning: no structured comments found include/linux/gpio/driver.h:371: warning: Function parameter or member 'init_valid_mask' not described in 'gpio_chip' include/linux/iio/hw-consumer.h:1: warning: no structured comments found include/linux/input/sparse-keymap.h:46: warning: Function parameter or member 'sw' not described in 'key_entry' include/linux/regulator/machine.h:199: warning: Function parameter or member 'max_uV_step' not described in 'regulation_constraints' include/linux/regulator/driver.h:228: warning: Function parameter or member 'resume' not described in 'regulator_ops' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw0' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw1' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw2' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.esw3' not described in 'irb' arch/s390/include/asm/cio.h:245: warning: Function parameter or member 'esw.eadm' not described in 'irb' drivers/slimbus/stream.c:1: warning: no structured comments found include/linux/spi/spi.h:180: warning: Function parameter or member 'driver_override' not described in 'spi_device' drivers/target/target_core_device.c:1: warning: no structured comments found drivers/usb/typec/bus.c:1: warning: no structured comments found drivers/usb/typec/class.c:1: warning: no structured comments found include/linux/w1.h:281: warning: Function parameter or member 'of_match_table' not described in 'w1_family' fs/direct-io.c:257: warning: Excess function parameter 'offset' description in 'dio_complete' fs/file_table.c:1: warning: no structured comments found fs/libfs.c:477: warning: Excess function parameter 'available' description in 'simple_write_end' fs/posix_acl.c:646: warning: Function parameter or member 'inode' not described in 'posix_acl_update_mode' fs/posix_acl.c:646: warning: Function parameter or member 'mode_p' not described in 'posix_acl_update_mode' fs/posix_acl.c:646: warning: Function parameter or member 'acl' not described in 'posix_acl_update_mode' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'mm' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'start' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:294: warning: Excess function parameter 'end' description in 'amdgpu_mn_invalidate_range_start_hsa' drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c:343: warning: Excess function parameter 'mm&#
[Intel-gfx] [v6 02/13] drm: Parse HDR metadata info from EDID
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 49 ++
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fa39592..fd8a621a 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2840,6 +2840,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK 0x04
+#define HDR_STATIC_METADATA_BLOCK 0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
#define EXT_VIDEO_DATA_BLOCK_420 0x0E
@@ -3587,6 +3588,12 @@ static int add_3d_struct_modes(struct drm_connector
*connector, u16 structure,
}
static int
+cea_db_payload_len_ext(const u8 *db)
+{
+ return (db[0] & 0x1f) - 1;
+}
+
+static int
cea_db_extended_tag(const u8 *db)
{
return db[1];
@@ -3822,6 +3829,46 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
+{
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != HDR_STATIC_METADATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static uint8_t eotf_supported(const u8 *edid_ext)
+{
+ return edid_ext[2] &
+ (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+BIT(HDMI_EOTF_SMPTE_ST2084));
+}
+
+static uint8_t hdr_metadata_type(const u8 *edid_ext)
+{
+ return edid_ext[3] &
+ BIT(HDMI_STATIC_METADATA_TYPE1);
+}
+
+static void
+drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
+{
+ u16 len;
+
+ len = cea_db_payload_len_ext(db);
+ connector->hdr_metadata.eotf = eotf_supported(db);
+ connector->hdr_metadata.metadata_type = hdr_metadata_type(db);
+
+ if (len >= 5)
+ connector->hdr_metadata.max_fall = db[5];
+ if (len >= 4)
+ connector->hdr_metadata.max_cll = db[4];
+}
+
static void
drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
@@ -4449,6 +4496,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_y420cmdb_bitmap(connector, db);
if (cea_db_is_vcdb(db))
drm_parse_vcdb(connector, db);
+ if (cea_db_is_hdmi_hdr_metadata_block(db))
+ drm_parse_hdr_metadata_block(connector, db);
}
}
--
1.9.1
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[Intel-gfx] [v6 00/13] Add HDR Metadata Parsing and handling in DRM layer
This patch series enables HDR support in drm. It basically defines HDR metadata structures, property to pass content (after blending) metadata from user space compositors to driver. Dynamic Range and Mastering infoframe creation and sending. ToDo: 1. We need to get the color framework in place for all planes which support HDR content in hardware. This is already in progres and patches are out for review in mailing list. 2. UserSpace/Compositors: Blending policies and metadata blob creation and passing to driver. Work is already in progress by Intel's middleware teams on wayland and we should be getting the initial version pretty soon for review. Please review and share your feedbacks/suggestions. Note: The intention for these patches is to get a design feedback on the uapi changes, generic property design and infoframe handling. This cannot get merged as of now without the userspace support in place. A POC has already been developed by Ville based on wayland. Please refer below link to see the component interactions and usage: https://lists.freedesktop.org/archives/wayland-devel/2017-December/036403.html v2: Updated Ville's POC changes to the patch series.Incorporated cleanups and fixes from Ville. Rebase on latest drm-tip. v3: Fixed a warning causing builds to break on CI. No major change. v4: Addressed Shashank's review comments. v5: Rebase on top of Ville's infoframe refactoring changes. Fixed non modeset case for HDR metadata update. Dropped a redundant patch. v6: Addressed Shashank's review comments and added RB's received. Note: Media driver and VAAPI changes for HDR are already out, with compositors changes also expected to land soon. Weston changes already floated and reviews started in community and is in active development along with GL efforts. Uma Shankar (10): drm: Add HDR source metadata property drm: Parse HDR metadata info from EDID drm: Parse Colorimetry data block from EDID drm/i915: Attach HDR metadata property to connector drm: Implement HDR output metadata set and get property handling drm: Enable HDR infoframe support drm/i915: Write HDR infoframe and send to panel drm/i915:Enabled Modeset when HDR Infoframe changes drm/i915: Set Infoframe for non modeset case for HDR video/hdmi: Add const variants for drm infoframe Ville Syrjälä (3): drm/i915: [DO NOT MERGE] hack for glk board outputs drm/i915: Add HLG EOTF drm/i915: Enable infoframes on GLK+ for HDR drivers/gpu/drm/drm_atomic.c| 2 + drivers/gpu/drm/drm_atomic_uapi.c | 13 +++ drivers/gpu/drm/drm_connector.c | 6 ++ drivers/gpu/drm/drm_edid.c | 131 + drivers/gpu/drm/i915/i915_reg.h | 4 + drivers/gpu/drm/i915/intel_atomic.c | 15 ++- drivers/gpu/drm/i915/intel_bios.c | 7 ++ drivers/gpu/drm/i915/intel_ddi.c| 13 +++ drivers/gpu/drm/i915/intel_drv.h| 1 + drivers/gpu/drm/i915/intel_hdmi.c | 59 ++- drivers/video/hdmi.c| 188 include/drm/drm_connector.h | 13 +++ include/drm/drm_edid.h | 4 + include/drm/drm_mode_config.h | 6 ++ include/linux/hdmi.h| 38 include/uapi/drm/drm_mode.h | 16 +++ 16 files changed, 513 insertions(+), 3 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v6 03/13] drm: Parse Colorimetry data block from EDID
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
v3: No Change
v4: Addressed Shashank's review comments. Updated
colorimetry field to 16 bit as DCI-P3 got added
in CEA 861-G spec, as pointed out by Shashank.
v5: Fixed checkpatch warnings with --strict option.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 25 +
include/drm/drm_connector.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fd8a621a..676569b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2840,6 +2840,7 @@ static int drm_cvt_modes(struct drm_connector *connector,
#define VIDEO_BLOCK 0x02
#define VENDOR_BLOCK0x03
#define SPEAKER_BLOCK 0x04
+#define COLORIMETRY_DATA_BLOCK 0x5
#define HDR_STATIC_METADATA_BLOCK 0x6
#define USE_EXTENDED_TAG 0x07
#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
@@ -3829,6 +3830,28 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
mode->clock = clock;
}
+static bool cea_db_is_hdmi_colorimetry_data_block(const u8 *db)
+{
+ if (cea_db_tag(db) != USE_EXTENDED_TAG)
+ return false;
+
+ if (db[1] != COLORIMETRY_DATA_BLOCK)
+ return false;
+
+ return true;
+}
+
+static void
+drm_parse_colorimetry_data_block(struct drm_connector *connector, const u8 *db)
+{
+ struct drm_hdmi_info *info = &connector->display_info.hdmi;
+ u16 len;
+
+ len = cea_db_payload_len_ext(db);
+ /* As per CEA 861-G spec */
+ info->colorimetry = ((db[3] & (0x1 << 7)) << 1) | db[2];
+}
+
static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
{
if (cea_db_tag(db) != USE_EXTENDED_TAG)
@@ -4498,6 +4521,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
drm_parse_vcdb(connector, db);
if (cea_db_is_hdmi_hdr_metadata_block(db))
drm_parse_hdr_metadata_block(connector, db);
+ if (cea_db_is_hdmi_colorimetry_data_block(db))
+ drm_parse_colorimetry_data_block(connector, db);
}
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 29388bd..94f926e 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -206,6 +206,9 @@ struct drm_hdmi_info {
/** @y420_dc_modes: bitmap of deep color support index */
u8 y420_dc_modes;
+
+ /* @colorimetry: bitmap of supported colorimetry modes */
+ u16 colorimetry;
};
/**
--
1.9.1
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[Intel-gfx] [v6 01/13] drm: Add HDR source metadata property
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
v3: No Change
v4: Addressed Shashank's review comments
v5: Rebase.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c | 6 ++
include/drm/drm_connector.h | 10 ++
include/drm/drm_mode_config.h | 6 ++
include/linux/hdmi.h| 10 ++
include/uapi/drm/drm_mode.h | 16
5 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 2355124..0bdae90 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1058,6 +1058,12 @@ int drm_connector_create_standard_properties(struct
drm_device *dev)
return -ENOMEM;
dev->mode_config.non_desktop_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "HDR_OUTPUT_METADATA", 0);
+ if (!prop)
+ return -ENOMEM;
+ dev->mode_config.hdr_output_metadata_property = prop;
+
return 0;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index c806199..29388bd 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -561,6 +561,13 @@ struct drm_connector_state {
* and the connector bpc limitations obtained from edid.
*/
u8 max_bpc;
+
+ /**
+* @metadata_blob_ptr:
+* DRM blob property for HDR output metadata
+*/
+ struct drm_property_blob *hdr_output_metadata_blob_ptr;
+ u8 hdr_metadata_changed : 1;
};
/**
@@ -1201,6 +1208,9 @@ struct drm_connector {
* &drm_mode_config.connector_free_work.
*/
struct llist_node free_node;
+
+ /* HDR metdata */
+ struct hdr_static_metadata hdr_metadata;
};
#define obj_to_connector(x) container_of(x, struct drm_connector, base)
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 7f60e8e..ef2656b 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -836,6 +836,12 @@ struct drm_mode_config {
*/
struct drm_property *writeback_out_fence_ptr_property;
+ /*
+* hdr_metadata_property: Connector property containing hdr metatda
+* This will be provided by userspace compositors based on HDR content
+*/
+ struct drm_property *hdr_output_metadata_property;
+
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 927ad64..a065194 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -152,6 +152,16 @@ enum hdmi_content_type {
HDMI_CONTENT_TYPE_GAME,
};
+enum hdmi_metadata_type {
+ HDMI_STATIC_METADATA_TYPE1 = 1,
+};
+
+enum hdmi_eotf {
+ HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
+ HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
+ HDMI_EOTF_SMPTE_ST2084,
+};
+
struct hdmi_avi_infoframe {
enum hdmi_infoframe_type type;
unsigned char version;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a439c2e..5012af2 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -630,6 +630,22 @@ struct drm_color_lut {
__u16 reserved;
};
+/* HDR Metadata */
+struct hdr_static_metadata {
+ uint8_t eotf;
+ uint8_t metadata_type;
+ struct {
+ uint16_t x, y;
+ } display_primaries[3];
+ struct {
+ uint16_t x, y;
+ } white_point;
+ uint16_t max_mastering_display_luminance;
+ uint16_t min_mastering_display_luminance;
+ uint16_t max_fall;
+ uint16_t max_cll;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
1.9.1
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[Intel-gfx] [v6 04/13] drm/i915: Attach HDR metadata property to connector
Attach HDR metadata property to connector object. v2: Rebase v3: Updated the property name as per updated name while creating hdr metadata property Signed-off-by: Uma Shankar Reviewed-by: Shashank Sharma --- drivers/gpu/drm/i915/intel_hdmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 5ccb305..5f06237 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -2719,6 +2719,8 @@ static void intel_hdmi_destroy(struct drm_connector *connector) drm_connector_attach_content_type_property(connector); connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, 0); if (!HAS_GMCH(dev_priv)) drm_connector_attach_max_bpc_property(connector, 8, 12); -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v6 12/13] drm/i915: Set Infoframe for non modeset case for HDR
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 69aa0d1..a27aab9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3566,6 +3566,10 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *intel_dig_port =
+ enc_to_dig_port(&encoder->base);
+
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
@@ -3575,6 +3579,15 @@ static void intel_ddi_update_pipe(struct intel_encoder
*encoder,
else if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
intel_hdcp_disable(to_intel_connector(conn_state->connector));
+
+ /* Set the infoframe for NON modeset cases as well */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ conn_state->hdr_metadata_changed)
+ intel_dig_port->set_infoframes(encoder,
+
crtc_state->has_infoframe,
+ crtc_state, conn_state);
+ }
}
static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
--
1.9.1
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[Intel-gfx] [v6 05/13] drm: Implement HDR output metadata set and get property handling
This patch implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is returned as blob in get
property call to userspace.
v2: Rebase and added Ville's POC changes
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_atomic.c | 2 ++
drivers/gpu/drm/drm_atomic_uapi.c | 13 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..8b9c126 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -881,6 +881,8 @@ static void drm_atomic_connector_print_state(struct
drm_printer *p,
drm_printf(p, "connector[%u]: %s\n", connector->base.id,
connector->name);
drm_printf(p, "\tcrtc=%s\n", state->crtc ? state->crtc->name :
"(null)");
+ drm_printf(p, "\thdr_metadata_changed=%d\n",
+ state->hdr_metadata_changed);
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
if (state->writeback_job && state->writeback_job->fb)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 4eb81f1..18c8b81f 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -686,6 +686,8 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
{
struct drm_device *dev = connector->dev;
struct drm_mode_config *config = &dev->mode_config;
+ bool replaced = false;
+ int ret;
if (property == config->prop_crtc_id) {
struct drm_crtc *crtc = drm_crtc_find(dev, NULL, val);
@@ -734,6 +736,14 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*/
if (state->link_status != DRM_LINK_STATUS_GOOD)
state->link_status = val;
+ } else if (property == config->hdr_output_metadata_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->hdr_output_metadata_blob_ptr,
+ val,
+ -1, sizeof(struct hdr_static_metadata),
+ &replaced);
+ state->hdr_metadata_changed |= replaced;
+ return ret;
} else if (property == config->aspect_ratio_property) {
state->picture_aspect_ratio = val;
} else if (property == config->content_type_property) {
@@ -820,6 +830,9 @@ static int drm_atomic_connector_set_property(struct
drm_connector *connector,
*val = state->colorspace;
} else if (property == connector->scaling_mode_property) {
*val = state->scaling_mode;
+ } else if (property == config->hdr_output_metadata_property) {
+ *val = (state->hdr_output_metadata_blob_ptr) ?
+ state->hdr_output_metadata_blob_ptr->base.id : 0;
} else if (property == connector->content_protection_property) {
*val = state->content_protection;
} else if (property == config->writeback_fb_id_property) {
--
1.9.1
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[Intel-gfx] [v6 07/13] drm/i915: Write HDR infoframe and send to panel
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation in compute config.
v6: Addressed Shashank's review comment. Added HDR metadata
support from GEN10 onwards as per Shashank's recommendation.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_hdmi.c | 41 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9f188e..c6c3cc7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1043,6 +1043,7 @@ struct intel_crtc_state {
union hdmi_infoframe avi;
union hdmi_infoframe spd;
union hdmi_infoframe hdmi;
+ union hdmi_infoframe drm;
} infoframes;
/* HDMI scrambling status */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 5f06237..e4bc7fc 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -555,6 +555,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
HDMI_INFOFRAME_TYPE_AVI,
HDMI_INFOFRAME_TYPE_SPD,
HDMI_INFOFRAME_TYPE_VENDOR,
+ HDMI_INFOFRAME_TYPE_DRM,
};
u32 intel_hdmi_infoframe_enable(unsigned int type)
@@ -777,6 +778,30 @@ void intel_read_infoframe(struct intel_encoder *encoder,
return true;
}
+static bool
+intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
+struct intel_crtc_state *crtc_state,
+struct drm_connector_state *conn_state)
+{
+ struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
+ struct hdr_static_metadata *hdr_metadata;
+ int ret;
+
+ hdr_metadata = (struct hdr_static_metadata *)
+ conn_state->hdr_output_metadata_blob_ptr->data;
+
+ ret = drm_hdmi_infoframe_set_hdr_metadata(frame, hdr_metadata);
+ if (ret < 0) {
+ DRM_ERROR("couldn't set HDR metadata in infoframe\n");
+ return false;
+ }
+
+ crtc_state->infoframes.enable |=
+ intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
+
+ return true;
+}
+
static void g4x_set_infoframes(struct intel_encoder *encoder,
bool enable,
const struct intel_crtc_state *crtc_state,
@@ -1175,6 +1200,9 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_write_infoframe(encoder, crtc_state,
HDMI_INFOFRAME_TYPE_VENDOR,
&crtc_state->infoframes.hdmi);
+ intel_write_infoframe(encoder, crtc_state,
+ HDMI_INFOFRAME_TYPE_DRM,
+ &crtc_state->infoframes.drm);
}
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
@@ -2381,6 +2409,19 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
return -EINVAL;
}
+ /*
+* Support HDR Metadata from Gen10 onwards
+* ToDo: Gen9 also can support HDR with LSPCON.
+* Support for the same to be enabled later.
+*/
+ if (INTEL_GEN(dev_priv) >= 10) {
+ if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config,
+ conn_state)) {
+ DRM_DEBUG_KMS("bad DRM infoframe\n");
+ return -EINVAL;
+ }
+ }
+
return 0;
}
--
1.9.1
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[Intel-gfx] [v6 09/13] drm/i915: Add HLG EOTF
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a logarithmic curve.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 3 ++-
include/linux/hdmi.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 78c0b97..4784447 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3868,7 +3868,8 @@ static uint8_t eotf_supported(const u8 *edid_ext)
return edid_ext[2] &
(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
-BIT(HDMI_EOTF_SMPTE_ST2084));
+BIT(HDMI_EOTF_SMPTE_ST2084) |
+BIT(HDMI_EOTF_BT_2100_HLG));
}
static uint8_t hdr_metadata_type(const u8 *edid_ext)
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index b925b24..202ed4a 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -161,6 +161,7 @@ enum hdmi_eotf {
HDMI_EOTF_TRADITIONAL_GAMMA_SDR,
HDMI_EOTF_TRADITIONAL_GAMMA_HDR,
HDMI_EOTF_SMPTE_ST2084,
+ HDMI_EOTF_BT_2100_HLG,
};
struct hdmi_avi_infoframe {
--
1.9.1
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[Intel-gfx] [v6 08/13] drm/i915: [DO NOT MERGE] hack for glk board outputs
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 64f2017..4934b5f 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1405,6 +1405,13 @@ static void parse_ddi_port(struct drm_i915_private
*dev_priv, enum port port,
is_hdmi = false;
}
+ if (IS_GEMINILAKE(dev_priv) && port == PORT_C) {
+ is_hdmi = true;
+ is_dvi = true;
+ is_dp = false;
+ is_edp = false;
+ }
+
info->supports_dvi = is_dvi;
info->supports_hdmi = is_hdmi;
info->supports_dp = is_dp;
--
1.9.1
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[Intel-gfx] [v6 13/13] video/hdmi: Add const variants for drm infoframe
Added the const version of infoframe for DRM metadata
for HDR.
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 63 ++--
include/linux/hdmi.h | 5 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 80bb0ee..f9ca555 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -668,6 +668,30 @@ int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe
*frame)
}
EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+static int hdmi_drm_infoframe_check_only(const struct hdmi_drm_infoframe
*frame)
+{
+ if (frame->type != HDMI_INFOFRAME_TYPE_DRM ||
+ frame->version != 1)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * hdmi_drm_infoframe_check() - check a HDMI DRM infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Validates that the infoframe is consistent and updates derived fields
+ * (eg. length) based on other fields.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame)
+{
+ return hdmi_drm_infoframe_check_only(frame);
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_check);
+
/**
* hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
* @frame: HDMI DRM infoframe
@@ -682,8 +706,8 @@ int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe
*frame)
* Returns the number of bytes packed into the binary buffer or a negative
* error code on failure.
*/
-ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
- size_t size)
+ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
+void *buffer, size_t size)
{
u8 *ptr = buffer;
size_t length;
@@ -736,6 +760,37 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
return length;
}
+EXPORT_SYMBOL(hdmi_drm_infoframe_pack_only);
+
+/**
+ * hdmi_drm_infoframe_pack() - check a HDMI DRM infoframe,
+ * and write it to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Validates that the infoframe is consistent and updates derived fields
+ * (eg. length) based on other fields, after which it packs the information
+ * contained in the @frame structure into a binary representation that
+ * can be written into the corresponding controller registers. This function
+ * also computes the checksum as required by section 5.3.5 of the HDMI 1.4
+ * specification.
+ *
+ * Returns the number of bytes packed into the binary buffer or a negative
+ * error code on failure.
+ */
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame,
+ void *buffer, size_t size)
+{
+ int ret;
+
+ ret = hdmi_drm_infoframe_check(frame);
+ if (ret)
+ return ret;
+
+ return hdmi_drm_infoframe_pack_only(frame, buffer, size);
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_pack);
/*
* hdmi_vendor_any_infoframe_check() - check a vendor infoframe
@@ -845,6 +900,10 @@ ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe
*frame, void *buffer,
length = hdmi_avi_infoframe_pack_only(&frame->avi,
buffer, size);
break;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ length = hdmi_drm_infoframe_pack_only(&frame->drm,
+ buffer, size);
+ break;
case HDMI_INFOFRAME_TYPE_SPD:
length = hdmi_spd_infoframe_pack_only(&frame->spd,
buffer, size);
diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h
index 202ed4a..fd8e534 100644
--- a/include/linux/hdmi.h
+++ b/include/linux/hdmi.h
@@ -213,6 +213,11 @@ ssize_t hdmi_avi_infoframe_pack_only(const struct
hdmi_avi_infoframe *frame,
void *buffer, size_t size);
int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame);
int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame);
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
+ size_t size);
+ssize_t hdmi_drm_infoframe_pack_only(const struct hdmi_drm_infoframe *frame,
+void *buffer, size_t size);
+int hdmi_drm_infoframe_check(struct hdmi_drm_infoframe *frame);
enum hdmi_spd_sdi {
HDMI_SPD_SDI_UNKNOWN,
--
1.9.1
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[Intel-gfx] [v6 06/13] drm: Enable HDR infoframe support
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: Rebase and added Ville's POC changes.
v3: No Change
v4: Addressed Shashank's review comments and merged the
patch making drm infoframe function arguments as constant.
v5: Rebase
v6: Fixed checkpatch warnings with --strict option. Addressed
Shashank's review comments and added his RB.
Signed-off-by: Uma Shankar
Signed-off-by: Ville Syrjälä
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/drm_edid.c | 56
drivers/video/hdmi.c | 129 +
include/drm/drm_edid.h | 4 ++
include/linux/hdmi.h | 22
4 files changed, 211 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 676569b..78c0b97 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4916,6 +4916,62 @@ static bool is_hdmi2_sink(struct drm_connector
*connector)
}
/**
+ * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
+ * HDR metadata from userspace
+ * @frame: HDMI AVI infoframe
+ * @hdr_source_metadata: hdr_source_metadata info from userspace
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int
+drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
+ void *hdr_metadata)
+{
+ struct hdr_static_metadata *hdr_source_metadata;
+ int err, i;
+
+ if (!frame || !hdr_metadata)
+ return true;
+
+ err = hdmi_drm_infoframe_init(frame);
+ if (err < 0)
+ return err;
+
+ DRM_DEBUG_KMS("type = %x\n", frame->type);
+
+ hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
+
+ frame->length = sizeof(struct hdr_static_metadata);
+
+ frame->eotf = hdr_source_metadata->eotf;
+ frame->metadata_type = hdr_source_metadata->metadata_type;
+
+ for (i = 0; i < 3; i++) {
+ frame->display_primaries[i].x =
+ hdr_source_metadata->display_primaries[i].x;
+ frame->display_primaries[i].y =
+ hdr_source_metadata->display_primaries[i].y;
+ }
+
+ frame->white_point.x = hdr_source_metadata->white_point.x;
+ frame->white_point.y = hdr_source_metadata->white_point.y;
+
+ frame->max_mastering_display_luminance =
+ hdr_source_metadata->max_mastering_display_luminance;
+ frame->min_mastering_display_luminance =
+ hdr_source_metadata->min_mastering_display_luminance;
+
+ frame->max_cll = hdr_source_metadata->max_cll;
+ frame->max_fall = hdr_source_metadata->max_fall;
+
+ hdmi_infoframe_log(KERN_CRIT, NULL,
+ (union hdmi_infoframe *)frame);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
+
+/**
* drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
* data from a DRM display mode
* @frame: HDMI AVI infoframe
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
index 799ae49..80bb0ee 100644
--- a/drivers/video/hdmi.c
+++ b/drivers/video/hdmi.c
@@ -650,6 +650,93 @@ ssize_t hdmi_vendor_infoframe_pack(struct
hdmi_vendor_infoframe *frame,
return 0;
}
+/**
+ * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and
+ * mastering infoframe
+ * @frame: HDMI DRM infoframe
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame)
+{
+ memset(frame, 0, sizeof(*frame));
+
+ frame->type = HDMI_INFOFRAME_TYPE_DRM;
+ frame->version = 1;
+
+ return 0;
+}
+EXPORT_SYMBOL(hdmi_drm_infoframe_init);
+
+/**
+ * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer
+ * @frame: HDMI DRM infoframe
+ * @buffer: destination buffer
+ * @size: size of buffer
+ *
+ * Packs the information contained in the @frame structure into a binary
+ * representation that can be written into the corresponding controller
+ * registers. Also computes the checksum as required by section 5.3.5 of
+ * the HDMI 1.4 specification.
+ *
+ * Returns the number of bytes packed into the binary buffer or a negative
+ * error code on failure.
+ */
+ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer,
+ size_t size)
+{
+ u8 *ptr = buffer;
+ size_t length;
+ int i;
+
+ length = HDMI_INFOFRAME_HEADER_SIZE + frame->length;
+
+ if (size < length)
+ return -ENOSPC;
+
+ memset(buffer, 0, size);
+
+ ptr[0] = frame->type;
+ ptr[1] = frame->vers
[Intel-gfx] [v6 10/13] drm/i915: Enable infoframes on GLK+ for HDR
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 18 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31a3020..fe931e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4718,6 +4718,7 @@ enum {
#define VIDEO_DIP_FREQ_MASK (3 << 16)
/* HSW and later: */
#define DRM_DIP_ENABLE (1 << 28)
+#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
#define PSR_VSC_BIT_7_SET(1 << 27)
#define VSC_SELECT_MASK (0x3 << 25)
#define VSC_SELECT_SHIFT 25
@@ -8156,6 +8157,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
#define _HSW_VIDEO_DIP_VS_ECC_A0x60280
#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
@@ -8169,6 +8171,7 @@ enum {
#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
#define _HSW_VIDEO_DIP_VS_ECC_B0x61280
#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
@@ -8194,6 +8197,7 @@ enum {
#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans,
_HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans,
_GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
#define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(trans,
_ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index e4bc7fc..8decafd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -134,6 +134,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return VIDEO_DIP_ENABLE_SPD_HSW;
case HDMI_INFOFRAME_TYPE_VENDOR:
return VIDEO_DIP_ENABLE_VS_HSW;
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return VIDEO_DIP_ENABLE_DRM_GLK;
default:
MISSING_CASE(type);
return 0;
@@ -159,6 +161,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
case HDMI_INFOFRAME_TYPE_VENDOR:
return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+ case HDMI_INFOFRAME_TYPE_DRM:
+ return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
default:
MISSING_CASE(type);
return INVALID_MMIO_REG;
@@ -545,7 +549,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder
*encoder,
return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+ VIDEO_DIP_ENABLE_DRM_GLK);
}
static const u8 infoframe_type_to_idx[] = {
@@ -1177,7 +1182,8 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+VIDEO_DIP_ENABLE_DRM_GLK);
if (!enable) {
I915_WRITE(reg, val);
@@ -1200,9 +1206,11 @@ static void hsw_set_infoframes(struct intel_encoder
*encoder,
intel_write_infoframe(encoder, crtc_state,
HDMI_INFOFRAME_TYPE_VENDOR,
&crtc_state->infoframes.hdmi);
- intel_write_infoframe(encoder, crtc_state,
- HDMI_INFOFRAME_TYPE_DRM,
- &crtc_state->infoframes.drm);
+ if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
+ conn_state->hdr_metadata_changed)
+ intel_write_infoframe(encoder, crtc_state,
+ HDMI_INFOFRAME_TYPE_DRM,
+ &cr
[Intel-gfx] [v6 11/13] drm/i915:Enabled Modeset when HDR Infoframe changes
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c
b/drivers/gpu/drm/i915/intel_atomic.c
index b844e88..4ff6042 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -102,6 +102,16 @@ int intel_digital_connector_atomic_set_property(struct
drm_connector *connector,
return -EINVAL;
}
+static bool blob_equal(const struct drm_property_blob *a,
+ const struct drm_property_blob *b)
+{
+ if (a && b)
+ return a->length == b->length &&
+ !memcmp(a->data, b->data, a->length);
+
+ return !a == !b;
+}
+
int intel_digital_connector_atomic_check(struct drm_connector *conn,
struct drm_connector_state *new_state)
{
@@ -129,7 +139,10 @@ int intel_digital_connector_atomic_check(struct
drm_connector *conn,
new_conn_state->base.colorspace != old_conn_state->base.colorspace
||
new_conn_state->base.picture_aspect_ratio !=
old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type !=
old_conn_state->base.content_type ||
- new_conn_state->base.scaling_mode !=
old_conn_state->base.scaling_mode)
+ new_conn_state->base.scaling_mode !=
+ old_conn_state->base.scaling_mode ||
+ !blob_equal(new_conn_state->base.hdr_output_metadata_blob_ptr,
+ old_conn_state->base.hdr_output_metadata_blob_ptr))
crtc_state->mode_changed = true;
return 0;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8decafd..4d06734 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -792,6 +792,10 @@ void intel_read_infoframe(struct intel_encoder *encoder,
struct hdr_static_metadata *hdr_metadata;
int ret;
+ if (!conn_state->hdr_output_metadata_blob_ptr ||
+ conn_state->hdr_output_metadata_blob_ptr->length == 0)
+ return true;
+
hdr_metadata = (struct hdr_static_metadata *)
conn_state->hdr_output_metadata_blob_ptr->data;
--
1.9.1
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Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
Op 19-03-2019 om 17:18 schreef Ville Syrjälä:
> On Tue, Mar 19, 2019 at 05:06:36PM +0100, Maarten Lankhorst wrote:
>> Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
>>> On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
There has unfortunately been a conflict with the following 3 commits:
commit e9961ab95af81b8d29054361cd5f0c575102cf87
Author: Ayan Kumar Halder
Date: Fri Nov 9 17:21:12 2018 +
drm: Added a new format DRM_FORMAT_XVYU2101010
commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
Author: Brian Starkey
Date: Fri Oct 5 10:27:00 2018 +0100
drm/fourcc: Add AFBC yuv fourccs for Mali
and
commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
Author: Swati Sharma
Date: Mon Mar 4 17:26:33 2019 +0530
drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
Unfortunately gcc didn't warn about the redefinitions, because the
Fix this by using new XYVU for i915, without alpha, and making the
Y41x definitions match msdn, with alpha.
>>> The naming of all these is rather unfortunate because now the alpha vs.
>>> non-alpha formats have totally different looking names :( Fourccs are
>>> stupid!
>>>
Fortunately we caught it early, and the conflict hasn't even landed in
drm-next yet.
Signed-off-by: Maarten Lankhorst
Cc: Brian Starkey
Cc: Swati Sharma
Cc: Ayan Kumar Halder
Cc: mal...@foss.arm.com
Cc: Daniel Vetter
Cc: Maxime Ripard
Cc: Sean Paul
Cc: Dave Airlie
Cc: Liviu Dudau
---
drivers/gpu/drm/drm_fourcc.c | 12 +--
drivers/gpu/drm/i915/intel_display.c | 18 -
drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
include/uapi/drm/drm_fourcc.h| 21 +--
4 files changed, 41 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index b914b16db9b2..6ea55fb4526d 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
- { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_VUY888, .depth = 0,
.num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
- { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
true, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
true, .is_yuv = true },
- { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
{ .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
},
- { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
- { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
- { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
},
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
true, .is_yuv = true },
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
true, .is_yuv = true },
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub
[Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
Re-enable clock gating of DDI clocks.
Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f02504d..716be38 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
*encoder)
DRM_ERROR("DDI port:%c buffer not idle\n",
port_name(port));
}
- gen11_dsi_ungate_clocks(encoder);
+ gen11_dsi_gate_clocks(encoder);
}
static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
--
1.9.1
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[Intel-gfx] [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at the later point in
the enable sequence.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index beb30d9..f02504d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
*encoder,
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ /* make sure that the ddi clocks are not gated */
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ }
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
POSTING_READ(DPCLKA_CFGCR0_ICL);
mutex_unlock(&dev_priv->dpll_lock);
--
1.9.1
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Re: [Intel-gfx] [PATCH 05/18] drm/i915: Introduce a mutex for file_priv->context_idr
On 19/03/2019 11:57, Chris Wilson wrote:
Define a mutex for the exclusive use of interacting with the per-file
context-idr, that was previously guarded by struct_mutex. This allows us
to reduce the coverage of struct_mutex, with a view to removing the last
bits coordinating GEM context later. (In the short term, we avoid taking
struct_mutex while using the extended constructor functions, preventing
some nasty recursion.)
v2: s/context_lock/context_idr_lock/
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 47 +++--
2 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 86080a6e0f45..219348121897 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -216,7 +216,9 @@ struct drm_i915_file_private {
*/
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
} mm;
+
struct idr context_idr;
+ struct mutex context_idr_lock; /* guards context_idr */
unsigned int bsd_engine;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index dff4220df911..799684d05704 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -579,9 +579,7 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
static int context_idr_cleanup(int id, void *p, void *data)
{
- struct i915_gem_context *ctx = p;
-
- context_close(ctx);
+ context_close(p);
return 0;
}
@@ -603,13 +601,15 @@ static int gem_context_register(struct i915_gem_context *ctx,
}
/* And finally expose ourselves to userspace via the idr */
+ mutex_lock(&fpriv->context_idr_lock);
ret = idr_alloc(&fpriv->context_idr, ctx,
DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
+ if (ret >= 0)
+ ctx->user_handle = ret;
+ mutex_unlock(&fpriv->context_idr_lock);
if (ret < 0)
goto err_name;
- ctx->user_handle = ret;
-
return 0;
err_name:
@@ -627,10 +627,11 @@ int i915_gem_context_open(struct drm_i915_private *i915,
int err;
idr_init(&file_priv->context_idr);
+ mutex_init(&file_priv->context_idr_lock);
mutex_lock(&i915->drm.struct_mutex);
-
ctx = i915_gem_create_context(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
if (IS_ERR(ctx)) {
err = PTR_ERR(ctx);
goto err;
@@ -643,14 +644,14 @@ int i915_gem_context_open(struct drm_i915_private *i915,
GEM_BUG_ON(ctx->user_handle != DEFAULT_CONTEXT_HANDLE);
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
- mutex_unlock(&i915->drm.struct_mutex);
-
return 0;
err_ctx:
+ mutex_lock(&i915->drm.struct_mutex);
context_close(ctx);
-err:
mutex_unlock(&i915->drm.struct_mutex);
+err:
+ mutex_destroy(&file_priv->context_idr_lock);
idr_destroy(&file_priv->context_idr);
return PTR_ERR(ctx);
}
@@ -663,6 +664,7 @@ void i915_gem_context_close(struct drm_file *file)
idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
idr_destroy(&file_priv->context_idr);
+ mutex_destroy(&file_priv->context_idr_lock);
}
static struct i915_request *
@@ -845,25 +847,22 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
return ret;
ctx = i915_gem_create_context(i915);
- if (IS_ERR(ctx)) {
- ret = PTR_ERR(ctx);
- goto err_unlock;
- }
+ mutex_unlock(&dev->struct_mutex);
+ if (IS_ERR(ctx))
+ return PTR_ERR(ctx);
ret = gem_context_register(ctx, file_priv);
if (ret)
goto err_ctx;
- mutex_unlock(&dev->struct_mutex);
-
args->ctx_id = ctx->user_handle;
DRM_DEBUG("HW context %d created\n", args->ctx_id);
return 0;
err_ctx:
+ mutex_lock(&dev->struct_mutex);
context_close(ctx);
-err_unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
}
@@ -874,7 +873,6 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
struct drm_i915_gem_context_destroy *args = data;
struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_gem_context *ctx;
- int ret;
if (args->pad != 0)
return -EINVAL;
@@ -882,21 +880,18 @@ int i915_gem_context_destroy_ioctl(struct drm_device
*dev, void *data,
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
return -ENOENT;
- ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
+ if (mutex_lock_interruptible(&file_priv->context_idr_lock))
+ return -EINTR;
+
+ ctx = idr_remove(&file_priv->context_idr, args->ctx_id);
+ mutex_unlock(&file_
Re: [Intel-gfx] [PATCH v2] drm/i915: Stop storing ctx->user_handle
On 19/03/2019 12:58, Chris Wilson wrote:
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 23 ---
drivers/gpu/drm/i915/i915_gem_context.h | 5
drivers/gpu/drm/i915/i915_gem_context_types.h | 9
drivers/gpu/drm/i915/i915_gpu_error.c | 11 -
drivers/gpu/drm/i915/i915_gpu_error.h | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
7 files changed, 16 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f4a07190a0e8..7970770f23a9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -409,9 +409,8 @@ static void print_context_stats(struct seq_file *m,
rcu_read_lock();
task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
- snprintf(name, sizeof(name), "%s/%d",
-task ? task->comm : "",
-ctx->user_handle);
+ snprintf(name, sizeof(name), "%s",
+task ? task->comm : "");
rcu_read_unlock();
print_file_stats(m, name, stats);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 799684d05704..95c5103e15a5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -602,20 +602,15 @@ static int gem_context_register(struct i915_gem_context
*ctx,
/* And finally expose ourselves to userspace via the idr */
mutex_lock(&fpriv->context_idr_lock);
- ret = idr_alloc(&fpriv->context_idr, ctx,
- DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
- if (ret >= 0)
- ctx->user_handle = ret;
+ ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL);
mutex_unlock(&fpriv->context_idr_lock);
- if (ret < 0)
- goto err_name;
-
- return 0;
+ if (ret >= 0)
+ goto out;
-err_name:
kfree(fetch_and_zero(&ctx->name));
err_pid:
put_pid(fetch_and_zero(&ctx->pid));
+out:
return ret;
}
@@ -638,11 +633,11 @@ int i915_gem_context_open(struct drm_i915_private *i915,
}
err = gem_context_register(ctx, file_priv);
- if (err)
+ if (err < 0)
goto err_ctx;
- GEM_BUG_ON(ctx->user_handle != DEFAULT_CONTEXT_HANDLE);
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
+ GEM_BUG_ON(err > 0);
return 0;
@@ -852,10 +847,10 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
return PTR_ERR(ctx);
ret = gem_context_register(ctx, file_priv);
- if (ret)
+ if (ret < 0)
goto err_ctx;
- args->ctx_id = ctx->user_handle;
+ args->ctx_id = ret;
DRM_DEBUG("HW context %d created\n", args->ctx_id);
return 0;
@@ -877,7 +872,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
if (args->pad != 0)
return -EINVAL;
- if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
+ if (!args->ctx_id)
return -ENOENT;
if (mutex_lock_interruptible(&file_priv->context_idr_lock))
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 8a1377691d6d..849b2a83c1ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -126,11 +126,6 @@ static inline void i915_gem_context_unpin_hw_id(struct
i915_gem_context *ctx)
atomic_dec(&ctx->hw_id_pin_count);
}
-static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
-{
- return c->user_handle == DEFAULT_CONTEXT_HANDLE;
-}
-
static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
{
return !ctx->file_priv;
diff --git a/drivers/gpu/drm/i915/i915_gem_context_types.h
b/drivers/gpu/drm/i915/i915_gem_context_types.h
index 2bf19730eaa9..63ae8eb21939 100644
--- a/drivers/gpu/drm/i915/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/i915_gem_context_types.h
@@ -129,15 +129,6 @@ struct i915_gem_context {
struct list_head active_engines;
struct mutex mutex;
- /**
-* @user_handle: userspace identifier
-*
-* A unique per-file identifier is generated from
-* &drm_i915_file_private.contexts.
-*/
- u32 user_handle;
-#define DEFAULT_CONTEXT_HANDLE 0
-
struct i915_sched_attr sched;
/** hw_contexts: per-engine logical HW state */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index e8674347f589..b101f037b61f 100644
---
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2] drm/i915/selftests: add test to verify get/put fw domains (rev5)
== Series Details ==
Series: series starting with [v2] drm/i915/selftests: add test to verify
get/put fw domains (rev5)
URL : https://patchwork.freedesktop.org/series/58202/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b3b753c99d3 drm/i915/selftests: add test to verify get/put fw domains
-:39: ERROR:TRAILING_WHITESPACE: trailing whitespace
#39: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:129:
+^I^I{ $
-:80: WARNING:MEMORY_BARRIER: memory barrier without comment
#80: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:170:
+ smp_store_mb(domain->active, false);
-:117: WARNING:MEMORY_BARRIER: memory barrier without comment
#117: FILE: drivers/gpu/drm/i915/selftests/intel_uncore.c:207:
+ smp_store_mb(domain->active, false);
total: 1 errors, 2 warnings, 0 checks, 152 lines checked
a53482214287 drm/i915/selftests: Calculate maximum ring size for preemption
chain
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> Re-enable clock gating of DDI clocks.
>
> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index f02504d..716be38 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
> *encoder)
> DRM_ERROR("DDI port:%c buffer not idle\n",
> port_name(port));
> }
> - gen11_dsi_ungate_clocks(encoder);
> + gen11_dsi_gate_clocks(encoder);
This also requires updating icl_sanitize_encoder_pll_mapping().
Currently it assumes that the DDI clock needs to be ungated if the
corresponding DSI port is disabled and gated if the port is enabled.
The changes in this patchset mean that the DDI clock should be gated for
DSI ports regardless of whether the port is enabled or not.
> }
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> --
> 1.9.1
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2] drm/i915/selftests: add test to verify get/put fw domains (rev5)
== Series Details ==
Series: series starting with [v2] drm/i915/selftests: add test to verify
get/put fw domains (rev5)
URL : https://patchwork.freedesktop.org/series/58202/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5778 -> Patchwork_12525
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12525 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12525, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58202/revisions/5/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12525:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-skl-6600u: PASS -> FAIL
Known issues
Here are the changes found in Patchwork_12525 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
Participating hosts (49 -> 42)
--
Additional (1): fi-icl-y
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5778 -> Patchwork_12525
CI_DRM_5778: 110de1a2cf715beda24f357eda8afd6404d63dda @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12525: a5348221428704a582978dbaae2468e31d29d7ae @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a53482214287 drm/i915/selftests: Calculate maximum ring size for preemption
chain
7b3b753c99d3 drm/i915/selftests: add test to verify get/put fw domains
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12525/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 00/10] Compartmentalize uncore code
Quoting Chris Wilson (2019-03-19 18:59:04) > Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:33) > > Compared to v1 [1], there is a new patch for further simplification of > > low-level fw get/put by always using the bitmasks since the upper bits > > of the fw reg are reserved on gen6 and I couldn't find any reason > > writing them wouldn't work in the git history. > > I put together a small selftest to trybot this on snb [2], if people > > think it is worth adding it to the tree I can clean it up and send it > > for review. > > > > Apart from the above, addresses the review comments, the only > > non-trivial one being moving the mmio setup under uncore. > > > > [1] https://patchwork.freedesktop.org/series/57962/ > > [2] https://patchwork.freedesktop.org/patch/292852/?series=58159&rev=1 > > I thought so. You just need to verify that the fw count is zero at the > start of the loop and then flush the hrtimer instead of the imprecise > usleep(). After beating around the bush to find the right mix of registers that give us the inspection we need, I've pushed your selftest. Hopefully that holds up to soak testing and provides a nice early warning canary. Thanks, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Engine relative MMIO
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/John-C-Harrison-Intel-com/drm-i915-Engine-relative-MMIO/20190320-141647
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s0-201911 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/intel_workarounds.c:1260:0:
drivers/gpu/drm/i915/selftests/intel_workarounds.c: In function
'check_dirty_whitelist':
>> drivers/gpu/drm/i915/selftests/intel_workarounds.c:520:12: error: implicit
>> declaration of function 'MI_LOAD_REGISTER_IMM'
>> [-Werror=implicit-function-declaration]
*cs++ = MI_LOAD_REGISTER_IMM(1);
^~~~
cc1: some warnings being treated as errors
vim +/MI_LOAD_REGISTER_IMM +520
drivers/gpu/drm/i915/selftests/intel_workarounds.c
34ae8455 Chris Wilson 2019-03-01 441
34ae8455 Chris Wilson 2019-03-01 442 static int check_dirty_whitelist(struct
i915_gem_context *ctx,
34ae8455 Chris Wilson 2019-03-01 443struct
intel_engine_cs *engine)
34ae8455 Chris Wilson 2019-03-01 444 {
34ae8455 Chris Wilson 2019-03-01 445 const u32 values[] = {
34ae8455 Chris Wilson 2019-03-01 446 0x,
34ae8455 Chris Wilson 2019-03-01 447 0x01010101,
34ae8455 Chris Wilson 2019-03-01 448 0x10100101,
34ae8455 Chris Wilson 2019-03-01 449 0x03030303,
34ae8455 Chris Wilson 2019-03-01 450 0x30300303,
34ae8455 Chris Wilson 2019-03-01 451 0x05050505,
34ae8455 Chris Wilson 2019-03-01 452 0x50500505,
34ae8455 Chris Wilson 2019-03-01 453 0x0f0f0f0f,
34ae8455 Chris Wilson 2019-03-01 454 0xf00ff00f,
34ae8455 Chris Wilson 2019-03-01 455 0x10101010,
34ae8455 Chris Wilson 2019-03-01 456 0xf0f01010,
34ae8455 Chris Wilson 2019-03-01 457 0x30303030,
34ae8455 Chris Wilson 2019-03-01 458 0xa0a03030,
34ae8455 Chris Wilson 2019-03-01 459 0x50505050,
34ae8455 Chris Wilson 2019-03-01 460 0xc0c05050,
34ae8455 Chris Wilson 2019-03-01 461 0xf0f0f0f0,
34ae8455 Chris Wilson 2019-03-01 462 0x,
34ae8455 Chris Wilson 2019-03-01 463 0x,
34ae8455 Chris Wilson 2019-03-01 464 0x,
34ae8455 Chris Wilson 2019-03-01 465 0x,
34ae8455 Chris Wilson 2019-03-01 466 0x00ff00ff,
34ae8455 Chris Wilson 2019-03-01 467 0xffff,
34ae8455 Chris Wilson 2019-03-01 468 0x00ff,
34ae8455 Chris Wilson 2019-03-01 469 0x,
34ae8455 Chris Wilson 2019-03-01 470 };
34ae8455 Chris Wilson 2019-03-01 471 struct i915_vma *scratch;
34ae8455 Chris Wilson 2019-03-01 472 struct i915_vma *batch;
34ae8455 Chris Wilson 2019-03-01 473 int err = 0, i, v;
34ae8455 Chris Wilson 2019-03-01 474 u32 *cs, *results;
34ae8455 Chris Wilson 2019-03-01 475
34ae8455 Chris Wilson 2019-03-01 476 scratch = create_scratch(ctx);
34ae8455 Chris Wilson 2019-03-01 477 if (IS_ERR(scratch))
34ae8455 Chris Wilson 2019-03-01 478 return PTR_ERR(scratch);
34ae8455 Chris Wilson 2019-03-01 479
34ae8455 Chris Wilson 2019-03-01 480 batch = create_batch(ctx);
34ae8455 Chris Wilson 2019-03-01 481 if (IS_ERR(batch)) {
34ae8455 Chris Wilson 2019-03-01 482 err = PTR_ERR(batch);
34ae8455 Chris Wilson 2019-03-01 483 goto out_scratch;
34ae8455 Chris Wilson 2019-03-01 484 }
34ae8455 Chris Wilson 2019-03-01 485
34ae8455 Chris Wilson 2019-03-01 486 for (i = 0; i <
engine->whitelist.count; i++) {
34ae8455 Chris Wilson 2019-03-01 487 u32 reg =
i915_mmio_reg_offset(engine->whitelist.list[i].reg);
34ae8455 Chris Wilson 2019-03-01 488 u64 addr = scratch->node.start;
34ae8455 Chris Wilson 2019-03-01 489 struct i915_request *rq;
34ae8455 Chris Wilson 2019-03-01 490 u32 srm, lrm, rsvd;
34ae8455 Chris Wilson 2019-03-01 491 u32 expect;
34ae8455 Chris Wilson 2019-03-01 492 int idx;
34ae8455 Chris Wilson 2019-03-01 493
34ae8455 Chris Wilson 2019-03-01 494 if (wo_register(engine, reg))
34ae8455 Chris Wilson 2019-03-01 495 continue;
34ae8455 Chris Wilson 2019-03-01 496
34ae8455 Chris Wilson 2019-03-01 497 srm = MI_STORE_REGISTER_MEM;
34ae8455 Chris Wilson 2019-03-01 498 lrm = MI_LOAD_REGISTER_MEM;
34ae8455 Chris Wilson 2019-03-01 499 if (INTEL_GE
Re: [Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
>
> When we return pages to the system, we ensure that they are marked as
> being in the CPU domain since any external access is uncontrolled and we
> must assume the worst. This means that we need to always flush the pages
> on acquisition if we need to use them on the GPU, and from the beginning
> have used set-domain. Set-domain is overkill for the purpose as it is a
> general synchronisation barrier, but our intent is to only flush the
> pages being swapped in. If we move that flush into the pages acquisition
> phase, we know then that when we have obj->mm.pages, they are coherent
> with the GPU and need only maintain that status without resorting to
> heavy handed use of set-domain.
>
> The principle knock-on effect for userspace is through mmap-gtt
> pagefaulting. Our uAPI has always implied that the GTT mmap was async
> (especially as when any pagefault occurs is unpredicatable to userspace)
> and so userspace had to apply explicit domain control itself
> (set-domain). However, swapping is transparent to the kernel, and so on
> first fault we need to acquire the pages and make them coherent for
> access through the GTT. Our use of set-domain here leaks into the uABI
> that the first pagefault was synchronous. This is unintentional and
> baring a few igt should be unoticed, nevertheless we bump the uABI
> version for mmap-gtt to reflect the change in behaviour.
>
> Another implication of the change is that gem_create() is presumed to
> create an object that is coherent with the CPU and is in the CPU write
> domain, so a set-domain(CPU) following a gem_create() would be a minor
> operation that merely checked whether we could allocate all pages for
> the object. On applying this change, a set-domain(CPU) causes a clflush
> as we acquire the pages. This will have a small impact on mesa as we move
> the clflush here on !llc from execbuf time to create, but that should
> have minimal performance impact as the same clflush exists but is now
> done early and because of the clflush issue, userspace recycles bo and
> so should resist allocating fresh objects.
>
> Internally, the presumption that objects are created in the CPU
> write-domain and remain so through writes to obj->mm.mapping is more
> prevalent than I expect; but easy enough to catch and apply a manual
> flush.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
> Cc: Daniele Ceraolo Spurio
> Cc: Antonio Argenziano
> Cc: Joonas Lahtinen
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +++
> drivers/gpu/drm/i915/i915_gem.c | 57 -
> drivers/gpu/drm/i915/i915_gem_dmabuf.c| 1 +
> drivers/gpu/drm/i915/i915_gem_execbuffer.c| 7 +--
> drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 +-
> drivers/gpu/drm/i915/intel_engine_cs.c| 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 63 +--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 62 +++---
> drivers/gpu/drm/i915/selftests/huge_pages.c | 5 +-
> .../gpu/drm/i915/selftests/i915_gem_context.c | 17 ++---
> .../gpu/drm/i915/selftests/i915_gem_dmabuf.c | 1 +
> .../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
> drivers/gpu/drm/i915/selftests/i915_request.c | 14 ++---
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +-
> .../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/selftests/intel_lrc.c| 5 +-
> .../drm/i915/selftests/intel_workarounds.c| 3 +
> 18 files changed, 127 insertions(+), 134 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c65c2e6649df..395aa9d5ba02 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2959,6 +2959,14 @@ i915_coherent_map_type(struct drm_i915_private *i915)
> void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
>enum i915_map_type type);
>
> +void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
> +unsigned long offset,
> +unsigned long size);
> +static inline void i915_gem_object_flush_map(struct drm_i915_gem_object *obj)
> +{
> + __i915_gem_object_flush_map(obj, 0, obj->base.size);
> +}
> +
> /**
> * i915_gem_object_unpin_map - releases an earlier mapping
> * @obj: the object to unmap
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b7086c8d4726..41d96414ef18 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1713,6 +1713,9 @@ static unsigned int tile_row_pages(const struct
> drm_i915_gem_object *obj)
> * 2 - Recognise WC as a separate cache domain so that we can flush the
> * delayed writes via GTT before performing direct access via WC.
> *
> + * 3 - Remove implicit
Re: [Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
Quoting Matthew Auld (2019-03-20 11:41:52)
> On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > drm_i915_gem_object *obj,
> >
> > lockdep_assert_held(&obj->mm.lock);
> >
> > + /* Make the pages coherent with the GPU (flushing any swapin). */
> > + if (obj->cache_dirty) {
> > + obj->write_domain = 0;
> > + if (i915_gem_object_has_struct_page(obj))
> > + drm_clflush_sg(pages);
> > + obj->cache_dirty = false;
> > + }
>
> Is it worth adding some special casing here for volatile objects, so
> that we avoid doing the clflush_sg every time we do set_pages for
> !llc?
>
> if (obj->cache_dirty && obj->mm.madvise == WILLNEED)
>
> Or is that meh?
No, even for volatile objects we have to be careful with what remains in
the CPU cache as that may obscure updates to the underlying page. We see
the very same problem with speculative cacheline loading.
A DONTNEED object should fail before it gets allocated pages :)
If it becomes DONTNEED in flight? Haven't considered that case, but I
think it is best we keep the pages around as we have people waiting for
them, so we should consider them in use and so only reap them after this
period of activity.
One agenda I have for local-memory is the per-fd private page pool,
where we can stuff cache flushed pages for reuse in !llc. However, all
the testing many, many years ago said that if userspace is doing the
write thing, such a cache is fruitless.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
>-Original Message-
>From: Kulkarni, Vandita
>Sent: Wednesday, March 20, 2019 3:39 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani ; Shankar, Uma ;
>Chauhan, Madhav ; Kulkarni, Vandita
>
>Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
You can drop dsi from commit header. Just drm/i915/icl/ should be good.
Also update header as Ungate ddi clocks if gated
>
>IO enable sequencing needs ddi clocks enabled.
>These clocks will be gated at the later point in the enable sequence.
>
>Signed-off-by: Vandita Kulkarni
>---
> drivers/gpu/drm/i915/icl_dsi.c | 8
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>index
>beb30d9..f02504d 100644
>--- a/drivers/gpu/drm/i915/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/icl_dsi.c
>@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
>*encoder,
> val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
>+ /* make sure that the ddi clocks are not gated */
>+ val = I915_READ(DPCLKA_CFGCR0_ICL);
>+ for_each_dsi_port(port, intel_dsi->ports) {
>+ val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>+ }
>+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+
> POSTING_READ(DPCLKA_CFGCR0_ICL);
I think you can reuse the val from top and avoid an extra write to the same
register.
Otherwise change looks ok to me. With above comments fixed,
Reviewed-by: Uma Shankar
>
> mutex_unlock(&dev_priv->dpll_lock);
>--
>1.9.1
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Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Imre
>Deak
>Sent: Wednesday, March 20, 2019 4:38 PM
>To: Kulkarni, Vandita
>Cc: Nikula, Jani ; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix port disable
>sequence
You can drop the dsi from drm/i915/icl/. Add at description or commit header.
Like
drm/i915/icl: Fix DSI port disable sequence
>
>On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
>> Re-enable clock gating of DDI clocks.
>>
>> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
>> Signed-off-by: Vandita Kulkarni
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
>> b/drivers/gpu/drm/i915/icl_dsi.c index f02504d..716be38 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -1125,7 +1125,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
>*encoder)
>> DRM_ERROR("DDI port:%c buffer not idle\n",
>>port_name(port));
>> }
>> -gen11_dsi_ungate_clocks(encoder);
>> +gen11_dsi_gate_clocks(encoder);
>
>This also requires updating icl_sanitize_encoder_pll_mapping().
>Currently it assumes that the DDI clock needs to be ungated if the
>corresponding DSI
>port is disabled and gated if the port is enabled.
>
>The changes in this patchset mean that the DDI clock should be gated for DSI
>ports
>regardless of whether the port is enabled or not.
I agree. This change look fine, but there is an issue there with
icl_sanitize_encoder_pll_mapping.
>> }
>>
>> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
>> --
>> 1.9.1
>>
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 11:41:52)
> > On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > drm_i915_gem_object *obj,
> > >
> > > lockdep_assert_held(&obj->mm.lock);
> > >
> > > + /* Make the pages coherent with the GPU (flushing any swapin). */
> > > + if (obj->cache_dirty) {
> > > + obj->write_domain = 0;
> > > + if (i915_gem_object_has_struct_page(obj))
> > > + drm_clflush_sg(pages);
> > > + obj->cache_dirty = false;
> > > + }
> >
> > Is it worth adding some special casing here for volatile objects, so
> > that we avoid doing the clflush_sg every time we do set_pages for
> > !llc?
> >
> > if (obj->cache_dirty && obj->mm.madvise == WILLNEED)
> >
> > Or is that meh?
>
> No, even for volatile objects we have to be careful with what remains in
> the CPU cache as that may obscure updates to the underlying page. We see
> the very same problem with speculative cacheline loading.
>
> A DONTNEED object should fail before it gets allocated pages :)
I was talking about kernel internal objects, which are marked as
DONTNEED just before we call set_pages(), and for that case it's
surely up to the caller to flush things before they even think of
doing the unpin(since it's volatile).
>
> If it becomes DONTNEED in flight? Haven't considered that case, but I
> think it is best we keep the pages around as we have people waiting for
> them, so we should consider them in use and so only reap them after this
> period of activity.
>
> One agenda I have for local-memory is the per-fd private page pool,
> where we can stuff cache flushed pages for reuse in !llc. However, all
> the testing many, many years ago said that if userspace is doing the
> write thing, such a cache is fruitless.
> -Chris
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[Intel-gfx] [CI] drm/i915: always use masks on FW regs
From: Daniele Ceraolo Spurio
Upper bits are reserved on gen6, so no issue if we write them. Note that
we're already doing this in the non-MT case of IVB, which uses the same
register.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_uncore.c | 44 +++--
drivers/gpu/drm/i915/intel_uncore.h | 4 ---
2 files changed, 16 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 7129eebc333b..b4cea3cf3915 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -59,18 +59,19 @@ intel_uncore_forcewake_domain_to_str(const enum
forcewake_domain_id id)
}
#define fw_ack(d) readl((d)->reg_ack)
-#define fw_set(d, val) writel((val), (d)->reg_set)
+#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
+#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
static inline void
-fw_domain_reset(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
{
/*
* We don't really know if the powerwell for the forcewake domain we are
* trying to reset here does exist at this point (engines could be fused
* off in ICL+), so no waiting for acks
*/
- fw_set(d, uncore->fw_reset);
+ /* WaRsClearFWBitsAtReset:bdw,skl */
+ fw_clear(d, 0x);
}
static inline void
@@ -146,14 +147,14 @@ fw_domain_wait_ack_with_fallback(const struct
intel_uncore_forcewake_domain *d,
do {
wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK);
- fw_set(d, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL_FALLBACK));
+ fw_set(d, FORCEWAKE_KERNEL_FALLBACK);
/* Give gt some time to relax before the polling frenzy */
udelay(10 * pass);
wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK);
ack_detected = (fw_ack(d) & ack_bit) == value;
- fw_set(d, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL_FALLBACK));
+ fw_clear(d, FORCEWAKE_KERNEL_FALLBACK);
} while (!ack_detected && pass++ < 10);
DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n",
@@ -176,10 +177,9 @@ fw_domain_wait_ack_clear_fallback(const struct
intel_uncore_forcewake_domain *d)
}
static inline void
-fw_domain_get(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_get(const struct intel_uncore_forcewake_domain *d)
{
- fw_set(d, uncore->fw_set);
+ fw_set(d, FORCEWAKE_KERNEL);
}
static inline void
@@ -201,10 +201,9 @@ fw_domain_wait_ack_set_fallback(const struct
intel_uncore_forcewake_domain *d)
}
static inline void
-fw_domain_put(const struct intel_uncore *uncore,
- const struct intel_uncore_forcewake_domain *d)
+fw_domain_put(const struct intel_uncore_forcewake_domain *d)
{
- fw_set(d, uncore->fw_clear);
+ fw_clear(d, FORCEWAKE_KERNEL);
}
static void
@@ -218,7 +217,7 @@ fw_domains_get(struct drm_i915_private *i915, enum
forcewake_domains fw_domains)
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
fw_domain_wait_ack_clear(d);
- fw_domain_get(uncore, d);
+ fw_domain_get(d);
}
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
@@ -239,7 +238,7 @@ fw_domains_get_with_fallback(struct drm_i915_private *i915,
for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
fw_domain_wait_ack_clear_fallback(d);
- fw_domain_get(uncore, d);
+ fw_domain_get(d);
}
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
@@ -258,7 +257,7 @@ fw_domains_put(struct drm_i915_private *i915, enum
forcewake_domains fw_domains)
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
- fw_domain_put(uncore, d);
+ fw_domain_put(d);
uncore->fw_domains_active &= ~fw_domains;
}
@@ -277,7 +276,7 @@ fw_domains_reset(struct drm_i915_private *i915,
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
for_each_fw_domain_masked(d, fw_domains, i915, tmp)
- fw_domain_reset(uncore, d);
+ fw_domain_reset(d);
}
static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
@@ -1371,7 +1370,7 @@ static void fw_domain_init(struct drm_i915_private
*dev_priv,
uncore->fw_domains |= BIT(domain_id);
- fw_domain_reset(uncore, d);
+ fw_domain_reset(d);
}
static void fw_domain_fini(struct drm_i915_private *dev_priv,
@@ -1396,17 +1395,6 @@ static void intel_uncore_fw_domains_init(struct
drm_i915_private *dev
Re: [Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
Quoting Matthew Auld (2019-03-20 12:26:00)
> On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > wrote:
> > > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > > drm_i915_gem_object *obj,
> > > >
> > > > lockdep_assert_held(&obj->mm.lock);
> > > >
> > > > + /* Make the pages coherent with the GPU (flushing any swapin).
> > > > */
> > > > + if (obj->cache_dirty) {
> > > > + obj->write_domain = 0;
> > > > + if (i915_gem_object_has_struct_page(obj))
> > > > + drm_clflush_sg(pages);
> > > > + obj->cache_dirty = false;
> > > > + }
> > >
> > > Is it worth adding some special casing here for volatile objects, so
> > > that we avoid doing the clflush_sg every time we do set_pages for
> > > !llc?
> > >
> > > if (obj->cache_dirty && obj->mm.madvise == WILLNEED)
> > >
> > > Or is that meh?
> >
> > No, even for volatile objects we have to be careful with what remains in
> > the CPU cache as that may obscure updates to the underlying page. We see
> > the very same problem with speculative cacheline loading.
> >
> > A DONTNEED object should fail before it gets allocated pages :)
>
> I was talking about kernel internal objects, which are marked as
> DONTNEED just before we call set_pages(), and for that case it's
> surely up to the caller to flush things before they even think of
> doing the unpin(since it's volatile).
But those objects also become WILLNEED at that point, and may still need
to be flushed.
The cost of the extra flushes is a worry, but not enough for me to be
concerned about. I think the convention that get_pages == coherent on
gpu improves quite a bit of our internal rummaging around and prevents
the ABI nightmare of mmap_gtt/mmap_offset. Will this flush remain inside
set_pages()? No, I don't think it will as pushing it into the callers
outside of the mm.lock itself makes sense, but I didn't think that was
of paramount importance compared to the uABI and can be done later.
-Chris
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Re: [Intel-gfx] [PATCH 07/18] drm/i915: Stop storing the context name as the timeline name
On 19/03/2019 11:57, Chris Wilson wrote:
The timeline->name is only used for convenience in pretty printing the
i915_request.fence->ops->get_timeline_name() and it is just as
convenient to pull it from the gem_context directly. The few instances
of its use inside GEM_TRACE() has proven more of a nuisance than
helpful, so not worth saving imo.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 5 ++---
drivers/gpu/drm/i915/i915_request.c| 7 ++-
drivers/gpu/drm/i915/i915_timeline.c | 5 +
drivers/gpu/drm/i915/i915_timeline.h | 2 --
drivers/gpu/drm/i915/i915_timeline_types.h | 1 -
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +--
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 4 +---
drivers/gpu/drm/i915/selftests/i915_timeline.c | 6 +++---
drivers/gpu/drm/i915/selftests/mock_engine.c | 9 ++---
10 files changed, 13 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 95c5103e15a5..196982f38a28 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -673,9 +673,8 @@ last_request_on_engine(struct i915_timeline *timeline,
rq = i915_active_request_raw(&timeline->last_request,
&engine->i915->drm.struct_mutex);
if (rq && rq->engine == engine) {
- GEM_TRACE("last request for %s on engine %s: %llx:%llu\n",
- timeline->name, engine->name,
- rq->fence.context, rq->fence.seqno);
+ GEM_TRACE("last request on engine %s: %llx:%llu\n",
+ engine->name, rq->fence.context, rq->fence.seqno);
GEM_BUG_ON(rq->timeline != timeline);
return rq;
}
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 0a3d94517d0a..1529824d7c61 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -66,7 +66,7 @@ static const char *i915_fence_get_timeline_name(struct
dma_fence *fence)
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
return "signaled";
- return to_request(fence)->timeline->name;
+ return to_request(fence)->gem_context->name ?: "[i915]";
}
static bool i915_fence_signaled(struct dma_fence *fence)
@@ -167,7 +167,6 @@ static void advance_ring(struct i915_request *request)
* is just about to be. Either works, if we miss the last two
* noops - they are safe to be replayed on a reset.
*/
- GEM_TRACE("marking %s as inactive\n", ring->timeline->name);
tail = READ_ONCE(request->tail);
list_del(&ring->active_link);
} else {
@@ -1064,10 +1063,8 @@ void i915_request_add(struct i915_request *request)
__i915_active_request_set(&timeline->last_request, request);
list_add_tail(&request->ring_link, &ring->request_list);
- if (list_is_first(&request->ring_link, &ring->request_list)) {
- GEM_TRACE("marking %s as active\n", ring->timeline->name);
+ if (list_is_first(&request->ring_link, &ring->request_list))
list_add(&ring->active_link, &request->i915->gt.active_rings);
- }
request->i915->gt.active_engines |= request->engine->mask;
request->emitted_jiffies = jiffies;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c b/drivers/gpu/drm/i915/i915_timeline.c
index 8484ba6e51d1..2f4907364920 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -197,7 +197,6 @@ static void cacheline_free(struct i915_timeline_cacheline
*cl)
int i915_timeline_init(struct drm_i915_private *i915,
struct i915_timeline *timeline,
- const char *name,
struct i915_vma *hwsp)
{
void *vaddr;
@@ -213,7 +212,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
timeline->i915 = i915;
- timeline->name = name;
timeline->pin_count = 0;
timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
@@ -342,7 +340,6 @@ void i915_timeline_fini(struct i915_timeline *timeline)
struct i915_timeline *
i915_timeline_create(struct drm_i915_private *i915,
-const char *name,
struct i915_vma *global_hwsp)
{
struct i915_timeline *timeline;
@@ -352,7 +349,7 @@ i915_timeline_create(struct drm_i915_private *i915,
if (!timeline)
return ERR_PTR(-ENOMEM);
- err = i915_timeline_init(i915, timeline, name, global_hwsp);
+ err = i915_timeline_init(i915, timeline, global_hwsp);
if (err) {
Re: [Intel-gfx] [PATCH 09/18] drm/i915: Create/destroy VM (ppGTT) for use with contexts
On 19/03/2019 11:57, Chris Wilson wrote:
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise with struct_mutex; it's lazy but required dammit
v4: Rewrite igt_ctx_shared_exec to be more different (aimed to be more
similarly, turned out different!)
v5: Fix up test unwind for aliasing-ppgtt (snb)
v6: Tighten language for uapi struct drm_i915_gem_vm_control.
v7: Patch the context image for runtime ppgtt switching!
Testcase: igt/gem_vm_create
Testcase: igt/gem_ctx_param/vm
Testcase: igt/gem_ctx_clone/vm
Testcase: igt/gem_ctx_shared
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 331 +-
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 1 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 238 ++---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 8 +-
include/uapi/drm/i915_drm.h | 43 +++
11 files changed, 580 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a3b00ecc58c9..fa991144e0f2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3121,6 +3121,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 219348121897..87ef2e031b2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -220,6 +220,9 @@ struct drm_i915_file_private {
struct idr context_idr;
struct mutex context_idr_lock; /* guards context_idr */
+ struct idr vm_idr;
+ struct mutex vm_idr_lock; /* guards vm_idr */
+
unsigned int bsd_engine;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 196982f38a28..966fbbc154d3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
#include "i915_drv.h"
#include "i915_globals.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
@@ -120,12 +121,15 @@ static void lut_close(struct i915_gem_context *ctx)
list_del(&lut->obj_link);
i915_lut_handle_free(lut);
}
+ INIT_LIST_HEAD(&ctx->handles_list);
rcu_read_lock();
radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
struct i915_vma *vma = rcu_dereference_raw(*slot);
radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
+
+ vma->open_count--;
__i915_gem_object_release_unless_active(vma->obj);
}
rcu_read_unlock();
@@ -305,8 +309,6 @@ static void context_close(struct i915_gem_context *ctx)
* the ppgtt).
*/
lut_close(ctx);
- if (ctx->ppgtt)
- i915_ppgtt_close(&ctx->ppgtt->vm);
ctx->file_priv = ERR_PTR(-EBADF);
i915_gem_context_put(ctx);
@@ -378,6 +380,28 @@ __create_context(struct drm_i915_private *dev_priv)
return ctx;
}
+static struct i915_hw_ppgtt *
+__set_ppgtt(struct i915_gem_context *ctx, struct i915_hw_ppgtt *ppgtt)
+{
+ struct i915_hw_ppgtt *old = ctx->ppgtt;
+
+ ctx->ppgtt = i915_ppgtt_get(ppgtt);
+ ctx->desc_template = default_desc_template(ctx->i915, ppgtt);
+
+ return old;
+}
+
+static void __assign_ppgtt(struct i915_gem_context *ctx,
+ struct i915_hw_ppgtt *ppgtt)
+{
+ if (ppgtt == ctx->ppgtt)
+ return;
+
+ ppgtt = __set_ppgtt(ctx, ppgtt);
+ if (ppgtt)
+ i915_ppgtt_put(ppgtt);
+}
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv)
{
@@ -403,8 +427,8 @@ i915_gem_create_context(struct drm_i915_private *dev_priv)
re
Re: [Intel-gfx] [PATCH 12/18] drm/i915: Allow userspace to clone contexts on creation
On 19/03/2019 11:57, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient if they were able to just pass in a target context to clone
during creation. This essentially extends the setparam during creation
to pull the details from a target context instead of the user supplied
parameters.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 154
include/uapi/drm/i915_drm.h | 14 +++
2 files changed, 168 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index fc1f64e19507..f36648329074 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1500,8 +1500,162 @@ static int create_setparam(struct i915_user_extension
__user *ext, void *data)
return ctx_setparam(arg->ctx, &local.param);
}
+static int clone_flags(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ dst->user_flags = src->user_flags;
+ return 0;
+}
+
+static int clone_schedattr(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ dst->sched = src->sched;
+ return 0;
+}
+
+static int clone_sseu(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ const struct intel_sseu default_sseu =
+ intel_device_default_sseu(dst->i915);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dst->i915, id) {
Hm in the load balancing patch this needs to be extended so the veng ce
is also handled here.
Possibly even when adding engine map the loop needs to iterate the map
and not for_each_engine?
+ struct intel_context *ce;
+ struct intel_sseu sseu;
+
+ ce = intel_context_lookup(src, engine);
+ if (!ce)
+ continue;
+
+ sseu = ce->sseu;
+ if (!memcmp(&sseu, &default_sseu, sizeof(sseu)))
Could memcmp against &ce->sseu directly and keep src_ce and dst_ce so
you can copy over without a temporary copy on stack?
+ continue;
+
+ ce = intel_context_pin_lock(dst, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ ce->sseu = sseu;
+ intel_context_pin_unlock(ce);
+ }
+
+ return 0;
+}
+
+static int clone_timeline(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ if (src->timeline) {
+ GEM_BUG_ON(src->timeline == dst->timeline);
+
+ if (dst->timeline)
+ i915_timeline_put(dst->timeline);
+ dst->timeline = i915_timeline_get(src->timeline);
+ }
+
+ return 0;
+}
+
+static int clone_vm(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ struct i915_hw_ppgtt *ppgtt;
+
+ rcu_read_lock();
+ do {
+ ppgtt = READ_ONCE(src->ppgtt);
+ if (!ppgtt)
+ break;
+
+ if (!kref_get_unless_zero(&ppgtt->ref))
+ continue;
+
+ /*
+* This ppgtt may have be reallocated between
+* the read and the kref, and reassigned to a third
+* context. In order to avoid inadvertent sharing
+* of this ppgtt with that third context (and not
+* src), we have to confirm that we have the same
+* ppgtt after passing through the strong memory
+* barrier implied by a successful
+* kref_get_unless_zero().
+*
+* Once we have acquired the current ppgtt of src,
+* we no longer care if it is released from src, as
+* it cannot be reallocated elsewhere.
+*/
+
+ if (ppgtt == READ_ONCE(src->ppgtt))
+ break;
+
+ i915_ppgtt_put(ppgtt);
+ } while (1);
+ rcu_read_unlock();
I still have the same problem. What if you added here:
GEM_BUG_ON(ppgtt != READ_ONCE(src->ppgtt));
Could it trigger? If so what is the point in the last check in the loop
above?
+
+ if (ppgtt) {
+ __assign_ppgtt(dst, ppgtt);
+ i915_ppgtt_put(ppgtt);
+ }
+
+ return 0;
+}
+
+static int create_clone(struct i915_user_extension __user *ext, void *data)
+{
+ static int (* const fn[])(struct i915_gem_context *dst,
+ struct i915_gem_context *src) = {
+#define MAP(x, y) [ilog2(I
Re: [Intel-gfx] [PATCH 13/18] drm/i915: Allow a context to define its set of engines
On 19/03/2019 11:57, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance) tuples to identify a
specific engine, with an API for the user to construct a map of engines
to capabilities. Into this picture, we then add a challenge of virtual
engines; one user engine that maps behind the scenes to any number of
physical engines. To keep it general, we want the user to have full
control over that mapping. To that end, we allow the user to constrain a
context to define the set of engines that it can access, order fully
controlled by the user via (class, instance). With such precise control
in context setup, we can continue to use the existing execbuf uABI of
specifying a single index; only now it doesn't automagically map onto
the engines, it uses the user defined engine map from the context.
The I915_EXEC_DEFAULT slot is left empty, and invalid for use by
execbuf. It's use will be revealed in the next patch.
v2: Fixup freeing of local on success of get_engines()
v3: Allow empty engines[]
v4: s/nengine/num_engines/
Testcase: igt/gem_ctx_engines
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 226 +-
drivers/gpu/drm/i915/i915_gem_context_types.h | 21 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 19 +-
drivers/gpu/drm/i915/i915_utils.h | 36 +++
include/uapi/drm/i915_drm.h | 42 +++-
5 files changed, 331 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f36648329074..f038c15e73d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -86,7 +86,9 @@
*/
#include
+
#include
+
#include "i915_drv.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -101,6 +103,21 @@ static struct i915_global_gem_context {
struct kmem_cache *slab_luts;
} global;
+static struct intel_engine_cs *
+lookup_user_engine(struct i915_gem_context *ctx,
+ unsigned long flags, u16 class, u16 instance)
+#define LOOKUP_USER_INDEX BIT(0)
+{
+ if (flags & LOOKUP_USER_INDEX) {
+ if (instance >= ctx->num_engines)
+ return NULL;
+
+ return ctx->engines[instance];
+ }
+
+ return intel_engine_lookup_user(ctx->i915, class, instance);
+}
+
struct i915_lut_handle *i915_lut_handle_alloc(void)
{
return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
@@ -235,6 +252,8 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
release_hw_id(ctx);
i915_ppgtt_put(ctx->ppgtt);
+ kfree(ctx->engines);
+
rbtree_postorder_for_each_entry_safe(it, n, &ctx->hw_contexts, node)
intel_context_put(it);
@@ -1377,9 +1396,9 @@ static int set_sseu(struct i915_gem_context *ctx,
if (user_sseu.flags || user_sseu.rsvd)
return -EINVAL;
- engine = intel_engine_lookup_user(i915,
- user_sseu.engine_class,
- user_sseu.engine_instance);
+ engine = lookup_user_engine(ctx, 0,
+ user_sseu.engine_class,
+ user_sseu.engine_instance);
if (!engine)
return -EINVAL;
@@ -1397,9 +1416,166 @@ static int set_sseu(struct i915_gem_context *ctx,
args->size = sizeof(user_sseu);
+ return 0;
+};
+
+struct set_engines {
+ struct i915_gem_context *ctx;
+ struct intel_engine_cs **engines;
+ unsigned int num_engines;
+};
+
+static const i915_user_extension_fn set_engines__extensions[] = {
+};
+
+static int
+set_engines(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ struct i915_context_param_engines __user *user;
+ struct set_engines set = { .ctx = ctx };
+ u64 size, extensions;
+ unsigned int n;
+ int err;
+
+ user = u64_to_user_ptr(args->value);
+ size = args->size;
+ if (!size)
+ goto out;
+
+ BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->class_instance)));
+ if (size < sizeof(*user) ||
+ !IS_ALIGNED(size, sizeof(*user->class_instance)))
+ return -EINVAL;
+
+ /* Internal limitation of u64 bitmaps + a few bits of u64 in the uABI */
+ set.num_engines =
+ (size - sizeof(*user)) / sizeof(*user->class_instance);
+ if (set.num_engines > I915_EXEC_RING_MASK + 1)
+ return -EINVAL;
+
+ set.engines = kmalloc_array(set.num_engines,
+ sizeof(*set.engines),
+ GFP_KERNEL);
Re: [Intel-gfx] [PATCH 14/18] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
On 19/03/2019 11:57, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context and do not have a valid global class:instance
lookup.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 24
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f038c15e73d8..cbd76ef95115 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1381,6 +1381,7 @@ static int set_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_sseu sseu;
+ unsigned long lookup;
int ret;
if (args->size < sizeof(user_sseu))
@@ -1393,10 +1394,17 @@ static int set_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
@@ -1967,6 +1975,7 @@ static int get_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_context *ce;
+ unsigned long lookup;
if (args->size == 0)
goto out;
@@ -1977,10 +1986,17 @@ static int get_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 4e67c2395b46..8ef6d60929c6 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1567,9 +1567,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
-* Unused for now. Must be cleared to zero.
+* Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Ensure minimum CDCLK requirement for audio (rev4)
== Series Details == Series: drm/i915: Ensure minimum CDCLK requirement for audio (rev4) URL : https://patchwork.freedesktop.org/series/58132/ State : failure == Summary == Applying: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled Applying: drm/i915: Skip modeset for cdclk changes if possible error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_cdclk.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0002 drm/i915: Skip modeset for cdclk changes if possible When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/selftests: Mark up preemption tests for hang detection
== Series Details == Series: drm/i915/selftests: Mark up preemption tests for hang detection URL : https://patchwork.freedesktop.org/series/58236/ State : failure == Summary == Applying: drm/i915/selftests: Mark up preemption tests for hang detection Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/selftests/intel_lrc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/selftests/intel_lrc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/selftests/intel_lrc.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch' to see the failed patch Patch failed at 0001 drm/i915/selftests: Mark up preemption tests for hang detection When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add HDR Metadata Parsing and handling in DRM layer (rev6)
== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev6) URL : https://patchwork.freedesktop.org/series/25091/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3ffebb6ddcbf drm: Add HDR source metadata property 6d0a7b41e79c drm: Parse HDR metadata info from EDID 02252707998b drm: Parse Colorimetry data block from EDID 311d0c32e536 drm/i915: Attach HDR metadata property to connector cc3d717ffd61 drm: Implement HDR output metadata set and get property handling -:52: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #52: FILE: drivers/gpu/drm/drm_atomic_uapi.c:741: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->hdr_output_metadata_blob_ptr, total: 0 errors, 0 warnings, 1 checks, 39 lines checked a39aa58b30aa drm: Enable HDR infoframe support bd2cd9ae7106 drm/i915: Write HDR infoframe and send to panel 504bef292ea4 drm/i915: [DO NOT MERGE] hack for glk board outputs aea5797dab83 drm/i915: Add HLG EOTF 2ca575ccdf2f drm/i915: Enable infoframes on GLK+ for HDR -:49: WARNING:LONG_LINE: line over 100 characters #49: FILE: drivers/gpu/drm/i915/i915_reg.h:8209: +#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) total: 0 errors, 1 warnings, 0 checks, 76 lines checked 9cb3d2a68365 drm/i915:Enabled Modeset when HDR Infoframe changes ba5c46ba53f9 drm/i915: Set Infoframe for non modeset case for HDR 9184e65ae696 video/hdmi: Add const variants for drm infoframe ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
during cdclk change(Abhay).
v4: Remove Power well 2 reset workaround(Ville).
v5: Remove unwanted Power well 2 register defined in v4(Abhay).
v6:
- Use a dedicated flag instead of state->modeset for min CDCLK changes
- Make get/put audio power domain symmetric
- Rebased on top of intel_wakeref tracking changes.
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
Tested-by: Abhay Kumar
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/intel_audio.c | 64 ++--
drivers/gpu/drm/i915/intel_cdclk.c | 30 ++---
drivers/gpu/drm/i915/intel_display.c | 9 -
drivers/gpu/drm/i915/intel_drv.h | 3 ++
5 files changed, 86 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c65c2e6649df..6b10cee4e77f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1624,6 +1624,8 @@ struct drm_i915_private {
struct intel_cdclk_state actual;
/* The current hardware cdclk state */
struct intel_cdclk_state hw;
+
+ int force_min_cdclk;
} cdclk;
/**
@@ -1743,6 +1745,7 @@ struct drm_i915_private {
*
*/
struct mutex av_mutex;
+ int audio_power_refcount;
struct {
struct mutex mutex;
diff --git a/drivers/gpu/drm/i915/intel_audio.c
b/drivers/gpu/drm/i915/intel_audio.c
index 502b57ce72ab..20324b0d34c7 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -741,18 +741,78 @@ void intel_init_audio_hooks(struct drm_i915_private
*dev_priv)
}
}
+static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
+ bool enable)
+{
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_atomic_state *state;
+ int ret;
+
+ drm_modeset_acquire_init(&ctx, 0);
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (WARN_ON(!state))
+ return;
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true;
+ to_intel_atomic_state(state)->cdclk.force_min_cdclk =
+ enable ? 2 * 96000 : 0;
+
+ /*
+* Protects dev_priv->cdclk.force_min_cdclk
+* Need to lock this here in case we have no active pipes
+* and thus wouldn't lock it during the commit otherwise.
+*/
+ ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
+ &ctx);
+ if (!ret)
+ ret = drm_atomic_commit(state);
+
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ WARN_ON(ret);
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
static unsigned long i915_audio_component_get_power(struct device *kdev)
{
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+ intel_wakeref_t ret;
+
/* Catch potential impedance mismatches before they occur! */
BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
- return intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
+ ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+
+ /* Force CDCLK to 2*BCLK as long as we need audio to be powered. */
+ if (dev_priv->audio_power_refcount++ == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, true);
+
+ return ret;
}
static void i915_audio_component_put_power(struct device *kdev,
unsigned long cookie)
{
- intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO, cookie);
+ struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+ /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
+ if (--dev_priv->audio_power_refcount == 0)
+ if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ glk_force_audio_cdclk(dev_priv, false);
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
}
static void i915_audio_component_codec_wake_override(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 21fb4e0d6c4e..7dcca84f31d1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/dr
[Intel-gfx] [CI 2/4] drm/i915: Save the old CDCLK atomic state
The old state will be needed by an upcoming patch to determine if the
commit increases or decreases CDCLK, so move the old state to the atomic
state (while keeping the new one in dev_priv). cdclk.logical and
cdclk.actual in the atomic state isn't used atm anywhere after the
atomic check phase, so this should be safe.
v2:
- Use swap() instead of opencoding it. (Ville)
Suggested-by: Ville Syrjälä
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_cdclk.c | 20
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 7dcca84f31d1..5c25626f8cf0 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -2100,6 +2100,26 @@ bool intel_cdclk_changed(const struct intel_cdclk_state
*a,
a->voltage_level != b->voltage_level;
}
+/**
+ * intel_cdclk_swap_state - make atomic CDCLK configuration effective
+ * @state: atomic state
+ *
+ * This is the CDCLK version of drm_atomic_helper_swap_state() since the
+ * helper does not handle driver-specific global state.
+ *
+ * Similarly to the atomic helpers this function does a complete swap,
+ * i.e. it also puts the old state into @state. This is used by the commit
+ * code to determine how CDCLK has changed (for instance did it increase or
+ * decrease).
+ */
+void intel_cdclk_swap_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+ swap(state->cdclk.logical, dev_priv->cdclk.logical);
+ swap(state->cdclk.actual, dev_priv->cdclk.actual);
+}
+
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
const char *context)
{
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index b4199cd53349..9c4ad124302c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13663,10 +13663,10 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_state->min_voltage_level,
sizeof(intel_state->min_voltage_level));
dev_priv->active_crtcs = intel_state->active_crtcs;
- dev_priv->cdclk.logical = intel_state->cdclk.logical;
- dev_priv->cdclk.actual = intel_state->cdclk.actual;
dev_priv->cdclk.force_min_cdclk =
intel_state->cdclk.force_min_cdclk;
+
+ intel_cdclk_swap_state(intel_state);
}
drm_atomic_state_get(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0b84e557c267..85dd6a9d1e42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1698,6 +1698,7 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_state *a,
const struct intel_cdclk_state *b);
bool intel_cdclk_changed(const struct intel_cdclk_state *a,
const struct intel_cdclk_state *b);
+void intel_cdclk_swap_state(struct intel_atomic_state *state);
void intel_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_state *cdclk_state);
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
--
2.13.2
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[Intel-gfx] [CI 4/4] drm/i915: Skip modeset for cdclk changes if possible
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe needs a modeset (or was disabled).
- Split CDCLK change to a pre/post plane update step.
v3:
- Use correct version of CDCLK state as old state. (Ville)
- Remove unused intel_cdclk_can_skip_modeset()
v4:
- For consistency call intel_set_cdclk_post_plane_update() only during
modesets (and not fastsets).
Signed-off-by: Ville Syrjälä
Signed-off-by: Abhay Kumar
Tested-by: Abhay Kumar
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_cdclk.c | 142 +++
drivers/gpu/drm/i915/intel_display.c | 42 ++-
drivers/gpu/drm/i915/intel_drv.h | 17 -
5 files changed, 170 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6b10cee4e77f..d8f91525c94c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -277,7 +277,8 @@ struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_state);
void (*set_cdclk)(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state);
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe);
int (*get_fifo_size)(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9b69cec21f7b..12b8170ced96 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9521,7 +9521,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
-#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
+#define ICL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define ICL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE(7)
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE(1 << 16)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
b/drivers/gpu/drm/i915/intel_cdclk.c
index 5c25626f8cf0..48cc42a7ef4f 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -516,7 +516,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv)
}
static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -598,7 +599,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
static void chv_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val, cmd = cdclk_state->voltage_level;
@@ -697,7 +699,8 @@ static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
}
static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
u32 val;
@@ -987,7 +990,8 @@ static void skl_dpll0_disable(struct drm_i915_private
*dev_priv)
}
static void skl_set_cdclk(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *cdclk_state)
+ const struct intel_cdclk_state *cdclk_state,
+ enum pipe pipe)
{
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
@@ -1158,7 +1162,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state);
+ skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
}
/**
@@ -1176,7 +1180,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
cdclk_state.vco = 0;
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
- skl_set_cdclk(dev_priv, &cdclk_state);
[Intel-gfx] [CI 3/4] drm/i915: Remove redundant store of logical CDCLK state
We copied the original state into the atomic state already earlier in
the function, so no need to do it a second time.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9c4ad124302c..f7b44773e1e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13031,8 +13031,6 @@ static int intel_modeset_checks(struct drm_atomic_state
*state)
DRM_DEBUG_KMS("New voltage level calculated to be logical %u,
actual %u\n",
intel_state->cdclk.logical.voltage_level,
intel_state->cdclk.actual.voltage_level);
- } else {
- to_intel_atomic_state(state)->cdclk.logical =
dev_priv->cdclk.logical;
}
intel_modeset_clear_plls(state);
--
2.13.2
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev6)
== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev6) URL : https://patchwork.freedesktop.org/series/25091/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12528 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12528 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12528, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/25091/revisions/6/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12528: ### IGT changes ### Possible regressions * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> FAIL - fi-bsw-n3050: NOTRUN -> FAIL - fi-byt-n2820: NOTRUN -> FAIL - fi-elk-e7500: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12528 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@basic-bsd2: - fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9 * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@prime_vgem@basic-fence-flip: - fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182] * igt@runner@aborted: - fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841] - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] - fi-snb-2600:NOTRUN -> FAIL [fdo#108929] Possible fixes * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#108929]: https://bugs.freedesktop.org/show_bug.cgi?id=108929 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (48 -> 42) -- Additional (1): fi-kbl-7500u Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y Build changes - * Linux: CI_DRM_5780 -> Patchwork_12528 CI_DRM_5780: 774f8c588542dda6d73161429cbf1e027789d6ef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12528: 9184e65ae696ba0aaa2fa93a4f6a6d3e04ecb625 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9184e65ae696 video/hdmi: Add const variants for drm infoframe ba5c46ba53f9 drm/i915: Set Infoframe for non modeset case for HDR 9cb3d2a68365 drm/i915:Enabled Modeset when HDR Infoframe changes 2ca575ccdf2f drm/i915: Enable infoframes on GLK+ for HDR aea5797dab83 drm/i915: Add HLG EOTF 504bef292ea4 drm/i915: [DO NOT MERGE] hack for glk board outputs bd2cd9ae7106 drm/i915: Write HDR infoframe and send to panel a39aa58b30aa drm: Enable HDR infoframe support cc3d717ffd61 drm: Implement HDR output metadata set and get property handling 311d0c32e536 drm/i915: Attach HDR metadata property to connector 02252707998b drm: Parse Colorimetry data block from EDID 6d0a7b41e79c drm: Parse HDR metadata info from EDID 3ffebb6ddcbf drm: Add HDR source metadata property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12528/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
On Wed, 20 Mar 2019 at 12:36, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 12:26:00)
> > On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> > >
> > > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > > wrote:
> > > > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > > > drm_i915_gem_object *obj,
> > > > >
> > > > > lockdep_assert_held(&obj->mm.lock);
> > > > >
> > > > > + /* Make the pages coherent with the GPU (flushing any
> > > > > swapin). */
> > > > > + if (obj->cache_dirty) {
> > > > > + obj->write_domain = 0;
> > > > > + if (i915_gem_object_has_struct_page(obj))
> > > > > + drm_clflush_sg(pages);
> > > > > + obj->cache_dirty = false;
> > > > > + }
> > > >
> > > > Is it worth adding some special casing here for volatile objects, so
> > > > that we avoid doing the clflush_sg every time we do set_pages for
> > > > !llc?
> > > >
> > > > if (obj->cache_dirty && obj->mm.madvise == WILLNEED)
> > > >
> > > > Or is that meh?
> > >
> > > No, even for volatile objects we have to be careful with what remains in
> > > the CPU cache as that may obscure updates to the underlying page. We see
> > > the very same problem with speculative cacheline loading.
> > >
> > > A DONTNEED object should fail before it gets allocated pages :)
> >
> > I was talking about kernel internal objects, which are marked as
> > DONTNEED just before we call set_pages(), and for that case it's
> > surely up to the caller to flush things before they even think of
> > doing the unpin(since it's volatile).
>
> But those objects also become WILLNEED at that point, and may still need
> to be flushed.
>
> The cost of the extra flushes is a worry, but not enough for me to be
> concerned about. I think the convention that get_pages == coherent on
> gpu improves quite a bit of our internal rummaging around and prevents
> the ABI nightmare of mmap_gtt/mmap_offset. Will this flush remain inside
> set_pages()? No, I don't think it will as pushing it into the callers
> outside of the mm.lock itself makes sense, but I didn't think that was
> of paramount importance compared to the uABI and can be done later.
Fair enough,
Reviewed-by: Matthew Auld
> -Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12529
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58241/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12529 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_basic@basic-bsd2:
- fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841]
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#103182]
* igt@runner@aborted:
- fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841]
Possible fixes
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (48 -> 42)
--
Additional (1): fi-kbl-7500u
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5780 -> Patchwork_12529
CI_DRM_5780: 774f8c588542dda6d73161429cbf1e027789d6ef @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12529: c02cf03dcc1a2a611ac8dcbda219882e1215f91f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c02cf03dcc1a drm/i915/icl/dsi: Fix port disable sequence
4aec4839ddd9 drm/i915/icl/dsi: Ungate clocks if gated
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12529/
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Re: [Intel-gfx] [PATCH 01/10] drm/i915: Extract check_luts()
On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_color.c | 68 ++
> > 1 file changed, 40 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index 467fd1a1630c..b6a992a5b14f 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -771,6 +771,38 @@ static int check_lut_size(const struct
> > drm_property_blob *lut, int expected)
> > return 0;
> > }
> >
> > +static int check_luts(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > + const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > + int gamma_length, degamma_length;
> > + u32 gamma_tests, degamma_tests;
> > +
> > + /* Always allow legacy gamma LUT with no further checking. */
> > + if (crtc_state_is_legacy_gamma(crtc_state))
> > + return 0;
> > +
> > + /* C8 needs the legacy LUT all to itself */
> > + if (crtc_state->c8_planes)
> > + return -EINVAL;
>
> Do we need to test for non-NULL gamma_lut here?
For c8? We already checked crtc_state_is_legacy_gamma() above.
>
> The logic is the same as before your patch, so either we already had a
> pre-existing bug or, more likely, I'm overlooking something obvious.
>
> > +
> > + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > + degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > + gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > +
> > + if (check_lut_size(degamma_lut, degamma_length) ||
> > + check_lut_size(gamma_lut, gamma_length))
> > + return -EINVAL;
> > +
> > + if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > + drm_color_lut_check(gamma_lut, gamma_tests))
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> > {
> > u32 cgm_mode = 0;
> > @@ -794,19 +826,11 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > bool limited_color_range = false;
> > - int gamma_length, degamma_length;
> > - u32 gamma_tests, degamma_tests;
> > int ret;
> >
> > - degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > - gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > - degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > - gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > -
> > - /* C8 needs the legacy LUT all to itself */
> > - if (crtc_state->c8_planes &&
> > - !crtc_state_is_legacy_gamma(crtc_state))
> > - return -EINVAL;
> > + ret = check_luts(crtc_state);
> > + if (ret)
> > + return ret;
> >
> > crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > !crtc_state->c8_planes;
> > @@ -828,25 +852,10 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > if (IS_CHERRYVIEW(dev_priv))
> > crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> >
> > - /* Always allow legacy gamma LUT with no further checking. */
> > if (!crtc_state->gamma_enable ||
> > - crtc_state_is_legacy_gamma(crtc_state)) {
> > + crtc_state_is_legacy_gamma(crtc_state))
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > - if (INTEL_GEN(dev_priv) >= 11 &&
> > - crtc_state->gamma_enable)
> > - crtc_state->gamma_mode |= POST_CSC_GAMMA_ENABLE;
> > - return 0;
> > - }
> > -
> > - if (check_lut_size(degamma_lut, degamma_length) ||
> > - check_lut_size(gamma_lut, gamma_length))
> > - return -EINVAL;
> > -
> > - if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > - drm_color_lut_check(gamma_lut, gamma_tests))
> > - return -EINVAL;
> > -
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + else if (INTEL_GEN(dev_priv) >= 11)
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT |
> > PRE_CSC_GAMMA_ENABLE |
> > POST_CSC_GAMMA_ENABLE;
>
> Should we drop the GAMMA_ENABLE here and just rely on the new check
> you're adding below to handle it?
This will get rewritten entirely in following patches, s
Re: [Intel-gfx] [PATCH 04/10] drm/i915: Extract chv_color_check()
On Tue, Mar 19, 2019 at 03:00:26PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:11PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Since CHV has the CGM unit we require a custom implementation
> > of .color_check().
> >
> > This fixes the computation of gamma_enable as previously we
> > left it enabled even when were using the CGM gamma instead.
> > Now we turn off the legacy LUT unless it's actually required.
>
> The CGM stuff is a bit non-obvious to anyone who hasn't focused on the
> CHV platform specifically, so it might be worth adding this
> justification in a code comment.
>
> In fact, a general overview comment somewhere (maybe on the CHV_COLORS
> definition?) about the difference between legacy gamma and CGM might be
> helpful. It looks like our public PRM's for CHV don't really cover
> anything display-wise.
Yeah. I think I had a patch somewhere where I document the full
pipeline for VLV/CHV. I'll see if I can dig it out.
>
> Anyway, the code change looks correct, so
>
> Reviewed-by: Matt Roper
>
>
> Matt
>
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_color.c | 28
> > 1 file changed, 24 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index 3d19b1a7ee95..cb88651f1da4 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -848,6 +848,29 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
> > *crtc_state)
> > return cgm_mode;
> > }
> >
> > +static int chv_color_check(struct intel_crtc_state *crtc_state)
> > +{
> > + int ret;
> > +
> > + ret = check_luts(crtc_state);
> > + if (ret)
> > + return ret;
> > +
> > + crtc_state->gamma_enable =
> > + crtc_state_is_legacy_gamma(crtc_state) &&
> > + !crtc_state->c8_planes;
> > +
> > + crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > +
> > + crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> > +
> > + ret = intel_color_add_affected_planes(crtc_state);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > static int _intel_color_check(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > @@ -877,9 +900,6 @@ static int _intel_color_check(struct intel_crtc_state
> > *crtc_state)
> >
> > crtc_state->csc_mode = 0;
> >
> > - if (IS_CHERRYVIEW(dev_priv))
> > - crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> > -
> > if (!crtc_state->gamma_enable ||
> > crtc_state_is_legacy_gamma(crtc_state))
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > @@ -917,7 +937,7 @@ void intel_color_init(struct intel_crtc *crtc)
> >
> > if (HAS_GMCH(dev_priv)) {
> > if (IS_CHERRYVIEW(dev_priv)) {
> > - dev_priv->display.color_check = _intel_color_check;
> > + dev_priv->display.color_check = chv_color_check;
> > dev_priv->display.color_commit = i9xx_color_commit;
> > dev_priv->display.load_luts = cherryview_load_luts;
> > } else {
> > --
> > 2.19.2
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 01/10] drm/i915: Extract check_luts()
On Tue, Mar 19, 2019 at 06:24:47PM +0200, Jani Nikula wrote:
> On Mon, 18 Mar 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_color.c | 68 ++
> > 1 file changed, 40 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > b/drivers/gpu/drm/i915/intel_color.c
> > index 467fd1a1630c..b6a992a5b14f 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -771,6 +771,38 @@ static int check_lut_size(const struct
> > drm_property_blob *lut, int expected)
> > return 0;
> > }
> >
> > +static int check_luts(const struct intel_crtc_state *crtc_state)
>
> luts_check() to be more in line with other _commit and _check functions?
Shrug. For some reason check_luts() feels more natural to me.
>
> BR,
> Jani.
>
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > + const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > + int gamma_length, degamma_length;
> > + u32 gamma_tests, degamma_tests;
> > +
> > + /* Always allow legacy gamma LUT with no further checking. */
> > + if (crtc_state_is_legacy_gamma(crtc_state))
> > + return 0;
> > +
> > + /* C8 needs the legacy LUT all to itself */
> > + if (crtc_state->c8_planes)
> > + return -EINVAL;
> > +
> > + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > + degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > + gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > +
> > + if (check_lut_size(degamma_lut, degamma_length) ||
> > + check_lut_size(gamma_lut, gamma_length))
> > + return -EINVAL;
> > +
> > + if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > + drm_color_lut_check(gamma_lut, gamma_tests))
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> > {
> > u32 cgm_mode = 0;
> > @@ -794,19 +826,11 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > const struct drm_property_blob *degamma_lut =
> > crtc_state->base.degamma_lut;
> > bool limited_color_range = false;
> > - int gamma_length, degamma_length;
> > - u32 gamma_tests, degamma_tests;
> > int ret;
> >
> > - degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > - gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > - degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > - gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > -
> > - /* C8 needs the legacy LUT all to itself */
> > - if (crtc_state->c8_planes &&
> > - !crtc_state_is_legacy_gamma(crtc_state))
> > - return -EINVAL;
> > + ret = check_luts(crtc_state);
> > + if (ret)
> > + return ret;
> >
> > crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > !crtc_state->c8_planes;
> > @@ -828,25 +852,10 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > if (IS_CHERRYVIEW(dev_priv))
> > crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> >
> > - /* Always allow legacy gamma LUT with no further checking. */
> > if (!crtc_state->gamma_enable ||
> > - crtc_state_is_legacy_gamma(crtc_state)) {
> > + crtc_state_is_legacy_gamma(crtc_state))
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > - if (INTEL_GEN(dev_priv) >= 11 &&
> > - crtc_state->gamma_enable)
> > - crtc_state->gamma_mode |= POST_CSC_GAMMA_ENABLE;
> > - return 0;
> > - }
> > -
> > - if (check_lut_size(degamma_lut, degamma_length) ||
> > - check_lut_size(gamma_lut, gamma_length))
> > - return -EINVAL;
> > -
> > - if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > - drm_color_lut_check(gamma_lut, gamma_tests))
> > - return -EINVAL;
> > -
> > - if (INTEL_GEN(dev_priv) >= 11)
> > + else if (INTEL_GEN(dev_priv) >= 11)
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT |
> > PRE_CSC_GAMMA_ENABLE |
> > POST_CSC_GAMMA_ENABLE;
> > @@ -858,6 +867,9 @@ int intel_color_check(struct intel_crtc_state
> > *crtc_state)
> > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> >
> > if (INTEL_GEN(dev_priv) >= 11) {
> > + if (crtc_state->gamma_enable)
> > + crtc_state->gamma_mode |=
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t v5 1/6] lib/igt_kms: Add writeback support
On Mon, Mar 18, 2019 at 07:05:29PM -0300, Rodrigo Siqueira wrote:
> On 03/18, Liviu Dudau wrote:
> > On Wed, Mar 06, 2019 at 06:30:05PM -0300, Rodrigo Siqueira wrote:
> > > Hi Liviu,
> > >
> > > I’m using your patchset to guide my implementation of writeback in the
> > > VKMS, so, first of all, thanks :)
> > >
> > > During my work, I noticed that you’re setting the drmSetClientCap()
> > > before drmModeGetResources() which make the writeback capability
> >
> > before? I believe your patchset moves it to be before, which makes
> > sense, as the writeback applies to connectors, not planes (sorry for the
> > confusion, I think I wrote the code when we were toying with the idea
> > that writeback was going to be a plane property).
> >
> > > ‘invisible’ for drmModeGetResources(). I made the following change, and
> > > I could pass the igt_display_require():
> > >
> > > diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> > > index f4ff3a96..bb2d8e06 100644
> > > --- a/lib/igt_kms.c
> > > +++ b/lib/igt_kms.c
> > > @@ -1912,6 +1912,12 @@ void igt_display_require(igt_display_t *display,
> > > int drm_fd)
> > >
> > > display->drm_fd = drm_fd;
> > >
> > > + drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
> > > + if (drmSetClientCap(drm_fd, DRM_CLIENT_CAP_ATOMIC, 1) == 0)
> > > + display->is_atomic = 1;
> > > +
> > > + drmSetClientCap(drm_fd, DRM_CLIENT_CAP_WRITEBACK_CONNECTORS, 1);
> > > +
> > > resources = drmModeGetResources(display->drm_fd);
> > > if (!resources)
> > > goto out;
> > > @@ -1924,12 +1930,6 @@ void igt_display_require(igt_display_t *display,
> > > int drm_fd)
> > > display->pipes = calloc(sizeof(igt_pipe_t), display->n_pipes);
> > > igt_assert_f(display->pipes, "Failed to allocate memory for %d
> > > pipes\n", display->n_pipes);
> > >
> > > - drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
> > > - if (drmSetClientCap(drm_fd, DRM_CLIENT_CAP_ATOMIC, 1) == 0)
> > > - display->is_atomic = 1;
> > > -
> > > - drmSetClientCap(drm_fd, DRM_CLIENT_CAP_WRITEBACK_CONNECTORS, 1);
> > > -
> > > plane_resources = drmModeGetPlaneResources(display->drm_fd);
> > > igt_assert(plane_resources);
> > >
> > > I'm not 100% confident about this issue, because of this I will send an
> > > RFC and see if I can get more details about this issue.
> >
> > It actually looks correct to me, so
> >
> > Acked-by: Liviu Dudau
> >
> > >
> > > Additionally, if you need any help with this patchset I will be glad to
> > > help since I’m using it \o/
> >
> > Well, I need to send an updated version and if you could review that
> > then I can merge it into igt.
>
> Sure! I will be glad to take some time to review your code :)
>
> I can also try to test it on my current implementation of VKMS.
> One question, I have a NanoPc-T1 device [1] which has a Mali GPU, can I
> test the writeback feature in this device? All kind of Mali GPU has
> support for the writeback feature?
>
> 1. http://wiki.friendlyarm.com/wiki/index.php/NanoPC-T1
(sorry, email fell through the cracks)
The writeback is a Mali Display Processor feature, not GPU. As such you
need a device that has Mali DP in it. Commercially there will be a
platform later this year, but until it is announced I cannot say more
about it.
Best regards,
Liviu
>
> Thanks!
> Best Regards
>
> > Best regards,
> > Liviu
> >
> > >
> > > Best Regards
> > > Rodrigo Siqueira
> > >
> > > On 02/04, Brian Starkey wrote:
> > > > Hi Liviu,
> > > >
> > > > On Tue, Jan 15, 2019 at 05:47:42PM +, Liviu Dudau wrote:
> > > > > From: Brian Starkey
> > > >
> > > > [snip]
> > > >
> > > > >
> > > > > +/**
> > > > > + * igt_output_set_writeback_fb:
> > > > > + * @output: Target output
> > > > > + * @fb: Target framebuffer
> > > > > + *
> > > > > + * This function sets the given @fb to be used as the target
> > > > > framebuffer for the
> > > > > + * writeback engine at the next atomic commit. It will also request
> > > > > a writeback
> > > > > + * out fence that will contain the fd number of the out fence
> > > > > created by KMS if
> > > > > + * the given @fb is valid.
> > > > > + */
> > > > > +void igt_output_set_writeback_fb(igt_output_t *output, struct igt_fb
> > > > > *fb)
> > > > > +{
> > > > > + igt_display_t *display = output->display;
> > > > > +
> > > > > + LOG(display, "%s: output_set_writeback_fb(%d)\n", output->name,
> > > > > fb ? fb->fb_id : 0);
> > > > > +
> > > > > + igt_output_set_prop_value(output,
> > > > > IGT_CONNECTOR_WRITEBACK_FB_ID, fb ? fb->fb_id : 0);
> > > > > + /* only request a writeback out fence if the framebuffer is
> > > > > valid */
> > > > > + if (fb)
> > > > > + igt_output_set_prop_value(output,
> > > > > IGT_CONNECTOR_WRITEBACK_OUT_FENCE_PTR,
> > > > > +
> > > > > (ptrdiff_t)&output->writeback_out_fence_fd);
> >
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_mocs_settings/mocs-isolation: Filter out missing rings
Chris Wilson writes:
> Don't try to evaluate whether reads executed on an absent ring do
> anything.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_mocs_settings.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
> index 21f7c6e12..1a311b8c0 100644
> --- a/tests/i915/gem_mocs_settings.c
> +++ b/tests/i915/gem_mocs_settings.c
> @@ -564,8 +564,8 @@ igt_main
> }
> }
>
> - igt_subtest_f("mocs-isolation-%s",
> - e->name) {
> + igt_subtest_f("mocs-isolation-%s", e->name) {
> + gem_require_ring(fd, e->exec_id | e->flags);
> gem_require_contexts(fd);
>
> isolation_test(fd, e->exec_id | e->flags);
> --
> 2.20.1
>
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: always use masks on FW regs
== Series Details == Series: drm/i915: always use masks on FW regs URL : https://patchwork.freedesktop.org/series/58246/ State : success == Summary == CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12530 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/58246/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12530 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_basic@basic-bsd2: - fi-kbl-7500u: NOTRUN -> SKIP [fdo#109271] +9 * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: NOTRUN -> DMESG-WARN [fdo#103841] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_psr@primary_mmap_gtt: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27 * igt@runner@aborted: - fi-kbl-7500u: NOTRUN -> FAIL [fdo#103841] - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@i915_selftest@live_uncore: - fi-ivb-3770:DMESG-FAIL [fdo#110210] -> PASS * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS Warnings * igt@i915_selftest@live_contexts: - fi-icl-u3: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569] [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103841]: https://bugs.freedesktop.org/show_bug.cgi?id=103841 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 [fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Participating hosts (48 -> 43) -- Additional (1): fi-kbl-7500u Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 Build changes - * Linux: CI_DRM_5780 -> Patchwork_12530 CI_DRM_5780: 774f8c588542dda6d73161429cbf1e027789d6ef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4892: 8ae86621d6fff60b6e20c6b0f9b336785c935b0f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12530: 0d8f0cf4abf2ab79b966775f1e62b00bf0e4098b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0d8f0cf4abf2 drm/i915: always use masks on FW regs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12530/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_mmap_gtt: Check that the initial pagefault is non-blocking
On Mon, 18 Mar 2019 at 08:58, Chris Wilson wrote: > > Signed-off-by: Chris Wilson Should do the trick, Reviewed-by: Matthew Auld ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm/i915: Extract check_luts()
On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > In prepartion for per-platform color_check() functions extract the
> > > common code into a separate function.
> > >
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/intel_color.c | 68 ++
> > > 1 file changed, 40 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > > b/drivers/gpu/drm/i915/intel_color.c
> > > index 467fd1a1630c..b6a992a5b14f 100644
> > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > @@ -771,6 +771,38 @@ static int check_lut_size(const struct
> > > drm_property_blob *lut, int expected)
> > > return 0;
> > > }
> > >
> > > +static int check_luts(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> > > + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > > + const struct drm_property_blob *degamma_lut =
> > > crtc_state->base.degamma_lut;
> > > + int gamma_length, degamma_length;
> > > + u32 gamma_tests, degamma_tests;
> > > +
> > > + /* Always allow legacy gamma LUT with no further checking. */
> > > + if (crtc_state_is_legacy_gamma(crtc_state))
> > > + return 0;
> > > +
> > > + /* C8 needs the legacy LUT all to itself */
> > > + if (crtc_state->c8_planes)
> > > + return -EINVAL;
> >
> > Do we need to test for non-NULL gamma_lut here?
>
> For c8? We already checked crtc_state_is_legacy_gamma() above.
>
If gamma_lut == NULL, crtc_state_is_legacy_gamma() will return false, so
we'll wind up rejecting any setup involving c8 planes with -EINVAL,
which I don't think is what we wanted.
Matt
> >
> > The logic is the same as before your patch, so either we already had a
> > pre-existing bug or, more likely, I'm overlooking something obvious.
> >
> > > +
> > > + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > > + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > > + degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > > + gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > > +
> > > + if (check_lut_size(degamma_lut, degamma_length) ||
> > > + check_lut_size(gamma_lut, gamma_length))
> > > + return -EINVAL;
> > > +
> > > + if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > > + drm_color_lut_check(gamma_lut, gamma_tests))
> > > + return -EINVAL;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> > > {
> > > u32 cgm_mode = 0;
> > > @@ -794,19 +826,11 @@ int intel_color_check(struct intel_crtc_state
> > > *crtc_state)
> > > const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
> > > const struct drm_property_blob *degamma_lut =
> > > crtc_state->base.degamma_lut;
> > > bool limited_color_range = false;
> > > - int gamma_length, degamma_length;
> > > - u32 gamma_tests, degamma_tests;
> > > int ret;
> > >
> > > - degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > > - gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > > - degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > > - gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > > -
> > > - /* C8 needs the legacy LUT all to itself */
> > > - if (crtc_state->c8_planes &&
> > > - !crtc_state_is_legacy_gamma(crtc_state))
> > > - return -EINVAL;
> > > + ret = check_luts(crtc_state);
> > > + if (ret)
> > > + return ret;
> > >
> > > crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > > !crtc_state->c8_planes;
> > > @@ -828,25 +852,10 @@ int intel_color_check(struct intel_crtc_state
> > > *crtc_state)
> > > if (IS_CHERRYVIEW(dev_priv))
> > > crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> > >
> > > - /* Always allow legacy gamma LUT with no further checking. */
> > > if (!crtc_state->gamma_enable ||
> > > - crtc_state_is_legacy_gamma(crtc_state)) {
> > > + crtc_state_is_legacy_gamma(crtc_state))
> > > crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > > - if (INTEL_GEN(dev_priv) >= 11 &&
> > > - crtc_state->gamma_enable)
> > > - crtc_state->gamma_mode |= POST_CSC_GAMMA_ENABLE;
> > > - return 0;
> > > - }
> > > -
> > > - if (check_lut_size(degamma_lut, degamma_length) ||
> > > - check_lut_size(gamma_lut, gamma_length))
> > > - return -EINVAL;
> > > -
> > > - if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > > - drm_color_lut_check(gamma_lut, gamma_tests))
> > > - return -EINVAL;
> > > -
> > > - if (INTEL_GEN(dev_priv) >= 11)
> > > + else if (INTEL_GEN(dev_priv) >=
Re: [Intel-gfx] [PATCH 7/9] drm/i915: Move some variables to tighter scope
On Mon, Mar 18, 2019 at 05:10:49PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:42PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Clean up skl_allocate_pipe_ddb() a bit by moving the 'wm' variable
> > to tighter scope. We'll also consitify it where appropriate.
> >
> > Cc: Neel Desai
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 23 +--
> > 1 file changed, 13 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8afbc56ad89a..b958a1a00014 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4336,7 +4336,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> > - struct skl_plane_wm *wm;
> > u16 alloc_size, start = 0;
> > u16 total[I915_MAX_PLANES] = {};
> > u16 uv_total[I915_MAX_PLANES] = {};
> > @@ -4393,7 +4392,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> > blocks = 0;
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + const struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> >
> > if (plane_id == PLANE_CURSOR) {
> > if (WARN_ON(wm->wm[level].min_ddb_alloc >
> > @@ -4427,6 +4427,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > * proportional to its relative data rate.
> > */
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > + const struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> > u64 rate;
> > u16 extra;
> >
> > @@ -4440,8 +4442,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > if (total_data_rate == 0)
> > break;
> >
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > -
> > rate = plane_data_rate[plane_id];
> > extra = min_t(u16, alloc_size,
> > DIV64_U64_ROUND_UP(alloc_size * rate,
> > @@ -4466,14 +4466,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> > /* Set the actual DDB start/end points for each plane */
> > start = alloc->start;
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - struct skl_ddb_entry *plane_alloc, *uv_plane_alloc;
> > + struct skl_ddb_entry *plane_alloc =
> > + &cstate->wm.skl.plane_ddb_y[plane_id];
> > + struct skl_ddb_entry *uv_plane_alloc =
> > + &cstate->wm.skl.plane_ddb_uv[plane_id];
> >
> > if (plane_id == PLANE_CURSOR)
> > continue;
> >
> > - plane_alloc = &cstate->wm.skl.plane_ddb_y[plane_id];
> > - uv_plane_alloc = &cstate->wm.skl.plane_ddb_uv[plane_id];
> > -
> > /* Gen11+ uses a separate plane for UV watermarks */
> > WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
> >
>
> This hunk is fine, but isn't what's described in the commit message.
> Maybe throw an extra sentence in there referencing this change?
Amended the commit message a bit, and fixed up the update vs. build
typo in the commit message of the other patch.
Series pushed to dinq. Thanks for the review.
>
> Aside from that,
>
> Reviewed-by: Matt Roper
>
> > @@ -4499,7 +4499,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > */
> > for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> >
> > /*
> > * We only disable the watermarks for each plane if
> > @@ -4535,7 +4536,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> > * don't have enough DDB blocks for it.
> > */
> > for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > - wm = &cstate->wm.skl.optimal.planes[plane_id];
> > + struct skl_plane_wm *wm =
> > + &cstate->wm.skl.optimal.planes[plane_id];
> > +
> > if (wm->trans_wm.plane_res_b >= total[plane_id])
> > memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
> > }
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/
Re: [Intel-gfx] [PATCH 5/6] drm/i915: Use HPLLVCO_MOBILE for all PNVs
On Tue, Mar 19, 2019 at 01:29:58PM +, Tvrtko Ursulin wrote: > > On 18/03/2019 16:56, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > To allow unsetting .is_mobile for the desktop variant > > of PNV fix up the cdclk code to select the mobile HPLLVCO register > > for both PNV variants. > > > > Cc: Tvrtko Ursulin > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_cdclk.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > b/drivers/gpu/drm/i915/intel_cdclk.c > > index 21fb4e0d6c4e..d27ccd23d753 100644 > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > @@ -234,7 +234,8 @@ static unsigned int intel_hpll_vco(struct > > drm_i915_private *dev_priv) > > else > > return 0; > > > > - tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); > > + tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? > > + HPLLVCO_MOBILE : HPLLVCO); > > > > vco = vco_table[tmp & 0x7]; > > if (vco == 0) > > > > Reviewed-by: Tvrtko Ursulin Pushed up to this one. Thanks for the review. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm/i915: Extract check_luts()
On Wed, Mar 20, 2019 at 08:14:56AM -0700, Matt Roper wrote:
> On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > In prepartion for per-platform color_check() functions extract the
> > > > common code into a separate function.
> > > >
> > > > Signed-off-by: Ville Syrjälä
> > > > ---
> > > > drivers/gpu/drm/i915/intel_color.c | 68 ++
> > > > 1 file changed, 40 insertions(+), 28 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_color.c
> > > > b/drivers/gpu/drm/i915/intel_color.c
> > > > index 467fd1a1630c..b6a992a5b14f 100644
> > > > --- a/drivers/gpu/drm/i915/intel_color.c
> > > > +++ b/drivers/gpu/drm/i915/intel_color.c
> > > > @@ -771,6 +771,38 @@ static int check_lut_size(const struct
> > > > drm_property_blob *lut, int expected)
> > > > return 0;
> > > > }
> > > >
> > > > +static int check_luts(const struct intel_crtc_state *crtc_state)
> > > > +{
> > > > + struct drm_i915_private *dev_priv =
> > > > to_i915(crtc_state->base.crtc->dev);
> > > > + const struct drm_property_blob *gamma_lut =
> > > > crtc_state->base.gamma_lut;
> > > > + const struct drm_property_blob *degamma_lut =
> > > > crtc_state->base.degamma_lut;
> > > > + int gamma_length, degamma_length;
> > > > + u32 gamma_tests, degamma_tests;
> > > > +
> > > > + /* Always allow legacy gamma LUT with no further checking. */
> > > > + if (crtc_state_is_legacy_gamma(crtc_state))
> > > > + return 0;
> > > > +
> > > > + /* C8 needs the legacy LUT all to itself */
> > > > + if (crtc_state->c8_planes)
> > > > + return -EINVAL;
> > >
> > > Do we need to test for non-NULL gamma_lut here?
> >
> > For c8? We already checked crtc_state_is_legacy_gamma() above.
> >
>
> If gamma_lut == NULL, crtc_state_is_legacy_gamma() will return false, so
> we'll wind up rejecting any setup involving c8 planes with -EINVAL,
> which I don't think is what we wanted.
I think it is. c8 scanout always uses the legacy LUT, so it had
better be populated with the correct data or else we'll risk
producing garbage on the display.
>
>
> Matt
>
>
> > >
> > > The logic is the same as before your patch, so either we already had a
> > > pre-existing bug or, more likely, I'm overlooking something obvious.
> > >
> > > > +
> > > > + degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > > > + gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > > > + degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > > > + gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > > > +
> > > > + if (check_lut_size(degamma_lut, degamma_length) ||
> > > > + check_lut_size(gamma_lut, gamma_length))
> > > > + return -EINVAL;
> > > > +
> > > > + if (drm_color_lut_check(degamma_lut, degamma_tests) ||
> > > > + drm_color_lut_check(gamma_lut, gamma_tests))
> > > > + return -EINVAL;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
> > > > {
> > > > u32 cgm_mode = 0;
> > > > @@ -794,19 +826,11 @@ int intel_color_check(struct intel_crtc_state
> > > > *crtc_state)
> > > > const struct drm_property_blob *gamma_lut =
> > > > crtc_state->base.gamma_lut;
> > > > const struct drm_property_blob *degamma_lut =
> > > > crtc_state->base.degamma_lut;
> > > > bool limited_color_range = false;
> > > > - int gamma_length, degamma_length;
> > > > - u32 gamma_tests, degamma_tests;
> > > > int ret;
> > > >
> > > > - degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > > > - gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> > > > - degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
> > > > - gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
> > > > -
> > > > - /* C8 needs the legacy LUT all to itself */
> > > > - if (crtc_state->c8_planes &&
> > > > - !crtc_state_is_legacy_gamma(crtc_state))
> > > > - return -EINVAL;
> > > > + ret = check_luts(crtc_state);
> > > > + if (ret)
> > > > + return ret;
> > > >
> > > > crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&
> > > > !crtc_state->c8_planes;
> > > > @@ -828,25 +852,10 @@ int intel_color_check(struct intel_crtc_state
> > > > *crtc_state)
> > > > if (IS_CHERRYVIEW(dev_priv))
> > > > crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> > > >
> > > > - /* Always allow legacy gamma LUT with no further checking. */
> > > > if (!crtc_state->gamma_enable ||
> > > > - crt
[Intel-gfx] [PATCH] drm/i915: Use __is_constexpr()
gcc-4.8 and older dislike the use of __builtin_constant_p() within a
constant expression context, and so we must use the magical
__is_constexpr() instead.
For example, with gcc-4.8.5:
../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argument to
‘__builtin_choose_expr’ not a constant
../include/linux/build_bug.h:16:45: error: bit-field ‘’ width not an
integer constant
Reported-by: Randy Dunlap
Fixes: baa09e7d2f42 ("drm/i915: use REG_FIELD_PREP() to define register
bitfield values")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc: Imre Deak
Cc: Randy Dunlap
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 85e8d1a1f70b..50d0b2ae89eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -161,10 +161,10 @@
*/
#define REG_FIELD_PREP(__mask, __val)
\
((u32)typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +
\
- BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) +
\
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +
\
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
__bf_shf(__mask + \
-
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(__val),
(~((__mask) >> __bf_shf(__mask)) & (__val)), 0
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
(~((__mask) >> __bf_shf(__mask)) & (__val)), 0
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote: > There has unfortunately been a conflict with the following 3 commits: > > commit e9961ab95af81b8d29054361cd5f0c575102cf87 > Author: Ayan Kumar Halder > Date: Fri Nov 9 17:21:12 2018 + > drm: Added a new format DRM_FORMAT_XVYU2101010 > > commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3 > Author: Brian Starkey > Date: Fri Oct 5 10:27:00 2018 +0100 > > drm/fourcc: Add AFBC yuv fourccs for Mali > > and > > commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b > Author: Swati Sharma > Date: Mon Mar 4 17:26:33 2019 +0530 > > drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc > > Unfortunately gcc didn't warn about the redefinitions, because the > ... sentence got cut off here. - ajax ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Don't check uv_wm in skl_plane_wm_equals()
From: Ville Syrjälä
The hardware never sees the uv_wm values (apart from
uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
is no point in comparing uv_wm to determine if we need to
reprogram the watermark registers. So let's check only the
rgb/y watermark in skl_plane_wm_equals(). But let's leave
a comment behind so that the next person reading this doesn't
get as confused as I did when I added this check.
If the ddb allocation ends up changing due to uv_wm
skl_ddb_add_affected_planes() takes care of adding the plane
to the state.
TODO: we should perhaps just eliminate uv_wm from the state
and simply track the min_ddb_alloc for uv instead.
Cc: Matt Roper
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53e9304c66ab..7debbb0c0ab6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5219,8 +5219,12 @@ static bool skl_plane_wm_equals(struct drm_i915_private
*dev_priv,
int level, max_level = ilk_wm_max_level(dev_priv);
for (level = 0; level <= max_level; level++) {
- if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) ||
- !skl_wm_level_equals(&wm1->uv_wm[level],
&wm2->uv_wm[level]))
+ /*
+* We don't check uv_wm as the hardware doesn't actually
+* use it. It only gets used for calculating the required
+* ddb allocation.
+*/
+ if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
return false;
}
--
2.19.2
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Re: [Intel-gfx] [PATCH 15/18] drm/i915: Load balancing across a virtual engine
On 19/03/2019 11:57, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
sseu: Lift the restriction to allow sseu to be reconfigured on virtual
engines composed of RENDER_CLASS (rcs).
v2: macroize check_user_mbz()
v3: Cancel virtual engines on wedging
v4: Commence commenting
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.h| 5 +
drivers/gpu/drm/i915/i915_gem_context.c| 126 -
drivers/gpu/drm/i915/i915_scheduler.c | 18 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
drivers/gpu/drm/i915/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/intel_lrc.c | 567 -
drivers/gpu/drm/i915/intel_lrc.h | 11 +
drivers/gpu/drm/i915/selftests/intel_lrc.c | 165 ++
include/uapi/drm/i915_drm.h| 30 ++
9 files changed, 912 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 5c073fe73664..3ca855505715 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -96,4 +96,9 @@ static inline bool __tasklet_enable(struct tasklet_struct *t)
return atomic_dec_and_test(&t->count);
}
+static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
+{
+ return test_bit(TASKLET_STATE_SCHED, &t->state);
+}
+
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index cbd76ef95115..8d8fcc8c7a86 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -86,6 +86,7 @@
*/
#include
+#include
#include
@@ -94,6 +95,7 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
+#include "intel_lrc.h"
#include "intel_workarounds.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -241,6 +243,20 @@ static void release_hw_id(struct i915_gem_context *ctx)
mutex_unlock(&i915->contexts.mutex);
}
+static void free_engines(struct intel_engine_cs **engines, int count)
+{
+ int i;
+
+ if (ZERO_OR_NULL_PTR(engines))
+ return;
+
+ /* We own the veng we created; regular engines are ignored */
+ for (i = 0; i < count; i++)
+ intel_virtual_engine_destroy(engines[i]);
+
+ kfree(engines);
+}
+
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
struct intel_context *it, *n;
@@ -25
Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
Op 20-03-2019 om 16:48 schreef Adam Jackson: > On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote: >> There has unfortunately been a conflict with the following 3 commits: >> >> commit e9961ab95af81b8d29054361cd5f0c575102cf87 >> Author: Ayan Kumar Halder >> Date: Fri Nov 9 17:21:12 2018 + >> drm: Added a new format DRM_FORMAT_XVYU2101010 >> >> commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3 >> Author: Brian Starkey >> Date: Fri Oct 5 10:27:00 2018 +0100 >> >> drm/fourcc: Add AFBC yuv fourccs for Mali >> >> and >> >> commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b >> Author: Swati Sharma >> Date: Mon Mar 4 17:26:33 2019 +0530 >> >> drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc >> >> Unfortunately gcc didn't warn about the redefinitions, because the >> > ... sentence got cut off here. > > - ajax > ... double defines were the set to same value, and gcc apparently no longer warns about that. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t] i915/gem_shrink: Open the device before using it!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
igt_device")
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
---
tests/i915/gem_shrink.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
index 73b6be725..51d1343ba 100644
--- a/tests/i915/gem_shrink.c
+++ b/tests/i915/gem_shrink.c
@@ -403,7 +403,12 @@ igt_main
unsigned int engine;
int fd;
- /* Spawn enough processes to use all memory, but each only
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+
+
+ /*
+* Spawn enough processes to use all memory, but each only
* uses half the available mappable aperture ~128MiB.
* Individually the processes would be ok, but en masse
* we expect the shrinker to start purging objects,
@@ -418,9 +423,6 @@ igt_main
intel_require_memory(num_processes, alloc_size,
CHECK_SWAP | CHECK_RAM);
- fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
-
nengine = 0;
for_each_engine(fd, engine)
engines[nengine++] = engine;
--
2.20.1
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Re: [Intel-gfx] [PATCH] drm/i915: Use __is_constexpr()
On 3/20/19 8:40 AM, Chris Wilson wrote:
> gcc-4.8 and older dislike the use of __builtin_constant_p() within a
> constant expression context, and so we must use the magical
> __is_constexpr() instead.
>
> For example, with gcc-4.8.5:
> ../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argument to
> ‘__builtin_choose_expr’ not a constant
> ../include/linux/build_bug.h:16:45: error: bit-field ‘’ width not
> an integer constant
>
> Reported-by: Randy Dunlap
> Fixes: baa09e7d2f42 ("drm/i915: use REG_FIELD_PREP() to define register
> bitfield values")
> Signed-off-by: Chris Wilson
> Cc: Jani Nikula
> Cc: Imre Deak
> Cc: Randy Dunlap
Acked-by: Randy Dunlap # build-tested
Thanks.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85e8d1a1f70b..50d0b2ae89eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -161,10 +161,10 @@
> */
> #define REG_FIELD_PREP(__mask, __val)
> \
> ((u32)typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) +
> \
> -BUILD_BUG_ON_ZERO(!__builtin_constant_p(__mask)) +
> \
> +BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +
> \
> BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask + \
> -
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__builtin_constant_p(__val),
> (~((__mask) >> __bf_shf(__mask)) & (__val)), 0
> +BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> (~((__mask) >> __bf_shf(__mask)) & (__val)), 0
>
> /**
> * REG_FIELD_GET() - Extract a u32 bitfield value
>
--
~Randy
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Re: [Intel-gfx] Potential NULL pointer dereference in intel_crt_get_edid
Thank you very much for your reply. Do you mean if I track the argument to the
callers, I should be able to figure out that the pin is always valid? I think I
have two questions for this approach. First, does it mean that the branch
returning NULL is practically dead code? Second, the driver code, as it appears
to me, does not have well-defined entry points like the main function. So if I
manage to track the arguments to a function whose caller is not explicit (e.g.,
it's address is taken in a structure), should I still assume that the pin is
valid when this function is used?
Thanks,
Shaobo
On 2019/3/19 2:32, Jani Nikula wrote:
On Mon, 18 Mar 2019, Shaobo He wrote:
I see. In light of this commit, is it a better solution than adding NULL-checks
is to replace the if branch conditioned by `WARN_ON` with simply `WARN` like the
following,
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
unsigned int pin)
{
WARN(!intel_gmbus_is_valid_pin(dev_priv, pin), "Invalid pin: %d\n",
pin);
return &dev_priv->gmbus[pin].adapter;
}
So all of this discussion is hypothetical in the sense that it really
should never happen. You can track down the args passed to
intel_gmbus_get_adapter(), while the static analyzer is unable to do
that.
BR,
Jani.
Shaobo
On 3/18/19 5:53 PM, Rodrigo Vivi wrote:
On Mon, Mar 18, 2019 at 05:39:48PM -0600, Shaobo He wrote:
Hi Rodrigo,
Sorry I'm a bit lost here. May I ask where the `WARN` is?
along with the return NULL
struct i2c_adapter *intel_gmbus_get_adapte()
if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
return NULL;
Thanks,
Shaobo
On 3/18/19 5:26 PM, Rodrigo Vivi wrote:
Hi Shaobo,
n Mon, Mar 18, 2019 at 05:01:10PM -0600, Shaobo He wrote:
Hello everyone,
My name is Shaobo He and I am a graduate student at University of Utah. I am
using a static analysis tool to search for null pointer dereferences and
came across a potentially invalid memory access in the file
drivers/gpu/drm/i915/intel_crt.c: in function `intel_crt_detect_ddc`,
function `intel_gmbus_get_adapter` can return a NULL pointer which is
if this happens we've done a terrible job on defining the platform...
dereferenced by the call to `drm_get_edid` or `intel_gmbus_is_forced_bit`.
but it seems you are right... this will reach i2c_transfer in the end
and it will break everything after we gave the Warning...
It seems that the return value of `intel_gmbus_get_adapter` is never
NULL-checked. If so, it would be better to replace the branch to return a
NULL pointer with something like `BUG_ON`.
what about just adding if (!i2c) return false
instead of BUG.
We already have the WARN to debug if this case ever happens.
Thanks,
Rodrigo.
Please let me know if it makes sense. I am looking forward to your reply.
Best,
Shaobo
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
== Series Details == Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled URL : https://patchwork.freedesktop.org/series/58273/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled -O:drivers/gpu/drm/i915/intel_cdclk.c:2204:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2193:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2245:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2245:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2234:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2234:29: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3559:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3562:16: warning: expression using sizeof(void) Commit: drm/i915: Save the old CDCLK atomic state Okay! Commit: drm/i915: Remove redundant store of logical CDCLK state Okay! Commit: drm/i915: Skip modeset for cdclk changes if possible -drivers/gpu/drm/i915/selftests/../i915_drv.h:3562:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3563:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
>-Original Message-
>From: Syrjala, Ville
>Sent: Tuesday, March 19, 2019 10:29 PM
>To: Lankhorst, Maarten
>Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>Sharma, Shashank ; Roper, Matthew D
>
>Subject: Re: [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
>
>On Tue, Mar 19, 2019 at 10:46:27AM +0200, Lankhorst, Maarten wrote:
>> tis 2019-03-19 klockan 14:00 +0530 skrev Uma Shankar:
>> > Multi Segment Gamma Mode is added in Gen11+ platforms.
>> > Added a property interface to enable that.
>> >
>> > Signed-off-by: Uma Shankar
>> > ---
>> > drivers/gpu/drm/i915/i915_drv.h| 1 +
>> > drivers/gpu/drm/i915/intel_color.c | 23 +++
>> > include/uapi/drm/i915_drm.h| 14 ++
>> > 3 files changed, 38 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> > b/drivers/gpu/drm/i915/i915_drv.h index 02231ae..f20d418 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -1736,6 +1736,7 @@ struct drm_i915_private {
>> >struct drm_property *force_audio_property;
>> >
>> >struct drm_property *gamma_mode_property;
>> > + struct drm_property *multi_segment_gamma_mode_property;
>>
>> Seems to me both properties should be part of drm core?
Sure Maarten, we can move gamma_mode property to drm.
>>
>> >/* hda/i915 audio component */
>> >struct i915_audio_component *audio_component; diff --git
>> > a/drivers/gpu/drm/i915/intel_color.c
>> > b/drivers/gpu/drm/i915/intel_color.c
>> > index 9d43d19..399d63d 100644
>> > --- a/drivers/gpu/drm/i915/intel_color.c
>> > +++ b/drivers/gpu/drm/i915/intel_color.c
>> > @@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const
>> > struct intel_crtc_state *crtc_state
>> >drm_object_attach_property(&crtc->base.base, prop, 0); }
>> >
>> > +void
>> > +intel_attach_multi_segment_gamma_mode_property(struct intel_crtc
>> > *crtc)
>> > +{
>> > + struct drm_device *dev = crtc->base.dev;
>> > + struct drm_i915_private *dev_priv = to_i915(dev);
>> > + struct drm_property *prop;
>> > +
>> > + prop = dev_priv->multi_segment_gamma_mode_property;
>> > + if (!prop) {
>> > + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
>> > + "Multi-segment Gamma",
>> > 0);
>> > + if (!prop)
>> > + return;
>> > +
>> > + dev_priv->multi_segment_gamma_mode_property = prop;
>> > + }
>> > +
>> > + drm_object_attach_property(&crtc->base.base, prop, 0); }
>> > +
>> > /*
>> > * When using limited range, multiply the matrix given by userspace
>> > by
>> > * the matrix that we would use for the limited range.
>> > @@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc)
>> > INTEL_INFO(dev_priv)-
>> > >color.gamma_lut_size);
>> >
>> >intel_attach_gamma_mode_property(crtc);
>> > +
>> > + if (INTEL_GEN(dev_priv) >= 11)
>> > + intel_attach_multi_segment_gamma_mode_property(crtc)
>> > ;
>> > }
>> > diff --git a/include/uapi/drm/i915_drm.h
>> > b/include/uapi/drm/i915_drm.h index aa2d4c7..8f1974e 100644
>> > --- a/include/uapi/drm/i915_drm.h
>> > +++ b/include/uapi/drm/i915_drm.h
>> > @@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info {
>> >__u8 data[];
>> > };
>> >
>> > +/*
>> > + * Structure for muti segmented gamma lut */ struct
>> > +multi_segment_gamma_lut {
>> > + /* Number of Lut Segments */
>> > + __u8 segment_cnt;
>> > + /* Precison of LUT entries in bits */
>> > + __u8 precision_bits;
>> > + /* Pointer having number of LUT elements in each segment */
>> > + __u32 *segment_lut_cnt_ptr;
>> > + /* Pointer to store exact lut values for each segment */
>> > + __u32 *segment_lut_ptr;
>> > +};
>> >
>> And perhaps a variation of this as description for all gamma mode
>> types.
>
>This is my old idea how to represent fancier LUTs:
>https://github.com/vsyrjala/linux/commit/1aab7625dca77b831e05e32af17904c2130
>0ff95
>https://github.com/vsyrjala/linux/commit/74ffa5d441702c53830f6d71bb687bb0ae5a
>a58f
>
>Each distinct segment of the curve would be just described by a fixed size
>range
>descriptor, and the entire blob would be made up of however many of those are
>needed.
>
>That way we don't even need any multi-segment uapi for setting up the LUT. The
>blob
>for that would just contain as many entries as the LUT needs in that specific
>mode.
Hi Ville,
This also sounds good. What is your suggestion on this. Any recommendation on
how to take this
forward.
Thanks & Regards,
Uma Shankar
>--
>Ville Syrjälä
>Intel
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Use __is_constexpr()
== Series Details == Series: drm/i915: Use __is_constexpr() URL : https://patchwork.freedesktop.org/series/58278/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3ae1e5b1f498 drm/i915: Use __is_constexpr() -:38: WARNING:LONG_LINE: line over 100 characters #38: FILE: drivers/gpu/drm/i915/i915_reg.h:167: + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0 total: 0 errors, 1 warnings, 0 checks, 12 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5781 -> Patchwork_12531
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58273/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12531 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: PASS -> DMESG-WARN [fdo#105128] / [fdo#107139]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@i915_selftest@live_uncore:
- fi-ivb-3770:PASS -> DMESG-FAIL [fdo#110210]
* igt@kms_addfb_basic@addfb25-y-tiled-small:
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] +56
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-n2820: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +52
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: PASS -> FAIL [fdo#103167]
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: FAIL [fdo#103182] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
Participating hosts (43 -> 40)
--
Additional (5): fi-byt-j1900 fi-hsw-peppy fi-icl-y fi-byt-n2820 fi-bsw-kefka
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan
fi-ctg-p8600 fi-bdw-samus fi-byt-clapper fi-skl-6700k2
Build changes
-
* Linux: CI_DRM_5781 -> Patchwork_12531
CI_DRM_5781: c6c48b877f32e50dd365885c3b90b988957a8216 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4893: 27939a179fcd143e3a179ffc7b0372718259587a @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12531: da8ee225449fbb3d43e61e1490f0d0104b115e93 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
da8ee225449f drm/i915: Skip modeset for cdclk changes if possible
6a17ac210939 drm/i915: Remove redundant store of logical CDCLK state
029cba7e560c drm/i915: Save the old CDCLK atomic state
c3e1f7af4155 drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is
enabled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12531/
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Re: [Intel-gfx] [PATCH v2 1/2] drm/selftests/mm: Switch to bitmap_zalloc()
Quoting Chris Wilson (2019-03-04 09:43:43) > Quoting Andy Shevchenko (2019-03-04 09:29:07) > > Switch to bitmap_zalloc() to show clearly what we are allocating. > > Besides that it returns pointer of bitmap type instead of opaque void *. > > > > Signed-off-by: Andy Shevchenko > Reviewed-by: Chris Wilson Applied to drm-misc-next. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup
PSR2 logic is incorrectly looking at this register bit during DC5 exit.
Not a DMC problem, but DMC enables DC5.
I'll update Bspec to require the bit to be not set when PSR2 is used.
> -Original Message-
> From: Runyan, Arthur J
> Sent: Tuesday, 12 March, 2019 4:42 PM
> To: Souza, Jose ; Vivi, Rodrigo
> ; Pandiyan, Dhinakaran
>
> Cc: Aigal, Pavana A ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> PSR1 setup
>
> Strange. DMC doesn't look at training patterns. I've asked the PSR2 guys to
> look for any cross-connection.
>
> > -Original Message-
> > From: Souza, Jose
> > Sent: Tuesday, 12 March, 2019 2:29 PM
> > To: Vivi, Rodrigo ; Pandiyan, Dhinakaran
> >
> > Cc: Runyan, Arthur J ; Aigal, Pavana A
> > ; intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> > PSR1 setup
> >
> > On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > > wrote:
> > > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is kept
> > > > > set
> > > > > while PSR2 is enabled, it causes some selective updates to fail
> > > > > after
> > > > > got back from DC6 for the first time.
> > >
> > > That's suspicious, why does a PSR1 control register have any effect
> > > on
> > > PSR2. Was PSR1 enabled before PSR2?
> >
> > Yes it only happens when switching from PSR1 -> PSR2, I caught this
> > issue now because I had a external connector attached so display was
> > never going to DC6.
> >
> > >
> > >
> > >
> > > > > So lets clear this register before enabled PSR2, as it could be
> > > > > set
> > > > > by a previous i915 module, firmware/BIOS or by a previous mode
> > > > > that
> > > > > is not compatible with PSR2.
> > > >
> > > > Does it happen when you don't have DMC loaded?
> > > >
> > > > Because It looks like a DMC bug for me...
> > > >
> > > > If by removing DMC we don't see the issue, could we please file
> > > > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > > >
> > > > Aa: Pavana
> > > >
> > > > If it doesn't happen with DMC loaded than maybe a HSD would for hw
> > > > team would be good anyway.
> > > >
> > > > Cc: Art.
> > > >
> > > > Thanks,
> > > > Rodrigo.
> > > >
> > > > > Cc: Dhinakaran Pandiyan
> > > > > Cc: Rodrigo Vivi
> > > > > Signed-off-by: José Roberto de Souza
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_psr.c | 12 ++--
> > > > > 1 file changed, 10 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > > intel_dp
> > > > > *intel_dp)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > > u32 val;
> > > > > + int idle_frames;
> > > > > +
> > > > > + /*
> > > > > + * Keeping this PSR1 register set while PSR2 is enabled causes
> > > > > some
> > > > > + * PSR2 selective updates to fail, corrupting screen.
> > > > > + */
> > > > > + val = I915_READ(EDP_PSR_CTL);
> > > > > + if (val & EDP_PSR_TP1_TP3_SEL)
> > > > > + I915_WRITE(EDP_PSR_CTL, val &
> ~EDP_PSR_TP1_TP3_SEL);
> > >
> > > Since PSR1 should be disabled at this point, a rmw is not necessary.
> > > Does this work?
> > > I915_WRITE(EDP_PSR_CTL, 0);
> > >
> > > We could do the same thing in psr_exit() as well.
> >
> > Write 0 also works and I'm doing RMW because I always try to save any
> > writes.
> >
> > No need to do it in psr_exit(), the important is do it here because
> > other i915 module or BIOS could leave it set.
> >
> > >
> > > > >
> > > > > /* Let's use 6 as the minimum to cover all known cases
> > > > > including the
> > > > >* off-by-one issue that HW has in some cases.
> > > > >*/
> > > > > - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > -
> > > > > + idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > idle_frames = max(idle_frames, dev_priv-
> >psr.sink_sync_latency
> > > > > + 1);
> > > > > val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
> > > > >
> > > > > --
> > > > > 2.21.0
> > > > >
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
== Series Details == Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated URL : https://patchwork.freedesktop.org/series/58241/ State : success == Summary == CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12529_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12529_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@preempt-other-bsd2: - shard-apl: NOTRUN -> SKIP [fdo#109271] +22 * igt@gem_pwrite@big-cpu-fbr: - shard-skl: NOTRUN -> SKIP [fdo#109271] +135 * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: PASS -> SKIP [fdo#109271] * igt@i915_pm_rpm@gem-mmap-cpu: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@system-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807] * igt@i915_selftest@live_workarounds: - shard-iclb: PASS -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +16 * igt@kms_busy@extended-pageflip-hang-newfb-render-e: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_cursor_crc@cursor-128x128-dpms: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_draw_crc@draw-method-xrgb-mmap-gtt-ytiled: - shard-skl: PASS -> FAIL [fdo#107791] / [fdo#108145] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_frontbuffer_tracking@basic: - shard-iclb: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff: - shard-glk: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> INCOMPLETE [fdo#106978] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#109247] +14 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +3 * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-glk: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] +1 * igt@kms_psr@cursor_mmap_gtt: - shard-iclb: PASS -> FAIL [fdo#107383] +2 * igt@kms_psr@cursor_plane_onoff: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +27 * igt@kms_psr@psr2_sprite_render: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom: - shard-kbl: PASS -> DMESG-FAIL [fdo#105763] * igt@kms_setmode@basic: - shard-hsw: PASS -> FAIL [fdo#99912] * igt@perf_pmu@rc6-runtime-pm: - shard-apl: PASS -> FAIL [fdo#105010] * igt@prime_vgem@wait-bsd1: - shard-snb: NOTRUN -> SKIP [fdo#109271] +33 Possible fixes * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: SKIP [fdo#109271] -> PASS * igt@i915_pm_rpm@modeset-lpsp: - shard-skl: INCOMPLETE [fdo#107807] -> PASS +1 * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-iclb: FAIL [fdo#103355] -> PASS * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-iclb: FAIL [fdo#105682] / [fdo#108040] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: FAIL [fdo#103167] -> PASS +7 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: - shard-iclb: FAIL [fdo#105682]
Re: [Intel-gfx] [PATCH] drm/i915: Fix PSR2 selective update corruption after PSR1 setup
Thanks for checking, appreciate it.
-DK
> -Original Message-
> From: Runyan, Arthur J
> Sent: Wednesday, March 20, 2019 11:58 AM
> To: Souza, Jose ; Vivi, Rodrigo
> ; Pandiyan, Dhinakaran
>
> Cc: Aigal, Pavana A ; 'intel-
> g...@lists.freedesktop.org'
> Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption after
> PSR1 setup
>
> PSR2 logic is incorrectly looking at this register bit during DC5 exit.
> Not a DMC problem, but DMC enables DC5.
> I'll update Bspec to require the bit to be not set when PSR2 is used.
>
> > -Original Message-
> > From: Runyan, Arthur J
> > Sent: Tuesday, 12 March, 2019 4:42 PM
> > To: Souza, Jose ; Vivi, Rodrigo
> > ; Pandiyan, Dhinakaran
> >
> > Cc: Aigal, Pavana A ; intel-
> > g...@lists.freedesktop.org
> > Subject: RE: [PATCH] drm/i915: Fix PSR2 selective update corruption
> > after
> > PSR1 setup
> >
> > Strange. DMC doesn't look at training patterns. I've asked the PSR2
> > guys to look for any cross-connection.
> >
> > > -Original Message-
> > > From: Souza, Jose
> > > Sent: Tuesday, 12 March, 2019 2:29 PM
> > > To: Vivi, Rodrigo ; Pandiyan, Dhinakaran
> > >
> > > Cc: Runyan, Arthur J ; Aigal, Pavana A
> > > ; intel-gfx@lists.freedesktop.org
> > > Subject: Re: [PATCH] drm/i915: Fix PSR2 selective update corruption
> > > after
> > > PSR1 setup
> > >
> > > On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > > > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > > > wrote:
> > > > > > For some reason if the PSR1 EDP_PSR_TP1_TP3_SEL register is
> > > > > > kept set while PSR2 is enabled, it causes some selective
> > > > > > updates to fail after got back from DC6 for the first time.
> > > >
> > > > That's suspicious, why does a PSR1 control register have any
> > > > effect on PSR2. Was PSR1 enabled before PSR2?
> > >
> > > Yes it only happens when switching from PSR1 -> PSR2, I caught this
> > > issue now because I had a external connector attached so display was
> > > never going to DC6.
> > >
> > > >
> > > >
> > > >
> > > > > > So lets clear this register before enabled PSR2, as it could
> > > > > > be set by a previous i915 module, firmware/BIOS or by a
> > > > > > previous mode that is not compatible with PSR2.
> > > > >
> > > > > Does it happen when you don't have DMC loaded?
> > > > >
> > > > > Because It looks like a DMC bug for me...
> > > > >
> > > > > If by removing DMC we don't see the issue, could we please file
> > > > > this bug to DMC while adding a FIXME with DMC bugged version on it?
> > > > >
> > > > > Aa: Pavana
> > > > >
> > > > > If it doesn't happen with DMC loaded than maybe a HSD would for
> > > > > hw team would be good anyway.
> > > > >
> > > > > Cc: Art.
> > > > >
> > > > > Thanks,
> > > > > Rodrigo.
> > > > >
> > > > > > Cc: Dhinakaran Pandiyan
> > > > > > Cc: Rodrigo Vivi
> > > > > > Signed-off-by: José Roberto de Souza
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/intel_psr.c | 12 ++--
> > > > > > 1 file changed, 10 insertions(+), 2 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > index 7bab6a009e0d..ae62f8124558 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > @@ -494,12 +494,20 @@ static void hsw_activate_psr2(struct
> > > > > > intel_dp
> > > > > > *intel_dp)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > > > u32 val;
> > > > > > + int idle_frames;
> > > > > > +
> > > > > > + /*
> > > > > > +* Keeping this PSR1 register set while PSR2 is enabled
> > > > > > +causes
> > > > > > some
> > > > > > +* PSR2 selective updates to fail, corrupting screen.
> > > > > > +*/
> > > > > > + val = I915_READ(EDP_PSR_CTL);
> > > > > > + if (val & EDP_PSR_TP1_TP3_SEL)
> > > > > > + I915_WRITE(EDP_PSR_CTL, val &
> > ~EDP_PSR_TP1_TP3_SEL);
> > > >
> > > > Since PSR1 should be disabled at this point, a rmw is not necessary.
> > > > Does this work?
> > > > I915_WRITE(EDP_PSR_CTL, 0);
> > > >
> > > > We could do the same thing in psr_exit() as well.
> > >
> > > Write 0 also works and I'm doing RMW because I always try to save
> > > any writes.
> > >
> > > No need to do it in psr_exit(), the important is do it here because
> > > other i915 module or BIOS could leave it set.
> > >
> > > >
> > > > > >
> > > > > > /* Let's use 6 as the minimum to cover all known cases
> > > > > > including the
> > > > > > * off-by-one issue that HW has in some cases.
> > > > > > */
> > > > > > - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > > -
> > > > > > + idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > > > > > idle_frames = max(idle_frames, dev_priv-
> > >psr.sink_sync_latency
> > > > > > + 1);
> > > > > > val = idle_frames << E
Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
Pushed to dinq, thanks for the review!
Regards
Manasi
On Wed, Mar 20, 2019 at 11:17:49AM +0200, Jani Nikula wrote:
> On Tue, 19 Mar 2019, Manasi Navare wrote:
> > This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> > to correctly do the left shifting to set the port sync
> > master select correctly.
> > I have tested this fix on ICL.
> >
> > Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI
> > registers")
> > Cc: Madhav Chauhan
> > Cc: Jani Nikula
> > Signed-off-by: Manasi Navare
>
> Auch.
>
> Reviewed-by: Jani Nikula
>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 85e8d1a1f70b..7a9d867eb49b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9352,7 +9352,7 @@ enum skl_power_gate {
> > #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, \
> > _TRANS_DDI_FUNC_CTL2_A)
> > #define PORT_SYNC_MODE_ENABLE (1 << 4)
> > -#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) < 0)
> > +#define PORT_SYNC_MODE_MASTER_SELECT(x) ((x) << 0)
> > #define PORT_SYNC_MODE_MASTER_SELECT_MASK (0x7 << 0)
> > #define PORT_SYNC_MODE_MASTER_SELECT_SHIFT0
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_shrink: Open the device before using it!
On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> igt_device")
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> ---
> tests/i915/gem_shrink.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
> index 73b6be725..51d1343ba 100644
> --- a/tests/i915/gem_shrink.c
> +++ b/tests/i915/gem_shrink.c
> @@ -403,7 +403,12 @@ igt_main
> unsigned int engine;
> int fd;
>
> - /* Spawn enough processes to use all memory, but each only
> + fd = drm_open_driver(DRIVER_INTEL);
> + igt_require_gem(fd);
> +
> +
Bonus newline?
Reviewed-by: Ville Syrjälä
> + /*
> + * Spawn enough processes to use all memory, but each only
>* uses half the available mappable aperture ~128MiB.
>* Individually the processes would be ok, but en masse
>* we expect the shrinker to start purging objects,
> @@ -418,9 +423,6 @@ igt_main
> intel_require_memory(num_processes, alloc_size,
>CHECK_SWAP | CHECK_RAM);
>
> - fd = drm_open_driver(DRIVER_INTEL);
> - igt_require_gem(fd);
> -
> nengine = 0;
> for_each_engine(fd, engine)
> engines[nengine++] = engine;
> --
> 2.20.1
>
> ___
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> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: always use masks on FW regs
== Series Details == Series: drm/i915: always use masks on FW regs URL : https://patchwork.freedesktop.org/series/58246/ State : success == Summary == CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12530_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12530_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_parallel@bsd1-fds: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +5 * igt@gem_exec_schedule@preempt-other-bsd2: - shard-apl: NOTRUN -> SKIP [fdo#109271] +21 * igt@gem_mmap_gtt@hang: - shard-iclb: NOTRUN -> FAIL [fdo#109677] * igt@gem_pwrite@big-cpu-fbr: - shard-skl: NOTRUN -> SKIP [fdo#109271] +110 * igt@gem_stolen@large-object-alloc: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gem_tiled_swapping@non-threaded: - shard-iclb: PASS -> FAIL [fdo#108686] * igt@gem_userptr_blits@coherency-sync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@i915_pm_backlight@fade_with_dpms: - shard-iclb: PASS -> INCOMPLETE [fdo#107820] * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: PASS -> SKIP [fdo#109271] * igt@i915_pm_rpm@gem-pread: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@system-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807] * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13 * igt@kms_busy@extended-pageflip-hang-newfb-render-e: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_cursor_crc@cursor-128x128-dpms: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-iclb: NOTRUN -> FAIL [fdo#103355] * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@flip-vs-fences: - shard-iclb: PASS -> INCOMPLETE [fdo#107713] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-iclb: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-iclb: PASS -> FAIL [fdo#109247] +21 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#103167] +3 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +4 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> INCOMPLETE [fdo#106978] * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c: - shard-iclb: NOTRUN -> SKIP [fdo#109289] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +2 * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-skl: NOTRUN -> FAIL [fdo#108145] +3 * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-apl: PASS -> FAIL [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-glk: PASS -> FAIL [fdo#108145] +1 * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-iclb: NOTRUN -> FAIL [fdo#109052] * igt@kms_psr2_su@page_flip: - shard-iclb: PASS -> SKIP [fdo#109642] * igt@kms_psr@cursor_mmap_gtt: - shard-iclb: PASS -> FAIL [fdo#107383] +1 * igt@kms_psr@cursor_plane_onoff: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +27 * igt@kms_psr@psr2_sprite_render: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_set
[Intel-gfx] [PULL] drm-intel-fixes
Hi Dave and Daniel, Here goes the first round of fixes for 5.1-rc cycle. I will be out on vacation next week, so next week's pull request might come from Jani. Although things looks calm right now. only 3 patches on top of -rc1: drm-intel-fixes-2019-03-20: A protection on our mmap against attempts to map past the end of the object; plus a fix off-by-one in our hang report and a protection; and a fix for eDP panels on Gen9 platforms on VBT absence. Thanks, Rodrigo. The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b: Linux 5.1-rc1 (2019-03-17 14:22:26 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2019-03-20 for you to fetch changes up to 000c4f90e3f0194eef218ff2c6a8fd8ca1de4313: drm/i915: Sanity check mmap length against object size (2019-03-18 13:59:42 -0700) A protection on our mmap against attempts to map past the end of the object; plus a fix off-by-one in our hang report and a protection; and a fix for eDP panels on Gen9 platforms on VBT absence. Chris Wilson (2): drm/i915: Fix off-by-one in reporting hanging process drm/i915: Sanity check mmap length against object size Thomas Preston (1): drm/i915/bios: assume eDP is present on port A when there is no VBT drivers/gpu/drm/i915/i915_gem.c | 15 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/intel_bios.c | 1 + 3 files changed, 11 insertions(+), 7 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_shrink: Open the device before using it!
Quoting Ville Syrjälä (2019-03-20 19:26:29)
> On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> > Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> > igt_device")
> > Signed-off-by: Chris Wilson
> > Cc: Michał Winiarski
> > ---
> > tests/i915/gem_shrink.c | 10 ++
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/tests/i915/gem_shrink.c b/tests/i915/gem_shrink.c
> > index 73b6be725..51d1343ba 100644
> > --- a/tests/i915/gem_shrink.c
> > +++ b/tests/i915/gem_shrink.c
> > @@ -403,7 +403,12 @@ igt_main
> > unsigned int engine;
> > int fd;
> >
> > - /* Spawn enough processes to use all memory, but each only
> > + fd = drm_open_driver(DRIVER_INTEL);
> > + igt_require_gem(fd);
> > +
> > +
>
> Bonus newline?
It's a 2-for-one, time-limited offer.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [CI 3/7] drm/i915: make more uncore function work on intel_uncore
From: Daniele Ceraolo Spurio
Move the init, fini, prune, suspend, resume function to work on
intel_uncore instead of dev_priv.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-5-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 20 +-
drivers/gpu/drm/i915/intel_uncore.c | 273 +-
drivers/gpu/drm/i915/intel_uncore.h | 12 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 6 +-
drivers/gpu/drm/i915/selftests/mock_uncore.h | 2 +-
6 files changed, 159 insertions(+), 156 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b540b33cbf73..70ee1b9e8208 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -998,11 +998,11 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
if (ret < 0)
goto err_bridge;
- intel_uncore_init(dev_priv);
+ intel_uncore_init(&dev_priv->uncore);
intel_device_info_init_mmio(dev_priv);
- intel_uncore_prune(dev_priv);
+ intel_uncore_prune(&dev_priv->uncore);
intel_uc_init_mmio(dev_priv);
@@ -1015,7 +1015,7 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
return 0;
err_uncore:
- intel_uncore_fini(dev_priv);
+ intel_uncore_fini(&dev_priv->uncore);
i915_mmio_cleanup(dev_priv);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1029,7 +1029,7 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
- intel_uncore_fini(dev_priv);
+ intel_uncore_fini(&dev_priv->uncore);
i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -2091,7 +2091,7 @@ static int i915_drm_suspend_late(struct drm_device *dev,
bool hibernation)
i915_gem_suspend_late(dev_priv);
- intel_uncore_suspend(dev_priv);
+ intel_uncore_suspend(&dev_priv->uncore);
intel_power_domains_suspend(dev_priv,
get_suspend_mode(dev_priv, hibernation));
@@ -2287,7 +2287,9 @@ static int i915_drm_resume_early(struct drm_device *dev)
DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
ret);
- intel_uncore_resume_early(dev_priv);
+ intel_uncore_resume_early(&dev_priv->uncore);
+
+ i915_check_and_clear_faults(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
gen9_sanitize_dc_state(dev_priv);
@@ -2857,7 +2859,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_runtime_pm_disable_interrupts(dev_priv);
- intel_uncore_suspend(dev_priv);
+ intel_uncore_suspend(&dev_priv->uncore);
ret = 0;
if (INTEL_GEN(dev_priv) >= 11) {
@@ -2874,7 +2876,7 @@ static int intel_runtime_suspend(struct device *kdev)
if (ret) {
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
- intel_uncore_runtime_resume(dev_priv);
+ intel_uncore_runtime_resume(&dev_priv->uncore);
intel_runtime_pm_enable_interrupts(dev_priv);
@@ -2971,7 +2973,7 @@ static int intel_runtime_resume(struct device *kdev)
ret = vlv_resume_prepare(dev_priv, true);
}
- intel_uncore_runtime_resume(dev_priv);
+ intel_uncore_runtime_resume(&dev_priv->uncore);
intel_runtime_pm_enable_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2e50697e72b4..d58f96ea774c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -525,62 +525,58 @@ check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv)
return ret;
}
-static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
+static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
unsigned int restore_forcewake)
{
+ struct drm_i915_private *i915 = uncore_to_i915(uncore);
+
/* clear out unclaimed reg detection bit */
- if (check_for_unclaimed_mmio(dev_priv))
+ if (check_for_unclaimed_mmio(i915))
DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
/* WaDisableShadowRegForCpd:chv */
- if (IS_CHERRYVIEW(dev_priv)) {
- __raw_i915_write32(dev_priv, GTFIFOCTL,
- __raw_i915_read32(dev_priv, GTFIFOCTL) |
+ if (IS_CHERRYVIEW(i915)) {
+ __raw_i915_write32(i915, GTFIFOCTL,
+ __raw_i915_read32(i915, GTFIFOCTL) |
[Intel-gfx] [CI 6/7] drm/i915: move regs pointer inside the uncore structure
From: Daniele Ceraolo Spurio
This will allow futher simplifications in the uncore handling.
v2: move register access setup under uncore (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-8-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 49 ++---
drivers/gpu/drm/i915/i915_drv.h | 6 +--
drivers/gpu/drm/i915/i915_irq.c | 22
drivers/gpu/drm/i915/intel_lrc.c | 6 +--
drivers/gpu/drm/i915/intel_uncore.c | 54 +--
drivers/gpu/drm/i915/intel_uncore.h | 4 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
7 files changed, 75 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 70ee1b9e8208..0aedf4dc0a04 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -935,46 +935,6 @@ static void i915_driver_cleanup_early(struct
drm_i915_private *dev_priv)
i915_engines_cleanup(dev_priv);
}
-static int i915_mmio_setup(struct drm_i915_private *dev_priv)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
- int mmio_bar;
- int mmio_size;
-
- mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
- /*
-* Before gen4, the registers and the GTT are behind different BARs.
-* However, from gen4 onwards, the registers and the GTT are shared
-* in the same BAR, so we want to restrict this ioremap from
-* clobbering the GTT which we want ioremap_wc instead. Fortunately,
-* the register BAR remains the same size for all the earlier
-* generations up to Ironlake.
-*/
- if (INTEL_GEN(dev_priv) < 5)
- mmio_size = 512 * 1024;
- else
- mmio_size = 2 * 1024 * 1024;
- dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
- if (dev_priv->regs == NULL) {
- DRM_ERROR("failed to map registers\n");
-
- return -EIO;
- }
-
- /* Try to make sure MCHBAR is enabled before poking at it */
- intel_setup_mchbar(dev_priv);
-
- return 0;
-}
-
-static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
-{
- struct pci_dev *pdev = dev_priv->drm.pdev;
-
- intel_teardown_mchbar(dev_priv);
- pci_iounmap(pdev, dev_priv->regs);
-}
-
/**
* i915_driver_init_mmio - setup device MMIO
* @dev_priv: device private
@@ -994,11 +954,12 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
if (i915_get_bridge_dev(dev_priv))
return -EIO;
- ret = i915_mmio_setup(dev_priv);
+ ret = intel_uncore_init(&dev_priv->uncore);
if (ret < 0)
goto err_bridge;
- intel_uncore_init(&dev_priv->uncore);
+ /* Try to make sure MCHBAR is enabled before poking at it */
+ intel_setup_mchbar(dev_priv);
intel_device_info_init_mmio(dev_priv);
@@ -1015,8 +976,8 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
return 0;
err_uncore:
+ intel_teardown_mchbar(dev_priv);
intel_uncore_fini(&dev_priv->uncore);
- i915_mmio_cleanup(dev_priv);
err_bridge:
pci_dev_put(dev_priv->bridge_dev);
@@ -1029,8 +990,8 @@ static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv)
*/
static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
{
+ intel_teardown_mchbar(dev_priv);
intel_uncore_fini(&dev_priv->uncore);
- i915_mmio_cleanup(dev_priv);
pci_dev_put(dev_priv->bridge_dev);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9ac9183fbff..54c9d82590a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1505,8 +1505,6 @@ struct drm_i915_private {
*/
resource_size_t stolen_usable_size; /* Total size minus reserved
ranges */
- void __iomem *regs;
-
struct intel_uncore uncore;
struct i915_virtual_gpu vgpu;
@@ -3489,14 +3487,14 @@ static inline u64 intel_rc6_residency_us(struct
drm_i915_private *dev_priv,
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private
*dev_priv, \
i915_reg_t reg) \
{ \
- return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
+ return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
}
#define __raw_write(x, s) \
static inline void __raw_i915_write##x(const struct drm_i915_private
*dev_priv, \
i915_reg_t reg, uint##x##_t val) \
{ \
- write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
+ write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
}
__raw_read(8, b)
__raw_
[Intel-gfx] [CI 1/7] drm/i915: use intel_uncore in fw get/put internal paths
From: Daniele Ceraolo Spurio
Get/put functions used outside of uncore.c are updated in the next
patch for a nicer split.
v2: use dev_priv where we still have it (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-3-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/intel_uncore.c | 191 +-
drivers/gpu/drm/i915/intel_uncore.h | 17 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 9 +-
6 files changed, 121 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 08683dca7775..a52b7cf1525d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1414,13 +1414,14 @@ static int ironlake_drpc_info(struct seq_file *m)
static int i915_forcewake_domains(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *fw_domain;
unsigned int tmp;
seq_printf(m, "user.bypass_count = %u\n",
- i915->uncore.user_forcewake.count);
+ uncore->user_forcewake.count);
- for_each_fw_domain(fw_domain, i915, tmp)
+ for_each_fw_domain(fw_domain, uncore, tmp)
seq_printf(m, "%s.wake_count = %u\n",
intel_uncore_forcewake_domain_to_str(fw_domain->id),
READ_ONCE(fw_domain->wake_count));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e380cd317dc..b540b33cbf73 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2919,7 +2919,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_opregion_notify_adapter(dev_priv, PCI_D1);
}
- assert_forcewakes_inactive(dev_priv);
+ assert_forcewakes_inactive(&dev_priv->uncore);
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
intel_hpd_poll_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 363b2d3e4d50..b9ac9183fbff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2102,6 +2102,11 @@ static inline struct drm_i915_private
*huc_to_i915(struct intel_huc *huc)
return container_of(huc, struct drm_i915_private, huc);
}
+static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore
*uncore)
+{
+ return container_of(uncore, struct drm_i915_private, uncore);
+}
+
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__, id__) \
for ((id__) = 0; \
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index b4cea3cf3915..ebbb9af970dc 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -207,66 +207,62 @@ fw_domain_put(const struct intel_uncore_forcewake_domain
*d)
}
static void
-fw_domains_get(struct drm_i915_private *i915, enum forcewake_domains
fw_domains)
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
fw_domain_wait_ack_clear(d);
fw_domain_get(d);
}
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_wait_ack_set(d);
uncore->fw_domains_active |= fw_domains;
}
static void
-fw_domains_get_with_fallback(struct drm_i915_private *i915,
+fw_domains_get_with_fallback(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- struct intel_uncore *uncore = &i915->uncore;
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
GEM_BUG_ON(fw_domains & ~uncore->fw_domains);
- for_each_fw_domain_masked(d, fw_domains, i915, tmp) {
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp) {
fw_domain_wait_ack_clear_fallback(d);
fw_domain_get(d);
}
- for_each_fw_domain_masked(d, fw_domains, i915, tmp)
+ for_each_fw_domain_masked(d, fw_domains, uncore, tmp)
fw_domain_wait_ack_set_fallback(d);
uncore->fw_domains_active |= fw_domains;
}
static void
[Intel-gfx] [CI 5/7] drm/i915: reduce the dev_priv->uncore dance in uncore.c
From: Daniele Ceraolo Spurio
Use a local variable where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-7-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 79 -
1 file changed, 43 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 62ee4bc6b7a6..bb9a10cc6904 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -313,6 +313,7 @@ static inline u32 fifo_free_entries(struct drm_i915_private
*dev_priv)
static void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u32 n;
/* On VLV, FIFO will be shared by both SW and HW.
@@ -320,7 +321,7 @@ static void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv)
if (IS_VALLEYVIEW(dev_priv))
n = fifo_free_entries(dev_priv);
else
- n = dev_priv->uncore.fifo_count;
+ n = uncore->fifo_count;
if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {
if (wait_for_atomic((n = fifo_free_entries(dev_priv)) >
@@ -331,7 +332,7 @@ static void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv)
}
}
- dev_priv->uncore.fifo_count = n - 1;
+ uncore->fifo_count = n - 1;
}
static enum hrtimer_restart
@@ -795,7 +796,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
#define GEN11_NEEDS_FORCE_WAKE(reg) \
((reg) < 0x4 || ((reg) >= 0x1c && (reg) < 0x1dc000))
-#define __gen6_reg_read_fw_domains(offset) \
+#define __gen6_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
if (NEEDS_FORCE_WAKE(offset)) \
@@ -881,19 +882,19 @@ static const struct intel_forcewake_range
__vlv_fw_ranges[] = {
GEN_FW_RANGE(0x3, 0x3, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_read_fw_domains(offset) \
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-#define __gen11_fwtable_reg_read_fw_domains(offset) \
+#define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
@@ -945,7 +946,7 @@ static bool is_gen##x##_shadowed(u32 offset) \
__is_genX_shadowed(8)
__is_genX_shadowed(11)
-#define __gen8_reg_write_fw_domains(offset) \
+#define __gen8_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd; \
if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
@@ -975,19 +976,19 @@ static const struct intel_forcewake_range
__chv_fw_ranges[] = {
GEN_FW_RANGE(0x3, 0x37fff, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_write_fw_domains(offset) \
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
-#define __gen11_fwtable_reg_write_fw_domains(offset) \
+#define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(&dev_priv->uncore, offset); \
+ __fwd = find_fw_domain(uncore, offset); \
__fwd; \
})
@@ -1137,16 +1138,17 @@ __gen2_read(64)
#undef GEN2_READ_HEADER
#define GEN6_READ_HEADER(x) \
+ struct intel_uncore *uncore = &dev_priv->uncore; \
u32 offset = i915_mmio_reg_offset(reg); \
unsigned long irqflags; \
u##x val = 0; \
assert_rpm_wakelock_held(dev_priv); \
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
+ spin_lock_irqsave(&uncore->lock, irqflags); \
unclaimed_reg_debug(dev_priv, reg, true, true)
#define GEN6_READ_FOOTER \
unclaimed_reg_debug(dev_priv, reg, true, false); \
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
+ spin_unlock_irqrestore(&uncore->lock, irqflags); \
trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
return val
@@ -1183,9 +1185,9 @@ static u##x \
func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace)
{ \
enum forc
[Intel-gfx] [CI 2/7] drm/i915: use intel_uncore for all forcewake get/put
From: Daniele Ceraolo Spurio
Now that the internal code all works on intel_uncore, flip the
external-facing interface.
v2: fix GVT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-4-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/gvt/mmio_context.c | 8 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 12 ++---
drivers/gpu/drm/i915/i915_gem.c | 20 +++
drivers/gpu/drm/i915/i915_perf.c | 6 +--
drivers/gpu/drm/i915/i915_reset.c | 12 ++---
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 4 +-
drivers/gpu/drm/i915/intel_guc.c | 8 +--
drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 52 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +--
drivers/gpu/drm/i915/intel_uncore.c | 52 ---
drivers/gpu/drm/i915/intel_uncore.h | 12 ++---
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 8 +--
17 files changed, 107 insertions(+), 115 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c
b/drivers/gpu/drm/i915/gvt/mmio_context.c
index f64c76dd11d4..a00a807a1d55 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -356,7 +356,7 @@ static void handle_tlb_pending_event(struct intel_vgpu
*vgpu, int ring_id)
if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
fw |= FORCEWAKE_RENDER;
- intel_uncore_forcewake_get(dev_priv, fw);
+ intel_uncore_forcewake_get(&dev_priv->uncore, fw);
I915_WRITE_FW(reg, 0x1);
@@ -365,7 +365,7 @@ static void handle_tlb_pending_event(struct intel_vgpu
*vgpu, int ring_id)
else
vgpu_vreg_t(vgpu, reg) = 0;
- intel_uncore_forcewake_put(dev_priv, fw);
+ intel_uncore_forcewake_put(&dev_priv->uncore, fw);
gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
}
@@ -552,9 +552,9 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre,
* performace for batch mmio read/write, so we need
* handle forcewake mannually.
*/
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
switch_mmio(pre, next, ring_id);
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
}
/**
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 7550e09939ae..3faf2438b9bc 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -988,7 +988,7 @@ static int workload_thread(void *priv)
workload->ring_id, workload);
if (need_force_wake)
- intel_uncore_forcewake_get(gvt->dev_priv,
+ intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
ret = dispatch_workload(workload);
@@ -1010,7 +1010,7 @@ static int workload_thread(void *priv)
complete_current_workload(gvt, ring_id);
if (need_force_wake)
- intel_uncore_forcewake_put(gvt->dev_priv,
+ intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
FORCEWAKE_ALL);
intel_runtime_pm_put_unchecked(gvt->dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index a52b7cf1525d..0dd8b3fa7fb9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1094,7 +1094,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
}
/* RPSTAT1 is in the GT power well */
- intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
reqf = I915_READ(GEN6_RPNSWREQ);
if (INTEL_GEN(dev_priv) >= 9)
@@ -1122,7 +1122,7 @@ static int i915_frequency_info(struct seq_file *m, void
*unused)
cagf = intel_gpu_freq(dev_priv,
intel_get_cagf(dev_priv, rpstat));
- intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
if (INTEL_GEN(dev_priv) >= 11) {
pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
@@ -2060,12 +2060,12 @@ static int i915_rps_boost
[Intel-gfx] [CI 7/7] drm/i915: make raw access function work on uncore
From: Daniele Ceraolo Spurio
This allows us to ditch i915 in some more places.
v2: use local var in check_vgpu (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-9-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 14 ++---
drivers/gpu/drm/i915/i915_vgpu.c| 7 ++-
drivers/gpu/drm/i915/intel_uncore.c | 90 +++--
3 files changed, 57 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54c9d82590a4..b35d2cb260da 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3484,17 +3484,17 @@ static inline u64 intel_rc6_residency_us(struct
drm_i915_private *dev_priv,
#define POSTING_READ16(reg)(void)I915_READ16_NOTRACE(reg)
#define __raw_read(x, s) \
-static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private
*dev_priv, \
+static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore
*uncore, \
i915_reg_t reg) \
{ \
- return read##s(dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
+ return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
}
#define __raw_write(x, s) \
-static inline void __raw_i915_write##x(const struct drm_i915_private
*dev_priv, \
+static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
i915_reg_t reg, uint##x##_t val) \
{ \
- write##s(val, dev_priv->uncore.regs + i915_mmio_reg_offset(reg)); \
+ write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
}
__raw_read(8, b)
__raw_read(16, w)
@@ -3535,9 +3535,9 @@ __raw_write(64, q)
* therefore generally be serialised, by either the dev_priv->uncore.lock or
* a more localised lock guarding all access to that bank of registers.
*/
-#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
-#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__),
(val__))
-#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__),
(val__))
+#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
+#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore,
(reg__), (val__))
+#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore,
(reg__), (val__))
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
/* "Broadcast RGB" property */
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 3b2d83f704e3..3d0b493e4200 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -60,22 +60,23 @@
*/
void i915_check_vgpu(struct drm_i915_private *dev_priv)
{
+ struct intel_uncore *uncore = &dev_priv->uncore;
u64 magic;
u16 version_major;
BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
- magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
+ magic = __raw_i915_read64(uncore, vgtif_reg(magic));
if (magic != VGT_MAGIC)
return;
- version_major = __raw_i915_read16(dev_priv, vgtif_reg(version_major));
+ version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
if (version_major < VGT_VERSION_MAJOR) {
DRM_INFO("VGT interface version mismatch!\n");
return;
}
- dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
+ dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
dev_priv->vgpu.active = true;
DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index e60856069971..1816eeae3ba9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -31,7 +31,7 @@
#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define GT_FIFO_TIMEOUT_MS 10
-#define __raw_posting_read(dev_priv__, reg__)
(void)__raw_i915_read32((dev_priv__), (reg__))
+#define __raw_posting_read(uncore__, reg__)
(void)__raw_i915_read32((uncore__), (reg__))
static const char * const forcewake_domain_names[] = {
"render",
@@ -275,23 +275,23 @@ fw_domains_reset(struct intel_uncore *uncore,
fw_domain_reset(d);
}
-static inline u32 gt_thread_status(struct drm_i915_private *dev_priv)
+static inline u32 gt_thread_status(struct intel_uncore *uncore)
{
u32 val;
- val = __raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG);
+ val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
return val;
}
-static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
+static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)
{
/
[Intel-gfx] [CI 4/7] drm/i915: make find_fw_domain work on intel_uncore
From: Daniele Ceraolo Spurio
Remove unneeded usage of dev_priv from 1 extra function.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-6-daniele.ceraolospu...@intel.com
---
drivers/gpu/drm/i915/intel_uncore.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index d58f96ea774c..62ee4bc6b7a6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -835,13 +835,13 @@ static int fw_range_cmp(u32 offset, const struct
intel_forcewake_range *entry)
})
static enum forcewake_domains
-find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
+find_fw_domain(struct intel_uncore *uncore, u32 offset)
{
const struct intel_forcewake_range *entry;
entry = BSEARCH(offset,
- dev_priv->uncore.fw_domains_table,
- dev_priv->uncore.fw_domains_table_entries,
+ uncore->fw_domains_table,
+ uncore->fw_domains_table_entries,
fw_range_cmp);
if (!entry)
@@ -853,11 +853,11 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32
offset)
* translate it here to the list of available domains.
*/
if (entry->domains == FORCEWAKE_ALL)
- return dev_priv->uncore.fw_domains;
+ return uncore->fw_domains;
- WARN(entry->domains & ~dev_priv->uncore.fw_domains,
+ WARN(entry->domains & ~uncore->fw_domains,
"Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
-entry->domains & ~dev_priv->uncore.fw_domains, offset);
+entry->domains & ~uncore->fw_domains, offset);
return entry->domains;
}
@@ -885,7 +885,7 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -893,7 +893,7 @@ static const struct intel_forcewake_range __vlv_fw_ranges[]
= {
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -979,7 +979,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[]
= {
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
@@ -987,7 +987,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[]
= {
({ \
enum forcewake_domains __fwd = 0; \
if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
- __fwd = find_fw_domain(dev_priv, offset); \
+ __fwd = find_fw_domain(&dev_priv->uncore, offset); \
__fwd; \
})
--
2.20.1
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