Re: [Intel-gfx] [PATCH] drm/i915: Handle YUV subpixel support better
Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
>> Op 18-03-2019 om 15:18 schreef Ville Syrjälä:
>>> On Mon, Mar 18, 2019 at 03:07:18PM +0100, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_sprite.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 268fb34ff0e2..862fc172042f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -269,7 +269,8 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
struct drm_rect *src = &plane_state->base.src;
- u32 src_x, src_y, src_w, src_h;
+ u32 src_x, src_y, src_w, src_h, hsub, vsub;
+ bool rotated = drm_rotation_90_or_270(plane_state->base.rotation);
/*
* Hardware doesn't handle subpixel coordinates.
@@ -287,18 +288,26 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
src->y1 = src_y << 16;
src->y2 = (src_y + src_h) << 16;
- if (fb->format->is_yuv &&
- (src_x & 1 || src_w & 1)) {
- DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV
planes\n",
-src_x, src_w);
+ if (!fb->format->is_yuv)
+ return 0;
+
+ /* YUV specific checks */
+ if (!rotated) {
+ hsub = fb->format->hsub;
+ vsub = fb->format->vsub;
+ } else {
+ hsub = vsub = max(fb->format->hsub, fb->format->vsub);
>>> Why this? From the looks of things there should be no need to deal with
>>> rotation in this function at all.
>> I wrote a dumb test that fails if I rotate YUYV.
>>
>> https://patchwork.freedesktop.org/patch/286170/
>>
>> Corrupted image:
>>
>> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_rotation(90°)
>> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_position(18,33)
>> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_size(44x65)
>> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_position(64,64)
>> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_size (256x256)
>>
>> I had a 80x128 fb, only showing the center part which should be white, with
>> a black border around it to cause CRC errors if we mess up clipping.
>>
>> The scaling works fine, but the clipping does not in this case. I am getting
>> a corrupted plane on screen which is mostly white, but with black dots in
>> each tile.
>>
>> Scaling just magnifies this corruption. :)
> Hmm. I just poked my KBL a bit and it is also showing curious
> behaviour. Even with 90/270 rotation it is in fact the TILEOFF
> X coordinate that needs to be even (actually the hw just appears
> to ignore the lsb). I can make the Y coordinate odd, and the image
> still looks correct to my eyes. So feels like someone forgot to
> to remove a (x&~1) from the hw when they added the 90/270 rotation,
> and yet they went to the trouble of making odd Y coordinates work
> correctly. Quite stange.
>
> Width/height being odd seems to handled just fine by the hw.
>
Hmm does that mean we should keep the original checks in place while checking
format->h/vsub, and on top reject the unrotated Y coordinate being a multiple
of hsub when rotating?
~Maarten
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr: remove drmP.h include that crept in
== Series Details == Series: drm/i915/psr: remove drmP.h include that crept in URL : https://patchwork.freedesktop.org/series/58136/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12501_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12501_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12501_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12501_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt: - shard-iclb: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_12501_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_schedule@fifo-bsd2: - shard-snb: NOTRUN -> SKIP [fdo#109271] +74 * igt@gem_exec_schedule@preempt-other-chain-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +1 * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-iclb: PASS -> INCOMPLETE [fdo#109100] / [fdo#109766] / [fdo#109801] * igt@gem_pread@stolen-uncached: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +21 * igt@gem_tiled_fence_blits@normal: - shard-iclb: PASS -> TIMEOUT [fdo#109673] +1 * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_rpm@gem-idle: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_suspend@fence-restore-untiled: - shard-iclb: PASS -> FAIL [fdo#103375] * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking: - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-e: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-c: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-glk: PASS -> FAIL [fdo#108145] - shard-iclb: PASS -> FAIL [fdo#107725] * igt@kms_chamelium@hdmi-crc-abgr: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: PASS -> FAIL [fdo#108682] * igt@kms_color@pipe-b-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] +1 * igt@kms_color@pipe-c-degamma: - shard-apl: PASS -> FAIL [fdo#104782] * igt@kms_content_protection@legacy: - shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] * igt@kms_cursor_crc@cursor-256x256-sliding: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-random: - shard-apl: PASS -> FAIL [fdo#103232] +5 * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-iclb: PASS -> FAIL [fdo#103355] * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_flip@2x-modeset-vs-vblank-race: - shard-iclb: NOTRUN -> SKIP [fdo#109274] * igt@kms_flip_tiling@flip-y-tiled: - shard-skl: PASS -> FAIL [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +11 * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc: - shard-skl: PASS -> FAIL [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-apl: PASS -> FAIL [fdo#103375] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: NOTRUN -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +4 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: PASS -> FAIL [fdo#109247] +12 * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt: - shard-
[Intel-gfx] [RFC v1 1/7] drm/i915: Add gamma mode property
Gen platforms support multiple gamma modes, currently
it's hard coded to operate only in 1 specific mode.
This patch adds a property to make gamma mode programmable.
User can select which mode should be used for a particular
usecase or scenario.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/intel_color.c | 46 ++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c65c2e6..02231ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1735,6 +1735,8 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *gamma_mode_property;
+
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
bool audio_component_registered;
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 467fd1a..9d43d19 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -92,6 +92,19 @@
0x0800, 0x0100, 0x0800,
};
+#define LEGACY_PALETTE_MODE_8BIT BIT(0)
+#define PRECISION_PALETTE_MODE_10BIT BIT(1)
+#define INTERPOLATED_GAMMA_MODE_12BIT BIT(2)
+#define MULTI_SEGMENTED_GAMMA_MODE_12BIT BIT(3)
+#define SPLIT_GAMMA_MODE_12BIT BIT(4)
+
+#define INTEL_GAMMA_MODE_MASK (\
+ LEGACY_PALETTE_MODE_8BIT | \
+ PRECISION_PALETTE_MODE_10BIT | \
+ INTERPOLATED_GAMMA_MODE_12BIT | \
+ MULTI_SEGMENTED_GAMMA_MODE_12BIT | \
+ BIT_SPLIT_GAMMA_MODE_12BIT)
+
static bool lut_is_legacy(const struct drm_property_blob *lut)
{
return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
@@ -105,6 +118,37 @@ static bool crtc_state_is_legacy_gamma(const struct
intel_crtc_state *crtc_state
lut_is_legacy(crtc_state->base.gamma_lut);
}
+static const struct drm_prop_enum_list gamma_mode_supported[] = {
+ { LEGACY_PALETTE_MODE_8BIT, "8 Bit Legacy Palette Mode" },
+ { PRECISION_PALETTE_MODE_10BIT, "10 Bit Precision Palette Mode" },
+ { INTERPOLATED_GAMMA_MODE_12BIT, "12 Bit Interploated Gamma Mode" },
+ { MULTI_SEGMENTED_GAMMA_MODE_12BIT,
+ "12 Bit Multi Segmented Gamma Mode" },
+ { SPLIT_GAMMA_MODE_12BIT, "12 Bit Split Gamma Mode" },
+};
+
+void
+intel_attach_gamma_mode_property(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_property *prop;
+
+ prop = dev_priv->gamma_mode_property;
+ if (!prop) {
+ prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
+ "Gamma Mode",
+ gamma_mode_supported,
+
ARRAY_SIZE(gamma_mode_supported));
+ if (!prop)
+ return;
+
+ dev_priv->gamma_mode_property = prop;
+ }
+
+ drm_object_attach_property(&crtc->base.base, prop, 0);
+}
+
/*
* When using limited range, multiply the matrix given by userspace by
* the matrix that we would use for the limited range.
@@ -907,4 +951,6 @@ void intel_color_init(struct intel_crtc *crtc)
INTEL_INFO(dev_priv)->color.degamma_lut_size,
true,
INTEL_INFO(dev_priv)->color.gamma_lut_size);
+
+ intel_attach_gamma_mode_property(crtc);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9f188e..fd84fe9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1034,6 +1034,9 @@ struct intel_crtc_state {
u8 nv12_planes;
u8 c8_planes;
+ /* Gamma mode type programmed on the pipe */
+ u32 gamma_mode_type;
+
/* bitmask of planes that will be updated during the commit */
u8 update_planes;
--
1.9.1
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[Intel-gfx] [RFC v1 4/7] drm/i915: Implement get set property handler for multi segment gamma
Implement get and set property handler for multi segment gamma
mode.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_display.c | 46
drivers/gpu/drm/i915/intel_drv.h | 12 ++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7604f16..8ac9728 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13679,6 +13679,39 @@ static int intel_atomic_commit(struct drm_device *dev,
return 0;
}
+static int
+intel_atomic_replace_property_blob_from_id(struct drm_device *dev,
+ struct drm_property_blob **blob,
+ u64 blob_id,
+ ssize_t expected_size,
+ ssize_t expected_elem_size,
+ bool *replaced)
+{
+ struct drm_property_blob *new_blob = NULL;
+
+ if (blob_id != 0) {
+ new_blob = drm_property_lookup_blob(dev, blob_id);
+ if (!new_blob)
+ return -EINVAL;
+
+ if (expected_size > 0 &&
+ new_blob->length != expected_size) {
+ drm_property_blob_put(new_blob);
+ return -EINVAL;
+ }
+ if (expected_elem_size > 0 &&
+ new_blob->length % expected_elem_size != 0) {
+ drm_property_blob_put(new_blob);
+ return -EINVAL;
+ }
+ }
+
+ *replaced |= drm_property_replace_blob(blob, new_blob);
+ drm_property_blob_put(new_blob);
+
+ return 0;
+}
+
/**
* intel_crtc_atomic_get_property - hook for crtc->atomic_get_property.
* @crtc: Crtc to get the property for.
@@ -13699,6 +13732,9 @@ int intel_crtc_atomic_get_property(struct drm_crtc
*crtc,
if (property == dev_priv->gamma_mode_property) {
*val = intel_crtc_state->gamma_mode_type;
+ } else if (property == dev_priv->multi_segment_gamma_mode_property) {
+ *val = (intel_crtc_state->multi_segment_gamma_lut) ?
+ intel_crtc_state->multi_segment_gamma_lut->base.id : 0;
} else {
DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name);
return -EINVAL;
@@ -13724,11 +13760,21 @@ int intel_crtc_atomic_set_property(struct drm_crtc
*crtc,
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state);
+ bool replaced = false;
+ int ret;
if (property == dev_priv->gamma_mode_property) {
intel_crtc_state->gamma_mode_type = val;
state->color_mgmt_changed |= replaced;
return 0;
+ } else if (property == dev_priv->multi_segment_gamma_mode_property) {
+ ret = intel_atomic_replace_property_blob_from_id(dev,
+
&intel_crtc_state->multi_segment_gamma_lut,
+ val, -1,
+ sizeof(struct multi_segment_gamma_lut),
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
}
DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index fd84fe9..7fccd28 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1037,6 +1037,18 @@ struct intel_crtc_state {
/* Gamma mode type programmed on the pipe */
u32 gamma_mode_type;
+ /**
+* @multi_segment_gamma_lut:
+*
+* Lookup table for converting pixel data after the color conversion
+* matrix @ctm. See drm_crtc_enable_color_mgmt(). The blob (if not
+* NULL) is an array of &struct drm_color_lut.
+*/
+ struct drm_property_blob *multi_segment_gamma_lut;
+
+ /* State to check for Gamma Mode Color Changes */
+ bool color_mgmt_changed : 1;
+
/* bitmask of planes that will be updated during the commit */
u8 update_planes;
--
1.9.1
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[Intel-gfx] [RFC v1 6/7] drm/i915/icl: Add support for multi segmented gamma mode
Gen11 introduced a new gamma mode i.e, multi segmented
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 105 +++--
1 file changed, 90 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 399d63d..7733c256 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -105,6 +105,9 @@
MULTI_SEGMENTED_GAMMA_MODE_12BIT | \
BIT_SPLIT_GAMMA_MODE_12BIT)
+#define GEN11_GET_MS10BITS_OF_LUT(lut) (((lut) >> 6) & 0x3FF)
+#define GEN11_GET_LS6BITS_OF_LUT(lut) ((lut) & 0x3F)
+
static bool lut_is_legacy(const struct drm_property_blob *lut)
{
return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
@@ -538,6 +541,10 @@ static void bdw_load_degamma_lut(const struct
intel_crtc_state *crtc_state)
if (degamma_lut) {
const struct drm_color_lut *lut = degamma_lut->data;
+ if (crtc_state->gamma_mode_type ==
+ MULTI_SEGMENTED_GAMMA_MODE_12BIT)
+ lut += 9;
+
for (i = 0; i < lut_size; i++) {
u32 word =
drm_color_lut_extract(lut[i].red, 10) << 20 |
@@ -563,6 +570,7 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;
u32 i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
+ u32 word;
WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
@@ -574,13 +582,32 @@ static void bdw_load_gamma_lut(const struct
intel_crtc_state *crtc_state, u32 of
if (gamma_lut) {
const struct drm_color_lut *lut = gamma_lut->data;
- for (i = 0; i < lut_size; i++) {
- u32 word =
- (drm_color_lut_extract(lut[i].red, 10) << 20) |
- (drm_color_lut_extract(lut[i].green, 10) << 10) |
- drm_color_lut_extract(lut[i].blue, 10);
-
- I915_WRITE(PREC_PAL_DATA(pipe), word);
+ if (crtc_state->gamma_mode_type ==
+ MULTI_SEGMENTED_GAMMA_MODE_12BIT) {
+ lut_size = 9 + 512;
+ for (i = 9; i < lut_size; i++) {
+ /* For Even Index */
+ word = (GEN11_GET_LS6BITS_OF_LUT(lut[i].red) <<
20) |
+ (GEN11_GET_LS6BITS_OF_LUT(lut[i].green)
<< 10)|
+ GEN11_GET_LS6BITS_OF_LUT(lut[i].blue);
+
+
I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word);
+
+/* For ODD index */
+word =
(GEN11_GET_MS10BITS_OF_LUT(lut[i].red) << 20) |
+
(GEN11_GET_MS10BITS_OF_LUT(lut[i].green) << 10) |
+
GEN11_GET_MS10BITS_OF_LUT(lut[i].blue);
+
+
I915_WRITE(PREC_PAL_MULTI_SEG_DATA(pipe), word);
+ }
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ word = (drm_color_lut_extract(lut[i].red, 10)
<< 20) |
+ (drm_color_lut_extract(lut[i].green,
10) << 10) |
+ drm_color_lut_extract(lut[i].blue, 10);
+
+ I915_WRITE(PREC_PAL_DATA(pipe), word);
+ }
}
/* Program the max register to clamp values > 1.0. */
@@ -685,15 +712,57 @@ static void glk_load_luts(const struct intel_crtc_state
*crtc_state)
bdw_load_gamma_lut(crtc_state, 0);
}
+static void icl_load_gamma_multi_segmented_lut(const struct intel_crtc_state
+ *crtc_state, u32 offset)
+{
+ struct drm_crtc *crtc = crtc_state->base.crtc;
+ struct drm_device *dev = crtc_state->base.crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ u32 i, lut_size = 9;
+
+ WARN_ON(offset & ~PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK);
+
+ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe),
+ (PAL_PREC_AUTO_INCREMENT | offset));
+
+ if (crtc_state->base.gamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut
*)crtc_state->base.gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u32 word;
+
+ /* For Even Index */
+ word = (GEN11_GET_LS6BITS_OF_LUT(lut[i].red) << 20) |
+
[Intel-gfx] [RFC v1 5/7] drm/i915/icl: Add register definitions for Multi Segmented gamma
Add macros to define multi segmented gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31a3020..44ca13b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define GAMMA_MODE_MODE_10BIT (1 << 0)
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0)
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
@@ -10147,6 +10148,22 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Add registers for Gen11 Multi Segmented Gamma Mode */
+#define _PAL_PREC_MULTI_SEG_INDEX_A0x4A408
+#define _PAL_PREC_MULTI_SEG_INDEX_B0x4AC08
+#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT BIT(15)
+#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK (0x1f << 0)
+
+#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
+#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+
+#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_INDEX_A, \
+ _PAL_PREC_MULTI_SEG_INDEX_B)
+#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \
+ _PAL_PREC_MULTI_SEG_DATA_A, \
+ _PAL_PREC_MULTI_SEG_DATA_B)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
1.9.1
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v1 0/7] Add Multi Segment Gamma Support
This series adds support for programmable gamma modes and exposes a property interface for the same. Also added, support for mult segment gamma mode introduced in ICL+ Uma Shankar (7): drm/i915: Add gamma mode property drm/i915: Add intel crtc set and get property callback drm/i915: Add Support for Multi Segment Gamma Mode drm/i915: Implement get set property handler for multi segment gamma drm/i915/icl: Add register definitions for Multi Segmented gamma drm/i915/icl: Add support for multi segmented gamma mode drm/i915: Add multi segment gamma for icl drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 17 +++ drivers/gpu/drm/i915/intel_color.c | 194 --- drivers/gpu/drm/i915/intel_display.c | 104 +++ drivers/gpu/drm/i915/intel_drv.h | 15 +++ include/uapi/drm/i915_drm.h | 14 +++ 6 files changed, 332 insertions(+), 15 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v1 2/7] drm/i915: Add intel crtc set and get property callback
Add intel crtc set and get property callbacks. Currently
added for gamma mode property set and get implementation.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_display.c | 58
1 file changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf..7604f16 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13679,6 +13679,62 @@ static int intel_atomic_commit(struct drm_device *dev,
return 0;
}
+/**
+ * intel_crtc_atomic_get_property - hook for crtc->atomic_get_property.
+ * @crtc: Crtc to get the property for.
+ * @state: Crtc state to retrieve the property from.
+ * @property: Property to retrieve.
+ * @val: Return value for the property.
+ *
+ * Returns the atomic property value for a crtc.
+ */
+int intel_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state);
+
+ if (property == dev_priv->gamma_mode_property) {
+ *val = intel_crtc_state->gamma_mode_type;
+ } else {
+ DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * intel_crtc_atomic_set_property - hook for crtc->atomic_set_property.
+ * @crtc: Crtc to set the property for.
+ * @state: Crtc state to set the property on.
+ * @property: Property to set.
+ * @val: New value for the property.
+ *
+ * Sets the atomic property value for a crtc.
+ */
+int intel_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(state);
+
+ if (property == dev_priv->gamma_mode_property) {
+ intel_crtc_state->gamma_mode_type = val;
+ state->color_mgmt_changed |= replaced;
+ return 0;
+ }
+
+ DRM_DEBUG_ATOMIC("Unknown property %s\n", property->name);
+ return -EINVAL;
+}
+
static const struct drm_crtc_funcs intel_crtc_funcs = {
.gamma_set = drm_atomic_helper_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
@@ -13689,6 +13745,8 @@ static int intel_atomic_commit(struct drm_device *dev,
.set_crc_source = intel_crtc_set_crc_source,
.verify_crc_source = intel_crtc_verify_crc_source,
.get_crc_sources = intel_crtc_get_crc_sources,
+ .atomic_get_property = intel_crtc_atomic_get_property,
+ .atomic_set_property = intel_crtc_atomic_set_property,
};
struct wait_rps_boost {
--
1.9.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
Multi Segment Gamma Mode is added in Gen11+ platforms.
Added a property interface to enable that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 23 +++
include/uapi/drm/i915_drm.h| 14 ++
3 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 02231ae..f20d418 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1736,6 +1736,7 @@ struct drm_i915_private {
struct drm_property *force_audio_property;
struct drm_property *gamma_mode_property;
+ struct drm_property *multi_segment_gamma_mode_property;
/* hda/i915 audio component */
struct i915_audio_component *audio_component;
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 9d43d19..399d63d 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const struct
intel_crtc_state *crtc_state
drm_object_attach_property(&crtc->base.base, prop, 0);
}
+void
+intel_attach_multi_segment_gamma_mode_property(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_property *prop;
+
+ prop = dev_priv->multi_segment_gamma_mode_property;
+ if (!prop) {
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "Multi-segment Gamma", 0);
+ if (!prop)
+ return;
+
+ dev_priv->multi_segment_gamma_mode_property = prop;
+ }
+
+ drm_object_attach_property(&crtc->base.base, prop, 0);
+}
+
/*
* When using limited range, multiply the matrix given by userspace by
* the matrix that we would use for the limited range.
@@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc)
INTEL_INFO(dev_priv)->color.gamma_lut_size);
intel_attach_gamma_mode_property(crtc);
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ intel_attach_multi_segment_gamma_mode_property(crtc);
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index aa2d4c7..8f1974e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/*
+ * Structure for muti segmented gamma lut
+ */
+struct multi_segment_gamma_lut {
+ /* Number of Lut Segments */
+ __u8 segment_cnt;
+ /* Precison of LUT entries in bits */
+ __u8 precision_bits;
+ /* Pointer having number of LUT elements in each segment */
+ __u32 *segment_lut_cnt_ptr;
+ /* Pointer to store exact lut values for each segment */
+ __u32 *segment_lut_ptr;
+};
+
#if defined(__cplusplus)
}
#endif
--
1.9.1
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [RFC v1 7/7] drm/i915: Add multi segment gamma for icl
Added support for ICL platform multi segment gamma
capabilties and attached the property, exposing the
same to userspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 7733c256..1e9f784 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -1011,6 +1011,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct multi_segment_gamma_lut multi_segment_lut;
+
drm_mode_crtc_set_gamma_size(&crtc->base, 256);
@@ -1049,6 +1051,24 @@ void intel_color_init(struct intel_crtc *crtc)
intel_attach_gamma_mode_property(crtc);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (IS_ICELAKE(dev_priv)) {
+ multi_segment_lut.segment_cnt = 3;
+ multi_segment_lut.precision_bits = 16;
+ multi_segment_lut.segment_lut_cnt_ptr = kzalloc(3 * sizeof(int),
+ GFP_KERNEL);
+ if (!multi_segment_lut.segment_lut_cnt_ptr)
+ return;
+ multi_segment_lut.segment_lut_cnt_ptr[0] = 9;
+ multi_segment_lut.segment_lut_cnt_ptr[1] = 256;
+ multi_segment_lut.segment_lut_cnt_ptr[2] = 256;
+
intel_attach_multi_segment_gamma_mode_property(crtc);
+
+ drm_property_replace_global_blob(crtc->base.dev,
+
&crtc->config->multi_segment_gamma_lut,
+sizeof(struct
multi_segment_gamma_lut),
+&multi_segment_lut,
+&crtc->base.base,
+
dev_priv->multi_segment_gamma_mode_property);
+ }
}
--
1.9.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Multi Segment Gamma Support
== Series Details == Series: Add Multi Segment Gamma Support URL : https://patchwork.freedesktop.org/series/58169/ State : warning == Summary == $ dim checkpatch origin/drm-tip 21ee2af67f85 drm/i915: Add gamma mode property a2f2f0bff701 drm/i915: Add intel crtc set and get property callback e83f5dac54cc drm/i915: Add Support for Multi Segment Gamma Mode 103a131a2e19 drm/i915: Implement get set property handler for multi segment gamma -:79: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #79: FILE: drivers/gpu/drm/i915/intel_display.c:13772: + ret = intel_atomic_replace_property_blob_from_id(dev, + &intel_crtc_state->multi_segment_gamma_lut, total: 0 errors, 0 warnings, 1 checks, 87 lines checked cd708119e5a6 drm/i915/icl: Add register definitions for Multi Segmented gamma 286cdabed18f drm/i915/icl: Add support for multi segmented gamma mode -:61: CHECK:SPACING: space preferred before that '|' (ctx:VxE) #61: FILE: drivers/gpu/drm/i915/intel_color.c:591: + (GEN11_GET_LS6BITS_OF_LUT(lut[i].green) << 10)| ^ total: 0 errors, 0 warnings, 1 checks, 152 lines checked d23e8eac8e99 drm/i915: Add multi segment gamma for icl ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Multi Segment Gamma Support
== Series Details == Series: Add Multi Segment Gamma Support URL : https://patchwork.freedesktop.org/series/58169/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add gamma mode property +drivers/gpu/drm/i915/intel_color.c:131:1: warning: symbol 'intel_attach_gamma_mode_property' was not declared. Should it be static? -drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void) Commit: drm/i915: Add intel crtc set and get property callback +^~~~ +drivers/gpu/drm/i915/intel_display.c:13691:5: warning: symbol 'intel_crtc_atomic_get_property' was not declared. Should it be static? +drivers/gpu/drm/i915/intel_display.c:13730:32: error: ‘replaced’ undeclared (first use in this function); did you mean ‘replace_fd’? +drivers/gpu/drm/i915/intel_display.c:13730:32: note: each undeclared identifier is reported only once for each function it appears in +drivers/gpu/drm/i915/intel_display.c:13730:46: error: undefined identifier 'replaced' +drivers/gpu/drm/i915/intel_display.c: In function ‘intel_crtc_atomic_set_property’: +make[1]: *** [drivers/gpu/drm/] Error 2 +make[2]: *** [drivers/gpu/drm/i915] Error 2 +make[3]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1 +make: *** [sub-make] Error 2 +replace_fd + state->color_mgmt_changed |= replaced; Commit: drm/i915: Add Support for Multi Segment Gamma Mode +drivers/gpu/drm/i915/intel_color.c:153:1: warning: symbol 'intel_attach_multi_segment_gamma_mode_property' was not declared. Should it be static? -drivers/gpu/drm/i915/selftests/../i915_drv.h:3560:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3561:16: warning: expression using sizeof(void) +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915: Implement get set property handler for multi segment gamma -^~~~ +drivers/gpu/drm/i915/gvt/gtt.c:757:9:expected void [noderef] **slot +drivers/gpu/drm/i915/gvt/gtt.c:757:9:expected void **slot +drivers/gpu/drm/i915/gvt/gtt.c:757:9:expected void **slot +drivers/gpu/drm/i915/gvt/gtt.c:757:9:expected void **slot +drivers/gpu/drm/i915/gvt/gtt.c:757:9:got void [noderef] ** +drivers/gpu/drm/i915/gvt/gtt.c:757:9:got void [noderef] ** +drivers/gpu/drm/i915/gvt/gtt.c:757:9:got void [noderef] ** +drivers/gpu/drm/i915/gvt/gtt.c:757:9:got void **slot +drivers/gpu/drm/i915/gvt/gtt.c:757:9: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/gtt.c:757:9: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gvt/gtt.c:757:9: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gvt/gtt.c:757:9: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/i915/gvt/gtt.c:758:45:expected void [noderef] **slot +drivers/gpu/drm/i915/gvt/gtt.c:758:45:got void **slot +drivers/gpu/drm/i915/gvt/gtt.c:758:45: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/i915/gvt/mmio.c:282:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/gvt/mmio.c:283:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) +drivers/gpu/drm/i915/gvt/vgpu.c:196:48: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:13730:32: error: ‘replaced’ undeclared (first use in this function); did you mean ‘replace_fd’? -O:drivers/gpu/drm/i915/intel_display.c:13730:32: note: each undeclared identifier is reported only once for each function it appears in -O:drivers/gpu/drm/i915/intel_display.c:13730:46: error: undefined identifier 'replaced' +drivers/gpu/drm
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/psr: remove drmP.h include that crept in
On Tue, 19 Mar 2019, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: remove drmP.h include that crept in > URL : https://patchwork.freedesktop.org/series/58136/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12501_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_12501_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_12501_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_12501_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt: > - shard-iclb: PASS -> INCOMPLETE I don't think so. Pushed, thanks for the review. BR, Jani. > > > Known issues > > > Here are the changes found in Patchwork_12501_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_schedule@fifo-bsd2: > - shard-snb: NOTRUN -> SKIP [fdo#109271] +74 > > * igt@gem_exec_schedule@preempt-other-chain-bsd2: > - shard-iclb: NOTRUN -> SKIP [fdo#109276] +1 > > * igt@gem_ppgtt@blt-vs-render-ctx0: > - shard-iclb: PASS -> INCOMPLETE [fdo#109100] / [fdo#109766] / > [fdo#109801] > > * igt@gem_pread@stolen-uncached: > - shard-kbl: NOTRUN -> SKIP [fdo#109271] +21 > > * igt@gem_tiled_fence_blits@normal: > - shard-iclb: PASS -> TIMEOUT [fdo#109673] +1 > > * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: > - shard-iclb: NOTRUN -> SKIP [fdo#109308] > > * igt@i915_pm_rpm@gem-idle: > - shard-skl: PASS -> INCOMPLETE [fdo#107807] > > * igt@i915_suspend@fence-restore-untiled: > - shard-iclb: PASS -> FAIL [fdo#103375] > > * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking: > - shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] > > * igt@kms_busy@extended-modeset-hang-newfb-render-a: > - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 > > * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-e: > - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 > > * igt@kms_busy@extended-modeset-hang-oldfb-render-d: > - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 > > * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-c: > - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: > - shard-glk: PASS -> FAIL [fdo#108145] > - shard-iclb: PASS -> FAIL [fdo#107725] > > * igt@kms_chamelium@hdmi-crc-abgr: > - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 > > * igt@kms_color@pipe-a-legacy-gamma: > - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] > > * igt@kms_color@pipe-b-ctm-0-75: > - shard-skl: PASS -> FAIL [fdo#108682] > > * igt@kms_color@pipe-b-gamma: > - shard-iclb: NOTRUN -> FAIL [fdo#104782] +1 > > * igt@kms_color@pipe-c-degamma: > - shard-apl: PASS -> FAIL [fdo#104782] > > * igt@kms_content_protection@legacy: > - shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] > > * igt@kms_cursor_crc@cursor-256x256-sliding: > - shard-skl: NOTRUN -> FAIL [fdo#103232] > > * igt@kms_cursor_crc@cursor-256x85-random: > - shard-apl: PASS -> FAIL [fdo#103232] +5 > > * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: > - shard-iclb: PASS -> FAIL [fdo#103355] > > * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled: > - shard-skl: PASS -> FAIL [fdo#103184] > > * igt@kms_flip@2x-modeset-vs-vblank-race: > - shard-iclb: NOTRUN -> SKIP [fdo#109274] > > * igt@kms_flip_tiling@flip-y-tiled: > - shard-skl: PASS -> FAIL [fdo#108303] > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: > - shard-iclb: PASS -> FAIL [fdo#103167] +11 > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc: > - shard-skl: PASS -> FAIL [fdo#105682] > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: > - shard-apl: PASS -> FAIL [fdo#103167] +1 > > * igt@kms_frontbuffer_tracking@fbc-suspend: > - shard-apl: PASS -> FAIL [fdo#103375] > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt: > - shard-skl: NOTRUN -> FAIL [fdo#103167] +1 > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt: > - shard-iclb: NOTRUN -> SKIP [fdo#109280
Re: [Intel-gfx] [PATCH] drm/i915: stick to kernel fixed size types
On Mon, 18 Mar 2019, Ville Syrjälä wrote:
> On Mon, Mar 18, 2019 at 06:00:19PM +0200, Jani Nikula wrote:
>> We no longer allow mixed C99 and kernel types, and the preference is to
>> use kernel types exclusively. Fix the C99 types that have crept in since
>> the mass conversion. No functional changes.
>>
>> Cc: Juha-Pekka Heikkila
>> Cc: Kevin Strasser
>> Cc: Ramalingam C
>> Cc: Swati Sharma
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Ville Syrjälä
Pushed, thanks for the review.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
>> drivers/gpu/drm/i915/intel_pipe_crc.c | 2 +-
>> drivers/gpu/drm/i915/intel_sprite.c | 10 +-
>> 3 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
>> b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 5ccb305a6e1c..26767785f14a 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1494,7 +1494,7 @@ static struct hdcp2_hdmi_msg_data {
>>
>> static
>> int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port
>> *intel_dig_port,
>> -uint8_t *rx_status)
>> +u8 *rx_status)
>> {
>> return intel_hdmi_hdcp_read(intel_dig_port,
>> HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
>> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
>> b/drivers/gpu/drm/i915/intel_pipe_crc.c
>> index 64a98712d61f..0b1378f0bff7 100644
>> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
>> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
>> @@ -363,7 +363,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
>> *dev_priv,
>> static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
>> enum pipe pipe,
>> enum intel_pipe_crc_source *source,
>> -uint32_t *val)
>> +u32 *val)
>> {
>> if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
>> *source = INTEL_PIPE_CRC_SOURCE_PIPE;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index e00559d4cf5a..d46af46027b6 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -1818,7 +1818,7 @@ static const u32 skl_plane_formats[] = {
>> DRM_FORMAT_VYUY,
>> };
>>
>> -static const uint32_t icl_plane_formats[] = {
>> +static const u32 icl_plane_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> DRM_FORMAT_XRGB,
>> @@ -1839,7 +1839,7 @@ static const uint32_t icl_plane_formats[] = {
>> DRM_FORMAT_Y416,
>> };
>>
>> -static const uint32_t icl_hdr_plane_formats[] = {
>> +static const u32 icl_hdr_plane_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> DRM_FORMAT_XRGB,
>> @@ -1880,7 +1880,7 @@ static const u32 skl_planar_formats[] = {
>> DRM_FORMAT_NV12,
>> };
>>
>> -static const uint32_t glk_planar_formats[] = {
>> +static const u32 glk_planar_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> DRM_FORMAT_XRGB,
>> @@ -1899,7 +1899,7 @@ static const uint32_t glk_planar_formats[] = {
>> DRM_FORMAT_P016,
>> };
>>
>> -static const uint32_t icl_planar_formats[] = {
>> +static const u32 icl_planar_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> DRM_FORMAT_XRGB,
>> @@ -1924,7 +1924,7 @@ static const uint32_t icl_planar_formats[] = {
>> DRM_FORMAT_Y416,
>> };
>>
>> -static const uint32_t icl_hdr_planar_formats[] = {
>> +static const u32 icl_hdr_planar_formats[] = {
>> DRM_FORMAT_C8,
>> DRM_FORMAT_RGB565,
>> DRM_FORMAT_XRGB,
>> --
>> 2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [v6 02/16] drm: Add Plane Degamma properties
Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Added "Display Color Hardware Pipeline" flow to kernel
documentation as suggested by "Ville Syrjala" and "Brian Starkey".
Moved the property creation to drm_color_mgmt.c file to consolidate
all color operations at one place.
v6: Fixed checkpatch issues with --strict as parameter.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 90 +++
drivers/gpu/drm/drm_atomic.c | 1 +
drivers/gpu/drm/drm_atomic_state_helper.c | 5 ++
drivers/gpu/drm/drm_atomic_uapi.c | 10
drivers/gpu/drm/drm_color_mgmt.c | 43 +--
include/drm/drm_plane.h | 24 +
6 files changed, 170 insertions(+), 3 deletions(-)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 23a3c98..9e64df5 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -473,12 +473,102 @@ FB_DAMAGE_CLIPS
Color Management Properties
---
+Below is how a typical hardware pipeline for color
+will look like:
+
+.. kernel-render:: DOT
+ :alt: Display Color Pipeline
+ :caption: Display Color Pipeline Overview
+
+ digraph "KMS" {
+ node [shape=box]
+
+ subgraph cluster_static {
+ style=dashed
+ label="Display Color Hardware Blocks"
+
+ node [bgcolor=grey style=filled]
+ "Plane Degamma A" -> "Plane CSC/CTM A"
+ "Plane CSC/CTM A" -> "Plane Gamma A"
+ "Pipe Blender" [color=lightblue,style=filled, width=5.25,
height=0.75];
+ "Plane Gamma A" -> "Pipe Blender"
+ "Pipe Blender" -> "Pipe DeGamma"
+ "Pipe DeGamma" -> "Pipe CSC/CTM"
+ "Pipe CSC/CTM" -> "Pipe Gamma"
+ "Pipe Gamma" -> "Pipe Output"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma B" -> "Plane CSC/CTM B"
+ "Plane CSC/CTM B" -> "Plane Gamma B"
+ "Plane Gamma B" -> "Pipe Blender"
+ }
+
+ subgraph cluster_static {
+ style=dashed
+
+ node [shape=box]
+ "Plane Degamma C" -> "Plane CSC/CTM C"
+ "Plane CSC/CTM C" -> "Plane Gamma C"
+ "Plane Gamma C" -> "Pipe Blender"
+ }
+
+ subgraph cluster_fb {
+ style=dashed
+ label="RAM"
+
+ node [shape=box width=1.7 height=0.2]
+
+ "FB 1" -> "Plane Degamma A"
+ "FB 2" -> "Plane Degamma B"
+ "FB 3" -> "Plane Degamma C"
+ }
+ }
+
+In real world usecases,
+
+1. Plane Degamma can be used to linearize a non linear gamma
+encoded framebuffer. This is needed to do any linear math like
+color space conversion. For ex, linearize frames encoded in SRGB
+or by HDR curve.
+
+2. Later Plane CTM block can convert the content to some different
+colorspace. For ex, SRGB to BT2020 etc.
+
+3. Plane Gamma block can be used later to re-apply the non-linear
+curve. This can also be used to apply Tone Mapping for HDR usecases.
+
+All the layers or framebuffers need to be converted to same color
+space and format before blending. The plane color hardware blocks
+can help with this. Once the Data is blended, similar color processing
+can be done on blended output using pipe color hardware blocks.
+
+DRM Properties have been created to define and expose all these
+hardware blocks to userspace. A userspace application (compositor
+or any color app) can use these interfaces and define policies to
+efficiently use the display hardware for such color operations.
+
+Pipe Color Management Properties
+-
+
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: overview
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:export:
+Plane Color Management Properties
+-
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: Plane Color Properties
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: export
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 5eb4013..6336542 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -655,6 +655,7 @@ static void drm_atomic_plane_print_state(struct drm_printer
*p,
drm_get_color_encoding_name(state->color_encoding));
drm_printf(p, "\tcolor-range=%s\n",
drm_get_color_range_name(state->color_range));
+ drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed);
if (plane->funcs->atomic_print_s
[Intel-gfx] [v6 06/16] drm/i915: Enable plane color features
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/intel_color.c | 15 +++
drivers/gpu/drm/i915/intel_device_info.h | 5 +
drivers/gpu/drm/i915/intel_drv.h | 9 +
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c65c2e6..3ef5e2b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,6 +55,7 @@
#include
#include
#include
+#include
#include
#include "i915_fixed.h"
@@ -334,6 +335,11 @@ struct drm_i915_display_funcs {
* involved with the same commit.
*/
void (*load_luts)(const struct intel_crtc_state *crtc_state);
+ /* Add Plane Color callbacks */
+ void (*load_plane_csc_matrix)(const struct drm_plane_state
+ *plane_state);
+ void (*load_plane_luts)(const struct drm_plane_state
+ *plane_state);
};
#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 467fd1a..0f8cb18 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -869,6 +869,21 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+void intel_plane_color_init(struct drm_plane *plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+
+ drm_plane_color_create_prop(plane->dev, plane);
+
+ /* Enable color management support when we have degamma or gamma LUTs.
*/
+ if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 ||
+ INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0)
+ drm_plane_enable_color_mgmt(plane,
+
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size,
+ true,
+
INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 6234570..e3c10bd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -193,6 +193,11 @@ struct intel_device_info {
u32 degamma_lut_tests;
u32 gamma_lut_tests;
} color;
+
+ struct plane_color_luts {
+ u16 plane_degamma_lut_size;
+ u16 plane_gamma_lut_size;
+ } plane_color;
};
struct intel_runtime_info {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9f188e..3bd5b818 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -658,6 +658,14 @@ struct intel_plane_state {
*/
u32 slave;
+ /*
+* Use reduced/limited/broadcast rbg range, compressing from the full
+* range fed into the crtcs.
+*/
+ bool limited_color_range;
+ /* Gamma mode programmed on the plane */
+ u32 gamma_mode;
+
struct drm_intel_sprite_colorkey ckey;
};
@@ -2518,6 +2526,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
+void intel_plane_color_init(struct drm_plane *plane);
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
--
1.9.1
___
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[Intel-gfx] [v6 14/16] drm/i915: Enable Plane Gamma/Degamma
Update the plane gamma and degamma feature in the
plane state and eventually program to PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 6 ++
drivers/gpu/drm/i915/intel_display.c | 6 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 019227b..7e2e746 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6757,6 +6757,7 @@ enum {
#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17)
#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
+#define PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE(1 << 14)
#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
#define PLANE_COLOR_ALPHA_DISABLE(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 22790b4..aa73f88 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -769,8 +769,14 @@ static void icl_load_plane_gamma_lut(const struct
drm_plane_state *state,
/* Loads the palette/gamma unit for the CRTC on Gen11+. */
static void icl_load_plane_luts(const struct drm_plane_state *state)
{
+ struct intel_plane_state *plane_state =
+ to_intel_plane_state(state);
+
icl_load_plane_degamma_lut(state, 0);
icl_load_plane_gamma_lut(state, 0);
+
+ plane_state->gamma_mode |= PLANE_COLOR_PLANE_PRECSC_GAMMA_ENABLE;
+ plane_state->gamma_mode |= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2c44ce4..78d161e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3805,7 +3805,11 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state
*crtc_state,
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
u32 plane_color_ctl = 0;
- plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ if (INTEL_GEN(dev_priv) <= 11)
+ plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
+ else
+ plane_color_ctl |= plane_state->gamma_mode;
+
plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
--
1.9.1
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[Intel-gfx] [v6 00/16] Add Plane Color Properties
This is how a typical display color hardware pipeline looks like: +---+ |RAM| | +--++-++-+ | | | FB 1 || FB 2 || FB N| | | +--++-++-+ | +---+ | Plane Color Hardware Block | ++ | +---v-+ +---v---+ +---v--+ | | | Plane A | | Plane B | | Plane N | | | | DeGamma | | Degamma | | Degamma | | | +---+-+ +---+---+ +---+--+ | | | | || | +---v-+ +---v---+ +---v--+ | | |Plane A | | Plane B | | Plane N | | | |CSC/CTM | | CSC/CTM | | CSC/CTM | | | +---+-+ ++--+ ++-+ | | | | | | | +---v-+ +v--+ +v-+ | | | Plane A | | Plane B | | Plane N | | | | Gamma | | Gamma | | Gamma| | | +---+-+ ++--+ ++-+ | | | | | | ++ +--v--v---v---| || || || Pipe Blender|| +++ ||| |+---v--+ | || Pipe DeGamma| | || | | |+---+--+ | ||Pipe Color | |+---v--+ Hardware| || Pipe CSC/CTM| | || | | |+---+--+ | ||| |+---v--+ | || Pipe Gamma | | || | | |+---+--+ | ||| +-+ | v Pipe Output This patch series adds properties for plane color features. It adds properties for degamma used to linearize data, CSC used for gamut conversion, and gamma used to again non-linearize data as per panel supported color space. These can be utilize by user space to convert planes from one format to another, one color space to another etc. Usersapce can take smart blending decisions and utilize these hardware supported plane color features to get accurate color profile. The same can help in consistent color quality from source to panel taking advantage of advanced color features in hardware. These patches just add the property interfaces and enable helper functions. This series adds Intel Gen9 specific plane gamma feature. We can build up and add other platform/hardware specific implementation on top of this series Note: This is just to get a design feedback whether these interfaces look ok. Based on community feedback on interfaces, we will implement IGT tests to validate plane color features. This is un-tested currently. Userspace implementation using these properties have been done in drm hwcomposer by "Alexandru-Cosmin Gheorghe alexandru-cosmin.gheor...@arm.com" from ARM. A merge request has been opened by Alexandru for drm_hwcomposer, implementing the property changes for the same. Please review that as well: https://gitlab.freedesktop.org/drm-hwcomposer/drm-hwcomposer/merge_requests/25 v2: Dropped legacy gamma table for plane as suggested by Maarten. Added Gen9/BDW plane gamma feature and rebase on tot. v3: Added a new drm_color_lut_ext structure to accommodate 32 bit precision entries, pointed to by Brian, Starkey for HDR usecases. Addressed Sean,Paul comments and moved plane color properties to drm_plane instead of mode_config. Added property documentation as suggested by Daniel, Vetter. Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov. v4: Rebase v5: Added "Display Color Hardware Pipeline" flow to kernel documentation as suggested by "Ville Syrjala" and "Brian Starkey". Moved the property creation to drm_color_mgmt.c file to consolidate all color operations at one place. Addressed Alexandru's review comments. v6: Rebase. Added support for ICL Color features. Enhanced Lut precision to accept input values in u32.32 format. This is needed for higher precision required in HDR data processing. Uma Shankar (16): drm: Add Enhanced Gamma LUT precision structure drm: Add Plane Degamma properties drm: Add Plane CTM property drm: Add Plane Gamma properties drm: Define helper function for plane color enabling drm/i915: Enable plane color features drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms drm/i915: Load plane co
[Intel-gfx] [v6 09/16] drm/i915: Add plane color capabilities
Add Plane color capabilties, support for
degamma and gamma added.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 12 +---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 11 +--
4 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index b56c3999..afb1d00 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -930,7 +930,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
-void intel_plane_color_init(struct drm_plane *plane)
+void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size,
+ u32 gamma_lut_size)
{
struct drm_i915_private *dev_priv = to_i915(plane->dev);
@@ -941,12 +942,9 @@ void intel_plane_color_init(struct drm_plane *plane)
drm_plane_color_create_prop(plane->dev, plane);
/* Enable color management support when we have degamma or gamma LUTs.
*/
- if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 ||
- INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0)
- drm_plane_enable_color_mgmt(plane,
-
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size,
- true,
-
INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size);
+ if (degamma_lut_size != 0 || gamma_lut_size != 0)
+ drm_plane_enable_color_mgmt(plane, degamma_lut_size,
+ true, gamma_lut_size);
}
void intel_color_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e922644..2c44ce4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14396,8 +14396,8 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv,
supported_rotations);
/* Add Plane Color properties */
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
- intel_plane_color_init(&plane->base);
+ if (IS_BROADWELL(dev_priv))
+ intel_plane_color_init(&plane->base, 0, 16);
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 16fae42..9a7033f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2526,7 +2526,8 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
int intel_color_check(struct intel_crtc_state *crtc_state);
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
-void intel_plane_color_init(struct drm_plane *plane);
+void intel_plane_color_init(struct drm_plane *plane, u32 degamma_lut_size,
+ u32 gamma_lut_size);
void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 121da10..74a8619 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2320,8 +2320,15 @@ struct intel_plane *
BIT(DRM_MODE_BLEND_COVERAGE));
/* Add Plane Color properties */
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
- intel_plane_color_init(&plane->base);
+ if (INTEL_GEN(dev_priv) <= 10)
+ intel_plane_color_init(&plane->base, 0, 16);
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ if (icl_is_hdr_plane(dev_priv, plane_id))
+ intel_plane_color_init(&plane->base, 128, 33);
+ else
+ intel_plane_color_init(&plane->base, 33, 33);
+ }
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
--
1.9.1
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[Intel-gfx] [v6 16/16] drm/i915: Enable Plane CSC
Implement plane CSC on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 86
drivers/gpu/drm/i915/intel_display.c | 3 ++
3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38e0c46..4b1ab54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6750,6 +6750,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE (1 << 21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index aa73f88..ed21d98 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -606,6 +606,90 @@ static void bdw_load_plane_gamma_lut(const struct
drm_plane_state *state,
}
}
+static void icl_load_plane_csc_matrix(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u16 coeffs[9] = {};
+ u16 postoff = 0;
+ int i;
+
+ if (state->ctm) {
+ struct drm_color_ctm *ctm = state->ctm->data;
+ const u64 *input;
+
+ input = ctm->matrix;
+
+ /*
+* Convert fixed point S31.32 input to format supported by the
+* hardware.
+*/
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+ u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+ /*
+* Clamp input value to min/max supported by
+* hardware.
+*/
+ abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+ /* sign bit */
+ if (CTM_COEFF_NEGATIVE(input[i]))
+ coeffs[i] |= 1 << 15;
+
+ if (abs_coeff < CTM_COEFF_0_125)
+ coeffs[i] |= (3 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 12);
+ else if (abs_coeff < CTM_COEFF_0_25)
+ coeffs[i] |= (2 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 11);
+ else if (abs_coeff < CTM_COEFF_0_5)
+ coeffs[i] |= (1 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 10);
+ else if (abs_coeff < CTM_COEFF_1_0)
+ coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+ else if (abs_coeff < CTM_COEFF_2_0)
+ coeffs[i] |= (7 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 8);
+ else
+ coeffs[i] |= (6 << 12) |
+ ILK_CSC_COEFF_FP(abs_coeff, 7);
+ }
+ } else {
+ /*
+* Load an identity matrix if no coefficients are provided.
+*
+* TODO: Check what kind of values actually come out of the
+* pipe with these coeff/postoff values and adjust to get the
+* best accuracy. Perhaps we even need to take the bpc value
+* into consideration.
+*/
+ for (i = 0; i < 3; i++)
+ coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
+ }
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 0),
+ coeffs[0] << 16 | coeffs[1]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 1), coeffs[2] << 16);
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 3),
+ coeffs[3] << 16 | coeffs[4]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 4), coeffs[5] << 16);
+
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 5),
+ coeffs[6] << 16 | coeffs[7]);
+ I915_WRITE(PLANE_CSC_COEFF(pipe, plane, 6), coeffs[8] << 16);
+
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ I915_WRITE(PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ I915_WRITE(PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
/* Loads the palette/gamma unit for the
[Intel-gfx] [v6 01/16] drm: Add Enhanced Gamma LUT precision structure
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
v4: Rebase
v5: Relocated the helper function to drm_color_mgmt.c. Declared
the same in a header file (Alexandru Gheorghe)
v6: Enhanced gamma lut structure to take U32.32 format as input.
This is needed for HDR usecase which require higher precision.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 19 +++
include/drm/drm_color_mgmt.h | 1 +
include/uapi/drm/drm_mode.h | 15 +++
3 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index d5d34d0..9dbfe1d 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -128,6 +128,25 @@ uint32_t drm_color_lut_extract(uint32_t user_input,
uint32_t bit_precision)
}
EXPORT_SYMBOL(drm_color_lut_extract);
+/*
+ * Added to accommodate enhanced LUT precision.
+ * Max LUT precision is 32 bits.
+ */
+u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision)
+{
+ u32 val = user_input & 0x;
+ u32 max = 0x >> (32 - bit_precision);
+
+ /* Round only if we're not using full precision. */
+ if (bit_precision < 32) {
+ val += 1UL << (32 - bit_precision - 1);
+ val >>= 32 - bit_precision;
+ }
+
+ return ((user_input & 0x) | clamp_val(val, 0, max));
+}
+EXPORT_SYMBOL(drm_color_lut_extract_ext);
+
/**
* drm_crtc_enable_color_mgmt - enable color management properties
* @crtc: DRM CRTC
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index d1c662d..c9d2746 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -30,6 +30,7 @@
struct drm_plane;
uint32_t drm_color_lut_extract(uint32_t user_input, uint32_t bit_precision);
+u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision);
void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
uint degamma_lut_size,
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a439c2e..a0fae71 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -630,6 +630,21 @@ struct drm_color_lut {
__u16 reserved;
};
+/*
+ * Creating 64 bit palette entries for better data
+ * precision. This will be required for HDR and
+ * similar color processing usecases.
+ */
+struct drm_color_lut_ext {
+ /*
+* Data is U32.32 fixed point format.
+*/
+ __u64 red;
+ __u64 green;
+ __u64 blue;
+ __u64 reserved;
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
1.9.1
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[Intel-gfx] [v6 13/16] drm/i915/icl: Implement Plane Gamma
Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 504c046..22790b4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -692,10 +692,85 @@ static void icl_load_plane_degamma_lut(const struct
drm_plane_state *state,
}
}
+static void icl_load_plane_gamma_lut(const struct drm_plane_state *state,
+u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ lut_size = 32;
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ if (state->degamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext
*)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(lut[i].red, 24);
+ u32 lut_val = (word & 0x7) >> 8;
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 24));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ (1 << 24) - 1);
+ }
+ } else {
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i),
+ lut[i].green);
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ }
+ }
+}
+
/* Loads the palette/gamma unit for the CRTC on Gen11+. */
static void icl_load_plane_luts(const struct drm_plane_state *state)
{
icl_load_plane_degamma_lut(state, 0);
+ icl_load_plane_gamma_lut(state, 0);
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
--
1.9.1
___
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[Intel-gfx] [v6 10/16] drm/i915/icl: Add ICL Plane Degamma Register definition
Add register definitions for ICL Plane Degamma.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0beed42..b9a2084 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10181,6 +10181,48 @@ enum skl_power_gate {
#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
_PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+/* Plane Color Register for Gen11+ */
+/* Plane Degamma Registers */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x70100
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x71100
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x70200
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x71200
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\
+
_PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_A 0x70400
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_B 0x71400
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_A 0x70500
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_B 0x71500
+#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\
+
_PLANE_PRE_CSC_GAMC_INDEX_5(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\
+
_PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_4_A 0x704D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4_B 0x714D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_A 0x705D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_B 0x715D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe) _PIPE(pipe,
_PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
+
_PLANE_PRE_CSC_GAMC_DATA_5(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
1.9.1
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[Intel-gfx] [v6 08/16] drm/i915: Load plane color luts from atomic flip
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 9d32a6f..32269bd 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -271,6 +271,9 @@ void skl_update_planes_on_crtc(struct intel_atomic_state
*state,
struct intel_plane_state *new_plane_state =
intel_atomic_get_new_plane_state(state, plane);
+ if (new_plane_state->base.color_mgmt_changed)
+ intel_color_load_plane_luts(&new_plane_state->base);
+
if (new_plane_state->base.visible) {
intel_update_plane(plane, new_crtc_state,
new_plane_state);
} else if (new_plane_state->slave) {
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index c756cd9..b56c3999 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -841,6 +841,14 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
*crtc_state)
return cgm_mode;
}
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state)
+{
+ struct drm_device *dev = plane_state->plane->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ dev_priv->display.load_plane_luts(plane_state);
+}
+
int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3bd5b818..16fae42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2527,6 +2527,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
void intel_color_commit(const struct intel_crtc_state *crtc_state);
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
void intel_plane_color_init(struct drm_plane *plane);
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state);
/* intel_lspcon.c */
bool lspcon_init(struct intel_digital_port *intel_dig_port);
--
1.9.1
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[Intel-gfx] [v6 12/16] drm/i915/icl: Add Plane Gamma Register Definitions
Add Plane Gamma Register definitions for ICL+
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9a2084..019227b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10222,7 +10222,47 @@ enum skl_power_gate {
#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)_MMIO_PLANE_GAMC(plane,
i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
_PLANE_PRE_CSC_GAMC_DATA_5(pipe))
-
+/* Plane Gamma Registers */
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712D8
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B)
+
+#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe),\
+
_PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_INDEX_4_A 0x704D8
+#define _PLANE_POST_CSC_GAMC_INDEX_4_B 0x714D8
+#define _PLANE_POST_CSC_GAMC_INDEX_5_A 0x705D8
+#define _PLANE_POST_CSC_GAMC_INDEX_5_B 0x715D8
+#define _PLANE_POST_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_INDEX_4_A, _PLANE_POST_CSC_GAMC_INDEX_4_B)
+#define _PLANE_POST_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe,
_PLANE_POSt_CSC_GAMC_INDEX_5_A, _PLANE_POST_CSC_GAMC_INDEX_5_B)
+
+#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_INDEX_4(pipe),\
+
_PLANE_POSt_CSC_GAMC_INDEX_5(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712DC
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_1_A, _PLANE_POST_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_ENH_2_A, _PLANE_POST_CSC_GAMC_DATA_ENH_2_B)
+
+#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe),\
+
_PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_POST_CSC_GAMC_DATA_4_A 0x704DC
+#define _PLANE_POST_CSC_GAMC_DATA_4_B 0x714DC
+#define _PLANE_POST_CSC_GAMC_DATA_5_A 0x705DC
+#define _PLANE_POST_CSC_GAMC_DATA_5_B 0x715DC
+#define _PLANE_POST_CSC_GAMC_DATA_4(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_4_A, _PLANE_POST_CSC_GAMC_DATA_4_B)
+#define _PLANE_POST_CSC_GAMC_DATA_5(pipe) _PIPE(pipe,
_PLANE_POST_CSC_GAMC_DATA_5_A, _PLANE_POST_CSC_GAMC_DATA_5_B)
+
+#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\
+
_PLANE_POST_CSC_GAMC_DATA_5(pipe))
+/* Plane Gamma Registers */
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
--
1.9.1
___
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[Intel-gfx] [v6 05/16] drm: Define helper function for plane color enabling
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 42
include/drm/drm_color_mgmt.h | 5 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index 8b42c3b..8a17f42 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -483,6 +483,48 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
EXPORT_SYMBOL(drm_plane_create_color_properties);
/**
+ * drm_plane_enable_color_mgmt - enable color management properties
+ * @plane: DRM Plane
+ * @plane_degamma_lut_size: the size of the degamma lut (before CSC)
+ * @plane_has_ctm: whether to attach ctm_property for CSC matrix
+ * @plane_gamma_lut_size: the size of the gamma lut (after CSC)
+ *
+ * This function lets the driver enable the color correction
+ * properties on a plane. This includes 3 degamma, csc and gamma
+ * properties that userspace can set and 2 size properties to inform
+ * the userspace of the lut sizes. Each of the properties are
+ * optional. The gamma and degamma properties are only attached if
+ * their size is not 0 and ctm_property is only attached if has_ctm is
+ * true.
+ */
+void drm_plane_enable_color_mgmt(struct drm_plane *plane,
+u32 plane_degamma_lut_size,
+bool plane_has_ctm,
+u32 plane_gamma_lut_size)
+{
+ if (plane_degamma_lut_size) {
+ drm_object_attach_property(&plane->base,
+ plane->degamma_lut_property, 0);
+ drm_object_attach_property(&plane->base,
+ plane->degamma_lut_size_property,
+ plane_degamma_lut_size);
+ }
+
+ if (plane_has_ctm)
+ drm_object_attach_property(&plane->base,
+ plane->ctm_property, 0);
+
+ if (plane_gamma_lut_size) {
+ drm_object_attach_property(&plane->base,
+ plane->gamma_lut_property, 0);
+ drm_object_attach_property(&plane->base,
+ plane->gamma_lut_size_property,
+ plane_gamma_lut_size);
+ }
+}
+EXPORT_SYMBOL(drm_plane_enable_color_mgmt);
+
+/**
* DOC: Plane Color Properties
*
* Plane Color management or color space adjustments is supported
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index c9d2746..8726cee 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -71,6 +71,11 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
enum drm_color_encoding default_encoding,
enum drm_color_range default_range);
+void drm_plane_enable_color_mgmt(struct drm_plane *plane,
+u32 plane_degamma_lut_size,
+bool plane_has_ctm,
+u32 plane_gamma_lut_size);
+
/**
* enum drm_color_lut_tests - hw-specific LUT tests to perform
*
--
1.9.1
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[Intel-gfx] [v6 03/16] drm: Add Plane CTM property
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic_state_helper.c | 4
drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
drivers/gpu/drm/drm_color_mgmt.c | 11 +++
include/drm/drm_plane.h | 15 +++
5 files changed, 43 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 9e64df5..14f79f1 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -569,6 +569,9 @@ Plane Color Management Properties
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: export
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: ctm_property
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index af22463..4d77363 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -245,6 +245,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
if (state->degamma_lut)
drm_property_blob_get(state->degamma_lut);
+ if (state->ctm)
+ drm_property_blob_get(state->ctm);
+
state->color_mgmt_changed = false;
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
@@ -293,6 +296,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
+ drm_property_blob_put(state->ctm);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index 78b2baf..a2b4f89 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -579,6 +579,14 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->ctm_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->ctm,
+ val,
+ sizeof(struct drm_color_ctm), -1,
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -645,6 +653,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
} else if (property == plane->degamma_lut_property) {
*val = (state->degamma_lut) ?
state->degamma_lut->base.id : 0;
+ } else if (property == plane->ctm_property) {
+ *val = (state->ctm) ? state->ctm->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index e339dcd..ad23b8c 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -496,6 +496,11 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
*
* degamma_lut_size_property:
* Range Property to indicate size of the plane degamma LUT.
+ *
+ * ctm_property:
+ * Blob property which allows a userspace to provide CTM coefficients
+ * to do color space conversion or any other enhancement by doing a
+ * matrix multiplication using the h/w CTM processing engine
*/
int drm_plane_color_create_prop(struct drm_device *dev,
struct drm_plane *plane)
@@ -515,6 +520,12 @@ int drm_plane_color_create_prop(struct drm_device *dev,
return -ENOMEM;
plane->degamma_lut_size_property = prop;
+ prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
+ "PLANE_CTM", 0);
+ if (!prop)
+ return -ENOMEM;
+ plane->ctm_property = prop;
+
return 0;
}
EXPORT_SYMBOL(drm_plane_color_create_prop);
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 757f1e8..38b52a2 1
[Intel-gfx] [v6 07/16] drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 25
drivers/gpu/drm/i915/intel_color.c | 57
drivers/gpu/drm/i915/intel_display.c | 4 +++
drivers/gpu/drm/i915/intel_sprite.c | 4 +++
5 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ef7410c..bf61c2e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -117,7 +117,10 @@
}
#define BDW_COLORS \
- .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \
+ .plane_color = { .plane_degamma_lut_size = 0, \
+.plane_gamma_lut_size = 16 }
+
#define CHV_COLORS \
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 477dfda..0beed42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -257,6 +257,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask))\
@@ -10156,6 +10160,27 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe)_MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Plane Gamma in Gen9+ */
+#define _PLANE_GAMC_1_A0x701d0
+#define _PLANE_GAMC_1_B0x711d0
+#define _PLANE_GAMC_2_A0x702d0
+#define _PLANE_GAMC_2_B0x712d0
+#define _PLANE_GAMC_1(pipe)_PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B)
+#define _PLANE_GAMC_2(pipe)_PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B)
+#define PLANE_GAMC(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe))
+
+#define _PLANE_GAMC16_1_A 0x70210
+#define _PLANE_GAMC16_1_B 0x71210
+#define _PLANE_GAMC16_2_A 0x70310
+#define _PLANE_GAMC16_2_B 0x71310
+#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \
+_PLANE_GAMC16_1_B)
+#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \
+_PLANE_GAMC16_2_B)
+#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
+ _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0f8cb18..c756cd9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -562,6 +562,59 @@ static void broadwell_load_luts(const struct
intel_crtc_state *crtc_state)
}
}
+static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state,
+u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size =
+ INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size;
+
+ if (state->gamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u32 word =
+ drm_color_lut_extract_ext(lut[i].red, 10) << 20 |
+ drm_color_lut_extract_ext(lut[i].green, 10) << 10 |
+ drm_color_lut_extract_ext(lut[i].blue, 10);
+
+ I915_WRITE(PLANE_GAMC(pipe, plane, i), word);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ i = lut_size - 1;
+ I915_WRITE(PLAN
[Intel-gfx] [v6 11/16] drm/i915/icl: Enable Plane Degamma
Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index afb1d00..504c046 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -615,6 +615,89 @@ static void broadwell_load_plane_luts(const struct
drm_plane_state *state)
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size);
}
+static void icl_load_plane_degamma_lut(const struct drm_plane_state *state,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ lut_size = 128;
+ if (state->degamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext
*)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u64 word = drm_color_lut_extract_ext(lut[i].red,
+24);
+ u32 lut_val = (word & 0x7) >> 8;
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i),
+ lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 24));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ (1 << 24) - 1);
+ }
+ } else {
+ lut_size = 32;
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i),
+ lut[i].green);
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ }
+ }
+}
+
+/* Loads the palette/gamma unit for the CRTC on Gen11+. */
+static void icl_load_plane_luts(const struct drm_plane_state *state)
+{
+ icl_load_plane_degamma_lut(state, 0);
+}
+
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -978,6 +1061,9 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.color_commit = ilk_color_commit;
}
+ if (INTEL_GEN(dev_priv) >= 11)
+
[Intel-gfx] [v6 15/16] drm/i915: Define Plane CSC Registers
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e2e746..38e0c46 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10263,6 +10263,50 @@ enum skl_power_gate {
#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane,
i, _PLANE_POST_CSC_GAMC_DATA_4(pipe),\
_PLANE_POST_CSC_GAMC_DATA_5(pipe))
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A,
\
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_CSC_COEFF(pipe, plane, index)_MMIO_PLANE(plane, \
+
_PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+
_PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane,
_PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4,
_PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
/* Plane Gamma Registers */
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
--
1.9.1
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[Intel-gfx] [v6 04/16] drm: Add Plane Gamma properties
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 6 ++
drivers/gpu/drm/drm_atomic_state_helper.c | 3 +++
drivers/gpu/drm/drm_atomic_uapi.c | 9 +
drivers/gpu/drm/drm_color_mgmt.c | 22 ++
include/drm/drm_plane.h | 22 ++
5 files changed, 62 insertions(+)
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 14f79f1..0877faf 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -572,6 +572,12 @@ Plane Color Management Properties
.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
:doc: ctm_property
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: gamma_lut_property
+
+.. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
+ :doc: gamma_lut_size_property
+
Tile Group Property
---
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 4d77363..712df6b 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -247,6 +247,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct
drm_plane *plane,
drm_property_blob_get(state->degamma_lut);
if (state->ctm)
drm_property_blob_get(state->ctm);
+ if (state->gamma_lut)
+ drm_property_blob_get(state->gamma_lut);
state->color_mgmt_changed = false;
}
@@ -297,6 +299,7 @@ void __drm_atomic_helper_plane_destroy_state(struct
drm_plane_state *state)
drm_property_blob_put(state->fb_damage_clips);
drm_property_blob_put(state->degamma_lut);
drm_property_blob_put(state->ctm);
+ drm_property_blob_put(state->gamma_lut);
}
EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state);
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
b/drivers/gpu/drm/drm_atomic_uapi.c
index a2b4f89..02aec5a 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -587,6 +587,13 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == plane->gamma_lut_property) {
+ ret = drm_atomic_replace_property_blob_from_id(dev,
+ &state->gamma_lut,
+ val, -1, sizeof(struct drm_color_lut),
+ &replaced);
+ state->color_mgmt_changed |= replaced;
+ return ret;
} else if (property == config->prop_fb_damage_clips) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->fb_damage_clips,
@@ -655,6 +662,8 @@ static int drm_atomic_plane_set_property(struct drm_plane
*plane,
state->degamma_lut->base.id : 0;
} else if (property == plane->ctm_property) {
*val = (state->ctm) ? state->ctm->base.id : 0;
+ } else if (property == plane->gamma_lut_property) {
+ *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
} else if (property == config->prop_fb_damage_clips) {
*val = (state->fb_damage_clips) ?
state->fb_damage_clips->base.id : 0;
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index ad23b8c..8b42c3b 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -501,6 +501,15 @@ int drm_plane_create_color_properties(struct drm_plane
*plane,
* Blob property which allows a userspace to provide CTM coefficients
* to do color space conversion or any other enhancement by doing a
* matrix multiplication using the h/w CTM processing engine
+ *
+ * gamma_lut_property:
+ * Blob property which allows a userspace to provide LUT values
+ * to apply gamma/tone-mapping curve using the h/w plane gamma
+ * processing engine, thereby making the content as non-linear
+ * or to perform any tone mapping operation for HDR usecases.
+ *
+ * gamma_lut_size_property:
+ * Range Property to indicate size of the plane gamma LUT.
*/
int drm_plane_color_create_prop(struct drm_device *dev,
struct drm_plane *plane)
@@ -526,6 +535,19 @@ int drm_plane_color_create_prop(struct
Re: [Intel-gfx] Potential NULL pointer dereference in intel_crt_get_edid
On Mon, 18 Mar 2019, Shaobo He wrote:
> I see. In light of this commit, is it a better solution than adding
> NULL-checks
> is to replace the if branch conditioned by `WARN_ON` with simply `WARN` like
> the
> following,
>
> struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
> unsigned int pin)
> {
> WARN(!intel_gmbus_is_valid_pin(dev_priv, pin), "Invalid pin: %d\n",
> pin);
>
> return &dev_priv->gmbus[pin].adapter;
> }
So all of this discussion is hypothetical in the sense that it really
should never happen. You can track down the args passed to
intel_gmbus_get_adapter(), while the static analyzer is unable to do
that.
BR,
Jani.
>
> Shaobo
> On 3/18/19 5:53 PM, Rodrigo Vivi wrote:
>> On Mon, Mar 18, 2019 at 05:39:48PM -0600, Shaobo He wrote:
>>> Hi Rodrigo,
>>>
>>> Sorry I'm a bit lost here. May I ask where the `WARN` is?
>>
>> along with the return NULL
>>
>> struct i2c_adapter *intel_gmbus_get_adapte()
>>if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
>> return NULL;
>>
>>>
>>> Thanks,
>>> Shaobo
>>> On 3/18/19 5:26 PM, Rodrigo Vivi wrote:
Hi Shaobo,
n Mon, Mar 18, 2019 at 05:01:10PM -0600, Shaobo He wrote:
> Hello everyone,
>
> My name is Shaobo He and I am a graduate student at University of Utah. I
> am
> using a static analysis tool to search for null pointer dereferences and
> came across a potentially invalid memory access in the file
> drivers/gpu/drm/i915/intel_crt.c: in function `intel_crt_detect_ddc`,
> function `intel_gmbus_get_adapter` can return a NULL pointer which is
if this happens we've done a terrible job on defining the platform...
> dereferenced by the call to `drm_get_edid` or `intel_gmbus_is_forced_bit`.
but it seems you are right... this will reach i2c_transfer in the end
and it will break everything after we gave the Warning...
> It seems that the return value of `intel_gmbus_get_adapter` is never
> NULL-checked. If so, it would be better to replace the branch to return a
> NULL pointer with something like `BUG_ON`.
what about just adding if (!i2c) return false
instead of BUG.
We already have the WARN to debug if this case ever happens.
Thanks,
Rodrigo.
>
> Please let me know if it makes sense. I am looking forward to your reply.
>
> Best,
> Shaobo
--
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Add Multi Segment Gamma Support
== Series Details ==
Series: Add Multi Segment Gamma Support
URL : https://patchwork.freedesktop.org/series/58169/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5770 -> Patchwork_12509
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12509 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12509, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58169/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12509:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> FAIL
- fi-pnv-d510:NOTRUN -> FAIL
- fi-bdw-gvtdvm: NOTRUN -> FAIL
- fi-hsw-peppy: NOTRUN -> FAIL
- fi-gdg-551: NOTRUN -> FAIL
- fi-snb-2520m: NOTRUN -> FAIL
- fi-hsw-4770:NOTRUN -> FAIL
- fi-whl-u: NOTRUN -> FAIL
- fi-icl-u3: NOTRUN -> FAIL
- fi-ivb-3770:NOTRUN -> FAIL
- fi-byt-j1900: NOTRUN -> FAIL
- fi-bsw-n3050: NOTRUN -> FAIL
- fi-blb-e6850: NOTRUN -> FAIL
- fi-bsw-kefka: NOTRUN -> FAIL
- fi-hsw-4770r: NOTRUN -> FAIL
- fi-byt-clapper: NOTRUN -> FAIL
- fi-bdw-5557u: NOTRUN -> FAIL
- fi-bwr-2160:NOTRUN -> FAIL
- fi-byt-n2820: NOTRUN -> FAIL
- fi-elk-e7500: NOTRUN -> FAIL
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-icl-y}: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12509 that come from known issues:
### IGT changes ###
Issues hit
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> FAIL [k.org#202107] / [k.org#202109]
- fi-bxt-j4205: NOTRUN -> FAIL [fdo#109516]
- fi-skl-iommu: NOTRUN -> FAIL [fdo#104108]
- fi-cfl-guc: NOTRUN -> FAIL [k.org#202107] / [k.org#202109]
- fi-kbl-7567u: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
- fi-skl-guc: NOTRUN -> FAIL [fdo#104108]
- fi-skl-6700k2: NOTRUN -> FAIL [fdo#104108]
- fi-kbl-x1275: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
- fi-cfl-8700k: NOTRUN -> FAIL [k.org#202107] / [k.org#202109]
- fi-skl-6600u: NOTRUN -> FAIL [fdo#104108]
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
- fi-apl-guc: NOTRUN -> FAIL [fdo#109373]
- fi-kbl-r: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
- fi-skl-6770hq: NOTRUN -> FAIL [fdo#104108]
- fi-kbl-guc: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
- fi-skl-gvtdvm: NOTRUN -> FAIL [fdo#104108]
- fi-snb-2600:NOTRUN -> FAIL [fdo#108929]
- fi-skl-6260u: NOTRUN -> FAIL [fdo#104108]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#108903]: https://bugs.freedesktop.org/show_bug.cgi?id=108903
[fdo#108904]: https://bugs.freedesktop.org/show_bug.cgi?id=108904
[fdo#108905]: https://bugs.freedesktop.org/show_bug.cgi?id=108905
[fdo#108929]: https://bugs.freedesktop.org/show_bug.cgi?id=108929
[fdo#109373]: https://bugs.freedesktop.org/show_bug.cgi?id=109373
[fdo#109516]: https://bugs.freedesktop.org/show_bug.cgi?id=109516
[k.org#202107]: https://bugzilla.kernel.org/show_bug.cgi?id=202107
[k.org#202109]: https://bugzilla.kernel.org/show_bug.cgi?id=202109
Participating hosts (44 -> 42)
--
Additional (2): fi-bsw-kefka fi-bsw-n3050
Missing(4): fi-kbl-soraka fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-
* Linux: CI_DRM_5770 -> Patchwork_12509
CI_DRM_5770: 7f60fa0ec6f20661a49a3eeed6e4b0a175783cf6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4888: 71ad19eb8fe4f0eecae3bf063e107293b90b9abc @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12509: d23e8eac8e99b570921ae2225b87f1cea6e4828f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d23e8eac8e99 drm/i915: Add multi segment gamma for icl
286cdabed18f drm/i915/icl: Add support for multi segmented gamma mode
cd708119e5a6 drm/i915/icl: Add register definitions for Multi Segmented gamma
103a131a2e19 drm/i915: Implement get set property handler for multi segment
gamma
e83f5dac54cc drm/i915: Add Support for Multi Segm
Re: [Intel-gfx] [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
tis 2019-03-19 klockan 14:00 +0530 skrev Uma Shankar:
> Multi Segment Gamma Mode is added in Gen11+ platforms.
> Added a property interface to enable that.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_drv.h| 1 +
> drivers/gpu/drm/i915/intel_color.c | 23 +++
> include/uapi/drm/i915_drm.h| 14 ++
> 3 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 02231ae..f20d418 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1736,6 +1736,7 @@ struct drm_i915_private {
> struct drm_property *force_audio_property;
>
> struct drm_property *gamma_mode_property;
> + struct drm_property *multi_segment_gamma_mode_property;
Seems to me both properties should be part of drm core?
> /* hda/i915 audio component */
> struct i915_audio_component *audio_component;
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 9d43d19..399d63d 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -149,6 +149,26 @@ static bool crtc_state_is_legacy_gamma(const
> struct intel_crtc_state *crtc_state
> drm_object_attach_property(&crtc->base.base, prop, 0);
> }
>
> +void
> +intel_attach_multi_segment_gamma_mode_property(struct intel_crtc
> *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_property *prop;
> +
> + prop = dev_priv->multi_segment_gamma_mode_property;
> + if (!prop) {
> + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB,
> +"Multi-segment Gamma",
> 0);
> + if (!prop)
> + return;
> +
> + dev_priv->multi_segment_gamma_mode_property = prop;
> + }
> +
> + drm_object_attach_property(&crtc->base.base, prop, 0);
> +}
> +
> /*
> * When using limited range, multiply the matrix given by userspace
> by
> * the matrix that we would use for the limited range.
> @@ -953,4 +973,7 @@ void intel_color_init(struct intel_crtc *crtc)
> INTEL_INFO(dev_priv)-
> >color.gamma_lut_size);
>
> intel_attach_gamma_mode_property(crtc);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + intel_attach_multi_segment_gamma_mode_property(crtc)
> ;
> }
> diff --git a/include/uapi/drm/i915_drm.h
> b/include/uapi/drm/i915_drm.h
> index aa2d4c7..8f1974e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1842,6 +1842,20 @@ struct drm_i915_query_topology_info {
> __u8 data[];
> };
>
> +/*
> + * Structure for muti segmented gamma lut
> + */
> +struct multi_segment_gamma_lut {
> + /* Number of Lut Segments */
> + __u8 segment_cnt;
> + /* Precison of LUT entries in bits */
> + __u8 precision_bits;
> + /* Pointer having number of LUT elements in each segment */
> + __u32 *segment_lut_cnt_ptr;
> + /* Pointer to store exact lut values for each segment */
> + __u32 *segment_lut_ptr;
> +};
>
And perhaps a variation of this as description for all gamma mode
types.
smime.p7s
Description: S/MIME cryptographic signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Clean up intel_color_check()
== Series Details ==
Series: drm/i915: Clean up intel_color_check()
URL : https://patchwork.freedesktop.org/series/58137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12502_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12502_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12502_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12502_full:
### IGT changes ###
Possible regressions
* igt@gem_create@create-clear:
- shard-hsw: PASS -> DMESG-WARN
* igt@runner@aborted:
- shard-hsw: NOTRUN -> FAIL
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@pixel-format-pipe-b-planes}:
- shard-iclb: PASS -> FAIL
Known issues
Here are the changes found in Patchwork_12502_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@fifo-bsd2:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +74
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-iclb: PASS -> INCOMPLETE [fdo#109766] / [fdo#109801]
* igt@gem_pread@stolen-uncached:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +21
* igt@gem_tiled_pread_pwrite:
- shard-iclb: PASS -> TIMEOUT [fdo#109673]
* igt@gem_wait@write-busy-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276]
* igt@i915_pm_rpm@debugfs-read:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@fences:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@system-suspend-devices:
- shard-iclb: PASS -> DMESG-WARN [fdo#109638]
* igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-hsw: PASS -> FAIL [fdo#106641]
- shard-snb: PASS -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-oldfb-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-c:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9
* igt@kms_busy@extended-pageflip-hang-newfb-render-f:
- shard-iclb: NOTRUN -> SKIP [fdo#109278]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chamelium@hdmi-crc-abgr:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +1
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-c-degamma:
- shard-iclb: NOTRUN -> FAIL [fdo#104782]
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739]
* igt@kms_cursor_crc@cursor-128x42-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
- shard-iclb: PASS -> FAIL [fdo#103355] +1
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_flip_tiling@flip-x-tiled:
- shard-iclb: PASS -> FAIL [fdo#108303]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +10
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#109247] +13
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +1
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
- shard-hsw: NOTRUN -> SKIP [fdo#109271] +9
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-skl: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane_al
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add Plane Color Properties (rev6)
== Series Details == Series: Add Plane Color Properties (rev6) URL : https://patchwork.freedesktop.org/series/30875/ State : warning == Summary == $ dim checkpatch origin/drm-tip ac8ffabdea94 drm: Add Enhanced Gamma LUT precision structure cb4da76aa060 drm: Add Plane Degamma properties -:180: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #180: FILE: drivers/gpu/drm/drm_atomic_uapi.c:577: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->degamma_lut, total: 0 errors, 0 warnings, 1 checks, 253 lines checked 6d1310f593e8 drm: Add Plane CTM property -:69: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #69: FILE: drivers/gpu/drm/drm_atomic_uapi.c:584: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->ctm, total: 0 errors, 0 warnings, 1 checks, 97 lines checked 874066e51de7 drm: Add Plane Gamma properties -:72: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #72: FILE: drivers/gpu/drm/drm_atomic_uapi.c:592: + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->gamma_lut, total: 0 errors, 0 warnings, 1 checks, 116 lines checked aa2c66edd9cb drm: Define helper function for plane color enabling a469bd374d08 drm/i915: Enable plane color features -:62: WARNING:LONG_LINE: line over 100 characters #62: FILE: drivers/gpu/drm/i915/intel_color.c:882: + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size, total: 0 errors, 1 warnings, 0 checks, 71 lines checked 3b9c169dbec3 drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms -:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #62: FILE: drivers/gpu/drm/i915/i915_reg.h:10170: +#define PLANE_GAMC(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe)) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #73: FILE: drivers/gpu/drm/i915/i915_reg.h:10181: +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ + _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) total: 0 errors, 0 warnings, 2 checks, 137 lines checked fe57d6db3259 drm/i915: Load plane color luts from atomic flip eba9f1c9b828 drm/i915: Add plane color capabilities 415f57b6a941 drm/i915/icl: Add ICL Plane Degamma Register definition -:24: WARNING:LONG_LINE: line over 100 characters #24: FILE: drivers/gpu/drm/i915/i915_reg.h:10190: +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) -:25: WARNING:LONG_LINE: line over 100 characters #25: FILE: drivers/gpu/drm/i915/i915_reg.h:10191: +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) -:27: WARNING:LONG_LINE: line over 100 characters #27: FILE: drivers/gpu/drm/i915/i915_reg.h:10193: +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\ -:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #27: FILE: drivers/gpu/drm/i915/i915_reg.h:10193: +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) -:28: WARNING:LONG_LINE: line over 100 characters #28: FILE: drivers/gpu/drm/i915/i915_reg.h:10194: + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) -:34: WARNING:LONG_LINE: line over 100 characters #34: FILE: drivers/gpu/drm/i915/i915_reg.h:10200: +#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B) -:35: WARNING:LONG_LINE: line over 100 characters #35: FILE: drivers/gpu/drm/i915/i915_reg.h:10201: +#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B) -:37: WARNING:LONG_LINE: line over 100 characters #37: FILE: drivers/gpu/drm/i915/i915_reg.h:10203: +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\ -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_reg.h:10203: +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_5(pipe)) -:38: WARNING:LONG_LINE: line over 100 characters #38: FILE: drivers/gpu/drm/i915/i915_reg.h:10204: +
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add Plane Color Properties (rev6)
== Series Details == Series: Add Plane Color Properties (rev6) URL : https://patchwork.freedesktop.org/series/30875/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm: Add Enhanced Gamma LUT precision structure +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) +drivers/gpu/drm/drm_color_mgmt.c:146:45: warning: expression using sizeof(void) Commit: drm: Add Plane Degamma properties Okay! Commit: drm: Add Plane CTM property Okay! Commit: drm: Add Plane Gamma properties Okay! Commit: drm: Define helper function for plane color enabling Okay! Commit: drm/i915: Enable plane color features -drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3564:16: warning: expression using sizeof(void) Commit: drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms Okay! Commit: drm/i915: Load plane color luts from atomic flip Okay! Commit: drm/i915: Add plane color capabilities Okay! Commit: drm/i915/icl: Add ICL Plane Degamma Register definition Okay! Commit: drm/i915/icl: Enable Plane Degamma +drivers/gpu/drm/i915/intel_color.c:635:55: warning: constant 0x7 is so big it is long Commit: drm/i915/icl: Add Plane Gamma Register Definitions Okay! Commit: drm/i915/icl: Implement Plane Gamma +drivers/gpu/drm/i915/intel_color.c:711:55: warning: constant 0x7 is so big it is long Commit: drm/i915: Enable Plane Gamma/Degamma Okay! Commit: drm/i915: Define Plane CSC Registers Okay! Commit: drm/i915: Enable Plane CSC +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:635:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:643:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:646:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:649:41: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_color.c:651:46: warning: too many warnings ___ Intel-
[Intel-gfx] ✓ Fi.CI.BAT: success for Add Plane Color Properties (rev6)
== Series Details == Series: Add Plane Color Properties (rev6) URL : https://patchwork.freedesktop.org/series/30875/ State : success == Summary == CI Bug Log - changes from CI_DRM_5771 -> Patchwork_12510 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/30875/revisions/6/mbox/ Known issues Here are the changes found in Patchwork_12510 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@userptr: - fi-kbl-8809g: PASS -> DMESG-WARN [fdo#108965] * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-kbl-7567u: NOTRUN -> SKIP [fdo#109271] +33 * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: PASS -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-skl-6260u: PASS -> INCOMPLETE [fdo#104108] Possible fixes * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1 * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#107362] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (47 -> 37) -- Additional (1): fi-kbl-7567u Missing(11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bxt-j4205 fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_5771 -> Patchwork_12510 CI_DRM_5771: c1500eaf9d004539bbc2b7458c6cbe3f6a6147dc @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4888: 71ad19eb8fe4f0eecae3bf063e107293b90b9abc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12510: 0193721b12d3e2e551e496c40ebf312a2ad8d577 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0193721b12d3 drm/i915: Enable Plane CSC 723fb9c0bb23 drm/i915: Define Plane CSC Registers d4c386908867 drm/i915: Enable Plane Gamma/Degamma d2c749cba6ef drm/i915/icl: Implement Plane Gamma dc49d1b1bc11 drm/i915/icl: Add Plane Gamma Register Definitions 6db8c958bceb drm/i915/icl: Enable Plane Degamma 415f57b6a941 drm/i915/icl: Add ICL Plane Degamma Register definition eba9f1c9b828 drm/i915: Add plane color capabilities fe57d6db3259 drm/i915: Load plane color luts from atomic flip 3b9c169dbec3 drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms a469bd374d08 drm/i915: Enable plane color features aa2c66edd9cb drm: Define helper function for plane color enabling 874066e51de7 drm: Add Plane Gamma properties 6d1310f593e8 drm: Add Plane CTM property cb4da76aa060 drm: Add Plane Degamma properties ac8ffabdea94 drm: Add Enhanced Gamma LUT precision structure == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12510/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: Inline skl_build_pipe_wm() into its only caller
On Mon, Mar 18, 2019 at 05:11:30PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:44PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > skl_build_pipe_wm() is quite pointless now. Just inline it into
>
> I think you actually mean skl_update_pipe_wm(), right?
Indeed.
>
> The code change looks good, so with an updated commit message,
>
> Reviewed-by: Matt Roper
Thanks.
>
> > skl_compute_wm().
> >
> > Cc: Neel Desai
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 32 ++--
> > 1 file changed, 6 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 80e964f7de58..ac0ca150a0d5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5257,23 +5257,6 @@ bool skl_ddb_allocation_overlaps(const struct
> > skl_ddb_entry *ddb,
> > return false;
> > }
> >
> > -static int skl_update_pipe_wm(struct intel_crtc_state *cstate,
> > - const struct skl_pipe_wm *old_pipe_wm,
> > - struct skl_pipe_wm *pipe_wm, /* out */
> > - bool *changed /* out */)
> > -{
> > - struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
> > - int ret;
> > -
> > - ret = skl_build_pipe_wm(cstate);
> > - if (ret)
> > - return ret;
> > -
> > - *changed = !skl_pipe_wm_equals(crtc, old_pipe_wm, pipe_wm);
> > -
> > - return 0;
> > -}
> > -
> > static u32
> > pipes_modified(struct intel_atomic_state *state)
> > {
> > @@ -5612,10 +5595,9 @@ static int
> > skl_compute_wm(struct intel_atomic_state *state)
> > {
> > struct intel_crtc *crtc;
> > - struct intel_crtc_state *cstate;
> > + struct intel_crtc_state *new_crtc_state;
> > struct intel_crtc_state *old_crtc_state;
> > struct skl_ddb_values *results = &state->wm_results;
> > - struct skl_pipe_wm *pipe_wm;
> > bool changed = false;
> > int ret, i;
> >
> > @@ -5633,12 +5615,8 @@ skl_compute_wm(struct intel_atomic_state *state)
> > * pipe allocations had to change.
> > */
> > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > - cstate, i) {
> > - const struct skl_pipe_wm *old_pipe_wm =
> > - &old_crtc_state->wm.skl.optimal;
> > -
> > - pipe_wm = &cstate->wm.skl.optimal;
> > - ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
> > &changed);
> > + new_crtc_state, i) {
> > + ret = skl_build_pipe_wm(new_crtc_state);
> > if (ret)
> > return ret;
> >
> > @@ -5646,7 +5624,9 @@ skl_compute_wm(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > - if (changed)
> > + if (!skl_pipe_wm_equals(crtc,
> > + &old_crtc_state->wm.skl.optimal,
> > + &new_crtc_state->wm.skl.optimal))
> > results->dirty_pipes |= drm_crtc_mask(&crtc->base);
> > }
> >
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
--
Ville Syrjälä
Intel
___
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Re: [Intel-gfx] [PATCH 4/9] drm/i915: Allocate enough DDB for the cursor
On Tue, Mar 12, 2019 at 10:58:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we just assume that 32 or 8 blocks of ddb is sufficient
> for the cursor. The 32 might be, but the 8 is certainly not. The
> minimum we need is at least what level 0 watermarks need, but that
> is a bit restrictive, so instead let's calculate what level 7
> would need for a 256x256 cursor. We'll use that to determine the
> fixed ddb allocation for the cursor. This way the cursor will never
> be responsible for missing out on deeper power saving states.
>
> Cc: Neel Desai
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_pm.c | 33 -
> 1 file changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9e7b4412f7a8..ae9a0ce4dcb9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3924,12 +3924,35 @@ skl_ddb_get_pipe_allocation_limits(struct
> drm_i915_private *dev_priv,
> alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
> }
>
> -static unsigned int skl_cursor_allocation(int num_active)
> +static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> + int width, const struct drm_format_info
> *format,
> + u64 modifier, unsigned int rotation,
> + u32 plane_pixel_rate, struct skl_wm_params *wp,
> + int color_plane);
> +static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
> + int level,
> + const struct skl_wm_params *wp,
> + const struct skl_wm_level *result_prev,
> + struct skl_wm_level *result /* out */);
> +
> +static unsigned int
> +skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> + int num_active)
> {
> - if (num_active == 1)
> - return 32;
> + struct skl_wm_level wm = {};
> + struct skl_wm_params wp;
> + int ret;
> +
> + ret = skl_compute_wm_params(crtc_state, 256,
> + drm_format_info(DRM_FORMAT_ARGB),
> + DRM_FORMAT_MOD_LINEAR,
> + DRM_MODE_ROTATE_0,
> + crtc_state->pixel_rate, &wp, 0);
> + WARN_ON(ret);
> +
> + skl_compute_plane_wm(crtc_state, 7, &wp, &wm, &wm);
Hmm. This borked if latency[7]==0. I guess I actually need to loop
here...
>
> - return 8;
> + return max_t(int, num_active == 1 ? 32 : 8, wm.min_ddb_alloc);
> }
>
> static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> @@ -4354,7 +4377,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - total[PLANE_CURSOR] = skl_cursor_allocation(num_active);
> + total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
> alloc_size -= total[PLANE_CURSOR];
> cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> alloc->end - total[PLANE_CURSOR];
> --
> 2.19.2
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/icl: pass cfgcr* register around instead of pll_id
On Mon, Mar 18, 2019 at 04:33:51PM -0700, Lucas De Marchi wrote:
> On Mon, Mar 18, 2019 at 08:53:23PM +0200, Ville Syrjälä wrote:
> >On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
> >> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
> >> >On Fri, Mar 15, 2019 at 05:45:26PM -0700, Lucas De Marchi wrote:
> >> >> The caller already knows what platform that is and what register should
> >> >> be used. Instead of keep adding if/else chains on a leaf functions,
> >> >> let the caller pass the register.
> >> >>
> >> >> We read cfgcr0 twice for CNL, but we were already doing that anyway.
> >> >>
> >> >> icl_calc_dp_combo_pll_link() is only used for ICL, but let's keep
> >> >> consistency with cnl_calc_wrpll_link().
> >> >>
> >> >> Signed-off-by: Lucas De Marchi
> >> >> ---
> >> >> drivers/gpu/drm/i915/icl_dsi.c| 4 +++-
> >> >> drivers/gpu/drm/i915/intel_ddi.c | 25 ++---
> >> >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++---
> >> >> drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +-
> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> >> >> 5 files changed, 22 insertions(+), 17 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> >> >> b/drivers/gpu/drm/i915/icl_dsi.c
> >> >> index beb30d9a855c..28f5da697693 100644
> >> >> --- a/drivers/gpu/drm/i915/icl_dsi.c
> >> >> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> >> >> @@ -1183,7 +1183,9 @@ static void gen11_dsi_get_config(struct
> >> >> intel_encoder *encoder,
> >> >>
> >> >> /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
> >> >> pll_id = intel_get_shared_dpll_id(dev_priv,
> >> >> pipe_config->shared_dpll);
> >> >> - pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
> >> >> + pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv,
> >> >> +
> >> >> ICL_DPLL_CFGCR0(pll_id),
> >> >> +
> >> >> ICL_DPLL_CFGCR1(pll_id));
> >> >> pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> >> >> pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
> >> >> }
> >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> >> >> b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> index 69aa0d148795..24675ef8b262 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> >> @@ -1304,18 +1304,13 @@ static int skl_calc_wrpll_link(struct
> >> >> drm_i915_private *dev_priv,
> >> >> }
> >> >>
> >> >> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >> >> - enum intel_dpll_id pll_id)
> >> >> + i915_reg_t cfgcr0_reg, i915_reg_t cfgcr1_reg)
> >> >> {
> >> >> u32 cfgcr0, cfgcr1;
> >> >> u32 p0, p1, p2, dco_freq, ref_clock;
> >> >>
> >> >> - if (INTEL_GEN(dev_priv) >= 11) {
> >> >> - cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
> >> >> - cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
> >> >> - } else {
> >> >> - cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
> >> >> - cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
> >> >> - }
> >> >> + cfgcr0 = I915_READ(cfgcr0_reg);
> >> >> + cfgcr1 = I915_READ(cfgcr1_reg);
> >> >
> >> >Don't we alredy have the dpll state read out at this point?
> >>
> >> nops.
> >
> >We must have it since bxt is already using it. Either that or bxt is
> >broken.
>
> oh.. I think you forgot to push
> https://patchwork.freedesktop.org/series/56354/
Ah yes. Now pushed. Thanks for reviewing it.
>
> I guess it will also make my life easier here.
>
> Lucas De Marchi
>
> >
> >--
> >Ville Syrjälä
> >Intel
--
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Re: [Intel-gfx] [PATCH] drm/i915: Handle YUV subpixel support better
On Tue, Mar 19, 2019 at 08:28:58AM +0100, Maarten Lankhorst wrote:
> Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> > On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
> >> Op 18-03-2019 om 15:18 schreef Ville Syrjälä:
> >>> On Mon, Mar 18, 2019 at 03:07:18PM +0100, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 29 +++--
> 1 file changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 268fb34ff0e2..862fc172042f 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -269,7 +269,8 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> struct drm_rect *src = &plane_state->base.src;
> -u32 src_x, src_y, src_w, src_h;
> +u32 src_x, src_y, src_w, src_h, hsub, vsub;
> +bool rotated =
> drm_rotation_90_or_270(plane_state->base.rotation);
>
> /*
> * Hardware doesn't handle subpixel coordinates.
> @@ -287,18 +288,26 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> src->y1 = src_y << 16;
> src->y2 = (src_y + src_h) << 16;
>
> -if (fb->format->is_yuv &&
> -(src_x & 1 || src_w & 1)) {
> -DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2
> for YUV planes\n",
> - src_x, src_w);
> +if (!fb->format->is_yuv)
> +return 0;
> +
> +/* YUV specific checks */
> +if (!rotated) {
> +hsub = fb->format->hsub;
> +vsub = fb->format->vsub;
> +} else {
> +hsub = vsub = max(fb->format->hsub, fb->format->vsub);
> >>> Why this? From the looks of things there should be no need to deal with
> >>> rotation in this function at all.
> >> I wrote a dumb test that fails if I rotate YUYV.
> >>
> >> https://patchwork.freedesktop.org/patch/286170/
> >>
> >> Corrupted image:
> >>
> >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_rotation(90°)
> >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_position(18,33)
> >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_size(44x65)
> >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_position(64,64)
> >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_size (256x256)
> >>
> >> I had a 80x128 fb, only showing the center part which should be white,
> >> with a black border around it to cause CRC errors if we mess up clipping.
> >>
> >> The scaling works fine, but the clipping does not in this case. I am
> >> getting a corrupted plane on screen which is mostly white, but with black
> >> dots in each tile.
> >>
> >> Scaling just magnifies this corruption. :)
> > Hmm. I just poked my KBL a bit and it is also showing curious
> > behaviour. Even with 90/270 rotation it is in fact the TILEOFF
> > X coordinate that needs to be even (actually the hw just appears
> > to ignore the lsb). I can make the Y coordinate odd, and the image
> > still looks correct to my eyes. So feels like someone forgot to
> > to remove a (x&~1) from the hw when they added the 90/270 rotation,
> > and yet they went to the trouble of making odd Y coordinates work
> > correctly. Quite stange.
> >
> > Width/height being odd seems to handled just fine by the hw.
> >
> Hmm does that mean we should keep the original checks in place while checking
> format->h/vsub, and on top reject the unrotated Y coordinate being a multiple
> of hsub when rotating?
Not quite sure. Based on what I see we could actually just swap the
coordinates (or do the check after the coordinates are already rotated)
and it should still work. But I didn't check if that would still work
when the scaler is involved.
--
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[Intel-gfx] [PATCH 17/18] drm/i915/execlists: Virtual engine bonding
Some users require that when a master batch is executed on one particular
engine, a companion batch is run simultaneously on a specific slave
engine. For this purpose, we introduce virtual engine bonding, allowing
maps of master:slaves to be constructed to constrain which physical
engines a virtual engine may select given a fence on a master engine.
For the moment, we continue to ignore the issue of preemption deferring
the master request for later. Ideally, we would like to then also remove
the slave and run something else rather than have it stall the pipeline.
With load balancing, we should be able to move workload around it, but
there is a similar stall on the master pipeline while it may wait for
the slave to be executed. At the cost of more latency for the bonded
request, it may be interesting to launch both on their engines in
lockstep. (Bubbles abound.)
Opens: Also what about bonding an engine as its own master? It doesn't
break anything internally, so allow the silliness.
v2: Emancipate the bonds
v3: Couple in delayed scheduling for the selftests
v4: Handle invalid mutually exclusive bonding
v5: Mention what the uapi does
v6: s/nbond/num_bonds/
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 50 +
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/i915_request.h | 3 +
drivers/gpu/drm/i915/intel_engine_types.h | 7 +
drivers/gpu/drm/i915/intel_lrc.c | 152 ++
drivers/gpu/drm/i915/intel_lrc.h | 4 +
drivers/gpu/drm/i915/selftests/intel_lrc.c| 185 ++
drivers/gpu/drm/i915/selftests/lib_sw_fence.c | 3 +
include/uapi/drm/i915_drm.h | 33
9 files changed, 438 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8d8fcc8c7a86..20deee296d04 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1519,8 +1519,58 @@ set_engines__load_balance(struct i915_user_extension
__user *base, void *data)
return 0;
}
+static int
+set_engines__bond(struct i915_user_extension __user *base, void *data)
+{
+ struct i915_context_engines_bond __user *ext =
+ container_of_user(base, typeof(*ext), base);
+ const struct set_engines *set = data;
+ unsigned int idx, class, instance;
+ struct intel_engine_cs *master;
+ u64 siblings;
+ int err;
+
+ if (get_user(idx, &ext->virtual_index))
+ return -EFAULT;
+
+ if (idx >= set->num_engines)
+ return -EINVAL;
+
+ idx = array_index_nospec(idx, set->num_engines);
+ if (!set->engines[idx])
+ return -EINVAL;
+
+ /*
+* A non-virtual engine has 0 siblings to choose between; and submit
+* fence will always be directed to the one engine.
+*/
+ if (!intel_engine_is_virtual(set->engines[idx]))
+ return 0;
+
+ err = check_user_mbz(&ext->mbz);
+ if (err)
+ return err;
+
+ if (get_user(class, &ext->master_class))
+ return -EFAULT;
+
+ if (get_user(instance, &ext->master_instance))
+ return -EFAULT;
+
+ master = intel_engine_lookup_user(set->ctx->i915, class, instance);
+ if (!master)
+ return -EINVAL;
+
+ if (get_user(siblings, &ext->sibling_mask))
+ return -EFAULT;
+
+ return intel_virtual_engine_attach_bond(set->engines[idx],
+ master, siblings);
+}
+
static const i915_user_extension_fn set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance,
+ [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
static int
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 3faf06d2a9b0..06e5c2a50080 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -742,6 +742,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->batch = NULL;
rq->capture_list = NULL;
rq->waitboost = false;
+ rq->execution_mask = ALL_ENGINES;
/*
* Reserve space in the ring buffer for all the commands required to
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index d4f6b2940130..5bdab6881b13 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -32,6 +32,8 @@
#include "i915_selftest.h"
#include "i915_sw_fence.h"
+#include "intel_engine_types.h"
+
#include
struct drm_file;
@@ -145,6 +147,7 @@ struct i915_request {
*/
struct i915_sched_node sched;
struct i915_dependency dep;
+ intel_engine_mask_t execution_mask;
/*
* A convenience pointer to the
[Intel-gfx] [PATCH 01/18] drm/i915/selftests: Provide stub reset functions
If a test fails, we quite often mark the device as wedged. Provide the
stub functions so that we can wedge the mock device, and avoid exploding
on test failures.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109981
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/selftests/mock_engine.c | 36
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.c
b/drivers/gpu/drm/i915/selftests/mock_engine.c
index 639d36eb904a..61744819172b 100644
--- a/drivers/gpu/drm/i915/selftests/mock_engine.c
+++ b/drivers/gpu/drm/i915/selftests/mock_engine.c
@@ -198,6 +198,37 @@ static void mock_submit_request(struct i915_request
*request)
spin_unlock_irqrestore(&engine->hw_lock, flags);
}
+static void mock_reset_prepare(struct intel_engine_cs *engine)
+{
+}
+
+static void mock_reset(struct intel_engine_cs *engine, bool stalled)
+{
+ GEM_BUG_ON(stalled);
+}
+
+static void mock_reset_finish(struct intel_engine_cs *engine)
+{
+}
+
+static void mock_cancel_requests(struct intel_engine_cs *engine)
+{
+ struct i915_request *request;
+ unsigned long flags;
+
+ spin_lock_irqsave(&engine->timeline.lock, flags);
+
+ /* Mark all submitted requests as skipped. */
+ list_for_each_entry(request, &engine->timeline.requests, sched.link) {
+ if (!i915_request_signaled(request))
+ dma_fence_set_error(&request->fence, -EIO);
+
+ i915_request_mark_complete(request);
+ }
+
+ spin_unlock_irqrestore(&engine->timeline.lock, flags);
+}
+
struct intel_engine_cs *mock_engine(struct drm_i915_private *i915,
const char *name,
int id)
@@ -223,6 +254,11 @@ struct intel_engine_cs *mock_engine(struct
drm_i915_private *i915,
engine->base.emit_fini_breadcrumb = mock_emit_breadcrumb;
engine->base.submit_request = mock_submit_request;
+ engine->base.reset.prepare = mock_reset_prepare;
+ engine->base.reset.reset = mock_reset;
+ engine->base.reset.finish = mock_reset_finish;
+ engine->base.cancel_requests = mock_cancel_requests;
+
if (i915_timeline_init(i915,
&engine->base.timeline,
engine->base.name,
--
2.20.1
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[Intel-gfx] [PATCH 18/18] drm/i915: Allow specification of parallel execbuf
There is a desire to split a task onto two engines and have them run at
the same time, e.g. scanline interleaving to spread the workload evenly.
Through the use of the out-fence from the first execbuf, we can
coordinate secondary execbuf to only become ready simultaneously with
the first, so that with all things idle the second execbufs are executed
in parallel with the first. The key difference here between the new
EXEC_FENCE_SUBMIT and the existing EXEC_FENCE_IN is that the in-fence
waits for the completion of the first request (so that all of its
rendering results are visible to the second execbuf, the more common
userspace fence requirement).
Since we only have a single input fence slot, userspace cannot mix an
in-fence and a submit-fence. It has to use one or the other! This is not
such a harsh requirement, since by virtue of the submit-fence, the
secondary execbuf inherit all of the dependencies from the first
request, and for the application the dependencies should be common
between the primary and secondary execbuf.
Suggested-by: Tvrtko Ursulin
Testcase: igt/gem_exec_fence/parallel
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 25 +-
include/uapi/drm/i915_drm.h| 17 ++-
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9a0fa3b21e9d..e7fdd9926266 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -421,6 +421,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
case I915_PARAM_HAS_EXEC_CAPTURE:
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
+ case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 66b3921cc8bd..3e9a6892a7a9 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2281,6 +2281,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
{
struct i915_execbuffer eb;
struct dma_fence *in_fence = NULL;
+ struct dma_fence *exec_fence = NULL;
struct sync_file *out_fence = NULL;
intel_wakeref_t wakeref;
int out_fence_fd = -1;
@@ -2324,11 +2325,24 @@ i915_gem_do_execbuffer(struct drm_device *dev,
return -EINVAL;
}
+ if (args->flags & I915_EXEC_FENCE_SUBMIT) {
+ if (in_fence) {
+ err = -EINVAL;
+ goto err_in_fence;
+ }
+
+ exec_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
+ if (!exec_fence) {
+ err = -EINVAL;
+ goto err_in_fence;
+ }
+ }
+
if (args->flags & I915_EXEC_FENCE_OUT) {
out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
if (out_fence_fd < 0) {
err = out_fence_fd;
- goto err_in_fence;
+ goto err_exec_fence;
}
}
@@ -2460,6 +2474,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_request;
}
+ if (exec_fence) {
+ err = i915_request_await_execution(eb.request, exec_fence,
+ eb.engine->bond_execute);
+ if (err < 0)
+ goto err_request;
+ }
+
if (fences) {
err = await_fence_array(&eb, fences);
if (err)
@@ -2520,6 +2541,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
err_out_fence:
if (out_fence_fd != -1)
put_unused_fd(out_fence_fd);
+err_exec_fence:
+ dma_fence_put(exec_fence);
err_in_fence:
dma_fence_put(in_fence);
return err;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 0d9ca4fb9edb..08f680dd2b1c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -593,6 +593,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1115,7 +1121,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
-#define _
[Intel-gfx] [PATCH 02/18] drm/i915: Flush pages on acquisition
When we return pages to the system, we ensure that they are marked as
being in the CPU domain since any external access is uncontrolled and we
must assume the worst. This means that we need to always flush the pages
on acquisition if we need to use them on the GPU, and from the beginning
have used set-domain. Set-domain is overkill for the purpose as it is a
general synchronisation barrier, but our intent is to only flush the
pages being swapped in. If we move that flush into the pages acquisition
phase, we know then that when we have obj->mm.pages, they are coherent
with the GPU and need only maintain that status without resorting to
heavy handed use of set-domain.
The principle knock-on effect for userspace is through mmap-gtt
pagefaulting. Our uAPI has always implied that the GTT mmap was async
(especially as when any pagefault occurs is unpredicatable to userspace)
and so userspace had to apply explicit domain control itself
(set-domain). However, swapping is transparent to the kernel, and so on
first fault we need to acquire the pages and make them coherent for
access through the GTT. Our use of set-domain here leaks into the uABI
that the first pagefault was synchronous. This is unintentional and
baring a few igt should be unoticed, nevertheless we bump the uABI
version for mmap-gtt to reflect the change in behaviour.
Another implication of the change is that gem_create() is presumed to
create an object that is coherent with the CPU and is in the CPU write
domain, so a set-domain(CPU) following a gem_create() would be a minor
operation that merely checked whether we could allocate all pages for
the object. On applying this change, a set-domain(CPU) causes a clflush
as we acquire the pages. This will have a small impact on mesa as we move
the clflush here on !llc from execbuf time to create, but that should
have minimal performance impact as the same clflush exists but is now
done early and because of the clflush issue, userspace recycles bo and
so should resist allocating fresh objects.
Internally, the presumption that objects are created in the CPU
write-domain and remain so through writes to obj->mm.mapping is more
prevalent than I expect; but easy enough to catch and apply a manual
flush.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Daniele Ceraolo Spurio
Cc: Antonio Argenziano
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++
drivers/gpu/drm/i915/i915_gem.c | 57 -
drivers/gpu/drm/i915/i915_gem_dmabuf.c| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 7 +--
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 4 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 63 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 62 +++---
drivers/gpu/drm/i915/selftests/huge_pages.c | 5 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 17 ++---
.../gpu/drm/i915/selftests/i915_gem_dmabuf.c | 1 +
.../gpu/drm/i915/selftests/i915_gem_evict.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 14 ++---
drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 5 +-
.../drm/i915/selftests/intel_workarounds.c| 3 +
18 files changed, 127 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c65c2e6649df..395aa9d5ba02 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2959,6 +2959,14 @@ i915_coherent_map_type(struct drm_i915_private *i915)
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
enum i915_map_type type);
+void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
+unsigned long offset,
+unsigned long size);
+static inline void i915_gem_object_flush_map(struct drm_i915_gem_object *obj)
+{
+ __i915_gem_object_flush_map(obj, 0, obj->base.size);
+}
+
/**
* i915_gem_object_unpin_map - releases an earlier mapping
* @obj: the object to unmap
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b7086c8d4726..41d96414ef18 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1713,6 +1713,9 @@ static unsigned int tile_row_pages(const struct
drm_i915_gem_object *obj)
* 2 - Recognise WC as a separate cache domain so that we can flush the
* delayed writes via GTT before performing direct access via WC.
*
+ * 3 - Remove implicit set-domain(GTT) and synchronisation on initial
+ * pagefault; swapin remains transparent.
+ *
* Restrictions:
*
* * snoopable objects cannot be accessed via the GTT. It can cause machine
@@ -1740,7 +1743,7 @@ static unsig
[Intel-gfx] [PATCH 04/18] drm/i915: Separate GEM context construction and registration to userspace
In later patches, it became apparent that userspace can see a partially
constructed GEM context and begin using it before it was ready, to much
hilarity. Close this window of opportunity by lifting the registration of
the context with userspace (the insertion of the context into the filp's
idr) to the very end of the CONTEXT_CREATE ioctl.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 138 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 8 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 12 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 17 ++-
7 files changed, 111 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2fa24326307a..dff4220df911 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -337,15 +337,13 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
}
static struct i915_gem_context *
-__create_hw_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+__create_context(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
int i;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
- if (ctx == NULL)
+ if (!ctx)
return ERR_PTR(-ENOMEM);
kref_init(&ctx->ref);
@@ -362,29 +360,6 @@ __create_hw_context(struct drm_i915_private *dev_priv,
INIT_LIST_HEAD(&ctx->handles_list);
INIT_LIST_HEAD(&ctx->hw_id_link);
- /* Default context will never have a file_priv */
- ret = DEFAULT_CONTEXT_HANDLE;
- if (file_priv) {
- ret = idr_alloc(&file_priv->context_idr, ctx,
- DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
- if (ret < 0)
- goto err_lut;
- }
- ctx->user_handle = ret;
-
- ctx->file_priv = file_priv;
- if (file_priv) {
- ctx->pid = get_task_pid(current, PIDTYPE_PID);
- ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
- current->comm,
- pid_nr(ctx->pid),
- ctx->user_handle);
- if (!ctx->name) {
- ret = -ENOMEM;
- goto err_pid;
- }
- }
-
/* NB: Mark all slices as needing a remap so that when the context first
* loads it will restore whatever remap state already exists. If there
* is no remap info, it will be a NOP. */
@@ -401,25 +376,10 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
return ctx;
-
-err_pid:
- put_pid(ctx->pid);
- idr_remove(&file_priv->context_idr, ctx->user_handle);
-err_lut:
- context_close(ctx);
- return ERR_PTR(ret);
-}
-
-static void __destroy_hw_context(struct i915_gem_context *ctx,
-struct drm_i915_file_private *file_priv)
-{
- idr_remove(&file_priv->context_idr, ctx->user_handle);
- context_close(ctx);
}
static struct i915_gem_context *
-i915_gem_create_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+i915_gem_create_context(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
@@ -428,18 +388,18 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
/* Reap the most stale context */
contexts_free_first(dev_priv);
- ctx = __create_hw_context(dev_priv, file_priv);
+ ctx = __create_context(dev_priv);
if (IS_ERR(ctx))
return ctx;
if (HAS_FULL_PPGTT(dev_priv)) {
struct i915_hw_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(dev_priv, file_priv);
+ ppgtt = i915_ppgtt_create(dev_priv);
if (IS_ERR(ppgtt)) {
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
- __destroy_hw_context(ctx, file_priv);
+ context_close(ctx);
return ERR_CAST(ppgtt);
}
@@ -475,7 +435,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
if (ret)
return ERR_PTR(ret);
- ctx = i915_gem_create_context(to_i915(dev), NULL);
+ ctx = i915_gem_create_context(to_i915(dev));
if (IS_ERR(ctx))
goto out;
@@ -511,7 +471,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
struct i915_gem_context *ctx;
[Intel-gfx] [PATCH 11/18] drm/i915: Allow contexts to share a single timeline across all engines
Previously, our view has been always to run the engines independently
within a context. (Multiple engines happened before we had contexts and
timelines, so they always operated independently and that behaviour
persisted into contexts.) However, at the user level the context often
represents a single timeline (e.g. GL contexts) and userspace must
ensure that the individual engines are serialised to present that
ordering to the client (or forgot about this detail entirely and hope no
one notices - a fair ploy if the client can only directly control one
engine themselves ;)
In the next patch, we will want to construct a set of engines that
operate as one, that have a single timeline interwoven between them, to
present a single virtual engine to the user. (They submit to the virtual
engine, then we decide which engine to execute on based.)
To that end, we want to be able to create contexts which have a single
timeline (fence context) shared between all engines, rather than multiple
timelines.
v2: Move the specialised timeline ordering to its own function.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 31 +--
drivers/gpu/drm/i915/i915_gem_context_types.h | 2 +
drivers/gpu/drm/i915/i915_request.c | 80 +--
drivers/gpu/drm/i915/i915_request.h | 5 +-
drivers/gpu/drm/i915/i915_sw_fence.c | 39 +++--
drivers/gpu/drm/i915/i915_sw_fence.h | 13 ++-
drivers/gpu/drm/i915/intel_lrc.c | 5 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
include/uapi/drm/i915_drm.h | 3 +-
9 files changed, 138 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 0d16edbb38c3..fc1f64e19507 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -238,6 +238,9 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
rbtree_postorder_for_each_entry_safe(it, n, &ctx->hw_contexts, node)
intel_context_put(it);
+ if (ctx->timeline)
+ i915_timeline_put(ctx->timeline);
+
kfree(ctx->name);
put_pid(ctx->pid);
@@ -403,12 +406,16 @@ static void __assign_ppgtt(struct i915_gem_context *ctx,
}
static struct i915_gem_context *
-i915_gem_create_context(struct drm_i915_private *dev_priv)
+i915_gem_create_context(struct drm_i915_private *dev_priv, unsigned int flags)
{
struct i915_gem_context *ctx;
lockdep_assert_held(&dev_priv->drm.struct_mutex);
+ if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE &&
+ !HAS_EXECLISTS(dev_priv))
+ return ERR_PTR(-EINVAL);
+
/* Reap the most stale context */
contexts_free_first(dev_priv);
@@ -431,6 +438,18 @@ i915_gem_create_context(struct drm_i915_private *dev_priv)
i915_ppgtt_put(ppgtt);
}
+ if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
+ struct i915_timeline *timeline;
+
+ timeline = i915_timeline_create(dev_priv, NULL);
+ if (IS_ERR(timeline)) {
+ context_close(ctx);
+ return ERR_CAST(timeline);
+ }
+
+ ctx->timeline = timeline;
+ }
+
trace_i915_context_create(ctx);
return ctx;
@@ -459,7 +478,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
if (ret)
return ERR_PTR(ret);
- ctx = i915_gem_create_context(to_i915(dev));
+ ctx = i915_gem_create_context(to_i915(dev), 0);
if (IS_ERR(ctx))
goto out;
@@ -495,7 +514,7 @@ i915_gem_context_create_kernel(struct drm_i915_private
*i915, int prio)
struct i915_gem_context *ctx;
int err;
- ctx = i915_gem_create_context(i915);
+ ctx = i915_gem_create_context(i915, 0);
if (IS_ERR(ctx))
return ctx;
@@ -658,7 +677,7 @@ int i915_gem_context_open(struct drm_i915_private *i915,
idr_init_base(&file_priv->vm_idr, 1);
mutex_lock(&i915->drm.struct_mutex);
- ctx = i915_gem_create_context(i915);
+ ctx = i915_gem_create_context(i915, 0);
mutex_unlock(&i915->drm.struct_mutex);
if (IS_ERR(ctx)) {
err = PTR_ERR(ctx);
@@ -800,7 +819,7 @@ last_request_on_engine(struct i915_timeline *timeline,
rq = i915_active_request_raw(&timeline->last_request,
&engine->i915->drm.struct_mutex);
- if (rq && rq->engine == engine) {
+ if (rq && rq->engine->mask & engine->mask) {
GEM_TRACE("last request on engine %s: %llx:%llu\n",
engine->name, rq->fence.context, rq->fence.seqno);
GEM_BUG_ON(rq->timeline != timeline);
@@ -1520,7 +1539,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void
[Intel-gfx] [PATCH 16/18] drm/i915: Extend execution fence to support a callback
In the next patch, we will want to configure the slave request
depending on which physical engine the master request is executed on.
For this, we introduce a callback from the execute fence to convey this
information.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 84 +++--
drivers/gpu/drm/i915/i915_request.h | 4 ++
2 files changed, 83 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index e9c2094ab8ea..3faf06d2a9b0 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -38,6 +38,8 @@ struct execute_cb {
struct list_head link;
struct irq_work work;
struct i915_sw_fence *fence;
+ void (*hook)(struct i915_request *rq, struct dma_fence *signal);
+ struct i915_request *signal;
};
static struct i915_global_request {
@@ -342,6 +344,17 @@ static void irq_execute_cb(struct irq_work *wrk)
kmem_cache_free(global.slab_execute_cbs, cb);
}
+static void irq_execute_cb_hook(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ cb->hook(container_of(cb->fence, struct i915_request, submit),
+&cb->signal->fence);
+ i915_request_put(cb->signal);
+
+ irq_execute_cb(wrk);
+}
+
static void __notify_execute_cb(struct i915_request *rq)
{
struct execute_cb *cb;
@@ -368,14 +381,19 @@ static void __notify_execute_cb(struct i915_request *rq)
}
static int
-i915_request_await_execution(struct i915_request *rq,
-struct i915_request *signal,
-gfp_t gfp)
+__i915_request_await_execution(struct i915_request *rq,
+ struct i915_request *signal,
+ void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal),
+ gfp_t gfp)
{
struct execute_cb *cb;
- if (i915_request_is_active(signal))
+ if (i915_request_is_active(signal)) {
+ if (hook)
+ hook(rq, &signal->fence);
return 0;
+ }
cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
if (!cb)
@@ -385,8 +403,18 @@ i915_request_await_execution(struct i915_request *rq,
i915_sw_fence_await(cb->fence);
init_irq_work(&cb->work, irq_execute_cb);
+ if (hook) {
+ cb->hook = hook;
+ cb->signal = i915_request_get(signal);
+ cb->work.func = irq_execute_cb_hook;
+ }
+
spin_lock_irq(&signal->lock);
if (i915_request_is_active(signal)) {
+ if (hook) {
+ hook(rq, &signal->fence);
+ i915_request_put(signal);
+ }
i915_sw_fence_complete(cb->fence);
kmem_cache_free(global.slab_execute_cbs, cb);
} else {
@@ -789,7 +817,7 @@ emit_semaphore_wait(struct i915_request *to,
return err;
/* Only submit our spinner after the signaler is running! */
- err = i915_request_await_execution(to, from, gfp);
+ err = __i915_request_await_execution(to, from, NULL, gfp);
if (err)
return err;
@@ -909,6 +937,52 @@ i915_request_await_dma_fence(struct i915_request *rq,
struct dma_fence *fence)
return 0;
}
+int
+i915_request_await_execution(struct i915_request *rq,
+struct dma_fence *fence,
+void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal))
+{
+ struct dma_fence **child = &fence;
+ unsigned int nchild = 1;
+ int ret;
+
+ if (dma_fence_is_array(fence)) {
+ struct dma_fence_array *array = to_dma_fence_array(fence);
+
+ /* XXX Error for signal-on-any fence arrays */
+
+ child = array->fences;
+ nchild = array->num_fences;
+ GEM_BUG_ON(!nchild);
+ }
+
+ do {
+ fence = *child++;
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+ continue;
+
+ /*
+* We don't squash repeated fence dependencies here as we
+* want to run our callback in all cases.
+*/
+
+ if (dma_fence_is_i915(fence))
+ ret = __i915_request_await_execution(rq,
+to_request(fence),
+hook,
+I915_FENCE_GFP);
+ else
+ ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
+
[Intel-gfx] [PATCH 14/18] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context and do not have a valid global class:instance
lookup.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 24
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f038c15e73d8..cbd76ef95115 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1381,6 +1381,7 @@ static int set_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_sseu sseu;
+ unsigned long lookup;
int ret;
if (args->size < sizeof(user_sseu))
@@ -1393,10 +1394,17 @@ static int set_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
@@ -1967,6 +1975,7 @@ static int get_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_context *ce;
+ unsigned long lookup;
if (args->size == 0)
goto out;
@@ -1977,10 +1986,17 @@ static int get_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 4e67c2395b46..8ef6d60929c6 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1567,9 +1567,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
-* Unused for now. Must be cleared to zero.
+* Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/18] drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2: Use intel_engine_mask_t consistently
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gvt/execlist.c | 11 ++-
drivers/gpu/drm/i915/gvt/execlist.h | 2 +-
drivers/gpu/drm/i915/gvt/gvt.h| 8 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 8 +-
drivers/gpu/drm/i915/gvt/scheduler.h | 6 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 9 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
drivers/gpu/drm/i915/i915_reset.c | 43
drivers/gpu/drm/i915/i915_reset.h | 9 +-
drivers/gpu/drm/i915/i915_scheduler.h | 86 +---
drivers/gpu/drm/i915/i915_scheduler_types.h | 98 +++
drivers/gpu/drm/i915/i915_timeline.h | 1 +
drivers/gpu/drm/i915/i915_timeline_types.h| 3 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +-
drivers/gpu/drm/i915/intel_engine_types.h | 8 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 2 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 3 +-
.../test_i915_scheduler_types_standalone.c| 7 ++
28 files changed, 189 insertions(+), 150 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_scheduler_types.h
create mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 68fecf355471..197b081769b5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -60,6 +60,7 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
i915-$(CONFIG_DRM_I915_WERROR) += \
test_i915_active_types_standalone.o \
test_i915_gem_context_types_standalone.o \
+ test_i915_scheduler_types_standalone.o \
test_i915_timeline_types_standalone.o \
test_intel_context_types_standalone.o \
test_intel_engine_types_standalone.o \
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c
b/drivers/gpu/drm/i915/gvt/execlist.c
index 1a93472cb34e..f21b8fb5b37e 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -526,12 +526,13 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu,
int ring_id)
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
}
-static void clean_execlist(struct intel_vgpu *vgpu, unsigned long engine_mask)
+static void clean_execlist(struct intel_vgpu *vgpu,
+ intel_engine_mask_t engine_mask)
{
- unsigned int tmp;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
struct intel_vgpu_submission *s = &vgpu->submission;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
kfree(s->ring_scan_buffer[engine->id]);
@@ -541,18 +542,18 @@ static void clean_execlist(struct intel_vgpu *vgpu,
unsigned long engine_mask)
}
static void reset_execlist(struct intel_vgpu *vgpu,
- unsigned long engine_mask)
+ intel_engine_mask_t engine_mask)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_engine_cs *engine;
- unsigned int tmp;
+ intel_engine_mask_t tmp;
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
init_vgpu_execlist(vgpu, engine->id);
}
static int init_execlist(struct intel_vgpu *vgpu,
-unsigned long engine_mask)
+intel_engine_mask_t engine_mask)
{
reset_execlist(vgpu, engine_mask);
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/execlist.h
b/drivers/gpu/drm/i915/gvt/execlist.h
index 714d709829a2..5ccc2c695848 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.h
+++ b/drivers/gpu/drm/i915/gvt/execlist.h
@@ -180,6 +180,6 @@ int intel_vgpu_init_execlist(struct intel_vgpu *vgpu);
int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id);
void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
- unsigned long engine_mask);
+ intel_engine_mask_t engine_mask);
#endif /
[Intel-gfx] [PATCH 15/18] drm/i915: Load balancing across a virtual engine
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load. The virtual engine has a single timeline across all
engines (it operates as a single queue), so it is not able to concurrently
run batches across multiple engines by itself; that is left up to the user
to submit multiple concurrent batches to multiple queues. Multiple users
will be load balanced across the system.
The mechanism used for load balancing in this patch is a late greedy
balancer. When a request is ready for execution, it is added to each
engine's queue, and when an engine is ready for its next request it
claims it from the virtual engine. The first engine to do so, wins, i.e.
the request is executed at the earliest opportunity (idle moment) in the
system.
As not all HW is created equal, the user is still able to skip the
virtual engine and execute the batch on a specific engine, all within the
same queue. It will then be executed in order on the correct engine,
with execution on other virtual engines being moved away due to the load
detection.
A couple of areas for potential improvement left!
- The virtual engine always take priority over equal-priority tasks.
Mostly broken up by applying FQ_CODEL rules for prioritising new clients,
and hopefully the virtual and real engines are not then congested (i.e.
all work is via virtual engines, or all work is to the real engine).
- We require the breadcrumb irq around every virtual engine request. For
normal engines, we eliminate the need for the slow round trip via
interrupt by using the submit fence and queueing in order. For virtual
engines, we have to allow any job to transfer to a new ring, and cannot
coalesce the submissions, so require the completion fence instead,
forcing the persistent use of interrupts.
- We only drip feed single requests through each virtual engine and onto
the physical engines, even if there was enough work to fill all ELSP,
leaving small stalls with an idle CS event at the end of every request.
Could we be greedy and fill both slots? Being lazy is virtuous for load
distribution on less-than-full workloads though.
Other areas of improvement are more general, such as reducing lock
contention, reducing dispatch overhead, looking at direct submission
rather than bouncing around tasklets etc.
sseu: Lift the restriction to allow sseu to be reconfigured on virtual
engines composed of RENDER_CLASS (rcs).
v2: macroize check_user_mbz()
v3: Cancel virtual engines on wedging
v4: Commence commenting
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.h| 5 +
drivers/gpu/drm/i915/i915_gem_context.c| 126 -
drivers/gpu/drm/i915/i915_scheduler.c | 18 +-
drivers/gpu/drm/i915/i915_timeline_types.h | 1 +
drivers/gpu/drm/i915/intel_engine_types.h | 8 +
drivers/gpu/drm/i915/intel_lrc.c | 567 -
drivers/gpu/drm/i915/intel_lrc.h | 11 +
drivers/gpu/drm/i915/selftests/intel_lrc.c | 165 ++
include/uapi/drm/i915_drm.h| 30 ++
9 files changed, 912 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 5c073fe73664..3ca855505715 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -96,4 +96,9 @@ static inline bool __tasklet_enable(struct tasklet_struct *t)
return atomic_dec_and_test(&t->count);
}
+static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
+{
+ return test_bit(TASKLET_STATE_SCHED, &t->state);
+}
+
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index cbd76ef95115..8d8fcc8c7a86 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -86,6 +86,7 @@
*/
#include
+#include
#include
@@ -94,6 +95,7 @@
#include "i915_trace.h"
#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
+#include "intel_lrc.h"
#include "intel_workarounds.h"
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
@@ -241,6 +243,20 @@ static void release_hw_id(struct i915_gem_context *ctx)
mutex_unlock(&i915->contexts.mutex);
}
+static void free_engines(struct intel_engine_cs **engines, int count)
+{
+ int i;
+
+ if (ZERO_OR_NULL_PTR(engines))
+ return;
+
+ /* We own the veng we created; regular engines are ignored */
+ for (i = 0; i < count; i++)
+ intel_virtual_engine_destroy(engines[i]);
+
+ kfree(engines);
+}
+
static void i915_gem_context_free(struct i915_gem_context *ctx)
{
struct intel_context *it, *n;
@@ -251,8 +267,7 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
[Intel-gfx] [PATCH 05/18] drm/i915: Introduce a mutex for file_priv->context_idr
Define a mutex for the exclusive use of interacting with the per-file
context-idr, that was previously guarded by struct_mutex. This allows us
to reduce the coverage of struct_mutex, with a view to removing the last
bits coordinating GEM context later. (In the short term, we avoid taking
struct_mutex while using the extended constructor functions, preventing
some nasty recursion.)
v2: s/context_lock/context_idr_lock/
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem_context.c | 47 +++--
2 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 86080a6e0f45..219348121897 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -216,7 +216,9 @@ struct drm_i915_file_private {
*/
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
} mm;
+
struct idr context_idr;
+ struct mutex context_idr_lock; /* guards context_idr */
unsigned int bsd_engine;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index dff4220df911..799684d05704 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -579,9 +579,7 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
static int context_idr_cleanup(int id, void *p, void *data)
{
- struct i915_gem_context *ctx = p;
-
- context_close(ctx);
+ context_close(p);
return 0;
}
@@ -603,13 +601,15 @@ static int gem_context_register(struct i915_gem_context
*ctx,
}
/* And finally expose ourselves to userspace via the idr */
+ mutex_lock(&fpriv->context_idr_lock);
ret = idr_alloc(&fpriv->context_idr, ctx,
DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
+ if (ret >= 0)
+ ctx->user_handle = ret;
+ mutex_unlock(&fpriv->context_idr_lock);
if (ret < 0)
goto err_name;
- ctx->user_handle = ret;
-
return 0;
err_name:
@@ -627,10 +627,11 @@ int i915_gem_context_open(struct drm_i915_private *i915,
int err;
idr_init(&file_priv->context_idr);
+ mutex_init(&file_priv->context_idr_lock);
mutex_lock(&i915->drm.struct_mutex);
-
ctx = i915_gem_create_context(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
if (IS_ERR(ctx)) {
err = PTR_ERR(ctx);
goto err;
@@ -643,14 +644,14 @@ int i915_gem_context_open(struct drm_i915_private *i915,
GEM_BUG_ON(ctx->user_handle != DEFAULT_CONTEXT_HANDLE);
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
- mutex_unlock(&i915->drm.struct_mutex);
-
return 0;
err_ctx:
+ mutex_lock(&i915->drm.struct_mutex);
context_close(ctx);
-err:
mutex_unlock(&i915->drm.struct_mutex);
+err:
+ mutex_destroy(&file_priv->context_idr_lock);
idr_destroy(&file_priv->context_idr);
return PTR_ERR(ctx);
}
@@ -663,6 +664,7 @@ void i915_gem_context_close(struct drm_file *file)
idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
idr_destroy(&file_priv->context_idr);
+ mutex_destroy(&file_priv->context_idr_lock);
}
static struct i915_request *
@@ -845,25 +847,22 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
return ret;
ctx = i915_gem_create_context(i915);
- if (IS_ERR(ctx)) {
- ret = PTR_ERR(ctx);
- goto err_unlock;
- }
+ mutex_unlock(&dev->struct_mutex);
+ if (IS_ERR(ctx))
+ return PTR_ERR(ctx);
ret = gem_context_register(ctx, file_priv);
if (ret)
goto err_ctx;
- mutex_unlock(&dev->struct_mutex);
-
args->ctx_id = ctx->user_handle;
DRM_DEBUG("HW context %d created\n", args->ctx_id);
return 0;
err_ctx:
+ mutex_lock(&dev->struct_mutex);
context_close(ctx);
-err_unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
}
@@ -874,7 +873,6 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
struct drm_i915_gem_context_destroy *args = data;
struct drm_i915_file_private *file_priv = file->driver_priv;
struct i915_gem_context *ctx;
- int ret;
if (args->pad != 0)
return -EINVAL;
@@ -882,21 +880,18 @@ int i915_gem_context_destroy_ioctl(struct drm_device
*dev, void *data,
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
return -ENOENT;
- ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
+ if (mutex_lock_interruptible(&file_priv->context_idr_lock))
+ return -EINTR;
+
+ ctx = idr_remove(&file_priv->context_idr, args->ctx_id);
+ mutex_unlock(&file_priv->context_idr_lock);
[Intel-gfx] [PATCH 07/18] drm/i915: Stop storing the context name as the timeline name
The timeline->name is only used for convenience in pretty printing the
i915_request.fence->ops->get_timeline_name() and it is just as
convenient to pull it from the gem_context directly. The few instances
of its use inside GEM_TRACE() has proven more of a nuisance than
helpful, so not worth saving imo.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 5 ++---
drivers/gpu/drm/i915/i915_request.c| 7 ++-
drivers/gpu/drm/i915/i915_timeline.c | 5 +
drivers/gpu/drm/i915/i915_timeline.h | 2 --
drivers/gpu/drm/i915/i915_timeline_types.h | 1 -
drivers/gpu/drm/i915/intel_engine_cs.c | 3 +--
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c| 4 +---
drivers/gpu/drm/i915/selftests/i915_timeline.c | 6 +++---
drivers/gpu/drm/i915/selftests/mock_engine.c | 9 ++---
10 files changed, 13 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 95c5103e15a5..196982f38a28 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -673,9 +673,8 @@ last_request_on_engine(struct i915_timeline *timeline,
rq = i915_active_request_raw(&timeline->last_request,
&engine->i915->drm.struct_mutex);
if (rq && rq->engine == engine) {
- GEM_TRACE("last request for %s on engine %s: %llx:%llu\n",
- timeline->name, engine->name,
- rq->fence.context, rq->fence.seqno);
+ GEM_TRACE("last request on engine %s: %llx:%llu\n",
+ engine->name, rq->fence.context, rq->fence.seqno);
GEM_BUG_ON(rq->timeline != timeline);
return rq;
}
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 0a3d94517d0a..1529824d7c61 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -66,7 +66,7 @@ static const char *i915_fence_get_timeline_name(struct
dma_fence *fence)
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
return "signaled";
- return to_request(fence)->timeline->name;
+ return to_request(fence)->gem_context->name ?: "[i915]";
}
static bool i915_fence_signaled(struct dma_fence *fence)
@@ -167,7 +167,6 @@ static void advance_ring(struct i915_request *request)
* is just about to be. Either works, if we miss the last two
* noops - they are safe to be replayed on a reset.
*/
- GEM_TRACE("marking %s as inactive\n", ring->timeline->name);
tail = READ_ONCE(request->tail);
list_del(&ring->active_link);
} else {
@@ -1064,10 +1063,8 @@ void i915_request_add(struct i915_request *request)
__i915_active_request_set(&timeline->last_request, request);
list_add_tail(&request->ring_link, &ring->request_list);
- if (list_is_first(&request->ring_link, &ring->request_list)) {
- GEM_TRACE("marking %s as active\n", ring->timeline->name);
+ if (list_is_first(&request->ring_link, &ring->request_list))
list_add(&ring->active_link, &request->i915->gt.active_rings);
- }
request->i915->gt.active_engines |= request->engine->mask;
request->emitted_jiffies = jiffies;
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index 8484ba6e51d1..2f4907364920 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -197,7 +197,6 @@ static void cacheline_free(struct i915_timeline_cacheline
*cl)
int i915_timeline_init(struct drm_i915_private *i915,
struct i915_timeline *timeline,
- const char *name,
struct i915_vma *hwsp)
{
void *vaddr;
@@ -213,7 +212,6 @@ int i915_timeline_init(struct drm_i915_private *i915,
BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
timeline->i915 = i915;
- timeline->name = name;
timeline->pin_count = 0;
timeline->has_initial_breadcrumb = !hwsp;
timeline->hwsp_cacheline = NULL;
@@ -342,7 +340,6 @@ void i915_timeline_fini(struct i915_timeline *timeline)
struct i915_timeline *
i915_timeline_create(struct drm_i915_private *i915,
-const char *name,
struct i915_vma *global_hwsp)
{
struct i915_timeline *timeline;
@@ -352,7 +349,7 @@ i915_timeline_create(struct drm_i915_private *i915,
if (!timeline)
return ERR_PTR(-ENOMEM);
- err = i915_timeline_init(i915, timeline, name, global_hwsp);
+ err = i915_timeline_init(i915, timeline, global_hwsp);
if (err) {
kfree(timeline);
return ERR_PTR(err);
[Intel-gfx] [PATCH 12/18] drm/i915: Allow userspace to clone contexts on creation
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient if they were able to just pass in a target context to clone
during creation. This essentially extends the setparam during creation
to pull the details from a target context instead of the user supplied
parameters.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 154
include/uapi/drm/i915_drm.h | 14 +++
2 files changed, 168 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index fc1f64e19507..f36648329074 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1500,8 +1500,162 @@ static int create_setparam(struct i915_user_extension
__user *ext, void *data)
return ctx_setparam(arg->ctx, &local.param);
}
+static int clone_flags(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ dst->user_flags = src->user_flags;
+ return 0;
+}
+
+static int clone_schedattr(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ dst->sched = src->sched;
+ return 0;
+}
+
+static int clone_sseu(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ const struct intel_sseu default_sseu =
+ intel_device_default_sseu(dst->i915);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dst->i915, id) {
+ struct intel_context *ce;
+ struct intel_sseu sseu;
+
+ ce = intel_context_lookup(src, engine);
+ if (!ce)
+ continue;
+
+ sseu = ce->sseu;
+ if (!memcmp(&sseu, &default_sseu, sizeof(sseu)))
+ continue;
+
+ ce = intel_context_pin_lock(dst, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ ce->sseu = sseu;
+ intel_context_pin_unlock(ce);
+ }
+
+ return 0;
+}
+
+static int clone_timeline(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ if (src->timeline) {
+ GEM_BUG_ON(src->timeline == dst->timeline);
+
+ if (dst->timeline)
+ i915_timeline_put(dst->timeline);
+ dst->timeline = i915_timeline_get(src->timeline);
+ }
+
+ return 0;
+}
+
+static int clone_vm(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ struct i915_hw_ppgtt *ppgtt;
+
+ rcu_read_lock();
+ do {
+ ppgtt = READ_ONCE(src->ppgtt);
+ if (!ppgtt)
+ break;
+
+ if (!kref_get_unless_zero(&ppgtt->ref))
+ continue;
+
+ /*
+* This ppgtt may have be reallocated between
+* the read and the kref, and reassigned to a third
+* context. In order to avoid inadvertent sharing
+* of this ppgtt with that third context (and not
+* src), we have to confirm that we have the same
+* ppgtt after passing through the strong memory
+* barrier implied by a successful
+* kref_get_unless_zero().
+*
+* Once we have acquired the current ppgtt of src,
+* we no longer care if it is released from src, as
+* it cannot be reallocated elsewhere.
+*/
+
+ if (ppgtt == READ_ONCE(src->ppgtt))
+ break;
+
+ i915_ppgtt_put(ppgtt);
+ } while (1);
+ rcu_read_unlock();
+
+ if (ppgtt) {
+ __assign_ppgtt(dst, ppgtt);
+ i915_ppgtt_put(ppgtt);
+ }
+
+ return 0;
+}
+
+static int create_clone(struct i915_user_extension __user *ext, void *data)
+{
+ static int (* const fn[])(struct i915_gem_context *dst,
+ struct i915_gem_context *src) = {
+#define MAP(x, y) [ilog2(I915_CONTEXT_CLONE_##x)] = y
+ MAP(FLAGS, clone_flags),
+ MAP(SCHEDATTR, clone_schedattr),
+ MAP(SSEU, clone_sseu),
+ MAP(TIMELINE, clone_timeline),
+ MAP(VM, clone_vm),
+#undef MAP
+ };
+ struct drm_i915_gem_context_create_ext_clone local;
+ const struct create_ext *arg = data;
+ struct i915_gem_context *dst = arg->ctx;
+ struct i915_gem_context *src;
+ int err, bit;
+
+ if (copy_from_user(&local, ext, sizeof(local)))
+ return -EFAULT
[Intel-gfx] [PATCH 10/18] drm/i915: Extend CONTEXT_CREATE to set parameters upon construction
It can be useful to have a single ioctl to create a context with all
the initial parameters instead of a series of create + setparam + setparam
ioctls. This extension to create context allows any of the parameters
to be passed in as a linked list to be applied to the newly constructed
context.
v2: Make a local copy of user setparam (Tvrtko)
v3: Use flags to detect availability of extension interface
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 452 +---
include/uapi/drm/i915_drm.h | 180 +-
3 files changed, 349 insertions(+), 285 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fa991144e0f2..9a0fa3b21e9d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3110,7 +3110,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY,
intel_sprite_set_colorkey_ioctl, DRM_MASTER),
DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl,
DRM_AUTH|DRM_RENDER_ALLOW),
- DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE,
i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT,
i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY,
i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS,
i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 966fbbc154d3..0d16edbb38c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1102,198 +1102,6 @@ static int set_ppgtt(struct i915_gem_context *ctx,
return err;
}
-static bool client_is_banned(struct drm_i915_file_private *file_priv)
-{
- return atomic_read(&file_priv->ban_score) >= I915_CLIENT_SCORE_BANNED;
-}
-
-int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file)
-{
- struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_context_create *args = data;
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct i915_gem_context *ctx;
- int ret;
-
- if (!DRIVER_CAPS(i915)->has_logical_contexts)
- return -ENODEV;
-
- if (args->pad != 0)
- return -EINVAL;
-
- ret = i915_terminally_wedged(i915);
- if (ret)
- return ret;
-
- if (client_is_banned(file_priv)) {
- DRM_DEBUG("client %s[%d] banned from creating ctx\n",
- current->comm,
- pid_nr(get_task_pid(current, PIDTYPE_PID)));
-
- return -EIO;
- }
-
- ret = i915_mutex_lock_interruptible(dev);
- if (ret)
- return ret;
-
- ctx = i915_gem_create_context(i915);
- mutex_unlock(&dev->struct_mutex);
- if (IS_ERR(ctx))
- return PTR_ERR(ctx);
-
- ret = gem_context_register(ctx, file_priv);
- if (ret < 0)
- goto err_ctx;
-
- args->ctx_id = ret;
- DRM_DEBUG("HW context %d created\n", args->ctx_id);
-
- return 0;
-
-err_ctx:
- mutex_lock(&dev->struct_mutex);
- context_close(ctx);
- mutex_unlock(&dev->struct_mutex);
- return ret;
-}
-
-int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file)
-{
- struct drm_i915_gem_context_destroy *args = data;
- struct drm_i915_file_private *file_priv = file->driver_priv;
- struct i915_gem_context *ctx;
-
- if (args->pad != 0)
- return -EINVAL;
-
- if (!args->ctx_id)
- return -ENOENT;
-
- if (mutex_lock_interruptible(&file_priv->context_idr_lock))
- return -EINTR;
-
- ctx = idr_remove(&file_priv->context_idr, args->ctx_id);
- mutex_unlock(&file_priv->context_idr_lock);
- if (!ctx)
- return -ENOENT;
-
- mutex_lock(&dev->struct_mutex);
- context_close(ctx);
- mutex_unlock(&dev->struct_mutex);
-
- return 0;
-}
-
-static int get_sseu(struct i915_gem_context *ctx,
- struct drm_i915_gem_context_param *args)
-{
- struct drm_i915_gem_context_param_sseu user_sseu;
- struct intel_engine_cs *engine;
- struct intel_context *ce;
-
- if (args->size == 0)
- goto out;
- else if (args->size < sizeof(user_sseu))
- return -EINVAL;
-
- if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
-
[Intel-gfx] [PATCH 06/18] drm/i915: Stop storing ctx->user_handle
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 23 ---
drivers/gpu/drm/i915/i915_gem_context.h | 5
drivers/gpu/drm/i915/i915_gem_context_types.h | 9
drivers/gpu/drm/i915/i915_gpu_error.c | 11 -
drivers/gpu/drm/i915/i915_gpu_error.h | 1 -
6 files changed, 15 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f4a07190a0e8..7970770f23a9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -409,9 +409,8 @@ static void print_context_stats(struct seq_file *m,
rcu_read_lock();
task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
- snprintf(name, sizeof(name), "%s/%d",
-task ? task->comm : "",
-ctx->user_handle);
+ snprintf(name, sizeof(name), "%s",
+task ? task->comm : "");
rcu_read_unlock();
print_file_stats(m, name, stats);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 799684d05704..95c5103e15a5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -602,20 +602,15 @@ static int gem_context_register(struct i915_gem_context
*ctx,
/* And finally expose ourselves to userspace via the idr */
mutex_lock(&fpriv->context_idr_lock);
- ret = idr_alloc(&fpriv->context_idr, ctx,
- DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
- if (ret >= 0)
- ctx->user_handle = ret;
+ ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL);
mutex_unlock(&fpriv->context_idr_lock);
- if (ret < 0)
- goto err_name;
-
- return 0;
+ if (ret >= 0)
+ goto out;
-err_name:
kfree(fetch_and_zero(&ctx->name));
err_pid:
put_pid(fetch_and_zero(&ctx->pid));
+out:
return ret;
}
@@ -638,11 +633,11 @@ int i915_gem_context_open(struct drm_i915_private *i915,
}
err = gem_context_register(ctx, file_priv);
- if (err)
+ if (err < 0)
goto err_ctx;
- GEM_BUG_ON(ctx->user_handle != DEFAULT_CONTEXT_HANDLE);
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
+ GEM_BUG_ON(err > 0);
return 0;
@@ -852,10 +847,10 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
return PTR_ERR(ctx);
ret = gem_context_register(ctx, file_priv);
- if (ret)
+ if (ret < 0)
goto err_ctx;
- args->ctx_id = ctx->user_handle;
+ args->ctx_id = ret;
DRM_DEBUG("HW context %d created\n", args->ctx_id);
return 0;
@@ -877,7 +872,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
if (args->pad != 0)
return -EINVAL;
- if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
+ if (!args->ctx_id)
return -ENOENT;
if (mutex_lock_interruptible(&file_priv->context_idr_lock))
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 8a1377691d6d..849b2a83c1ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -126,11 +126,6 @@ static inline void i915_gem_context_unpin_hw_id(struct
i915_gem_context *ctx)
atomic_dec(&ctx->hw_id_pin_count);
}
-static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c)
-{
- return c->user_handle == DEFAULT_CONTEXT_HANDLE;
-}
-
static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
{
return !ctx->file_priv;
diff --git a/drivers/gpu/drm/i915/i915_gem_context_types.h
b/drivers/gpu/drm/i915/i915_gem_context_types.h
index 2bf19730eaa9..63ae8eb21939 100644
--- a/drivers/gpu/drm/i915/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/i915_gem_context_types.h
@@ -129,15 +129,6 @@ struct i915_gem_context {
struct list_head active_engines;
struct mutex mutex;
- /**
-* @user_handle: userspace identifier
-*
-* A unique per-file identifier is generated from
-* &drm_i915_file_private.contexts.
-*/
- u32 user_handle;
-#define DEFAULT_CONTEXT_HANDLE 0
-
struct i915_sched_attr sched;
/** hw_contexts: per-engine logical HW state */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index e8674347f589..b101f037b61f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/
[Intel-gfx] [PATCH 13/18] drm/i915: Allow a context to define its set of engines
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance) tuples to identify a
specific engine, with an API for the user to construct a map of engines
to capabilities. Into this picture, we then add a challenge of virtual
engines; one user engine that maps behind the scenes to any number of
physical engines. To keep it general, we want the user to have full
control over that mapping. To that end, we allow the user to constrain a
context to define the set of engines that it can access, order fully
controlled by the user via (class, instance). With such precise control
in context setup, we can continue to use the existing execbuf uABI of
specifying a single index; only now it doesn't automagically map onto
the engines, it uses the user defined engine map from the context.
The I915_EXEC_DEFAULT slot is left empty, and invalid for use by
execbuf. It's use will be revealed in the next patch.
v2: Fixup freeing of local on success of get_engines()
v3: Allow empty engines[]
v4: s/nengine/num_engines/
Testcase: igt/gem_ctx_engines
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 226 +-
drivers/gpu/drm/i915/i915_gem_context_types.h | 21 ++
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 19 +-
drivers/gpu/drm/i915/i915_utils.h | 36 +++
include/uapi/drm/i915_drm.h | 42 +++-
5 files changed, 331 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index f36648329074..f038c15e73d8 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -86,7 +86,9 @@
*/
#include
+
#include
+
#include "i915_drv.h"
#include "i915_globals.h"
#include "i915_trace.h"
@@ -101,6 +103,21 @@ static struct i915_global_gem_context {
struct kmem_cache *slab_luts;
} global;
+static struct intel_engine_cs *
+lookup_user_engine(struct i915_gem_context *ctx,
+ unsigned long flags, u16 class, u16 instance)
+#define LOOKUP_USER_INDEX BIT(0)
+{
+ if (flags & LOOKUP_USER_INDEX) {
+ if (instance >= ctx->num_engines)
+ return NULL;
+
+ return ctx->engines[instance];
+ }
+
+ return intel_engine_lookup_user(ctx->i915, class, instance);
+}
+
struct i915_lut_handle *i915_lut_handle_alloc(void)
{
return kmem_cache_alloc(global.slab_luts, GFP_KERNEL);
@@ -235,6 +252,8 @@ static void i915_gem_context_free(struct i915_gem_context
*ctx)
release_hw_id(ctx);
i915_ppgtt_put(ctx->ppgtt);
+ kfree(ctx->engines);
+
rbtree_postorder_for_each_entry_safe(it, n, &ctx->hw_contexts, node)
intel_context_put(it);
@@ -1377,9 +1396,9 @@ static int set_sseu(struct i915_gem_context *ctx,
if (user_sseu.flags || user_sseu.rsvd)
return -EINVAL;
- engine = intel_engine_lookup_user(i915,
- user_sseu.engine_class,
- user_sseu.engine_instance);
+ engine = lookup_user_engine(ctx, 0,
+ user_sseu.engine_class,
+ user_sseu.engine_instance);
if (!engine)
return -EINVAL;
@@ -1397,9 +1416,166 @@ static int set_sseu(struct i915_gem_context *ctx,
args->size = sizeof(user_sseu);
+ return 0;
+};
+
+struct set_engines {
+ struct i915_gem_context *ctx;
+ struct intel_engine_cs **engines;
+ unsigned int num_engines;
+};
+
+static const i915_user_extension_fn set_engines__extensions[] = {
+};
+
+static int
+set_engines(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ struct i915_context_param_engines __user *user;
+ struct set_engines set = { .ctx = ctx };
+ u64 size, extensions;
+ unsigned int n;
+ int err;
+
+ user = u64_to_user_ptr(args->value);
+ size = args->size;
+ if (!size)
+ goto out;
+
+ BUILD_BUG_ON(!IS_ALIGNED(sizeof(*user), sizeof(*user->class_instance)));
+ if (size < sizeof(*user) ||
+ !IS_ALIGNED(size, sizeof(*user->class_instance)))
+ return -EINVAL;
+
+ /* Internal limitation of u64 bitmaps + a few bits of u64 in the uABI */
+ set.num_engines =
+ (size - sizeof(*user)) / sizeof(*user->class_instance);
+ if (set.num_engines > I915_EXEC_RING_MASK + 1)
+ return -EINVAL;
+
+ set.engines = kmalloc_array(set.num_engines,
+ sizeof(*set.engines),
+ GFP_KERNEL);
+ if (!set.engines)
+ return -
[Intel-gfx] [PATCH 09/18] drm/i915: Create/destroy VM (ppGTT) for use with contexts
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise with struct_mutex; it's lazy but required dammit
v4: Rewrite igt_ctx_shared_exec to be more different (aimed to be more
similarly, turned out different!)
v5: Fix up test unwind for aliasing-ppgtt (snb)
v6: Tighten language for uapi struct drm_i915_gem_vm_control.
v7: Patch the context image for runtime ppgtt switching!
Testcase: igt/gem_vm_create
Testcase: igt/gem_ctx_param/vm
Testcase: igt/gem_ctx_clone/vm
Testcase: igt/gem_ctx_shared
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 331 +-
drivers/gpu/drm/i915/i915_gem_context.h | 5 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 19 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 1 -
.../gpu/drm/i915/selftests/i915_gem_context.c | 238 ++---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 8 +-
include/uapi/drm/i915_drm.h | 43 +++
11 files changed, 580 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a3b00ecc58c9..fa991144e0f2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -3121,6 +3121,8 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG,
i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl,
DRM_UNLOCKED|DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl,
DRM_RENDER_ALLOW),
};
static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 219348121897..87ef2e031b2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -220,6 +220,9 @@ struct drm_i915_file_private {
struct idr context_idr;
struct mutex context_idr_lock; /* guards context_idr */
+ struct idr vm_idr;
+ struct mutex vm_idr_lock; /* guards vm_idr */
+
unsigned int bsd_engine;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 196982f38a28..966fbbc154d3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,7 @@
#include "i915_drv.h"
#include "i915_globals.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
@@ -120,12 +121,15 @@ static void lut_close(struct i915_gem_context *ctx)
list_del(&lut->obj_link);
i915_lut_handle_free(lut);
}
+ INIT_LIST_HEAD(&ctx->handles_list);
rcu_read_lock();
radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
struct i915_vma *vma = rcu_dereference_raw(*slot);
radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
+
+ vma->open_count--;
__i915_gem_object_release_unless_active(vma->obj);
}
rcu_read_unlock();
@@ -305,8 +309,6 @@ static void context_close(struct i915_gem_context *ctx)
* the ppgtt).
*/
lut_close(ctx);
- if (ctx->ppgtt)
- i915_ppgtt_close(&ctx->ppgtt->vm);
ctx->file_priv = ERR_PTR(-EBADF);
i915_gem_context_put(ctx);
@@ -378,6 +380,28 @@ __create_context(struct drm_i915_private *dev_priv)
return ctx;
}
+static struct i915_hw_ppgtt *
+__set_ppgtt(struct i915_gem_context *ctx, struct i915_hw_ppgtt *ppgtt)
+{
+ struct i915_hw_ppgtt *old = ctx->ppgtt;
+
+ ctx->ppgtt = i915_ppgtt_get(ppgtt);
+ ctx->desc_template = default_desc_template(ctx->i915, ppgtt);
+
+ return old;
+}
+
+static void __assign_ppgtt(struct i915_gem_context *ctx,
+ struct i915_hw_ppgtt *ppgtt)
+{
+ if (ppgtt == ctx->ppgtt)
+ return;
+
+ ppgtt = __set_ppgtt(ctx, ppgtt);
+ if (ppgtt)
+ i915_ppgtt_put(ppgtt);
+}
+
static struct i915_gem_context *
i915_gem_create_context(struct drm_i915_private *dev_priv)
{
@@ -403,8 +427,8 @@ i915_gem_create_context(struct drm_i915_private *dev_priv)
return ERR_CAST(ppgtt);
}
-
[Intel-gfx] [PATCH 08/18] drm/i915: Introduce the i915_user_extension_method
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked into the ioctl data only when required by the
user. The key advantage being able to ignore large control structs for
optional interfaces/extensions, while being able to process them in a
consistent manner.
In comparison to other extensible ioctls, the key difference is the
use of a linked chain of extension structs vs an array of tagged
pointers. For example,
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
__u32 length_dw;
__u64 chunk_data;
};
struct drm_amdgpu_cs_in {
__u32 ctx_id;
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u64 chunks;
};
allows userspace to pass in array of pointers to extension structs, but
must therefore keep constructing that array along side the command stream.
In dynamic situations like that, a linked list is preferred and does not
similar from extra cache line misses as the extension structs themselves
must still be loaded separate to the chunks array.
v2: Apply the tail call optimisation directly to nip the worry of stack
overflow in the bud.
v3: Defend against recursion.
v4: Fixup local types to match new uabi
Opens:
- do we include the result as an out-field in each chain?
struct i915_user_extension {
__u64 next_extension;
__u64 name;
__s32 result;
__u32 mbz; /* reserved for future use */
};
* Undecided, so provision some room for future expansion.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_user_extensions.c | 61 +
drivers/gpu/drm/i915/i915_user_extensions.h | 20 +++
drivers/gpu/drm/i915/i915_utils.h | 31 +++
include/uapi/drm/i915_drm.h | 22
5 files changed, 135 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.c
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 197b081769b5..1f3e8b145fc0 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -46,6 +46,7 @@ i915-y := i915_drv.o \
i915_sw_fence.o \
i915_syncmap.o \
i915_sysfs.o \
+ i915_user_extensions.o \
intel_csr.o \
intel_device_info.o \
intel_pm.o \
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c
b/drivers/gpu/drm/i915/i915_user_extensions.c
new file mode 100644
index ..c822d0aafd2d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "i915_user_extensions.h"
+#include "i915_utils.h"
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned int count,
+void *data)
+{
+ unsigned int stackdepth = 512;
+
+ while (ext) {
+ int i, err;
+ u32 name;
+ u64 next;
+
+ if (!stackdepth--) /* recursion vs useful flexibility */
+ return -E2BIG;
+
+ err = check_user_mbz(&ext->flags);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(ext->rsvd); i++) {
+ err = check_user_mbz(&ext->rsvd[i]);
+ if (err)
+ return err;
+ }
+
+ if (get_user(name, &ext->name))
+ return -EFAULT;
+
+ err = -EINVAL;
+ if (name < count) {
+ name = array_index_nospec(name, count);
+ if (tbl[name])
+ err = tbl[name](ext, data);
+ }
+ if (err)
+ return err;
+
+ if (get_user(next, &ext->next_extension) ||
+ overflows_type(next, ext))
+ return -EFAULT;
+
+ ext = u64_to_user_ptr(next);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.h
b/drivers/gpu/drm/i915/i915_user_extensions.h
new file mode 100644
index ..a14bf6bba9a1
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef I915_USER_EXTENSI
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/18] drm/i915/selftests: Provide stub reset functions
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4af79bb9ca20 drm/i915/selftests: Provide stub reset functions
383e05f979e8 drm/i915: Flush pages on acquisition
b283b7c85d62 drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h
-:652: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#652:
new file mode 100644
-:657: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#657: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:1:
+/*
-:658: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#658: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:2:
+ * SPDX-License-Identifier: MIT
-:913: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#913: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:1:
+/*
-:914: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#914: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 5 warnings, 0 checks, 730 lines checked
d0f146918e12 drm/i915: Separate GEM context construction and registration to
userspace
0c91e73a8852 drm/i915: Introduce a mutex for file_priv->context_idr
82bce97b4b34 drm/i915: Stop storing ctx->user_handle
6d809b9cfe5a drm/i915: Stop storing the context name as the timeline name
b2401f795713 drm/i915: Introduce the i915_user_extension_method
-:72: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#72:
new file mode 100644
-:77: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#77: FILE: drivers/gpu/drm/i915/i915_user_extensions.c:1:
+/*
-:78: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#78: FILE: drivers/gpu/drm/i915/i915_user_extensions.c:2:
+ * SPDX-License-Identifier: MIT
-:144: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#144: FILE: drivers/gpu/drm/i915/i915_user_extensions.h:1:
+/*
-:145: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#145: FILE: drivers/gpu/drm/i915/i915_user_extensions.h:2:
+ * SPDX-License-Identifier: MIT
-:178: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ptr' - possible
side-effects?
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:178: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible
side-effects?
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:178: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'member' may be better as
'(member)' to avoid precedence issues
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'U' - possible side-effects?
#198: FILE: drivers/gpu/drm/i915/i915_utils.h:134:
+#define check_user_mbz(U) ({ \
+ typeof(*(U)) mbz__; \
+ get_user(mbz__, (U)) ? -EFAULT : mbz__ ? -EINVAL : 0; \
+})
total: 0 errors, 5 warnings, 4 checks, 153 lines checked
704b8c113249 drm/i915: Create/destroy VM (ppGTT) for use with contexts
-:693: WARNING:LINE_SPACING: Missing a blank line after declarations
#693: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:504:
+ struct drm_file *file;
+ IGT_TIMEOUT(end_time);
-:755: CHECK:MULTIPLE_ASSIGNMENTS: multiple
[Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
There has unfortunately been a conflict with the following 3 commits:
commit e9961ab95af81b8d29054361cd5f0c575102cf87
Author: Ayan Kumar Halder
Date: Fri Nov 9 17:21:12 2018 +
drm: Added a new format DRM_FORMAT_XVYU2101010
commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
Author: Brian Starkey
Date: Fri Oct 5 10:27:00 2018 +0100
drm/fourcc: Add AFBC yuv fourccs for Mali
and
commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
Author: Swati Sharma
Date: Mon Mar 4 17:26:33 2019 +0530
drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
Unfortunately gcc didn't warn about the redefinitions, because the
Fix this by using new XYVU for i915, without alpha, and making the
Y41x definitions match msdn, with alpha.
Fortunately we caught it early, and the conflict hasn't even landed in
drm-next yet.
Signed-off-by: Maarten Lankhorst
Cc: Brian Starkey
Cc: Swati Sharma
Cc: Ayan Kumar Halder
Cc: mal...@foss.arm.com
Cc: Daniel Vetter
Cc: Maxime Ripard
Cc: Sean Paul
Cc: Dave Airlie
Cc: Liviu Dudau
---
drivers/gpu/drm/drm_fourcc.c | 12 +--
drivers/gpu/drm/i915/intel_display.c | 18 -
drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
include/uapi/drm/drm_fourcc.h| 21 +--
4 files changed, 41 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index b914b16db9b2..6ea55fb4526d 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VUY888, .depth = 0,
.num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
- { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XVYU12_16161616, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XVYU16161616,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y0L0,.depth = 0,
.num_planes = 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/in
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/18] drm/i915/selftests: Provide stub reset functions
== Series Details == Series: series starting with [01/18] drm/i915/selftests: Provide stub reset functions URL : https://patchwork.freedesktop.org/series/58179/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Provide stub reset functions Okay! Commit: drm/i915: Flush pages on acquisition -drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) Commit: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) Commit: drm/i915: Separate GEM context construction and registration to userspace Okay! Commit: drm/i915: Introduce a mutex for file_priv->context_idr -drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) Commit: drm/i915: Stop storing ctx->user_handle Okay! Commit: drm/i915: Stop storing the context name as the timeline name Okay! Commit: drm/i915: Introduce the i915_user_extension_method Okay! Commit: drm/i915: Create/destroy VM (ppGTT) for use with contexts -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1132:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1132:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:565:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:565:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) Commit: drm/i915: Extend CONTEXT_CREATE to set parameters upon construction Okay! Commit: drm/i915: Allow contexts to share a single timeline across all engines Okay! Commit: drm/i915: Allow userspace to clone contexts on creation +drivers/gpu/drm/i915/i915_gem_context.c:1611:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1612:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1613:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1614:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1615:17: error: bad integer constant expression -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:452:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) -./include/linux/slab.h:664:13: warning: call with no type! Commit: drm/i915: Allow a context to define its set of engines -O:drivers/gpu/drm/i915/i915_gem_context.c:1611:17: error: bad integer constant expression -O:drivers/gpu/drm/i915/i915_gem_context.c:1612:17: error: bad integer constant expression -O:drivers/gpu/drm/i915/i915_gem_context.c:1613:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1820:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1821:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1822:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1823:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_utils.h:84:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:84:13: error: undefined identifier '__builtin_mul_overflow' +drivers/gpu/drm/i915/i915_utils.h:84:13:got void +drivers/g
Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Watchdog timeout: IRQ handler for gen8+
On 18/03/2019 00:15, Carlos Santa wrote:
On Mon, 2019-03-11 at 10:39 +, Tvrtko Ursulin wrote:
On 08/03/2019 03:16, Carlos Santa wrote:
On Fri, 2019-03-01 at 09:36 +, Chris Wilson wrote:
Quoting Carlos Santa (2019-02-21 02:58:16)
+#define GEN8_WATCHDOG_1000US(dev_priv)
watchdog_to_clock_counts(dev_priv, 1000)
+static void gen8_watchdog_irq_handler(unsigned long data)
+{
+ struct intel_engine_cs *engine = (struct
intel_engine_cs
*)data;
+ struct drm_i915_private *dev_priv = engine->i915;
+ unsigned int hung = 0;
+ u32 current_seqno=0;
+ char msg[80];
+ unsigned int tmp;
+ int len;
+
+ /* Stop the counter to prevent further timeout
interrupts
*/
+ I915_WRITE_FW(RING_CNTR(engine->mmio_base),
get_watchdog_disable(engine));
+
+ /* Read the heartbeat seqno once again to check if we
are
stuck? */
+ current_seqno =
intel_engine_get_hangcheck_seqno(engine);
I have said this before, but this doesn't exist either, it's just
a
temporary glitch in the matrix.
Chris, Tvrtko, I need some guidance on how to find the quilty seqno
during a hang, can you please advice here what to do?
When an interrupt fires you need to ascertain whether the same
request
which enabled the watchdog is running, correct?
So I think you would need this, with a disclaimer that I haven't
thought
about the details really:
1. Take a reference to timeline hwsp when setting up the watchdog for
a
request.
2. Store the initial seqno associated with this request.
3. Force enable user interrupts.
4. When timeout fires, inspect the HWSP seqno to see if the request
completed or not.
5. Reset the engine if not completed.
6. Put the timeline/hwsp reference.
static int gen8_emit_bb_start(struct i915_request *rq,
u64 offset, u32
len,
const unsigned
int flags)
{
struct i915_timeline *tl;
u32 seqno;
if (enable_watchdog) {
/* Start watchdog timer */
cs = gen8_emit_start_watchdog(rq, cs);
tl = ce->ring->timeline;
i915_timeline_get_seqno(tl, rq, &seqno);
/*Store initial hwsp seqno associated with this request
engine->watchdog_hwsp_seqno = tl->hwsp_seqno;
You should not need to allocate a new seqno and also having something
stored per engine does not make clear how will you solve out of order.
Maybe you just set up the timer, then lets see below..
Also, are you not trying to do the software implementation to start with?
}
}
static void gen8_watchdog_tasklet(unsigned long data)
{
struct i915_request *rq;
rq = intel_engine_find_active_request(engine);
/* Inspect the watchdog seqno once again for
completion? */
if (!i915_seqno_passed(engine->watchdog_hwsp_seqno, rq-
fence.seqno)) {
//Reset Engine
}
}
What happens if you simply reset without checking anything? You know hw
timer wouldn't have fired if the context wasn't running, correct?
(Ignoring the race condition between interrupt raised -> hw interrupt
delivered -> serviced -> tasklet scheduled -> tasklet running. Which may
mean request has completed in the meantime and you reset the engine for
nothing. But this is probably not 100% solvable.)
Regards,
Tvrtko
Tvrtko, is the above acceptable to inspect whether the seqno has
completed?
I noticed there's a helper function i915_request_completed(struct
i915_request *rq) but it will require me to modify it in order to pass
2 different seqnos.
Regards,
Carlos
If the user interrupt fires with the request completed cancel the
above
operations.
There could be an inherent race between inspecting the seqno and
deciding to reset. Not sure at the moment what to do. Maybe just call
it
bad luck?
I also think for the software implementation you need to force no
request coalescing for contexts with timeout set. Because you want
to
have 100% defined borders for request in and out - since the timeout
is
defined per request.
In this case you don't need the user interrupt for the trailing edge
signal but can use context complete. Maybe putting hooks into
context_in/out in intel_lrc.c would work under these circumstances.
Also if preempted you need to cancel the timer setup and store
elapsed
execution time.
Or it may make sense to just disable preemption for these contexts.
Otherwise there is no point in trying to mandate the timeout?
But it is also kind of bad since non-privileged contexts can make
themselves non-preemptable by setting the watchdog timeout.
Maybe as a compromise we need to automatically apply an elevated
priority level, but not as high to be completely non-preemptable.
Sounds
like a hard question.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gf
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/18] drm/i915/selftests: Provide stub reset functions
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions
URL : https://patchwork.freedesktop.org/series/58179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12511
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12511 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12511, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58179/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12511:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live_requests:
- fi-hsw-peppy: NOTRUN -> INCOMPLETE
- fi-ivb-3770:PASS -> INCOMPLETE
- fi-blb-e6850: PASS -> INCOMPLETE
- fi-gdg-551: NOTRUN -> INCOMPLETE
- fi-ilk-650: PASS -> INCOMPLETE
- fi-pnv-d510:NOTRUN -> INCOMPLETE
- fi-snb-2520m: PASS -> INCOMPLETE
- fi-bwr-2160:PASS -> INCOMPLETE
* igt@i915_selftest@live_workarounds:
- fi-bsw-n3050: NOTRUN -> INCOMPLETE
- fi-cfl-guc: PASS -> INCOMPLETE
- fi-bsw-kefka: NOTRUN -> INCOMPLETE
- fi-hsw-4770r: PASS -> INCOMPLETE
- fi-cfl-8109u: PASS -> INCOMPLETE
- fi-kbl-guc: PASS -> INCOMPLETE
- fi-skl-6600u: PASS -> INCOMPLETE
- fi-bdw-5557u: PASS -> INCOMPLETE
- fi-kbl-7567u: PASS -> INCOMPLETE
- fi-whl-u: PASS -> INCOMPLETE
- fi-skl-iommu: PASS -> INCOMPLETE
- fi-skl-6770hq: PASS -> INCOMPLETE
- fi-kbl-x1275: PASS -> INCOMPLETE
- fi-icl-u3: PASS -> INCOMPLETE
- fi-skl-6260u: PASS -> INCOMPLETE
- fi-kbl-r: PASS -> INCOMPLETE
- fi-kbl-8809g: PASS -> INCOMPLETE
- fi-skl-guc: PASS -> INCOMPLETE
- fi-hsw-4770:PASS -> INCOMPLETE
- fi-cfl-8700k: PASS -> INCOMPLETE
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> FAIL
- fi-pnv-d510:NOTRUN -> FAIL
- fi-cfl-8109u: NOTRUN -> FAIL
- fi-hsw-peppy: NOTRUN -> FAIL
- fi-gdg-551: NOTRUN -> FAIL
- fi-snb-2520m: NOTRUN -> FAIL
- fi-bxt-j4205: NOTRUN -> FAIL
- fi-whl-u: NOTRUN -> FAIL
- fi-icl-u3: NOTRUN -> FAIL
- fi-ivb-3770:NOTRUN -> FAIL
- fi-cfl-guc: NOTRUN -> FAIL
- fi-kbl-7567u: NOTRUN -> FAIL
- fi-blb-e6850: NOTRUN -> FAIL
- fi-kbl-x1275: NOTRUN -> FAIL
- fi-cfl-8700k: NOTRUN -> FAIL
- fi-kbl-8809g: NOTRUN -> FAIL
- fi-apl-guc: NOTRUN -> FAIL
- fi-kbl-r: NOTRUN -> FAIL
- fi-bwr-2160:NOTRUN -> FAIL
- fi-kbl-guc: NOTRUN -> FAIL
- fi-snb-2600:NOTRUN -> FAIL
- fi-elk-e7500: NOTRUN -> FAIL
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_workarounds:
- {fi-icl-y}: PASS -> INCOMPLETE
- {fi-skl-lmem}: PASS -> INCOMPLETE
* igt@runner@aborted:
- {fi-icl-y}: NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_12511 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@i915_selftest@live_requests:
- fi-elk-e7500: PASS -> INCOMPLETE [fdo#103989]
- fi-snb-2600:PASS -> INCOMPLETE [fdo#105411]
* igt@i915_selftest@live_workarounds:
- fi-byt-clapper: PASS -> INCOMPLETE [fdo#102657]
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]
- fi-byt-n2820: PASS -> INCOMPLETE [fdo#102657]
- fi-skl-6700k2: NOTRUN -> INCOMPLETE [fdo#104108]
- fi-byt-j1900: PASS -> INCOMPLETE [fdo#102657]
- fi-bxt-j4205: PASS -> INCOMPLETE [fdo#103927]
- fi-skl-gvtdvm: PASS -> INCOMPLETE [fdo#105600]
- fi-bdw-gvtdvm: PASS -> INCOMPLETE [fdo#105600]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182] +1
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-pnv-d510:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/fourcc: Fix conflicting Y41x definitions
== Series Details ==
Series: drm/fourcc: Fix conflicting Y41x definitions
URL : https://patchwork.freedesktop.org/series/58182/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
68cd4376136d drm/fourcc: Fix conflicting Y41x definitions
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit e9961ab95af8 ("drm: Added a new
format DRM_FORMAT_XVYU2101010")'
#8:
commit e9961ab95af81b8d29054361cd5f0c575102cf87
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 7ba0fee247ee ("drm/fourcc: Add
AFBC yuv fourccs for Mali")'
#13:
commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 50bf5d7d595f ("drm: Add Y2xx and
Y4xx (xx:10/12/16) format definitions and fourcc")'
#21:
commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
-:65: WARNING:LONG_LINE: line over 100 characters
#65: FILE: drivers/gpu/drm/drm_fourcc.c:237:
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/drm_fourcc.c:238:
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/drm_fourcc.c:239:
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
-:68: WARNING:LONG_LINE: line over 100 characters
#68: FILE: drivers/gpu/drm/drm_fourcc.c:240:
+ { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:69: WARNING:LONG_LINE: line over 100 characters
#69: FILE: drivers/gpu/drm/drm_fourcc.c:241:
+ { .format = DRM_FORMAT_XVYU12_16161616, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:70: WARNING:LONG_LINE: line over 100 characters
#70: FILE: drivers/gpu/drm/drm_fourcc.c:242:
+ { .format = DRM_FORMAT_XVYU16161616,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:203: WARNING:LONG_LINE_COMMENT: line over 100 characters
#203: FILE: include/uapi/drm/drm_fourcc.h:165:
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /* [31:0]
X:Y:Cb:Cr 8:8:8:8 little endian */
-:215: WARNING:LONG_LINE_COMMENT: line over 100 characters
#215: FILE: include/uapi/drm/drm_fourcc.h:173:
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
-:216: WARNING:LONG_LINE_COMMENT: line over 100 characters
#216: FILE: include/uapi/drm/drm_fourcc.h:174:
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
-:217: WARNING:LONG_LINE_COMMENT: line over 100 characters
#217: FILE: include/uapi/drm/drm_fourcc.h:175:
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
-:226: WARNING:LONG_LINE_COMMENT: line over 100 characters
#226: FILE: include/uapi/drm/drm_fourcc.h:181:
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0]
A:Cr:Y:Cb 2:10:10:10 little endian */
-:227: WARNING:LONG_LINE_COMMENT: line over 100 characters
#227: FILE: include/uapi/drm/drm_fourcc.h:182:
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0]
A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-:228: WARNING:LONG_LINE_COMMENT: line over 100 characters
#228: FILE: include/uapi/drm/drm_fourcc.h:183:
+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0]
A:Cr:Y:Cb 16:16:16:16 little endian */
-:230: WARNING:LONG_LINE_COMMENT: line over 100 characters
#230: FILE: include/uapi/drm/drm_fourcc.h:185:
+#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0]
X:Cr:Y:Cb 2:10:10:10 little endian */
-:231: WARNING:LONG_LINE_COMMENT: line over 100 characters
#231: FILE: include/uapi/drm/drm_fourcc.h:186:
+#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /*
[63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-:232: WARNING:LONG_LINE_COMMENT: line over 100 characters
#232: FILE: include/uapi/drm/drm_fourcc.h:187:
+#define DRM_FORMAT_XVYU16161616fourcc_code('X', 'V', '4', '8') /*
[63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
total: 3 errors, 16 warnings, 0 checks, 164 lines checked
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop
Re: [Intel-gfx] [PATCH] drm/i915: Handle YUV subpixel support better
On Tue, Mar 19, 2019 at 01:15:55PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 19, 2019 at 08:28:58AM +0100, Maarten Lankhorst wrote:
> > Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> > > On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
> > >> Op 18-03-2019 om 15:18 schreef Ville Syrjälä:
> > >>> On Mon, Mar 18, 2019 at 03:07:18PM +0100, Maarten Lankhorst wrote:
> > Signed-off-by: Maarten Lankhorst
> > ---
> > drivers/gpu/drm/i915/intel_sprite.c | 29 +++--
> > 1 file changed, 19 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 268fb34ff0e2..862fc172042f 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -269,7 +269,8 @@ int intel_plane_check_src_coordinates(struct
> > intel_plane_state *plane_state)
> > {
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > struct drm_rect *src = &plane_state->base.src;
> > - u32 src_x, src_y, src_w, src_h;
> > + u32 src_x, src_y, src_w, src_h, hsub, vsub;
> > + bool rotated =
> > drm_rotation_90_or_270(plane_state->base.rotation);
> >
> > /*
> > * Hardware doesn't handle subpixel coordinates.
> > @@ -287,18 +288,26 @@ int intel_plane_check_src_coordinates(struct
> > intel_plane_state *plane_state)
> > src->y1 = src_y << 16;
> > src->y2 = (src_y + src_h) << 16;
> >
> > - if (fb->format->is_yuv &&
> > - (src_x & 1 || src_w & 1)) {
> > - DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2
> > for YUV planes\n",
> > -src_x, src_w);
> > + if (!fb->format->is_yuv)
> > + return 0;
> > +
> > + /* YUV specific checks */
> > + if (!rotated) {
> > + hsub = fb->format->hsub;
> > + vsub = fb->format->vsub;
> > + } else {
> > + hsub = vsub = max(fb->format->hsub, fb->format->vsub);
> > >>> Why this? From the looks of things there should be no need to deal with
> > >>> rotation in this function at all.
> > >> I wrote a dumb test that fails if I rotate YUYV.
> > >>
> > >> https://patchwork.freedesktop.org/patch/286170/
> > >>
> > >> Corrupted image:
> > >>
> > >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_rotation(90°)
> > >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_position(18,33)
> > >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: src_set_size(44x65)
> > >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_position(64,64)
> > >> (kms_yuv:1155) igt_kms-DEBUG: display: A.0: plane_set_size (256x256)
> > >>
> > >> I had a 80x128 fb, only showing the center part which should be white,
> > >> with a black border around it to cause CRC errors if we mess up clipping.
> > >>
> > >> The scaling works fine, but the clipping does not in this case. I am
> > >> getting a corrupted plane on screen which is mostly white, but with
> > >> black dots in each tile.
> > >>
> > >> Scaling just magnifies this corruption. :)
> > > Hmm. I just poked my KBL a bit and it is also showing curious
> > > behaviour. Even with 90/270 rotation it is in fact the TILEOFF
> > > X coordinate that needs to be even (actually the hw just appears
> > > to ignore the lsb). I can make the Y coordinate odd, and the image
> > > still looks correct to my eyes. So feels like someone forgot to
> > > to remove a (x&~1) from the hw when they added the 90/270 rotation,
> > > and yet they went to the trouble of making odd Y coordinates work
> > > correctly. Quite stange.
> > >
> > > Width/height being odd seems to handled just fine by the hw.
> > >
> > Hmm does that mean we should keep the original checks in place while
> > checking format->h/vsub, and on top reject the unrotated Y coordinate being
> > a multiple of hsub when rotating?
>
> Not quite sure. Based on what I see we could actually just swap the
> coordinates (or do the check after the coordinates are already rotated)
> and it should still work. But I didn't check if that would still work
> when the scaler is involved.
Hmm. The spec disagrees with this observed behaviour of PLANE_OFFSET.
It claims our current code should be fine.
PLANE_SIZE also has this slightly confusing table for GLK+:
PixelFormat Rotate Width Height
YUV 420 Planar - NV12 All EvenEven
YUV 420 Planar - P01x All EvenEven
YUV 422 All EvenEven
RGB565 90, 270 EvenEven
which pretty much matches the w/h part of your patch.
--
Ville Syrjälä
Intel
___
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https://lists.freed
Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Watchdog timeout: IRQ handler for gen8+
On 19/03/2019 12:39, Tvrtko Ursulin wrote:
On 18/03/2019 00:15, Carlos Santa wrote:
On Mon, 2019-03-11 at 10:39 +, Tvrtko Ursulin wrote:
On 08/03/2019 03:16, Carlos Santa wrote:
On Fri, 2019-03-01 at 09:36 +, Chris Wilson wrote:
Quoting Carlos Santa (2019-02-21 02:58:16)
+#define GEN8_WATCHDOG_1000US(dev_priv)
watchdog_to_clock_counts(dev_priv, 1000)
+static void gen8_watchdog_irq_handler(unsigned long data)
+{
+ struct intel_engine_cs *engine = (struct
intel_engine_cs
*)data;
+ struct drm_i915_private *dev_priv = engine->i915;
+ unsigned int hung = 0;
+ u32 current_seqno=0;
+ char msg[80];
+ unsigned int tmp;
+ int len;
+
+ /* Stop the counter to prevent further timeout
interrupts
*/
+ I915_WRITE_FW(RING_CNTR(engine->mmio_base),
get_watchdog_disable(engine));
+
+ /* Read the heartbeat seqno once again to check if we
are
stuck? */
+ current_seqno =
intel_engine_get_hangcheck_seqno(engine);
I have said this before, but this doesn't exist either, it's just
a
temporary glitch in the matrix.
Chris, Tvrtko, I need some guidance on how to find the quilty seqno
during a hang, can you please advice here what to do?
When an interrupt fires you need to ascertain whether the same
request
which enabled the watchdog is running, correct?
So I think you would need this, with a disclaimer that I haven't
thought
about the details really:
1. Take a reference to timeline hwsp when setting up the watchdog for
a
request.
2. Store the initial seqno associated with this request.
3. Force enable user interrupts.
4. When timeout fires, inspect the HWSP seqno to see if the request
completed or not.
5. Reset the engine if not completed.
6. Put the timeline/hwsp reference.
static int gen8_emit_bb_start(struct i915_request *rq,
u64 offset, u32
len,
const unsigned
int flags)
{
struct i915_timeline *tl;
u32 seqno;
if (enable_watchdog) {
/* Start watchdog timer */
cs = gen8_emit_start_watchdog(rq, cs);
tl = ce->ring->timeline;
i915_timeline_get_seqno(tl, rq, &seqno);
/*Store initial hwsp seqno associated with this request
engine->watchdog_hwsp_seqno = tl->hwsp_seqno;
You should not need to allocate a new seqno and also having something
stored per engine does not make clear how will you solve out of order.
Maybe you just set up the timer, then lets see below..
Also, are you not trying to do the software implementation to start with?
}
}
static void gen8_watchdog_tasklet(unsigned long data)
{
struct i915_request *rq;
rq = intel_engine_find_active_request(engine);
/* Inspect the watchdog seqno once again for
completion? */
if (!i915_seqno_passed(engine->watchdog_hwsp_seqno, rq-
fence.seqno)) {
//Reset Engine
}
}
What happens if you simply reset without checking anything? You know hw
timer wouldn't have fired if the context wasn't running, correct?
(Ignoring the race condition between interrupt raised -> hw interrupt
delivered -> serviced -> tasklet scheduled -> tasklet running. Which may
mean request has completed in the meantime and you reset the engine for
nothing. But this is probably not 100% solvable.)
Good idea would be to write some tests to exercise some normal and more
edge case scenarios like coalesced requests, preemption etc. Checking
which request got reset etc.
Regards,
Tvrtko
Regards,
Tvrtko
Tvrtko, is the above acceptable to inspect whether the seqno has
completed?
I noticed there's a helper function i915_request_completed(struct
i915_request *rq) but it will require me to modify it in order to pass
2 different seqnos.
Regards,
Carlos
If the user interrupt fires with the request completed cancel the
above
operations.
There could be an inherent race between inspecting the seqno and
deciding to reset. Not sure at the moment what to do. Maybe just call
it
bad luck?
I also think for the software implementation you need to force no
request coalescing for contexts with timeout set. Because you want
to
have 100% defined borders for request in and out - since the timeout
is
defined per request.
In this case you don't need the user interrupt for the trailing edge
signal but can use context complete. Maybe putting hooks into
context_in/out in intel_lrc.c would work under these circumstances.
Also if preempted you need to cancel the timer setup and store
elapsed
execution time.
Or it may make sense to just disable preemption for these contexts.
Otherwise there is no point in trying to mandate the timeout?
But it is also kind of bad since non-privileged contexts can make
themselves non-preemptable by setting the watchdog timeout.
Maybe as a compromise we need to automatically apply an elevated
priority level, but not as high to be completely non-preemptable.
Sounds
like a hard question.
Regards,
Tvrtko
[Intel-gfx] [PATCH v2] drm/i915: Stop storing ctx->user_handle
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 23 ---
drivers/gpu/drm/i915/i915_gem_context.h | 5
drivers/gpu/drm/i915/i915_gem_context_types.h | 9
drivers/gpu/drm/i915/i915_gpu_error.c | 11 -
drivers/gpu/drm/i915/i915_gpu_error.h | 1 -
drivers/gpu/drm/i915/selftests/mock_context.c | 2 +-
7 files changed, 16 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f4a07190a0e8..7970770f23a9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -409,9 +409,8 @@ static void print_context_stats(struct seq_file *m,
rcu_read_lock();
task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
- snprintf(name, sizeof(name), "%s/%d",
-task ? task->comm : "",
-ctx->user_handle);
+ snprintf(name, sizeof(name), "%s",
+task ? task->comm : "");
rcu_read_unlock();
print_file_stats(m, name, stats);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 799684d05704..95c5103e15a5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -602,20 +602,15 @@ static int gem_context_register(struct i915_gem_context
*ctx,
/* And finally expose ourselves to userspace via the idr */
mutex_lock(&fpriv->context_idr_lock);
- ret = idr_alloc(&fpriv->context_idr, ctx,
- DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
- if (ret >= 0)
- ctx->user_handle = ret;
+ ret = idr_alloc(&fpriv->context_idr, ctx, 0, 0, GFP_KERNEL);
mutex_unlock(&fpriv->context_idr_lock);
- if (ret < 0)
- goto err_name;
-
- return 0;
+ if (ret >= 0)
+ goto out;
-err_name:
kfree(fetch_and_zero(&ctx->name));
err_pid:
put_pid(fetch_and_zero(&ctx->pid));
+out:
return ret;
}
@@ -638,11 +633,11 @@ int i915_gem_context_open(struct drm_i915_private *i915,
}
err = gem_context_register(ctx, file_priv);
- if (err)
+ if (err < 0)
goto err_ctx;
- GEM_BUG_ON(ctx->user_handle != DEFAULT_CONTEXT_HANDLE);
GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
+ GEM_BUG_ON(err > 0);
return 0;
@@ -852,10 +847,10 @@ int i915_gem_context_create_ioctl(struct drm_device *dev,
void *data,
return PTR_ERR(ctx);
ret = gem_context_register(ctx, file_priv);
- if (ret)
+ if (ret < 0)
goto err_ctx;
- args->ctx_id = ctx->user_handle;
+ args->ctx_id = ret;
DRM_DEBUG("HW context %d created\n", args->ctx_id);
return 0;
@@ -877,7 +872,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev,
void *data,
if (args->pad != 0)
return -EINVAL;
- if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
+ if (!args->ctx_id)
return -ENOENT;
if (mutex_lock_interruptible(&file_priv->context_idr_lock))
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
b/drivers/gpu/drm/i915/i915_gem_context.h
index 8a1377691d6d..849b2a83c1ec 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -126,11 +126,6 @@ static inline void i915_gem_context_unpin_hw_id(struct
i915_gem_context *ctx)
atomic_dec(&ctx->hw_id_pin_count);
}
-static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c)
-{
- return c->user_handle == DEFAULT_CONTEXT_HANDLE;
-}
-
static inline bool i915_gem_context_is_kernel(struct i915_gem_context *ctx)
{
return !ctx->file_priv;
diff --git a/drivers/gpu/drm/i915/i915_gem_context_types.h
b/drivers/gpu/drm/i915/i915_gem_context_types.h
index 2bf19730eaa9..63ae8eb21939 100644
--- a/drivers/gpu/drm/i915/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/i915_gem_context_types.h
@@ -129,15 +129,6 @@ struct i915_gem_context {
struct list_head active_engines;
struct mutex mutex;
- /**
-* @user_handle: userspace identifier
-*
-* A unique per-file identifier is generated from
-* &drm_i915_file_private.contexts.
-*/
- u32 user_handle;
-#define DEFAULT_CONTEXT_HANDLE 0
-
struct i915_sched_attr sched;
/** hw_contexts: per-engine logical HW state */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index e8674347f589..b101f037b61f 10
Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORMAT_XVYU2101010
>
> commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
> Author: Brian Starkey
> Date: Fri Oct 5 10:27:00 2018 +0100
>
> drm/fourcc: Add AFBC yuv fourccs for Mali
>
> and
>
> commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
> Author: Swati Sharma
> Date: Mon Mar 4 17:26:33 2019 +0530
>
> drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
>
> Unfortunately gcc didn't warn about the redefinitions, because the
>
> Fix this by using new XYVU for i915, without alpha, and making the
> Y41x definitions match msdn, with alpha.
The naming of all these is rather unfortunate because now the alpha vs.
non-alpha formats have totally different looking names :( Fourccs are
stupid!
>
> Fortunately we caught it early, and the conflict hasn't even landed in
> drm-next yet.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Brian Starkey
> Cc: Swati Sharma
> Cc: Ayan Kumar Halder
> Cc: mal...@foss.arm.com
> Cc: Daniel Vetter
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: Dave Airlie
> Cc: Liviu Dudau
> ---
> drivers/gpu/drm/drm_fourcc.c | 12 +--
> drivers/gpu/drm/i915/intel_display.c | 18 -
> drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
> include/uapi/drm/drm_fourcc.h| 21 +--
> 4 files changed, 41 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index b914b16db9b2..6ea55fb4526d 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
> format)
> { .format = DRM_FORMAT_UYVY,.depth = 0,
> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VYUY,.depth = 0,
> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_XYUV,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y210,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VUY888, .depth = 0,
> .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> { .format = DRM_FORMAT_AYUV,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> - { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y210,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y212,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y216,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y412,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y416,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_Y412,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_Y416,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_XVYU12_16161616, .depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
Damn these 10/12 in 16 formats are annoying.
Maybe it would look nicer to put the 12 at the end?
> +
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection logic
== Series Details == Series: series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection logic URL : https://patchwork.freedesktop.org/series/58139/ State : success == Summary == CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12503_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12503_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-clear: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@gem_ctx_param@invalid-param-get: - shard-skl: NOTRUN -> FAIL [fdo#109559] * igt@gem_ctx_param@invalid-param-set: - shard-skl: NOTRUN -> FAIL [fdo#109674] * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_mmap_gtt@hang: - shard-iclb: PASS -> FAIL [fdo#109677] * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-iclb: PASS -> INCOMPLETE [fdo#109766] / [fdo#109801] * igt@gem_pwrite@stolen-uncached: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +1 * igt@gem_tiled_fence_blits@normal: - shard-iclb: PASS -> TIMEOUT [fdo#109673] +1 * igt@gem_tiled_pread_pwrite: - shard-iclb: NOTRUN -> TIMEOUT [fdo#109673] * igt@gem_userptr_blits@coherency-sync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#108059] * igt@kms_atomic_transition@3x-modeset-transitions: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +12 * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-skl: PASS -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2 * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-pageflip-hang-newfb-render-b: - shard-glk: PASS -> DMESG-WARN [fdo#107956] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +9 * igt@kms_color@pipe-a-ctm-max: - shard-skl: NOTRUN -> FAIL [fdo#108147] * igt@kms_color@pipe-a-degamma: - shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145] * igt@kms_color@pipe-b-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] +1 * igt@kms_color@pipe-b-legacy-gamma: - shard-apl: PASS -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-128x128-onscreen: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] +1 * igt@kms_cursor_crc@cursor-128x42-random: - shard-apl: PASS -> FAIL [fdo#103232] +2 * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +7 * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-iclb: PASS -> FAIL [fdo#103355] - shard-hsw: PASS -> FAIL [fdo#103355] * igt@kms_cursor_legacy@cursora-vs-flipa-toggle: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@kms_flip@flip-vs-suspend: - shard-skl: NOTRUN -> INCOMPLETE [fdo#109507] * igt@kms_force_connector_basic@force-connector-state: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-iclb: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +24 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: - shard-glk: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#103167] +6 * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-iclb: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] +1 * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt: - shard-skl: NOTRUN -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt: - shard-iclb: NOTRUN -> FAIL [fdo#109247] +1 * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +16 * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +18 * igt@kms_pipe
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/fourcc: Fix conflicting Y41x definitions
== Series Details ==
Series: drm/fourcc: Fix conflicting Y41x definitions
URL : https://patchwork.freedesktop.org/series/58182/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12512
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58182/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12512 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182] +1
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#109779]: https://bugs.freedesktop.org/show_bug.cgi?id=109779
Participating hosts (41 -> 41)
--
Additional (6): fi-bsw-n3050 fi-hsw-peppy fi-gdg-551 fi-pnv-d510 fi-bsw-kefka
fi-skl-6700k2
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5772 -> Patchwork_12512
CI_DRM_5772: 16930b29faa6d6fe08f44affe7753c85db95258f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4889: e3faf0fd49b7e3a763bf89e11fb4fdce81839da2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12512: 68cd4376136de120a91900855e9627326e8e9317 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
68cd4376136d drm/fourcc: Fix conflicting Y41x definitions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12512/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/18] drm/i915/selftests: Provide stub reset functions (rev2)
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions (rev2)
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58fb48773f00 drm/i915/selftests: Provide stub reset functions
8ad2cbde4c11 drm/i915: Flush pages on acquisition
f4793bc16874 drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h
-:652: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#652:
new file mode 100644
-:657: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#657: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:1:
+/*
-:658: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#658: FILE: drivers/gpu/drm/i915/i915_scheduler_types.h:2:
+ * SPDX-License-Identifier: MIT
-:913: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#913: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:1:
+/*
-:914: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#914: FILE: drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 5 warnings, 0 checks, 730 lines checked
1b198564eec8 drm/i915: Separate GEM context construction and registration to
userspace
e56b4575afb8 drm/i915: Introduce a mutex for file_priv->context_idr
9a2c41a4a900 drm/i915: Stop storing ctx->user_handle
ad0bb57b1067 drm/i915: Stop storing the context name as the timeline name
49a44c5b96d9 drm/i915: Introduce the i915_user_extension_method
-:72: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#72:
new file mode 100644
-:77: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#77: FILE: drivers/gpu/drm/i915/i915_user_extensions.c:1:
+/*
-:78: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#78: FILE: drivers/gpu/drm/i915/i915_user_extensions.c:2:
+ * SPDX-License-Identifier: MIT
-:144: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#144: FILE: drivers/gpu/drm/i915/i915_user_extensions.h:1:
+/*
-:145: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use
line 1 instead
#145: FILE: drivers/gpu/drm/i915/i915_user_extensions.h:2:
+ * SPDX-License-Identifier: MIT
-:178: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ptr' - possible
side-effects?
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:178: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible
side-effects?
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:178: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'member' may be better as
'(member)' to avoid precedence issues
#178: FILE: drivers/gpu/drm/i915/i915_utils.h:114:
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->member) && \
+!__same_type(*(ptr), void),\
+"pointer type mismatch in container_of()");\
+ ((type __user *)(__mptr - offsetof(type, member))); })
-:198: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'U' - possible side-effects?
#198: FILE: drivers/gpu/drm/i915/i915_utils.h:134:
+#define check_user_mbz(U) ({ \
+ typeof(*(U)) mbz__; \
+ get_user(mbz__, (U)) ? -EFAULT : mbz__ ? -EINVAL : 0; \
+})
total: 0 errors, 5 warnings, 4 checks, 153 lines checked
da478a2b2e84 drm/i915: Create/destroy VM (ppGTT) for use with contexts
-:693: WARNING:LINE_SPACING: Missing a blank line after declarations
#693: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:504:
+ struct drm_file *file;
+ IGT_TIMEOUT(end_time);
-:755: CHECK:MULTIPLE_ASSIGNMENTS: m
Re: [Intel-gfx] [PATCH 1/6] drm/i915: Reorder gen3/4 swizzle detection logic
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
g33/i964g/g45 are the exceptional cases when it comes to
the swizzle detectiong. Let's reorder the code to handle
them first and let everything else be handled by the
else branch. This allows us to unset .is_mobile for the
desktop PNV variant (which supposedly must follow the
"mobile" path here).
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 65 +++
1 file changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 65624b8e4d15..9418ad499b7e 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -585,8 +585,38 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv)
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
- } else if (IS_MOBILE(dev_priv) ||
- IS_I915G(dev_priv) || IS_I945G(dev_priv)) {
+ } else if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
+ /* The 965, G33, and newer, have a very flexible memory
+* configuration. It will enable dual-channel mode
+* (interleaving) on as much memory as it can, and the GPU
+* will additionally sometimes enable different bit 6
+* swizzling for tiled objects from the CPU.
+*
+* Here's what I found on the G965:
+*slot fill memory size swizzling
+* 0A 0B 1A 1B1-ch 2-ch
+* 512 000 5120 O
+* 512 0512 0 16 1008 X
+* 512 00512 16 1008 X
+* 0512 0512 16 1008 X
+* 1024 1024 1024 0 2048 1024 O
+*
+* We could probably detect this based on either the DRB
+* matching, which was the case for the swizzling required in
+* the table above, or from the 1-ch value being less than
+* the minimum size of a rank.
+*
+* Reports indicate that the swizzling actually
+* varies depending upon page placement inside the
+* channels, i.e. we see swizzled pages where the
+* banks of memory are paired and unswizzled on the
+* uneven portion, so leave that as unknown.
+*/
+ if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
+ swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+ swizzle_y = I915_BIT_6_SWIZZLE_9;
+ }
+ } else {
u32 dcc;
/* On 9xx chipsets, channel interleave by the CPU is
@@ -636,37 +666,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private
*dev_priv)
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
}
- } else {
- /* The 965, G33, and newer, have a very flexible memory
-* configuration. It will enable dual-channel mode
-* (interleaving) on as much memory as it can, and the GPU
-* will additionally sometimes enable different bit 6
-* swizzling for tiled objects from the CPU.
-*
-* Here's what I found on the G965:
-*slot fill memory size swizzling
-* 0A 0B 1A 1B1-ch 2-ch
-* 512 000 5120 O
-* 512 0512 0 16 1008 X
-* 512 00512 16 1008 X
-* 0512 0512 16 1008 X
-* 1024 1024 1024 0 2048 1024 O
-*
-* We could probably detect this based on either the DRB
-* matching, which was the case for the swizzling required in
-* the table above, or from the 1-ch value being less than
-* the minimum size of a rank.
-*
-* Reports indicate that the swizzling actually
-* varies depending upon page placement inside the
-* channels, i.e. we see swizzled pages where the
-* banks of memory are paired and unswizzled on the
-* uneven portion, so leave that as unknown.
-*/
- if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
- swizzle_x = I915_BIT_6_SWIZZLE_9_10;
- swizzle_y = I915_BIT_6_SWIZZLE_9;
- }
}
if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
Old/new/future behaviour checks out as far as I can see.
Review
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/18] drm/i915/selftests: Provide stub reset functions (rev2)
== Series Details == Series: series starting with [01/18] drm/i915/selftests: Provide stub reset functions (rev2) URL : https://patchwork.freedesktop.org/series/58179/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Provide stub reset functions Okay! Commit: drm/i915: Flush pages on acquisition -drivers/gpu/drm/i915/selftests/../i915_drv.h:3558:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) Commit: drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h -drivers/gpu/drm/i915/selftests/../i915_drv.h:3566:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) Commit: drm/i915: Separate GEM context construction and registration to userspace Okay! Commit: drm/i915: Introduce a mutex for file_priv->context_idr -drivers/gpu/drm/i915/selftests/../i915_drv.h:3565:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) Commit: drm/i915: Stop storing ctx->user_handle Okay! Commit: drm/i915: Stop storing the context name as the timeline name Okay! Commit: drm/i915: Introduce the i915_user_extension_method Okay! Commit: drm/i915: Create/destroy VM (ppGTT) for use with contexts -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1132:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:1132:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:565:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/selftests/i915_gem_context.c:565:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) Commit: drm/i915: Extend CONTEXT_CREATE to set parameters upon construction Okay! Commit: drm/i915: Allow contexts to share a single timeline across all engines Okay! Commit: drm/i915: Allow userspace to clone contexts on creation +drivers/gpu/drm/i915/i915_gem_context.c:1611:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1612:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1613:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1614:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1615:17: error: bad integer constant expression -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:1260:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:452:16: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:569:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/i915_gem_context.c:691:33: warning: expression using sizeof(void) -./include/linux/slab.h:664:13: warning: call with no type! Commit: drm/i915: Allow a context to define its set of engines -O:drivers/gpu/drm/i915/i915_gem_context.c:1611:17: error: bad integer constant expression -O:drivers/gpu/drm/i915/i915_gem_context.c:1612:17: error: bad integer constant expression -O:drivers/gpu/drm/i915/i915_gem_context.c:1613:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1820:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1821:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1822:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_gem_context.c:1823:17: error: bad integer constant expression +drivers/gpu/drm/i915/i915_utils.h:84:13: error: incorrect type in conditional +drivers/gpu/drm/i915/i915_utils.h:84:13: error: undefined identifier '__builtin_mul_overflow' +drivers/gpu/drm/i915/i915_utils.h:84:13:got void +dr
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Introduce i9xx_has_pfit()
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf2af75..0ddd83dbd768 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7961,14 +7961,22 @@ static int vlv_crtc_compute_clock(struct intel_crtc
*crtc,
return 0;
}
+static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
+{
+ if (IS_I830(dev_priv))
+ return false;
+
+ return IS_GEN(dev_priv, 4) ||
Shouldn't this be INTEL_GEN() >= 4 || ... ? Or even this check alone as
first in the function.
+ IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
+}
+
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
- if (INTEL_GEN(dev_priv) <= 3 &&
- (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
+ if (!i9xx_has_pfit(dev_priv))
return;
tmp = I915_READ(PFIT_CONTROL);
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: Introduce i9xx_has_pps()
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
Add a small helper to determine if we have the panel power
sequencer or not. We'll make PNV an exceptional case so
that we can unset .is_mobile for the desktop variant.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0ddd83dbd768..2ba61181746d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1441,6 +1441,14 @@ static void chv_enable_pll(struct intel_crtc *crtc,
}
}
+static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
+{
+ if (IS_I830(dev_priv))
+ return false;
+
+ return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
+}
+
static void i9xx_enable_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state)
{
@@ -1452,7 +1460,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
assert_pipe_disabled(dev_priv, crtc->pipe);
/* PLL is protected by panel, make sure we can write it */
- if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
+ if (i9xx_has_pps(dev_priv))
assert_panel_unlocked(dev_priv, crtc->pipe);
/*
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 4/6] drm/i915: Introduce i915_has_asle()
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
We want to allow the desktop PNV to not have .is_mobile set. To
that end let's add a small helper to determine if the platform
has the ASLE interrupt (or equivalent). Supposdely both PNV
variants have it.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 82d487189a34..1375bba45548 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -748,13 +748,21 @@ void i915_disable_pipestat(struct drm_i915_private
*dev_priv,
POSTING_READ(reg);
}
+static bool i915_has_asle(struct drm_i915_private *dev_priv)
+{
+ if (!dev_priv->opregion.asle)
+ return false;
+
+ return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
+}
+
/**
* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
* @dev_priv: i915 device private
*/
static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
{
- if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
+ if (!i915_has_asle(dev_priv))
return;
spin_lock_irq(&dev_priv->irq_lock);
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
___
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Re: [Intel-gfx] [PATCH 5/6] drm/i915: Use HPLLVCO_MOBILE for all PNVs
On 18/03/2019 16:56, Ville Syrjala wrote: From: Ville Syrjälä To allow unsetting .is_mobile for the desktop variant of PNV fix up the cdclk code to select the mobile HPLLVCO register for both PNV variants. Cc: Tvrtko Ursulin Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_cdclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 21fb4e0d6c4e..d27ccd23d753 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -234,7 +234,8 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) else return 0; - tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); + tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? + HPLLVCO_MOBILE : HPLLVCO); vco = vco_table[tmp & 0x7]; if (vco == 0) Reviewed-by: Tvrtko Ursulin Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/18] drm/i915/selftests: Provide stub reset functions (rev2)
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions (rev2)
URL : https://patchwork.freedesktop.org/series/58179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12513
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58179/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12513 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +55
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182]
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
* igt@kms_chamelium@hdmi-edid-read:
- fi-hsw-peppy: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: NOTRUN -> DMESG-FAIL [fdo#102614] / [fdo#107814]
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- {fi-icl-y}: DMESG-WARN [fdo#109638] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107814]: https://bugs.freedesktop.org/show_bug.cgi?id=107814
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
Participating hosts (41 -> 42)
--
Additional (6): fi-bsw-n3050 fi-hsw-peppy fi-gdg-551 fi-pnv-d510 fi-bsw-kefka
fi-skl-6700k2
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5772 -> Patchwork_12513
CI_DRM_5772: 16930b29faa6d6fe08f44affe7753c85db95258f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4889: e3faf0fd49b7e3a763bf89e11fb4fdce81839da2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12513: d1d3ac6c6916aef024319e1a68735327b326391f @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d1d3ac6c6916 drm/i915: Allow specification of parallel execbuf
c584d1697f6f drm/i915/execlists: Virtual engine bonding
9a7b936e9c73 drm/i915: Extend execution fence to support a callback
8df62463e41e drm/i915: Load balancing across a virtual engine
d64f177b1ad9 drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local
ctx->engine[]
a9295a3f81ed drm/i915: Allow a context to define its set of engines
281831a71ef7 drm/i915: Allow userspace to clone contexts on creation
32f18f1740ab drm/i915: Allow contexts to share a single timeline across all
engines
ab79a55630ef drm/i915: Extend CONTEXT_CREATE to set parameters upon construction
da478a2b2e84 drm/i915: Create/destroy VM (ppGTT) for use with contexts
49a44c5b96d9 drm/i915: Introduce the i915_user_extension_method
ad0bb57b1067 drm/i915: Stop storing the context name as the timeline name
9a2c41a4a900 drm/i915: Stop storing ctx->user_handle
e56b4575afb8 drm/i915: Introduce a mutex for file_priv->context_idr
1b198564eec8 drm/i915: Separate GEM context construction and registration to
userspace
f4793bc16874 drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h
8ad2cbde4c11 drm/i915: Flush pages on acquisition
58fb48773f00 drm/i915/selftests: Provide stub reset functions
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12513/
___
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Re: [Intel-gfx] [PATCH 6/6] drm/i915: Clean up gen2 DPLL readout
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
The current gen2 DPLL readout code:
* assumes i845/i865 have LVDS which is not true
* assumes only pipe B can drive LVDS (true, but makes
the code appear a bit magical)
* hard to parse in general
Clean it up by checking for i85x (the only gen2 platform
with LVDS) and reusing intel_lvds_port_enabled().
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2ba61181746d..9f31d94fc04b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10809,7 +10809,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int pipe = pipe_config->cpu_transcoder;
u32 dpll = pipe_config->dpll_hw_state.dpll;
u32 fp;
struct dpll clock;
@@ -10858,10 +10857,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc
*crtc,
else
port_clock = i9xx_calc_dpll_params(refclk, &clock);
} else {
- u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
- bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
+ enum pipe lvds_pipe;
+
+ if (IS_I85X(dev_priv) &&
+ intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
+ lvds_pipe == crtc->pipe) {
+ u32 lvds = I915_READ(LVDS);
- if (is_lvds) {
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS)
>>
DPLL_FPA01_P1_POST_DIV_SHIFT);
I defer to domain experts on this one.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 04/18] drm/i915: Separate GEM context construction and registration to userspace
On 19/03/2019 11:57, Chris Wilson wrote:
In later patches, it became apparent that userspace can see a partially
constructed GEM context and begin using it before it was ready, to much
hilarity. Close this window of opportunity by lifting the registration of
the context with userspace (the insertion of the context into the filp's
idr) to the very end of the CONTEXT_CREATE ioctl.
Thanks, persistent absence of change logs really helps me.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 138 ++
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 8 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 12 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 17 ++-
7 files changed, 111 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 2fa24326307a..dff4220df911 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -337,15 +337,13 @@ static u32 default_desc_template(const struct
drm_i915_private *i915,
}
static struct i915_gem_context *
-__create_hw_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+__create_context(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
int i;
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
- if (ctx == NULL)
+ if (!ctx)
return ERR_PTR(-ENOMEM);
kref_init(&ctx->ref);
@@ -362,29 +360,6 @@ __create_hw_context(struct drm_i915_private *dev_priv,
INIT_LIST_HEAD(&ctx->handles_list);
INIT_LIST_HEAD(&ctx->hw_id_link);
- /* Default context will never have a file_priv */
- ret = DEFAULT_CONTEXT_HANDLE;
- if (file_priv) {
- ret = idr_alloc(&file_priv->context_idr, ctx,
- DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
- if (ret < 0)
- goto err_lut;
- }
- ctx->user_handle = ret;
-
- ctx->file_priv = file_priv;
- if (file_priv) {
- ctx->pid = get_task_pid(current, PIDTYPE_PID);
- ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
- current->comm,
- pid_nr(ctx->pid),
- ctx->user_handle);
- if (!ctx->name) {
- ret = -ENOMEM;
- goto err_pid;
- }
- }
-
/* NB: Mark all slices as needing a remap so that when the context first
* loads it will restore whatever remap state already exists. If there
* is no remap info, it will be a NOP. */
@@ -401,25 +376,10 @@ __create_hw_context(struct drm_i915_private *dev_priv,
ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
return ctx;
-
-err_pid:
- put_pid(ctx->pid);
- idr_remove(&file_priv->context_idr, ctx->user_handle);
-err_lut:
- context_close(ctx);
- return ERR_PTR(ret);
-}
-
-static void __destroy_hw_context(struct i915_gem_context *ctx,
-struct drm_i915_file_private *file_priv)
-{
- idr_remove(&file_priv->context_idr, ctx->user_handle);
- context_close(ctx);
}
static struct i915_gem_context *
-i915_gem_create_context(struct drm_i915_private *dev_priv,
- struct drm_i915_file_private *file_priv)
+i915_gem_create_context(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
@@ -428,18 +388,18 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
/* Reap the most stale context */
contexts_free_first(dev_priv);
- ctx = __create_hw_context(dev_priv, file_priv);
+ ctx = __create_context(dev_priv);
if (IS_ERR(ctx))
return ctx;
if (HAS_FULL_PPGTT(dev_priv)) {
struct i915_hw_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(dev_priv, file_priv);
+ ppgtt = i915_ppgtt_create(dev_priv);
if (IS_ERR(ppgtt)) {
DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
- __destroy_hw_context(ctx, file_priv);
+ context_close(ctx);
return ERR_CAST(ppgtt);
}
@@ -475,7 +435,7 @@ i915_gem_context_create_gvt(struct drm_device *dev)
if (ret)
return ERR_PTR(ret);
- ctx = i915_gem_create_context(to_i915(dev), NULL);
+ ctx = i915_gem_create_context(to_i915(dev));
if (IS_ERR(ctx))
goto out;
@@ -511,7 +471,7 @@ i915_gem_context_cr
[Intel-gfx] [PATCH] drm/i915/selftests: Calculate maximum ring size for preemption chain
32 is too many for the likes of kbl, and in order to insert that many
requests into the ring requires us to declare the first few hung --
understandably a slow and unexpected process. Instead, measure the size
of a singe requests and use that to estimate the upper bound on the
chain length we can use for our test, remembering to flush the previous
chain between tests for safety.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 40 --
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c
b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index d61520ea03c1..42068ed5eec0 100644
--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
@@ -615,14 +615,33 @@ static int live_chain_preempt(void *arg)
struct i915_sched_attr attr = {
.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
};
- int count, i;
+ struct i915_request *rq;
+ int ring_size, count, i;
if (!intel_engine_has_preemption(engine))
continue;
- for_each_prime_number_from(count, 1, 32) { /* must fit ring! */
- struct i915_request *rq;
+ rq = igt_spinner_create_request(&lo.spin,
+ lo.ctx, engine,
+ MI_ARB_CHECK);
+ if (IS_ERR(rq))
+ goto err_wedged;
+ i915_request_add(rq);
+
+ ring_size = rq->wa_tail - rq->head;
+ if (ring_size < 0)
+ ring_size += rq->ring->size;
+ ring_size = rq->ring->size / ring_size;
+ pr_debug("%s(%s): Using maximum of %d requests\n",
+__func__, engine->name, ring_size);
+ igt_spinner_end(&lo.spin);
+ if (i915_request_wait(rq, I915_WAIT_LOCKED, HZ / 2) < 0) {
+ pr_err("Timed out waiting to flush %s\n", engine->name);
+ goto err_wedged;
+ }
+
+ for_each_prime_number_from(count, 1, ring_size) {
rq = igt_spinner_create_request(&hi.spin,
hi.ctx, engine,
MI_ARB_CHECK);
@@ -664,6 +683,21 @@ static int live_chain_preempt(void *arg)
goto err_wedged;
}
igt_spinner_end(&lo.spin);
+
+ rq = i915_request_alloc(engine, lo.ctx);
+ if (IS_ERR(rq))
+ goto err_wedged;
+ i915_request_add(rq);
+ if (i915_request_wait(rq, I915_WAIT_LOCKED, HZ / 5) <
0) {
+ struct drm_printer p =
+ drm_info_printer(i915->drm.dev);
+
+ pr_err("Failed to flush low priority chain of
%d requests\n",
+ count);
+ intel_engine_dump(engine, &p,
+ "%s\n", engine->name);
+ goto err_wedged;
+ }
}
}
--
2.20.1
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Re: [Intel-gfx] [PATCH 04/18] drm/i915: Separate GEM context construction and registration to userspace
Quoting Tvrtko Ursulin (2019-03-19 13:41:37) > > On 19/03/2019 11:57, Chris Wilson wrote: > > In later patches, it became apparent that userspace can see a partially > > constructed GEM context and begin using it before it was ready, to much > > hilarity. Close this window of opportunity by lifting the registration of > > the context with userspace (the insertion of the context into the filp's > > idr) to the very end of the CONTEXT_CREATE ioctl. > > Thanks, persistent absence of change logs really helps me. And nothing of significance changed, that was the point. The debug name of the context was changed to avoid having the self-referential problem of how to get the ctx-id but set the ctx->name prior to inserting the id into the context; which could have been pushed under the idr_lock, but I choose to take the course of removing the extra user_handle as evidenced by the next few patches. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORMAT_XVYU2101010
>
> commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
> Author: Brian Starkey
> Date: Fri Oct 5 10:27:00 2018 +0100
>
> drm/fourcc: Add AFBC yuv fourccs for Mali
>
> and
>
> commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
> Author: Swati Sharma
> Date: Mon Mar 4 17:26:33 2019 +0530
>
> drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
>
> Unfortunately gcc didn't warn about the redefinitions, because the
>
> Fix this by using new XYVU for i915, without alpha, and making the
> Y41x definitions match msdn, with alpha.
>
> Fortunately we caught it early, and the conflict hasn't even landed in
> drm-next yet.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Brian Starkey
> Cc: Swati Sharma
> Cc: Ayan Kumar Halder
> Cc: mal...@foss.arm.com
> Cc: Daniel Vetter
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: Dave Airlie
> Cc: Liviu Dudau
> ---
> drivers/gpu/drm/drm_fourcc.c | 12 +--
> drivers/gpu/drm/i915/intel_display.c | 18 -
> drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
> include/uapi/drm/drm_fourcc.h| 21 +--
> 4 files changed, 41 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index b914b16db9b2..6ea55fb4526d 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
> format)
> { .format = DRM_FORMAT_UYVY,.depth = 0,
> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VYUY,.depth = 0,
> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_XYUV,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y210,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VUY888, .depth = 0,
> .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> { .format = DRM_FORMAT_AYUV,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> - { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y210,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y212,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y216,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y412,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_Y416,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_Y410,.depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_Y412,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_Y416,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
> .is_yuv = true },
> + { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_XVYU12_16161616, .depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_XVYU16161616,.depth = 0,
> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_Y0L0,.depth = 0,
> .num_planes = 1,
> .char_per_
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev5)
== Series Details == Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev5) URL : https://patchwork.freedesktop.org/series/57900/ State : success == Summary == CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12504_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12504_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] * igt@gem_mmap_gtt@hang: - shard-iclb: PASS -> FAIL [fdo#109677] * igt@gem_ppgtt@blt-vs-render-ctx0: - shard-iclb: PASS -> INCOMPLETE [fdo#109766] / [fdo#109801] * igt@gem_pwrite@stolen-uncached: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +1 * igt@gem_tiled_swapping@non-threaded: - shard-apl: PASS -> DMESG-WARN [fdo#108686] * igt@gem_userptr_blits@coherency-sync: - shard-iclb: NOTRUN -> SKIP [fdo#109290] * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#108059] * igt@i915_suspend@forcewake: - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-pageflip-hang-newfb-render-b: - shard-glk: PASS -> DMESG-WARN [fdo#107956] * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-iclb: PASS -> FAIL [fdo#107725] * igt@kms_chamelium@vga-edid-read: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +9 * igt@kms_color@pipe-b-ctm-0-75: - shard-skl: PASS -> FAIL [fdo#108682] * igt@kms_color@pipe-b-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] +1 * igt@kms_cursor_crc@cursor-128x128-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_cursor_crc@cursor-128x42-offscreen: - shard-skl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +7 * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-iclb: PASS -> FAIL [fdo#103355] * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: NOTRUN -> FAIL [fdo#105363] * igt@kms_flip_tiling@flip-y-tiled: - shard-skl: NOTRUN -> FAIL [fdo#108303] * igt@kms_force_connector_basic@force-connector-state: - shard-iclb: NOTRUN -> SKIP [fdo#109285] * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109280] +24 * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-glk: PASS -> FAIL [fdo#103167] +2 * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt: - shard-iclb: PASS -> FAIL [fdo#109247] +16 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: PASS -> FAIL [fdo#103167] +4 * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247] * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +18 * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +1 * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-kbl: NOTRUN -> INCOMPLETE [fdo#103665] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +10 * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_scaling@2x-scaler-multi-pipe: - shard-iclb: NOTRUN -> SKIP [fdo#109274] / [fdo#109278] * igt@kms_psr@no_drrs: - shard-iclb: PASS -> FAIL [fdo#108341] * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: PASS -> SKIP [fdo#109441] * igt@kms_psr@psr2_cursor_render: - shard-iclb: NOTRUN -> SKIP [fdo#109441] +2 * igt@kms_psr@sprite_mmap_cpu: - shard-iclb: PASS -> FAIL [fdo#107383] +2 * igt@kms_setmode@basic: - shard-skl: NOTRUN -> FAIL [fdo#99912] - shard-iclb: NOTRUN -> FAIL [fdo#99912] - shard-hsw: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-a-ts-continuation-sus
Re: [Intel-gfx] [PATCH 2/6] drm/i915: Introduce i9xx_has_pfit()
On Tue, Mar 19, 2019 at 01:24:16PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make the code self-documenting by introducing i9xx_has_pfit().
> > Also make PNV an exceptional case so that we can unset
> > .is_mobile for the desktop variant.
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 12 ++--
> > 1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 61acbaf2af75..0ddd83dbd768 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7961,14 +7961,22 @@ static int vlv_crtc_compute_clock(struct intel_crtc
> > *crtc,
> > return 0;
> > }
> >
> > +static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
> > +{
> > + if (IS_I830(dev_priv))
> > + return false;
> > +
> > + return IS_GEN(dev_priv, 4) ||
>
> Shouldn't this be INTEL_GEN() >= 4 || ... ? Or even this check alone as
> first in the function.
Doh. I had it as >=4 initially, but then decided that ilk+ aren't
relevant here and tweaked it to gen4 only. Which means I totally
forgot about vlv/chv. v2 coming up.
>
> > + IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
> > +}
> > +
> > static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> > struct intel_crtc_state *pipe_config)
> > {
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > u32 tmp;
> >
> > - if (INTEL_GEN(dev_priv) <= 3 &&
> > - (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
> > + if (!i9xx_has_pfit(dev_priv))
> > return;
> >
> > tmp = I915_READ(PFIT_CONTROL);
> >
>
> Regards,
>
> Tvrtko
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 6/6] drm/i915: Clean up gen2 DPLL readout
On Tue, Mar 19, 2019 at 01:34:31PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The current gen2 DPLL readout code:
> > * assumes i845/i865 have LVDS which is not true
> > * assumes only pipe B can drive LVDS (true, but makes
> >the code appear a bit magical)
> > * hard to parse in general
> >
> > Clean it up by checking for i85x (the only gen2 platform
> > with LVDS) and reusing intel_lvds_port_enabled().
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Ville Syrjälä
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 10 ++
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 2ba61181746d..9f31d94fc04b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10809,7 +10809,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc
> > *crtc,
> > {
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > - int pipe = pipe_config->cpu_transcoder;
> > u32 dpll = pipe_config->dpll_hw_state.dpll;
> > u32 fp;
> > struct dpll clock;
> > @@ -10858,10 +10857,13 @@ static void i9xx_crtc_clock_get(struct intel_crtc
> > *crtc,
> > else
> > port_clock = i9xx_calc_dpll_params(refclk, &clock);
> > } else {
> > - u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
> > - bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
> > + enum pipe lvds_pipe;
> > +
> > + if (IS_I85X(dev_priv) &&
> > + intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
> > + lvds_pipe == crtc->pipe) {
> > + u32 lvds = I915_READ(LVDS);
> >
> > - if (is_lvds) {
> > clock.p1 = ffs((dpll &
> > DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
> >DPLL_FPA01_P1_POST_DIV_SHIFT);
> >
> >
>
> I defer to domain experts on this one.
Yeah. This wasn't really meant to be part of this series. It just
happened to live in the same branch where I had already typed up
some of the i9xx_has_pfit() etc. and hence got piggybacked to the
list.
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/cml: Add CML PCI IDS
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/58147/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12505_full
Summary
---
**SUCCESS**
No regressions found.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_12505_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@pixel-format-pipe-a-planes-source-clamping}:
- shard-glk: SKIP [fdo#109271] -> FAIL
Known issues
Here are the changes found in Patchwork_12505_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +13
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: PASS -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-modeset-hang-newfb-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb-render-xtiled:
- shard-snb: PASS -> SKIP [fdo#109271] +1
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: PASS -> FAIL [fdo#103060]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: NOTRUN -> FAIL [fdo#108303]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: NOTRUN -> INCOMPLETE [fdo#103665]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
- shard-hsw: PASS -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +116
* igt@sw_sync@sync_busy_fork_unixsocket:
- shard-skl: NOTRUN -> FAIL [fdo#110150 ]
* igt@tools_test@tools_test:
- shard-apl: PASS -> SKIP [fdo#109271]
Possible fixes
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS +2
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-skl: FAIL [fdo#107362] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-glk: FAIL [fdo#
[Intel-gfx] [PATCH v2 2/6] drm/i915: Introduce i9xx_has_pfit()
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
v2: s/gen4/gen>=4/ (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf2af75..98270d0cd763 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7961,14 +7961,22 @@ static int vlv_crtc_compute_clock(struct intel_crtc
*crtc,
return 0;
}
+static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
+{
+ if (IS_I830(dev_priv))
+ return false;
+
+ return INTEL_GEN(dev_priv) >= 4 ||
+ IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
+}
+
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
- if (INTEL_GEN(dev_priv) <= 3 &&
- (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
+ if (!i9xx_has_pfit(dev_priv))
return;
tmp = I915_READ(PFIT_CONTROL);
--
2.19.2
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Add some missing curly braces
== Series Details ==
Series: series starting with [1/3] drm/i915: Add some missing curly braces
URL : https://patchwork.freedesktop.org/series/58148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12506_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12506_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
* igt@i915_pm_rpm@sysfs-read:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: PASS -> FAIL [fdo#108682]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x42-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: NOTRUN -> INCOMPLETE [fdo#103665]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-hsw: PASS -> FAIL [fdo#99912]
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +63
* igt@sw_sync@sync_busy_fork_unixsocket:
- shard-skl: NOTRUN -> FAIL [fdo#110150 ]
Possible fixes
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* {igt@kms_plane@pixel-format-pipe-b-planes}:
- shard-glk: SKIP [fdo#109271] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: FAIL [fdo#108145] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-c-tiling-yf}:
- shard-apl: FAIL [fdo#110037] -> PASS +1
* igt@kms_vblank@pipe-b-wait-idle-hang:
- shard-snb: SKIP [fdo#109271] -> PASS +2
Warnings
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freede
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915: Lock the gem_context->active_list while dropping the link
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Lock the
gem_context->active_list while dropping the link
URL : https://patchwork.freedesktop.org/series/58151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12507_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12507_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
* igt@gem_softpin@noreloc-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_pm_rpm@gem-evict-pwrite:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@i915_pm_rpm@gem-idle:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@kms_busy@basic-modeset-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-128x128-left-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: PASS -> FAIL [fdo#105767]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_flip_tiling@flip-y-tiled:
- shard-skl: NOTRUN -> FAIL [fdo#108303]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-apl: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +106
* igt@sw_sync@sync_busy_fork_unixsocket:
- shard-skl: NOTRUN -> FAIL [fdo#110150 ]
* igt@tools_test@sysfs_l3_parity:
- shard-hsw: PASS -> SKIP [fdo#109271]
* igt@tools_test@tools_test:
- shard-snb: PASS -> SKIP [fdo#109271]
Possible fixes
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- shard-skl: FAIL [fdo#103184] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb-render-untiled:
- shard-snb: SKIP [fdo#109271] -> PASS +1
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS +1
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-skl: FAIL [fdo#107362] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-glk: FAIL [fdo#110037] -> PASS +1
* {igt@kms_plane_multiple@atomic-pipe-c-tiling-yf}:
- shard-apl: FAIL [fdo#110037] -> PASS +1
* igt@kms_plane_scaling@pipe-a-scaler-with-clipping-clamping:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- sh
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915: Add support for retrying hotplug
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Add support for retrying hotplug
URL : https://patchwork.freedesktop.org/series/58156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12508_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12508_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@vecs0-s3:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@gem_ctx_param@invalid-param-get:
- shard-skl: NOTRUN -> FAIL [fdo#109559]
* igt@gem_ctx_param@invalid-param-set:
- shard-skl: NOTRUN -> FAIL [fdo#109674]
* igt@i915_pm_rpm@pc8-residency:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#107807]
* igt@kms_busy@basic-modeset-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-skl: PASS -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-glk: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_color@pipe-c-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-128x42-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: PASS -> FAIL [fdo#103355]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167] +1
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +18
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: NOTRUN -> INCOMPLETE [fdo#103665]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: PASS -> FAIL [fdo#109016]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@perf_pmu@busy-accuracy-98-vcs1:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +104
* igt@sw_sync@sync_busy_fork_unixsocket:
- shard-skl: NOTRUN -> FAIL [fdo#110150 ]
Possible fixes
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- shard-snb: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x85-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- shard-skl: FAIL [fdo#103184] -> PASS +1
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
- shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-none}:
- shard-glk: FAIL [fdo#110037] -> PASS
* {igt@kms_plane_multiple@atomic-pipe-b-tiling-x}:
- shard-apl: FAIL [fdo#110037] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_vblank@pipe-b-wait-idle-hang:
- shard-snb: SKIP [fdo#109271] -> PASS +2
Warnings
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_plane_scaling@pipe-c-scaler-w
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add some missing curly braces
On Mon, Mar 18, 2019 at 01:34:37PM -0700, Rodrigo Vivi wrote:
> On Mon, Mar 18, 2019 at 10:26:51PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Sprinkle some curly braces in accordance with the coding style.
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Rodrigo Vivi
Thanks. Series pushed to dinq.
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 11 +++
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 61acbaf2af75..bfe792789a52 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1621,14 +1621,15 @@ static void ironlake_enable_pch_transcoder(const
> > struct intel_crtc_state *crtc_s
> > }
> >
> > val &= ~TRANS_INTERLACE_MASK;
> > - if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
> > + if ((pipeconf_val & PIPECONF_INTERLACE_MASK) ==
> > PIPECONF_INTERLACED_ILK) {
> > if (HAS_PCH_IBX(dev_priv) &&
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> > val |= TRANS_LEGACY_INTERLACED_ILK;
> > else
> > val |= TRANS_INTERLACED;
> > - else
> > + } else {
> > val |= TRANS_PROGRESSIVE;
> > + }
> >
> > I915_WRITE(reg, val | TRANS_ENABLE);
> > if (intel_wait_for_register(dev_priv,
> > @@ -7759,8 +7760,9 @@ static void i9xx_set_pipeconf(const struct
> > intel_crtc_state *crtc_state)
> > pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> > else
> > pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
> > - } else
> > + } else {
> > pipeconf |= PIPECONF_PROGRESSIVE;
> > + }
> >
> > if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > crtc_state->limited_color_range)
> > @@ -8876,8 +8878,9 @@ static void ironlake_compute_dpll(struct intel_crtc
> > *intel_crtc,
> > dev_priv->vbt.lvds_ssc_freq == 10) ||
> > (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
> > factor = 25;
> > - } else if (crtc_state->sdvo_tv_clock)
> > + } else if (crtc_state->sdvo_tv_clock) {
> > factor = 20;
> > + }
> >
> > fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
> >
> > --
> > 2.19.2
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Calculate maximum ring size for preemption chain
== Series Details ==
Series: drm/i915/selftests: Calculate maximum ring size for preemption chain
URL : https://patchwork.freedesktop.org/series/58188/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12514
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58188/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12514 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] +106
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: NOTRUN -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-gdg-551: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> SKIP [fdo#109271] +41
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_exec_suspend@basic-s4-devices:
- {fi-icl-y}: DMESG-WARN [fdo#109638] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (41 -> 39)
--
Additional (4): fi-gdg-551 fi-bsw-n3050 fi-skl-6700k2 fi-pnv-d510
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-snb-2520m
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5772 -> Patchwork_12514
CI_DRM_5772: 16930b29faa6d6fe08f44affe7753c85db95258f @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4889: e3faf0fd49b7e3a763bf89e11fb4fdce81839da2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12514: 07a8fb8e3204aef541b52dfb5d8990e54782fb70 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
07a8fb8e3204 drm/i915/selftests: Calculate maximum ring size for preemption
chain
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12514/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Pass dev_priv to intel_is_dual_link_lvds()
On Mon, 18 Mar 2019, Ville Syrjälä wrote: > On Mon, Mar 18, 2019 at 09:45:16PM +0100, Michal Wajdeczko wrote: >> > Make things look a bit nicer by passing dev_priv to >> >> In other places we are changing naming from dev_priv to i915. >> Can we do the same here ? > > The display code uses dev_priv quite consistently,. We could > go for i915 I suppose but I'd prefer a mass conversion rather > than the death by a thousand cuts approach. The display > code is already messy enough when it comes to naming local > variables. We could use i915 in display code as a convention for code that does not do register access. ;) BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection logic (rev2)
== Series Details ==
Series: series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection
logic (rev2)
URL : https://patchwork.freedesktop.org/series/58139/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5773 -> Patchwork_12515
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/58139/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12515 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-gfx0:
- fi-cfl-guc: NOTRUN -> SKIP [fdo#109271] +49
* igt@gem_close_race@basic-process:
- fi-skl-6770hq: PASS -> DMESG-WARN [fdo#105541]
* igt@gem_exec_basic@readonly-bsd2:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@basic-flip-c:
- fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +62
* igt@kms_force_connector_basic@force-load-detect:
- fi-bxt-j4205: NOTRUN -> SKIP [fdo#109271] +47
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
Possible fixes
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
Participating hosts (43 -> 41)
--
Additional (4): fi-cfl-guc fi-bxt-j4205 fi-bsw-n3050 fi-pnv-d510
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5773 -> Patchwork_12515
CI_DRM_5773: b1f30d7018c1d5f9e9abfb5dc6b8d84c3148dd57 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4889: e3faf0fd49b7e3a763bf89e11fb4fdce81839da2 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12515: 665759afae799b5e9acfa68256342652b0c0f406 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
665759afae79 drm/i915: Clean up gen2 DPLL readout
b78fc6aef66b drm/i915: Use HPLLVCO_MOBILE for all PNVs
c58b8fe1d55f drm/i915: Introduce i915_has_asle()
4f86f82f9a45 drm/i915: Introduce i9xx_has_pps()
b5d3b94a82d1 drm/i915: Introduce i9xx_has_pfit()
90f3794d0025 drm/i915: Reorder gen3/4 swizzle detection logic
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12515/
___
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[Intel-gfx] [PATCH v2 4/9] drm/i915: Allocate enough DDB for the cursor
From: Ville Syrjälä
Currently we just assume that 32 or 8 blocks of ddb is sufficient
for the cursor. The 32 might be, but the 8 is certainly not. The
minimum we need is at least what level 0 watermarks need, but that
is a bit restrictive, so instead let's calculate what level 7
would need for a 256x256 cursor. We'll use that to determine the
fixed ddb allocation for the cursor. This way the cursor will never
be responsible for missing out on deeper power saving states.
v2: Loop to make sure this works even if some wm levels are
totally disabled (latency==0)
Cc: Neel Desai
Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper #v1
---
drivers/gpu/drm/i915/intel_pm.c | 41 +
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e7b4412f7a8..b35a55a59680 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3924,12 +3924,43 @@ skl_ddb_get_pipe_allocation_limits(struct
drm_i915_private *dev_priv,
alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
}
-static unsigned int skl_cursor_allocation(int num_active)
+static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
+int width, const struct drm_format_info
*format,
+u64 modifier, unsigned int rotation,
+u32 plane_pixel_rate, struct skl_wm_params *wp,
+int color_plane);
+static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
+int level,
+const struct skl_wm_params *wp,
+const struct skl_wm_level *result_prev,
+struct skl_wm_level *result /* out */);
+
+static unsigned int
+skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
+ int num_active)
{
- if (num_active == 1)
- return 32;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
+ struct skl_wm_level wm = {};
+ int ret, min_ddb_alloc = 0;
+ struct skl_wm_params wp;
+
+ ret = skl_compute_wm_params(crtc_state, 256,
+ drm_format_info(DRM_FORMAT_ARGB),
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_MODE_ROTATE_0,
+ crtc_state->pixel_rate, &wp, 0);
+ WARN_ON(ret);
+
+ for (level = 0; level <= max_level; level++) {
+ skl_compute_plane_wm(crtc_state, 7, &wp, &wm, &wm);
+ if (wm.min_ddb_alloc == U16_MAX)
+ break;
+
+ min_ddb_alloc = wm.min_ddb_alloc;
+ }
- return 8;
+ return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
}
static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
@@ -4354,7 +4385,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
return 0;
/* Allocate fixed number of blocks for cursor. */
- total[PLANE_CURSOR] = skl_cursor_allocation(num_active);
+ total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
alloc_size -= total[PLANE_CURSOR];
cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
alloc->end - total[PLANE_CURSOR];
--
2.19.2
___
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Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
> On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
>> There has unfortunately been a conflict with the following 3 commits:
>>
>> commit e9961ab95af81b8d29054361cd5f0c575102cf87
>> Author: Ayan Kumar Halder
>> Date: Fri Nov 9 17:21:12 2018 +
>> drm: Added a new format DRM_FORMAT_XVYU2101010
>>
>> commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
>> Author: Brian Starkey
>> Date: Fri Oct 5 10:27:00 2018 +0100
>>
>> drm/fourcc: Add AFBC yuv fourccs for Mali
>>
>> and
>>
>> commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
>> Author: Swati Sharma
>> Date: Mon Mar 4 17:26:33 2019 +0530
>>
>> drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
>>
>> Unfortunately gcc didn't warn about the redefinitions, because the
>>
>> Fix this by using new XYVU for i915, without alpha, and making the
>> Y41x definitions match msdn, with alpha.
> The naming of all these is rather unfortunate because now the alpha vs.
> non-alpha formats have totally different looking names :( Fourccs are
> stupid!
>
>> Fortunately we caught it early, and the conflict hasn't even landed in
>> drm-next yet.
>>
>> Signed-off-by: Maarten Lankhorst
>> Cc: Brian Starkey
>> Cc: Swati Sharma
>> Cc: Ayan Kumar Halder
>> Cc: mal...@foss.arm.com
>> Cc: Daniel Vetter
>> Cc: Maxime Ripard
>> Cc: Sean Paul
>> Cc: Dave Airlie
>> Cc: Liviu Dudau
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 12 +--
>> drivers/gpu/drm/i915/intel_display.c | 18 -
>> drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
>> include/uapi/drm/drm_fourcc.h| 21 +--
>> 4 files changed, 41 insertions(+), 40 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index b914b16db9b2..6ea55fb4526d 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
>> format)
>> { .format = DRM_FORMAT_UYVY,.depth = 0,
>> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_VYUY,.depth = 0,
>> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_XYUV,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> -{ .format = DRM_FORMAT_Y210,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_VUY888, .depth = 0,
>> .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> -{ .format = DRM_FORMAT_Y410,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
>> true, .is_yuv = true },
>> { .format = DRM_FORMAT_AYUV,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
>> true, .is_yuv = true },
>> -{ .format = DRM_FORMAT_XVYU2101010, .depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_Y210,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_Y212,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_Y216,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> -{ .format = DRM_FORMAT_Y410,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> -{ .format = DRM_FORMAT_Y412,.depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> -{ .format = DRM_FORMAT_Y416,.depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> +{ .format = DRM_FORMAT_Y410,.depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
>> true, .is_yuv = true },
>> +{ .format = DRM_FORMAT_Y412,.depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
>> true, .is_yuv = true },
>> +{ .format = DRM_FORMAT_Y416,.depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
>> true, .is_yuv = true },
>> +{ .format = DRM_FORMAT_XVYU2101010, .depth = 0,
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>> +{ .format = DRM_FORMAT_XVYU12_16161616, .depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true }
Re: [Intel-gfx] [PATCH] drm/fourcc: Fix conflicting Y41x definitions
On Tue, Mar 19, 2019 at 05:06:36PM +0100, Maarten Lankhorst wrote:
> Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
> > On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> >> There has unfortunately been a conflict with the following 3 commits:
> >>
> >> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> >> Author: Ayan Kumar Halder
> >> Date: Fri Nov 9 17:21:12 2018 +
> >> drm: Added a new format DRM_FORMAT_XVYU2101010
> >>
> >> commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
> >> Author: Brian Starkey
> >> Date: Fri Oct 5 10:27:00 2018 +0100
> >>
> >> drm/fourcc: Add AFBC yuv fourccs for Mali
> >>
> >> and
> >>
> >> commit 50bf5d7d595fd0705ef3785f80e679b6da501e5b
> >> Author: Swati Sharma
> >> Date: Mon Mar 4 17:26:33 2019 +0530
> >>
> >> drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
> >>
> >> Unfortunately gcc didn't warn about the redefinitions, because the
> >>
> >> Fix this by using new XYVU for i915, without alpha, and making the
> >> Y41x definitions match msdn, with alpha.
> > The naming of all these is rather unfortunate because now the alpha vs.
> > non-alpha formats have totally different looking names :( Fourccs are
> > stupid!
> >
> >> Fortunately we caught it early, and the conflict hasn't even landed in
> >> drm-next yet.
> >>
> >> Signed-off-by: Maarten Lankhorst
> >> Cc: Brian Starkey
> >> Cc: Swati Sharma
> >> Cc: Ayan Kumar Halder
> >> Cc: mal...@foss.arm.com
> >> Cc: Daniel Vetter
> >> Cc: Maxime Ripard
> >> Cc: Sean Paul
> >> Cc: Dave Airlie
> >> Cc: Liviu Dudau
> >> ---
> >> drivers/gpu/drm/drm_fourcc.c | 12 +--
> >> drivers/gpu/drm/i915/intel_display.c | 18 -
> >> drivers/gpu/drm/i915/intel_sprite.c | 30 ++--
> >> include/uapi/drm/drm_fourcc.h| 21 +--
> >> 4 files changed, 41 insertions(+), 40 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> >> index b914b16db9b2..6ea55fb4526d 100644
> >> --- a/drivers/gpu/drm/drm_fourcc.c
> >> +++ b/drivers/gpu/drm/drm_fourcc.c
> >> @@ -229,17 +229,17 @@ const struct drm_format_info *__drm_format_info(u32
> >> format)
> >>{ .format = DRM_FORMAT_UYVY,.depth = 0,
> >> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_VYUY,.depth = 0,
> >> .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_XYUV,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >> - { .format = DRM_FORMAT_Y210,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_VUY888, .depth = 0,
> >> .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >> - { .format = DRM_FORMAT_Y410,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
> >>{ .format = DRM_FORMAT_AYUV,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
> >> - { .format = DRM_FORMAT_XVYU2101010, .depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_Y210,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_Y212,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >>{ .format = DRM_FORMAT_Y216,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true
> >> },
> >> - { .format = DRM_FORMAT_Y410,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >> - { .format = DRM_FORMAT_Y412,.depth = 0,
> >> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >> - { .format = DRM_FORMAT_Y416,.depth = 0,
> >> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true
> >> },
> >> + { .format = DRM_FORMAT_Y410,.depth = 0,
> >> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
> >> + { .format = DRM_FORMAT_Y412,.depth = 0,
> >> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
> >> + { .format = DRM_FORMAT_Y416,.depth = 0,
> >> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha =
> >> true, .is_yuv = true },
>
