Re: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
Quoting Dale B Stimson (2019-03-01 00:36:10)
> On Sat, Feb 23, 2019 at 09:45:10AM +, Chris Wilson wrote:
> > Verify that our list of nonpriv registers exist and are writable.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Dale B Stimson
> > Cc: Tvrtko Ursulin
> > Cc: Joonas Lahtinen
> > ---
> > tests/i915/gem_ctx_isolation.c | 164 +++--
> > 1 file changed, 135 insertions(+), 29 deletions(-)
> >
> > diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> > index 839d49ad..991a997f 100644
> > --- a/tests/i915/gem_ctx_isolation.c
> > +++ b/tests/i915/gem_ctx_isolation.c
> > @@ -59,16 +59,23 @@ enum {
> >
> > static const struct named_register {
> > const char *name;
> > - unsigned int gen_mask;
> > - unsigned int engine_mask;
> > - uint32_t offset;
> > + unsigned int gen_mask; /* on which gen the register exists */
> > + unsigned int engine_mask; /* preferred engine / powerwell */
> > + uint32_t offset; /* address of register, from bottom of mmio bar */
> > uint32_t count;
> > uint32_t ignore_bits;
> > + uint32_t write_mask; /* some registers bits do not exist */
> > bool masked;
> > } nonpriv_registers[] = {
> > { "NOPID", NOCTX, RCS0, 0x2094 },
> > { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> > - { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
> > + {
> > + "INSTPM",
> > + GEN6, RCS0, 0x20c0,
> > + .ignore_bits = BIT(8) /* ro counter */,
> > + .write_mask = BIT(8) /* rsvd varies between gen */,
> > + .masked = true,
> > + },
> > { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
> > { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
> > { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
> > @@ -78,7 +85,7 @@ static const struct named_register {
> > { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
> > { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
> > { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
> > - { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
> > + { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3
> > },
>
> I can't find a reason for adding ".write_mask = ~0x3".
Observed behaviour on byt.
> > { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> > - { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> > - { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> > - { "GT_MODE", GEN8, RCS0, 0x7008 },
> > - { "L3_Config", GEN7, RCS0, 0x7034 },
> > - { "TD_CTL", GEN8, RCS0, 0xe400 },
> > + { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
> > + { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
> > + { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
> > + { "L3_Config", GEN8, RCS0, 0x7034 },
> > + { "TD_CTL", GEN8, RCS0, 0xe400, .masked = true },
>
> It looks to me like TD_CTL should not be ".masked = true", as docs state
> "reserved" and "31:16 MBZ".
Ah, side-effect of not using asymmetric 31-16, 15-0.
Looks like it should be .write_mask=0x instead.
-Chris
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[Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Sanitycheck nonpriv access
Verify that our list of nonpriv registers exist and are writable.
v2: TD_CTL has a write_mask of 0x instead of being a masked
register.
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
---
tests/i915/gem_ctx_isolation.c | 167 +++--
1 file changed, 138 insertions(+), 29 deletions(-)
diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index 839d49ade..e50cc9a72 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -59,16 +59,23 @@ enum {
static const struct named_register {
const char *name;
- unsigned int gen_mask;
- unsigned int engine_mask;
- uint32_t offset;
+ unsigned int gen_mask; /* on which gen the register exists */
+ unsigned int engine_mask; /* preferred engine / powerwell */
+ uint32_t offset; /* address of register, from bottom of mmio bar */
uint32_t count;
uint32_t ignore_bits;
+ uint32_t write_mask; /* some registers bits do not exist */
bool masked;
} nonpriv_registers[] = {
{ "NOPID", NOCTX, RCS0, 0x2094 },
{ "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
- { "INSTPM", GEN6, RCS0, 0x20c0, 1, BIT(8) /* ro counter */, true },
+ {
+ "INSTPM",
+ GEN6, RCS0, 0x20c0,
+ .ignore_bits = BIT(8) /* ro counter */,
+ .write_mask = BIT(8) /* rsvd varies between gen */,
+ .masked = true,
+ },
{ "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
{ "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
{ "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
@@ -78,7 +85,7 @@ static const struct named_register {
{ "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
{ "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
{ "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
- { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
{ "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
{ "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
@@ -86,7 +93,7 @@ static const struct named_register {
{ "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
{ "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
{ "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
- { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418, .write_mask = 0x1 },
{ "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
{ "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
{ "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
@@ -94,45 +101,45 @@ static const struct named_register {
{ "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
{ "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
- { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x4 },
{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
{ "OACTXID", GEN8, RCS0, 0x2364 },
- { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
- { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
- { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
- { "GT_MODE", GEN8, RCS0, 0x7008 },
- { "L3_Config", GEN7, RCS0, 0x7034 },
- { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
+ { "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
+ { "L3_Config", GEN8, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400, .write_mask = 0x },
{ "TD_CTL2", GEN8, RCS0, 0xe404 },
- { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
- { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
- { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
- { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_NUM_PRIMS_WRITTEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITTEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITTEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITTEN3", GEN6, RCS0, 0x5218, 2 },
{ "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
{ "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
{ "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
{ "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
- { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
- { "SO_WRITE_OFFSET1", GEN7,
[Intel-gfx] [PATCH 2/6] drm/i915: Preparations for enabling P010, P012, P016 formats
From: Juha-Pekka Heikkila
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Signed-off-by: Swati Sharma
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 27 +--
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 14 +++---
drivers/gpu/drm/i915/intel_sprite.c | 22 +++---
5 files changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7961cf0..9d32a6f 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -136,7 +136,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->active_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
- new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)
+ is_planar_yuv_format(new_plane_state->base.fb->format->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7c5e84e..61ad775 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2681,6 +2681,12 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3179,7 +3185,7 @@ int skl_check_plane_surface(struct intel_plane_state
*plane_state)
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
@@ -3604,6 +3610,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -5027,9 +5039,9 @@ u16 skl_scaler_calc_phase(int sub, int scale, bool
chroma_cosited)
return 0;
}
- if (format && format->format == DRM_FORMAT_NV12 &&
+ if (format && is_planar_yuv_format(format->format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
- DRM_DEBUG_KMS("NV12: src dimensions not met\n");
+ DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
return -EINVAL;
}
@@ -5103,7 +5115,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
if (!icl_is_hdr_plane(intel_plane) &&
- fb && fb->format->format == DRM_FORMAT_NV12)
+ fb && is_planar_yuv_format(fb->format->format))
need_scaler = true;
ret = skl_update_scaler(crtc_state, force_detach,
@@ -5140,6 +5152,9 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
@@ -11191,7 +11206,7 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
}
if (!linked_state) {
- DRM_DEBUG_KMS("Need %d free Y planes for NV12\n",
+ DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n",
hweight8(crtc_state->nv12_planes));
return -EINVAL;
@@ -13909,7 +13924,7 @@ static void fb_obj_bump_render_priority(struct
drm_i915_gem_object *obj)
*or
*cdclk/crtc_clock
*/
- mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ mult = is_plana
[Intel-gfx] [PATCH 1/6] drm/i915: Add P010, P012, P016 plane control definitions
From: Juha-Pekka Heikkila
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila
Signed-off-by: Swati Sharma
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b482b..ce4ad20 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6602,8 +6602,11 @@ enum {
#define PLANE_CTL_FORMAT_YUV422 (0 << 24)
#define PLANE_CTL_FORMAT_NV12(1 << 24)
#define PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
+#define PLANE_CTL_FORMAT_P010(3 << 24)
#define PLANE_CTL_FORMAT_XRGB_ (4 << 24)
+#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
+#define PLANE_CTL_FORMAT_P016(7 << 24)
#define PLANE_CTL_FORMAT_AYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
--
1.9.1
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[Intel-gfx] [PATCH 4/6] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
From: Swati Sharma
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: For each component, valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: For each component valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.
Y410: Each color component occupies 10 bits and X component
takes 2 bits, thus each pixel occupies 32 bits.
Y412: Each color component is 16 bits where valid data
occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
Thus, each pixel occupies 64 bits.
Y416: Each color component occupies 16 bits for valid data,
doesn't require any padding bits. Thus, each pixel
occupies 64 bits.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
Reviewed-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 18 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index ba7e19d..45c9882 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y0L0,.depth = 0,
.num_planes = 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index bab2029..6e20ced 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
#define DRM_FORMAT_VYUYfourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /* [31:0]
X:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian per 2 Y pixels */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0]
X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0]
X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
+#
[Intel-gfx] [PATCH 0/6] Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats
From: Swati Sharma This patch series is for enabling P0xx, Y2xx and Y4xx pixel formats for intel's i915 driver. In this patch series, Juha Pekka's patch series Gen10+ P0xx formats https://patchwork.freedesktop.org/series/56053/ is combined with Swati's https://patchwork.freedesktop.org/series/55035/ for Gen11+ pixel formats (Y2xx and Y4xx). P0xx pixel formats are enabled from GLK whereas Y2xx and Y4xx are enabled from ICL platform. These patches enable planar formats YUV420-P010, P012 and P016 (Intial 3 patches of Juha) for GLK+ platform and packed format YUV422-Y210, Y212 and Y216 and YUV444-Y410, Y412, Y416 for 10, 12 and 16 bits for ICL+ platforms. IGT validating all these pixel formats is written by Maarten Lankhorst https://patchwork.freedesktop.org/patch/284508/ IGT needs libraries for pixman and cairo to support more than 8bpc. Need cairo >= 1.17.2 and pixman-1 >= 0.36.0. Tested with custom cairo and pixman. P0xx and Y2xx successfully validated for HDR planes, SDR planes having CRC mismatch (known bug for all YUV formats). Juha-Pekka Heikkila (3): drm/i915: Add P010, P012, P016 plane control definitions drm/i915: Preparations for enabling P010, P012, P016 formats drm/i915: Enable P010, P012, P016 formats for primary and sprite planes Swati Sharma (3): drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes drivers/gpu/drm/drm_fourcc.c | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 9 +++ drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 57 ++-- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 14 ++-- drivers/gpu/drm/i915/intel_sprite.c | 108 -- include/uapi/drm/drm_fourcc.h | 18 - 8 files changed, 195 insertions(+), 20 deletions(-) -- 1.9.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Enable P010, P012, P016 formats for primary and sprite planes
From: Juha-Pekka Heikkila
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila
Signed-off-by: Swati Sharma
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_sprite.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 1be7d59..0db3c5d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1832,6 +1832,25 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_NV12,
};
+static const uint32_t glk_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -2114,8 +2133,13 @@ struct intel_plane *
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
- formats = skl_planar_formats;
- num_formats = ARRAY_SIZE(skl_planar_formats);
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ formats = glk_planar_formats;
+ num_formats = ARRAY_SIZE(glk_planar_formats);
+ } else {
+ formats = skl_planar_formats;
+ num_formats = ARRAY_SIZE(skl_planar_formats);
+ }
} else {
formats = skl_plane_formats;
num_formats = ARRAY_SIZE(skl_plane_formats);
--
1.9.1
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[Intel-gfx] [PATCH 6/6] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes
From: Swati Sharma
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 30 ++
drivers/gpu/drm/i915/intel_sprite.c | 60 +++-
2 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61ad775..6825267 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2687,6 +2687,18 @@ int skl_format_to_fourcc(int format, bool rgb_order,
bool alpha)
return DRM_FORMAT_P012;
case PLANE_CTL_FORMAT_P016:
return DRM_FORMAT_P016;
+ case PLANE_CTL_FORMAT_Y210:
+ return DRM_FORMAT_Y210;
+ case PLANE_CTL_FORMAT_Y212:
+ return DRM_FORMAT_Y212;
+ case PLANE_CTL_FORMAT_Y216:
+ return DRM_FORMAT_Y216;
+ case PLANE_CTL_FORMAT_Y410:
+ return DRM_FORMAT_Y410;
+ case PLANE_CTL_FORMAT_Y412:
+ return DRM_FORMAT_Y412;
+ case PLANE_CTL_FORMAT_Y416:
+ return DRM_FORMAT_Y416;
default:
case PLANE_CTL_FORMAT_XRGB_:
if (rgb_order) {
@@ -3616,6 +3628,18 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
return PLANE_CTL_FORMAT_P012;
case DRM_FORMAT_P016:
return PLANE_CTL_FORMAT_P016;
+ case DRM_FORMAT_Y210:
+ return PLANE_CTL_FORMAT_Y210;
+ case DRM_FORMAT_Y212:
+ return PLANE_CTL_FORMAT_Y212;
+ case DRM_FORMAT_Y216:
+ return PLANE_CTL_FORMAT_Y216;
+ case DRM_FORMAT_Y410:
+ return PLANE_CTL_FORMAT_Y410;
+ case DRM_FORMAT_Y412:
+ return PLANE_CTL_FORMAT_Y412;
+ case DRM_FORMAT_Y416:
+ return PLANE_CTL_FORMAT_Y416;
default:
MISSING_CASE(pixel_format);
}
@@ -5155,6 +5179,12 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ case DRM_FORMAT_Y410:
+ case DRM_FORMAT_Y412:
+ case DRM_FORMAT_Y416:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 0db3c5d..89d7bf7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1816,6 +1816,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_VYUY,
};
+static const uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const u32 skl_planar_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -1851,6 +1872,31 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device
*dev, void *data,
DRM_FORMAT_P016,
};
+static const uint32_t icl_planar_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+ DRM_FORMAT_Y410,
+ DRM_FORMAT_Y412,
+ DRM_FORMAT_Y416,
+};
+
static const u64 skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1993,6 +2039,12 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
+ case DRM_FORMAT_Y410:
+ case DRM_FORMAT_Y412:
+ case DRM_FORMAT_Y416:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -2133,13 +2185,19 @@ struct intel_plane *
plane->update_slave = icl_update_slave;
if (skl_plane_has_planar(dev_priv, pi
[Intel-gfx] [PATCH 5/6] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions
From: Swati Sharma
Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
16 bits)
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ce4ad20..54bba61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6612,6 +6612,12 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210 (1 << 23)
+#define PLANE_CTL_FORMAT_Y212 (3 << 23)
+#define PLANE_CTL_FORMAT_Y216 (5 << 23)
+#define PLANE_CTL_FORMAT_Y410 (7 << 23)
+#define PLANE_CTL_FORMAT_Y412 (9 << 23)
+#define PLANE_CTL_FORMAT_Y416 (0xb << 23)
#define PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
--
1.9.1
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3)
== Series Details ==
Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3)
URL : https://patchwork.freedesktop.org/series/56606/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5ce21c7dd534 drm/i915: Add P010, P012, P016 plane control definitions
9096b3421086 drm/i915: Preparations for enabling P010, P012, P016 formats
e5606e0fb29e drm/i915: Enable P010, P012, P016 formats for primary and sprite
planes
-:22: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#22: FILE: drivers/gpu/drm/i915/intel_sprite.c:1835:
+static const uint32_t glk_planar_formats[] = {
total: 0 errors, 0 warnings, 1 checks, 40 lines checked
291c4cd3bc3a drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
-:48: WARNING:LONG_LINE: line over 100 characters
#48: FILE: drivers/gpu/drm/drm_fourcc.c:229:
+ { .format = DRM_FORMAT_Y210,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
-:49: WARNING:LONG_LINE: line over 100 characters
#49: FILE: drivers/gpu/drm/drm_fourcc.c:230:
+ { .format = DRM_FORMAT_Y212,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/gpu/drm/drm_fourcc.c:231:
+ { .format = DRM_FORMAT_Y216,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/drm_fourcc.c:232:
+ { .format = DRM_FORMAT_Y410,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:52: WARNING:LONG_LINE: line over 100 characters
#52: FILE: drivers/gpu/drm/drm_fourcc.c:233:
+ { .format = DRM_FORMAT_Y412,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:53: WARNING:LONG_LINE: line over 100 characters
#53: FILE: drivers/gpu/drm/drm_fourcc.c:234:
+ { .format = DRM_FORMAT_Y416,.depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
-:66: WARNING:LONG_LINE_COMMENT: line over 100 characters
#66: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_XYUVfourcc_code('X', 'Y', 'U', 'V') /* [31:0]
X:Y:Cb:Cr 8:8:8:8 little endian */
-:72: WARNING:LONG_LINE_COMMENT: line over 100 characters
#72: FILE: include/uapi/drm/drm_fourcc.h:160:
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
-:73: WARNING:LONG_LINE_COMMENT: line over 100 characters
#73: FILE: include/uapi/drm/drm_fourcc.h:161:
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0]
Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
-:74: WARNING:LONG_LINE_COMMENT: line over 100 characters
#74: FILE: include/uapi/drm/drm_fourcc.h:162:
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0]
Y0:Cb0:Y1:Cr1 16:16:16:16 little endian per 2 Y pixels */
-:80: WARNING:LONG_LINE_COMMENT: line over 100 characters
#80: FILE: include/uapi/drm/drm_fourcc.h:168:
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0]
X:V:Y:U 2:10:10:10 little endian */
-:81: WARNING:LONG_LINE_COMMENT: line over 100 characters
#81: FILE: include/uapi/drm/drm_fourcc.h:169:
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0]
X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
-:82: WARNING:LONG_LINE_COMMENT: line over 100 characters
#82: FILE: include/uapi/drm/drm_fourcc.h:170:
+#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0]
X:V:Y:U 16:16:16:16 little endian */
total: 0 errors, 13 warnings, 0 checks, 36 lines checked
07e294567498 drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control
definitions
4d716705c852 drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for
universal planes
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:75: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#75: FILE: drivers/gpu/drm/i915/intel_sprite.c:1819:
+static const uint32_t icl_plane_formats[] = {
-:103: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#103: FILE: drivers/gpu/drm/i915/intel_sprite.c:1875:
+static const uint32_t icl_planar_formats[] = {
total: 0 errors, 1 warnings, 2 checks, 138 lines checked
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3)
== Series Details == Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3) URL : https://patchwork.freedesktop.org/series/56606/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Add P010, P012, P016 plane control definitions Okay! Commit: drm/i915: Preparations for enabling P010, P012, P016 formats -O:drivers/gpu/drm/i915/intel_display.c:13915:21: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_display.c:13915:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13930:21: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_display.c:13930:21: warning: expression using sizeof(void) Commit: drm/i915: Enable P010, P012, P016 formats for primary and sprite planes Okay! Commit: drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc Okay! Commit: drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions Okay! Commit: drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 4/6] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
On 15-Feb-19 2:12 AM, Juha-Pekka Heikkilä wrote:
Swati Sharma kirjoitti 13.2.2019 klo 15.25:
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: For each component, valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: For each component valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.
Y410: Each color component occupies 10 bits and X component
takes 2 bits, thus each pixel occupies 32 bits.
Y412: Each color component is 16 bits where valid data
occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
Thus, each pixel occupies 64 bits.
Y416: Each color component occupies 16 bits for valid data,
doesn't require any padding bits. Thus, each pixel
occupies 64 bits.
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/drm_fourcc.c | 6 ++
include/uapi/drm/drm_fourcc.h | 18 +-
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index ba7e19d..45c9882 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info
*__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
= 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV, .depth = 0, .num_planes
= 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
= 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
.is_yuv = true },
+ { .format = DRM_FORMAT_Y210, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y212, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y216, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y410, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y412, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
+ { .format = DRM_FORMAT_Y416, .depth = 0,
.num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv =
true },
{ .format = DRM_FORMAT_Y0L0, .depth = 0, .num_planes
= 1,
.char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 },
.block_h = { 2, 0, 0 },
.hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h
b/include/uapi/drm/drm_fourcc.h
index bab2029..6e20ced 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V')
/* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV fourcc_code('X', 'Y', 'U', 'V') /*
[31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
^^
one tab removed?
Don't y showing like this :/
With that fixed this is
Reviewed-by: Juha-Pekka Heikkila
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /*
[63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian per 2
Y pixels */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /*
[63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian per 2
Y pixels */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /*
[63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian per 2 Y pixels */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /*
[31:0] X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /*
[63:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:
[Intel-gfx] [PATCH v2] drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot
write to, so check the register exists before merging such patches.
v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Michał Winiarski
---
.../drm/i915/selftests/intel_workarounds.c| 376 ++
1 file changed, 376 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index e6ffc8ac22dc..daceb605ddd1 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -12,6 +12,14 @@
#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
+#include "mock_drm.h"
+
+static const struct wo_register {
+ enum intel_platform platform;
+ u32 reg;
+} wo_registers[] = {
+ { INTEL_GEMINILAKE, 0x731c }
+};
#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
struct wa_lists {
@@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
return err;
}
+static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void *ptr;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+
+ ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err_obj;
+ }
+ memset(ptr, 0xc5, PAGE_SIZE);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static struct i915_vma *create_batch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static u32 reg_write(u32 old, u32 new, u32 rsvd)
+{
+ if (rsvd == 0x) {
+ old &= ~(new >> 16);
+ old |= new & (new >> 16);
+ } else {
+ old &= ~rsvd;
+ old |= new & rsvd;
+ }
+
+ return old;
+}
+
+static bool wo_register(struct intel_engine_cs *engine, u32 reg)
+{
+ enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
+ if (wo_registers[i].platform == platform &&
+ wo_registers[i].reg == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static int check_dirty_whitelist(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine)
+{
+ const u32 values[] = {
+ 0x,
+ 0x01010101,
+ 0x10100101,
+ 0x03030303,
+ 0x30300303,
+ 0x05050505,
+ 0x50500505,
+ 0x0f0f0f0f,
+ 0xf00ff00f,
+ 0x10101010,
+ 0xf0f01010,
+ 0x30303030,
+ 0xa0a03030,
+ 0x50505050,
+ 0xc0c05050,
+ 0xf0f0f0f0,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x00ff00ff,
+ 0xffff,
+ 0x00ff,
+ 0x,
+ };
+ struct i915_vma *scratch;
+ struct i915_vma *batch;
+ int err = 0, i, v;
+ u32 *cs;
+
+ scratch = create_scratch(ctx);
+ if (IS_ERR(scratch))
+ return PTR_ERR(scratch);
+
+ batch = create_batch(ctx);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_scratch;
+ }
+
+ for (i = 0; i < engine->whitelist.count; i++) {
+ u32 reg = i915_mmio_reg_offset(eng
[Intel-gfx] [PATCH v3] drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot
write to, so check the register exists before merging such patches.
v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only
Signed-off-by: Chris Wilson
Cc: Dale B Stimson
Cc: Michał Winiarski
---
.../drm/i915/selftests/intel_workarounds.c| 376 ++
1 file changed, 376 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index e6ffc8ac22dc..33b3ced83fde 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -12,6 +12,14 @@
#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
+#include "mock_drm.h"
+
+static const struct wo_register {
+ enum intel_platform platform;
+ u32 reg;
+} wo_registers[] = {
+ { INTEL_GEMINILAKE, 0x731c }
+};
#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
struct wa_lists {
@@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
return err;
}
+static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void *ptr;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+
+ ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(ptr)) {
+ err = PTR_ERR(ptr);
+ goto err_obj;
+ }
+ memset(ptr, 0xc5, PAGE_SIZE);
+ i915_gem_object_unpin_map(obj);
+
+ vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_cpu_domain(obj, false);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static struct i915_vma *create_batch(struct i915_gem_context *ctx)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_obj;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ goto err_obj;
+
+ err = i915_gem_object_set_to_wc_domain(obj, true);
+ if (err)
+ goto err_obj;
+
+ return vma;
+
+err_obj:
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+}
+
+static u32 reg_write(u32 old, u32 new, u32 rsvd)
+{
+ if (rsvd == 0x) {
+ old &= ~(new >> 16);
+ old |= new & (new >> 16);
+ } else {
+ old &= ~rsvd;
+ old |= new & rsvd;
+ }
+
+ return old;
+}
+
+static bool wo_register(struct intel_engine_cs *engine, u32 reg)
+{
+ enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
+ if (wo_registers[i].platform == platform &&
+ wo_registers[i].reg == reg)
+ return true;
+ }
+
+ return false;
+}
+
+static int check_dirty_whitelist(struct i915_gem_context *ctx,
+struct intel_engine_cs *engine)
+{
+ const u32 values[] = {
+ 0x,
+ 0x01010101,
+ 0x10100101,
+ 0x03030303,
+ 0x30300303,
+ 0x05050505,
+ 0x50500505,
+ 0x0f0f0f0f,
+ 0xf00ff00f,
+ 0x10101010,
+ 0xf0f01010,
+ 0x30303030,
+ 0xa0a03030,
+ 0x50505050,
+ 0xc0c05050,
+ 0xf0f0f0f0,
+ 0x,
+ 0x,
+ 0x,
+ 0x,
+ 0x00ff00ff,
+ 0xffff,
+ 0x00ff,
+ 0x,
+ };
+ struct i915_vma *scratch;
+ struct i915_vma *batch;
+ int err = 0, i, v;
+ u32 *cs;
+
+ scratch = create_scratch(ctx);
+ if (IS_ERR(scratch))
+ return PTR_ERR(scratch);
+
+ batch = create_batch(ctx);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_scratch;
+ }
+
+ for (i = 0; i < engine->whitelist.count; i++) {
+ u32 reg = i915_mmio_reg_offset(eng
[Intel-gfx] ✓ Fi.CI.BAT: success for Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3)
== Series Details == Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3) URL : https://patchwork.freedesktop.org/series/56606/ State : success == Summary == CI Bug Log - changes from CI_DRM_5675 -> Patchwork_12336 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/56606/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_12336 that come from known issues: ### IGT changes ### Issues hit * igt@i915_pm_rpm@module-reload: - fi-skl-6770hq: PASS -> FAIL [fdo#108511] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: SKIP [fdo#109271] -> PASS * igt@i915_pm_rpm@basic-rte: - fi-bsw-kefka: FAIL [fdo#108800] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (42 -> 38) -- Missing(4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u Build changes - * Linux: CI_DRM_5675 -> Patchwork_12336 CI_DRM_5675: 204c772a8bb7898bcc4e80f329f5334ff88aeba8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4864: 6be2dc8ddfa332d129149aa3b13db14fa2cd6c0a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12336: 4d716705c8527ae1480377658820b0bbf4d0bdf4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4d716705c852 drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes 07e294567498 drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions 291c4cd3bc3a drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc e5606e0fb29e drm/i915: Enable P010, P012, P016 formats for primary and sprite planes 9096b3421086 drm/i915: Preparations for enabling P010, P012, P016 formats 5ce21c7dd534 drm/i915: Add P010, P012, P016 plane control definitions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12336/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 0/4] drm & vgaarb: handle vgacon removal in vgaarb.
v7: - codestype fixes. - new patch, switching i915 to use drm_fb_helper_remove_conflicting_pci_framebuffers v6: buildfix. Gerd Hoffmann (4): drm: move i915_kick_out_vgacon to vgaarb drm/fb-helper: call vga_remove_vgacon automatically. drm/qxl: remove conflicting framebuffers earlier drm/i915: switch to drm_fb_helper_remove_conflicting_pci_framebuffers include/drm/drm_fb_helper.h | 14 ++-- include/linux/vgaarb.h | 2 ++ drivers/gpu/drm/i915/i915_drv.c | 71 ++--- drivers/gpu/drm/qxl/qxl_drv.c | 5 ++- drivers/gpu/vga/vgaarb.c| 49 5 files changed, 68 insertions(+), 73 deletions(-) -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 1/4] drm: move i915_kick_out_vgacon to vgaarb
Also rename it to vga_remove_vgacon and add kerneldoc text.
Signed-off-by: Gerd Hoffmann
Reviewed-by: Daniel Vetter
---
include/linux/vgaarb.h | 2 ++
drivers/gpu/drm/i915/i915_drv.c | 35 +
drivers/gpu/vga/vgaarb.c| 49 +
3 files changed, 52 insertions(+), 34 deletions(-)
diff --git a/include/linux/vgaarb.h b/include/linux/vgaarb.h
index ee162e3e879b..553b34c8b5f7 100644
--- a/include/linux/vgaarb.h
+++ b/include/linux/vgaarb.h
@@ -125,9 +125,11 @@ extern void vga_put(struct pci_dev *pdev, unsigned int
rsrc);
#ifdef CONFIG_VGA_ARB
extern struct pci_dev *vga_default_device(void);
extern void vga_set_default_device(struct pci_dev *pdev);
+extern int vga_remove_vgacon(struct pci_dev *pdev);
#else
static inline struct pci_dev *vga_default_device(void) { return NULL; };
static inline void vga_set_default_device(struct pci_dev *pdev) { };
+static inline int vga_remove_vgacon(struct pci_dev *pdev) { return 0; };
#endif
/*
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6630212f2faf..9df65d386d11 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -757,39 +757,6 @@ static int i915_kick_out_firmware_fb(struct
drm_i915_private *dev_priv)
return ret;
}
-#if !defined(CONFIG_VGA_CONSOLE)
-static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
-{
- return 0;
-}
-#elif !defined(CONFIG_DUMMY_CONSOLE)
-static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
-{
- return -ENODEV;
-}
-#else
-static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
-{
- int ret = 0;
-
- DRM_INFO("Replacing VGA console driver\n");
-
- console_lock();
- if (con_is_bound(&vga_con))
- ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1,
1);
- if (ret == 0) {
- ret = do_unregister_con_driver(&vga_con);
-
- /* Ignore "already unregistered". */
- if (ret == -ENODEV)
- ret = 0;
- }
- console_unlock();
-
- return ret;
-}
-#endif
-
static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
/*
@@ -1420,7 +1387,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
goto err_ggtt;
}
- ret = i915_kick_out_vgacon(dev_priv);
+ ret = vga_remove_vgacon(pdev);
if (ret) {
DRM_ERROR("failed to remove conflicting VGA console\n");
goto err_ggtt;
diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c
index dc8e039bfab5..f2f3ef8af271 100644
--- a/drivers/gpu/vga/vgaarb.c
+++ b/drivers/gpu/vga/vgaarb.c
@@ -48,6 +48,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -168,6 +170,53 @@ void vga_set_default_device(struct pci_dev *pdev)
vga_default = pci_dev_get(pdev);
}
+/**
+ * vga_remove_vgacon - deactivete vga console
+ *
+ * Unbind and unregister vgacon in case pdev is the default vga
+ * device. Can be called by gpu drivers on initialization to make
+ * sure vga register access done by vgacon will not disturb the
+ * device.
+ *
+ * @pdev: pci device.
+ */
+#if !defined(CONFIG_VGA_CONSOLE)
+int vga_remove_vgacon(struct pci_dev *pdev)
+{
+ return 0;
+}
+#elif !defined(CONFIG_DUMMY_CONSOLE)
+int vga_remove_vgacon(struct pci_dev *pdev)
+{
+ return -ENODEV;
+}
+#else
+int vga_remove_vgacon(struct pci_dev *pdev)
+{
+ int ret = 0;
+
+ if (pdev != vga_default)
+ return 0;
+ vgaarb_info(&pdev->dev, "deactivate vga console\n");
+
+ console_lock();
+ if (con_is_bound(&vga_con))
+ ret = do_take_over_console(&dummy_con, 0,
+ MAX_NR_CONSOLES - 1, 1);
+ if (ret == 0) {
+ ret = do_unregister_con_driver(&vga_con);
+
+ /* Ignore "already unregistered". */
+ if (ret == -ENODEV)
+ ret = 0;
+ }
+ console_unlock();
+
+ return ret;
+}
+#endif
+EXPORT_SYMBOL(vga_remove_vgacon);
+
static inline void vga_irq_set_state(struct vga_device *vgadev, bool state)
{
if (vgadev->irq_set_state)
--
2.9.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v7 2/4] drm/fb-helper: call vga_remove_vgacon automatically.
Add vga_remove_vgacon() call to
drm_fb_helper_remove_conflicting_pci_framebuffers().
Signed-off-by: Gerd Hoffmann
Reviewed-by: Daniel Vetter
---
include/drm/drm_fb_helper.h | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index bb9acea61369..286d58efed5d 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -36,6 +36,7 @@ struct drm_fb_helper;
#include
#include
#include
+#include
enum mode_set_atomic {
LEAVE_ATOMIC_MODE_SET,
@@ -642,11 +643,18 @@ drm_fb_helper_remove_conflicting_pci_framebuffers(struct
pci_dev *pdev,
int resource_id,
const char *name)
{
+ int ret = 0;
+
+ /*
+* WARNING: Apparently we must kick fbdev drivers before vgacon,
+* otherwise the vga fbdev driver falls over.
+*/
#if IS_REACHABLE(CONFIG_FB)
- return remove_conflicting_pci_framebuffers(pdev, resource_id, name);
-#else
- return 0;
+ ret = remove_conflicting_pci_framebuffers(pdev, resource_id, name);
#endif
+ if (ret == 0)
+ ret = vga_remove_vgacon(pdev);
+ return ret;
}
#endif
--
2.9.3
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[Intel-gfx] [PATCH v7 4/4] drm/i915: switch to drm_fb_helper_remove_conflicting_pci_framebuffers
Signed-off-by: Gerd Hoffmann
---
drivers/gpu/drm/i915/i915_drv.c | 38 ++
1 file changed, 2 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9df65d386d11..c6f1e0dbdd58 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -732,31 +732,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
return ret;
}
-static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
-{
- struct apertures_struct *ap;
- struct pci_dev *pdev = dev_priv->drm.pdev;
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
- bool primary;
- int ret;
-
- ap = alloc_apertures(1);
- if (!ap)
- return -ENOMEM;
-
- ap->ranges[0].base = ggtt->gmadr.start;
- ap->ranges[0].size = ggtt->mappable_end;
-
- primary =
- pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
-
- ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb",
primary);
-
- kfree(ap);
-
- return ret;
-}
-
static void intel_init_dpio(struct drm_i915_private *dev_priv)
{
/*
@@ -1377,22 +1352,13 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
if (ret)
goto err_perf;
- /*
-* WARNING: Apparently we must kick fbdev drivers before vgacon,
-* otherwise the vga fbdev driver falls over.
-*/
- ret = i915_kick_out_firmware_fb(dev_priv);
+ ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 2,
+ "inteldrmfb");
if (ret) {
DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
goto err_ggtt;
}
- ret = vga_remove_vgacon(pdev);
- if (ret) {
- DRM_ERROR("failed to remove conflicting VGA console\n");
- goto err_ggtt;
- }
-
ret = i915_ggtt_init_hw(dev_priv);
if (ret)
goto err_ggtt;
--
2.9.3
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[Intel-gfx] [PATCH v7 3/4] drm/qxl: remove conflicting framebuffers earlier
Add error checking while being at it. Signed-off-by: Gerd Hoffmann Reviewed-by: Daniel Vetter --- drivers/gpu/drm/qxl/qxl_drv.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index bb81e310eb6d..578d867a81d5 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -79,6 +79,10 @@ qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret) goto free_dev; + ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "qxl"); + if (ret) + goto disable_pci; + ret = qxl_device_init(qdev, &qxl_driver, pdev); if (ret) goto disable_pci; @@ -94,7 +98,6 @@ qxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret) goto modeset_cleanup; - drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "qxl"); drm_fbdev_generic_setup(&qdev->ddev, 32); return 0; -- 2.9.3 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4 2/5] drm/i915: Watchdog timeout: IRQ handler for gen8+
Quoting Carlos Santa (2019-02-21 02:58:16)
> +#define GEN8_WATCHDOG_1000US(dev_priv) watchdog_to_clock_counts(dev_priv,
> 1000)
> +static void gen8_watchdog_irq_handler(unsigned long data)
> +{
> + struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
> + struct drm_i915_private *dev_priv = engine->i915;
> + unsigned int hung = 0;
> + u32 current_seqno=0;
> + char msg[80];
> + unsigned int tmp;
> + int len;
> +
> + /* Stop the counter to prevent further timeout interrupts */
> + I915_WRITE_FW(RING_CNTR(engine->mmio_base),
> get_watchdog_disable(engine));
> +
> + /* Read the heartbeat seqno once again to check if we are stuck? */
> + current_seqno = intel_engine_get_hangcheck_seqno(engine);
I have said this before, but this doesn't exist either, it's just a
temporary glitch in the matrix.
> +if (current_seqno == engine->current_seqno) {
> + hung |= engine->mask;
> +
> + len = scnprintf(msg, sizeof(msg), "%s on ", "watchdog
> timeout");
> + for_each_engine_masked(engine, dev_priv, hung, tmp)
> + len += scnprintf(msg + len, sizeof(msg) - len,
> +"%s, ", engine->name);
> + msg[len-2] = '\0';
> +
> + i915_handle_error(dev_priv, hung, 0, "%s", msg);
> +
> + /* Reset timer in case GPU hangs without another request
> being added */
> + i915_queue_hangcheck(dev_priv);
You still haven't explained why we are not just resetting the engine
immediately. Have you looked at the preempt-timeout patches that need to
do the same thing from timer-irq context?
Resending the same old stuff over and over again is just exasperating.
-Chris
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[Intel-gfx] [RFT i-g-t] lib/i915: Assert mmap size alignment
From: Tvrtko Ursulin
Fishing for fails...
/*
mmap(2) mandates size is page aligned so check this in our wrappers.
*/
Signed-off-by: Tvrtko Ursulin
---
lib/i915/gem_mman.c | 4
tests/kms_psr.c | 8
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 3cf9a6bbdb31..084dbb3b3678 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -57,6 +57,8 @@ void *__gem_mmap__gtt(int fd, uint32_t handle, uint64_t size,
unsigned prot)
struct drm_i915_gem_mmap_gtt mmap_arg;
void *ptr;
+ igt_assert(!(size & 4095));
+
memset(&mmap_arg, 0, sizeof(mmap_arg));
mmap_arg.handle = handle;
if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg))
@@ -162,6 +164,8 @@ static void
{
struct drm_i915_gem_mmap arg;
+ igt_assert(!(size & 4095));
+
memset(&arg, 0, sizeof(arg));
arg.handle = handle;
arg.offset = offset;
diff --git a/tests/kms_psr.c b/tests/kms_psr.c
index 3e16a6bf4f37..5d3f0ed87eec 100644
--- a/tests/kms_psr.c
+++ b/tests/kms_psr.c
@@ -270,8 +270,8 @@ static void run_test(data_t *data)
expected = "GREEN";
break;
case MMAP_GTT:
- ptr = gem_mmap__gtt(data->drm_fd, handle, data->mod_size,
- PROT_WRITE);
+ ptr = gem_mmap__gtt(data->drm_fd, handle,
+ ALIGN(data->mod_size, 4096), PROT_WRITE);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
memset(ptr, 0xcc, data->mod_size);
@@ -279,8 +279,8 @@ static void run_test(data_t *data)
expected = "BLACK or TRANSPARENT mark on top of plane in test";
break;
case MMAP_CPU:
- ptr = gem_mmap__cpu(data->drm_fd, handle, 0, data->mod_size,
- PROT_WRITE);
+ ptr = gem_mmap__cpu(data->drm_fd, handle, 0,
+ ALIGN(data->mod_size, 4096), PROT_WRITE);
gem_set_domain(data->drm_fd, handle,
I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
memset(ptr, 0, data->mod_size);
--
2.19.1
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Check that whitelisted registers are accessible (rev4)
== Series Details ==
Series: drm/i915/selftests: Check that whitelisted registers are accessible
(rev4)
URL : https://patchwork.freedesktop.org/series/57342/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5675 -> Patchwork_12337
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57342/revisions/4/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12337:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_objects:
- {fi-icl-y}: NOTRUN -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12337 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@readonly-bsd1:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_suspend@basic-s3:
- fi-ilk-650: PASS -> DMESG-WARN [fdo#106387]
- fi-byt-clapper: PASS -> INCOMPLETE [fdo#102657]
* igt@i915_selftest@live_contexts:
- fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569]
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@i915_selftest@live_evict:
- fi-bsw-kefka: PASS -> DMESG-WARN [fdo#107709]
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> WARN [fdo#109380]
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: NOTRUN -> FAIL [fdo#103167]
- fi-icl-u2: NOTRUN -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> FAIL [fdo#107709]
- fi-kbl-r: NOTRUN -> FAIL [fdo#108903] / [fdo#108904] /
[fdo#108905]
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#108903]: https://bugs.freedesktop.org/show_bug.cgi?id=108903
[fdo#108904]: https://bugs.freedesktop.org/show_bug.cgi?id=108904
[fdo#108905]: https://bugs.freedesktop.org/show_bug.cgi?id=108905
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109309]: https://bugs.free
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm & vgaarb: handle vgacon removal in vgaarb. (rev3)
== Series Details == Series: drm & vgaarb: handle vgacon removal in vgaarb. (rev3) URL : https://patchwork.freedesktop.org/series/57086/ State : warning == Summary == $ dim checkpatch origin/drm-tip e56773c102aa drm: move i915_kick_out_vgacon to vgaarb -:139: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #139: FILE: include/linux/vgaarb.h:128: +extern int vga_remove_vgacon(struct pci_dev *pdev); total: 0 errors, 0 warnings, 1 checks, 119 lines checked 88d013712162 drm/fb-helper: call vga_remove_vgacon automatically. 374ceab5203b drm/qxl: remove conflicting framebuffers earlier 336255cd1c41 drm/i915: switch to drm_fb_helper_remove_conflicting_pci_framebuffers -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 55 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm: move a detected edid member to drm_connector from intel_connector
In order to use a detected edid on drm helper functions, it moves
a detected edid member to drm_connector structure from intel_connector
structure.
v2: Rebased.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/intel_connector.c | 2 +-
drivers/gpu/drm/i915/intel_dp.c| 17 -
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_hdmi.c | 8
include/drm/drm_connector.h| 7 +++
5 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_connector.c
b/drivers/gpu/drm/i915/intel_connector.c
index 848dd9e728d8..175cdbcbdc4e 100644
--- a/drivers/gpu/drm/i915/intel_connector.c
+++ b/drivers/gpu/drm/i915/intel_connector.c
@@ -86,7 +86,7 @@ void intel_connector_destroy(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
- kfree(intel_connector->detect_edid);
+ kfree(intel_connector->base.detect_edid);
intel_hdcp_cleanup(intel_connector);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e1a051c0fbfe..bc493656e183 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4479,7 +4479,7 @@ static u8 intel_dp_autotest_edid(struct intel_dp
*intel_dp)
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct drm_connector *connector = &intel_connector->base;
- if (intel_connector->detect_edid == NULL ||
+ if (connector->detect_edid == NULL ||
connector->edid_corrupt ||
intel_dp->aux.i2c_defer_count > 6) {
/* Check EDID read for NACKs, DEFERs and corruption
@@ -4496,12 +4496,12 @@ static u8 intel_dp_autotest_edid(struct intel_dp
*intel_dp)
intel_dp->aux.i2c_defer_count);
intel_dp->compliance.test_data.edid =
INTEL_DP_RESOLUTION_FAILSAFE;
} else {
- struct edid *block = intel_connector->detect_edid;
+ struct edid *block = connector->detect_edid;
/* We have to write the checksum
* of the last block read
*/
- block += intel_connector->detect_edid->extensions;
+ block += connector->detect_edid->extensions;
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
block->checksum) <= 0)
@@ -5355,7 +5355,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
intel_dp_unset_edid(intel_dp);
edid = intel_dp_get_edid(intel_dp);
- intel_connector->detect_edid = edid;
+ intel_connector->base.detect_edid = edid;
intel_dp->has_audio = drm_detect_monitor_audio(edid);
drm_dp_cec_set_edid(&intel_dp->aux, edid);
@@ -5367,8 +5367,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
struct intel_connector *intel_connector = intel_dp->attached_connector;
drm_dp_cec_unset_edid(&intel_dp->aux);
- kfree(intel_connector->detect_edid);
- intel_connector->detect_edid = NULL;
+ kfree(intel_connector->base.detect_edid);
+ intel_connector->base.detect_edid = NULL;
intel_dp->has_audio = false;
}
@@ -5471,8 +5471,7 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp->aux.i2c_defer_count = 0;
intel_dp_set_edid(intel_dp);
- if (intel_dp_is_edp(intel_dp) ||
- to_intel_connector(connector)->detect_edid)
+ if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
status = connector_status_connected;
intel_dp_check_service_irq(intel_dp);
@@ -5515,7 +5514,7 @@ static int intel_dp_get_modes(struct drm_connector
*connector)
struct intel_connector *intel_connector = to_intel_connector(connector);
struct edid *edid;
- edid = intel_connector->detect_edid;
+ edid = connector->detect_edid;
if (edid) {
int ret = intel_connector_update_modes(connector, edid);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5412373e2f98..6f641980a877 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -503,7 +503,6 @@ struct intel_connector {
/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
struct edid *edid;
- struct edid *detect_edid;
/* since POLL and HPD connectors may use the same HPD line keep the
native
state of connector->polled in case hotplug storm detection changes
it */
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index cd422a7b4da0..82fd4b535c45 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2395,8 +2395,8 @@ intel_hdmi_unset_edid(struct drm_connector *connector)
intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE
[Intel-gfx] [PATCH 2/2] drm: Add detection of changing of edid on between suspend and resume
The hotplug detection routine of drm_helper_hpd_irq_event() can detect
changing of status of connector, but it can not detect changing of edid.
Following scenario requires detection of changing of edid.
1) plug display device to a connector
2) system suspend
3) unplug 1)'s display device and plug the other display device to a
connector
4) system resume
It adds edid check routine when a connector status still remains as
"connector_status_connected".
v2: Add NULL check before comparing of EDIDs.
v3: Make it as part of existing drm_helper_hpd_irq_event() (Stan, Mika)
Testcase: igt/kms_chamelium/hdmi-edid-change-during-hibernate
Testcase: igt/kms_chamelium/hdmi-edid-change-during-suspend
Testcase: igt/kms_chamelium/dp-edid-change-during-hibernate
Testcase: igt/kms_chamelium/dp-edid-change-during-suspend
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_probe_helper.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_probe_helper.c
b/drivers/gpu/drm/drm_probe_helper.c
index 6fd08e04b323..036a57d2b29e 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -742,7 +742,16 @@ EXPORT_SYMBOL(drm_kms_helper_poll_fini);
* panels.
*
* This helper function is useful for drivers which can't or don't track
hotplug
- * interrupts for each connector.
+ * interrupts for each connector. And it also supports a detection of changing
+ * of edid on between suspend and resume when a connector status still remains
+ * as "connector_status_connected".
+ *
+ * Following scenario requires detection of changing of edid.
+ * 1) plug display device to a connector
+ * 2) system suspend
+ * 3) unplug 1)'s display device and plug the other display device to a
+ connector
+ * 4) system resume
*
* Drivers which support hotplug interrupts for each connector individually and
* which have a more fine-grained detect logic should bypass this code and
@@ -760,6 +769,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
enum drm_connector_status old_status;
+ struct edid *old_edid;
bool changed = false;
if (!dev->mode_config.poll_enabled)
@@ -773,6 +783,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
continue;
old_status = connector->status;
+ old_edid = connector->detect_edid;
connector->status = drm_helper_probe_detect(connector, NULL,
false);
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to
%s\n",
@@ -782,6 +793,22 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev)
drm_get_connector_status_name(connector->status));
if (old_status != connector->status)
changed = true;
+
+ /* Check changing of edid when a connector status still remains
+* as "connector_status_connected".
+*/
+ if (old_status == connector->status &&
+ old_status == connector_status_connected) {
+ if (!old_edid || !connector->detect_edid)
+ continue;
+
+ if (memcmp(old_edid, connector->detect_edid,
sizeof(*old_edid))) {
+ changed = true;
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] edid
updated\n",
+ connector->base.id,
+ connector->name);
+ }
+ }
}
drm_connector_list_iter_end(&conn_iter);
mutex_unlock(&dev->mode_config.mutex);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm & vgaarb: handle vgacon removal in vgaarb. (rev3)
== Series Details ==
Series: drm & vgaarb: handle vgacon removal in vgaarb. (rev3)
URL : https://patchwork.freedesktop.org/series/57086/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5675 -> Patchwork_12338
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57086/revisions/3/mbox/
Known issues
Here are the changes found in Patchwork_12338 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@readonly-bsd1:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718]
* igt@gem_workarounds@basic-read:
- fi-snb-2600:NOTRUN -> SKIP [fdo#109271] +57
* igt@i915_selftest@live_contexts:
- fi-icl-u3: NOTRUN -> DMESG-FAIL [fdo#108569]
- fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] / [fdo#109278] +2
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_busy@basic-flip-c:
- fi-snb-2600:NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: NOTRUN -> FAIL [fdo#103167]
- fi-icl-u2: NOTRUN -> FAIL [fdo#103167]
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: FAIL [fdo#108800] -> PASS
* igt@i915_selftest@live_execlists:
- fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#109779]: https://bugs.freedesktop.org/show_bug.cgi?id=109779
Participating hosts (42 -> 41)
--
Additional (4): fi-icl-y fi-icl-u2 fi-icl-u3 fi-snb-2600
Missing(5): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan
Build changes
-
* Linux: CI_DRM_5675 -> Patchwork_12338
CI_DRM_5675: 204c772a8bb7898bcc4e80f329f5334ff88aeba8 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4864: 6be2dc8ddfa332d
Re: [Intel-gfx] [PATCH 10/11] drm/i915/execlists: Skip direct submission if only lite-restore
Quoting Tvrtko Ursulin (2019-02-28 13:20:50) > > On 26/02/2019 10:24, Chris Wilson wrote: > > If we resubmitting the active context, simply skip the submission as > > we are It took multiple reads to even notice that the third word was missing, mainly because I kept skipping the "we". > > performing the submission from the interrupt handler has higher > > From the tasklet? Yes, the interrupt handler bottom half. > You mean wait for ctx complete and then > execlists_dequeue, instead of lite-restore? Yes. We can measure the relatively large impact of lite-restoring on throughput (the delay in the GPU reloading the context is quite noticeable), but it only affects a certain microbenchmark. In theory, making sure we avoid the stall while handling the interrupt and resubmitting should offset that cost and be much preferred for multi-context situations, but there the interrupt overhead on an *idle* system (~5-7us) is not as significant and so the impact seems not as significant (in fact due to quirky hw, sometimes it is preferable not to resubmit during an inflight CS event). Anyway I just keep getting annoyed by the extra latency induced by lite-restore without a good way to balance it against avoiding the CS completion stall. And I live in fear of our tasklet being thrown to ksoftirqd again. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 10/11] drm/i915/execlists: Skip direct submission if only lite-restore
Quoting Chris Wilson (2019-03-01 10:22:30) > Quoting Tvrtko Ursulin (2019-02-28 13:20:50) > > > > On 26/02/2019 10:24, Chris Wilson wrote: > > > If we resubmitting the active context, simply skip the submission as > > > > we are > > It took multiple reads to even notice that the third word was missing, > mainly because I kept skipping the "we". > > > > performing the submission from the interrupt handler has higher > > > > From the tasklet? > > Yes, the interrupt handler bottom half. > > > You mean wait for ctx complete and then > > execlists_dequeue, instead of lite-restore? > > Yes. We can measure the relatively large impact of lite-restoring on > throughput (the delay in the GPU reloading the context is quite > noticeable), but it only affects a certain microbenchmark. In theory, > making sure we avoid the stall while handling the interrupt and > resubmitting should offset that cost and be much preferred for > multi-context situations, but there the interrupt overhead on an *idle* > system (~5-7us) is not as significant and so the impact seems not as > significant (in fact due to quirky hw, sometimes it is preferable not to > resubmit during an inflight CS event). On idle systems, that lite-restore cost is visible even on top of a normal context switch, i.e. submitting A, AB, [CS interrupt], B is marginally slower than A, [CS interrupt], B !!! /o\ Sometimes I don't get our HW at all, -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 2/2] automake: Make librt mandatory
From: Tvrtko Ursulin librt is required by libintel_tools so express it as mandatory in autoconf and also drop explicit mentions from Makefile.am. This also fixes a build warning of: tests/Makefile.am:134: warning: variable 'pm_rc6_residency_LDADD' is defined but no program or tests/Makefile.am:134: library has 'pm_rc6_residency' as canonical name (possible typo) Signed-off-by: Tvrtko Ursulin --- benchmarks/Makefile.am | 2 +- configure.ac | 4 ++-- tests/Makefile.am | 5 + 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am index c166d636d507..1f05adf31527 100644 --- a/benchmarks/Makefile.am +++ b/benchmarks/Makefile.am @@ -24,5 +24,5 @@ gem_exec_tracer_la_LIBADD = -ldl gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_latency_LDADD = $(LDADD) -lpthread gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) -gem_syslatency_LDADD = $(LDADD) -lpthread -lrt +gem_syslatency_LDADD = $(LDADD) -lpthread gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread diff --git a/configure.ac b/configure.ac index e22703d03198..a3f541a2f888 100644 --- a/configure.ac +++ b/configure.ac @@ -58,12 +58,12 @@ AX_GCC_FUNC_ATTRIBUTE([constructor]) dnl Check for POSIX timers AC_CHECK_FUNCS(timer_create, [], [ AC_CHECK_LIB(rt, timer_create, [ - AC_DEFINE(HAVE_TIMER_CREATE, 1) TIMER_LIBS="-lrt" ], [ AC_CHECK_LIB(pthread, timer_create, [ - AC_DEFINE(HAVE_TIMER_CREATE, 1) TIMER_LIBS="-lpthread" + ], [ + AC_MSG_ERROR([Failed to find library containing timer_create.]) ]) ]) ]) diff --git a/tests/Makefile.am b/tests/Makefile.am index c5dd210c7163..289249b42b97 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -128,10 +128,7 @@ gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_userptr_blits_LDADD = $(LDADD) -lpthread perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -gem_eio_LDADD = $(LDADD) -lrt -gem_wait_LDADD = $(LDADD) -lrt -kms_flip_LDADD = $(LDADD) -lrt -lpthread -pm_rc6_residency_LDADD = $(LDADD) -lrt +kms_flip_LDADD = $(LDADD) -lpthread prime_nv_test_CFLAGS = $(AM_CFLAGS) $(DRM_NOUVEAU_CFLAGS) prime_nv_test_LDADD = $(LDADD) $(DRM_NOUVEAU_LIBS) -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t 1/2] autoconf: Silence void pointer arithmetic warnings
From: Tvrtko Ursulin Meson build does it so make the two symmetrical in this respect. v2: * Do it properly. (Chris Wilson) Signed-off-by: Tvrtko Ursulin --- configure.ac | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configure.ac b/configure.ac index 4f55ea5d0f89..e22703d03198 100644 --- a/configure.ac +++ b/configure.ac @@ -256,6 +256,9 @@ AC_ARG_ENABLE(werror, [Fail on warnings]), [], [enable_werror=no]) +# disable "warning: pointer of type ‘void *’ used in arithmetic" +AS_COMPILER_FLAG([-Wno-pointer-arith], [CWARNFLAGS+=" -Wno-pointer-arith"], []) + if test "x$enable_debug" = xyes; then AS_COMPILER_FLAG([-g3], [DEBUG_CFLAGS="-g3"], [DEBUG_CFLAGS="-g"]) AS_COMPILER_FLAG([-Og], [DEBUG_CFLAGS+=" -Og -Wno-maybe-uninitialized"], # disable maybe-uninitialized due to false positives -- 2.19.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v6 0/3] drm & vgaarb: handle vgacon removal in vgaarb.
On Fri, Mar 01, 2019 at 07:12:04AM +0100, Gerd Hoffmann wrote: > Hi, > > > > Hmm, I see the test results in patchwork, but I can't remember having > > > seen a mail. > > > So the next question: where the results are sent to? > > From page above sent by Arek: > > " Since we accept patches through mailing lists, this is where you can > > find the results - they are sent out as a replies to the original > > mail. Here are the mailing lists we currently support:" > > Hmm, I'm not subscribed to intel-gfx, so that explains why I havn't > seen the result mails. Any chance to sent the results also to the > patch submitter? Yes, this is the case now. I re-enabled sending the result emails to the authors just yesterday. We had it like that since forever, but recently there was an change to fdo mailing lists which was overwritting "From" headers to workaround some delivery issues, so this feature had to be temporaily disabled. Sorry for the incovenience. -- Cheers, Arek ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] autoconf: Silence void pointer arithmetic warnings
Quoting Tvrtko Ursulin (2019-03-01 10:32:01) > From: Tvrtko Ursulin > > Meson build does it so make the two symmetrical in this respect. > > v2: > * Do it properly. (Chris Wilson) > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] automake: Make librt mandatory
Quoting Tvrtko Ursulin (2019-03-01 10:32:02) > From: Tvrtko Ursulin > > librt is required by libintel_tools so express it as mandatory in autoconf > and also drop explicit mentions from Makefile.am. > > This also fixes a build warning of: > > tests/Makefile.am:134: warning: variable 'pm_rc6_residency_LDADD' is > defined but no program or > tests/Makefile.am:134: library has 'pm_rc6_residency' as canonical name > (possible typo) > > Signed-off-by: Tvrtko Ursulin > --- > benchmarks/Makefile.am | 2 +- > configure.ac | 4 ++-- > tests/Makefile.am | 5 + > 3 files changed, 4 insertions(+), 7 deletions(-) > > diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am > index c166d636d507..1f05adf31527 100644 > --- a/benchmarks/Makefile.am > +++ b/benchmarks/Makefile.am > @@ -24,5 +24,5 @@ gem_exec_tracer_la_LIBADD = -ldl > gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) > gem_latency_LDADD = $(LDADD) -lpthread > gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) > -gem_syslatency_LDADD = $(LDADD) -lpthread -lrt > +gem_syslatency_LDADD = $(LDADD) -lpthread Ok, LDADD here pulls in libintel_tools.la > gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread > diff --git a/configure.ac b/configure.ac > index e22703d03198..a3f541a2f888 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -58,12 +58,12 @@ AX_GCC_FUNC_ATTRIBUTE([constructor]) > dnl Check for POSIX timers > AC_CHECK_FUNCS(timer_create, [], [ > AC_CHECK_LIB(rt, timer_create, [ > - AC_DEFINE(HAVE_TIMER_CREATE, 1) > TIMER_LIBS="-lrt" > ], [ > AC_CHECK_LIB(pthread, timer_create, [ > - AC_DEFINE(HAVE_TIMER_CREATE, 1) > TIMER_LIBS="-lpthread" > + ], [ > + AC_MSG_ERROR([Failed to find library containing > timer_create.]) > ]) > ]) > ]) > diff --git a/tests/Makefile.am b/tests/Makefile.am > index c5dd210c7163..289249b42b97 100644 > --- a/tests/Makefile.am > +++ b/tests/Makefile.am > @@ -128,10 +128,7 @@ gem_userptr_blits_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) > gem_userptr_blits_LDADD = $(LDADD) -lpthread > perf_pmu_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la > > -gem_eio_LDADD = $(LDADD) -lrt > -gem_wait_LDADD = $(LDADD) -lrt > -kms_flip_LDADD = $(LDADD) -lrt -lpthread > -pm_rc6_residency_LDADD = $(LDADD) -lrt > +kms_flip_LDADD = $(LDADD) -lpthread Ok, only those 4. The other one in overlay doesn't pull in libintel_tools.la, but we should probably use $(TIMER_LIBS) there instead. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3)
== Series Details == Series: Enable P0xx (planar), Y2xx/Y4xx (packed) pixel formats (rev3) URL : https://patchwork.freedesktop.org/series/56606/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5675_full -> Patchwork_12336_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12336_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12336_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12336_full: ### IGT changes ### Possible regressions * igt@kms_available_modes_crc@available_mode_test_crc: - shard-iclb: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12336_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-semaphore-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109275] +3 * igt@gem_busy@extended-semaphore-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109275] / [fdo#109276] +1 * igt@gem_ctx_isolation@bcs0-s3: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +21 * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109281] +5 * igt@gem_ctx_isolation@vcs1-s3: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] * igt@gem_ctx_param@invalid-param-set: - shard-iclb: NOTRUN -> FAIL [fdo#109674] * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] +3 * igt@gem_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +20 * igt@gem_exec_parse@oacontrol-tracking: - shard-skl: NOTRUN -> SKIP [fdo#109271] +93 * igt@gem_exec_schedule@preempt-other-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +125 * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> SKIP [fdo#109292] +1 * igt@gem_mocs_settings@mocs-reset-ctx-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +16 * igt@gem_mocs_settings@mocs-settings-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +5 * igt@gem_pwrite@huge-gtt-backwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +10 * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109312] +1 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +16 * igt@gem_tiled_blits@interruptible: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@i915_pm_lpsp@non-edp: - shard-iclb: NOTRUN -> SKIP [fdo#109301] +3 * igt@i915_pm_rpm@basic-rte: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#108654] * igt@i915_pm_rpm@cursor-dpms: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107724] +2 * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] +4 * igt@i915_pm_rpm@fences-dpms: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@legacy-planes: - shard-iclb: NOTRUN -> INCOMPLETE [fdo#108840] / [fdo#109369] * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-iclb: NOTRUN -> SKIP [fdo#109293] +1 * igt@i915_pm_rps@min-max-config-loaded: - shard-iclb: NOTRUN -> FAIL [fdo#102250] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] +1 * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> SKIP [fdo#109303] * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> SKIP [fdo#109302] * igt@i915_selftest@live_contexts: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@i915_suspend@fence-restore-tiled2untiled: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@kms_atomic_transition@3x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +6 * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +51 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WA
[Intel-gfx] [PATCH 1/5] drm/i915/execlists: Suppress redundant preemption
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
v3: Tvrtko pointed out that this, the existing logic, makes
I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
v5: Except not all priorities were made equal, and the WAIT not preempting
is only if we start off as !NEWCLIENT.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 38
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4f2187aa44e4..f57cfe2fc078 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,6 +164,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -190,8 +192,30 @@ static inline int rq_prio(const struct i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
+ int prio = rq_prio(rq);
+
+ /*
+* On unwinding the active request, we give it a priority bump
+* equivalent to a freshly submitted request. This protects it from
+* being gazumped again, but it would be preferable if we didn't
+* let it be gazumped in the first place!
+*
+* See __unwind_incomplete_requests()
+*/
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
+ /*
+* After preemption, we insert the active request at the
+* end of the new priority level. This means that we will be
+* _lower_ priority than the preemptee all things equal (and
+* so the preemption is valid), so adjust our comparison
+* accordingly.
+*/
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
/* Restrict mere WAIT boosts from triggering preemption */
- return rq_prio(rq) | __NO_PREEMPTION;
+ return prio | __NO_PREEMPTION;
}
static int queue_prio(const struct intel_engine_execlists *execlists)
@@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(&engine->timeline.lock);
@@ -390,9 +414,15 @@ __unwind_incomplete_requests(struct intel_engine_cs
*engine)
* The active request is now effectively the start of a new client
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
+*
+* One consequence of this preemption boost is that we may jump
+* over lesser priorities (such as I915_PRIORITY_WAIT), effectively
+* making those priorities non-preemptible. They will be moved forward
+* in the priority queue, but they will not gain immediate access to
+* the GPU.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
+ prio |= ACTIVE_PRIORITY;
active->sched.attr.priority = prio;
list_move_tail(&active->sched.link,
i915_sched_lookup_priolist(engine, prio));
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915: Keep timeline HWSP allocated until idle across the system
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until its use across entire system has completed,
as any other timeline active on the GPU may still refer back to the
already retired timeline. We both have to delay recycling available
cachelines and unpinning old HWSP until the next idle point.
An easy option would be to simply keep all used HWSP until the system as
a whole was idle, i.e. we could release them all at once on parking.
However, on a busy system, we may never see a global idle point,
essentially meaning the resource will be leaked until we are forced to
do a GC pass. We already employ a fine-grained idle detection mechanism
for vma, which we can reuse here so that each cacheline can be freed
immediately after the last request using it is retired.
v3: Keep track of the activity of each cacheline.
v4: cacheline_free() on canceling the seqno tracking
v5: Finally with a testcase to exercise wraparound
v6: Pack cacheline into empty bits of page-aligned vaddr
v7: Use i915_utils to hide the pointer casting around bit manipulation
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 31 +-
drivers/gpu/drm/i915/i915_request.h | 11 +
drivers/gpu/drm/i915/i915_timeline.c | 293 --
drivers/gpu/drm/i915/i915_timeline.h | 11 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 113 +++
5 files changed, 420 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 719d1a5ab082..d354967d6ae8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -325,11 +325,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -532,8 +527,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(&i915->drm.struct_mutex);
@@ -610,24 +607,27 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
-
INIT_LIST_HEAD(&rq->active_list);
+
+ tl = ce->ring->timeline;
+ ret = i915_timeline_get_seqno(tl, rq, &seqno);
+ if (ret)
+ goto err_free;
+
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
+ rq->timeline = tl;
GEM_BUG_ON(rq->timeline == &engine->timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->hwsp_cacheline = tl->hwsp_cacheline;
+ rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
spin_lock_init(&rq->lock);
- dma_fence_init(&rq->fence,
- &i915_fence_ops,
- &rq->lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
+ tl->fence_context, seqno);
/* We bump the ref for the fence chain */
i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
@@ -687,6 +687,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
+err_free:
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
mutex_unlock(&ce->ring->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index be3ded6bcf56..ea1e6f0ade53 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -38,6 +38,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+struct i915_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -148,6 +149,16 @@ struct i915_request {
*/
const u32 *hwsp_seqno;
+ /*
+* If we need to access the timeline's seqno for this request in
+* another request, we need to keep a read reference to this associated
+* cacheline, so that we do not free and recycle it before the foriegn
+* observers have completed. Hence, we keep a
[Intel-gfx] [PATCH 2/5] drm/i915: Introduce i915_timeline.mutex
A simple mutex used for guarding the flow of requests in and out of the
timeline. In the short-term, it will be used only to guard the addition
of requests into the timeline, taken on alloc and released on commit so
that only one caller can construct a request into the timeline
(important as the seqno and ring pointers must be serialised). This will
be used by observers to ensure that the seqno/hwsp is stable. Later,
when we have reduced retiring to only operate on a single timeline at a
time, we can then use the mutex as the sole guard required for retiring.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c| 6 +-
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +---
drivers/gpu/drm/i915/selftests/mock_timeline.c | 1 +
5 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index c65f6c990fdd..719d1a5ab082 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -563,6 +563,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
return ERR_CAST(ce);
reserve_gt(i915);
+ mutex_lock(&ce->ring->timeline->mutex);
/* Move our oldest request to the slab-cache (if not in use!) */
rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
@@ -688,6 +689,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
+ mutex_unlock(&ce->ring->timeline->mutex);
unreserve_gt(i915);
intel_context_unpin(ce);
return ERR_PTR(ret);
@@ -880,7 +882,7 @@ void i915_request_add(struct i915_request *request)
GEM_TRACE("%s fence %llx:%lld\n",
engine->name, request->fence.context, request->fence.seqno);
- lockdep_assert_held(&request->i915->drm.struct_mutex);
+ lockdep_assert_held(&request->timeline->mutex);
trace_i915_request_add(request);
/*
@@ -991,6 +993,8 @@ void i915_request_add(struct i915_request *request)
*/
if (prev && i915_request_completed(prev))
i915_request_retire_upto(prev);
+
+ mutex_unlock(&request->timeline->mutex);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index b2202d2e58a2..87a80558da28 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -162,6 +162,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->fence_context = dma_fence_context_alloc(1);
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 7bec7d2e45bf..36c3849f7108 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -44,6 +44,8 @@ struct i915_timeline {
#define TIMELINE_CLIENT 0 /* default subclass */
#define TIMELINE_ENGINE 1
+ struct mutex mutex; /* protects the flow of requests */
+
unsigned int pin_count;
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 7da52e3d67af..7e1b65b8eb19 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -141,14 +141,12 @@ static int igt_fence_wait(void *arg)
err = -ENOMEM;
goto out_locked;
}
- mutex_unlock(&i915->drm.struct_mutex); /* safe as we are single user */
if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
pr_err("fence wait success before submit (expected
timeout)!\n");
- goto out_device;
+ goto out_locked;
}
- mutex_lock(&i915->drm.struct_mutex);
i915_request_add(request);
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c
b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index d2de9ece2118..416d85233263 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -14,6 +14,7 @@ void mock_timeline_init(struct i915_timeline *timeline, u64
context)
timeline->fence_context = context;
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
--
2.20.1
___
Intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 5 +
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..1524de65b37f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.semaphore |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!request->sched.semaphore)
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..fd684b9ed108 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->semaphore = 0;
}
static struct i915_dependency *
@@ -69,6 +70,10 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->semaphore && !node_started(signal))
+ node->semaphore |= signal->semaphore << 1;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..068a6750540f 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned long semaphore;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53d6f7fdb50e..2268860cca44 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
-#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE)
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
struct intel_engine_cs *engine,
--
2.20.1
_
[Intel-gfx] [PATCH 4/5] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
As might be reasonably expected, HW semaphores excel in inter-engine
synchronisation microbenchmarks (where the 3x reduced latency / increased
throughput more than offset the power cost of spinning on a second ring)
and have significant improvement (can be up to ~10%, most see no change)
for single clients that utilize multiple engines (typically media players
and transcoders), without regressing multiple clients that can saturate
the system or changing the power envelope dramatically.
v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
v4: Tell the world and include it as part of scheduler caps.
Testcase: igt/gem_exec_whisper
Testcase: igt/benchmarks/gem_wsim
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 138 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 160 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..c08abdef5eb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,7 +351,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = 0;
+ value = !!(dev_priv->caps.scheduler &
I915_SCHEDULER_CAP_SEMAPHORES);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d354967d6ae8..59e30b8c4ee9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -32,9 +33,16 @@
#include "i915_active.h"
#include "i915_reset.h"
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
static struct i915_global_request {
struct kmem_cache *slab_requests;
struct kmem_cache *slab_dependencies;
+ struct kmem_cache *slab_execute_cbs;
} global;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
@@ -325,6 +333,69 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kmem_cache_free(global.slab_execute_cbs, cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(&rq->lock);
+
+ if (list_empty(&rq->execute_cb))
+ return;
+
+ list_for_each_entry(cb, &rq->execute_cb, link)
+ irq_work_queue(&cb->work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(&rq->execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+
+ if (i915_request_is_active(signal))
+ return 0;
+
+ cb = kmem_c
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm: move a detected edid member to drm_connector from intel_connector
== Series Details == Series: series starting with [1/2] drm: move a detected edid member to drm_connector from intel_connector URL : https://patchwork.freedesktop.org/series/57397/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6c66b5f875a6 drm: move a detected edid member to drm_connector from intel_connector -:37: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!connector->detect_edid" #37: FILE: drivers/gpu/drm/i915/intel_dp.c:4482: + if (connector->detect_edid == NULL || total: 0 errors, 0 warnings, 1 checks, 111 lines checked 3b877e903a5d drm: Add detection of changing of edid on between suspend and resume ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm: move a detected edid member to drm_connector from intel_connector
== Series Details == Series: series starting with [1/2] drm: move a detected edid member to drm_connector from intel_connector URL : https://patchwork.freedesktop.org/series/57397/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5676 -> Patchwork_12339 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12339 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12339, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/57397/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12339: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - fi-byt-j1900: PASS -> DMESG-WARN * igt@runner@aborted: - fi-bsw-n3050: NOTRUN -> FAIL Known issues Here are the changes found in Patchwork_12339 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_module_load@reload-with-fault-injection: - fi-bsw-n3050: PASS -> DMESG-WARN [fdo#107732] * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@runner@aborted: - fi-byt-j1900: NOTRUN -> FAIL [fdo#105602] Possible fixes * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 Participating hosts (44 -> 41) -- Additional (2): fi-icl-u2 fi-pnv-d510 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y Build changes - * Linux: CI_DRM_5676 -> Patchwork_12339 CI_DRM_5676: 3911a5d7d3de6d8e491868bb0cd506346131d71b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12339: 3b877e903a5d54cc8fdb5da849978d7a18b21099 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3b877e903a5d drm: Add detection of changing of edid on between suspend and resume 6c66b5f875a6 drm: move a detected edid member to drm_connector from intel_connector == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12339/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listi
[Intel-gfx] [PATCH xf86-video-intel v2] sna: Switch back to hwcursor on the next cursor update
From: Ville Syrjälä Once we've switched to using the swcursor (possibly due to the cursor ioctl failing) we currently keep using the swcursor until the modeset. That's not particularly great as the swcursor has several issues. Apart from the (presumably expected) flicker, the cursor also tends to leave horrible trails behind around dri2/3 windows (happens with tearfree at least). To avoid some of that let's try to switch back to the hwcursor a bit sooner. We can do that neatly via the convenient swcursor block handler. v2 [ickle]: Apply the restoration after the screen update is complete. References: https://bugs.freedesktop.org/show_bug.cgi?id=106935 Signed-off-by: Ville Syrjälä --- src/sna/sna_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/sna/sna_display.c b/src/sna/sna_display.c index fe67f85b6..0ea608cb6 100644 --- a/src/sna/sna_display.c +++ b/src/sna/sna_display.c @@ -9106,6 +9106,9 @@ void sna_mode_redisplay(struct sna *sna) return; } + /* Try to switch back to the HW cursor on the next cursor update */ + sna->cursor.disable = false; + if (!sna->mode.shadow_enabled) return; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Keep timeline HWSP allocated until idle across the system
On 01/03/2019 11:05, Chris Wilson wrote:
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until its use across entire system has completed,
as any other timeline active on the GPU may still refer back to the
already retired timeline. We both have to delay recycling available
cachelines and unpinning old HWSP until the next idle point.
An easy option would be to simply keep all used HWSP until the system as
a whole was idle, i.e. we could release them all at once on parking.
However, on a busy system, we may never see a global idle point,
essentially meaning the resource will be leaked until we are forced to
do a GC pass. We already employ a fine-grained idle detection mechanism
for vma, which we can reuse here so that each cacheline can be freed
immediately after the last request using it is retired.
v3: Keep track of the activity of each cacheline.
v4: cacheline_free() on canceling the seqno tracking
v5: Finally with a testcase to exercise wraparound
v6: Pack cacheline into empty bits of page-aligned vaddr
v7: Use i915_utils to hide the pointer casting around bit manipulation
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 31 +-
drivers/gpu/drm/i915/i915_request.h | 11 +
drivers/gpu/drm/i915/i915_timeline.c | 293 --
drivers/gpu/drm/i915/i915_timeline.h | 11 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 113 +++
5 files changed, 420 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 719d1a5ab082..d354967d6ae8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -325,11 +325,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -532,8 +527,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(&i915->drm.struct_mutex);
@@ -610,24 +607,27 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
-
INIT_LIST_HEAD(&rq->active_list);
+
+ tl = ce->ring->timeline;
+ ret = i915_timeline_get_seqno(tl, rq, &seqno);
+ if (ret)
+ goto err_free;
+
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
+ rq->timeline = tl;
GEM_BUG_ON(rq->timeline == &engine->timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->hwsp_cacheline = tl->hwsp_cacheline;
+ rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
spin_lock_init(&rq->lock);
- dma_fence_init(&rq->fence,
- &i915_fence_ops,
- &rq->lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
+ tl->fence_context, seqno);
/* We bump the ref for the fence chain */
i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
@@ -687,6 +687,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
+err_free:
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
mutex_unlock(&ce->ring->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index be3ded6bcf56..ea1e6f0ade53 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -38,6 +38,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+struct i915_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -148,6 +149,16 @@ struct i915_request {
*/
const u32 *hwsp_seqno;
+ /*
+* If we need to access the timeline's seqno for this request in
+* another request, we need to keep a read reference to this associated
+* cacheline, so that we do not free and recycle it before the foriegn
fo
Re: [Intel-gfx] [PATCH 3/7] drm/leases: Don't init to 0 in drm_master_create
Daniel Vetter writes: > We kzalloc. > > Cc: Keith Packard > Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/drm_auth.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c > index 1669c42c40ed..bcf0a5a1018f 100644 > --- a/drivers/gpu/drm/drm_auth.c > +++ b/drivers/gpu/drm/drm_auth.c > @@ -109,8 +109,6 @@ struct drm_master *drm_master_create(struct drm_device > *dev) > master->dev = dev; > > /* initialize the tree of output resource lessees */ > - master->lessor = NULL; > - master->lessee_id = 0; > INIT_LIST_HEAD(&master->lessees); > INIT_LIST_HEAD(&master->lessee_list); > idr_init(&master->leases); > -- > 2.14.4 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] drm/i915/execlists: Suppress redundant preemption
ping on below
On 28/02/2019 13:11, Tvrtko Ursulin wrote:
On 26/02/2019 10:23, Chris Wilson wrote:
On unwinding the active request we give it a small (limited to internal
priority levels) boost to prevent it from being gazumped a second time.
However, this means that it can be promoted to above the request that
triggered the preemption request, causing a preempt-to-idle cycle for no
change. We can avoid this if we take the boost into account when
checking if the preemption request is valid.
v2: After preemption the active request will be after the preemptee if
they end up with equal priority.
v3: Tvrtko pointed out that this, the existing logic, makes
I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
v5: Except not all priorities were made equal, and the WAIT not
preempting
is only if we start off as !NEWCLIENT.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 38
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
b/drivers/gpu/drm/i915/intel_lrc.c
index 0e20f3bc8210..dba19baf6808 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,6 +164,8 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
+#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+
static int execlists_context_deferred_alloc(struct i915_gem_context
*ctx,
struct intel_engine_cs *engine,
struct intel_context *ce);
@@ -190,8 +192,30 @@ static inline int rq_prio(const struct
i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
+ int prio = rq_prio(rq);
+
+ /*
+ * On unwinding the active request, we give it a priority bump
+ * equivalent to a freshly submitted request. This protects it from
+ * being gazumped again, but it would be preferable if we didn't
+ * let it be gazumped in the first place!
+ *
+ * See __unwind_incomplete_requests()
+ */
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
+ /*
+ * After preemption, we insert the active request at the
+ * end of the new priority level. This means that we will be
+ * _lower_ priority than the preemptee all things equal (and
+ * so the preemption is valid), so adjust our comparison
+ * accordingly.
+ */
+ prio |= ACTIVE_PRIORITY;
+ prio--;
+ }
+
/* Restrict mere WAIT boosts from triggering preemption */
- return rq_prio(rq) | __NO_PREEMPTION;
+ return prio | __NO_PREEMPTION;
}
static int queue_prio(const struct intel_engine_execlists *execlists)
@@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct
intel_engine_cs *engine)
{
struct i915_request *rq, *rn, *active = NULL;
struct list_head *uninitialized_var(pl);
- int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
+ int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
lockdep_assert_held(&engine->timeline.lock);
@@ -390,9 +414,15 @@ __unwind_incomplete_requests(struct
intel_engine_cs *engine)
* The active request is now effectively the start of a new client
* stream, so give it the equivalent small priority bump to prevent
* it being gazumped a second time by another peer.
+ *
+ * One consequence of this preemption boost is that we may jump
+ * over lesser priorities (such as I915_PRIORITY_WAIT), effectively
+ * making those priorities non-preemptible. They will be moved
forward
After the previous patch wait priority is non-preemptible by definition
making this suggestion preemption boost is making it so not accurate.
+ * in the priority queue, but they will not gain immediate access to
+ * the GPU.
*/
- if (!(prio & I915_PRIORITY_NEWCLIENT)) {
- prio |= I915_PRIORITY_NEWCLIENT;
+ if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
What is the importance of the has_started check? Hasn't the active
request been running by definition?
+ prio |= ACTIVE_PRIORITY;
active->sched.attr.priority = prio;
list_move_tail(&active->sched.link,
i915_sched_lookup_priolist(engine, prio));
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57400/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915: Introduce i915_timeline.mutex Okay! Commit: drm/i915: Keep timeline HWSP allocated until idle across the system Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ -O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/5] drm/i915: Keep timeline HWSP allocated until idle across the system
Quoting Tvrtko Ursulin (2019-03-01 11:29:06)
>
> On 01/03/2019 11:05, Chris Wilson wrote:
> > +int i915_timeline_read_hwsp(struct i915_request *from,
> > + struct i915_request *to,
> > + u32 *hwsp)
> > +{
> > + struct i915_timeline_cacheline *cl = from->hwsp_cacheline;
>
> Is it okay to access the pointer outside the mutex? Below in
> cacheline_ref it is used.
Hmm, good question. The pointer is safe...
> It kind of evaporated what I learnt from the initial review since there
> is so much new stuff.. :(
>
> > + struct i915_timeline *tl = from->timeline;
> > + int err;
> > +
> > + GEM_BUG_ON(to->timeline == tl);
> > +
> > + mutex_lock_nested(&tl->mutex, SINGLE_DEPTH_NESTING);
> > + err = i915_request_completed(from);
...as we may only release it on retiring the request...
> > + if (!err)
> > + err = cacheline_ref(cl, to);
> > + if (!err) {
> > + if (likely(cl == tl->hwsp_cacheline)) {
>
> Or it's here where you check it is still the same?
So to get here, we have proven under the mutex (so no simultaneous
retiring) that the pointer is still valid and current and so safe to
dereference.
It can't be changed on the old request (so no READ_ONCE or mutex
required to store the pointer in a local), but it may be left dangling.
-Chris
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 03/11] drm/i915/execlists: Suppress redundant preemption
Quoting Tvrtko Ursulin (2019-03-01 11:31:26)
>
> ping on below
>
> On 28/02/2019 13:11, Tvrtko Ursulin wrote:
> >
> > On 26/02/2019 10:23, Chris Wilson wrote:
> >> On unwinding the active request we give it a small (limited to internal
> >> priority levels) boost to prevent it from being gazumped a second time.
> >> However, this means that it can be promoted to above the request that
> >> triggered the preemption request, causing a preempt-to-idle cycle for no
> >> change. We can avoid this if we take the boost into account when
> >> checking if the preemption request is valid.
> >>
> >> v2: After preemption the active request will be after the preemptee if
> >> they end up with equal priority.
> >>
> >> v3: Tvrtko pointed out that this, the existing logic, makes
> >> I915_PRIORITY_WAIT non-preemptible. Document this interesting quirk!
> >>
> >> v4: Prove Tvrtko was right about WAIT being non-preemptible and test it.
> >> v5: Except not all priorities were made equal, and the WAIT not
> >> preempting
> >> is only if we start off as !NEWCLIENT.
> >>
> >> Signed-off-by: Chris Wilson
> >> Cc: Tvrtko Ursulin
> >> ---
> >> drivers/gpu/drm/i915/intel_lrc.c | 38
> >> 1 file changed, 34 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> >> b/drivers/gpu/drm/i915/intel_lrc.c
> >> index 0e20f3bc8210..dba19baf6808 100644
> >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >> @@ -164,6 +164,8 @@
> >> #define WA_TAIL_DWORDS 2
> >> #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
> >> +#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
> >> +
> >> static int execlists_context_deferred_alloc(struct i915_gem_context
> >> *ctx,
> >> struct intel_engine_cs *engine,
> >> struct intel_context *ce);
> >> @@ -190,8 +192,30 @@ static inline int rq_prio(const struct
> >> i915_request *rq)
> >> static int effective_prio(const struct i915_request *rq)
> >> {
> >> + int prio = rq_prio(rq);
> >> +
> >> + /*
> >> + * On unwinding the active request, we give it a priority bump
> >> + * equivalent to a freshly submitted request. This protects it from
> >> + * being gazumped again, but it would be preferable if we didn't
> >> + * let it be gazumped in the first place!
> >> + *
> >> + * See __unwind_incomplete_requests()
> >> + */
> >> + if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
> >> + /*
> >> + * After preemption, we insert the active request at the
> >> + * end of the new priority level. This means that we will be
> >> + * _lower_ priority than the preemptee all things equal (and
> >> + * so the preemption is valid), so adjust our comparison
> >> + * accordingly.
> >> + */
> >> + prio |= ACTIVE_PRIORITY;
> >> + prio--;
> >> + }
> >> +
> >> /* Restrict mere WAIT boosts from triggering preemption */
> >> - return rq_prio(rq) | __NO_PREEMPTION;
> >> + return prio | __NO_PREEMPTION;
> >> }
> >> static int queue_prio(const struct intel_engine_execlists *execlists)
> >> @@ -359,7 +383,7 @@ __unwind_incomplete_requests(struct
> >> intel_engine_cs *engine)
> >> {
> >> struct i915_request *rq, *rn, *active = NULL;
> >> struct list_head *uninitialized_var(pl);
> >> - int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
> >> + int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
> >> lockdep_assert_held(&engine->timeline.lock);
> >> @@ -390,9 +414,15 @@ __unwind_incomplete_requests(struct
> >> intel_engine_cs *engine)
> >> * The active request is now effectively the start of a new client
> >> * stream, so give it the equivalent small priority bump to prevent
> >> * it being gazumped a second time by another peer.
> >> + *
> >> + * One consequence of this preemption boost is that we may jump
> >> + * over lesser priorities (such as I915_PRIORITY_WAIT), effectively
> >> + * making those priorities non-preemptible. They will be moved
> >> forward
> >
> > After the previous patch wait priority is non-preemptible by definition
> > making this suggestion preemption boost is making it so not accurate.
> >
> >> + * in the priority queue, but they will not gain immediate access to
> >> + * the GPU.
> >> */
> >> - if (!(prio & I915_PRIORITY_NEWCLIENT)) {
> >> - prio |= I915_PRIORITY_NEWCLIENT;
> >> + if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
> >
> > What is the importance of the has_started check? Hasn't the active
> > request been running by definition?
No. Semaphores. This is all about defending against incorrect promotion
while a request is still spinning on its dependencies (or else we get
promoted above them and PI is broken).
-Chris
___
Intel-gfx ma
Re: [Intel-gfx] [PATCH 4/5] drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+
On 01/03/2019 11:05, Chris Wilson wrote:
Having introduced per-context seqno, we now have a means to identity
progress across the system without feel of rollback as befell the
global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
advance of submission safe in the knowledge that our target seqno and
address is stable.
However, since we are telling the GPU to busy-spin on the target address
until it matches the signaling seqno, we only want to do so when we are
sure that busy-spin will be completed quickly. To achieve this we only
submit the request to HW once the signaler is itself executing (modulo
preemption causing us to wait longer), and we only do so for default and
above priority requests (so that idle priority tasks never themselves
hog the GPU waiting for others).
As might be reasonably expected, HW semaphores excel in inter-engine
synchronisation microbenchmarks (where the 3x reduced latency / increased
throughput more than offset the power cost of spinning on a second ring)
and have significant improvement (can be up to ~10%, most see no change)
for single clients that utilize multiple engines (typically media players
and transcoders), without regressing multiple clients that can saturate
the system or changing the power envelope dramatically.
v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
v4: Tell the world and include it as part of scheduler caps.
Testcase: igt/gem_exec_whisper
Testcase: igt/benchmarks/gem_wsim
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 138 +-
drivers/gpu/drm/i915/i915_request.h | 1 +
drivers/gpu/drm/i915/i915_sw_fence.c | 4 +-
drivers/gpu/drm/i915/i915_sw_fence.h | 3 +
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_gpu_commands.h | 9 +-
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 7 ++
include/uapi/drm/i915_drm.h | 1 +
10 files changed, 160 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c6354f6cdbdb..c08abdef5eb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -351,7 +351,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = 0;
+ value = !!(dev_priv->caps.scheduler &
I915_SCHEDULER_CAP_SEMAPHORES);
break;
case I915_PARAM_HAS_SECURE_BATCHES:
value = capable(CAP_SYS_ADMIN);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index d354967d6ae8..59e30b8c4ee9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -22,8 +22,9 @@
*
*/
-#include
#include
+#include
+#include
#include
#include
#include
@@ -32,9 +33,16 @@
#include "i915_active.h"
#include "i915_reset.h"
+struct execute_cb {
+ struct list_head link;
+ struct irq_work work;
+ struct i915_sw_fence *fence;
+};
+
static struct i915_global_request {
struct kmem_cache *slab_requests;
struct kmem_cache *slab_dependencies;
+ struct kmem_cache *slab_execute_cbs;
} global;
static const char *i915_fence_get_driver_name(struct dma_fence *fence)
@@ -325,6 +333,69 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
+static void irq_execute_cb(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ i915_sw_fence_complete(cb->fence);
+ kmem_cache_free(global.slab_execute_cbs, cb);
+}
+
+static void __notify_execute_cb(struct i915_request *rq)
+{
+ struct execute_cb *cb;
+
+ lockdep_assert_held(&rq->lock);
+
+ if (list_empty(&rq->execute_cb))
+ return;
+
+ list_for_each_entry(cb, &rq->execute_cb, link)
+ irq_work_queue(&cb->work);
+
+ /*
+* XXX Rollback on __i915_request_unsubmit()
+*
+* In the future, perhaps when we have an active time-slicing scheduler,
+* it will be interesting to unsubmit parallel execution and remove
+* busywaits from the GPU until their master is restarted. This is
+* quite hairy, we have to carefully rollback the fence and do a
+* preempt-to-idle cycle on the target engine, all the while the
+* master execute_cb may refire.
+*/
+ INIT_LIST_HEAD(&rq->execute_cb);
+}
+
+static int
+i915_request_await_execution(struct i915_request *rq,
+struct i915_request *signal,
+gfp_t gfp)
+{
+ struct execute_cb *cb;
+
+ if (i915
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Introduce i915_timeline.mutex
On 01/03/2019 11:05, Chris Wilson wrote:
A simple mutex used for guarding the flow of requests in and out of the
timeline. In the short-term, it will be used only to guard the addition
of requests into the timeline, taken on alloc and released on commit so
that only one caller can construct a request into the timeline
(important as the seqno and ring pointers must be serialised). This will
be used by observers to ensure that the seqno/hwsp is stable. Later,
when we have reduced retiring to only operate on a single timeline at a
time, we can then use the mutex as the sole guard required for retiring.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c| 6 +-
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +---
drivers/gpu/drm/i915/selftests/mock_timeline.c | 1 +
5 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index c65f6c990fdd..719d1a5ab082 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -563,6 +563,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
return ERR_CAST(ce);
reserve_gt(i915);
+ mutex_lock(&ce->ring->timeline->mutex);
/* Move our oldest request to the slab-cache (if not in use!) */
rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
@@ -688,6 +689,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
+ mutex_unlock(&ce->ring->timeline->mutex);
unreserve_gt(i915);
intel_context_unpin(ce);
return ERR_PTR(ret);
@@ -880,7 +882,7 @@ void i915_request_add(struct i915_request *request)
GEM_TRACE("%s fence %llx:%lld\n",
engine->name, request->fence.context, request->fence.seqno);
- lockdep_assert_held(&request->i915->drm.struct_mutex);
+ lockdep_assert_held(&request->timeline->mutex);
trace_i915_request_add(request);
/*
@@ -991,6 +993,8 @@ void i915_request_add(struct i915_request *request)
*/
if (prev && i915_request_completed(prev))
i915_request_retire_upto(prev);
+
+ mutex_unlock(&request->timeline->mutex);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index b2202d2e58a2..87a80558da28 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -162,6 +162,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->fence_context = dma_fence_context_alloc(1);
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 7bec7d2e45bf..36c3849f7108 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -44,6 +44,8 @@ struct i915_timeline {
#define TIMELINE_CLIENT 0 /* default subclass */
#define TIMELINE_ENGINE 1
+ struct mutex mutex; /* protects the flow of requests */
+
unsigned int pin_count;
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 7da52e3d67af..7e1b65b8eb19 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -141,14 +141,12 @@ static int igt_fence_wait(void *arg)
err = -ENOMEM;
goto out_locked;
}
- mutex_unlock(&i915->drm.struct_mutex); /* safe as we are single user */
if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
pr_err("fence wait success before submit (expected
timeout)!\n");
- goto out_device;
+ goto out_locked;
}
- mutex_lock(&i915->drm.struct_mutex);
i915_request_add(request);
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index d2de9ece2118..416d85233263 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -14,6 +14,7 @@ void mock_timeline_init(struct i915_timeline *timeline, u64
context)
timeline->fence_context = context;
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
So hard to predict if this will be okay in the
Re: [Intel-gfx] [RFC v4 12/25] drm/i915: Add drm_driver->initial_client_display callback
Den 16.04.2018 10.38, skrev Daniel Vetter:
> On Sat, Apr 14, 2018 at 01:53:05PM +0200, Noralf Trønnes wrote:
>> As part of moving the modesetting code out of drm_fb_helper and into
>> drm_client, the drm_fb_helper_funcs->initial_config callback needs to go.
>> Replace it with a drm_driver->initial_client_display callback that can
>> work for all in-kernel clients.
>>
>> TODO:
>> - Add a patch that moves the function out of intel_fbdev.c since it's not
>> fbdev specific anymore.
>>
>> Signed-off-by: Noralf Trønnes
>
> So the reason we originally added this callback for i915 fast boot was
> that there wasn't any atomic around yet. And it was all an experiment to
> figure out how to best go about designing fastboot.
>
> But now we have fbdev, and fastboot design is also pretty clear:
>
> 1. driver loads
> 2. driver reads out current hw state, reconstructs a full atomic state for
> everything and stuffs it into connector/crtc/plane->state pointers.
> 3. fbdev and any other client read out current state (with some caveats)
> and just take it over.
>
> What non-fastboot drivers do:
> 1. drivers load
> 2. reset both hw and sw state to everything off.
>
> Now the intel_fb_initial_config is all generic code really, and it will
> neatly fall back to the default config if everything is off. This means we
> could:
> 1. Move the intel_fb_initial_config into the fbdev helpers.
> 2. Nuke the ->initial_config callback.
>
> And pronto! every driver which implements hw state readout will get fbdev
> fastboot for free.
>
I'm back working on this now and there's one intel specific thing:
num_pipes, in that function that I don't know how to handle when moving
the code into the fbdev helper:
static bool intel_fb_initial_config(...)
{
[...]
/*
* If the BIOS didn't enable everything it could, fall back to have the
* same user experiencing of lighting up as much as possible like the
* fbdev helper library.
*/
if (num_connectors_enabled != num_connectors_detected &&
num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
DRM_DEBUG_KMS("Enabled: %i, detected: %i\n",
num_connectors_enabled,
num_connectors_detected);
fallback = true;
}
Noralf.
> And since you've already rewritting the intel code to use drm_client, it's
> practically done already. Just need to s/intel_/drm_fbdev_helper_ or
> something like that :-)
> -Daniel
>
>> ---
>> drivers/gpu/drm/drm_fb_helper.c| 19 +--
>> drivers/gpu/drm/i915/i915_drv.c| 1 +
>> drivers/gpu/drm/i915/intel_drv.h | 11
>> drivers/gpu/drm/i915/intel_fbdev.c | 113
>> ++---
>> include/drm/drm_drv.h | 21 +++
>> 5 files changed, 104 insertions(+), 61 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_fb_helper.c
>> b/drivers/gpu/drm/drm_fb_helper.c
>> index b992f59dad30..5407bf6dc8c0 100644
>> --- a/drivers/gpu/drm/drm_fb_helper.c
>> +++ b/drivers/gpu/drm/drm_fb_helper.c
>> @@ -2103,6 +2103,20 @@ static void drm_setup_crtcs(struct drm_fb_helper
>> *fb_helper,
>> /* prevent concurrent modification of connector_count by hotplug */
>> lockdep_assert_held(&fb_helper->lock);
>>
>> +mutex_lock(&dev->mode_config.mutex);
>> +if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) == 0)
>> +DRM_DEBUG_KMS("No connectors reported connected with modes\n");
>> +
>> +if (dev->driver->initial_client_display) {
>> +display = dev->driver->initial_client_display(dev, width,
>> height);
>> +if (display) {
>> +drm_client_display_free(fb_helper->display);
>> +fb_helper->display = display;
>> +mutex_unlock(&dev->mode_config.mutex);
>> +return;
>> +}
>> +}
>> +
>> crtcs = kcalloc(fb_helper->connector_count,
>> sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
>> modes = kcalloc(fb_helper->connector_count,
>> @@ -2120,9 +2134,6 @@ static void drm_setup_crtcs(struct drm_fb_helper
>> *fb_helper,
>> if (IS_ERR(display))
>> goto out;
>>
>> -mutex_lock(&fb_helper->dev->mode_config.mutex);
>> -if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) == 0)
>> -DRM_DEBUG_KMS("No connectors reported connected with modes\n");
>> drm_enable_connectors(fb_helper, enabled);
>>
>> if (!(fb_helper->funcs->initial_config &&
>> @@ -2144,7 +2155,6 @@ static void drm_setup_crtcs(struct drm_fb_helper
>> *fb_helper,
>>
>> drm_pick_crtcs(fb_helper, crtcs, modes, 0, width, height);
>> }
>> -mutex_unlock(&fb_helper->dev->mode_config.mutex);
>>
>> /* need to set the modesets up here for use later */
>> /* fill out the connector<->crtc mappings into the modes
Re: [Intel-gfx] [PATCH 2/5] drm/i915: Introduce i915_timeline.mutex
Quoting Tvrtko Ursulin (2019-03-01 11:38:11) > > On 01/03/2019 11:05, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c > > b/drivers/gpu/drm/i915/selftests/mock_timeline.c > > index d2de9ece2118..416d85233263 100644 > > --- a/drivers/gpu/drm/i915/selftests/mock_timeline.c > > +++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c > > @@ -14,6 +14,7 @@ void mock_timeline_init(struct i915_timeline *timeline, > > u64 context) > > timeline->fence_context = context; > > > > spin_lock_init(&timeline->lock); > > + mutex_init(&timeline->mutex); > > > > INIT_ACTIVE_REQUEST(&timeline->barrier); > > INIT_ACTIVE_REQUEST(&timeline->last_request); > > > > So hard to predict if this will be okay in the future and keep a mental > image of the endgame in ones head. Yeah, it'll change anyway as soon as we meet the enemy. At the moment, it seems a fundamental mutex that we can't avoid, the timeline must be serialised (for access to the ring and seqno, request construct must be sequential) and from there we extend it to cover retirement and activity tracking. It may be that we can split the mutex further (allow for parallel construction and retirement? but that seems an unlikely win since timeline == client and so we expect to parcel work up into timeline/client bundles), but for now timeline->mutex seems like a solid plan of action. (At least it gets us as far as allowing clients to submit requests independently, after that my crystal ball is cloudy.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Prioritise non-busywait semaphore workloads
On 01/03/2019 11:05, Chris Wilson wrote:
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 5 +
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..1524de65b37f 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.semaphore |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!request->sched.semaphore)
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..fd684b9ed108 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->semaphore = 0;
}
static struct i915_dependency *
@@ -69,6 +70,10 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->semaphore && !node_started(signal))
+ node->semaphore |= signal->semaphore << 1;
Maybe I am confused.. this moves the bit flag to the left. Can't it fall
off the end and we end up with zero after a deep enough chain?
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..068a6750540f 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned long semaphore;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
unsigned int?
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53d6f7fdb50e..2268860cca44 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
-#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT)
+#define ACTIVE_PRIORITY (I915_PRIORITY
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/execlists: Suppress redundant preemption
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Suppress redundant preemption URL : https://patchwork.freedesktop.org/series/57400/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676 -> Patchwork_12340 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57400/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12340 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@i915_selftest@live_hangcheck: - fi-icl-u3: PASS -> INCOMPLETE [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +20 * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS * igt@kms_busy@basic-flip-b: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (44 -> 40) -- Additional (2): fi-icl-u2 fi-pnv-d510 Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-skl-6770hq fi-byt-squawks fi-bsw-cyan Build changes - * Linux: CI_DRM_5676 -> Patchwork_12340 CI_DRM_5676: 3911a5d7d3de6d8e491868bb0cd506346131d71b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12340: 7b69f5e30b4f8fa5e34c74a72e464947995c5574 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7b69f5e30b4f drm/i915: Prioritise non-busywait semaphore workloads cc94eb7d794e drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ f3d37bb464f1 drm/i915: Keep timeline HWSP allocated until idle across the system d06ba23a4b7b drm/i915: Introduce i915_timeline.mutex 9407a5e6f45b drm/i915/execlists: Suppress redundant preemption == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12340/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC v4 12/25] drm/i915: Add drm_driver->initial_client_display callback
On Fri, Mar 1, 2019 at 12:46 PM Noralf Trønnes wrote:
>
>
>
> Den 16.04.2018 10.38, skrev Daniel Vetter:
> > On Sat, Apr 14, 2018 at 01:53:05PM +0200, Noralf Trønnes wrote:
> >> As part of moving the modesetting code out of drm_fb_helper and into
> >> drm_client, the drm_fb_helper_funcs->initial_config callback needs to go.
> >> Replace it with a drm_driver->initial_client_display callback that can
> >> work for all in-kernel clients.
> >>
> >> TODO:
> >> - Add a patch that moves the function out of intel_fbdev.c since it's not
> >> fbdev specific anymore.
> >>
> >> Signed-off-by: Noralf Trønnes
> >
> > So the reason we originally added this callback for i915 fast boot was
> > that there wasn't any atomic around yet. And it was all an experiment to
> > figure out how to best go about designing fastboot.
> >
> > But now we have fbdev, and fastboot design is also pretty clear:
> >
> > 1. driver loads
> > 2. driver reads out current hw state, reconstructs a full atomic state for
> > everything and stuffs it into connector/crtc/plane->state pointers.
> > 3. fbdev and any other client read out current state (with some caveats)
> > and just take it over.
> >
> > What non-fastboot drivers do:
> > 1. drivers load
> > 2. reset both hw and sw state to everything off.
> >
> > Now the intel_fb_initial_config is all generic code really, and it will
> > neatly fall back to the default config if everything is off. This means we
> > could:
> > 1. Move the intel_fb_initial_config into the fbdev helpers.
> > 2. Nuke the ->initial_config callback.
> >
> > And pronto! every driver which implements hw state readout will get fbdev
> > fastboot for free.
> >
>
> I'm back working on this now and there's one intel specific thing:
> num_pipes, in that function that I don't know how to handle when moving
> the code into the fbdev helper:
num_pipes == dev->mode_config.num_crtcs. Or should at least if we
managed to set up everything correctly. Not exactly sure why we've
used that intel-ism there, shouldn't have any effect when switching
over.
-Daniel
>
> static bool intel_fb_initial_config(...)
> {
> [...]
> /*
> * If the BIOS didn't enable everything it could, fall back to have
> the
> * same user experiencing of lighting up as much as possible like the
> * fbdev helper library.
> */
> if (num_connectors_enabled != num_connectors_detected &&
> num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
> DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
> DRM_DEBUG_KMS("Enabled: %i, detected: %i\n",
> num_connectors_enabled,
> num_connectors_detected);
> fallback = true;
> }
>
> Noralf.
>
> > And since you've already rewritting the intel code to use drm_client, it's
> > practically done already. Just need to s/intel_/drm_fbdev_helper_ or
> > something like that :-)
> > -Daniel
> >
> >> ---
> >> drivers/gpu/drm/drm_fb_helper.c| 19 +--
> >> drivers/gpu/drm/i915/i915_drv.c| 1 +
> >> drivers/gpu/drm/i915/intel_drv.h | 11
> >> drivers/gpu/drm/i915/intel_fbdev.c | 113
> >> ++---
> >> include/drm/drm_drv.h | 21 +++
> >> 5 files changed, 104 insertions(+), 61 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/drm_fb_helper.c
> >> b/drivers/gpu/drm/drm_fb_helper.c
> >> index b992f59dad30..5407bf6dc8c0 100644
> >> --- a/drivers/gpu/drm/drm_fb_helper.c
> >> +++ b/drivers/gpu/drm/drm_fb_helper.c
> >> @@ -2103,6 +2103,20 @@ static void drm_setup_crtcs(struct drm_fb_helper
> >> *fb_helper,
> >> /* prevent concurrent modification of connector_count by hotplug */
> >> lockdep_assert_held(&fb_helper->lock);
> >>
> >> +mutex_lock(&dev->mode_config.mutex);
> >> +if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) ==
> >> 0)
> >> +DRM_DEBUG_KMS("No connectors reported connected with
> >> modes\n");
> >> +
> >> +if (dev->driver->initial_client_display) {
> >> +display = dev->driver->initial_client_display(dev, width,
> >> height);
> >> +if (display) {
> >> +drm_client_display_free(fb_helper->display);
> >> +fb_helper->display = display;
> >> +mutex_unlock(&dev->mode_config.mutex);
> >> +return;
> >> +}
> >> +}
> >> +
> >> crtcs = kcalloc(fb_helper->connector_count,
> >> sizeof(struct drm_fb_helper_crtc *), GFP_KERNEL);
> >> modes = kcalloc(fb_helper->connector_count,
> >> @@ -2120,9 +2134,6 @@ static void drm_setup_crtcs(struct drm_fb_helper
> >> *fb_helper,
> >> if (IS_ERR(display))
> >> goto out;
> >>
> >> -mutex_lock(&fb_helper->dev->mode_config.mutex);
> >> -if (drm_fb_helper_probe_connector_modes(fb_helper, width, height) ==
> >> 0)
> >> -DRM_DEBUG_KMS("No connectors repo
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Prioritise non-busywait semaphore workloads
Quoting Tvrtko Ursulin (2019-03-01 11:48:25)
>
> On 01/03/2019 11:05, Chris Wilson wrote:
> > @@ -69,6 +70,10 @@ bool __i915_sched_node_add_dependency(struct
> > i915_sched_node *node,
> > dep->signaler = signal;
> > dep->flags = flags;
> >
> > + /* Keep track of whether anyone on this chain has a semaphore
> > */
> > + if (signal->semaphore && !node_started(signal))
> > + node->semaphore |= signal->semaphore << 1;
>
> Maybe I am confused.. this moves the bit flag to the left. Can't it fall
> off the end and we end up with zero after a deep enough chain?
Yup. I was working on the likelihood of that happening being small
enough to below the level of care :)
The semaphore being 64 requests ago and still not retired? That's like
igt levels of stress :)
Hmm, at one point I was using the history to determine whether this
request itself had a semaphore, but that's gone. So we can just use
if (signal->semaphore && !node_started(signal))
node->semaphore |= signal->semaphore;
> > @@ -74,6 +75,8 @@ struct i915_sched_node {
> > struct list_head waiters_list; /* those after us, they depend upon us
> > */
> > struct list_head link;
> > struct i915_sched_attr attr;
> > + unsigned long semaphore;
> > +#define I915_SCHED_HAS_SEMAPHORE BIT(0)
>
> unsigned int?
Everything is/will-be aligned to a pointer, and this gave us a deeper
chain :)
However, the chain is moot, so unsigned int is fine. And we can call it
flags if we aren't keeping the chain.
-Chris
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Check that whitelisted registers are accessible (rev4)
== Series Details == Series: drm/i915/selftests: Check that whitelisted registers are accessible (rev4) URL : https://patchwork.freedesktop.org/series/57342/ State : success == Summary == CI Bug Log - changes from CI_DRM_5675_full -> Patchwork_12337_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12337_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-semaphore-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109275] +3 * igt@gem_busy@extended-semaphore-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109275] / [fdo#109276] +1 * igt@gem_ctx_isolation@rcs0-s3: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +22 * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109281] +5 * igt@gem_ctx_param@invalid-param-get: - shard-skl: NOTRUN -> FAIL [fdo#109559] - shard-iclb: NOTRUN -> FAIL [fdo#109559] * igt@gem_ctx_param@invalid-param-set: - shard-iclb: NOTRUN -> FAIL [fdo#109674] * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] +3 * igt@gem_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +22 * igt@gem_exec_schedule@preempt-other-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +117 * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> SKIP [fdo#109292] +1 * igt@gem_mocs_settings@mocs-reset-ctx-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +17 * igt@gem_mocs_settings@mocs-settings-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +5 * igt@gem_pwrite@huge-gtt-backwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +10 * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109312] +1 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +14 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_backlight@fade_with_suspend: - shard-iclb: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_lpsp@non-edp: - shard-iclb: NOTRUN -> SKIP [fdo#109301] +3 * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-kbl: PASS -> SKIP [fdo#109271] * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] +4 * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-iclb: NOTRUN -> SKIP [fdo#109293] * igt@i915_pm_rpm@pm-tiling: - shard-iclb: NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#108840] * igt@i915_pm_rps@min-max-config-loaded: - shard-iclb: NOTRUN -> FAIL [fdo#102250] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] +1 * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> SKIP [fdo#109303] * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> SKIP [fdo#109302] * igt@i915_selftest@live_contexts: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_atomic_transition@3x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_available_modes_crc@available_mode_test_crc: - shard-iclb: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +7 * igt@kms_busy@extended-modeset-hang-newfb-render-b: - shard-hsw: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +53 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-e: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +7 * igt@kms_ccs@pipe-a-crc-primary-rotation-180: - shard-iclb: NOTRUN -> FAIL [fdo#107725] +8 * igt@kms_chamelium@dp-frame-dump: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +45 * igt@kms_chv_cursor_fail@pipe-c-64x64-right-edge: - shard-skl: NOTRUN -> FAIL [fdo#104671] * igt@kms_color@pipe-b-gamma: - shard-iclb: NOTRUN -> FAIL [fdo#104782] +7 * igt@kms_color@pipe-c-ctm-max: - shard-iclb: NOTRUN ->
[Intel-gfx] [PATCH v2] drm/i915: Prioritise non-busywait semaphore workloads
We don't want to busywait on the GPU if we have other work to do. If we
give non-busywaiting workloads higher (initial) priority than workloads
that require a busywait, we will prioritise work that is ready to run
immediately. We then also have to be careful that we don't give earlier
semaphores an accidental boost because later work doesn't wait on other
rings, hence we keep a history of semaphore usage of the dependency chain.
v2: Stop rolling the bits into a chain and just use a flag in case this
request or any of our dependencies use a semaphore. The rolling around
was contagious as Tvrtko was heard to fall off his chair.
Testcase: igt/gem_exec_schedule/semaphore
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 16
drivers/gpu/drm/i915/i915_scheduler.c | 6 ++
drivers/gpu/drm/i915/i915_scheduler.h | 9 ++---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
4 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 59e30b8c4ee9..bcf3c1a155e2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -813,6 +813,7 @@ emit_semaphore_wait(struct i915_request *to,
*cs++ = 0;
intel_ring_advance(to, cs);
+ to->sched.flags |= I915_SCHED_HAS_SEMAPHORE;
return 0;
}
@@ -1083,6 +1084,21 @@ void i915_request_add(struct i915_request *request)
if (engine->schedule) {
struct i915_sched_attr attr = request->gem_context->sched;
+ /*
+* Boost actual workloads past semaphores!
+*
+* With semaphores we spin on one engine waiting for another,
+* simply to reduce the latency of starting our work when
+* the signaler completes. However, if there is any other
+* work that we could be doing on this engine instead, that
+* is better utilisation and will reduce the overall duration
+* of the current work. To avoid PI boosting a semaphore
+* far in the distance past over useful work, we keep a history
+* of any semaphore use along our dependency chain.
+*/
+ if (!(request->sched.flags & I915_SCHED_HAS_SEMAPHORE))
+ attr.priority |= I915_PRIORITY_NOSEMAPHORE;
+
/*
* Boost priorities to new clients (new request flows).
*
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 50018ad30233..8a64748a7912 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -39,6 +39,7 @@ void i915_sched_node_init(struct i915_sched_node *node)
INIT_LIST_HEAD(&node->waiters_list);
INIT_LIST_HEAD(&node->link);
node->attr.priority = I915_PRIORITY_INVALID;
+ node->flags = 0;
}
static struct i915_dependency *
@@ -69,6 +70,11 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node
*node,
dep->signaler = signal;
dep->flags = flags;
+ /* Keep track of whether anyone on this chain has a semaphore */
+ if (signal->flags & I915_SCHED_HAS_SEMAPHORE &&
+ !node_started(signal))
+ node->flags |= I915_SCHED_HAS_SEMAPHORE;
+
ret = true;
}
diff --git a/drivers/gpu/drm/i915/i915_scheduler.h
b/drivers/gpu/drm/i915/i915_scheduler.h
index 7d4a49750d92..6ce450cf63fa 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.h
+++ b/drivers/gpu/drm/i915/i915_scheduler.h
@@ -24,14 +24,15 @@ enum {
I915_PRIORITY_INVALID = INT_MIN
};
-#define I915_USER_PRIORITY_SHIFT 2
+#define I915_USER_PRIORITY_SHIFT 3
#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT)
#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1)
-#define I915_PRIORITY_WAIT ((u8)BIT(0))
-#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_WAIT ((u8)BIT(0))
+#define I915_PRIORITY_NEWCLIENT((u8)BIT(1))
+#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2))
#define __NO_PREEMPTION (I915_PRIORITY_WAIT)
@@ -74,6 +75,8 @@ struct i915_sched_node {
struct list_head waiters_list; /* those after us, they depend upon us */
struct list_head link;
struct i915_sched_attr attr;
+ unsigned int flags;
+#define I915_SCHED_HAS_SEMAPHORE BIT(0)
};
struct i915_dependency {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 53d6f7fdb50e..2268860cca44 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -164,7 +164,7 @@
#define WA_TAIL_DWORDS 2
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
-#define ACTIVE_PRIORIT
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2)
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2) URL : https://patchwork.freedesktop.org/series/57400/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/execlists: Suppress redundant preemption Okay! Commit: drm/i915: Introduce i915_timeline.mutex Okay! Commit: drm/i915: Keep timeline HWSP allocated until idle across the system Okay! Commit: drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ -O:drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/i915_drv.c:351:25: warning: expression using sizeof(void) Commit: drm/i915: Prioritise non-busywait semaphore workloads Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2)
== Series Details == Series: series starting with [1/5] drm/i915/execlists: Suppress redundant preemption (rev2) URL : https://patchwork.freedesktop.org/series/57400/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676 -> Patchwork_12341 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57400/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_12341 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 Participating hosts (44 -> 41) -- Additional (2): fi-icl-u2 fi-pnv-d510 Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper Build changes - * Linux: CI_DRM_5676 -> Patchwork_12341 CI_DRM_5676: 3911a5d7d3de6d8e491868bb0cd506346131d71b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12341: 0782c9f2934088efdfd8195aca62b93f8c7f8a66 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0782c9f29340 drm/i915: Prioritise non-busywait semaphore workloads 857513cd949f drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ ddb6b2f74eaa drm/i915: Keep timeline HWSP allocated until idle across the system afeaf0b7bd09 drm/i915: Introduce i915_timeline.mutex 4563df2aa310 drm/i915/execlists: Suppress redundant preemption == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12341/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/17] drm/imx: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert imx to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Philipp Zabel
---
drivers/gpu/drm/imx/ipuv3-crtc.c | 30 ++
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index ec3602ebbc1c..54a32c6f2407 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -101,26 +101,6 @@ static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
drm_crtc_vblank_off(crtc);
}
-static void imx_drm_crtc_reset(struct drm_crtc *crtc)
-{
- struct imx_crtc_state *state;
-
- if (crtc->state) {
- if (crtc->state->mode_blob)
- drm_property_blob_put(crtc->state->mode_blob);
-
- state = to_imx_crtc_state(crtc->state);
- memset(state, 0, sizeof(*state));
- } else {
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return;
- crtc->state = &state->base;
- }
-
- state->base.crtc = crtc;
-}
-
static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc
*crtc)
{
struct imx_crtc_state *state;
@@ -144,6 +124,16 @@ static void imx_drm_crtc_destroy_state(struct drm_crtc
*crtc,
kfree(to_imx_crtc_state(state));
}
+static void imx_drm_crtc_reset(struct drm_crtc *crtc)
+{
+ struct imx_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
+
+ if (crtc->state)
+ imx_drm_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
static int ipu_enable_vblank(struct drm_crtc *crtc)
{
struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
--
2.20.1
___
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[Intel-gfx] [PATCH 11/17] drm/omap: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert omap to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c
b/drivers/gpu/drm/omapdrm/omap_crtc.c
index d99e24dcc0bf..2546002b1c5c 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -549,14 +549,13 @@ static int omap_crtc_atomic_get_property(struct drm_crtc
*crtc,
static void omap_crtc_reset(struct drm_crtc *crtc)
{
- if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- kfree(crtc->state);
- crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
+ struct omap_crtc_state *crtc_state =
+ kzalloc(sizeof(*crtc_state), GFP_KERNEL);
if (crtc->state)
- crtc->state->crtc = crtc;
+ drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
}
static struct drm_crtc_state *
--
2.20.1
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[Intel-gfx] [PATCH 04/17] drm/amd: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert amd to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version.
Signed-off-by: Maarten Lankhorst
Cc: Harry Wentland
Cc: Leo Li
Cc: Alex Deucher
Cc: "Christian König"
Cc: "David (ChunMing) Zhou"
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0642dfe22582..975ed22e39d2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3072,18 +3072,12 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc,
static void dm_crtc_reset_state(struct drm_crtc *crtc)
{
- struct dm_crtc_state *state;
+ struct dm_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
if (crtc->state)
dm_crtc_destroy_state(crtc, crtc->state);
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (WARN_ON(!state))
- return;
-
- crtc->state = &state->base;
- crtc->state->crtc = crtc;
-
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
}
static struct drm_crtc_state *
--
2.20.1
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[Intel-gfx] [PATCH 07/17] drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper.
i915 has its own hw readout and doesn't use the reset helpers directly.
Still it has 2 places where it initialises the crtc_state. Fix those
by calling __drm_atomic_helper_crtc_reset().
Signed-off-by: Maarten Lankhorst
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7c5e84ef5171..2e14a50dbf6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14447,9 +14447,8 @@ static int intel_crtc_init(struct drm_i915_private
*dev_priv, enum pipe pipe)
ret = -ENOMEM;
goto fail;
}
+ __drm_atomic_helper_crtc_reset(&intel_crtc->base, &crtc_state->base);
intel_crtc->config = crtc_state;
- intel_crtc->base.state = &crtc_state->base;
- crtc_state->base.crtc = &intel_crtc->base;
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -15986,7 +15985,7 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
__drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
memset(crtc_state, 0, sizeof(*crtc_state));
- crtc_state->base.crtc = &crtc->base;
+ __drm_atomic_helper_crtc_reset(&crtc->base, &crtc_state->base);
crtc_state->base.active = crtc_state->base.enable =
dev_priv->display.get_pipe_config(crtc, crtc_state);
--
2.20.1
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[Intel-gfx] [PATCH 02/17] drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state.
We already have __drm_atomic_helper_connector_reset() and
__drm_atomic_helper_plane_reset(), extend this to crtc as well.
This will allow us to set default values in the crtc_state, without
having to do it in each driver separately.
Of all drivers that need conversion, only nouveau is done in this
commit, because it wrote its own __drm_atomic_helper_crtc_reset(),
clashing with the drm core.
Signed-off-by: Maarten Lankhorst
Cc: Ben Skeggs
---
drivers/gpu/drm/drm_atomic_state_helper.c | 34 +++
drivers/gpu/drm/nouveau/dispnv50/head.c | 13 ++---
include/drm/drm_atomic_state_helper.h | 2 ++
3 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c
b/drivers/gpu/drm/drm_atomic_state_helper.c
index 4985384e51f6..bc5ee66f75b3 100644
--- a/drivers/gpu/drm/drm_atomic_state_helper.c
+++ b/drivers/gpu/drm/drm_atomic_state_helper.c
@@ -55,6 +55,29 @@
* for these functions.
*/
+/**
+ * __drm_atomic_helper_crtc_reset - reset state on CRTC
+ * @crtc: drm CRTC
+ * @crtc_state: CRTC state to assign
+ *
+ * Initializes the newly allocated @crtc_state and assigns it to
+ * the &drm_crtc->state pointer of @crtc, usually required when
+ * initializing the drivers or when called from the &drm_crtc_funcs.reset
+ * hook.
+ *
+ * This is useful for drivers that subclass the CRTC state.
+ */
+void
+__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ if (crtc_state)
+ crtc_state->crtc = crtc;
+
+ crtc->state = crtc_state;
+}
+EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset);
+
/**
* drm_atomic_helper_crtc_reset - default &drm_crtc_funcs.reset hook for CRTCs
* @crtc: drm CRTC
@@ -64,14 +87,13 @@
*/
void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc)
{
- if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- kfree(crtc->state);
- crtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL);
+ struct drm_crtc_state *crtc_state =
+ kzalloc(sizeof(*crtc->state), GFP_KERNEL);
if (crtc->state)
- crtc->state->crtc = crtc;
+ crtc->funcs->atomic_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, crtc_state);
}
EXPORT_SYMBOL(drm_atomic_helper_crtc_reset);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c
b/drivers/gpu/drm/nouveau/dispnv50/head.c
index 2e7a0c347ddb..93754743090f 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c
@@ -419,16 +419,6 @@ nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
return &asyh->state;
}
-static void
-__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
- struct drm_crtc_state *state)
-{
- if (crtc->state)
- crtc->funcs->atomic_destroy_state(crtc, crtc->state);
- crtc->state = state;
- crtc->state->crtc = crtc;
-}
-
static void
nv50_head_reset(struct drm_crtc *crtc)
{
@@ -437,6 +427,9 @@ nv50_head_reset(struct drm_crtc *crtc)
if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL
return;
+ if (crtc->state)
+ nv50_head_atomic_destroy_state(crtc, crtc->state);
+
__drm_atomic_helper_crtc_reset(crtc, &asyh->state);
}
diff --git a/include/drm/drm_atomic_state_helper.h
b/include/drm/drm_atomic_state_helper.h
index 66c92cbd8e16..4e6d2e7a40b8 100644
--- a/include/drm/drm_atomic_state_helper.h
+++ b/include/drm/drm_atomic_state_helper.h
@@ -37,6 +37,8 @@ struct drm_private_state;
struct drm_modeset_acquire_ctx;
struct drm_device;
+void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
+ struct drm_crtc_state *state);
void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc);
void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
--
2.20.1
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[Intel-gfx] [PATCH 03/17] drm/docs: Fix typo in __drm_atomic_helper_connector_reset
Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/drm_atomic_state_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index bc5ee66f75b3..172c8c698a46 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -335,7 +335,7 @@ EXPORT_SYMBOL(drm_atomic_helper_plane_destroy_state); * @conn_state: connector state to assign * * Initializes the newly allocated @conn_state and assigns it to - * the &drm_conector->state pointer of @connector, usually required when + * the &drm_connector->state pointer of @connector, usually required when * initializing the drivers or when called from the &drm_connector_funcs.reset * hook. * -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/17] drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert msm to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Rob Clark
Cc: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 28 +--
2 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index b776fca571f3..eb156cb73dd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -753,14 +753,12 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool
async)
static void dpu_crtc_reset(struct drm_crtc *crtc)
{
- struct dpu_crtc_state *cstate;
+ struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (crtc->state)
dpu_crtc_destroy_state(crtc, crtc->state);
- crtc->state = kzalloc(sizeof(*cstate), GFP_KERNEL);
- if (crtc->state)
- crtc->state->crtc = crtc;
+ __drm_atomic_helper_crtc_reset(crtc, &cstate->base);
}
/**
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index b0cf63c4e3d7..bf24a08feab9 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1002,23 +1002,6 @@ mdp5_crtc_atomic_print_state(struct drm_printer *p,
drm_printf(p, "\tcmd_mode=%d\n", mdp5_cstate->cmd_mode);
}
-static void mdp5_crtc_reset(struct drm_crtc *crtc)
-{
- struct mdp5_crtc_state *mdp5_cstate;
-
- if (crtc->state) {
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
- kfree(to_mdp5_crtc_state(crtc->state));
- }
-
- mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
-
- if (mdp5_cstate) {
- mdp5_cstate->base.crtc = crtc;
- crtc->state = &mdp5_cstate->base;
- }
-}
-
static struct drm_crtc_state *
mdp5_crtc_duplicate_state(struct drm_crtc *crtc)
{
@@ -1046,6 +1029,17 @@ static void mdp5_crtc_destroy_state(struct drm_crtc
*crtc, struct drm_crtc_state
kfree(mdp5_cstate);
}
+static void mdp5_crtc_reset(struct drm_crtc *crtc)
+{
+ struct mdp5_crtc_state *mdp5_cstate =
+ mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL);
+
+ if (crtc->state)
+ mdp5_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base);
+}
+
static const struct drm_crtc_funcs mdp5_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy = mdp5_crtc_destroy,
--
2.20.1
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[Intel-gfx] [PATCH 15/17] drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert vc4 to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(),
call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_crtc.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index e7c04a9eb219..fdf21594b050 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -1041,12 +1041,13 @@ static void vc4_crtc_destroy_state(struct drm_crtc
*crtc,
static void
vc4_crtc_reset(struct drm_crtc *crtc)
{
- if (crtc->state)
- vc4_crtc_destroy_state(crtc->state);
+ struct vc4_crtc_state *crtc_state =
+ kzalloc(sizeof(*crtc_state), GFP_KERNEL);
- crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
if (crtc->state)
- crtc->state->crtc = crtc;
+ vc4_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
}
static const struct drm_crtc_funcs vc4_crtc_funcs = {
--
2.20.1
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[Intel-gfx] [PATCH 06/17] drm/atmel-hlcdc: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert atmel-hlcdc to using __drm_atomic_helper_crtc_reset(), instead
of writing its own version. Instead of open coding destroy_state(),
call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Boris Brezillon
---
.../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 29 +++
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 8070a558d7b1..816161d0a09d 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -400,24 +400,6 @@ void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
}
-static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
-{
- struct atmel_hlcdc_crtc_state *state;
-
- if (crtc->state) {
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
- state = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state);
- kfree(state);
- crtc->state = NULL;
- }
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (state) {
- crtc->state = &state->base;
- crtc->state->crtc = crtc;
- }
-}
-
static struct drm_crtc_state *
atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc)
{
@@ -447,6 +429,17 @@ static void atmel_hlcdc_crtc_destroy_state(struct drm_crtc
*crtc,
kfree(state);
}
+static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc)
+{
+ struct atmel_hlcdc_crtc_state *state =
+ kzalloc(sizeof(*state), GFP_KERNEL);
+
+ if (crtc->state)
+ atmel_hlcdc_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
static int atmel_hlcdc_crtc_enable_vblank(struct drm_crtc *c)
{
struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
--
2.20.1
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[Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(), call
it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Laurent Pinchart
Cc: Kieran Bingham
Cc: linux-renesas-...@vger.kernel.org
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 4cdea14d552f..7766551e67fc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
static void rcar_du_crtc_reset(struct drm_crtc *crtc)
{
- struct rcar_du_crtc_state *state;
+ struct rcar_du_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (crtc->state) {
+ if (crtc->state)
rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
- crtc->state = NULL;
- }
- state = kzalloc(sizeof(*state), GFP_KERNEL);
+ __drm_atomic_helper_crtc_reset(crtc, &state->state);
if (state == NULL)
return;
state->crc.source = VSP1_DU_CRC_NONE;
state->crc.index = 0;
-
- crtc->state = &state->state;
- crtc->state->crtc = crtc;
}
static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
--
2.20.1
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[Intel-gfx] [PATCH 09/17] drm/mediatek: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert mediatek to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: CK Hu
Cc: Philipp Zabel
Cc: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 29 +
1 file changed, 10 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index acad088173da..3b18bbadd415 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -108,25 +108,6 @@ static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
-static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
-{
- struct mtk_crtc_state *state;
-
- if (crtc->state) {
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- state = to_mtk_crtc_state(crtc->state);
- memset(state, 0, sizeof(*state));
- } else {
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return;
- crtc->state = &state->base;
- }
-
- state->base.crtc = crtc;
-}
-
static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc
*crtc)
{
struct mtk_crtc_state *state;
@@ -150,6 +131,16 @@ static void mtk_drm_crtc_destroy_state(struct drm_crtc
*crtc,
kfree(to_mtk_crtc_state(state));
}
+static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
+{
+ struct mtk_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
+
+ if (crtc->state)
+ mtk_drm_crtc_destroy_state(crtc, &state->base);
+
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
--
2.20.1
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[Intel-gfx] [PATCH 01/17] drm/vc4: Fix memory leak during gpu reset.
__drm_atomic_helper_crtc_destroy_state does not free memory, it only
cleans it up. Fix this by calling the functions own destroy function.
Fixes: 6d6e50039187 ("drm/vc4: Allocate the right amount of space for boot-time
CRTC state.")
Cc: Eric Anholt
Cc: # v4.6+
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 730008d3da76..e7c04a9eb219 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -1042,7 +1042,7 @@ static void
vc4_crtc_reset(struct drm_crtc *crtc)
{
if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
+ vc4_crtc_destroy_state(crtc->state);
crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
if (crtc->state)
--
2.20.1
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[Intel-gfx] [PATCH 14/17] drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert tegra to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(),
call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: linux-te...@vger.kernel.org
---
drivers/gpu/drm/tegra/dc.c | 30 +++---
1 file changed, 11 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 607a6ea17ecc..57c88d78cdaa 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -1153,25 +1153,6 @@ static void tegra_dc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
-static void tegra_crtc_reset(struct drm_crtc *crtc)
-{
- struct tegra_dc_state *state;
-
- if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- kfree(crtc->state);
- crtc->state = NULL;
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (state) {
- crtc->state = &state->base;
- crtc->state->crtc = crtc;
- }
-
- drm_crtc_vblank_reset(crtc);
-}
-
static struct drm_crtc_state *
tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
{
@@ -1198,6 +1179,17 @@ static void tegra_crtc_atomic_destroy_state(struct
drm_crtc *crtc,
kfree(state);
}
+static void tegra_crtc_reset(struct drm_crtc *crtc)
+{
+ struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
+
+ if (crtc->state)
+ tegra_crtc_atomic_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+ drm_crtc_vblank_reset(crtc);
+}
+
#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
static const struct debugfs_reg32 tegra_dc_regs[] = {
--
2.20.1
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[Intel-gfx] [PATCH 16/17] drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert vkms to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(),
call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Rodrigo Siqueira
Cc: Haneen Mohammed
Cc: Daniel Vetter
---
drivers/gpu/drm/vkms/vkms_crtc.c | 33 +---
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c
index 8a9aeb0a9ea8..550888e72c96 100644
--- a/drivers/gpu/drm/vkms/vkms_crtc.c
+++ b/drivers/gpu/drm/vkms/vkms_crtc.c
@@ -83,26 +83,6 @@ bool vkms_get_vblank_timestamp(struct drm_device *dev,
unsigned int pipe,
return true;
}
-static void vkms_atomic_crtc_reset(struct drm_crtc *crtc)
-{
- struct vkms_crtc_state *vkms_state = NULL;
-
- if (crtc->state) {
- vkms_state = to_vkms_crtc_state(crtc->state);
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
- kfree(vkms_state);
- crtc->state = NULL;
- }
-
- vkms_state = kzalloc(sizeof(*vkms_state), GFP_KERNEL);
- if (!vkms_state)
- return;
- INIT_WORK(&vkms_state->crc_work, vkms_crc_work_handle);
-
- crtc->state = &vkms_state->base;
- crtc->state->crtc = crtc;
-}
-
static struct drm_crtc_state *
vkms_atomic_crtc_duplicate_state(struct drm_crtc *crtc)
{
@@ -135,6 +115,19 @@ static void vkms_atomic_crtc_destroy_state(struct drm_crtc
*crtc,
}
}
+static void vkms_atomic_crtc_reset(struct drm_crtc *crtc)
+{
+ struct vkms_crtc_state *vkms_state =
+ kzalloc(sizeof(*vkms_state), GFP_KERNEL);
+
+ if (crtc->state)
+ vkms_atomic_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &vkms_state->base);
+ if (vkms_state)
+ INIT_WORK(&vkms_state->crc_work, vkms_crc_work_handle);
+}
+
static const struct drm_crtc_funcs vkms_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.destroy= drm_crtc_cleanup,
--
2.20.1
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[Intel-gfx] [PATCH 00/17] drm: Start subclassing crtc_state.
When we want to start adding default values to crtc_state, it makes sense fix all drivers to call __drm_atomic_helper_crtc_reset, like we do for connectors and planes. Maarten Lankhorst (17): drm/vc4: Fix memory leak during gpu reset. drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. drm/docs: Fix typo in __drm_atomic_helper_connector_reset drm/amd: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/atmel-hlcdc: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper. drm/imx: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/mediatek: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/omap: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset. drm/vmwgfx: Convert to using __drm_atomic_helper_crtc_reset() for reset. .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++ drivers/gpu/drm/arm/malidp_crtc.c | 28 ++- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c| 29 ++- drivers/gpu/drm/drm_atomic_state_helper.c | 36 +++ drivers/gpu/drm/i915/intel_display.c | 5 ++- drivers/gpu/drm/imx/ipuv3-crtc.c | 30 ++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 29 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 ++-- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 28 ++- drivers/gpu/drm/nouveau/dispnv50/head.c | 13 ++- drivers/gpu/drm/omapdrm/omap_crtc.c | 11 +++--- drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 11 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 22 ++-- drivers/gpu/drm/tegra/dc.c| 30 ++-- drivers/gpu/drm/vc4/vc4_crtc.c| 9 ++--- drivers/gpu/drm/vkms/vkms_crtc.c | 33 +++-- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 20 +++ include/drm/drm_atomic_state_helper.h | 2 ++ 18 files changed, 145 insertions(+), 207 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/17] drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert mali to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
malidp_crtc_destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Liviu Dudau
Cc: Brian Starkey
---
drivers/gpu/drm/arm/malidp_crtc.c | 28 +++-
1 file changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
b/drivers/gpu/drm/arm/malidp_crtc.c
index 56aad288666e..d6690e016f0b 100644
--- a/drivers/gpu/drm/arm/malidp_crtc.c
+++ b/drivers/gpu/drm/arm/malidp_crtc.c
@@ -463,23 +463,6 @@ static struct drm_crtc_state
*malidp_crtc_duplicate_state(struct drm_crtc *crtc)
return &state->base;
}
-static void malidp_crtc_reset(struct drm_crtc *crtc)
-{
- struct malidp_crtc_state *state = NULL;
-
- if (crtc->state) {
- state = to_malidp_crtc_state(crtc->state);
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
- }
-
- kfree(state);
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (state) {
- crtc->state = &state->base;
- crtc->state->crtc = crtc;
- }
-}
-
static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
@@ -493,6 +476,17 @@ static void malidp_crtc_destroy_state(struct drm_crtc
*crtc,
kfree(mali_state);
}
+static void malidp_crtc_reset(struct drm_crtc *crtc)
+{
+ struct malidp_crtc_state *state =
+ kzalloc(sizeof(*state), GFP_KERNEL);
+
+ if (crtc->state)
+ malidp_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
--
2.20.1
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[Intel-gfx] [PATCH 13/17] drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert rockchip to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding
destroy_state(), call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: linux-rockc...@lists.infradead.org
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 22 ++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c7d4c6073ea5..1cf1658f1c01 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1201,17 +1201,6 @@ static void vop_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
-static void vop_crtc_reset(struct drm_crtc *crtc)
-{
- if (crtc->state)
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
- kfree(crtc->state);
-
- crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
- if (crtc->state)
- crtc->state->crtc = crtc;
-}
-
static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *rockchip_state;
@@ -1233,6 +1222,17 @@ static void vop_crtc_destroy_state(struct drm_crtc *crtc,
kfree(s);
}
+static void vop_crtc_reset(struct drm_crtc *crtc)
+{
+ struct rockchip_crtc_state *crtc_state =
+ kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+
+ if (crtc->state)
+ vop_crtc_destroy_state(crtc, crtc->state);
+
+ __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
+}
+
#ifdef CONFIG_DRM_ANALOGIX_DP
static struct drm_connector *vop_get_edp_connector(struct vop *vop)
{
--
2.20.1
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[Intel-gfx] [PATCH 17/17] drm/vmwgfx: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Convert vmwgfx to using __drm_atomic_helper_crtc_reset(), instead of
writing its own version. Instead of open coding destroy_state(),
call it directly for freeing the old state.
Signed-off-by: Maarten Lankhorst
Cc: Thomas Hellstrom
---
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index ed2f67822f45..602f549f09f6 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -611,24 +611,12 @@ vmw_du_crtc_duplicate_state(struct drm_crtc *crtc)
*/
void vmw_du_crtc_reset(struct drm_crtc *crtc)
{
- struct vmw_crtc_state *vcs;
-
-
- if (crtc->state) {
- __drm_atomic_helper_crtc_destroy_state(crtc->state);
-
- kfree(vmw_crtc_state_to_vcs(crtc->state));
- }
+ struct vmw_crtc_state *vcs = kzalloc(sizeof(*vcs), GFP_KERNEL);
- vcs = kzalloc(sizeof(*vcs), GFP_KERNEL);
-
- if (!vcs) {
- DRM_ERROR("Cannot allocate vmw_crtc_state\n");
- return;
- }
+ if (crtc->state)
+ vmw_du_crtc_destroy_state(crtc, crtc->state);
- crtc->state = &vcs->base;
- crtc->state->crtc = crtc;
+ __drm_atomic_helper_crtc_reset(crtc, &vcs->base);
}
--
2.20.1
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm & vgaarb: handle vgacon removal in vgaarb. (rev3)
== Series Details == Series: drm & vgaarb: handle vgacon removal in vgaarb. (rev3) URL : https://patchwork.freedesktop.org/series/57086/ State : success == Summary == CI Bug Log - changes from CI_DRM_5675_full -> Patchwork_12338_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12338_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_busy@extended-semaphore-blt: - shard-iclb: NOTRUN -> SKIP [fdo#109275] +3 * igt@gem_busy@extended-semaphore-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109275] / [fdo#109276] +1 * igt@gem_ctx_isolation@bcs0-s3: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +23 * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109281] +5 * igt@gem_ctx_isolation@vcs1-s3: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] * igt@gem_ctx_param@invalid-param-get: - shard-skl: NOTRUN -> FAIL [fdo#109559] - shard-iclb: NOTRUN -> FAIL [fdo#109559] * igt@gem_ctx_param@invalid-param-set: - shard-iclb: NOTRUN -> FAIL [fdo#109674] * igt@gem_ctx_param@set-priority-not-supported: - shard-iclb: NOTRUN -> SKIP [fdo#109314] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] +3 * igt@gem_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +22 * igt@gem_exec_schedule@preempt-other-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +130 * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> SKIP [fdo#109292] +1 * igt@gem_mocs_settings@mocs-reset-ctx-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +17 * igt@gem_mocs_settings@mocs-settings-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +5 * igt@gem_pwrite@huge-gtt-backwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +10 * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109312] +1 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +16 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_backlight@fade_with_suspend: - shard-iclb: NOTRUN -> FAIL [fdo#107847] * igt@i915_pm_lpsp@non-edp: - shard-iclb: NOTRUN -> SKIP [fdo#109301] +2 * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] +4 * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@gem-mmap-cpu: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-iclb: NOTRUN -> SKIP [fdo#109293] +1 * igt@i915_pm_rpm@modeset-stress-extra-wait: - shard-iclb: NOTRUN -> INCOMPLETE [fdo#108840] * igt@i915_pm_rpm@universal-planes: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#108654] * igt@i915_pm_rps@min-max-config-loaded: - shard-iclb: NOTRUN -> FAIL [fdo#102250] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#108344] * igt@i915_pm_rps@waitboost: - shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> SKIP [fdo#109303] * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> SKIP [fdo#109302] * igt@i915_selftest@live_contexts: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@i915_suspend@fence-restore-tiled2untiled: - shard-snb: PASS -> INCOMPLETE [fdo#105411] * igt@kms_atomic_transition@3x-modeset-transitions-nonblocking: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_available_modes_crc@available_mode_test_crc: - shard-iclb: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-newfb-render-a: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +8 * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +52 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_busy@extended-modeset-hang-oldfb-render-e: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_ccs@pipe-a-crc-primary-rotation-180: - shard-iclb: NOTRUN -> FAIL [fdo#107725] +8 * igt@kms_chamelium@dp-frame-dump: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +46 * igt@kms_colo
Re: [Intel-gfx] [PATCH xf86-video-intel 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property
Quoting Ville Syrjala (2019-02-18 19:50:52) > From: Ville Syrjälä > > Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when > the running with > 8bpc. > > Cc: Mario Kleiner > Signed-off-by: Ville Syrjälä Looks fine to me, so I'll push unless any one objects. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 12/17] drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Hi Maarten,
Thank you for the patch.
On Fri, Mar 01, 2019 at 01:56:22PM +0100, Maarten Lankhorst wrote:
> Convert rcar-du to using __drm_atomic_helper_crtc_reset(), instead of
> writing its own version. Instead of open coding destroy_state(), call
> it directly for freeing the old state.
I don't think the second sentence applies to this patch.
> Signed-off-by: Maarten Lankhorst
> Cc: Laurent Pinchart
> Cc: Kieran Bingham
> Cc: linux-renesas-...@vger.kernel.org
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 4cdea14d552f..7766551e67fc 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -891,22 +891,17 @@ static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
>
> static void rcar_du_crtc_reset(struct drm_crtc *crtc)
> {
> - struct rcar_du_crtc_state *state;
> + struct rcar_du_crtc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
>
> - if (crtc->state) {
> + if (crtc->state)
> rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
> - crtc->state = NULL;
> - }
>
> - state = kzalloc(sizeof(*state), GFP_KERNEL);
> + __drm_atomic_helper_crtc_reset(crtc, &state->state);
state may be NULL here if the above kzalloc() failed. Let's keep the
original order of the function, and simply call
__drm_atomic_helper_crtc_reset() after the NULL check below.
> if (state == NULL)
> return;
>
> state->crc.source = VSP1_DU_CRC_NONE;
> state->crc.index = 0;
> -
> - crtc->state = &state->state;
> - crtc->state->crtc = crtc;
> }
>
> static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
--
Regards,
Laurent Pinchart
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Start subclassing crtc_state.
== Series Details == Series: drm: Start subclassing crtc_state. URL : https://patchwork.freedesktop.org/series/57425/ State : warning == Summary == $ dim checkpatch origin/drm-tip 51d3cd4204fb drm/vc4: Fix memory leak during gpu reset. fdfc56a108d3 drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. 34f32bdeca76 drm/docs: Fix typo in __drm_atomic_helper_connector_reset -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 8 lines checked f8574e1d416a drm/amd: Convert to using __drm_atomic_helper_crtc_reset() for reset. c3ddc7689a67 drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset. 97817e87cd77 drm/atmel-hlcdc: Convert to using __drm_atomic_helper_crtc_reset() for reset. 9158964fdd37 drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper. c9bf362dac3b drm/imx: Convert to using __drm_atomic_helper_crtc_reset() for reset. 70cc75e4022f drm/mediatek: Convert to using __drm_atomic_helper_crtc_reset() for reset. 3a057b72363e drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset. d6083ed9c6f7 drm/omap: Convert to using __drm_atomic_helper_crtc_reset() for reset. 5412a63fabc8 drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset. 837ea0cf17aa drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset. 725895026dd3 drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset. df9f94b77ae9 drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset. 21dea2d6f4e3 drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset. 58ec786d5c8e drm/vmwgfx: Convert to using __drm_atomic_helper_crtc_reset() for reset. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Start subclassing crtc_state.
== Series Details == Series: drm: Start subclassing crtc_state. URL : https://patchwork.freedesktop.org/series/57425/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/vc4: Fix memory leak during gpu reset. Okay! Commit: drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. Okay! Commit: drm/docs: Fix typo in __drm_atomic_helper_connector_reset Okay! Commit: drm/amd: Convert to using __drm_atomic_helper_crtc_reset() for reset. -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3586:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4453:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4453:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4457:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4457:27: warning: expression using sizeof(void) -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4600:17: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:3580:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4447:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4447:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4451:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4451:27: warning: expression using sizeof(void) +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:4594:17: warning: Using plain integer as NULL pointer Commit: drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/atmel-hlcdc: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper. Okay! Commit: drm/imx: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/mediatek: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/omap: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! Commit: drm/vmwgfx: Convert to using __drm_atomic_helper_crtc_reset() for reset. Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/crc: Make IPS workaround generic
On Thu, Feb 28, 2019 at 11:26:57PM +, Souza, Jose wrote:
> On Thu, 2019-02-28 at 18:56 +0200, Ville Syrjälä wrote:
> > On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Roberto de Souza
> > wrote:
> > > Other features like PSR2 also needs to be disabled while getting
> > > CRC
> > > so lets rename ips_force_disable to crc_enabled, drop all this
> > > checks
> > > for pipe A and HSW and BDW and make it generic and
> > > hsw_compute_ips_config() will take care of all the checks removed
> > > from here.
> > >
> > > Cc: Dhinakaran Pandiyan
> > > Cc: Ville Syrjälä
> > > Signed-off-by: José Roberto de Souza
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 10 +--
> > > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > > drivers/gpu/drm/i915/intel_pipe_crc.c | 42 +
> > > --
> > > 3 files changed, 24 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 816e8f124b3b..328967c642b3 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6751,7 +6751,13 @@ static bool hsw_compute_ips_config(struct
> > > intel_crtc_state *crtc_state)
> > > if (!hsw_crtc_state_ips_capable(crtc_state))
> > > return false;
> > >
> > > - if (crtc_state->ips_force_disable)
> > > + /*
> > > + * When IPS gets enabled, the pipe CRC changes. Since IPS gets
> > > + * enabled and disabled dynamically based on package C states,
> > > + * user space can't make reliable use of the CRCs, so let's
> > > just
> > > + * completely disable it.
> > > + */
> > > + if (crtc_state->crc_enabled)
> > > return false;
> >
> > Hmm. I was wondering how we even manage to pass the state checker
> > with
> > the current code. But apparently we don't have state checking for
> > IPS.
> > I would suggest moving this into hsw_compute_ips_config() and then
> > adding the state checker (for HSW only though since BDW can't do the
> > readout).
> >
> > >
> > > /* IPS should be fine as long as at least one plane is enabled.
> > > */
> > > @@ -11684,7 +11690,7 @@ clear_intel_crtc_state(struct
> > > intel_crtc_state *crtc_state)
> > > saved_state->shared_dpll = crtc_state->shared_dpll;
> > > saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
> > > saved_state->pch_pfit.force_thru = crtc_state-
> > > >pch_pfit.force_thru;
> > > - saved_state->ips_force_disable = crtc_state->ips_force_disable;
> > > + saved_state->crc_enabled = crtc_state->crc_enabled;
> > > if (IS_G4X(dev_priv) ||
> > > IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > saved_state->wm = crtc_state->wm;
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 5412373e2f98..2be64529e4a2 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -999,7 +999,8 @@ struct intel_crtc_state {
> > > struct intel_link_m_n fdi_m_n;
> > >
> > > bool ips_enabled;
> > > - bool ips_force_disable;
> > > +
> > > + bool crc_enabled;
> > >
> > > bool enable_fbc;
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > index 53d4ec68d3c4..f6d0b2aaffe2 100644
> > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> > > @@ -280,11 +280,12 @@ static int ilk_pipe_crc_ctl_reg(enum
> > > intel_pipe_crc_source *source,
> > > return 0;
> > > }
> > >
> > > -static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
> > > - bool enable)
> > > +static void
> > > +intel_crtc_crc_prepare(struct drm_i915_private *dev_priv, struct
> > > drm_crtc *crtc,
> >
> > Just pass in the intel_crtc
>
> Okay
>
> >
> > > +bool enable)
> > > {
> > > struct drm_device *dev = &dev_priv->drm;
> > > - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> > > PIPE_A);
> > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >
> > and then we don't have to have an ugly name for this.
> >
> > Also pasing in dev_priv is redundant when you're already passing in
> > the
> > crtc.
> >
>
> okay
>
> > The function name isn't super descriptive. It makes me think we're
> > preparing for CRC capture, when in fact it just adds/removes the
> > w/as.
>
> What about: intel_crtc_crc_workarounds_setup()?
Or _setup_workarounds() so that it reads more naturally?
>
> >
> > > struct intel_crtc_state *pipe_config;
> > > struct drm_atomic_state *state;
> > > struct drm_modeset_acquire_ctx ctx;
> > > @@ -301,23 +302,15 @@ static void hsw_pipe_A_crc_wa(struct
> > > drm_i915_private *dev_priv,
> > > state->acquire_ctx = &ctx;
> > >
> > > retry:
> > > - pipe_config = intel_atomic_get_crtc_state(state, crtc);
> > > + pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
> > > if (IS_ERR(pipe_config)) {
> > > re
Re: [Intel-gfx] [PATCH 05/17] drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset.
Hi Maarten,
On Fri, Mar 01, 2019 at 01:56:15PM +0100, Maarten Lankhorst wrote:
> Convert mali to using __drm_atomic_helper_crtc_reset(), instead of
> writing its own version. Instead of open coding
> malidp_crtc_destroy_state(), call it directly for freeing the old state.
>
> Signed-off-by: Maarten Lankhorst
> Cc: Liviu Dudau
Acked-by: Liviu Dudau
If you need me to take this patch into malidp tree let me know,
otherwise I expect is going to show up in drm-misc-next at some moment.
Best regards,
Liviu
> Cc: Brian Starkey
> ---
> drivers/gpu/drm/arm/malidp_crtc.c | 28 +++-
> 1 file changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/arm/malidp_crtc.c
> b/drivers/gpu/drm/arm/malidp_crtc.c
> index 56aad288666e..d6690e016f0b 100644
> --- a/drivers/gpu/drm/arm/malidp_crtc.c
> +++ b/drivers/gpu/drm/arm/malidp_crtc.c
> @@ -463,23 +463,6 @@ static struct drm_crtc_state
> *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
> return &state->base;
> }
>
> -static void malidp_crtc_reset(struct drm_crtc *crtc)
> -{
> - struct malidp_crtc_state *state = NULL;
> -
> - if (crtc->state) {
> - state = to_malidp_crtc_state(crtc->state);
> - __drm_atomic_helper_crtc_destroy_state(crtc->state);
> - }
> -
> - kfree(state);
> - state = kzalloc(sizeof(*state), GFP_KERNEL);
> - if (state) {
> - crtc->state = &state->base;
> - crtc->state->crtc = crtc;
> - }
> -}
> -
> static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state)
> {
> @@ -493,6 +476,17 @@ static void malidp_crtc_destroy_state(struct drm_crtc
> *crtc,
> kfree(mali_state);
> }
>
> +static void malidp_crtc_reset(struct drm_crtc *crtc)
> +{
> + struct malidp_crtc_state *state =
> + kzalloc(sizeof(*state), GFP_KERNEL);
> +
> + if (crtc->state)
> + malidp_crtc_destroy_state(crtc, crtc->state);
> +
> + __drm_atomic_helper_crtc_reset(crtc, &state->base);
> +}
> +
> static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
> {
> struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
> --
> 2.20.1
>
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--
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---
¯\_(ツ)_/¯
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't manually add connectors and planes state
On Thu, Feb 28, 2019 at 09:27:48PM +, Souza, Jose wrote: > On Thu, 2019-02-28 at 13:37 +0200, Ville Syrjälä wrote: > > On Wed, Feb 27, 2019 at 03:04:08PM -0800, José Roberto de Souza > > wrote: > > > drm_atomic_commit() call chain already takes care of adding > > > connectors and planes, so lets no add then manually if not changing > > > their states. > > > > The specific callgraph would make review easier. > > Appending this to the commit message is enough? > > drm_atomic_commit() > drm_atomic_check_only() > config->funcs->atomic_check()/intel_atomic_check() > drm_atomic_helper_check() > drm_atomic_helper_check_modeset() > for_each_oldnew_crtc_in_state() > drm_atomic_add_affected > _connectors() > drm_atomic_add_affected > _planes() Yes, that helps. Thanks. Reviewed-by: Ville Syrjälä Hmm. I wonder if fastboot has actually broken this code. Maybe we need to set connectors_changed instead of mode_changed to guarantee the full modeset... > > > > > > Cc: Ville Syrjälä > > > Cc: Lyude Paul > > > Signed-off-by: José Roberto de Souza > > > --- > > > drivers/gpu/drm/i915/intel_ddi.c | 8 > > > 1 file changed, 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index 34dd5823398a..c22ddde2dfc1 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -3975,14 +3975,6 @@ static int modeset_pipe(struct drm_crtc > > > *crtc, > > > > > > crtc_state->mode_changed = true; > > > > > > - ret = drm_atomic_add_affected_connectors(state, crtc); > > > - if (ret) > > > - goto out; > > > - > > > - ret = drm_atomic_add_affected_planes(state, crtc); > > > - if (ret) > > > - goto out; > > > - > > > ret = drm_atomic_commit(state); > > > out: > > > drm_atomic_state_put(state); > > > -- > > > 2.21.0 -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Start subclassing crtc_state.
== Series Details == Series: drm: Start subclassing crtc_state. URL : https://patchwork.freedesktop.org/series/57425/ State : success == Summary == CI Bug Log - changes from CI_DRM_5676 -> Patchwork_12342 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57425/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12342 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17 * igt@gem_exec_basic@readonly-bsd1: - fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7 * igt@gem_exec_basic@readonly-bsd2: - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] +76 * igt@gem_exec_parse@basic-allowed: - fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1 * igt@i915_selftest@live_contexts: - fi-icl-u2: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@kms_busy@basic-flip-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] - fi-pnv-d510:NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_chamelium@dp-edid-read: - fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2 * igt@kms_chamelium@vga-hpd-fast: - fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1 * igt@kms_force_connector_basic@prune-stale-modes: - fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3 * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: NOTRUN -> FAIL [fdo#103167] * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c: - fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +48 Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS * igt@i915_selftest@live_evict: - fi-bsw-kefka: DMESG-WARN [fdo#107709] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] / [fdo#109720] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107709]: https://bugs.freedesktop.org/show_bug.cgi?id=107709 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (44 -> 39) -- Additional (2): fi-icl-u2 fi-pnv-d510 Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-icl-y fi-byt-clapper Build changes - * Linux: CI_DRM_5676 -> Patchwork_12342 CI_DRM_5676: 3911a5d7d3de6d8e491868bb0cd506346131d71b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4866: 189956af183c245eb237b3be4fa22953ec93bbe0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12342: 58ec786d5c8e797c5371b9dae2006c73ad007cd8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 58ec786d5c8e drm/vmwgfx: Convert to using __drm_atomic_helper_crtc_reset() for reset. 21dea2d6f4e3 drm/vkms: Convert to using __drm_atomic_helper_crtc_reset() for reset. df9f94b77ae9 drm/vc4: Convert to using __drm_atomic_helper_crtc_reset() for reset. 725895026dd3 drm/tegra: Convert to using __drm_atomic_helper_crtc_reset() for reset. 837ea0cf17aa drm/rockchip: Convert to using __drm_atomic_helper_crtc_reset() for reset. 5412a63fabc8 drm/rcar-du: Convert to using __drm_atomic_helper_crtc_reset() for reset. d6083ed9c6f7 drm/omap: Convert to using __drm_atomic_helper_crtc_reset() for reset. 3a057b72363e drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset. 70cc75e4022f drm/mediatek: Convert to using __drm_atomic_helper_crtc_reset() for reset. c9bf362dac3b drm/imx: Convert to using __drm_atomic_helper_crtc_reset() for reset. 9158964fdd37 drm/i915: Use the new __drm_atomic_helper_crtc_reset() helper. 97817e87cd77 drm/atmel-hlcdc: Convert to using __drm_atomic_helper_crtc_reset() for reset. c3ddc7689a67 drm/mali: Convert to using __drm_atomic_helper_crtc_reset() for reset. f8574e1d416a drm/amd: Convert to using __drm_atomic_helper_crtc_reset() for reset. 34f32bdeca76 drm/docs: Fix typo in __drm_atomic_helper_connector_reset fdfc56a108d3 drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. 51d3cd
[Intel-gfx] [PATCH 36/38] drm/i915: Allow specification of parallel execbuf
There is a desire to split a task onto two engines and have them run at
the same time, e.g. scanline interleaving to spread the workload evenly.
Through the use of the out-fence from the first execbuf, we can
coordinate secondary execbuf to only become ready simultaneously with
the first, so that with all things idle the second execbufs are executed
in parallel with the first. The key difference here between the new
EXEC_FENCE_SUBMIT and the existing EXEC_FENCE_IN is that the in-fence
waits for the completion of the first request (so that all of its
rendering results are visible to the second execbuf, the more common
userspace fence requirement).
Since we only have a single input fence slot, userspace cannot mix an
in-fence and a submit-fence. It has to use one or the other! This is not
such a harsh requirement, since by virtue of the submit-fence, the
secondary execbuf inherit all of the dependencies from the first
request, and for the application the dependencies should be common
between the primary and secondary execbuf.
Suggested-by: Tvrtko Ursulin
Testcase: igt/gem_exec_fence/parallel
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 25 +-
include/uapi/drm/i915_drm.h| 17 ++-
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index de8effed4381..a7f99f4b8bf8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -421,6 +421,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void
*data,
case I915_PARAM_HAS_EXEC_CAPTURE:
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
+ case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 5ea2e1c8b927..6150f4db877d 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2285,6 +2285,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
{
struct i915_execbuffer eb;
struct dma_fence *in_fence = NULL;
+ struct dma_fence *exec_fence = NULL;
struct sync_file *out_fence = NULL;
intel_wakeref_t wakeref;
int out_fence_fd = -1;
@@ -2328,11 +2329,24 @@ i915_gem_do_execbuffer(struct drm_device *dev,
return -EINVAL;
}
+ if (args->flags & I915_EXEC_FENCE_SUBMIT) {
+ if (in_fence) {
+ err = -EINVAL;
+ goto err_in_fence;
+ }
+
+ exec_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
+ if (!exec_fence) {
+ err = -EINVAL;
+ goto err_in_fence;
+ }
+ }
+
if (args->flags & I915_EXEC_FENCE_OUT) {
out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
if (out_fence_fd < 0) {
err = out_fence_fd;
- goto err_in_fence;
+ goto err_exec_fence;
}
}
@@ -2464,6 +2478,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_request;
}
+ if (exec_fence) {
+ err = i915_request_await_execution(eb.request, exec_fence,
+ eb.engine->bond_execute);
+ if (err < 0)
+ goto err_request;
+ }
+
if (fences) {
err = await_fence_array(&eb, fences);
if (err)
@@ -2524,6 +2545,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
err_out_fence:
if (out_fence_fd != -1)
put_unused_fd(out_fence_fd);
+err_exec_fence:
+ dma_fence_put(exec_fence);
err_in_fence:
dma_fence_put(in_fence);
return err;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index c9683b19aaf2..677d435ac64b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -591,6 +591,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
+ * execution through use of explicit fence support.
+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
+ */
+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1113,7 +1119,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I
[Intel-gfx] [PATCH 34/38] drm/i915: Extend execution fence to support a callback
In the next patch, we will want to configure the slave request
depending on which physical engine the master request is executed on.
For this, we introduce a callback from the execute fence to convey this
information.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c | 84 +++--
drivers/gpu/drm/i915/i915_request.h | 4 ++
2 files changed, 83 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index e0807a61dcf4..db98b4bf5d5e 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -37,6 +37,8 @@ struct execute_cb {
struct list_head link;
struct irq_work work;
struct i915_sw_fence *fence;
+ void (*hook)(struct i915_request *rq, struct dma_fence *signal);
+ struct i915_request *signal;
};
static struct i915_global_request {
@@ -341,6 +343,17 @@ static void irq_execute_cb(struct irq_work *wrk)
kmem_cache_free(global.slab_execute_cbs, cb);
}
+static void irq_execute_cb_hook(struct irq_work *wrk)
+{
+ struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
+
+ cb->hook(container_of(cb->fence, struct i915_request, submit),
+&cb->signal->fence);
+ i915_request_put(cb->signal);
+
+ irq_execute_cb(wrk);
+}
+
static void __notify_execute_cb(struct i915_request *rq)
{
struct execute_cb *cb;
@@ -367,14 +380,19 @@ static void __notify_execute_cb(struct i915_request *rq)
}
static int
-i915_request_await_execution(struct i915_request *rq,
-struct i915_request *signal,
-gfp_t gfp)
+__i915_request_await_execution(struct i915_request *rq,
+ struct i915_request *signal,
+ void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal),
+ gfp_t gfp)
{
struct execute_cb *cb;
- if (i915_request_is_active(signal))
+ if (i915_request_is_active(signal)) {
+ if (hook)
+ hook(rq, &signal->fence);
return 0;
+ }
cb = kmem_cache_alloc(global.slab_execute_cbs, gfp);
if (!cb)
@@ -384,8 +402,18 @@ i915_request_await_execution(struct i915_request *rq,
i915_sw_fence_await(cb->fence);
init_irq_work(&cb->work, irq_execute_cb);
+ if (hook) {
+ cb->hook = hook;
+ cb->signal = i915_request_get(signal);
+ cb->work.func = irq_execute_cb_hook;
+ }
+
spin_lock_irq(&signal->lock);
if (i915_request_is_active(signal)) {
+ if (hook) {
+ hook(rq, &signal->fence);
+ i915_request_put(signal);
+ }
i915_sw_fence_complete(cb->fence);
kmem_cache_free(global.slab_execute_cbs, cb);
} else {
@@ -788,7 +816,7 @@ emit_semaphore_wait(struct i915_request *to,
return err;
/* Only submit our spinner after the signaler is running! */
- err = i915_request_await_execution(to, from, gfp);
+ err = __i915_request_await_execution(to, from, NULL, gfp);
if (err)
return err;
@@ -908,6 +936,52 @@ i915_request_await_dma_fence(struct i915_request *rq,
struct dma_fence *fence)
return 0;
}
+int
+i915_request_await_execution(struct i915_request *rq,
+struct dma_fence *fence,
+void (*hook)(struct i915_request *rq,
+ struct dma_fence *signal))
+{
+ struct dma_fence **child = &fence;
+ unsigned int nchild = 1;
+ int ret;
+
+ if (dma_fence_is_array(fence)) {
+ struct dma_fence_array *array = to_dma_fence_array(fence);
+
+ /* XXX Error for signal-on-any fence arrays */
+
+ child = array->fences;
+ nchild = array->num_fences;
+ GEM_BUG_ON(!nchild);
+ }
+
+ do {
+ fence = *child++;
+ if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
+ continue;
+
+ /*
+* We don't squash repeated fence dependencies here as we
+* want to run our callback in all cases.
+*/
+
+ if (dma_fence_is_i915(fence))
+ ret = __i915_request_await_execution(rq,
+to_request(fence),
+hook,
+I915_FENCE_GFP);
+ else
+ ret = i915_sw_fence_await_dma_fence(&rq->submit, fence,
+ I915_FENCE_TIMEOUT,
+
[Intel-gfx] [PATCH 35/38] drm/i915/execlists: Virtual engine bonding
Some users require that when a master batch is executed on one particular
engine, a companion batch is run simultaneously on a specific slave
engine. For this purpose, we introduce virtual engine bonding, allowing
maps of master:slaves to be constructed to constrain which physical
engines a virtual engine may select given a fence on a master engine.
For the moment, we continue to ignore the issue of preemption deferring
the master request for later. Ideally, we would like to then also remove
the slave and run something else rather than have it stall the pipeline.
With load balancing, we should be able to move workload around it, but
there is a similar stall on the master pipeline while it may wait for
the slave to be executed. At the cost of more latency for the bonded
request, it may be interesting to launch both on their engines in
lockstep. (Bubbles abound.)
Opens: Also what about bonding an engine as its own master? It doesn't
break anything internally, so allow the silliness.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 46 ++
drivers/gpu/drm/i915/i915_request.c| 1 +
drivers/gpu/drm/i915/i915_request.h| 1 +
drivers/gpu/drm/i915/intel_engine_types.h | 7 +
drivers/gpu/drm/i915/intel_lrc.c | 97
drivers/gpu/drm/i915/intel_lrc.h | 3 +
drivers/gpu/drm/i915/selftests/intel_lrc.c | 167 +
include/uapi/drm/i915_drm.h| 22 +++
8 files changed, 344 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 57c85e990e80..c21460c7f842 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1459,8 +1459,54 @@ set_engines__load_balance(struct i915_user_extension
__user *base, void *data)
return 0;
}
+static int
+set_engines__bond(struct i915_user_extension __user *base, void *data)
+{
+ struct i915_context_engines_bond __user *ext =
+ container_of_user(base, typeof(*ext), base);
+ const struct set_engines *set = data;
+ struct intel_engine_cs *master;
+ u32 class, instance, siblings;
+ u16 idx;
+ int err;
+
+ if (get_user(idx, &ext->engine_index))
+ return -EFAULT;
+
+ if (idx >= set->nengine || !set->engines[idx])
+ return -EINVAL;
+
+ /*
+* A non-virtual engine has 0 siblings to choose between; and submit
fence will
+* always be directed to the one engine.
+*/
+ if (!intel_engine_is_virtual(set->engines[idx]))
+ return 0;
+
+ err = check_user_mbz16(&ext->mbz);
+ if (err)
+ return err;
+
+ if (get_user(class, &ext->master_class))
+ return -EFAULT;
+
+ if (get_user(instance, &ext->master_instance))
+ return -EFAULT;
+
+ master = intel_engine_lookup_user(set->ctx->i915, class, instance);
+ if (!master)
+ return -EINVAL;
+
+ if (get_user(siblings, &ext->sibling_mask))
+ return -EFAULT;
+
+ return intel_virtual_engine_attach_bond(set->engines[idx],
+ master, siblings);
+}
+
static const i915_user_extension_fn set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_engines__load_balance,
+ [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
static int
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index db98b4bf5d5e..ccee1cff8961 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -741,6 +741,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
rq->batch = NULL;
rq->capture_list = NULL;
rq->waitboost = false;
+ rq->execution_mask = ~0u;
/*
* Reserve space in the ring buffer for all the commands required to
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index fef6aabbb1a4..01de566c8e73 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -145,6 +145,7 @@ struct i915_request {
*/
struct i915_sched_node sched;
struct i915_dependency dep;
+ unsigned int execution_mask;
/*
* A convenience pointer to the current breadcrumb value stored in
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
b/drivers/gpu/drm/i915/intel_engine_types.h
index fe59fa24013e..e455a09a7100 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -382,6 +382,13 @@ struct intel_engine_cs {
*/
void(*submit_request)(struct i915_request *rq);
+ /*
+* Called on signaling of a SUBMIT_FENCE, passing along the signaling
+* request down to the bonded pairs.
+*
[Intel-gfx] [PATCH 32/38] drm/i915: Introduce intel_context.pin_mutex for pin management
Introduce a mutex to start locking the HW contexts independently of
struct_mutex, with a view to reducing the coarse struct_mutex. The
intel_context.pin_mutex is used to guard the transition to and from being
pinned on the gpu, and so is required before starting to build any
request, and released when the execution is completed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 76 +++
drivers/gpu/drm/i915/intel_context.c | 56 --
drivers/gpu/drm/i915/intel_context.h | 38 ++
drivers/gpu/drm/i915/intel_context_types.h| 8 +-
drivers/gpu/drm/i915/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 2 +-
9 files changed, 110 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c6a25c3276ee..4babea524fc8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4706,7 +4706,7 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
if (!state)
continue;
- GEM_BUG_ON(ce->pin_count);
+ GEM_BUG_ON(intel_context_is_pinned(ce));
/*
* As we will hold a reference to the logical state, it will
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 60b17f6a727d..321b26e302e5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1096,23 +1096,27 @@ static int gen8_emit_rpcs_config(struct i915_request
*rq,
}
static int
-gen8_modify_rpcs_gpu(struct intel_context *ce,
-struct intel_engine_cs *engine,
-struct intel_sseu sseu)
+gen8_modify_rpcs_gpu(struct intel_context *ce, struct intel_sseu sseu)
{
- struct drm_i915_private *i915 = engine->i915;
+ struct drm_i915_private *i915 = ce->engine->i915;
struct i915_request *rq, *prev;
intel_wakeref_t wakeref;
int ret;
- GEM_BUG_ON(!ce->pin_count);
+ lockdep_assert_held(&ce->pin_mutex);
- lockdep_assert_held(&i915->drm.struct_mutex);
+ /*
+* If context is not idle we have to submit an ordered request to modify
+* its context image via the kernel context. Pristine and idle contexts
+* will be configured on pinning.
+*/
+ if (!intel_context_is_pinned(ce))
+ return 0;
/* Submitting requests etc needs the hw awake. */
wakeref = intel_runtime_pm_get(i915);
- rq = i915_request_alloc(engine, i915->kernel_context);
+ rq = i915_request_alloc(ce->engine, i915->kernel_context);
if (IS_ERR(rq)) {
ret = PTR_ERR(rq);
goto out_put;
@@ -1156,53 +1160,30 @@ gen8_modify_rpcs_gpu(struct intel_context *ce,
}
static int
-__i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_sseu sseu)
+i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_sseu sseu)
{
struct intel_context *ce;
int ret = 0;
- ce = intel_context_instance(ctx, engine);
- if (IS_ERR(ce))
- return PTR_ERR(ce);
-
GEM_BUG_ON(INTEL_GEN(ctx->i915) < 8);
GEM_BUG_ON(engine->id != RCS);
+ ce = intel_context_pin_lock(ctx, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
/* Nothing to do if unmodified. */
if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
- return 0;
-
- /*
-* If context is not idle we have to submit an ordered request to modify
-* its context image via the kernel context. Pristine and idle contexts
-* will be configured on pinning.
-*/
- if (ce->pin_count)
- ret = gen8_modify_rpcs_gpu(ce, engine, sseu);
+ goto unlock;
+ ret = gen8_modify_rpcs_gpu(ce, sseu);
if (!ret)
ce->sseu = sseu;
- return ret;
-}
-
-static int
-i915_gem_context_reconfigure_sseu(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_sseu sseu)
-{
- int ret;
-
- ret = mutex_lock_interruptible(&ctx->i915->drm.struct_mutex);
- if (ret)
- return ret;
-
- ret = __i915_gem_context_reconfigure_sseu(ctx, engine, sseu);
-
- mutex_unlock(&ctx->i915->drm.struct_mutex);
-
+unlock:
+ intel_context_pin_unlock(ce);
return ret;
}
@@ -16
[Intel-gfx] [PATCH 23/38] drm/i915: Re-arrange execbuf so context is known before engine
From: Tvrtko Ursulin
Needed for a following patch.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 07c0af316f86..53d0d70c97fa 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -2312,10 +2312,6 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
- eb.engine = eb_select_engine(eb.i915, file, args);
- if (!eb.engine)
- return -EINVAL;
-
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
@@ -2340,6 +2336,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_destroy;
+ eb.engine = eb_select_engine(eb.i915, file, args);
+ if (!eb.engine) {
+ err = -EINVAL;
+ goto err_engine;
+ }
+
/*
* Take a local wakeref for preparing to dispatch the execbuf as
* we expect to access the hardware fairly frequently in the
@@ -2505,6 +2507,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
mutex_unlock(&dev->struct_mutex);
err_rpm:
intel_runtime_pm_put(eb.i915, wakeref);
+err_engine:
i915_gem_context_put(eb.ctx);
err_destroy:
eb_destroy(&eb);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/38] drm/i915: Introduce a context barrier callback
In the next patch, we will want to update live state within a context.
As this state may be in use by the GPU and we haven't been explicitly
tracking its activity, we instead attach it to a request we send down
the context setup with its new state and on retiring that request
cleanup the old state as we then know that it is no longer live.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 74 +
.../gpu/drm/i915/selftests/i915_gem_context.c | 103 ++
2 files changed, 177 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 3b5145b30d85..91926a407548 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -707,6 +707,80 @@ last_request_on_engine(struct i915_timeline *timeline,
return NULL;
}
+struct context_barrier_task {
+ struct i915_active base;
+ void (*task)(void *data);
+ void *data;
+};
+
+static void cb_retire(struct i915_active *base)
+{
+ struct context_barrier_task *cb = container_of(base, typeof(*cb), base);
+
+ if (cb->task)
+ cb->task(cb->data);
+
+ i915_active_fini(&cb->base);
+ kfree(cb);
+}
+
+I915_SELFTEST_DECLARE(static unsigned long context_barrier_inject_fault);
+static int context_barrier_task(struct i915_gem_context *ctx,
+ unsigned long engines,
+ void (*task)(void *data),
+ void *data)
+{
+ struct drm_i915_private *i915 = ctx->i915;
+ struct context_barrier_task *cb;
+ struct intel_context *ce;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ lockdep_assert_held(&i915->drm.struct_mutex);
+ GEM_BUG_ON(!task);
+
+ cb = kmalloc(sizeof(*cb), GFP_KERNEL);
+ if (!cb)
+ return -ENOMEM;
+
+ i915_active_init(i915, &cb->base, cb_retire);
+ i915_active_acquire(&cb->base);
+
+ wakeref = intel_runtime_pm_get(i915);
+ list_for_each_entry(ce, &ctx->active_engines, active_link) {
+ struct intel_engine_cs *engine = ce->engine;
+ struct i915_request *rq;
+
+ if (!(ce->engine->mask & engines))
+ continue;
+
+ if (I915_SELFTEST_ONLY(context_barrier_inject_fault &
+ engine->mask)) {
+ err = -ENXIO;
+ break;
+ }
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ err = i915_active_ref(&cb->base, rq->fence.context, rq);
+ i915_request_add(rq);
+ if (err)
+ break;
+ }
+ intel_runtime_pm_put(i915, wakeref);
+
+ cb->task = err ? NULL : task; /* caller needs to unwind instead */
+ cb->data = data;
+
+ i915_active_release(&cb->base);
+
+ return err;
+}
+
int i915_gem_switch_to_kernel_context(struct drm_i915_private *i915,
unsigned long mask)
{
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 7ae5033457b6..4f7c04247354 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1594,10 +1594,113 @@ static int igt_switch_to_kernel_context(void *arg)
return err;
}
+static void mock_barrier_task(void *data)
+{
+ unsigned int *counter = data;
+
+ ++*counter;
+}
+
+static int mock_context_barrier(void *arg)
+{
+#undef pr_fmt
+#define pr_fmt(x) "context_barrier_task():" # x
+ struct drm_i915_private *i915 = arg;
+ struct i915_gem_context *ctx;
+ struct i915_request *rq;
+ intel_wakeref_t wakeref;
+ unsigned int counter;
+ int err;
+
+ /*
+* The context barrier provides us with a callback after it emits
+* a request; useful for retiring old state after loading new.
+*/
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ ctx = mock_context(i915, "mock");
+ if (IS_ERR(ctx)) {
+ err = PTR_ERR(ctx);
+ goto unlock;
+ }
+
+ counter = 0;
+ err = context_barrier_task(ctx, 0, mock_barrier_task, &counter);
+ if (err) {
+ pr_err("Failed at line %d, err=%d\n", __LINE__, err);
+ goto out;
+ }
+ if (counter == 0) {
+ pr_err("Did not retire immediately with 0 engines\n");
+ err = -EINVAL;
+ goto out;
+ }
+
+ counter = 0;
+ err = context_barrier_task(ctx, -1, mock_barrier_task, &counter);
+ if (err) {
+ pr_err("Failed at line %d, err=%d\n", __LINE__, err);
+ goto out;
+
[Intel-gfx] [PATCH 25/38] drm/i915: Extend I915_CONTEXT_PARAM_SSEU to support local ctx->engine[]
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context and do not have a valid global class:instance
lookup.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 24
include/uapi/drm/i915_drm.h | 3 ++-
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 85067a3dc72c..d04fa649bc0e 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1341,6 +1341,7 @@ static int set_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_sseu sseu;
+ unsigned long lookup;
int ret;
if (args->size < sizeof(user_sseu))
@@ -1353,10 +1354,17 @@ static int set_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
@@ -1802,6 +1810,7 @@ static int get_sseu(struct i915_gem_context *ctx,
struct drm_i915_gem_context_param_sseu user_sseu;
struct intel_engine_cs *engine;
struct intel_context *ce;
+ unsigned long lookup;
int ret;
if (args->size == 0)
@@ -1813,10 +1822,17 @@ static int get_sseu(struct i915_gem_context *ctx,
sizeof(user_sseu)))
return -EFAULT;
- if (user_sseu.flags || user_sseu.rsvd)
+ if (user_sseu.rsvd)
return -EINVAL;
- engine = lookup_user_engine(ctx, 0,
+ if (user_sseu.flags & ~(I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX))
+ return -EINVAL;
+
+ lookup = 0;
+ if (user_sseu.flags & I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX)
+ lookup |= LOOKUP_USER_INDEX;
+
+ engine = lookup_user_engine(ctx, lookup,
user_sseu.engine_class,
user_sseu.engine_instance);
if (!engine)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 85ccba4f04e8..b68e1ad12c0f 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1565,9 +1565,10 @@ struct drm_i915_gem_context_param_sseu {
__u16 engine_instance;
/*
-* Unused for now. Must be cleared to zero.
+* Unknown flags must be cleared to zero.
*/
__u32 flags;
+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/38] drm/i915: Allow userspace to clone contexts on creation
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient if they were able to just pass in a target context to clone
during creation. This essentially extends the setparam during creation
to pull the details from a target context instead of the user supplied
parameters.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 71 +
include/uapi/drm/i915_drm.h | 14 +
2 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index d8e2228636ba..48fb2ffb5f8c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1456,8 +1456,79 @@ static int create_setparam(struct i915_user_extension
__user *ext, void *data)
return ctx_setparam(data, &local.setparam);
}
+static void clone_sseu(struct i915_gem_context *dst,
+ struct i915_gem_context *src)
+{
+ const struct intel_sseu default_sseu =
+ intel_device_default_sseu(dst->i915);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, dst->i915, id) {
+ struct intel_context *ce;
+ struct intel_sseu sseu;
+
+ ce = to_intel_context(src, engine);
+ if (!ce)
+ continue;
+
+ sseu = ce->sseu;
+ if (!memcmp(&sseu, &default_sseu, sizeof(sseu)))
+ continue;
+
+ ce = to_intel_context(dst, engine);
+ ce->sseu = sseu;
+ }
+}
+
+static int create_clone(struct i915_user_extension __user *ext, void *data)
+{
+ struct drm_i915_gem_context_create_ext_clone local;
+ struct i915_gem_context *dst = data;
+ struct i915_gem_context *src;
+
+ if (copy_from_user(&local, ext, sizeof(local)))
+ return -EFAULT;
+
+ if (local.flags & I915_CONTEXT_CLONE_UNKNOWN)
+ return -EINVAL;
+
+ if (local.rsvd)
+ return -EINVAL;
+
+ rcu_read_lock();
+ src = __i915_gem_context_lookup_rcu(dst->file_priv, local.clone);
+ rcu_read_unlock();
+ if (!src)
+ return -ENOENT;
+
+ if (local.flags & I915_CONTEXT_CLONE_FLAGS)
+ dst->user_flags = src->user_flags;
+
+ if (local.flags & I915_CONTEXT_CLONE_SCHED)
+ dst->sched = src->sched;
+
+ if (local.flags & I915_CONTEXT_CLONE_SSEU)
+ clone_sseu(dst, src);
+
+ if (local.flags & I915_CONTEXT_CLONE_TIMELINE && src->timeline) {
+ if (dst->timeline)
+ i915_timeline_put(dst->timeline);
+ dst->timeline = i915_timeline_get(src->timeline);
+ }
+
+ if (local.flags & I915_CONTEXT_CLONE_VM && src->ppgtt) {
+ if (dst->ppgtt)
+ i915_ppgtt_put(dst->ppgtt);
+ dst->ppgtt = i915_ppgtt_get(src->ppgtt);
+ }
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_CONTEXT_CREATE_EXT_SETPARAM] = create_setparam,
+ [I915_CONTEXT_CREATE_EXT_CLONE] = create_clone,
};
static bool client_is_banned(struct drm_i915_file_private *file_priv)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 451d2f36830b..60cbb2e4f140 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1577,6 +1577,20 @@ struct drm_i915_gem_context_create_ext_setparam {
struct drm_i915_gem_context_param setparam;
};
+struct drm_i915_gem_context_create_ext_clone {
+#define I915_CONTEXT_CREATE_EXT_CLONE 1
+ struct i915_user_extension base;
+ __u32 clone;
+ __u32 flags;
+#define I915_CONTEXT_CLONE_FLAGS (1u << 0)
+#define I915_CONTEXT_CLONE_SCHED (1u << 1)
+#define I915_CONTEXT_CLONE_SSEU(1u << 2)
+#define I915_CONTEXT_CLONE_TIMELINE(1u << 3)
+#define I915_CONTEXT_CLONE_VM (1u << 4)
+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
+ __u64 rsvd;
+};
+
struct drm_i915_gem_context_destroy {
__u32 ctx_id;
__u32 pad;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/38] drm/i915: Keep timeline HWSP allocated until idle across the system
In preparation for enabling HW semaphores, we need to keep in flight
timeline HWSP alive until its use across entire system has completed,
as any other timeline active on the GPU may still refer back to the
already retired timeline. We both have to delay recycling available
cachelines and unpinning old HWSP until the next idle point.
An easy option would be to simply keep all used HWSP until the system as
a whole was idle, i.e. we could release them all at once on parking.
However, on a busy system, we may never see a global idle point,
essentially meaning the resource will be leaked until we are forced to
do a GC pass. We already employ a fine-grained idle detection mechanism
for vma, which we can reuse here so that each cacheline can be freed
immediately after the last request using it is retired.
v3: Keep track of the activity of each cacheline.
v4: cacheline_free() on canceling the seqno tracking
v5: Finally with a testcase to exercise wraparound
v6: Pack cacheline into empty bits of page-aligned vaddr
v7: Use i915_utils to hide the pointer casting around bit manipulation
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_request.c | 31 +-
drivers/gpu/drm/i915/i915_request.h | 11 +
drivers/gpu/drm/i915/i915_timeline.c | 293 --
drivers/gpu/drm/i915/i915_timeline.h | 11 +-
.../gpu/drm/i915/selftests/i915_timeline.c| 113 +++
5 files changed, 420 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 719d1a5ab082..d354967d6ae8 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -325,11 +325,6 @@ void i915_request_retire_upto(struct i915_request *rq)
} while (tmp != rq);
}
-static u32 timeline_get_seqno(struct i915_timeline *tl)
-{
- return tl->seqno += 1 + tl->has_initial_breadcrumb;
-}
-
static void move_to_timeline(struct i915_request *request,
struct i915_timeline *timeline)
{
@@ -532,8 +527,10 @@ struct i915_request *
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context
*ctx)
{
struct drm_i915_private *i915 = engine->i915;
- struct i915_request *rq;
struct intel_context *ce;
+ struct i915_timeline *tl;
+ struct i915_request *rq;
+ u32 seqno;
int ret;
lockdep_assert_held(&i915->drm.struct_mutex);
@@ -610,24 +607,27 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
}
}
- rq->rcustate = get_state_synchronize_rcu();
-
INIT_LIST_HEAD(&rq->active_list);
+
+ tl = ce->ring->timeline;
+ ret = i915_timeline_get_seqno(tl, rq, &seqno);
+ if (ret)
+ goto err_free;
+
rq->i915 = i915;
rq->engine = engine;
rq->gem_context = ctx;
rq->hw_context = ce;
rq->ring = ce->ring;
- rq->timeline = ce->ring->timeline;
+ rq->timeline = tl;
GEM_BUG_ON(rq->timeline == &engine->timeline);
- rq->hwsp_seqno = rq->timeline->hwsp_seqno;
+ rq->hwsp_seqno = tl->hwsp_seqno;
+ rq->hwsp_cacheline = tl->hwsp_cacheline;
+ rq->rcustate = get_state_synchronize_rcu(); /* acts as smp_mb() */
spin_lock_init(&rq->lock);
- dma_fence_init(&rq->fence,
- &i915_fence_ops,
- &rq->lock,
- rq->timeline->fence_context,
- timeline_get_seqno(rq->timeline));
+ dma_fence_init(&rq->fence, &i915_fence_ops, &rq->lock,
+ tl->fence_context, seqno);
/* We bump the ref for the fence chain */
i915_sw_fence_init(&i915_request_get(rq)->submit, submit_notify);
@@ -687,6 +687,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
GEM_BUG_ON(!list_empty(&rq->sched.signalers_list));
GEM_BUG_ON(!list_empty(&rq->sched.waiters_list));
+err_free:
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
mutex_unlock(&ce->ring->timeline->mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.h
b/drivers/gpu/drm/i915/i915_request.h
index be3ded6bcf56..ea1e6f0ade53 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -38,6 +38,7 @@ struct drm_file;
struct drm_i915_gem_object;
struct i915_request;
struct i915_timeline;
+struct i915_timeline_cacheline;
struct i915_capture_list {
struct i915_capture_list *next;
@@ -148,6 +149,16 @@ struct i915_request {
*/
const u32 *hwsp_seqno;
+ /*
+* If we need to access the timeline's seqno for this request in
+* another request, we need to keep a read reference to this associated
+* cacheline, so that we do not free and recycle it before the foriegn
+* observers have completed. Hence, we keep a
[Intel-gfx] [PATCH 14/38] drm/i915: Introduce the i915_user_extension_method
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked into the ioctl data only when required by the
user. The key advantage being able to ignore large control structs for
optional interfaces/extensions, while being able to process them in a
consistent manner.
In comparison to other extensible ioctls, the key difference is the
use of a linked chain of extension structs vs an array of tagged
pointers. For example,
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
__u32 length_dw;
__u64 chunk_data;
};
struct drm_amdgpu_cs_in {
__u32 ctx_id;
__u32 bo_list_handle;
__u32 num_chunks;
__u32 _pad;
__u64 chunks;
};
allows userspace to pass in array of pointers to extension structs, but
must therefore keep constructing that array along side the command stream.
In dynamic situations like that, a linked list is preferred and does not
similar from extra cache line misses as the extension structs themselves
must still be loaded separate to the chunks array.
v2: Apply the tail call optimisation directly to nip the worry of stack
overflow in the bud.
v3: Defend against recursion.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_user_extensions.c | 43 +
drivers/gpu/drm/i915/i915_user_extensions.h | 20 ++
drivers/gpu/drm/i915/i915_utils.h | 7
include/uapi/drm/i915_drm.h | 20 ++
5 files changed, 91 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.c
create mode 100644 drivers/gpu/drm/i915/i915_user_extensions.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a1d834068765..89105b1aaf12 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -46,6 +46,7 @@ i915-y := i915_drv.o \
i915_sw_fence.o \
i915_syncmap.o \
i915_sysfs.o \
+ i915_user_extensions.o \
intel_csr.o \
intel_device_info.o \
intel_pm.o \
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.c
b/drivers/gpu/drm/i915/i915_user_extensions.c
new file mode 100644
index ..879b4094b2d7
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.c
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include
+#include
+#include
+
+#include "i915_user_extensions.h"
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data)
+{
+ unsigned int stackdepth = 512;
+
+ while (ext) {
+ int err;
+ u64 x;
+
+ if (!stackdepth--) /* recursion vs useful flexibility */
+ return -EINVAL;
+
+ if (get_user(x, &ext->name))
+ return -EFAULT;
+
+ err = -EINVAL;
+ if (x < count && tbl[x])
+ err = tbl[x](ext, data);
+ if (err)
+ return err;
+
+ if (get_user(x, &ext->next_extension))
+ return -EFAULT;
+
+ ext = u64_to_user_ptr(x);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_user_extensions.h
b/drivers/gpu/drm/i915/i915_user_extensions.h
new file mode 100644
index ..313a510b068a
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_user_extensions.h
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef I915_USER_EXTENSIONS_H
+#define I915_USER_EXTENSIONS_H
+
+struct i915_user_extension;
+
+typedef int (*i915_user_extension_fn)(struct i915_user_extension __user *ext,
+ void *data);
+
+int i915_user_extensions(struct i915_user_extension __user *ext,
+const i915_user_extension_fn *tbl,
+unsigned long count,
+void *data);
+
+#endif /* I915_USER_EXTENSIONS_H */
diff --git a/drivers/gpu/drm/i915/i915_utils.h
b/drivers/gpu/drm/i915/i915_utils.h
index 9726df37c4c4..fcc751aa1ea8 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -105,6 +105,13 @@
__T;\
})
+#define container_of_user(ptr, type, member) ({
\
+ void __user *__mptr = (void __user *)(ptr); \
+ BUILD_BUG_ON_MSG(!__same_type(*(ptr), ((type *)0)->memb
[Intel-gfx] [PATCH 30/38] drm/i915: Make context pinning part of intel_context_ops
Push the intel_context pin callback down from intel_engine_cs onto the
context itself by virtue of having a central caller for
intel_context_pin() being able to lookup the intel_context itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_context.c | 34 ++
drivers/gpu/drm/i915/intel_context.h | 7 +-
drivers/gpu/drm/i915/intel_context_types.h | 1 +
drivers/gpu/drm/i915/intel_engine_types.h| 2 -
drivers/gpu/drm/i915/intel_lrc.c | 114 ---
drivers/gpu/drm/i915/intel_ringbuffer.c | 45 ++--
drivers/gpu/drm/i915/selftests/mock_engine.c | 32 +-
7 files changed, 98 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_context.c
b/drivers/gpu/drm/i915/intel_context.c
index 242b1b6ad253..7de02be0b552 100644
--- a/drivers/gpu/drm/i915/intel_context.c
+++ b/drivers/gpu/drm/i915/intel_context.c
@@ -110,6 +110,40 @@ intel_context_instance(struct i915_gem_context *ctx,
return pos;
}
+struct intel_context *
+intel_context_pin(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+ int err;
+
+ lockdep_assert_held(&ctx->i915->drm.struct_mutex);
+
+ ce = intel_context_instance(ctx, engine);
+ if (IS_ERR(ce))
+ return ce;
+
+ if (unlikely(!ce->pin_count++)) {
+ err = ce->ops->pin(ce);
+ if (err)
+ goto err_unpin;
+
+ mutex_lock(&ctx->mutex);
+ list_add(&ce->active_link, &ctx->active_engines);
+ mutex_unlock(&ctx->mutex);
+
+ i915_gem_context_get(ctx);
+ GEM_BUG_ON(ce->gem_context != ctx);
+ }
+ GEM_BUG_ON(!ce->pin_count); /* no overflow! */
+
+ return ce;
+
+err_unpin:
+ ce->pin_count = 0;
+ return ERR_PTR(err);
+}
+
static void intel_context_retire(struct i915_active_request *active,
struct i915_request *rq)
{
diff --git a/drivers/gpu/drm/i915/intel_context.h
b/drivers/gpu/drm/i915/intel_context.h
index c3fffd9b8ae4..aa34311a472e 100644
--- a/drivers/gpu/drm/i915/intel_context.h
+++ b/drivers/gpu/drm/i915/intel_context.h
@@ -45,11 +45,8 @@ __intel_context_insert(struct i915_gem_context *ctx,
void
__intel_context_remove(struct intel_context *ce);
-static inline struct intel_context *
-intel_context_pin(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
-{
- return engine->context_pin(engine, ctx);
-}
+struct intel_context *
+intel_context_pin(struct i915_gem_context *ctx, struct intel_engine_cs
*engine);
static inline void __intel_context_pin(struct intel_context *ce)
{
diff --git a/drivers/gpu/drm/i915/intel_context_types.h
b/drivers/gpu/drm/i915/intel_context_types.h
index 857f5c335324..804fa93de853 100644
--- a/drivers/gpu/drm/i915/intel_context_types.h
+++ b/drivers/gpu/drm/i915/intel_context_types.h
@@ -19,6 +19,7 @@ struct intel_context;
struct intel_ring;
struct intel_context_ops {
+ int (*pin)(struct intel_context *ce);
void (*unpin)(struct intel_context *ce);
void (*destroy)(struct intel_context *ce);
};
diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
b/drivers/gpu/drm/i915/intel_engine_types.h
index 5dac6b439f95..aefc66605729 100644
--- a/drivers/gpu/drm/i915/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/intel_engine_types.h
@@ -357,8 +357,6 @@ struct intel_engine_cs {
void(*set_default_submission)(struct intel_engine_cs
*engine);
const struct intel_context_ops *context;
- struct intel_context *(*context_pin)(struct intel_engine_cs *engine,
-struct i915_gem_context *ctx);
int (*request_alloc)(struct i915_request *rq);
int (*init_context)(struct i915_request *rq);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0800f8edffeb..8dddea8e1c97 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -166,9 +166,8 @@
#define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE)
-static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine,
- struct intel_context *ce);
+static int execlists_context_deferred_alloc(struct intel_context *ce,
+ struct intel_engine_cs *engine);
static void execlists_init_reg_state(u32 *reg_state,
struct intel_context *ce,
struct intel_engine_cs *engine,
@@ -330,11 +329,10 @@ assert_priority_queue(const struct i915_request *prev,
* engine info, SW context ID and SW counter need to form a unique number
* (Context ID) per lrc.
*/
-static void
-intel_lr_context_de
[Intel-gfx] [PATCH 02/38] drm/i915: Introduce i915_timeline.mutex
A simple mutex used for guarding the flow of requests in and out of the
timeline. In the short-term, it will be used only to guard the addition
of requests into the timeline, taken on alloc and released on commit so
that only one caller can construct a request into the timeline
(important as the seqno and ring pointers must be serialised). This will
be used by observers to ensure that the seqno/hwsp is stable. Later,
when we have reduced retiring to only operate on a single timeline at a
time, we can then use the mutex as the sole guard required for retiring.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_request.c| 6 +-
drivers/gpu/drm/i915/i915_timeline.c | 1 +
drivers/gpu/drm/i915/i915_timeline.h | 2 ++
drivers/gpu/drm/i915/selftests/i915_request.c | 4 +---
drivers/gpu/drm/i915/selftests/mock_timeline.c | 1 +
5 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index c65f6c990fdd..719d1a5ab082 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -563,6 +563,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
return ERR_CAST(ce);
reserve_gt(i915);
+ mutex_lock(&ce->ring->timeline->mutex);
/* Move our oldest request to the slab-cache (if not in use!) */
rq = list_first_entry(&ce->ring->request_list, typeof(*rq), ring_link);
@@ -688,6 +689,7 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
kmem_cache_free(global.slab_requests, rq);
err_unreserve:
+ mutex_unlock(&ce->ring->timeline->mutex);
unreserve_gt(i915);
intel_context_unpin(ce);
return ERR_PTR(ret);
@@ -880,7 +882,7 @@ void i915_request_add(struct i915_request *request)
GEM_TRACE("%s fence %llx:%lld\n",
engine->name, request->fence.context, request->fence.seqno);
- lockdep_assert_held(&request->i915->drm.struct_mutex);
+ lockdep_assert_held(&request->timeline->mutex);
trace_i915_request_add(request);
/*
@@ -991,6 +993,8 @@ void i915_request_add(struct i915_request *request)
*/
if (prev && i915_request_completed(prev))
i915_request_retire_upto(prev);
+
+ mutex_unlock(&request->timeline->mutex);
}
static unsigned long local_clock_us(unsigned int *cpu)
diff --git a/drivers/gpu/drm/i915/i915_timeline.c
b/drivers/gpu/drm/i915/i915_timeline.c
index b2202d2e58a2..87a80558da28 100644
--- a/drivers/gpu/drm/i915/i915_timeline.c
+++ b/drivers/gpu/drm/i915/i915_timeline.c
@@ -162,6 +162,7 @@ int i915_timeline_init(struct drm_i915_private *i915,
timeline->fence_context = dma_fence_context_alloc(1);
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
diff --git a/drivers/gpu/drm/i915/i915_timeline.h
b/drivers/gpu/drm/i915/i915_timeline.h
index 7bec7d2e45bf..36c3849f7108 100644
--- a/drivers/gpu/drm/i915/i915_timeline.h
+++ b/drivers/gpu/drm/i915/i915_timeline.h
@@ -44,6 +44,8 @@ struct i915_timeline {
#define TIMELINE_CLIENT 0 /* default subclass */
#define TIMELINE_ENGINE 1
+ struct mutex mutex; /* protects the flow of requests */
+
unsigned int pin_count;
const u32 *hwsp_seqno;
struct i915_vma *hwsp_ggtt;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c
b/drivers/gpu/drm/i915/selftests/i915_request.c
index 7da52e3d67af..7e1b65b8eb19 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -141,14 +141,12 @@ static int igt_fence_wait(void *arg)
err = -ENOMEM;
goto out_locked;
}
- mutex_unlock(&i915->drm.struct_mutex); /* safe as we are single user */
if (dma_fence_wait_timeout(&request->fence, false, T) != -ETIME) {
pr_err("fence wait success before submit (expected
timeout)!\n");
- goto out_device;
+ goto out_locked;
}
- mutex_lock(&i915->drm.struct_mutex);
i915_request_add(request);
mutex_unlock(&i915->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/selftests/mock_timeline.c
b/drivers/gpu/drm/i915/selftests/mock_timeline.c
index d2de9ece2118..416d85233263 100644
--- a/drivers/gpu/drm/i915/selftests/mock_timeline.c
+++ b/drivers/gpu/drm/i915/selftests/mock_timeline.c
@@ -14,6 +14,7 @@ void mock_timeline_init(struct i915_timeline *timeline, u64
context)
timeline->fence_context = context;
spin_lock_init(&timeline->lock);
+ mutex_init(&timeline->mutex);
INIT_ACTIVE_REQUEST(&timeline->barrier);
INIT_ACTIVE_REQUEST(&timeline->last_request);
--
2.20.1
___
Intel-gfx
