[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy request.
Thanks to Chris for helping with reset magic.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
.../drm/i915/selftests/intel_workarounds.c| 58 +++
1 file changed, 48 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index d1a0923d2f38..8e49c005d4db 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -6,6 +6,7 @@
#include "../i915_selftest.h"
+#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
@@ -159,35 +160,57 @@ static int check_whitelist(const struct whitelist *w,
static int do_device_reset(struct intel_engine_cs *engine)
{
- i915_reset(engine->i915, ENGINE_MASK(engine->id), NULL);
+ set_bit(I915_RESET_HANDOFF, &engine->i915->gpu_error.flags);
+ i915_reset(engine->i915, ENGINE_MASK(engine->id), "live_workarounds");
return 0;
}
static int do_engine_reset(struct intel_engine_cs *engine)
{
- return i915_reset_engine(engine, NULL);
+ return i915_reset_engine(engine, "live_workarounds");
}
-static int switch_to_scratch_context(struct intel_engine_cs *engine)
+static int
+switch_to_scratch_context(struct intel_engine_cs *engine,
+ struct igt_spinner *spin)
{
struct i915_gem_context *ctx;
struct i915_request *rq;
+ int err = 0;
ctx = kernel_context(engine->i915);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
intel_runtime_pm_get(engine->i915);
- rq = i915_request_alloc(engine, ctx);
+
+ if (spin)
+ rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
+ else
+ rq = i915_request_alloc(engine, ctx);
+
intel_runtime_pm_put(engine->i915);
kernel_context_close(ctx);
- if (IS_ERR(rq))
- return PTR_ERR(rq);
+
+ if (IS_ERR(rq)) {
+ spin = NULL;
+ err = PTR_ERR(rq);
+ goto err;
+ }
i915_request_add(rq);
- return 0;
+ if (spin && !igt_wait_for_spinner(spin, rq)) {
+ pr_err("Spinner failed to start\n");
+ err = -ETIMEDOUT;
+ }
+
+err:
+ if (err && spin)
+ igt_spinner_end(spin);
+
+ return err;
}
static int check_whitelist_across_reset(struct intel_engine_cs *engine,
@@ -195,9 +218,20 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
const struct whitelist *w,
const char *name)
{
+ bool want_spin = reset == do_engine_reset;
struct i915_gem_context *ctx;
+ struct igt_spinner spin;
int err;
+ pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
+ w->count, name);
+
+ if (want_spin) {
+ err = igt_spinner_init(&spin, engine->i915);
+ if (err)
+ return err;
+ }
+
ctx = kernel_context(engine->i915);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
@@ -208,11 +242,17 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
goto out;
}
- err = switch_to_scratch_context(engine);
+ err = switch_to_scratch_context(engine, want_spin ? &spin : NULL);
if (err)
goto out;
err = reset(engine);
+
+ if (want_spin) {
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+ }
+
if (err) {
pr_err("%s reset failed\n", name);
goto out;
@@ -259,8 +299,6 @@ static int live_reset_whitelist(void *arg)
if (!whitelist_build(engine, &w))
return 0;
- pr_info("Checking %d whitelisted registers (RING_NONPRIV)\n", w.count);
-
set_bit(I915_RESET_BACKOFF, &error->flags);
set_bit(I915_RESET_ENGINE + engine->id, &error->flags);
--
2.19.1
___
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[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Extract spinner code
From: Tvrtko Ursulin
Pull out spinner code to a standalone file to enable it to be shortly used
by other and new test cases.
Plain code movement - no functional changes.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 199
drivers/gpu/drm/i915/selftests/igt_spinner.h | 37 +++
drivers/gpu/drm/i915/selftests/intel_lrc.c | 301 ---
4 files changed, 290 insertions(+), 250 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/igt_spinner.c
create mode 100644 drivers/gpu/drm/i915/selftests/igt_spinner.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0ff878c994e2..e56370b046b4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -164,7 +164,8 @@ i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/i915_random.o \
selftests/i915_selftest.o \
- selftests/igt_flush_test.o
+ selftests/igt_flush_test.o \
+ selftests/igt_spinner.o
# virtual gpu code
i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
b/drivers/gpu/drm/i915/selftests/igt_spinner.c
new file mode 100644
index ..8cd34f6e6859
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -0,0 +1,199 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "igt_spinner.h"
+
+int igt_spinner_init(struct igt_spinner *spin, struct drm_i915_private *i915)
+{
+ unsigned int mode;
+ void *vaddr;
+ int err;
+
+ GEM_BUG_ON(INTEL_GEN(i915) < 8);
+
+ memset(spin, 0, sizeof(*spin));
+ spin->i915 = i915;
+
+ spin->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(spin->hws)) {
+ err = PTR_ERR(spin->hws);
+ goto err;
+ }
+
+ spin->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(spin->obj)) {
+ err = PTR_ERR(spin->obj);
+ goto err_hws;
+ }
+
+ i915_gem_object_set_cache_level(spin->hws, I915_CACHE_LLC);
+ vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto err_obj;
+ }
+ spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
+
+ mode = i915_coherent_map_type(i915);
+ vaddr = i915_gem_object_pin_map(spin->obj, mode);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto err_unpin_hws;
+ }
+ spin->batch = vaddr;
+
+ return 0;
+
+err_unpin_hws:
+ i915_gem_object_unpin_map(spin->hws);
+err_obj:
+ i915_gem_object_put(spin->obj);
+err_hws:
+ i915_gem_object_put(spin->hws);
+err:
+ return err;
+}
+
+static unsigned int seqno_offset(u64 fence)
+{
+ return offset_in_page(sizeof(u32) * fence);
+}
+
+static u64 hws_address(const struct i915_vma *hws,
+ const struct i915_request *rq)
+{
+ return hws->node.start + seqno_offset(rq->fence.context);
+}
+
+static int emit_recurse_batch(struct igt_spinner *spin,
+ struct i915_request *rq,
+ u32 arbitration_command)
+{
+ struct i915_address_space *vm = &rq->gem_context->ppgtt->vm;
+ struct i915_vma *hws, *vma;
+ u32 *batch;
+ int err;
+
+ vma = i915_vma_instance(spin->obj, vm, NULL);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ hws = i915_vma_instance(spin->hws, vm, NULL);
+ if (IS_ERR(hws))
+ return PTR_ERR(hws);
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ return err;
+
+ err = i915_vma_pin(hws, 0, 0, PIN_USER);
+ if (err)
+ goto unpin_vma;
+
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (err)
+ goto unpin_hws;
+
+ if (!i915_gem_object_has_active_reference(vma->obj)) {
+ i915_gem_object_get(vma->obj);
+ i915_gem_object_set_active_reference(vma->obj);
+ }
+
+ err = i915_vma_move_to_active(hws, rq, 0);
+ if (err)
+ goto unpin_hws;
+
+ if (!i915_gem_object_has_active_reference(hws->obj)) {
+ i915_gem_object_get(hws->obj);
+ i915_gem_object_set_active_reference(hws->obj);
+ }
+
+ batch = spin->batch;
+
+ *batch++ = MI_STORE_DWORD_IMM_GEN4;
+ *batch++ = lower_32_bits(hws_address(hws, rq));
+ *batch++ = upper_32_bits(hws_address(hws, rq));
+ *batch++ = rq->fence.seqno;
+
+ *batch++ = arbitration_command;
+
+ *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
+ *batch++ = lower_32_bits(vma->node.start);
+ *batch++ = upper_32_bits(vma->node.start);
+ *batch++ = MI_BATCH_BUFFER_END; /* not reached */
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim checkpatch origin/drm-tip afa57c2cbca8 drm/i915/selftests: Extract spinner code -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 -:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #33: FILE: drivers/gpu/drm/i915/selftests/igt_spinner.c:1: +/* -:238: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #238: FILE: drivers/gpu/drm/i915/selftests/igt_spinner.h:1: +/* total: 0 errors, 3 warnings, 0 checks, 755 lines checked fb93a854e613 drm/i915/selftests: Fix live_workarounds to actually do resets ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Extract spinner code +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/selftests: Fix live_workarounds to actually do resets Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove whitelist application from ringbuffer backend (rev3)
== Series Details ==
Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3)
URL : https://patchwork.freedesktop.org/series/53243/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10960_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_10960_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_softpin@noreloc-s3:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@i915_selftest@live_hangcheck:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108315]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@busy-flip:
- shard-skl: PASS -> FAIL [fdo#103257]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-kbl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
- {shard-iclb}: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- {shard-iclb}: PASS -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +5
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@pm_rpm@basic-pci-d3-state:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@gem-mmap-gtt:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@modeset-stress-extra-wait:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
Possible fixes
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-skl: INCOMPLETE [fdo#104108] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +2
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-glk: FAIL [fdo#108145] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS
* igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP
* igt@pm_rpm@pm-tiling:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107807] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: h
Re: [Intel-gfx] [PATCH 01/16] drm/i915: Properly set PCH as NOP when display is disabled
On Sat, Nov 03, 2018 at 11:41:10PM +0200, Jani Nikula wrote:
> On Fri, 12 Oct 2018, José Roberto de Souza wrote:
> > num_pipes is set to 0 if disable_display is set inside
> > intel_device_info_runtime_init() but when that happen PCH will
> > already be set in intel_detect_pch().
> >
> > i915_driver_load()
> > i915_driver_init_early()
> > ...
> > intel_detect_pch()
> > ...
> > ...
> > i915_driver_init_hw()
> > intel_device_info_runtime_init()
> >
> > So now setting num_pipes = 0 earlier to avoid this problem.
>
> I'm growing this nagging feeling that this may be the wrong direction.
>
> It's just that disabling an existing display and not having display are
> two very different things. Even if our goal here is use the former to
> test the latter, I think it's more subtle than this. You already saw
> some of this in patch 15 of this series. You can't just pretend there's
> no display if you also want to gain benefits.
I'm tending to agree with this. If you want to *disable* display you
will need to do something with the HW because it's there in an unknown
state. If you don't have the HW, you can't do that because you will not
have the registers you need.
> I'm also not sure if we need to go as far as Chris is suggesting in [1],
> but assuming disable display means num_pipes = 0 from start prevents us
Could we have both approaches? I think they differ mainly on the
initialization part, but it is useful to just shutdown the display when
we don't need it.
Lucas De Marchi
> from doing that later on, because we'll start making assumptions. Like
> you already do in this series.
>
> Again, there's a bunch of useful stuff in the series that could be
> merged with a different ordering. Including patches 3-5 that look
> superficially good but do need an in-depth review. The init sequences
> are hard, and we should add more asserts and comments on the ordering,
> because we tend to forget why things are the way they are.
>
>
> BR,
> Jani.
>
> [1] https://patchwork.freedesktop.org/series/51000/
>
> >
> > Cc: Jani Nikula
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 5 +
> > drivers/gpu/drm/i915/intel_device_info.c | 8 ++--
> > 2 files changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index baac35f698f9..e3efc3dd8a30 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1649,6 +1649,11 @@ i915_driver_create(struct pci_dev *pdev, const
> > struct pci_device_id *ent)
> > memcpy(device_info, match_info, sizeof(*device_info));
> > device_info->device_id = pdev->device;
> >
> > + if (i915_modparams.disable_display) {
> > + DRM_INFO("Display disabled (module parameter)\n");
> > + device_info->num_pipes = 0;
> > + }
> > +
> > BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
> > BITS_PER_TYPE(device_info->platform_mask));
> > BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 03df4e33763d..69be3f211737 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -775,12 +775,8 @@ void intel_device_info_runtime_init(struct
> > intel_device_info *info)
> > info->num_sprites[pipe] = 1;
> > }
> >
> > - if (i915_modparams.disable_display) {
> > - DRM_INFO("Display disabled (module parameter)\n");
> > - info->num_pipes = 0;
> > - } else if (info->num_pipes > 0 &&
> > - (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> > - HAS_PCH_SPLIT(dev_priv)) {
> > + if (info->num_pipes > 0 && (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
> > + HAS_PCH_SPLIT(dev_priv)) {
> > u32 fuse_strap = I915_READ(FUSE_STRAP);
> > u32 sfuse_strap = I915_READ(SFUSE_STRAP);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10974
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53298/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_10974 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-bsw-kefka: FAIL [fdo#108656] -> PASS
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: FAIL [fdo#108880] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
Warnings
* igt@i915_selftest@live_contexts:
- {fi-icl-u3}:INCOMPLETE [fdo#108315] -> DMESG-FAIL [fdo#108569]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
Participating hosts (50 -> 44)
--
Additional (1): fi-glk-j4005
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5227 -> Patchwork_10974
CI_DRM_5227: 95052693524067ba66e1a6733355739fbcc8d5b6 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10974: fb93a854e61368ca0d8457ac01cc0de7f663c0e6 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fb93a854e613 drm/i915/selftests: Fix live_workarounds to actually do resets
afa57c2cbca8 drm/i915/selftests: Extract spinner code
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10974/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property
On Thu, Nov 29, 2018 at 05:52:28PM +, Strasser, Kevin wrote: > Daniel Vetter wrote: > > Do we have end-to-end userspace for this? > > I have patches for IGT and I'm planning on adding usage code to Weston. Apart > from that there is a Windows use case that Tina mentioned previously. I take > it that you will need to see the Weston part before accepting this. Yup. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
From: Tvrtko Ursulin
The test was missing some magic ingredients to actually trigger the
resets.
In case of the full reset we need the I915_RESET_HANDOFF flag set, and in
case of engine reset we need a busy request.
Thanks to Chris for helping with reset magic.
v2:
* Grab RPM ref over reset.
Signed-off-by: Tvrtko Ursulin
Cc: Chris Wilson
---
.../drm/i915/selftests/intel_workarounds.c| 65 +++
1 file changed, 53 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index d1a0923d2f38..80396b3592f5 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -6,6 +6,7 @@
#include "../i915_selftest.h"
+#include "igt_spinner.h"
#include "igt_wedge_me.h"
#include "mock_context.h"
@@ -159,35 +160,57 @@ static int check_whitelist(const struct whitelist *w,
static int do_device_reset(struct intel_engine_cs *engine)
{
- i915_reset(engine->i915, ENGINE_MASK(engine->id), NULL);
+ set_bit(I915_RESET_HANDOFF, &engine->i915->gpu_error.flags);
+ i915_reset(engine->i915, ENGINE_MASK(engine->id), "live_workarounds");
return 0;
}
static int do_engine_reset(struct intel_engine_cs *engine)
{
- return i915_reset_engine(engine, NULL);
+ return i915_reset_engine(engine, "live_workarounds");
}
-static int switch_to_scratch_context(struct intel_engine_cs *engine)
+static int
+switch_to_scratch_context(struct intel_engine_cs *engine,
+ struct igt_spinner *spin)
{
struct i915_gem_context *ctx;
struct i915_request *rq;
+ int err = 0;
ctx = kernel_context(engine->i915);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
intel_runtime_pm_get(engine->i915);
- rq = i915_request_alloc(engine, ctx);
+
+ if (spin)
+ rq = igt_spinner_create_request(spin, ctx, engine, MI_NOOP);
+ else
+ rq = i915_request_alloc(engine, ctx);
+
intel_runtime_pm_put(engine->i915);
kernel_context_close(ctx);
- if (IS_ERR(rq))
- return PTR_ERR(rq);
+
+ if (IS_ERR(rq)) {
+ spin = NULL;
+ err = PTR_ERR(rq);
+ goto err;
+ }
i915_request_add(rq);
- return 0;
+ if (spin && !igt_wait_for_spinner(spin, rq)) {
+ pr_err("Spinner failed to start\n");
+ err = -ETIMEDOUT;
+ }
+
+err:
+ if (err && spin)
+ igt_spinner_end(spin);
+
+ return err;
}
static int check_whitelist_across_reset(struct intel_engine_cs *engine,
@@ -195,10 +218,22 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
const struct whitelist *w,
const char *name)
{
+ struct drm_i915_private *i915 = engine->i915;
+ bool want_spin = reset == do_engine_reset;
struct i915_gem_context *ctx;
+ struct igt_spinner spin;
int err;
- ctx = kernel_context(engine->i915);
+ pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
+ w->count, name);
+
+ if (want_spin) {
+ err = igt_spinner_init(&spin, i915);
+ if (err)
+ return err;
+ }
+
+ ctx = kernel_context(i915);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
@@ -208,11 +243,19 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
goto out;
}
- err = switch_to_scratch_context(engine);
+ err = switch_to_scratch_context(engine, want_spin ? &spin : NULL);
if (err)
goto out;
+ intel_runtime_pm_get(i915);
err = reset(engine);
+ intel_runtime_pm_put(i915);
+
+ if (want_spin) {
+ igt_spinner_end(&spin);
+ igt_spinner_fini(&spin);
+ }
+
if (err) {
pr_err("%s reset failed\n", name);
goto out;
@@ -227,7 +270,7 @@ static int check_whitelist_across_reset(struct
intel_engine_cs *engine,
kernel_context_close(ctx);
- ctx = kernel_context(engine->i915);
+ ctx = kernel_context(i915);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
@@ -259,8 +302,6 @@ static int live_reset_whitelist(void *arg)
if (!whitelist_build(engine, &w))
return 0;
- pr_info("Checking %d whitelisted registers (RING_NONPRIV)\n", w.count);
-
set_bit(I915_RESET_BACKOFF, &error->flags);
set_bit(I915_RESET_ENGINE + engine->id, &error->flags);
--
2.19.1
___
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[Intel-gfx] [PATCH 3/6] drm/i915: Allocate a common scratch page
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications by not assuming per-engine isolation.
For later use, it simplifies engine initialisation (by removing the
allocation that required struct_mutex!) and means that we can always rely
on there being a scratch page.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 7
drivers/gpu/drm/i915/i915_gem.c | 50 -
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 42 -
drivers/gpu/drm/i915/intel_lrc.c| 17 +++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 33 +---
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ---
7 files changed, 71 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43ac6873a2bb..6cd576424ec0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1995,6 +1995,8 @@ struct drm_i915_private {
struct delayed_work idle_work;
ktime_t last_init_time;
+
+ struct i915_vma *scratch;
} gt;
/* perform PHY state sanity checks? */
@@ -3723,4 +3725,9 @@ static inline int intel_hws_csb_write_index(struct
drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
+static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
+{
+ return i915_ggtt_offset(i915->gt.scratch);
+}
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0eaa8a6f0423..a6f798333e24 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5497,6 +5497,44 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
goto out_ctx;
}
+static int
+i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int ret;
+
+ obj = i915_gem_object_create_stolen(i915, size);
+ if (!obj)
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj)) {
+ DRM_ERROR("Failed to allocate scratch page\n");
+ return PTR_ERR(obj);
+ }
+
+ vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unref;
+ }
+
+ ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
+ if (ret)
+ goto err_unref;
+
+ i915->gt.scratch = vma;
+ return 0;
+
+err_unref:
+ i915_gem_object_put(obj);
+ return ret;
+}
+
+static void i915_gem_fini_scratch(struct drm_i915_private *i915)
+{
+ i915_vma_unpin_and_release(&i915->gt.scratch, 0);
+}
+
int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
@@ -5543,12 +5581,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
goto err_unlock;
}
- ret = i915_gem_contexts_init(dev_priv);
+ ret = i915_gem_init_scratch(dev_priv,
+ IS_GEN2(dev_priv) ? SZ_256K : PAGE_SIZE);
if (ret) {
GEM_BUG_ON(ret == -EIO);
goto err_ggtt;
}
+ ret = i915_gem_contexts_init(dev_priv);
+ if (ret) {
+ GEM_BUG_ON(ret == -EIO);
+ goto err_scratch;
+ }
+
ret = intel_engines_init(dev_priv);
if (ret) {
GEM_BUG_ON(ret == -EIO);
@@ -5621,6 +5666,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
err_context:
if (ret != -EIO)
i915_gem_contexts_fini(dev_priv);
+err_scratch:
+ i915_gem_fini_scratch(dev_priv);
err_ggtt:
err_unlock:
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
@@ -5672,6 +5719,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_uc_fini(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
+ i915_gem_fini_scratch(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index a6885a59568b..07465123c166 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1571,7 +1571,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
if (HAS_BROKEN_CS_TLB(i915))
ee->wa_batchbuffer =
i915_error_object_create(i915,
-
engine->scr
[Intel-gfx] [PATCH 6/6] drm/i915: Pipeline PDP updates for Braswell
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as it is unserialised with any access (read or write)
the GPU is doing. By asserting that Braswell is not used with vGPU
(currently an unsupported platform) we can eliminate the dangerous
direct write into the context image and solely use the pipelined update.
However, the LRI of the PDP fouls up the GPU, causing it to freeze and
take out the machine with "forcewake ack timeouts". This seems possible
to workaround by preventing the GPU from sleeping (via means of
disabling the power-state management interface, i.e. forcing each ring
to remain awake) around the update.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108656
References: https://bugs.freedesktop.org/show_bug.cgi?id=108714
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 -
drivers/gpu/drm/i915/i915_request.c | 5 -
drivers/gpu/drm/i915/intel_lrc.c| 137 +++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +-
4 files changed, 68 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index add1fe7aeb93..62bde517d383 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1423,8 +1423,6 @@ static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm,
gen8_initialize_pd(vm, pd);
gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
-
- mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
}
ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index ca95ab2f4cfa..8ab8e8e6a086 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -719,11 +719,6 @@ i915_request_alloc(struct intel_engine_cs *engine, struct
i915_gem_context *ctx)
*/
rq->head = rq->ring->emit;
- /* Unconditionally invalidate GPU caches and TLBs. */
- ret = engine->emit_flush(rq, EMIT_INVALIDATE);
- if (ret)
- goto err_unwind;
-
ret = engine->request_alloc(rq);
if (ret)
goto err_unwind;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index de070dca4033..0a690c557113 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -363,31 +363,12 @@ execlists_context_schedule_out(struct i915_request *rq,
unsigned long status)
trace_i915_request_out(rq);
}
-static void
-execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
-{
- ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
- ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
- ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
- ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
-}
-
static u64 execlists_update_context(struct i915_request *rq)
{
- struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
struct intel_context *ce = rq->hw_context;
- u32 *reg_state = ce->lrc_reg_state;
-
- reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
- /*
-* True 32b PPGTT with dynamic page allocation: update PDP
-* registers and point the unallocated PDPs to scratch page.
-* PML4 is allocated during ppgtt init, so this is not needed
-* in 48-bit mode.
-*/
- if (!i915_vm_is_48bit(&ppgtt->vm))
- execlists_update_context_pdps(ppgtt, reg_state);
+ ce->lrc_reg_state[CTX_RING_TAIL + 1] =
+ intel_ring_set_tail(rq->ring, rq->tail);
/*
* Make sure the context image is complete before we submit it to HW.
@@ -1240,29 +1221,80 @@ execlists_context_pin(struct intel_engine_cs *engine,
return __execlists_context_pin(engine, ctx, ce);
}
+static int emit_pdps(struct i915_request *rq)
+{
+ const struct intel_engine_cs * const engine = rq->engine;
+ struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt;
+ int err, i;
+ u32 *cs;
+
+ err = engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ return err;
+
+ cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /*
+* Force the GPU (not just the local engine/powerwell!) to remain awake,
+* or else we may kill the machine with "timed out waiting for
+* forcewake ack request".
+*/
+
+ *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
+ for (i = GEN8_3LVL_PDPES; i--; ) {
+ const dm
[Intel-gfx] [PATCH 4/6] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index defe671130ab..a48fbe2557ea 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -308,6 +308,7 @@ static int igt_hang_sanitycheck(void *arg)
goto unlock;
for_each_engine(engine, i915, id) {
+ struct igt_wedge_me w;
long timeout;
if (!intel_engine_can_store_dword(engine))
@@ -328,9 +329,14 @@ static int igt_hang_sanitycheck(void *arg)
i915_request_add(rq);
- timeout = i915_request_wait(rq,
- I915_WAIT_LOCKED,
- MAX_SCHEDULE_TIMEOUT);
+ timeout = 0;
+ igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)
+ timeout = i915_request_wait(rq,
+ I915_WAIT_LOCKED,
+ MAX_SCHEDULE_TIMEOUT);
+ if (i915_terminally_wedged(&i915->gpu_error))
+ timeout = -EIO;
+
i915_request_put(rq);
if (timeout < 0) {
--
2.20.0.rc1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Extract spinner code
Quoting Tvrtko Ursulin (2018-11-30 08:02:53) > From: Tvrtko Ursulin > > Pull out spinner code to a standalone file to enable it to be shortly used > by other and new test cases. > > Plain code movement - no functional changes. > > Signed-off-by: Tvrtko Ursulin Shiver me conflicts. Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915/selftests: Reorder request allocation vs vma pinning
Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--
.../gpu/drm/i915/selftests/intel_hangcheck.c | 123 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 86 ++--
3 files changed, 119 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 26c065c8d2c0..a0c7cbc212ba 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -972,7 +972,6 @@ static int gpu_write(struct i915_vma *vma,
{
struct i915_request *rq;
struct i915_vma *batch;
- int flags = 0;
int err;
GEM_BUG_ON(!intel_engine_can_store_dword(engine));
@@ -981,14 +980,14 @@ static int gpu_write(struct i915_vma *vma,
if (err)
return err;
- rq = i915_request_alloc(engine, ctx);
- if (IS_ERR(rq))
- return PTR_ERR(rq);
-
batch = gpu_write_dw(vma, dword * sizeof(u32), value);
- if (IS_ERR(batch)) {
- err = PTR_ERR(batch);
- goto err_request;
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_batch;
}
err = i915_vma_move_to_active(batch, rq, 0);
@@ -996,21 +995,21 @@ static int gpu_write(struct i915_vma *vma,
goto err_request;
i915_gem_object_set_active_reference(batch->obj);
- i915_vma_unpin(batch);
- i915_vma_close(batch);
- err = engine->emit_bb_start(rq,
- batch->node.start, batch->node.size,
- flags);
+ err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
if (err)
goto err_request;
- err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+ err = engine->emit_bb_start(rq,
+ batch->node.start, batch->node.size,
+ 0);
+err_request:
if (err)
i915_request_skip(rq, err);
-
-err_request:
i915_request_add(rq);
+err_batch:
+ i915_vma_unpin(batch);
+ i915_vma_close(batch);
return err;
}
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index a48fbe2557ea..b767fab9ce1f 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -102,52 +102,87 @@ static u64 hws_address(const struct i915_vma *hws,
return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
}
-static int emit_recurse_batch(struct hang *h,
- struct i915_request *rq)
+static int move_to_active(struct i915_vma *vma,
+ struct i915_request *rq,
+ unsigned int flags)
+{
+ int err;
+
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (err)
+ return err;
+
+ if (!i915_gem_object_has_active_reference(vma->obj)) {
+ i915_gem_object_get(vma->obj);
+ i915_gem_object_set_active_reference(vma->obj);
+ }
+
+ return 0;
+}
+
+static struct i915_request *
+hang_create_request(struct hang *h, struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = h->i915;
struct i915_address_space *vm =
- rq->gem_context->ppgtt ?
- &rq->gem_context->ppgtt->vm :
- &i915->ggtt.vm;
+ h->ctx->ppgtt ? &h->ctx->ppgtt->vm : &i915->ggtt.vm;
+ struct i915_request *rq = NULL;
struct i915_vma *hws, *vma;
unsigned int flags;
u32 *batch;
int err;
+ if (i915_gem_object_is_active(h->obj)) {
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+
+ obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vaddr = i915_gem_object_pin_map(obj,
+
i915_coherent_map_type(h->i915));
+ if (IS_ERR(vaddr)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(vaddr);
+ }
+
+ i915_gem_object_unpin_map(h->obj);
+ i915_gem_object_put(h->obj);
+
+ h->obj = obj;
+ h->batch = vaddr;
+ }
+
vma = i915_vma_instance(h->obj, vm, NULL);
if (IS_ERR(vma))
- return PTR_ERR(vma);
+ return ERR_CAST(vma);
hws = i915_vm
[Intel-gfx] [PATCH 2/6] drm/i915/ringbuffer: Clear semaphore sync registers on ring init
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6c9a67ae3d26..9875ee474b83 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
+ if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
+ I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
+ I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
+ if (HAS_VEBOX(dev_priv))
+ I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
+ }
+
/* Enforce ordering by reading HEAD register back */
I915_READ_HEAD(engine);
--
2.20.0.rc1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Complete the fences as they are cancelled due to wedging
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the code to complete the fences before the
locks are dropped.
<1>[ 354.473346] BUG: unable to handle kernel NULL pointer dereference at
0250
<6>[ 354.473363] PGD 0 P4D 0
<4>[ 354.473370] Oops: [#1] PREEMPT SMP PTI
<4>[ 354.473380] CPU: 0 PID: 4470 Comm: gem_eio Tainted: G U
4.20.0-rc4-CI-CI_DRM_5216+ #1
<4>[ 354.473393] Hardware name: Intel Corporation NUC7CJYH/NUC7JYB, BIOS
JYGLKCPX.86A.0027.2018.0125.1347 01/25/2018
<4>[ 354.473480] RIP: 0010:__i915_schedule+0x311/0x5e0 [i915]
<4>[ 354.473490] Code: 49 89 44 24 20 4d 89 4c 24 28 4d 89 29 44 39 b3 a0 04
00 00 7d 3a 41 8b 44 24 78 85 c0 74 13 48 8b 93 78 04 00 00 48 83 e2 fc <39> 82
50 02 00 00 79 1e 44 89 b3 a0 04 00 00 48 8d bb d0 03 00 00
<4>[ 354.473515] RSP: 0018:c91bba90 EFLAGS: 00010046
<4>[ 354.473524] RAX: 0003 RBX: 8882624c8008 RCX:
f34a7378
<4>[ 354.473535] RDX: RSI: RDI:
8882624c8048
<4>[ 354.473545] RBP: c91bbab0 R08: 5963f1f1 R09:
<4>[ 354.473556] R10: c91bba10 R11: 8882624c8060 R12:
88824fdd7b98
<4>[ 354.473567] R13: 88824fdd7bb8 R14: 0001 R15:
88824fdd7750
<4>[ 354.473578] FS: 7f44b4b5b980() GS:888277e0()
knlGS:
<4>[ 354.473590] CS: 0010 DS: ES: CR0: 80050033
<4>[ 354.473599] CR2: 0250 CR3: 00026976e000 CR4:
00340ef0
<4>[ 354.473611] Call Trace:
<4>[ 354.473622] ? lock_acquire+0xa6/0x1c0
<4>[ 354.473677] ? i915_schedule_bump_priority+0x57/0xd0 [i915]
<4>[ 354.473736] i915_schedule_bump_priority+0x72/0xd0 [i915]
<4>[ 354.473792] i915_request_wait+0x4db/0x840 [i915]
<4>[ 354.473804] ? get_pwq.isra.4+0x2c/0x50
<4>[ 354.473813] ? ___preempt_schedule+0x16/0x18
<4>[ 354.473824] ? wake_up_q+0x70/0x70
<4>[ 354.473831] ? wake_up_q+0x70/0x70
<4>[ 354.473882] ? gen6_rps_boost+0x118/0x120 [i915]
<4>[ 354.473936] i915_gem_object_wait_fence+0x8a/0x110 [i915]
<4>[ 354.473991] i915_gem_object_wait+0x113/0x500 [i915]
<4>[ 354.474047] i915_gem_wait_ioctl+0x11c/0x2f0 [i915]
<4>[ 354.474101] ? i915_gem_unset_wedged+0x210/0x210 [i915]
<4>[ 354.474113] drm_ioctl_kernel+0x81/0xf0
<4>[ 354.474123] drm_ioctl+0x2de/0x390
<4>[ 354.474175] ? i915_gem_unset_wedged+0x210/0x210 [i915]
<4>[ 354.474187] ? finish_task_switch+0x95/0x260
<4>[ 354.474197] ? lock_acquire+0xa6/0x1c0
<4>[ 354.474207] do_vfs_ioctl+0xa0/0x6e0
<4>[ 354.474217] ? __fget+0xfc/0x1e0
<4>[ 354.474225] ksys_ioctl+0x35/0x60
<4>[ 354.474233] __x64_sys_ioctl+0x11/0x20
<4>[ 354.474241] do_syscall_64+0x55/0x190
<4>[ 354.474251] entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4>[ 354.474260] RIP: 0033:0x7f44b3de65d7
<4>[ 354.474267] Code: b3 66 90 48 8b 05 b1 48 2d 00 64 c7 00 26 00 00 00 48
c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d
01 f0 ff ff 73 01 c3 48 8b 0d 81 48 2d 00 f7 d8 64 89 01 48
<4>[ 354.474293] RSP: 002b:7fff974948e8 EFLAGS: 0246 ORIG_RAX:
0010
<4>[ 354.474305] RAX: ffda RBX: RCX:
7f44b3de65d7
<4>[ 354.474316] RDX: 7fff97494940 RSI: c010646c RDI:
0007
<4>[ 354.474327] RBP: 7fff97494940 R08: R09:
7f44b40bbc40
<4>[ 354.474337] R10: R11: 0246 R12:
c010646c
<4>[ 354.474348] R13: 0007 R14: R15:
v2: Avoid floating requests.
v3: Can't call dma_fence_signal() under the timeline lock!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 56 ++---
drivers/gpu/drm/i915/intel_lrc.c| 13 --
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +-
3 files changed, 33 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..0eaa8a6f0423 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3308,16 +3308,6 @@ void i915_gem_reset_finish(struct drm_i915_private
*dev_priv)
}
static void nop_submit_request(struct i915_request *request)
-{
- GEM_TRACE("%s fence %llx:%d -> -EIO\n",
- request->engine->name,
- request->fence.context, request->fence.seqno);
- dma_fence_set_error(&request->fence, -EIO);
-
- i915_request_submit(request);
-}
-
-static void nop_complete_submit_request(struct i915_request *request)
{
unsigned long flags;
@@ -3330,6 +3320,8 @@ static void nop_complete_submit_request(struct
i915_request *request)
__i915_request_submit(request);
intel_engine_init_global_seqno(re
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
Quoting Tvrtko Ursulin (2018-11-30 08:02:54) > From: Tvrtko Ursulin > > The test was missing some magic ingredients to actually trigger the > resets. > > In case of the full reset we need the I915_RESET_HANDOFF flag set, and in > case of engine reset we need a busy request. > > Thanks to Chris for helping with reset magic. > > Signed-off-by: Tvrtko Ursulin > Cc: Chris Wilson Thanks for fixing up my fail, Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/lease: Send a distinct uevent
On Thu, Nov 29, 2018 at 04:06:56PM -0800, Keith Packard wrote: > Daniel Vetter writes: > > > Cc: Keith Packard > > Reviewed-by: Keith Packard Thanks for review, pushed to drm-misc-fixes. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
== Series Details ==
Series: series starting with [1/2] drm/i915:
s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/
URL : https://patchwork.freedesktop.org/series/53275/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10961_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_10961_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10961_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_10961_full:
### IGT changes ###
Possible regressions
* igt@kms_draw_crc@draw-method-xrgb-pwrite-ytiled:
- shard-skl: NOTRUN -> FAIL
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
* igt@tools_test@tools_test:
- shard-kbl: PASS -> SKIP
Known issues
Here are the changes found in Patchwork_10961_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@drm_import_export@import-close-race-flink:
- shard-skl: PASS -> TIMEOUT [fdo#108667]
* igt@gem_exec_schedule@pi-ringfull-render:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: NOTRUN -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-offscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
- shard-skl: NOTRUN -> FAIL [fdo#105682] +3
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103167] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +4
* igt@kms_plane_scaling@pipe-b-scaler-with-rotation:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +2
* igt@kms_rotation_crc@primary-rotation-180:
- shard-skl: NOTRUN -> FAIL [fdo#103925] / [fdo#107815]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +7
* igt@pm_rpm@basic-pci-d3-state:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#108840] +1
Possible fixes
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_cursor_crc@cursor-256x256-dpms:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +2
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- {shard-iclb}: FAIL [fdo#103167] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -
Re: [Intel-gfx] [PATCH] drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
Quoting Randy Dunlap (2018-11-29 22:16:08)
> On 11/29/18 1:05 PM, Chris Wilson wrote:
> > 248 "multiple definition of ...". E.g.:
> >
> > LD [M] drivers/gpu/drm/i915/i915.o
> > ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume':
> > i915_irq.c:(.text+0x58f0): multiple definition of `intel_opregion_resume';
> > drivers/gpu/drm/i915/i915_drv.o:i915_drv.c:(.text+0x2d40): first defined
> > here
> >
> > Reported-by: Randy Dunlap
> > Reported-by: Stephen Rothwell
> > Fixes: a950adc6c343 ("drm/i915: Stop calling intel_opregion
> > unregister/register in suspend/resume")
> > Signed-off-by: Chris Wilson
>
> Acked-by: Randy Dunlap # build tested
And pushed, sorry for the noise.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/vgpu: Disallow loading on old vGPU hosts
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.
Reported-by: Mika Kuoppala
Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++
drivers/gpu/drm/i915/intel_lrc.c| 32 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ---
3 files changed, 23 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e39016713464..3e5e2efce670 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1384,6 +1384,20 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
}
}
+ if (HAS_EXECLISTS(dev_priv)) {
+ /*
+* Older GVT emulation depends upon intercepting CSB mmio,
+* which we no longer use, preferring to use the HWSP cache
+* instead.
+*/
+ if (intel_vgpu_active(dev_priv) &&
+ !intel_vgpu_has_hwsp_emulation(dev_priv)) {
+ i915_report_error(dev_priv,
+ "old vGPU host found, support for
HWSP emulation required\n");
+ return -ENXIO;
+ }
+ }
+
intel_sanitize_options(dev_priv);
i915_perf_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a690c557113..1848ca2bf9ee 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -748,6 +748,8 @@ execlists_cancel_port_requests(struct
intel_engine_execlists * const execlists)
static void reset_csb_pointers(struct intel_engine_execlists *execlists)
{
+ const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+
/*
* After a reset, the HW starts writing into CSB entry [0]. We
* therefore have to set our HEAD pointer back one entry so that
@@ -757,8 +759,8 @@ static void reset_csb_pointers(struct
intel_engine_execlists *execlists)
* inline comparison of our cached head position against the last HW
* write works even before the first interrupt.
*/
- execlists->csb_head = execlists->csb_write_reset;
- WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
+ execlists->csb_head = reset_value;
+ WRITE_ONCE(*execlists->csb_write, reset_value);
}
static void nop_submission_tasklet(unsigned long data)
@@ -2213,12 +2215,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
logical_ring_default_irqs(engine);
}
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
- /* Older GVT emulation depends upon intercepting CSB mmio */
- return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
-}
-
static int logical_ring_init(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -2250,22 +2246,12 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
execlists->csb_read =
i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
- if (csb_force_mmio(i915)) {
- execlists->csb_status = (u32 __force *)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
-
- execlists->csb_write = (u32 __force *)execlists->csb_read;
- execlists->csb_write_reset =
- _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
- GEN8_CSB_ENTRIES - 1);
- } else {
- execlists->csb_status =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ execlists->csb_status =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+
+ execlists->csb_write =
+ &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
- execlists->csb_write =
-
&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
- execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
- }
reset_csb_pointers(execlists);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 970fb5c05c36..2f7d1ce54f1e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -338,15 +338,6 @@ struct intel_engine_execlists {
*/
u32 preempt_complete_status;
- /**
-* @csb_write_reset: reset value for CSB write pointer
-*
-*
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim checkpatch origin/drm-tip bcfddfda17f5 drm/i915/selftests: Extract spinner code -:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #29: new file mode 100644 -:34: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #34: FILE: drivers/gpu/drm/i915/selftests/igt_spinner.c:1: +/* -:239: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #239: FILE: drivers/gpu/drm/i915/selftests/igt_spinner.h:1: +/* total: 0 errors, 3 warnings, 0 checks, 755 lines checked dc4e63c0e82f drm/i915/selftests: Fix live_workarounds to actually do resets ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Extract spinner code +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915/selftests: Fix live_workarounds to actually do resets Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53298/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_10975 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: PASS -> FAIL [fdo#108880]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-apl-guc: DMESG-WARN [fdo#108566] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
Participating hosts (50 -> 43)
--
Additional (1): fi-icl-y
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-pnv-d510
Build changes
-
* Linux: CI_DRM_5230 -> Patchwork_10975
CI_DRM_5230: b0a2de64f8969163f6e01071d5e05748f18a8bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10975: dc4e63c0e82fe413f33149832a5581f4a7a64887 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dc4e63c0e82f drm/i915/selftests: Fix live_workarounds to actually do resets
bcfddfda17f5 drm/i915/selftests: Extract spinner code
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10975/
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging
== Series Details == Series: series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53308/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1826a0f0e99f drm/i915: Complete the fences as they are cancelled due to wedging -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: <1>[ 354.473346] BUG: unable to handle kernel NULL pointer dereference at 0250 total: 0 errors, 1 warnings, 0 checks, 143 lines checked 7457cba9434a drm/i915/ringbuffer: Clear semaphore sync registers on ring init e0e3ac8bdd61 drm/i915: Allocate a common scratch page e5832e383cc9 drm/i915/selftests: Terminate hangcheck sanitycheck forcibly 725e7b22dc50 drm/i915/selftests: Reorder request allocation vs vma pinning c19b34b6c7fe drm/i915: Pipeline PDP updates for Braswell ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging
== Series Details == Series: series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53308/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Complete the fences as they are cancelled due to wedging Okay! Commit: drm/i915/ringbuffer: Clear semaphore sync registers on ring init Okay! Commit: drm/i915: Allocate a common scratch page -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) Commit: drm/i915/selftests: Terminate hangcheck sanitycheck forcibly Okay! Commit: drm/i915/selftests: Reorder request allocation vs vma pinning Okay! Commit: drm/i915: Pipeline PDP updates for Braswell Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/8] drm/i915: Introduce per-engine workarounds
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far the registers in 0x2xxx and
0xbxxx address range have been identified to be affected.
This losing of applied workarounds has obvious negative effects and can
even lead to hard system hangs (see the linked Bugzilla).
Rather than just restoring this re-application, because we have also
observed that it is not safe to just re-write all GT workarounds after
engine resets (GPU might be live and weird hardware states can happen),
we introduce a new class of per-engine workarounds and move only the
affected GT workarounds over.
Using the framework introduced in the previous patch, we therefore after
engine reset, re-apply only the workarounds living in the affected MMIO
address ranges.
Signed-off-by: Tvrtko Ursulin
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945
Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds")
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +
drivers/gpu/drm/i915/intel_workarounds.c | 249 +--
drivers/gpu/drm/i915/intel_workarounds.h | 3 +
5 files changed, 148 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 759c0fd58f8c..ef5d202e9d45 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -723,6 +723,8 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
__intel_context_unpin(i915->kernel_context, engine);
i915_timeline_fini(&engine->timeline);
+
+ intel_wa_list_free(&engine->wa_list);
}
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 11f4e6148557..dfafc3f710d6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1617,6 +1617,8 @@ static bool unexpected_starting_state(struct
intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
+ intel_engine_workarounds_apply(engine);
+
intel_mocs_init_engine(engine);
intel_engine_reset_breadcrumbs(engine);
@@ -2314,6 +2316,8 @@ int logical_render_ring_init(struct intel_engine_cs
*engine)
ret);
}
+ intel_engine_workarounds_init(engine);
+
return 0;
err_cleanup_common:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8a2270b209b0..c5ff3d31cab7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -15,6 +15,7 @@
#include "i915_selftest.h"
#include "i915_timeline.h"
#include "intel_gpu_commands.h"
+#include "intel_workarounds.h"
struct drm_printer;
struct i915_sched_attr;
@@ -451,6 +452,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
+ struct i915_wa_list wa_list;
struct i915_vma *scratch;
u32 irq_keep_mask; /* always keep these interrupts */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index ff20ebf9e040..be63a2af3481 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -653,17 +653,6 @@ static void gen9_gt_workarounds_init(struct
drm_i915_private *dev_priv)
{
struct i915_wa_list *wal = &dev_priv->gt_wa_list;
- /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal,
-GEN9_CSFE_CHICKEN1_RCS,
-GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
-
-
- /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
- wa_write_or(wal,
- BDW_SCRATCH1,
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
-
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(dev_priv))
wa_write_or(wal,
@@ -685,24 +674,6 @@ static void gen9_gt_workarounds_init(struct
drm_i915_private *dev_priv)
wa_write_or(wal,
GAM_ECOCHK,
BDW_DISABLE_HDC_INVALIDATION);
-
- /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
- if (IS_GEN9_LP(dev_priv))
- wa_write_masked_or(wal,
- GEN8_L3SQCREG1,
- L3_PRIO_CREDITS_MASK,
-
[Intel-gfx] [PATCH 0/8] Restore workarounds after engine reset and unify their handling
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was discovered to be unsafe to simply re-apply all of them, against
a possibly active GPU, and potentially from IRQ context, the approach taken was
to split GT workarounds and per-engine workarounds. Latter so far contain the
ones living in the 0x2xxx and 0xbxxx range, which were empirically shown to be
lost after RCS reset.
This way only a smaller set of affected workarounds can be applied after engine
resetm, which is done with irq safe read-modify-write cycle.
The series is structured like this so first two patches are as standalone as
possible so it is easy (easier) to backport them. The rest of the series
cleans up the whole workaround handling by moving all four classes of them to a
common framework.
Tvrtko Ursulin (8):
drm/i915: Record GT workarounds in a list
drm/i915: Introduce per-engine workarounds
drm/i915: Verify GT workaround state at runtime
drm/i915: Verify engine workaround state at runtime
drm/i915/selftests: Add tests for GT and engine workaround
verification
drm/i915: Move register white-listing to the common workaround
framework
drm/i915: Fuse per-context workaround handling with the common
framework
drm/i915: Trim unused workaround list entries
drivers/gpu/drm/i915/i915_debugfs.c | 11 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +
drivers/gpu/drm/i915/i915_drv.h | 18 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 3 +
drivers/gpu/drm/i915/intel_lrc.c | 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +
drivers/gpu/drm/i915/intel_workarounds.c | 896 +++---
drivers/gpu/drm/i915/intel_workarounds.h | 33 +-
.../drm/i915/selftests/intel_workarounds.c| 130 ++-
11 files changed, 726 insertions(+), 393 deletions(-)
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: Verify engine workaround state at runtime
From: Tvrtko Ursulin
Analogue to the previous patch we add at runtime verification that after
engine reset all respective workarounds have been correctly applied.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
drivers/gpu/drm/i915/intel_workarounds.h | 2 ++
3 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 14d019c9455b..a5add317a06b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2382,6 +2382,9 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
if (ret)
goto out;
+ /* Catch engine workarounds not restored by engine re-init. */
+ intel_engine_workarounds_verify(engine, engine->name);
+
out:
intel_engine_cancel_stop_cs(engine);
i915_gem_reset_finish_engine(engine);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index a5c0d206b2a4..2d17d8a36a57 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1313,6 +1313,12 @@ void intel_engine_workarounds_apply(struct
intel_engine_cs *engine)
wa_list_apply(engine->i915, &engine->wa_list);
}
+void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+const char *from)
+{
+ wa_list_verify(engine->i915, &engine->wa_list, from);
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/intel_workarounds.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
b/drivers/gpu/drm/i915/intel_workarounds.h
index 845c18dc110d..f72cfda32d68 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -40,5 +40,7 @@ void intel_whitelist_workarounds_apply(struct intel_engine_cs
*engine);
void intel_engine_workarounds_init(struct intel_engine_cs *engine);
void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
+void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+const char *from);
#endif
--
2.19.1
___
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[Intel-gfx] [PATCH 1/8] drm/i915: Record GT workarounds in a list
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is allocated on demand as workarounds are added to the list.
This is a temporary implementation which later in the series gets fused
with the existing per context workaround list handling. It is separated at
this stage since the following patch fixes a bug which needs to be as easy
to backport as possible.
Also, since in the following patch we will be adding a new class of
workarounds (per engine) which can be applied from interrupt context, we
straight away make the provision for safe read-modify-write cycle.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/intel_workarounds.c | 443 +++
drivers/gpu/drm/i915/intel_workarounds.h | 22 ++
5 files changed, 327 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e39016713464..2f3dc1cf83a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1453,6 +1453,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
intel_uncore_sanitize(dev_priv);
+ intel_gt_workarounds_init(dev_priv);
i915_gem_load_init_fences(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43ac6873a2bb..9ddbcc1f3554 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -69,6 +69,7 @@
#include "intel_ringbuffer.h"
#include "intel_uncore.h"
#include "intel_wopcm.h"
+#include "intel_workarounds.h"
#include "intel_uc.h"
#include "i915_gem.h"
@@ -1652,6 +1653,7 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
struct i915_workarounds workarounds;
+ struct i915_wa_list gt_wa_list;
struct i915_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..18adb3dd1fcd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5706,6 +5706,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_contexts_fini(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ intel_wa_list_free(&dev_priv->gt_wa_list);
+
intel_cleanup_gt_powersave(dev_priv);
intel_uc_fini_misc(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index e5cd6c6c66c3..ff20ebf9e040 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,6 +48,18 @@
* - Public functions to init or apply the given workaround type.
*/
+static void wa_init_start(struct i915_wa_list *wal, const char *name)
+{
+ wal->name = name;
+}
+
+static void wa_init_finish(struct i915_wa_list *wal)
+{
+ if (wal->count)
+ DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
+wal->count, wal->name);
+}
+
static void wa_add(struct drm_i915_private *i915,
i915_reg_t reg, const u32 mask, const u32 val)
{
@@ -575,28 +587,88 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
return 0;
}
-static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static void
+wal_add(struct i915_wa_list *wal, const struct i915_wa *wa)
+{
+ const unsigned int grow = 4;
+
+ if (wal->__size == wal->count) {
+ struct i915_wa *list;
+
+ list = kcalloc(wal->__size + grow, sizeof(*wa), GFP_KERNEL);
+ if (!list) {
+ DRM_ERROR("No space for workaround init!\n");
+ return;
+ }
+
+ if (wal->list)
+ memcpy(list, wal->list, sizeof(*wa) * wal->count);
+
+ wal->list = list;
+ wal->__size += grow;
+ }
+
+ memcpy(&wal->list[wal->count], wa, sizeof(*wa));
+ wal->count++;
+}
+
+static void
+wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = val,
+ .val = _MASKED_BIT_ENABLE(val)
+ };
+
+ wal_add(wal, &wa);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+ u32 val)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = mask,
+ .val = val
+ };
+
+ wal_add(wal, &wa);
}
-static void chv_gt_workarounds
[Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 83 ---
drivers/gpu/drm/i915/intel_workarounds.h | 1 +
.../drm/i915/selftests/intel_workarounds.c| 40 -
6 files changed, 57 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ef5d202e9d45..496462d77ebc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -725,6 +725,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
i915_timeline_fini(&engine->timeline);
intel_wa_list_free(&engine->wa_list);
+ intel_wa_list_free(&engine->whitelist);
}
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dfafc3f710d6..4eead104cd9c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2316,6 +2316,7 @@ int logical_render_ring_init(struct intel_engine_cs
*engine)
ret);
}
+ intel_whitelist_workarounds_init(engine);
intel_engine_workarounds_init(engine);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c5ff3d31cab7..91a750e90dc4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -453,6 +453,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
struct i915_wa_list wa_list;
+ struct i915_wa_list whitelist;
struct i915_vma *scratch;
u32 irq_keep_mask; /* always keep these interrupts */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index a21a21855e6a..21964209d970 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1032,29 +1032,20 @@ bool intel_gt_workarounds_verify(struct
drm_i915_private *dev_priv,
return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
}
-struct whitelist {
- i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
- unsigned int count;
- u32 nopid;
-};
-
-static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
- return;
-
- w->reg[w->count++] = reg;
-}
+ struct i915_wa wa = {
+ .reg = reg
+ };
-static void bdw_whitelist_build(struct whitelist *w)
-{
-}
+ if (GEM_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
+ return;
-static void chv_whitelist_build(struct whitelist *w)
-{
+ wal_add(wal, &wa);
}
-static void gen9_whitelist_build(struct whitelist *w)
+static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
@@ -1066,7 +1057,7 @@ static void gen9_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_HDC_CHICKEN1);
}
-static void skl_whitelist_build(struct whitelist *w)
+static void skl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1074,12 +1065,12 @@ static void skl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void bxt_whitelist_build(struct whitelist *w)
+static void bxt_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
}
-static void kbl_whitelist_build(struct whitelist *w)
+static void kbl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1087,7 +1078,7 @@ static void kbl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void glk_whitelist_build(struct whitelist *w)
+static void glk_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1095,18 +1086,18 @@ static void glk_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
}
-static void cfl_whitelist_build(struct whitelist *w)
+static void cfl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
}
-static void cnl_whitelist_build(struct whitelist *w)
+static void cnl_whitelist_build(struct i915_wa_list *w)
{
/* WaEnablePreemptionGranularityControlByUMD:cnl */
whiteli
[Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index de2bddbc64b4..abfe4b530c23 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const
char *name)
static void wa_init_finish(struct i915_wa_list *wal)
{
+ /* Trim unused entries. */
+ if (wal->count < wal->__size) {
+ struct i915_wa *wa =
+ kcalloc(wal->count, sizeof(*wa), GFP_KERNEL);
+
+ if (wa) {
+ memcpy(wa, wal->list, sizeof(*wa) * wal->count);
+ kfree(wal->list);
+ wal->list = wa;
+ wal->__size = wal->count;
+ }
+ }
+
if (wal->count)
DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
wal->wa_count, wal->name);
--
2.19.1
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
At this stage these are the driver initialization and engine reset.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++
drivers/gpu/drm/i915/i915_gem.c | 3 ++
drivers/gpu/drm/i915/intel_workarounds.c | 46
drivers/gpu/drm/i915/intel_workarounds.h | 2 ++
4 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f3dc1cf83a6..14d019c9455b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -53,6 +53,7 @@
#include "i915_vgpu.h"
#include "intel_drv.h"
#include "intel_uc.h"
+#include "intel_workarounds.h"
static struct drm_driver driver;
@@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs *engine,
const char *msg)
goto out;
}
+ /* Catch GT workarounds affected by engine reset. */
+ intel_gt_workarounds_verify(engine->i915, engine->name);
+
/*
* The request that caused the hang is stuck on elsp, we know the
* active request and can drop it, adjust head to skip the offending
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 18adb3dd1fcd..1eff471d4366 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+ /* Apply the GT workarounds... */
intel_gt_workarounds_apply(dev_priv);
+ /* ...and determine whether they are sticking. */
+ intel_gt_workarounds_verify(dev_priv, "init");
i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index be63a2af3481..a5c0d206b2a4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -981,6 +981,52 @@ void intel_gt_workarounds_apply(struct drm_i915_private
*dev_priv)
wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
}
+static void
+wa_fail(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
+{
+ DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x,
mask=%x)\n",
+ name, from,
+ i915_mmio_reg_offset(wa->reg),
+ cur, cur & wa->mask, wa->val, wa->mask);
+}
+
+static void
+wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
+ const char *from)
+{
+ u32 bits = wa->mask;
+ u32 cur_ = cur;
+ u32 val_ = wa->val;
+
+ while (bits) {
+ if ((bits & 1) && ((cur_ & 1) != (val_ & 1))) {
+ wa_fail(wa, cur, name, from);
+ break;
+ }
+
+ bits >>= 1;
+ cur_ >>= 1;
+ val_ >>= 1;
+ }
+}
+
+static void wa_list_verify(struct drm_i915_private *dev_priv,
+ const struct i915_wa_list *wal,
+ const char *from)
+{
+ struct i915_wa *wa;
+ unsigned int i;
+
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
+ wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
+}
+
+void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+const char *from)
+{
+ wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+}
+
struct whitelist {
i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
unsigned int count;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
b/drivers/gpu/drm/i915/intel_workarounds.h
index 2998767d51ca..845c18dc110d 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -33,6 +33,8 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
+void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+const char *from);
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
--
2.19.1
___
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[Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration of all four classes of workarounds onto the
common framework.
Existing macros are kept untouched for smaller code churn.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +-
drivers/gpu/drm/i915/i915_drv.h | 16 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/intel_workarounds.c | 267 ++-
drivers/gpu/drm/i915/intel_workarounds.h | 3 +-
6 files changed, 128 insertions(+), 176 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 129b9a6f8309..c65cbb990d02 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3375,13 +3375,14 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
- int i;
+ const struct i915_wa_list *wal = &node_to_i915(m->private)->wa_list;
+ struct i915_wa *wa;
+ unsigned int i;
- seq_printf(m, "Workarounds applied: %d\n", wa->count);
- for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "Workarounds applied: %u\n", wal->count);
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
- wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
+ i915_mmio_reg_offset(wa->reg), wa->val, wa->mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ddbcc1f3554..274e5c8b6c9a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1189,20 +1189,6 @@ struct i915_frontbuffer_tracking {
unsigned flip_bits;
};
-struct i915_wa_reg {
- u32 addr;
- u32 value;
- /* bitmask representing WA bits */
- u32 mask;
-};
-
-#define I915_MAX_WA_REGS 16
-
-struct i915_workarounds {
- struct i915_wa_reg reg[I915_MAX_WA_REGS];
- u32 count;
-};
-
struct i915_virtual_gpu {
bool active;
u32 caps;
@@ -1652,7 +1638,7 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
- struct i915_workarounds workarounds;
+ struct i915_wa_list wa_list;
struct i915_wa_list gt_wa_list;
struct i915_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1eff471d4366..0fcbc4ed6973 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5709,6 +5709,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_contexts_fini(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ intel_wa_list_free(&dev_priv->wa_list);
intel_wa_list_free(&dev_priv->gt_wa_list);
intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..aae7e13c7420 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -535,16 +535,12 @@ static bool needs_preempt_context(struct drm_i915_private
*i915)
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
- ret = intel_ctx_workarounds_init(dev_priv);
- if (ret)
- return ret;
-
+ intel_ctx_workarounds_init(dev_priv);
init_contexts(dev_priv);
/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 21964209d970..de2bddbc64b4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -57,61 +57,85 @@ static void wa_init_finish(struct i915_wa_list *wal)
{
if (wal->count)
DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
-wal->count, wal->name);
+wal->wa_count, wal->name);
}
-static void wa_add(struct drm_i915_private *i915,
- i915_reg_t reg, const u32 mask, const u32 val)
+static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
{
- struct i915_workarounds *wa = &i915->workarounds;
- unsigned int start = 0, end = wa->count;
- unsigned int addr = i915_mmio_reg_offset(re
[Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 21 +++--
drivers/gpu/drm/i915/intel_workarounds.h | 4 +-
.../drm/i915/selftests/intel_workarounds.c| 90 +++
3 files changed, 105 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 2d17d8a36a57..a21a21855e6a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -990,7 +990,7 @@ wa_fail(const struct i915_wa *wa, u32 cur, const char
*name, const char *from)
cur, cur & wa->mask, wa->val, wa->mask);
}
-static void
+static bool
wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
const char *from)
{
@@ -1001,30 +1001,35 @@ wa_verify_bits(const struct i915_wa *wa, u32 cur, const
char *name,
while (bits) {
if ((bits & 1) && ((cur_ & 1) != (val_ & 1))) {
wa_fail(wa, cur, name, from);
- break;
+ return false;
}
bits >>= 1;
cur_ >>= 1;
val_ >>= 1;
}
+
+ return true;
}
-static void wa_list_verify(struct drm_i915_private *dev_priv,
+static bool wa_list_verify(struct drm_i915_private *dev_priv,
const struct i915_wa_list *wal,
const char *from)
{
struct i915_wa *wa;
unsigned int i;
+ bool res = true;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
+ res &= wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
+
+ return res;
}
-void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
const char *from)
{
- wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+ return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
}
struct whitelist {
@@ -1313,10 +1318,10 @@ void intel_engine_workarounds_apply(struct
intel_engine_cs *engine)
wa_list_apply(engine->i915, &engine->wa_list);
}
-void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
const char *from)
{
- wa_list_verify(engine->i915, &engine->wa_list, from);
+ return wa_list_verify(engine->i915, &engine->wa_list, from);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
b/drivers/gpu/drm/i915/intel_workarounds.h
index f72cfda32d68..8f664d8b9e08 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -33,14 +33,14 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
-void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
const char *from);
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
void intel_engine_workarounds_init(struct intel_engine_cs *engine);
void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
-void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
const char *from);
#endif
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index 80396b3592f5..c009eb2af7fc 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -327,10 +327,100 @@ static int live_reset_whitelist(void *arg)
return err;
}
+static bool verify_gt_engine_wa(struct drm_i915_private *i915, const char *str)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ bool ok = true;
+
+ ok &= intel_gt_workarounds_verify(i915, str);
+
+ for_each_engine(engine, i915, id)
+ ok &= intel_engine_workarounds_verify(engine, str);
+
+ return ok;
+}
+
+static int
+live_gpu_reset_gt_engine_workarounds(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_gpu_error *error = &i915->gpu_error;
+ bool ok;
+
+ if (!intel_has_gpu_reset(i915))
+ return 0;
+
+
Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
Quoting Tvrtko Ursulin (2018-11-30 11:31:56) > From: Tvrtko Ursulin > > Since we now have all the GT workarounds in a table, by adding a simple > shared helper function we can now verify that their values are still > applied after some interesting events in the lifetime of the driver. > > At this stage these are the driver initialization and engine reset. > > Signed-off-by: Tvrtko Ursulin > --- > drivers/gpu/drm/i915/i915_drv.c | 4 +++ > drivers/gpu/drm/i915/i915_gem.c | 3 ++ > drivers/gpu/drm/i915/intel_workarounds.c | 46 > drivers/gpu/drm/i915/intel_workarounds.h | 2 ++ > 4 files changed, 55 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 2f3dc1cf83a6..14d019c9455b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -53,6 +53,7 @@ > #include "i915_vgpu.h" > #include "intel_drv.h" > #include "intel_uc.h" > +#include "intel_workarounds.h" > > static struct drm_driver driver; > > @@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs *engine, > const char *msg) > goto out; > } > > + /* Catch GT workarounds affected by engine reset. */ > + intel_gt_workarounds_verify(engine->i915, engine->name); I'd rather, quite strongly, not have this inside i915_reset_engine() itself. i915_reset_engine() is [designed to be] called from atomic context. Adding I915_READ() here is questionable. My preference is to have all this inside selftests/intel_workarounds where we can cross check the gt/all-engines after device reset and other engine reset. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification
Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
> From: Tvrtko Ursulin
>
> Two simple selftests which test that both GT and engine workarounds are
> not lost after either a full GPU reset, or after the per-engine ones.
>
> (Including checks that one engine reset is not affecting workarounds not
> belonging to itself.)
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 21 +++--
> drivers/gpu/drm/i915/intel_workarounds.h | 4 +-
> .../drm/i915/selftests/intel_workarounds.c| 90 +++
> 3 files changed, 105 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index 2d17d8a36a57..a21a21855e6a 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -990,7 +990,7 @@ wa_fail(const struct i915_wa *wa, u32 cur, const char
> *name, const char *from)
> cur, cur & wa->mask, wa->val, wa->mask);
> }
>
> -static void
> +static bool
> wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
>const char *from)
> {
> @@ -1001,30 +1001,35 @@ wa_verify_bits(const struct i915_wa *wa, u32 cur,
> const char *name,
> while (bits) {
> if ((bits & 1) && ((cur_ & 1) != (val_ & 1))) {
> wa_fail(wa, cur, name, from);
> - break;
> + return false;
> }
>
> bits >>= 1;
> cur_ >>= 1;
> val_ >>= 1;
> }
> +
> + return true;
> }
>
> -static void wa_list_verify(struct drm_i915_private *dev_priv,
> +static bool wa_list_verify(struct drm_i915_private *dev_priv,
>const struct i915_wa_list *wal,
>const char *from)
> {
> struct i915_wa *wa;
> unsigned int i;
> + bool res = true;
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> - wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
> + res &= wa_verify_bits(wa, I915_READ(wa->reg), wal->name,
> from);
> +
> + return res;
> }
>
> -void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
> +bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
> const char *from)
> {
> - wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
> + return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
> }
>
> struct whitelist {
> @@ -1313,10 +1318,10 @@ void intel_engine_workarounds_apply(struct
> intel_engine_cs *engine)
> wa_list_apply(engine->i915, &engine->wa_list);
> }
>
> -void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
> +bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
> const char *from)
> {
> - wa_list_verify(engine->i915, &engine->wa_list, from);
> + return wa_list_verify(engine->i915, &engine->wa_list, from);
> }
>
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
> b/drivers/gpu/drm/i915/intel_workarounds.h
> index f72cfda32d68..8f664d8b9e08 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.h
> +++ b/drivers/gpu/drm/i915/intel_workarounds.h
> @@ -33,14 +33,14 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
>
> void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
> -void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
> +bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
> const char *from);
>
> void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
>
> void intel_engine_workarounds_init(struct intel_engine_cs *engine);
> void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
> -void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
> +bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
> const char *from);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> index 80396b3592f5..c009eb2af7fc 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
> @@ -327,10 +327,100 @@ static int live_reset_whitelist(void *arg)
> return err;
> }
>
> +static bool verify_gt_engine_wa(struct drm_i915_private *i915, const char
> *str)
> +{
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> + bool ok = true;
> +
> + ok &= intel_gt_workarounds_verify(i915, str);
> +
> + for_each_engine(engine, i915, id)
> + ok &= intel_engine_workarounds_v
Re: [Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework
Quoting Tvrtko Ursulin (2018-11-30 11:31:59)
> -static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
> +static void
> +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> {
> - if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
> - return;
> -
> - w->reg[w->count++] = reg;
> -}
> + struct i915_wa wa = {
> + .reg = reg
> + };
>
> -static void bdw_whitelist_build(struct whitelist *w)
> -{
> -}
> + if (GEM_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
We only need this code for pre-merge testing of patches as the build
list is static.
-Chris
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Re: [Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework
Quoting Tvrtko Ursulin (2018-11-30 11:32:00)
> From: Tvrtko Ursulin
>
> Convert the per context workaround handling code to run against the newly
> introduced common workaround framework and fuse the two to use the
> existing smarter list add helper, the one which does the sorted insert and
> merges registers where possible.
>
> This completes migration of all four classes of workarounds onto the
> common framework.
>
> Existing macros are kept untouched for smaller code churn.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> @@ -1652,7 +1638,7 @@ struct drm_i915_private {
>
> int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
>
> - struct i915_workarounds workarounds;
> + struct i915_wa_list wa_list;
> struct i915_wa_list gt_wa_list;
ctx_wa_list ?
-Chris
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging
== Series Details ==
Series: series starting with [1/6] drm/i915: Complete the fences as they are
cancelled due to wedging
URL : https://patchwork.freedesktop.org/series/53308/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10976
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53308/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_10976:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-u3}:PASS -> DMESG-WARN
* {igt@runner@aborted}:
- {fi-icl-u3}:NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_10976 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: PASS -> FAIL [fdo#108880]
* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-apl-guc: DMESG-WARN [fdo#108566] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
Participating hosts (50 -> 45)
--
Additional (1): fi-icl-y
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5230 -> Patchwork_10976
CI_DRM_5230: b0a2de64f8969163f6e01071d5e05748f18a8bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10976: c19b34b6c7fe784029535a8743bd098eb06cdadd @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c19b34b6c7fe drm/i915: Pipeline PDP updates for Braswell
725e7b22dc50 drm/i915/selftests: Reorder request allocation vs vma pinning
e5832e383cc9 drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
e0e3ac8bdd61 drm/i915: Allocate a common scratch page
7457cba9434a drm/i915/ringbuffer: Clear semaphore sync registers on ring init
1826a0f0e99f drm/i915: Complete the fences as they are cancelled due to wedging
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10976/
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries
Quoting Tvrtko Ursulin (2018-11-30 11:32:01)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/intel_workarounds.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index de2bddbc64b4..abfe4b530c23 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const
> char *name)
>
> static void wa_init_finish(struct i915_wa_list *wal)
> {
> + /* Trim unused entries. */
> + if (wal->count < wal->__size) {
> + struct i915_wa *wa =
> + kcalloc(wal->count, sizeof(*wa), GFP_KERNEL);
kcalloc followed by memcpy, what have you done with Tvrtko?
kmemdup ?
-Chris
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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
> From: Tvrtko Ursulin
>
> Since we now have all the GT workarounds in a table, by adding a simple
> shared helper function we can now verify that their values are still
> applied after some interesting events in the lifetime of the driver.
>
> At this stage these are the driver initialization and engine reset.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 +++
> drivers/gpu/drm/i915/i915_gem.c | 3 ++
> drivers/gpu/drm/i915/intel_workarounds.c | 46
> drivers/gpu/drm/i915/intel_workarounds.h | 2 ++
> 4 files changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2f3dc1cf83a6..14d019c9455b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -53,6 +53,7 @@
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> #include "intel_uc.h"
> +#include "intel_workarounds.h"
>
> static struct drm_driver driver;
>
> @@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs *engine,
> const char *msg)
> goto out;
> }
>
> + /* Catch GT workarounds affected by engine reset. */
> + intel_gt_workarounds_verify(engine->i915, engine->name);
> +
> /*
> * The request that caused the hang is stuck on elsp, we know the
> * active request and can drop it, adjust head to skip the offending
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 18adb3dd1fcd..1eff471d4366 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> + /* Apply the GT workarounds... */
> intel_gt_workarounds_apply(dev_priv);
> + /* ...and determine whether they are sticking. */
> + intel_gt_workarounds_verify(dev_priv, "init");
>
> i915_gem_init_swizzling(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index be63a2af3481..a5c0d206b2a4 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -981,6 +981,52 @@ void intel_gt_workarounds_apply(struct drm_i915_private
> *dev_priv)
> wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
> }
>
> +static void
> +wa_fail(const struct i915_wa *wa, u32 cur, const char *name, const char
> *from)
> +{
> + DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x,
> mask=%x)\n",
> + name, from,
> + i915_mmio_reg_offset(wa->reg),
> + cur, cur & wa->mask, wa->val, wa->mask);
> +}
> +
> +static void
> +wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
> + const char *from)
> +{
> + u32 bits = wa->mask;
> + u32 cur_ = cur;
> + u32 val_ = wa->val;
Make sure wa->mask is set to ~0u for whole registers, which it must be
for the wa_fail.
if ((cur ^ wa->val) & wa->mask) {
wa_fail(wa, cur, name, whom);
return false; /* make it bool now to save churn later? */
}
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/vgpu: Disallow loading on old vGPU hosts
Chris Wilson writes:
> Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> actually broke the force-mmio mode for our execlists implementation. No
> one noticed, so ergo no one is actually using an old vGPU host (where we
> required the older method) and so can simply remove the broken support.
>
> Reported-by: Mika Kuoppala
> Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
> Signed-off-by: Chris Wilson
> Cc: Tvrtko Ursulin
> Cc: Joonas Lahtinen
> Cc: Mika Kuoppala
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/i915_drv.c | 14 +++
> drivers/gpu/drm/i915/intel_lrc.c| 32 +++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ---
> 3 files changed, 23 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e39016713464..3e5e2efce670 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1384,6 +1384,20 @@ static int i915_driver_init_hw(struct drm_i915_private
> *dev_priv)
> }
> }
>
> + if (HAS_EXECLISTS(dev_priv)) {
> + /*
> + * Older GVT emulation depends upon intercepting CSB mmio,
> + * which we no longer use, preferring to use the HWSP cache
> + * instead.
> + */
> + if (intel_vgpu_active(dev_priv) &&
> + !intel_vgpu_has_hwsp_emulation(dev_priv)) {
> + i915_report_error(dev_priv,
> + "old vGPU host found, support for
> HWSP emulation required\n");
> + return -ENXIO;
> + }
> + }
> +
> intel_sanitize_options(dev_priv);
>
> i915_perf_init(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> b/drivers/gpu/drm/i915/intel_lrc.c
> index 0a690c557113..1848ca2bf9ee 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -748,6 +748,8 @@ execlists_cancel_port_requests(struct
> intel_engine_execlists * const execlists)
>
> static void reset_csb_pointers(struct intel_engine_execlists *execlists)
> {
> + const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
> +
> /*
>* After a reset, the HW starts writing into CSB entry [0]. We
>* therefore have to set our HEAD pointer back one entry so that
> @@ -757,8 +759,8 @@ static void reset_csb_pointers(struct
> intel_engine_execlists *execlists)
>* inline comparison of our cached head position against the last HW
>* write works even before the first interrupt.
>*/
> - execlists->csb_head = execlists->csb_write_reset;
> - WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
> + execlists->csb_head = reset_value;
> + WRITE_ONCE(*execlists->csb_write, reset_value);
> }
>
> static void nop_submission_tasklet(unsigned long data)
> @@ -2213,12 +2215,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
> logical_ring_default_irqs(engine);
> }
>
> -static bool csb_force_mmio(struct drm_i915_private *i915)
> -{
> - /* Older GVT emulation depends upon intercepting CSB mmio */
> - return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
> -}
> -
> static int logical_ring_init(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
> @@ -2250,22 +2246,12 @@ static int logical_ring_init(struct intel_engine_cs
> *engine)
>
> execlists->csb_read =
> i915->regs +
> i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
This can go too?
-Mika
> - if (csb_force_mmio(i915)) {
> - execlists->csb_status = (u32 __force *)
> - (i915->regs +
> i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
> -
> - execlists->csb_write = (u32 __force *)execlists->csb_read;
> - execlists->csb_write_reset =
> - _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
> - GEN8_CSB_ENTRIES - 1);
> - } else {
> - execlists->csb_status =
> - &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> + execlists->csb_status =
> + &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> +
> + execlists->csb_write =
> + &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
>
> - execlists->csb_write =
> -
> &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
> - execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
> - }
> reset_csb_pointers(execlists);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 970fb5c05c36..2f7d1ce54f1e 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@
Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
On 30/11/2018 11:38, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:31:56) From: Tvrtko Ursulin Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver. At this stage these are the driver initialization and engine reset. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.c | 4 +++ drivers/gpu/drm/i915/i915_gem.c | 3 ++ drivers/gpu/drm/i915/intel_workarounds.c | 46 drivers/gpu/drm/i915/intel_workarounds.h | 2 ++ 4 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2f3dc1cf83a6..14d019c9455b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -53,6 +53,7 @@ #include "i915_vgpu.h" #include "intel_drv.h" #include "intel_uc.h" +#include "intel_workarounds.h" static struct drm_driver driver; @@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) goto out; } + /* Catch GT workarounds affected by engine reset. */ + intel_gt_workarounds_verify(engine->i915, engine->name); I'd rather, quite strongly, not have this inside i915_reset_engine() itself. i915_reset_engine() is [designed to be] called from atomic context. Adding I915_READ() here is questionable. My preference is to have all this inside selftests/intel_workarounds where we can cross check the gt/all-engines after device reset and other engine reset. I wasn't sure myself how much value checking it here adds, but regarding I915_READs, they are happening during engine->init_hw anyway. So I don't think a few more would harm. But yes, as said, since I was unsure myself I am happy to drop this hunk. Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for Restore workarounds after engine reset and unify their handling
== Series Details == Series: Restore workarounds after engine reset and unify their handling URL : https://patchwork.freedesktop.org/series/53313/ State : failure == Summary == Applying: drm/i915: Record GT workarounds in a list Applying: drm/i915: Introduce per-engine workarounds Applying: drm/i915: Verify GT workaround state at runtime Applying: drm/i915: Verify engine workaround state at runtime Applying: drm/i915/selftests: Add tests for GT and engine workaround verification Applying: drm/i915: Move register white-listing to the common workaround framework error: sha1 information is lacking or useless (drivers/gpu/drm/i915/selftests/intel_workarounds.c). error: could not build fake ancestor Patch failed at 0006 drm/i915: Move register white-listing to the common workaround framework Use 'git am --show-current-patch' to see the failed patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vgpu: Disallow loading on old vGPU hosts
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10977
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53311/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_10977:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-u3}:PASS -> DMESG-WARN
* {igt@runner@aborted}:
- {fi-icl-u3}:NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_10977 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_coherency:
- fi-gdg-551: PASS -> DMESG-FAIL [fdo#107164]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-apl-guc: DMESG-WARN [fdo#108566] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107164]: https://bugs.freedesktop.org/show_bug.cgi?id=107164
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
Participating hosts (50 -> 43)
--
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900
fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5230 -> Patchwork_10977
CI_DRM_5230: b0a2de64f8969163f6e01071d5e05748f18a8bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10977: 2c6a54e8583e69035ef5cb888c0f04a93ae56a89 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2c6a54e8583e drm/i915/vgpu: Disallow loading on old vGPU hosts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10977/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
On 30/11/2018 09:53, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 08:02:54) From: Tvrtko Ursulin The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy request. Thanks to Chris for helping with reset magic. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Thanks for fixing up my fail, Reviewed-by: Chris Wilson Thanks, happy with v2 as well? (adds rpm over reset) Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3)
== Series Details ==
Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC
config to intel_crtc_state (rev3)
URL : https://patchwork.freedesktop.org/series/53184/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10963_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_10963_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10963_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_10963_full:
### IGT changes ###
Possible regressions
* igt@gem_eio@reset-stress:
- shard-glk: PASS -> FAIL
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_10963_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-skl: NOTRUN -> FAIL [fdo#103158] +1
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: PASS -> TIMEOUT [fdo#108039]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_psr@suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#107773]
* igt@kms_rmfb@close-fd:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +1
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
* igt@pm_rpm@legacy-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
* igt@pm_rpm@modeset-lpsp-stress:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> ( 2 FAIL ) [fdo#108315] / [fdo#108756]
Possible fixes
* igt@gem_userptr_blits@readonly-unsync:
- shard-skl: TIMEOUT [fdo#108887] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-b:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- {shard-iclb}: FAIL [fdo#103167] -> PASS
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107807] -> PASS
Warnings
* igt@i915_selftest@live_contex
Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets
Quoting Tvrtko Ursulin (2018-11-30 12:17:13) > > On 30/11/2018 09:53, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-30 08:02:54) > >> From: Tvrtko Ursulin > >> > >> The test was missing some magic ingredients to actually trigger the > >> resets. > >> > >> In case of the full reset we need the I915_RESET_HANDOFF flag set, and in > >> case of engine reset we need a busy request. > >> > >> Thanks to Chris for helping with reset magic. > >> > >> Signed-off-by: Tvrtko Ursulin > >> Cc: Chris Wilson > > > > Thanks for fixing up my fail, > > Reviewed-by: Chris Wilson > > Thanks, happy with v2 as well? (adds rpm over reset) Yup, was trying to save electrons :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/vgpu: Disallow loading on old vGPU hosts
Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
actually broke the force-mmio mode for our execlists implementation. No
one noticed, so ergo no one is actually using an old vGPU host (where we
required the older method) and so can simply remove the broken support.
v2: csb_read can go as well (Mika)
Reported-by: Mika Kuoppala
Fixes: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++
drivers/gpu/drm/i915/intel_lrc.c| 32 +++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 16 -
3 files changed, 22 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e39016713464..3e5e2efce670 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1384,6 +1384,20 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
}
}
+ if (HAS_EXECLISTS(dev_priv)) {
+ /*
+* Older GVT emulation depends upon intercepting CSB mmio,
+* which we no longer use, preferring to use the HWSP cache
+* instead.
+*/
+ if (intel_vgpu_active(dev_priv) &&
+ !intel_vgpu_has_hwsp_emulation(dev_priv)) {
+ i915_report_error(dev_priv,
+ "old vGPU host found, support for
HWSP emulation required\n");
+ return -ENXIO;
+ }
+ }
+
intel_sanitize_options(dev_priv);
i915_perf_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0a690c557113..bb5abd4f7516 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -748,6 +748,8 @@ execlists_cancel_port_requests(struct
intel_engine_execlists * const execlists)
static void reset_csb_pointers(struct intel_engine_execlists *execlists)
{
+ const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
+
/*
* After a reset, the HW starts writing into CSB entry [0]. We
* therefore have to set our HEAD pointer back one entry so that
@@ -757,8 +759,8 @@ static void reset_csb_pointers(struct
intel_engine_execlists *execlists)
* inline comparison of our cached head position against the last HW
* write works even before the first interrupt.
*/
- execlists->csb_head = execlists->csb_write_reset;
- WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
+ execlists->csb_head = reset_value;
+ WRITE_ONCE(*execlists->csb_write, reset_value);
}
static void nop_submission_tasklet(unsigned long data)
@@ -2213,12 +2215,6 @@ logical_ring_setup(struct intel_engine_cs *engine)
logical_ring_default_irqs(engine);
}
-static bool csb_force_mmio(struct drm_i915_private *i915)
-{
- /* Older GVT emulation depends upon intercepting CSB mmio */
- return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
-}
-
static int logical_ring_init(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
@@ -2248,24 +2244,12 @@ static int logical_ring_init(struct intel_engine_cs
*engine)
upper_32_bits(ce->lrc_desc);
}
- execlists->csb_read =
- i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
- if (csb_force_mmio(i915)) {
- execlists->csb_status = (u32 __force *)
- (i915->regs +
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
+ execlists->csb_status =
+ &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
- execlists->csb_write = (u32 __force *)execlists->csb_read;
- execlists->csb_write_reset =
- _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
- GEN8_CSB_ENTRIES - 1);
- } else {
- execlists->csb_status =
- &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
+ execlists->csb_write =
+ &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
- execlists->csb_write =
-
&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
- execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
- }
reset_csb_pointers(execlists);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 970fb5c05c36..096043b784f0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -312,13 +312,6 @@ struct intel_engine_execlists {
*/
struct rb_root_cached qu
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)
On 29/11/2018 19:36, Rodrigo Vivi wrote:
> On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
>> Hi,
>>
>>> -Original Message-
>>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
>>> Of
>>> Rodrigo Vivi
>>> Sent: torstai 29. marraskuuta 2018 8.18
>>> To: Souza, Jose
>>> Cc: intel-gfx@lists.freedesktop.org
>>> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id
>>> following atomic guidelines (rev2)
>>>
>>> On Wed, Nov 28, 2018 at 02:13:12PM -0800, Souza, Jose wrote:
On Wed, 2018-11-28 at 21:02 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
> URL : https://patchwork.freedesktop.org/series/53132/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_10934 absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the
> changes
> introduced in Patchwork_10934, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false
> positives in CI.
>
> External URL:
> https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/m
> box/
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_10934:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live_sanitycheck:
> - fi-apl-guc: PASS -> DMESG-WARN
>
> * {igt@runner@aborted}:
> - fi-apl-guc: NOTRUN -> FAIL
Both are pretty much non related with display, what do you think
Rodrigo? It is a merge blocker?
>>>
>>> I got addicted to see all green on CI. So I always prefer to trigger a
>>> retest. So
>>> anyone following the link that is merged with the patch doens't have to
>>> understand and analyze why it was merged with BAT failure.
>>>
>>> I just triggered the re-test for this patch.
>> Martin, Arek, fyi, not preferred?
>
> Yes, I'd like to hear their opinion.
>
> On this case a simple BAT would be enough because we don't have PSR monitors
> on shrd ones.
> However most of the times trigger the retest is unavoidable because we need
> to make it to pass BAT and go for the full run.
>
> Besides the green-report-link reason I exposed above.
I agree that we should only push stuff when CI is green.
However, using the re-try button is the wrong way as it requires more
machine time, and it may hide low-probably issues introduced by the patch.
Instead, we should file/edit bugs and then ask cibuglog to re-send the
report. I have been doing this ofr a couple of people already, but we
need to advertise this more!
Martin
>
> Thanks,
> Rodrigo.
>
>>>
>>> Thanks,
>>> Rodrigo.
>>>
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_10934 that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@i915_selftest@live_hangcheck:
> - fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044]
>
> * igt@kms_pipe_crc_basic@read-crc-pipe-a:
> - fi-byt-clapper: PASS -> FAIL [fdo#107362]
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or
> FAILURE).
>
> [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
> [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
>
>
> Participating hosts (50 -> 44)
> --
>
> Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> squawks fi-bsw-cyan fi-ctg-p8600
>
>
> Build changes
> -
>
> * Linux: CI_DRM_5216 -> Patchwork_10934
>
> CI_DRM_5216: 2236cef56d19627516af1f1b19b155d65fbc9834 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_10934: 2ebde49b2d0906d8106b020a2b0480bc5f552a01 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 2ebde49b2d09 drm/i915/psr: Get pipe id following atomic guidelines
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10934/
>>>
>>>
>>> ___
>>> Intel-gfx mailing list
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Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
> Hi,
>
> I am looking for a way to export the color encoding and range selection
> to user space. I came across those properties and am wondering, why
> they are meant only for non RGB color encodings. Would it be okay, to
> modify them and use with RGB formats as well?
What you trying to do? Input limited range RGB data and expand to full
range?
>
> Regards,
> Chris
>
>
> On 02/19/2018 09:28 PM, Ville Syrjala wrote:
> > From: Jyri Sarha
> >
> > Add a standard optional properties to support different non RGB color
> > encodings in DRM planes. COLOR_ENCODING select the supported non RGB
> > color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
> > the value ranges within the selected color encoding. The properties
> > are stored to drm_plane object to allow different set of supported
> > encoding for different planes on the device.
> >
> > v2: Add/fix kerneldocs, verify bitmasks (danvet)
> >
> > Cc: Harry Wentland
> > Cc: Daniel Vetter
> > Cc: Daniel Stone
> > Cc: Russell King - ARM Linux
> > Cc: Ilia Mirkin
> > Cc: Hans Verkuil
> > Cc: Uma Shankar
> > Cc: Shashank Sharma
> > Reviewed-by: Ville Syrjälä
> > Signed-off-by: Jyri Sarha
> > [vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
> > Signed-off-by: Ville Syrjälä
> > Reviewed-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_atomic.c | 8 +++
> > drivers/gpu/drm/drm_color_mgmt.c | 103
> > +++
> > include/drm/drm_color_mgmt.h | 19
> > include/drm/drm_plane.h | 32
> > 4 files changed, 162 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> > index 46733d534587..452a0b0bafbc 100644
> > --- a/drivers/gpu/drm/drm_atomic.c
> > +++ b/drivers/gpu/drm/drm_atomic.c
> > @@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
> > drm_plane *plane,
> > state->rotation = val;
> > } else if (property == plane->zpos_property) {
> > state->zpos = val;
> > + } else if (property == plane->color_encoding_property) {
> > + state->color_encoding = val;
> > + } else if (property == plane->color_range_property) {
> > + state->color_range = val;
> > } else if (plane->funcs->atomic_set_property) {
> > return plane->funcs->atomic_set_property(plane, state,
> > property, val);
> > @@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
> > *val = state->rotation;
> > } else if (property == plane->zpos_property) {
> > *val = state->zpos;
> > + } else if (property == plane->color_encoding_property) {
> > + *val = state->color_encoding;
> > + } else if (property == plane->color_range_property) {
> > + *val = state->color_range;
> > } else if (plane->funcs->atomic_get_property) {
> > return plane->funcs->atomic_get_property(plane, state,
> > property, val);
> > } else {
> > diff --git a/drivers/gpu/drm/drm_color_mgmt.c
> > b/drivers/gpu/drm/drm_color_mgmt.c
> > index 0d002b045bd2..4b83e078d3e9 100644
> > --- a/drivers/gpu/drm/drm_color_mgmt.c
> > +++ b/drivers/gpu/drm/drm_color_mgmt.c
> > @@ -88,6 +88,20 @@
> >* drm_mode_crtc_set_gamma_size(). Drivers which support both should use
> >* drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp
> > with the
> >* "GAMMA_LUT" property above.
> > + *
> > + * Support for different non RGB color encodings is controlled through
> > + * &drm_plane specific COLOR_ENCODING and COLOR_RANGE properties. They
> > + * are set up by calling drm_plane_create_color_properties().
> > + *
> > + * "COLOR_ENCODING"
> > + * Optional plane enum property to support different non RGB
> > + * color encodings. The driver can provide a subset of standard
> > + * enum values supported by the DRM plane.
> > + *
> > + * "COLOR_RANGE"
> > + * Optional plane enum property to support different non RGB
> > + * color parameter ranges. The driver can provide a subset of
> > + * standard enum values supported by the DRM plane.
> >*/
> >
> > /**
> > @@ -339,3 +353,92 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
> > drm_modeset_unlock(&crtc->mutex);
> > return ret;
> > }
> > +
> > +static const char * const color_encoding_name[] = {
> > + [DRM_COLOR_YCBCR_BT601] = "ITU-R BT.601 YCbCr",
> > + [DRM_COLOR_YCBCR_BT709] = "ITU-R BT.709 YCbCr",
> > + [DRM_COLOR_YCBCR_BT2020] = "ITU-R BT.2020 YCbCr",
> > +};
> > +
> > +static const char * const color_range_name[] = {
> > + [DRM_COLOR_YCBCR_FULL_RANGE] = "YCbCr full range",
> > + [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range",
> > +};
> > +
> > +/**
> > + * drm_plane_create_color_properties - color encoding related plane
> > properties
> > + * @plane: plane object
> > + * @suppor
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
== Series Details ==
Series: drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)
URL : https://patchwork.freedesktop.org/series/53311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10979
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53311/revisions/2/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_10979:
### IGT changes ###
Possible regressions
* igt@kms_flip@basic-flip-vs-dpms:
- {fi-icl-u3}:PASS -> DMESG-WARN
* {igt@runner@aborted}:
- {fi-icl-u3}:NOTRUN -> FAIL
Known issues
Here are the changes found in Patchwork_10979 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160:PASS -> DMESG-FAIL [fdo#108735]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-apl-guc: DMESG-WARN [fdo#108566] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Participating hosts (50 -> 44)
--
Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600
Build changes
-
* Linux: CI_DRM_5230 -> Patchwork_10979
CI_DRM_5230: b0a2de64f8969163f6e01071d5e05748f18a8bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10979: 7d5f36355bfbbe1efd2cd901a6dbbbca400da0ad @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
7d5f36355bfb drm/i915/vgpu: Disallow loading on old vGPU hosts
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10979/
___
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Re: [Intel-gfx] [PATCH v11 01/23] drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions
a bit by moving the pll to port mapping and unmapping functions to the
ddi encoder hooks. This allows removal of a bunch of boilerplate code
from the functions.
Additionally, the ICL DSI encoder needs to do the clock gating and
ungating slightly differently, and this allows its own handling in a
clean fashion.
Looks good to me,
Reviewed-by: Madhav Chauhan
Regards,
Madhav
Cc: Madhav Chauhan
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_ddi.c | 84 +++-
drivers/gpu/drm/i915/intel_display.c | 6 ---
drivers/gpu/drm/i915/intel_drv.h | 6 ---
3 files changed, 34 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad11540ac436..7bad6c857b81 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2785,69 +2785,45 @@ uint32_t icl_dpclka_cfgcr0_clk_off(struct
drm_i915_private *dev_priv,
return 0;
}
-void icl_map_plls_to_ports(struct drm_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct drm_atomic_state *old_state)
+static void icl_map_plls_to_ports(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct drm_connector_state *conn_state;
- struct drm_connector *conn;
- int i;
-
- for_each_new_connector_in_state(old_state, conn, conn_state, i) {
- struct intel_encoder *encoder =
- to_intel_encoder(conn_state->best_encoder);
- enum port port;
- uint32_t val;
-
- if (conn_state->crtc != crtc)
- continue;
-
- port = encoder->port;
- mutex_lock(&dev_priv->dpll_lock);
+ enum port port = encoder->port;
+ u32 val;
- val = I915_READ(DPCLKA_CFGCR0_ICL);
- WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+ mutex_lock(&dev_priv->dpll_lock);
- if (intel_port_is_combophy(dev_priv, port)) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
- I915_WRITE(DPCLKA_CFGCR0_ICL, val);
- POSTING_READ(DPCLKA_CFGCR0_ICL);
- }
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
- val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ if (intel_port_is_combophy(dev_priv, port)) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+ val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
-
- mutex_unlock(&dev_priv->dpll_lock);
+ POSTING_READ(DPCLKA_CFGCR0_ICL);
}
+
+ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+
+ mutex_unlock(&dev_priv->dpll_lock);
}
-void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
-struct intel_crtc_state *crtc_state,
-struct drm_atomic_state *old_state)
+static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct drm_connector_state *old_conn_state;
- struct drm_connector *conn;
- int i;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
+ u32 val;
- for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
- struct intel_encoder *encoder =
- to_intel_encoder(old_conn_state->best_encoder);
- enum port port;
+ mutex_lock(&dev_priv->dpll_lock);
- if (old_conn_state->crtc != crtc)
- continue;
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
- port = encoder->port;
- mutex_lock(&dev_priv->dpll_lock);
- I915_WRITE(DPCLKA_CFGCR0_ICL,
- I915_READ(DPCLKA_CFGCR0_ICL) |
- icl_dpclka_cfgcr0_clk_off(dev_priv, port));
- mutex_unlock(&dev_priv->dpll_lock);
- }
+ mutex_unlock(&dev_priv->dpll_lock);
}
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
@@ -3208,6 +3184,9 @@ static void intel_ddi_pre_enable(struct intel_encoder
*enc
Re: [Intel-gfx] [PATCH v11 17/23] drm/i915/icl: add dummy DSI GPIO element execution function
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add dummy debug logging GPIO element execution function for ICL.
Looks fine to me.
Reviewed-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index b41ca6436401..a1a8b3790e61 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -336,6 +336,12 @@ static void bxt_exec_gpio(struct drm_i915_private
*dev_priv,
gpiod_set_value(gpio_desc, value);
}
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+ u8 gpio_source, u8 gpio_index, bool value)
+{
+ DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
+}
+
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -359,7 +365,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
*intel_dsi, const u8 *data)
/* pull up/down */
value = *data++ & 1;
- if (IS_VALLEYVIEW(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
___
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Re: [Intel-gfx] [PATCH v11 20/23] drm/i915/icl: add pll mapping for DSI
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Add encoder specific pll mapping for DSI. The differences with the DDI
version are big enough to warrant a separate function.
Cc: Madhav Chauhan
Cc: Vandita Kulkarni
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index e3aa9d3d2291..1907640a2e6a 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -570,6 +570,27 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder
*encoder)
mutex_unlock(&dev_priv->dpll_lock);
}
+static void gen11_dsi_map_pll(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+ enum port port;
+ u32 val;
+
+ mutex_lock(&dev_priv->dpll_lock);
+
+ val = I915_READ(DPCLKA_CFGCR0_ICL);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+ val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ }
+ I915_WRITE(DPCLKA_CFGCR0_ICL, val);
We need to read back DPCLKA_CFGCR0_ICL to ensure write completed before
next step as per BSPEC.
With this fix,
Reviewed-by: Madhav Chauhan
Regards,
Madhav
+
+ mutex_unlock(&dev_priv->dpll_lock);
+}
+
static void
gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
@@ -978,6 +999,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder
*encoder,
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ /* step3b */
+ gen11_dsi_map_pll(encoder, pipe_config);
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
___
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Re: [Intel-gfx] [PATCH v11 23/23] HACK: drm/i915/bios: ignore VBT not overflowing the mailbox
On 11/29/2018 7:42 PM, Jani Nikula wrote:
Some machines seem to have a broken opregion where the VBT overflows the
mailbox. Ignore this until properly fixed.
Right, otherwise DSI modeset doesn't progress further.
Acked-by: Madhav Chauhan
Regards,
Madhav
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_bios.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 0694aa8bb9bc..39e502ea557c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1706,7 +1706,6 @@ bool intel_bios_is_valid_vbt(const void *buf, size_t size)
bdb = get_bdb_header(vbt);
if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
DRM_DEBUG_DRIVER("BDB incomplete\n");
- return false;
}
return vbt;
___
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Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
On 11/2/2018 5:17 PM, Jani Nikula wrote: Next version of [1]. Sorry for the spam, needed to get the authorship straight. Fixed power domains and compute config hook initialization. Overall, with this series ICL DSI dual link video mode feature looks complete to me. Thanks!! Regards, Madhav BR, Jani. [1] https://patchwork.freedesktop.org/series/51011/ Jani Nikula (1): drm/i915/icl: add dummy DSI GPIO element execution function Madhav Chauhan (14): drm/i915/icl: Allocate DSI encoder/connector drm/i915/icl: Fill DSI ports info drm/i915/icl: Allocate DSI hosts and imlement host transfer drm/i915/icl: Add get config functionality for DSI drm/i915/icl: Get HW state for DSI encoder drm/i915/icl: Add DSI encoder remaining functions drm/i915/icl: Configure DSI Dual link mode drm/i915/icl: Consider DSI for getting transcoder state drm/i915/icl: Get pipe timings for DSI drm/i915/icl: Define missing bitfield for shortplug reg drm/i915/icl: Define Panel power ctrl register drm/i915/icl: Define display GPIO pins for DSI HACK: drm/i915/icl: Add changes to program DSI panel GPIOs HACK: drm/i915/icl: Configure backlight functions for DSI drivers/gpu/drm/i915/i915_reg.h | 12 + drivers/gpu/drm/i915/icl_dsi.c | 417 ++- drivers/gpu/drm/i915/intel_display.c | 34 ++- drivers/gpu/drm/i915/intel_dsi_vbt.c | 58 - drivers/gpu/drm/i915/intel_panel.c | 3 +- 5 files changed, 505 insertions(+), 19 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling
> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Madhav Chauhan > Sent: Friday, November 30, 2018 7:43 PM > To: Nikula, Jani ; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling > > On 11/2/2018 5:17 PM, Jani Nikula wrote: > > Next version of [1]. Sorry for the spam, needed to get the authorship > > straight. Fixed power domains and compute config hook initialization. > > Overall, with this series ICL DSI dual link video mode feature looks complete > to me. Thanks!! I meant for v11 :) > > Regards, > Madhav > > > > > BR, > > Jani. > > > > [1] https://patchwork.freedesktop.org/series/51011/ > > > > > > Jani Nikula (1): > >drm/i915/icl: add dummy DSI GPIO element execution function > > > > Madhav Chauhan (14): > >drm/i915/icl: Allocate DSI encoder/connector > >drm/i915/icl: Fill DSI ports info > >drm/i915/icl: Allocate DSI hosts and imlement host transfer > >drm/i915/icl: Add get config functionality for DSI > >drm/i915/icl: Get HW state for DSI encoder > >drm/i915/icl: Add DSI encoder remaining functions > >drm/i915/icl: Configure DSI Dual link mode > >drm/i915/icl: Consider DSI for getting transcoder state > >drm/i915/icl: Get pipe timings for DSI > >drm/i915/icl: Define missing bitfield for shortplug reg > >drm/i915/icl: Define Panel power ctrl register > >drm/i915/icl: Define display GPIO pins for DSI > >HACK: drm/i915/icl: Add changes to program DSI panel GPIOs > >HACK: drm/i915/icl: Configure backlight functions for DSI > > > > drivers/gpu/drm/i915/i915_reg.h | 12 + > > drivers/gpu/drm/i915/icl_dsi.c | 417 > ++- > > drivers/gpu/drm/i915/intel_display.c | 34 ++- > > drivers/gpu/drm/i915/intel_dsi_vbt.c | 58 - > > drivers/gpu/drm/i915/intel_panel.c | 3 +- > > 5 files changed, 505 insertions(+), 19 deletions(-) > > > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats
On Thu, Nov 29, 2018 at 09:39:52PM +, Strasser, Kevin wrote: > Ville Syrjälä wrote: > > On Wed, Nov 28, 2018 at 10:38:10PM -0800, Kevin Strasser wrote: > >> This series defines new formats and adds a plane property to be used for > >> floating point framebuffer content. Implementation is then added to i915. > >> > >> I have shared an IGT branch which adds test coverage for the new formats: > >> https://github.com/strassek/xorg-intel-gpu-tools/tree/fp16 > > > > Looks about similar as what I had written. I wrote my half<->full > > conversion thing from scratch which probably means it has more rounding > > errors and whatnot. The speed of mine wasn't exactly stellar and looks > > like your version probably has the same issue. So I was actually > > thinking of using the sse instructions meant for this > > could provide a nice speedup. I guess we might want the pure c version > > as a backup though. Hmm. Now I also seem to recall that I noticed > > there being a compiler intrinsic even for single value half<->full > > precision conversion. Did you look into using that (if I didn't imagine > > it)? > > You are thinking of vcvtps2ph and vcvtph2ps, I haven't yet had a chance to > give them a try, but I agree it seems like a good idea. > > > BTW I just rebased my fp16 for pre-icl platforms: > > git://github.com/vsyrjala/linux.git fp16_scanout_2 > > > > Apart from the ivb/hsw w/a there isn't all that much unexpected > > when it comes to fp16 on those platforms either. > > I don't mean to step on your toes with this series, were you waiting for / > working on a real usecase before pushing that code? I pretty much just did it so that I could test >10bpc gamma LUTs. But I got sidetracked by other things so I didn't really get even that far. Also another problem is that igt depends on cairo which didn't support rendering at >10bpc, so I couldn't really test that stuff properly even if I wanted to. Maarten has patches to wire up floats into cairo but I think he just said that it still kinda uses 8bpc precision only :( Anyways, the fact that you did icl and I did pre-icl is pretty good division of labour. Sometimes things work out by accident :) -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
Hi Ville,
As Christoph cannot respond till middle next week I can try to respond
in his absence, as I am familiar with the subject.
On 30.11.2018 14:25, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
>> Hi,
>>
>> I am looking for a way to export the color encoding and range selection
>> to user space. I came across those properties and am wondering, why
>> they are meant only for non RGB color encodings. Would it be okay, to
>> modify them and use with RGB formats as well?
> What you trying to do? Input limited range RGB data and expand to full
> range?
For example. But there are two more general questions, which
surprisingly we have not found answer for.
1. What color encoding and range drm should expect on its input RGB
buffers by default?
2. How userspace should inform drm that given buffer has specified
non-default color encoding and range?
Hopefully this patch introduces such properties but only for YCbCr
formats, the question is what should be the best way to expand it to RGB
formats:
A. Add another enums: DRM_COLOR_RGB_BT601 and friends.
B. Reuse current enums, but remove format information from them:
DRM_COLOR_YCBCR_BT601 => DRM_COLOR_BT601.
Regards
Andrzej
>
>> Regards,
>> Chris
>>
>>
>> On 02/19/2018 09:28 PM, Ville Syrjala wrote:
>>> From: Jyri Sarha
>>>
>>> Add a standard optional properties to support different non RGB color
>>> encodings in DRM planes. COLOR_ENCODING select the supported non RGB
>>> color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
>>> the value ranges within the selected color encoding. The properties
>>> are stored to drm_plane object to allow different set of supported
>>> encoding for different planes on the device.
>>>
>>> v2: Add/fix kerneldocs, verify bitmasks (danvet)
>>>
>>> Cc: Harry Wentland
>>> Cc: Daniel Vetter
>>> Cc: Daniel Stone
>>> Cc: Russell King - ARM Linux
>>> Cc: Ilia Mirkin
>>> Cc: Hans Verkuil
>>> Cc: Uma Shankar
>>> Cc: Shashank Sharma
>>> Reviewed-by: Ville Syrjälä
>>> Signed-off-by: Jyri Sarha
>>> [vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
>>> Signed-off-by: Ville Syrjälä
>>> Reviewed-by: Daniel Vetter
>>> ---
>>> drivers/gpu/drm/drm_atomic.c | 8 +++
>>> drivers/gpu/drm/drm_color_mgmt.c | 103
>>> +++
>>> include/drm/drm_color_mgmt.h | 19
>>> include/drm/drm_plane.h | 32
>>> 4 files changed, 162 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
>>> index 46733d534587..452a0b0bafbc 100644
>>> --- a/drivers/gpu/drm/drm_atomic.c
>>> +++ b/drivers/gpu/drm/drm_atomic.c
>>> @@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
>>> drm_plane *plane,
>>> state->rotation = val;
>>> } else if (property == plane->zpos_property) {
>>> state->zpos = val;
>>> + } else if (property == plane->color_encoding_property) {
>>> + state->color_encoding = val;
>>> + } else if (property == plane->color_range_property) {
>>> + state->color_range = val;
>>> } else if (plane->funcs->atomic_set_property) {
>>> return plane->funcs->atomic_set_property(plane, state,
>>> property, val);
>>> @@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
>>> *val = state->rotation;
>>> } else if (property == plane->zpos_property) {
>>> *val = state->zpos;
>>> + } else if (property == plane->color_encoding_property) {
>>> + *val = state->color_encoding;
>>> + } else if (property == plane->color_range_property) {
>>> + *val = state->color_range;
>>> } else if (plane->funcs->atomic_get_property) {
>>> return plane->funcs->atomic_get_property(plane, state,
>>> property, val);
>>> } else {
>>> diff --git a/drivers/gpu/drm/drm_color_mgmt.c
>>> b/drivers/gpu/drm/drm_color_mgmt.c
>>> index 0d002b045bd2..4b83e078d3e9 100644
>>> --- a/drivers/gpu/drm/drm_color_mgmt.c
>>> +++ b/drivers/gpu/drm/drm_color_mgmt.c
>>> @@ -88,6 +88,20 @@
>>>* drm_mode_crtc_set_gamma_size(). Drivers which support both should use
>>>* drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp
>>> with the
>>>* "GAMMA_LUT" property above.
>>> + *
>>> + * Support for different non RGB color encodings is controlled through
>>> + * &drm_plane specific COLOR_ENCODING and COLOR_RANGE properties. They
>>> + * are set up by calling drm_plane_create_color_properties().
>>> + *
>>> + * "COLOR_ENCODING"
>>> + * Optional plane enum property to support different non RGB
>>> + * color encodings. The driver can provide a subset of standard
>>> + * enum values supported by the DRM plane.
>>> + *
>>> + * "COLOR_RANGE"
>>> + * Optional plane enum property to support different non RGB
>>> + * color parameter ranges. The driver can provide a subset o
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond till middle next week I can try to respond
> in his absence, as I am familiar with the subject.
>
> On 30.11.2018 14:25, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
> >> Hi,
> >>
> >> I am looking for a way to export the color encoding and range selection
> >> to user space. I came across those properties and am wondering, why
> >> they are meant only for non RGB color encodings. Would it be okay, to
> >> modify them and use with RGB formats as well?
> > What you trying to do? Input limited range RGB data and expand to full
> > range?
>
>
> For example. But there are two more general questions, which
> surprisingly we have not found answer for.
>
> 1. What color encoding and range drm should expect on its input RGB
> buffers by default?
RGB is just RGB. There is no encoding. It's assumed to be full range
because no one really uses anything else.
>
> 2. How userspace should inform drm that given buffer has specified
> non-default color encoding and range?
>
>
> Hopefully this patch introduces such properties but only for YCbCr
> formats, the question is what should be the best way to expand it to RGB
> formats:
>
> A. Add another enums: DRM_COLOR_RGB_BT601 and friends.
BT.601 specifies how to encoder RGB data as YCbCr. So without
YCbCr BT.601 does not mean anything. Well, the standard does
contain other things as well I suppose, but for the purposes
of the color encoding prop only that one part is relevant.
>
> B. Reuse current enums, but remove format information from them:
> DRM_COLOR_YCBCR_BT601 => DRM_COLOR_BT601.
>
>
> Regards
>
> Andrzej
>
> >
> >> Regards,
> >> Chris
> >>
> >>
> >> On 02/19/2018 09:28 PM, Ville Syrjala wrote:
> >>> From: Jyri Sarha
> >>>
> >>> Add a standard optional properties to support different non RGB color
> >>> encodings in DRM planes. COLOR_ENCODING select the supported non RGB
> >>> color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
> >>> the value ranges within the selected color encoding. The properties
> >>> are stored to drm_plane object to allow different set of supported
> >>> encoding for different planes on the device.
> >>>
> >>> v2: Add/fix kerneldocs, verify bitmasks (danvet)
> >>>
> >>> Cc: Harry Wentland
> >>> Cc: Daniel Vetter
> >>> Cc: Daniel Stone
> >>> Cc: Russell King - ARM Linux
> >>> Cc: Ilia Mirkin
> >>> Cc: Hans Verkuil
> >>> Cc: Uma Shankar
> >>> Cc: Shashank Sharma
> >>> Reviewed-by: Ville Syrjälä
> >>> Signed-off-by: Jyri Sarha
> >>> [vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
> >>> Signed-off-by: Ville Syrjälä
> >>> Reviewed-by: Daniel Vetter
> >>> ---
> >>> drivers/gpu/drm/drm_atomic.c | 8 +++
> >>> drivers/gpu/drm/drm_color_mgmt.c | 103
> >>> +++
> >>> include/drm/drm_color_mgmt.h | 19
> >>> include/drm/drm_plane.h | 32
> >>> 4 files changed, 162 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> >>> index 46733d534587..452a0b0bafbc 100644
> >>> --- a/drivers/gpu/drm/drm_atomic.c
> >>> +++ b/drivers/gpu/drm/drm_atomic.c
> >>> @@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
> >>> drm_plane *plane,
> >>> state->rotation = val;
> >>> } else if (property == plane->zpos_property) {
> >>> state->zpos = val;
> >>> + } else if (property == plane->color_encoding_property) {
> >>> + state->color_encoding = val;
> >>> + } else if (property == plane->color_range_property) {
> >>> + state->color_range = val;
> >>> } else if (plane->funcs->atomic_set_property) {
> >>> return plane->funcs->atomic_set_property(plane, state,
> >>> property, val);
> >>> @@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane
> >>> *plane,
> >>> *val = state->rotation;
> >>> } else if (property == plane->zpos_property) {
> >>> *val = state->zpos;
> >>> + } else if (property == plane->color_encoding_property) {
> >>> + *val = state->color_encoding;
> >>> + } else if (property == plane->color_range_property) {
> >>> + *val = state->color_range;
> >>> } else if (plane->funcs->atomic_get_property) {
> >>> return plane->funcs->atomic_get_property(plane, state,
> >>> property, val);
> >>> } else {
> >>> diff --git a/drivers/gpu/drm/drm_color_mgmt.c
> >>> b/drivers/gpu/drm/drm_color_mgmt.c
> >>> index 0d002b045bd2..4b83e078d3e9 100644
> >>> --- a/drivers/gpu/drm/drm_color_mgmt.c
> >>> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> >>> @@ -88,6 +88,20 @@
> >>>* drm_mode_crtc_set_gamma_size(). Drivers which support both should use
> >>>* drm_atomic_helper_legacy_gamma_set() to alias the
Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
Quoting Tvrtko Ursulin (2018-11-30 12:02:56) > > On 30/11/2018 11:38, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-30 11:31:56) > >> From: Tvrtko Ursulin > >> > >> Since we now have all the GT workarounds in a table, by adding a simple > >> shared helper function we can now verify that their values are still > >> applied after some interesting events in the lifetime of the driver. > >> > >> At this stage these are the driver initialization and engine reset. > >> > >> Signed-off-by: Tvrtko Ursulin > >> --- > >> drivers/gpu/drm/i915/i915_drv.c | 4 +++ > >> drivers/gpu/drm/i915/i915_gem.c | 3 ++ > >> drivers/gpu/drm/i915/intel_workarounds.c | 46 > >> drivers/gpu/drm/i915/intel_workarounds.h | 2 ++ > >> 4 files changed, 55 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.c > >> b/drivers/gpu/drm/i915/i915_drv.c > >> index 2f3dc1cf83a6..14d019c9455b 100644 > >> --- a/drivers/gpu/drm/i915/i915_drv.c > >> +++ b/drivers/gpu/drm/i915/i915_drv.c > >> @@ -53,6 +53,7 @@ > >> #include "i915_vgpu.h" > >> #include "intel_drv.h" > >> #include "intel_uc.h" > >> +#include "intel_workarounds.h" > >> > >> static struct drm_driver driver; > >> > >> @@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs > >> *engine, const char *msg) > >> goto out; > >> } > >> > >> + /* Catch GT workarounds affected by engine reset. */ > >> + intel_gt_workarounds_verify(engine->i915, engine->name); > > > > I'd rather, quite strongly, not have this inside i915_reset_engine() > > itself. i915_reset_engine() is [designed to be] called from atomic > > context. Adding I915_READ() here is questionable. My preference is to > > have all this inside selftests/intel_workarounds where we can cross > > check the gt/all-engines after device reset and other engine reset. > > I wasn't sure myself how much value checking it here adds, but regarding > I915_READs, they are happening during engine->init_hw anyway. So I don't > think a few more would harm. But yes, as said, since I was unsure myself > I am happy to drop this hunk. Adding the I915_READ isn't the end-of-the-world, I am more wary of the slipperly slope and suddenly finding ourselves with a per-engine reset that is no longer suitable for fast resets, possibly from hardirq context. (Although that's more likely to be softirq really.) In this case, I think we can satisfy ourselves with a comprehensive yet fast test suite. And there's no harm in having the checks on idle for runtime consistency checking (we can even inject SRM before idling for completeness). -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On 11/30/18 15:20, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond till middle next week I can try to respond
> in his absence, as I am familiar with the subject.
>
> On 30.11.2018 14:25, Ville Syrjälä wrote:
>> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
>>> Hi,
>>>
>>> I am looking for a way to export the color encoding and range selection
>>> to user space. I came across those properties and am wondering, why
>>> they are meant only for non RGB color encodings. Would it be okay, to
>>> modify them and use with RGB formats as well?
>> What you trying to do? Input limited range RGB data and expand to full
>> range?
>
>
> For example. But there are two more general questions, which
> surprisingly we have not found answer for.
>
> 1. What color encoding and range drm should expect on its input RGB
> buffers by default?
While I am not a drm expert, I am pretty certain it always expects
full range RGB.
There is a real use-case for being able to give drm limited range RGB:
if the image was filled from an HDMI receiver and that receiver got
limited range RGB. That said, most (but not all) receivers can expand
it to full range before writing to memory.
> 2. How userspace should inform drm that given buffer has specified
> non-default color encoding and range?
>
>
> Hopefully this patch introduces such properties but only for YCbCr
> formats, the question is what should be the best way to expand it to RGB
> formats:
>
> A. Add another enums: DRM_COLOR_RGB_BT601 and friends.
>
> B. Reuse current enums, but remove format information from them:
> DRM_COLOR_YCBCR_BT601 => DRM_COLOR_BT601.
The colorspace (BT601, REC709, BT2020) is independent of the quantization
range (full/limited) and of the color encoding (YCbCr, RGB). There is also
the transfer function, another independent setting.
More background info is here:
https://hverkuil.home.xs4all.nl/spec/uapi/v4l/colorspaces.html
If all you use is a desktop, then it is all simple: full range sRGB. But if
you start mixing video captured from an HDMI receiver, then it can become
much more complex.
Regards,
Hans
>
>
> Regards
>
> Andrzej
>
>>
>>> Regards,
>>> Chris
>>>
>>>
>>> On 02/19/2018 09:28 PM, Ville Syrjala wrote:
From: Jyri Sarha
Add a standard optional properties to support different non RGB color
encodings in DRM planes. COLOR_ENCODING select the supported non RGB
color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
the value ranges within the selected color encoding. The properties
are stored to drm_plane object to allow different set of supported
encoding for different planes on the device.
v2: Add/fix kerneldocs, verify bitmasks (danvet)
Cc: Harry Wentland
Cc: Daniel Vetter
Cc: Daniel Stone
Cc: Russell King - ARM Linux
Cc: Ilia Mirkin
Cc: Hans Verkuil
Cc: Uma Shankar
Cc: Shashank Sharma
Reviewed-by: Ville Syrjälä
Signed-off-by: Jyri Sarha
[vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
Signed-off-by: Ville Syrjälä
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/drm_atomic.c | 8 +++
drivers/gpu/drm/drm_color_mgmt.c | 103
+++
include/drm/drm_color_mgmt.h | 19
include/drm/drm_plane.h | 32
4 files changed, 162 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 46733d534587..452a0b0bafbc 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
drm_plane *plane,
state->rotation = val;
} else if (property == plane->zpos_property) {
state->zpos = val;
+ } else if (property == plane->color_encoding_property) {
+ state->color_encoding = val;
+ } else if (property == plane->color_range_property) {
+ state->color_range = val;
} else if (plane->funcs->atomic_set_property) {
return plane->funcs->atomic_set_property(plane, state,
property, val);
@@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
*val = state->rotation;
} else if (property == plane->zpos_property) {
*val = state->zpos;
+ } else if (property == plane->color_encoding_property) {
+ *val = state->color_encoding;
+ } else if (property == plane->color_range_property) {
+ *val = state->color_range;
} else if (plane->funcs->atomic_get_property) {
return plane->funcs->atomic_get_property(plane, state,
property, val);
} else {
diff --git a/drivers/gpu/drm/drm_color_mgmt.c
b/drivers/gpu/drm/drm_color_mgmt.c
index 0d002
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On 11/30/18 15:29, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
>> Hi Ville,
>>
>> As Christoph cannot respond till middle next week I can try to respond
>> in his absence, as I am familiar with the subject.
>>
>> On 30.11.2018 14:25, Ville Syrjälä wrote:
>>> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote:
Hi,
I am looking for a way to export the color encoding and range selection
to user space. I came across those properties and am wondering, why
they are meant only for non RGB color encodings. Would it be okay, to
modify them and use with RGB formats as well?
>>> What you trying to do? Input limited range RGB data and expand to full
>>> range?
>>
>>
>> For example. But there are two more general questions, which
>> surprisingly we have not found answer for.
>>
>> 1. What color encoding and range drm should expect on its input RGB
>> buffers by default?
>
> RGB is just RGB. There is no encoding. It's assumed to be full range
> because no one really uses anything else.
For simple desktop usage that's true. When dealing with video inputs,
this becomes much more complicated.
>
>>
>> 2. How userspace should inform drm that given buffer has specified
>> non-default color encoding and range?
>>
>>
>> Hopefully this patch introduces such properties but only for YCbCr
>> formats, the question is what should be the best way to expand it to RGB
>> formats:
>>
>> A. Add another enums: DRM_COLOR_RGB_BT601 and friends.
>
> BT.601 specifies how to encoder RGB data as YCbCr. So without
> YCbCr BT.601 does not mean anything. Well, the standard does
> contain other things as well I suppose, but for the purposes
> of the color encoding prop only that one part is relevant.
Ah, I misunderstood the meaning of DRM_COLOR_RGB_BT601.
This is the equivalent of V4L2_YCBCR_ENC_601, and that's indeed
only defined for Y'CbCr. But it is often (ab)used as an alias for
the SMPTE170M colorspace (used by SDTV).
V4L2 has the following defines for colorspaces, transfer functions,
Y'CbCr (and HSV) encodings and quantization ranges:
https://hverkuil.home.xs4all.nl/spec/uapi/v4l/colorspaces-defs.html
Missing in this list is the color encoding (RGB vs YCbCr vs HSV) which
is set through the pixelformat fourcc.
And indeed, we don't have an RGB encoding define since RGB is just RGB :-)
Regards,
Hans
>
>>
>> B. Reuse current enums, but remove format information from them:
>> DRM_COLOR_YCBCR_BT601 => DRM_COLOR_BT601.
>>
>>
>> Regards
>>
>> Andrzej
>>
>>>
Regards,
Chris
On 02/19/2018 09:28 PM, Ville Syrjala wrote:
> From: Jyri Sarha
>
> Add a standard optional properties to support different non RGB color
> encodings in DRM planes. COLOR_ENCODING select the supported non RGB
> color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
> the value ranges within the selected color encoding. The properties
> are stored to drm_plane object to allow different set of supported
> encoding for different planes on the device.
>
> v2: Add/fix kerneldocs, verify bitmasks (danvet)
>
> Cc: Harry Wentland
> Cc: Daniel Vetter
> Cc: Daniel Stone
> Cc: Russell King - ARM Linux
> Cc: Ilia Mirkin
> Cc: Hans Verkuil
> Cc: Uma Shankar
> Cc: Shashank Sharma
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Jyri Sarha
> [vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_atomic.c | 8 +++
> drivers/gpu/drm/drm_color_mgmt.c | 103
> +++
> include/drm/drm_color_mgmt.h | 19
> include/drm/drm_plane.h | 32
> 4 files changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 46733d534587..452a0b0bafbc 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
> drm_plane *plane,
> state->rotation = val;
> } else if (property == plane->zpos_property) {
> state->zpos = val;
> + } else if (property == plane->color_encoding_property) {
> + state->color_encoding = val;
> + } else if (property == plane->color_range_property) {
> + state->color_range = val;
> } else if (plane->funcs->atomic_set_property) {
> return plane->funcs->atomic_set_property(plane, state,
> property, val);
> @@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane
> *plane,
> *val = state->rotation;
> } else if (property == plane->zpos_property) {
> *val
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)
On 30/11/2018 11:24, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Extract spinner code
(rev2)
URL : https://patchwork.freedesktop.org/series/53298/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/53298/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_10975 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: PASS -> FAIL [fdo#108880]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* {igt@runner@aborted}:
- {fi-icl-y}: NOTRUN -> FAIL [fdo#108070]
Possible fixes
* igt@gem_ctx_create@basic-files:
- fi-kbl-7560u: INCOMPLETE [fdo#103665] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-apl-guc: DMESG-WARN [fdo#108566] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108070]: https://bugs.freedesktop.org/show_bug.cgi?id=108070
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
Participating hosts (50 -> 43)
--
Additional (1): fi-icl-y
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks
fi-bsw-cyan fi-ctg-p8600 fi-icl-u3 fi-pnv-d510
Build changes
-
* Linux: CI_DRM_5230 -> Patchwork_10975
CI_DRM_5230: b0a2de64f8969163f6e01071d5e05748f18a8bab @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10975: dc4e63c0e82fe413f33149832a5581f4a7a64887 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dc4e63c0e82f drm/i915/selftests: Fix live_workarounds to actually do resets
bcfddfda17f5 drm/i915/selftests: Extract spinner code
Pushed, thanks for the reviews and help with reset magic!
Regards,
Tvrtko
___
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Remove Wa_1604302699
On 29/11/2018 14:47, Patchwork wrote: == Series Details == Series: drm/i915/icl: Remove Wa_1604302699 URL : https://patchwork.freedesktop.org/series/53244/ State : success == Summary == CI Bug Log - changes from CI_DRM_5222 -> Patchwork_10955 Summary --- **WARNING** Minor unknown changes coming with Patchwork_10955 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10955, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/53244/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_10955: ### IGT changes ### Warnings * igt@prime_vgem@basic-fence-flip: - fi-ivb-3520m: SKIP -> PASS Known issues Here are the changes found in Patchwork_10955 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b: - fi-skl-guc: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] Possible fixes * igt@gem_mmap_gtt@basic: - fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (49 -> 41) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 Build changes - * Linux: CI_DRM_5222 -> Patchwork_10955 CI_DRM_5222: a6f85043a0ca86eb0072e69bf92b77f7d9d6d5d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4735: b05c028ccdb6ac8e8d8499a041bb14dfe358ee26 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10955: 11100b9f61c3f4c893fdd337b2fa733ee3cdce02 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 11100b9f61c3 drm/i915/icl: Remove Wa_1604302699 Pushed, thanks for review! Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove whitelist application from ringbuffer backend (rev3)
On 29/11/2018 17:48, Patchwork wrote: == Series Details == Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3) URL : https://patchwork.freedesktop.org/series/53243/ State : success == Summary == CI Bug Log - changes from CI_DRM_5224 -> Patchwork_10960 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53243/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_10960 that come from known issues: ### IGT changes ### Issues hit * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#107362] +1 Possible fixes * igt@kms_frontbuffer_tracking@basic: - fi-byt-clapper: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 Participating hosts (50 -> 42) -- Missing(8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y Build changes - * Linux: CI_DRM_5224 -> Patchwork_10960 CI_DRM_5224: 67ee0d0da79f5b32636d496fd2127da1eecf6262 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10960: 2c213561982b431d679d5839a1c3f345fe275381 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2c213561982b drm/i915: Remove whitelist application from ringbuffer backend Pushed, thanks for the review! Regards, Tvrtko ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification
On 30/11/2018 11:43, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 21 +++--
drivers/gpu/drm/i915/intel_workarounds.h | 4 +-
.../drm/i915/selftests/intel_workarounds.c| 90 +++
3 files changed, 105 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 2d17d8a36a57..a21a21855e6a 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -990,7 +990,7 @@ wa_fail(const struct i915_wa *wa, u32 cur, const char
*name, const char *from)
cur, cur & wa->mask, wa->val, wa->mask);
}
-static void
+static bool
wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
const char *from)
{
@@ -1001,30 +1001,35 @@ wa_verify_bits(const struct i915_wa *wa, u32 cur, const
char *name,
while (bits) {
if ((bits & 1) && ((cur_ & 1) != (val_ & 1))) {
wa_fail(wa, cur, name, from);
- break;
+ return false;
}
bits >>= 1;
cur_ >>= 1;
val_ >>= 1;
}
+
+ return true;
}
-static void wa_list_verify(struct drm_i915_private *dev_priv,
+static bool wa_list_verify(struct drm_i915_private *dev_priv,
const struct i915_wa_list *wal,
const char *from)
{
struct i915_wa *wa;
unsigned int i;
+ bool res = true;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
+ res &= wa_verify_bits(wa, I915_READ(wa->reg), wal->name, from);
+
+ return res;
}
-void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
const char *from)
{
- wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+ return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
}
struct whitelist {
@@ -1313,10 +1318,10 @@ void intel_engine_workarounds_apply(struct
intel_engine_cs *engine)
wa_list_apply(engine->i915, &engine->wa_list);
}
-void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
const char *from)
{
- wa_list_verify(engine->i915, &engine->wa_list, from);
+ return wa_list_verify(engine->i915, &engine->wa_list, from);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
b/drivers/gpu/drm/i915/intel_workarounds.h
index f72cfda32d68..8f664d8b9e08 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -33,14 +33,14 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
-void intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
const char *from);
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
void intel_engine_workarounds_init(struct intel_engine_cs *engine);
void intel_engine_workarounds_apply(struct intel_engine_cs *engine);
-void intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
const char *from);
#endif
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index 80396b3592f5..c009eb2af7fc 100644
--- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
@@ -327,10 +327,100 @@ static int live_reset_whitelist(void *arg)
return err;
}
+static bool verify_gt_engine_wa(struct drm_i915_private *i915, const char *str)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ bool ok = true;
+
+ ok &= intel_gt_workarounds_verify(i915, str);
+
+ for_each_engine(engine, i915, id)
+ ok &= intel_engine_workarounds_verify(engine, str);
Ok, ok.
+
+ return ok;
+}
+
+static int
+live_gpu_reset_gt_engine_workarounds(void *arg)
+{
+ struct drm_i915
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: > On 11/30/18 15:29, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: > >> Hi Ville, > >> > >> As Christoph cannot respond till middle next week I can try to respond > >> in his absence, as I am familiar with the subject. > >> > >> On 30.11.2018 14:25, Ville Syrjälä wrote: > >>> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote: > Hi, > > I am looking for a way to export the color encoding and range selection > to user space. I came across those properties and am wondering, why > they are meant only for non RGB color encodings. Would it be okay, to > modify them and use with RGB formats as well? > >>> What you trying to do? Input limited range RGB data and expand to full > >>> range? > >> > >> > >> For example. But there are two more general questions, which > >> surprisingly we have not found answer for. > >> > >> 1. What color encoding and range drm should expect on its input RGB > >> buffers by default? > > > > RGB is just RGB. There is no encoding. It's assumed to be full range > > because no one really uses anything else. > > For simple desktop usage that's true. When dealing with video inputs, > this becomes much more complicated. > > > > >> > >> 2. How userspace should inform drm that given buffer has specified > >> non-default color encoding and range? > >> > >> > >> Hopefully this patch introduces such properties but only for YCbCr > >> formats, the question is what should be the best way to expand it to RGB > >> formats: > >> > >> A. Add another enums: DRM_COLOR_RGB_BT601 and friends. > > > > BT.601 specifies how to encoder RGB data as YCbCr. So without > > YCbCr BT.601 does not mean anything. Well, the standard does > > contain other things as well I suppose, but for the purposes > > of the color encoding prop only that one part is relevant. > > Ah, I misunderstood the meaning of DRM_COLOR_RGB_BT601. > This is the equivalent of V4L2_YCBCR_ENC_601, and that's indeed > only defined for Y'CbCr. But it is often (ab)used as an alias for > the SMPTE170M colorspace (used by SDTV). > > V4L2 has the following defines for colorspaces, transfer functions, > Y'CbCr (and HSV) encodings and quantization ranges: > > https://hverkuil.home.xs4all.nl/spec/uapi/v4l/colorspaces-defs.html Yeah, we're going to be introducing other properties to control colorspace and transfer function in kms as well. Actually some patches towards that have been floated a few times already. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework
On 30/11/2018 11:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:00)
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration of all four classes of workarounds onto the
common framework.
Existing macros are kept untouched for smaller code churn.
Signed-off-by: Tvrtko Ursulin
---
@@ -1652,7 +1638,7 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
- struct i915_workarounds workarounds;
+ struct i915_wa_list wa_list;
struct i915_wa_list gt_wa_list;
ctx_wa_list ?
Can do, will do.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework
On 30/11/2018 11:45, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:59)
-static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
- return;
-
- w->reg[w->count++] = reg;
-}
+ struct i915_wa wa = {
+ .reg = reg
+ };
-static void bdw_whitelist_build(struct whitelist *w)
-{
-}
+ if (GEM_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
We only need this code for pre-merge testing of patches as the build
list is static.
I interpret this as change to GEM_DEBUG_WARN_ON - makes sense.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries
On 30/11/2018 11:49, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:32:01)
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index de2bddbc64b4..abfe4b530c23 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const
char *name)
static void wa_init_finish(struct i915_wa_list *wal)
{
+ /* Trim unused entries. */
+ if (wal->count < wal->__size) {
+ struct i915_wa *wa =
+ kcalloc(wal->count, sizeof(*wa), GFP_KERNEL);
kcalloc followed by memcpy, what have you done with Tvrtko?
kmemdup ?
Oh well, the richer the API the easier to forget. :)
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime
On 30/11/2018 11:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 11:31:56)
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
At this stage these are the driver initialization and engine reset.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++
drivers/gpu/drm/i915/i915_gem.c | 3 ++
drivers/gpu/drm/i915/intel_workarounds.c | 46
drivers/gpu/drm/i915/intel_workarounds.h | 2 ++
4 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f3dc1cf83a6..14d019c9455b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -53,6 +53,7 @@
#include "i915_vgpu.h"
#include "intel_drv.h"
#include "intel_uc.h"
+#include "intel_workarounds.h"
static struct drm_driver driver;
@@ -2362,6 +2363,9 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
goto out;
}
+ /* Catch GT workarounds affected by engine reset. */
+ intel_gt_workarounds_verify(engine->i915, engine->name);
+
/*
* The request that caused the hang is stuck on elsp, we know the
* active request and can drop it, adjust head to skip the offending
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 18adb3dd1fcd..1eff471d4366 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+ /* Apply the GT workarounds... */
intel_gt_workarounds_apply(dev_priv);
+ /* ...and determine whether they are sticking. */
+ intel_gt_workarounds_verify(dev_priv, "init");
i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index be63a2af3481..a5c0d206b2a4 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -981,6 +981,52 @@ void intel_gt_workarounds_apply(struct drm_i915_private
*dev_priv)
wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
}
+static void
+wa_fail(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
+{
+ DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x,
mask=%x)\n",
+ name, from,
+ i915_mmio_reg_offset(wa->reg),
+ cur, cur & wa->mask, wa->val, wa->mask);
+}
+
+static void
+wa_verify_bits(const struct i915_wa *wa, u32 cur, const char *name,
+ const char *from)
+{
+ u32 bits = wa->mask;
+ u32 cur_ = cur;
+ u32 val_ = wa->val;
Make sure wa->mask is set to ~0u for whole registers, which it must be
for the wa_fail.
It is (wa_write), unless you spotted a miss?
if ((cur ^ wa->val) & wa->mask) {
wa_fail(wa, cur, name, whom);
Not sure if I feel like laughing or crying at my implementation. :) I
was cleaning up the lot when I realized it all reduces to simplicity,
but obviously missed this one..
return false; /* make it bool now to save churn later? */
}
Okay.
Regards,
Tvrtko
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Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification
Quoting Tvrtko Ursulin (2018-11-30 15:15:28)
>
> On 30/11/2018 11:43, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-11-30 11:31:58)
> >> From: Tvrtko Ursulin
> >>
> >> Two simple selftests which test that both GT and engine workarounds are
> >> not lost after either a full GPU reset, or after the per-engine ones.
> >>
> >> (Including checks that one engine reset is not affecting workarounds not
> >> belonging to itself.)
> >>
> >> Signed-off-by: Tvrtko Ursulin
> >> ---
> >> +static int
> >> +live_engine_reset_gt_engine_workarounds(void *arg)
> >> +{
> >> + struct drm_i915_private *i915 = arg;
> >> + struct i915_gpu_error *error = &i915->gpu_error;
> >> + struct intel_engine_cs *engine;
> >> + enum intel_engine_id id;
> >> + bool ok;
> >> +
> >> + if (!intel_has_reset_engine(i915))
> >> + return 0;
> >
> > May be easier to take global_reset_lock/unlock from
> > selftests/intel_hanghceck.
>
> I looked inside and did not find anything with this name so I don't know
> what you mean?
This function
static void global_reset_lock(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
pr_debug("%s: current gpu_error=%08lx\n",
__func__, i915->gpu_error.flags);
while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags))
wait_event(i915->gpu_error.reset_queue,
!test_bit(I915_RESET_BACKOFF,
&i915->gpu_error.flags));
for_each_engine(engine, i915, id) {
while (test_and_set_bit(I915_RESET_ENGINE + id,
&i915->gpu_error.flags))
wait_on_bit(&i915->gpu_error.flags,
I915_RESET_ENGINE + id,
TASK_UNINTERRUPTIBLE);
}
}
in selftests/intel_hangcheck.c
> >> +
> >> + for_each_engine(engine, i915, id) {
> >> + pr_info("Verifying after %s reset...\n", engine->name);
> >> +
> >> + set_bit(I915_RESET_BACKOFF, &error->flags);
> >> + set_bit(I915_RESET_ENGINE + engine->id, &error->flags);
> >> +
> >> + ok = verify_gt_engine_wa(i915, "before reset");
> >> + if (!ok)
> >> + goto out;
> >> +
> >> + intel_runtime_pm_get(i915);
> >> + i915_reset_engine(engine, "live_workarounds");
> >> + intel_runtime_pm_put(i915);
> >
> > Once idle, and once with a spinner?
>
> If idle then engine reset does nothing, so maybe I am again not
> following you.
The engine is idle here, so no reset, right?
Also worth verifying in case we change the implementation and there is
variation in HW between resetting from different states.
-Chris
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Re: [Intel-gfx] [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support
>-Original Message-
>From: Roper, Matthew D
>Sent: Friday, November 30, 2018 4:38 AM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ;
>Sharma,
>Shashank
>Subject: Re: [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support
>
>On Thu, Nov 29, 2018 at 08:21:41PM +0530, Uma Shankar wrote:
>> Add support for icl pipe degamma and gamma.
>>
>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>> Maarten's comments.
>>
>> v3: Addressed Matt's review comments. Removed rmw patterns as
>> suggested by Matt.
>>
>> Signed-off-by: Uma Shankar
>> ---
>> drivers/gpu/drm/i915/i915_reg.h| 3 ++
>> drivers/gpu/drm/i915/intel_color.c | 73
>> ++
>> 2 files changed, 76 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 47baf2fe..b0147bf 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7058,6 +7058,9 @@ enum {
>> #define GAMMA_MODE_MODE_12BIT (2 << 0)
>> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
>>
>> +#define PRE_CSC_GAMMA_ENABLE(1 << 31)
>> +#define POST_CSC_GAMMA_ENABLE (1 << 30)
>> +
>> /* DMC/CSR */
>> #define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
>> #define CSR_SSP_BASE_ADDR_GEN9 0x2FC0
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..7c8c996 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -422,6 +422,7 @@ static void bdw_load_degamma_lut(struct
>> drm_crtc_state *state) static void bdw_load_gamma_lut(struct
>> drm_crtc_state *state, u32 offset) {
>> struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
>> +struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>> enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
>> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>>
>> @@ -464,6 +465,9 @@ static void bdw_load_gamma_lut(struct drm_crtc_state
>*state, u32 offset)
>> I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
>> }
>> +
>> +if (INTEL_GEN(dev_priv) >= 11)
>> +intel_state->gamma_mode |= POST_CSC_GAMMA_ENABLE;
>
>icl_load_luts updates this field as soon as this function returns, so it might
>be
>easier to make this update there, at the same point you set MODE_10BIT.
>
>However the overall use and handling of gamma_mode by the driver seems
>strange. Generally we try to calculate important state variables during atomic
>check and then use those derived state values during the commit programming
>phase, but we're not following that pattern with this field.
>Can we just move the logic to build this field into the atomic check phase so
>that
>we're not trying to update state during the commit?
>
>Actually, looking closer, I'm not sure if we even need this field. For most
>platforms we have a fixed set of bits that we write (e.g.,
>PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE |
>GAMMA_MODE_10_BIT for ICL), so we can just put those directly into the
>I915_WRITE statement.
>Unless I'm overlooking something, the only place where this variable is used
>for
>something else is in haswell_load_luts() where we have to disable IPS before
>accessing the LUT's if we're in split gamma mode.
>But the driver itself only ever sets 8BIT for Haswell as far as I can see.
>BIOS might
>have put us in split mode before the driver loaded, but that might be easier to
>sanitize during hardware state readout?
Yeah I agree, we can avoid this state variable altogether. I will try to clean
it up
and resend the series.
>
>> }
>>
>> /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ @@
>> -523,6 +527,53 @@ static void glk_load_degamma_lut(struct drm_crtc_state
>*state)
>> I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); }
>>
>> +static void icl_load_degamma_lut(struct drm_crtc_state *state) {
>> +struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
>> +struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>> +enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
>> +const uint32_t lut_size = INTEL_INFO(dev_priv)-
>>color.degamma_lut_size;
>> +uint32_t i;
>> +
>> +/*
>> + * When setting the auto-increment bit, the hardware seems to
>> + * ignore the index bits, so we need to reset it to index 0
>> + * separately.
>> + */
>> +I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
>> +I915_WRITE(PRE_CSC_GAMC_INDEX(pipe),
>PRE_CSC_GAMC_AUTO_INCREMENT);
>> +
>> +if (state->degamma_lut) {
>> +struct drm_color_lut *lut =
>> +(struct drm_color_lut *) state->degamma_lut->data;
>> +for (i = 0; i < lut_size; i++) {
>> +/*
>> + * First 33 en
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
On 11/30/18 16:16, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: >> On 11/30/18 15:29, Ville Syrjälä wrote: >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: Hi Ville, As Christoph cannot respond till middle next week I can try to respond in his absence, as I am familiar with the subject. On 30.11.2018 14:25, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote: >> Hi, >> >> I am looking for a way to export the color encoding and range selection >> to user space. I came across those properties and am wondering, why >> they are meant only for non RGB color encodings. Would it be okay, to >> modify them and use with RGB formats as well? > What you trying to do? Input limited range RGB data and expand to full > range? For example. But there are two more general questions, which surprisingly we have not found answer for. 1. What color encoding and range drm should expect on its input RGB buffers by default? >>> >>> RGB is just RGB. There is no encoding. It's assumed to be full range >>> because no one really uses anything else. >> >> For simple desktop usage that's true. When dealing with video inputs, >> this becomes much more complicated. >> >>> 2. How userspace should inform drm that given buffer has specified non-default color encoding and range? Hopefully this patch introduces such properties but only for YCbCr formats, the question is what should be the best way to expand it to RGB formats: A. Add another enums: DRM_COLOR_RGB_BT601 and friends. >>> >>> BT.601 specifies how to encoder RGB data as YCbCr. So without >>> YCbCr BT.601 does not mean anything. Well, the standard does >>> contain other things as well I suppose, but for the purposes >>> of the color encoding prop only that one part is relevant. >> >> Ah, I misunderstood the meaning of DRM_COLOR_RGB_BT601. >> This is the equivalent of V4L2_YCBCR_ENC_601, and that's indeed >> only defined for Y'CbCr. But it is often (ab)used as an alias for >> the SMPTE170M colorspace (used by SDTV). >> >> V4L2 has the following defines for colorspaces, transfer functions, >> Y'CbCr (and HSV) encodings and quantization ranges: >> >> https://hverkuil.home.xs4all.nl/spec/uapi/v4l/colorspaces-defs.html > > Yeah, we're going to be introducing other properties to control > colorspace and transfer function in kms as well. Actually some > patches towards that have been floated a few times already. > Great. Let's try to keep drm and V4L2 in sync for this. It should be possible to convert from one to the other without having to do weird things. I'll try to pay attention to these patches, but just ping me if you want me to take a look at something. I put a lot of effort into the V4L2 colorspace documentation, trying to put all the information in one place, esp. all the formulas. Regards, Hans ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm: Fix up drm_atomic_state_helper.[hc] extraction
On Thu, Nov 29, 2018 at 10:36:13AM -0500, Sean Paul wrote:
> On Wed, Nov 28, 2018 at 5:07 AM Daniel Vetter wrote:
> >
> > I've misplaced two functions by accident:
> > - drm_atomic_helper_duplicate_state is really part of the
> > resume/suspend/shutdown device-wide helpers.
> > - drm_atomic_helper_legacy_gamma_set is part of the legacy ioctl
> > compat helpers.
> >
> > Move them both back.
> >
> > Fixes: 9ef8a9dc4b21 ("drm: Extract drm_atomic_state_helper.[hc]")
> > Cc: Ville Syrjälä
> > Signed-off-by: Daniel Vetter
>
> Reviewed-by: Sean Paul
Applied, thanks for reviewing.
-Daniel
>
> > ---
> > drivers/gpu/drm/drm_atomic_helper.c | 157 ++
> > drivers/gpu/drm/drm_atomic_state_helper.c | 157 --
> > include/drm/drm_atomic_helper.h | 7 +
> > include/drm/drm_atomic_state_helper.h | 7 -
> > 4 files changed, 164 insertions(+), 164 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_helper.c
> > b/drivers/gpu/drm/drm_atomic_helper.c
> > index 9b22774a9867..de7d872f9f1a 100644
> > --- a/drivers/gpu/drm/drm_atomic_helper.c
> > +++ b/drivers/gpu/drm/drm_atomic_helper.c
> > @@ -3135,6 +3135,93 @@ void drm_atomic_helper_shutdown(struct drm_device
> > *dev)
> > }
> > EXPORT_SYMBOL(drm_atomic_helper_shutdown);
> >
> > +/**
> > + * drm_atomic_helper_duplicate_state - duplicate an atomic state object
> > + * @dev: DRM device
> > + * @ctx: lock acquisition context
> > + *
> > + * Makes a copy of the current atomic state by looping over all objects and
> > + * duplicating their respective states. This is used for example by
> > suspend/
> > + * resume support code to save the state prior to suspend such that it can
> > + * be restored upon resume.
> > + *
> > + * Note that this treats atomic state as persistent between save and
> > restore.
> > + * Drivers must make sure that this is possible and won't result in
> > confusion
> > + * or erroneous behaviour.
> > + *
> > + * Note that if callers haven't already acquired all modeset locks this
> > might
> > + * return -EDEADLK, which must be handled by calling drm_modeset_backoff().
> > + *
> > + * Returns:
> > + * A pointer to the copy of the atomic state object on success or an
> > + * ERR_PTR()-encoded error code on failure.
> > + *
> > + * See also:
> > + * drm_atomic_helper_suspend(), drm_atomic_helper_resume()
> > + */
> > +struct drm_atomic_state *
> > +drm_atomic_helper_duplicate_state(struct drm_device *dev,
> > + struct drm_modeset_acquire_ctx *ctx)
> > +{
> > + struct drm_atomic_state *state;
> > + struct drm_connector *conn;
> > + struct drm_connector_list_iter conn_iter;
> > + struct drm_plane *plane;
> > + struct drm_crtc *crtc;
> > + int err = 0;
> > +
> > + state = drm_atomic_state_alloc(dev);
> > + if (!state)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + state->acquire_ctx = ctx;
> > +
> > + drm_for_each_crtc(crtc, dev) {
> > + struct drm_crtc_state *crtc_state;
> > +
> > + crtc_state = drm_atomic_get_crtc_state(state, crtc);
> > + if (IS_ERR(crtc_state)) {
> > + err = PTR_ERR(crtc_state);
> > + goto free;
> > + }
> > + }
> > +
> > + drm_for_each_plane(plane, dev) {
> > + struct drm_plane_state *plane_state;
> > +
> > + plane_state = drm_atomic_get_plane_state(state, plane);
> > + if (IS_ERR(plane_state)) {
> > + err = PTR_ERR(plane_state);
> > + goto free;
> > + }
> > + }
> > +
> > + drm_connector_list_iter_begin(dev, &conn_iter);
> > + drm_for_each_connector_iter(conn, &conn_iter) {
> > + struct drm_connector_state *conn_state;
> > +
> > + conn_state = drm_atomic_get_connector_state(state, conn);
> > + if (IS_ERR(conn_state)) {
> > + err = PTR_ERR(conn_state);
> > + drm_connector_list_iter_end(&conn_iter);
> > + goto free;
> > + }
> > + }
> > + drm_connector_list_iter_end(&conn_iter);
> > +
> > + /* clear the acquire context so that it isn't accidentally reused */
> > + state->acquire_ctx = NULL;
> > +
> > +free:
> > + if (err < 0) {
> > + drm_atomic_state_put(state);
> > + state = ERR_PTR(err);
> > + }
> > +
> > + return state;
> > +}
> > +EXPORT_SYMBOL(drm_atomic_helper_duplicate_state);
> > +
> > /**
> > * drm_atomic_helper_suspend - subsystem-level suspend helper
> > * @dev: DRM device
> > @@ -3418,3 +3505,73 @@ int drm_atomic_helper_page_flip_target(struct
> > drm_crtc *crtc,
> > return ret;
> > }
> > EXPORT_SYMBOL(drm_atomic_helper_page_flip_target);
> > +
> > +/**
> > + * drm_atomic_helper_legacy_gamma_set - set the legacy g
Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: Change KVMGT as self load module
On Fri, 30 Nov 2018 14:51:24 +0800 Zhenyu Wang wrote: > This trys to make 'kvmgt' module as self loadable instead of loading > by i915/gvt device model. So hypervisor specific module could be > stand-alone, e.g only after loading hypervisor specific module, GVT > feature could be enabled via specific hypervisor interface, e.g VFIO/mdev. > > So this trys to use hypervisor module register/unregister interface > for that. Hypervisor module needs to take care of module reference > itself when working for hypervisor interface, e.g reference counting > for any VFIO/mdev creation. This doesn't sound right and I don't see that it's how it works today. mdev core doesn't take a reference to the vendor driver, it's the vendor driver's responsibility to take a module reference when a device is opened. Likewise created, but unused devices probably shouldn't hold a reference, they should be cleaned up on module release callback. Thanks, Alex ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/fbdev: Make skip_vt_switch the default (rev3)
== Series Details ==
Series: drm/fbdev: Make skip_vt_switch the default (rev3)
URL : https://patchwork.freedesktop.org/series/53094/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56cf8aa074f9 drm/fbdev: Make skip_vt_switch the default
-:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 18c437caa5b1 ("Revert
"drm/radeon: dont switch vt on suspend"")'
#22:
commit 18c437caa5b18a235dd65cec224eab54bebcee65
-:137: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch
author 'Daniel Vetter '
total: 1 errors, 1 warnings, 0 checks, 47 lines checked
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Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
Hi, On Fri, Nov 30, 2018 at 04:34:54PM +0100, Hans Verkuil wrote: > On 11/30/18 16:16, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: > >> On 11/30/18 15:29, Ville Syrjälä wrote: > >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: > Hi Ville, > > As Christoph cannot respond till middle next week I can try to respond > in his absence, as I am familiar with the subject. > > On 30.11.2018 14:25, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote: > >> Hi, > >> > >> I am looking for a way to export the color encoding and range selection > >> to user space. I came across those properties and am wondering, why > >> they are meant only for non RGB color encodings. Would it be okay, to > >> modify them and use with RGB formats as well? > > What you trying to do? Input limited range RGB data and expand to full > > range? > > > For example. But there are two more general questions, which > surprisingly we have not found answer for. > > 1. What color encoding and range drm should expect on its input RGB > buffers by default? This is where I personally think we've got an unfortunate disconnect in the KMS UAPI. For YCbCr buffers, these properties specify the encoding and range of the data in the buffer. But everything else in the pipe is described in terms of the processing to apply - i.e. the KMS driver doesn't know what transfer function the data uses, it only knows the degamma LUT it's told to apply to it. It would have been more uniform if the COLOR_ENCODING/COLOR_RANGE properties were a single "ENCODING_CONVERSION" property stating what conversion should be applied. > >>> > >>> RGB is just RGB. There is no encoding. It's assumed to be full range > >>> because no one really uses anything else. > >> > >> For simple desktop usage that's true. When dealing with video inputs, > >> this becomes much more complicated. > >> When the plane degamma/ctm/gamma properties land, those could be used to convert limited range to whatever the pipe-internal format is, I think. That pipe-internal format would be whatever userspace decides it is, via converting input buffers using the various color conversion properties. > >>> > > 2. How userspace should inform drm that given buffer has specified > non-default color encoding and range? > My understanding is that DRM would never be informed of this - only what to do with the data (which does of-course imply an encoding, but it's not told to DRM explicitly). > > Hopefully this patch introduces such properties but only for YCbCr > formats, the question is what should be the best way to expand it to RGB > formats: > > A. Add another enums: DRM_COLOR_RGB_BT601 and friends. > >>> > >>> BT.601 specifies how to encoder RGB data as YCbCr. So without > >>> YCbCr BT.601 does not mean anything. Well, the standard does > >>> contain other things as well I suppose, but for the purposes > >>> of the color encoding prop only that one part is relevant. > >> > >> Ah, I misunderstood the meaning of DRM_COLOR_RGB_BT601. > >> This is the equivalent of V4L2_YCBCR_ENC_601, and that's indeed > >> only defined for Y'CbCr. But it is often (ab)used as an alias for > >> the SMPTE170M colorspace (used by SDTV). > >> > >> V4L2 has the following defines for colorspaces, transfer functions, > >> Y'CbCr (and HSV) encodings and quantization ranges: > >> > >> https://hverkuil.home.xs4all.nl/spec/uapi/v4l/colorspaces-defs.html > > > > Yeah, we're going to be introducing other properties to control > > colorspace and transfer function in kms as well. Actually some > > patches towards that have been floated a few times already. > > > > Great. Let's try to keep drm and V4L2 in sync for this. It should be > possible to convert from one to the other without having to do weird > things. > > I'll try to pay attention to these patches, but just ping me if you > want me to take a look at something. > > I put a lot of effort into the V4L2 colorspace documentation, trying to > put all the information in one place, esp. all the formulas. There's always going to be a bit of a disconnect here - in KMS, it's userspace which needs to handle all this stuff. It would be up to userspace to set e.g. DEGAMMA_LUT to a LUT which corresponds to SMPTE 2084, rather than the kernel driver being told directly that the buffer is encoded using the SMPTE 2084 transfer function. Actually I want to put an RFC together to allow DEGAMMA_LUT/GAMMA_LUT to be set to some pre-defined values (e.g. sRGB, PQ, HLG) to suit hardware which has built-in hard-coded transfer functions (and potentially also save userspace some effort of coming up with LUTs). Cheers, -Brian > > Regards, > > Hans > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedeskt
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
== Series Details ==
Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume
URL : https://patchwork.freedesktop.org/series/53284/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10965_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_10965_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10965_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_10965_full:
### IGT changes ###
Warnings
* igt@kms_chv_cursor_fail@pipe-b-64x64-left-edge:
- shard-snb: PASS -> SKIP +2
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_10965_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_eio@reset-stress:
- shard-glk: PASS -> FAIL [fdo#107799]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +2
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-skl: PASS -> FAIL [fdo#100368]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +3
* igt@kms_properties@connector-properties-atomic:
- shard-skl: NOTRUN -> FAIL [fdo#108642]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@pm_rpm@gem-execbuf-stress-pc8:
- {shard-iclb}: SKIP -> INCOMPLETE [fdo#107713] / [fdo#108840]
* igt@pm_rpm@gem-pread:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@pm_rpm@legacy-planes-dpms:
- shard-skl: PASS -> INCOMPLETE [fdo#105959] / [fdo#107807]
* igt@pm_rpm@system-suspend-execbuf:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@pm_rpm@universal-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654] / [fdo#108756]
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> FAIL [fdo#108756]
Possible fixes
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-hsw: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-onscreen:
- shard-glk: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@dr
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/fbdev: Make skip_vt_switch the default (rev3)
== Series Details == Series: drm/fbdev: Make skip_vt_switch the default (rev3) URL : https://patchwork.freedesktop.org/series/53094/ State : success == Summary == CI Bug Log - changes from CI_DRM_5234 -> Patchwork_10980 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53094/revisions/3/mbox/ Known issues Here are the changes found in Patchwork_10980 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-bsw-kefka: PASS -> INCOMPLETE [fdo#108714] * igt@gem_exec_suspend@basic-s4-devices: - fi-ivb-3520m: PASS -> FAIL [fdo#108880] * igt@kms_chamelium@common-hpd-after-suspend: - fi-skl-6700k2: PASS -> INCOMPLETE [fdo#104108] / [fdo#105524] / [k.org#199541] Possible fixes * igt@gem_ctx_create@basic-files: - fi-bsw-n3050: FAIL [fdo#108656] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#105524]: https://bugs.freedesktop.org/show_bug.cgi?id=105524 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656 [fdo#108714]: https://bugs.freedesktop.org/show_bug.cgi?id=108714 [fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880 [k.org#199541]: https://bugzilla.kernel.org/show_bug.cgi?id=199541 Participating hosts (49 -> 44) -- Additional (1): fi-pnv-d510 Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 Build changes - * Linux: CI_DRM_5234 -> Patchwork_10980 CI_DRM_5234: bfc64dfb7011de1dd3513cad50fe25e2f2080ac7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10980: 56cf8aa074f9cbd85242ef0235e1ec5897ea53ec @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 56cf8aa074f9 drm/fbdev: Make skip_vt_switch the default == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10980/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10967_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_10967_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10967_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_10967_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
Known issues
Here are the changes found in Patchwork_10967_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108039]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> FAIL [fdo#108597]
* igt@kms_cursor_crc@cursor-128x128-sliding:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-apl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: PASS -> FAIL [fdo#104873]
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +1
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-apl: NOTRUN -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_properties@connector-properties-atomic:
- shard-skl: NOTRUN -> FAIL [fdo#108642]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@pm_rpm@dpms-mode-unset-non-lpsp:
- shard-skl: SKIP -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-iclb}: SKIP -> INCOMPLETE [fdo#108840]
* igt@pm_rpm@reg-read-ioctl:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +3
* igt@pm_rpm@universal-planes:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654] / [fdo#108756]
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> FAIL [fdo#108756]
Possible fixes
* igt@gem_userptr_blits@readonly-unsync:
- shard-skl: TIMEOUT [fdo#108887] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
- {shard-iclb}: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: FAIL [fdo#103232] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-size-change:
- shard-apl: FAIL [fdo#103232] -> PASS
* igt@kms_draw_crc@draw-method-xrgb-pwrite-y
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ddi: Check for unexpectedly disabled transcoders
On Fri, Nov 30, 2018 at 07:31:01AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/ddi: Check for unexpectedly disabled transcoders
> URL : https://patchwork.freedesktop.org/series/53256/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10959_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_10959_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_10959_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_10959_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_draw_crc@draw-method-xrgb-pwrite-ytiled:
> - shard-skl: NOTRUN -> FAIL
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
> - shard-kbl: PASS -> FAIL
These are unrelated, the only effect of the change would be to emit a
warning, but that's not the case here.
>
>
> Warnings
>
> * igt@tools_test@tools_test:
> - shard-snb: PASS -> SKIP
The platform is unrelated to the change.
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_10959_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@drm_import_export@import-close-race-flink:
> - shard-skl: PASS -> TIMEOUT [fdo#108667]
>
> * igt@gem_ctx_isolation@vecs0-s3:
> - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
>
> * igt@gem_exec_schedule@pi-ringfull-bsd:
> - shard-skl: NOTRUN -> FAIL [fdo#103158] +1
>
> * igt@gem_ppgtt@blt-vs-render-ctxn:
> - shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#106023] /
> [fdo#106887]
>
> * igt@i915_hangman@hangcheck-unterminated:
> - shard-apl: PASS -> INCOMPLETE [fdo#103927]
>
> * igt@i915_suspend@fence-restore-tiled2untiled:
> - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]
>
> * igt@kms_busy@extended-modeset-hang-newfb-render-a:
> - {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +1
>
> * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
> - shard-glk: PASS -> FAIL [fdo#108145]
>
> * igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
> - shard-skl: NOTRUN -> FAIL [fdo#104671]
>
> * igt@kms_color@pipe-a-ctm-max:
> - shard-apl: PASS -> FAIL [fdo#108147]
>
> * igt@kms_cursor_crc@cursor-128x128-offscreen:
> - shard-skl: PASS -> FAIL [fdo#103232]
>
> * igt@kms_cursor_crc@cursor-128x128-suspend:
> - shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
>
> * igt@kms_cursor_crc@cursor-256x256-onscreen:
> - shard-glk: PASS -> FAIL [fdo#103232]
>
> * igt@kms_cursor_crc@cursor-256x85-offscreen:
> - shard-skl: NOTRUN -> FAIL [fdo#103232] +1
>
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
> - shard-glk: PASS -> FAIL [fdo#105363]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu:
> - shard-apl: PASS -> FAIL [fdo#103167]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
> - shard-glk: PASS -> FAIL [fdo#103167] +1
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
> - {shard-iclb}: PASS -> FAIL [fdo#103167] +3
>
> * igt@kms_frontbuffer_tracking@fbcpsr-tilingchange:
> - shard-skl: NOTRUN -> FAIL [fdo#105682] +2
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
> - shard-skl: PASS -> INCOMPLETE [fdo#106978]
>
> * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
> - shard-skl: NOTRUN -> FAIL [fdo#103167] +2
>
> * igt@kms_plane@plane-position-covered-pipe-c-planes:
> - shard-glk: PASS -> FAIL [fdo#103166] +2
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
> - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] +1
>
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
> - shard-skl: NOTRUN -> FAIL [fdo#108145]
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: PASS -> FAIL [fdo#107815]
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
> - {shard-iclb}: PASS -> FAIL [fdo#103166] +4
>
> * igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
> - shard-apl: PASS -> FAIL [fdo#103166]
>
> * igt@kms_rmfb@close-f
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)
On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
>
>
> On 29/11/2018 19:36, Rodrigo Vivi wrote:
> > On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
> >> Hi,
> >>
> >>> -Original Message-
> >>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> >>> Behalf Of
> >>> Rodrigo Vivi
> >>> Sent: torstai 29. marraskuuta 2018 8.18
> >>> To: Souza, Jose
> >>> Cc: intel-gfx@lists.freedesktop.org
> >>> Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe
> >>> id
> >>> following atomic guidelines (rev2)
> >>>
> >>> On Wed, Nov 28, 2018 at 02:13:12PM -0800, Souza, Jose wrote:
> On Wed, 2018-11-28 at 21:02 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev2)
> > URL : https://patchwork.freedesktop.org/series/53132/
> > State : failure
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_5216 -> Patchwork_10934
> >
> >
> > Summary
> > ---
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with Patchwork_10934 absolutely
> > need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the
> > changes
> > introduced in Patchwork_10934, please notify your bug team to
> > allow them
> > to document this new failure mode, which will reduce false
> > positives in CI.
> >
> > External URL:
> > https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/2/m
> > box/
> >
> > Possible new issues
> > ---
> >
> > Here are the unknown changes that may have been introduced in
> > Patchwork_10934:
> >
> > ### IGT changes ###
> >
> > Possible regressions
> >
> > * igt@i915_selftest@live_sanitycheck:
> > - fi-apl-guc: PASS -> DMESG-WARN
> >
> > * {igt@runner@aborted}:
> > - fi-apl-guc: NOTRUN -> FAIL
>
> Both are pretty much non related with display, what do you think
> Rodrigo? It is a merge blocker?
> >>>
> >>> I got addicted to see all green on CI. So I always prefer to trigger a
> >>> retest. So
> >>> anyone following the link that is merged with the patch doens't have to
> >>> understand and analyze why it was merged with BAT failure.
> >>>
> >>> I just triggered the re-test for this patch.
> >> Martin, Arek, fyi, not preferred?
> >
> > Yes, I'd like to hear their opinion.
> >
> > On this case a simple BAT would be enough because we don't have PSR monitors
> > on shrd ones.
> > However most of the times trigger the retest is unavoidable because we need
> > to make it to pass BAT and go for the full run.
> >
> > Besides the green-report-link reason I exposed above.
>
> I agree that we should only push stuff when CI is green.
>
> However, using the re-try button is the wrong way as it requires more
> machine time, and it may hide low-probably issues introduced by the patch.
>
> Instead, we should file/edit bugs and then ask cibuglog to re-send the
> report. I have been doing this ofr a couple of people already, but we
> need to advertise this more!
This makes total sense for me. But I wonder if we don't need at least
one re-run.
My feeling is that if we tell people to file bugs and regenerate
reports they might just end up accidentally ignoring regressions that
was caused by their own patches.
But anyway is there a doc with step-by-step instructions anywhere that
we could learn from and start doing this without overwhelming a single
person?
Thanks a lot!
>
> Martin
>
> >
> > Thanks,
> > Rodrigo.
> >
> >>>
> >>> Thanks,
> >>> Rodrigo.
> >>>
>
> >
> >
> > Known issues
> >
> >
> > Here are the changes found in Patchwork_10934 that come from known
> > issues:
> >
> > ### IGT changes ###
> >
> > Issues hit
> >
> > * igt@i915_selftest@live_hangcheck:
> > - fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044]
> >
> > * igt@kms_pipe_crc_basic@read-crc-pipe-a:
> > - fi-byt-clapper: PASS -> FAIL [fdo#107362]
> >
> >
> > {name}: This element is suppressed. This means it is ignored when
> > computing
> > the status of the difference (SUCCESS, WARNING, or
> > FAILURE).
> >
> > [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
> > [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
> >
> >
> > Participating hosts (50 -> 44)
> > --
> >
> > Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> > squawks fi-bsw-cyan fi-ctg-p8600
> >
> >
> > Build changes
> > -
> >
> > * Linux: CI_DRM_5216 -> Patchw
Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane
Hi,
I am looking for a way to export the color encoding and range selection
to user space. I came across those properties and am wondering, why
they are meant only for non RGB color encodings. Would it be okay, to
modify them and use with RGB formats as well?
Regards,
Chris
On 02/19/2018 09:28 PM, Ville Syrjala wrote:
> From: Jyri Sarha
>
> Add a standard optional properties to support different non RGB color
> encodings in DRM planes. COLOR_ENCODING select the supported non RGB
> color encoding, for instance ITU-R BT.709 YCbCr. COLOR_RANGE selects
> the value ranges within the selected color encoding. The properties
> are stored to drm_plane object to allow different set of supported
> encoding for different planes on the device.
>
> v2: Add/fix kerneldocs, verify bitmasks (danvet)
>
> Cc: Harry Wentland
> Cc: Daniel Vetter
> Cc: Daniel Stone
> Cc: Russell King - ARM Linux
> Cc: Ilia Mirkin
> Cc: Hans Verkuil
> Cc: Uma Shankar
> Cc: Shashank Sharma
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Jyri Sarha
> [vsyrjala v2: Add/fix kerneldocs, verify bitmasks]
> Signed-off-by: Ville Syrjälä
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_atomic.c | 8 +++
> drivers/gpu/drm/drm_color_mgmt.c | 103
> +++
> include/drm/drm_color_mgmt.h | 19
> include/drm/drm_plane.h | 32
> 4 files changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 46733d534587..452a0b0bafbc 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -759,6 +759,10 @@ static int drm_atomic_plane_set_property(struct
> drm_plane *plane,
> state->rotation = val;
> } else if (property == plane->zpos_property) {
> state->zpos = val;
> + } else if (property == plane->color_encoding_property) {
> + state->color_encoding = val;
> + } else if (property == plane->color_range_property) {
> + state->color_range = val;
> } else if (plane->funcs->atomic_set_property) {
> return plane->funcs->atomic_set_property(plane, state,
> property, val);
> @@ -818,6 +822,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane,
> *val = state->rotation;
> } else if (property == plane->zpos_property) {
> *val = state->zpos;
> + } else if (property == plane->color_encoding_property) {
> + *val = state->color_encoding;
> + } else if (property == plane->color_range_property) {
> + *val = state->color_range;
> } else if (plane->funcs->atomic_get_property) {
> return plane->funcs->atomic_get_property(plane, state,
> property, val);
> } else {
> diff --git a/drivers/gpu/drm/drm_color_mgmt.c
> b/drivers/gpu/drm/drm_color_mgmt.c
> index 0d002b045bd2..4b83e078d3e9 100644
> --- a/drivers/gpu/drm/drm_color_mgmt.c
> +++ b/drivers/gpu/drm/drm_color_mgmt.c
> @@ -88,6 +88,20 @@
>* drm_mode_crtc_set_gamma_size(). Drivers which support both should use
>* drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp with
> the
>* "GAMMA_LUT" property above.
> + *
> + * Support for different non RGB color encodings is controlled through
> + * &drm_plane specific COLOR_ENCODING and COLOR_RANGE properties. They
> + * are set up by calling drm_plane_create_color_properties().
> + *
> + * "COLOR_ENCODING"
> + * Optional plane enum property to support different non RGB
> + * color encodings. The driver can provide a subset of standard
> + * enum values supported by the DRM plane.
> + *
> + * "COLOR_RANGE"
> + * Optional plane enum property to support different non RGB
> + * color parameter ranges. The driver can provide a subset of
> + * standard enum values supported by the DRM plane.
>*/
>
> /**
> @@ -339,3 +353,92 @@ int drm_mode_gamma_get_ioctl(struct drm_device *dev,
> drm_modeset_unlock(&crtc->mutex);
> return ret;
> }
> +
> +static const char * const color_encoding_name[] = {
> + [DRM_COLOR_YCBCR_BT601] = "ITU-R BT.601 YCbCr",
> + [DRM_COLOR_YCBCR_BT709] = "ITU-R BT.709 YCbCr",
> + [DRM_COLOR_YCBCR_BT2020] = "ITU-R BT.2020 YCbCr",
> +};
> +
> +static const char * const color_range_name[] = {
> + [DRM_COLOR_YCBCR_FULL_RANGE] = "YCbCr full range",
> + [DRM_COLOR_YCBCR_LIMITED_RANGE] = "YCbCr limited range",
> +};
> +
> +/**
> + * drm_plane_create_color_properties - color encoding related plane
> properties
> + * @plane: plane object
> + * @supported_encodings: bitfield indicating supported color encodings
> + * @supported_ranges: bitfileld indicating supported color ranges
> + * @default_encoding: default color encoding
> + * @default_range: default color range
> + *
> + * Create and attach plane specific COLOR_ENCODING and COLOR_RANGE
> + * properties to @plane. The supported encodings and ranges should
> + *
[Intel-gfx] [PATCH v2 0/8] Restore workarounds after engine reset and unify their handling
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was discovered to be unsafe to simply re-apply all of them, against
a possibly active GPU, and potentially from IRQ context, the approach taken was
to split GT workarounds and per-engine workarounds. Latter so far contain the
ones living in the 0x2xxx and 0xbxxx range, which were empirically shown to be
lost after RCS reset.
This way only a smaller set of affected workarounds can be applied after engine
resetm, which is done with irq safe read-modify-write cycle.
The series is structured like this so first two patches are as standalone as
possible so it is easy (easier) to backport them. The rest of the series
cleans up the whole workaround handling by moving all four classes of them to a
common framework.
v2:
* One patch less due removing verification after engine reset.
* See patch change logs.
Tvrtko Ursulin (7):
drm/i915: Record GT workarounds in a list
drm/i915: Introduce per-engine workarounds
drm/i915: Verify GT workaround state after GPU init
drm/i915/selftests: Add tests for GT and engine workaround
verification
drm/i915: Move register white-listing to the common workaround
framework
drm/i915: Fuse per-context workaround handling with the common
framework
drm/i915: Trim unused workaround list entries
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 17 +-
drivers/gpu/drm/i915/i915_gem.c | 5 +
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 4 +
drivers/gpu/drm/i915/intel_lrc.c | 5 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +
drivers/gpu/drm/i915/intel_workarounds.c | 879 +++---
drivers/gpu/drm/i915/intel_workarounds.h | 31 +-
drivers/gpu/drm/i915/selftests/igt_common.c | 44 +
drivers/gpu/drm/i915/selftests/igt_common.h | 15 +
.../gpu/drm/i915/selftests/intel_hangcheck.c | 51 +-
.../drm/i915/selftests/intel_workarounds.c| 187 +++-
15 files changed, 823 insertions(+), 440 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.c
create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.h
--
2.19.1
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[Intel-gfx] [PATCH 4/7] drm/i915/selftests: Add tests for GT and engine workaround verification
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
v2:
* Rebase for series refactoring.
* Add spinner for actual engine reset!
* Add idle reset test as well. (Chris Wilson)
* Share existing global_reset_lock. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 +
drivers/gpu/drm/i915/selftests/igt_common.c | 44 ++
drivers/gpu/drm/i915/selftests/igt_common.h | 15 ++
.../gpu/drm/i915/selftests/intel_hangcheck.c | 51 ++
.../drm/i915/selftests/intel_workarounds.c| 147 +-
6 files changed, 217 insertions(+), 47 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.c
create mode 100644 drivers/gpu/drm/i915/selftests/igt_common.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 50a8fa8fce64..ceeb21f8aa0c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -166,6 +166,7 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
selftests/i915_random.o \
selftests/i915_selftest.o \
selftests/igt_flush_test.o \
+ selftests/igt_common.o \
selftests/igt_spinner.o
# virtual gpu code
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index d80ea817..5a4d70e02b63 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1303,4 +1303,10 @@ void intel_engine_workarounds_apply(struct
intel_engine_cs *engine)
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/intel_workarounds.c"
+
+bool intel_engine_workarounds_verify(struct intel_engine_cs *engine,
+const char *from)
+{
+ return wa_list_verify(engine->i915, &engine->wa_list, from);
+}
#endif
diff --git a/drivers/gpu/drm/i915/selftests/igt_common.c
b/drivers/gpu/drm/i915/selftests/igt_common.c
new file mode 100644
index ..ad00fdf895be
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/igt_common.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#include "igt_common.h"
+
+#include "../i915_drv.h"
+#include "../intel_ringbuffer.h"
+
+void igt_global_reset_lock(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ pr_debug("%s: current gpu_error=%08lx\n",
+__func__, i915->gpu_error.flags);
+
+ while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags))
+ wait_event(i915->gpu_error.reset_queue,
+ !test_bit(I915_RESET_BACKOFF,
+&i915->gpu_error.flags));
+
+ for_each_engine(engine, i915, id) {
+ while (test_and_set_bit(I915_RESET_ENGINE + id,
+ &i915->gpu_error.flags))
+ wait_on_bit(&i915->gpu_error.flags,
+ I915_RESET_ENGINE + id,
+ TASK_UNINTERRUPTIBLE);
+ }
+}
+
+void igt_global_reset_unlock(struct drm_i915_private *i915)
+{
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ for_each_engine(engine, i915, id)
+ clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
+
+ clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags);
+ wake_up_all(&i915->gpu_error.reset_queue);
+}
diff --git a/drivers/gpu/drm/i915/selftests/igt_common.h
b/drivers/gpu/drm/i915/selftests/igt_common.h
new file mode 100644
index ..3df12ed10200
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/igt_common.h
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef __I915_SELFTESTS_IGT_COMMON_H__
+#define __I915_SELFTESTS_IGT_COMMON_H__
+
+#include "../i915_drv.h"
+
+void igt_global_reset_lock(struct drm_i915_private *i915);
+void igt_global_reset_unlock(struct drm_i915_private *i915);
+
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index defe671130ab..af31e4a4979d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -25,6 +25,7 @@
#include
#include "../i915_selftest.h"
+#include "igt_common.h"
#include "i915_random.h"
#include "igt_flush_test.h"
#include "igt_wedge_me.h"
@@ -348,40 +349,6 @@ static int igt_hang_sanitycheck(void *arg)
return err;
}
-static void global_reset_lock(struct drm_i915_private *i915)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- pr_debug("%s: current gpu_error=%
[Intel-gfx] [PATCH 7/7] drm/i915: Trim unused workaround list entries
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
v2:
* Simplify with kmemdup. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_workarounds.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 3e6b388ea022..9d876d554e57 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -55,6 +55,19 @@ static void wa_init_start(struct i915_wa_list *wal, const
char *name)
static void wa_init_finish(struct i915_wa_list *wal)
{
+ /* Trim unused entries. */
+ if (wal->count < wal->__size) {
+ struct i915_wa *list = kmemdup(wal->list,
+ wal->count * sizeof(*list),
+ GFP_KERNEL);
+
+ if (list) {
+ kfree(wal->list);
+ wal->list = list;
+ wal->__size = wal->count;
+ }
+ }
+
if (wal->count)
DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
wal->wa_count, wal->name);
--
2.19.1
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[Intel-gfx] [PATCH 5/7] drm/i915: Move register white-listing to the common workaround framework
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
v2:
* Use GEM_DEBUG_WARN_ON for the sanity check. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_engine_cs.c| 1 +
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 83 ---
drivers/gpu/drm/i915/intel_workarounds.h | 1 +
.../drm/i915/selftests/intel_workarounds.c| 40 -
6 files changed, 57 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index ef5d202e9d45..496462d77ebc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -725,6 +725,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
i915_timeline_fini(&engine->timeline);
intel_wa_list_free(&engine->wa_list);
+ intel_wa_list_free(&engine->whitelist);
}
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index dfafc3f710d6..4eead104cd9c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2316,6 +2316,7 @@ int logical_render_ring_init(struct intel_engine_cs
*engine)
ret);
}
+ intel_whitelist_workarounds_init(engine);
intel_engine_workarounds_init(engine);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c5ff3d31cab7..91a750e90dc4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -453,6 +453,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
struct i915_wa_list wa_list;
+ struct i915_wa_list whitelist;
struct i915_vma *scratch;
u32 irq_keep_mask; /* always keep these interrupts */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5a4d70e02b63..9bd044b8e545 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1015,29 +1015,20 @@ bool intel_gt_workarounds_verify(struct
drm_i915_private *dev_priv,
return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
}
-struct whitelist {
- i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
- unsigned int count;
- u32 nopid;
-};
-
-static void whitelist_reg(struct whitelist *w, i915_reg_t reg)
+static void
+whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
- if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS))
- return;
-
- w->reg[w->count++] = reg;
-}
+ struct i915_wa wa = {
+ .reg = reg
+ };
-static void bdw_whitelist_build(struct whitelist *w)
-{
-}
+ if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
+ return;
-static void chv_whitelist_build(struct whitelist *w)
-{
+ wal_add(wal, &wa);
}
-static void gen9_whitelist_build(struct whitelist *w)
+static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
@@ -1049,7 +1040,7 @@ static void gen9_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_HDC_CHICKEN1);
}
-static void skl_whitelist_build(struct whitelist *w)
+static void skl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1057,12 +1048,12 @@ static void skl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void bxt_whitelist_build(struct whitelist *w)
+static void bxt_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
}
-static void kbl_whitelist_build(struct whitelist *w)
+static void kbl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1070,7 +1061,7 @@ static void kbl_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN8_L3SQCREG4);
}
-static void glk_whitelist_build(struct whitelist *w)
+static void glk_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
@@ -1078,18 +1069,18 @@ static void glk_whitelist_build(struct whitelist *w)
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
}
-static void cfl_whitelist_build(struct whitelist *w)
+static void cfl_whitelist_build(struct i915_wa_list *w)
{
gen9_whitelist_build(w);
}
-static void cnl_whitelist_build(struct whitelist *w)
+static void cnl_whitelist_build(struct i915_wa_list *w)
{
[Intel-gfx] [PATCH 6/7] drm/i915: Fuse per-context workaround handling with the common framework
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration of all four classes of workarounds onto the
common framework.
Existing macros are kept untouched for smaller code churn.
v2:
* Rename to list name ctx_wa_list and move from dev_priv to engine.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 15 --
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 267 ++-
drivers/gpu/drm/i915/intel_workarounds.h | 3 +-
7 files changed, 129 insertions(+), 176 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 129b9a6f8309..38dcee1ca062 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3375,13 +3375,15 @@ static int i915_shared_dplls_info(struct seq_file *m,
void *unused)
static int i915_wa_registers(struct seq_file *m, void *unused)
{
- struct i915_workarounds *wa = &node_to_i915(m->private)->workarounds;
- int i;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ const struct i915_wa_list *wal = &i915->engine[RCS]->ctx_wa_list;
+ struct i915_wa *wa;
+ unsigned int i;
- seq_printf(m, "Workarounds applied: %d\n", wa->count);
- for (i = 0; i < wa->count; ++i)
+ seq_printf(m, "Workarounds applied: %u\n", wal->count);
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
- wa->reg[i].addr, wa->reg[i].value, wa->reg[i].mask);
+ i915_mmio_reg_offset(wa->reg), wa->val, wa->mask);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ddbcc1f3554..443e08f4736a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1189,20 +1189,6 @@ struct i915_frontbuffer_tracking {
unsigned flip_bits;
};
-struct i915_wa_reg {
- u32 addr;
- u32 value;
- /* bitmask representing WA bits */
- u32 mask;
-};
-
-#define I915_MAX_WA_REGS 16
-
-struct i915_workarounds {
- struct i915_wa_reg reg[I915_MAX_WA_REGS];
- u32 count;
-};
-
struct i915_virtual_gpu {
bool active;
u32 caps;
@@ -1652,7 +1638,6 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
- struct i915_workarounds workarounds;
struct i915_wa_list gt_wa_list;
struct i915_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index b97963db0287..aae7e13c7420 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -535,16 +535,12 @@ static bool needs_preempt_context(struct drm_i915_private
*i915)
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
- int ret;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
GEM_BUG_ON(dev_priv->preempt_context);
- ret = intel_ctx_workarounds_init(dev_priv);
- if (ret)
- return ret;
-
+ intel_ctx_workarounds_init(dev_priv);
init_contexts(dev_priv);
/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 496462d77ebc..6b427bc52f78 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -724,6 +724,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
i915_timeline_fini(&engine->timeline);
+ intel_wa_list_free(&engine->ctx_wa_list);
intel_wa_list_free(&engine->wa_list);
intel_wa_list_free(&engine->whitelist);
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 91a750e90dc4..8f985c35ec92 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -452,6 +452,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
+ struct i915_wa_list ctx_wa_list;
struct i915_wa_list wa_list;
struct i915_wa_list whitelist;
struct i915_vma *scratch;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 9bd044b8e545..3e6b388ea022 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i9
[Intel-gfx] [PATCH 1/7] drm/i915: Record GT workarounds in a list
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is allocated on demand as workarounds are added to the list.
This is a temporary implementation which later in the series gets fused
with the existing per context workaround list handling. It is separated at
this stage since the following patch fixes a bug which needs to be as easy
to backport as possible.
Also, since in the following patch we will be adding a new class of
workarounds (per engine) which can be applied from interrupt context, we
straight away make the provision for safe read-modify-write cycle.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 2 +
drivers/gpu/drm/i915/intel_workarounds.c | 443 +++
drivers/gpu/drm/i915/intel_workarounds.h | 22 ++
5 files changed, 327 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e39016713464..2f3dc1cf83a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1453,6 +1453,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
intel_uncore_sanitize(dev_priv);
+ intel_gt_workarounds_init(dev_priv);
i915_gem_load_init_fences(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 43ac6873a2bb..9ddbcc1f3554 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -69,6 +69,7 @@
#include "intel_ringbuffer.h"
#include "intel_uncore.h"
#include "intel_wopcm.h"
+#include "intel_workarounds.h"
#include "intel_uc.h"
#include "i915_gem.h"
@@ -1652,6 +1653,7 @@ struct drm_i915_private {
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
struct i915_workarounds workarounds;
+ struct i915_wa_list gt_wa_list;
struct i915_frontbuffer_tracking fb_tracking;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c55b1f75c980..18adb3dd1fcd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5706,6 +5706,8 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_contexts_fini(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ intel_wa_list_free(&dev_priv->gt_wa_list);
+
intel_cleanup_gt_powersave(dev_priv);
intel_uc_fini_misc(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index e5cd6c6c66c3..ff20ebf9e040 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -48,6 +48,18 @@
* - Public functions to init or apply the given workaround type.
*/
+static void wa_init_start(struct i915_wa_list *wal, const char *name)
+{
+ wal->name = name;
+}
+
+static void wa_init_finish(struct i915_wa_list *wal)
+{
+ if (wal->count)
+ DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
+wal->count, wal->name);
+}
+
static void wa_add(struct drm_i915_private *i915,
i915_reg_t reg, const u32 mask, const u32 val)
{
@@ -575,28 +587,88 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
return 0;
}
-static void bdw_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+static void
+wal_add(struct i915_wa_list *wal, const struct i915_wa *wa)
+{
+ const unsigned int grow = 4;
+
+ if (wal->__size == wal->count) {
+ struct i915_wa *list;
+
+ list = kcalloc(wal->__size + grow, sizeof(*wa), GFP_KERNEL);
+ if (!list) {
+ DRM_ERROR("No space for workaround init!\n");
+ return;
+ }
+
+ if (wal->list)
+ memcpy(list, wal->list, sizeof(*wa) * wal->count);
+
+ wal->list = list;
+ wal->__size += grow;
+ }
+
+ memcpy(&wal->list[wal->count], wa, sizeof(*wa));
+ wal->count++;
+}
+
+static void
+wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = val,
+ .val = _MASKED_BIT_ENABLE(val)
+ };
+
+ wal_add(wal, &wa);
+}
+
+static void
+wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+ u32 val)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .mask = mask,
+ .val = val
+ };
+
+ wal_add(wal, &wa);
}
-static void chv_gt_workarounds
[Intel-gfx] [PATCH 2/7] drm/i915: Introduce per-engine workarounds
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far the registers in 0x2xxx and
0xbxxx address range have been identified to be affected.
This losing of applied workarounds has obvious negative effects and can
even lead to hard system hangs (see the linked Bugzilla).
Rather than just restoring this re-application, because we have also
observed that it is not safe to just re-write all GT workarounds after
engine resets (GPU might be live and weird hardware states can happen),
we introduce a new class of per-engine workarounds and move only the
affected GT workarounds over.
Using the framework introduced in the previous patch, we therefore after
engine reset, re-apply only the workarounds living in the affected MMIO
address ranges.
Signed-off-by: Tvrtko Ursulin
Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=107945
Fixes: 59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds")
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Cc: Chris Wilson
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: intel-gfx@lists.freedesktop.org
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +
drivers/gpu/drm/i915/intel_workarounds.c | 249 +--
drivers/gpu/drm/i915/intel_workarounds.h | 3 +
5 files changed, 148 insertions(+), 112 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 759c0fd58f8c..ef5d202e9d45 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -723,6 +723,8 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
__intel_context_unpin(i915->kernel_context, engine);
i915_timeline_fini(&engine->timeline);
+
+ intel_wa_list_free(&engine->wa_list);
}
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 11f4e6148557..dfafc3f710d6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1617,6 +1617,8 @@ static bool unexpected_starting_state(struct
intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
+ intel_engine_workarounds_apply(engine);
+
intel_mocs_init_engine(engine);
intel_engine_reset_breadcrumbs(engine);
@@ -2314,6 +2316,8 @@ int logical_render_ring_init(struct intel_engine_cs
*engine)
ret);
}
+ intel_engine_workarounds_init(engine);
+
return 0;
err_cleanup_common:
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8a2270b209b0..c5ff3d31cab7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -15,6 +15,7 @@
#include "i915_selftest.h"
#include "i915_timeline.h"
#include "intel_gpu_commands.h"
+#include "intel_workarounds.h"
struct drm_printer;
struct i915_sched_attr;
@@ -451,6 +452,7 @@ struct intel_engine_cs {
struct intel_hw_status_page status_page;
struct i915_ctx_workarounds wa_ctx;
+ struct i915_wa_list wa_list;
struct i915_vma *scratch;
u32 irq_keep_mask; /* always keep these interrupts */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index ff20ebf9e040..be63a2af3481 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -653,17 +653,6 @@ static void gen9_gt_workarounds_init(struct
drm_i915_private *dev_priv)
{
struct i915_wa_list *wal = &dev_priv->gt_wa_list;
- /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal,
-GEN9_CSFE_CHICKEN1_RCS,
-GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
-
-
- /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
- wa_write_or(wal,
- BDW_SCRATCH1,
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
-
/* WaDisableKillLogic:bxt,skl,kbl */
if (!IS_COFFEELAKE(dev_priv))
wa_write_or(wal,
@@ -685,24 +674,6 @@ static void gen9_gt_workarounds_init(struct
drm_i915_private *dev_priv)
wa_write_or(wal,
GAM_ECOCHK,
BDW_DISABLE_HDC_INVALIDATION);
-
- /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
- if (IS_GEN9_LP(dev_priv))
- wa_write_masked_or(wal,
- GEN8_L3SQCREG1,
- L3_PRIO_CREDITS_MASK,
-
[Intel-gfx] [PATCH 3/7] drm/i915: Verify GT workaround state after GPU init
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
Initially we only do this after GPU initialization.
v2:
Chris Wilson:
* Simplify verification by realizing it's a simple xor and and.
* Remove verification from engine reset path.
* Return bool straight away from the verify API.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_gem.c | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 34
drivers/gpu/drm/i915/intel_workarounds.h | 2 ++
4 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f3dc1cf83a6..4883a20ed9ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -53,6 +53,7 @@
#include "i915_vgpu.h"
#include "intel_drv.h"
#include "intel_uc.h"
+#include "intel_workarounds.h"
static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 18adb3dd1fcd..1eff471d4366 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5334,7 +5334,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
+ /* Apply the GT workarounds... */
intel_gt_workarounds_apply(dev_priv);
+ /* ...and determine whether they are sticking. */
+ intel_gt_workarounds_verify(dev_priv, "init");
i915_gem_init_swizzling(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index be63a2af3481..d80ea817 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -981,6 +981,40 @@ void intel_gt_workarounds_apply(struct drm_i915_private
*dev_priv)
wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
}
+static bool
+wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char
*from)
+{
+ if ((cur ^ wa->val) & wa->mask) {
+ DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x,
mask=%x)\n",
+ name, from, i915_mmio_reg_offset(wa->reg), cur,
+ cur & wa->mask, wa->val, wa->mask);
+
+ return false;
+ }
+
+ return true;
+}
+
+static bool wa_list_verify(struct drm_i915_private *dev_priv,
+ const struct i915_wa_list *wal,
+ const char *from)
+{
+ struct i915_wa *wa;
+ unsigned int i;
+ bool ok = true;
+
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
+ ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
+
+ return ok;
+}
+
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+const char *from)
+{
+ return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
+}
+
struct whitelist {
i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
unsigned int count;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.h
b/drivers/gpu/drm/i915/intel_workarounds.h
index 2998767d51ca..f2a4e8c36027 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.h
+++ b/drivers/gpu/drm/i915/intel_workarounds.h
@@ -33,6 +33,8 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
void intel_gt_workarounds_init(struct drm_i915_private *dev_priv);
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv);
+bool intel_gt_workarounds_verify(struct drm_i915_private *dev_priv,
+const char *from);
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
--
2.19.1
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Restore workarounds after engine reset and unify their handling (rev2)
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev2)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1125245b3d4b drm/i915: Record GT workarounds in a list
-:460: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#460: FILE: drivers/gpu/drm/i915/intel_workarounds.c:912:
+ wa_masked_en(wal,
+ _3D_CHICKEN3,
-:722: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#722: FILE: drivers/gpu/drm/i915/intel_workarounds.h:20:
+^Iunsigned int ^Icount;$
total: 0 errors, 1 warnings, 1 checks, 685 lines checked
42b374d1ba00 drm/i915: Introduce per-engine workarounds
-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 59b449d5c82a ("drm/i915: Split
out functions for different kinds of workarounds")'
#10:
59b449d5c82a ("drm/i915: Split out functions for different kinds of
total: 1 errors, 0 warnings, 0 checks, 371 lines checked
e9a04e2832a9 drm/i915: Verify GT workaround state after GPU init
6549917a0bd0 drm/i915/selftests: Add tests for GT and engine workaround
verification
-:49: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#49:
new file mode 100644
-:54: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#54: FILE: drivers/gpu/drm/i915/selftests/igt_common.c:1:
+/*
-:104: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier
tag in line 1
#104: FILE: drivers/gpu/drm/i915/selftests/igt_common.h:1:
+/*
total: 0 errors, 3 warnings, 0 checks, 365 lines checked
a3beaa49924a drm/i915: Move register white-listing to the common workaround
framework
f4ea75c6a6cd drm/i915: Fuse per-context workaround handling with the common
framework
b7af01a81fb8 drm/i915: Trim unused workaround list entries
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore workarounds after engine reset and unify their handling (rev2)
== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Record GT workarounds in a list -drivers/gpu/drm/i915/selftests/../i915_drv.h:3570:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) +./include/linux/slab.h:665:13: error: undefined identifier '__builtin_mul_overflow' +./include/linux/slab.h:665:13: warning: call with no type! Commit: drm/i915: Introduce per-engine workarounds Okay! Commit: drm/i915: Verify GT workaround state after GPU init Okay! Commit: drm/i915/selftests: Add tests for GT and engine workaround verification +./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000 becomes 0) Commit: drm/i915: Move register white-listing to the common workaround framework Okay! Commit: drm/i915: Fuse per-context workaround handling with the common framework -drivers/gpu/drm/i915/selftests/../i915_drv.h:3572:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3557:16: warning: expression using sizeof(void) Commit: drm/i915: Trim unused workaround list entries Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Get pipe id following atomic guidelines (rev5)
Pushed to drm-intel-next-queued, thanks for the review Rodrigo.
On Thu, 2018-11-29 at 23:52 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
> URL : https://patchwork.freedesktop.org/series/53132/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10968
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
> External URL:
> https://patchwork.freedesktop.org/api/1.0/series/53132/revisions/5/mbox/
>
> Known issues
>
>
> Here are the changes found in Patchwork_10968 that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@kms_frontbuffer_tracking@basic:
> - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614]
>
>
> Possible fixes
>
> * igt@gem_ctx_create@basic-files:
> - fi-bsw-kefka: FAIL [fdo#108656] -> PASS
>
> * igt@kms_frontbuffer_tracking@basic:
> - fi-byt-clapper: FAIL [fdo#103167] -> PASS
>
>
> Warnings
>
> * igt@i915_selftest@live_contexts:
> - {fi-icl-u3}:INCOMPLETE [fdo#108315] -> DMESG-FAIL
> [fdo#108569]
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or
> FAILURE).
>
> [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656
>
>
> Participating hosts (50 -> 44)
> --
>
> Additional (1): fi-glk-j4005
> Missing(7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-
> squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
>
>
> Build changes
> -
>
> * Linux: CI_DRM_5227 -> Patchwork_10968
>
> CI_DRM_5227: 95052693524067ba66e1a6733355739fbcc8d5b6 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_10968: 364eb06faaf7a8c47634d63692a241dd94b37c84 @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> 364eb06faaf7 drm/i915/psr: Get pipe id following atomic guidelines
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10968/
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[Intel-gfx] ✓ Fi.CI.BAT: success for Restore workarounds after engine reset and unify their handling (rev2)
== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : success == Summary == CI Bug Log - changes from CI_DRM_5235 -> Patchwork_10981 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/53313/revisions/2/mbox/ Known issues Here are the changes found in Patchwork_10981 that come from known issues: ### IGT changes ### Issues hit * igt@kms_frontbuffer_tracking@basic: - fi-hsw-peppy: PASS -> DMESG-WARN [fdo#102614] * igt@kms_pipe_crc_basic@read-crc-pipe-a: - fi-byt-clapper: NOTRUN -> FAIL [fdo#107362] Possible fixes * igt@gem_ctx_create@basic-files: - fi-bsw-kefka: FAIL [fdo#108656] -> PASS * igt@gem_exec_suspend@basic-s3: - fi-byt-clapper: INCOMPLETE [fdo#102657] -> PASS * igt@i915_selftest@live_execlists: - fi-apl-guc: INCOMPLETE [fdo#103927] -> PASS * igt@i915_selftest@live_hangcheck: - fi-kbl-7560u: INCOMPLETE [fdo#108044] -> PASS [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614 [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044 [fdo#108656]: https://bugs.freedesktop.org/show_bug.cgi?id=108656 Participating hosts (50 -> 44) -- Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 Build changes - * Linux: CI_DRM_5235 -> Patchwork_10981 CI_DRM_5235: 5e327aec3fa3fc277b40818e06785743cf16b1ad @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10981: b7af01a81fb8c4c250ba60f24eb7b0272bcf7d3f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b7af01a81fb8 drm/i915: Trim unused workaround list entries f4ea75c6a6cd drm/i915: Fuse per-context workaround handling with the common framework a3beaa49924a drm/i915: Move register white-listing to the common workaround framework 6549917a0bd0 drm/i915/selftests: Add tests for GT and engine workaround verification e9a04e2832a9 drm/i915: Verify GT workaround state after GPU init 42b374d1ba00 drm/i915: Introduce per-engine workarounds 1125245b3d4b drm/i915: Record GT workarounds in a list == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10981/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Get pipe id following atomic guidelines (rev5)
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5)
URL : https://patchwork.freedesktop.org/series/53132/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5227_full -> Patchwork_10968_full
Summary
---
**WARNING**
Minor unknown changes coming with Patchwork_10968_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10968_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_10968_full:
### IGT changes ###
Warnings
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
Known issues
Here are the changes found in Patchwork_10968_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s4-devices:
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665] / [fdo#106023] /
[fdo#106887]
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-suspend:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_flip@dpms-vs-vblank-race-interruptible:
- shard-apl: PASS -> FAIL [fdo#103060]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-skl: PASS -> FAIL [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-skl: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_rmfb@rmfb-ioctl:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107724] +1
* igt@kms_rotation_crc@primary-rotation-180:
- shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815]
* igt@pm_backlight@fade_with_suspend:
- {shard-iclb}: NOTRUN -> FAIL [fdo#107847]
* igt@pm_rpm@dpms-lpsp:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@dpms-mode-unset-non-lpsp:
- shard-skl: SKIP -> INCOMPLETE [fdo#107807]
* igt@pm_rpm@fences:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +2
* {igt@runner@aborted}:
- {shard-iclb}: NOTRUN -> FAIL [fdo#108315]
Possible fixes
* igt@kms_chv_cursor_fail@pipe-a-128x128-top-edge:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +1
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +5
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- {shard-iclb}: INCOMPLETE [fdo#107713] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +3
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- {shard-iclb}: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x
